Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 26
- Kernel Errors: 38
- Errors: 0
- Boot result: PASS
1 09:28:04.151519 lava-dispatcher, installed at version: 2023.08
2 09:28:04.151768 start: 0 validate
3 09:28:04.151898 Start time: 2023-10-20 09:28:04.151891+00:00 (UTC)
4 09:28:04.152009 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:28:04.152138 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:28:04.421155 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:28:04.421803 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:28:22.433922 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:28:22.434648 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:28:22.698888 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:28:22.699547 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:28:23.221436 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:28:23.222099 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:28:26.227394 validate duration: 22.08
16 09:28:26.227651 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:28:26.227789 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:28:26.227873 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:28:26.227992 Not decompressing ramdisk as can be used compressed.
20 09:28:26.228077 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 09:28:26.228143 saving as /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/ramdisk/initrd.cpio.gz
22 09:28:26.228207 total size: 4665395 (4 MB)
23 09:28:26.497847 progress 0 % (0 MB)
24 09:28:26.500207 progress 5 % (0 MB)
25 09:28:26.502304 progress 10 % (0 MB)
26 09:28:26.504300 progress 15 % (0 MB)
27 09:28:26.506309 progress 20 % (0 MB)
28 09:28:26.508283 progress 25 % (1 MB)
29 09:28:26.510324 progress 30 % (1 MB)
30 09:28:26.512255 progress 35 % (1 MB)
31 09:28:26.514252 progress 40 % (1 MB)
32 09:28:26.516437 progress 45 % (2 MB)
33 09:28:26.518424 progress 50 % (2 MB)
34 09:28:26.520366 progress 55 % (2 MB)
35 09:28:26.522372 progress 60 % (2 MB)
36 09:28:26.524298 progress 65 % (2 MB)
37 09:28:26.526203 progress 70 % (3 MB)
38 09:28:26.528129 progress 75 % (3 MB)
39 09:28:26.529526 progress 80 % (3 MB)
40 09:28:26.530920 progress 85 % (3 MB)
41 09:28:26.532196 progress 90 % (4 MB)
42 09:28:26.533419 progress 95 % (4 MB)
43 09:28:26.534663 progress 100 % (4 MB)
44 09:28:26.534816 4 MB downloaded in 0.31 s (14.51 MB/s)
45 09:28:26.534971 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:28:26.535202 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:28:26.535286 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:28:26.535368 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:28:26.535500 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:28:26.535566 saving as /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/kernel/Image
52 09:28:26.535625 total size: 49236480 (46 MB)
53 09:28:26.535727 No compression specified
54 09:28:26.536834 progress 0 % (0 MB)
55 09:28:26.549733 progress 5 % (2 MB)
56 09:28:26.562825 progress 10 % (4 MB)
57 09:28:26.575920 progress 15 % (7 MB)
58 09:28:26.589425 progress 20 % (9 MB)
59 09:28:26.602760 progress 25 % (11 MB)
60 09:28:26.617168 progress 30 % (14 MB)
61 09:28:26.631509 progress 35 % (16 MB)
62 09:28:26.645677 progress 40 % (18 MB)
63 09:28:26.659982 progress 45 % (21 MB)
64 09:28:26.673957 progress 50 % (23 MB)
65 09:28:26.687854 progress 55 % (25 MB)
66 09:28:26.701817 progress 60 % (28 MB)
67 09:28:26.715685 progress 65 % (30 MB)
68 09:28:26.729613 progress 70 % (32 MB)
69 09:28:26.743536 progress 75 % (35 MB)
70 09:28:26.757686 progress 80 % (37 MB)
71 09:28:26.771048 progress 85 % (39 MB)
72 09:28:26.784238 progress 90 % (42 MB)
73 09:28:26.797563 progress 95 % (44 MB)
74 09:28:26.810679 progress 100 % (46 MB)
75 09:28:26.810917 46 MB downloaded in 0.28 s (170.57 MB/s)
76 09:28:26.811071 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:28:26.811302 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:28:26.811388 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:28:26.811472 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:28:26.811633 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:28:26.811732 saving as /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/dtb/mt8192-asurada-spherion-r0.dtb
83 09:28:26.811793 total size: 47278 (0 MB)
84 09:28:26.811852 No compression specified
85 09:28:26.812964 progress 69 % (0 MB)
86 09:28:26.813237 progress 100 % (0 MB)
87 09:28:26.813395 0 MB downloaded in 0.00 s (28.19 MB/s)
88 09:28:26.813515 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:28:26.813795 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:28:26.813879 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:28:26.813960 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:28:26.814073 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 09:28:26.814140 saving as /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/nfsrootfs/full.rootfs.tar
95 09:28:26.814204 total size: 200813988 (191 MB)
96 09:28:26.814264 Using unxz to decompress xz
97 09:28:26.818572 progress 0 % (0 MB)
98 09:28:27.379558 progress 5 % (9 MB)
99 09:28:27.928891 progress 10 % (19 MB)
100 09:28:28.530566 progress 15 % (28 MB)
101 09:28:28.922217 progress 20 % (38 MB)
102 09:28:29.253543 progress 25 % (47 MB)
103 09:28:29.858318 progress 30 % (57 MB)
104 09:28:30.441181 progress 35 % (67 MB)
105 09:28:31.051918 progress 40 % (76 MB)
106 09:28:31.627236 progress 45 % (86 MB)
107 09:28:32.226523 progress 50 % (95 MB)
108 09:28:32.907238 progress 55 % (105 MB)
109 09:28:33.614301 progress 60 % (114 MB)
110 09:28:33.734136 progress 65 % (124 MB)
111 09:28:33.874829 progress 70 % (134 MB)
112 09:28:33.979555 progress 75 % (143 MB)
113 09:28:34.054282 progress 80 % (153 MB)
114 09:28:34.126370 progress 85 % (162 MB)
115 09:28:34.235823 progress 90 % (172 MB)
116 09:28:34.561045 progress 95 % (181 MB)
117 09:28:35.164544 progress 100 % (191 MB)
118 09:28:35.169925 191 MB downloaded in 8.36 s (22.92 MB/s)
119 09:28:35.170302 end: 1.4.1 http-download (duration 00:00:08) [common]
121 09:28:35.170693 end: 1.4 download-retry (duration 00:00:08) [common]
122 09:28:35.170820 start: 1.5 download-retry (timeout 00:09:51) [common]
123 09:28:35.170944 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 09:28:35.171130 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:28:35.171230 saving as /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/modules/modules.tar
126 09:28:35.171322 total size: 8614716 (8 MB)
127 09:28:35.171427 Using unxz to decompress xz
128 09:28:35.176731 progress 0 % (0 MB)
129 09:28:35.198054 progress 5 % (0 MB)
130 09:28:35.222139 progress 10 % (0 MB)
131 09:28:35.246383 progress 15 % (1 MB)
132 09:28:35.270700 progress 20 % (1 MB)
133 09:28:35.295228 progress 25 % (2 MB)
134 09:28:35.321952 progress 30 % (2 MB)
135 09:28:35.349163 progress 35 % (2 MB)
136 09:28:35.373052 progress 40 % (3 MB)
137 09:28:35.397987 progress 45 % (3 MB)
138 09:28:35.424278 progress 50 % (4 MB)
139 09:28:35.449446 progress 55 % (4 MB)
140 09:28:35.475284 progress 60 % (4 MB)
141 09:28:35.501633 progress 65 % (5 MB)
142 09:28:35.529437 progress 70 % (5 MB)
143 09:28:35.556166 progress 75 % (6 MB)
144 09:28:35.583881 progress 80 % (6 MB)
145 09:28:35.610502 progress 85 % (7 MB)
146 09:28:35.636444 progress 90 % (7 MB)
147 09:28:35.666805 progress 95 % (7 MB)
148 09:28:35.695548 progress 100 % (8 MB)
149 09:28:35.702161 8 MB downloaded in 0.53 s (15.48 MB/s)
150 09:28:35.702481 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:28:35.702890 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:28:35.702986 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 09:28:35.703084 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 09:28:39.283670 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8
156 09:28:39.283901 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 09:28:39.284006 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 09:28:39.284183 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h
159 09:28:39.284323 makedir: /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin
160 09:28:39.284427 makedir: /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/tests
161 09:28:39.284526 makedir: /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/results
162 09:28:39.284630 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-add-keys
163 09:28:39.284776 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-add-sources
164 09:28:39.284914 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-background-process-start
165 09:28:39.285044 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-background-process-stop
166 09:28:39.285173 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-common-functions
167 09:28:39.285300 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-echo-ipv4
168 09:28:39.285425 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-install-packages
169 09:28:39.285598 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-installed-packages
170 09:28:39.285725 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-os-build
171 09:28:39.285853 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-probe-channel
172 09:28:39.285984 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-probe-ip
173 09:28:39.286128 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-target-ip
174 09:28:39.286258 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-target-mac
175 09:28:39.286389 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-target-storage
176 09:28:39.286518 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-case
177 09:28:39.286644 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-event
178 09:28:39.286768 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-feedback
179 09:28:39.286892 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-raise
180 09:28:39.287022 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-reference
181 09:28:39.287169 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-runner
182 09:28:39.287307 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-set
183 09:28:39.287434 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-test-shell
184 09:28:39.287561 Updating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-add-keys (debian)
185 09:28:39.287753 Updating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-add-sources (debian)
186 09:28:39.287897 Updating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-install-packages (debian)
187 09:28:39.288039 Updating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-installed-packages (debian)
188 09:28:39.288178 Updating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/bin/lava-os-build (debian)
189 09:28:39.288300 Creating /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/environment
190 09:28:39.288395 LAVA metadata
191 09:28:39.288465 - LAVA_JOB_ID=11826808
192 09:28:39.288527 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:28:39.288629 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 09:28:39.288705 skipped lava-vland-overlay
195 09:28:39.288781 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:28:39.288859 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 09:28:39.288919 skipped lava-multinode-overlay
198 09:28:39.288990 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:28:39.289067 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 09:28:39.289140 Loading test definitions
201 09:28:39.289228 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 09:28:39.289296 Using /lava-11826808 at stage 0
203 09:28:39.289582 uuid=11826808_1.6.2.3.1 testdef=None
204 09:28:39.289670 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:28:39.289754 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 09:28:39.290214 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:28:39.290461 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 09:28:39.291033 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:28:39.291261 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 09:28:39.291984 runner path: /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/0/tests/0_timesync-off test_uuid 11826808_1.6.2.3.1
213 09:28:39.292144 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:28:39.292366 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 09:28:39.292438 Using /lava-11826808 at stage 0
217 09:28:39.292536 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:28:39.292614 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/0/tests/1_kselftest-tpm2'
219 09:28:46.614415 Running '/usr/bin/git checkout kernelci.org
220 09:28:46.762486 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 09:28:46.763274 uuid=11826808_1.6.2.3.5 testdef=None
222 09:28:46.763493 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 09:28:46.763828 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 09:28:46.764600 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:28:46.764839 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 09:28:46.765859 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:28:46.766095 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 09:28:46.767021 runner path: /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/0/tests/1_kselftest-tpm2 test_uuid 11826808_1.6.2.3.5
232 09:28:46.767116 BOARD='mt8192-asurada-spherion-r0'
233 09:28:46.767181 BRANCH='cip'
234 09:28:46.767241 SKIPFILE='/dev/null'
235 09:28:46.767299 SKIP_INSTALL='True'
236 09:28:46.767386 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:28:46.767488 TST_CASENAME=''
238 09:28:46.767588 TST_CMDFILES='tpm2'
239 09:28:46.767798 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:28:46.768009 Creating lava-test-runner.conf files
242 09:28:46.768072 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826808/lava-overlay-tt4kgb2h/lava-11826808/0 for stage 0
243 09:28:46.768171 - 0_timesync-off
244 09:28:46.768239 - 1_kselftest-tpm2
245 09:28:46.768336 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 09:28:46.768425 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 09:28:54.333140 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:28:54.333300 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 09:28:54.333430 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:28:54.333531 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 09:28:54.333625 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 09:28:54.453823 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:28:54.454222 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 09:28:54.454343 extracting modules file /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8
255 09:28:54.679986 extracting modules file /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826808/extract-overlay-ramdisk-wlaq0bx9/ramdisk
256 09:28:54.908395 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:28:54.908552 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 09:28:54.908644 [common] Applying overlay to NFS
259 09:28:54.908717 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826808/compress-overlay-wz8xfhcz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8
260 09:28:55.839786 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:28:55.839943 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 09:28:55.840038 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:28:55.840131 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 09:28:55.840220 Building ramdisk /var/lib/lava/dispatcher/tmp/11826808/extract-overlay-ramdisk-wlaq0bx9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826808/extract-overlay-ramdisk-wlaq0bx9/ramdisk
265 09:28:56.140564 >> 119368 blocks
266 09:28:58.064658 rename /var/lib/lava/dispatcher/tmp/11826808/extract-overlay-ramdisk-wlaq0bx9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/ramdisk/ramdisk.cpio.gz
267 09:28:58.065245 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:28:58.065404 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 09:28:58.065603 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 09:28:58.065790 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/kernel/Image'
271 09:29:11.066698 Returned 0 in 13 seconds
272 09:29:11.167386 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/kernel/image.itb
273 09:29:11.518736 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:29:11.519126 output: Created: Fri Oct 20 10:29:11 2023
275 09:29:11.519236 output: Image 0 (kernel-1)
276 09:29:11.519333 output: Description:
277 09:29:11.519429 output: Created: Fri Oct 20 10:29:11 2023
278 09:29:11.519526 output: Type: Kernel Image
279 09:29:11.519617 output: Compression: lzma compressed
280 09:29:11.519704 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
281 09:29:11.519770 output: Architecture: AArch64
282 09:29:11.519832 output: OS: Linux
283 09:29:11.519888 output: Load Address: 0x00000000
284 09:29:11.519950 output: Entry Point: 0x00000000
285 09:29:11.520008 output: Hash algo: crc32
286 09:29:11.520069 output: Hash value: 05d3904e
287 09:29:11.520125 output: Image 1 (fdt-1)
288 09:29:11.520194 output: Description: mt8192-asurada-spherion-r0
289 09:29:11.520281 output: Created: Fri Oct 20 10:29:11 2023
290 09:29:11.520365 output: Type: Flat Device Tree
291 09:29:11.520461 output: Compression: uncompressed
292 09:29:11.520547 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 09:29:11.520632 output: Architecture: AArch64
294 09:29:11.520720 output: Hash algo: crc32
295 09:29:11.520804 output: Hash value: cc4352de
296 09:29:11.520890 output: Image 2 (ramdisk-1)
297 09:29:11.520974 output: Description: unavailable
298 09:29:11.521058 output: Created: Fri Oct 20 10:29:11 2023
299 09:29:11.521144 output: Type: RAMDisk Image
300 09:29:11.521230 output: Compression: Unknown Compression
301 09:29:11.521314 output: Data Size: 17795134 Bytes = 17378.06 KiB = 16.97 MiB
302 09:29:11.521400 output: Architecture: AArch64
303 09:29:11.521484 output: OS: Linux
304 09:29:11.521567 output: Load Address: unavailable
305 09:29:11.521653 output: Entry Point: unavailable
306 09:29:11.521738 output: Hash algo: crc32
307 09:29:11.521821 output: Hash value: e0e63be2
308 09:29:11.521907 output: Default Configuration: 'conf-1'
309 09:29:11.521991 output: Configuration 0 (conf-1)
310 09:29:11.522074 output: Description: mt8192-asurada-spherion-r0
311 09:29:11.522161 output: Kernel: kernel-1
312 09:29:11.522245 output: Init Ramdisk: ramdisk-1
313 09:29:11.522328 output: FDT: fdt-1
314 09:29:11.522413 output: Loadables: kernel-1
315 09:29:11.522497 output:
316 09:29:11.522741 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 09:29:11.522849 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 09:29:11.522955 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 09:29:11.523050 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 09:29:11.523163 No LXC device requested
321 09:29:11.523276 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:29:11.523398 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 09:29:11.523508 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:29:11.523610 Checking files for TFTP limit of 4294967296 bytes.
325 09:29:11.524170 end: 1 tftp-deploy (duration 00:00:45) [common]
326 09:29:11.524319 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:29:11.524444 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:29:11.524616 substitutions:
329 09:29:11.524713 - {DTB}: 11826808/tftp-deploy-sgpti5nv/dtb/mt8192-asurada-spherion-r0.dtb
330 09:29:11.524811 - {INITRD}: 11826808/tftp-deploy-sgpti5nv/ramdisk/ramdisk.cpio.gz
331 09:29:11.524901 - {KERNEL}: 11826808/tftp-deploy-sgpti5nv/kernel/Image
332 09:29:11.524992 - {LAVA_MAC}: None
333 09:29:11.525080 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8
334 09:29:11.525167 - {NFS_SERVER_IP}: 192.168.201.1
335 09:29:11.525256 - {PRESEED_CONFIG}: None
336 09:29:11.525344 - {PRESEED_LOCAL}: None
337 09:29:11.525429 - {RAMDISK}: 11826808/tftp-deploy-sgpti5nv/ramdisk/ramdisk.cpio.gz
338 09:29:11.525517 - {ROOT_PART}: None
339 09:29:11.525603 - {ROOT}: None
340 09:29:11.525688 - {SERVER_IP}: 192.168.201.1
341 09:29:11.525775 - {TEE}: None
342 09:29:11.525862 Parsed boot commands:
343 09:29:11.525946 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:29:11.526181 Parsed boot commands: tftpboot 192.168.201.1 11826808/tftp-deploy-sgpti5nv/kernel/image.itb 11826808/tftp-deploy-sgpti5nv/kernel/cmdline
345 09:29:11.526303 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:29:11.526423 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:29:11.526555 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:29:11.526679 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:29:11.526768 Not connected, no need to disconnect.
350 09:29:11.526849 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:29:11.526934 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:29:11.527016 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 09:29:11.531346 Setting prompt string to ['lava-test: # ']
354 09:29:11.531784 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:29:11.531932 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:29:11.532064 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:29:11.532162 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:29:11.532421 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 09:29:16.675569 >> Command sent successfully.
360 09:29:16.678736 Returned 0 in 5 seconds
361 09:29:16.779146 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 09:29:16.779479 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 09:29:16.779585 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 09:29:16.779717 Setting prompt string to 'Starting depthcharge on Spherion...'
366 09:29:16.779791 Changing prompt to 'Starting depthcharge on Spherion...'
367 09:29:16.779867 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 09:29:16.780140 [Enter `^Ec?' for help]
369 09:29:16.953719
370 09:29:16.953863
371 09:29:16.953937 F0: 102B 0000
372 09:29:16.954003
373 09:29:16.954062 F3: 1001 0000 [0200]
374 09:29:16.954121
375 09:29:16.957038 F3: 1001 0000
376 09:29:16.957123
377 09:29:16.957188 F7: 102D 0000
378 09:29:16.957250
379 09:29:16.960425 F1: 0000 0000
380 09:29:16.960508
381 09:29:16.960574 V0: 0000 0000 [0001]
382 09:29:16.960639
383 09:29:16.963671 00: 0007 8000
384 09:29:16.963759
385 09:29:16.963824 01: 0000 0000
386 09:29:16.963888
387 09:29:16.966880 BP: 0C00 0209 [0000]
388 09:29:16.966963
389 09:29:16.967028 G0: 1182 0000
390 09:29:16.967089
391 09:29:16.970630 EC: 0000 0021 [4000]
392 09:29:16.970713
393 09:29:16.970778 S7: 0000 0000 [0000]
394 09:29:16.970840
395 09:29:16.973993 CC: 0000 0000 [0001]
396 09:29:16.974077
397 09:29:16.974142 T0: 0000 0040 [010F]
398 09:29:16.974204
399 09:29:16.974262 Jump to BL
400 09:29:16.974320
401 09:29:17.000611
402 09:29:17.000717
403 09:29:17.000783
404 09:29:17.007566 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 09:29:17.010958 ARM64: Exception handlers installed.
406 09:29:17.014848 ARM64: Testing exception
407 09:29:17.017893 ARM64: Done test exception
408 09:29:17.025157 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 09:29:17.035050 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 09:29:17.041587 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 09:29:17.052352 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 09:29:17.058742 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 09:29:17.065594 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 09:29:17.078609 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 09:29:17.085136 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 09:29:17.103220 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 09:29:17.106532 WDT: Last reset was cold boot
418 09:29:17.110286 SPI1(PAD0) initialized at 2873684 Hz
419 09:29:17.113220 SPI5(PAD0) initialized at 992727 Hz
420 09:29:17.116610 VBOOT: Loading verstage.
421 09:29:17.123352 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:29:17.127087 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 09:29:17.130426 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 09:29:17.133701 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 09:29:17.140930 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 09:29:17.147268 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 09:29:17.159127 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 09:29:17.159211
429 09:29:17.159276
430 09:29:17.169190 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 09:29:17.172293 ARM64: Exception handlers installed.
432 09:29:17.175988 ARM64: Testing exception
433 09:29:17.176071 ARM64: Done test exception
434 09:29:17.182412 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 09:29:17.185761 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 09:29:17.199804 Probing TPM: . done!
437 09:29:17.199887 TPM ready after 0 ms
438 09:29:17.206472 Connected to device vid:did:rid of 1ae0:0028:00
439 09:29:17.213202 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 09:29:17.272988 Initialized TPM device CR50 revision 0
441 09:29:17.284804 tlcl_send_startup: Startup return code is 0
442 09:29:17.284892 TPM: setup succeeded
443 09:29:17.296420 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 09:29:17.305093 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:29:17.318778 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 09:29:17.326553 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 09:29:17.330090 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 09:29:17.333146 in-header: 03 07 00 00 08 00 00 00
449 09:29:17.337116 in-data: aa e4 47 04 13 02 00 00
450 09:29:17.341035 Chrome EC: UHEPI supported
451 09:29:17.344626 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 09:29:17.349451 in-header: 03 95 00 00 08 00 00 00
453 09:29:17.352738 in-data: 18 20 20 08 00 00 00 00
454 09:29:17.352819 Phase 1
455 09:29:17.360469 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 09:29:17.364246 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 09:29:17.371388 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 09:29:17.371480 Recovery requested (1009000e)
459 09:29:17.384273 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 09:29:17.388204 tlcl_extend: response is 0
461 09:29:17.397290 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 09:29:17.402454 tlcl_extend: response is 0
463 09:29:17.409719 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 09:29:17.429465 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 09:29:17.435757 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 09:29:17.435844
467 09:29:17.435931
468 09:29:17.445810 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 09:29:17.449118 ARM64: Exception handlers installed.
470 09:29:17.452366 ARM64: Testing exception
471 09:29:17.452452 ARM64: Done test exception
472 09:29:17.474946 pmic_efuse_setting: Set efuses in 11 msecs
473 09:29:17.478248 pmwrap_interface_init: Select PMIF_VLD_RDY
474 09:29:17.484897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 09:29:17.488000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 09:29:17.495591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 09:29:17.499042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 09:29:17.502818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 09:29:17.510014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 09:29:17.514119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 09:29:17.517838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 09:29:17.522040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 09:29:17.529282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 09:29:17.533179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 09:29:17.537224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 09:29:17.540971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 09:29:17.548236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 09:29:17.551622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 09:29:17.558993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 09:29:17.562864 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 09:29:17.570230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 09:29:17.574312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 09:29:17.581675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 09:29:17.585355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 09:29:17.592855 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 09:29:17.599764 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 09:29:17.603675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 09:29:17.607525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 09:29:17.614583 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 09:29:17.618610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 09:29:17.625924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 09:29:17.629575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 09:29:17.632547 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 09:29:17.640013 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 09:29:17.644017 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 09:29:17.648015 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 09:29:17.655317 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 09:29:17.658469 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 09:29:17.662527 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 09:29:17.669806 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 09:29:17.673800 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 09:29:17.677729 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 09:29:17.680908 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 09:29:17.688286 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 09:29:17.692070 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 09:29:17.695196 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 09:29:17.699534 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 09:29:17.703103 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 09:29:17.710669 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 09:29:17.713981 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 09:29:17.717645 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 09:29:17.721289 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 09:29:17.725228 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 09:29:17.728516 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 09:29:17.736447 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 09:29:17.747901 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 09:29:17.751785 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 09:29:17.759024 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 09:29:17.766267 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 09:29:17.773642 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 09:29:17.777556 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:29:17.780894 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 09:29:17.788223 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x0
534 09:29:17.792097 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 09:29:17.800568 [RTC]rtc_osc_init,62: osc32con val = 0xde71
536 09:29:17.803842 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 09:29:17.812960 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 09:29:17.821960 [RTC]rtc_get_frequency_meter,154: input=23, output=943
539 09:29:17.831578 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 09:29:17.841327 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 09:29:17.850322 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 09:29:17.860758 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 09:29:17.869627 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 09:29:17.873825 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 09:29:17.881180 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 09:29:17.884487 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 09:29:17.887810 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 09:29:17.891906 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 09:29:17.895212 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 09:29:17.899154 ADC[4]: Raw value=906203 ID=7
551 09:29:17.899237 ADC[3]: Raw value=213441 ID=1
552 09:29:17.903277 RAM Code: 0x71
553 09:29:17.906473 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 09:29:17.913601 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 09:29:17.921212 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 09:29:17.929038 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 09:29:17.932337 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 09:29:17.936088 in-header: 03 07 00 00 08 00 00 00
559 09:29:17.939936 in-data: aa e4 47 04 13 02 00 00
560 09:29:17.940047 Chrome EC: UHEPI supported
561 09:29:17.947679 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 09:29:17.951037 in-header: 03 95 00 00 08 00 00 00
563 09:29:17.954828 in-data: 18 20 20 08 00 00 00 00
564 09:29:17.958675 MRC: failed to locate region type 0.
565 09:29:17.965564 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 09:29:17.965648 DRAM-K: Running full calibration
567 09:29:17.973280 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 09:29:17.976949 header.status = 0x0
569 09:29:17.977036 header.version = 0x6 (expected: 0x6)
570 09:29:17.981181 header.size = 0xd00 (expected: 0xd00)
571 09:29:17.984489 header.flags = 0x0
572 09:29:17.988573 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 09:29:18.008346 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 09:29:18.015577 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 09:29:18.019346 dram_init: ddr_geometry: 2
576 09:29:18.019430 [EMI] MDL number = 2
577 09:29:18.023155 [EMI] Get MDL freq = 0
578 09:29:18.023237 dram_init: ddr_type: 0
579 09:29:18.026797 is_discrete_lpddr4: 1
580 09:29:18.031115 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 09:29:18.031199
582 09:29:18.031263
583 09:29:18.031324 [Bian_co] ETT version 0.0.0.1
584 09:29:18.034371 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 09:29:18.038316
586 09:29:18.042144 dramc_set_vcore_voltage set vcore to 650000
587 09:29:18.042227 Read voltage for 800, 4
588 09:29:18.042292 Vio18 = 0
589 09:29:18.046140 Vcore = 650000
590 09:29:18.046221 Vdram = 0
591 09:29:18.046287 Vddq = 0
592 09:29:18.049485 Vmddr = 0
593 09:29:18.049566 dram_init: config_dvfs: 1
594 09:29:18.053344 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 09:29:18.060849 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 09:29:18.064943 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 09:29:18.068594 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 09:29:18.072278 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 09:29:18.076211 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 09:29:18.076297 MEM_TYPE=3, freq_sel=18
601 09:29:18.080309 sv_algorithm_assistance_LP4_1600
602 09:29:18.083170 ============ PULL DRAM RESETB DOWN ============
603 09:29:18.090123 ========== PULL DRAM RESETB DOWN end =========
604 09:29:18.093229 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 09:29:18.097176 ===================================
606 09:29:18.100397 LPDDR4 DRAM CONFIGURATION
607 09:29:18.104420 ===================================
608 09:29:18.104503 EX_ROW_EN[0] = 0x0
609 09:29:18.107584 EX_ROW_EN[1] = 0x0
610 09:29:18.107705 LP4Y_EN = 0x0
611 09:29:18.111494 WORK_FSP = 0x0
612 09:29:18.111576 WL = 0x2
613 09:29:18.114818 RL = 0x2
614 09:29:18.114900 BL = 0x2
615 09:29:18.118878 RPST = 0x0
616 09:29:18.118961 RD_PRE = 0x0
617 09:29:18.119026 WR_PRE = 0x1
618 09:29:18.122686 WR_PST = 0x0
619 09:29:18.122768 DBI_WR = 0x0
620 09:29:18.125870 DBI_RD = 0x0
621 09:29:18.129106 OTF = 0x1
622 09:29:18.129189 ===================================
623 09:29:18.132291 ===================================
624 09:29:18.135997 ANA top config
625 09:29:18.139145 ===================================
626 09:29:18.142988 DLL_ASYNC_EN = 0
627 09:29:18.143071 ALL_SLAVE_EN = 1
628 09:29:18.146088 NEW_RANK_MODE = 1
629 09:29:18.149384 DLL_IDLE_MODE = 1
630 09:29:18.152683 LP45_APHY_COMB_EN = 1
631 09:29:18.152766 TX_ODT_DIS = 1
632 09:29:18.156749 NEW_8X_MODE = 1
633 09:29:18.160053 ===================================
634 09:29:18.163327 ===================================
635 09:29:18.166550 data_rate = 1600
636 09:29:18.170266 CKR = 1
637 09:29:18.173391 DQ_P2S_RATIO = 8
638 09:29:18.173474 ===================================
639 09:29:18.176339 CA_P2S_RATIO = 8
640 09:29:18.180257 DQ_CA_OPEN = 0
641 09:29:18.183442 DQ_SEMI_OPEN = 0
642 09:29:18.186513 CA_SEMI_OPEN = 0
643 09:29:18.190024 CA_FULL_RATE = 0
644 09:29:18.190107 DQ_CKDIV4_EN = 1
645 09:29:18.193626 CA_CKDIV4_EN = 1
646 09:29:18.196627 CA_PREDIV_EN = 0
647 09:29:18.200195 PH8_DLY = 0
648 09:29:18.203103 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 09:29:18.206501 DQ_AAMCK_DIV = 4
650 09:29:18.206609 CA_AAMCK_DIV = 4
651 09:29:18.210338 CA_ADMCK_DIV = 4
652 09:29:18.213595 DQ_TRACK_CA_EN = 0
653 09:29:18.216883 CA_PICK = 800
654 09:29:18.220192 CA_MCKIO = 800
655 09:29:18.224036 MCKIO_SEMI = 0
656 09:29:18.224119 PLL_FREQ = 3068
657 09:29:18.227914 DQ_UI_PI_RATIO = 32
658 09:29:18.231670 CA_UI_PI_RATIO = 0
659 09:29:18.235038 ===================================
660 09:29:18.238886 ===================================
661 09:29:18.238968 memory_type:LPDDR4
662 09:29:18.242629 GP_NUM : 10
663 09:29:18.242711 SRAM_EN : 1
664 09:29:18.246318 MD32_EN : 0
665 09:29:18.250162 ===================================
666 09:29:18.250281 [ANA_INIT] >>>>>>>>>>>>>>
667 09:29:18.253900 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 09:29:18.257140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:29:18.260654 ===================================
670 09:29:18.264068 data_rate = 1600,PCW = 0X7600
671 09:29:18.267474 ===================================
672 09:29:18.270875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 09:29:18.277410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:29:18.280674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 09:29:18.287210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 09:29:18.290707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:29:18.293998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 09:29:18.294081 [ANA_INIT] flow start
679 09:29:18.297263 [ANA_INIT] PLL >>>>>>>>
680 09:29:18.300438 [ANA_INIT] PLL <<<<<<<<
681 09:29:18.300520 [ANA_INIT] MIDPI >>>>>>>>
682 09:29:18.303999 [ANA_INIT] MIDPI <<<<<<<<
683 09:29:18.307207 [ANA_INIT] DLL >>>>>>>>
684 09:29:18.307290 [ANA_INIT] flow end
685 09:29:18.314047 ============ LP4 DIFF to SE enter ============
686 09:29:18.317034 ============ LP4 DIFF to SE exit ============
687 09:29:18.320773 [ANA_INIT] <<<<<<<<<<<<<
688 09:29:18.324307 [Flow] Enable top DCM control >>>>>
689 09:29:18.327603 [Flow] Enable top DCM control <<<<<
690 09:29:18.327725 Enable DLL master slave shuffle
691 09:29:18.334311 ==============================================================
692 09:29:18.337661 Gating Mode config
693 09:29:18.341075 ==============================================================
694 09:29:18.344436 Config description:
695 09:29:18.353881 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 09:29:18.360663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 09:29:18.364363 SELPH_MODE 0: By rank 1: By Phase
698 09:29:18.370533 ==============================================================
699 09:29:18.373992 GAT_TRACK_EN = 1
700 09:29:18.377434 RX_GATING_MODE = 2
701 09:29:18.380749 RX_GATING_TRACK_MODE = 2
702 09:29:18.380850 SELPH_MODE = 1
703 09:29:18.384201 PICG_EARLY_EN = 1
704 09:29:18.387562 VALID_LAT_VALUE = 1
705 09:29:18.394497 ==============================================================
706 09:29:18.397799 Enter into Gating configuration >>>>
707 09:29:18.401045 Exit from Gating configuration <<<<
708 09:29:18.404154 Enter into DVFS_PRE_config >>>>>
709 09:29:18.414036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 09:29:18.417496 Exit from DVFS_PRE_config <<<<<
711 09:29:18.421288 Enter into PICG configuration >>>>
712 09:29:18.424440 Exit from PICG configuration <<<<
713 09:29:18.427472 [RX_INPUT] configuration >>>>>
714 09:29:18.431178 [RX_INPUT] configuration <<<<<
715 09:29:18.434498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 09:29:18.441076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 09:29:18.447580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 09:29:18.450775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 09:29:18.457482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 09:29:18.464290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 09:29:18.467624 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 09:29:18.470994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 09:29:18.477989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 09:29:18.481442 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 09:29:18.484692 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 09:29:18.490914 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 09:29:18.494311 ===================================
728 09:29:18.494394 LPDDR4 DRAM CONFIGURATION
729 09:29:18.497561 ===================================
730 09:29:18.501331 EX_ROW_EN[0] = 0x0
731 09:29:18.501430 EX_ROW_EN[1] = 0x0
732 09:29:18.504734 LP4Y_EN = 0x0
733 09:29:18.504816 WORK_FSP = 0x0
734 09:29:18.508047 WL = 0x2
735 09:29:18.508129 RL = 0x2
736 09:29:18.511308 BL = 0x2
737 09:29:18.514409 RPST = 0x0
738 09:29:18.514492 RD_PRE = 0x0
739 09:29:18.517658 WR_PRE = 0x1
740 09:29:18.517740 WR_PST = 0x0
741 09:29:18.521114 DBI_WR = 0x0
742 09:29:18.521196 DBI_RD = 0x0
743 09:29:18.524172 OTF = 0x1
744 09:29:18.527488 ===================================
745 09:29:18.531378 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 09:29:18.534466 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 09:29:18.537612 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 09:29:18.541311 ===================================
749 09:29:18.544784 LPDDR4 DRAM CONFIGURATION
750 09:29:18.547992 ===================================
751 09:29:18.551141 EX_ROW_EN[0] = 0x10
752 09:29:18.551246 EX_ROW_EN[1] = 0x0
753 09:29:18.554273 LP4Y_EN = 0x0
754 09:29:18.554354 WORK_FSP = 0x0
755 09:29:18.558117 WL = 0x2
756 09:29:18.558200 RL = 0x2
757 09:29:18.561401 BL = 0x2
758 09:29:18.561484 RPST = 0x0
759 09:29:18.564699 RD_PRE = 0x0
760 09:29:18.564781 WR_PRE = 0x1
761 09:29:18.568126 WR_PST = 0x0
762 09:29:18.568209 DBI_WR = 0x0
763 09:29:18.571388 DBI_RD = 0x0
764 09:29:18.571470 OTF = 0x1
765 09:29:18.574719 ===================================
766 09:29:18.581439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 09:29:18.586448 nWR fixed to 40
768 09:29:18.589517 [ModeRegInit_LP4] CH0 RK0
769 09:29:18.589599 [ModeRegInit_LP4] CH0 RK1
770 09:29:18.592780 [ModeRegInit_LP4] CH1 RK0
771 09:29:18.596150 [ModeRegInit_LP4] CH1 RK1
772 09:29:18.596232 match AC timing 13
773 09:29:18.602649 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 09:29:18.605920 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 09:29:18.608983 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 09:29:18.616052 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 09:29:18.619331 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 09:29:18.619415 [EMI DOE] emi_dcm 0
779 09:29:18.626178 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 09:29:18.626286 ==
781 09:29:18.629492 Dram Type= 6, Freq= 0, CH_0, rank 0
782 09:29:18.632912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 09:29:18.633027 ==
784 09:29:18.639568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 09:29:18.646102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 09:29:18.653273 [CA 0] Center 36 (6~67) winsize 62
787 09:29:18.656520 [CA 1] Center 36 (6~67) winsize 62
788 09:29:18.660317 [CA 2] Center 34 (4~65) winsize 62
789 09:29:18.663373 [CA 3] Center 34 (4~64) winsize 61
790 09:29:18.666589 [CA 4] Center 33 (3~63) winsize 61
791 09:29:18.670032 [CA 5] Center 32 (2~62) winsize 61
792 09:29:18.670115
793 09:29:18.673396 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 09:29:18.673479
795 09:29:18.676939 [CATrainingPosCal] consider 1 rank data
796 09:29:18.680205 u2DelayCellTimex100 = 270/100 ps
797 09:29:18.683353 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 09:29:18.686800 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 09:29:18.693725 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 09:29:18.697073 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 09:29:18.699968 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 09:29:18.703282 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 09:29:18.703390
804 09:29:18.706621 CA PerBit enable=1, Macro0, CA PI delay=32
805 09:29:18.706728
806 09:29:18.709992 [CBTSetCACLKResult] CA Dly = 32
807 09:29:18.710076 CS Dly: 4 (0~35)
808 09:29:18.710142 ==
809 09:29:18.713706 Dram Type= 6, Freq= 0, CH_0, rank 1
810 09:29:18.720601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 09:29:18.720686 ==
812 09:29:18.723816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 09:29:18.730413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 09:29:18.739599 [CA 0] Center 36 (6~67) winsize 62
815 09:29:18.743035 [CA 1] Center 36 (6~67) winsize 62
816 09:29:18.746277 [CA 2] Center 33 (3~64) winsize 62
817 09:29:18.749476 [CA 3] Center 33 (3~64) winsize 62
818 09:29:18.752826 [CA 4] Center 32 (2~63) winsize 62
819 09:29:18.756156 [CA 5] Center 32 (2~63) winsize 62
820 09:29:18.756306
821 09:29:18.759554 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 09:29:18.759696
823 09:29:18.762948 [CATrainingPosCal] consider 2 rank data
824 09:29:18.766252 u2DelayCellTimex100 = 270/100 ps
825 09:29:18.769462 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 09:29:18.773027 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 09:29:18.779863 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
828 09:29:18.783210 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 09:29:18.786575 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 09:29:18.789795 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 09:29:18.789878
832 09:29:18.793050 CA PerBit enable=1, Macro0, CA PI delay=32
833 09:29:18.793134
834 09:29:18.796253 [CBTSetCACLKResult] CA Dly = 32
835 09:29:18.796337 CS Dly: 5 (0~37)
836 09:29:18.796402
837 09:29:18.800018 ----->DramcWriteLeveling(PI) begin...
838 09:29:18.803367 ==
839 09:29:18.803490 Dram Type= 6, Freq= 0, CH_0, rank 0
840 09:29:18.807559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 09:29:18.811139 ==
842 09:29:18.811251 Write leveling (Byte 0): 31 => 31
843 09:29:18.814524 Write leveling (Byte 1): 29 => 29
844 09:29:18.818019 DramcWriteLeveling(PI) end<-----
845 09:29:18.818132
846 09:29:18.818233 ==
847 09:29:18.821428 Dram Type= 6, Freq= 0, CH_0, rank 0
848 09:29:18.824594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 09:29:18.828393 ==
850 09:29:18.828500 [Gating] SW mode calibration
851 09:29:18.835171 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 09:29:18.842104 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 09:29:18.845208 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 09:29:18.848565 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 09:29:18.855434 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 09:29:18.858580 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:29:18.861954 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:29:18.868748 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:29:18.872105 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:29:18.875543 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:29:18.882607 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:29:18.885875 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:29:18.888916 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:29:18.892542 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:29:18.899305 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:29:18.902053 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:29:18.905787 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:29:18.912323 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:29:18.915745 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 09:29:18.919162 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 09:29:18.925990 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
872 09:29:18.929333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:29:18.932426 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:29:18.939006 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:29:18.942760 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:29:18.945709 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:29:18.952254 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 09:29:18.956082 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 09:29:18.959395 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 09:29:18.962370 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
881 09:29:18.969227 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:29:18.972628 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:29:18.976103 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:29:18.982795 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 09:29:18.986132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 09:29:18.989414 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
887 09:29:18.996049 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
888 09:29:18.999155 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
889 09:29:19.002871 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:29:19.009364 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:29:19.012652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:29:19.016223 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:29:19.022913 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 09:29:19.026162 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 09:29:19.029552 0 11 8 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
896 09:29:19.036411 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
897 09:29:19.039621 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:29:19.042870 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:29:19.046203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:29:19.052718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 09:29:19.055973 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 09:29:19.059259 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 09:29:19.066012 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 09:29:19.069695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 09:29:19.072719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:29:19.079463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:29:19.082880 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:29:19.086140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:29:19.092754 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:29:19.096180 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:29:19.099462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:29:19.106123 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:29:19.109400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:29:19.113021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:29:19.119788 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:29:19.122910 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 09:29:19.126204 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 09:29:19.129592 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 09:29:19.136415 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 09:29:19.139592 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 09:29:19.142981 Total UI for P1: 0, mck2ui 16
922 09:29:19.146109 best dqsien dly found for B0: ( 0, 14, 6)
923 09:29:19.149903 Total UI for P1: 0, mck2ui 16
924 09:29:19.153608 best dqsien dly found for B1: ( 0, 14, 8)
925 09:29:19.157284 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 09:29:19.160514 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 09:29:19.160597
928 09:29:19.163713 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 09:29:19.167553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 09:29:19.170955 [Gating] SW calibration Done
931 09:29:19.171038 ==
932 09:29:19.174311 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:29:19.177462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:29:19.177546 ==
935 09:29:19.180608 RX Vref Scan: 0
936 09:29:19.180690
937 09:29:19.180756 RX Vref 0 -> 0, step: 1
938 09:29:19.180846
939 09:29:19.183937 RX Delay -130 -> 252, step: 16
940 09:29:19.187602 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 09:29:19.193791 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 09:29:19.197149 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 09:29:19.200468 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 09:29:19.203733 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 09:29:19.207080 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 09:29:19.214031 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 09:29:19.217189 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 09:29:19.220851 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 09:29:19.224086 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 09:29:19.227224 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 09:29:19.234556 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 09:29:19.237201 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 09:29:19.240679 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 09:29:19.243980 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 09:29:19.247333 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 09:29:19.251229 ==
957 09:29:19.251312 Dram Type= 6, Freq= 0, CH_0, rank 0
958 09:29:19.257755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 09:29:19.257866 ==
960 09:29:19.257973 DQS Delay:
961 09:29:19.260840 DQS0 = 0, DQS1 = 0
962 09:29:19.260921 DQM Delay:
963 09:29:19.264176 DQM0 = 90, DQM1 = 85
964 09:29:19.264285 DQ Delay:
965 09:29:19.267994 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
966 09:29:19.271027 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 09:29:19.274539 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
968 09:29:19.277738 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 09:29:19.277822
970 09:29:19.277920
971 09:29:19.278014 ==
972 09:29:19.280972 Dram Type= 6, Freq= 0, CH_0, rank 0
973 09:29:19.284359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 09:29:19.284471 ==
975 09:29:19.284542
976 09:29:19.284610
977 09:29:19.287661 TX Vref Scan disable
978 09:29:19.290963 == TX Byte 0 ==
979 09:29:19.294281 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 09:29:19.297649 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 09:29:19.301254 == TX Byte 1 ==
982 09:29:19.304431 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 09:29:19.307493 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 09:29:19.307601 ==
985 09:29:19.311069 Dram Type= 6, Freq= 0, CH_0, rank 0
986 09:29:19.314559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 09:29:19.314642 ==
988 09:29:19.329073 TX Vref=22, minBit 5, minWin=27, winSum=448
989 09:29:19.332269 TX Vref=24, minBit 9, minWin=27, winSum=450
990 09:29:19.335322 TX Vref=26, minBit 0, minWin=28, winSum=454
991 09:29:19.338500 TX Vref=28, minBit 8, minWin=27, winSum=456
992 09:29:19.341946 TX Vref=30, minBit 8, minWin=28, winSum=458
993 09:29:19.345411 TX Vref=32, minBit 0, minWin=28, winSum=456
994 09:29:19.352280 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
995 09:29:19.352362
996 09:29:19.355533 Final TX Range 1 Vref 30
997 09:29:19.355615
998 09:29:19.355721 ==
999 09:29:19.358652 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 09:29:19.362084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 09:29:19.362172 ==
1002 09:29:19.362271
1003 09:29:19.362366
1004 09:29:19.365410 TX Vref Scan disable
1005 09:29:19.368681 == TX Byte 0 ==
1006 09:29:19.372006 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 09:29:19.375770 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 09:29:19.379072 == TX Byte 1 ==
1009 09:29:19.382552 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 09:29:19.385763 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 09:29:19.385878
1012 09:29:19.389205 [DATLAT]
1013 09:29:19.389311 Freq=800, CH0 RK0
1014 09:29:19.389434
1015 09:29:19.392380 DATLAT Default: 0xa
1016 09:29:19.392490 0, 0xFFFF, sum = 0
1017 09:29:19.395816 1, 0xFFFF, sum = 0
1018 09:29:19.395901 2, 0xFFFF, sum = 0
1019 09:29:19.399284 3, 0xFFFF, sum = 0
1020 09:29:19.399394 4, 0xFFFF, sum = 0
1021 09:29:19.402663 5, 0xFFFF, sum = 0
1022 09:29:19.402773 6, 0xFFFF, sum = 0
1023 09:29:19.406068 7, 0xFFFF, sum = 0
1024 09:29:19.406182 8, 0xFFFF, sum = 0
1025 09:29:19.408924 9, 0x0, sum = 1
1026 09:29:19.409020 10, 0x0, sum = 2
1027 09:29:19.412140 11, 0x0, sum = 3
1028 09:29:19.412250 12, 0x0, sum = 4
1029 09:29:19.415480 best_step = 10
1030 09:29:19.415597
1031 09:29:19.415718 ==
1032 09:29:19.419332 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 09:29:19.422585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 09:29:19.422710 ==
1035 09:29:19.425429 RX Vref Scan: 1
1036 09:29:19.425594
1037 09:29:19.425701 Set Vref Range= 32 -> 127
1038 09:29:19.425807
1039 09:29:19.429171 RX Vref 32 -> 127, step: 1
1040 09:29:19.429348
1041 09:29:19.432572 RX Delay -95 -> 252, step: 8
1042 09:29:19.432679
1043 09:29:19.435465 Set Vref, RX VrefLevel [Byte0]: 32
1044 09:29:19.439076 [Byte1]: 32
1045 09:29:19.439187
1046 09:29:19.442207 Set Vref, RX VrefLevel [Byte0]: 33
1047 09:29:19.445872 [Byte1]: 33
1048 09:29:19.448872
1049 09:29:19.448953 Set Vref, RX VrefLevel [Byte0]: 34
1050 09:29:19.452621 [Byte1]: 34
1051 09:29:19.456822
1052 09:29:19.456933 Set Vref, RX VrefLevel [Byte0]: 35
1053 09:29:19.460225 [Byte1]: 35
1054 09:29:19.464215
1055 09:29:19.464311 Set Vref, RX VrefLevel [Byte0]: 36
1056 09:29:19.468310 [Byte1]: 36
1057 09:29:19.471847
1058 09:29:19.471947 Set Vref, RX VrefLevel [Byte0]: 37
1059 09:29:19.475337 [Byte1]: 37
1060 09:29:19.480143
1061 09:29:19.480252 Set Vref, RX VrefLevel [Byte0]: 38
1062 09:29:19.483162 [Byte1]: 38
1063 09:29:19.486948
1064 09:29:19.487031 Set Vref, RX VrefLevel [Byte0]: 39
1065 09:29:19.490628 [Byte1]: 39
1066 09:29:19.494701
1067 09:29:19.494810 Set Vref, RX VrefLevel [Byte0]: 40
1068 09:29:19.497913 [Byte1]: 40
1069 09:29:19.502128
1070 09:29:19.502239 Set Vref, RX VrefLevel [Byte0]: 41
1071 09:29:19.505450 [Byte1]: 41
1072 09:29:19.509565
1073 09:29:19.509675 Set Vref, RX VrefLevel [Byte0]: 42
1074 09:29:19.512960 [Byte1]: 42
1075 09:29:19.517617
1076 09:29:19.517731 Set Vref, RX VrefLevel [Byte0]: 43
1077 09:29:19.521099 [Byte1]: 43
1078 09:29:19.525100
1079 09:29:19.525183 Set Vref, RX VrefLevel [Byte0]: 44
1080 09:29:19.528411 [Byte1]: 44
1081 09:29:19.532460
1082 09:29:19.532542 Set Vref, RX VrefLevel [Byte0]: 45
1083 09:29:19.535677 [Byte1]: 45
1084 09:29:19.540241
1085 09:29:19.540354 Set Vref, RX VrefLevel [Byte0]: 46
1086 09:29:19.543548 [Byte1]: 46
1087 09:29:19.548028
1088 09:29:19.548116 Set Vref, RX VrefLevel [Byte0]: 47
1089 09:29:19.551028 [Byte1]: 47
1090 09:29:19.555079
1091 09:29:19.555172 Set Vref, RX VrefLevel [Byte0]: 48
1092 09:29:19.558994 [Byte1]: 48
1093 09:29:19.562911
1094 09:29:19.562995 Set Vref, RX VrefLevel [Byte0]: 49
1095 09:29:19.566489 [Byte1]: 49
1096 09:29:19.570527
1097 09:29:19.570611 Set Vref, RX VrefLevel [Byte0]: 50
1098 09:29:19.574013 [Byte1]: 50
1099 09:29:19.578012
1100 09:29:19.578096 Set Vref, RX VrefLevel [Byte0]: 51
1101 09:29:19.581613 [Byte1]: 51
1102 09:29:19.585712
1103 09:29:19.585794 Set Vref, RX VrefLevel [Byte0]: 52
1104 09:29:19.588959 [Byte1]: 52
1105 09:29:19.593399
1106 09:29:19.593512 Set Vref, RX VrefLevel [Byte0]: 53
1107 09:29:19.596665 [Byte1]: 53
1108 09:29:19.600995
1109 09:29:19.601119 Set Vref, RX VrefLevel [Byte0]: 54
1110 09:29:19.604147 [Byte1]: 54
1111 09:29:19.608342
1112 09:29:19.608424 Set Vref, RX VrefLevel [Byte0]: 55
1113 09:29:19.611837 [Byte1]: 55
1114 09:29:19.616502
1115 09:29:19.616584 Set Vref, RX VrefLevel [Byte0]: 56
1116 09:29:19.619278 [Byte1]: 56
1117 09:29:19.623995
1118 09:29:19.624076 Set Vref, RX VrefLevel [Byte0]: 57
1119 09:29:19.627352 [Byte1]: 57
1120 09:29:19.631331
1121 09:29:19.631438 Set Vref, RX VrefLevel [Byte0]: 58
1122 09:29:19.634680 [Byte1]: 58
1123 09:29:19.638682
1124 09:29:19.638764 Set Vref, RX VrefLevel [Byte0]: 59
1125 09:29:19.642406 [Byte1]: 59
1126 09:29:19.646793
1127 09:29:19.646874 Set Vref, RX VrefLevel [Byte0]: 60
1128 09:29:19.650205 [Byte1]: 60
1129 09:29:19.654136
1130 09:29:19.654217 Set Vref, RX VrefLevel [Byte0]: 61
1131 09:29:19.657491 [Byte1]: 61
1132 09:29:19.662070
1133 09:29:19.662150 Set Vref, RX VrefLevel [Byte0]: 62
1134 09:29:19.665497 [Byte1]: 62
1135 09:29:19.669257
1136 09:29:19.669338 Set Vref, RX VrefLevel [Byte0]: 63
1137 09:29:19.672826 [Byte1]: 63
1138 09:29:19.676726
1139 09:29:19.676820 Set Vref, RX VrefLevel [Byte0]: 64
1140 09:29:19.680306 [Byte1]: 64
1141 09:29:19.684587
1142 09:29:19.684667 Set Vref, RX VrefLevel [Byte0]: 65
1143 09:29:19.688081 [Byte1]: 65
1144 09:29:19.692455
1145 09:29:19.692535 Set Vref, RX VrefLevel [Byte0]: 66
1146 09:29:19.695376 [Byte1]: 66
1147 09:29:19.700069
1148 09:29:19.700169 Set Vref, RX VrefLevel [Byte0]: 67
1149 09:29:19.702983 [Byte1]: 67
1150 09:29:19.707498
1151 09:29:19.707580 Set Vref, RX VrefLevel [Byte0]: 68
1152 09:29:19.710771 [Byte1]: 68
1153 09:29:19.715135
1154 09:29:19.715243 Set Vref, RX VrefLevel [Byte0]: 69
1155 09:29:19.718404 [Byte1]: 69
1156 09:29:19.722412
1157 09:29:19.722493 Set Vref, RX VrefLevel [Byte0]: 70
1158 09:29:19.725759 [Byte1]: 70
1159 09:29:19.729849
1160 09:29:19.729931 Set Vref, RX VrefLevel [Byte0]: 71
1161 09:29:19.733202 [Byte1]: 71
1162 09:29:19.738056
1163 09:29:19.738138 Set Vref, RX VrefLevel [Byte0]: 72
1164 09:29:19.740808 [Byte1]: 72
1165 09:29:19.745544
1166 09:29:19.745625 Set Vref, RX VrefLevel [Byte0]: 73
1167 09:29:19.748995 [Byte1]: 73
1168 09:29:19.752891
1169 09:29:19.752972 Set Vref, RX VrefLevel [Byte0]: 74
1170 09:29:19.756226 [Byte1]: 74
1171 09:29:19.760838
1172 09:29:19.760920 Set Vref, RX VrefLevel [Byte0]: 75
1173 09:29:19.764027 [Byte1]: 75
1174 09:29:19.768111
1175 09:29:19.768193 Set Vref, RX VrefLevel [Byte0]: 76
1176 09:29:19.771350 [Byte1]: 76
1177 09:29:19.775997
1178 09:29:19.776078 Final RX Vref Byte 0 = 61 to rank0
1179 09:29:19.779197 Final RX Vref Byte 1 = 61 to rank0
1180 09:29:19.782345 Final RX Vref Byte 0 = 61 to rank1
1181 09:29:19.786014 Final RX Vref Byte 1 = 61 to rank1==
1182 09:29:19.789070 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 09:29:19.792181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 09:29:19.795852 ==
1185 09:29:19.795934 DQS Delay:
1186 09:29:19.795998 DQS0 = 0, DQS1 = 0
1187 09:29:19.799489 DQM Delay:
1188 09:29:19.799571 DQM0 = 92, DQM1 = 85
1189 09:29:19.802951 DQ Delay:
1190 09:29:19.803033 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1191 09:29:19.806073 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1192 09:29:19.809526 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1193 09:29:19.812616 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1194 09:29:19.812723
1195 09:29:19.815997
1196 09:29:19.823000 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1197 09:29:19.825954 CH0 RK0: MR19=606, MR18=4B41
1198 09:29:19.833105 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1199 09:29:19.833218
1200 09:29:19.835882 ----->DramcWriteLeveling(PI) begin...
1201 09:29:19.835964 ==
1202 09:29:19.839316 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 09:29:19.842657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 09:29:19.842739 ==
1205 09:29:19.845971 Write leveling (Byte 0): 33 => 33
1206 09:29:19.849255 Write leveling (Byte 1): 29 => 29
1207 09:29:19.852567 DramcWriteLeveling(PI) end<-----
1208 09:29:19.852648
1209 09:29:19.852712 ==
1210 09:29:19.855769 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 09:29:19.859064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 09:29:19.859146 ==
1213 09:29:19.862465 [Gating] SW mode calibration
1214 09:29:19.869355 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 09:29:19.876007 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 09:29:19.920187 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 09:29:19.920988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 09:29:19.921080 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1219 09:29:19.921350 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:29:19.921435 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:29:19.921726 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:29:19.922013 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:29:19.922105 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:29:19.922431 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:29:19.922513 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:29:19.964530 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:29:19.964887 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:29:19.964970 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:29:19.965053 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:29:19.965149 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:29:19.965260 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:29:19.965353 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 09:29:19.965446 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1234 09:29:19.965770 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1235 09:29:19.966055 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:29:20.008187 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:29:20.008601 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 09:29:20.008690 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 09:29:20.008755 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 09:29:20.008816 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 09:29:20.008874 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 09:29:20.008931 0 9 8 | B1->B0 | 2b2b 2929 | 1 1 | (1 1) (1 1)
1243 09:29:20.008986 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 09:29:20.009405 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 09:29:20.009670 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 09:29:20.052181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 09:29:20.052312 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 09:29:20.052598 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 09:29:20.052699 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1250 09:29:20.052803 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 0)
1251 09:29:20.052917 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:29:20.053012 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 09:29:20.053126 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 09:29:20.053267 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 09:29:20.053864 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 09:29:20.093340 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 09:29:20.093555 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1258 09:29:20.093915 0 11 8 | B1->B0 | 4141 4040 | 0 0 | (0 0) (0 0)
1259 09:29:20.094032 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 09:29:20.094131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 09:29:20.094242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 09:29:20.094330 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 09:29:20.094416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 09:29:20.094515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 09:29:20.097533 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 09:29:20.100999 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1267 09:29:20.104367 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 09:29:20.107322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:29:20.110661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:29:20.117501 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 09:29:20.120953 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:29:20.124414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:29:20.130575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:29:20.134084 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:29:20.137351 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 09:29:20.144054 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 09:29:20.147453 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 09:29:20.150984 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:29:20.157633 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 09:29:20.160918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 09:29:20.164096 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 09:29:20.167734 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 09:29:20.171126 Total UI for P1: 0, mck2ui 16
1284 09:29:20.174207 best dqsien dly found for B0: ( 0, 14, 6)
1285 09:29:20.178026 Total UI for P1: 0, mck2ui 16
1286 09:29:20.181177 best dqsien dly found for B1: ( 0, 14, 6)
1287 09:29:20.184407 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1288 09:29:20.187843 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1289 09:29:20.187927
1290 09:29:20.194637 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1291 09:29:20.197696 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 09:29:20.197820 [Gating] SW calibration Done
1293 09:29:20.201054 ==
1294 09:29:20.204408 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 09:29:20.207786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 09:29:20.207872 ==
1297 09:29:20.207937 RX Vref Scan: 0
1298 09:29:20.207996
1299 09:29:20.211227 RX Vref 0 -> 0, step: 1
1300 09:29:20.211309
1301 09:29:20.214376 RX Delay -130 -> 252, step: 16
1302 09:29:20.217834 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1303 09:29:20.221365 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1304 09:29:20.224788 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1305 09:29:20.231574 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1306 09:29:20.234927 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1307 09:29:20.238136 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1308 09:29:20.241226 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1309 09:29:20.244552 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1310 09:29:20.251632 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1311 09:29:20.254972 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1312 09:29:20.258198 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1313 09:29:20.261524 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1314 09:29:20.264792 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1315 09:29:20.271913 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1316 09:29:20.275107 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1317 09:29:20.277999 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1318 09:29:20.278081 ==
1319 09:29:20.281496 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 09:29:20.285243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 09:29:20.285325 ==
1322 09:29:20.288273 DQS Delay:
1323 09:29:20.288355 DQS0 = 0, DQS1 = 0
1324 09:29:20.291557 DQM Delay:
1325 09:29:20.291705 DQM0 = 93, DQM1 = 85
1326 09:29:20.291772 DQ Delay:
1327 09:29:20.294897 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1328 09:29:20.298014 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1329 09:29:20.301683 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1330 09:29:20.304958 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1331 09:29:20.305039
1332 09:29:20.305149
1333 09:29:20.308139 ==
1334 09:29:20.308223 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 09:29:20.314845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 09:29:20.314928 ==
1337 09:29:20.314994
1338 09:29:20.315054
1339 09:29:20.315112 TX Vref Scan disable
1340 09:29:20.319216 == TX Byte 0 ==
1341 09:29:20.322170 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1342 09:29:20.325638 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1343 09:29:20.328754 == TX Byte 1 ==
1344 09:29:20.332024 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1345 09:29:20.335328 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1346 09:29:20.338745 ==
1347 09:29:20.342114 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 09:29:20.345338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 09:29:20.345445 ==
1350 09:29:20.358116 TX Vref=22, minBit 8, minWin=27, winSum=446
1351 09:29:20.361602 TX Vref=24, minBit 10, minWin=27, winSum=449
1352 09:29:20.364912 TX Vref=26, minBit 1, minWin=28, winSum=455
1353 09:29:20.368260 TX Vref=28, minBit 2, minWin=28, winSum=454
1354 09:29:20.371585 TX Vref=30, minBit 6, minWin=28, winSum=458
1355 09:29:20.374940 TX Vref=32, minBit 2, minWin=28, winSum=455
1356 09:29:20.381427 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 30
1357 09:29:20.381509
1358 09:29:20.384994 Final TX Range 1 Vref 30
1359 09:29:20.385076
1360 09:29:20.385139 ==
1361 09:29:20.388719 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 09:29:20.391809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 09:29:20.391945 ==
1364 09:29:20.392037
1365 09:29:20.394946
1366 09:29:20.395027 TX Vref Scan disable
1367 09:29:20.398118 == TX Byte 0 ==
1368 09:29:20.401559 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1369 09:29:20.405259 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1370 09:29:20.408271 == TX Byte 1 ==
1371 09:29:20.412066 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1372 09:29:20.415514 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1373 09:29:20.418842
1374 09:29:20.418942 [DATLAT]
1375 09:29:20.419036 Freq=800, CH0 RK1
1376 09:29:20.419128
1377 09:29:20.422231 DATLAT Default: 0xa
1378 09:29:20.422312 0, 0xFFFF, sum = 0
1379 09:29:20.425382 1, 0xFFFF, sum = 0
1380 09:29:20.425464 2, 0xFFFF, sum = 0
1381 09:29:20.428658 3, 0xFFFF, sum = 0
1382 09:29:20.428741 4, 0xFFFF, sum = 0
1383 09:29:20.431948 5, 0xFFFF, sum = 0
1384 09:29:20.432032 6, 0xFFFF, sum = 0
1385 09:29:20.435100 7, 0xFFFF, sum = 0
1386 09:29:20.435271 8, 0xFFFF, sum = 0
1387 09:29:20.438650 9, 0x0, sum = 1
1388 09:29:20.438734 10, 0x0, sum = 2
1389 09:29:20.441626 11, 0x0, sum = 3
1390 09:29:20.441740 12, 0x0, sum = 4
1391 09:29:20.445141 best_step = 10
1392 09:29:20.445224
1393 09:29:20.445288 ==
1394 09:29:20.449016 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 09:29:20.451795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 09:29:20.452084 ==
1397 09:29:20.455092 RX Vref Scan: 0
1398 09:29:20.455228
1399 09:29:20.455296 RX Vref 0 -> 0, step: 1
1400 09:29:20.455357
1401 09:29:20.458355 RX Delay -95 -> 252, step: 8
1402 09:29:20.465533 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1403 09:29:20.468991 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1404 09:29:20.472440 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 09:29:20.475844 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1406 09:29:20.479309 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 09:29:20.482018 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1408 09:29:20.488835 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 09:29:20.492144 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 09:29:20.495377 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1411 09:29:20.499228 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1412 09:29:20.502858 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1413 09:29:20.509519 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1414 09:29:20.512933 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1415 09:29:20.516151 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1416 09:29:20.519207 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 09:29:20.522654 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1418 09:29:20.526404 ==
1419 09:29:20.529580 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 09:29:20.532831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 09:29:20.533182 ==
1422 09:29:20.533454 DQS Delay:
1423 09:29:20.536148 DQS0 = 0, DQS1 = 0
1424 09:29:20.536491 DQM Delay:
1425 09:29:20.539560 DQM0 = 92, DQM1 = 83
1426 09:29:20.540025 DQ Delay:
1427 09:29:20.543023 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1428 09:29:20.546424 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1429 09:29:20.549451 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1430 09:29:20.552745 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1431 09:29:20.553092
1432 09:29:20.553363
1433 09:29:20.559925 [DQSOSCAuto] RK1, (LSB)MR18= 0x4515, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1434 09:29:20.563632 CH0 RK1: MR19=606, MR18=4515
1435 09:29:20.569849 CH0_RK1: MR19=0x606, MR18=0x4515, DQSOSC=392, MR23=63, INC=96, DEC=64
1436 09:29:20.573732 [RxdqsGatingPostProcess] freq 800
1437 09:29:20.576100 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 09:29:20.579893 Pre-setting of DQS Precalculation
1439 09:29:20.586320 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 09:29:20.586696 ==
1441 09:29:20.589745 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 09:29:20.592917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 09:29:20.593307 ==
1444 09:29:20.599525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 09:29:20.606024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 09:29:20.613666 [CA 0] Center 36 (6~67) winsize 62
1447 09:29:20.616875 [CA 1] Center 36 (6~67) winsize 62
1448 09:29:20.620438 [CA 2] Center 34 (4~65) winsize 62
1449 09:29:20.623884 [CA 3] Center 34 (4~65) winsize 62
1450 09:29:20.627182 [CA 4] Center 35 (5~65) winsize 61
1451 09:29:20.630564 [CA 5] Center 34 (4~64) winsize 61
1452 09:29:20.631102
1453 09:29:20.634067 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1454 09:29:20.634456
1455 09:29:20.637103 [CATrainingPosCal] consider 1 rank data
1456 09:29:20.640662 u2DelayCellTimex100 = 270/100 ps
1457 09:29:20.644086 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 09:29:20.647531 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 09:29:20.654213 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 09:29:20.657784 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 09:29:20.661219 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1462 09:29:20.664339 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1463 09:29:20.664729
1464 09:29:20.667808 CA PerBit enable=1, Macro0, CA PI delay=34
1465 09:29:20.668197
1466 09:29:20.670977 [CBTSetCACLKResult] CA Dly = 34
1467 09:29:20.671509 CS Dly: 6 (0~37)
1468 09:29:20.671912 ==
1469 09:29:20.674308 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 09:29:20.681030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 09:29:20.681496 ==
1472 09:29:20.684605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 09:29:20.691553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 09:29:20.700097 [CA 0] Center 36 (6~67) winsize 62
1475 09:29:20.703403 [CA 1] Center 36 (6~67) winsize 62
1476 09:29:20.706632 [CA 2] Center 35 (4~66) winsize 63
1477 09:29:20.710953 [CA 3] Center 34 (4~65) winsize 62
1478 09:29:20.714227 [CA 4] Center 35 (4~66) winsize 63
1479 09:29:20.717979 [CA 5] Center 34 (4~65) winsize 62
1480 09:29:20.718512
1481 09:29:20.721362 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1482 09:29:20.721776
1483 09:29:20.725100 [CATrainingPosCal] consider 2 rank data
1484 09:29:20.728891 u2DelayCellTimex100 = 270/100 ps
1485 09:29:20.732398 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 09:29:20.736309 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 09:29:20.740310 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 09:29:20.743765 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 09:29:20.746881 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1490 09:29:20.750214 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 09:29:20.750632
1492 09:29:20.753381 CA PerBit enable=1, Macro0, CA PI delay=34
1493 09:29:20.753852
1494 09:29:20.757090 [CBTSetCACLKResult] CA Dly = 34
1495 09:29:20.757512 CS Dly: 6 (0~38)
1496 09:29:20.757894
1497 09:29:20.760752 ----->DramcWriteLeveling(PI) begin...
1498 09:29:20.761179 ==
1499 09:29:20.763631 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 09:29:20.770305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 09:29:20.770695 ==
1502 09:29:20.774007 Write leveling (Byte 0): 29 => 29
1503 09:29:20.777673 Write leveling (Byte 1): 30 => 30
1504 09:29:20.778158 DramcWriteLeveling(PI) end<-----
1505 09:29:20.778471
1506 09:29:20.780531 ==
1507 09:29:20.780958 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 09:29:20.787373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 09:29:20.787913 ==
1510 09:29:20.790534 [Gating] SW mode calibration
1511 09:29:20.796987 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 09:29:20.800352 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 09:29:20.806985 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 09:29:20.810176 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1515 09:29:20.813851 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 09:29:20.820688 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 09:29:20.824021 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:29:20.827162 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:29:20.830464 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:29:20.837307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:29:20.840596 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:29:20.844113 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:29:20.850664 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:29:20.853960 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:29:20.857648 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:29:20.863865 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:29:20.867315 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:29:20.870773 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:29:20.877160 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 09:29:20.880725 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 09:29:20.884080 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 09:29:20.890321 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:29:20.894050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:29:20.897515 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 09:29:20.903534 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 09:29:20.907042 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 09:29:20.910484 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 09:29:20.916968 0 9 4 | B1->B0 | 2323 2424 | 1 1 | (1 1) (1 1)
1539 09:29:20.920354 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1540 09:29:20.923564 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 09:29:20.926986 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 09:29:20.934221 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 09:29:20.937473 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 09:29:20.940759 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 09:29:20.947748 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 09:29:20.950624 0 10 4 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
1547 09:29:20.954401 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1548 09:29:20.960835 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 09:29:20.964149 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 09:29:20.967776 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 09:29:20.973899 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 09:29:20.976989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 09:29:20.980933 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 09:29:20.983932 0 11 4 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (0 0)
1555 09:29:20.990915 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1556 09:29:20.993860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 09:29:20.997666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 09:29:21.004135 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 09:29:21.007313 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 09:29:21.010657 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 09:29:21.017481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 09:29:21.020661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 09:29:21.024482 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 09:29:21.030612 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 09:29:21.034029 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:29:21.037324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:29:21.044412 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:29:21.047880 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:29:21.050749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:29:21.057439 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:29:21.060723 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:29:21.063607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:29:21.071066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:29:21.074020 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 09:29:21.077317 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 09:29:21.084515 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 09:29:21.087357 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 09:29:21.090648 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1579 09:29:21.093913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1580 09:29:21.097331 Total UI for P1: 0, mck2ui 16
1581 09:29:21.101083 best dqsien dly found for B1: ( 0, 14, 4)
1582 09:29:21.107563 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 09:29:21.107874 Total UI for P1: 0, mck2ui 16
1584 09:29:21.114420 best dqsien dly found for B0: ( 0, 14, 6)
1585 09:29:21.117782 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1586 09:29:21.120616 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 09:29:21.120890
1588 09:29:21.124012 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1589 09:29:21.127358 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 09:29:21.130643 [Gating] SW calibration Done
1591 09:29:21.130916 ==
1592 09:29:21.134133 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 09:29:21.137598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 09:29:21.137872 ==
1595 09:29:21.140951 RX Vref Scan: 0
1596 09:29:21.141224
1597 09:29:21.141438 RX Vref 0 -> 0, step: 1
1598 09:29:21.141641
1599 09:29:21.144455 RX Delay -130 -> 252, step: 16
1600 09:29:21.147735 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 09:29:21.154041 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1602 09:29:21.157461 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1603 09:29:21.161062 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1604 09:29:21.164548 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1605 09:29:21.167878 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1606 09:29:21.174267 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1607 09:29:21.177508 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1608 09:29:21.180812 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1609 09:29:21.184533 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1610 09:29:21.187766 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1611 09:29:21.194093 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1612 09:29:21.197490 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 09:29:21.200894 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1614 09:29:21.204404 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1615 09:29:21.207528 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1616 09:29:21.207768 ==
1617 09:29:21.211427 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 09:29:21.217528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 09:29:21.217610 ==
1620 09:29:21.217675 DQS Delay:
1621 09:29:21.221021 DQS0 = 0, DQS1 = 0
1622 09:29:21.221103 DQM Delay:
1623 09:29:21.221168 DQM0 = 93, DQM1 = 87
1624 09:29:21.224273 DQ Delay:
1625 09:29:21.227508 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1626 09:29:21.231003 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1627 09:29:21.234354 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1628 09:29:21.237778 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1629 09:29:21.237859
1630 09:29:21.237922
1631 09:29:21.237981 ==
1632 09:29:21.241243 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 09:29:21.244512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 09:29:21.244594 ==
1635 09:29:21.244658
1636 09:29:21.244716
1637 09:29:21.247946 TX Vref Scan disable
1638 09:29:21.248026 == TX Byte 0 ==
1639 09:29:21.254693 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 09:29:21.257457 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 09:29:21.257537 == TX Byte 1 ==
1642 09:29:21.264343 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1643 09:29:21.267751 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1644 09:29:21.267832 ==
1645 09:29:21.271148 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 09:29:21.274450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 09:29:21.274544 ==
1648 09:29:21.289325 TX Vref=22, minBit 1, minWin=26, winSum=436
1649 09:29:21.292405 TX Vref=24, minBit 3, minWin=26, winSum=441
1650 09:29:21.296322 TX Vref=26, minBit 2, minWin=27, winSum=447
1651 09:29:21.299785 TX Vref=28, minBit 2, minWin=27, winSum=449
1652 09:29:21.302804 TX Vref=30, minBit 1, minWin=27, winSum=449
1653 09:29:21.306092 TX Vref=32, minBit 1, minWin=27, winSum=448
1654 09:29:21.313318 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1655 09:29:21.313587
1656 09:29:21.315931 Final TX Range 1 Vref 28
1657 09:29:21.316174
1658 09:29:21.316361 ==
1659 09:29:21.319412 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 09:29:21.322852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 09:29:21.323266 ==
1662 09:29:21.323671
1663 09:29:21.324017
1664 09:29:21.326081 TX Vref Scan disable
1665 09:29:21.329462 == TX Byte 0 ==
1666 09:29:21.332586 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1667 09:29:21.336006 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1668 09:29:21.339562 == TX Byte 1 ==
1669 09:29:21.343008 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1670 09:29:21.346224 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1671 09:29:21.346714
1672 09:29:21.349493 [DATLAT]
1673 09:29:21.349978 Freq=800, CH1 RK0
1674 09:29:21.350470
1675 09:29:21.352876 DATLAT Default: 0xa
1676 09:29:21.353264 0, 0xFFFF, sum = 0
1677 09:29:21.355903 1, 0xFFFF, sum = 0
1678 09:29:21.356325 2, 0xFFFF, sum = 0
1679 09:29:21.359488 3, 0xFFFF, sum = 0
1680 09:29:21.360176 4, 0xFFFF, sum = 0
1681 09:29:21.362669 5, 0xFFFF, sum = 0
1682 09:29:21.363058 6, 0xFFFF, sum = 0
1683 09:29:21.366232 7, 0xFFFF, sum = 0
1684 09:29:21.366620 8, 0xFFFF, sum = 0
1685 09:29:21.369428 9, 0x0, sum = 1
1686 09:29:21.369815 10, 0x0, sum = 2
1687 09:29:21.372981 11, 0x0, sum = 3
1688 09:29:21.373372 12, 0x0, sum = 4
1689 09:29:21.373680 best_step = 10
1690 09:29:21.376464
1691 09:29:21.376843 ==
1692 09:29:21.379997 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 09:29:21.382745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 09:29:21.383190 ==
1695 09:29:21.383678 RX Vref Scan: 1
1696 09:29:21.384036
1697 09:29:21.386166 Set Vref Range= 32 -> 127
1698 09:29:21.386439
1699 09:29:21.389642 RX Vref 32 -> 127, step: 1
1700 09:29:21.389914
1701 09:29:21.393177 RX Delay -79 -> 252, step: 8
1702 09:29:21.393389
1703 09:29:21.396145 Set Vref, RX VrefLevel [Byte0]: 32
1704 09:29:21.399571 [Byte1]: 32
1705 09:29:21.399764
1706 09:29:21.402912 Set Vref, RX VrefLevel [Byte0]: 33
1707 09:29:21.406395 [Byte1]: 33
1708 09:29:21.406522
1709 09:29:21.409937 Set Vref, RX VrefLevel [Byte0]: 34
1710 09:29:21.412585 [Byte1]: 34
1711 09:29:21.412711
1712 09:29:21.416044 Set Vref, RX VrefLevel [Byte0]: 35
1713 09:29:21.419450 [Byte1]: 35
1714 09:29:21.423778
1715 09:29:21.423901 Set Vref, RX VrefLevel [Byte0]: 36
1716 09:29:21.427081 [Byte1]: 36
1717 09:29:21.431307
1718 09:29:21.431430 Set Vref, RX VrefLevel [Byte0]: 37
1719 09:29:21.434319 [Byte1]: 37
1720 09:29:21.438990
1721 09:29:21.439114 Set Vref, RX VrefLevel [Byte0]: 38
1722 09:29:21.442086 [Byte1]: 38
1723 09:29:21.446460
1724 09:29:21.446584 Set Vref, RX VrefLevel [Byte0]: 39
1725 09:29:21.449570 [Byte1]: 39
1726 09:29:21.453945
1727 09:29:21.454070 Set Vref, RX VrefLevel [Byte0]: 40
1728 09:29:21.457053 [Byte1]: 40
1729 09:29:21.461403
1730 09:29:21.461526 Set Vref, RX VrefLevel [Byte0]: 41
1731 09:29:21.464962 [Byte1]: 41
1732 09:29:21.468601
1733 09:29:21.468748 Set Vref, RX VrefLevel [Byte0]: 42
1734 09:29:21.472367 [Byte1]: 42
1735 09:29:21.476546
1736 09:29:21.476684 Set Vref, RX VrefLevel [Byte0]: 43
1737 09:29:21.479622 [Byte1]: 43
1738 09:29:21.484406
1739 09:29:21.484545 Set Vref, RX VrefLevel [Byte0]: 44
1740 09:29:21.487265 [Byte1]: 44
1741 09:29:21.491963
1742 09:29:21.492119 Set Vref, RX VrefLevel [Byte0]: 45
1743 09:29:21.494706 [Byte1]: 45
1744 09:29:21.498991
1745 09:29:21.499146 Set Vref, RX VrefLevel [Byte0]: 46
1746 09:29:21.502506 [Byte1]: 46
1747 09:29:21.506645
1748 09:29:21.506802 Set Vref, RX VrefLevel [Byte0]: 47
1749 09:29:21.509899 [Byte1]: 47
1750 09:29:21.514137
1751 09:29:21.514291 Set Vref, RX VrefLevel [Byte0]: 48
1752 09:29:21.517418 [Byte1]: 48
1753 09:29:21.521534
1754 09:29:21.521716 Set Vref, RX VrefLevel [Byte0]: 49
1755 09:29:21.525087 [Byte1]: 49
1756 09:29:21.529408
1757 09:29:21.529572 Set Vref, RX VrefLevel [Byte0]: 50
1758 09:29:21.532915 [Byte1]: 50
1759 09:29:21.536689
1760 09:29:21.536879 Set Vref, RX VrefLevel [Byte0]: 51
1761 09:29:21.540265 [Byte1]: 51
1762 09:29:21.544529
1763 09:29:21.544737 Set Vref, RX VrefLevel [Byte0]: 52
1764 09:29:21.547852 [Byte1]: 52
1765 09:29:21.552284
1766 09:29:21.552504 Set Vref, RX VrefLevel [Byte0]: 53
1767 09:29:21.555301 [Byte1]: 53
1768 09:29:21.559534
1769 09:29:21.559759 Set Vref, RX VrefLevel [Byte0]: 54
1770 09:29:21.562650 [Byte1]: 54
1771 09:29:21.567122
1772 09:29:21.567437 Set Vref, RX VrefLevel [Byte0]: 55
1773 09:29:21.570532 [Byte1]: 55
1774 09:29:21.575012
1775 09:29:21.575490 Set Vref, RX VrefLevel [Byte0]: 56
1776 09:29:21.578333 [Byte1]: 56
1777 09:29:21.582537
1778 09:29:21.582985 Set Vref, RX VrefLevel [Byte0]: 57
1779 09:29:21.585712 [Byte1]: 57
1780 09:29:21.589831
1781 09:29:21.590206 Set Vref, RX VrefLevel [Byte0]: 58
1782 09:29:21.593523 [Byte1]: 58
1783 09:29:21.597574
1784 09:29:21.598073 Set Vref, RX VrefLevel [Byte0]: 59
1785 09:29:21.600520 [Byte1]: 59
1786 09:29:21.605061
1787 09:29:21.605434 Set Vref, RX VrefLevel [Byte0]: 60
1788 09:29:21.608663 [Byte1]: 60
1789 09:29:21.612445
1790 09:29:21.612822 Set Vref, RX VrefLevel [Byte0]: 61
1791 09:29:21.615942 [Byte1]: 61
1792 09:29:21.619886
1793 09:29:21.620302 Set Vref, RX VrefLevel [Byte0]: 62
1794 09:29:21.623824 [Byte1]: 62
1795 09:29:21.627858
1796 09:29:21.628286 Set Vref, RX VrefLevel [Byte0]: 63
1797 09:29:21.631242 [Byte1]: 63
1798 09:29:21.635443
1799 09:29:21.635932 Set Vref, RX VrefLevel [Byte0]: 64
1800 09:29:21.638685 [Byte1]: 64
1801 09:29:21.642693
1802 09:29:21.643252 Set Vref, RX VrefLevel [Byte0]: 65
1803 09:29:21.645928 [Byte1]: 65
1804 09:29:21.650529
1805 09:29:21.650966 Set Vref, RX VrefLevel [Byte0]: 66
1806 09:29:21.653891 [Byte1]: 66
1807 09:29:21.657773
1808 09:29:21.658295 Set Vref, RX VrefLevel [Byte0]: 67
1809 09:29:21.660840 [Byte1]: 67
1810 09:29:21.665483
1811 09:29:21.665857 Set Vref, RX VrefLevel [Byte0]: 68
1812 09:29:21.668775 [Byte1]: 68
1813 09:29:21.673161
1814 09:29:21.673739 Set Vref, RX VrefLevel [Byte0]: 69
1815 09:29:21.676717 [Byte1]: 69
1816 09:29:21.680619
1817 09:29:21.681047 Set Vref, RX VrefLevel [Byte0]: 70
1818 09:29:21.683923 [Byte1]: 70
1819 09:29:21.688111
1820 09:29:21.688581 Set Vref, RX VrefLevel [Byte0]: 71
1821 09:29:21.691300 [Byte1]: 71
1822 09:29:21.695741
1823 09:29:21.696117 Final RX Vref Byte 0 = 60 to rank0
1824 09:29:21.699124 Final RX Vref Byte 1 = 57 to rank0
1825 09:29:21.702327 Final RX Vref Byte 0 = 60 to rank1
1826 09:29:21.705451 Final RX Vref Byte 1 = 57 to rank1==
1827 09:29:21.709093 Dram Type= 6, Freq= 0, CH_1, rank 0
1828 09:29:21.715349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 09:29:21.715854 ==
1830 09:29:21.716272 DQS Delay:
1831 09:29:21.716561 DQS0 = 0, DQS1 = 0
1832 09:29:21.718772 DQM Delay:
1833 09:29:21.719148 DQM0 = 95, DQM1 = 90
1834 09:29:21.722127 DQ Delay:
1835 09:29:21.725571 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1836 09:29:21.729080 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1837 09:29:21.732433 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1838 09:29:21.735963 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1839 09:29:21.736340
1840 09:29:21.736636
1841 09:29:21.741947 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1842 09:29:21.745389 CH1 RK0: MR19=606, MR18=324F
1843 09:29:21.752555 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1844 09:29:21.752933
1845 09:29:21.755207 ----->DramcWriteLeveling(PI) begin...
1846 09:29:21.755588 ==
1847 09:29:21.758698 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 09:29:21.762009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 09:29:21.762389 ==
1850 09:29:21.765671 Write leveling (Byte 0): 27 => 27
1851 09:29:21.769344 Write leveling (Byte 1): 28 => 28
1852 09:29:21.772091 DramcWriteLeveling(PI) end<-----
1853 09:29:21.772482
1854 09:29:21.772781 ==
1855 09:29:21.775505 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 09:29:21.779301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 09:29:21.779717 ==
1858 09:29:21.782343 [Gating] SW mode calibration
1859 09:29:21.788818 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1860 09:29:21.795403 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1861 09:29:21.799470 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 09:29:21.802332 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1863 09:29:21.809008 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:29:21.812433 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:29:21.815691 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:29:21.822265 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:29:21.825754 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:29:21.829210 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:29:21.835786 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 09:29:21.839092 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:29:21.842624 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 09:29:21.848797 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 09:29:21.852013 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 09:29:21.855497 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 09:29:21.859288 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 09:29:21.866116 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1877 09:29:21.868786 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1878 09:29:21.872325 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1879 09:29:21.879433 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:29:21.882497 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 09:29:21.885981 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 09:29:21.892390 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 09:29:21.895535 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:29:21.899341 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:29:21.905567 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:29:21.909302 0 9 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
1887 09:29:21.912729 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1888 09:29:21.919387 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 09:29:21.922753 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 09:29:21.926050 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 09:29:21.929455 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 09:29:21.935877 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 09:29:21.939035 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1894 09:29:21.942531 0 10 4 | B1->B0 | 2c2c 3030 | 1 1 | (1 0) (1 1)
1895 09:29:21.949423 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1896 09:29:21.953007 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:29:21.956439 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 09:29:21.962333 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 09:29:21.966151 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 09:29:21.969653 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 09:29:21.976486 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:29:21.979931 0 11 4 | B1->B0 | 3e3e 2d2d | 0 0 | (0 0) (0 0)
1903 09:29:21.983201 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1904 09:29:21.989893 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 09:29:21.992602 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 09:29:21.996145 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 09:29:22.003118 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 09:29:22.005984 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 09:29:22.009660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1910 09:29:22.016177 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1911 09:29:22.019315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1912 09:29:22.022966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 09:29:22.026585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 09:29:22.033128 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 09:29:22.036702 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 09:29:22.039523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 09:29:22.046227 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 09:29:22.049442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 09:29:22.052754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 09:29:22.059776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 09:29:22.062900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 09:29:22.066591 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 09:29:22.073031 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 09:29:22.076230 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 09:29:22.079691 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1926 09:29:22.086403 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1927 09:29:22.089759 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 09:29:22.092912 Total UI for P1: 0, mck2ui 16
1929 09:29:22.096112 best dqsien dly found for B0: ( 0, 14, 4)
1930 09:29:22.099975 Total UI for P1: 0, mck2ui 16
1931 09:29:22.102796 best dqsien dly found for B1: ( 0, 14, 2)
1932 09:29:22.106173 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1933 09:29:22.109446 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1934 09:29:22.109825
1935 09:29:22.113266 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1936 09:29:22.116332 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1937 09:29:22.119978 [Gating] SW calibration Done
1938 09:29:22.120358 ==
1939 09:29:22.123040 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 09:29:22.126403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 09:29:22.126795 ==
1942 09:29:22.129700 RX Vref Scan: 0
1943 09:29:22.130094
1944 09:29:22.130392 RX Vref 0 -> 0, step: 1
1945 09:29:22.132930
1946 09:29:22.133308 RX Delay -130 -> 252, step: 16
1947 09:29:22.139610 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1948 09:29:22.143115 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1949 09:29:22.146551 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1950 09:29:22.150017 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1951 09:29:22.153132 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1952 09:29:22.159684 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1953 09:29:22.163083 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1954 09:29:22.166395 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1955 09:29:22.169599 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1956 09:29:22.172922 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1957 09:29:22.176279 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1958 09:29:22.182917 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1959 09:29:22.186357 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1960 09:29:22.189382 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1961 09:29:22.193078 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1962 09:29:22.199748 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1963 09:29:22.200132 ==
1964 09:29:22.202975 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 09:29:22.206093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 09:29:22.206481 ==
1967 09:29:22.206784 DQS Delay:
1968 09:29:22.209429 DQS0 = 0, DQS1 = 0
1969 09:29:22.209812 DQM Delay:
1970 09:29:22.212693 DQM0 = 92, DQM1 = 89
1971 09:29:22.213080 DQ Delay:
1972 09:29:22.216255 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1973 09:29:22.219593 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1974 09:29:22.223284 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1975 09:29:22.226373 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1976 09:29:22.226757
1977 09:29:22.227054
1978 09:29:22.227338 ==
1979 09:29:22.229428 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 09:29:22.233226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 09:29:22.233663 ==
1982 09:29:22.233998
1983 09:29:22.236678
1984 09:29:22.237092 TX Vref Scan disable
1985 09:29:22.239976 == TX Byte 0 ==
1986 09:29:22.243267 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1987 09:29:22.246423 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1988 09:29:22.249584 == TX Byte 1 ==
1989 09:29:22.252972 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1990 09:29:22.256514 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1991 09:29:22.256928 ==
1992 09:29:22.259687 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 09:29:22.266341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 09:29:22.266724 ==
1995 09:29:22.278366 TX Vref=22, minBit 1, minWin=26, winSum=444
1996 09:29:22.281013 TX Vref=24, minBit 0, minWin=27, winSum=446
1997 09:29:22.284967 TX Vref=26, minBit 0, minWin=27, winSum=448
1998 09:29:22.287707 TX Vref=28, minBit 2, minWin=27, winSum=451
1999 09:29:22.291727 TX Vref=30, minBit 2, minWin=27, winSum=451
2000 09:29:22.295024 TX Vref=32, minBit 2, minWin=27, winSum=447
2001 09:29:22.301337 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
2002 09:29:22.301720
2003 09:29:22.304850 Final TX Range 1 Vref 28
2004 09:29:22.305230
2005 09:29:22.305527 ==
2006 09:29:22.308377 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 09:29:22.311627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 09:29:22.312052 ==
2009 09:29:22.312356
2010 09:29:22.312634
2011 09:29:22.314966 TX Vref Scan disable
2012 09:29:22.317995 == TX Byte 0 ==
2013 09:29:22.321954 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2014 09:29:22.325394 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2015 09:29:22.328651 == TX Byte 1 ==
2016 09:29:22.331717 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2017 09:29:22.334909 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2018 09:29:22.335325
2019 09:29:22.338211 [DATLAT]
2020 09:29:22.338622 Freq=800, CH1 RK1
2021 09:29:22.338951
2022 09:29:22.342057 DATLAT Default: 0xa
2023 09:29:22.342473 0, 0xFFFF, sum = 0
2024 09:29:22.345515 1, 0xFFFF, sum = 0
2025 09:29:22.345899 2, 0xFFFF, sum = 0
2026 09:29:22.348289 3, 0xFFFF, sum = 0
2027 09:29:22.348688 4, 0xFFFF, sum = 0
2028 09:29:22.351543 5, 0xFFFF, sum = 0
2029 09:29:22.351975 6, 0xFFFF, sum = 0
2030 09:29:22.354993 7, 0xFFFF, sum = 0
2031 09:29:22.355377 8, 0xFFFF, sum = 0
2032 09:29:22.358529 9, 0x0, sum = 1
2033 09:29:22.358918 10, 0x0, sum = 2
2034 09:29:22.361803 11, 0x0, sum = 3
2035 09:29:22.362188 12, 0x0, sum = 4
2036 09:29:22.365263 best_step = 10
2037 09:29:22.365641
2038 09:29:22.365941 ==
2039 09:29:22.368766 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 09:29:22.371667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 09:29:22.372099 ==
2042 09:29:22.372403 RX Vref Scan: 0
2043 09:29:22.375395
2044 09:29:22.375819 RX Vref 0 -> 0, step: 1
2045 09:29:22.376124
2046 09:29:22.378768 RX Delay -79 -> 252, step: 8
2047 09:29:22.381899 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2048 09:29:22.388704 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2049 09:29:22.392041 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2050 09:29:22.395328 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2051 09:29:22.398852 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2052 09:29:22.402106 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2053 09:29:22.405493 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2054 09:29:22.412093 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2055 09:29:22.415294 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2056 09:29:22.418412 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2057 09:29:22.422019 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2058 09:29:22.425524 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2059 09:29:22.432145 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2060 09:29:22.435340 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2061 09:29:22.438511 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2062 09:29:22.441841 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2063 09:29:22.442258 ==
2064 09:29:22.445545 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 09:29:22.448555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 09:29:22.451672 ==
2067 09:29:22.452104 DQS Delay:
2068 09:29:22.452438 DQS0 = 0, DQS1 = 0
2069 09:29:22.455412 DQM Delay:
2070 09:29:22.455928 DQM0 = 97, DQM1 = 91
2071 09:29:22.458789 DQ Delay:
2072 09:29:22.462167 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2073 09:29:22.465471 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2074 09:29:22.468835 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2075 09:29:22.471983 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2076 09:29:22.472365
2077 09:29:22.472816
2078 09:29:22.478258 [DQSOSCAuto] RK1, (LSB)MR18= 0x4914, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2079 09:29:22.481767 CH1 RK1: MR19=606, MR18=4914
2080 09:29:22.488544 CH1_RK1: MR19=0x606, MR18=0x4914, DQSOSC=391, MR23=63, INC=96, DEC=64
2081 09:29:22.491744 [RxdqsGatingPostProcess] freq 800
2082 09:29:22.494851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2083 09:29:22.498451 Pre-setting of DQS Precalculation
2084 09:29:22.505309 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2085 09:29:22.512105 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2086 09:29:22.518697 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2087 09:29:22.519111
2088 09:29:22.519433
2089 09:29:22.522005 [Calibration Summary] 1600 Mbps
2090 09:29:22.522502 CH 0, Rank 0
2091 09:29:22.525529 SW Impedance : PASS
2092 09:29:22.528812 DUTY Scan : NO K
2093 09:29:22.529224 ZQ Calibration : PASS
2094 09:29:22.532132 Jitter Meter : NO K
2095 09:29:22.532554 CBT Training : PASS
2096 09:29:22.535347 Write leveling : PASS
2097 09:29:22.538843 RX DQS gating : PASS
2098 09:29:22.539255 RX DQ/DQS(RDDQC) : PASS
2099 09:29:22.541848 TX DQ/DQS : PASS
2100 09:29:22.545648 RX DATLAT : PASS
2101 09:29:22.546056 RX DQ/DQS(Engine): PASS
2102 09:29:22.548569 TX OE : NO K
2103 09:29:22.549019 All Pass.
2104 09:29:22.549346
2105 09:29:22.552065 CH 0, Rank 1
2106 09:29:22.552530 SW Impedance : PASS
2107 09:29:22.555589 DUTY Scan : NO K
2108 09:29:22.558557 ZQ Calibration : PASS
2109 09:29:22.559066 Jitter Meter : NO K
2110 09:29:22.561963 CBT Training : PASS
2111 09:29:22.565569 Write leveling : PASS
2112 09:29:22.566009 RX DQS gating : PASS
2113 09:29:22.568496 RX DQ/DQS(RDDQC) : PASS
2114 09:29:22.568960 TX DQ/DQS : PASS
2115 09:29:22.572180 RX DATLAT : PASS
2116 09:29:22.575699 RX DQ/DQS(Engine): PASS
2117 09:29:22.576135 TX OE : NO K
2118 09:29:22.579118 All Pass.
2119 09:29:22.579528
2120 09:29:22.579921 CH 1, Rank 0
2121 09:29:22.582361 SW Impedance : PASS
2122 09:29:22.582775 DUTY Scan : NO K
2123 09:29:22.585679 ZQ Calibration : PASS
2124 09:29:22.588972 Jitter Meter : NO K
2125 09:29:22.589387 CBT Training : PASS
2126 09:29:22.592091 Write leveling : PASS
2127 09:29:22.595774 RX DQS gating : PASS
2128 09:29:22.596193 RX DQ/DQS(RDDQC) : PASS
2129 09:29:22.599374 TX DQ/DQS : PASS
2130 09:29:22.599841 RX DATLAT : PASS
2131 09:29:22.602621 RX DQ/DQS(Engine): PASS
2132 09:29:22.606082 TX OE : NO K
2133 09:29:22.606495 All Pass.
2134 09:29:22.606817
2135 09:29:22.607117 CH 1, Rank 1
2136 09:29:22.609509 SW Impedance : PASS
2137 09:29:22.612892 DUTY Scan : NO K
2138 09:29:22.613303 ZQ Calibration : PASS
2139 09:29:22.616167 Jitter Meter : NO K
2140 09:29:22.619580 CBT Training : PASS
2141 09:29:22.620070 Write leveling : PASS
2142 09:29:22.622239 RX DQS gating : PASS
2143 09:29:22.626169 RX DQ/DQS(RDDQC) : PASS
2144 09:29:22.626633 TX DQ/DQS : PASS
2145 09:29:22.629505 RX DATLAT : PASS
2146 09:29:22.632301 RX DQ/DQS(Engine): PASS
2147 09:29:22.632762 TX OE : NO K
2148 09:29:22.633135 All Pass.
2149 09:29:22.636360
2150 09:29:22.636811 DramC Write-DBI off
2151 09:29:22.638979 PER_BANK_REFRESH: Hybrid Mode
2152 09:29:22.639465 TX_TRACKING: ON
2153 09:29:22.642749 [GetDramInforAfterCalByMRR] Vendor 6.
2154 09:29:22.646048 [GetDramInforAfterCalByMRR] Revision 606.
2155 09:29:22.652935 [GetDramInforAfterCalByMRR] Revision 2 0.
2156 09:29:22.653501 MR0 0x3b3b
2157 09:29:22.653873 MR8 0x5151
2158 09:29:22.656112 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 09:29:22.656589
2160 09:29:22.659401 MR0 0x3b3b
2161 09:29:22.659870 MR8 0x5151
2162 09:29:22.662493 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 09:29:22.662896
2164 09:29:22.673278 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2165 09:29:22.676324 [FAST_K] Save calibration result to emmc
2166 09:29:22.679507 [FAST_K] Save calibration result to emmc
2167 09:29:22.682737 dram_init: config_dvfs: 1
2168 09:29:22.686603 dramc_set_vcore_voltage set vcore to 662500
2169 09:29:22.687218 Read voltage for 1200, 2
2170 09:29:22.689949 Vio18 = 0
2171 09:29:22.690423 Vcore = 662500
2172 09:29:22.690866 Vdram = 0
2173 09:29:22.693123 Vddq = 0
2174 09:29:22.693613 Vmddr = 0
2175 09:29:22.696376 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2176 09:29:22.702590 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2177 09:29:22.706353 MEM_TYPE=3, freq_sel=15
2178 09:29:22.709452 sv_algorithm_assistance_LP4_1600
2179 09:29:22.713257 ============ PULL DRAM RESETB DOWN ============
2180 09:29:22.715935 ========== PULL DRAM RESETB DOWN end =========
2181 09:29:22.719355 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 09:29:22.722684 ===================================
2183 09:29:22.726394 LPDDR4 DRAM CONFIGURATION
2184 09:29:22.729351 ===================================
2185 09:29:22.732728 EX_ROW_EN[0] = 0x0
2186 09:29:22.733167 EX_ROW_EN[1] = 0x0
2187 09:29:22.736026 LP4Y_EN = 0x0
2188 09:29:22.736471 WORK_FSP = 0x0
2189 09:29:22.739416 WL = 0x4
2190 09:29:22.739909 RL = 0x4
2191 09:29:22.743001 BL = 0x2
2192 09:29:22.743453 RPST = 0x0
2193 09:29:22.746281 RD_PRE = 0x0
2194 09:29:22.746739 WR_PRE = 0x1
2195 09:29:22.749899 WR_PST = 0x0
2196 09:29:22.750414 DBI_WR = 0x0
2197 09:29:22.753312 DBI_RD = 0x0
2198 09:29:22.753707 OTF = 0x1
2199 09:29:22.756674 ===================================
2200 09:29:22.759937 ===================================
2201 09:29:22.762971 ANA top config
2202 09:29:22.767064 ===================================
2203 09:29:22.770305 DLL_ASYNC_EN = 0
2204 09:29:22.770730 ALL_SLAVE_EN = 0
2205 09:29:22.773051 NEW_RANK_MODE = 1
2206 09:29:22.776564 DLL_IDLE_MODE = 1
2207 09:29:22.779932 LP45_APHY_COMB_EN = 1
2208 09:29:22.780338 TX_ODT_DIS = 1
2209 09:29:22.783363 NEW_8X_MODE = 1
2210 09:29:22.786592 ===================================
2211 09:29:22.789798 ===================================
2212 09:29:22.793250 data_rate = 2400
2213 09:29:22.797133 CKR = 1
2214 09:29:22.800584 DQ_P2S_RATIO = 8
2215 09:29:22.803591 ===================================
2216 09:29:22.804256 CA_P2S_RATIO = 8
2217 09:29:22.806653 DQ_CA_OPEN = 0
2218 09:29:22.810522 DQ_SEMI_OPEN = 0
2219 09:29:22.813685 CA_SEMI_OPEN = 0
2220 09:29:22.816727 CA_FULL_RATE = 0
2221 09:29:22.820184 DQ_CKDIV4_EN = 0
2222 09:29:22.820601 CA_CKDIV4_EN = 0
2223 09:29:22.823525 CA_PREDIV_EN = 0
2224 09:29:22.826582 PH8_DLY = 17
2225 09:29:22.830383 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2226 09:29:22.833166 DQ_AAMCK_DIV = 4
2227 09:29:22.836733 CA_AAMCK_DIV = 4
2228 09:29:22.837159 CA_ADMCK_DIV = 4
2229 09:29:22.840065 DQ_TRACK_CA_EN = 0
2230 09:29:22.843223 CA_PICK = 1200
2231 09:29:22.846806 CA_MCKIO = 1200
2232 09:29:22.850220 MCKIO_SEMI = 0
2233 09:29:22.853625 PLL_FREQ = 2366
2234 09:29:22.856651 DQ_UI_PI_RATIO = 32
2235 09:29:22.857076 CA_UI_PI_RATIO = 0
2236 09:29:22.860080 ===================================
2237 09:29:22.863282 ===================================
2238 09:29:22.866689 memory_type:LPDDR4
2239 09:29:22.870530 GP_NUM : 10
2240 09:29:22.871004 SRAM_EN : 1
2241 09:29:22.873776 MD32_EN : 0
2242 09:29:22.876486 ===================================
2243 09:29:22.879945 [ANA_INIT] >>>>>>>>>>>>>>
2244 09:29:22.883236 <<<<<< [CONFIGURE PHASE]: ANA_TX
2245 09:29:22.886666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2246 09:29:22.889977 ===================================
2247 09:29:22.890387 data_rate = 2400,PCW = 0X5b00
2248 09:29:22.893836 ===================================
2249 09:29:22.896606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2250 09:29:22.903460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 09:29:22.909978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 09:29:22.913929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2253 09:29:22.917351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2254 09:29:22.920590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2255 09:29:22.923895 [ANA_INIT] flow start
2256 09:29:22.924304 [ANA_INIT] PLL >>>>>>>>
2257 09:29:22.927368 [ANA_INIT] PLL <<<<<<<<
2258 09:29:22.930320 [ANA_INIT] MIDPI >>>>>>>>
2259 09:29:22.930844 [ANA_INIT] MIDPI <<<<<<<<
2260 09:29:22.933560 [ANA_INIT] DLL >>>>>>>>
2261 09:29:22.937501 [ANA_INIT] DLL <<<<<<<<
2262 09:29:22.937913 [ANA_INIT] flow end
2263 09:29:22.944041 ============ LP4 DIFF to SE enter ============
2264 09:29:22.947246 ============ LP4 DIFF to SE exit ============
2265 09:29:22.950519 [ANA_INIT] <<<<<<<<<<<<<
2266 09:29:22.953730 [Flow] Enable top DCM control >>>>>
2267 09:29:22.957342 [Flow] Enable top DCM control <<<<<
2268 09:29:22.957754 Enable DLL master slave shuffle
2269 09:29:22.963524 ==============================================================
2270 09:29:22.967261 Gating Mode config
2271 09:29:22.970575 ==============================================================
2272 09:29:22.973694 Config description:
2273 09:29:22.984029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2274 09:29:22.990734 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2275 09:29:22.994122 SELPH_MODE 0: By rank 1: By Phase
2276 09:29:23.000635 ==============================================================
2277 09:29:23.003920 GAT_TRACK_EN = 1
2278 09:29:23.007283 RX_GATING_MODE = 2
2279 09:29:23.010518 RX_GATING_TRACK_MODE = 2
2280 09:29:23.010932 SELPH_MODE = 1
2281 09:29:23.013739 PICG_EARLY_EN = 1
2282 09:29:23.017106 VALID_LAT_VALUE = 1
2283 09:29:23.023856 ==============================================================
2284 09:29:23.027242 Enter into Gating configuration >>>>
2285 09:29:23.030571 Exit from Gating configuration <<<<
2286 09:29:23.033914 Enter into DVFS_PRE_config >>>>>
2287 09:29:23.043803 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2288 09:29:23.046860 Exit from DVFS_PRE_config <<<<<
2289 09:29:23.050315 Enter into PICG configuration >>>>
2290 09:29:23.053614 Exit from PICG configuration <<<<
2291 09:29:23.057029 [RX_INPUT] configuration >>>>>
2292 09:29:23.060514 [RX_INPUT] configuration <<<<<
2293 09:29:23.063892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2294 09:29:23.070493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2295 09:29:23.076899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 09:29:23.080404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 09:29:23.086925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 09:29:23.093951 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 09:29:23.097492 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2300 09:29:23.100595 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2301 09:29:23.107280 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2302 09:29:23.110970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2303 09:29:23.114254 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2304 09:29:23.120992 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 09:29:23.124496 ===================================
2306 09:29:23.124875 LPDDR4 DRAM CONFIGURATION
2307 09:29:23.127982 ===================================
2308 09:29:23.131048 EX_ROW_EN[0] = 0x0
2309 09:29:23.131457 EX_ROW_EN[1] = 0x0
2310 09:29:23.134391 LP4Y_EN = 0x0
2311 09:29:23.134800 WORK_FSP = 0x0
2312 09:29:23.137864 WL = 0x4
2313 09:29:23.138275 RL = 0x4
2314 09:29:23.141185 BL = 0x2
2315 09:29:23.144484 RPST = 0x0
2316 09:29:23.144892 RD_PRE = 0x0
2317 09:29:23.147830 WR_PRE = 0x1
2318 09:29:23.148242 WR_PST = 0x0
2319 09:29:23.151129 DBI_WR = 0x0
2320 09:29:23.151667 DBI_RD = 0x0
2321 09:29:23.154190 OTF = 0x1
2322 09:29:23.157241 ===================================
2323 09:29:23.160617 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2324 09:29:23.164107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2325 09:29:23.167524 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 09:29:23.170998 ===================================
2327 09:29:23.174307 LPDDR4 DRAM CONFIGURATION
2328 09:29:23.177805 ===================================
2329 09:29:23.180440 EX_ROW_EN[0] = 0x10
2330 09:29:23.180520 EX_ROW_EN[1] = 0x0
2331 09:29:23.183846 LP4Y_EN = 0x0
2332 09:29:23.183926 WORK_FSP = 0x0
2333 09:29:23.187193 WL = 0x4
2334 09:29:23.187272 RL = 0x4
2335 09:29:23.190412 BL = 0x2
2336 09:29:23.190492 RPST = 0x0
2337 09:29:23.193866 RD_PRE = 0x0
2338 09:29:23.193945 WR_PRE = 0x1
2339 09:29:23.197601 WR_PST = 0x0
2340 09:29:23.197681 DBI_WR = 0x0
2341 09:29:23.200705 DBI_RD = 0x0
2342 09:29:23.200785 OTF = 0x1
2343 09:29:23.204376 ===================================
2344 09:29:23.210866 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2345 09:29:23.210947 ==
2346 09:29:23.213855 Dram Type= 6, Freq= 0, CH_0, rank 0
2347 09:29:23.220892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2348 09:29:23.220973 ==
2349 09:29:23.221037 [Duty_Offset_Calibration]
2350 09:29:23.223785 B0:2 B1:1 CA:1
2351 09:29:23.223864
2352 09:29:23.227459 [DutyScan_Calibration_Flow] k_type=0
2353 09:29:23.236047
2354 09:29:23.236127 ==CLK 0==
2355 09:29:23.239371 Final CLK duty delay cell = 0
2356 09:29:23.242838 [0] MAX Duty = 5218%(X100), DQS PI = 24
2357 09:29:23.246011 [0] MIN Duty = 4875%(X100), DQS PI = 0
2358 09:29:23.246117 [0] AVG Duty = 5046%(X100)
2359 09:29:23.246208
2360 09:29:23.249941 CH0 CLK Duty spec in!! Max-Min= 343%
2361 09:29:23.256494 [DutyScan_Calibration_Flow] ====Done====
2362 09:29:23.256576
2363 09:29:23.259633 [DutyScan_Calibration_Flow] k_type=1
2364 09:29:23.273797
2365 09:29:23.273902 ==DQS 0 ==
2366 09:29:23.277244 Final DQS duty delay cell = -4
2367 09:29:23.280509 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2368 09:29:23.283923 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2369 09:29:23.287377 [-4] AVG Duty = 4953%(X100)
2370 09:29:23.287457
2371 09:29:23.287519 ==DQS 1 ==
2372 09:29:23.291335 Final DQS duty delay cell = -4
2373 09:29:23.294579 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2374 09:29:23.298111 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2375 09:29:23.300770 [-4] AVG Duty = 4922%(X100)
2376 09:29:23.300850
2377 09:29:23.304224 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2378 09:29:23.304304
2379 09:29:23.307556 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2380 09:29:23.310870 [DutyScan_Calibration_Flow] ====Done====
2381 09:29:23.310949
2382 09:29:23.314137 [DutyScan_Calibration_Flow] k_type=3
2383 09:29:23.330201
2384 09:29:23.330282 ==DQM 0 ==
2385 09:29:23.333922 Final DQM duty delay cell = 0
2386 09:29:23.336982 [0] MAX Duty = 5156%(X100), DQS PI = 30
2387 09:29:23.340162 [0] MIN Duty = 4906%(X100), DQS PI = 58
2388 09:29:23.340251 [0] AVG Duty = 5031%(X100)
2389 09:29:23.344036
2390 09:29:23.344115 ==DQM 1 ==
2391 09:29:23.346938 Final DQM duty delay cell = -4
2392 09:29:23.350640 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2393 09:29:23.353647 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2394 09:29:23.357167 [-4] AVG Duty = 4922%(X100)
2395 09:29:23.357247
2396 09:29:23.360350 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2397 09:29:23.360430
2398 09:29:23.363594 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2399 09:29:23.367305 [DutyScan_Calibration_Flow] ====Done====
2400 09:29:23.367385
2401 09:29:23.370337 [DutyScan_Calibration_Flow] k_type=2
2402 09:29:23.386995
2403 09:29:23.387077 ==DQ 0 ==
2404 09:29:23.390305 Final DQ duty delay cell = 0
2405 09:29:23.393830 [0] MAX Duty = 5062%(X100), DQS PI = 32
2406 09:29:23.397541 [0] MIN Duty = 4906%(X100), DQS PI = 0
2407 09:29:23.397991 [0] AVG Duty = 4984%(X100)
2408 09:29:23.398380
2409 09:29:23.400889 ==DQ 1 ==
2410 09:29:23.404133 Final DQ duty delay cell = 0
2411 09:29:23.407397 [0] MAX Duty = 5093%(X100), DQS PI = 10
2412 09:29:23.410845 [0] MIN Duty = 4938%(X100), DQS PI = 36
2413 09:29:23.411257 [0] AVG Duty = 5015%(X100)
2414 09:29:23.411793
2415 09:29:23.414169 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2416 09:29:23.414579
2417 09:29:23.417344 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2418 09:29:23.423948 [DutyScan_Calibration_Flow] ====Done====
2419 09:29:23.424357 ==
2420 09:29:23.427697 Dram Type= 6, Freq= 0, CH_1, rank 0
2421 09:29:23.430992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2422 09:29:23.431447 ==
2423 09:29:23.434427 [Duty_Offset_Calibration]
2424 09:29:23.434876 B0:1 B1:0 CA:0
2425 09:29:23.435263
2426 09:29:23.437794 [DutyScan_Calibration_Flow] k_type=0
2427 09:29:23.446715
2428 09:29:23.447202 ==CLK 0==
2429 09:29:23.449935 Final CLK duty delay cell = -4
2430 09:29:23.453173 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2431 09:29:23.456517 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2432 09:29:23.459864 [-4] AVG Duty = 4969%(X100)
2433 09:29:23.460328
2434 09:29:23.463084 CH1 CLK Duty spec in!! Max-Min= 124%
2435 09:29:23.466556 [DutyScan_Calibration_Flow] ====Done====
2436 09:29:23.467007
2437 09:29:23.470067 [DutyScan_Calibration_Flow] k_type=1
2438 09:29:23.486438
2439 09:29:23.486976 ==DQS 0 ==
2440 09:29:23.489487 Final DQS duty delay cell = 0
2441 09:29:23.493041 [0] MAX Duty = 5094%(X100), DQS PI = 24
2442 09:29:23.495623 [0] MIN Duty = 4875%(X100), DQS PI = 0
2443 09:29:23.499169 [0] AVG Duty = 4984%(X100)
2444 09:29:23.499249
2445 09:29:23.499312 ==DQS 1 ==
2446 09:29:23.502544 Final DQS duty delay cell = 0
2447 09:29:23.505919 [0] MAX Duty = 5218%(X100), DQS PI = 20
2448 09:29:23.509238 [0] MIN Duty = 4969%(X100), DQS PI = 8
2449 09:29:23.512665 [0] AVG Duty = 5093%(X100)
2450 09:29:23.512745
2451 09:29:23.516032 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2452 09:29:23.516112
2453 09:29:23.519416 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2454 09:29:23.522756 [DutyScan_Calibration_Flow] ====Done====
2455 09:29:23.522836
2456 09:29:23.525461 [DutyScan_Calibration_Flow] k_type=3
2457 09:29:23.542251
2458 09:29:23.542331 ==DQM 0 ==
2459 09:29:23.546095 Final DQM duty delay cell = 0
2460 09:29:23.549117 [0] MAX Duty = 5156%(X100), DQS PI = 6
2461 09:29:23.552414 [0] MIN Duty = 5031%(X100), DQS PI = 0
2462 09:29:23.552495 [0] AVG Duty = 5093%(X100)
2463 09:29:23.555608
2464 09:29:23.555723 ==DQM 1 ==
2465 09:29:23.559149 Final DQM duty delay cell = 0
2466 09:29:23.562578 [0] MAX Duty = 5031%(X100), DQS PI = 16
2467 09:29:23.565923 [0] MIN Duty = 4907%(X100), DQS PI = 36
2468 09:29:23.566005 [0] AVG Duty = 4969%(X100)
2469 09:29:23.566068
2470 09:29:23.572635 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2471 09:29:23.572715
2472 09:29:23.576030 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2473 09:29:23.579404 [DutyScan_Calibration_Flow] ====Done====
2474 09:29:23.579484
2475 09:29:23.582742 [DutyScan_Calibration_Flow] k_type=2
2476 09:29:23.598302
2477 09:29:23.598383 ==DQ 0 ==
2478 09:29:23.601334 Final DQ duty delay cell = -4
2479 09:29:23.605036 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2480 09:29:23.608206 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2481 09:29:23.611849 [-4] AVG Duty = 4984%(X100)
2482 09:29:23.611930
2483 09:29:23.611993 ==DQ 1 ==
2484 09:29:23.614763 Final DQ duty delay cell = 0
2485 09:29:23.618022 [0] MAX Duty = 5125%(X100), DQS PI = 20
2486 09:29:23.621445 [0] MIN Duty = 4969%(X100), DQS PI = 12
2487 09:29:23.621525 [0] AVG Duty = 5047%(X100)
2488 09:29:23.624996
2489 09:29:23.628159 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2490 09:29:23.628240
2491 09:29:23.631575 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2492 09:29:23.634946 [DutyScan_Calibration_Flow] ====Done====
2493 09:29:23.638199 nWR fixed to 30
2494 09:29:23.638280 [ModeRegInit_LP4] CH0 RK0
2495 09:29:23.642214 [ModeRegInit_LP4] CH0 RK1
2496 09:29:23.645124 [ModeRegInit_LP4] CH1 RK0
2497 09:29:23.645205 [ModeRegInit_LP4] CH1 RK1
2498 09:29:23.648425 match AC timing 7
2499 09:29:23.652172 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2500 09:29:23.655345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2501 09:29:23.661837 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2502 09:29:23.665225 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2503 09:29:23.671923 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2504 09:29:23.672003 ==
2505 09:29:23.675404 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 09:29:23.678789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 09:29:23.678869 ==
2508 09:29:23.685427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2509 09:29:23.688772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2510 09:29:23.698870 [CA 0] Center 39 (8~70) winsize 63
2511 09:29:23.702094 [CA 1] Center 39 (8~70) winsize 63
2512 09:29:23.705096 [CA 2] Center 35 (5~66) winsize 62
2513 09:29:23.708700 [CA 3] Center 34 (4~65) winsize 62
2514 09:29:23.711929 [CA 4] Center 33 (3~64) winsize 62
2515 09:29:23.715170 [CA 5] Center 32 (3~62) winsize 60
2516 09:29:23.715250
2517 09:29:23.718517 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2518 09:29:23.718598
2519 09:29:23.721784 [CATrainingPosCal] consider 1 rank data
2520 09:29:23.724930 u2DelayCellTimex100 = 270/100 ps
2521 09:29:23.728607 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2522 09:29:23.731681 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2523 09:29:23.738674 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2524 09:29:23.741893 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2525 09:29:23.745091 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2526 09:29:23.748425 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2527 09:29:23.748506
2528 09:29:23.752172 CA PerBit enable=1, Macro0, CA PI delay=32
2529 09:29:23.752253
2530 09:29:23.755296 [CBTSetCACLKResult] CA Dly = 32
2531 09:29:23.755377 CS Dly: 6 (0~37)
2532 09:29:23.755440 ==
2533 09:29:23.758664 Dram Type= 6, Freq= 0, CH_0, rank 1
2534 09:29:23.765741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 09:29:23.765822 ==
2536 09:29:23.768850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 09:29:23.775603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2538 09:29:23.784497 [CA 0] Center 38 (8~69) winsize 62
2539 09:29:23.787905 [CA 1] Center 38 (8~69) winsize 62
2540 09:29:23.791300 [CA 2] Center 35 (5~66) winsize 62
2541 09:29:23.794523 [CA 3] Center 34 (4~65) winsize 62
2542 09:29:23.798078 [CA 4] Center 33 (3~64) winsize 62
2543 09:29:23.801483 [CA 5] Center 32 (3~62) winsize 60
2544 09:29:23.801563
2545 09:29:23.804696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2546 09:29:23.804776
2547 09:29:23.807979 [CATrainingPosCal] consider 2 rank data
2548 09:29:23.811112 u2DelayCellTimex100 = 270/100 ps
2549 09:29:23.814219 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2550 09:29:23.818091 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2551 09:29:23.824608 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2552 09:29:23.828013 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2553 09:29:23.831176 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2554 09:29:23.834397 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2555 09:29:23.834483
2556 09:29:23.837680 CA PerBit enable=1, Macro0, CA PI delay=32
2557 09:29:23.837773
2558 09:29:23.841096 [CBTSetCACLKResult] CA Dly = 32
2559 09:29:23.841196 CS Dly: 6 (0~38)
2560 09:29:23.841274
2561 09:29:23.844462 ----->DramcWriteLeveling(PI) begin...
2562 09:29:23.844564 ==
2563 09:29:23.847826 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 09:29:23.854640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 09:29:23.854761 ==
2566 09:29:23.857651 Write leveling (Byte 0): 33 => 33
2567 09:29:23.861404 Write leveling (Byte 1): 30 => 30
2568 09:29:23.861554 DramcWriteLeveling(PI) end<-----
2569 09:29:23.864324
2570 09:29:23.864471 ==
2571 09:29:23.867715 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 09:29:23.871520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 09:29:23.871735 ==
2574 09:29:23.874448 [Gating] SW mode calibration
2575 09:29:23.880977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2576 09:29:23.884556 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2577 09:29:23.891383 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2578 09:29:23.894564 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2579 09:29:23.898435 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 09:29:23.904054 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 09:29:23.908038 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 09:29:23.911487 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 09:29:23.917945 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
2584 09:29:23.921239 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2585 09:29:23.924382 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2586 09:29:23.931345 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 09:29:23.934718 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 09:29:23.937995 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 09:29:23.944738 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 09:29:23.948200 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 09:29:23.951582 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2592 09:29:23.954923 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2593 09:29:23.961475 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2594 09:29:23.964686 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 09:29:23.968086 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 09:29:23.974764 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 09:29:23.978082 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 09:29:23.981384 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 09:29:23.987804 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 09:29:23.991058 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 09:29:23.994795 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 09:29:24.001497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 09:29:24.004735 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 09:29:24.007828 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 09:29:24.014676 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 09:29:24.018067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 09:29:24.021295 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 09:29:24.024488 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 09:29:24.031202 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 09:29:24.034875 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 09:29:24.037881 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 09:29:24.044712 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 09:29:24.047940 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 09:29:24.051320 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 09:29:24.058154 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2616 09:29:24.061550 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2617 09:29:24.064854 Total UI for P1: 0, mck2ui 16
2618 09:29:24.068037 best dqsien dly found for B0: ( 1, 3, 24)
2619 09:29:24.071363 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2620 09:29:24.078165 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 09:29:24.078246 Total UI for P1: 0, mck2ui 16
2622 09:29:24.084961 best dqsien dly found for B1: ( 1, 3, 30)
2623 09:29:24.088207 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2624 09:29:24.091584 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2625 09:29:24.091672
2626 09:29:24.094934 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2627 09:29:24.098250 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2628 09:29:24.101489 [Gating] SW calibration Done
2629 09:29:24.101569 ==
2630 09:29:24.104878 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 09:29:24.108190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 09:29:24.108276 ==
2633 09:29:24.111794 RX Vref Scan: 0
2634 09:29:24.111873
2635 09:29:24.111936 RX Vref 0 -> 0, step: 1
2636 09:29:24.111994
2637 09:29:24.114929 RX Delay -40 -> 252, step: 8
2638 09:29:24.117975 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2639 09:29:24.125030 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2640 09:29:24.128249 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2641 09:29:24.131258 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2642 09:29:24.134624 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2643 09:29:24.138205 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2644 09:29:24.141675 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2645 09:29:24.147787 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2646 09:29:24.151312 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2647 09:29:24.155320 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2648 09:29:24.158115 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2649 09:29:24.161453 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2650 09:29:24.167797 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2651 09:29:24.171581 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2652 09:29:24.174662 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2653 09:29:24.178308 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2654 09:29:24.178389 ==
2655 09:29:24.181638 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 09:29:24.188337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 09:29:24.188417 ==
2658 09:29:24.188480 DQS Delay:
2659 09:29:24.191870 DQS0 = 0, DQS1 = 0
2660 09:29:24.191949 DQM Delay:
2661 09:29:24.192012 DQM0 = 121, DQM1 = 113
2662 09:29:24.195160 DQ Delay:
2663 09:29:24.198520 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2664 09:29:24.201856 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2665 09:29:24.205280 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2666 09:29:24.208574 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2667 09:29:24.208654
2668 09:29:24.208716
2669 09:29:24.208774 ==
2670 09:29:24.212005 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 09:29:24.214773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 09:29:24.214853 ==
2673 09:29:24.218610
2674 09:29:24.218689
2675 09:29:24.218752 TX Vref Scan disable
2676 09:29:24.221748 == TX Byte 0 ==
2677 09:29:24.224786 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2678 09:29:24.228109 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2679 09:29:24.231461 == TX Byte 1 ==
2680 09:29:24.234719 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2681 09:29:24.238076 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2682 09:29:24.238159 ==
2683 09:29:24.242021 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 09:29:24.248027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 09:29:24.248107 ==
2686 09:29:24.259083 TX Vref=22, minBit 0, minWin=24, winSum=406
2687 09:29:24.262522 TX Vref=24, minBit 0, minWin=25, winSum=411
2688 09:29:24.265733 TX Vref=26, minBit 7, minWin=25, winSum=421
2689 09:29:24.268939 TX Vref=28, minBit 0, minWin=26, winSum=425
2690 09:29:24.272743 TX Vref=30, minBit 13, minWin=25, winSum=422
2691 09:29:24.275899 TX Vref=32, minBit 4, minWin=25, winSum=421
2692 09:29:24.282761 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
2693 09:29:24.282842
2694 09:29:24.286259 Final TX Range 1 Vref 28
2695 09:29:24.286339
2696 09:29:24.286402 ==
2697 09:29:24.289478 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 09:29:24.292649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 09:29:24.292729 ==
2700 09:29:24.292792
2701 09:29:24.292850
2702 09:29:24.296315 TX Vref Scan disable
2703 09:29:24.299137 == TX Byte 0 ==
2704 09:29:24.302627 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2705 09:29:24.306295 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2706 09:29:24.309318 == TX Byte 1 ==
2707 09:29:24.313131 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 09:29:24.316598 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 09:29:24.316678
2710 09:29:24.319935 [DATLAT]
2711 09:29:24.320018 Freq=1200, CH0 RK0
2712 09:29:24.320083
2713 09:29:24.323373 DATLAT Default: 0xd
2714 09:29:24.323459 0, 0xFFFF, sum = 0
2715 09:29:24.326796 1, 0xFFFF, sum = 0
2716 09:29:24.326876 2, 0xFFFF, sum = 0
2717 09:29:24.329936 3, 0xFFFF, sum = 0
2718 09:29:24.330017 4, 0xFFFF, sum = 0
2719 09:29:24.333017 5, 0xFFFF, sum = 0
2720 09:29:24.333097 6, 0xFFFF, sum = 0
2721 09:29:24.336388 7, 0xFFFF, sum = 0
2722 09:29:24.336469 8, 0xFFFF, sum = 0
2723 09:29:24.339650 9, 0xFFFF, sum = 0
2724 09:29:24.339744 10, 0xFFFF, sum = 0
2725 09:29:24.343044 11, 0xFFFF, sum = 0
2726 09:29:24.343125 12, 0x0, sum = 1
2727 09:29:24.346326 13, 0x0, sum = 2
2728 09:29:24.346406 14, 0x0, sum = 3
2729 09:29:24.349672 15, 0x0, sum = 4
2730 09:29:24.349752 best_step = 13
2731 09:29:24.349817
2732 09:29:24.349875 ==
2733 09:29:24.353140 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 09:29:24.356496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 09:29:24.359626 ==
2736 09:29:24.359739 RX Vref Scan: 1
2737 09:29:24.359801
2738 09:29:24.362990 Set Vref Range= 32 -> 127
2739 09:29:24.363069
2740 09:29:24.366309 RX Vref 32 -> 127, step: 1
2741 09:29:24.366389
2742 09:29:24.366451 RX Delay -13 -> 252, step: 4
2743 09:29:24.366510
2744 09:29:24.370204 Set Vref, RX VrefLevel [Byte0]: 32
2745 09:29:24.373411 [Byte1]: 32
2746 09:29:24.377174
2747 09:29:24.377254 Set Vref, RX VrefLevel [Byte0]: 33
2748 09:29:24.380468 [Byte1]: 33
2749 09:29:24.385200
2750 09:29:24.385279 Set Vref, RX VrefLevel [Byte0]: 34
2751 09:29:24.388606 [Byte1]: 34
2752 09:29:24.393348
2753 09:29:24.393430 Set Vref, RX VrefLevel [Byte0]: 35
2754 09:29:24.396887 [Byte1]: 35
2755 09:29:24.400878
2756 09:29:24.400974 Set Vref, RX VrefLevel [Byte0]: 36
2757 09:29:24.404150 [Byte1]: 36
2758 09:29:24.409148
2759 09:29:24.409227 Set Vref, RX VrefLevel [Byte0]: 37
2760 09:29:24.412299 [Byte1]: 37
2761 09:29:24.416922
2762 09:29:24.417001 Set Vref, RX VrefLevel [Byte0]: 38
2763 09:29:24.419956 [Byte1]: 38
2764 09:29:24.424818
2765 09:29:24.424898 Set Vref, RX VrefLevel [Byte0]: 39
2766 09:29:24.427893 [Byte1]: 39
2767 09:29:24.432929
2768 09:29:24.433009 Set Vref, RX VrefLevel [Byte0]: 40
2769 09:29:24.435789 [Byte1]: 40
2770 09:29:24.440451
2771 09:29:24.440532 Set Vref, RX VrefLevel [Byte0]: 41
2772 09:29:24.443809 [Byte1]: 41
2773 09:29:24.448110
2774 09:29:24.448189 Set Vref, RX VrefLevel [Byte0]: 42
2775 09:29:24.451957 [Byte1]: 42
2776 09:29:24.456078
2777 09:29:24.456157 Set Vref, RX VrefLevel [Byte0]: 43
2778 09:29:24.459348 [Byte1]: 43
2779 09:29:24.463898
2780 09:29:24.463978 Set Vref, RX VrefLevel [Byte0]: 44
2781 09:29:24.467188 [Byte1]: 44
2782 09:29:24.471910
2783 09:29:24.472001 Set Vref, RX VrefLevel [Byte0]: 45
2784 09:29:24.475288 [Byte1]: 45
2785 09:29:24.479742
2786 09:29:24.479822 Set Vref, RX VrefLevel [Byte0]: 46
2787 09:29:24.482980 [Byte1]: 46
2788 09:29:24.487568
2789 09:29:24.487673 Set Vref, RX VrefLevel [Byte0]: 47
2790 09:29:24.491088 [Byte1]: 47
2791 09:29:24.495648
2792 09:29:24.495728 Set Vref, RX VrefLevel [Byte0]: 48
2793 09:29:24.499005 [Byte1]: 48
2794 09:29:24.503905
2795 09:29:24.503984 Set Vref, RX VrefLevel [Byte0]: 49
2796 09:29:24.507376 [Byte1]: 49
2797 09:29:24.511241
2798 09:29:24.511320 Set Vref, RX VrefLevel [Byte0]: 50
2799 09:29:24.514534 [Byte1]: 50
2800 09:29:24.519394
2801 09:29:24.519473 Set Vref, RX VrefLevel [Byte0]: 51
2802 09:29:24.522741 [Byte1]: 51
2803 09:29:24.527402
2804 09:29:24.527481 Set Vref, RX VrefLevel [Byte0]: 52
2805 09:29:24.530689 [Byte1]: 52
2806 09:29:24.535187
2807 09:29:24.535267 Set Vref, RX VrefLevel [Byte0]: 53
2808 09:29:24.538223 [Byte1]: 53
2809 09:29:24.542956
2810 09:29:24.543037 Set Vref, RX VrefLevel [Byte0]: 54
2811 09:29:24.546633 [Byte1]: 54
2812 09:29:24.551069
2813 09:29:24.551168 Set Vref, RX VrefLevel [Byte0]: 55
2814 09:29:24.554252 [Byte1]: 55
2815 09:29:24.558775
2816 09:29:24.558882 Set Vref, RX VrefLevel [Byte0]: 56
2817 09:29:24.562068 [Byte1]: 56
2818 09:29:24.566737
2819 09:29:24.566817 Set Vref, RX VrefLevel [Byte0]: 57
2820 09:29:24.570309 [Byte1]: 57
2821 09:29:24.575011
2822 09:29:24.575092 Set Vref, RX VrefLevel [Byte0]: 58
2823 09:29:24.578105 [Byte1]: 58
2824 09:29:24.582707
2825 09:29:24.582813 Set Vref, RX VrefLevel [Byte0]: 59
2826 09:29:24.585864 [Byte1]: 59
2827 09:29:24.590001
2828 09:29:24.590081 Set Vref, RX VrefLevel [Byte0]: 60
2829 09:29:24.593931 [Byte1]: 60
2830 09:29:24.598661
2831 09:29:24.598741 Set Vref, RX VrefLevel [Byte0]: 61
2832 09:29:24.601467 [Byte1]: 61
2833 09:29:24.606176
2834 09:29:24.606269 Set Vref, RX VrefLevel [Byte0]: 62
2835 09:29:24.612194 [Byte1]: 62
2836 09:29:24.612276
2837 09:29:24.616160 Set Vref, RX VrefLevel [Byte0]: 63
2838 09:29:24.619434 [Byte1]: 63
2839 09:29:24.619515
2840 09:29:24.622832 Set Vref, RX VrefLevel [Byte0]: 64
2841 09:29:24.625581 [Byte1]: 64
2842 09:29:24.629675
2843 09:29:24.629755 Set Vref, RX VrefLevel [Byte0]: 65
2844 09:29:24.633032 [Byte1]: 65
2845 09:29:24.637802
2846 09:29:24.637886 Set Vref, RX VrefLevel [Byte0]: 66
2847 09:29:24.641035 [Byte1]: 66
2848 09:29:24.645641
2849 09:29:24.645721 Set Vref, RX VrefLevel [Byte0]: 67
2850 09:29:24.648909 [Byte1]: 67
2851 09:29:24.653206
2852 09:29:24.653296 Set Vref, RX VrefLevel [Byte0]: 68
2853 09:29:24.656500 [Byte1]: 68
2854 09:29:24.661166
2855 09:29:24.661262 Set Vref, RX VrefLevel [Byte0]: 69
2856 09:29:24.664691 [Byte1]: 69
2857 09:29:24.669413
2858 09:29:24.669492 Final RX Vref Byte 0 = 56 to rank0
2859 09:29:24.672696 Final RX Vref Byte 1 = 49 to rank0
2860 09:29:24.675917 Final RX Vref Byte 0 = 56 to rank1
2861 09:29:24.679511 Final RX Vref Byte 1 = 49 to rank1==
2862 09:29:24.682548 Dram Type= 6, Freq= 0, CH_0, rank 0
2863 09:29:24.686021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 09:29:24.689209 ==
2865 09:29:24.689304 DQS Delay:
2866 09:29:24.689368 DQS0 = 0, DQS1 = 0
2867 09:29:24.692548 DQM Delay:
2868 09:29:24.692628 DQM0 = 121, DQM1 = 112
2869 09:29:24.696221 DQ Delay:
2870 09:29:24.699074 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2871 09:29:24.702795 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2872 09:29:24.705830 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2873 09:29:24.709571 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =120
2874 09:29:24.709651
2875 09:29:24.709714
2876 09:29:24.715956 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2877 09:29:24.719611 CH0 RK0: MR19=404, MR18=140E
2878 09:29:24.726372 CH0_RK0: MR19=0x404, MR18=0x140E, DQSOSC=402, MR23=63, INC=40, DEC=27
2879 09:29:24.726453
2880 09:29:24.729618 ----->DramcWriteLeveling(PI) begin...
2881 09:29:24.729700 ==
2882 09:29:24.733041 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 09:29:24.736390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 09:29:24.736470 ==
2885 09:29:24.739678 Write leveling (Byte 0): 34 => 34
2886 09:29:24.742997 Write leveling (Byte 1): 30 => 30
2887 09:29:24.746311 DramcWriteLeveling(PI) end<-----
2888 09:29:24.746391
2889 09:29:24.746455 ==
2890 09:29:24.749667 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 09:29:24.756295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 09:29:24.756377 ==
2893 09:29:24.756440 [Gating] SW mode calibration
2894 09:29:24.766015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2895 09:29:24.769384 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2896 09:29:24.772643 0 15 0 | B1->B0 | 3434 3231 | 0 1 | (0 0) (0 0)
2897 09:29:24.779867 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 09:29:24.783258 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 09:29:24.786551 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 09:29:24.793107 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 09:29:24.796296 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 09:29:24.799575 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 09:29:24.806647 0 15 28 | B1->B0 | 2e2e 2c2c | 0 1 | (0 1) (1 0)
2904 09:29:24.810083 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:29:24.813379 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:29:24.816282 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 09:29:24.823052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 09:29:24.826853 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 09:29:24.830007 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 09:29:24.836556 1 0 24 | B1->B0 | 2929 2626 | 0 1 | (0 0) (0 0)
2911 09:29:24.839821 1 0 28 | B1->B0 | 3e3e 3b3b | 0 0 | (0 0) (0 0)
2912 09:29:24.843188 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:29:24.849819 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:29:24.853066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 09:29:24.856493 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 09:29:24.862878 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 09:29:24.866192 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 09:29:24.870023 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 09:29:24.876722 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2920 09:29:24.880034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:29:24.883397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:29:24.890060 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:29:24.892815 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:29:24.896165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:29:24.903372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:29:24.906784 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:29:24.910106 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:29:24.913329 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:29:24.919768 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:29:24.923390 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 09:29:24.926995 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 09:29:24.932967 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 09:29:24.936916 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 09:29:24.939551 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 09:29:24.946282 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2936 09:29:24.950007 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2937 09:29:24.953210 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 09:29:24.956752 Total UI for P1: 0, mck2ui 16
2939 09:29:24.960300 best dqsien dly found for B0: ( 1, 3, 30)
2940 09:29:24.963405 Total UI for P1: 0, mck2ui 16
2941 09:29:24.966598 best dqsien dly found for B1: ( 1, 3, 30)
2942 09:29:24.969933 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2943 09:29:24.973350 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2944 09:29:24.973430
2945 09:29:24.980149 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2946 09:29:24.983513 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2947 09:29:24.983620 [Gating] SW calibration Done
2948 09:29:24.986633 ==
2949 09:29:24.986741 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 09:29:24.993580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 09:29:24.993677 ==
2952 09:29:24.993742 RX Vref Scan: 0
2953 09:29:24.993801
2954 09:29:24.996824 RX Vref 0 -> 0, step: 1
2955 09:29:24.996906
2956 09:29:25.000073 RX Delay -40 -> 252, step: 8
2957 09:29:25.003357 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2958 09:29:25.006550 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2959 09:29:25.009859 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2960 09:29:25.016455 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2961 09:29:25.019817 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2962 09:29:25.023831 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2963 09:29:25.026529 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 09:29:25.029774 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2965 09:29:25.033416 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2966 09:29:25.039901 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2967 09:29:25.043363 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2968 09:29:25.046705 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2969 09:29:25.050076 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2970 09:29:25.056856 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2971 09:29:25.060196 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2972 09:29:25.063429 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2973 09:29:25.063509 ==
2974 09:29:25.066842 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 09:29:25.069860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 09:29:25.069966 ==
2977 09:29:25.073705 DQS Delay:
2978 09:29:25.073806 DQS0 = 0, DQS1 = 0
2979 09:29:25.073896 DQM Delay:
2980 09:29:25.076856 DQM0 = 121, DQM1 = 112
2981 09:29:25.076925 DQ Delay:
2982 09:29:25.080389 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2983 09:29:25.083517 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2984 09:29:25.087145 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2985 09:29:25.093801 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2986 09:29:25.093884
2987 09:29:25.093959
2988 09:29:25.094018 ==
2989 09:29:25.096702 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 09:29:25.100096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 09:29:25.100177 ==
2992 09:29:25.100241
2993 09:29:25.100300
2994 09:29:25.103146 TX Vref Scan disable
2995 09:29:25.103226 == TX Byte 0 ==
2996 09:29:25.109655 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2997 09:29:25.113502 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2998 09:29:25.116888 == TX Byte 1 ==
2999 09:29:25.120214 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3000 09:29:25.123575 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3001 09:29:25.123681 ==
3002 09:29:25.126955 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 09:29:25.129626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 09:29:25.129707 ==
3005 09:29:25.143526 TX Vref=22, minBit 1, minWin=25, winSum=416
3006 09:29:25.146855 TX Vref=24, minBit 0, minWin=26, winSum=422
3007 09:29:25.150276 TX Vref=26, minBit 3, minWin=25, winSum=422
3008 09:29:25.153017 TX Vref=28, minBit 0, minWin=26, winSum=428
3009 09:29:25.156388 TX Vref=30, minBit 1, minWin=26, winSum=429
3010 09:29:25.159835 TX Vref=32, minBit 0, minWin=26, winSum=428
3011 09:29:25.166561 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3012 09:29:25.166643
3013 09:29:25.169904 Final TX Range 1 Vref 30
3014 09:29:25.169985
3015 09:29:25.170048 ==
3016 09:29:25.173351 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 09:29:25.176468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 09:29:25.176551 ==
3019 09:29:25.176615
3020 09:29:25.179841
3021 09:29:25.179918 TX Vref Scan disable
3022 09:29:25.183335 == TX Byte 0 ==
3023 09:29:25.186351 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3024 09:29:25.189562 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3025 09:29:25.193396 == TX Byte 1 ==
3026 09:29:25.196509 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3027 09:29:25.199711 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3028 09:29:25.199792
3029 09:29:25.203435 [DATLAT]
3030 09:29:25.203516 Freq=1200, CH0 RK1
3031 09:29:25.203580
3032 09:29:25.206596 DATLAT Default: 0xd
3033 09:29:25.206677 0, 0xFFFF, sum = 0
3034 09:29:25.209992 1, 0xFFFF, sum = 0
3035 09:29:25.210074 2, 0xFFFF, sum = 0
3036 09:29:25.213210 3, 0xFFFF, sum = 0
3037 09:29:25.213304 4, 0xFFFF, sum = 0
3038 09:29:25.216970 5, 0xFFFF, sum = 0
3039 09:29:25.217055 6, 0xFFFF, sum = 0
3040 09:29:25.219914 7, 0xFFFF, sum = 0
3041 09:29:25.223514 8, 0xFFFF, sum = 0
3042 09:29:25.223651 9, 0xFFFF, sum = 0
3043 09:29:25.226848 10, 0xFFFF, sum = 0
3044 09:29:25.226974 11, 0xFFFF, sum = 0
3045 09:29:25.230067 12, 0x0, sum = 1
3046 09:29:25.230210 13, 0x0, sum = 2
3047 09:29:25.230335 14, 0x0, sum = 3
3048 09:29:25.233353 15, 0x0, sum = 4
3049 09:29:25.233506 best_step = 13
3050 09:29:25.233645
3051 09:29:25.236961 ==
3052 09:29:25.237094 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 09:29:25.243623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 09:29:25.243836 ==
3055 09:29:25.244001 RX Vref Scan: 0
3056 09:29:25.244164
3057 09:29:25.246996 RX Vref 0 -> 0, step: 1
3058 09:29:25.247219
3059 09:29:25.250018 RX Delay -13 -> 252, step: 4
3060 09:29:25.253704 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3061 09:29:25.257074 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3062 09:29:25.264017 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3063 09:29:25.267499 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3064 09:29:25.270788 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3065 09:29:25.274151 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3066 09:29:25.277504 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3067 09:29:25.284258 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3068 09:29:25.287476 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3069 09:29:25.290185 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3070 09:29:25.293909 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3071 09:29:25.297288 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3072 09:29:25.303570 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3073 09:29:25.307421 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3074 09:29:25.310576 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3075 09:29:25.313992 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3076 09:29:25.314435 ==
3077 09:29:25.317374 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 09:29:25.324049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 09:29:25.324469 ==
3080 09:29:25.324809 DQS Delay:
3081 09:29:25.325139 DQS0 = 0, DQS1 = 0
3082 09:29:25.327394 DQM Delay:
3083 09:29:25.327953 DQM0 = 121, DQM1 = 110
3084 09:29:25.330702 DQ Delay:
3085 09:29:25.333948 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3086 09:29:25.337254 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3087 09:29:25.340204 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3088 09:29:25.343797 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3089 09:29:25.344358
3090 09:29:25.344840
3091 09:29:25.350640 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3092 09:29:25.354225 CH0 RK1: MR19=403, MR18=10F1
3093 09:29:25.360805 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3094 09:29:25.363796 [RxdqsGatingPostProcess] freq 1200
3095 09:29:25.370424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 09:29:25.373757 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 09:29:25.374250 best DQS1 dly(2T, 0.5T) = (0, 11)
3098 09:29:25.377506 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 09:29:25.380874 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3100 09:29:25.384262 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 09:29:25.387615 best DQS1 dly(2T, 0.5T) = (0, 11)
3102 09:29:25.390334 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 09:29:25.394316 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3104 09:29:25.397585 Pre-setting of DQS Precalculation
3105 09:29:25.404163 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 09:29:25.404578 ==
3107 09:29:25.407511 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 09:29:25.410566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 09:29:25.410982 ==
3110 09:29:25.417441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 09:29:25.420753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3112 09:29:25.430083 [CA 0] Center 37 (7~68) winsize 62
3113 09:29:25.433572 [CA 1] Center 37 (7~68) winsize 62
3114 09:29:25.436883 [CA 2] Center 34 (4~65) winsize 62
3115 09:29:25.440338 [CA 3] Center 34 (4~64) winsize 61
3116 09:29:25.443599 [CA 4] Center 34 (4~64) winsize 61
3117 09:29:25.447104 [CA 5] Center 33 (3~63) winsize 61
3118 09:29:25.447519
3119 09:29:25.449760 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3120 09:29:25.450175
3121 09:29:25.453172 [CATrainingPosCal] consider 1 rank data
3122 09:29:25.456567 u2DelayCellTimex100 = 270/100 ps
3123 09:29:25.460019 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 09:29:25.463251 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 09:29:25.470011 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3126 09:29:25.473614 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 09:29:25.476691 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 09:29:25.480113 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 09:29:25.480529
3130 09:29:25.483408 CA PerBit enable=1, Macro0, CA PI delay=33
3131 09:29:25.483886
3132 09:29:25.487183 [CBTSetCACLKResult] CA Dly = 33
3133 09:29:25.487593 CS Dly: 7 (0~38)
3134 09:29:25.487996 ==
3135 09:29:25.490044 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 09:29:25.496777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 09:29:25.497353 ==
3138 09:29:25.500037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 09:29:25.506926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 09:29:25.515986 [CA 0] Center 37 (7~68) winsize 62
3141 09:29:25.519212 [CA 1] Center 37 (7~68) winsize 62
3142 09:29:25.522464 [CA 2] Center 35 (5~65) winsize 61
3143 09:29:25.525744 [CA 3] Center 34 (4~65) winsize 62
3144 09:29:25.528920 [CA 4] Center 34 (4~65) winsize 62
3145 09:29:25.532148 [CA 5] Center 34 (4~64) winsize 61
3146 09:29:25.532562
3147 09:29:25.535624 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3148 09:29:25.536081
3149 09:29:25.538970 [CATrainingPosCal] consider 2 rank data
3150 09:29:25.542472 u2DelayCellTimex100 = 270/100 ps
3151 09:29:25.545749 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 09:29:25.549106 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 09:29:25.555803 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 09:29:25.559063 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 09:29:25.562556 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 09:29:25.565994 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3157 09:29:25.566408
3158 09:29:25.569378 CA PerBit enable=1, Macro0, CA PI delay=33
3159 09:29:25.569796
3160 09:29:25.572519 [CBTSetCACLKResult] CA Dly = 33
3161 09:29:25.572934 CS Dly: 8 (0~41)
3162 09:29:25.573278
3163 09:29:25.575786 ----->DramcWriteLeveling(PI) begin...
3164 09:29:25.578937 ==
3165 09:29:25.582294 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 09:29:25.585742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 09:29:25.586161 ==
3168 09:29:25.589122 Write leveling (Byte 0): 27 => 27
3169 09:29:25.592422 Write leveling (Byte 1): 29 => 29
3170 09:29:25.595859 DramcWriteLeveling(PI) end<-----
3171 09:29:25.596367
3172 09:29:25.596825 ==
3173 09:29:25.599138 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 09:29:25.602495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 09:29:25.602919 ==
3176 09:29:25.605752 [Gating] SW mode calibration
3177 09:29:25.612430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 09:29:25.615498 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 09:29:25.622557 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3180 09:29:25.625567 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 09:29:25.628988 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 09:29:25.635747 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 09:29:25.638792 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 09:29:25.642508 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 09:29:25.649396 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3186 09:29:25.652426 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3187 09:29:25.655591 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:29:25.662653 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 09:29:25.665987 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 09:29:25.669414 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 09:29:25.676035 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 09:29:25.679488 1 0 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
3193 09:29:25.682760 1 0 24 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (0 0)
3194 09:29:25.686022 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:29:25.692623 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:29:25.696130 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:29:25.699628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 09:29:25.705770 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 09:29:25.709208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 09:29:25.712448 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 09:29:25.719088 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3202 09:29:25.722402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 09:29:25.725534 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:29:25.732562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:29:25.735830 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:29:25.739111 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:29:25.745394 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:29:25.748996 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:29:25.752024 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:29:25.758874 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:29:25.762540 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:29:25.765860 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:29:25.772453 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 09:29:25.775788 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 09:29:25.779347 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 09:29:25.782340 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 09:29:25.788941 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3218 09:29:25.791976 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 09:29:25.795660 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 09:29:25.799128 Total UI for P1: 0, mck2ui 16
3221 09:29:25.802588 best dqsien dly found for B0: ( 1, 3, 26)
3222 09:29:25.805722 Total UI for P1: 0, mck2ui 16
3223 09:29:25.809168 best dqsien dly found for B1: ( 1, 3, 26)
3224 09:29:25.812561 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3225 09:29:25.816066 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3226 09:29:25.816234
3227 09:29:25.822977 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 09:29:25.825703 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3229 09:29:25.825934 [Gating] SW calibration Done
3230 09:29:25.829176 ==
3231 09:29:25.832401 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 09:29:25.836425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 09:29:25.836787 ==
3234 09:29:25.837071 RX Vref Scan: 0
3235 09:29:25.837334
3236 09:29:25.839339 RX Vref 0 -> 0, step: 1
3237 09:29:25.839797
3238 09:29:25.842670 RX Delay -40 -> 252, step: 8
3239 09:29:25.846141 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3240 09:29:25.849738 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3241 09:29:25.852981 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3242 09:29:25.859812 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3243 09:29:25.863207 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3244 09:29:25.866189 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3245 09:29:25.870291 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3246 09:29:25.873632 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3247 09:29:25.880069 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3248 09:29:25.883132 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3249 09:29:25.886500 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3250 09:29:25.890520 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3251 09:29:25.893825 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 09:29:25.900061 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3253 09:29:25.903263 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3254 09:29:25.906863 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3255 09:29:25.907459 ==
3256 09:29:25.910509 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 09:29:25.913340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 09:29:25.913955 ==
3259 09:29:25.917015 DQS Delay:
3260 09:29:25.917576 DQS0 = 0, DQS1 = 0
3261 09:29:25.920462 DQM Delay:
3262 09:29:25.921019 DQM0 = 119, DQM1 = 116
3263 09:29:25.921389 DQ Delay:
3264 09:29:25.923767 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3265 09:29:25.926779 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3266 09:29:25.933386 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3267 09:29:25.936699 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3268 09:29:25.937153
3269 09:29:25.937498
3270 09:29:25.937797 ==
3271 09:29:25.940139 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 09:29:25.943613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 09:29:25.944200 ==
3274 09:29:25.944539
3275 09:29:25.944846
3276 09:29:25.946973 TX Vref Scan disable
3277 09:29:25.950158 == TX Byte 0 ==
3278 09:29:25.953612 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3279 09:29:25.957012 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3280 09:29:25.960157 == TX Byte 1 ==
3281 09:29:25.963425 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3282 09:29:25.966567 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3283 09:29:25.967000 ==
3284 09:29:25.970096 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 09:29:25.973437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 09:29:25.973959 ==
3287 09:29:25.986252 TX Vref=22, minBit 1, minWin=25, winSum=414
3288 09:29:25.990345 TX Vref=24, minBit 9, minWin=25, winSum=418
3289 09:29:25.993644 TX Vref=26, minBit 3, minWin=25, winSum=419
3290 09:29:25.996291 TX Vref=28, minBit 1, minWin=26, winSum=429
3291 09:29:25.999555 TX Vref=30, minBit 1, minWin=26, winSum=429
3292 09:29:26.002941 TX Vref=32, minBit 2, minWin=26, winSum=433
3293 09:29:26.009501 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 32
3294 09:29:26.009955
3295 09:29:26.013006 Final TX Range 1 Vref 32
3296 09:29:26.013575
3297 09:29:26.014011 ==
3298 09:29:26.016726 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 09:29:26.019675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 09:29:26.020190 ==
3301 09:29:26.020574
3302 09:29:26.020892
3303 09:29:26.022985 TX Vref Scan disable
3304 09:29:26.026684 == TX Byte 0 ==
3305 09:29:26.029886 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3306 09:29:26.033448 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3307 09:29:26.036241 == TX Byte 1 ==
3308 09:29:26.040269 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3309 09:29:26.042933 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3310 09:29:26.043341
3311 09:29:26.046486 [DATLAT]
3312 09:29:26.046991 Freq=1200, CH1 RK0
3313 09:29:26.047324
3314 09:29:26.050485 DATLAT Default: 0xd
3315 09:29:26.051005 0, 0xFFFF, sum = 0
3316 09:29:26.053554 1, 0xFFFF, sum = 0
3317 09:29:26.053969 2, 0xFFFF, sum = 0
3318 09:29:26.057434 3, 0xFFFF, sum = 0
3319 09:29:26.057943 4, 0xFFFF, sum = 0
3320 09:29:26.059835 5, 0xFFFF, sum = 0
3321 09:29:26.060251 6, 0xFFFF, sum = 0
3322 09:29:26.063264 7, 0xFFFF, sum = 0
3323 09:29:26.063723 8, 0xFFFF, sum = 0
3324 09:29:26.066516 9, 0xFFFF, sum = 0
3325 09:29:26.066930 10, 0xFFFF, sum = 0
3326 09:29:26.069654 11, 0xFFFF, sum = 0
3327 09:29:26.070073 12, 0x0, sum = 1
3328 09:29:26.073503 13, 0x0, sum = 2
3329 09:29:26.074043 14, 0x0, sum = 3
3330 09:29:26.076732 15, 0x0, sum = 4
3331 09:29:26.077148 best_step = 13
3332 09:29:26.077473
3333 09:29:26.077771 ==
3334 09:29:26.080031 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 09:29:26.086904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 09:29:26.087315 ==
3337 09:29:26.087671 RX Vref Scan: 1
3338 09:29:26.088214
3339 09:29:26.089865 Set Vref Range= 32 -> 127
3340 09:29:26.090274
3341 09:29:26.093555 RX Vref 32 -> 127, step: 1
3342 09:29:26.094005
3343 09:29:26.094333 RX Delay -5 -> 252, step: 4
3344 09:29:26.094642
3345 09:29:26.096998 Set Vref, RX VrefLevel [Byte0]: 32
3346 09:29:26.099609 [Byte1]: 32
3347 09:29:26.104410
3348 09:29:26.104912 Set Vref, RX VrefLevel [Byte0]: 33
3349 09:29:26.107839 [Byte1]: 33
3350 09:29:26.112328
3351 09:29:26.112843 Set Vref, RX VrefLevel [Byte0]: 34
3352 09:29:26.115187 [Byte1]: 34
3353 09:29:26.120050
3354 09:29:26.120565 Set Vref, RX VrefLevel [Byte0]: 35
3355 09:29:26.123186 [Byte1]: 35
3356 09:29:26.127904
3357 09:29:26.128329 Set Vref, RX VrefLevel [Byte0]: 36
3358 09:29:26.131151 [Byte1]: 36
3359 09:29:26.135541
3360 09:29:26.136010 Set Vref, RX VrefLevel [Byte0]: 37
3361 09:29:26.138913 [Byte1]: 37
3362 09:29:26.143508
3363 09:29:26.144002 Set Vref, RX VrefLevel [Byte0]: 38
3364 09:29:26.146859 [Byte1]: 38
3365 09:29:26.151486
3366 09:29:26.152104 Set Vref, RX VrefLevel [Byte0]: 39
3367 09:29:26.154440 [Byte1]: 39
3368 09:29:26.159096
3369 09:29:26.159490 Set Vref, RX VrefLevel [Byte0]: 40
3370 09:29:26.162172 [Byte1]: 40
3371 09:29:26.167053
3372 09:29:26.167343 Set Vref, RX VrefLevel [Byte0]: 41
3373 09:29:26.170539 [Byte1]: 41
3374 09:29:26.174998
3375 09:29:26.175305 Set Vref, RX VrefLevel [Byte0]: 42
3376 09:29:26.178129 [Byte1]: 42
3377 09:29:26.182622
3378 09:29:26.183021 Set Vref, RX VrefLevel [Byte0]: 43
3379 09:29:26.185970 [Byte1]: 43
3380 09:29:26.191233
3381 09:29:26.191848 Set Vref, RX VrefLevel [Byte0]: 44
3382 09:29:26.194072 [Byte1]: 44
3383 09:29:26.198488
3384 09:29:26.199002 Set Vref, RX VrefLevel [Byte0]: 45
3385 09:29:26.202177 [Byte1]: 45
3386 09:29:26.206556
3387 09:29:26.206976 Set Vref, RX VrefLevel [Byte0]: 46
3388 09:29:26.210230 [Byte1]: 46
3389 09:29:26.214360
3390 09:29:26.214875 Set Vref, RX VrefLevel [Byte0]: 47
3391 09:29:26.217725 [Byte1]: 47
3392 09:29:26.222289
3393 09:29:26.222803 Set Vref, RX VrefLevel [Byte0]: 48
3394 09:29:26.225286 [Byte1]: 48
3395 09:29:26.230114
3396 09:29:26.230627 Set Vref, RX VrefLevel [Byte0]: 49
3397 09:29:26.233706 [Byte1]: 49
3398 09:29:26.238344
3399 09:29:26.238856 Set Vref, RX VrefLevel [Byte0]: 50
3400 09:29:26.240801 [Byte1]: 50
3401 09:29:26.245874
3402 09:29:26.246391 Set Vref, RX VrefLevel [Byte0]: 51
3403 09:29:26.248803 [Byte1]: 51
3404 09:29:26.253643
3405 09:29:26.254054 Set Vref, RX VrefLevel [Byte0]: 52
3406 09:29:26.256501 [Byte1]: 52
3407 09:29:26.261141
3408 09:29:26.261655 Set Vref, RX VrefLevel [Byte0]: 53
3409 09:29:26.264581 [Byte1]: 53
3410 09:29:26.269304
3411 09:29:26.269821 Set Vref, RX VrefLevel [Byte0]: 54
3412 09:29:26.272539 [Byte1]: 54
3413 09:29:26.280626
3414 09:29:26.281040 Set Vref, RX VrefLevel [Byte0]: 55
3415 09:29:26.281367 [Byte1]: 55
3416 09:29:26.284915
3417 09:29:26.285324 Set Vref, RX VrefLevel [Byte0]: 56
3418 09:29:26.288337 [Byte1]: 56
3419 09:29:26.292996
3420 09:29:26.293512 Set Vref, RX VrefLevel [Byte0]: 57
3421 09:29:26.296129 [Byte1]: 57
3422 09:29:26.300845
3423 09:29:26.301359 Set Vref, RX VrefLevel [Byte0]: 58
3424 09:29:26.303946 [Byte1]: 58
3425 09:29:26.308200
3426 09:29:26.308608 Set Vref, RX VrefLevel [Byte0]: 59
3427 09:29:26.312081 [Byte1]: 59
3428 09:29:26.316102
3429 09:29:26.316614 Set Vref, RX VrefLevel [Byte0]: 60
3430 09:29:26.319693 [Byte1]: 60
3431 09:29:26.324394
3432 09:29:26.324943 Set Vref, RX VrefLevel [Byte0]: 61
3433 09:29:26.327548 [Byte1]: 61
3434 09:29:26.332395
3435 09:29:26.332946 Set Vref, RX VrefLevel [Byte0]: 62
3436 09:29:26.335587 [Byte1]: 62
3437 09:29:26.340338
3438 09:29:26.340900 Set Vref, RX VrefLevel [Byte0]: 63
3439 09:29:26.342990 [Byte1]: 63
3440 09:29:26.348003
3441 09:29:26.348553 Set Vref, RX VrefLevel [Byte0]: 64
3442 09:29:26.351334 [Byte1]: 64
3443 09:29:26.356039
3444 09:29:26.356587 Set Vref, RX VrefLevel [Byte0]: 65
3445 09:29:26.358801 [Byte1]: 65
3446 09:29:26.363365
3447 09:29:26.363972 Set Vref, RX VrefLevel [Byte0]: 66
3448 09:29:26.366982 [Byte1]: 66
3449 09:29:26.371234
3450 09:29:26.371828 Set Vref, RX VrefLevel [Byte0]: 67
3451 09:29:26.374818 [Byte1]: 67
3452 09:29:26.379097
3453 09:29:26.379698 Set Vref, RX VrefLevel [Byte0]: 68
3454 09:29:26.382530 [Byte1]: 68
3455 09:29:26.386936
3456 09:29:26.387392 Final RX Vref Byte 0 = 55 to rank0
3457 09:29:26.390366 Final RX Vref Byte 1 = 51 to rank0
3458 09:29:26.393738 Final RX Vref Byte 0 = 55 to rank1
3459 09:29:26.397193 Final RX Vref Byte 1 = 51 to rank1==
3460 09:29:26.400297 Dram Type= 6, Freq= 0, CH_1, rank 0
3461 09:29:26.406976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 09:29:26.407486 ==
3463 09:29:26.407883 DQS Delay:
3464 09:29:26.408194 DQS0 = 0, DQS1 = 0
3465 09:29:26.409928 DQM Delay:
3466 09:29:26.410339 DQM0 = 120, DQM1 = 117
3467 09:29:26.413291 DQ Delay:
3468 09:29:26.417500 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3469 09:29:26.420497 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3470 09:29:26.423804 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =112
3471 09:29:26.426666 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3472 09:29:26.427082
3473 09:29:26.427425
3474 09:29:26.433254 [DQSOSCAuto] RK0, (LSB)MR18= 0xff11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3475 09:29:26.436690 CH1 RK0: MR19=304, MR18=FF11
3476 09:29:26.443587 CH1_RK0: MR19=0x304, MR18=0xFF11, DQSOSC=403, MR23=63, INC=40, DEC=26
3477 09:29:26.444046
3478 09:29:26.447279 ----->DramcWriteLeveling(PI) begin...
3479 09:29:26.447840 ==
3480 09:29:26.450347 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 09:29:26.453587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 09:29:26.457248 ==
3483 09:29:26.457759 Write leveling (Byte 0): 26 => 26
3484 09:29:26.460555 Write leveling (Byte 1): 29 => 29
3485 09:29:26.463914 DramcWriteLeveling(PI) end<-----
3486 09:29:26.464431
3487 09:29:26.464761 ==
3488 09:29:26.467364 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 09:29:26.473540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 09:29:26.474057 ==
3491 09:29:26.477542 [Gating] SW mode calibration
3492 09:29:26.483553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3493 09:29:26.486682 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3494 09:29:26.493468 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 09:29:26.496986 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 09:29:26.500224 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 09:29:26.503409 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 09:29:26.509930 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3499 09:29:26.513244 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (1 0) (1 1)
3500 09:29:26.516618 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (0 1)
3501 09:29:26.523295 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3502 09:29:26.526830 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 09:29:26.530388 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 09:29:26.536946 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 09:29:26.539904 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 09:29:26.543271 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 09:29:26.549854 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3508 09:29:26.553328 1 0 24 | B1->B0 | 4242 2d2d | 0 0 | (1 1) (0 0)
3509 09:29:26.556721 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 09:29:26.563298 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 09:29:26.567074 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 09:29:26.570463 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 09:29:26.577084 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 09:29:26.580177 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 09:29:26.583768 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3516 09:29:26.590416 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3517 09:29:26.593202 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:29:26.596869 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 09:29:26.603631 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 09:29:26.606841 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 09:29:26.610067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:29:26.613682 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 09:29:26.619881 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 09:29:26.623293 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 09:29:26.626217 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 09:29:26.632968 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 09:29:26.636360 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 09:29:26.640116 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 09:29:26.646706 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 09:29:26.649504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 09:29:26.653302 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3532 09:29:26.660022 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3533 09:29:26.663319 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3534 09:29:26.666327 Total UI for P1: 0, mck2ui 16
3535 09:29:26.669377 best dqsien dly found for B1: ( 1, 3, 22)
3536 09:29:26.672877 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 09:29:26.676324 Total UI for P1: 0, mck2ui 16
3538 09:29:26.679672 best dqsien dly found for B0: ( 1, 3, 26)
3539 09:29:26.683223 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3540 09:29:26.686572 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3541 09:29:26.687082
3542 09:29:26.693296 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3543 09:29:26.696567 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3544 09:29:26.699701 [Gating] SW calibration Done
3545 09:29:26.700113 ==
3546 09:29:26.703285 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 09:29:26.706054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 09:29:26.706472 ==
3549 09:29:26.706800 RX Vref Scan: 0
3550 09:29:26.707107
3551 09:29:26.709774 RX Vref 0 -> 0, step: 1
3552 09:29:26.710185
3553 09:29:26.712410 RX Delay -40 -> 252, step: 8
3554 09:29:26.715883 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3555 09:29:26.719475 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3556 09:29:26.726143 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3557 09:29:26.729114 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3558 09:29:26.732370 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3559 09:29:26.736191 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3560 09:29:26.739201 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3561 09:29:26.745508 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3562 09:29:26.749466 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3563 09:29:26.753093 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3564 09:29:26.756187 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3565 09:29:26.759912 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3566 09:29:26.765991 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3567 09:29:26.769141 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3568 09:29:26.772416 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3569 09:29:26.776278 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3570 09:29:26.776788 ==
3571 09:29:26.779153 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 09:29:26.782821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 09:29:26.785710 ==
3574 09:29:26.786155 DQS Delay:
3575 09:29:26.786512 DQS0 = 0, DQS1 = 0
3576 09:29:26.789858 DQM Delay:
3577 09:29:26.790365 DQM0 = 120, DQM1 = 117
3578 09:29:26.792699 DQ Delay:
3579 09:29:26.795840 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3580 09:29:26.799415 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3581 09:29:26.802367 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3582 09:29:26.806295 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3583 09:29:26.806710
3584 09:29:26.807034
3585 09:29:26.807334 ==
3586 09:29:26.809002 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 09:29:26.812915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 09:29:26.813481 ==
3589 09:29:26.815795
3590 09:29:26.816212
3591 09:29:26.816539 TX Vref Scan disable
3592 09:29:26.820023 == TX Byte 0 ==
3593 09:29:26.822657 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3594 09:29:26.826045 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3595 09:29:26.828963 == TX Byte 1 ==
3596 09:29:26.833260 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 09:29:26.836180 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 09:29:26.836602 ==
3599 09:29:26.838910 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 09:29:26.845801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 09:29:26.846330 ==
3602 09:29:26.856107 TX Vref=22, minBit 9, minWin=25, winSum=422
3603 09:29:26.859705 TX Vref=24, minBit 1, minWin=26, winSum=423
3604 09:29:26.863248 TX Vref=26, minBit 1, minWin=26, winSum=427
3605 09:29:26.866563 TX Vref=28, minBit 9, minWin=26, winSum=436
3606 09:29:26.869611 TX Vref=30, minBit 10, minWin=25, winSum=436
3607 09:29:26.876229 TX Vref=32, minBit 9, minWin=26, winSum=434
3608 09:29:26.879769 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3609 09:29:26.880193
3610 09:29:26.883219 Final TX Range 1 Vref 28
3611 09:29:26.883673
3612 09:29:26.884009 ==
3613 09:29:26.885921 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 09:29:26.889574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 09:29:26.890101 ==
3616 09:29:26.892965
3617 09:29:26.893383
3618 09:29:26.893781 TX Vref Scan disable
3619 09:29:26.896487 == TX Byte 0 ==
3620 09:29:26.899437 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3621 09:29:26.906368 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3622 09:29:26.906895 == TX Byte 1 ==
3623 09:29:26.909678 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3624 09:29:26.916317 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3625 09:29:26.916824
3626 09:29:26.917153 [DATLAT]
3627 09:29:26.917461 Freq=1200, CH1 RK1
3628 09:29:26.917798
3629 09:29:26.920256 DATLAT Default: 0xd
3630 09:29:26.920777 0, 0xFFFF, sum = 0
3631 09:29:26.922586 1, 0xFFFF, sum = 0
3632 09:29:26.923009 2, 0xFFFF, sum = 0
3633 09:29:26.926334 3, 0xFFFF, sum = 0
3634 09:29:26.926872 4, 0xFFFF, sum = 0
3635 09:29:26.929262 5, 0xFFFF, sum = 0
3636 09:29:26.929692 6, 0xFFFF, sum = 0
3637 09:29:26.948444 7, 0xFFFF, sum = 0
3638 09:29:26.948979 8, 0xFFFF, sum = 0
3639 09:29:26.949345 9, 0xFFFF, sum = 0
3640 09:29:26.949670 10, 0xFFFF, sum = 0
3641 09:29:26.949975 11, 0xFFFF, sum = 0
3642 09:29:26.950272 12, 0x0, sum = 1
3643 09:29:26.950562 13, 0x0, sum = 2
3644 09:29:26.950848 14, 0x0, sum = 3
3645 09:29:26.951128 15, 0x0, sum = 4
3646 09:29:26.951411 best_step = 13
3647 09:29:26.951741
3648 09:29:26.952379 ==
3649 09:29:26.952761 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 09:29:26.956139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 09:29:26.956607 ==
3652 09:29:26.956941 RX Vref Scan: 0
3653 09:29:26.957252
3654 09:29:26.959481 RX Vref 0 -> 0, step: 1
3655 09:29:26.959981
3656 09:29:26.962844 RX Delay -5 -> 252, step: 4
3657 09:29:26.966102 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3658 09:29:26.972498 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3659 09:29:26.975929 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3660 09:29:26.979685 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3661 09:29:26.982857 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3662 09:29:26.986305 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3663 09:29:26.989784 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3664 09:29:26.996244 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3665 09:29:26.999504 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3666 09:29:27.002867 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3667 09:29:27.006461 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3668 09:29:27.012893 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3669 09:29:27.016279 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3670 09:29:27.019411 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3671 09:29:27.022839 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3672 09:29:27.026095 iDelay=195, Bit 15, Center 126 (63 ~ 190) 128
3673 09:29:27.026513 ==
3674 09:29:27.029051 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 09:29:27.035627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 09:29:27.036339 ==
3677 09:29:27.036859 DQS Delay:
3678 09:29:27.039358 DQS0 = 0, DQS1 = 0
3679 09:29:27.040048 DQM Delay:
3680 09:29:27.042473 DQM0 = 120, DQM1 = 117
3681 09:29:27.043106 DQ Delay:
3682 09:29:27.045973 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3683 09:29:27.048907 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3684 09:29:27.052286 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =110
3685 09:29:27.055658 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3686 09:29:27.056113
3687 09:29:27.056526
3688 09:29:27.065850 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3689 09:29:27.066143 CH1 RK1: MR19=403, MR18=11EE
3690 09:29:27.071842 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3691 09:29:27.075536 [RxdqsGatingPostProcess] freq 1200
3692 09:29:27.081899 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3693 09:29:27.085177 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 09:29:27.088497 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 09:29:27.091813 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 09:29:27.095143 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 09:29:27.098494 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 09:29:27.101766 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 09:29:27.105097 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 09:29:27.108484 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 09:29:27.108608 Pre-setting of DQS Precalculation
3702 09:29:27.115075 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3703 09:29:27.121811 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3704 09:29:27.128126 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3705 09:29:27.128253
3706 09:29:27.128368
3707 09:29:27.132094 [Calibration Summary] 2400 Mbps
3708 09:29:27.135238 CH 0, Rank 0
3709 09:29:27.135321 SW Impedance : PASS
3710 09:29:27.138219 DUTY Scan : NO K
3711 09:29:27.141446 ZQ Calibration : PASS
3712 09:29:27.141544 Jitter Meter : NO K
3713 09:29:27.144861 CBT Training : PASS
3714 09:29:27.148249 Write leveling : PASS
3715 09:29:27.148435 RX DQS gating : PASS
3716 09:29:27.151468 RX DQ/DQS(RDDQC) : PASS
3717 09:29:27.151563 TX DQ/DQS : PASS
3718 09:29:27.154886 RX DATLAT : PASS
3719 09:29:27.158155 RX DQ/DQS(Engine): PASS
3720 09:29:27.158287 TX OE : NO K
3721 09:29:27.161382 All Pass.
3722 09:29:27.161489
3723 09:29:27.161595 CH 0, Rank 1
3724 09:29:27.164464 SW Impedance : PASS
3725 09:29:27.164576 DUTY Scan : NO K
3726 09:29:27.168089 ZQ Calibration : PASS
3727 09:29:27.171435 Jitter Meter : NO K
3728 09:29:27.171516 CBT Training : PASS
3729 09:29:27.174713 Write leveling : PASS
3730 09:29:27.178247 RX DQS gating : PASS
3731 09:29:27.178328 RX DQ/DQS(RDDQC) : PASS
3732 09:29:27.181197 TX DQ/DQS : PASS
3733 09:29:27.184634 RX DATLAT : PASS
3734 09:29:27.184715 RX DQ/DQS(Engine): PASS
3735 09:29:27.187776 TX OE : NO K
3736 09:29:27.187857 All Pass.
3737 09:29:27.187920
3738 09:29:27.191427 CH 1, Rank 0
3739 09:29:27.191509 SW Impedance : PASS
3740 09:29:27.194682 DUTY Scan : NO K
3741 09:29:27.198014 ZQ Calibration : PASS
3742 09:29:27.198095 Jitter Meter : NO K
3743 09:29:27.201291 CBT Training : PASS
3744 09:29:27.204566 Write leveling : PASS
3745 09:29:27.204647 RX DQS gating : PASS
3746 09:29:27.207836 RX DQ/DQS(RDDQC) : PASS
3747 09:29:27.211175 TX DQ/DQS : PASS
3748 09:29:27.211256 RX DATLAT : PASS
3749 09:29:27.214510 RX DQ/DQS(Engine): PASS
3750 09:29:27.214591 TX OE : NO K
3751 09:29:27.217857 All Pass.
3752 09:29:27.217989
3753 09:29:27.218111 CH 1, Rank 1
3754 09:29:27.221230 SW Impedance : PASS
3755 09:29:27.221358 DUTY Scan : NO K
3756 09:29:27.224507 ZQ Calibration : PASS
3757 09:29:27.227929 Jitter Meter : NO K
3758 09:29:27.228059 CBT Training : PASS
3759 09:29:27.231395 Write leveling : PASS
3760 09:29:27.234681 RX DQS gating : PASS
3761 09:29:27.234806 RX DQ/DQS(RDDQC) : PASS
3762 09:29:27.237902 TX DQ/DQS : PASS
3763 09:29:27.240953 RX DATLAT : PASS
3764 09:29:27.241080 RX DQ/DQS(Engine): PASS
3765 09:29:27.244045 TX OE : NO K
3766 09:29:27.244179 All Pass.
3767 09:29:27.244300
3768 09:29:27.247770 DramC Write-DBI off
3769 09:29:27.250879 PER_BANK_REFRESH: Hybrid Mode
3770 09:29:27.250967 TX_TRACKING: ON
3771 09:29:27.261124 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3772 09:29:27.264935 [FAST_K] Save calibration result to emmc
3773 09:29:27.267530 dramc_set_vcore_voltage set vcore to 650000
3774 09:29:27.270850 Read voltage for 600, 5
3775 09:29:27.270932 Vio18 = 0
3776 09:29:27.270996 Vcore = 650000
3777 09:29:27.274188 Vdram = 0
3778 09:29:27.274270 Vddq = 0
3779 09:29:27.274333 Vmddr = 0
3780 09:29:27.280524 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3781 09:29:27.284125 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3782 09:29:27.287476 MEM_TYPE=3, freq_sel=19
3783 09:29:27.290594 sv_algorithm_assistance_LP4_1600
3784 09:29:27.293938 ============ PULL DRAM RESETB DOWN ============
3785 09:29:27.297443 ========== PULL DRAM RESETB DOWN end =========
3786 09:29:27.303882 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3787 09:29:27.307472 ===================================
3788 09:29:27.307555 LPDDR4 DRAM CONFIGURATION
3789 09:29:27.310954 ===================================
3790 09:29:27.314032 EX_ROW_EN[0] = 0x0
3791 09:29:27.317217 EX_ROW_EN[1] = 0x0
3792 09:29:27.317299 LP4Y_EN = 0x0
3793 09:29:27.320585 WORK_FSP = 0x0
3794 09:29:27.320665 WL = 0x2
3795 09:29:27.323833 RL = 0x2
3796 09:29:27.323914 BL = 0x2
3797 09:29:27.327186 RPST = 0x0
3798 09:29:27.327267 RD_PRE = 0x0
3799 09:29:27.330550 WR_PRE = 0x1
3800 09:29:27.330631 WR_PST = 0x0
3801 09:29:27.333993 DBI_WR = 0x0
3802 09:29:27.334074 DBI_RD = 0x0
3803 09:29:27.337321 OTF = 0x1
3804 09:29:27.340704 ===================================
3805 09:29:27.343981 ===================================
3806 09:29:27.344063 ANA top config
3807 09:29:27.347137 ===================================
3808 09:29:27.350433 DLL_ASYNC_EN = 0
3809 09:29:27.353648 ALL_SLAVE_EN = 1
3810 09:29:27.356912 NEW_RANK_MODE = 1
3811 09:29:27.356995 DLL_IDLE_MODE = 1
3812 09:29:27.360050 LP45_APHY_COMB_EN = 1
3813 09:29:27.363845 TX_ODT_DIS = 1
3814 09:29:27.367054 NEW_8X_MODE = 1
3815 09:29:27.370123 ===================================
3816 09:29:27.373425 ===================================
3817 09:29:27.376816 data_rate = 1200
3818 09:29:27.376898 CKR = 1
3819 09:29:27.380241 DQ_P2S_RATIO = 8
3820 09:29:27.383476 ===================================
3821 09:29:27.386805 CA_P2S_RATIO = 8
3822 09:29:27.390042 DQ_CA_OPEN = 0
3823 09:29:27.393648 DQ_SEMI_OPEN = 0
3824 09:29:27.396775 CA_SEMI_OPEN = 0
3825 09:29:27.396857 CA_FULL_RATE = 0
3826 09:29:27.400134 DQ_CKDIV4_EN = 1
3827 09:29:27.404040 CA_CKDIV4_EN = 1
3828 09:29:27.407291 CA_PREDIV_EN = 0
3829 09:29:27.410254 PH8_DLY = 0
3830 09:29:27.413468 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3831 09:29:27.413550 DQ_AAMCK_DIV = 4
3832 09:29:27.417374 CA_AAMCK_DIV = 4
3833 09:29:27.420465 CA_ADMCK_DIV = 4
3834 09:29:27.423456 DQ_TRACK_CA_EN = 0
3835 09:29:27.426785 CA_PICK = 600
3836 09:29:27.430533 CA_MCKIO = 600
3837 09:29:27.430615 MCKIO_SEMI = 0
3838 09:29:27.433921 PLL_FREQ = 2288
3839 09:29:27.437338 DQ_UI_PI_RATIO = 32
3840 09:29:27.440674 CA_UI_PI_RATIO = 0
3841 09:29:27.443333 ===================================
3842 09:29:27.446777 ===================================
3843 09:29:27.450083 memory_type:LPDDR4
3844 09:29:27.450165 GP_NUM : 10
3845 09:29:27.453291 SRAM_EN : 1
3846 09:29:27.456681 MD32_EN : 0
3847 09:29:27.460578 ===================================
3848 09:29:27.460660 [ANA_INIT] >>>>>>>>>>>>>>
3849 09:29:27.463305 <<<<<< [CONFIGURE PHASE]: ANA_TX
3850 09:29:27.466612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3851 09:29:27.469996 ===================================
3852 09:29:27.473738 data_rate = 1200,PCW = 0X5800
3853 09:29:27.476841 ===================================
3854 09:29:27.479990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3855 09:29:27.486928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 09:29:27.490278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 09:29:27.496758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3858 09:29:27.500305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3859 09:29:27.503463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3860 09:29:27.503545 [ANA_INIT] flow start
3861 09:29:27.506793 [ANA_INIT] PLL >>>>>>>>
3862 09:29:27.510206 [ANA_INIT] PLL <<<<<<<<
3863 09:29:27.510288 [ANA_INIT] MIDPI >>>>>>>>
3864 09:29:27.513553 [ANA_INIT] MIDPI <<<<<<<<
3865 09:29:27.516738 [ANA_INIT] DLL >>>>>>>>
3866 09:29:27.516819 [ANA_INIT] flow end
3867 09:29:27.523404 ============ LP4 DIFF to SE enter ============
3868 09:29:27.526786 ============ LP4 DIFF to SE exit ============
3869 09:29:27.530004 [ANA_INIT] <<<<<<<<<<<<<
3870 09:29:27.533156 [Flow] Enable top DCM control >>>>>
3871 09:29:27.536811 [Flow] Enable top DCM control <<<<<
3872 09:29:27.536894 Enable DLL master slave shuffle
3873 09:29:27.543643 ==============================================================
3874 09:29:27.546982 Gating Mode config
3875 09:29:27.550205 ==============================================================
3876 09:29:27.553492 Config description:
3877 09:29:27.563255 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3878 09:29:27.569833 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3879 09:29:27.573168 SELPH_MODE 0: By rank 1: By Phase
3880 09:29:27.580436 ==============================================================
3881 09:29:27.583578 GAT_TRACK_EN = 1
3882 09:29:27.586760 RX_GATING_MODE = 2
3883 09:29:27.590072 RX_GATING_TRACK_MODE = 2
3884 09:29:27.590154 SELPH_MODE = 1
3885 09:29:27.593177 PICG_EARLY_EN = 1
3886 09:29:27.597039 VALID_LAT_VALUE = 1
3887 09:29:27.603545 ==============================================================
3888 09:29:27.606617 Enter into Gating configuration >>>>
3889 09:29:27.609926 Exit from Gating configuration <<<<
3890 09:29:27.613217 Enter into DVFS_PRE_config >>>>>
3891 09:29:27.623076 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3892 09:29:27.626281 Exit from DVFS_PRE_config <<<<<
3893 09:29:27.629990 Enter into PICG configuration >>>>
3894 09:29:27.633011 Exit from PICG configuration <<<<
3895 09:29:27.636284 [RX_INPUT] configuration >>>>>
3896 09:29:27.639495 [RX_INPUT] configuration <<<<<
3897 09:29:27.642915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3898 09:29:27.649830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3899 09:29:27.656362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 09:29:27.663020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 09:29:27.669707 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 09:29:27.672909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 09:29:27.679559 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3904 09:29:27.682912 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3905 09:29:27.686167 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3906 09:29:27.689759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3907 09:29:27.696271 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3908 09:29:27.699535 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 09:29:27.702815 ===================================
3910 09:29:27.706156 LPDDR4 DRAM CONFIGURATION
3911 09:29:27.709473 ===================================
3912 09:29:27.709555 EX_ROW_EN[0] = 0x0
3913 09:29:27.713555 EX_ROW_EN[1] = 0x0
3914 09:29:27.713715 LP4Y_EN = 0x0
3915 09:29:27.716577 WORK_FSP = 0x0
3916 09:29:27.716712 WL = 0x2
3917 09:29:27.720030 RL = 0x2
3918 09:29:27.720163 BL = 0x2
3919 09:29:27.723513 RPST = 0x0
3920 09:29:27.723705 RD_PRE = 0x0
3921 09:29:27.726665 WR_PRE = 0x1
3922 09:29:27.726776 WR_PST = 0x0
3923 09:29:27.730332 DBI_WR = 0x0
3924 09:29:27.730490 DBI_RD = 0x0
3925 09:29:27.733371 OTF = 0x1
3926 09:29:27.736666 ===================================
3927 09:29:27.739795 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3928 09:29:27.742720 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3929 09:29:27.749428 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 09:29:27.752824 ===================================
3931 09:29:27.752927 LPDDR4 DRAM CONFIGURATION
3932 09:29:27.756170 ===================================
3933 09:29:27.759249 EX_ROW_EN[0] = 0x10
3934 09:29:27.763188 EX_ROW_EN[1] = 0x0
3935 09:29:27.763321 LP4Y_EN = 0x0
3936 09:29:27.766172 WORK_FSP = 0x0
3937 09:29:27.766305 WL = 0x2
3938 09:29:27.769742 RL = 0x2
3939 09:29:27.769892 BL = 0x2
3940 09:29:27.772743 RPST = 0x0
3941 09:29:27.772893 RD_PRE = 0x0
3942 09:29:27.776260 WR_PRE = 0x1
3943 09:29:27.776524 WR_PST = 0x0
3944 09:29:27.779345 DBI_WR = 0x0
3945 09:29:27.779550 DBI_RD = 0x0
3946 09:29:27.782672 OTF = 0x1
3947 09:29:27.786051 ===================================
3948 09:29:27.792816 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3949 09:29:27.796738 nWR fixed to 30
3950 09:29:27.797122 [ModeRegInit_LP4] CH0 RK0
3951 09:29:27.799970 [ModeRegInit_LP4] CH0 RK1
3952 09:29:27.802932 [ModeRegInit_LP4] CH1 RK0
3953 09:29:27.806274 [ModeRegInit_LP4] CH1 RK1
3954 09:29:27.806361 match AC timing 17
3955 09:29:27.813149 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3956 09:29:27.816006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3957 09:29:27.819901 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3958 09:29:27.826195 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3959 09:29:27.829907 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3960 09:29:27.830080 ==
3961 09:29:27.833180 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 09:29:27.836480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 09:29:27.836643 ==
3964 09:29:27.842515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 09:29:27.849357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3966 09:29:27.852541 [CA 0] Center 35 (5~66) winsize 62
3967 09:29:27.856347 [CA 1] Center 35 (5~66) winsize 62
3968 09:29:27.859364 [CA 2] Center 34 (3~65) winsize 63
3969 09:29:27.862866 [CA 3] Center 33 (2~64) winsize 63
3970 09:29:27.866877 [CA 4] Center 33 (2~64) winsize 63
3971 09:29:27.869786 [CA 5] Center 32 (2~62) winsize 61
3972 09:29:27.870207
3973 09:29:27.872491 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3974 09:29:27.872911
3975 09:29:27.876093 [CATrainingPosCal] consider 1 rank data
3976 09:29:27.879252 u2DelayCellTimex100 = 270/100 ps
3977 09:29:27.882574 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3978 09:29:27.886069 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3979 09:29:27.889071 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3980 09:29:27.892696 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3981 09:29:27.895907 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3982 09:29:27.899412 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3983 09:29:27.902672
3984 09:29:27.905193 CA PerBit enable=1, Macro0, CA PI delay=32
3985 09:29:27.905699
3986 09:29:27.908943 [CBTSetCACLKResult] CA Dly = 32
3987 09:29:27.909513 CS Dly: 4 (0~35)
3988 09:29:27.909988 ==
3989 09:29:27.912212 Dram Type= 6, Freq= 0, CH_0, rank 1
3990 09:29:27.915450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 09:29:27.915918 ==
3992 09:29:27.922445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 09:29:27.929254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3994 09:29:27.932296 [CA 0] Center 35 (5~66) winsize 62
3995 09:29:27.935628 [CA 1] Center 35 (5~66) winsize 62
3996 09:29:27.939411 [CA 2] Center 34 (3~65) winsize 63
3997 09:29:27.942410 [CA 3] Center 33 (3~64) winsize 62
3998 09:29:27.945820 [CA 4] Center 32 (2~63) winsize 62
3999 09:29:27.949476 [CA 5] Center 32 (2~63) winsize 62
4000 09:29:27.950003
4001 09:29:27.952629 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4002 09:29:27.953100
4003 09:29:27.956105 [CATrainingPosCal] consider 2 rank data
4004 09:29:27.959527 u2DelayCellTimex100 = 270/100 ps
4005 09:29:27.962255 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4006 09:29:27.965360 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4007 09:29:27.969324 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4008 09:29:27.972151 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4009 09:29:27.979115 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4010 09:29:27.982445 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
4011 09:29:27.982965
4012 09:29:27.985706 CA PerBit enable=1, Macro0, CA PI delay=32
4013 09:29:27.986129
4014 09:29:27.988573 [CBTSetCACLKResult] CA Dly = 32
4015 09:29:27.989093 CS Dly: 4 (0~36)
4016 09:29:27.989426
4017 09:29:27.991951 ----->DramcWriteLeveling(PI) begin...
4018 09:29:27.992480 ==
4019 09:29:27.995582 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 09:29:28.001642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 09:29:28.002058 ==
4022 09:29:28.005196 Write leveling (Byte 0): 33 => 33
4023 09:29:28.008651 Write leveling (Byte 1): 33 => 33
4024 09:29:28.009067 DramcWriteLeveling(PI) end<-----
4025 09:29:28.009393
4026 09:29:28.012041 ==
4027 09:29:28.015771 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 09:29:28.018789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 09:29:28.019206 ==
4030 09:29:28.022091 [Gating] SW mode calibration
4031 09:29:28.029079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4032 09:29:28.031757 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4033 09:29:28.038339 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 09:29:28.041535 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 09:29:28.044831 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4036 09:29:28.051619 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4037 09:29:28.055251 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4038 09:29:28.058872 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 09:29:28.065302 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 09:29:28.068951 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 09:29:28.071421 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 09:29:28.078148 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 09:29:28.081278 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4044 09:29:28.085059 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4045 09:29:28.092161 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4046 09:29:28.094967 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 09:29:28.098818 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 09:29:28.105344 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 09:29:28.108661 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 09:29:28.112107 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 09:29:28.115422 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 09:29:28.121562 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 09:29:28.125028 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4054 09:29:28.128115 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:29:28.134550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:29:28.138325 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:29:28.141256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:29:28.147973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:29:28.151237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:29:28.154484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:29:28.161194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 09:29:28.164618 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 09:29:28.168118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 09:29:28.174839 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 09:29:28.178216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 09:29:28.181367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 09:29:28.187942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 09:29:28.191345 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4069 09:29:28.194684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4070 09:29:28.197748 Total UI for P1: 0, mck2ui 16
4071 09:29:28.200899 best dqsien dly found for B0: ( 0, 13, 12)
4072 09:29:28.207535 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 09:29:28.207994 Total UI for P1: 0, mck2ui 16
4074 09:29:28.214863 best dqsien dly found for B1: ( 0, 13, 18)
4075 09:29:28.217930 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4076 09:29:28.221510 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4077 09:29:28.222020
4078 09:29:28.224490 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4079 09:29:28.227529 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4080 09:29:28.230931 [Gating] SW calibration Done
4081 09:29:28.231490 ==
4082 09:29:28.234221 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 09:29:28.237594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 09:29:28.238008 ==
4085 09:29:28.240736 RX Vref Scan: 0
4086 09:29:28.241142
4087 09:29:28.241462 RX Vref 0 -> 0, step: 1
4088 09:29:28.241764
4089 09:29:28.244410 RX Delay -230 -> 252, step: 16
4090 09:29:28.250975 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4091 09:29:28.254786 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4092 09:29:28.257675 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4093 09:29:28.260863 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4094 09:29:28.264293 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4095 09:29:28.270990 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4096 09:29:28.274585 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4097 09:29:28.277967 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4098 09:29:28.281141 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4099 09:29:28.284552 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4100 09:29:28.291503 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4101 09:29:28.294937 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4102 09:29:28.298007 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4103 09:29:28.301489 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4104 09:29:28.308329 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4105 09:29:28.311455 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4106 09:29:28.311996 ==
4107 09:29:28.314665 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 09:29:28.317998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 09:29:28.318473 ==
4110 09:29:28.321507 DQS Delay:
4111 09:29:28.322054 DQS0 = 0, DQS1 = 0
4112 09:29:28.322388 DQM Delay:
4113 09:29:28.324238 DQM0 = 52, DQM1 = 45
4114 09:29:28.324651 DQ Delay:
4115 09:29:28.327827 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4116 09:29:28.331808 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4117 09:29:28.334834 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4118 09:29:28.338325 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4119 09:29:28.338851
4120 09:29:28.339180
4121 09:29:28.339480 ==
4122 09:29:28.341410 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 09:29:28.344703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 09:29:28.348006 ==
4125 09:29:28.348416
4126 09:29:28.348737
4127 09:29:28.349035 TX Vref Scan disable
4128 09:29:28.351075 == TX Byte 0 ==
4129 09:29:28.354730 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4130 09:29:28.358314 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4131 09:29:28.361520 == TX Byte 1 ==
4132 09:29:28.364404 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4133 09:29:28.367781 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4134 09:29:28.371147 ==
4135 09:29:28.375107 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 09:29:28.377996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 09:29:28.378549 ==
4138 09:29:28.378892
4139 09:29:28.379196
4140 09:29:28.381293 TX Vref Scan disable
4141 09:29:28.381703 == TX Byte 0 ==
4142 09:29:28.387893 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4143 09:29:28.391504 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4144 09:29:28.392052 == TX Byte 1 ==
4145 09:29:28.397911 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4146 09:29:28.400581 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4147 09:29:28.400994
4148 09:29:28.401319 [DATLAT]
4149 09:29:28.403887 Freq=600, CH0 RK0
4150 09:29:28.404298
4151 09:29:28.404620 DATLAT Default: 0x9
4152 09:29:28.407274 0, 0xFFFF, sum = 0
4153 09:29:28.407721 1, 0xFFFF, sum = 0
4154 09:29:28.410512 2, 0xFFFF, sum = 0
4155 09:29:28.414783 3, 0xFFFF, sum = 0
4156 09:29:28.415301 4, 0xFFFF, sum = 0
4157 09:29:28.417464 5, 0xFFFF, sum = 0
4158 09:29:28.417979 6, 0xFFFF, sum = 0
4159 09:29:28.421498 7, 0xFFFF, sum = 0
4160 09:29:28.422023 8, 0x0, sum = 1
4161 09:29:28.422359 9, 0x0, sum = 2
4162 09:29:28.424353 10, 0x0, sum = 3
4163 09:29:28.424770 11, 0x0, sum = 4
4164 09:29:28.428010 best_step = 9
4165 09:29:28.428521
4166 09:29:28.428846 ==
4167 09:29:28.431136 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 09:29:28.434351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 09:29:28.434789 ==
4170 09:29:28.437930 RX Vref Scan: 1
4171 09:29:28.438407
4172 09:29:28.438844 RX Vref 0 -> 0, step: 1
4173 09:29:28.439262
4174 09:29:28.441284 RX Delay -163 -> 252, step: 8
4175 09:29:28.441695
4176 09:29:28.444404 Set Vref, RX VrefLevel [Byte0]: 56
4177 09:29:28.447675 [Byte1]: 49
4178 09:29:28.451916
4179 09:29:28.452440 Final RX Vref Byte 0 = 56 to rank0
4180 09:29:28.454969 Final RX Vref Byte 1 = 49 to rank0
4181 09:29:28.458369 Final RX Vref Byte 0 = 56 to rank1
4182 09:29:28.461349 Final RX Vref Byte 1 = 49 to rank1==
4183 09:29:28.464397 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 09:29:28.471531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 09:29:28.472090 ==
4186 09:29:28.472423 DQS Delay:
4187 09:29:28.472833 DQS0 = 0, DQS1 = 0
4188 09:29:28.474559 DQM Delay:
4189 09:29:28.475156 DQM0 = 53, DQM1 = 45
4190 09:29:28.477710 DQ Delay:
4191 09:29:28.481770 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4192 09:29:28.484705 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4193 09:29:28.487917 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4194 09:29:28.491716 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4195 09:29:28.492226
4196 09:29:28.492554
4197 09:29:28.497626 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4198 09:29:28.501066 CH0 RK0: MR19=808, MR18=7063
4199 09:29:28.507733 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4200 09:29:28.508250
4201 09:29:28.511925 ----->DramcWriteLeveling(PI) begin...
4202 09:29:28.512440 ==
4203 09:29:28.514639 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 09:29:28.518293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 09:29:28.518817 ==
4206 09:29:28.521831 Write leveling (Byte 0): 32 => 32
4207 09:29:28.525112 Write leveling (Byte 1): 31 => 31
4208 09:29:28.527856 DramcWriteLeveling(PI) end<-----
4209 09:29:28.528375
4210 09:29:28.528818 ==
4211 09:29:28.531199 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 09:29:28.534367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 09:29:28.534902 ==
4214 09:29:28.537436 [Gating] SW mode calibration
4215 09:29:28.544316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 09:29:28.551335 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4217 09:29:28.554702 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 09:29:28.557854 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 09:29:28.564716 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 09:29:28.567906 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4221 09:29:28.571452 0 9 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4222 09:29:28.577601 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 09:29:28.581738 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 09:29:28.584522 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 09:29:28.591153 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 09:29:28.594524 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 09:29:28.597347 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 09:29:28.604618 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4229 09:29:28.607702 0 10 16 | B1->B0 | 3e3e 4343 | 1 0 | (0 0) (0 0)
4230 09:29:28.610731 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 09:29:28.617668 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 09:29:28.620835 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 09:29:28.624341 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 09:29:28.630556 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 09:29:28.633559 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 09:29:28.637103 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4237 09:29:28.644005 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:29:28.647259 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:29:28.650659 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:29:28.657148 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:29:28.660854 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:29:28.663667 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 09:29:28.670413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 09:29:28.673638 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 09:29:28.677148 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 09:29:28.684244 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 09:29:28.686749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 09:29:28.690812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 09:29:28.697037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 09:29:28.700186 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 09:29:28.703520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 09:29:28.710417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 09:29:28.713672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 09:29:28.717170 Total UI for P1: 0, mck2ui 16
4255 09:29:28.719990 best dqsien dly found for B0: ( 0, 13, 14)
4256 09:29:28.723266 Total UI for P1: 0, mck2ui 16
4257 09:29:28.726735 best dqsien dly found for B1: ( 0, 13, 14)
4258 09:29:28.730081 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4259 09:29:28.733192 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4260 09:29:28.733627
4261 09:29:28.736441 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4262 09:29:28.740027 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4263 09:29:28.743516 [Gating] SW calibration Done
4264 09:29:28.744145 ==
4265 09:29:28.746551 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 09:29:28.752609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 09:29:28.753170 ==
4268 09:29:28.753614 RX Vref Scan: 0
4269 09:29:28.754058
4270 09:29:28.756019 RX Vref 0 -> 0, step: 1
4271 09:29:28.756453
4272 09:29:28.759391 RX Delay -230 -> 252, step: 16
4273 09:29:28.763070 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4274 09:29:28.766483 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4275 09:29:28.769741 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4276 09:29:28.776504 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4277 09:29:28.779442 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4278 09:29:28.782817 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4279 09:29:28.786314 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4280 09:29:28.789691 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4281 09:29:28.796169 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4282 09:29:28.799103 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4283 09:29:28.802710 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4284 09:29:28.806059 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4285 09:29:28.812595 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4286 09:29:28.816275 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4287 09:29:28.819044 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4288 09:29:28.822656 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4289 09:29:28.823168 ==
4290 09:29:28.826410 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 09:29:28.832636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 09:29:28.833133 ==
4293 09:29:28.833479 DQS Delay:
4294 09:29:28.835932 DQS0 = 0, DQS1 = 0
4295 09:29:28.836340 DQM Delay:
4296 09:29:28.836663 DQM0 = 52, DQM1 = 42
4297 09:29:28.839116 DQ Delay:
4298 09:29:28.842799 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4299 09:29:28.845893 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4300 09:29:28.849371 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4301 09:29:28.852581 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4302 09:29:28.853135
4303 09:29:28.853474
4304 09:29:28.853778 ==
4305 09:29:28.855960 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 09:29:28.859504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 09:29:28.860084 ==
4308 09:29:28.860418
4309 09:29:28.860717
4310 09:29:28.862901 TX Vref Scan disable
4311 09:29:28.866282 == TX Byte 0 ==
4312 09:29:28.869691 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4313 09:29:28.872666 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4314 09:29:28.875968 == TX Byte 1 ==
4315 09:29:28.879338 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4316 09:29:28.882628 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4317 09:29:28.883053 ==
4318 09:29:28.885724 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 09:29:28.888797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 09:29:28.889216 ==
4321 09:29:28.892024
4322 09:29:28.892434
4323 09:29:28.892806 TX Vref Scan disable
4324 09:29:28.895833 == TX Byte 0 ==
4325 09:29:28.899237 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4326 09:29:28.902650 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4327 09:29:28.906210 == TX Byte 1 ==
4328 09:29:28.909272 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4329 09:29:28.915522 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4330 09:29:28.915799
4331 09:29:28.915946 [DATLAT]
4332 09:29:28.916078 Freq=600, CH0 RK1
4333 09:29:28.916206
4334 09:29:28.919063 DATLAT Default: 0x9
4335 09:29:28.919218 0, 0xFFFF, sum = 0
4336 09:29:28.922193 1, 0xFFFF, sum = 0
4337 09:29:28.922352 2, 0xFFFF, sum = 0
4338 09:29:28.925756 3, 0xFFFF, sum = 0
4339 09:29:28.928681 4, 0xFFFF, sum = 0
4340 09:29:28.928820 5, 0xFFFF, sum = 0
4341 09:29:28.932168 6, 0xFFFF, sum = 0
4342 09:29:28.932343 7, 0xFFFF, sum = 0
4343 09:29:28.935113 8, 0x0, sum = 1
4344 09:29:28.935218 9, 0x0, sum = 2
4345 09:29:28.935304 10, 0x0, sum = 3
4346 09:29:28.938904 11, 0x0, sum = 4
4347 09:29:28.938999 best_step = 9
4348 09:29:28.939072
4349 09:29:28.939138 ==
4350 09:29:28.942091 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 09:29:28.948582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 09:29:28.948664 ==
4353 09:29:28.948729 RX Vref Scan: 0
4354 09:29:28.948789
4355 09:29:28.951751 RX Vref 0 -> 0, step: 1
4356 09:29:28.951831
4357 09:29:28.955269 RX Delay -179 -> 252, step: 8
4358 09:29:28.958781 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4359 09:29:28.965233 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4360 09:29:28.968599 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4361 09:29:28.972184 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4362 09:29:28.975356 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4363 09:29:28.978834 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4364 09:29:28.985410 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4365 09:29:28.988997 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4366 09:29:28.991960 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4367 09:29:28.995531 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4368 09:29:28.998591 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4369 09:29:29.005305 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4370 09:29:29.008412 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4371 09:29:29.012203 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4372 09:29:29.015722 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4373 09:29:29.022132 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4374 09:29:29.022637 ==
4375 09:29:29.025779 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 09:29:29.028540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 09:29:29.029051 ==
4378 09:29:29.029381 DQS Delay:
4379 09:29:29.032146 DQS0 = 0, DQS1 = 0
4380 09:29:29.032571 DQM Delay:
4381 09:29:29.035188 DQM0 = 53, DQM1 = 46
4382 09:29:29.035597 DQ Delay:
4383 09:29:29.038407 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4384 09:29:29.042378 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4385 09:29:29.045545 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4386 09:29:29.048722 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4387 09:29:29.049134
4388 09:29:29.049460
4389 09:29:29.055126 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4390 09:29:29.058560 CH0 RK1: MR19=808, MR18=6323
4391 09:29:29.065984 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4392 09:29:29.068634 [RxdqsGatingPostProcess] freq 600
4393 09:29:29.072397 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4394 09:29:29.075815 Pre-setting of DQS Precalculation
4395 09:29:29.082533 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4396 09:29:29.083038 ==
4397 09:29:29.085936 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 09:29:29.089111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 09:29:29.089619 ==
4400 09:29:29.095878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 09:29:29.102389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4402 09:29:29.105547 [CA 0] Center 35 (5~66) winsize 62
4403 09:29:29.109076 [CA 1] Center 35 (5~66) winsize 62
4404 09:29:29.112216 [CA 2] Center 34 (4~65) winsize 62
4405 09:29:29.115910 [CA 3] Center 34 (4~65) winsize 62
4406 09:29:29.118410 [CA 4] Center 34 (4~65) winsize 62
4407 09:29:29.122545 [CA 5] Center 33 (3~64) winsize 62
4408 09:29:29.123075
4409 09:29:29.125866 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4410 09:29:29.126373
4411 09:29:29.128324 [CATrainingPosCal] consider 1 rank data
4412 09:29:29.132016 u2DelayCellTimex100 = 270/100 ps
4413 09:29:29.135484 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 09:29:29.139009 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 09:29:29.142067 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 09:29:29.144957 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 09:29:29.148455 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 09:29:29.151687 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 09:29:29.152193
4420 09:29:29.158486 CA PerBit enable=1, Macro0, CA PI delay=33
4421 09:29:29.158897
4422 09:29:29.159220 [CBTSetCACLKResult] CA Dly = 33
4423 09:29:29.161508 CS Dly: 6 (0~37)
4424 09:29:29.161917 ==
4425 09:29:29.165339 Dram Type= 6, Freq= 0, CH_1, rank 1
4426 09:29:29.168313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 09:29:29.168725 ==
4428 09:29:29.175205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4429 09:29:29.181755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4430 09:29:29.186386 [CA 0] Center 36 (5~67) winsize 63
4431 09:29:29.188166 [CA 1] Center 36 (5~67) winsize 63
4432 09:29:29.191425 [CA 2] Center 34 (4~65) winsize 62
4433 09:29:29.194732 [CA 3] Center 34 (3~65) winsize 63
4434 09:29:29.198264 [CA 4] Center 34 (4~65) winsize 62
4435 09:29:29.201327 [CA 5] Center 34 (3~65) winsize 63
4436 09:29:29.201715
4437 09:29:29.204676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4438 09:29:29.205110
4439 09:29:29.207993 [CATrainingPosCal] consider 2 rank data
4440 09:29:29.211369 u2DelayCellTimex100 = 270/100 ps
4441 09:29:29.214765 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4442 09:29:29.218117 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 09:29:29.221176 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 09:29:29.224572 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 09:29:29.228412 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4446 09:29:29.235104 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4447 09:29:29.235515
4448 09:29:29.238520 CA PerBit enable=1, Macro0, CA PI delay=33
4449 09:29:29.238935
4450 09:29:29.241784 [CBTSetCACLKResult] CA Dly = 33
4451 09:29:29.242201 CS Dly: 6 (0~37)
4452 09:29:29.242529
4453 09:29:29.245065 ----->DramcWriteLeveling(PI) begin...
4454 09:29:29.245486 ==
4455 09:29:29.248340 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 09:29:29.251448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 09:29:29.255322 ==
4458 09:29:29.255808 Write leveling (Byte 0): 31 => 31
4459 09:29:29.258133 Write leveling (Byte 1): 32 => 32
4460 09:29:29.261818 DramcWriteLeveling(PI) end<-----
4461 09:29:29.262224
4462 09:29:29.262541 ==
4463 09:29:29.264758 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 09:29:29.271213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 09:29:29.271720 ==
4466 09:29:29.272059 [Gating] SW mode calibration
4467 09:29:29.281170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4468 09:29:29.284867 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4469 09:29:29.288109 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 09:29:29.294975 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 09:29:29.297783 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 09:29:29.301610 0 9 12 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
4473 09:29:29.308240 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4474 09:29:29.311775 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 09:29:29.315290 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 09:29:29.321994 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 09:29:29.325115 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 09:29:29.328539 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 09:29:29.335129 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4480 09:29:29.337859 0 10 12 | B1->B0 | 3434 3a3a | 1 1 | (0 0) (0 0)
4481 09:29:29.341785 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 09:29:29.347813 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 09:29:29.351311 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 09:29:29.354563 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 09:29:29.361672 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 09:29:29.364848 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 09:29:29.367973 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 09:29:29.374633 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:29:29.377822 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:29:29.381372 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:29:29.387718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:29:29.391025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:29:29.394566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:29:29.401010 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:29:29.404639 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:29:29.407807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 09:29:29.410841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 09:29:29.418075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 09:29:29.421368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 09:29:29.424089 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 09:29:29.430853 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 09:29:29.433916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 09:29:29.437276 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 09:29:29.444558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4505 09:29:29.447778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 09:29:29.451127 Total UI for P1: 0, mck2ui 16
4507 09:29:29.454483 best dqsien dly found for B0: ( 0, 13, 12)
4508 09:29:29.457930 Total UI for P1: 0, mck2ui 16
4509 09:29:29.461272 best dqsien dly found for B1: ( 0, 13, 12)
4510 09:29:29.463872 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4511 09:29:29.467336 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4512 09:29:29.467756
4513 09:29:29.470671 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4514 09:29:29.474015 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4515 09:29:29.477848 [Gating] SW calibration Done
4516 09:29:29.478289 ==
4517 09:29:29.480858 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 09:29:29.487176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 09:29:29.487553 ==
4520 09:29:29.487936 RX Vref Scan: 0
4521 09:29:29.488260
4522 09:29:29.491044 RX Vref 0 -> 0, step: 1
4523 09:29:29.491420
4524 09:29:29.494130 RX Delay -230 -> 252, step: 16
4525 09:29:29.497267 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4526 09:29:29.500691 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4527 09:29:29.504372 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4528 09:29:29.511032 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4529 09:29:29.513871 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4530 09:29:29.517110 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4531 09:29:29.520364 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4532 09:29:29.527050 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4533 09:29:29.531000 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4534 09:29:29.533888 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4535 09:29:29.537330 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4536 09:29:29.540453 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4537 09:29:29.547134 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4538 09:29:29.550589 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4539 09:29:29.553702 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4540 09:29:29.557141 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4541 09:29:29.557550 ==
4542 09:29:29.560400 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 09:29:29.567365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 09:29:29.567915 ==
4545 09:29:29.568243 DQS Delay:
4546 09:29:29.570427 DQS0 = 0, DQS1 = 0
4547 09:29:29.570838 DQM Delay:
4548 09:29:29.571162 DQM0 = 53, DQM1 = 52
4549 09:29:29.573743 DQ Delay:
4550 09:29:29.577161 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4551 09:29:29.580421 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4552 09:29:29.584024 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4553 09:29:29.587137 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4554 09:29:29.587547
4555 09:29:29.587922
4556 09:29:29.588228 ==
4557 09:29:29.590739 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 09:29:29.593748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 09:29:29.594262 ==
4560 09:29:29.594643
4561 09:29:29.594948
4562 09:29:29.597071 TX Vref Scan disable
4563 09:29:29.597652 == TX Byte 0 ==
4564 09:29:29.603620 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4565 09:29:29.607216 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4566 09:29:29.607777 == TX Byte 1 ==
4567 09:29:29.613918 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4568 09:29:29.617188 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4569 09:29:29.617866 ==
4570 09:29:29.620024 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 09:29:29.624016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 09:29:29.624544 ==
4573 09:29:29.624875
4574 09:29:29.625176
4575 09:29:29.627349 TX Vref Scan disable
4576 09:29:29.630708 == TX Byte 0 ==
4577 09:29:29.633604 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4578 09:29:29.640637 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4579 09:29:29.641175 == TX Byte 1 ==
4580 09:29:29.643209 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4581 09:29:29.650080 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4582 09:29:29.650581
4583 09:29:29.650911 [DATLAT]
4584 09:29:29.651216 Freq=600, CH1 RK0
4585 09:29:29.651511
4586 09:29:29.653424 DATLAT Default: 0x9
4587 09:29:29.653964 0, 0xFFFF, sum = 0
4588 09:29:29.656910 1, 0xFFFF, sum = 0
4589 09:29:29.657389 2, 0xFFFF, sum = 0
4590 09:29:29.660148 3, 0xFFFF, sum = 0
4591 09:29:29.663586 4, 0xFFFF, sum = 0
4592 09:29:29.664154 5, 0xFFFF, sum = 0
4593 09:29:29.667081 6, 0xFFFF, sum = 0
4594 09:29:29.667591 7, 0xFFFF, sum = 0
4595 09:29:29.667983 8, 0x0, sum = 1
4596 09:29:29.670105 9, 0x0, sum = 2
4597 09:29:29.670517 10, 0x0, sum = 3
4598 09:29:29.673774 11, 0x0, sum = 4
4599 09:29:29.674290 best_step = 9
4600 09:29:29.674617
4601 09:29:29.674915 ==
4602 09:29:29.677143 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 09:29:29.684026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 09:29:29.684539 ==
4605 09:29:29.684866 RX Vref Scan: 1
4606 09:29:29.685167
4607 09:29:29.687469 RX Vref 0 -> 0, step: 1
4608 09:29:29.688053
4609 09:29:29.689779 RX Delay -163 -> 252, step: 8
4610 09:29:29.690189
4611 09:29:29.693389 Set Vref, RX VrefLevel [Byte0]: 55
4612 09:29:29.696619 [Byte1]: 51
4613 09:29:29.697156
4614 09:29:29.699856 Final RX Vref Byte 0 = 55 to rank0
4615 09:29:29.703804 Final RX Vref Byte 1 = 51 to rank0
4616 09:29:29.706726 Final RX Vref Byte 0 = 55 to rank1
4617 09:29:29.709809 Final RX Vref Byte 1 = 51 to rank1==
4618 09:29:29.713577 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 09:29:29.716644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 09:29:29.717058 ==
4621 09:29:29.720213 DQS Delay:
4622 09:29:29.720622 DQS0 = 0, DQS1 = 0
4623 09:29:29.720946 DQM Delay:
4624 09:29:29.723318 DQM0 = 48, DQM1 = 45
4625 09:29:29.723779 DQ Delay:
4626 09:29:29.726338 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4627 09:29:29.729950 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4628 09:29:29.733499 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4629 09:29:29.736562 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4630 09:29:29.736973
4631 09:29:29.737297
4632 09:29:29.746519 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4633 09:29:29.749932 CH1 RK0: MR19=808, MR18=4D73
4634 09:29:29.753598 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4635 09:29:29.754245
4636 09:29:29.756468 ----->DramcWriteLeveling(PI) begin...
4637 09:29:29.760017 ==
4638 09:29:29.763394 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 09:29:29.766782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 09:29:29.767297 ==
4641 09:29:29.769736 Write leveling (Byte 0): 30 => 30
4642 09:29:29.773477 Write leveling (Byte 1): 30 => 30
4643 09:29:29.776456 DramcWriteLeveling(PI) end<-----
4644 09:29:29.776872
4645 09:29:29.777196 ==
4646 09:29:29.779998 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 09:29:29.783732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 09:29:29.784249 ==
4649 09:29:29.787013 [Gating] SW mode calibration
4650 09:29:29.793067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4651 09:29:29.799527 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4652 09:29:29.803149 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 09:29:29.806572 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 09:29:29.809474 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 09:29:29.816926 0 9 12 | B1->B0 | 2d2d 3030 | 1 0 | (1 0) (0 1)
4656 09:29:29.819379 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 09:29:29.823369 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 09:29:29.830084 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 09:29:29.832848 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 09:29:29.836345 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 09:29:29.843080 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 09:29:29.846305 0 10 8 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4663 09:29:29.849334 0 10 12 | B1->B0 | 3f3f 3a3a | 0 0 | (0 0) (0 0)
4664 09:29:29.855971 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 09:29:29.859352 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 09:29:29.862642 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 09:29:29.869518 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 09:29:29.872513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 09:29:29.876674 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 09:29:29.883233 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 09:29:29.886240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:29:29.889667 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:29:29.896409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:29:29.899577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 09:29:29.902977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:29:29.909939 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:29:29.912860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:29:29.916293 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 09:29:29.923244 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 09:29:29.926570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 09:29:29.929860 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 09:29:29.936183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 09:29:29.939468 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 09:29:29.942681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 09:29:29.945451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 09:29:29.952212 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 09:29:29.955448 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 09:29:29.959309 Total UI for P1: 0, mck2ui 16
4689 09:29:29.962499 best dqsien dly found for B0: ( 0, 13, 10)
4690 09:29:29.966170 Total UI for P1: 0, mck2ui 16
4691 09:29:29.969302 best dqsien dly found for B1: ( 0, 13, 10)
4692 09:29:29.972619 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4693 09:29:29.976094 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4694 09:29:29.976603
4695 09:29:29.979471 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 09:29:29.985657 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4697 09:29:29.986168 [Gating] SW calibration Done
4698 09:29:29.986496 ==
4699 09:29:29.988828 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 09:29:29.995948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 09:29:29.996458 ==
4702 09:29:29.996784 RX Vref Scan: 0
4703 09:29:29.997089
4704 09:29:29.998686 RX Vref 0 -> 0, step: 1
4705 09:29:29.999092
4706 09:29:30.002456 RX Delay -230 -> 252, step: 16
4707 09:29:30.005501 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4708 09:29:30.008577 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4709 09:29:30.015292 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4710 09:29:30.018721 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4711 09:29:30.021904 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4712 09:29:30.025583 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4713 09:29:30.028562 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4714 09:29:30.035464 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4715 09:29:30.038783 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4716 09:29:30.042072 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4717 09:29:30.045377 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4718 09:29:30.052098 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4719 09:29:30.055258 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4720 09:29:30.058510 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4721 09:29:30.062468 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4722 09:29:30.065662 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4723 09:29:30.068331 ==
4724 09:29:30.071928 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 09:29:30.075525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 09:29:30.075976 ==
4727 09:29:30.076303 DQS Delay:
4728 09:29:30.078938 DQS0 = 0, DQS1 = 0
4729 09:29:30.079345 DQM Delay:
4730 09:29:30.082469 DQM0 = 50, DQM1 = 48
4731 09:29:30.082983 DQ Delay:
4732 09:29:30.085779 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4733 09:29:30.088875 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4734 09:29:30.092621 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4735 09:29:30.094969 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4736 09:29:30.095380
4737 09:29:30.095752
4738 09:29:30.096066 ==
4739 09:29:30.098634 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 09:29:30.101539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 09:29:30.102008 ==
4742 09:29:30.102363
4743 09:29:30.102671
4744 09:29:30.104891 TX Vref Scan disable
4745 09:29:30.108210 == TX Byte 0 ==
4746 09:29:30.111466 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4747 09:29:30.115251 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4748 09:29:30.118376 == TX Byte 1 ==
4749 09:29:30.121941 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4750 09:29:30.124986 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4751 09:29:30.125584 ==
4752 09:29:30.128846 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 09:29:30.131954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 09:29:30.135185 ==
4755 09:29:30.135600
4756 09:29:30.135992
4757 09:29:30.136301 TX Vref Scan disable
4758 09:29:30.139344 == TX Byte 0 ==
4759 09:29:30.142357 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4760 09:29:30.149213 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4761 09:29:30.149632 == TX Byte 1 ==
4762 09:29:30.152104 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 09:29:30.159244 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 09:29:30.159809
4765 09:29:30.160148 [DATLAT]
4766 09:29:30.160452 Freq=600, CH1 RK1
4767 09:29:30.160742
4768 09:29:30.162609 DATLAT Default: 0x9
4769 09:29:30.163123 0, 0xFFFF, sum = 0
4770 09:29:30.165646 1, 0xFFFF, sum = 0
4771 09:29:30.166068 2, 0xFFFF, sum = 0
4772 09:29:30.168747 3, 0xFFFF, sum = 0
4773 09:29:30.172566 4, 0xFFFF, sum = 0
4774 09:29:30.172987 5, 0xFFFF, sum = 0
4775 09:29:30.175800 6, 0xFFFF, sum = 0
4776 09:29:30.176222 7, 0xFFFF, sum = 0
4777 09:29:30.178981 8, 0x0, sum = 1
4778 09:29:30.179501 9, 0x0, sum = 2
4779 09:29:30.179942 10, 0x0, sum = 3
4780 09:29:30.182344 11, 0x0, sum = 4
4781 09:29:30.182762 best_step = 9
4782 09:29:30.183087
4783 09:29:30.183393 ==
4784 09:29:30.185421 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 09:29:30.192345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 09:29:30.192811 ==
4787 09:29:30.193144 RX Vref Scan: 0
4788 09:29:30.193454
4789 09:29:30.196063 RX Vref 0 -> 0, step: 1
4790 09:29:30.196574
4791 09:29:30.199346 RX Delay -163 -> 252, step: 8
4792 09:29:30.202501 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4793 09:29:30.209615 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4794 09:29:30.212040 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4795 09:29:30.215382 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4796 09:29:30.218872 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4797 09:29:30.222072 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4798 09:29:30.229271 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4799 09:29:30.232282 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4800 09:29:30.235547 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4801 09:29:30.238631 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4802 09:29:30.241888 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4803 09:29:30.249052 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4804 09:29:30.251910 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4805 09:29:30.255549 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4806 09:29:30.258451 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4807 09:29:30.261941 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4808 09:29:30.265382 ==
4809 09:29:30.268745 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 09:29:30.271906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 09:29:30.272317 ==
4812 09:29:30.272640 DQS Delay:
4813 09:29:30.275723 DQS0 = 0, DQS1 = 0
4814 09:29:30.276141 DQM Delay:
4815 09:29:30.278434 DQM0 = 48, DQM1 = 45
4816 09:29:30.278937 DQ Delay:
4817 09:29:30.282340 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4818 09:29:30.285342 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4819 09:29:30.288418 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4820 09:29:30.292148 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4821 09:29:30.292557
4822 09:29:30.292881
4823 09:29:30.298589 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4824 09:29:30.302221 CH1 RK1: MR19=808, MR18=6D25
4825 09:29:30.308780 CH1_RK1: MR19=0x808, MR18=0x6D25, DQSOSC=389, MR23=63, INC=173, DEC=115
4826 09:29:30.312036 [RxdqsGatingPostProcess] freq 600
4827 09:29:30.318818 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4828 09:29:30.321927 Pre-setting of DQS Precalculation
4829 09:29:30.325489 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4830 09:29:30.331739 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4831 09:29:30.337890 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4832 09:29:30.338479
4833 09:29:30.339004
4834 09:29:30.341384 [Calibration Summary] 1200 Mbps
4835 09:29:30.344905 CH 0, Rank 0
4836 09:29:30.345315 SW Impedance : PASS
4837 09:29:30.348367 DUTY Scan : NO K
4838 09:29:30.351266 ZQ Calibration : PASS
4839 09:29:30.351914 Jitter Meter : NO K
4840 09:29:30.354639 CBT Training : PASS
4841 09:29:30.357784 Write leveling : PASS
4842 09:29:30.358292 RX DQS gating : PASS
4843 09:29:30.361587 RX DQ/DQS(RDDQC) : PASS
4844 09:29:30.362156 TX DQ/DQS : PASS
4845 09:29:30.364467 RX DATLAT : PASS
4846 09:29:30.368075 RX DQ/DQS(Engine): PASS
4847 09:29:30.368492 TX OE : NO K
4848 09:29:30.371235 All Pass.
4849 09:29:30.371694
4850 09:29:30.372059 CH 0, Rank 1
4851 09:29:30.374734 SW Impedance : PASS
4852 09:29:30.375325 DUTY Scan : NO K
4853 09:29:30.377904 ZQ Calibration : PASS
4854 09:29:30.381570 Jitter Meter : NO K
4855 09:29:30.382070 CBT Training : PASS
4856 09:29:30.384866 Write leveling : PASS
4857 09:29:30.387929 RX DQS gating : PASS
4858 09:29:30.388469 RX DQ/DQS(RDDQC) : PASS
4859 09:29:30.391125 TX DQ/DQS : PASS
4860 09:29:30.394807 RX DATLAT : PASS
4861 09:29:30.395223 RX DQ/DQS(Engine): PASS
4862 09:29:30.397566 TX OE : NO K
4863 09:29:30.398050 All Pass.
4864 09:29:30.398455
4865 09:29:30.401297 CH 1, Rank 0
4866 09:29:30.401834 SW Impedance : PASS
4867 09:29:30.404523 DUTY Scan : NO K
4868 09:29:30.407681 ZQ Calibration : PASS
4869 09:29:30.408122 Jitter Meter : NO K
4870 09:29:30.410977 CBT Training : PASS
4871 09:29:30.414680 Write leveling : PASS
4872 09:29:30.415119 RX DQS gating : PASS
4873 09:29:30.417935 RX DQ/DQS(RDDQC) : PASS
4874 09:29:30.418379 TX DQ/DQS : PASS
4875 09:29:30.421257 RX DATLAT : PASS
4876 09:29:30.424779 RX DQ/DQS(Engine): PASS
4877 09:29:30.425228 TX OE : NO K
4878 09:29:30.427550 All Pass.
4879 09:29:30.428090
4880 09:29:30.428439 CH 1, Rank 1
4881 09:29:30.430860 SW Impedance : PASS
4882 09:29:30.431394 DUTY Scan : NO K
4883 09:29:30.434165 ZQ Calibration : PASS
4884 09:29:30.437436 Jitter Meter : NO K
4885 09:29:30.437661 CBT Training : PASS
4886 09:29:30.440631 Write leveling : PASS
4887 09:29:30.443745 RX DQS gating : PASS
4888 09:29:30.443981 RX DQ/DQS(RDDQC) : PASS
4889 09:29:30.447565 TX DQ/DQS : PASS
4890 09:29:30.451017 RX DATLAT : PASS
4891 09:29:30.451253 RX DQ/DQS(Engine): PASS
4892 09:29:30.453684 TX OE : NO K
4893 09:29:30.453922 All Pass.
4894 09:29:30.454125
4895 09:29:30.457096 DramC Write-DBI off
4896 09:29:30.460611 PER_BANK_REFRESH: Hybrid Mode
4897 09:29:30.460792 TX_TRACKING: ON
4898 09:29:30.470651 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4899 09:29:30.473992 [FAST_K] Save calibration result to emmc
4900 09:29:30.477244 dramc_set_vcore_voltage set vcore to 662500
4901 09:29:30.480489 Read voltage for 933, 3
4902 09:29:30.480671 Vio18 = 0
4903 09:29:30.480823 Vcore = 662500
4904 09:29:30.484081 Vdram = 0
4905 09:29:30.484261 Vddq = 0
4906 09:29:30.484402 Vmddr = 0
4907 09:29:30.490573 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4908 09:29:30.493572 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4909 09:29:30.496878 MEM_TYPE=3, freq_sel=17
4910 09:29:30.500042 sv_algorithm_assistance_LP4_1600
4911 09:29:30.503543 ============ PULL DRAM RESETB DOWN ============
4912 09:29:30.506928 ========== PULL DRAM RESETB DOWN end =========
4913 09:29:30.513750 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4914 09:29:30.517057 ===================================
4915 09:29:30.517222 LPDDR4 DRAM CONFIGURATION
4916 09:29:30.520414 ===================================
4917 09:29:30.523696 EX_ROW_EN[0] = 0x0
4918 09:29:30.526881 EX_ROW_EN[1] = 0x0
4919 09:29:30.527087 LP4Y_EN = 0x0
4920 09:29:30.530714 WORK_FSP = 0x0
4921 09:29:30.530935 WL = 0x3
4922 09:29:30.533500 RL = 0x3
4923 09:29:30.533710 BL = 0x2
4924 09:29:30.536913 RPST = 0x0
4925 09:29:30.537121 RD_PRE = 0x0
4926 09:29:30.540302 WR_PRE = 0x1
4927 09:29:30.540511 WR_PST = 0x0
4928 09:29:30.543696 DBI_WR = 0x0
4929 09:29:30.543906 DBI_RD = 0x0
4930 09:29:30.547015 OTF = 0x1
4931 09:29:30.550271 ===================================
4932 09:29:30.553384 ===================================
4933 09:29:30.553596 ANA top config
4934 09:29:30.557344 ===================================
4935 09:29:30.560042 DLL_ASYNC_EN = 0
4936 09:29:30.563454 ALL_SLAVE_EN = 1
4937 09:29:30.566907 NEW_RANK_MODE = 1
4938 09:29:30.567119 DLL_IDLE_MODE = 1
4939 09:29:30.570343 LP45_APHY_COMB_EN = 1
4940 09:29:30.573882 TX_ODT_DIS = 1
4941 09:29:30.577409 NEW_8X_MODE = 1
4942 09:29:30.580082 ===================================
4943 09:29:30.583448 ===================================
4944 09:29:30.583672 data_rate = 1866
4945 09:29:30.586863 CKR = 1
4946 09:29:30.590183 DQ_P2S_RATIO = 8
4947 09:29:30.593523 ===================================
4948 09:29:30.596825 CA_P2S_RATIO = 8
4949 09:29:30.600596 DQ_CA_OPEN = 0
4950 09:29:30.603718 DQ_SEMI_OPEN = 0
4951 09:29:30.603972 CA_SEMI_OPEN = 0
4952 09:29:30.607314 CA_FULL_RATE = 0
4953 09:29:30.610343 DQ_CKDIV4_EN = 1
4954 09:29:30.613636 CA_CKDIV4_EN = 1
4955 09:29:30.617543 CA_PREDIV_EN = 0
4956 09:29:30.620793 PH8_DLY = 0
4957 09:29:30.621171 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4958 09:29:30.624027 DQ_AAMCK_DIV = 4
4959 09:29:30.627040 CA_AAMCK_DIV = 4
4960 09:29:30.630673 CA_ADMCK_DIV = 4
4961 09:29:30.633872 DQ_TRACK_CA_EN = 0
4962 09:29:30.637076 CA_PICK = 933
4963 09:29:30.637459 CA_MCKIO = 933
4964 09:29:30.640261 MCKIO_SEMI = 0
4965 09:29:30.643671 PLL_FREQ = 3732
4966 09:29:30.647277 DQ_UI_PI_RATIO = 32
4967 09:29:30.650430 CA_UI_PI_RATIO = 0
4968 09:29:30.653693 ===================================
4969 09:29:30.657048 ===================================
4970 09:29:30.660447 memory_type:LPDDR4
4971 09:29:30.660863 GP_NUM : 10
4972 09:29:30.663999 SRAM_EN : 1
4973 09:29:30.664414 MD32_EN : 0
4974 09:29:30.667520 ===================================
4975 09:29:30.670852 [ANA_INIT] >>>>>>>>>>>>>>
4976 09:29:30.673702 <<<<<< [CONFIGURE PHASE]: ANA_TX
4977 09:29:30.676999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4978 09:29:30.680151 ===================================
4979 09:29:30.683419 data_rate = 1866,PCW = 0X8f00
4980 09:29:30.686725 ===================================
4981 09:29:30.690009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4982 09:29:30.696974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 09:29:30.700428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 09:29:30.706889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4985 09:29:30.709998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4986 09:29:30.713825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4987 09:29:30.714243 [ANA_INIT] flow start
4988 09:29:30.716981 [ANA_INIT] PLL >>>>>>>>
4989 09:29:30.720198 [ANA_INIT] PLL <<<<<<<<
4990 09:29:30.720610 [ANA_INIT] MIDPI >>>>>>>>
4991 09:29:30.723277 [ANA_INIT] MIDPI <<<<<<<<
4992 09:29:30.726880 [ANA_INIT] DLL >>>>>>>>
4993 09:29:30.727405 [ANA_INIT] flow end
4994 09:29:30.733804 ============ LP4 DIFF to SE enter ============
4995 09:29:30.736438 ============ LP4 DIFF to SE exit ============
4996 09:29:30.740578 [ANA_INIT] <<<<<<<<<<<<<
4997 09:29:30.743800 [Flow] Enable top DCM control >>>>>
4998 09:29:30.746685 [Flow] Enable top DCM control <<<<<
4999 09:29:30.747100 Enable DLL master slave shuffle
5000 09:29:30.753298 ==============================================================
5001 09:29:30.756802 Gating Mode config
5002 09:29:30.760097 ==============================================================
5003 09:29:30.763942 Config description:
5004 09:29:30.773300 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5005 09:29:30.780661 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5006 09:29:30.783677 SELPH_MODE 0: By rank 1: By Phase
5007 09:29:30.790029 ==============================================================
5008 09:29:30.793258 GAT_TRACK_EN = 1
5009 09:29:30.796864 RX_GATING_MODE = 2
5010 09:29:30.799825 RX_GATING_TRACK_MODE = 2
5011 09:29:30.800249 SELPH_MODE = 1
5012 09:29:30.803118 PICG_EARLY_EN = 1
5013 09:29:30.806739 VALID_LAT_VALUE = 1
5014 09:29:30.813205 ==============================================================
5015 09:29:30.816214 Enter into Gating configuration >>>>
5016 09:29:30.820348 Exit from Gating configuration <<<<
5017 09:29:30.823276 Enter into DVFS_PRE_config >>>>>
5018 09:29:30.833614 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5019 09:29:30.836545 Exit from DVFS_PRE_config <<<<<
5020 09:29:30.839632 Enter into PICG configuration >>>>
5021 09:29:30.843426 Exit from PICG configuration <<<<
5022 09:29:30.846664 [RX_INPUT] configuration >>>>>
5023 09:29:30.849507 [RX_INPUT] configuration <<<<<
5024 09:29:30.852996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5025 09:29:30.859544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5026 09:29:30.866149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 09:29:30.873700 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 09:29:30.879498 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 09:29:30.883220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 09:29:30.889880 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5031 09:29:30.892992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5032 09:29:30.896540 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5033 09:29:30.900021 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5034 09:29:30.906536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5035 09:29:30.909543 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 09:29:30.913235 ===================================
5037 09:29:30.916438 LPDDR4 DRAM CONFIGURATION
5038 09:29:30.919391 ===================================
5039 09:29:30.919853 EX_ROW_EN[0] = 0x0
5040 09:29:30.922725 EX_ROW_EN[1] = 0x0
5041 09:29:30.923182 LP4Y_EN = 0x0
5042 09:29:30.925988 WORK_FSP = 0x0
5043 09:29:30.926405 WL = 0x3
5044 09:29:30.929554 RL = 0x3
5045 09:29:30.930063 BL = 0x2
5046 09:29:30.932617 RPST = 0x0
5047 09:29:30.933149 RD_PRE = 0x0
5048 09:29:30.936146 WR_PRE = 0x1
5049 09:29:30.936560 WR_PST = 0x0
5050 09:29:30.939144 DBI_WR = 0x0
5051 09:29:30.939556 DBI_RD = 0x0
5052 09:29:30.942290 OTF = 0x1
5053 09:29:30.945624 ===================================
5054 09:29:30.949024 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5055 09:29:30.952381 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5056 09:29:30.959376 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 09:29:30.962712 ===================================
5058 09:29:30.963128 LPDDR4 DRAM CONFIGURATION
5059 09:29:30.965433 ===================================
5060 09:29:30.968719 EX_ROW_EN[0] = 0x10
5061 09:29:30.972564 EX_ROW_EN[1] = 0x0
5062 09:29:30.972979 LP4Y_EN = 0x0
5063 09:29:30.975811 WORK_FSP = 0x0
5064 09:29:30.976222 WL = 0x3
5065 09:29:30.979053 RL = 0x3
5066 09:29:30.979464 BL = 0x2
5067 09:29:30.982469 RPST = 0x0
5068 09:29:30.982879 RD_PRE = 0x0
5069 09:29:30.985811 WR_PRE = 0x1
5070 09:29:30.986101 WR_PST = 0x0
5071 09:29:30.988477 DBI_WR = 0x0
5072 09:29:30.988768 DBI_RD = 0x0
5073 09:29:30.991909 OTF = 0x1
5074 09:29:30.995168 ===================================
5075 09:29:31.001987 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5076 09:29:31.005434 nWR fixed to 30
5077 09:29:31.008890 [ModeRegInit_LP4] CH0 RK0
5078 09:29:31.009085 [ModeRegInit_LP4] CH0 RK1
5079 09:29:31.012157 [ModeRegInit_LP4] CH1 RK0
5080 09:29:31.015444 [ModeRegInit_LP4] CH1 RK1
5081 09:29:31.015653 match AC timing 9
5082 09:29:31.022155 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5083 09:29:31.025446 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5084 09:29:31.028669 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5085 09:29:31.035150 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5086 09:29:31.038307 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5087 09:29:31.038381 ==
5088 09:29:31.041960 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 09:29:31.045328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 09:29:31.045402 ==
5091 09:29:31.051777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 09:29:31.058608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5093 09:29:31.062037 [CA 0] Center 37 (7~68) winsize 62
5094 09:29:31.065459 [CA 1] Center 37 (7~68) winsize 62
5095 09:29:31.068198 [CA 2] Center 34 (4~65) winsize 62
5096 09:29:31.071493 [CA 3] Center 33 (3~64) winsize 62
5097 09:29:31.074739 [CA 4] Center 33 (3~64) winsize 62
5098 09:29:31.078638 [CA 5] Center 32 (2~62) winsize 61
5099 09:29:31.078711
5100 09:29:31.081863 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5101 09:29:31.081934
5102 09:29:31.084900 [CATrainingPosCal] consider 1 rank data
5103 09:29:31.088326 u2DelayCellTimex100 = 270/100 ps
5104 09:29:31.091832 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5105 09:29:31.095151 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5106 09:29:31.098591 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5107 09:29:31.101444 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5108 09:29:31.104995 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5109 09:29:31.108426 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5110 09:29:31.108498
5111 09:29:31.111606 CA PerBit enable=1, Macro0, CA PI delay=32
5112 09:29:31.115268
5113 09:29:31.115399 [CBTSetCACLKResult] CA Dly = 32
5114 09:29:31.118427 CS Dly: 5 (0~36)
5115 09:29:31.118510 ==
5116 09:29:31.121891 Dram Type= 6, Freq= 0, CH_0, rank 1
5117 09:29:31.124748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 09:29:31.124824 ==
5119 09:29:31.132081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 09:29:31.138221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5121 09:29:31.141431 [CA 0] Center 37 (6~68) winsize 63
5122 09:29:31.145185 [CA 1] Center 37 (7~68) winsize 62
5123 09:29:31.148302 [CA 2] Center 34 (4~65) winsize 62
5124 09:29:31.152055 [CA 3] Center 34 (4~65) winsize 62
5125 09:29:31.155080 [CA 4] Center 33 (3~63) winsize 61
5126 09:29:31.158174 [CA 5] Center 32 (2~63) winsize 62
5127 09:29:31.158258
5128 09:29:31.162018 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5129 09:29:31.162102
5130 09:29:31.165353 [CATrainingPosCal] consider 2 rank data
5131 09:29:31.168227 u2DelayCellTimex100 = 270/100 ps
5132 09:29:31.171610 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5133 09:29:31.174974 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5134 09:29:31.178318 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5135 09:29:31.181596 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5136 09:29:31.184991 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5137 09:29:31.188272 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5138 09:29:31.188357
5139 09:29:31.194792 CA PerBit enable=1, Macro0, CA PI delay=32
5140 09:29:31.194877
5141 09:29:31.194962 [CBTSetCACLKResult] CA Dly = 32
5142 09:29:31.197882 CS Dly: 5 (0~37)
5143 09:29:31.197966
5144 09:29:31.201210 ----->DramcWriteLeveling(PI) begin...
5145 09:29:31.201295 ==
5146 09:29:31.204598 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 09:29:31.207849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 09:29:31.207933 ==
5149 09:29:31.211504 Write leveling (Byte 0): 32 => 32
5150 09:29:31.214822 Write leveling (Byte 1): 30 => 30
5151 09:29:31.218309 DramcWriteLeveling(PI) end<-----
5152 09:29:31.218392
5153 09:29:31.218478 ==
5154 09:29:31.221674 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 09:29:31.227817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 09:29:31.227904 ==
5157 09:29:31.227989 [Gating] SW mode calibration
5158 09:29:31.237964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 09:29:31.241140 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5160 09:29:31.244948 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5161 09:29:31.251049 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 09:29:31.254795 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 09:29:31.257770 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 09:29:31.264790 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 09:29:31.267913 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 09:29:31.271387 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5167 09:29:31.277950 0 14 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
5168 09:29:31.281482 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5169 09:29:31.284585 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 09:29:31.291512 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 09:29:31.294702 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 09:29:31.297863 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 09:29:31.304620 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 09:29:31.308065 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5175 09:29:31.311583 0 15 28 | B1->B0 | 2525 3f3f | 0 1 | (0 0) (0 0)
5176 09:29:31.318411 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5177 09:29:31.321343 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 09:29:31.324805 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 09:29:31.328210 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 09:29:31.334479 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 09:29:31.337765 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 09:29:31.341688 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 09:29:31.348308 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5184 09:29:31.351535 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5185 09:29:31.354748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:29:31.361498 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:29:31.364884 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 09:29:31.368187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:29:31.374704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 09:29:31.378175 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:29:31.381283 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:29:31.387806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 09:29:31.391289 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 09:29:31.394685 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 09:29:31.401419 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 09:29:31.404440 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 09:29:31.408211 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 09:29:31.414769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 09:29:31.417575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5200 09:29:31.421097 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 09:29:31.424370 Total UI for P1: 0, mck2ui 16
5202 09:29:31.427876 best dqsien dly found for B0: ( 1, 2, 28)
5203 09:29:31.431176 Total UI for P1: 0, mck2ui 16
5204 09:29:31.434557 best dqsien dly found for B1: ( 1, 2, 28)
5205 09:29:31.437863 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5206 09:29:31.441233 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5207 09:29:31.441411
5208 09:29:31.444412 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5209 09:29:31.451143 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5210 09:29:31.451341 [Gating] SW calibration Done
5211 09:29:31.451483 ==
5212 09:29:31.454662 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 09:29:31.461325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 09:29:31.461504 ==
5215 09:29:31.461644 RX Vref Scan: 0
5216 09:29:31.461792
5217 09:29:31.464691 RX Vref 0 -> 0, step: 1
5218 09:29:31.464867
5219 09:29:31.467426 RX Delay -80 -> 252, step: 8
5220 09:29:31.470734 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5221 09:29:31.474361 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5222 09:29:31.477672 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5223 09:29:31.480968 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5224 09:29:31.487524 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5225 09:29:31.491199 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5226 09:29:31.494475 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5227 09:29:31.497766 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5228 09:29:31.501547 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5229 09:29:31.504491 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5230 09:29:31.510933 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5231 09:29:31.514493 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5232 09:29:31.517744 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5233 09:29:31.521082 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5234 09:29:31.524733 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5235 09:29:31.527633 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5236 09:29:31.527815 ==
5237 09:29:31.530978 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 09:29:31.537927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 09:29:31.538149 ==
5240 09:29:31.538369 DQS Delay:
5241 09:29:31.541272 DQS0 = 0, DQS1 = 0
5242 09:29:31.541426 DQM Delay:
5243 09:29:31.544065 DQM0 = 104, DQM1 = 94
5244 09:29:31.544213 DQ Delay:
5245 09:29:31.547524 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5246 09:29:31.550869 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5247 09:29:31.554191 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =91
5248 09:29:31.558006 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5249 09:29:31.558275
5250 09:29:31.558539
5251 09:29:31.558721 ==
5252 09:29:31.561216 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 09:29:31.564569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 09:29:31.564821 ==
5255 09:29:31.565084
5256 09:29:31.565284
5257 09:29:31.567974 TX Vref Scan disable
5258 09:29:31.571172 == TX Byte 0 ==
5259 09:29:31.574554 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5260 09:29:31.578013 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5261 09:29:31.581268 == TX Byte 1 ==
5262 09:29:31.584760 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 09:29:31.587415 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 09:29:31.587842 ==
5265 09:29:31.591322 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 09:29:31.597446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 09:29:31.597796 ==
5268 09:29:31.598130
5269 09:29:31.598470
5270 09:29:31.598778 TX Vref Scan disable
5271 09:29:31.601613 == TX Byte 0 ==
5272 09:29:31.605077 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5273 09:29:31.611616 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5274 09:29:31.612018 == TX Byte 1 ==
5275 09:29:31.614863 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5276 09:29:31.621524 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5277 09:29:31.621928
5278 09:29:31.622261 [DATLAT]
5279 09:29:31.622617 Freq=933, CH0 RK0
5280 09:29:31.622925
5281 09:29:31.624653 DATLAT Default: 0xd
5282 09:29:31.625034 0, 0xFFFF, sum = 0
5283 09:29:31.627734 1, 0xFFFF, sum = 0
5284 09:29:31.628107 2, 0xFFFF, sum = 0
5285 09:29:31.631419 3, 0xFFFF, sum = 0
5286 09:29:31.634956 4, 0xFFFF, sum = 0
5287 09:29:31.635285 5, 0xFFFF, sum = 0
5288 09:29:31.638278 6, 0xFFFF, sum = 0
5289 09:29:31.638666 7, 0xFFFF, sum = 0
5290 09:29:31.641822 8, 0xFFFF, sum = 0
5291 09:29:31.642251 9, 0xFFFF, sum = 0
5292 09:29:31.644962 10, 0x0, sum = 1
5293 09:29:31.645296 11, 0x0, sum = 2
5294 09:29:31.645631 12, 0x0, sum = 3
5295 09:29:31.648268 13, 0x0, sum = 4
5296 09:29:31.648717 best_step = 11
5297 09:29:31.649144
5298 09:29:31.651738 ==
5299 09:29:31.652103 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 09:29:31.658170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 09:29:31.658502 ==
5302 09:29:31.658895 RX Vref Scan: 1
5303 09:29:31.659213
5304 09:29:31.661528 RX Vref 0 -> 0, step: 1
5305 09:29:31.661852
5306 09:29:31.664931 RX Delay -45 -> 252, step: 4
5307 09:29:31.665366
5308 09:29:31.668569 Set Vref, RX VrefLevel [Byte0]: 56
5309 09:29:31.671836 [Byte1]: 49
5310 09:29:31.672165
5311 09:29:31.675054 Final RX Vref Byte 0 = 56 to rank0
5312 09:29:31.678276 Final RX Vref Byte 1 = 49 to rank0
5313 09:29:31.681867 Final RX Vref Byte 0 = 56 to rank1
5314 09:29:31.684899 Final RX Vref Byte 1 = 49 to rank1==
5315 09:29:31.688456 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 09:29:31.691573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 09:29:31.692050 ==
5318 09:29:31.694718 DQS Delay:
5319 09:29:31.695189 DQS0 = 0, DQS1 = 0
5320 09:29:31.698269 DQM Delay:
5321 09:29:31.698682 DQM0 = 104, DQM1 = 95
5322 09:29:31.698939 DQ Delay:
5323 09:29:31.704884 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5324 09:29:31.708049 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5325 09:29:31.711562 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =92
5326 09:29:31.714916 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5327 09:29:31.715328
5328 09:29:31.715585
5329 09:29:31.721365 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5330 09:29:31.724274 CH0 RK0: MR19=505, MR18=3229
5331 09:29:31.731513 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5332 09:29:31.732086
5333 09:29:31.734849 ----->DramcWriteLeveling(PI) begin...
5334 09:29:31.735361 ==
5335 09:29:31.737972 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 09:29:31.741552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 09:29:31.742064 ==
5338 09:29:31.745379 Write leveling (Byte 0): 32 => 32
5339 09:29:31.748219 Write leveling (Byte 1): 31 => 31
5340 09:29:31.751316 DramcWriteLeveling(PI) end<-----
5341 09:29:31.751792
5342 09:29:31.752135 ==
5343 09:29:31.754615 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 09:29:31.758183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 09:29:31.758696 ==
5346 09:29:31.761343 [Gating] SW mode calibration
5347 09:29:31.767614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 09:29:31.774459 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 09:29:31.778006 0 14 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
5350 09:29:31.784077 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 09:29:31.787868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 09:29:31.791230 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 09:29:31.797757 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 09:29:31.800889 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 09:29:31.804140 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5356 09:29:31.811133 0 14 28 | B1->B0 | 2a2a 2b2b | 1 1 | (1 1) (1 0)
5357 09:29:31.814520 0 15 0 | B1->B0 | 2424 2727 | 0 1 | (0 0) (0 0)
5358 09:29:31.817578 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 09:29:31.820744 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 09:29:31.827942 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 09:29:31.831724 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 09:29:31.834755 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 09:29:31.841441 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5364 09:29:31.844836 0 15 28 | B1->B0 | 3737 3232 | 0 0 | (0 0) (0 0)
5365 09:29:31.847809 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 09:29:31.854371 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 09:29:31.857733 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 09:29:31.861094 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 09:29:31.867831 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 09:29:31.870953 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 09:29:31.873836 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 09:29:31.880589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5373 09:29:31.884283 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5374 09:29:31.887330 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:29:31.894113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:29:31.897528 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:29:31.900531 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 09:29:31.907758 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 09:29:31.910744 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 09:29:31.914333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 09:29:31.921026 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 09:29:31.923762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 09:29:31.926912 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 09:29:31.934428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 09:29:31.937543 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 09:29:31.941112 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 09:29:31.947150 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 09:29:31.950558 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 09:29:31.953799 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 09:29:31.957272 Total UI for P1: 0, mck2ui 16
5391 09:29:31.960422 best dqsien dly found for B0: ( 1, 2, 28)
5392 09:29:31.963631 Total UI for P1: 0, mck2ui 16
5393 09:29:31.967309 best dqsien dly found for B1: ( 1, 2, 28)
5394 09:29:31.970748 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5395 09:29:31.974088 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5396 09:29:31.974600
5397 09:29:31.976902 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5398 09:29:31.984124 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 09:29:31.984628 [Gating] SW calibration Done
5400 09:29:31.985034 ==
5401 09:29:31.987310 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 09:29:31.993660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 09:29:31.994156 ==
5404 09:29:31.994481 RX Vref Scan: 0
5405 09:29:31.994785
5406 09:29:31.997333 RX Vref 0 -> 0, step: 1
5407 09:29:31.997839
5408 09:29:32.000299 RX Delay -80 -> 252, step: 8
5409 09:29:32.003594 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5410 09:29:32.006877 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5411 09:29:32.010670 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5412 09:29:32.013823 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5413 09:29:32.020233 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5414 09:29:32.023564 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5415 09:29:32.026868 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5416 09:29:32.030412 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5417 09:29:32.033599 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5418 09:29:32.036924 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5419 09:29:32.043823 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5420 09:29:32.047156 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5421 09:29:32.050285 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5422 09:29:32.053666 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5423 09:29:32.057359 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5424 09:29:32.063399 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5425 09:29:32.063858 ==
5426 09:29:32.066728 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 09:29:32.069986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 09:29:32.070488 ==
5429 09:29:32.070816 DQS Delay:
5430 09:29:32.073119 DQS0 = 0, DQS1 = 0
5431 09:29:32.073525 DQM Delay:
5432 09:29:32.077092 DQM0 = 104, DQM1 = 94
5433 09:29:32.077505 DQ Delay:
5434 09:29:32.080504 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5435 09:29:32.083584 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5436 09:29:32.087065 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5437 09:29:32.090374 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5438 09:29:32.090882
5439 09:29:32.091202
5440 09:29:32.091556 ==
5441 09:29:32.093343 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 09:29:32.096919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 09:29:32.100425 ==
5444 09:29:32.100928
5445 09:29:32.101248
5446 09:29:32.101745 TX Vref Scan disable
5447 09:29:32.103575 == TX Byte 0 ==
5448 09:29:32.107091 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5449 09:29:32.110362 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5450 09:29:32.113582 == TX Byte 1 ==
5451 09:29:32.116719 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5452 09:29:32.120162 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5453 09:29:32.120672 ==
5454 09:29:32.123803 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 09:29:32.130571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 09:29:32.131083 ==
5457 09:29:32.131408
5458 09:29:32.131757
5459 09:29:32.132087 TX Vref Scan disable
5460 09:29:32.134895 == TX Byte 0 ==
5461 09:29:32.137672 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5462 09:29:32.140866 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5463 09:29:32.144654 == TX Byte 1 ==
5464 09:29:32.148073 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5465 09:29:32.150755 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5466 09:29:32.154520
5467 09:29:32.154928 [DATLAT]
5468 09:29:32.155253 Freq=933, CH0 RK1
5469 09:29:32.155558
5470 09:29:32.158389 DATLAT Default: 0xb
5471 09:29:32.158891 0, 0xFFFF, sum = 0
5472 09:29:32.161741 1, 0xFFFF, sum = 0
5473 09:29:32.162251 2, 0xFFFF, sum = 0
5474 09:29:32.164173 3, 0xFFFF, sum = 0
5475 09:29:32.164586 4, 0xFFFF, sum = 0
5476 09:29:32.167865 5, 0xFFFF, sum = 0
5477 09:29:32.168374 6, 0xFFFF, sum = 0
5478 09:29:32.171138 7, 0xFFFF, sum = 0
5479 09:29:32.174749 8, 0xFFFF, sum = 0
5480 09:29:32.175263 9, 0xFFFF, sum = 0
5481 09:29:32.177569 10, 0x0, sum = 1
5482 09:29:32.178034 11, 0x0, sum = 2
5483 09:29:32.178379 12, 0x0, sum = 3
5484 09:29:32.180855 13, 0x0, sum = 4
5485 09:29:32.181374 best_step = 11
5486 09:29:32.181701
5487 09:29:32.182001 ==
5488 09:29:32.184656 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 09:29:32.191115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 09:29:32.191530 ==
5491 09:29:32.191903 RX Vref Scan: 0
5492 09:29:32.192209
5493 09:29:32.194535 RX Vref 0 -> 0, step: 1
5494 09:29:32.195019
5495 09:29:32.198158 RX Delay -45 -> 252, step: 4
5496 09:29:32.201022 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5497 09:29:32.207886 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5498 09:29:32.211299 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5499 09:29:32.214324 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5500 09:29:32.217343 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5501 09:29:32.221349 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5502 09:29:32.224480 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5503 09:29:32.231302 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5504 09:29:32.234767 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5505 09:29:32.238081 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5506 09:29:32.240613 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5507 09:29:32.244584 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5508 09:29:32.251024 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5509 09:29:32.254143 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5510 09:29:32.257570 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5511 09:29:32.260726 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5512 09:29:32.261175 ==
5513 09:29:32.263742 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 09:29:32.271216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 09:29:32.271779 ==
5516 09:29:32.272114 DQS Delay:
5517 09:29:32.272415 DQS0 = 0, DQS1 = 0
5518 09:29:32.274144 DQM Delay:
5519 09:29:32.274553 DQM0 = 105, DQM1 = 94
5520 09:29:32.277351 DQ Delay:
5521 09:29:32.280535 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5522 09:29:32.284326 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5523 09:29:32.287454 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5524 09:29:32.290937 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5525 09:29:32.291577
5526 09:29:32.291976
5527 09:29:32.297289 [DQSOSCAuto] RK1, (LSB)MR18= 0x2901, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5528 09:29:32.300390 CH0 RK1: MR19=505, MR18=2901
5529 09:29:32.307865 CH0_RK1: MR19=0x505, MR18=0x2901, DQSOSC=408, MR23=63, INC=65, DEC=43
5530 09:29:32.310801 [RxdqsGatingPostProcess] freq 933
5531 09:29:32.317404 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5532 09:29:32.317862 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 09:29:32.320672 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 09:29:32.324091 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 09:29:32.327152 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 09:29:32.330930 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 09:29:32.334274 best DQS1 dly(2T, 0.5T) = (0, 10)
5538 09:29:32.337585 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 09:29:32.340879 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5540 09:29:32.344365 Pre-setting of DQS Precalculation
5541 09:29:32.348017 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5542 09:29:32.351024 ==
5543 09:29:32.351440 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 09:29:32.357278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 09:29:32.357789 ==
5546 09:29:32.360300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 09:29:32.367523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5548 09:29:32.370831 [CA 0] Center 36 (6~67) winsize 62
5549 09:29:32.374692 [CA 1] Center 36 (6~67) winsize 62
5550 09:29:32.377670 [CA 2] Center 34 (4~65) winsize 62
5551 09:29:32.381244 [CA 3] Center 34 (4~65) winsize 62
5552 09:29:32.384252 [CA 4] Center 34 (4~65) winsize 62
5553 09:29:32.387579 [CA 5] Center 33 (3~63) winsize 61
5554 09:29:32.388034
5555 09:29:32.391229 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5556 09:29:32.391794
5557 09:29:32.393991 [CATrainingPosCal] consider 1 rank data
5558 09:29:32.397655 u2DelayCellTimex100 = 270/100 ps
5559 09:29:32.400540 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 09:29:32.403967 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 09:29:32.411159 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 09:29:32.414326 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 09:29:32.417556 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5564 09:29:32.420669 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5565 09:29:32.421085
5566 09:29:32.424153 CA PerBit enable=1, Macro0, CA PI delay=33
5567 09:29:32.424635
5568 09:29:32.427316 [CBTSetCACLKResult] CA Dly = 33
5569 09:29:32.427763 CS Dly: 7 (0~38)
5570 09:29:32.428096 ==
5571 09:29:32.430464 Dram Type= 6, Freq= 0, CH_1, rank 1
5572 09:29:32.437502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 09:29:32.437983 ==
5574 09:29:32.440538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 09:29:32.447880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5576 09:29:32.451135 [CA 0] Center 37 (6~68) winsize 63
5577 09:29:32.454673 [CA 1] Center 37 (6~68) winsize 63
5578 09:29:32.457845 [CA 2] Center 35 (4~66) winsize 63
5579 09:29:32.460980 [CA 3] Center 34 (4~65) winsize 62
5580 09:29:32.464270 [CA 4] Center 34 (4~65) winsize 62
5581 09:29:32.467746 [CA 5] Center 34 (4~64) winsize 61
5582 09:29:32.468159
5583 09:29:32.471078 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5584 09:29:32.471490
5585 09:29:32.474478 [CATrainingPosCal] consider 2 rank data
5586 09:29:32.478117 u2DelayCellTimex100 = 270/100 ps
5587 09:29:32.480918 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 09:29:32.484105 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 09:29:32.490582 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5590 09:29:32.494112 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5591 09:29:32.497389 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5592 09:29:32.501017 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5593 09:29:32.501528
5594 09:29:32.504132 CA PerBit enable=1, Macro0, CA PI delay=33
5595 09:29:32.504640
5596 09:29:32.506987 [CBTSetCACLKResult] CA Dly = 33
5597 09:29:32.507411 CS Dly: 8 (0~40)
5598 09:29:32.510783
5599 09:29:32.513784 ----->DramcWriteLeveling(PI) begin...
5600 09:29:32.514206 ==
5601 09:29:32.517719 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 09:29:32.520219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 09:29:32.520645 ==
5604 09:29:32.524005 Write leveling (Byte 0): 26 => 26
5605 09:29:32.526916 Write leveling (Byte 1): 28 => 28
5606 09:29:32.530412 DramcWriteLeveling(PI) end<-----
5607 09:29:32.530922
5608 09:29:32.531250 ==
5609 09:29:32.533768 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 09:29:32.536707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 09:29:32.537139 ==
5612 09:29:32.540196 [Gating] SW mode calibration
5613 09:29:32.547180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 09:29:32.553579 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5615 09:29:32.557135 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 09:29:32.560433 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 09:29:32.567108 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 09:29:32.570105 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 09:29:32.573529 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 09:29:32.580491 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 09:29:32.583791 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5622 09:29:32.586825 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5623 09:29:32.593543 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 09:29:32.596495 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 09:29:32.599744 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 09:29:32.606502 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 09:29:32.609860 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 09:29:32.613133 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5629 09:29:32.619759 0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5630 09:29:32.622986 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5631 09:29:32.626198 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 09:29:32.633162 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 09:29:32.636630 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 09:29:32.639465 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 09:29:32.643262 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 09:29:32.649602 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5637 09:29:32.653297 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 09:29:32.656210 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:29:32.662734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:29:32.666460 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:29:32.669874 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:29:32.676124 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:29:32.679980 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 09:29:32.683080 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 09:29:32.689674 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 09:29:32.692759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:29:32.696018 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 09:29:32.703155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 09:29:32.705974 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 09:29:32.710067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 09:29:32.716332 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 09:29:32.719810 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 09:29:32.723001 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5654 09:29:32.729787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 09:29:32.730299 Total UI for P1: 0, mck2ui 16
5656 09:29:32.736377 best dqsien dly found for B0: ( 1, 2, 24)
5657 09:29:32.736887 Total UI for P1: 0, mck2ui 16
5658 09:29:32.739610 best dqsien dly found for B1: ( 1, 2, 24)
5659 09:29:32.746202 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5660 09:29:32.749753 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5661 09:29:32.750167
5662 09:29:32.753254 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 09:29:32.756029 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 09:29:32.759762 [Gating] SW calibration Done
5665 09:29:32.760181 ==
5666 09:29:32.762855 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 09:29:32.765970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 09:29:32.766480 ==
5669 09:29:32.769424 RX Vref Scan: 0
5670 09:29:32.769932
5671 09:29:32.770257 RX Vref 0 -> 0, step: 1
5672 09:29:32.770559
5673 09:29:32.772907 RX Delay -80 -> 252, step: 8
5674 09:29:32.775983 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5675 09:29:32.780151 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5676 09:29:32.785918 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5677 09:29:32.789247 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5678 09:29:32.792589 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5679 09:29:32.795922 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5680 09:29:32.799440 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 09:29:32.802580 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5682 09:29:32.809570 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5683 09:29:32.812927 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5684 09:29:32.816390 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5685 09:29:32.819435 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5686 09:29:32.822491 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5687 09:29:32.826365 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5688 09:29:32.833173 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5689 09:29:32.835898 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5690 09:29:32.836320 ==
5691 09:29:32.839197 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 09:29:32.842769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 09:29:32.843284 ==
5694 09:29:32.846257 DQS Delay:
5695 09:29:32.846761 DQS0 = 0, DQS1 = 0
5696 09:29:32.847087 DQM Delay:
5697 09:29:32.849269 DQM0 = 102, DQM1 = 98
5698 09:29:32.849684 DQ Delay:
5699 09:29:32.852623 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5700 09:29:32.855781 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5701 09:29:32.859162 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5702 09:29:32.862483 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5703 09:29:32.866220
5704 09:29:32.866730
5705 09:29:32.867070 ==
5706 09:29:32.869008 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 09:29:32.872343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 09:29:32.872762 ==
5709 09:29:32.873129
5710 09:29:32.873580
5711 09:29:32.875464 TX Vref Scan disable
5712 09:29:32.875913 == TX Byte 0 ==
5713 09:29:32.882557 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 09:29:32.886301 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 09:29:32.886808 == TX Byte 1 ==
5716 09:29:32.892824 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5717 09:29:32.896205 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5718 09:29:32.896623 ==
5719 09:29:32.899235 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 09:29:32.902672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 09:29:32.903201 ==
5722 09:29:32.903565
5723 09:29:32.903948
5724 09:29:32.905702 TX Vref Scan disable
5725 09:29:32.908879 == TX Byte 0 ==
5726 09:29:32.912274 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 09:29:32.915928 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 09:29:32.919036 == TX Byte 1 ==
5729 09:29:32.922479 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5730 09:29:32.925868 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5731 09:29:32.926380
5732 09:29:32.928628 [DATLAT]
5733 09:29:32.929072 Freq=933, CH1 RK0
5734 09:29:32.929401
5735 09:29:32.932228 DATLAT Default: 0xd
5736 09:29:32.932640 0, 0xFFFF, sum = 0
5737 09:29:32.935911 1, 0xFFFF, sum = 0
5738 09:29:32.936429 2, 0xFFFF, sum = 0
5739 09:29:32.938740 3, 0xFFFF, sum = 0
5740 09:29:32.939162 4, 0xFFFF, sum = 0
5741 09:29:32.942534 5, 0xFFFF, sum = 0
5742 09:29:32.942954 6, 0xFFFF, sum = 0
5743 09:29:32.945846 7, 0xFFFF, sum = 0
5744 09:29:32.946412 8, 0xFFFF, sum = 0
5745 09:29:32.948831 9, 0xFFFF, sum = 0
5746 09:29:32.949250 10, 0x0, sum = 1
5747 09:29:32.951949 11, 0x0, sum = 2
5748 09:29:32.952372 12, 0x0, sum = 3
5749 09:29:32.955244 13, 0x0, sum = 4
5750 09:29:32.955703 best_step = 11
5751 09:29:32.956046
5752 09:29:32.956351 ==
5753 09:29:32.958584 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 09:29:32.965126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 09:29:32.965543 ==
5756 09:29:32.965869 RX Vref Scan: 1
5757 09:29:32.966172
5758 09:29:32.968199 RX Vref 0 -> 0, step: 1
5759 09:29:32.968613
5760 09:29:32.972296 RX Delay -45 -> 252, step: 4
5761 09:29:32.972709
5762 09:29:32.975793 Set Vref, RX VrefLevel [Byte0]: 55
5763 09:29:32.978373 [Byte1]: 51
5764 09:29:32.978788
5765 09:29:32.981963 Final RX Vref Byte 0 = 55 to rank0
5766 09:29:32.985768 Final RX Vref Byte 1 = 51 to rank0
5767 09:29:32.988601 Final RX Vref Byte 0 = 55 to rank1
5768 09:29:32.991947 Final RX Vref Byte 1 = 51 to rank1==
5769 09:29:32.995451 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 09:29:32.998458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 09:29:32.998873 ==
5772 09:29:33.001591 DQS Delay:
5773 09:29:33.002015 DQS0 = 0, DQS1 = 0
5774 09:29:33.002405 DQM Delay:
5775 09:29:33.004848 DQM0 = 103, DQM1 = 100
5776 09:29:33.005259 DQ Delay:
5777 09:29:33.008206 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5778 09:29:33.011606 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5779 09:29:33.014903 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5780 09:29:33.018110 DQ12 =108, DQ13 =104, DQ14 =108, DQ15 =108
5781 09:29:33.021914
5782 09:29:33.022326
5783 09:29:33.028164 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5784 09:29:33.031688 CH1 RK0: MR19=505, MR18=1A31
5785 09:29:33.038496 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5786 09:29:33.038997
5787 09:29:33.041654 ----->DramcWriteLeveling(PI) begin...
5788 09:29:33.042076 ==
5789 09:29:33.045093 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 09:29:33.048447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 09:29:33.048860 ==
5792 09:29:33.051684 Write leveling (Byte 0): 26 => 26
5793 09:29:33.054864 Write leveling (Byte 1): 27 => 27
5794 09:29:33.058378 DramcWriteLeveling(PI) end<-----
5795 09:29:33.058830
5796 09:29:33.059153 ==
5797 09:29:33.061669 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 09:29:33.065257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 09:29:33.065672 ==
5800 09:29:33.068001 [Gating] SW mode calibration
5801 09:29:33.074763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 09:29:33.081615 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 09:29:33.084674 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 09:29:33.088509 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 09:29:33.094990 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 09:29:33.098187 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 09:29:33.101729 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 09:29:33.108322 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5809 09:29:33.111531 0 14 24 | B1->B0 | 2a2a 3030 | 0 1 | (1 0) (1 0)
5810 09:29:33.114893 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5811 09:29:33.121680 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 09:29:33.124900 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 09:29:33.128342 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 09:29:33.135041 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 09:29:33.138354 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 09:29:33.141470 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 09:29:33.148117 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (1 1) (0 0)
5818 09:29:33.151366 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
5819 09:29:33.154720 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 09:29:33.161079 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 09:29:33.164948 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 09:29:33.168075 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 09:29:33.174495 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 09:29:33.177786 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 09:29:33.181036 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5826 09:29:33.184660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5827 09:29:33.191117 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:29:33.194242 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:29:33.197893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:29:33.204703 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:29:33.208053 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 09:29:33.211516 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 09:29:33.217970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 09:29:33.221173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:29:33.224847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:29:33.231187 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 09:29:33.234559 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 09:29:33.238243 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 09:29:33.245003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 09:29:33.248116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5841 09:29:33.251300 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5842 09:29:33.258122 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5843 09:29:33.258614 Total UI for P1: 0, mck2ui 16
5844 09:29:33.264471 best dqsien dly found for B1: ( 1, 2, 22)
5845 09:29:33.267751 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 09:29:33.270991 Total UI for P1: 0, mck2ui 16
5847 09:29:33.274355 best dqsien dly found for B0: ( 1, 2, 28)
5848 09:29:33.278293 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5849 09:29:33.281742 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5850 09:29:33.282161
5851 09:29:33.284976 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5852 09:29:33.288209 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5853 09:29:33.291704 [Gating] SW calibration Done
5854 09:29:33.292208 ==
5855 09:29:33.294748 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 09:29:33.298632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 09:29:33.299154 ==
5858 09:29:33.301984 RX Vref Scan: 0
5859 09:29:33.302507
5860 09:29:33.304999 RX Vref 0 -> 0, step: 1
5861 09:29:33.305506
5862 09:29:33.305838 RX Delay -80 -> 252, step: 8
5863 09:29:33.311407 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5864 09:29:33.314868 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5865 09:29:33.317778 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5866 09:29:33.321167 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5867 09:29:33.324551 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5868 09:29:33.328217 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5869 09:29:33.334618 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5870 09:29:33.337901 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5871 09:29:33.341118 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5872 09:29:33.344656 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5873 09:29:33.347399 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5874 09:29:33.351145 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5875 09:29:33.357912 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5876 09:29:33.361072 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5877 09:29:33.364289 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5878 09:29:33.367451 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5879 09:29:33.367911 ==
5880 09:29:33.371373 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 09:29:33.377563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 09:29:33.378079 ==
5883 09:29:33.378455 DQS Delay:
5884 09:29:33.378771 DQS0 = 0, DQS1 = 0
5885 09:29:33.380972 DQM Delay:
5886 09:29:33.381481 DQM0 = 102, DQM1 = 99
5887 09:29:33.384598 DQ Delay:
5888 09:29:33.387737 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5889 09:29:33.391204 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5890 09:29:33.394565 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =95
5891 09:29:33.398160 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5892 09:29:33.398676
5893 09:29:33.399009
5894 09:29:33.399316 ==
5895 09:29:33.401089 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 09:29:33.404584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 09:29:33.405094 ==
5898 09:29:33.405427
5899 09:29:33.405732
5900 09:29:33.407729 TX Vref Scan disable
5901 09:29:33.411059 == TX Byte 0 ==
5902 09:29:33.414194 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5903 09:29:33.417616 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5904 09:29:33.420663 == TX Byte 1 ==
5905 09:29:33.424196 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5906 09:29:33.427589 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5907 09:29:33.428148 ==
5908 09:29:33.431507 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 09:29:33.433971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 09:29:33.437193 ==
5911 09:29:33.437605
5912 09:29:33.437931
5913 09:29:33.438235 TX Vref Scan disable
5914 09:29:33.441130 == TX Byte 0 ==
5915 09:29:33.444421 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5916 09:29:33.450671 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5917 09:29:33.451085 == TX Byte 1 ==
5918 09:29:33.454244 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5919 09:29:33.460772 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5920 09:29:33.461344
5921 09:29:33.461681 [DATLAT]
5922 09:29:33.461988 Freq=933, CH1 RK1
5923 09:29:33.462284
5924 09:29:33.464204 DATLAT Default: 0xb
5925 09:29:33.464716 0, 0xFFFF, sum = 0
5926 09:29:33.467174 1, 0xFFFF, sum = 0
5927 09:29:33.470901 2, 0xFFFF, sum = 0
5928 09:29:33.471421 3, 0xFFFF, sum = 0
5929 09:29:33.474273 4, 0xFFFF, sum = 0
5930 09:29:33.474789 5, 0xFFFF, sum = 0
5931 09:29:33.477146 6, 0xFFFF, sum = 0
5932 09:29:33.477567 7, 0xFFFF, sum = 0
5933 09:29:33.480507 8, 0xFFFF, sum = 0
5934 09:29:33.481022 9, 0xFFFF, sum = 0
5935 09:29:33.484197 10, 0x0, sum = 1
5936 09:29:33.484704 11, 0x0, sum = 2
5937 09:29:33.487178 12, 0x0, sum = 3
5938 09:29:33.487763 13, 0x0, sum = 4
5939 09:29:33.488111 best_step = 11
5940 09:29:33.490397
5941 09:29:33.490888 ==
5942 09:29:33.494070 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 09:29:33.497089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 09:29:33.497505 ==
5945 09:29:33.497947 RX Vref Scan: 0
5946 09:29:33.498333
5947 09:29:33.500547 RX Vref 0 -> 0, step: 1
5948 09:29:33.500963
5949 09:29:33.503719 RX Delay -45 -> 252, step: 4
5950 09:29:33.507626 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5951 09:29:33.513711 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5952 09:29:33.516963 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5953 09:29:33.520918 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5954 09:29:33.524181 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5955 09:29:33.527597 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5956 09:29:33.533699 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5957 09:29:33.537307 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5958 09:29:33.540393 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5959 09:29:33.543385 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5960 09:29:33.546643 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5961 09:29:33.553098 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5962 09:29:33.556605 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5963 09:29:33.559952 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5964 09:29:33.563348 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5965 09:29:33.566779 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5966 09:29:33.570006 ==
5967 09:29:33.570493 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 09:29:33.576615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 09:29:33.577109 ==
5970 09:29:33.577440 DQS Delay:
5971 09:29:33.580002 DQS0 = 0, DQS1 = 0
5972 09:29:33.580489 DQM Delay:
5973 09:29:33.583178 DQM0 = 105, DQM1 = 101
5974 09:29:33.583589 DQ Delay:
5975 09:29:33.586482 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5976 09:29:33.590160 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5977 09:29:33.593080 DQ8 =92, DQ9 =92, DQ10 =98, DQ11 =94
5978 09:29:33.596473 DQ12 =108, DQ13 =108, DQ14 =106, DQ15 =110
5979 09:29:33.596889
5980 09:29:33.597214
5981 09:29:33.606941 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5982 09:29:33.607360 CH1 RK1: MR19=505, MR18=2F03
5983 09:29:33.613222 CH1_RK1: MR19=0x505, MR18=0x2F03, DQSOSC=407, MR23=63, INC=65, DEC=43
5984 09:29:33.616414 [RxdqsGatingPostProcess] freq 933
5985 09:29:33.623168 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 09:29:33.626396 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 09:29:33.629769 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 09:29:33.633288 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 09:29:33.636567 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 09:29:33.639745 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 09:29:33.640167 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 09:29:33.643378 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 09:29:33.646471 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 09:29:33.649687 Pre-setting of DQS Precalculation
5995 09:29:33.656413 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 09:29:33.663240 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 09:29:33.670007 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 09:29:33.670425
5999 09:29:33.670747
6000 09:29:33.673225 [Calibration Summary] 1866 Mbps
6001 09:29:33.673711 CH 0, Rank 0
6002 09:29:33.676340 SW Impedance : PASS
6003 09:29:33.679773 DUTY Scan : NO K
6004 09:29:33.680186 ZQ Calibration : PASS
6005 09:29:33.683190 Jitter Meter : NO K
6006 09:29:33.686590 CBT Training : PASS
6007 09:29:33.687084 Write leveling : PASS
6008 09:29:33.689701 RX DQS gating : PASS
6009 09:29:33.693265 RX DQ/DQS(RDDQC) : PASS
6010 09:29:33.693681 TX DQ/DQS : PASS
6011 09:29:33.696301 RX DATLAT : PASS
6012 09:29:33.699624 RX DQ/DQS(Engine): PASS
6013 09:29:33.700074 TX OE : NO K
6014 09:29:33.700406 All Pass.
6015 09:29:33.703043
6016 09:29:33.703455 CH 0, Rank 1
6017 09:29:33.706472 SW Impedance : PASS
6018 09:29:33.706885 DUTY Scan : NO K
6019 09:29:33.709677 ZQ Calibration : PASS
6020 09:29:33.710095 Jitter Meter : NO K
6021 09:29:33.713048 CBT Training : PASS
6022 09:29:33.716367 Write leveling : PASS
6023 09:29:33.716780 RX DQS gating : PASS
6024 09:29:33.719739 RX DQ/DQS(RDDQC) : PASS
6025 09:29:33.723230 TX DQ/DQS : PASS
6026 09:29:33.723821 RX DATLAT : PASS
6027 09:29:33.726403 RX DQ/DQS(Engine): PASS
6028 09:29:33.729624 TX OE : NO K
6029 09:29:33.730043 All Pass.
6030 09:29:33.730374
6031 09:29:33.730679 CH 1, Rank 0
6032 09:29:33.732889 SW Impedance : PASS
6033 09:29:33.736373 DUTY Scan : NO K
6034 09:29:33.736786 ZQ Calibration : PASS
6035 09:29:33.739628 Jitter Meter : NO K
6036 09:29:33.743018 CBT Training : PASS
6037 09:29:33.743430 Write leveling : PASS
6038 09:29:33.746443 RX DQS gating : PASS
6039 09:29:33.749711 RX DQ/DQS(RDDQC) : PASS
6040 09:29:33.750126 TX DQ/DQS : PASS
6041 09:29:33.752902 RX DATLAT : PASS
6042 09:29:33.756636 RX DQ/DQS(Engine): PASS
6043 09:29:33.757050 TX OE : NO K
6044 09:29:33.757381 All Pass.
6045 09:29:33.757682
6046 09:29:33.759456 CH 1, Rank 1
6047 09:29:33.759954 SW Impedance : PASS
6048 09:29:33.763154 DUTY Scan : NO K
6049 09:29:33.766402 ZQ Calibration : PASS
6050 09:29:33.766896 Jitter Meter : NO K
6051 09:29:33.769579 CBT Training : PASS
6052 09:29:33.772708 Write leveling : PASS
6053 09:29:33.773126 RX DQS gating : PASS
6054 09:29:33.776373 RX DQ/DQS(RDDQC) : PASS
6055 09:29:33.779708 TX DQ/DQS : PASS
6056 09:29:33.780138 RX DATLAT : PASS
6057 09:29:33.782893 RX DQ/DQS(Engine): PASS
6058 09:29:33.786117 TX OE : NO K
6059 09:29:33.786648 All Pass.
6060 09:29:33.787153
6061 09:29:33.787500 DramC Write-DBI off
6062 09:29:33.789497 PER_BANK_REFRESH: Hybrid Mode
6063 09:29:33.792831 TX_TRACKING: ON
6064 09:29:33.799375 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 09:29:33.802715 [FAST_K] Save calibration result to emmc
6066 09:29:33.809590 dramc_set_vcore_voltage set vcore to 650000
6067 09:29:33.810007 Read voltage for 400, 6
6068 09:29:33.812945 Vio18 = 0
6069 09:29:33.813359 Vcore = 650000
6070 09:29:33.813684 Vdram = 0
6071 09:29:33.813987 Vddq = 0
6072 09:29:33.816116 Vmddr = 0
6073 09:29:33.819677 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 09:29:33.826248 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 09:29:33.829500 MEM_TYPE=3, freq_sel=20
6076 09:29:33.829932 sv_algorithm_assistance_LP4_800
6077 09:29:33.836535 ============ PULL DRAM RESETB DOWN ============
6078 09:29:33.839516 ========== PULL DRAM RESETB DOWN end =========
6079 09:29:33.842822 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 09:29:33.846336 ===================================
6081 09:29:33.849722 LPDDR4 DRAM CONFIGURATION
6082 09:29:33.853027 ===================================
6083 09:29:33.856310 EX_ROW_EN[0] = 0x0
6084 09:29:33.856725 EX_ROW_EN[1] = 0x0
6085 09:29:33.859412 LP4Y_EN = 0x0
6086 09:29:33.859933 WORK_FSP = 0x0
6087 09:29:33.863362 WL = 0x2
6088 09:29:33.863823 RL = 0x2
6089 09:29:33.866563 BL = 0x2
6090 09:29:33.866977 RPST = 0x0
6091 09:29:33.869548 RD_PRE = 0x0
6092 09:29:33.869965 WR_PRE = 0x1
6093 09:29:33.872847 WR_PST = 0x0
6094 09:29:33.873267 DBI_WR = 0x0
6095 09:29:33.876104 DBI_RD = 0x0
6096 09:29:33.876522 OTF = 0x1
6097 09:29:33.879391 ===================================
6098 09:29:33.883445 ===================================
6099 09:29:33.886598 ANA top config
6100 09:29:33.889646 ===================================
6101 09:29:33.893203 DLL_ASYNC_EN = 0
6102 09:29:33.893678 ALL_SLAVE_EN = 1
6103 09:29:33.896182 NEW_RANK_MODE = 1
6104 09:29:33.899950 DLL_IDLE_MODE = 1
6105 09:29:33.902960 LP45_APHY_COMB_EN = 1
6106 09:29:33.903456 TX_ODT_DIS = 1
6107 09:29:33.906261 NEW_8X_MODE = 1
6108 09:29:33.910050 ===================================
6109 09:29:33.913350 ===================================
6110 09:29:33.916091 data_rate = 800
6111 09:29:33.919359 CKR = 1
6112 09:29:33.923342 DQ_P2S_RATIO = 4
6113 09:29:33.926714 ===================================
6114 09:29:33.929226 CA_P2S_RATIO = 4
6115 09:29:33.929661 DQ_CA_OPEN = 0
6116 09:29:33.932663 DQ_SEMI_OPEN = 1
6117 09:29:33.936600 CA_SEMI_OPEN = 1
6118 09:29:33.939237 CA_FULL_RATE = 0
6119 09:29:33.942984 DQ_CKDIV4_EN = 0
6120 09:29:33.946265 CA_CKDIV4_EN = 1
6121 09:29:33.946776 CA_PREDIV_EN = 0
6122 09:29:33.949354 PH8_DLY = 0
6123 09:29:33.952735 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 09:29:33.956203 DQ_AAMCK_DIV = 0
6125 09:29:33.959425 CA_AAMCK_DIV = 0
6126 09:29:33.962905 CA_ADMCK_DIV = 4
6127 09:29:33.963340 DQ_TRACK_CA_EN = 0
6128 09:29:33.966261 CA_PICK = 800
6129 09:29:33.969443 CA_MCKIO = 400
6130 09:29:33.972897 MCKIO_SEMI = 400
6131 09:29:33.976476 PLL_FREQ = 3016
6132 09:29:33.979806 DQ_UI_PI_RATIO = 32
6133 09:29:33.983010 CA_UI_PI_RATIO = 32
6134 09:29:33.986440 ===================================
6135 09:29:33.989723 ===================================
6136 09:29:33.990214 memory_type:LPDDR4
6137 09:29:33.992547 GP_NUM : 10
6138 09:29:33.996508 SRAM_EN : 1
6139 09:29:33.996926 MD32_EN : 0
6140 09:29:33.999689 ===================================
6141 09:29:34.002934 [ANA_INIT] >>>>>>>>>>>>>>
6142 09:29:34.006172 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 09:29:34.009254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 09:29:34.012702 ===================================
6145 09:29:34.015793 data_rate = 800,PCW = 0X7400
6146 09:29:34.016278 ===================================
6147 09:29:34.022664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 09:29:34.025704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 09:29:34.039128 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 09:29:34.042328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 09:29:34.045779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 09:29:34.049085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 09:29:34.052889 [ANA_INIT] flow start
6154 09:29:34.053303 [ANA_INIT] PLL >>>>>>>>
6155 09:29:34.055799 [ANA_INIT] PLL <<<<<<<<
6156 09:29:34.059115 [ANA_INIT] MIDPI >>>>>>>>
6157 09:29:34.062500 [ANA_INIT] MIDPI <<<<<<<<
6158 09:29:34.063115 [ANA_INIT] DLL >>>>>>>>
6159 09:29:34.065808 [ANA_INIT] flow end
6160 09:29:34.069261 ============ LP4 DIFF to SE enter ============
6161 09:29:34.072605 ============ LP4 DIFF to SE exit ============
6162 09:29:34.076270 [ANA_INIT] <<<<<<<<<<<<<
6163 09:29:34.079388 [Flow] Enable top DCM control >>>>>
6164 09:29:34.082794 [Flow] Enable top DCM control <<<<<
6165 09:29:34.086112 Enable DLL master slave shuffle
6166 09:29:34.089420 ==============================================================
6167 09:29:34.092584 Gating Mode config
6168 09:29:34.099283 ==============================================================
6169 09:29:34.099802 Config description:
6170 09:29:34.109024 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 09:29:34.115548 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 09:29:34.122226 SELPH_MODE 0: By rank 1: By Phase
6173 09:29:34.125624 ==============================================================
6174 09:29:34.128707 GAT_TRACK_EN = 0
6175 09:29:34.131890 RX_GATING_MODE = 2
6176 09:29:34.135201 RX_GATING_TRACK_MODE = 2
6177 09:29:34.138771 SELPH_MODE = 1
6178 09:29:34.141994 PICG_EARLY_EN = 1
6179 09:29:34.145047 VALID_LAT_VALUE = 1
6180 09:29:34.148482 ==============================================================
6181 09:29:34.151669 Enter into Gating configuration >>>>
6182 09:29:34.155802 Exit from Gating configuration <<<<
6183 09:29:34.158252 Enter into DVFS_PRE_config >>>>>
6184 09:29:34.172020 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 09:29:34.175447 Exit from DVFS_PRE_config <<<<<
6186 09:29:34.178538 Enter into PICG configuration >>>>
6187 09:29:34.181785 Exit from PICG configuration <<<<
6188 09:29:34.182237 [RX_INPUT] configuration >>>>>
6189 09:29:34.185022 [RX_INPUT] configuration <<<<<
6190 09:29:34.191917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 09:29:34.195293 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 09:29:34.201699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 09:29:34.208369 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 09:29:34.215255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 09:29:34.221676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 09:29:34.224884 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 09:29:34.228089 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 09:29:34.234805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 09:29:34.238642 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 09:29:34.241617 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 09:29:34.244877 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 09:29:34.248240 ===================================
6203 09:29:34.251759 LPDDR4 DRAM CONFIGURATION
6204 09:29:34.254604 ===================================
6205 09:29:34.258129 EX_ROW_EN[0] = 0x0
6206 09:29:34.258548 EX_ROW_EN[1] = 0x0
6207 09:29:34.261468 LP4Y_EN = 0x0
6208 09:29:34.261970 WORK_FSP = 0x0
6209 09:29:34.264683 WL = 0x2
6210 09:29:34.265146 RL = 0x2
6211 09:29:34.268202 BL = 0x2
6212 09:29:34.268621 RPST = 0x0
6213 09:29:34.271276 RD_PRE = 0x0
6214 09:29:34.271744 WR_PRE = 0x1
6215 09:29:34.274627 WR_PST = 0x0
6216 09:29:34.275047 DBI_WR = 0x0
6217 09:29:34.278022 DBI_RD = 0x0
6218 09:29:34.278443 OTF = 0x1
6219 09:29:34.281822 ===================================
6220 09:29:34.288309 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 09:29:34.291377 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 09:29:34.294916 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 09:29:34.297881 ===================================
6224 09:29:34.301025 LPDDR4 DRAM CONFIGURATION
6225 09:29:34.304391 ===================================
6226 09:29:34.307563 EX_ROW_EN[0] = 0x10
6227 09:29:34.308165 EX_ROW_EN[1] = 0x0
6228 09:29:34.310949 LP4Y_EN = 0x0
6229 09:29:34.311367 WORK_FSP = 0x0
6230 09:29:34.314314 WL = 0x2
6231 09:29:34.314727 RL = 0x2
6232 09:29:34.317402 BL = 0x2
6233 09:29:34.317825 RPST = 0x0
6234 09:29:34.321316 RD_PRE = 0x0
6235 09:29:34.321726 WR_PRE = 0x1
6236 09:29:34.324715 WR_PST = 0x0
6237 09:29:34.325213 DBI_WR = 0x0
6238 09:29:34.327464 DBI_RD = 0x0
6239 09:29:34.328075 OTF = 0x1
6240 09:29:34.330774 ===================================
6241 09:29:34.337735 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 09:29:34.342803 nWR fixed to 30
6243 09:29:34.345879 [ModeRegInit_LP4] CH0 RK0
6244 09:29:34.346299 [ModeRegInit_LP4] CH0 RK1
6245 09:29:34.349504 [ModeRegInit_LP4] CH1 RK0
6246 09:29:34.352365 [ModeRegInit_LP4] CH1 RK1
6247 09:29:34.352807 match AC timing 19
6248 09:29:34.358745 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 09:29:34.362599 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 09:29:34.365781 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 09:29:34.372242 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 09:29:34.376092 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 09:29:34.376517 ==
6254 09:29:34.379221 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 09:29:34.382575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 09:29:34.382997 ==
6257 09:29:34.389484 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 09:29:34.396242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 09:29:34.399410 [CA 0] Center 36 (8~64) winsize 57
6260 09:29:34.402637 [CA 1] Center 36 (8~64) winsize 57
6261 09:29:34.403057 [CA 2] Center 36 (8~64) winsize 57
6262 09:29:34.405979 [CA 3] Center 36 (8~64) winsize 57
6263 09:29:34.409115 [CA 4] Center 36 (8~64) winsize 57
6264 09:29:34.412445 [CA 5] Center 36 (8~64) winsize 57
6265 09:29:34.412884
6266 09:29:34.416077 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 09:29:34.416492
6268 09:29:34.422658 [CATrainingPosCal] consider 1 rank data
6269 09:29:34.423141 u2DelayCellTimex100 = 270/100 ps
6270 09:29:34.429103 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 09:29:34.432599 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 09:29:34.435789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 09:29:34.439046 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 09:29:34.442449 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 09:29:34.445679 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 09:29:34.446192
6277 09:29:34.448658 CA PerBit enable=1, Macro0, CA PI delay=36
6278 09:29:34.449080
6279 09:29:34.452680 [CBTSetCACLKResult] CA Dly = 36
6280 09:29:34.455850 CS Dly: 1 (0~32)
6281 09:29:34.456291 ==
6282 09:29:34.459239 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 09:29:34.462374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 09:29:34.462790 ==
6285 09:29:34.469127 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 09:29:34.471983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 09:29:34.475808 [CA 0] Center 36 (8~64) winsize 57
6288 09:29:34.478851 [CA 1] Center 36 (8~64) winsize 57
6289 09:29:34.482239 [CA 2] Center 36 (8~64) winsize 57
6290 09:29:34.485835 [CA 3] Center 36 (8~64) winsize 57
6291 09:29:34.489119 [CA 4] Center 36 (8~64) winsize 57
6292 09:29:34.492446 [CA 5] Center 36 (8~64) winsize 57
6293 09:29:34.492867
6294 09:29:34.495807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 09:29:34.496290
6296 09:29:34.498549 [CATrainingPosCal] consider 2 rank data
6297 09:29:34.502312 u2DelayCellTimex100 = 270/100 ps
6298 09:29:34.505416 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:29:34.508511 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 09:29:34.512239 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 09:29:34.518735 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 09:29:34.522425 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 09:29:34.525656 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 09:29:34.526075
6305 09:29:34.528887 CA PerBit enable=1, Macro0, CA PI delay=36
6306 09:29:34.529366
6307 09:29:34.531936 [CBTSetCACLKResult] CA Dly = 36
6308 09:29:34.532436 CS Dly: 1 (0~32)
6309 09:29:34.532771
6310 09:29:34.535687 ----->DramcWriteLeveling(PI) begin...
6311 09:29:34.536218 ==
6312 09:29:34.538801 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 09:29:34.545283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 09:29:34.545803 ==
6315 09:29:34.548696 Write leveling (Byte 0): 40 => 8
6316 09:29:34.549221 Write leveling (Byte 1): 40 => 8
6317 09:29:34.552550 DramcWriteLeveling(PI) end<-----
6318 09:29:34.553066
6319 09:29:34.553394 ==
6320 09:29:34.555717 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 09:29:34.562292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 09:29:34.562716 ==
6323 09:29:34.565701 [Gating] SW mode calibration
6324 09:29:34.571787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 09:29:34.575689 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 09:29:34.582207 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 09:29:34.585603 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 09:29:34.589007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 09:29:34.595824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 09:29:34.598676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 09:29:34.602001 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 09:29:34.608905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 09:29:34.612277 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 09:29:34.615718 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 09:29:34.618390 Total UI for P1: 0, mck2ui 16
6336 09:29:34.622000 best dqsien dly found for B0: ( 0, 14, 24)
6337 09:29:34.624916 Total UI for P1: 0, mck2ui 16
6338 09:29:34.628894 best dqsien dly found for B1: ( 0, 14, 24)
6339 09:29:34.632091 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 09:29:34.635261 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 09:29:34.635806
6342 09:29:34.638635 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 09:29:34.644832 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 09:29:34.645256 [Gating] SW calibration Done
6345 09:29:34.645586 ==
6346 09:29:34.648317 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 09:29:34.654997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 09:29:34.655465 ==
6349 09:29:34.655854 RX Vref Scan: 0
6350 09:29:34.656171
6351 09:29:34.658728 RX Vref 0 -> 0, step: 1
6352 09:29:34.659252
6353 09:29:34.661610 RX Delay -410 -> 252, step: 16
6354 09:29:34.665500 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6355 09:29:34.668253 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6356 09:29:34.674997 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6357 09:29:34.678345 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6358 09:29:34.681925 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6359 09:29:34.684960 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6360 09:29:34.691875 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6361 09:29:34.694774 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6362 09:29:34.698350 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6363 09:29:34.701452 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6364 09:29:34.708632 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6365 09:29:34.711964 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6366 09:29:34.715015 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6367 09:29:34.718048 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6368 09:29:34.725186 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6369 09:29:34.728324 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6370 09:29:34.728793 ==
6371 09:29:34.731557 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 09:29:34.735070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 09:29:34.735547 ==
6374 09:29:34.738345 DQS Delay:
6375 09:29:34.738810 DQS0 = 27, DQS1 = 35
6376 09:29:34.741612 DQM Delay:
6377 09:29:34.742060 DQM0 = 11, DQM1 = 11
6378 09:29:34.742363 DQ Delay:
6379 09:29:34.745039 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6380 09:29:34.748179 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6381 09:29:34.751629 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6382 09:29:34.755056 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6383 09:29:34.755468
6384 09:29:34.755834
6385 09:29:34.756137 ==
6386 09:29:34.758539 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 09:29:34.761714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 09:29:34.764673 ==
6389 09:29:34.765177
6390 09:29:34.765502
6391 09:29:34.765800 TX Vref Scan disable
6392 09:29:34.768342 == TX Byte 0 ==
6393 09:29:34.771701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 09:29:34.775123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 09:29:34.778537 == TX Byte 1 ==
6396 09:29:34.781741 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 09:29:34.784684 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 09:29:34.785206 ==
6399 09:29:34.787828 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 09:29:34.794905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 09:29:34.795417 ==
6402 09:29:34.795797
6403 09:29:34.796112
6404 09:29:34.796406 TX Vref Scan disable
6405 09:29:34.797890 == TX Byte 0 ==
6406 09:29:34.801156 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 09:29:34.804782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 09:29:34.808183 == TX Byte 1 ==
6409 09:29:34.811351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 09:29:34.814651 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 09:29:34.815158
6412 09:29:34.818246 [DATLAT]
6413 09:29:34.818659 Freq=400, CH0 RK0
6414 09:29:34.818986
6415 09:29:34.821269 DATLAT Default: 0xf
6416 09:29:34.821771 0, 0xFFFF, sum = 0
6417 09:29:34.824756 1, 0xFFFF, sum = 0
6418 09:29:34.825261 2, 0xFFFF, sum = 0
6419 09:29:34.827773 3, 0xFFFF, sum = 0
6420 09:29:34.828192 4, 0xFFFF, sum = 0
6421 09:29:34.830970 5, 0xFFFF, sum = 0
6422 09:29:34.831385 6, 0xFFFF, sum = 0
6423 09:29:34.834191 7, 0xFFFF, sum = 0
6424 09:29:34.834607 8, 0xFFFF, sum = 0
6425 09:29:34.837865 9, 0xFFFF, sum = 0
6426 09:29:34.838372 10, 0xFFFF, sum = 0
6427 09:29:34.841303 11, 0xFFFF, sum = 0
6428 09:29:34.844138 12, 0xFFFF, sum = 0
6429 09:29:34.844558 13, 0x0, sum = 1
6430 09:29:34.847846 14, 0x0, sum = 2
6431 09:29:34.848267 15, 0x0, sum = 3
6432 09:29:34.848602 16, 0x0, sum = 4
6433 09:29:34.851046 best_step = 14
6434 09:29:34.851632
6435 09:29:34.852015 ==
6436 09:29:34.854295 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 09:29:34.857862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 09:29:34.858358 ==
6439 09:29:34.860749 RX Vref Scan: 1
6440 09:29:34.861162
6441 09:29:34.861488 RX Vref 0 -> 0, step: 1
6442 09:29:34.864309
6443 09:29:34.864725 RX Delay -311 -> 252, step: 8
6444 09:29:34.865054
6445 09:29:34.867815 Set Vref, RX VrefLevel [Byte0]: 56
6446 09:29:34.870981 [Byte1]: 49
6447 09:29:34.875683
6448 09:29:34.876107 Final RX Vref Byte 0 = 56 to rank0
6449 09:29:34.879054 Final RX Vref Byte 1 = 49 to rank0
6450 09:29:34.882493 Final RX Vref Byte 0 = 56 to rank1
6451 09:29:34.886233 Final RX Vref Byte 1 = 49 to rank1==
6452 09:29:34.889595 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 09:29:34.895247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 09:29:34.895694 ==
6455 09:29:34.896053 DQS Delay:
6456 09:29:34.898693 DQS0 = 28, DQS1 = 36
6457 09:29:34.899116 DQM Delay:
6458 09:29:34.899440 DQM0 = 10, DQM1 = 12
6459 09:29:34.902047 DQ Delay:
6460 09:29:34.905348 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6461 09:29:34.905786 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6462 09:29:34.908655 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6463 09:29:34.912494 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6464 09:29:34.912912
6465 09:29:34.915314
6466 09:29:34.921918 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6467 09:29:34.925743 CH0 RK0: MR19=C0C, MR18=CBB8
6468 09:29:34.932143 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6469 09:29:34.932614 ==
6470 09:29:34.935570 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 09:29:34.939071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 09:29:34.939484 ==
6473 09:29:34.942451 [Gating] SW mode calibration
6474 09:29:34.949140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 09:29:34.952473 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 09:29:34.958581 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 09:29:34.962530 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 09:29:34.966060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 09:29:34.972350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 09:29:34.975671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 09:29:34.979240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 09:29:34.986066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 09:29:34.989160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 09:29:34.992366 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 09:29:34.995561 Total UI for P1: 0, mck2ui 16
6486 09:29:34.998854 best dqsien dly found for B0: ( 0, 14, 24)
6487 09:29:35.002374 Total UI for P1: 0, mck2ui 16
6488 09:29:35.005908 best dqsien dly found for B1: ( 0, 14, 24)
6489 09:29:35.009371 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 09:29:35.012410 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 09:29:35.012827
6492 09:29:35.019207 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 09:29:35.021989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 09:29:35.022445 [Gating] SW calibration Done
6495 09:29:35.025339 ==
6496 09:29:35.028638 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 09:29:35.032086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 09:29:35.032504 ==
6499 09:29:35.032832 RX Vref Scan: 0
6500 09:29:35.033138
6501 09:29:35.035440 RX Vref 0 -> 0, step: 1
6502 09:29:35.035885
6503 09:29:35.038692 RX Delay -410 -> 252, step: 16
6504 09:29:35.041889 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6505 09:29:35.045474 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6506 09:29:35.052057 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6507 09:29:35.055407 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6508 09:29:35.058854 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6509 09:29:35.065904 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6510 09:29:35.068799 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6511 09:29:35.072059 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6512 09:29:35.075141 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6513 09:29:35.078585 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6514 09:29:35.085124 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6515 09:29:35.088541 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6516 09:29:35.091394 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6517 09:29:35.098652 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6518 09:29:35.101534 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6519 09:29:35.105130 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6520 09:29:35.105669 ==
6521 09:29:35.108407 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 09:29:35.111520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 09:29:35.114798 ==
6524 09:29:35.115208 DQS Delay:
6525 09:29:35.115527 DQS0 = 27, DQS1 = 35
6526 09:29:35.118867 DQM Delay:
6527 09:29:35.119330 DQM0 = 11, DQM1 = 11
6528 09:29:35.121651 DQ Delay:
6529 09:29:35.122059 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6530 09:29:35.125416 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6531 09:29:35.128541 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6532 09:29:35.131582 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6533 09:29:35.132026
6534 09:29:35.132349
6535 09:29:35.132764 ==
6536 09:29:35.134900 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 09:29:35.141536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 09:29:35.141928 ==
6539 09:29:35.142323
6540 09:29:35.142694
6541 09:29:35.143094 TX Vref Scan disable
6542 09:29:35.144760 == TX Byte 0 ==
6543 09:29:35.148149 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6544 09:29:35.151417 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6545 09:29:35.155170 == TX Byte 1 ==
6546 09:29:35.158270 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6547 09:29:35.161669 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6548 09:29:35.165084 ==
6549 09:29:35.165464 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 09:29:35.171622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 09:29:35.172042 ==
6552 09:29:35.172345
6553 09:29:35.172625
6554 09:29:35.174355 TX Vref Scan disable
6555 09:29:35.174733 == TX Byte 0 ==
6556 09:29:35.177709 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6557 09:29:35.184644 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6558 09:29:35.185087 == TX Byte 1 ==
6559 09:29:35.188086 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6560 09:29:35.191557 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6561 09:29:35.194908
6562 09:29:35.195310 [DATLAT]
6563 09:29:35.195611 Freq=400, CH0 RK1
6564 09:29:35.195947
6565 09:29:35.197542 DATLAT Default: 0xe
6566 09:29:35.197919 0, 0xFFFF, sum = 0
6567 09:29:35.200840 1, 0xFFFF, sum = 0
6568 09:29:35.201228 2, 0xFFFF, sum = 0
6569 09:29:35.204644 3, 0xFFFF, sum = 0
6570 09:29:35.205031 4, 0xFFFF, sum = 0
6571 09:29:35.207781 5, 0xFFFF, sum = 0
6572 09:29:35.211468 6, 0xFFFF, sum = 0
6573 09:29:35.211891 7, 0xFFFF, sum = 0
6574 09:29:35.214308 8, 0xFFFF, sum = 0
6575 09:29:35.214692 9, 0xFFFF, sum = 0
6576 09:29:35.217590 10, 0xFFFF, sum = 0
6577 09:29:35.217981 11, 0xFFFF, sum = 0
6578 09:29:35.220926 12, 0xFFFF, sum = 0
6579 09:29:35.221290 13, 0x0, sum = 1
6580 09:29:35.224453 14, 0x0, sum = 2
6581 09:29:35.224836 15, 0x0, sum = 3
6582 09:29:35.227933 16, 0x0, sum = 4
6583 09:29:35.228319 best_step = 14
6584 09:29:35.228615
6585 09:29:35.228891 ==
6586 09:29:35.231244 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 09:29:35.234201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 09:29:35.234583 ==
6589 09:29:35.237512 RX Vref Scan: 0
6590 09:29:35.237987
6591 09:29:35.241172 RX Vref 0 -> 0, step: 1
6592 09:29:35.241641
6593 09:29:35.241940 RX Delay -311 -> 252, step: 8
6594 09:29:35.250024 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6595 09:29:35.253293 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6596 09:29:35.256639 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6597 09:29:35.259895 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6598 09:29:35.266426 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6599 09:29:35.269834 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6600 09:29:35.273503 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6601 09:29:35.276739 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6602 09:29:35.283472 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6603 09:29:35.287076 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6604 09:29:35.290500 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6605 09:29:35.293486 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6606 09:29:35.300144 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6607 09:29:35.303866 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6608 09:29:35.306472 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6609 09:29:35.310577 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6610 09:29:35.313593 ==
6611 09:29:35.317092 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 09:29:35.320571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 09:29:35.321085 ==
6614 09:29:35.321419 DQS Delay:
6615 09:29:35.323794 DQS0 = 24, DQS1 = 32
6616 09:29:35.324303 DQM Delay:
6617 09:29:35.326804 DQM0 = 8, DQM1 = 10
6618 09:29:35.327217 DQ Delay:
6619 09:29:35.330238 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6620 09:29:35.332988 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6621 09:29:35.336279 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6622 09:29:35.340059 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6623 09:29:35.340473
6624 09:29:35.340795
6625 09:29:35.346305 [DQSOSCAuto] RK1, (LSB)MR18= 0xc263, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6626 09:29:35.350193 CH0 RK1: MR19=C0C, MR18=C263
6627 09:29:35.356333 CH0_RK1: MR19=0xC0C, MR18=0xC263, DQSOSC=385, MR23=63, INC=398, DEC=265
6628 09:29:35.360001 [RxdqsGatingPostProcess] freq 400
6629 09:29:35.362853 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 09:29:35.366333 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 09:29:35.369555 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 09:29:35.372739 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 09:29:35.376689 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 09:29:35.379976 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 09:29:35.382682 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 09:29:35.386158 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 09:29:35.389572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 09:29:35.392945 Pre-setting of DQS Precalculation
6639 09:29:35.396395 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 09:29:35.396805 ==
6641 09:29:35.399587 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 09:29:35.406096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 09:29:35.406564 ==
6644 09:29:35.409647 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 09:29:35.415911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6646 09:29:35.419394 [CA 0] Center 36 (8~64) winsize 57
6647 09:29:35.422867 [CA 1] Center 36 (8~64) winsize 57
6648 09:29:35.426167 [CA 2] Center 36 (8~64) winsize 57
6649 09:29:35.429102 [CA 3] Center 36 (8~64) winsize 57
6650 09:29:35.432522 [CA 4] Center 36 (8~64) winsize 57
6651 09:29:35.435832 [CA 5] Center 36 (8~64) winsize 57
6652 09:29:35.436063
6653 09:29:35.439277 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6654 09:29:35.439507
6655 09:29:35.442963 [CATrainingPosCal] consider 1 rank data
6656 09:29:35.445828 u2DelayCellTimex100 = 270/100 ps
6657 09:29:35.449172 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 09:29:35.452622 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 09:29:35.455941 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 09:29:35.458886 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 09:29:35.462239 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 09:29:35.465670 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 09:29:35.465890
6664 09:29:35.472357 CA PerBit enable=1, Macro0, CA PI delay=36
6665 09:29:35.472578
6666 09:29:35.475944 [CBTSetCACLKResult] CA Dly = 36
6667 09:29:35.476165 CS Dly: 1 (0~32)
6668 09:29:35.476444 ==
6669 09:29:35.479353 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 09:29:35.482280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 09:29:35.482591 ==
6672 09:29:35.489043 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 09:29:35.495913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 09:29:35.499173 [CA 0] Center 36 (8~64) winsize 57
6675 09:29:35.502760 [CA 1] Center 36 (8~64) winsize 57
6676 09:29:35.506013 [CA 2] Center 36 (8~64) winsize 57
6677 09:29:35.506235 [CA 3] Center 36 (8~64) winsize 57
6678 09:29:35.509074 [CA 4] Center 36 (8~64) winsize 57
6679 09:29:35.512587 [CA 5] Center 36 (8~64) winsize 57
6680 09:29:35.512900
6681 09:29:35.519275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 09:29:35.519495
6683 09:29:35.522662 [CATrainingPosCal] consider 2 rank data
6684 09:29:35.522910 u2DelayCellTimex100 = 270/100 ps
6685 09:29:35.529637 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:29:35.532937 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 09:29:35.536390 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 09:29:35.539176 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 09:29:35.542401 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 09:29:35.545886 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 09:29:35.546120
6692 09:29:35.549149 CA PerBit enable=1, Macro0, CA PI delay=36
6693 09:29:35.549382
6694 09:29:35.552208 [CBTSetCACLKResult] CA Dly = 36
6695 09:29:35.556021 CS Dly: 1 (0~32)
6696 09:29:35.556253
6697 09:29:35.559481 ----->DramcWriteLeveling(PI) begin...
6698 09:29:35.559733 ==
6699 09:29:35.562234 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 09:29:35.565776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 09:29:35.566009 ==
6702 09:29:35.569051 Write leveling (Byte 0): 40 => 8
6703 09:29:35.572442 Write leveling (Byte 1): 40 => 8
6704 09:29:35.575853 DramcWriteLeveling(PI) end<-----
6705 09:29:35.576101
6706 09:29:35.576335 ==
6707 09:29:35.579277 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 09:29:35.582478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 09:29:35.582713 ==
6710 09:29:35.585679 [Gating] SW mode calibration
6711 09:29:35.592685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 09:29:35.599173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 09:29:35.602422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 09:29:35.605683 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 09:29:35.612429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 09:29:35.615484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 09:29:35.619180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 09:29:35.625328 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 09:29:35.628871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 09:29:35.632420 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 09:29:35.638848 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 09:29:35.639038 Total UI for P1: 0, mck2ui 16
6723 09:29:35.645101 best dqsien dly found for B0: ( 0, 14, 24)
6724 09:29:35.645289 Total UI for P1: 0, mck2ui 16
6725 09:29:35.652023 best dqsien dly found for B1: ( 0, 14, 24)
6726 09:29:35.655343 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 09:29:35.658531 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 09:29:35.658775
6729 09:29:35.662294 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 09:29:35.665564 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 09:29:35.668935 [Gating] SW calibration Done
6732 09:29:35.669122 ==
6733 09:29:35.672240 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 09:29:35.675557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 09:29:35.675819 ==
6736 09:29:35.678405 RX Vref Scan: 0
6737 09:29:35.678638
6738 09:29:35.678836 RX Vref 0 -> 0, step: 1
6739 09:29:35.679041
6740 09:29:35.681926 RX Delay -410 -> 252, step: 16
6741 09:29:35.688828 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6742 09:29:35.692219 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6743 09:29:35.695370 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6744 09:29:35.698752 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6745 09:29:35.702084 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6746 09:29:35.708621 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6747 09:29:35.712112 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6748 09:29:35.715173 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6749 09:29:35.718526 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6750 09:29:35.725169 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6751 09:29:35.728752 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6752 09:29:35.731930 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6753 09:29:35.735249 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6754 09:29:35.741691 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6755 09:29:35.745307 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6756 09:29:35.748442 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6757 09:29:35.748620 ==
6758 09:29:35.751894 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 09:29:35.758447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 09:29:35.758637 ==
6761 09:29:35.758828 DQS Delay:
6762 09:29:35.761987 DQS0 = 35, DQS1 = 35
6763 09:29:35.762387 DQM Delay:
6764 09:29:35.762790 DQM0 = 18, DQM1 = 13
6765 09:29:35.765890 DQ Delay:
6766 09:29:35.768603 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6767 09:29:35.772378 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6768 09:29:35.772783 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6769 09:29:35.778922 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6770 09:29:35.779447
6771 09:29:35.779867
6772 09:29:35.780197 ==
6773 09:29:35.782442 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 09:29:35.785809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 09:29:35.786189 ==
6776 09:29:35.786485
6777 09:29:35.786757
6778 09:29:35.789181 TX Vref Scan disable
6779 09:29:35.789660 == TX Byte 0 ==
6780 09:29:35.792550 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 09:29:35.799230 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 09:29:35.799835 == TX Byte 1 ==
6783 09:29:35.802055 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 09:29:35.808760 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 09:29:35.809308 ==
6786 09:29:35.811892 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 09:29:35.815414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 09:29:35.815937 ==
6789 09:29:35.816426
6790 09:29:35.816855
6791 09:29:35.818595 TX Vref Scan disable
6792 09:29:35.818963 == TX Byte 0 ==
6793 09:29:35.822038 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 09:29:35.828767 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 09:29:35.829198 == TX Byte 1 ==
6796 09:29:35.832217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 09:29:35.838798 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 09:29:35.839350
6799 09:29:35.839828 [DATLAT]
6800 09:29:35.840292 Freq=400, CH1 RK0
6801 09:29:35.841968
6802 09:29:35.842429 DATLAT Default: 0xf
6803 09:29:35.845502 0, 0xFFFF, sum = 0
6804 09:29:35.845885 1, 0xFFFF, sum = 0
6805 09:29:35.849240 2, 0xFFFF, sum = 0
6806 09:29:35.849724 3, 0xFFFF, sum = 0
6807 09:29:35.852168 4, 0xFFFF, sum = 0
6808 09:29:35.852554 5, 0xFFFF, sum = 0
6809 09:29:35.855473 6, 0xFFFF, sum = 0
6810 09:29:35.855938 7, 0xFFFF, sum = 0
6811 09:29:35.858673 8, 0xFFFF, sum = 0
6812 09:29:35.859055 9, 0xFFFF, sum = 0
6813 09:29:35.862317 10, 0xFFFF, sum = 0
6814 09:29:35.862699 11, 0xFFFF, sum = 0
6815 09:29:35.865202 12, 0xFFFF, sum = 0
6816 09:29:35.865685 13, 0x0, sum = 1
6817 09:29:35.868545 14, 0x0, sum = 2
6818 09:29:35.869002 15, 0x0, sum = 3
6819 09:29:35.872059 16, 0x0, sum = 4
6820 09:29:35.872609 best_step = 14
6821 09:29:35.872930
6822 09:29:35.873210 ==
6823 09:29:35.875463 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 09:29:35.882348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 09:29:35.882727 ==
6826 09:29:35.883025 RX Vref Scan: 1
6827 09:29:35.883297
6828 09:29:35.885425 RX Vref 0 -> 0, step: 1
6829 09:29:35.885814
6830 09:29:35.889186 RX Delay -311 -> 252, step: 8
6831 09:29:35.889666
6832 09:29:35.892268 Set Vref, RX VrefLevel [Byte0]: 55
6833 09:29:35.895520 [Byte1]: 51
6834 09:29:35.896060
6835 09:29:35.899094 Final RX Vref Byte 0 = 55 to rank0
6836 09:29:35.902409 Final RX Vref Byte 1 = 51 to rank0
6837 09:29:35.905873 Final RX Vref Byte 0 = 55 to rank1
6838 09:29:35.908591 Final RX Vref Byte 1 = 51 to rank1==
6839 09:29:35.911943 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 09:29:35.915521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 09:29:35.915980 ==
6842 09:29:35.918686 DQS Delay:
6843 09:29:35.919062 DQS0 = 28, DQS1 = 32
6844 09:29:35.922041 DQM Delay:
6845 09:29:35.922417 DQM0 = 10, DQM1 = 10
6846 09:29:35.922716 DQ Delay:
6847 09:29:35.925247 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6848 09:29:35.928637 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6849 09:29:35.932050 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6850 09:29:35.935357 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6851 09:29:35.935905
6852 09:29:35.936241
6853 09:29:35.945255 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6854 09:29:35.945816 CH1 RK0: MR19=C0C, MR18=94CC
6855 09:29:35.951541 CH1_RK0: MR19=0xC0C, MR18=0x94CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6856 09:29:35.952109 ==
6857 09:29:35.954593 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 09:29:35.961660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 09:29:35.962090 ==
6860 09:29:35.964956 [Gating] SW mode calibration
6861 09:29:35.971621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 09:29:35.975113 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 09:29:35.981539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 09:29:35.985407 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 09:29:35.988194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 09:29:35.994528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 09:29:35.998158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 09:29:36.001597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 09:29:36.008328 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 09:29:36.011799 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 09:29:36.014491 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 09:29:36.017992 Total UI for P1: 0, mck2ui 16
6873 09:29:36.021082 best dqsien dly found for B0: ( 0, 14, 24)
6874 09:29:36.024765 Total UI for P1: 0, mck2ui 16
6875 09:29:36.027672 best dqsien dly found for B1: ( 0, 14, 24)
6876 09:29:36.031152 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 09:29:36.034577 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 09:29:36.034954
6879 09:29:36.041042 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 09:29:36.044540 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 09:29:36.044933 [Gating] SW calibration Done
6882 09:29:36.047849 ==
6883 09:29:36.051595 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 09:29:36.053932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 09:29:36.054317 ==
6886 09:29:36.054617 RX Vref Scan: 0
6887 09:29:36.054893
6888 09:29:36.057169 RX Vref 0 -> 0, step: 1
6889 09:29:36.057545
6890 09:29:36.060822 RX Delay -410 -> 252, step: 16
6891 09:29:36.063696 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6892 09:29:36.070808 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6893 09:29:36.074221 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6894 09:29:36.077537 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6895 09:29:36.080692 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6896 09:29:36.087477 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6897 09:29:36.090874 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6898 09:29:36.094308 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6899 09:29:36.097508 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6900 09:29:36.100671 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6901 09:29:36.107719 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6902 09:29:36.110419 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6903 09:29:36.113906 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6904 09:29:36.120621 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6905 09:29:36.123709 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6906 09:29:36.127030 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6907 09:29:36.127404 ==
6908 09:29:36.130732 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 09:29:36.133640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 09:29:36.137788 ==
6911 09:29:36.138281 DQS Delay:
6912 09:29:36.138584 DQS0 = 35, DQS1 = 35
6913 09:29:36.140349 DQM Delay:
6914 09:29:36.140723 DQM0 = 19, DQM1 = 14
6915 09:29:36.143733 DQ Delay:
6916 09:29:36.144109 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6917 09:29:36.147422 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6918 09:29:36.150444 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6919 09:29:36.153738 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6920 09:29:36.154171
6921 09:29:36.154506
6922 09:29:36.154808 ==
6923 09:29:36.157240 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 09:29:36.164009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 09:29:36.164457 ==
6926 09:29:36.164919
6927 09:29:36.165231
6928 09:29:36.165526 TX Vref Scan disable
6929 09:29:36.167431 == TX Byte 0 ==
6930 09:29:36.170886 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6931 09:29:36.174166 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6932 09:29:36.177417 == TX Byte 1 ==
6933 09:29:36.180713 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6934 09:29:36.183697 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6935 09:29:36.184140 ==
6936 09:29:36.187779 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 09:29:36.193757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 09:29:36.194233 ==
6939 09:29:36.194558
6940 09:29:36.194924
6941 09:29:36.197239 TX Vref Scan disable
6942 09:29:36.197794 == TX Byte 0 ==
6943 09:29:36.200503 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6944 09:29:36.203994 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6945 09:29:36.207252 == TX Byte 1 ==
6946 09:29:36.210483 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6947 09:29:36.213788 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6948 09:29:36.214227
6949 09:29:36.217049 [DATLAT]
6950 09:29:36.217474 Freq=400, CH1 RK1
6951 09:29:36.217797
6952 09:29:36.220430 DATLAT Default: 0xe
6953 09:29:36.220842 0, 0xFFFF, sum = 0
6954 09:29:36.224154 1, 0xFFFF, sum = 0
6955 09:29:36.224608 2, 0xFFFF, sum = 0
6956 09:29:36.227245 3, 0xFFFF, sum = 0
6957 09:29:36.227860 4, 0xFFFF, sum = 0
6958 09:29:36.231003 5, 0xFFFF, sum = 0
6959 09:29:36.231626 6, 0xFFFF, sum = 0
6960 09:29:36.233870 7, 0xFFFF, sum = 0
6961 09:29:36.234333 8, 0xFFFF, sum = 0
6962 09:29:36.237814 9, 0xFFFF, sum = 0
6963 09:29:36.240816 10, 0xFFFF, sum = 0
6964 09:29:36.241285 11, 0xFFFF, sum = 0
6965 09:29:36.243797 12, 0xFFFF, sum = 0
6966 09:29:36.244216 13, 0x0, sum = 1
6967 09:29:36.247444 14, 0x0, sum = 2
6968 09:29:36.248026 15, 0x0, sum = 3
6969 09:29:36.248520 16, 0x0, sum = 4
6970 09:29:36.250436 best_step = 14
6971 09:29:36.250878
6972 09:29:36.251202 ==
6973 09:29:36.254399 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 09:29:36.257565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 09:29:36.258017 ==
6976 09:29:36.260414 RX Vref Scan: 0
6977 09:29:36.260857
6978 09:29:36.261186 RX Vref 0 -> 0, step: 1
6979 09:29:36.264024
6980 09:29:36.264478 RX Delay -311 -> 252, step: 8
6981 09:29:36.272210 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6982 09:29:36.275618 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6983 09:29:36.278655 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6984 09:29:36.282228 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6985 09:29:36.288830 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6986 09:29:36.292030 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6987 09:29:36.295483 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6988 09:29:36.298890 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6989 09:29:36.305804 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6990 09:29:36.309197 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6991 09:29:36.312727 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6992 09:29:36.315955 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6993 09:29:36.322623 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6994 09:29:36.325767 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6995 09:29:36.329159 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6996 09:29:36.332528 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6997 09:29:36.336031 ==
6998 09:29:36.336511 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 09:29:36.342575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 09:29:36.342990 ==
7001 09:29:36.343313 DQS Delay:
7002 09:29:36.345950 DQS0 = 32, DQS1 = 36
7003 09:29:36.346457 DQM Delay:
7004 09:29:36.348792 DQM0 = 14, DQM1 = 14
7005 09:29:36.349202 DQ Delay:
7006 09:29:36.352336 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7007 09:29:36.355331 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =16
7008 09:29:36.358455 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7009 09:29:36.362087 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7010 09:29:36.362591
7011 09:29:36.362958
7012 09:29:36.368714 [DQSOSCAuto] RK1, (LSB)MR18= 0xc95b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7013 09:29:36.372255 CH1 RK1: MR19=C0C, MR18=C95B
7014 09:29:36.378631 CH1_RK1: MR19=0xC0C, MR18=0xC95B, DQSOSC=384, MR23=63, INC=400, DEC=267
7015 09:29:36.381895 [RxdqsGatingPostProcess] freq 400
7016 09:29:36.385319 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 09:29:36.388694 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 09:29:36.391986 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 09:29:36.395511 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 09:29:36.398579 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 09:29:36.401664 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 09:29:36.405187 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 09:29:36.408570 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 09:29:36.411868 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 09:29:36.415240 Pre-setting of DQS Precalculation
7026 09:29:36.418364 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 09:29:36.428486 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 09:29:36.435187 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 09:29:36.435694
7030 09:29:36.436023
7031 09:29:36.438441 [Calibration Summary] 800 Mbps
7032 09:29:36.439094 CH 0, Rank 0
7033 09:29:36.441752 SW Impedance : PASS
7034 09:29:36.442402 DUTY Scan : NO K
7035 09:29:36.444936 ZQ Calibration : PASS
7036 09:29:36.448333 Jitter Meter : NO K
7037 09:29:36.448761 CBT Training : PASS
7038 09:29:36.451753 Write leveling : PASS
7039 09:29:36.454969 RX DQS gating : PASS
7040 09:29:36.455492 RX DQ/DQS(RDDQC) : PASS
7041 09:29:36.458378 TX DQ/DQS : PASS
7042 09:29:36.461623 RX DATLAT : PASS
7043 09:29:36.462374 RX DQ/DQS(Engine): PASS
7044 09:29:36.464828 TX OE : NO K
7045 09:29:36.465561 All Pass.
7046 09:29:36.466231
7047 09:29:36.468474 CH 0, Rank 1
7048 09:29:36.469190 SW Impedance : PASS
7049 09:29:36.471562 DUTY Scan : NO K
7050 09:29:36.474671 ZQ Calibration : PASS
7051 09:29:36.474952 Jitter Meter : NO K
7052 09:29:36.477873 CBT Training : PASS
7053 09:29:36.478131 Write leveling : NO K
7054 09:29:36.481750 RX DQS gating : PASS
7055 09:29:36.485168 RX DQ/DQS(RDDQC) : PASS
7056 09:29:36.485469 TX DQ/DQS : PASS
7057 09:29:36.488407 RX DATLAT : PASS
7058 09:29:36.491590 RX DQ/DQS(Engine): PASS
7059 09:29:36.491937 TX OE : NO K
7060 09:29:36.494511 All Pass.
7061 09:29:36.494729
7062 09:29:36.494902 CH 1, Rank 0
7063 09:29:36.498045 SW Impedance : PASS
7064 09:29:36.498265 DUTY Scan : NO K
7065 09:29:36.501558 ZQ Calibration : PASS
7066 09:29:36.504393 Jitter Meter : NO K
7067 09:29:36.504614 CBT Training : PASS
7068 09:29:36.507735 Write leveling : PASS
7069 09:29:36.511187 RX DQS gating : PASS
7070 09:29:36.511453 RX DQ/DQS(RDDQC) : PASS
7071 09:29:36.514361 TX DQ/DQS : PASS
7072 09:29:36.517938 RX DATLAT : PASS
7073 09:29:36.518158 RX DQ/DQS(Engine): PASS
7074 09:29:36.521331 TX OE : NO K
7075 09:29:36.521553 All Pass.
7076 09:29:36.521725
7077 09:29:36.524442 CH 1, Rank 1
7078 09:29:36.524661 SW Impedance : PASS
7079 09:29:36.527794 DUTY Scan : NO K
7080 09:29:36.528065 ZQ Calibration : PASS
7081 09:29:36.531200 Jitter Meter : NO K
7082 09:29:36.534883 CBT Training : PASS
7083 09:29:36.535403 Write leveling : NO K
7084 09:29:36.538197 RX DQS gating : PASS
7085 09:29:36.541467 RX DQ/DQS(RDDQC) : PASS
7086 09:29:36.541877 TX DQ/DQS : PASS
7087 09:29:36.544932 RX DATLAT : PASS
7088 09:29:36.548238 RX DQ/DQS(Engine): PASS
7089 09:29:36.548649 TX OE : NO K
7090 09:29:36.551505 All Pass.
7091 09:29:36.552030
7092 09:29:36.552357 DramC Write-DBI off
7093 09:29:36.554917 PER_BANK_REFRESH: Hybrid Mode
7094 09:29:36.555327 TX_TRACKING: ON
7095 09:29:36.565034 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 09:29:36.568206 [FAST_K] Save calibration result to emmc
7097 09:29:36.571773 dramc_set_vcore_voltage set vcore to 725000
7098 09:29:36.574828 Read voltage for 1600, 0
7099 09:29:36.575245 Vio18 = 0
7100 09:29:36.577946 Vcore = 725000
7101 09:29:36.578355 Vdram = 0
7102 09:29:36.578678 Vddq = 0
7103 09:29:36.581349 Vmddr = 0
7104 09:29:36.584610 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 09:29:36.591192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 09:29:36.591739 MEM_TYPE=3, freq_sel=13
7107 09:29:36.594544 sv_algorithm_assistance_LP4_3733
7108 09:29:36.601256 ============ PULL DRAM RESETB DOWN ============
7109 09:29:36.604669 ========== PULL DRAM RESETB DOWN end =========
7110 09:29:36.608023 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 09:29:36.611050 ===================================
7112 09:29:36.614452 LPDDR4 DRAM CONFIGURATION
7113 09:29:36.617566 ===================================
7114 09:29:36.621258 EX_ROW_EN[0] = 0x0
7115 09:29:36.621671 EX_ROW_EN[1] = 0x0
7116 09:29:36.624214 LP4Y_EN = 0x0
7117 09:29:36.624715 WORK_FSP = 0x1
7118 09:29:36.627778 WL = 0x5
7119 09:29:36.628203 RL = 0x5
7120 09:29:36.630847 BL = 0x2
7121 09:29:36.631311 RPST = 0x0
7122 09:29:36.634587 RD_PRE = 0x0
7123 09:29:36.635000 WR_PRE = 0x1
7124 09:29:36.637641 WR_PST = 0x1
7125 09:29:36.638052 DBI_WR = 0x0
7126 09:29:36.641040 DBI_RD = 0x0
7127 09:29:36.641467 OTF = 0x1
7128 09:29:36.644204 ===================================
7129 09:29:36.647391 ===================================
7130 09:29:36.650883 ANA top config
7131 09:29:36.654177 ===================================
7132 09:29:36.654629 DLL_ASYNC_EN = 0
7133 09:29:36.657547 ALL_SLAVE_EN = 0
7134 09:29:36.661036 NEW_RANK_MODE = 1
7135 09:29:36.664296 DLL_IDLE_MODE = 1
7136 09:29:36.667551 LP45_APHY_COMB_EN = 1
7137 09:29:36.667973 TX_ODT_DIS = 0
7138 09:29:36.670884 NEW_8X_MODE = 1
7139 09:29:36.674070 ===================================
7140 09:29:36.677321 ===================================
7141 09:29:36.680443 data_rate = 3200
7142 09:29:36.683758 CKR = 1
7143 09:29:36.687381 DQ_P2S_RATIO = 8
7144 09:29:36.690490 ===================================
7145 09:29:36.694510 CA_P2S_RATIO = 8
7146 09:29:36.694996 DQ_CA_OPEN = 0
7147 09:29:36.697502 DQ_SEMI_OPEN = 0
7148 09:29:36.700957 CA_SEMI_OPEN = 0
7149 09:29:36.704178 CA_FULL_RATE = 0
7150 09:29:36.707403 DQ_CKDIV4_EN = 0
7151 09:29:36.707872 CA_CKDIV4_EN = 0
7152 09:29:36.710859 CA_PREDIV_EN = 0
7153 09:29:36.714135 PH8_DLY = 12
7154 09:29:36.717174 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 09:29:36.720627 DQ_AAMCK_DIV = 4
7156 09:29:36.723941 CA_AAMCK_DIV = 4
7157 09:29:36.724357 CA_ADMCK_DIV = 4
7158 09:29:36.727262 DQ_TRACK_CA_EN = 0
7159 09:29:36.730582 CA_PICK = 1600
7160 09:29:36.733886 CA_MCKIO = 1600
7161 09:29:36.737154 MCKIO_SEMI = 0
7162 09:29:36.740863 PLL_FREQ = 3068
7163 09:29:36.744137 DQ_UI_PI_RATIO = 32
7164 09:29:36.747310 CA_UI_PI_RATIO = 0
7165 09:29:36.750681 ===================================
7166 09:29:36.751168 ===================================
7167 09:29:36.754303 memory_type:LPDDR4
7168 09:29:36.757150 GP_NUM : 10
7169 09:29:36.757563 SRAM_EN : 1
7170 09:29:36.761123 MD32_EN : 0
7171 09:29:36.764320 ===================================
7172 09:29:36.767523 [ANA_INIT] >>>>>>>>>>>>>>
7173 09:29:36.770852 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 09:29:36.774186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 09:29:36.777505 ===================================
7176 09:29:36.778019 data_rate = 3200,PCW = 0X7600
7177 09:29:36.780872 ===================================
7178 09:29:36.784217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 09:29:36.790772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 09:29:36.797317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 09:29:36.801142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 09:29:36.804334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 09:29:36.807706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 09:29:36.810880 [ANA_INIT] flow start
7185 09:29:36.811453 [ANA_INIT] PLL >>>>>>>>
7186 09:29:36.814614 [ANA_INIT] PLL <<<<<<<<
7187 09:29:36.817697 [ANA_INIT] MIDPI >>>>>>>>
7188 09:29:36.820936 [ANA_INIT] MIDPI <<<<<<<<
7189 09:29:36.821350 [ANA_INIT] DLL >>>>>>>>
7190 09:29:36.824100 [ANA_INIT] DLL <<<<<<<<
7191 09:29:36.827632 [ANA_INIT] flow end
7192 09:29:36.830706 ============ LP4 DIFF to SE enter ============
7193 09:29:36.833694 ============ LP4 DIFF to SE exit ============
7194 09:29:36.837053 [ANA_INIT] <<<<<<<<<<<<<
7195 09:29:36.840399 [Flow] Enable top DCM control >>>>>
7196 09:29:36.844055 [Flow] Enable top DCM control <<<<<
7197 09:29:36.847066 Enable DLL master slave shuffle
7198 09:29:36.850623 ==============================================================
7199 09:29:36.854642 Gating Mode config
7200 09:29:36.857007 ==============================================================
7201 09:29:36.860372 Config description:
7202 09:29:36.870681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 09:29:36.877238 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 09:29:36.880574 SELPH_MODE 0: By rank 1: By Phase
7205 09:29:36.886997 ==============================================================
7206 09:29:36.890676 GAT_TRACK_EN = 1
7207 09:29:36.893680 RX_GATING_MODE = 2
7208 09:29:36.897121 RX_GATING_TRACK_MODE = 2
7209 09:29:36.900528 SELPH_MODE = 1
7210 09:29:36.903727 PICG_EARLY_EN = 1
7211 09:29:36.904145 VALID_LAT_VALUE = 1
7212 09:29:36.910153 ==============================================================
7213 09:29:36.913903 Enter into Gating configuration >>>>
7214 09:29:36.916684 Exit from Gating configuration <<<<
7215 09:29:36.920831 Enter into DVFS_PRE_config >>>>>
7216 09:29:36.930582 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 09:29:36.933903 Exit from DVFS_PRE_config <<<<<
7218 09:29:36.937493 Enter into PICG configuration >>>>
7219 09:29:36.940559 Exit from PICG configuration <<<<
7220 09:29:36.944166 [RX_INPUT] configuration >>>>>
7221 09:29:36.946973 [RX_INPUT] configuration <<<<<
7222 09:29:36.953794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 09:29:36.957236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 09:29:36.963847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 09:29:36.970674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 09:29:36.976853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 09:29:36.983402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 09:29:36.986622 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 09:29:36.990379 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 09:29:36.993793 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 09:29:36.996823 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 09:29:37.003312 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 09:29:37.006824 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 09:29:37.010373 ===================================
7235 09:29:37.013153 LPDDR4 DRAM CONFIGURATION
7236 09:29:37.017076 ===================================
7237 09:29:37.017496 EX_ROW_EN[0] = 0x0
7238 09:29:37.020202 EX_ROW_EN[1] = 0x0
7239 09:29:37.020588 LP4Y_EN = 0x0
7240 09:29:37.023541 WORK_FSP = 0x1
7241 09:29:37.023957 WL = 0x5
7242 09:29:37.026825 RL = 0x5
7243 09:29:37.027222 BL = 0x2
7244 09:29:37.030066 RPST = 0x0
7245 09:29:37.033404 RD_PRE = 0x0
7246 09:29:37.033820 WR_PRE = 0x1
7247 09:29:37.036536 WR_PST = 0x1
7248 09:29:37.036923 DBI_WR = 0x0
7249 09:29:37.040226 DBI_RD = 0x0
7250 09:29:37.040712 OTF = 0x1
7251 09:29:37.043116 ===================================
7252 09:29:37.046760 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 09:29:37.053531 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 09:29:37.056116 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 09:29:37.060135 ===================================
7256 09:29:37.063952 LPDDR4 DRAM CONFIGURATION
7257 09:29:37.066235 ===================================
7258 09:29:37.066625 EX_ROW_EN[0] = 0x10
7259 09:29:37.069871 EX_ROW_EN[1] = 0x0
7260 09:29:37.070361 LP4Y_EN = 0x0
7261 09:29:37.073357 WORK_FSP = 0x1
7262 09:29:37.073741 WL = 0x5
7263 09:29:37.076586 RL = 0x5
7264 09:29:37.076971 BL = 0x2
7265 09:29:37.079889 RPST = 0x0
7266 09:29:37.080275 RD_PRE = 0x0
7267 09:29:37.083116 WR_PRE = 0x1
7268 09:29:37.086549 WR_PST = 0x1
7269 09:29:37.086936 DBI_WR = 0x0
7270 09:29:37.089994 DBI_RD = 0x0
7271 09:29:37.090479 OTF = 0x1
7272 09:29:37.092716 ===================================
7273 09:29:37.099449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 09:29:37.099911 ==
7275 09:29:37.102518 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 09:29:37.106601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 09:29:37.106986 ==
7278 09:29:37.109751 [Duty_Offset_Calibration]
7279 09:29:37.110185 B0:2 B1:1 CA:1
7280 09:29:37.113087
7281 09:29:37.113469 [DutyScan_Calibration_Flow] k_type=0
7282 09:29:37.124482
7283 09:29:37.124889 ==CLK 0==
7284 09:29:37.127689 Final CLK duty delay cell = 0
7285 09:29:37.131216 [0] MAX Duty = 5187%(X100), DQS PI = 24
7286 09:29:37.134561 [0] MIN Duty = 4907%(X100), DQS PI = 0
7287 09:29:37.135032 [0] AVG Duty = 5047%(X100)
7288 09:29:37.137977
7289 09:29:37.138498 CH0 CLK Duty spec in!! Max-Min= 280%
7290 09:29:37.144178 [DutyScan_Calibration_Flow] ====Done====
7291 09:29:37.144584
7292 09:29:37.147440 [DutyScan_Calibration_Flow] k_type=1
7293 09:29:37.163522
7294 09:29:37.164023 ==DQS 0 ==
7295 09:29:37.166952 Final DQS duty delay cell = -4
7296 09:29:37.170575 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7297 09:29:37.173653 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7298 09:29:37.176725 [-4] AVG Duty = 4891%(X100)
7299 09:29:37.177108
7300 09:29:37.177410 ==DQS 1 ==
7301 09:29:37.179960 Final DQS duty delay cell = 0
7302 09:29:37.183425 [0] MAX Duty = 5187%(X100), DQS PI = 2
7303 09:29:37.186742 [0] MIN Duty = 5031%(X100), DQS PI = 52
7304 09:29:37.190495 [0] AVG Duty = 5109%(X100)
7305 09:29:37.190991
7306 09:29:37.193711 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7307 09:29:37.194200
7308 09:29:37.196704 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7309 09:29:37.199937 [DutyScan_Calibration_Flow] ====Done====
7310 09:29:37.200363
7311 09:29:37.203401 [DutyScan_Calibration_Flow] k_type=3
7312 09:29:37.220193
7313 09:29:37.220672 ==DQM 0 ==
7314 09:29:37.223400 Final DQM duty delay cell = 0
7315 09:29:37.227067 [0] MAX Duty = 5187%(X100), DQS PI = 26
7316 09:29:37.230110 [0] MIN Duty = 4875%(X100), DQS PI = 58
7317 09:29:37.233676 [0] AVG Duty = 5031%(X100)
7318 09:29:37.234198
7319 09:29:37.234527 ==DQM 1 ==
7320 09:29:37.236619 Final DQM duty delay cell = -4
7321 09:29:37.240664 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7322 09:29:37.243738 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7323 09:29:37.246501 [-4] AVG Duty = 4922%(X100)
7324 09:29:37.247001
7325 09:29:37.250317 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7326 09:29:37.250731
7327 09:29:37.253019 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7328 09:29:37.256358 [DutyScan_Calibration_Flow] ====Done====
7329 09:29:37.256771
7330 09:29:37.259516 [DutyScan_Calibration_Flow] k_type=2
7331 09:29:37.277342
7332 09:29:37.277846 ==DQ 0 ==
7333 09:29:37.281070 Final DQ duty delay cell = 0
7334 09:29:37.283972 [0] MAX Duty = 5093%(X100), DQS PI = 28
7335 09:29:37.287838 [0] MIN Duty = 4907%(X100), DQS PI = 0
7336 09:29:37.288336 [0] AVG Duty = 5000%(X100)
7337 09:29:37.288666
7338 09:29:37.291151 ==DQ 1 ==
7339 09:29:37.294401 Final DQ duty delay cell = 0
7340 09:29:37.297742 [0] MAX Duty = 5156%(X100), DQS PI = 22
7341 09:29:37.301026 [0] MIN Duty = 4907%(X100), DQS PI = 34
7342 09:29:37.301444 [0] AVG Duty = 5031%(X100)
7343 09:29:37.301778
7344 09:29:37.304387 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7345 09:29:37.304801
7346 09:29:37.311117 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7347 09:29:37.314203 [DutyScan_Calibration_Flow] ====Done====
7348 09:29:37.314719 ==
7349 09:29:37.317382 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 09:29:37.320624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 09:29:37.321278 ==
7352 09:29:37.324255 [Duty_Offset_Calibration]
7353 09:29:37.324672 B0:1 B1:0 CA:0
7354 09:29:37.325003
7355 09:29:37.327802 [DutyScan_Calibration_Flow] k_type=0
7356 09:29:37.337158
7357 09:29:37.337658 ==CLK 0==
7358 09:29:37.340429 Final CLK duty delay cell = -4
7359 09:29:37.343517 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7360 09:29:37.346767 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7361 09:29:37.349989 [-4] AVG Duty = 4922%(X100)
7362 09:29:37.350421
7363 09:29:37.353589 CH1 CLK Duty spec in!! Max-Min= 156%
7364 09:29:37.356789 [DutyScan_Calibration_Flow] ====Done====
7365 09:29:37.357194
7366 09:29:37.360181 [DutyScan_Calibration_Flow] k_type=1
7367 09:29:37.376965
7368 09:29:37.377440 ==DQS 0 ==
7369 09:29:37.380375 Final DQS duty delay cell = 0
7370 09:29:37.383631 [0] MAX Duty = 5062%(X100), DQS PI = 24
7371 09:29:37.386985 [0] MIN Duty = 4844%(X100), DQS PI = 14
7372 09:29:37.389929 [0] AVG Duty = 4953%(X100)
7373 09:29:37.390441
7374 09:29:37.390918 ==DQS 1 ==
7375 09:29:37.393608 Final DQS duty delay cell = 0
7376 09:29:37.396760 [0] MAX Duty = 5249%(X100), DQS PI = 48
7377 09:29:37.399851 [0] MIN Duty = 4907%(X100), DQS PI = 42
7378 09:29:37.403394 [0] AVG Duty = 5078%(X100)
7379 09:29:37.403977
7380 09:29:37.406922 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7381 09:29:37.407333
7382 09:29:37.410305 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7383 09:29:37.413668 [DutyScan_Calibration_Flow] ====Done====
7384 09:29:37.414078
7385 09:29:37.416336 [DutyScan_Calibration_Flow] k_type=3
7386 09:29:37.434248
7387 09:29:37.434727 ==DQM 0 ==
7388 09:29:37.436899 Final DQM duty delay cell = 0
7389 09:29:37.440440 [0] MAX Duty = 5187%(X100), DQS PI = 40
7390 09:29:37.443717 [0] MIN Duty = 5000%(X100), DQS PI = 16
7391 09:29:37.447051 [0] AVG Duty = 5093%(X100)
7392 09:29:37.447459
7393 09:29:37.447827 ==DQM 1 ==
7394 09:29:37.450292 Final DQM duty delay cell = 0
7395 09:29:37.453741 [0] MAX Duty = 5093%(X100), DQS PI = 8
7396 09:29:37.456969 [0] MIN Duty = 4907%(X100), DQS PI = 2
7397 09:29:37.460269 [0] AVG Duty = 5000%(X100)
7398 09:29:37.460680
7399 09:29:37.463416 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7400 09:29:37.463873
7401 09:29:37.467431 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7402 09:29:37.470328 [DutyScan_Calibration_Flow] ====Done====
7403 09:29:37.470738
7404 09:29:37.473547 [DutyScan_Calibration_Flow] k_type=2
7405 09:29:37.489862
7406 09:29:37.490454 ==DQ 0 ==
7407 09:29:37.492883 Final DQ duty delay cell = -4
7408 09:29:37.496187 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7409 09:29:37.499541 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7410 09:29:37.503281 [-4] AVG Duty = 4953%(X100)
7411 09:29:37.503840
7412 09:29:37.504364 ==DQ 1 ==
7413 09:29:37.506531 Final DQ duty delay cell = 0
7414 09:29:37.509535 [0] MAX Duty = 5125%(X100), DQS PI = 8
7415 09:29:37.513244 [0] MIN Duty = 4938%(X100), DQS PI = 0
7416 09:29:37.513844 [0] AVG Duty = 5031%(X100)
7417 09:29:37.514329
7418 09:29:37.519728 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7419 09:29:37.520148
7420 09:29:37.523238 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7421 09:29:37.526615 [DutyScan_Calibration_Flow] ====Done====
7422 09:29:37.529536 nWR fixed to 30
7423 09:29:37.529833 [ModeRegInit_LP4] CH0 RK0
7424 09:29:37.533333 [ModeRegInit_LP4] CH0 RK1
7425 09:29:37.536434 [ModeRegInit_LP4] CH1 RK0
7426 09:29:37.536724 [ModeRegInit_LP4] CH1 RK1
7427 09:29:37.540189 match AC timing 5
7428 09:29:37.542903 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 09:29:37.549576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 09:29:37.553169 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 09:29:37.556226 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 09:29:37.563013 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 09:29:37.563455 [MiockJmeterHQA]
7434 09:29:37.563793
7435 09:29:37.566651 [DramcMiockJmeter] u1RxGatingPI = 0
7436 09:29:37.569741 0 : 4252, 4026
7437 09:29:37.570160 4 : 4368, 4140
7438 09:29:37.573064 8 : 4252, 4027
7439 09:29:37.573484 12 : 4255, 4029
7440 09:29:37.573816 16 : 4253, 4027
7441 09:29:37.576372 20 : 4252, 4027
7442 09:29:37.576797 24 : 4255, 4029
7443 09:29:37.579971 28 : 4253, 4027
7444 09:29:37.580547 32 : 4252, 4027
7445 09:29:37.582787 36 : 4365, 4140
7446 09:29:37.583207 40 : 4252, 4026
7447 09:29:37.583542 44 : 4255, 4029
7448 09:29:37.586075 48 : 4252, 4027
7449 09:29:37.586708 52 : 4363, 4137
7450 09:29:37.589517 56 : 4253, 4027
7451 09:29:37.589999 60 : 4360, 4138
7452 09:29:37.592981 64 : 4250, 4027
7453 09:29:37.593489 68 : 4250, 4027
7454 09:29:37.595954 72 : 4250, 4027
7455 09:29:37.596375 76 : 4253, 4029
7456 09:29:37.596711 80 : 4361, 4138
7457 09:29:37.599030 84 : 4249, 4027
7458 09:29:37.599449 88 : 4361, 94
7459 09:29:37.602714 92 : 4252, 0
7460 09:29:37.603135 96 : 4363, 0
7461 09:29:37.603469 100 : 4360, 0
7462 09:29:37.605947 104 : 4363, 0
7463 09:29:37.606367 108 : 4250, 0
7464 09:29:37.609706 112 : 4250, 0
7465 09:29:37.610299 116 : 4250, 0
7466 09:29:37.610710 120 : 4253, 0
7467 09:29:37.612600 124 : 4361, 0
7468 09:29:37.613022 128 : 4250, 0
7469 09:29:37.615830 132 : 4250, 0
7470 09:29:37.616290 136 : 4250, 0
7471 09:29:37.616628 140 : 4361, 0
7472 09:29:37.619121 144 : 4360, 0
7473 09:29:37.619751 148 : 4250, 0
7474 09:29:37.620126 152 : 4250, 0
7475 09:29:37.622569 156 : 4250, 0
7476 09:29:37.622992 160 : 4252, 0
7477 09:29:37.625757 164 : 4250, 0
7478 09:29:37.626252 168 : 4250, 0
7479 09:29:37.626596 172 : 4252, 0
7480 09:29:37.628943 176 : 4361, 0
7481 09:29:37.629365 180 : 4250, 0
7482 09:29:37.632885 184 : 4250, 0
7483 09:29:37.633345 188 : 4250, 0
7484 09:29:37.633681 192 : 4361, 0
7485 09:29:37.635951 196 : 4361, 0
7486 09:29:37.636370 200 : 4250, 0
7487 09:29:37.639382 204 : 4250, 1315
7488 09:29:37.639862 208 : 4250, 3998
7489 09:29:37.642608 212 : 4250, 4027
7490 09:29:37.643124 216 : 4250, 4027
7491 09:29:37.646052 220 : 4363, 4140
7492 09:29:37.646475 224 : 4361, 4137
7493 09:29:37.646811 228 : 4250, 4027
7494 09:29:37.649053 232 : 4363, 4140
7495 09:29:37.649520 236 : 4360, 4138
7496 09:29:37.652556 240 : 4250, 4027
7497 09:29:37.652980 244 : 4250, 4027
7498 09:29:37.655947 248 : 4252, 4029
7499 09:29:37.656372 252 : 4250, 4027
7500 09:29:37.659305 256 : 4250, 4027
7501 09:29:37.659798 260 : 4250, 4027
7502 09:29:37.662883 264 : 4252, 4029
7503 09:29:37.663397 268 : 4250, 4027
7504 09:29:37.665805 272 : 4363, 4140
7505 09:29:37.666225 276 : 4361, 4138
7506 09:29:37.669148 280 : 4250, 4027
7507 09:29:37.669586 284 : 4363, 4140
7508 09:29:37.669925 288 : 4360, 4138
7509 09:29:37.672592 292 : 4250, 4027
7510 09:29:37.673018 296 : 4250, 4027
7511 09:29:37.676104 300 : 4252, 4029
7512 09:29:37.676527 304 : 4250, 4027
7513 09:29:37.678705 308 : 4250, 3947
7514 09:29:37.679129 312 : 4250, 2017
7515 09:29:37.679463
7516 09:29:37.681960 MIOCK jitter meter ch=0
7517 09:29:37.682378
7518 09:29:37.686036 1T = (312-88) = 224 dly cells
7519 09:29:37.692324 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7520 09:29:37.692747 ==
7521 09:29:37.695926 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 09:29:37.699343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 09:29:37.699916 ==
7524 09:29:37.702396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 09:29:37.709541 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 09:29:37.712510 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 09:29:37.718758 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 09:29:37.727614 [CA 0] Center 43 (12~74) winsize 63
7529 09:29:37.730791 [CA 1] Center 43 (12~74) winsize 63
7530 09:29:37.733985 [CA 2] Center 38 (9~68) winsize 60
7531 09:29:37.737466 [CA 3] Center 38 (8~68) winsize 61
7532 09:29:37.740733 [CA 4] Center 36 (7~66) winsize 60
7533 09:29:37.744201 [CA 5] Center 36 (7~65) winsize 59
7534 09:29:37.744681
7535 09:29:37.747572 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 09:29:37.748104
7537 09:29:37.750772 [CATrainingPosCal] consider 1 rank data
7538 09:29:37.754092 u2DelayCellTimex100 = 290/100 ps
7539 09:29:37.757166 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7540 09:29:37.763956 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7541 09:29:37.767467 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7542 09:29:37.770717 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7543 09:29:37.773919 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7544 09:29:37.777458 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7545 09:29:37.777866
7546 09:29:37.780786 CA PerBit enable=1, Macro0, CA PI delay=36
7547 09:29:37.781200
7548 09:29:37.784228 [CBTSetCACLKResult] CA Dly = 36
7549 09:29:37.784638 CS Dly: 9 (0~40)
7550 09:29:37.790732 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 09:29:37.794183 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 09:29:37.794666 ==
7553 09:29:37.797357 Dram Type= 6, Freq= 0, CH_0, rank 1
7554 09:29:37.800418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 09:29:37.800847 ==
7556 09:29:37.807011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 09:29:37.810489 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 09:29:37.816885 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 09:29:37.820711 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 09:29:37.830265 [CA 0] Center 43 (13~73) winsize 61
7561 09:29:37.833414 [CA 1] Center 42 (12~73) winsize 62
7562 09:29:37.837282 [CA 2] Center 38 (8~68) winsize 61
7563 09:29:37.840573 [CA 3] Center 38 (8~68) winsize 61
7564 09:29:37.843272 [CA 4] Center 36 (6~66) winsize 61
7565 09:29:37.846612 [CA 5] Center 35 (6~65) winsize 60
7566 09:29:37.846740
7567 09:29:37.849948 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7568 09:29:37.850082
7569 09:29:37.853227 [CATrainingPosCal] consider 2 rank data
7570 09:29:37.856498 u2DelayCellTimex100 = 290/100 ps
7571 09:29:37.859751 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7572 09:29:37.867028 CA1 delay=42 (12~73),Diff = 6 PI (20 cell)
7573 09:29:37.869678 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7574 09:29:37.873517 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7575 09:29:37.876697 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7576 09:29:37.879955 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7577 09:29:37.880035
7578 09:29:37.882971 CA PerBit enable=1, Macro0, CA PI delay=36
7579 09:29:37.883052
7580 09:29:37.886363 [CBTSetCACLKResult] CA Dly = 36
7581 09:29:37.889740 CS Dly: 10 (0~42)
7582 09:29:37.893514 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 09:29:37.896519 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 09:29:37.896600
7585 09:29:37.900316 ----->DramcWriteLeveling(PI) begin...
7586 09:29:37.900399 ==
7587 09:29:37.903071 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 09:29:37.906812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 09:29:37.910234 ==
7590 09:29:37.910389 Write leveling (Byte 0): 36 => 36
7591 09:29:37.913562 Write leveling (Byte 1): 29 => 29
7592 09:29:37.917031 DramcWriteLeveling(PI) end<-----
7593 09:29:37.917168
7594 09:29:37.917239 ==
7595 09:29:37.920215 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 09:29:37.926799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 09:29:37.926882 ==
7598 09:29:37.926946 [Gating] SW mode calibration
7599 09:29:37.936405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7600 09:29:37.940012 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7601 09:29:37.943788 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7602 09:29:37.949828 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 09:29:37.953408 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7604 09:29:37.957140 1 4 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7605 09:29:37.962972 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7606 09:29:37.966164 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 09:29:37.970137 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7608 09:29:37.977166 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7609 09:29:37.980033 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7610 09:29:37.983424 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7611 09:29:37.990034 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7612 09:29:37.993313 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7613 09:29:37.996597 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7614 09:29:38.003058 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 09:29:38.006576 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 09:29:38.010269 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 09:29:38.016508 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7618 09:29:38.020103 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7619 09:29:38.023356 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7620 09:29:38.029982 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7621 09:29:38.033236 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7622 09:29:38.036540 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 09:29:38.043346 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7624 09:29:38.046983 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 09:29:38.049642 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 09:29:38.056479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 09:29:38.059454 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 09:29:38.063325 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 09:29:38.069546 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 09:29:38.072822 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 09:29:38.076575 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 09:29:38.083241 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 09:29:38.086496 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 09:29:38.089857 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 09:29:38.093142 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:29:38.099518 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:29:38.103032 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:29:38.106442 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:29:38.112685 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 09:29:38.116101 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 09:29:38.119386 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 09:29:38.125863 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 09:29:38.129634 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 09:29:38.132717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 09:29:38.139203 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 09:29:38.142444 Total UI for P1: 0, mck2ui 16
7647 09:29:38.145618 best dqsien dly found for B0: ( 1, 9, 12)
7648 09:29:38.149027 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 09:29:38.152791 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 09:29:38.155740 Total UI for P1: 0, mck2ui 16
7651 09:29:38.159466 best dqsien dly found for B1: ( 1, 9, 18)
7652 09:29:38.162524 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7653 09:29:38.166190 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7654 09:29:38.166574
7655 09:29:38.172667 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7656 09:29:38.176004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7657 09:29:38.179305 [Gating] SW calibration Done
7658 09:29:38.179742 ==
7659 09:29:38.182617 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 09:29:38.186082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 09:29:38.186467 ==
7662 09:29:38.186766 RX Vref Scan: 0
7663 09:29:38.187046
7664 09:29:38.189136 RX Vref 0 -> 0, step: 1
7665 09:29:38.189522
7666 09:29:38.192469 RX Delay 0 -> 252, step: 8
7667 09:29:38.195878 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7668 09:29:38.199085 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7669 09:29:38.205692 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7670 09:29:38.208940 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7671 09:29:38.212146 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7672 09:29:38.215480 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7673 09:29:38.219445 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7674 09:29:38.222194 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7675 09:29:38.229306 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7676 09:29:38.232582 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7677 09:29:38.235910 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7678 09:29:38.239284 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7679 09:29:38.245846 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7680 09:29:38.249134 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7681 09:29:38.252447 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7682 09:29:38.255665 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7683 09:29:38.256061 ==
7684 09:29:38.258694 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 09:29:38.262004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 09:29:38.265702 ==
7687 09:29:38.266129 DQS Delay:
7688 09:29:38.266552 DQS0 = 0, DQS1 = 0
7689 09:29:38.268749 DQM Delay:
7690 09:29:38.269167 DQM0 = 137, DQM1 = 129
7691 09:29:38.272290 DQ Delay:
7692 09:29:38.275717 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7693 09:29:38.279142 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7694 09:29:38.282353 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7695 09:29:38.285225 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7696 09:29:38.285616
7697 09:29:38.285916
7698 09:29:38.286196 ==
7699 09:29:38.288691 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 09:29:38.292353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 09:29:38.292738 ==
7702 09:29:38.293042
7703 09:29:38.295479
7704 09:29:38.295903 TX Vref Scan disable
7705 09:29:38.299050 == TX Byte 0 ==
7706 09:29:38.302374 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7707 09:29:38.305508 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7708 09:29:38.308923 == TX Byte 1 ==
7709 09:29:38.312308 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7710 09:29:38.315612 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7711 09:29:38.316029 ==
7712 09:29:38.318918 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 09:29:38.325416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 09:29:38.325799 ==
7715 09:29:38.336042
7716 09:29:38.339444 TX Vref early break, caculate TX vref
7717 09:29:38.342709 TX Vref=16, minBit 4, minWin=22, winSum=379
7718 09:29:38.345993 TX Vref=18, minBit 4, minWin=23, winSum=389
7719 09:29:38.349249 TX Vref=20, minBit 0, minWin=24, winSum=400
7720 09:29:38.352512 TX Vref=22, minBit 0, minWin=24, winSum=408
7721 09:29:38.356335 TX Vref=24, minBit 3, minWin=24, winSum=419
7722 09:29:38.363023 TX Vref=26, minBit 1, minWin=25, winSum=422
7723 09:29:38.366316 TX Vref=28, minBit 2, minWin=25, winSum=425
7724 09:29:38.369097 TX Vref=30, minBit 6, minWin=24, winSum=416
7725 09:29:38.372523 TX Vref=32, minBit 6, minWin=23, winSum=400
7726 09:29:38.379123 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 28
7727 09:29:38.379507
7728 09:29:38.382515 Final TX Range 0 Vref 28
7729 09:29:38.383005
7730 09:29:38.383337 ==
7731 09:29:38.385895 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 09:29:38.389081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 09:29:38.389500 ==
7734 09:29:38.389824
7735 09:29:38.390126
7736 09:29:38.392833 TX Vref Scan disable
7737 09:29:38.396015 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7738 09:29:38.399022 == TX Byte 0 ==
7739 09:29:38.402482 u2DelayCellOfst[0]=10 cells (3 PI)
7740 09:29:38.405801 u2DelayCellOfst[1]=13 cells (4 PI)
7741 09:29:38.409184 u2DelayCellOfst[2]=10 cells (3 PI)
7742 09:29:38.412443 u2DelayCellOfst[3]=10 cells (3 PI)
7743 09:29:38.416047 u2DelayCellOfst[4]=6 cells (2 PI)
7744 09:29:38.419621 u2DelayCellOfst[5]=0 cells (0 PI)
7745 09:29:38.420078 u2DelayCellOfst[6]=16 cells (5 PI)
7746 09:29:38.422458 u2DelayCellOfst[7]=16 cells (5 PI)
7747 09:29:38.428958 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7748 09:29:38.432535 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7749 09:29:38.433080 == TX Byte 1 ==
7750 09:29:38.435879 u2DelayCellOfst[8]=3 cells (1 PI)
7751 09:29:38.439039 u2DelayCellOfst[9]=0 cells (0 PI)
7752 09:29:38.442426 u2DelayCellOfst[10]=6 cells (2 PI)
7753 09:29:38.445862 u2DelayCellOfst[11]=6 cells (2 PI)
7754 09:29:38.449235 u2DelayCellOfst[12]=10 cells (3 PI)
7755 09:29:38.452661 u2DelayCellOfst[13]=10 cells (3 PI)
7756 09:29:38.455967 u2DelayCellOfst[14]=13 cells (4 PI)
7757 09:29:38.459178 u2DelayCellOfst[15]=10 cells (3 PI)
7758 09:29:38.462417 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7759 09:29:38.465870 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7760 09:29:38.469139 DramC Write-DBI on
7761 09:29:38.469536 ==
7762 09:29:38.472497 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 09:29:38.476035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 09:29:38.476453 ==
7765 09:29:38.476778
7766 09:29:38.479201
7767 09:29:38.479703 TX Vref Scan disable
7768 09:29:38.482504 == TX Byte 0 ==
7769 09:29:38.485174 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7770 09:29:38.488599 == TX Byte 1 ==
7771 09:29:38.491895 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7772 09:29:38.492316 DramC Write-DBI off
7773 09:29:38.495170
7774 09:29:38.495582 [DATLAT]
7775 09:29:38.495981 Freq=1600, CH0 RK0
7776 09:29:38.496298
7777 09:29:38.498503 DATLAT Default: 0xf
7778 09:29:38.498923 0, 0xFFFF, sum = 0
7779 09:29:38.501725 1, 0xFFFF, sum = 0
7780 09:29:38.502325 2, 0xFFFF, sum = 0
7781 09:29:38.505124 3, 0xFFFF, sum = 0
7782 09:29:38.508622 4, 0xFFFF, sum = 0
7783 09:29:38.509048 5, 0xFFFF, sum = 0
7784 09:29:38.511948 6, 0xFFFF, sum = 0
7785 09:29:38.512370 7, 0xFFFF, sum = 0
7786 09:29:38.515022 8, 0xFFFF, sum = 0
7787 09:29:38.515456 9, 0xFFFF, sum = 0
7788 09:29:38.518261 10, 0xFFFF, sum = 0
7789 09:29:38.518836 11, 0xFFFF, sum = 0
7790 09:29:38.521627 12, 0xFFFF, sum = 0
7791 09:29:38.522108 13, 0xFFFF, sum = 0
7792 09:29:38.524915 14, 0x0, sum = 1
7793 09:29:38.525377 15, 0x0, sum = 2
7794 09:29:38.528061 16, 0x0, sum = 3
7795 09:29:38.528586 17, 0x0, sum = 4
7796 09:29:38.531832 best_step = 15
7797 09:29:38.532315
7798 09:29:38.532794 ==
7799 09:29:38.534701 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 09:29:38.538585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 09:29:38.539188 ==
7802 09:29:38.541366 RX Vref Scan: 1
7803 09:29:38.541941
7804 09:29:38.542483 Set Vref Range= 24 -> 127
7805 09:29:38.542988
7806 09:29:38.544917 RX Vref 24 -> 127, step: 1
7807 09:29:38.545453
7808 09:29:38.548205 RX Delay 19 -> 252, step: 4
7809 09:29:38.548786
7810 09:29:38.551387 Set Vref, RX VrefLevel [Byte0]: 24
7811 09:29:38.554411 [Byte1]: 24
7812 09:29:38.554926
7813 09:29:38.558450 Set Vref, RX VrefLevel [Byte0]: 25
7814 09:29:38.561559 [Byte1]: 25
7815 09:29:38.564723
7816 09:29:38.565303 Set Vref, RX VrefLevel [Byte0]: 26
7817 09:29:38.568292 [Byte1]: 26
7818 09:29:38.572174
7819 09:29:38.572619 Set Vref, RX VrefLevel [Byte0]: 27
7820 09:29:38.575721 [Byte1]: 27
7821 09:29:38.579719
7822 09:29:38.580201 Set Vref, RX VrefLevel [Byte0]: 28
7823 09:29:38.582890 [Byte1]: 28
7824 09:29:38.587545
7825 09:29:38.588001 Set Vref, RX VrefLevel [Byte0]: 29
7826 09:29:38.590790 [Byte1]: 29
7827 09:29:38.594839
7828 09:29:38.595337 Set Vref, RX VrefLevel [Byte0]: 30
7829 09:29:38.598299 [Byte1]: 30
7830 09:29:38.602928
7831 09:29:38.603393 Set Vref, RX VrefLevel [Byte0]: 31
7832 09:29:38.605643 [Byte1]: 31
7833 09:29:38.610302
7834 09:29:38.610717 Set Vref, RX VrefLevel [Byte0]: 32
7835 09:29:38.613534 [Byte1]: 32
7836 09:29:38.617671
7837 09:29:38.621133 Set Vref, RX VrefLevel [Byte0]: 33
7838 09:29:38.624535 [Byte1]: 33
7839 09:29:38.624953
7840 09:29:38.627968 Set Vref, RX VrefLevel [Byte0]: 34
7841 09:29:38.630514 [Byte1]: 34
7842 09:29:38.630941
7843 09:29:38.633999 Set Vref, RX VrefLevel [Byte0]: 35
7844 09:29:38.637317 [Byte1]: 35
7845 09:29:38.637734
7846 09:29:38.640549 Set Vref, RX VrefLevel [Byte0]: 36
7847 09:29:38.643875 [Byte1]: 36
7848 09:29:38.647835
7849 09:29:38.648286 Set Vref, RX VrefLevel [Byte0]: 37
7850 09:29:38.651203 [Byte1]: 37
7851 09:29:38.655567
7852 09:29:38.656057 Set Vref, RX VrefLevel [Byte0]: 38
7853 09:29:38.658699 [Byte1]: 38
7854 09:29:38.663425
7855 09:29:38.663902 Set Vref, RX VrefLevel [Byte0]: 39
7856 09:29:38.666216 [Byte1]: 39
7857 09:29:38.670918
7858 09:29:38.671298 Set Vref, RX VrefLevel [Byte0]: 40
7859 09:29:38.674295 [Byte1]: 40
7860 09:29:38.678112
7861 09:29:38.678521 Set Vref, RX VrefLevel [Byte0]: 41
7862 09:29:38.681380 [Byte1]: 41
7863 09:29:38.685811
7864 09:29:38.686244 Set Vref, RX VrefLevel [Byte0]: 42
7865 09:29:38.689303 [Byte1]: 42
7866 09:29:38.693139
7867 09:29:38.693718 Set Vref, RX VrefLevel [Byte0]: 43
7868 09:29:38.696627 [Byte1]: 43
7869 09:29:38.701002
7870 09:29:38.701409 Set Vref, RX VrefLevel [Byte0]: 44
7871 09:29:38.704027 [Byte1]: 44
7872 09:29:38.708302
7873 09:29:38.708907 Set Vref, RX VrefLevel [Byte0]: 45
7874 09:29:38.711904 [Byte1]: 45
7875 09:29:38.715824
7876 09:29:38.719179 Set Vref, RX VrefLevel [Byte0]: 46
7877 09:29:38.722320 [Byte1]: 46
7878 09:29:38.722909
7879 09:29:38.725544 Set Vref, RX VrefLevel [Byte0]: 47
7880 09:29:38.728940 [Byte1]: 47
7881 09:29:38.729399
7882 09:29:38.732349 Set Vref, RX VrefLevel [Byte0]: 48
7883 09:29:38.735706 [Byte1]: 48
7884 09:29:38.736286
7885 09:29:38.739148 Set Vref, RX VrefLevel [Byte0]: 49
7886 09:29:38.742420 [Byte1]: 49
7887 09:29:38.746533
7888 09:29:38.747083 Set Vref, RX VrefLevel [Byte0]: 50
7889 09:29:38.749926 [Byte1]: 50
7890 09:29:38.753888
7891 09:29:38.754196 Set Vref, RX VrefLevel [Byte0]: 51
7892 09:29:38.757306 [Byte1]: 51
7893 09:29:38.761143
7894 09:29:38.761598 Set Vref, RX VrefLevel [Byte0]: 52
7895 09:29:38.764403 [Byte1]: 52
7896 09:29:38.769123
7897 09:29:38.769413 Set Vref, RX VrefLevel [Byte0]: 53
7898 09:29:38.772576 [Byte1]: 53
7899 09:29:38.776507
7900 09:29:38.776726 Set Vref, RX VrefLevel [Byte0]: 54
7901 09:29:38.779697 [Byte1]: 54
7902 09:29:38.784243
7903 09:29:38.784419 Set Vref, RX VrefLevel [Byte0]: 55
7904 09:29:38.787504 [Byte1]: 55
7905 09:29:38.791374
7906 09:29:38.791538 Set Vref, RX VrefLevel [Byte0]: 56
7907 09:29:38.794636 [Byte1]: 56
7908 09:29:38.798954
7909 09:29:38.799065 Set Vref, RX VrefLevel [Byte0]: 57
7910 09:29:38.802663 [Byte1]: 57
7911 09:29:38.806428
7912 09:29:38.806546 Set Vref, RX VrefLevel [Byte0]: 58
7913 09:29:38.809757 [Byte1]: 58
7914 09:29:38.814654
7915 09:29:38.814735 Set Vref, RX VrefLevel [Byte0]: 59
7916 09:29:38.817432 [Byte1]: 59
7917 09:29:38.821768
7918 09:29:38.821849 Set Vref, RX VrefLevel [Byte0]: 60
7919 09:29:38.824949 [Byte1]: 60
7920 09:29:38.829045
7921 09:29:38.829152 Set Vref, RX VrefLevel [Byte0]: 61
7922 09:29:38.832711 [Byte1]: 61
7923 09:29:38.837147
7924 09:29:38.837228 Set Vref, RX VrefLevel [Byte0]: 62
7925 09:29:38.840144 [Byte1]: 62
7926 09:29:38.844700
7927 09:29:38.844781 Set Vref, RX VrefLevel [Byte0]: 63
7928 09:29:38.848040 [Byte1]: 63
7929 09:29:38.851943
7930 09:29:38.852024 Set Vref, RX VrefLevel [Byte0]: 64
7931 09:29:38.855222 [Byte1]: 64
7932 09:29:38.859963
7933 09:29:38.860044 Set Vref, RX VrefLevel [Byte0]: 65
7934 09:29:38.863158 [Byte1]: 65
7935 09:29:38.866987
7936 09:29:38.867069 Set Vref, RX VrefLevel [Byte0]: 66
7937 09:29:38.870819 [Byte1]: 66
7938 09:29:38.874981
7939 09:29:38.875063 Set Vref, RX VrefLevel [Byte0]: 67
7940 09:29:38.878417 [Byte1]: 67
7941 09:29:38.882315
7942 09:29:38.882396 Set Vref, RX VrefLevel [Byte0]: 68
7943 09:29:38.885673 [Byte1]: 68
7944 09:29:38.889851
7945 09:29:38.889930 Set Vref, RX VrefLevel [Byte0]: 69
7946 09:29:38.893106 [Byte1]: 69
7947 09:29:38.897554
7948 09:29:38.897634 Set Vref, RX VrefLevel [Byte0]: 70
7949 09:29:38.900974 [Byte1]: 70
7950 09:29:38.904845
7951 09:29:38.904924 Set Vref, RX VrefLevel [Byte0]: 71
7952 09:29:38.908101 [Byte1]: 71
7953 09:29:38.912587
7954 09:29:38.912704 Set Vref, RX VrefLevel [Byte0]: 72
7955 09:29:38.915854 [Byte1]: 72
7956 09:29:38.919882
7957 09:29:38.919961 Set Vref, RX VrefLevel [Byte0]: 73
7958 09:29:38.923993 [Byte1]: 73
7959 09:29:38.927864
7960 09:29:38.927944 Set Vref, RX VrefLevel [Byte0]: 74
7961 09:29:38.931146 [Byte1]: 74
7962 09:29:38.935018
7963 09:29:38.935106 Set Vref, RX VrefLevel [Byte0]: 75
7964 09:29:38.938777 [Byte1]: 75
7965 09:29:38.943001
7966 09:29:38.943079 Final RX Vref Byte 0 = 53 to rank0
7967 09:29:38.946575 Final RX Vref Byte 1 = 61 to rank0
7968 09:29:38.949573 Final RX Vref Byte 0 = 53 to rank1
7969 09:29:38.953287 Final RX Vref Byte 1 = 61 to rank1==
7970 09:29:38.956109 Dram Type= 6, Freq= 0, CH_0, rank 0
7971 09:29:38.963087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 09:29:38.963249 ==
7973 09:29:38.963317 DQS Delay:
7974 09:29:38.963376 DQS0 = 0, DQS1 = 0
7975 09:29:38.966192 DQM Delay:
7976 09:29:38.966272 DQM0 = 133, DQM1 = 128
7977 09:29:38.969377 DQ Delay:
7978 09:29:38.972684 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =130
7979 09:29:38.976404 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7980 09:29:38.979820 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7981 09:29:38.983236 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7982 09:29:38.983316
7983 09:29:38.983379
7984 09:29:38.983437
7985 09:29:38.985823 [DramC_TX_OE_Calibration] TA2
7986 09:29:38.989666 Original DQ_B0 (3 6) =30, OEN = 27
7987 09:29:38.992977 Original DQ_B1 (3 6) =30, OEN = 27
7988 09:29:38.996338 24, 0x0, End_B0=24 End_B1=24
7989 09:29:38.996420 25, 0x0, End_B0=25 End_B1=25
7990 09:29:38.999571 26, 0x0, End_B0=26 End_B1=26
7991 09:29:39.002929 27, 0x0, End_B0=27 End_B1=27
7992 09:29:39.006223 28, 0x0, End_B0=28 End_B1=28
7993 09:29:39.006313 29, 0x0, End_B0=29 End_B1=29
7994 09:29:39.009300 30, 0x0, End_B0=30 End_B1=30
7995 09:29:39.012639 31, 0x4141, End_B0=30 End_B1=30
7996 09:29:39.015918 Byte0 end_step=30 best_step=27
7997 09:29:39.019115 Byte1 end_step=30 best_step=27
7998 09:29:39.022482 Byte0 TX OE(2T, 0.5T) = (3, 3)
7999 09:29:39.022562 Byte1 TX OE(2T, 0.5T) = (3, 3)
8000 09:29:39.026225
8001 09:29:39.026600
8002 09:29:39.032862 [DQSOSCAuto] RK0, (LSB)MR18= 0x2621, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
8003 09:29:39.036264 CH0 RK0: MR19=303, MR18=2621
8004 09:29:39.042952 CH0_RK0: MR19=0x303, MR18=0x2621, DQSOSC=390, MR23=63, INC=24, DEC=16
8005 09:29:39.043367
8006 09:29:39.046279 ----->DramcWriteLeveling(PI) begin...
8007 09:29:39.046753 ==
8008 09:29:39.049632 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 09:29:39.052904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 09:29:39.053437 ==
8011 09:29:39.056198 Write leveling (Byte 0): 36 => 36
8012 09:29:39.059931 Write leveling (Byte 1): 27 => 27
8013 09:29:39.063040 DramcWriteLeveling(PI) end<-----
8014 09:29:39.063732
8015 09:29:39.064175 ==
8016 09:29:39.066183 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 09:29:39.069778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 09:29:39.070318 ==
8019 09:29:39.072837 [Gating] SW mode calibration
8020 09:29:39.079219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8021 09:29:39.086206 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8022 09:29:39.089405 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 09:29:39.092472 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 09:29:39.099350 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 09:29:39.103193 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8026 09:29:39.105893 1 4 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
8027 09:29:39.112872 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 09:29:39.116058 1 4 24 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
8029 09:29:39.119410 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8030 09:29:39.125890 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8031 09:29:39.129237 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 09:29:39.132558 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8033 09:29:39.139260 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8034 09:29:39.142703 1 5 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
8035 09:29:39.146238 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 09:29:39.153007 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 09:29:39.156387 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 09:29:39.159539 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 09:29:39.166334 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8040 09:29:39.169559 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8041 09:29:39.172764 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8042 09:29:39.179336 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8043 09:29:39.182676 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 09:29:39.185904 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 09:29:39.189184 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 09:29:39.195878 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 09:29:39.198932 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 09:29:39.202599 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 09:29:39.208857 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 09:29:39.212372 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8051 09:29:39.215595 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8052 09:29:39.222501 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 09:29:39.225488 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 09:29:39.229084 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 09:29:39.236042 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 09:29:39.239043 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 09:29:39.242563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 09:29:39.249116 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 09:29:39.252670 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 09:29:39.256068 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 09:29:39.262275 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 09:29:39.265561 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 09:29:39.269030 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 09:29:39.275504 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 09:29:39.278830 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8066 09:29:39.282103 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8067 09:29:39.288835 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 09:29:39.288919 Total UI for P1: 0, mck2ui 16
8069 09:29:39.295355 best dqsien dly found for B0: ( 1, 9, 14)
8070 09:29:39.295438 Total UI for P1: 0, mck2ui 16
8071 09:29:39.298498 best dqsien dly found for B1: ( 1, 9, 14)
8072 09:29:39.305035 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8073 09:29:39.308416 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8074 09:29:39.308503
8075 09:29:39.311693 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8076 09:29:39.315187 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8077 09:29:39.318591 [Gating] SW calibration Done
8078 09:29:39.318693 ==
8079 09:29:39.321971 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 09:29:39.325305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 09:29:39.325428 ==
8082 09:29:39.328348 RX Vref Scan: 0
8083 09:29:39.328470
8084 09:29:39.328565 RX Vref 0 -> 0, step: 1
8085 09:29:39.328673
8086 09:29:39.332007 RX Delay 0 -> 252, step: 8
8087 09:29:39.335044 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8088 09:29:39.338568 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8089 09:29:39.345053 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8090 09:29:39.348137 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8091 09:29:39.351876 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8092 09:29:39.355032 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8093 09:29:39.358172 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8094 09:29:39.364669 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8095 09:29:39.368049 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8096 09:29:39.371431 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8097 09:29:39.374920 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8098 09:29:39.381349 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8099 09:29:39.385207 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8100 09:29:39.387791 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8101 09:29:39.391141 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8102 09:29:39.394528 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8103 09:29:39.397908 ==
8104 09:29:39.397990 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 09:29:39.404426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 09:29:39.404534 ==
8107 09:29:39.404604 DQS Delay:
8108 09:29:39.407889 DQS0 = 0, DQS1 = 0
8109 09:29:39.407971 DQM Delay:
8110 09:29:39.411238 DQM0 = 136, DQM1 = 128
8111 09:29:39.411319 DQ Delay:
8112 09:29:39.414518 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8113 09:29:39.417683 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8114 09:29:39.420964 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8115 09:29:39.424359 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8116 09:29:39.424442
8117 09:29:39.424506
8118 09:29:39.424565 ==
8119 09:29:39.427762 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 09:29:39.434348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 09:29:39.434436 ==
8122 09:29:39.434505
8123 09:29:39.434569
8124 09:29:39.434630 TX Vref Scan disable
8125 09:29:39.438387 == TX Byte 0 ==
8126 09:29:39.441617 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8127 09:29:39.444941 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8128 09:29:39.448428 == TX Byte 1 ==
8129 09:29:39.451577 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8130 09:29:39.457950 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8131 09:29:39.458085 ==
8132 09:29:39.461554 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 09:29:39.464474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 09:29:39.464626 ==
8135 09:29:39.479148
8136 09:29:39.482367 TX Vref early break, caculate TX vref
8137 09:29:39.485748 TX Vref=16, minBit 1, minWin=23, winSum=389
8138 09:29:39.488942 TX Vref=18, minBit 1, minWin=23, winSum=396
8139 09:29:39.492254 TX Vref=20, minBit 0, minWin=24, winSum=407
8140 09:29:39.495967 TX Vref=22, minBit 1, minWin=24, winSum=411
8141 09:29:39.499053 TX Vref=24, minBit 1, minWin=24, winSum=422
8142 09:29:39.505517 TX Vref=26, minBit 1, minWin=25, winSum=424
8143 09:29:39.508917 TX Vref=28, minBit 6, minWin=25, winSum=423
8144 09:29:39.512789 TX Vref=30, minBit 4, minWin=24, winSum=415
8145 09:29:39.516069 TX Vref=32, minBit 4, minWin=24, winSum=410
8146 09:29:39.519433 TX Vref=34, minBit 0, minWin=24, winSum=403
8147 09:29:39.522619 TX Vref=36, minBit 0, minWin=24, winSum=394
8148 09:29:39.529083 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8149 09:29:39.529168
8150 09:29:39.532261 Final TX Range 0 Vref 26
8151 09:29:39.532348
8152 09:29:39.532411 ==
8153 09:29:39.535873 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 09:29:39.539101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 09:29:39.539211 ==
8156 09:29:39.539279
8157 09:29:39.542326
8158 09:29:39.542406 TX Vref Scan disable
8159 09:29:39.548849 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8160 09:29:39.548931 == TX Byte 0 ==
8161 09:29:39.552204 u2DelayCellOfst[0]=10 cells (3 PI)
8162 09:29:39.555528 u2DelayCellOfst[1]=13 cells (4 PI)
8163 09:29:39.558938 u2DelayCellOfst[2]=10 cells (3 PI)
8164 09:29:39.562051 u2DelayCellOfst[3]=6 cells (2 PI)
8165 09:29:39.565387 u2DelayCellOfst[4]=6 cells (2 PI)
8166 09:29:39.568663 u2DelayCellOfst[5]=0 cells (0 PI)
8167 09:29:39.572039 u2DelayCellOfst[6]=16 cells (5 PI)
8168 09:29:39.575572 u2DelayCellOfst[7]=13 cells (4 PI)
8169 09:29:39.578613 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8170 09:29:39.581888 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8171 09:29:39.585137 == TX Byte 1 ==
8172 09:29:39.588852 u2DelayCellOfst[8]=3 cells (1 PI)
8173 09:29:39.588934 u2DelayCellOfst[9]=0 cells (0 PI)
8174 09:29:39.592473 u2DelayCellOfst[10]=6 cells (2 PI)
8175 09:29:39.595470 u2DelayCellOfst[11]=3 cells (1 PI)
8176 09:29:39.598844 u2DelayCellOfst[12]=10 cells (3 PI)
8177 09:29:39.602375 u2DelayCellOfst[13]=10 cells (3 PI)
8178 09:29:39.605255 u2DelayCellOfst[14]=16 cells (5 PI)
8179 09:29:39.608724 u2DelayCellOfst[15]=10 cells (3 PI)
8180 09:29:39.611922 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8181 09:29:39.618993 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8182 09:29:39.619075 DramC Write-DBI on
8183 09:29:39.619140 ==
8184 09:29:39.622461 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 09:29:39.628915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 09:29:39.629010 ==
8187 09:29:39.629088
8188 09:29:39.629158
8189 09:29:39.629225 TX Vref Scan disable
8190 09:29:39.632857 == TX Byte 0 ==
8191 09:29:39.636173 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8192 09:29:39.639554 == TX Byte 1 ==
8193 09:29:39.642667 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8194 09:29:39.645960 DramC Write-DBI off
8195 09:29:39.646042
8196 09:29:39.646105 [DATLAT]
8197 09:29:39.646165 Freq=1600, CH0 RK1
8198 09:29:39.646224
8199 09:29:39.649174 DATLAT Default: 0xf
8200 09:29:39.649259 0, 0xFFFF, sum = 0
8201 09:29:39.652485 1, 0xFFFF, sum = 0
8202 09:29:39.652568 2, 0xFFFF, sum = 0
8203 09:29:39.655629 3, 0xFFFF, sum = 0
8204 09:29:39.658951 4, 0xFFFF, sum = 0
8205 09:29:39.659034 5, 0xFFFF, sum = 0
8206 09:29:39.662974 6, 0xFFFF, sum = 0
8207 09:29:39.663062 7, 0xFFFF, sum = 0
8208 09:29:39.666267 8, 0xFFFF, sum = 0
8209 09:29:39.666375 9, 0xFFFF, sum = 0
8210 09:29:39.668922 10, 0xFFFF, sum = 0
8211 09:29:39.669004 11, 0xFFFF, sum = 0
8212 09:29:39.672375 12, 0xFFFF, sum = 0
8213 09:29:39.672468 13, 0xFFFF, sum = 0
8214 09:29:39.675761 14, 0x0, sum = 1
8215 09:29:39.675865 15, 0x0, sum = 2
8216 09:29:39.679228 16, 0x0, sum = 3
8217 09:29:39.679336 17, 0x0, sum = 4
8218 09:29:39.682302 best_step = 15
8219 09:29:39.682383
8220 09:29:39.682446 ==
8221 09:29:39.685875 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 09:29:39.689216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 09:29:39.689303 ==
8224 09:29:39.692641 RX Vref Scan: 0
8225 09:29:39.692735
8226 09:29:39.692809 RX Vref 0 -> 0, step: 1
8227 09:29:39.692877
8228 09:29:39.696026 RX Delay 19 -> 252, step: 4
8229 09:29:39.699323 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8230 09:29:39.705867 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8231 09:29:39.708972 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8232 09:29:39.712407 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8233 09:29:39.715495 iDelay=191, Bit 4, Center 136 (83 ~ 190) 108
8234 09:29:39.719148 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8235 09:29:39.725504 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8236 09:29:39.728855 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8237 09:29:39.732256 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8238 09:29:39.735788 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8239 09:29:39.739421 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8240 09:29:39.746046 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8241 09:29:39.748734 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8242 09:29:39.752435 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8243 09:29:39.755430 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8244 09:29:39.759368 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8245 09:29:39.759470 ==
8246 09:29:39.762054 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 09:29:39.768812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 09:29:39.768899 ==
8249 09:29:39.768967 DQS Delay:
8250 09:29:39.772144 DQS0 = 0, DQS1 = 0
8251 09:29:39.772226 DQM Delay:
8252 09:29:39.775468 DQM0 = 134, DQM1 = 127
8253 09:29:39.775574 DQ Delay:
8254 09:29:39.778858 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8255 09:29:39.782281 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =142
8256 09:29:39.785607 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8257 09:29:39.788796 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8258 09:29:39.788902
8259 09:29:39.788984
8260 09:29:39.789046
8261 09:29:39.791881 [DramC_TX_OE_Calibration] TA2
8262 09:29:39.795650 Original DQ_B0 (3 6) =30, OEN = 27
8263 09:29:39.799007 Original DQ_B1 (3 6) =30, OEN = 27
8264 09:29:39.802181 24, 0x0, End_B0=24 End_B1=24
8265 09:29:39.805538 25, 0x0, End_B0=25 End_B1=25
8266 09:29:39.805621 26, 0x0, End_B0=26 End_B1=26
8267 09:29:39.808959 27, 0x0, End_B0=27 End_B1=27
8268 09:29:39.812206 28, 0x0, End_B0=28 End_B1=28
8269 09:29:39.815618 29, 0x0, End_B0=29 End_B1=29
8270 09:29:39.815744 30, 0x0, End_B0=30 End_B1=30
8271 09:29:39.819004 31, 0x4141, End_B0=30 End_B1=30
8272 09:29:39.822282 Byte0 end_step=30 best_step=27
8273 09:29:39.825389 Byte1 end_step=30 best_step=27
8274 09:29:39.828700 Byte0 TX OE(2T, 0.5T) = (3, 3)
8275 09:29:39.831996 Byte1 TX OE(2T, 0.5T) = (3, 3)
8276 09:29:39.832077
8277 09:29:39.832141
8278 09:29:39.839023 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8279 09:29:39.842056 CH0 RK1: MR19=303, MR18=2008
8280 09:29:39.848827 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8281 09:29:39.852025 [RxdqsGatingPostProcess] freq 1600
8282 09:29:39.855572 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8283 09:29:39.858456 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 09:29:39.862219 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 09:29:39.865326 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 09:29:39.869054 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 09:29:39.872021 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 09:29:39.875493 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 09:29:39.878917 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 09:29:39.882184 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 09:29:39.885614 Pre-setting of DQS Precalculation
8292 09:29:39.888889 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8293 09:29:39.888996 ==
8294 09:29:39.892311 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 09:29:39.895621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 09:29:39.895742 ==
8297 09:29:39.902377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 09:29:39.905624 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 09:29:39.912136 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 09:29:39.915352 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 09:29:39.925830 [CA 0] Center 41 (12~71) winsize 60
8302 09:29:39.929156 [CA 1] Center 41 (12~71) winsize 60
8303 09:29:39.932353 [CA 2] Center 38 (9~68) winsize 60
8304 09:29:39.935589 [CA 3] Center 37 (8~66) winsize 59
8305 09:29:39.938943 [CA 4] Center 37 (8~67) winsize 60
8306 09:29:39.942366 [CA 5] Center 36 (7~66) winsize 60
8307 09:29:39.942465
8308 09:29:39.945651 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 09:29:39.945724
8310 09:29:39.948837 [CATrainingPosCal] consider 1 rank data
8311 09:29:39.952058 u2DelayCellTimex100 = 290/100 ps
8312 09:29:39.955254 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8313 09:29:39.961959 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8314 09:29:39.965226 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8315 09:29:39.968445 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 09:29:39.972204 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8317 09:29:39.975154 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8318 09:29:39.975252
8319 09:29:39.978810 CA PerBit enable=1, Macro0, CA PI delay=36
8320 09:29:39.978906
8321 09:29:39.982211 [CBTSetCACLKResult] CA Dly = 36
8322 09:29:39.985649 CS Dly: 10 (0~41)
8323 09:29:39.988441 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 09:29:39.992025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 09:29:39.992104 ==
8326 09:29:39.995336 Dram Type= 6, Freq= 0, CH_1, rank 1
8327 09:29:39.998768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 09:29:39.998840 ==
8329 09:29:40.005168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8330 09:29:40.008309 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8331 09:29:40.015007 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8332 09:29:40.018292 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8333 09:29:40.028916 [CA 0] Center 42 (13~72) winsize 60
8334 09:29:40.032059 [CA 1] Center 41 (12~71) winsize 60
8335 09:29:40.035283 [CA 2] Center 38 (9~68) winsize 60
8336 09:29:40.038455 [CA 3] Center 37 (8~67) winsize 60
8337 09:29:40.041798 [CA 4] Center 38 (9~68) winsize 60
8338 09:29:40.045201 [CA 5] Center 37 (8~67) winsize 60
8339 09:29:40.045300
8340 09:29:40.048441 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8341 09:29:40.048514
8342 09:29:40.051902 [CATrainingPosCal] consider 2 rank data
8343 09:29:40.055544 u2DelayCellTimex100 = 290/100 ps
8344 09:29:40.059078 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8345 09:29:40.065774 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8346 09:29:40.068470 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8347 09:29:40.071765 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8348 09:29:40.075004 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8349 09:29:40.078844 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8350 09:29:40.078975
8351 09:29:40.082090 CA PerBit enable=1, Macro0, CA PI delay=37
8352 09:29:40.082211
8353 09:29:40.085322 [CBTSetCACLKResult] CA Dly = 37
8354 09:29:40.088551 CS Dly: 11 (0~44)
8355 09:29:40.091629 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8356 09:29:40.095176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8357 09:29:40.095351
8358 09:29:40.098664 ----->DramcWriteLeveling(PI) begin...
8359 09:29:40.098867 ==
8360 09:29:40.101505 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 09:29:40.104916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 09:29:40.108770 ==
8363 09:29:40.108852 Write leveling (Byte 0): 25 => 25
8364 09:29:40.111391 Write leveling (Byte 1): 27 => 27
8365 09:29:40.115257 DramcWriteLeveling(PI) end<-----
8366 09:29:40.115338
8367 09:29:40.115401 ==
8368 09:29:40.118380 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 09:29:40.125252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 09:29:40.125328 ==
8371 09:29:40.128512 [Gating] SW mode calibration
8372 09:29:40.134852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8373 09:29:40.138215 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8374 09:29:40.145400 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 09:29:40.148068 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 09:29:40.151440 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8377 09:29:40.154769 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 09:29:40.161450 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 09:29:40.164711 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 09:29:40.168727 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 09:29:40.175009 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 09:29:40.178300 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 09:29:40.182027 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 09:29:40.188348 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8385 09:29:40.191745 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8386 09:29:40.195218 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 09:29:40.201914 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 09:29:40.204996 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 09:29:40.208782 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 09:29:40.215367 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 09:29:40.218945 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 09:29:40.222142 1 6 8 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (1 1)
8393 09:29:40.228943 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8394 09:29:40.231965 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 09:29:40.235264 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 09:29:40.241592 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 09:29:40.244969 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 09:29:40.248304 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 09:29:40.255354 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 09:29:40.258651 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 09:29:40.262222 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8402 09:29:40.268104 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8403 09:29:40.271428 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 09:29:40.274676 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 09:29:40.281916 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 09:29:40.285064 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 09:29:40.288145 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 09:29:40.291504 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 09:29:40.297835 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 09:29:40.301260 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 09:29:40.307990 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 09:29:40.311326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 09:29:40.315182 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 09:29:40.318419 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 09:29:40.324537 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 09:29:40.328267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 09:29:40.331563 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8418 09:29:40.338335 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 09:29:40.341785 Total UI for P1: 0, mck2ui 16
8420 09:29:40.345017 best dqsien dly found for B0: ( 1, 9, 10)
8421 09:29:40.345434 Total UI for P1: 0, mck2ui 16
8422 09:29:40.351446 best dqsien dly found for B1: ( 1, 9, 10)
8423 09:29:40.354578 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8424 09:29:40.357829 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8425 09:29:40.358242
8426 09:29:40.361359 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8427 09:29:40.364595 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8428 09:29:40.367880 [Gating] SW calibration Done
8429 09:29:40.368378 ==
8430 09:29:40.371035 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 09:29:40.375005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 09:29:40.375501 ==
8433 09:29:40.378320 RX Vref Scan: 0
8434 09:29:40.378784
8435 09:29:40.379254 RX Vref 0 -> 0, step: 1
8436 09:29:40.381932
8437 09:29:40.382628 RX Delay 0 -> 252, step: 8
8438 09:29:40.384844 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8439 09:29:40.391442 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8440 09:29:40.394661 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8441 09:29:40.398014 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8442 09:29:40.401836 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8443 09:29:40.405025 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8444 09:29:40.411044 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8445 09:29:40.414288 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8446 09:29:40.418331 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8447 09:29:40.421410 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8448 09:29:40.424557 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8449 09:29:40.431609 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8450 09:29:40.434413 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8451 09:29:40.437653 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8452 09:29:40.440956 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8453 09:29:40.444842 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8454 09:29:40.447835 ==
8455 09:29:40.451066 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 09:29:40.454366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 09:29:40.454788 ==
8458 09:29:40.455118 DQS Delay:
8459 09:29:40.457525 DQS0 = 0, DQS1 = 0
8460 09:29:40.457995 DQM Delay:
8461 09:29:40.461550 DQM0 = 136, DQM1 = 132
8462 09:29:40.462069 DQ Delay:
8463 09:29:40.464450 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8464 09:29:40.467815 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8465 09:29:40.470942 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8466 09:29:40.474172 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8467 09:29:40.474586
8468 09:29:40.474914
8469 09:29:40.475223 ==
8470 09:29:40.477522 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 09:29:40.484034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 09:29:40.484461 ==
8473 09:29:40.484795
8474 09:29:40.485102
8475 09:29:40.485392 TX Vref Scan disable
8476 09:29:40.487919 == TX Byte 0 ==
8477 09:29:40.491286 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8478 09:29:40.497865 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8479 09:29:40.498445 == TX Byte 1 ==
8480 09:29:40.501091 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8481 09:29:40.507783 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8482 09:29:40.508320 ==
8483 09:29:40.511205 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 09:29:40.514424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 09:29:40.515020 ==
8486 09:29:40.526691
8487 09:29:40.529843 TX Vref early break, caculate TX vref
8488 09:29:40.533230 TX Vref=16, minBit 0, minWin=22, winSum=375
8489 09:29:40.536526 TX Vref=18, minBit 0, minWin=23, winSum=385
8490 09:29:40.539553 TX Vref=20, minBit 1, minWin=23, winSum=395
8491 09:29:40.542983 TX Vref=22, minBit 0, minWin=24, winSum=404
8492 09:29:40.546219 TX Vref=24, minBit 1, minWin=24, winSum=418
8493 09:29:40.552812 TX Vref=26, minBit 0, minWin=24, winSum=420
8494 09:29:40.556730 TX Vref=28, minBit 2, minWin=25, winSum=429
8495 09:29:40.559912 TX Vref=30, minBit 0, minWin=25, winSum=422
8496 09:29:40.562767 TX Vref=32, minBit 0, minWin=25, winSum=418
8497 09:29:40.566471 TX Vref=34, minBit 2, minWin=23, winSum=401
8498 09:29:40.573306 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 28
8499 09:29:40.573841
8500 09:29:40.576375 Final TX Range 0 Vref 28
8501 09:29:40.576907
8502 09:29:40.577399 ==
8503 09:29:40.579710 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 09:29:40.582741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 09:29:40.583359 ==
8506 09:29:40.583880
8507 09:29:40.584353
8508 09:29:40.586535 TX Vref Scan disable
8509 09:29:40.592955 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8510 09:29:40.593385 == TX Byte 0 ==
8511 09:29:40.596084 u2DelayCellOfst[0]=16 cells (5 PI)
8512 09:29:40.599500 u2DelayCellOfst[1]=10 cells (3 PI)
8513 09:29:40.602950 u2DelayCellOfst[2]=0 cells (0 PI)
8514 09:29:40.606337 u2DelayCellOfst[3]=6 cells (2 PI)
8515 09:29:40.609504 u2DelayCellOfst[4]=6 cells (2 PI)
8516 09:29:40.612924 u2DelayCellOfst[5]=20 cells (6 PI)
8517 09:29:40.616333 u2DelayCellOfst[6]=20 cells (6 PI)
8518 09:29:40.616785 u2DelayCellOfst[7]=6 cells (2 PI)
8519 09:29:40.622764 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8520 09:29:40.625906 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 09:29:40.629066 == TX Byte 1 ==
8522 09:29:40.629477 u2DelayCellOfst[8]=0 cells (0 PI)
8523 09:29:40.632480 u2DelayCellOfst[9]=3 cells (1 PI)
8524 09:29:40.635684 u2DelayCellOfst[10]=10 cells (3 PI)
8525 09:29:40.639496 u2DelayCellOfst[11]=3 cells (1 PI)
8526 09:29:40.642731 u2DelayCellOfst[12]=13 cells (4 PI)
8527 09:29:40.646048 u2DelayCellOfst[13]=16 cells (5 PI)
8528 09:29:40.649216 u2DelayCellOfst[14]=16 cells (5 PI)
8529 09:29:40.652459 u2DelayCellOfst[15]=16 cells (5 PI)
8530 09:29:40.655546 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8531 09:29:40.662350 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8532 09:29:40.662488 DramC Write-DBI on
8533 09:29:40.662557 ==
8534 09:29:40.665517 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 09:29:40.668658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 09:29:40.672218 ==
8537 09:29:40.672300
8538 09:29:40.672363
8539 09:29:40.672421 TX Vref Scan disable
8540 09:29:40.675243 == TX Byte 0 ==
8541 09:29:40.678881 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8542 09:29:40.682239 == TX Byte 1 ==
8543 09:29:40.685478 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8544 09:29:40.688721 DramC Write-DBI off
8545 09:29:40.688817
8546 09:29:40.688929 [DATLAT]
8547 09:29:40.689023 Freq=1600, CH1 RK0
8548 09:29:40.689096
8549 09:29:40.691617 DATLAT Default: 0xf
8550 09:29:40.695016 0, 0xFFFF, sum = 0
8551 09:29:40.695099 1, 0xFFFF, sum = 0
8552 09:29:40.698346 2, 0xFFFF, sum = 0
8553 09:29:40.698511 3, 0xFFFF, sum = 0
8554 09:29:40.702041 4, 0xFFFF, sum = 0
8555 09:29:40.702141 5, 0xFFFF, sum = 0
8556 09:29:40.705212 6, 0xFFFF, sum = 0
8557 09:29:40.705294 7, 0xFFFF, sum = 0
8558 09:29:40.708212 8, 0xFFFF, sum = 0
8559 09:29:40.708294 9, 0xFFFF, sum = 0
8560 09:29:40.712050 10, 0xFFFF, sum = 0
8561 09:29:40.712137 11, 0xFFFF, sum = 0
8562 09:29:40.714815 12, 0xFFFF, sum = 0
8563 09:29:40.714897 13, 0xFFFF, sum = 0
8564 09:29:40.718151 14, 0x0, sum = 1
8565 09:29:40.718232 15, 0x0, sum = 2
8566 09:29:40.721450 16, 0x0, sum = 3
8567 09:29:40.721531 17, 0x0, sum = 4
8568 09:29:40.724663 best_step = 15
8569 09:29:40.724747
8570 09:29:40.724811 ==
8571 09:29:40.728002 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 09:29:40.731277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 09:29:40.731386 ==
8574 09:29:40.734544 RX Vref Scan: 1
8575 09:29:40.734624
8576 09:29:40.734686 Set Vref Range= 24 -> 127
8577 09:29:40.734744
8578 09:29:40.737862 RX Vref 24 -> 127, step: 1
8579 09:29:40.737945
8580 09:29:40.741202 RX Delay 27 -> 252, step: 4
8581 09:29:40.741282
8582 09:29:40.745016 Set Vref, RX VrefLevel [Byte0]: 24
8583 09:29:40.748117 [Byte1]: 24
8584 09:29:40.748223
8585 09:29:40.751519 Set Vref, RX VrefLevel [Byte0]: 25
8586 09:29:40.754765 [Byte1]: 25
8587 09:29:40.758031
8588 09:29:40.758128 Set Vref, RX VrefLevel [Byte0]: 26
8589 09:29:40.761112 [Byte1]: 26
8590 09:29:40.765842
8591 09:29:40.765938 Set Vref, RX VrefLevel [Byte0]: 27
8592 09:29:40.769041 [Byte1]: 27
8593 09:29:40.773030
8594 09:29:40.773122 Set Vref, RX VrefLevel [Byte0]: 28
8595 09:29:40.776355 [Byte1]: 28
8596 09:29:40.780680
8597 09:29:40.780759 Set Vref, RX VrefLevel [Byte0]: 29
8598 09:29:40.783692 [Byte1]: 29
8599 09:29:40.787816
8600 09:29:40.787895 Set Vref, RX VrefLevel [Byte0]: 30
8601 09:29:40.791348 [Byte1]: 30
8602 09:29:40.795857
8603 09:29:40.795938 Set Vref, RX VrefLevel [Byte0]: 31
8604 09:29:40.798934 [Byte1]: 31
8605 09:29:40.803050
8606 09:29:40.803131 Set Vref, RX VrefLevel [Byte0]: 32
8607 09:29:40.806658 [Byte1]: 32
8608 09:29:40.810934
8609 09:29:40.811018 Set Vref, RX VrefLevel [Byte0]: 33
8610 09:29:40.814213 [Byte1]: 33
8611 09:29:40.818463
8612 09:29:40.818543 Set Vref, RX VrefLevel [Byte0]: 34
8613 09:29:40.821784 [Byte1]: 34
8614 09:29:40.825855
8615 09:29:40.825935 Set Vref, RX VrefLevel [Byte0]: 35
8616 09:29:40.829155 [Byte1]: 35
8617 09:29:40.832960
8618 09:29:40.833040 Set Vref, RX VrefLevel [Byte0]: 36
8619 09:29:40.836792 [Byte1]: 36
8620 09:29:40.840797
8621 09:29:40.840878 Set Vref, RX VrefLevel [Byte0]: 37
8622 09:29:40.844102 [Byte1]: 37
8623 09:29:40.848597
8624 09:29:40.848677 Set Vref, RX VrefLevel [Byte0]: 38
8625 09:29:40.851817 [Byte1]: 38
8626 09:29:40.855610
8627 09:29:40.855702 Set Vref, RX VrefLevel [Byte0]: 39
8628 09:29:40.859062 [Byte1]: 39
8629 09:29:40.863067
8630 09:29:40.863173 Set Vref, RX VrefLevel [Byte0]: 40
8631 09:29:40.867093 [Byte1]: 40
8632 09:29:40.870959
8633 09:29:40.871038 Set Vref, RX VrefLevel [Byte0]: 41
8634 09:29:40.874214 [Byte1]: 41
8635 09:29:40.878235
8636 09:29:40.878315 Set Vref, RX VrefLevel [Byte0]: 42
8637 09:29:40.881633 [Byte1]: 42
8638 09:29:40.886198
8639 09:29:40.886306 Set Vref, RX VrefLevel [Byte0]: 43
8640 09:29:40.889468 [Byte1]: 43
8641 09:29:40.893373
8642 09:29:40.893479 Set Vref, RX VrefLevel [Byte0]: 44
8643 09:29:40.896607 [Byte1]: 44
8644 09:29:40.900917
8645 09:29:40.900997 Set Vref, RX VrefLevel [Byte0]: 45
8646 09:29:40.904455 [Byte1]: 45
8647 09:29:40.908856
8648 09:29:40.908936 Set Vref, RX VrefLevel [Byte0]: 46
8649 09:29:40.912039 [Byte1]: 46
8650 09:29:40.915900
8651 09:29:40.915981 Set Vref, RX VrefLevel [Byte0]: 47
8652 09:29:40.919534 [Byte1]: 47
8653 09:29:40.923518
8654 09:29:40.923624 Set Vref, RX VrefLevel [Byte0]: 48
8655 09:29:40.927132 [Byte1]: 48
8656 09:29:40.931176
8657 09:29:40.931270 Set Vref, RX VrefLevel [Byte0]: 49
8658 09:29:40.934397 [Byte1]: 49
8659 09:29:40.938786
8660 09:29:40.938867 Set Vref, RX VrefLevel [Byte0]: 50
8661 09:29:40.941965 [Byte1]: 50
8662 09:29:40.946066
8663 09:29:40.946146 Set Vref, RX VrefLevel [Byte0]: 51
8664 09:29:40.949477 [Byte1]: 51
8665 09:29:40.953906
8666 09:29:40.954015 Set Vref, RX VrefLevel [Byte0]: 52
8667 09:29:40.957208 [Byte1]: 52
8668 09:29:40.961263
8669 09:29:40.961345 Set Vref, RX VrefLevel [Byte0]: 53
8670 09:29:40.964630 [Byte1]: 53
8671 09:29:40.968698
8672 09:29:40.968779 Set Vref, RX VrefLevel [Byte0]: 54
8673 09:29:40.971874 [Byte1]: 54
8674 09:29:40.976424
8675 09:29:40.976505 Set Vref, RX VrefLevel [Byte0]: 55
8676 09:29:40.979776 [Byte1]: 55
8677 09:29:40.983868
8678 09:29:40.983949 Set Vref, RX VrefLevel [Byte0]: 56
8679 09:29:40.987178 [Byte1]: 56
8680 09:29:40.991588
8681 09:29:40.991692 Set Vref, RX VrefLevel [Byte0]: 57
8682 09:29:40.995105 [Byte1]: 57
8683 09:29:40.999104
8684 09:29:40.999184 Set Vref, RX VrefLevel [Byte0]: 58
8685 09:29:41.002381 [Byte1]: 58
8686 09:29:41.006228
8687 09:29:41.006309 Set Vref, RX VrefLevel [Byte0]: 59
8688 09:29:41.009940 [Byte1]: 59
8689 09:29:41.014186
8690 09:29:41.014294 Set Vref, RX VrefLevel [Byte0]: 60
8691 09:29:41.017246 [Byte1]: 60
8692 09:29:41.021839
8693 09:29:41.021927 Set Vref, RX VrefLevel [Byte0]: 61
8694 09:29:41.025101 [Byte1]: 61
8695 09:29:41.028802
8696 09:29:41.028875 Set Vref, RX VrefLevel [Byte0]: 62
8697 09:29:41.032409 [Byte1]: 62
8698 09:29:41.036561
8699 09:29:41.036655 Set Vref, RX VrefLevel [Byte0]: 63
8700 09:29:41.039977 [Byte1]: 63
8701 09:29:41.044151
8702 09:29:41.044224 Set Vref, RX VrefLevel [Byte0]: 64
8703 09:29:41.047545 [Byte1]: 64
8704 09:29:41.051790
8705 09:29:41.051872 Set Vref, RX VrefLevel [Byte0]: 65
8706 09:29:41.054816 [Byte1]: 65
8707 09:29:41.059026
8708 09:29:41.059133 Set Vref, RX VrefLevel [Byte0]: 66
8709 09:29:41.062685 [Byte1]: 66
8710 09:29:41.066453
8711 09:29:41.066560 Set Vref, RX VrefLevel [Byte0]: 67
8712 09:29:41.069910 [Byte1]: 67
8713 09:29:41.074507
8714 09:29:41.074581 Set Vref, RX VrefLevel [Byte0]: 68
8715 09:29:41.077905 [Byte1]: 68
8716 09:29:41.081891
8717 09:29:41.081994 Set Vref, RX VrefLevel [Byte0]: 69
8718 09:29:41.085239 [Byte1]: 69
8719 09:29:41.089338
8720 09:29:41.089439 Set Vref, RX VrefLevel [Byte0]: 70
8721 09:29:41.092551 [Byte1]: 70
8722 09:29:41.096676
8723 09:29:41.096758 Set Vref, RX VrefLevel [Byte0]: 71
8724 09:29:41.099974 [Byte1]: 71
8725 09:29:41.104659
8726 09:29:41.104750 Set Vref, RX VrefLevel [Byte0]: 72
8727 09:29:41.107961 [Byte1]: 72
8728 09:29:41.111871
8729 09:29:41.111969 Set Vref, RX VrefLevel [Byte0]: 73
8730 09:29:41.114918 [Byte1]: 73
8731 09:29:41.119334
8732 09:29:41.119451 Set Vref, RX VrefLevel [Byte0]: 74
8733 09:29:41.122534 [Byte1]: 74
8734 09:29:41.126996
8735 09:29:41.127089 Set Vref, RX VrefLevel [Byte0]: 75
8736 09:29:41.130168 [Byte1]: 75
8737 09:29:41.134890
8738 09:29:41.135005 Set Vref, RX VrefLevel [Byte0]: 76
8739 09:29:41.138170 [Byte1]: 76
8740 09:29:41.142061
8741 09:29:41.142143 Final RX Vref Byte 0 = 59 to rank0
8742 09:29:41.145721 Final RX Vref Byte 1 = 56 to rank0
8743 09:29:41.148880 Final RX Vref Byte 0 = 59 to rank1
8744 09:29:41.152084 Final RX Vref Byte 1 = 56 to rank1==
8745 09:29:41.155284 Dram Type= 6, Freq= 0, CH_1, rank 0
8746 09:29:41.162121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 09:29:41.162226 ==
8748 09:29:41.162318 DQS Delay:
8749 09:29:41.162415 DQS0 = 0, DQS1 = 0
8750 09:29:41.165558 DQM Delay:
8751 09:29:41.165663 DQM0 = 134, DQM1 = 131
8752 09:29:41.168519 DQ Delay:
8753 09:29:41.171797 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8754 09:29:41.175356 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8755 09:29:41.178599 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8756 09:29:41.182007 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8757 09:29:41.182108
8758 09:29:41.182198
8759 09:29:41.182287
8760 09:29:41.185214 [DramC_TX_OE_Calibration] TA2
8761 09:29:41.188510 Original DQ_B0 (3 6) =30, OEN = 27
8762 09:29:41.191937 Original DQ_B1 (3 6) =30, OEN = 27
8763 09:29:41.195183 24, 0x0, End_B0=24 End_B1=24
8764 09:29:41.195268 25, 0x0, End_B0=25 End_B1=25
8765 09:29:41.198654 26, 0x0, End_B0=26 End_B1=26
8766 09:29:41.201898 27, 0x0, End_B0=27 End_B1=27
8767 09:29:41.205242 28, 0x0, End_B0=28 End_B1=28
8768 09:29:41.205354 29, 0x0, End_B0=29 End_B1=29
8769 09:29:41.208639 30, 0x0, End_B0=30 End_B1=30
8770 09:29:41.211991 31, 0x4141, End_B0=30 End_B1=30
8771 09:29:41.215280 Byte0 end_step=30 best_step=27
8772 09:29:41.218470 Byte1 end_step=30 best_step=27
8773 09:29:41.221628 Byte0 TX OE(2T, 0.5T) = (3, 3)
8774 09:29:41.221711 Byte1 TX OE(2T, 0.5T) = (3, 3)
8775 09:29:41.225557
8776 09:29:41.225689
8777 09:29:41.232210 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8778 09:29:41.235291 CH1 RK0: MR19=303, MR18=1826
8779 09:29:41.242005 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8780 09:29:41.242140
8781 09:29:41.245375 ----->DramcWriteLeveling(PI) begin...
8782 09:29:41.245459 ==
8783 09:29:41.248750 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 09:29:41.251916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 09:29:41.251999 ==
8786 09:29:41.254865 Write leveling (Byte 0): 24 => 24
8787 09:29:41.258653 Write leveling (Byte 1): 29 => 29
8788 09:29:41.261894 DramcWriteLeveling(PI) end<-----
8789 09:29:41.262027
8790 09:29:41.262144 ==
8791 09:29:41.265246 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 09:29:41.268527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 09:29:41.268612 ==
8794 09:29:41.271818 [Gating] SW mode calibration
8795 09:29:41.278590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8796 09:29:41.284940 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8797 09:29:41.288375 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 09:29:41.291845 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 09:29:41.298609 1 4 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8800 09:29:41.301710 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8801 09:29:41.305062 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 09:29:41.311736 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 09:29:41.315180 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 09:29:41.317878 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 09:29:41.325001 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 09:29:41.328303 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8807 09:29:41.331593 1 5 8 | B1->B0 | 2929 3434 | 1 1 | (1 0) (1 0)
8808 09:29:41.338339 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8809 09:29:41.341569 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 09:29:41.344741 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 09:29:41.351455 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 09:29:41.354833 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 09:29:41.358009 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 09:29:41.364823 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 09:29:41.368128 1 6 8 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)
8816 09:29:41.371285 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 09:29:41.378301 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 09:29:41.381584 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 09:29:41.385025 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 09:29:41.391126 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 09:29:41.394336 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 09:29:41.398024 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 09:29:41.401101 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8824 09:29:41.408138 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8825 09:29:41.411330 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 09:29:41.414600 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 09:29:41.421364 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 09:29:41.424641 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 09:29:41.427747 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 09:29:41.434320 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 09:29:41.437812 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 09:29:41.441145 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 09:29:41.447830 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 09:29:41.451005 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 09:29:41.454339 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 09:29:41.461207 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 09:29:41.464369 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 09:29:41.467556 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8839 09:29:41.474225 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8840 09:29:41.477446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8841 09:29:41.481041 Total UI for P1: 0, mck2ui 16
8842 09:29:41.484106 best dqsien dly found for B1: ( 1, 9, 6)
8843 09:29:41.487274 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 09:29:41.490733 Total UI for P1: 0, mck2ui 16
8845 09:29:41.494028 best dqsien dly found for B0: ( 1, 9, 10)
8846 09:29:41.497446 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8847 09:29:41.500886 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8848 09:29:41.500995
8849 09:29:41.507172 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8850 09:29:41.511017 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8851 09:29:41.511097 [Gating] SW calibration Done
8852 09:29:41.514381 ==
8853 09:29:41.514462 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 09:29:41.520968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 09:29:41.521049 ==
8856 09:29:41.521113 RX Vref Scan: 0
8857 09:29:41.521172
8858 09:29:41.524211 RX Vref 0 -> 0, step: 1
8859 09:29:41.524292
8860 09:29:41.527438 RX Delay 0 -> 252, step: 8
8861 09:29:41.530507 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8862 09:29:41.534389 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8863 09:29:41.537500 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8864 09:29:41.544106 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8865 09:29:41.547436 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8866 09:29:41.550725 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8867 09:29:41.554114 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8868 09:29:41.557359 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8869 09:29:41.564129 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8870 09:29:41.567456 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8871 09:29:41.570839 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8872 09:29:41.573979 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8873 09:29:41.577181 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8874 09:29:41.583943 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8875 09:29:41.587189 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8876 09:29:41.590398 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8877 09:29:41.590490 ==
8878 09:29:41.593415 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 09:29:41.597069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 09:29:41.597147 ==
8881 09:29:41.600335 DQS Delay:
8882 09:29:41.600409 DQS0 = 0, DQS1 = 0
8883 09:29:41.603631 DQM Delay:
8884 09:29:41.603741 DQM0 = 136, DQM1 = 133
8885 09:29:41.606893 DQ Delay:
8886 09:29:41.610577 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8887 09:29:41.613630 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8888 09:29:41.616946 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8889 09:29:41.620229 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8890 09:29:41.620302
8891 09:29:41.620372
8892 09:29:41.620457 ==
8893 09:29:41.623462 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 09:29:41.627364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 09:29:41.627460 ==
8896 09:29:41.627546
8897 09:29:41.627629
8898 09:29:41.630573 TX Vref Scan disable
8899 09:29:41.633844 == TX Byte 0 ==
8900 09:29:41.636957 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8901 09:29:41.640112 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8902 09:29:41.643856 == TX Byte 1 ==
8903 09:29:41.647161 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8904 09:29:41.650425 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8905 09:29:41.650519 ==
8906 09:29:41.653976 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 09:29:41.657147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 09:29:41.659975 ==
8909 09:29:41.672898
8910 09:29:41.675872 TX Vref early break, caculate TX vref
8911 09:29:41.679154 TX Vref=16, minBit 0, minWin=22, winSum=380
8912 09:29:41.683105 TX Vref=18, minBit 0, minWin=23, winSum=387
8913 09:29:41.685780 TX Vref=20, minBit 0, minWin=24, winSum=400
8914 09:29:41.689711 TX Vref=22, minBit 2, minWin=24, winSum=403
8915 09:29:41.693073 TX Vref=24, minBit 0, minWin=24, winSum=417
8916 09:29:41.699545 TX Vref=26, minBit 0, minWin=25, winSum=422
8917 09:29:41.702690 TX Vref=28, minBit 1, minWin=25, winSum=426
8918 09:29:41.705770 TX Vref=30, minBit 0, minWin=25, winSum=418
8919 09:29:41.709595 TX Vref=32, minBit 0, minWin=24, winSum=411
8920 09:29:41.712382 TX Vref=34, minBit 0, minWin=23, winSum=404
8921 09:29:41.716235 TX Vref=36, minBit 0, minWin=23, winSum=393
8922 09:29:41.722678 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8923 09:29:41.722810
8924 09:29:41.726003 Final TX Range 0 Vref 28
8925 09:29:41.726113
8926 09:29:41.726209 ==
8927 09:29:41.729812 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 09:29:41.732703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 09:29:41.732793 ==
8930 09:29:41.732887
8931 09:29:41.732980
8932 09:29:41.735898 TX Vref Scan disable
8933 09:29:41.742907 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8934 09:29:41.742989 == TX Byte 0 ==
8935 09:29:41.746316 u2DelayCellOfst[0]=20 cells (6 PI)
8936 09:29:41.749355 u2DelayCellOfst[1]=13 cells (4 PI)
8937 09:29:41.752390 u2DelayCellOfst[2]=0 cells (0 PI)
8938 09:29:41.755873 u2DelayCellOfst[3]=6 cells (2 PI)
8939 09:29:41.759091 u2DelayCellOfst[4]=6 cells (2 PI)
8940 09:29:41.762379 u2DelayCellOfst[5]=20 cells (6 PI)
8941 09:29:41.765811 u2DelayCellOfst[6]=20 cells (6 PI)
8942 09:29:41.769218 u2DelayCellOfst[7]=6 cells (2 PI)
8943 09:29:41.772771 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8944 09:29:41.776161 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8945 09:29:41.779428 == TX Byte 1 ==
8946 09:29:41.779511 u2DelayCellOfst[8]=0 cells (0 PI)
8947 09:29:41.782669 u2DelayCellOfst[9]=6 cells (2 PI)
8948 09:29:41.785875 u2DelayCellOfst[10]=13 cells (4 PI)
8949 09:29:41.789099 u2DelayCellOfst[11]=6 cells (2 PI)
8950 09:29:41.792401 u2DelayCellOfst[12]=16 cells (5 PI)
8951 09:29:41.795664 u2DelayCellOfst[13]=16 cells (5 PI)
8952 09:29:41.799015 u2DelayCellOfst[14]=20 cells (6 PI)
8953 09:29:41.802325 u2DelayCellOfst[15]=20 cells (6 PI)
8954 09:29:41.805488 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8955 09:29:41.812610 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8956 09:29:41.812721 DramC Write-DBI on
8957 09:29:41.812819 ==
8958 09:29:41.815869 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 09:29:41.822104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 09:29:41.822187 ==
8961 09:29:41.822252
8962 09:29:41.822312
8963 09:29:41.822369 TX Vref Scan disable
8964 09:29:41.826178 == TX Byte 0 ==
8965 09:29:41.829631 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8966 09:29:41.832484 == TX Byte 1 ==
8967 09:29:41.835831 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8968 09:29:41.839154 DramC Write-DBI off
8969 09:29:41.839252
8970 09:29:41.839343 [DATLAT]
8971 09:29:41.839438 Freq=1600, CH1 RK1
8972 09:29:41.839525
8973 09:29:41.842569 DATLAT Default: 0xf
8974 09:29:41.842648 0, 0xFFFF, sum = 0
8975 09:29:41.845914 1, 0xFFFF, sum = 0
8976 09:29:41.846017 2, 0xFFFF, sum = 0
8977 09:29:41.849152 3, 0xFFFF, sum = 0
8978 09:29:41.852524 4, 0xFFFF, sum = 0
8979 09:29:41.852642 5, 0xFFFF, sum = 0
8980 09:29:41.855802 6, 0xFFFF, sum = 0
8981 09:29:41.855914 7, 0xFFFF, sum = 0
8982 09:29:41.858964 8, 0xFFFF, sum = 0
8983 09:29:41.859037 9, 0xFFFF, sum = 0
8984 09:29:41.862659 10, 0xFFFF, sum = 0
8985 09:29:41.862773 11, 0xFFFF, sum = 0
8986 09:29:41.865601 12, 0xFFFF, sum = 0
8987 09:29:41.865685 13, 0xFFFF, sum = 0
8988 09:29:41.869357 14, 0x0, sum = 1
8989 09:29:41.869440 15, 0x0, sum = 2
8990 09:29:41.872707 16, 0x0, sum = 3
8991 09:29:41.872790 17, 0x0, sum = 4
8992 09:29:41.876075 best_step = 15
8993 09:29:41.876158
8994 09:29:41.876224 ==
8995 09:29:41.878825 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 09:29:41.882269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 09:29:41.882340 ==
8998 09:29:41.885513 RX Vref Scan: 0
8999 09:29:41.885587
9000 09:29:41.885649 RX Vref 0 -> 0, step: 1
9001 09:29:41.885707
9002 09:29:41.888842 RX Delay 19 -> 252, step: 4
9003 09:29:41.892615 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9004 09:29:41.899137 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
9005 09:29:41.902350 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9006 09:29:41.905679 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9007 09:29:41.908987 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9008 09:29:41.912373 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9009 09:29:41.915763 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9010 09:29:41.922320 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9011 09:29:41.925608 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9012 09:29:41.928903 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9013 09:29:41.932291 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9014 09:29:41.938633 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9015 09:29:41.942133 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9016 09:29:41.945444 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9017 09:29:41.948758 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9018 09:29:41.951751 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9019 09:29:41.955566 ==
9020 09:29:41.955693 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 09:29:41.962204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 09:29:41.962288 ==
9023 09:29:41.962353 DQS Delay:
9024 09:29:41.965521 DQS0 = 0, DQS1 = 0
9025 09:29:41.965604 DQM Delay:
9026 09:29:41.968919 DQM0 = 134, DQM1 = 130
9027 09:29:41.969002 DQ Delay:
9028 09:29:41.972094 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
9029 09:29:41.975052 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9030 09:29:41.978531 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9031 09:29:41.981802 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9032 09:29:41.981887
9033 09:29:41.981988
9034 09:29:41.982082
9035 09:29:41.985249 [DramC_TX_OE_Calibration] TA2
9036 09:29:41.988670 Original DQ_B0 (3 6) =30, OEN = 27
9037 09:29:41.991866 Original DQ_B1 (3 6) =30, OEN = 27
9038 09:29:41.995071 24, 0x0, End_B0=24 End_B1=24
9039 09:29:41.998492 25, 0x0, End_B0=25 End_B1=25
9040 09:29:41.998576 26, 0x0, End_B0=26 End_B1=26
9041 09:29:42.001690 27, 0x0, End_B0=27 End_B1=27
9042 09:29:42.005015 28, 0x0, End_B0=28 End_B1=28
9043 09:29:42.009008 29, 0x0, End_B0=29 End_B1=29
9044 09:29:42.009093 30, 0x0, End_B0=30 End_B1=30
9045 09:29:42.012167 31, 0x4141, End_B0=30 End_B1=30
9046 09:29:42.015387 Byte0 end_step=30 best_step=27
9047 09:29:42.018767 Byte1 end_step=30 best_step=27
9048 09:29:42.021969 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 09:29:42.025196 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 09:29:42.025279
9051 09:29:42.025344
9052 09:29:42.032268 [DQSOSCAuto] RK1, (LSB)MR18= 0x260b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
9053 09:29:42.034940 CH1 RK1: MR19=303, MR18=260B
9054 09:29:42.041681 CH1_RK1: MR19=0x303, MR18=0x260B, DQSOSC=390, MR23=63, INC=24, DEC=16
9055 09:29:42.045024 [RxdqsGatingPostProcess] freq 1600
9056 09:29:42.048359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 09:29:42.052066 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 09:29:42.055037 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 09:29:42.058458 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 09:29:42.061941 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 09:29:42.065109 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 09:29:42.068654 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 09:29:42.071599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 09:29:42.075005 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 09:29:42.078396 Pre-setting of DQS Precalculation
9066 09:29:42.081617 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 09:29:42.088379 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 09:29:42.095017 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 09:29:42.098324
9070 09:29:42.098432
9071 09:29:42.098525 [Calibration Summary] 3200 Mbps
9072 09:29:42.101843 CH 0, Rank 0
9073 09:29:42.101950 SW Impedance : PASS
9074 09:29:42.105043 DUTY Scan : NO K
9075 09:29:42.108286 ZQ Calibration : PASS
9076 09:29:42.108359 Jitter Meter : NO K
9077 09:29:42.111520 CBT Training : PASS
9078 09:29:42.114929 Write leveling : PASS
9079 09:29:42.115003 RX DQS gating : PASS
9080 09:29:42.118790 RX DQ/DQS(RDDQC) : PASS
9081 09:29:42.121517 TX DQ/DQS : PASS
9082 09:29:42.121589 RX DATLAT : PASS
9083 09:29:42.124826 RX DQ/DQS(Engine): PASS
9084 09:29:42.128147 TX OE : PASS
9085 09:29:42.128253 All Pass.
9086 09:29:42.128343
9087 09:29:42.128436 CH 0, Rank 1
9088 09:29:42.131575 SW Impedance : PASS
9089 09:29:42.134824 DUTY Scan : NO K
9090 09:29:42.134929 ZQ Calibration : PASS
9091 09:29:42.138577 Jitter Meter : NO K
9092 09:29:42.141933 CBT Training : PASS
9093 09:29:42.142014 Write leveling : PASS
9094 09:29:42.145187 RX DQS gating : PASS
9095 09:29:42.145272 RX DQ/DQS(RDDQC) : PASS
9096 09:29:42.148590 TX DQ/DQS : PASS
9097 09:29:42.152061 RX DATLAT : PASS
9098 09:29:42.152144 RX DQ/DQS(Engine): PASS
9099 09:29:42.155259 TX OE : PASS
9100 09:29:42.155341 All Pass.
9101 09:29:42.155406
9102 09:29:42.158553 CH 1, Rank 0
9103 09:29:42.158635 SW Impedance : PASS
9104 09:29:42.161942 DUTY Scan : NO K
9105 09:29:42.165201 ZQ Calibration : PASS
9106 09:29:42.165283 Jitter Meter : NO K
9107 09:29:42.168232 CBT Training : PASS
9108 09:29:42.171630 Write leveling : PASS
9109 09:29:42.171721 RX DQS gating : PASS
9110 09:29:42.174713 RX DQ/DQS(RDDQC) : PASS
9111 09:29:42.177989 TX DQ/DQS : PASS
9112 09:29:42.178071 RX DATLAT : PASS
9113 09:29:42.181402 RX DQ/DQS(Engine): PASS
9114 09:29:42.185097 TX OE : PASS
9115 09:29:42.185191 All Pass.
9116 09:29:42.185271
9117 09:29:42.185330 CH 1, Rank 1
9118 09:29:42.188453 SW Impedance : PASS
9119 09:29:42.191812 DUTY Scan : NO K
9120 09:29:42.191893 ZQ Calibration : PASS
9121 09:29:42.194979 Jitter Meter : NO K
9122 09:29:42.197986 CBT Training : PASS
9123 09:29:42.198102 Write leveling : PASS
9124 09:29:42.201825 RX DQS gating : PASS
9125 09:29:42.201915 RX DQ/DQS(RDDQC) : PASS
9126 09:29:42.205065 TX DQ/DQS : PASS
9127 09:29:42.208106 RX DATLAT : PASS
9128 09:29:42.208187 RX DQ/DQS(Engine): PASS
9129 09:29:42.211823 TX OE : PASS
9130 09:29:42.211904 All Pass.
9131 09:29:42.211967
9132 09:29:42.214751 DramC Write-DBI on
9133 09:29:42.218236 PER_BANK_REFRESH: Hybrid Mode
9134 09:29:42.218366 TX_TRACKING: ON
9135 09:29:42.228096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 09:29:42.234985 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 09:29:42.241362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 09:29:42.244753 [FAST_K] Save calibration result to emmc
9139 09:29:42.248189 sync common calibartion params.
9140 09:29:42.251719 sync cbt_mode0:1, 1:1
9141 09:29:42.254921 dram_init: ddr_geometry: 2
9142 09:29:42.255005 dram_init: ddr_geometry: 2
9143 09:29:42.258395 dram_init: ddr_geometry: 2
9144 09:29:42.261756 0:dram_rank_size:100000000
9145 09:29:42.264460 1:dram_rank_size:100000000
9146 09:29:42.267805 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 09:29:42.271107 DFS_SHUFFLE_HW_MODE: ON
9148 09:29:42.274455 dramc_set_vcore_voltage set vcore to 725000
9149 09:29:42.278089 Read voltage for 1600, 0
9150 09:29:42.278187 Vio18 = 0
9151 09:29:42.278289 Vcore = 725000
9152 09:29:42.281000 Vdram = 0
9153 09:29:42.281104 Vddq = 0
9154 09:29:42.281209 Vmddr = 0
9155 09:29:42.284332 switch to 3200 Mbps bootup
9156 09:29:42.288276 [DramcRunTimeConfig]
9157 09:29:42.288350 PHYPLL
9158 09:29:42.288432 DPM_CONTROL_AFTERK: ON
9159 09:29:42.291401 PER_BANK_REFRESH: ON
9160 09:29:42.294328 REFRESH_OVERHEAD_REDUCTION: ON
9161 09:29:42.294414 CMD_PICG_NEW_MODE: OFF
9162 09:29:42.297684 XRTWTW_NEW_MODE: ON
9163 09:29:42.301031 XRTRTR_NEW_MODE: ON
9164 09:29:42.301114 TX_TRACKING: ON
9165 09:29:42.301179 RDSEL_TRACKING: OFF
9166 09:29:42.304816 DQS Precalculation for DVFS: ON
9167 09:29:42.307922 RX_TRACKING: OFF
9168 09:29:42.308004 HW_GATING DBG: ON
9169 09:29:42.311203 ZQCS_ENABLE_LP4: ON
9170 09:29:42.311285 RX_PICG_NEW_MODE: ON
9171 09:29:42.314460 TX_PICG_NEW_MODE: ON
9172 09:29:42.317810 ENABLE_RX_DCM_DPHY: ON
9173 09:29:42.320923 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 09:29:42.321006 DUMMY_READ_FOR_TRACKING: OFF
9175 09:29:42.324049 !!! SPM_CONTROL_AFTERK: OFF
9176 09:29:42.327773 !!! SPM could not control APHY
9177 09:29:42.331055 IMPEDANCE_TRACKING: ON
9178 09:29:42.331138 TEMP_SENSOR: ON
9179 09:29:42.333943 HW_SAVE_FOR_SR: OFF
9180 09:29:42.334025 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 09:29:42.341072 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 09:29:42.341177 Read ODT Tracking: ON
9183 09:29:42.344049 Refresh Rate DeBounce: ON
9184 09:29:42.347852 DFS_NO_QUEUE_FLUSH: ON
9185 09:29:42.347935 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 09:29:42.351019 ENABLE_DFS_RUNTIME_MRW: OFF
9187 09:29:42.354393 DDR_RESERVE_NEW_MODE: ON
9188 09:29:42.357779 MR_CBT_SWITCH_FREQ: ON
9189 09:29:42.357861 =========================
9190 09:29:42.376930 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 09:29:42.380208 dram_init: ddr_geometry: 2
9192 09:29:42.398415 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 09:29:42.401775 dram_init: dram init end (result: 0)
9194 09:29:42.408775 DRAM-K: Full calibration passed in 24429 msecs
9195 09:29:42.411847 MRC: failed to locate region type 0.
9196 09:29:42.412006 DRAM rank0 size:0x100000000,
9197 09:29:42.415052 DRAM rank1 size=0x100000000
9198 09:29:42.425501 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 09:29:42.431761 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 09:29:42.438893 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 09:29:42.445619 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 09:29:42.448677 DRAM rank0 size:0x100000000,
9203 09:29:42.451994 DRAM rank1 size=0x100000000
9204 09:29:42.452072 CBMEM:
9205 09:29:42.455711 IMD: root @ 0xfffff000 254 entries.
9206 09:29:42.458507 IMD: root @ 0xffffec00 62 entries.
9207 09:29:42.462221 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 09:29:42.465376 WARNING: RO_VPD is uninitialized or empty.
9209 09:29:42.471981 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 09:29:42.478679 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 09:29:42.491314 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9212 09:29:42.502726 BS: romstage times (exec / console): total (unknown) / 23964 ms
9213 09:29:42.502825
9214 09:29:42.502891
9215 09:29:42.512800 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 09:29:42.516075 ARM64: Exception handlers installed.
9217 09:29:42.519708 ARM64: Testing exception
9218 09:29:42.522593 ARM64: Done test exception
9219 09:29:42.522691 Enumerating buses...
9220 09:29:42.526053 Show all devs... Before device enumeration.
9221 09:29:42.529361 Root Device: enabled 1
9222 09:29:42.532708 CPU_CLUSTER: 0: enabled 1
9223 09:29:42.532788 CPU: 00: enabled 1
9224 09:29:42.535989 Compare with tree...
9225 09:29:42.536074 Root Device: enabled 1
9226 09:29:42.539218 CPU_CLUSTER: 0: enabled 1
9227 09:29:42.542462 CPU: 00: enabled 1
9228 09:29:42.542566 Root Device scanning...
9229 09:29:42.545808 scan_static_bus for Root Device
9230 09:29:42.549363 CPU_CLUSTER: 0 enabled
9231 09:29:42.552570 scan_static_bus for Root Device done
9232 09:29:42.555789 scan_bus: bus Root Device finished in 8 msecs
9233 09:29:42.555872 done
9234 09:29:42.562571 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 09:29:42.565786 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 09:29:42.572407 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 09:29:42.576043 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 09:29:42.579407 Allocating resources...
9239 09:29:42.582735 Reading resources...
9240 09:29:42.586085 Root Device read_resources bus 0 link: 0
9241 09:29:42.586191 DRAM rank0 size:0x100000000,
9242 09:29:42.589484 DRAM rank1 size=0x100000000
9243 09:29:42.592884 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 09:29:42.595619 CPU: 00 missing read_resources
9245 09:29:42.599481 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 09:29:42.605838 Root Device read_resources bus 0 link: 0 done
9247 09:29:42.605945 Done reading resources.
9248 09:29:42.612551 Show resources in subtree (Root Device)...After reading.
9249 09:29:42.615941 Root Device child on link 0 CPU_CLUSTER: 0
9250 09:29:42.619152 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 09:29:42.629189 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 09:29:42.629302 CPU: 00
9253 09:29:42.632324 Root Device assign_resources, bus 0 link: 0
9254 09:29:42.635477 CPU_CLUSTER: 0 missing set_resources
9255 09:29:42.641950 Root Device assign_resources, bus 0 link: 0 done
9256 09:29:42.642058 Done setting resources.
9257 09:29:42.648946 Show resources in subtree (Root Device)...After assigning values.
9258 09:29:42.652296 Root Device child on link 0 CPU_CLUSTER: 0
9259 09:29:42.655713 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 09:29:42.665460 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 09:29:42.665573 CPU: 00
9262 09:29:42.668795 Done allocating resources.
9263 09:29:42.672029 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 09:29:42.675150 Enabling resources...
9265 09:29:42.675268 done.
9266 09:29:42.682040 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 09:29:42.682149 Initializing devices...
9268 09:29:42.685335 Root Device init
9269 09:29:42.685423 init hardware done!
9270 09:29:42.688526 0x00000018: ctrlr->caps
9271 09:29:42.691849 52.000 MHz: ctrlr->f_max
9272 09:29:42.691960 0.400 MHz: ctrlr->f_min
9273 09:29:42.695663 0x40ff8080: ctrlr->voltages
9274 09:29:42.695761 sclk: 390625
9275 09:29:42.698909 Bus Width = 1
9276 09:29:42.699007 sclk: 390625
9277 09:29:42.702210 Bus Width = 1
9278 09:29:42.702315 Early init status = 3
9279 09:29:42.708791 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 09:29:42.711763 in-header: 03 fc 00 00 01 00 00 00
9281 09:29:42.711840 in-data: 00
9282 09:29:42.718774 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 09:29:42.721475 in-header: 03 fd 00 00 00 00 00 00
9284 09:29:42.724877 in-data:
9285 09:29:42.728310 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 09:29:42.731556 in-header: 03 fc 00 00 01 00 00 00
9287 09:29:42.735030 in-data: 00
9288 09:29:42.738256 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 09:29:42.743576 in-header: 03 fd 00 00 00 00 00 00
9290 09:29:42.747049 in-data:
9291 09:29:42.750172 [SSUSB] Setting up USB HOST controller...
9292 09:29:42.753410 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 09:29:42.757008 [SSUSB] phy power-on done.
9294 09:29:42.760131 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 09:29:42.766595 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 09:29:42.770242 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 09:29:42.776569 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 09:29:42.783466 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9299 09:29:42.790035 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 09:29:42.796545 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 09:29:42.803443 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9302 09:29:42.806424 SPM: binary array size = 0x9dc
9303 09:29:42.809798 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 09:29:42.816407 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 09:29:42.823294 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 09:29:42.826576 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 09:29:42.833097 configure_display: Starting display init
9308 09:29:42.866734 anx7625_power_on_init: Init interface.
9309 09:29:42.869913 anx7625_disable_pd_protocol: Disabled PD feature.
9310 09:29:42.873095 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 09:29:42.900909 anx7625_start_dp_work: Secure OCM version=00
9312 09:29:42.904249 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 09:29:42.919054 sp_tx_get_edid_block: EDID Block = 1
9314 09:29:43.021925 Extracted contents:
9315 09:29:43.025104 header: 00 ff ff ff ff ff ff 00
9316 09:29:43.028261 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 09:29:43.031839 version: 01 04
9318 09:29:43.035106 basic params: 95 1f 11 78 0a
9319 09:29:43.038441 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 09:29:43.041466 established: 00 00 00
9321 09:29:43.048646 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 09:29:43.051322 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 09:29:43.057901 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 09:29:43.064404 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 09:29:43.071361 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 09:29:43.074619 extensions: 00
9327 09:29:43.074727 checksum: fb
9328 09:29:43.074822
9329 09:29:43.077680 Manufacturer: IVO Model 57d Serial Number 0
9330 09:29:43.081041 Made week 0 of 2020
9331 09:29:43.081181 EDID version: 1.4
9332 09:29:43.084353 Digital display
9333 09:29:43.088288 6 bits per primary color channel
9334 09:29:43.088362 DisplayPort interface
9335 09:29:43.091010 Maximum image size: 31 cm x 17 cm
9336 09:29:43.094396 Gamma: 220%
9337 09:29:43.094492 Check DPMS levels
9338 09:29:43.097612 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 09:29:43.104189 First detailed timing is preferred timing
9340 09:29:43.104286 Established timings supported:
9341 09:29:43.107452 Standard timings supported:
9342 09:29:43.111334 Detailed timings
9343 09:29:43.114304 Hex of detail: 383680a07038204018303c0035ae10000019
9344 09:29:43.120955 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 09:29:43.124457 0780 0798 07c8 0820 hborder 0
9346 09:29:43.127930 0438 043b 0447 0458 vborder 0
9347 09:29:43.131201 -hsync -vsync
9348 09:29:43.131307 Did detailed timing
9349 09:29:43.137873 Hex of detail: 000000000000000000000000000000000000
9350 09:29:43.141234 Manufacturer-specified data, tag 0
9351 09:29:43.144462 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 09:29:43.147494 ASCII string: InfoVision
9353 09:29:43.150957 Hex of detail: 000000fe00523134304e574635205248200a
9354 09:29:43.154407 ASCII string: R140NWF5 RH
9355 09:29:43.154507 Checksum
9356 09:29:43.157906 Checksum: 0xfb (valid)
9357 09:29:43.161086 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 09:29:43.164292 DSI data_rate: 832800000 bps
9359 09:29:43.171136 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 09:29:43.174293 anx7625_parse_edid: pixelclock(138800).
9361 09:29:43.177474 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 09:29:43.181314 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 09:29:43.184545 anx7625_dsi_config: config dsi.
9364 09:29:43.190936 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 09:29:43.203558 anx7625_dsi_config: success to config DSI
9366 09:29:43.207010 anx7625_dp_start: MIPI phy setup OK.
9367 09:29:43.210231 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 09:29:43.213577 mtk_ddp_mode_set invalid vrefresh 60
9369 09:29:43.216819 main_disp_path_setup
9370 09:29:43.216918 ovl_layer_smi_id_en
9371 09:29:43.220168 ovl_layer_smi_id_en
9372 09:29:43.220281 ccorr_config
9373 09:29:43.220378 aal_config
9374 09:29:43.223455 gamma_config
9375 09:29:43.223563 postmask_config
9376 09:29:43.227393 dither_config
9377 09:29:43.230425 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 09:29:43.237130 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 09:29:43.240384 Root Device init finished in 552 msecs
9380 09:29:43.243608 CPU_CLUSTER: 0 init
9381 09:29:43.250323 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 09:29:43.253748 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 09:29:43.256949 APU_MBOX 0x190000b0 = 0x10001
9384 09:29:43.260137 APU_MBOX 0x190001b0 = 0x10001
9385 09:29:43.263632 APU_MBOX 0x190005b0 = 0x10001
9386 09:29:43.266489 APU_MBOX 0x190006b0 = 0x10001
9387 09:29:43.269804 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 09:29:43.282534 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9389 09:29:43.295184 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 09:29:43.301780 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 09:29:43.313812 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9392 09:29:43.322429 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 09:29:43.325759 CPU_CLUSTER: 0 init finished in 81 msecs
9394 09:29:43.328994 Devices initialized
9395 09:29:43.332434 Show all devs... After init.
9396 09:29:43.332534 Root Device: enabled 1
9397 09:29:43.335766 CPU_CLUSTER: 0: enabled 1
9398 09:29:43.338890 CPU: 00: enabled 1
9399 09:29:43.342628 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9400 09:29:43.345817 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 09:29:43.349200 ELOG: NV offset 0x57f000 size 0x1000
9402 09:29:43.355995 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9403 09:29:43.362573 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 09:29:43.365289 ELOG: Event(17) added with size 13 at 2023-10-20 09:28:09 UTC
9405 09:29:43.372023 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 09:29:43.375819 in-header: 03 f9 00 00 2c 00 00 00
9407 09:29:43.385641 in-data: 66 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 09:29:43.392384 ELOG: Event(A1) added with size 10 at 2023-10-20 09:28:09 UTC
9409 09:29:43.398814 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 09:29:43.405553 ELOG: Event(A0) added with size 9 at 2023-10-20 09:28:09 UTC
9411 09:29:43.409050 elog_add_boot_reason: Logged dev mode boot
9412 09:29:43.411940 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9413 09:29:43.415879 Finalize devices...
9414 09:29:43.415963 Devices finalized
9415 09:29:43.422022 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 09:29:43.425201 Writing coreboot table at 0xffe64000
9417 09:29:43.428504 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 09:29:43.431866 1. 0000000040000000-00000000400fffff: RAM
9419 09:29:43.438578 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 09:29:43.442089 3. 000000004032b000-00000000545fffff: RAM
9421 09:29:43.445331 4. 0000000054600000-000000005465ffff: BL31
9422 09:29:43.448515 5. 0000000054660000-00000000ffe63fff: RAM
9423 09:29:43.455490 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 09:29:43.458682 7. 0000000100000000-000000023fffffff: RAM
9425 09:29:43.462048 Passing 5 GPIOs to payload:
9426 09:29:43.465447 NAME | PORT | POLARITY | VALUE
9427 09:29:43.468842 EC in RW | 0x000000aa | low | undefined
9428 09:29:43.475574 EC interrupt | 0x00000005 | low | undefined
9429 09:29:43.478929 TPM interrupt | 0x000000ab | high | undefined
9430 09:29:43.485488 SD card detect | 0x00000011 | high | undefined
9431 09:29:43.488856 speaker enable | 0x00000093 | high | undefined
9432 09:29:43.492051 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 09:29:43.495259 in-header: 03 f9 00 00 02 00 00 00
9434 09:29:43.495361 in-data: 02 00
9435 09:29:43.498644 ADC[4]: Raw value=904357 ID=7
9436 09:29:43.502365 ADC[3]: Raw value=213441 ID=1
9437 09:29:43.505462 RAM Code: 0x71
9438 09:29:43.505566 ADC[6]: Raw value=75701 ID=0
9439 09:29:43.508687 ADC[5]: Raw value=212703 ID=1
9440 09:29:43.511882 SKU Code: 0x1
9441 09:29:43.514930 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 77d7
9442 09:29:43.518444 coreboot table: 964 bytes.
9443 09:29:43.521862 IMD ROOT 0. 0xfffff000 0x00001000
9444 09:29:43.525337 IMD SMALL 1. 0xffffe000 0x00001000
9445 09:29:43.528482 RO MCACHE 2. 0xffffc000 0x00001104
9446 09:29:43.532093 CONSOLE 3. 0xfff7c000 0x00080000
9447 09:29:43.535438 FMAP 4. 0xfff7b000 0x00000452
9448 09:29:43.538424 TIME STAMP 5. 0xfff7a000 0x00000910
9449 09:29:43.542137 VBOOT WORK 6. 0xfff66000 0x00014000
9450 09:29:43.545356 RAMOOPS 7. 0xffe66000 0x00100000
9451 09:29:43.548697 COREBOOT 8. 0xffe64000 0x00002000
9452 09:29:43.548810 IMD small region:
9453 09:29:43.551931 IMD ROOT 0. 0xffffec00 0x00000400
9454 09:29:43.555126 VPD 1. 0xffffeb80 0x0000006c
9455 09:29:43.558502 MMC STATUS 2. 0xffffeb60 0x00000004
9456 09:29:43.564967 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 09:29:43.568246 Probing TPM: done!
9458 09:29:43.571581 Connected to device vid:did:rid of 1ae0:0028:00
9459 09:29:43.581867 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9460 09:29:43.585176 Initialized TPM device CR50 revision 0
9461 09:29:43.589228 Checking cr50 for pending updates
9462 09:29:43.592494 Reading cr50 TPM mode
9463 09:29:43.601108 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 09:29:43.607205 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 09:29:43.647849 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9466 09:29:43.650733 Checking segment from ROM address 0x40100000
9467 09:29:43.654289 Checking segment from ROM address 0x4010001c
9468 09:29:43.661084 Loading segment from ROM address 0x40100000
9469 09:29:43.661187 code (compression=0)
9470 09:29:43.668067 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 09:29:43.677604 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 09:29:43.677716 it's not compressed!
9473 09:29:43.684471 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 09:29:43.687826 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 09:29:43.708376 Loading segment from ROM address 0x4010001c
9476 09:29:43.708514 Entry Point 0x80000000
9477 09:29:43.711523 Loaded segments
9478 09:29:43.714676 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9479 09:29:43.721394 Jumping to boot code at 0x80000000(0xffe64000)
9480 09:29:43.727876 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 09:29:43.734930 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 09:29:43.742233 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9483 09:29:43.746222 Checking segment from ROM address 0x40100000
9484 09:29:43.749508 Checking segment from ROM address 0x4010001c
9485 09:29:43.756085 Loading segment from ROM address 0x40100000
9486 09:29:43.756198 code (compression=1)
9487 09:29:43.762665 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 09:29:43.772328 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 09:29:43.772439 using LZMA
9490 09:29:43.780839 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 09:29:43.787631 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 09:29:43.791154 Loading segment from ROM address 0x4010001c
9493 09:29:43.791265 Entry Point 0x54601000
9494 09:29:43.794464 Loaded segments
9495 09:29:43.797979 NOTICE: MT8192 bl31_setup
9496 09:29:43.804756 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 09:29:43.808084 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 09:29:43.811404 WARNING: region 0:
9499 09:29:43.814617 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 09:29:43.814740 WARNING: region 1:
9501 09:29:43.821042 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 09:29:43.824897 WARNING: region 2:
9503 09:29:43.828256 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 09:29:43.831424 WARNING: region 3:
9505 09:29:43.834496 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 09:29:43.837798 WARNING: region 4:
9507 09:29:43.841227 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 09:29:43.844529 WARNING: region 5:
9509 09:29:43.848381 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 09:29:43.850986 WARNING: region 6:
9511 09:29:43.854445 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 09:29:43.854554 WARNING: region 7:
9513 09:29:43.861000 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 09:29:43.868195 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 09:29:43.871494 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 09:29:43.874535 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 09:29:43.880975 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 09:29:43.884748 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 09:29:43.888007 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 09:29:43.894563 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 09:29:43.897537 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 09:29:43.904544 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 09:29:43.908231 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 09:29:43.911469 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 09:29:43.917998 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 09:29:43.921256 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 09:29:43.924560 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 09:29:43.931011 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 09:29:43.934958 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 09:29:43.938305 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 09:29:43.944845 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 09:29:43.948152 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 09:29:43.954630 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 09:29:43.957981 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 09:29:43.961365 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 09:29:43.967867 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 09:29:43.971190 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 09:29:43.977834 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 09:29:43.981216 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 09:29:43.984503 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 09:29:43.991769 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 09:29:43.994424 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 09:29:43.998385 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 09:29:44.005087 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 09:29:44.008155 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 09:29:44.011244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 09:29:44.018025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 09:29:44.021125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 09:29:44.024748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 09:29:44.028054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 09:29:44.035015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 09:29:44.038126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 09:29:44.041421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 09:29:44.044747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 09:29:44.051126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 09:29:44.054741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 09:29:44.057846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 09:29:44.061626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 09:29:44.067994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 09:29:44.071363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 09:29:44.074764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 09:29:44.081420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 09:29:44.084614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 09:29:44.088624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 09:29:44.095072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 09:29:44.098325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 09:29:44.104976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 09:29:44.108266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 09:29:44.115253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 09:29:44.118415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 09:29:44.121759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 09:29:44.128341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 09:29:44.131386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 09:29:44.138020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 09:29:44.141596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 09:29:44.148526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 09:29:44.152006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 09:29:44.154749 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 09:29:44.161813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 09:29:44.164965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 09:29:44.171783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 09:29:44.175162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 09:29:44.181671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 09:29:44.184953 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 09:29:44.188792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 09:29:44.195471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 09:29:44.198896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 09:29:44.205382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 09:29:44.208661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 09:29:44.215397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 09:29:44.218778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 09:29:44.221881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 09:29:44.228347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 09:29:44.231610 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 09:29:44.238144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 09:29:44.242074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 09:29:44.248332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 09:29:44.251902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 09:29:44.255409 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 09:29:44.261936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 09:29:44.265449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 09:29:44.272002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 09:29:44.275293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 09:29:44.278466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 09:29:44.285822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 09:29:44.288843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 09:29:44.295257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 09:29:44.298621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 09:29:44.305242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 09:29:44.308398 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 09:29:44.312317 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 09:29:44.315740 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 09:29:44.322298 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 09:29:44.325571 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 09:29:44.328792 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 09:29:44.335291 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 09:29:44.338723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 09:29:44.345313 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 09:29:44.348728 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 09:29:44.352085 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 09:29:44.358645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 09:29:44.361999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 09:29:44.368673 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 09:29:44.372026 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 09:29:44.375275 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 09:29:44.382322 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 09:29:44.385448 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 09:29:44.389181 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 09:29:44.395904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 09:29:44.398772 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 09:29:44.402159 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 09:29:44.409013 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 09:29:44.412324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 09:29:44.415551 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 09:29:44.419013 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 09:29:44.425885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 09:29:44.429148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 09:29:44.432583 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 09:29:44.439329 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 09:29:44.442608 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 09:29:44.445921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 09:29:44.452656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 09:29:44.455993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 09:29:44.462646 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 09:29:44.466039 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 09:29:44.469358 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 09:29:44.475950 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 09:29:44.479056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 09:29:44.485657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 09:29:44.489072 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 09:29:44.492499 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 09:29:44.498996 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 09:29:44.502132 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 09:29:44.505722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 09:29:44.512458 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 09:29:44.515388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 09:29:44.521944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 09:29:44.525499 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 09:29:44.529199 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 09:29:44.535765 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 09:29:44.539121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 09:29:44.545418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 09:29:44.548764 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 09:29:44.551967 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 09:29:44.558615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 09:29:44.561985 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 09:29:44.565342 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 09:29:44.572036 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 09:29:44.575441 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 09:29:44.582124 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 09:29:44.585452 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 09:29:44.588829 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 09:29:44.595283 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 09:29:44.598970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 09:29:44.605257 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 09:29:44.608762 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 09:29:44.612564 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 09:29:44.619109 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 09:29:44.622040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 09:29:44.625866 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 09:29:44.631910 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 09:29:44.635517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 09:29:44.642455 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 09:29:44.645623 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 09:29:44.649053 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 09:29:44.655417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 09:29:44.659197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 09:29:44.665272 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 09:29:44.668631 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 09:29:44.671975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 09:29:44.678553 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 09:29:44.681865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 09:29:44.685931 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 09:29:44.691874 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 09:29:44.695271 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 09:29:44.702366 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 09:29:44.705686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 09:29:44.712180 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 09:29:44.715246 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 09:29:44.718822 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 09:29:44.724970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 09:29:44.728625 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 09:29:44.734901 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 09:29:44.738501 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 09:29:44.741758 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 09:29:44.748870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 09:29:44.751760 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 09:29:44.758555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 09:29:44.761475 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 09:29:44.765203 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 09:29:44.771920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 09:29:44.775319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 09:29:44.781956 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 09:29:44.785385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 09:29:44.788155 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 09:29:44.794947 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 09:29:44.798355 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 09:29:44.805024 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 09:29:44.808206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 09:29:44.814929 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 09:29:44.818249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 09:29:44.821543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 09:29:44.828038 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 09:29:44.831858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 09:29:44.838488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 09:29:44.841738 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 09:29:44.844958 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 09:29:44.851658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 09:29:44.855246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 09:29:44.861571 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 09:29:44.864828 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 09:29:44.871509 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 09:29:44.874675 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 09:29:44.878157 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 09:29:44.884859 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 09:29:44.888142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 09:29:44.894836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 09:29:44.898092 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 09:29:44.901457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 09:29:44.908160 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 09:29:44.911246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 09:29:44.917995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 09:29:44.921528 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 09:29:44.924897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 09:29:44.927880 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 09:29:44.934475 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 09:29:44.937675 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 09:29:44.941519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 09:29:44.948456 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 09:29:44.951863 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 09:29:44.954513 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 09:29:44.961302 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 09:29:44.964944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 09:29:44.968157 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 09:29:44.974654 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 09:29:44.978071 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 09:29:44.981311 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 09:29:44.988264 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 09:29:44.991300 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 09:29:44.997750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 09:29:45.001021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 09:29:45.004321 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 09:29:45.011241 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 09:29:45.014350 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 09:29:45.017639 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 09:29:45.024366 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 09:29:45.027762 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 09:29:45.031060 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 09:29:45.037772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 09:29:45.040846 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 09:29:45.047520 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 09:29:45.050795 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 09:29:45.054057 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 09:29:45.060879 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 09:29:45.064302 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 09:29:45.067613 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 09:29:45.073978 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 09:29:45.077550 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 09:29:45.080991 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 09:29:45.087737 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 09:29:45.090891 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 09:29:45.094136 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 09:29:45.100898 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 09:29:45.103866 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 09:29:45.107760 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 09:29:45.111024 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 09:29:45.114327 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 09:29:45.120673 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 09:29:45.124030 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 09:29:45.127448 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 09:29:45.134406 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 09:29:45.137115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 09:29:45.140731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 09:29:45.143963 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 09:29:45.150716 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 09:29:45.153993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 09:29:45.160619 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 09:29:45.163994 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 09:29:45.167205 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 09:29:45.173529 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 09:29:45.176876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 09:29:45.183603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 09:29:45.186744 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 09:29:45.190493 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 09:29:45.197023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 09:29:45.200182 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 09:29:45.207490 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 09:29:45.210736 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 09:29:45.213819 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 09:29:45.220628 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 09:29:45.223649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 09:29:45.230590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 09:29:45.233969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 09:29:45.237289 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 09:29:45.244125 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 09:29:45.247337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 09:29:45.253776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 09:29:45.257162 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 09:29:45.261167 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 09:29:45.267154 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 09:29:45.271006 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 09:29:45.277429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 09:29:45.280609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 09:29:45.283925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 09:29:45.290878 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 09:29:45.294139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 09:29:45.300528 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 09:29:45.303834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 09:29:45.307212 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 09:29:45.313752 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 09:29:45.317548 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 09:29:45.324044 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 09:29:45.327266 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 09:29:45.333988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 09:29:45.337291 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 09:29:45.340788 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 09:29:45.347485 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 09:29:45.350786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 09:29:45.353785 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 09:29:45.360264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 09:29:45.363729 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 09:29:45.370360 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 09:29:45.373595 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 09:29:45.376884 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 09:29:45.384070 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 09:29:45.387387 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 09:29:45.394205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 09:29:45.396946 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 09:29:45.403565 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 09:29:45.407375 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 09:29:45.410558 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 09:29:45.417273 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 09:29:45.420571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 09:29:45.427038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 09:29:45.430624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 09:29:45.433767 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 09:29:45.440474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 09:29:45.443553 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 09:29:45.450427 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 09:29:45.453418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 09:29:45.457116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 09:29:45.463209 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 09:29:45.466784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 09:29:45.473168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 09:29:45.476601 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 09:29:45.483080 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 09:29:45.486938 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 09:29:45.490130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 09:29:45.496958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 09:29:45.500245 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 09:29:45.506979 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 09:29:45.509739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 09:29:45.516665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 09:29:45.520051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 09:29:45.523472 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 09:29:45.529697 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 09:29:45.533465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 09:29:45.539822 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 09:29:45.543207 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 09:29:45.549885 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 09:29:45.553171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 09:29:45.556385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 09:29:45.563311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 09:29:45.566585 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 09:29:45.573279 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 09:29:45.576477 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 09:29:45.582850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 09:29:45.586508 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 09:29:45.589616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 09:29:45.596306 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 09:29:45.599631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 09:29:45.606422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 09:29:45.609775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 09:29:45.616341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 09:29:45.619579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 09:29:45.622781 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 09:29:45.629557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 09:29:45.632911 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 09:29:45.639610 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 09:29:45.642988 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 09:29:45.649645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 09:29:45.652962 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 09:29:45.656335 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 09:29:45.662971 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 09:29:45.666381 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 09:29:45.672570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 09:29:45.675866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 09:29:45.682949 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 09:29:45.686206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 09:29:45.692361 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 09:29:45.696091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 09:29:45.699226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 09:29:45.705998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 09:29:45.709316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 09:29:45.716140 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 09:29:45.718867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 09:29:45.722748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 09:29:45.729208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 09:29:45.732508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 09:29:45.739198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 09:29:45.742530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 09:29:45.749245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 09:29:45.752540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 09:29:45.758922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 09:29:45.762284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 09:29:45.768948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 09:29:45.772354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 09:29:45.778934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 09:29:45.781870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 09:29:45.789008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 09:29:45.791999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 09:29:45.798676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 09:29:45.802155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 09:29:45.808586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 09:29:45.812157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 09:29:45.818641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 09:29:45.821643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 09:29:45.828719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 09:29:45.831834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 09:29:45.838367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 09:29:45.841782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 09:29:45.848337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 09:29:45.851642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 09:29:45.858207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 09:29:45.861511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 09:29:45.868477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 09:29:45.871996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 09:29:45.875296 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 09:29:45.878005 INFO: [APUAPC] vio 0
9950 09:29:45.884825 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 09:29:45.888343 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 09:29:45.891798 INFO: [APUAPC] D0_APC_0: 0x400510
9953 09:29:45.895092 INFO: [APUAPC] D0_APC_1: 0x0
9954 09:29:45.898312 INFO: [APUAPC] D0_APC_2: 0x1540
9955 09:29:45.901799 INFO: [APUAPC] D0_APC_3: 0x0
9956 09:29:45.905078 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 09:29:45.907801 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 09:29:45.911483 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 09:29:45.914582 INFO: [APUAPC] D1_APC_3: 0x0
9960 09:29:45.918334 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 09:29:45.921323 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 09:29:45.924802 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 09:29:45.924885 INFO: [APUAPC] D2_APC_3: 0x0
9964 09:29:45.928219 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 09:29:45.931483 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 09:29:45.934755 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 09:29:45.937763 INFO: [APUAPC] D3_APC_3: 0x0
9968 09:29:45.941123 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 09:29:45.944731 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 09:29:45.947722 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 09:29:45.951115 INFO: [APUAPC] D4_APC_3: 0x0
9972 09:29:45.954977 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 09:29:45.958093 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 09:29:45.961118 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 09:29:45.964763 INFO: [APUAPC] D5_APC_3: 0x0
9976 09:29:45.968137 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 09:29:45.970830 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 09:29:45.974160 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 09:29:45.977518 INFO: [APUAPC] D6_APC_3: 0x0
9980 09:29:45.980895 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 09:29:45.984114 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 09:29:45.987492 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 09:29:45.991085 INFO: [APUAPC] D7_APC_3: 0x0
9984 09:29:45.994474 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 09:29:45.997868 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 09:29:46.001150 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 09:29:46.004335 INFO: [APUAPC] D8_APC_3: 0x0
9988 09:29:46.007674 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 09:29:46.010994 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 09:29:46.014416 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 09:29:46.017709 INFO: [APUAPC] D9_APC_3: 0x0
9992 09:29:46.021088 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 09:29:46.024488 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 09:29:46.027771 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 09:29:46.031027 INFO: [APUAPC] D10_APC_3: 0x0
9996 09:29:46.033801 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 09:29:46.037162 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 09:29:46.040548 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 09:29:46.043898 INFO: [APUAPC] D11_APC_3: 0x0
10000 09:29:46.047650 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 09:29:46.050841 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 09:29:46.053775 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 09:29:46.057197 INFO: [APUAPC] D12_APC_3: 0x0
10004 09:29:46.060567 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 09:29:46.064021 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 09:29:46.067392 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 09:29:46.070726 INFO: [APUAPC] D13_APC_3: 0x0
10008 09:29:46.073711 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 09:29:46.077467 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 09:29:46.080495 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 09:29:46.083731 INFO: [APUAPC] D14_APC_3: 0x0
10012 09:29:46.086998 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 09:29:46.090628 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 09:29:46.094310 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 09:29:46.097169 INFO: [APUAPC] D15_APC_3: 0x0
10016 09:29:46.100483 INFO: [APUAPC] APC_CON: 0x4
10017 09:29:46.103803 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 09:29:46.107746 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 09:29:46.107827 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 09:29:46.110933 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 09:29:46.114216 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 09:29:46.117449 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 09:29:46.120749 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 09:29:46.124234 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 09:29:46.127450 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 09:29:46.130861 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 09:29:46.134138 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 09:29:46.136836 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 09:29:46.140189 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 09:29:46.143552 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 09:29:46.143632 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 09:29:46.146896 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 09:29:46.150262 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 09:29:46.153761 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 09:29:46.157051 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 09:29:46.160242 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 09:29:46.163441 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 09:29:46.166839 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 09:29:46.170059 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 09:29:46.173391 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 09:29:46.176748 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 09:29:46.179992 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 09:29:46.183094 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 09:29:46.183174 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 09:29:46.186903 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 09:29:46.190116 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 09:29:46.193411 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 09:29:46.196722 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 09:29:46.200313 INFO: [NOCDAPC] APC_CON: 0x4
10050 09:29:46.203105 INFO: [APUAPC] set_apusys_apc done
10051 09:29:46.206581 INFO: [DEVAPC] devapc_init done
10052 09:29:46.209837 INFO: GICv3 without legacy support detected.
10053 09:29:46.213432 INFO: ARM GICv3 driver initialized in EL3
10054 09:29:46.220058 INFO: Maximum SPI INTID supported: 639
10055 09:29:46.223207 INFO: BL31: Initializing runtime services
10056 09:29:46.229938 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 09:29:46.230019 INFO: SPM: enable CPC mode
10058 09:29:46.236508 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 09:29:46.239871 INFO: BL31: Preparing for EL3 exit to normal world
10060 09:29:46.243124 INFO: Entry point address = 0x80000000
10061 09:29:46.246384 INFO: SPSR = 0x8
10062 09:29:46.252611
10063 09:29:46.252738
10064 09:29:46.252803
10065 09:29:46.256050 Starting depthcharge on Spherion...
10066 09:29:46.256132
10067 09:29:46.256197 Wipe memory regions:
10068 09:29:46.256259
10069 09:29:46.256934 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10070 09:29:46.257034 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 09:29:46.257119 Setting prompt string to ['asurada:']
10072 09:29:46.257202 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 09:29:46.258707 [0x00000040000000, 0x00000054600000)
10074 09:29:46.381551
10075 09:29:46.381690 [0x00000054660000, 0x00000080000000)
10076 09:29:46.642042
10077 09:29:46.642174 [0x000000821a7280, 0x000000ffe64000)
10078 09:29:47.386376
10079 09:29:47.386515 [0x00000100000000, 0x00000240000000)
10080 09:29:49.276934
10081 09:29:49.280104 Initializing XHCI USB controller at 0x11200000.
10082 09:29:50.317899
10083 09:29:50.320817 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10084 09:29:50.320905
10085 09:29:50.320969
10086 09:29:50.321029
10087 09:29:50.321313 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 09:29:50.421736 asurada: tftpboot 192.168.201.1 11826808/tftp-deploy-sgpti5nv/kernel/image.itb 11826808/tftp-deploy-sgpti5nv/kernel/cmdline
10090 09:29:50.421889 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 09:29:50.421970 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 09:29:50.426167 tftpboot 192.168.201.1 11826808/tftp-deploy-sgpti5nv/kernel/image.ittp-deploy-sgpti5nv/kernel/cmdline
10093 09:29:50.426276
10094 09:29:50.426368 Waiting for link
10095 09:29:50.586834
10096 09:29:50.586966 R8152: Initializing
10097 09:29:50.587033
10098 09:29:50.590039 Version 9 (ocp_data = 6010)
10099 09:29:50.590113
10100 09:29:50.593323 R8152: Done initializing
10101 09:29:50.593390
10102 09:29:50.593449 Adding net device
10103 09:29:52.466346
10104 09:29:52.466477 done.
10105 09:29:52.466543
10106 09:29:52.466602 MAC: 00:e0:4c:78:7a:aa
10107 09:29:52.466659
10108 09:29:52.469489 Sending DHCP discover... done.
10109 09:29:52.469570
10110 09:29:52.473180 Waiting for reply... done.
10111 09:29:52.473261
10112 09:29:52.475895 Sending DHCP request... done.
10113 09:29:52.475977
10114 09:29:52.492320 Waiting for reply... done.
10115 09:29:52.492408
10116 09:29:52.492472 My ip is 192.168.201.12
10117 09:29:52.492532
10118 09:29:52.495526 The DHCP server ip is 192.168.201.1
10119 09:29:52.495632
10120 09:29:52.502590 TFTP server IP predefined by user: 192.168.201.1
10121 09:29:52.502672
10122 09:29:52.508894 Bootfile predefined by user: 11826808/tftp-deploy-sgpti5nv/kernel/image.itb
10123 09:29:52.508976
10124 09:29:52.509040 Sending tftp read request... done.
10125 09:29:52.509100
10126 09:29:52.515656 Waiting for the transfer...
10127 09:29:52.515756
10128 09:29:52.770225 00000000 ################################################################
10129 09:29:52.770383
10130 09:29:53.024474 00080000 ################################################################
10131 09:29:53.024608
10132 09:29:53.277010 00100000 ################################################################
10133 09:29:53.277145
10134 09:29:53.528388 00180000 ################################################################
10135 09:29:53.528523
10136 09:29:53.778835 00200000 ################################################################
10137 09:29:53.778971
10138 09:29:54.032227 00280000 ################################################################
10139 09:29:54.032355
10140 09:29:54.293032 00300000 ################################################################
10141 09:29:54.293222
10142 09:29:54.546548 00380000 ################################################################
10143 09:29:54.546685
10144 09:29:54.797597 00400000 ################################################################
10145 09:29:54.797837
10146 09:29:55.057435 00480000 ################################################################
10147 09:29:55.057570
10148 09:29:55.308180 00500000 ################################################################
10149 09:29:55.308327
10150 09:29:55.576793 00580000 ################################################################
10151 09:29:55.576938
10152 09:29:55.849416 00600000 ################################################################
10153 09:29:55.849564
10154 09:29:56.118589 00680000 ################################################################
10155 09:29:56.118747
10156 09:29:56.378812 00700000 ################################################################
10157 09:29:56.378961
10158 09:29:56.639074 00780000 ################################################################
10159 09:29:56.639217
10160 09:29:56.894509 00800000 ################################################################
10161 09:29:56.894654
10162 09:29:57.148491 00880000 ################################################################
10163 09:29:57.148639
10164 09:29:57.401313 00900000 ################################################################
10165 09:29:57.401448
10166 09:29:57.649608 00980000 ################################################################
10167 09:29:57.649775
10168 09:29:57.900140 00a00000 ################################################################
10169 09:29:57.900280
10170 09:29:58.152420 00a80000 ################################################################
10171 09:29:58.152566
10172 09:29:58.405299 00b00000 ################################################################
10173 09:29:58.405437
10174 09:29:58.652169 00b80000 ################################################################
10175 09:29:58.652315
10176 09:29:58.919296 00c00000 ################################################################
10177 09:29:58.919443
10178 09:29:59.181389 00c80000 ################################################################
10179 09:29:59.181536
10180 09:29:59.448565 00d00000 ################################################################
10181 09:29:59.448701
10182 09:29:59.698063 00d80000 ################################################################
10183 09:29:59.698199
10184 09:29:59.950113 00e00000 ################################################################
10185 09:29:59.950268
10186 09:30:00.205045 00e80000 ################################################################
10187 09:30:00.205174
10188 09:30:00.460724 00f00000 ################################################################
10189 09:30:00.460870
10190 09:30:00.713048 00f80000 ################################################################
10191 09:30:00.713190
10192 09:30:00.961439 01000000 ################################################################
10193 09:30:00.961584
10194 09:30:01.209519 01080000 ################################################################
10195 09:30:01.209666
10196 09:30:01.475804 01100000 ################################################################
10197 09:30:01.475935
10198 09:30:01.737118 01180000 ################################################################
10199 09:30:01.737260
10200 09:30:02.006579 01200000 ################################################################
10201 09:30:02.006729
10202 09:30:02.289042 01280000 ################################################################
10203 09:30:02.289185
10204 09:30:02.557269 01300000 ################################################################
10205 09:30:02.557439
10206 09:30:02.814895 01380000 ################################################################
10207 09:30:02.815029
10208 09:30:03.083274 01400000 ################################################################
10209 09:30:03.083408
10210 09:30:03.332056 01480000 ################################################################
10211 09:30:03.332189
10212 09:30:03.587076 01500000 ################################################################
10213 09:30:03.587248
10214 09:30:03.862322 01580000 ################################################################
10215 09:30:03.862499
10216 09:30:04.133375 01600000 ################################################################
10217 09:30:04.133509
10218 09:30:04.398304 01680000 ################################################################
10219 09:30:04.398451
10220 09:30:04.675200 01700000 ################################################################
10221 09:30:04.675365
10222 09:30:04.957034 01780000 ################################################################
10223 09:30:04.957185
10224 09:30:05.223881 01800000 ################################################################
10225 09:30:05.224075
10226 09:30:05.480263 01880000 ################################################################
10227 09:30:05.480410
10228 09:30:05.741728 01900000 ################################################################
10229 09:30:05.741882
10230 09:30:06.000865 01980000 ################################################################
10231 09:30:06.001024
10232 09:30:06.267041 01a00000 ################################################################
10233 09:30:06.267195
10234 09:30:06.522789 01a80000 ################################################################
10235 09:30:06.522939
10236 09:30:06.779173 01b00000 ################################################################
10237 09:30:06.779325
10238 09:30:06.804568 01b80000 ####### done.
10239 09:30:06.804719
10240 09:30:06.807810 The bootfile was 28888706 bytes long.
10241 09:30:06.807901
10242 09:30:06.811392 Sending tftp read request... done.
10243 09:30:06.811496
10244 09:30:06.814734 Waiting for the transfer...
10245 09:30:06.814836
10246 09:30:06.814901 00000000 # done.
10247 09:30:06.814980
10248 09:30:06.824508 Command line loaded dynamically from TFTP file: 11826808/tftp-deploy-sgpti5nv/kernel/cmdline
10249 09:30:06.824657
10250 09:30:06.844857 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10251 09:30:06.847917
10252 09:30:06.848014 Loading FIT.
10253 09:30:06.848079
10254 09:30:06.851455 Image ramdisk-1 has 17795134 bytes.
10255 09:30:06.851546
10256 09:30:06.854758 Image fdt-1 has 47278 bytes.
10257 09:30:06.854846
10258 09:30:06.854911 Image kernel-1 has 11044258 bytes.
10259 09:30:06.858082
10260 09:30:06.864488 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10261 09:30:06.864636
10262 09:30:06.881480 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10263 09:30:06.884701
10264 09:30:06.888034 Choosing best match conf-1 for compat google,spherion-rev2.
10265 09:30:06.892385
10266 09:30:06.897128 Connected to device vid:did:rid of 1ae0:0028:00
10267 09:30:06.903983
10268 09:30:06.907136 tpm_get_response: command 0x17b, return code 0x0
10269 09:30:06.907244
10270 09:30:06.914067 ec_init: CrosEC protocol v3 supported (256, 248)
10271 09:30:06.914198
10272 09:30:06.917239 tpm_cleanup: add release locality here.
10273 09:30:06.917331
10274 09:30:06.920933 Shutting down all USB controllers.
10275 09:30:06.921022
10276 09:30:06.923780 Removing current net device
10277 09:30:06.923868
10278 09:30:06.927138 Exiting depthcharge with code 4 at timestamp: 49925581
10279 09:30:06.930842
10280 09:30:06.934364 LZMA decompressing kernel-1 to 0x821a6718
10281 09:30:06.934459
10282 09:30:06.937136 LZMA decompressing kernel-1 to 0x40000000
10283 09:30:08.326205
10284 09:30:08.326351 jumping to kernel
10285 09:30:08.326798 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10286 09:30:08.326902 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10287 09:30:08.326978 Setting prompt string to ['Linux version [0-9]']
10288 09:30:08.327046 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10289 09:30:08.327113 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10290 09:30:08.407922
10291 09:30:08.411177 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10292 09:30:08.414776 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10293 09:30:08.414869 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10294 09:30:08.414941 Setting prompt string to []
10295 09:30:08.415019 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10296 09:30:08.415095 Using line separator: #'\n'#
10297 09:30:08.415155 No login prompt set.
10298 09:30:08.415217 Parsing kernel messages
10299 09:30:08.415272 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10300 09:30:08.415417 [login-action] Waiting for messages, (timeout 00:04:03)
10301 09:30:08.434552 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10302 09:30:08.437704 [ 0.000000] random: crng init done
10303 09:30:08.440946 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10304 09:30:08.444797 [ 0.000000] efi: UEFI not found.
10305 09:30:08.454667 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10306 09:30:08.460858 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10307 09:30:08.471004 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10308 09:30:08.480940 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10309 09:30:08.487463 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10310 09:30:08.493866 [ 0.000000] printk: bootconsole [mtk8250] enabled
10311 09:30:08.500718 [ 0.000000] NUMA: No NUMA configuration found
10312 09:30:08.507140 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10313 09:30:08.510320 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10314 09:30:08.513910 [ 0.000000] Zone ranges:
10315 09:30:08.520400 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10316 09:30:08.523898 [ 0.000000] DMA32 empty
10317 09:30:08.530619 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10318 09:30:08.533798 [ 0.000000] Movable zone start for each node
10319 09:30:08.537162 [ 0.000000] Early memory node ranges
10320 09:30:08.544508 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10321 09:30:08.550229 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10322 09:30:08.556989 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10323 09:30:08.560684 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10324 09:30:08.566894 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10325 09:30:08.573526 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10326 09:30:08.632071 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10327 09:30:08.639130 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10328 09:30:08.645424 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10329 09:30:08.648671 [ 0.000000] psci: probing for conduit method from DT.
10330 09:30:08.655394 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10331 09:30:08.658902 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10332 09:30:08.665437 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10333 09:30:08.668484 [ 0.000000] psci: SMC Calling Convention v1.2
10334 09:30:08.675153 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10335 09:30:08.678656 [ 0.000000] Detected VIPT I-cache on CPU0
10336 09:30:08.685448 [ 0.000000] CPU features: detected: GIC system register CPU interface
10337 09:30:08.691904 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10338 09:30:08.698343 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10339 09:30:08.705239 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10340 09:30:08.712100 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10341 09:30:08.718505 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10342 09:30:08.725416 [ 0.000000] alternatives: applying boot alternatives
10343 09:30:08.728587 [ 0.000000] Fallback order for Node 0: 0
10344 09:30:08.735424 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10345 09:30:08.738757 [ 0.000000] Policy zone: Normal
10346 09:30:08.761687 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10347 09:30:08.774759 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10348 09:30:08.785059 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10349 09:30:08.795028 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10350 09:30:08.801300 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10351 09:30:08.804798 <6>[ 0.000000] software IO TLB: area num 8.
10352 09:30:08.860901 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10353 09:30:09.010425 <6>[ 0.000000] Memory: 7952116K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400652K reserved, 32768K cma-reserved)
10354 09:30:09.017083 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10355 09:30:09.023827 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10356 09:30:09.026977 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10357 09:30:09.033941 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10358 09:30:09.040814 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10359 09:30:09.043852 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10360 09:30:09.053812 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10361 09:30:09.060696 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10362 09:30:09.063887 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10363 09:30:09.071504 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10364 09:30:09.074744 <6>[ 0.000000] GICv3: 608 SPIs implemented
10365 09:30:09.081324 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10366 09:30:09.084576 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10367 09:30:09.088328 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10368 09:30:09.097935 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10369 09:30:09.108181 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10370 09:30:09.121170 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10371 09:30:09.127914 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10372 09:30:09.137139 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10373 09:30:09.150182 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10374 09:30:09.157241 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10375 09:30:09.163574 <6>[ 0.009179] Console: colour dummy device 80x25
10376 09:30:09.173932 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10377 09:30:09.177091 <6>[ 0.024413] pid_max: default: 32768 minimum: 301
10378 09:30:09.183201 <6>[ 0.029284] LSM: Security Framework initializing
10379 09:30:09.189867 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 09:30:09.199939 <6>[ 0.042036] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 09:30:09.206849 <6>[ 0.051449] cblist_init_generic: Setting adjustable number of callback queues.
10382 09:30:09.213160 <6>[ 0.058938] cblist_init_generic: Setting shift to 3 and lim to 1.
10383 09:30:09.220201 <6>[ 0.065275] cblist_init_generic: Setting adjustable number of callback queues.
10384 09:30:09.226964 <6>[ 0.072702] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 09:30:09.233663 <6>[ 0.079142] rcu: Hierarchical SRCU implementation.
10386 09:30:09.240245 <6>[ 0.084157] rcu: Max phase no-delay instances is 1000.
10387 09:30:09.246545 <6>[ 0.091183] EFI services will not be available.
10388 09:30:09.249582 <6>[ 0.096137] smp: Bringing up secondary CPUs ...
10389 09:30:09.258011 <6>[ 0.101186] Detected VIPT I-cache on CPU1
10390 09:30:09.264550 <6>[ 0.101254] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 09:30:09.270646 <6>[ 0.101284] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 09:30:09.274536 <6>[ 0.101613] Detected VIPT I-cache on CPU2
10393 09:30:09.281000 <6>[ 0.101663] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 09:30:09.287202 <6>[ 0.101679] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 09:30:09.294115 <6>[ 0.101936] Detected VIPT I-cache on CPU3
10396 09:30:09.301080 <6>[ 0.101983] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 09:30:09.307316 <6>[ 0.101997] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 09:30:09.311068 <6>[ 0.102306] CPU features: detected: Spectre-v4
10399 09:30:09.317142 <6>[ 0.102312] CPU features: detected: Spectre-BHB
10400 09:30:09.320554 <6>[ 0.102316] Detected PIPT I-cache on CPU4
10401 09:30:09.327254 <6>[ 0.102373] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 09:30:09.333738 <6>[ 0.102390] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 09:30:09.340737 <6>[ 0.102681] Detected PIPT I-cache on CPU5
10404 09:30:09.347055 <6>[ 0.102744] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 09:30:09.353773 <6>[ 0.102761] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 09:30:09.357548 <6>[ 0.103041] Detected PIPT I-cache on CPU6
10407 09:30:09.364045 <6>[ 0.103106] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 09:30:09.370419 <6>[ 0.103122] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 09:30:09.377277 <6>[ 0.103418] Detected PIPT I-cache on CPU7
10410 09:30:09.383602 <6>[ 0.103483] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 09:30:09.390637 <6>[ 0.103499] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 09:30:09.393778 <6>[ 0.103546] smp: Brought up 1 node, 8 CPUs
10413 09:30:09.400583 <6>[ 0.244797] SMP: Total of 8 processors activated.
10414 09:30:09.403761 <6>[ 0.249725] CPU features: detected: 32-bit EL0 Support
10415 09:30:09.413314 <6>[ 0.255088] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 09:30:09.420417 <6>[ 0.263944] CPU features: detected: Common not Private translations
10417 09:30:09.423301 <6>[ 0.270420] CPU features: detected: CRC32 instructions
10418 09:30:09.430408 <6>[ 0.275771] CPU features: detected: RCpc load-acquire (LDAPR)
10419 09:30:09.436549 <6>[ 0.281731] CPU features: detected: LSE atomic instructions
10420 09:30:09.443467 <6>[ 0.287512] CPU features: detected: Privileged Access Never
10421 09:30:09.446564 <6>[ 0.293292] CPU features: detected: RAS Extension Support
10422 09:30:09.456505 <6>[ 0.298936] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 09:30:09.459855 <6>[ 0.306198] CPU: All CPU(s) started at EL2
10424 09:30:09.466463 <6>[ 0.310515] alternatives: applying system-wide alternatives
10425 09:30:09.475374 <6>[ 0.321228] devtmpfs: initialized
10426 09:30:09.487503 <6>[ 0.330322] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 09:30:09.497766 <6>[ 0.340274] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 09:30:09.504429 <6>[ 0.348286] pinctrl core: initialized pinctrl subsystem
10429 09:30:09.507778 <6>[ 0.354928] DMI not present or invalid.
10430 09:30:09.514135 <6>[ 0.359333] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 09:30:09.524196 <6>[ 0.366189] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 09:30:09.531160 <6>[ 0.373773] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 09:30:09.540588 <6>[ 0.381990] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 09:30:09.544155 <6>[ 0.390229] audit: initializing netlink subsys (disabled)
10435 09:30:09.553719 <5>[ 0.395921] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10436 09:30:09.560562 <6>[ 0.396630] thermal_sys: Registered thermal governor 'step_wise'
10437 09:30:09.567301 <6>[ 0.403881] thermal_sys: Registered thermal governor 'power_allocator'
10438 09:30:09.570524 <6>[ 0.410140] cpuidle: using governor menu
10439 09:30:09.576900 <6>[ 0.421105] NET: Registered PF_QIPCRTR protocol family
10440 09:30:09.583621 <6>[ 0.426597] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 09:30:09.586753 <6>[ 0.433700] ASID allocator initialised with 32768 entries
10442 09:30:09.594326 <6>[ 0.440256] Serial: AMBA PL011 UART driver
10443 09:30:09.602962 <4>[ 0.449030] Trying to register duplicate clock ID: 134
10444 09:30:09.658083 <6>[ 0.507090] KASLR enabled
10445 09:30:09.672188 <6>[ 0.514794] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 09:30:09.679198 <6>[ 0.521810] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 09:30:09.685850 <6>[ 0.528298] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 09:30:09.692247 <6>[ 0.535300] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 09:30:09.698492 <6>[ 0.541788] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 09:30:09.705281 <6>[ 0.548792] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 09:30:09.711913 <6>[ 0.555278] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 09:30:09.718586 <6>[ 0.562282] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 09:30:09.722016 <6>[ 0.569798] ACPI: Interpreter disabled.
10454 09:30:09.730590 <6>[ 0.576210] iommu: Default domain type: Translated
10455 09:30:09.737180 <6>[ 0.581320] iommu: DMA domain TLB invalidation policy: strict mode
10456 09:30:09.740696 <5>[ 0.587980] SCSI subsystem initialized
10457 09:30:09.747008 <6>[ 0.592130] usbcore: registered new interface driver usbfs
10458 09:30:09.753880 <6>[ 0.597863] usbcore: registered new interface driver hub
10459 09:30:09.756795 <6>[ 0.603415] usbcore: registered new device driver usb
10460 09:30:09.763388 <6>[ 0.609502] pps_core: LinuxPPS API ver. 1 registered
10461 09:30:09.773452 <6>[ 0.614698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 09:30:09.776545 <6>[ 0.624044] PTP clock support registered
10463 09:30:09.780128 <6>[ 0.628284] EDAC MC: Ver: 3.0.0
10464 09:30:09.787770 <6>[ 0.633436] FPGA manager framework
10465 09:30:09.794264 <6>[ 0.637115] Advanced Linux Sound Architecture Driver Initialized.
10466 09:30:09.797386 <6>[ 0.643891] vgaarb: loaded
10467 09:30:09.804509 <6>[ 0.647068] clocksource: Switched to clocksource arch_sys_counter
10468 09:30:09.807313 <5>[ 0.653509] VFS: Disk quotas dquot_6.6.0
10469 09:30:09.813813 <6>[ 0.657692] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 09:30:09.816964 <6>[ 0.664878] pnp: PnP ACPI: disabled
10471 09:30:09.825631 <6>[ 0.671625] NET: Registered PF_INET protocol family
10472 09:30:09.835552 <6>[ 0.677222] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 09:30:09.846934 <6>[ 0.689547] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 09:30:09.856923 <6>[ 0.698361] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 09:30:09.863511 <6>[ 0.706332] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 09:30:09.869902 <6>[ 0.715031] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 09:30:09.882306 <6>[ 0.724797] TCP: Hash tables configured (established 65536 bind 65536)
10478 09:30:09.888520 <6>[ 0.731657] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 09:30:09.895521 <6>[ 0.738857] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 09:30:09.902100 <6>[ 0.746561] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 09:30:09.908457 <6>[ 0.752709] RPC: Registered named UNIX socket transport module.
10482 09:30:09.912110 <6>[ 0.758860] RPC: Registered udp transport module.
10483 09:30:09.918459 <6>[ 0.763792] RPC: Registered tcp transport module.
10484 09:30:09.925286 <6>[ 0.768725] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 09:30:09.928437 <6>[ 0.775389] PCI: CLS 0 bytes, default 64
10486 09:30:09.931510 <6>[ 0.779707] Unpacking initramfs...
10487 09:30:09.949180 <6>[ 0.791628] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 09:30:09.959060 <6>[ 0.800276] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 09:30:09.961907 <6>[ 0.809124] kvm [1]: IPA Size Limit: 40 bits
10490 09:30:09.968886 <6>[ 0.813652] kvm [1]: GICv3: no GICV resource entry
10491 09:30:09.972234 <6>[ 0.818669] kvm [1]: disabling GICv2 emulation
10492 09:30:09.978524 <6>[ 0.823359] kvm [1]: GIC system register CPU interface enabled
10493 09:30:09.985498 <6>[ 0.831111] kvm [1]: vgic interrupt IRQ18
10494 09:30:09.988803 <6>[ 0.835495] kvm [1]: VHE mode initialized successfully
10495 09:30:09.996132 <5>[ 0.841885] Initialise system trusted keyrings
10496 09:30:10.002483 <6>[ 0.846676] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 09:30:10.010637 <6>[ 0.856602] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 09:30:10.017599 <5>[ 0.862975] NFS: Registering the id_resolver key type
10499 09:30:10.020650 <5>[ 0.868272] Key type id_resolver registered
10500 09:30:10.027488 <5>[ 0.872684] Key type id_legacy registered
10501 09:30:10.033997 <6>[ 0.876957] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 09:30:10.040464 <6>[ 0.883878] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 09:30:10.047294 <6>[ 0.891608] 9p: Installing v9fs 9p2000 file system support
10504 09:30:10.084007 <5>[ 0.929690] Key type asymmetric registered
10505 09:30:10.086954 <5>[ 0.934020] Asymmetric key parser 'x509' registered
10506 09:30:10.097203 <6>[ 0.939158] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 09:30:10.100492 <6>[ 0.946769] io scheduler mq-deadline registered
10508 09:30:10.103478 <6>[ 0.951531] io scheduler kyber registered
10509 09:30:10.122855 <6>[ 0.968667] EINJ: ACPI disabled.
10510 09:30:10.154439 <4>[ 0.993770] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 09:30:10.163942 <4>[ 1.004485] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 09:30:10.178933 <6>[ 1.025102] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 09:30:10.187261 <6>[ 1.033039] printk: console [ttyS0] disabled
10514 09:30:10.214812 <6>[ 1.057684] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 09:30:10.221789 <6>[ 1.067172] printk: console [ttyS0] enabled
10516 09:30:10.225091 <6>[ 1.067172] printk: console [ttyS0] enabled
10517 09:30:10.231686 <6>[ 1.076067] printk: bootconsole [mtk8250] disabled
10518 09:30:10.234828 <6>[ 1.076067] printk: bootconsole [mtk8250] disabled
10519 09:30:10.241564 <6>[ 1.087094] SuperH (H)SCI(F) driver initialized
10520 09:30:10.244735 <6>[ 1.092359] msm_serial: driver initialized
10521 09:30:10.258410 <6>[ 1.101274] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 09:30:10.268736 <6>[ 1.109819] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 09:30:10.275539 <6>[ 1.118360] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 09:30:10.285617 <6>[ 1.126994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 09:30:10.292169 <6>[ 1.135706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 09:30:10.301748 <6>[ 1.144419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 09:30:10.311599 <6>[ 1.152958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 09:30:10.318644 <6>[ 1.161745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 09:30:10.328466 <6>[ 1.170287] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 09:30:10.339908 <6>[ 1.185715] loop: module loaded
10531 09:30:10.346096 <6>[ 1.191781] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 09:30:10.369240 <4>[ 1.215009] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 09:30:10.375997 <6>[ 1.221849] megasas: 07.719.03.00-rc1
10534 09:30:10.385292 <6>[ 1.231299] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 09:30:10.392490 <6>[ 1.238454] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 09:30:10.409577 <6>[ 1.255238] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 09:30:10.465579 <6>[ 1.305203] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10538 09:30:10.670183 <6>[ 1.516200] Freeing initrd memory: 17372K
10539 09:30:10.680349 <6>[ 1.526649] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 09:30:10.691902 <6>[ 1.537581] tun: Universal TUN/TAP device driver, 1.6
10541 09:30:10.695187 <6>[ 1.543648] thunder_xcv, ver 1.0
10542 09:30:10.698106 <6>[ 1.547151] thunder_bgx, ver 1.0
10543 09:30:10.701844 <6>[ 1.550640] nicpf, ver 1.0
10544 09:30:10.712023 <6>[ 1.554655] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 09:30:10.715268 <6>[ 1.562131] hns3: Copyright (c) 2017 Huawei Corporation.
10546 09:30:10.722233 <6>[ 1.567719] hclge is initializing
10547 09:30:10.725184 <6>[ 1.571298] e1000: Intel(R) PRO/1000 Network Driver
10548 09:30:10.732119 <6>[ 1.576427] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 09:30:10.735214 <6>[ 1.582444] e1000e: Intel(R) PRO/1000 Network Driver
10550 09:30:10.741841 <6>[ 1.587660] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 09:30:10.748539 <6>[ 1.593845] igb: Intel(R) Gigabit Ethernet Network Driver
10552 09:30:10.755248 <6>[ 1.599495] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 09:30:10.762241 <6>[ 1.605333] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 09:30:10.765360 <6>[ 1.611852] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 09:30:10.772106 <6>[ 1.618313] sky2: driver version 1.30
10556 09:30:10.779105 <6>[ 1.623325] VFIO - User Level meta-driver version: 0.3
10557 09:30:10.785539 <6>[ 1.631569] usbcore: registered new interface driver usb-storage
10558 09:30:10.791923 <6>[ 1.638013] usbcore: registered new device driver onboard-usb-hub
10559 09:30:10.801470 <6>[ 1.647129] mt6397-rtc mt6359-rtc: registered as rtc0
10560 09:30:10.811321 <6>[ 1.652590] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:28:37 UTC (1697794117)
10561 09:30:10.814809 <6>[ 1.662149] i2c_dev: i2c /dev entries driver
10562 09:30:10.830730 <6>[ 1.673787] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10563 09:30:10.851116 <6>[ 1.696780] cpu cpu0: EM: created perf domain
10564 09:30:10.854224 <6>[ 1.701696] cpu cpu4: EM: created perf domain
10565 09:30:10.860997 <6>[ 1.707285] sdhci: Secure Digital Host Controller Interface driver
10566 09:30:10.868128 <6>[ 1.713714] sdhci: Copyright(c) Pierre Ossman
10567 09:30:10.874763 <6>[ 1.718668] Synopsys Designware Multimedia Card Interface Driver
10568 09:30:10.881093 <6>[ 1.725303] sdhci-pltfm: SDHCI platform and OF driver helper
10569 09:30:10.884841 <6>[ 1.725424] mmc0: CQHCI version 5.10
10570 09:30:10.891230 <6>[ 1.735292] ledtrig-cpu: registered to indicate activity on CPUs
10571 09:30:10.898340 <6>[ 1.742203] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10572 09:30:10.904611 <6>[ 1.749248] usbcore: registered new interface driver usbhid
10573 09:30:10.907749 <6>[ 1.755073] usbhid: USB HID core driver
10574 09:30:10.914502 <6>[ 1.759285] spi_master spi0: will run message pump with realtime priority
10575 09:30:10.957304 <6>[ 1.796823] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10576 09:30:10.973318 <6>[ 1.812769] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10577 09:30:10.981012 <6>[ 1.826389] mmc0: Command Queue Engine enabled
10578 09:30:10.987606 <6>[ 1.831162] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10579 09:30:10.994393 <6>[ 1.838095] cros-ec-spi spi0.0: Chrome EC device registered
10580 09:30:10.997301 <6>[ 1.838389] mmcblk0: mmc0:0001 DA4128 116 GiB
10581 09:30:11.009326 <6>[ 1.855091] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10582 09:30:11.016271 <6>[ 1.862426] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 09:30:11.026358 <6>[ 1.866673] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 09:30:11.029389 <6>[ 1.868362] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10585 09:30:11.036515 <6>[ 1.878216] NET: Registered PF_PACKET protocol family
10586 09:30:11.043153 <6>[ 1.882769] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10587 09:30:11.046279 <6>[ 1.887577] 9pnet: Installing 9P2000 support
10588 09:30:11.053205 <5>[ 1.898562] Key type dns_resolver registered
10589 09:30:11.056380 <6>[ 1.903527] registered taskstats version 1
10590 09:30:11.063025 <5>[ 1.907903] Loading compiled-in X.509 certificates
10591 09:30:11.090777 <4>[ 1.930076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 09:30:11.100724 <4>[ 1.940843] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 09:30:11.107405 <3>[ 1.951378] debugfs: File 'uA_load' in directory '/' already present!
10594 09:30:11.114138 <3>[ 1.958133] debugfs: File 'min_uV' in directory '/' already present!
10595 09:30:11.120621 <3>[ 1.964751] debugfs: File 'max_uV' in directory '/' already present!
10596 09:30:11.127104 <3>[ 1.971363] debugfs: File 'constraint_flags' in directory '/' already present!
10597 09:30:11.138858 <3>[ 1.981735] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10598 09:30:11.150055 <6>[ 1.996127] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10599 09:30:11.157041 <6>[ 2.002929] xhci-mtk 11200000.usb: xHCI Host Controller
10600 09:30:11.163544 <6>[ 2.008426] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10601 09:30:11.173522 <6>[ 2.016262] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10602 09:30:11.180335 <6>[ 2.025686] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10603 09:30:11.186770 <6>[ 2.031773] xhci-mtk 11200000.usb: xHCI Host Controller
10604 09:30:11.193139 <6>[ 2.037251] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10605 09:30:11.200320 <6>[ 2.044901] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10606 09:30:11.206638 <6>[ 2.052598] hub 1-0:1.0: USB hub found
10607 09:30:11.209812 <6>[ 2.056611] hub 1-0:1.0: 1 port detected
10608 09:30:11.216696 <6>[ 2.060884] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10609 09:30:11.223446 <6>[ 2.069430] hub 2-0:1.0: USB hub found
10610 09:30:11.226568 <6>[ 2.073438] hub 2-0:1.0: 1 port detected
10611 09:30:11.234701 <6>[ 2.081101] mtk-msdc 11f70000.mmc: Got CD GPIO
10612 09:30:11.245437 <6>[ 2.088294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10613 09:30:11.252135 <6>[ 2.096328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10614 09:30:11.262306 <4>[ 2.104231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10615 09:30:11.272183 <6>[ 2.113767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10616 09:30:11.278834 <6>[ 2.121844] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10617 09:30:11.285491 <6>[ 2.129874] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10618 09:30:11.295448 <6>[ 2.137799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10619 09:30:11.302515 <6>[ 2.145616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10620 09:30:11.312223 <6>[ 2.153433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10621 09:30:11.321869 <6>[ 2.163966] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10622 09:30:11.329002 <6>[ 2.172340] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10623 09:30:11.338508 <6>[ 2.180690] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10624 09:30:11.345310 <6>[ 2.189029] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10625 09:30:11.355493 <6>[ 2.197368] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10626 09:30:11.361947 <6>[ 2.205706] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10627 09:30:11.371952 <6>[ 2.214043] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10628 09:30:11.378509 <6>[ 2.222381] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10629 09:30:11.388745 <6>[ 2.230719] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10630 09:30:11.395513 <6>[ 2.239068] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10631 09:30:11.405454 <6>[ 2.247407] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10632 09:30:11.411835 <6>[ 2.255748] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10633 09:30:11.422104 <6>[ 2.264087] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10634 09:30:11.428571 <6>[ 2.272426] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10635 09:30:11.438921 <6>[ 2.280765] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10636 09:30:11.445273 <6>[ 2.289500] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10637 09:30:11.452205 <6>[ 2.296664] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10638 09:30:11.458615 <6>[ 2.303415] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10639 09:30:11.465083 <6>[ 2.310176] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10640 09:30:11.471968 <6>[ 2.317121] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10641 09:30:11.481734 <6>[ 2.323979] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10642 09:30:11.491864 <6>[ 2.333111] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10643 09:30:11.501866 <6>[ 2.342231] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10644 09:30:11.508156 <6>[ 2.351524] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10645 09:30:11.517993 <6>[ 2.360992] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10646 09:30:11.528207 <6>[ 2.370459] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10647 09:30:11.537909 <6>[ 2.379579] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10648 09:30:11.548053 <6>[ 2.389050] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10649 09:30:11.557672 <6>[ 2.398169] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10650 09:30:11.568146 <6>[ 2.407464] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10651 09:30:11.577673 <6>[ 2.417624] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10652 09:30:11.587449 <6>[ 2.429140] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10653 09:30:11.594512 <6>[ 2.439008] Trying to probe devices needed for running init ...
10654 09:30:11.636146 <6>[ 2.479338] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10655 09:30:11.791277 <6>[ 2.637369] hub 1-1:1.0: USB hub found
10656 09:30:11.794252 <6>[ 2.641879] hub 1-1:1.0: 4 ports detected
10657 09:30:11.916316 <6>[ 2.759314] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10658 09:30:11.943337 <6>[ 2.789235] hub 2-1:1.0: USB hub found
10659 09:30:11.946715 <6>[ 2.793730] hub 2-1:1.0: 3 ports detected
10660 09:30:12.116753 <6>[ 2.959432] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10661 09:30:12.248330 <6>[ 3.094272] hub 1-1.4:1.0: USB hub found
10662 09:30:12.251072 <6>[ 3.098826] hub 1-1.4:1.0: 2 ports detected
10663 09:30:12.328436 <6>[ 3.171416] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10664 09:30:12.548737 <6>[ 3.391382] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10665 09:30:12.740438 <6>[ 3.583366] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10666 09:30:23.885631 <6>[ 14.736397] ALSA device list:
10667 09:30:23.892225 <6>[ 14.739688] No soundcards found.
10668 09:30:23.900013 <6>[ 14.747629] Freeing unused kernel memory: 8384K
10669 09:30:23.903214 <6>[ 14.752618] Run /init as init process
10670 09:30:23.914627 Loading, please wait...
10671 09:30:23.935192 Starting version 247.3-7+deb11u2
10672 09:30:24.128104 <6>[ 14.972244] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 09:30:24.137824 <6>[ 14.980664] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10674 09:30:24.144952 <6>[ 14.989529] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10675 09:30:24.189679 <3>[ 15.004952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 09:30:24.189860 <3>[ 15.013313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 09:30:24.189970 <6>[ 15.014051] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10678 09:30:24.190065 <3>[ 15.021541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 09:30:24.193597 <3>[ 15.022266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 09:30:24.197488 <6>[ 15.029268] mc: Linux media interface: v0.10
10681 09:30:24.203681 <3>[ 15.037057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 09:30:24.210664 <6>[ 15.052565] remoteproc remoteproc0: scp is available
10683 09:30:24.217038 <6>[ 15.055942] usbcore: registered new interface driver r8152
10684 09:30:24.223426 <3>[ 15.057683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 09:30:24.230005 <6>[ 15.062965] remoteproc remoteproc0: powering up scp
10686 09:30:24.236978 <4>[ 15.068606] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10687 09:30:24.243590 <3>[ 15.068628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 09:30:24.253276 <4>[ 15.069752] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10689 09:30:24.260854 <6>[ 15.072352] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10690 09:30:24.267238 <6>[ 15.076712] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10691 09:30:24.277495 <3>[ 15.081845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 09:30:24.280933 <6>[ 15.082236] videodev: Linux video capture interface: v2.00
10693 09:30:24.287379 <6>[ 15.089197] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10694 09:30:24.294300 <3>[ 15.097253] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 09:30:24.304270 <4>[ 15.097349] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10696 09:30:24.307532 <4>[ 15.097349] Fallback method does not support PEC.
10697 09:30:24.317820 <3>[ 15.117092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10698 09:30:24.324178 <6>[ 15.120399] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10699 09:30:24.330676 <6>[ 15.120406] pci_bus 0000:00: root bus resource [bus 00-ff]
10700 09:30:24.337741 <6>[ 15.120412] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10701 09:30:24.347438 <6>[ 15.120417] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10702 09:30:24.353913 <6>[ 15.120476] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10703 09:30:24.360523 <6>[ 15.120545] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10704 09:30:24.370588 <3>[ 15.120618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 09:30:24.377205 <3>[ 15.120623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 09:30:24.387415 <3>[ 15.120625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 09:30:24.393654 <3>[ 15.120681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 09:30:24.403291 <3>[ 15.120684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 09:30:24.410448 <3>[ 15.120687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 09:30:24.413265 <6>[ 15.120825] pci 0000:00:00.0: supports D1 D2
10711 09:30:24.423276 <6>[ 15.120829] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10712 09:30:24.429853 <6>[ 15.122673] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 09:30:24.436358 <6>[ 15.122914] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10714 09:30:24.443393 <6>[ 15.122950] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10715 09:30:24.449724 <6>[ 15.122976] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10716 09:30:24.459831 <6>[ 15.122995] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10717 09:30:24.462856 <6>[ 15.123151] pci 0000:01:00.0: supports D1 D2
10718 09:30:24.469959 <6>[ 15.123156] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 09:30:24.479763 <6>[ 15.131666] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10720 09:30:24.489842 <3>[ 15.134510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 09:30:24.495920 <6>[ 15.140262] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10722 09:30:24.502574 <6>[ 15.140594] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10723 09:30:24.512514 <6>[ 15.147497] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10724 09:30:24.519718 <3>[ 15.148235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 09:30:24.526221 <3>[ 15.148259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 09:30:24.535718 <3>[ 15.150956] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 09:30:24.546102 <6>[ 15.161918] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10728 09:30:24.552430 <4>[ 15.171188] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10729 09:30:24.562768 <6>[ 15.177813] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10730 09:30:24.568988 <6>[ 15.181605] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10731 09:30:24.579066 <4>[ 15.183508] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10732 09:30:24.585774 <6>[ 15.190623] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10733 09:30:24.595364 <6>[ 15.190647] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10734 09:30:24.602407 <6>[ 15.190662] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10735 09:30:24.608793 <6>[ 15.190678] pci 0000:00:00.0: PCI bridge to [bus 01]
10736 09:30:24.615447 <6>[ 15.190686] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10737 09:30:24.622281 <6>[ 15.192590] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10738 09:30:24.628721 <6>[ 15.200976] usbcore: registered new interface driver cdc_ether
10739 09:30:24.635955 <6>[ 15.207714] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10740 09:30:24.639077 <6>[ 15.215813] r8152 2-1.3:1.0 eth0: v1.12.13
10741 09:30:24.645693 <6>[ 15.222819] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10742 09:30:24.652242 <6>[ 15.223195] usbcore: registered new interface driver r8153_ecm
10743 09:30:24.655318 <6>[ 15.223234] Bluetooth: Core ver 2.22
10744 09:30:24.658660 <6>[ 15.223426] NET: Registered PF_BLUETOOTH protocol family
10745 09:30:24.665092 <6>[ 15.223435] Bluetooth: HCI device and connection manager initialized
10746 09:30:24.672101 <6>[ 15.223458] Bluetooth: HCI socket layer initialized
10747 09:30:24.678283 <6>[ 15.223463] Bluetooth: L2CAP socket layer initialized
10748 09:30:24.682147 <6>[ 15.223480] Bluetooth: SCO socket layer initialized
10749 09:30:24.691938 <6>[ 15.230717] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10750 09:30:24.698187 <6>[ 15.230735] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10751 09:30:24.705308 <6>[ 15.240606] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10752 09:30:24.711602 <6>[ 15.246810] remoteproc remoteproc0: remote processor scp is now up
10753 09:30:24.718480 <6>[ 15.248812] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10754 09:30:24.724837 <6>[ 15.250652] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10755 09:30:24.734862 <6>[ 15.253328] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10756 09:30:24.744944 <6>[ 15.256819] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10757 09:30:24.751512 <6>[ 15.275243] usbcore: registered new interface driver btusb
10758 09:30:24.757736 <6>[ 15.275413] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10759 09:30:24.767827 <4>[ 15.276347] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10760 09:30:24.774328 <3>[ 15.276358] Bluetooth: hci0: Failed to load firmware file (-2)
10761 09:30:24.781351 <3>[ 15.276361] Bluetooth: hci0: Failed to set up firmware (-2)
10762 09:30:24.791228 <4>[ 15.276365] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10763 09:30:24.797947 <6>[ 15.282952] usbcore: registered new interface driver uvcvideo
10764 09:30:24.804234 <5>[ 15.288415] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10765 09:30:24.811354 <5>[ 15.299158] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10766 09:30:24.821262 <4>[ 15.664941] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10767 09:30:24.827715 <6>[ 15.673870] cfg80211: failed to load regulatory.db
10768 09:30:24.866051 <6>[ 15.710355] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10769 09:30:24.872377 <6>[ 15.717858] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10770 09:30:24.896659 <6>[ 15.744501] mt7921e 0000:01:00.0: ASIC revision: 79610010
10771 09:30:25.002444 <4>[ 15.843420] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 09:30:25.016769 Begin: Loading essential drivers ... done.
10773 09:30:25.023413 Begin: Running /scripts/init-premount ... done.
10774 09:30:25.029809 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10775 09:30:25.036817 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10776 09:30:25.039832 Device /sys/class/net/enx00e04c787aaa found
10777 09:30:25.042974 done.
10778 09:30:25.120893 <4>[ 15.962048] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 09:30:25.127828 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10780 09:30:25.239720 <4>[ 16.080965] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 09:30:25.355291 <4>[ 16.196359] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 09:30:25.471347 <4>[ 16.312246] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 09:30:25.586888 <4>[ 16.428181] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 09:30:25.703399 <4>[ 16.544140] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 09:30:25.819123 <4>[ 16.660089] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 09:30:25.935125 <4>[ 16.776051] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 09:30:26.050743 <4>[ 16.892014] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 09:30:26.090090 <6>[ 16.938003] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10789 09:30:26.157936 <3>[ 17.005920] mt7921e 0000:01:00.0: hardware init failed
10790 09:30:26.304939 IP-Config: no response after 2 secs - giving up
10791 09:30:26.347053 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10792 09:30:26.353547 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10793 09:30:26.360309 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10794 09:30:26.366644 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10795 09:30:26.373635 host : mt8192-asurada-spherion-r0-cbg-0
10796 09:30:26.380046 domain : lava-rack
10797 09:30:26.383502 rootserver: 192.168.201.1 rootpath:
10798 09:30:26.386772 filename :
10799 09:30:26.478123 done.
10800 09:30:26.484818 Begin: Running /scripts/nfs-bottom ... done.
10801 09:30:26.505601 Begin: Running /scripts/init-bottom ... done.
10802 09:30:27.665142 <6>[ 18.512742] NET: Registered PF_INET6 protocol family
10803 09:30:27.672405 <6>[ 18.520126] Segment Routing with IPv6
10804 09:30:27.675407 <6>[ 18.524168] In-situ OAM (IOAM) with IPv6
10805 09:30:27.786740 <30>[ 18.617971] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10806 09:30:27.794160 <30>[ 18.642330] systemd[1]: Detected architecture arm64.
10807 09:30:27.813560
10808 09:30:27.816712 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10809 09:30:27.816801
10810 09:30:27.833465 <30>[ 18.681360] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10811 09:30:28.596709 <30>[ 19.441547] systemd[1]: Queued start job for default target Graphical Interface.
10812 09:30:28.629757 <30>[ 19.477773] systemd[1]: Created slice system-getty.slice.
10813 09:30:28.636133 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10814 09:30:28.652698 <30>[ 19.500773] systemd[1]: Created slice system-modprobe.slice.
10815 09:30:28.659458 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10816 09:30:28.677443 <30>[ 19.525482] systemd[1]: Created slice system-serial\x2dgetty.slice.
10817 09:30:28.687675 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10818 09:30:28.700181 <30>[ 19.548395] systemd[1]: Created slice User and Session Slice.
10819 09:30:28.707119 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10820 09:30:28.727924 <30>[ 19.572215] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10821 09:30:28.737397 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10822 09:30:28.755518 <30>[ 19.600106] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10823 09:30:28.762053 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10824 09:30:28.786208 <30>[ 19.627499] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10825 09:30:28.793144 <30>[ 19.639643] systemd[1]: Reached target Local Encrypted Volumes.
10826 09:30:28.799503 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10827 09:30:28.815568 <30>[ 19.663892] systemd[1]: Reached target Paths.
10828 09:30:28.822190 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10829 09:30:28.835287 <30>[ 19.683346] systemd[1]: Reached target Remote File Systems.
10830 09:30:28.842241 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10831 09:30:28.859881 <30>[ 19.707728] systemd[1]: Reached target Slices.
10832 09:30:28.866403 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10833 09:30:28.879366 <30>[ 19.727373] systemd[1]: Reached target Swap.
10834 09:30:28.882630 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10835 09:30:28.902688 <30>[ 19.747847] systemd[1]: Listening on initctl Compatibility Named Pipe.
10836 09:30:28.909540 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10837 09:30:28.916213 <30>[ 19.763874] systemd[1]: Listening on Journal Audit Socket.
10838 09:30:28.923135 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10839 09:30:28.940527 <30>[ 19.788514] systemd[1]: Listening on Journal Socket (/dev/log).
10840 09:30:28.946802 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10841 09:30:28.963810 <30>[ 19.811909] systemd[1]: Listening on Journal Socket.
10842 09:30:28.970035 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10843 09:30:28.987921 <30>[ 19.832714] systemd[1]: Listening on Network Service Netlink Socket.
10844 09:30:28.994240 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10845 09:30:29.009376 <30>[ 19.857677] systemd[1]: Listening on udev Control Socket.
10846 09:30:29.016412 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10847 09:30:29.031481 <30>[ 19.879780] systemd[1]: Listening on udev Kernel Socket.
10848 09:30:29.037838 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10849 09:30:29.087704 <30>[ 19.935817] systemd[1]: Mounting Huge Pages File System...
10850 09:30:29.093998 Mounting [0;1;39mHuge Pages File System[0m...
10851 09:30:29.109607 <30>[ 19.957587] systemd[1]: Mounting POSIX Message Queue File System...
10852 09:30:29.116529 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10853 09:30:29.134543 <30>[ 19.982363] systemd[1]: Mounting Kernel Debug File System...
10854 09:30:29.140842 Mounting [0;1;39mKernel Debug File System[0m...
10855 09:30:29.158935 <30>[ 20.003845] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10856 09:30:29.182948 <30>[ 20.027693] systemd[1]: Starting Create list of static device nodes for the current kernel...
10857 09:30:29.189230 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10858 09:30:29.212598 <30>[ 20.060399] systemd[1]: Starting Load Kernel Module configfs...
10859 09:30:29.218940 Starting [0;1;39mLoad Kernel Module configfs[0m...
10860 09:30:29.239896 <30>[ 20.088269] systemd[1]: Starting Load Kernel Module drm...
10861 09:30:29.246678 Starting [0;1;39mLoad Kernel Module drm[0m...
10862 09:30:29.268734 <30>[ 20.116639] systemd[1]: Starting Load Kernel Module fuse...
10863 09:30:29.275217 Starting [0;1;39mLoad Kernel Module fuse[0m...
10864 09:30:29.303965 <6>[ 20.151747] fuse: init (API version 7.37)
10865 09:30:29.313404 <30>[ 20.152850] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 09:30:29.347709 <30>[ 20.196078] systemd[1]: Starting Journal Service...
10867 09:30:29.354678 Starting [0;1;39mJournal Service[0m...
10868 09:30:29.376838 <30>[ 20.224821] systemd[1]: Starting Load Kernel Modules...
10869 09:30:29.383219 Starting [0;1;39mLoad Kernel Modules[0m...
10870 09:30:29.404108 <30>[ 20.248954] systemd[1]: Starting Remount Root and Kernel File Systems...
10871 09:30:29.410885 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10872 09:30:29.429060 <30>[ 20.277083] systemd[1]: Starting Coldplug All udev Devices...
10873 09:30:29.435747 Starting [0;1;39mColdplug All udev Devices[0m...
10874 09:30:29.454839 <30>[ 20.302696] systemd[1]: Mounted Huge Pages File System.
10875 09:30:29.461122 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10876 09:30:29.472555 <3>[ 20.317637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 09:30:29.479398 <30>[ 20.327281] systemd[1]: Mounted POSIX Message Queue File System.
10878 09:30:29.485769 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10879 09:30:29.503257 <30>[ 20.351649] systemd[1]: Mounted Kernel Debug File System.
10880 09:30:29.513338 <3>[ 20.351692] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 09:30:29.520403 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10882 09:30:29.539588 <30>[ 20.384436] systemd[1]: Finished Create list of static device nodes for the current kernel.
10883 09:30:29.556655 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current<3>[ 20.398930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 09:30:29.556828 kernel[0m.
10885 09:30:29.572691 <30>[ 20.420619] systemd[1]: modprobe@configfs.service: Succeeded.
10886 09:30:29.579796 <30>[ 20.427626] systemd[1]: Finished Load Kernel Module configfs.
10887 09:30:29.589935 <3>[ 20.429591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 09:30:29.596270 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10889 09:30:29.612413 <30>[ 20.460231] systemd[1]: modprobe@drm.service: Succeeded.
10890 09:30:29.622632 <3>[ 20.465395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 09:30:29.625821 <30>[ 20.466971] systemd[1]: Finished Load Kernel Module drm.
10892 09:30:29.632823 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10893 09:30:29.649050 <30>[ 20.497418] systemd[1]: modprobe@fuse.service: Succeeded.
10894 09:30:29.659153 <3>[ 20.498523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 09:30:29.665764 <30>[ 20.505024] systemd[1]: Finished Load Kernel Module fuse.
10896 09:30:29.668995 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10897 09:30:29.688646 <3>[ 20.533585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 09:30:29.696153 <30>[ 20.544530] systemd[1]: Finished Load Kernel Modules.
10899 09:30:29.703084 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10900 09:30:29.718122 <3>[ 20.563291] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 09:30:29.725247 <30>[ 20.564745] systemd[1]: Finished Remount Root and Kernel File Systems.
10902 09:30:29.731629 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10903 09:30:29.749116 <3>[ 20.593475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 09:30:29.777796 <3>[ 20.622629] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 09:30:29.784690 <30>[ 20.623273] systemd[1]: Mounting FUSE Control File System...
10906 09:30:29.790943 Mounting [0;1;39mFUSE Control File System[0m...
10907 09:30:29.810608 <30>[ 20.655357] systemd[1]: Mounting Kernel Configuration File System...
10908 09:30:29.813784 Mounting [0;1;39mKernel Configuration File System[0m...
10909 09:30:29.838336 <30>[ 20.683053] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10910 09:30:29.847951 <30>[ 20.692262] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10911 09:30:29.876023 <30>[ 20.723913] systemd[1]: Starting Load/Save Random Seed...
10912 09:30:29.882396 Starting [0;1;39mLoad/Save Random Seed[0m...
10913 09:30:29.899976 <30>[ 20.747664] systemd[1]: Starting Apply Kernel Variables...
10914 09:30:29.919934 Starting [0;1;39mApply Kernel Variable<4>[ 20.757732] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10915 09:30:29.920080 s[0m...
10916 09:30:29.929734 <3>[ 20.773624] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10917 09:30:29.938348 <30>[ 20.786476] systemd[1]: Starting Create System Users...
10918 09:30:29.944962 Starting [0;1;39mCreate System Users[0m...
10919 09:30:29.961801 <30>[ 20.810069] systemd[1]: Started Journal Service.
10920 09:30:29.968686 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10921 09:30:29.992802 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10922 09:30:30.007361 See 'systemctl status systemd-udev-trigger.service' for details.
10923 09:30:30.024697 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10924 09:30:30.044094 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10925 09:30:30.061193 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10926 09:30:30.076850 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10927 09:30:30.093336 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10928 09:30:30.148066 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10929 09:30:30.171164 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10930 09:30:30.189484 <46>[ 21.034556] systemd-journald[295]: Received client request to flush runtime journal.
10931 09:30:30.582948 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10932 09:30:30.600262 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10933 09:30:30.615555 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10934 09:30:30.667521 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10935 09:30:31.567186 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10936 09:30:31.616449 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10937 09:30:31.640316 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10938 09:30:31.692772 Starting [0;1;39mNetwork Service[0m...
10939 09:30:31.849886 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10940 09:30:32.090157 Starting [0;1;39mNetwork Time Synchronization[0m...
10941 09:30:32.111583 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10942 09:30:32.173226 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10943 09:30:32.376734 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10944 09:30:32.391808 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10945 09:30:32.410611 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10946 09:30:32.462908 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10947 09:30:32.480282 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10948 09:30:32.504272 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10949 09:30:32.560167 Starting [0;1;39mNetwork Name Resolution[0m...
10950 09:30:32.580246 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10951 09:30:32.595848 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10952 09:30:32.616528 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10953 09:30:32.634149 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10954 09:30:32.654150 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10955 09:30:32.666995 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10956 09:30:32.683175 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10957 09:30:33.334521 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10958 09:30:33.367851 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10959 09:30:33.688382 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10960 09:30:33.721569 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10961 09:30:33.735219 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10962 09:30:33.760581 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10963 09:30:33.775711 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10964 09:30:33.790938 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10965 09:30:33.851939 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10966 09:30:34.003106 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10967 09:30:34.139947 Starting [0;1;39mUser Login Management[0m...
10968 09:30:34.155626 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10969 09:30:34.481709 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10970 09:30:34.504841 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10971 09:30:34.520795 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10972 09:30:34.538731 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10973 09:30:34.583111 Starting [0;1;39mPermit User Sessions[0m...
10974 09:30:34.600314 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10975 09:30:34.611142 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10976 09:30:34.660261 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10977 09:30:34.681263 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10978 09:30:34.700748 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10979 09:30:34.716281 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10980 09:30:34.732284 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10981 09:30:34.771300 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10982 09:30:34.823683 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10983 09:30:34.906076
10984 09:30:34.906224
10985 09:30:34.909500 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10986 09:30:34.909580
10987 09:30:34.912839 debian-bullseye-arm64 login: root (automatic login)
10988 09:30:34.912918
10989 09:30:34.913008
10990 09:30:35.240847 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
10991 09:30:35.240986
10992 09:30:35.247567 The programs included with the Debian GNU/Linux system are free software;
10993 09:30:35.254024 the exact distribution terms for each program are described in the
10994 09:30:35.257449 individual files in /usr/share/doc/*/copyright.
10995 09:30:35.257567
10996 09:30:35.264490 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10997 09:30:35.267207 permitted by applicable law.
10998 09:30:36.182235 Matched prompt #10: / #
11000 09:30:36.182506 Setting prompt string to ['/ #']
11001 09:30:36.182597 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11003 09:30:36.182787 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11004 09:30:36.182876 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11005 09:30:36.182945 Setting prompt string to ['/ #']
11006 09:30:36.183004 Forcing a shell prompt, looking for ['/ #']
11008 09:30:36.233309 / #
11009 09:30:36.233683 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11010 09:30:36.233938 Waiting using forced prompt support (timeout 00:02:30)
11011 09:30:36.239083
11012 09:30:36.239801 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11013 09:30:36.240138 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11015 09:30:36.341020 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8'
11016 09:30:36.346667 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826808/extract-nfsrootfs-kqu7qhw8'
11018 09:30:36.448017 / # export NFS_SERVER_IP='192.168.201.1'
11019 09:30:36.453714 export NFS_SERVER_IP='192.168.201.1'
11020 09:30:36.454319 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11021 09:30:36.454669 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11022 09:30:36.455067 end: 2 depthcharge-action (duration 00:01:25) [common]
11023 09:30:36.455396 start: 3 lava-test-retry (timeout 00:07:50) [common]
11024 09:30:36.455732 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11025 09:30:36.455998 Using namespace: common
11027 09:30:36.557023 / # #
11028 09:30:36.557645 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11029 09:30:36.563138 #
11030 09:30:36.563902 Using /lava-11826808
11032 09:30:36.665365 / # export SHELL=/bin/bash
11033 09:30:36.671169 export SHELL=/bin/bash
11035 09:30:36.772528 / # . /lava-11826808/environment
11036 09:30:36.778280 . /lava-11826808/environment
11038 09:30:36.884931 / # /lava-11826808/bin/lava-test-runner /lava-11826808/0
11039 09:30:36.885497 Test shell timeout: 10s (minimum of the action and connection timeout)
11040 09:30:36.891088 /lava-11826808/bin/lava-test-runner /lava-11826808/0
11041 09:30:37.153569 + export TESTRUN_ID=0_timesync-off
11042 09:30:37.156875 + TESTRUN_ID=0_timesync-off
11043 09:30:37.160162 + cd /lava-11826808/0/tests/0_timesync-off
11044 09:30:37.163269 ++ cat uuid
11045 09:30:37.166401 + UUID=11826808_1.6.2.3.1
11046 09:30:37.166912 + set +x
11047 09:30:37.172864 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11826808_1.6.2.3.1>
11048 09:30:37.173567 Received signal: <STARTRUN> 0_timesync-off 11826808_1.6.2.3.1
11049 09:30:37.173941 Starting test lava.0_timesync-off (11826808_1.6.2.3.1)
11050 09:30:37.174491 Skipping test definition patterns.
11051 09:30:37.176110 + systemctl stop systemd-timesyncd
11052 09:30:37.217140 + set +x
11053 09:30:37.220351 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11826808_1.6.2.3.1>
11054 09:30:37.221251 Received signal: <ENDRUN> 0_timesync-off 11826808_1.6.2.3.1
11055 09:30:37.221828 Ending use of test pattern.
11056 09:30:37.222340 Ending test lava.0_timesync-off (11826808_1.6.2.3.1), duration 0.05
11058 09:30:37.285088 + export TESTRUN_ID=1_kselftest-tpm2
11059 09:30:37.288171 + TESTRUN_ID=1_kselftest-tpm2
11060 09:30:37.294483 + cd /lava-11826808/0/tests/1_kselftest-tpm2
11061 09:30:37.295060 ++ cat uuid
11062 09:30:37.297838 + UUID=11826808_1.6.2.3.5
11063 09:30:37.298296 + set +x
11064 09:30:37.301253 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 11826808_1.6.2.3.5>
11065 09:30:37.301935 Received signal: <STARTRUN> 1_kselftest-tpm2 11826808_1.6.2.3.5
11066 09:30:37.302318 Starting test lava.1_kselftest-tpm2 (11826808_1.6.2.3.5)
11067 09:30:37.302779 Skipping test definition patterns.
11068 09:30:37.304842 + cd ./automated/linux/kselftest/
11069 09:30:37.331542 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11070 09:30:37.363537 INFO: install_deps skipped
11071 09:30:37.478682 --2023-10-20 09:29:03-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11072 09:30:37.485161 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11073 09:30:37.618579 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11074 09:30:37.751335 HTTP request sent, awaiting response... 200 OK
11075 09:30:37.754702 Length: 2964156 (2.8M) [application/octet-stream]
11076 09:30:37.757570 Saving to: 'kselftest.tar.xz'
11077 09:30:37.757981
11078 09:30:37.758310
11079 09:30:38.016876 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11080 09:30:38.282316 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11081 09:30:38.730395 kselftest.tar.xz 7%[> ] 217.50K 411KB/s
11082 09:30:39.007057 kselftest.tar.xz 28%[====> ] 824.13K 843KB/s
11083 09:30:39.083511 kselftest.tar.xz 84%[===============> ] 2.39M 1.91MB/s
11084 09:30:39.089776 kselftest.tar.xz 100%[===================>] 2.83M 2.12MB/s in 1.3s
11085 09:30:39.090405
11086 09:30:39.348565 2023-10-20 09:29:05 (2.12 MB/s) - 'kselftest.tar.xz' saved [2964156/2964156]
11087 09:30:39.349164
11088 09:30:44.666238 skiplist:
11089 09:30:44.669294 ========================================
11090 09:30:44.673087 ========================================
11091 09:30:44.709804 tpm2:test_smoke.sh
11092 09:30:44.713128 tpm2:test_space.sh
11093 09:30:44.727227 ============== Tests to run ===============
11094 09:30:44.727362 tpm2:test_smoke.sh
11095 09:30:44.730510 tpm2:test_space.sh
11096 09:30:44.733696 ===========End Tests to run ===============
11097 09:30:44.733797 shardfile-tpm2 pass
11098 09:30:44.830552 <12>[ 35.679824] kselftest: Running tests in tpm2
11099 09:30:44.839828 TAP version 13
11100 09:30:44.851803 1..2
11101 09:30:44.881170 # selftests: tpm2: test_smoke.sh
11102 09:30:46.288388 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11103 09:30:46.291529 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11104 09:30:46.298273 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11105 09:30:46.301363 # Traceback (most recent call last):
11106 09:30:46.311354 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11107 09:30:46.311494 # if self.tpm:
11108 09:30:46.318621 # AttributeError: 'Client' object has no attribute 'tpm'
11109 09:30:46.321919 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11110 09:30:46.328490 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11111 09:30:46.331397 # Traceback (most recent call last):
11112 09:30:46.341320 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11113 09:30:46.345250 # if self.tpm:
11114 09:30:46.348541 # AttributeError: 'Client' object has no attribute 'tpm'
11115 09:30:46.354904 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11116 09:30:46.361753 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11117 09:30:46.361844 # Traceback (most recent call last):
11118 09:30:46.371971 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11119 09:30:46.375236 # if self.tpm:
11120 09:30:46.378342 # AttributeError: 'Client' object has no attribute 'tpm'
11121 09:30:46.384944 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11122 09:30:46.391513 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11123 09:30:46.395135 # Traceback (most recent call last):
11124 09:30:46.404962 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11125 09:30:46.405116 # if self.tpm:
11126 09:30:46.412176 # AttributeError: 'Client' object has no attribute 'tpm'
11127 09:30:46.415345 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11128 09:30:46.421851 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11129 09:30:46.425074 # Traceback (most recent call last):
11130 09:30:46.435429 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11131 09:30:46.438814 # if self.tpm:
11132 09:30:46.441792 # AttributeError: 'Client' object has no attribute 'tpm'
11133 09:30:46.445547 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11134 09:30:46.452100 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11135 09:30:46.455291 # Traceback (most recent call last):
11136 09:30:46.465679 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11137 09:30:46.468724 # if self.tpm:
11138 09:30:46.472270 # AttributeError: 'Client' object has no attribute 'tpm'
11139 09:30:46.478533 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11140 09:30:46.485783 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11141 09:30:46.488847 # Traceback (most recent call last):
11142 09:30:46.498665 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11143 09:30:46.498798 # if self.tpm:
11144 09:30:46.505541 # AttributeError: 'Client' object has no attribute 'tpm'
11145 09:30:46.508692 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11146 09:30:46.515921 # Exception ignored in: <function Client.__del__ at 0xffff90af9d30>
11147 09:30:46.523925 # Traceback (most recent call last):
11148 09:30:46.531037 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11149 09:30:46.531206 # if self.tpm:
11150 09:30:46.534272 # AttributeError: 'Client' object has no attribute 'tpm'
11151 09:30:46.537534 #
11152 09:30:46.544024 # ======================================================================
11153 09:30:46.547467 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11154 09:30:46.554191 # ----------------------------------------------------------------------
11155 09:30:46.557256 # Traceback (most recent call last):
11156 09:30:46.567684 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11157 09:30:46.570932 # self.root_key = self.client.create_root_key()
11158 09:30:46.584657 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11159 09:30:46.587919 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11160 09:30:46.598164 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11161 09:30:46.601396 # raise ProtocolError(cc, rc)
11162 09:30:46.608190 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11163 09:30:46.608316 #
11164 09:30:46.614673 # ======================================================================
11165 09:30:46.617809 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11166 09:30:46.624360 # ----------------------------------------------------------------------
11167 09:30:46.627988 # Traceback (most recent call last):
11168 09:30:46.637717 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11169 09:30:46.641062 # self.client = tpm2.Client()
11170 09:30:46.651424 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11171 09:30:46.657731 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11172 09:30:46.660832 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11173 09:30:46.660965 #
11174 09:30:46.667804 # ======================================================================
11175 09:30:46.674588 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11176 09:30:46.681146 # ----------------------------------------------------------------------
11177 09:30:46.684304 # Traceback (most recent call last):
11178 09:30:46.694175 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11179 09:30:46.697406 # self.client = tpm2.Client()
11180 09:30:46.707735 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11181 09:30:46.711275 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11182 09:30:46.717669 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11183 09:30:46.717783 #
11184 09:30:46.724002 # ======================================================================
11185 09:30:46.727891 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11186 09:30:46.734169 # ----------------------------------------------------------------------
11187 09:30:46.737410 # Traceback (most recent call last):
11188 09:30:46.747696 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11189 09:30:46.750756 # self.client = tpm2.Client()
11190 09:30:46.761791 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11191 09:30:46.766254 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11192 09:30:46.769660 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11193 09:30:46.769760 #
11194 09:30:46.776773 # ======================================================================
11195 09:30:46.783844 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11196 09:30:46.788433 # ----------------------------------------------------------------------
11197 09:30:46.791843 # Traceback (most recent call last):
11198 09:30:46.802985 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11199 09:30:46.808679 # self.client = tpm2.Client()
11200 09:30:46.815011 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11201 09:30:46.819548 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11202 09:30:46.829206 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11203 09:30:46.829342 #
11204 09:30:46.832409 # ======================================================================
11205 09:30:46.836001 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11206 09:30:46.843049 # ----------------------------------------------------------------------
11207 09:30:46.846332 # Traceback (most recent call last):
11208 09:30:46.856104 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11209 09:30:46.859174 # self.client = tpm2.Client()
11210 09:30:46.869392 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11211 09:30:46.872509 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11212 09:30:46.879044 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11213 09:30:46.879132 #
11214 09:30:46.886026 # ======================================================================
11215 09:30:46.888922 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11216 09:30:46.895670 # ----------------------------------------------------------------------
11217 09:30:46.899295 # Traceback (most recent call last):
11218 09:30:46.909469 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11219 09:30:46.912443 # self.client = tpm2.Client()
11220 09:30:46.922365 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11221 09:30:46.929528 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11222 09:30:46.932639 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11223 09:30:46.932728 #
11224 09:30:46.938973 # ======================================================================
11225 09:30:46.946259 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11226 09:30:46.952897 # ----------------------------------------------------------------------
11227 09:30:46.956049 # Traceback (most recent call last):
11228 09:30:46.966429 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11229 09:30:46.969506 # self.client = tpm2.Client()
11230 09:30:46.979659 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11231 09:30:46.982871 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11232 09:30:46.989877 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11233 09:30:46.989979 #
11234 09:30:46.995960 # ======================================================================
11235 09:30:46.999552 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11236 09:30:47.005910 # ----------------------------------------------------------------------
11237 09:30:47.009386 # Traceback (most recent call last):
11238 09:30:47.019511 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11239 09:30:47.022965 # self.client = tpm2.Client()
11240 09:30:47.032538 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11241 09:30:47.039226 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11242 09:30:47.042982 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11243 09:30:47.043087 #
11244 09:30:47.049647 # ----------------------------------------------------------------------
11245 09:30:47.052951 # Ran 9 tests in 0.040s
11246 09:30:47.053057 #
11247 09:30:47.053122 # FAILED (errors=9)
11248 09:30:47.059440 # test_async (tpm2_tests.AsyncTest) ... ok
11249 09:30:47.062753 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11250 09:30:47.062856 #
11251 09:30:47.069349 # ----------------------------------------------------------------------
11252 09:30:47.072557 # Ran 2 tests in 0.025s
11253 09:30:47.072642 #
11254 09:30:47.072708 # OK
11255 09:30:47.076306 ok 1 selftests: tpm2: test_smoke.sh
11256 09:30:47.079459 # selftests: tpm2: test_space.sh
11257 09:30:47.082804 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11258 09:30:47.089210 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11259 09:30:47.092888 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11260 09:30:47.099747 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11261 09:30:47.099870 #
11262 09:30:47.106001 # ======================================================================
11263 09:30:47.109783 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11264 09:30:47.116184 # ----------------------------------------------------------------------
11265 09:30:47.119272 # Traceback (most recent call last):
11266 09:30:47.129556 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11267 09:30:47.132628 # root1 = space1.create_root_key()
11268 09:30:47.142958 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11269 09:30:47.149214 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11270 09:30:47.159450 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11271 09:30:47.162776 # raise ProtocolError(cc, rc)
11272 09:30:47.169666 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11273 09:30:47.169781 #
11274 09:30:47.176064 # ======================================================================
11275 09:30:47.179187 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11276 09:30:47.186428 # ----------------------------------------------------------------------
11277 09:30:47.189559 # Traceback (most recent call last):
11278 09:30:47.199844 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11279 09:30:47.202754 # space1.create_root_key()
11280 09:30:47.212989 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11281 09:30:47.219393 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11282 09:30:47.229205 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11283 09:30:47.232842 # raise ProtocolError(cc, rc)
11284 09:30:47.239455 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11285 09:30:47.239579 #
11286 09:30:47.245838 # ======================================================================
11287 09:30:47.249552 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11288 09:30:47.256265 # ----------------------------------------------------------------------
11289 09:30:47.259223 # Traceback (most recent call last):
11290 09:30:47.269433 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11291 09:30:47.272632 # root1 = space1.create_root_key()
11292 09:30:47.282884 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11293 09:30:47.289442 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11294 09:30:47.299229 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11295 09:30:47.303033 # raise ProtocolError(cc, rc)
11296 09:30:47.309139 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11297 09:30:47.309237 #
11298 09:30:47.316295 # ======================================================================
11299 09:30:47.319513 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11300 09:30:47.326128 # ----------------------------------------------------------------------
11301 09:30:47.329436 # Traceback (most recent call last):
11302 09:30:47.343019 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11303 09:30:47.345786 # root1 = space1.create_root_key()
11304 09:30:47.356107 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11305 09:30:47.359389 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11306 09:30:47.369891 # File "/lava-11826808/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11307 09:30:47.372884 # raise ProtocolError(cc, rc)
11308 09:30:47.379880 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11309 09:30:47.380097 #
11310 09:30:47.386335 # ----------------------------------------------------------------------
11311 09:30:47.389452 # Ran 4 tests in 0.081s
11312 09:30:47.389547 #
11313 09:30:47.389618 # FAILED (errors=4)
11314 09:30:47.396437 not ok 2 selftests: tpm2: test_space.sh # exit=1
11315 09:30:47.419099 tpm2_test_smoke_sh pass
11316 09:30:47.422742 tpm2_test_space_sh fail
11317 09:30:47.439214 + ../../utils/send-to-lava.sh ./output/result.txt
11318 09:30:47.491717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11319 09:30:47.492113 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11321 09:30:47.526106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11322 09:30:47.526425 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11324 09:30:47.562320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11325 09:30:47.562668 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11327 09:30:47.565532 + set +x
11328 09:30:47.568497 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 11826808_1.6.2.3.5>
11329 09:30:47.568763 Received signal: <ENDRUN> 1_kselftest-tpm2 11826808_1.6.2.3.5
11330 09:30:47.568850 Ending use of test pattern.
11331 09:30:47.568929 Ending test lava.1_kselftest-tpm2 (11826808_1.6.2.3.5), duration 10.27
11333 09:30:47.572307 <LAVA_TEST_RUNNER EXIT>
11334 09:30:47.572596 ok: lava_test_shell seems to have completed
11335 09:30:47.572762 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11336 09:30:47.572897 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11337 09:30:47.573025 end: 3 lava-test-retry (duration 00:00:11) [common]
11338 09:30:47.573128 start: 4 finalize (timeout 00:07:39) [common]
11339 09:30:47.573262 start: 4.1 power-off (timeout 00:00:30) [common]
11340 09:30:47.573557 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11341 09:30:47.652292 >> Command sent successfully.
11342 09:30:47.655268 Returned 0 in 0 seconds
11343 09:30:47.755730 end: 4.1 power-off (duration 00:00:00) [common]
11345 09:30:47.756114 start: 4.2 read-feedback (timeout 00:07:38) [common]
11346 09:30:47.756407 Listened to connection for namespace 'common' for up to 1s
11347 09:30:48.757334 Finalising connection for namespace 'common'
11348 09:30:48.757502 Disconnecting from shell: Finalise
11349 09:30:48.757609 / #
11350 09:30:48.857963 end: 4.2 read-feedback (duration 00:00:01) [common]
11351 09:30:48.858147 end: 4 finalize (duration 00:00:01) [common]
11352 09:30:48.858281 Cleaning after the job
11353 09:30:48.858401 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/ramdisk
11354 09:30:48.861315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/kernel
11355 09:30:48.873924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/dtb
11356 09:30:48.874162 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/nfsrootfs
11357 09:30:48.965090 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826808/tftp-deploy-sgpti5nv/modules
11358 09:30:48.972550 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826808
11359 09:30:49.630369 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826808
11360 09:30:49.630549 Job finished correctly