Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Kernel Errors: 32
- Errors: 1
- Boot result: PASS
1 09:31:44.251329 lava-dispatcher, installed at version: 2023.08
2 09:31:44.251550 start: 0 validate
3 09:31:44.251708 Start time: 2023-10-20 09:31:44.251699+00:00 (UTC)
4 09:31:44.251840 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:31:44.251986 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:31:44.519710 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:31:44.519881 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:31:44.785106 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:31:44.785345 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:31:45.050429 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:31:45.050657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:31:45.318987 validate duration: 1.07
14 09:31:45.319360 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:31:45.319497 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:31:45.319620 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:31:45.319771 Not decompressing ramdisk as can be used compressed.
18 09:31:45.319891 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 09:31:45.319994 saving as /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/ramdisk/rootfs.cpio.gz
20 09:31:45.320092 total size: 26246609 (25 MB)
21 09:31:45.321638 progress 0 % (0 MB)
22 09:31:45.329422 progress 5 % (1 MB)
23 09:31:45.337181 progress 10 % (2 MB)
24 09:31:45.344837 progress 15 % (3 MB)
25 09:31:45.352504 progress 20 % (5 MB)
26 09:31:45.360110 progress 25 % (6 MB)
27 09:31:45.367791 progress 30 % (7 MB)
28 09:31:45.375491 progress 35 % (8 MB)
29 09:31:45.383148 progress 40 % (10 MB)
30 09:31:45.390731 progress 45 % (11 MB)
31 09:31:45.398266 progress 50 % (12 MB)
32 09:31:45.405923 progress 55 % (13 MB)
33 09:31:45.413389 progress 60 % (15 MB)
34 09:31:45.420923 progress 65 % (16 MB)
35 09:31:45.428390 progress 70 % (17 MB)
36 09:31:45.435839 progress 75 % (18 MB)
37 09:31:45.443356 progress 80 % (20 MB)
38 09:31:45.450738 progress 85 % (21 MB)
39 09:31:45.458088 progress 90 % (22 MB)
40 09:31:45.465445 progress 95 % (23 MB)
41 09:31:45.472851 progress 100 % (25 MB)
42 09:31:45.473161 25 MB downloaded in 0.15 s (163.53 MB/s)
43 09:31:45.473383 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:31:45.473776 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:31:45.473900 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:31:45.474029 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:31:45.474209 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:31:45.474311 saving as /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/kernel/Image
50 09:31:45.474404 total size: 49236480 (46 MB)
51 09:31:45.474499 No compression specified
52 09:31:45.476123 progress 0 % (0 MB)
53 09:31:45.490269 progress 5 % (2 MB)
54 09:31:45.504537 progress 10 % (4 MB)
55 09:31:45.518899 progress 15 % (7 MB)
56 09:31:45.533190 progress 20 % (9 MB)
57 09:31:45.547308 progress 25 % (11 MB)
58 09:31:45.561659 progress 30 % (14 MB)
59 09:31:45.575804 progress 35 % (16 MB)
60 09:31:45.590284 progress 40 % (18 MB)
61 09:31:45.604329 progress 45 % (21 MB)
62 09:31:45.618408 progress 50 % (23 MB)
63 09:31:45.632395 progress 55 % (25 MB)
64 09:31:45.646555 progress 60 % (28 MB)
65 09:31:45.660822 progress 65 % (30 MB)
66 09:31:45.674960 progress 70 % (32 MB)
67 09:31:45.689111 progress 75 % (35 MB)
68 09:31:45.703705 progress 80 % (37 MB)
69 09:31:45.717619 progress 85 % (39 MB)
70 09:31:45.731605 progress 90 % (42 MB)
71 09:31:45.744870 progress 95 % (44 MB)
72 09:31:45.757912 progress 100 % (46 MB)
73 09:31:45.758130 46 MB downloaded in 0.28 s (165.50 MB/s)
74 09:31:45.758287 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:31:45.758535 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:31:45.758628 start: 1.3 download-retry (timeout 00:10:00) [common]
78 09:31:45.758724 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 09:31:45.758867 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:31:45.758944 saving as /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/dtb/mt8192-asurada-spherion-r0.dtb
81 09:31:45.759008 total size: 47278 (0 MB)
82 09:31:45.759078 No compression specified
83 09:31:45.760228 progress 69 % (0 MB)
84 09:31:45.760518 progress 100 % (0 MB)
85 09:31:45.760683 0 MB downloaded in 0.00 s (26.97 MB/s)
86 09:31:45.760812 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:31:45.761047 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:31:45.761138 start: 1.4 download-retry (timeout 00:10:00) [common]
90 09:31:45.761224 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 09:31:45.761343 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:31:45.761415 saving as /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/modules/modules.tar
93 09:31:45.761477 total size: 8614716 (8 MB)
94 09:31:45.761545 Using unxz to decompress xz
95 09:31:45.766081 progress 0 % (0 MB)
96 09:31:45.787470 progress 5 % (0 MB)
97 09:31:45.812010 progress 10 % (0 MB)
98 09:31:45.836712 progress 15 % (1 MB)
99 09:31:45.860608 progress 20 % (1 MB)
100 09:31:45.885044 progress 25 % (2 MB)
101 09:31:45.912053 progress 30 % (2 MB)
102 09:31:45.939790 progress 35 % (2 MB)
103 09:31:45.963867 progress 40 % (3 MB)
104 09:31:45.989257 progress 45 % (3 MB)
105 09:31:46.015083 progress 50 % (4 MB)
106 09:31:46.040124 progress 55 % (4 MB)
107 09:31:46.065221 progress 60 % (4 MB)
108 09:31:46.091165 progress 65 % (5 MB)
109 09:31:46.118679 progress 70 % (5 MB)
110 09:31:46.142499 progress 75 % (6 MB)
111 09:31:46.169801 progress 80 % (6 MB)
112 09:31:46.195847 progress 85 % (7 MB)
113 09:31:46.221639 progress 90 % (7 MB)
114 09:31:46.252185 progress 95 % (7 MB)
115 09:31:46.280472 progress 100 % (8 MB)
116 09:31:46.286801 8 MB downloaded in 0.53 s (15.64 MB/s)
117 09:31:46.287104 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:31:46.287523 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:31:46.287658 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:31:46.287780 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:31:46.287894 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:31:46.288018 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:31:46.288296 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh
125 09:31:46.288475 makedir: /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin
126 09:31:46.288617 makedir: /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/tests
127 09:31:46.288759 makedir: /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/results
128 09:31:46.288912 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-add-keys
129 09:31:46.289100 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-add-sources
130 09:31:46.289276 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-background-process-start
131 09:31:46.289449 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-background-process-stop
132 09:31:46.289618 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-common-functions
133 09:31:46.289787 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-echo-ipv4
134 09:31:46.289953 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-install-packages
135 09:31:46.290120 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-installed-packages
136 09:31:46.290289 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-os-build
137 09:31:46.290475 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-probe-channel
138 09:31:46.290662 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-probe-ip
139 09:31:46.290834 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-target-ip
140 09:31:46.291005 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-target-mac
141 09:31:46.291172 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-target-storage
142 09:31:46.291345 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-case
143 09:31:46.291515 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-event
144 09:31:46.291688 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-feedback
145 09:31:46.291857 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-raise
146 09:31:46.292027 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-reference
147 09:31:46.292193 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-runner
148 09:31:46.292360 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-set
149 09:31:46.292528 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-test-shell
150 09:31:46.292698 Updating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-install-packages (oe)
151 09:31:46.292898 Updating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/bin/lava-installed-packages (oe)
152 09:31:46.293062 Creating /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/environment
153 09:31:46.293209 LAVA metadata
154 09:31:46.293314 - LAVA_JOB_ID=11826815
155 09:31:46.293412 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:31:46.293560 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:31:46.293658 skipped lava-vland-overlay
158 09:31:46.293768 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:31:46.293889 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:31:46.293985 skipped lava-multinode-overlay
161 09:31:46.294092 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:31:46.294214 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:31:46.294323 Loading test definitions
164 09:31:46.294457 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:31:46.294564 Using /lava-11826815 at stage 0
166 09:31:46.294937 uuid=11826815_1.5.2.3.1 testdef=None
167 09:31:46.295060 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:31:46.295181 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:31:46.295876 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:31:46.296275 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:31:46.297208 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:31:46.297587 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:31:46.298492 runner path: /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11826815_1.5.2.3.1
176 09:31:46.298691 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:31:46.298939 Creating lava-test-runner.conf files
179 09:31:46.299037 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826815/lava-overlay-42i814eh/lava-11826815/0 for stage 0
180 09:31:46.299162 - 0_v4l2-compliance-mtk-vcodec-enc
181 09:31:46.299300 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:31:46.299420 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:31:46.308060 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:31:46.308207 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:31:46.308329 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:31:46.308451 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:31:46.308572 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:31:47.092614 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:31:47.093037 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:31:47.093189 extracting modules file /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826815/extract-overlay-ramdisk-f697s4rg/ramdisk
191 09:31:47.423844 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:31:47.424011 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 09:31:47.424123 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826815/compress-overlay-7vhb15di/overlay-1.5.2.4.tar.gz to ramdisk
194 09:31:47.424226 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826815/compress-overlay-7vhb15di/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826815/extract-overlay-ramdisk-f697s4rg/ramdisk
195 09:31:47.434026 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:31:47.434176 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 09:31:47.434300 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:31:47.434426 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 09:31:47.434544 Building ramdisk /var/lib/lava/dispatcher/tmp/11826815/extract-overlay-ramdisk-f697s4rg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826815/extract-overlay-ramdisk-f697s4rg/ramdisk
200 09:31:48.031677 >> 228397 blocks
201 09:31:52.075609 rename /var/lib/lava/dispatcher/tmp/11826815/extract-overlay-ramdisk-f697s4rg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/ramdisk/ramdisk.cpio.gz
202 09:31:52.076073 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:31:52.076201 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 09:31:52.076312 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 09:31:52.076475 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/kernel/Image'
206 09:32:04.815106 Returned 0 in 12 seconds
207 09:32:04.915762 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/kernel/image.itb
208 09:32:05.519876 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:32:05.520249 output: Created: Fri Oct 20 10:32:05 2023
210 09:32:05.520326 output: Image 0 (kernel-1)
211 09:32:05.520402 output: Description:
212 09:32:05.520468 output: Created: Fri Oct 20 10:32:05 2023
213 09:32:05.520532 output: Type: Kernel Image
214 09:32:05.520596 output: Compression: lzma compressed
215 09:32:05.520659 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
216 09:32:05.520721 output: Architecture: AArch64
217 09:32:05.520782 output: OS: Linux
218 09:32:05.520840 output: Load Address: 0x00000000
219 09:32:05.520900 output: Entry Point: 0x00000000
220 09:32:05.520959 output: Hash algo: crc32
221 09:32:05.521015 output: Hash value: 05d3904e
222 09:32:05.521070 output: Image 1 (fdt-1)
223 09:32:05.521125 output: Description: mt8192-asurada-spherion-r0
224 09:32:05.521179 output: Created: Fri Oct 20 10:32:05 2023
225 09:32:05.521234 output: Type: Flat Device Tree
226 09:32:05.521287 output: Compression: uncompressed
227 09:32:05.521341 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:32:05.521394 output: Architecture: AArch64
229 09:32:05.521447 output: Hash algo: crc32
230 09:32:05.521500 output: Hash value: cc4352de
231 09:32:05.521553 output: Image 2 (ramdisk-1)
232 09:32:05.521606 output: Description: unavailable
233 09:32:05.521660 output: Created: Fri Oct 20 10:32:05 2023
234 09:32:05.521714 output: Type: RAMDisk Image
235 09:32:05.521768 output: Compression: Unknown Compression
236 09:32:05.521821 output: Data Size: 39349745 Bytes = 38427.49 KiB = 37.53 MiB
237 09:32:05.521874 output: Architecture: AArch64
238 09:32:05.521927 output: OS: Linux
239 09:32:05.521980 output: Load Address: unavailable
240 09:32:05.522033 output: Entry Point: unavailable
241 09:32:05.522085 output: Hash algo: crc32
242 09:32:05.522138 output: Hash value: 4954d9de
243 09:32:05.522191 output: Default Configuration: 'conf-1'
244 09:32:05.522244 output: Configuration 0 (conf-1)
245 09:32:05.522297 output: Description: mt8192-asurada-spherion-r0
246 09:32:05.522350 output: Kernel: kernel-1
247 09:32:05.522404 output: Init Ramdisk: ramdisk-1
248 09:32:05.522457 output: FDT: fdt-1
249 09:32:05.522509 output: Loadables: kernel-1
250 09:32:05.522563 output:
251 09:32:05.522763 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 09:32:05.522862 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 09:32:05.522966 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 09:32:05.523066 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 09:32:05.523145 No LXC device requested
256 09:32:05.523227 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:32:05.523311 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 09:32:05.523388 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:32:05.523459 Checking files for TFTP limit of 4294967296 bytes.
260 09:32:05.523976 end: 1 tftp-deploy (duration 00:00:20) [common]
261 09:32:05.524081 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:32:05.524173 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:32:05.524302 substitutions:
264 09:32:05.524370 - {DTB}: 11826815/tftp-deploy-k85cv_7w/dtb/mt8192-asurada-spherion-r0.dtb
265 09:32:05.524436 - {INITRD}: 11826815/tftp-deploy-k85cv_7w/ramdisk/ramdisk.cpio.gz
266 09:32:05.524496 - {KERNEL}: 11826815/tftp-deploy-k85cv_7w/kernel/Image
267 09:32:05.524555 - {LAVA_MAC}: None
268 09:32:05.524612 - {PRESEED_CONFIG}: None
269 09:32:05.524669 - {PRESEED_LOCAL}: None
270 09:32:05.524725 - {RAMDISK}: 11826815/tftp-deploy-k85cv_7w/ramdisk/ramdisk.cpio.gz
271 09:32:05.524782 - {ROOT_PART}: None
272 09:32:05.524836 - {ROOT}: None
273 09:32:05.524891 - {SERVER_IP}: 192.168.201.1
274 09:32:05.524946 - {TEE}: None
275 09:32:05.525000 Parsed boot commands:
276 09:32:05.525054 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:32:05.525237 Parsed boot commands: tftpboot 192.168.201.1 11826815/tftp-deploy-k85cv_7w/kernel/image.itb 11826815/tftp-deploy-k85cv_7w/kernel/cmdline
278 09:32:05.525328 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:32:05.525416 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:32:05.525515 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:32:05.525603 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:32:05.525675 Not connected, no need to disconnect.
283 09:32:05.525750 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:32:05.525830 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:32:05.525899 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 09:32:05.529884 Setting prompt string to ['lava-test: # ']
287 09:32:05.530318 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:32:05.530477 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:32:05.530620 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:32:05.530746 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:32:05.531085 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 09:32:10.671455 >> Command sent successfully.
293 09:32:10.673862 Returned 0 in 5 seconds
294 09:32:10.774254 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:32:10.774696 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:32:10.774831 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:32:10.774931 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:32:10.774998 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:32:10.775070 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:32:10.775405 [Enter `^Ec?' for help]
302 09:32:10.948628
303 09:32:10.948798
304 09:32:10.948873 F0: 102B 0000
305 09:32:10.948941
306 09:32:10.949004 F3: 1001 0000 [0200]
307 09:32:10.949064
308 09:32:10.952102 F3: 1001 0000
309 09:32:10.952221
310 09:32:10.952320 F7: 102D 0000
311 09:32:10.952421
312 09:32:10.952519 F1: 0000 0000
313 09:32:10.952611
314 09:32:10.956013 V0: 0000 0000 [0001]
315 09:32:10.956129
316 09:32:10.956223 00: 0007 8000
317 09:32:10.956295
318 09:32:10.959479 01: 0000 0000
319 09:32:10.959600
320 09:32:10.959713 BP: 0C00 0209 [0000]
321 09:32:10.959783
322 09:32:10.959846 G0: 1182 0000
323 09:32:10.963477
324 09:32:10.963591 EC: 0000 0021 [4000]
325 09:32:10.963689
326 09:32:10.967297 S7: 0000 0000 [0000]
327 09:32:10.967414
328 09:32:10.967515 CC: 0000 0000 [0001]
329 09:32:10.967615
330 09:32:10.970578 T0: 0000 0040 [010F]
331 09:32:10.970695
332 09:32:10.970794 Jump to BL
333 09:32:10.970894
334 09:32:10.994995
335 09:32:10.995152
336 09:32:10.995252
337 09:32:11.003226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:32:11.007319 ARM64: Exception handlers installed.
339 09:32:11.010116 ARM64: Testing exception
340 09:32:11.010235 ARM64: Done test exception
341 09:32:11.017979 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:32:11.028697 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:32:11.035945 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:32:11.046090 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:32:11.052600 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:32:11.062470 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:32:11.073795 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:32:11.080237 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:32:11.098189 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:32:11.101581 WDT: Last reset was cold boot
351 09:32:11.104384 SPI1(PAD0) initialized at 2873684 Hz
352 09:32:11.107899 SPI5(PAD0) initialized at 992727 Hz
353 09:32:11.111400 VBOOT: Loading verstage.
354 09:32:11.117637 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:32:11.122386 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:32:11.125679 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:32:11.129014 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:32:11.135276 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:32:11.142275 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:32:11.152893 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 09:32:11.153024
362 09:32:11.153124
363 09:32:11.163482 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:32:11.167029 ARM64: Exception handlers installed.
365 09:32:11.167152 ARM64: Testing exception
366 09:32:11.170232 ARM64: Done test exception
367 09:32:11.173600 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:32:11.180581 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:32:11.193782 Probing TPM: . done!
370 09:32:11.193894 TPM ready after 0 ms
371 09:32:11.201626 Connected to device vid:did:rid of 1ae0:0028:00
372 09:32:11.208535 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 09:32:11.268270 Initialized TPM device CR50 revision 0
374 09:32:11.279873 tlcl_send_startup: Startup return code is 0
375 09:32:11.280006 TPM: setup succeeded
376 09:32:11.291479 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:32:11.300373 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:32:11.312664 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:32:11.322300 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:32:11.326354 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:32:11.329795 in-header: 03 07 00 00 08 00 00 00
382 09:32:11.333884 in-data: aa e4 47 04 13 02 00 00
383 09:32:11.334009 Chrome EC: UHEPI supported
384 09:32:11.341145 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:32:11.345759 in-header: 03 95 00 00 08 00 00 00
386 09:32:11.349104 in-data: 18 20 20 08 00 00 00 00
387 09:32:11.349225 Phase 1
388 09:32:11.352689 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:32:11.360336 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:32:11.367692 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:32:11.367831 Recovery requested (1009000e)
392 09:32:11.380021 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:32:11.384168 tlcl_extend: response is 0
394 09:32:11.393687 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:32:11.398133 tlcl_extend: response is 0
396 09:32:11.405588 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:32:11.424948 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 09:32:11.431744 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 09:32:11.431843
400 09:32:11.431913
401 09:32:11.441845 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:32:11.445075 ARM64: Exception handlers installed.
403 09:32:11.448253 ARM64: Testing exception
404 09:32:11.448335 ARM64: Done test exception
405 09:32:11.470675 pmic_efuse_setting: Set efuses in 11 msecs
406 09:32:11.473832 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:32:11.480451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:32:11.484692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:32:11.487999 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:32:11.495226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:32:11.499271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:32:11.503189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:32:11.510236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:32:11.513812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:32:11.517670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:32:11.524697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:32:11.528667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:32:11.532684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:32:11.535986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:32:11.543575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:32:11.547037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:32:11.554987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:32:11.558664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:32:11.565873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:32:11.569772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:32:11.577277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:32:11.581495 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:32:11.588824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:32:11.592168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:32:11.599795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:32:11.603085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:32:11.610369 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:32:11.614398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:32:11.621999 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:32:11.625237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:32:11.628975 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:32:11.636247 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:32:11.640176 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:32:11.644139 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:32:11.651018 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:32:11.655013 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:32:11.658635 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:32:11.666271 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:32:11.670194 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:32:11.673879 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:32:11.677387 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:32:11.684673 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:32:11.688172 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:32:11.691925 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:32:11.695888 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:32:11.699809 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:32:11.703051 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:32:11.710905 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:32:11.714857 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:32:11.718272 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:32:11.722299 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:32:11.725364 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:32:11.733577 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:32:11.740574 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:32:11.747999 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:32:11.755918 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:32:11.762685 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:32:11.766206 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:32:11.773558 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:32:11.777486 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:32:11.784963 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 09:32:11.788133 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:32:11.795716 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 09:32:11.799606 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:32:11.807924 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 09:32:11.817677 [RTC]rtc_get_frequency_meter,154: input=23, output=943
472 09:32:11.827055 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 09:32:11.836319 [RTC]rtc_get_frequency_meter,154: input=17, output=806
474 09:32:11.846351 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 09:32:11.855385 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 09:32:11.866564 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 09:32:11.870107 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 09:32:11.873690 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 09:32:11.877633 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 09:32:11.885319 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 09:32:11.888566 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 09:32:11.892267 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 09:32:11.892379 ADC[4]: Raw value=905465 ID=7
484 09:32:11.896051 ADC[3]: Raw value=213810 ID=1
485 09:32:11.899799 RAM Code: 0x71
486 09:32:11.902915 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 09:32:11.906730 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 09:32:11.917877 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 09:32:11.921628 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 09:32:11.925111 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 09:32:11.928612 in-header: 03 07 00 00 08 00 00 00
492 09:32:11.932500 in-data: aa e4 47 04 13 02 00 00
493 09:32:11.936474 Chrome EC: UHEPI supported
494 09:32:11.943737 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 09:32:11.947740 in-header: 03 95 00 00 08 00 00 00
496 09:32:11.950957 in-data: 18 20 20 08 00 00 00 00
497 09:32:11.955035 MRC: failed to locate region type 0.
498 09:32:11.958530 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 09:32:11.962627 DRAM-K: Running full calibration
500 09:32:11.970156 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 09:32:11.970273 header.status = 0x0
502 09:32:11.973936 header.version = 0x6 (expected: 0x6)
503 09:32:11.977981 header.size = 0xd00 (expected: 0xd00)
504 09:32:11.978090 header.flags = 0x0
505 09:32:11.985331 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 09:32:12.003127 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
507 09:32:12.010709 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 09:32:12.014603 dram_init: ddr_geometry: 2
509 09:32:12.014717 [EMI] MDL number = 2
510 09:32:12.018008 [EMI] Get MDL freq = 0
511 09:32:12.018116 dram_init: ddr_type: 0
512 09:32:12.021385 is_discrete_lpddr4: 1
513 09:32:12.025164 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 09:32:12.025271
515 09:32:12.025368
516 09:32:12.029049 [Bian_co] ETT version 0.0.0.1
517 09:32:12.033039 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 09:32:12.033148
519 09:32:12.036360 dramc_set_vcore_voltage set vcore to 650000
520 09:32:12.036464 Read voltage for 800, 4
521 09:32:12.039750 Vio18 = 0
522 09:32:12.039839 Vcore = 650000
523 09:32:12.039908 Vdram = 0
524 09:32:12.043181 Vddq = 0
525 09:32:12.043257 Vmddr = 0
526 09:32:12.046613 dram_init: config_dvfs: 1
527 09:32:12.050701 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 09:32:12.054056 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 09:32:12.058108 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 09:32:12.062086 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 09:32:12.068795 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 09:32:12.071961 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 09:32:12.072047 MEM_TYPE=3, freq_sel=18
534 09:32:12.075283 sv_algorithm_assistance_LP4_1600
535 09:32:12.081611 ============ PULL DRAM RESETB DOWN ============
536 09:32:12.084969 ========== PULL DRAM RESETB DOWN end =========
537 09:32:12.089668 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 09:32:12.092988 ===================================
539 09:32:12.097135 LPDDR4 DRAM CONFIGURATION
540 09:32:12.097221 ===================================
541 09:32:12.100862 EX_ROW_EN[0] = 0x0
542 09:32:12.100948 EX_ROW_EN[1] = 0x0
543 09:32:12.104096 LP4Y_EN = 0x0
544 09:32:12.104215 WORK_FSP = 0x0
545 09:32:12.107426 WL = 0x2
546 09:32:12.107531 RL = 0x2
547 09:32:12.110814 BL = 0x2
548 09:32:12.110916 RPST = 0x0
549 09:32:12.114571 RD_PRE = 0x0
550 09:32:12.114681 WR_PRE = 0x1
551 09:32:12.117838 WR_PST = 0x0
552 09:32:12.117920 DBI_WR = 0x0
553 09:32:12.120844 DBI_RD = 0x0
554 09:32:12.120918 OTF = 0x1
555 09:32:12.124912 ===================================
556 09:32:12.128223 ===================================
557 09:32:12.132251 ANA top config
558 09:32:12.132332 ===================================
559 09:32:12.135470 DLL_ASYNC_EN = 0
560 09:32:12.139179 ALL_SLAVE_EN = 1
561 09:32:12.142369 NEW_RANK_MODE = 1
562 09:32:12.145571 DLL_IDLE_MODE = 1
563 09:32:12.145676 LP45_APHY_COMB_EN = 1
564 09:32:12.148897 TX_ODT_DIS = 1
565 09:32:12.153063 NEW_8X_MODE = 1
566 09:32:12.157062 ===================================
567 09:32:12.159768 ===================================
568 09:32:12.159848 data_rate = 1600
569 09:32:12.163657 CKR = 1
570 09:32:12.166899 DQ_P2S_RATIO = 8
571 09:32:12.170386 ===================================
572 09:32:12.173678 CA_P2S_RATIO = 8
573 09:32:12.176906 DQ_CA_OPEN = 0
574 09:32:12.180136 DQ_SEMI_OPEN = 0
575 09:32:12.180217 CA_SEMI_OPEN = 0
576 09:32:12.183462 CA_FULL_RATE = 0
577 09:32:12.186605 DQ_CKDIV4_EN = 1
578 09:32:12.190279 CA_CKDIV4_EN = 1
579 09:32:12.193492 CA_PREDIV_EN = 0
580 09:32:12.193596 PH8_DLY = 0
581 09:32:12.196846 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 09:32:12.200220 DQ_AAMCK_DIV = 4
583 09:32:12.203481 CA_AAMCK_DIV = 4
584 09:32:12.206635 CA_ADMCK_DIV = 4
585 09:32:12.210571 DQ_TRACK_CA_EN = 0
586 09:32:12.210680 CA_PICK = 800
587 09:32:12.213819 CA_MCKIO = 800
588 09:32:12.217032 MCKIO_SEMI = 0
589 09:32:12.220961 PLL_FREQ = 3068
590 09:32:12.224787 DQ_UI_PI_RATIO = 32
591 09:32:12.224894 CA_UI_PI_RATIO = 0
592 09:32:12.228577 ===================================
593 09:32:12.231642 ===================================
594 09:32:12.235664 memory_type:LPDDR4
595 09:32:12.235746 GP_NUM : 10
596 09:32:12.239632 SRAM_EN : 1
597 09:32:12.242844 MD32_EN : 0
598 09:32:12.242959 ===================================
599 09:32:12.247222 [ANA_INIT] >>>>>>>>>>>>>>
600 09:32:12.250906 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 09:32:12.254296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 09:32:12.257742 ===================================
603 09:32:12.257848 data_rate = 1600,PCW = 0X7600
604 09:32:12.261037 ===================================
605 09:32:12.267254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 09:32:12.270591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:32:12.277814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 09:32:12.280980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 09:32:12.284320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:32:12.287744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 09:32:12.291164 [ANA_INIT] flow start
612 09:32:12.294421 [ANA_INIT] PLL >>>>>>>>
613 09:32:12.294505 [ANA_INIT] PLL <<<<<<<<
614 09:32:12.297589 [ANA_INIT] MIDPI >>>>>>>>
615 09:32:12.300746 [ANA_INIT] MIDPI <<<<<<<<
616 09:32:12.300861 [ANA_INIT] DLL >>>>>>>>
617 09:32:12.304747 [ANA_INIT] flow end
618 09:32:12.308103 ============ LP4 DIFF to SE enter ============
619 09:32:12.311285 ============ LP4 DIFF to SE exit ============
620 09:32:12.314615 [ANA_INIT] <<<<<<<<<<<<<
621 09:32:12.317992 [Flow] Enable top DCM control >>>>>
622 09:32:12.321407 [Flow] Enable top DCM control <<<<<
623 09:32:12.324877 Enable DLL master slave shuffle
624 09:32:12.331293 ==============================================================
625 09:32:12.331379 Gating Mode config
626 09:32:12.338171 ==============================================================
627 09:32:12.338286 Config description:
628 09:32:12.347647 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 09:32:12.354529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 09:32:12.361233 SELPH_MODE 0: By rank 1: By Phase
631 09:32:12.364477 ==============================================================
632 09:32:12.368172 GAT_TRACK_EN = 1
633 09:32:12.371495 RX_GATING_MODE = 2
634 09:32:12.374816 RX_GATING_TRACK_MODE = 2
635 09:32:12.377941 SELPH_MODE = 1
636 09:32:12.381113 PICG_EARLY_EN = 1
637 09:32:12.384490 VALID_LAT_VALUE = 1
638 09:32:12.387837 ==============================================================
639 09:32:12.391805 Enter into Gating configuration >>>>
640 09:32:12.394568 Exit from Gating configuration <<<<
641 09:32:12.398086 Enter into DVFS_PRE_config >>>>>
642 09:32:12.408256 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 09:32:12.411359 Exit from DVFS_PRE_config <<<<<
644 09:32:12.414991 Enter into PICG configuration >>>>
645 09:32:12.418248 Exit from PICG configuration <<<<
646 09:32:12.421711 [RX_INPUT] configuration >>>>>
647 09:32:12.425138 [RX_INPUT] configuration <<<<<
648 09:32:12.431876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 09:32:12.435075 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 09:32:12.441755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 09:32:12.448435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 09:32:12.455269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 09:32:12.461442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 09:32:12.465280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 09:32:12.468568 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 09:32:12.471719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 09:32:12.474976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 09:32:12.481808 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 09:32:12.484860 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 09:32:12.488400 ===================================
661 09:32:12.491650 LPDDR4 DRAM CONFIGURATION
662 09:32:12.494896 ===================================
663 09:32:12.494994 EX_ROW_EN[0] = 0x0
664 09:32:12.498303 EX_ROW_EN[1] = 0x0
665 09:32:12.498407 LP4Y_EN = 0x0
666 09:32:12.501769 WORK_FSP = 0x0
667 09:32:12.501871 WL = 0x2
668 09:32:12.505161 RL = 0x2
669 09:32:12.505262 BL = 0x2
670 09:32:12.508430 RPST = 0x0
671 09:32:12.508513 RD_PRE = 0x0
672 09:32:12.511508 WR_PRE = 0x1
673 09:32:12.511607 WR_PST = 0x0
674 09:32:12.515388 DBI_WR = 0x0
675 09:32:12.518509 DBI_RD = 0x0
676 09:32:12.518618 OTF = 0x1
677 09:32:12.521640 ===================================
678 09:32:12.525410 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 09:32:12.528799 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 09:32:12.534864 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 09:32:12.538411 ===================================
682 09:32:12.538519 LPDDR4 DRAM CONFIGURATION
683 09:32:12.541669 ===================================
684 09:32:12.544909 EX_ROW_EN[0] = 0x10
685 09:32:12.548325 EX_ROW_EN[1] = 0x0
686 09:32:12.548428 LP4Y_EN = 0x0
687 09:32:12.552166 WORK_FSP = 0x0
688 09:32:12.552268 WL = 0x2
689 09:32:12.555169 RL = 0x2
690 09:32:12.555270 BL = 0x2
691 09:32:12.558784 RPST = 0x0
692 09:32:12.558859 RD_PRE = 0x0
693 09:32:12.561964 WR_PRE = 0x1
694 09:32:12.562068 WR_PST = 0x0
695 09:32:12.565003 DBI_WR = 0x0
696 09:32:12.565106 DBI_RD = 0x0
697 09:32:12.568364 OTF = 0x1
698 09:32:12.572399 ===================================
699 09:32:12.578861 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 09:32:12.582105 nWR fixed to 40
701 09:32:12.582219 [ModeRegInit_LP4] CH0 RK0
702 09:32:12.585366 [ModeRegInit_LP4] CH0 RK1
703 09:32:12.588659 [ModeRegInit_LP4] CH1 RK0
704 09:32:12.592024 [ModeRegInit_LP4] CH1 RK1
705 09:32:12.592117 match AC timing 13
706 09:32:12.595584 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 09:32:12.602186 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 09:32:12.605382 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 09:32:12.608816 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 09:32:12.615382 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 09:32:12.615467 [EMI DOE] emi_dcm 0
712 09:32:12.621923 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 09:32:12.622008 ==
714 09:32:12.625264 Dram Type= 6, Freq= 0, CH_0, rank 0
715 09:32:12.629099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 09:32:12.629187 ==
717 09:32:12.632039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 09:32:12.638804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 09:32:12.648746 [CA 0] Center 36 (6~67) winsize 62
720 09:32:12.652076 [CA 1] Center 36 (6~67) winsize 62
721 09:32:12.655369 [CA 2] Center 34 (4~65) winsize 62
722 09:32:12.658788 [CA 3] Center 33 (3~64) winsize 62
723 09:32:12.662016 [CA 4] Center 33 (3~63) winsize 61
724 09:32:12.665787 [CA 5] Center 32 (2~62) winsize 61
725 09:32:12.665885
726 09:32:12.668933 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 09:32:12.669033
728 09:32:12.672069 [CATrainingPosCal] consider 1 rank data
729 09:32:12.675367 u2DelayCellTimex100 = 270/100 ps
730 09:32:12.678793 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 09:32:12.682139 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 09:32:12.689049 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 09:32:12.692477 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 09:32:12.695633 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 09:32:12.699114 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 09:32:12.699225
737 09:32:12.702482 CA PerBit enable=1, Macro0, CA PI delay=32
738 09:32:12.702590
739 09:32:12.705830 [CBTSetCACLKResult] CA Dly = 32
740 09:32:12.705936 CS Dly: 5 (0~36)
741 09:32:12.706030 ==
742 09:32:12.708849 Dram Type= 6, Freq= 0, CH_0, rank 1
743 09:32:12.715593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 09:32:12.715692 ==
745 09:32:12.719198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 09:32:12.725585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 09:32:12.734991 [CA 0] Center 36 (6~67) winsize 62
748 09:32:12.738122 [CA 1] Center 36 (6~67) winsize 62
749 09:32:12.741782 [CA 2] Center 34 (3~65) winsize 63
750 09:32:12.745147 [CA 3] Center 34 (3~65) winsize 63
751 09:32:12.748524 [CA 4] Center 33 (3~63) winsize 61
752 09:32:12.751401 [CA 5] Center 32 (2~63) winsize 62
753 09:32:12.751486
754 09:32:12.754669 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 09:32:12.754755
756 09:32:12.758008 [CATrainingPosCal] consider 2 rank data
757 09:32:12.761981 u2DelayCellTimex100 = 270/100 ps
758 09:32:12.765242 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 09:32:12.768651 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 09:32:12.775115 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 09:32:12.778332 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 09:32:12.781451 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 09:32:12.784846 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 09:32:12.784935
765 09:32:12.788258 CA PerBit enable=1, Macro0, CA PI delay=32
766 09:32:12.788344
767 09:32:12.791512 [CBTSetCACLKResult] CA Dly = 32
768 09:32:12.791629 CS Dly: 5 (0~36)
769 09:32:12.791710
770 09:32:12.795336 ----->DramcWriteLeveling(PI) begin...
771 09:32:12.798822 ==
772 09:32:12.798925 Dram Type= 6, Freq= 0, CH_0, rank 0
773 09:32:12.802919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 09:32:12.806395 ==
775 09:32:12.806514 Write leveling (Byte 0): 31 => 31
776 09:32:12.809958 Write leveling (Byte 1): 29 => 29
777 09:32:12.813444 DramcWriteLeveling(PI) end<-----
778 09:32:12.813534
779 09:32:12.813617 ==
780 09:32:12.817279 Dram Type= 6, Freq= 0, CH_0, rank 0
781 09:32:12.820347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 09:32:12.820462 ==
783 09:32:12.824282 [Gating] SW mode calibration
784 09:32:12.830925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 09:32:12.837680 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 09:32:12.841508 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 09:32:12.844700 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 09:32:12.850902 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 09:32:12.854390 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:32:12.857816 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:32:12.860958 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:32:12.867781 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:32:12.871060 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:32:12.874864 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:32:12.881340 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:32:12.884605 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:32:12.887822 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:32:12.895062 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:32:12.898289 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:32:12.901331 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:32:12.908179 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:32:12.911578 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:32:12.915012 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 09:32:12.921215 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 09:32:12.925141 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:32:12.928027 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:32:12.931314 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:32:12.937896 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:32:12.941601 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:32:12.944558 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:32:12.951738 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:32:12.955127 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
813 09:32:12.958023 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
814 09:32:12.965025 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:32:12.968444 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:32:12.971941 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:32:12.978561 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:32:12.981815 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 09:32:12.985355 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
820 09:32:12.991901 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
821 09:32:12.995303 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
822 09:32:12.998709 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:32:13.005107 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:32:13.008277 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:32:13.011531 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:32:13.014927 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:32:13.021792 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 09:32:13.025192 0 11 8 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
829 09:32:13.028389 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
830 09:32:13.035165 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:32:13.038410 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:32:13.041753 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:32:13.048371 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:32:13.051688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:32:13.055681 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 09:32:13.062283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 09:32:13.065439 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 09:32:13.068460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:32:13.071923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:32:13.078778 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:32:13.081970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:32:13.085463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:32:13.092207 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:32:13.095489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:32:13.098697 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:32:13.105089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:32:13.109054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:32:13.112082 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:32:13.118529 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:32:13.121883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:32:13.125259 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 09:32:13.131850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 09:32:13.131961 Total UI for P1: 0, mck2ui 16
854 09:32:13.138415 best dqsien dly found for B0: ( 0, 14, 4)
855 09:32:13.141926 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 09:32:13.145224 Total UI for P1: 0, mck2ui 16
857 09:32:13.148551 best dqsien dly found for B1: ( 0, 14, 8)
858 09:32:13.152585 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 09:32:13.156095 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 09:32:13.156214
861 09:32:13.159286 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 09:32:13.162511 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 09:32:13.165984 [Gating] SW calibration Done
864 09:32:13.166094 ==
865 09:32:13.169340 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:32:13.172667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:32:13.172773 ==
868 09:32:13.176019 RX Vref Scan: 0
869 09:32:13.176100
870 09:32:13.176166 RX Vref 0 -> 0, step: 1
871 09:32:13.176227
872 09:32:13.179282 RX Delay -130 -> 252, step: 16
873 09:32:13.182425 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 09:32:13.189277 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 09:32:13.192989 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 09:32:13.195958 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 09:32:13.199332 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 09:32:13.203061 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 09:32:13.209840 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 09:32:13.212676 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 09:32:13.216009 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 09:32:13.219365 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 09:32:13.223119 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
884 09:32:13.226073 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 09:32:13.233088 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 09:32:13.236338 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 09:32:13.239524 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 09:32:13.242876 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 09:32:13.242962 ==
890 09:32:13.246265 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:32:13.252965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:32:13.253053 ==
893 09:32:13.253122 DQS Delay:
894 09:32:13.256302 DQS0 = 0, DQS1 = 0
895 09:32:13.256386 DQM Delay:
896 09:32:13.256480 DQM0 = 89, DQM1 = 86
897 09:32:13.259719 DQ Delay:
898 09:32:13.262991 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 09:32:13.266229 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 09:32:13.269565 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 09:32:13.272993 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 09:32:13.273104
903 09:32:13.273201
904 09:32:13.273293 ==
905 09:32:13.276435 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:32:13.279897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:32:13.280017 ==
908 09:32:13.280120
909 09:32:13.280214
910 09:32:13.283153 TX Vref Scan disable
911 09:32:13.283272 == TX Byte 0 ==
912 09:32:13.289948 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 09:32:13.293164 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 09:32:13.293275 == TX Byte 1 ==
915 09:32:13.299884 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 09:32:13.303135 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 09:32:13.303248 ==
918 09:32:13.306399 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:32:13.309749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:32:13.309861 ==
921 09:32:13.323986 TX Vref=22, minBit 4, minWin=27, winSum=446
922 09:32:13.327205 TX Vref=24, minBit 7, minWin=27, winSum=451
923 09:32:13.330414 TX Vref=26, minBit 8, minWin=27, winSum=453
924 09:32:13.333829 TX Vref=28, minBit 3, minWin=28, winSum=456
925 09:32:13.337252 TX Vref=30, minBit 2, minWin=28, winSum=459
926 09:32:13.340599 TX Vref=32, minBit 10, minWin=27, winSum=454
927 09:32:13.347371 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
928 09:32:13.347498
929 09:32:13.350704 Final TX Range 1 Vref 30
930 09:32:13.350793
931 09:32:13.350861 ==
932 09:32:13.353813 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:32:13.357245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:32:13.357354 ==
935 09:32:13.357450
936 09:32:13.357543
937 09:32:13.360542 TX Vref Scan disable
938 09:32:13.363783 == TX Byte 0 ==
939 09:32:13.367816 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 09:32:13.370863 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 09:32:13.374282 == TX Byte 1 ==
942 09:32:13.377626 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 09:32:13.380958 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 09:32:13.381066
945 09:32:13.383751 [DATLAT]
946 09:32:13.383839 Freq=800, CH0 RK0
947 09:32:13.383909
948 09:32:13.387071 DATLAT Default: 0xa
949 09:32:13.387145 0, 0xFFFF, sum = 0
950 09:32:13.390459 1, 0xFFFF, sum = 0
951 09:32:13.390575 2, 0xFFFF, sum = 0
952 09:32:13.393713 3, 0xFFFF, sum = 0
953 09:32:13.393816 4, 0xFFFF, sum = 0
954 09:32:13.397038 5, 0xFFFF, sum = 0
955 09:32:13.397118 6, 0xFFFF, sum = 0
956 09:32:13.400967 7, 0xFFFF, sum = 0
957 09:32:13.401057 8, 0xFFFF, sum = 0
958 09:32:13.404250 9, 0x0, sum = 1
959 09:32:13.404335 10, 0x0, sum = 2
960 09:32:13.407514 11, 0x0, sum = 3
961 09:32:13.407628 12, 0x0, sum = 4
962 09:32:13.410690 best_step = 10
963 09:32:13.410801
964 09:32:13.410897 ==
965 09:32:13.413970 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:32:13.417191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:32:13.417315 ==
968 09:32:13.420431 RX Vref Scan: 1
969 09:32:13.420515
970 09:32:13.420584 Set Vref Range= 32 -> 127
971 09:32:13.420647
972 09:32:13.423861 RX Vref 32 -> 127, step: 1
973 09:32:13.423946
974 09:32:13.427595 RX Delay -79 -> 252, step: 8
975 09:32:13.427690
976 09:32:13.430940 Set Vref, RX VrefLevel [Byte0]: 32
977 09:32:13.433692 [Byte1]: 32
978 09:32:13.433777
979 09:32:13.436958 Set Vref, RX VrefLevel [Byte0]: 33
980 09:32:13.440331 [Byte1]: 33
981 09:32:13.444249
982 09:32:13.444334 Set Vref, RX VrefLevel [Byte0]: 34
983 09:32:13.447515 [Byte1]: 34
984 09:32:13.451306
985 09:32:13.451382 Set Vref, RX VrefLevel [Byte0]: 35
986 09:32:13.455021 [Byte1]: 35
987 09:32:13.459227
988 09:32:13.459342 Set Vref, RX VrefLevel [Byte0]: 36
989 09:32:13.462754 [Byte1]: 36
990 09:32:13.467142
991 09:32:13.467258 Set Vref, RX VrefLevel [Byte0]: 37
992 09:32:13.470530 [Byte1]: 37
993 09:32:13.474170
994 09:32:13.474289 Set Vref, RX VrefLevel [Byte0]: 38
995 09:32:13.477398 [Byte1]: 38
996 09:32:13.481988
997 09:32:13.482110 Set Vref, RX VrefLevel [Byte0]: 39
998 09:32:13.485371 [Byte1]: 39
999 09:32:13.489363
1000 09:32:13.489478 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:32:13.492791 [Byte1]: 40
1002 09:32:13.496895
1003 09:32:13.497008 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:32:13.500527 [Byte1]: 41
1005 09:32:13.504619
1006 09:32:13.504708 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:32:13.507778 [Byte1]: 42
1008 09:32:13.511764
1009 09:32:13.511876 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:32:13.515000 [Byte1]: 43
1011 09:32:13.519734
1012 09:32:13.519847 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:32:13.523045 [Byte1]: 44
1014 09:32:13.527225
1015 09:32:13.527315 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:32:13.530511 [Byte1]: 45
1017 09:32:13.534535
1018 09:32:13.534623 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:32:13.537907 [Byte1]: 46
1020 09:32:13.541876
1021 09:32:13.541961 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:32:13.545144 [Byte1]: 47
1023 09:32:13.549731
1024 09:32:13.549820 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:32:13.553044 [Byte1]: 48
1026 09:32:13.557273
1027 09:32:13.557385 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:32:13.560634 [Byte1]: 49
1029 09:32:13.565027
1030 09:32:13.565112 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:32:13.568199 [Byte1]: 50
1032 09:32:13.572151
1033 09:32:13.572237 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:32:13.575371 [Byte1]: 51
1035 09:32:13.579714
1036 09:32:13.579827 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:32:13.583236 [Byte1]: 52
1038 09:32:13.587237
1039 09:32:13.587349 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:32:13.590585 [Byte1]: 53
1041 09:32:13.595190
1042 09:32:13.595301 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:32:13.598195 [Byte1]: 54
1044 09:32:13.602770
1045 09:32:13.602883 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:32:13.605940 [Byte1]: 55
1047 09:32:13.609891
1048 09:32:13.609975 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:32:13.613123 [Byte1]: 56
1050 09:32:13.617774
1051 09:32:13.617889 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:32:13.620935 [Byte1]: 57
1053 09:32:13.625413
1054 09:32:13.625524 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:32:13.628756 [Byte1]: 58
1056 09:32:13.632618
1057 09:32:13.632706 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:32:13.635957 [Byte1]: 59
1059 09:32:13.640637
1060 09:32:13.640721 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:32:13.643201 [Byte1]: 60
1062 09:32:13.647994
1063 09:32:13.648078 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:32:13.651237 [Byte1]: 61
1065 09:32:13.655131
1066 09:32:13.655237 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:32:13.658575 [Byte1]: 62
1068 09:32:13.662645
1069 09:32:13.662735 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:32:13.665987 [Byte1]: 63
1071 09:32:13.670654
1072 09:32:13.670765 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:32:13.673982 [Byte1]: 64
1074 09:32:13.678196
1075 09:32:13.678301 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:32:13.681653 [Byte1]: 65
1077 09:32:13.685680
1078 09:32:13.685793 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:32:13.688989 [Byte1]: 66
1080 09:32:13.692941
1081 09:32:13.693051 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:32:13.696700 [Byte1]: 67
1083 09:32:13.700777
1084 09:32:13.700883 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:32:13.703595 [Byte1]: 68
1086 09:32:13.707930
1087 09:32:13.708040 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:32:13.711275 [Byte1]: 69
1089 09:32:13.715546
1090 09:32:13.715663 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:32:13.719032 [Byte1]: 70
1092 09:32:13.723026
1093 09:32:13.723111 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:32:13.726481 [Byte1]: 71
1095 09:32:13.730935
1096 09:32:13.731045 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:32:13.733889 [Byte1]: 72
1098 09:32:13.738749
1099 09:32:13.738861 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:32:13.741988 [Byte1]: 73
1101 09:32:13.745926
1102 09:32:13.746036 Set Vref, RX VrefLevel [Byte0]: 74
1103 09:32:13.749303 [Byte1]: 74
1104 09:32:13.753487
1105 09:32:13.753597 Set Vref, RX VrefLevel [Byte0]: 75
1106 09:32:13.756512 [Byte1]: 75
1107 09:32:13.761366
1108 09:32:13.761449 Set Vref, RX VrefLevel [Byte0]: 76
1109 09:32:13.764073 [Byte1]: 76
1110 09:32:13.768644
1111 09:32:13.768750 Set Vref, RX VrefLevel [Byte0]: 77
1112 09:32:13.772101 [Byte1]: 77
1113 09:32:13.776269
1114 09:32:13.776356 Set Vref, RX VrefLevel [Byte0]: 78
1115 09:32:13.779688 [Byte1]: 78
1116 09:32:13.783589
1117 09:32:13.783714 Final RX Vref Byte 0 = 54 to rank0
1118 09:32:13.787181 Final RX Vref Byte 1 = 59 to rank0
1119 09:32:13.790511 Final RX Vref Byte 0 = 54 to rank1
1120 09:32:13.793896 Final RX Vref Byte 1 = 59 to rank1==
1121 09:32:13.797202 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 09:32:13.800615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 09:32:13.803985 ==
1124 09:32:13.804072 DQS Delay:
1125 09:32:13.804167 DQS0 = 0, DQS1 = 0
1126 09:32:13.807464 DQM Delay:
1127 09:32:13.807578 DQM0 = 91, DQM1 = 85
1128 09:32:13.810723 DQ Delay:
1129 09:32:13.810857 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 09:32:13.814074 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1131 09:32:13.817344 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1132 09:32:13.820542 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 09:32:13.823994
1134 09:32:13.824115
1135 09:32:13.830808 [DQSOSCAuto] RK0, (LSB)MR18= 0x5046, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1136 09:32:13.834074 CH0 RK0: MR19=606, MR18=5046
1137 09:32:13.840393 CH0_RK0: MR19=0x606, MR18=0x5046, DQSOSC=389, MR23=63, INC=97, DEC=65
1138 09:32:13.840477
1139 09:32:13.843921 ----->DramcWriteLeveling(PI) begin...
1140 09:32:13.844035 ==
1141 09:32:13.847371 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 09:32:13.850709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 09:32:13.850817 ==
1144 09:32:13.854044 Write leveling (Byte 0): 35 => 35
1145 09:32:13.857176 Write leveling (Byte 1): 31 => 31
1146 09:32:13.860855 DramcWriteLeveling(PI) end<-----
1147 09:32:13.860976
1148 09:32:13.861065 ==
1149 09:32:13.863989 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 09:32:13.867256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 09:32:13.867379 ==
1152 09:32:13.911382 [Gating] SW mode calibration
1153 09:32:13.911684 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 09:32:13.911764 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 09:32:13.911829 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 09:32:13.911892 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 09:32:13.911952 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 09:32:13.912023 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:32:13.912084 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:32:13.912732 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:32:13.955870 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:32:13.956017 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:32:13.956284 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:32:13.956353 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:32:13.956414 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:32:13.956473 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:32:13.956531 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:32:13.956599 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:32:13.956657 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:32:13.957177 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:32:13.999755 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:32:13.999932 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1173 09:32:14.000230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1174 09:32:14.000330 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:32:14.000423 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:32:14.000513 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:32:14.000601 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:32:14.000701 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:32:14.000790 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:32:14.000877 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1181 09:32:14.000963 0 9 8 | B1->B0 | 2b2b 2c2c | 1 0 | (0 0) (0 0)
1182 09:32:14.043893 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 09:32:14.044231 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 09:32:14.044306 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 09:32:14.044369 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 09:32:14.044429 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 09:32:14.044489 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 09:32:14.044558 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 0)
1189 09:32:14.044618 0 10 8 | B1->B0 | 2626 2c2c | 0 0 | (1 1) (1 0)
1190 09:32:14.044869 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:32:14.044966 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:32:14.087837 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:32:14.088223 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:32:14.088329 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:32:14.088423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:32:14.088514 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1197 09:32:14.088603 0 11 8 | B1->B0 | 4141 3f3f | 0 1 | (0 0) (0 0)
1198 09:32:14.088690 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 09:32:14.088791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 09:32:14.088880 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 09:32:14.088967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 09:32:14.095266 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 09:32:14.098670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 09:32:14.101800 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 09:32:14.105445 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 09:32:14.112168 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 09:32:14.115669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:32:14.119035 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:32:14.125565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:32:14.129062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:32:14.132452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:32:14.138671 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:32:14.142510 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:32:14.145635 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:32:14.152458 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:32:14.155749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:32:14.158871 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 09:32:14.165629 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 09:32:14.169056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:32:14.172412 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 09:32:14.175865 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 09:32:14.182517 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 09:32:14.185988 Total UI for P1: 0, mck2ui 16
1224 09:32:14.188757 best dqsien dly found for B0: ( 0, 14, 8)
1225 09:32:14.192117 Total UI for P1: 0, mck2ui 16
1226 09:32:14.195404 best dqsien dly found for B1: ( 0, 14, 8)
1227 09:32:14.198765 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 09:32:14.202087 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 09:32:14.202199
1230 09:32:14.205774 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 09:32:14.208707 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 09:32:14.212233 [Gating] SW calibration Done
1233 09:32:14.212319 ==
1234 09:32:14.215729 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 09:32:14.219031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 09:32:14.219116 ==
1237 09:32:14.222088 RX Vref Scan: 0
1238 09:32:14.222196
1239 09:32:14.222287 RX Vref 0 -> 0, step: 1
1240 09:32:14.222380
1241 09:32:14.225768 RX Delay -130 -> 252, step: 16
1242 09:32:14.229345 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 09:32:14.235979 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 09:32:14.238859 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1245 09:32:14.242334 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1246 09:32:14.245624 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 09:32:14.248920 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1248 09:32:14.255933 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 09:32:14.259334 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 09:32:14.262640 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 09:32:14.266047 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1252 09:32:14.269162 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1253 09:32:14.275810 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 09:32:14.279172 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1255 09:32:14.282559 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1256 09:32:14.285938 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 09:32:14.289388 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1258 09:32:14.292691 ==
1259 09:32:14.292809 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 09:32:14.299392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 09:32:14.299518 ==
1262 09:32:14.299616 DQS Delay:
1263 09:32:14.302741 DQS0 = 0, DQS1 = 0
1264 09:32:14.302832 DQM Delay:
1265 09:32:14.306223 DQM0 = 94, DQM1 = 86
1266 09:32:14.306334 DQ Delay:
1267 09:32:14.309630 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1268 09:32:14.312321 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =101
1269 09:32:14.316122 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1270 09:32:14.319067 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1271 09:32:14.319150
1272 09:32:14.319216
1273 09:32:14.319278 ==
1274 09:32:14.322726 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 09:32:14.326211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 09:32:14.326296 ==
1277 09:32:14.326362
1278 09:32:14.326423
1279 09:32:14.329493 TX Vref Scan disable
1280 09:32:14.332817 == TX Byte 0 ==
1281 09:32:14.336080 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1282 09:32:14.339333 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1283 09:32:14.342407 == TX Byte 1 ==
1284 09:32:14.346112 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 09:32:14.349172 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 09:32:14.349255 ==
1287 09:32:14.352634 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 09:32:14.355819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 09:32:14.355915 ==
1290 09:32:14.370759 TX Vref=22, minBit 8, minWin=27, winSum=445
1291 09:32:14.373865 TX Vref=24, minBit 12, minWin=27, winSum=449
1292 09:32:14.377584 TX Vref=26, minBit 1, minWin=28, winSum=454
1293 09:32:14.381011 TX Vref=28, minBit 1, minWin=28, winSum=456
1294 09:32:14.384314 TX Vref=30, minBit 1, minWin=28, winSum=454
1295 09:32:14.387822 TX Vref=32, minBit 1, minWin=28, winSum=450
1296 09:32:14.394021 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 28
1297 09:32:14.394106
1298 09:32:14.397368 Final TX Range 1 Vref 28
1299 09:32:14.397452
1300 09:32:14.397518 ==
1301 09:32:14.400722 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 09:32:14.403998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 09:32:14.404088 ==
1304 09:32:14.404155
1305 09:32:14.407374
1306 09:32:14.407457 TX Vref Scan disable
1307 09:32:14.410717 == TX Byte 0 ==
1308 09:32:14.414014 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1309 09:32:14.417346 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1310 09:32:14.421306 == TX Byte 1 ==
1311 09:32:14.424447 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 09:32:14.427365 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 09:32:14.427448
1314 09:32:14.430847 [DATLAT]
1315 09:32:14.430931 Freq=800, CH0 RK1
1316 09:32:14.430999
1317 09:32:14.434118 DATLAT Default: 0xa
1318 09:32:14.434201 0, 0xFFFF, sum = 0
1319 09:32:14.437483 1, 0xFFFF, sum = 0
1320 09:32:14.437569 2, 0xFFFF, sum = 0
1321 09:32:14.440949 3, 0xFFFF, sum = 0
1322 09:32:14.441033 4, 0xFFFF, sum = 0
1323 09:32:14.444321 5, 0xFFFF, sum = 0
1324 09:32:14.444407 6, 0xFFFF, sum = 0
1325 09:32:14.447699 7, 0xFFFF, sum = 0
1326 09:32:14.447785 8, 0xFFFF, sum = 0
1327 09:32:14.451105 9, 0x0, sum = 1
1328 09:32:14.451189 10, 0x0, sum = 2
1329 09:32:14.454367 11, 0x0, sum = 3
1330 09:32:14.454451 12, 0x0, sum = 4
1331 09:32:14.457683 best_step = 10
1332 09:32:14.457766
1333 09:32:14.457832 ==
1334 09:32:14.461576 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 09:32:14.464510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 09:32:14.464596 ==
1337 09:32:14.467826 RX Vref Scan: 0
1338 09:32:14.467908
1339 09:32:14.467974 RX Vref 0 -> 0, step: 1
1340 09:32:14.468035
1341 09:32:14.470974 RX Delay -79 -> 252, step: 8
1342 09:32:14.477946 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 09:32:14.481312 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1344 09:32:14.484474 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 09:32:14.487929 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 09:32:14.491194 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 09:32:14.494853 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1348 09:32:14.501373 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 09:32:14.504897 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 09:32:14.507675 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1351 09:32:14.511683 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1352 09:32:14.514446 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 09:32:14.521775 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 09:32:14.525226 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1355 09:32:14.528516 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1356 09:32:14.531839 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 09:32:14.535018 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 09:32:14.538173 ==
1359 09:32:14.538255 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 09:32:14.544699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 09:32:14.544801 ==
1362 09:32:14.544883 DQS Delay:
1363 09:32:14.547996 DQS0 = 0, DQS1 = 0
1364 09:32:14.548077 DQM Delay:
1365 09:32:14.551405 DQM0 = 92, DQM1 = 82
1366 09:32:14.551515 DQ Delay:
1367 09:32:14.554925 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1368 09:32:14.558219 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1369 09:32:14.561694 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1370 09:32:14.564778 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1371 09:32:14.564867
1372 09:32:14.564966
1373 09:32:14.571306 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1374 09:32:14.575278 CH0 RK1: MR19=606, MR18=4112
1375 09:32:14.581395 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1376 09:32:14.584776 [RxdqsGatingPostProcess] freq 800
1377 09:32:14.588188 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 09:32:14.591368 Pre-setting of DQS Precalculation
1379 09:32:14.598656 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 09:32:14.598769 ==
1381 09:32:14.601741 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 09:32:14.604645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 09:32:14.604729 ==
1384 09:32:14.611800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 09:32:14.618025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 09:32:14.626508 [CA 0] Center 36 (6~67) winsize 62
1387 09:32:14.628828 [CA 1] Center 36 (6~67) winsize 62
1388 09:32:14.632766 [CA 2] Center 34 (4~65) winsize 62
1389 09:32:14.636159 [CA 3] Center 34 (4~65) winsize 62
1390 09:32:14.639525 [CA 4] Center 34 (4~65) winsize 62
1391 09:32:14.642868 [CA 5] Center 34 (4~64) winsize 61
1392 09:32:14.642972
1393 09:32:14.646145 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 09:32:14.646234
1395 09:32:14.649419 [CATrainingPosCal] consider 1 rank data
1396 09:32:14.652455 u2DelayCellTimex100 = 270/100 ps
1397 09:32:14.656219 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 09:32:14.659503 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 09:32:14.666045 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 09:32:14.669230 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 09:32:14.672764 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 09:32:14.676175 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 09:32:14.676299
1404 09:32:14.679328 CA PerBit enable=1, Macro0, CA PI delay=34
1405 09:32:14.679441
1406 09:32:14.682685 [CBTSetCACLKResult] CA Dly = 34
1407 09:32:14.682780 CS Dly: 5 (0~36)
1408 09:32:14.682876 ==
1409 09:32:14.686438 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 09:32:14.692732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 09:32:14.692819 ==
1412 09:32:14.696089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 09:32:14.702838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 09:32:14.712685 [CA 0] Center 36 (6~67) winsize 62
1415 09:32:14.715369 [CA 1] Center 36 (6~67) winsize 62
1416 09:32:14.719542 [CA 2] Center 35 (4~66) winsize 63
1417 09:32:14.722780 [CA 3] Center 34 (4~65) winsize 62
1418 09:32:14.726663 [CA 4] Center 35 (5~66) winsize 62
1419 09:32:14.730478 [CA 5] Center 34 (4~65) winsize 62
1420 09:32:14.730662
1421 09:32:14.734050 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 09:32:14.734218
1423 09:32:14.737726 [CATrainingPosCal] consider 2 rank data
1424 09:32:14.737834 u2DelayCellTimex100 = 270/100 ps
1425 09:32:14.741337 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 09:32:14.748351 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 09:32:14.751849 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 09:32:14.755034 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 09:32:14.758203 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 09:32:14.761954 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 09:32:14.762081
1432 09:32:14.765053 CA PerBit enable=1, Macro0, CA PI delay=34
1433 09:32:14.765171
1434 09:32:14.768535 [CBTSetCACLKResult] CA Dly = 34
1435 09:32:14.768639 CS Dly: 6 (0~38)
1436 09:32:14.768733
1437 09:32:14.771780 ----->DramcWriteLeveling(PI) begin...
1438 09:32:14.775220 ==
1439 09:32:14.778487 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 09:32:14.781935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 09:32:14.782035 ==
1442 09:32:14.784658 Write leveling (Byte 0): 25 => 25
1443 09:32:14.788612 Write leveling (Byte 1): 30 => 30
1444 09:32:14.791998 DramcWriteLeveling(PI) end<-----
1445 09:32:14.792090
1446 09:32:14.792160 ==
1447 09:32:14.795425 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 09:32:14.798727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 09:32:14.798830 ==
1450 09:32:14.802053 [Gating] SW mode calibration
1451 09:32:14.808643 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 09:32:14.811822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 09:32:14.818553 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1454 09:32:14.821931 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 09:32:14.825400 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 09:32:14.832166 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:32:14.835483 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:32:14.838870 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:32:14.845327 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:32:14.848520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:32:14.852318 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:32:14.858591 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:32:14.862326 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:32:14.865233 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:32:14.872011 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:32:14.875227 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:32:14.878621 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:32:14.882044 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:32:14.888763 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 09:32:14.891785 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1471 09:32:14.895513 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:32:14.901829 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:32:14.905164 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:32:14.908722 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:32:14.915515 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:32:14.918709 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:32:14.921927 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:32:14.928749 0 9 4 | B1->B0 | 2323 2525 | 1 1 | (1 1) (1 1)
1479 09:32:14.932086 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1480 09:32:14.935425 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 09:32:14.942270 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 09:32:14.945691 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 09:32:14.949054 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 09:32:14.955398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 09:32:14.958775 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 09:32:14.962078 0 10 4 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (1 0)
1487 09:32:14.968914 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
1488 09:32:14.972044 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:32:14.975303 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:32:14.978636 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:32:14.985498 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:32:14.988718 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:32:14.991723 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:32:14.998894 0 11 4 | B1->B0 | 2e2e 3737 | 0 0 | (0 0) (0 0)
1495 09:32:15.002044 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 09:32:15.005344 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 09:32:15.012210 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 09:32:15.015382 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 09:32:15.018800 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 09:32:15.025440 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 09:32:15.029084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1502 09:32:15.032453 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1503 09:32:15.039035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:32:15.042355 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:32:15.045753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:32:15.052043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:32:15.055483 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:32:15.058636 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:32:15.062298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:32:15.068916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:32:15.072408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:32:15.075742 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:32:15.082397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:32:15.085952 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:32:15.089277 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:32:15.095697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:32:15.099035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:32:15.102307 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 09:32:15.109098 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 09:32:15.109215 Total UI for P1: 0, mck2ui 16
1521 09:32:15.116143 best dqsien dly found for B0: ( 0, 14, 6)
1522 09:32:15.116243 Total UI for P1: 0, mck2ui 16
1523 09:32:15.119077 best dqsien dly found for B1: ( 0, 14, 4)
1524 09:32:15.126037 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 09:32:15.129444 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 09:32:15.129554
1527 09:32:15.132527 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 09:32:15.135740 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 09:32:15.138937 [Gating] SW calibration Done
1530 09:32:15.139020 ==
1531 09:32:15.142159 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 09:32:15.145673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 09:32:15.145780 ==
1534 09:32:15.145874 RX Vref Scan: 0
1535 09:32:15.149266
1536 09:32:15.149413 RX Vref 0 -> 0, step: 1
1537 09:32:15.149519
1538 09:32:15.152937 RX Delay -130 -> 252, step: 16
1539 09:32:15.155563 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1540 09:32:15.158972 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 09:32:15.165661 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 09:32:15.169600 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 09:32:15.172869 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 09:32:15.175594 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 09:32:15.178954 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1546 09:32:15.185727 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 09:32:15.188988 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 09:32:15.192366 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 09:32:15.195615 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 09:32:15.198989 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 09:32:15.205563 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1552 09:32:15.209659 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1553 09:32:15.212507 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1554 09:32:15.215950 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1555 09:32:15.216034 ==
1556 09:32:15.219295 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 09:32:15.225943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 09:32:15.226053 ==
1559 09:32:15.226157 DQS Delay:
1560 09:32:15.226249 DQS0 = 0, DQS1 = 0
1561 09:32:15.229190 DQM Delay:
1562 09:32:15.229292 DQM0 = 95, DQM1 = 91
1563 09:32:15.232590 DQ Delay:
1564 09:32:15.235956 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1565 09:32:15.239197 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1566 09:32:15.242388 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1567 09:32:15.245614 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1568 09:32:15.245714
1569 09:32:15.245806
1570 09:32:15.245899 ==
1571 09:32:15.249510 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 09:32:15.252578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 09:32:15.252690 ==
1574 09:32:15.252784
1575 09:32:15.252876
1576 09:32:15.256233 TX Vref Scan disable
1577 09:32:15.256343 == TX Byte 0 ==
1578 09:32:15.262413 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1579 09:32:15.266108 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1580 09:32:15.266191 == TX Byte 1 ==
1581 09:32:15.273179 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 09:32:15.276207 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 09:32:15.276303 ==
1584 09:32:15.279354 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 09:32:15.282737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 09:32:15.282822 ==
1587 09:32:15.297682 TX Vref=22, minBit 1, minWin=26, winSum=435
1588 09:32:15.300866 TX Vref=24, minBit 1, minWin=26, winSum=438
1589 09:32:15.304181 TX Vref=26, minBit 3, minWin=26, winSum=442
1590 09:32:15.307259 TX Vref=28, minBit 1, minWin=27, winSum=445
1591 09:32:15.310656 TX Vref=30, minBit 1, minWin=27, winSum=448
1592 09:32:15.314055 TX Vref=32, minBit 0, minWin=26, winSum=443
1593 09:32:15.320919 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1594 09:32:15.321003
1595 09:32:15.324172 Final TX Range 1 Vref 30
1596 09:32:15.324256
1597 09:32:15.324322 ==
1598 09:32:15.327697 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 09:32:15.330396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 09:32:15.330479 ==
1601 09:32:15.330545
1602 09:32:15.330606
1603 09:32:15.333638 TX Vref Scan disable
1604 09:32:15.337611 == TX Byte 0 ==
1605 09:32:15.340380 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 09:32:15.344139 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 09:32:15.347528 == TX Byte 1 ==
1608 09:32:15.350992 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 09:32:15.354260 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 09:32:15.354344
1611 09:32:15.357120 [DATLAT]
1612 09:32:15.357202 Freq=800, CH1 RK0
1613 09:32:15.357269
1614 09:32:15.360485 DATLAT Default: 0xa
1615 09:32:15.360594 0, 0xFFFF, sum = 0
1616 09:32:15.363849 1, 0xFFFF, sum = 0
1617 09:32:15.363933 2, 0xFFFF, sum = 0
1618 09:32:15.367134 3, 0xFFFF, sum = 0
1619 09:32:15.367218 4, 0xFFFF, sum = 0
1620 09:32:15.370248 5, 0xFFFF, sum = 0
1621 09:32:15.370333 6, 0xFFFF, sum = 0
1622 09:32:15.374012 7, 0xFFFF, sum = 0
1623 09:32:15.377065 8, 0xFFFF, sum = 0
1624 09:32:15.377150 9, 0x0, sum = 1
1625 09:32:15.377217 10, 0x0, sum = 2
1626 09:32:15.380759 11, 0x0, sum = 3
1627 09:32:15.380843 12, 0x0, sum = 4
1628 09:32:15.383943 best_step = 10
1629 09:32:15.384026
1630 09:32:15.384093 ==
1631 09:32:15.387273 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 09:32:15.390717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 09:32:15.390803 ==
1634 09:32:15.394162 RX Vref Scan: 1
1635 09:32:15.394261
1636 09:32:15.394353 Set Vref Range= 32 -> 127
1637 09:32:15.394442
1638 09:32:15.397370 RX Vref 32 -> 127, step: 1
1639 09:32:15.397469
1640 09:32:15.400571 RX Delay -79 -> 252, step: 8
1641 09:32:15.400683
1642 09:32:15.403834 Set Vref, RX VrefLevel [Byte0]: 32
1643 09:32:15.407862 [Byte1]: 32
1644 09:32:15.407944
1645 09:32:15.410822 Set Vref, RX VrefLevel [Byte0]: 33
1646 09:32:15.413927 [Byte1]: 33
1647 09:32:15.417365
1648 09:32:15.417519 Set Vref, RX VrefLevel [Byte0]: 34
1649 09:32:15.420619 [Byte1]: 34
1650 09:32:15.424782
1651 09:32:15.424868 Set Vref, RX VrefLevel [Byte0]: 35
1652 09:32:15.428135 [Byte1]: 35
1653 09:32:15.432808
1654 09:32:15.432920 Set Vref, RX VrefLevel [Byte0]: 36
1655 09:32:15.435607 [Byte1]: 36
1656 09:32:15.440057
1657 09:32:15.440170 Set Vref, RX VrefLevel [Byte0]: 37
1658 09:32:15.443315 [Byte1]: 37
1659 09:32:15.447328
1660 09:32:15.447450 Set Vref, RX VrefLevel [Byte0]: 38
1661 09:32:15.451148 [Byte1]: 38
1662 09:32:15.455096
1663 09:32:15.455199 Set Vref, RX VrefLevel [Byte0]: 39
1664 09:32:15.458401 [Byte1]: 39
1665 09:32:15.462555
1666 09:32:15.462666 Set Vref, RX VrefLevel [Byte0]: 40
1667 09:32:15.466080 [Byte1]: 40
1668 09:32:15.470189
1669 09:32:15.470271 Set Vref, RX VrefLevel [Byte0]: 41
1670 09:32:15.473317 [Byte1]: 41
1671 09:32:15.477967
1672 09:32:15.478075 Set Vref, RX VrefLevel [Byte0]: 42
1673 09:32:15.481241 [Byte1]: 42
1674 09:32:15.485160
1675 09:32:15.485243 Set Vref, RX VrefLevel [Byte0]: 43
1676 09:32:15.488487 [Byte1]: 43
1677 09:32:15.492641
1678 09:32:15.492764 Set Vref, RX VrefLevel [Byte0]: 44
1679 09:32:15.495932 [Byte1]: 44
1680 09:32:15.500690
1681 09:32:15.500808 Set Vref, RX VrefLevel [Byte0]: 45
1682 09:32:15.503769 [Byte1]: 45
1683 09:32:15.508131
1684 09:32:15.508213 Set Vref, RX VrefLevel [Byte0]: 46
1685 09:32:15.511071 [Byte1]: 46
1686 09:32:15.515364
1687 09:32:15.515474 Set Vref, RX VrefLevel [Byte0]: 47
1688 09:32:15.518856 [Byte1]: 47
1689 09:32:15.522793
1690 09:32:15.522897 Set Vref, RX VrefLevel [Byte0]: 48
1691 09:32:15.526684 [Byte1]: 48
1692 09:32:15.530768
1693 09:32:15.530851 Set Vref, RX VrefLevel [Byte0]: 49
1694 09:32:15.533687 [Byte1]: 49
1695 09:32:15.537982
1696 09:32:15.538093 Set Vref, RX VrefLevel [Byte0]: 50
1697 09:32:15.541253 [Byte1]: 50
1698 09:32:15.545665
1699 09:32:15.545780 Set Vref, RX VrefLevel [Byte0]: 51
1700 09:32:15.549204 [Byte1]: 51
1701 09:32:15.553162
1702 09:32:15.553277 Set Vref, RX VrefLevel [Byte0]: 52
1703 09:32:15.556392 [Byte1]: 52
1704 09:32:15.561070
1705 09:32:15.561188 Set Vref, RX VrefLevel [Byte0]: 53
1706 09:32:15.563793 [Byte1]: 53
1707 09:32:15.568558
1708 09:32:15.568673 Set Vref, RX VrefLevel [Byte0]: 54
1709 09:32:15.571840 [Byte1]: 54
1710 09:32:15.575939
1711 09:32:15.576040 Set Vref, RX VrefLevel [Byte0]: 55
1712 09:32:15.579215 [Byte1]: 55
1713 09:32:15.583229
1714 09:32:15.583333 Set Vref, RX VrefLevel [Byte0]: 56
1715 09:32:15.586583 [Byte1]: 56
1716 09:32:15.591259
1717 09:32:15.591379 Set Vref, RX VrefLevel [Byte0]: 57
1718 09:32:15.593867 [Byte1]: 57
1719 09:32:15.598566
1720 09:32:15.598687 Set Vref, RX VrefLevel [Byte0]: 58
1721 09:32:15.601934 [Byte1]: 58
1722 09:32:15.606014
1723 09:32:15.606138 Set Vref, RX VrefLevel [Byte0]: 59
1724 09:32:15.609455 [Byte1]: 59
1725 09:32:15.613571
1726 09:32:15.613687 Set Vref, RX VrefLevel [Byte0]: 60
1727 09:32:15.616845 [Byte1]: 60
1728 09:32:15.621407
1729 09:32:15.621534 Set Vref, RX VrefLevel [Byte0]: 61
1730 09:32:15.624866 [Byte1]: 61
1731 09:32:15.628654
1732 09:32:15.628780 Set Vref, RX VrefLevel [Byte0]: 62
1733 09:32:15.632203 [Byte1]: 62
1734 09:32:15.635976
1735 09:32:15.636072 Set Vref, RX VrefLevel [Byte0]: 63
1736 09:32:15.639693 [Byte1]: 63
1737 09:32:15.643872
1738 09:32:15.643997 Set Vref, RX VrefLevel [Byte0]: 64
1739 09:32:15.646762 [Byte1]: 64
1740 09:32:15.651554
1741 09:32:15.651665 Set Vref, RX VrefLevel [Byte0]: 65
1742 09:32:15.654887 [Byte1]: 65
1743 09:32:15.658638
1744 09:32:15.658741 Set Vref, RX VrefLevel [Byte0]: 66
1745 09:32:15.662310 [Byte1]: 66
1746 09:32:15.666154
1747 09:32:15.666261 Set Vref, RX VrefLevel [Byte0]: 67
1748 09:32:15.669801 [Byte1]: 67
1749 09:32:15.673768
1750 09:32:15.673845 Set Vref, RX VrefLevel [Byte0]: 68
1751 09:32:15.677110 [Byte1]: 68
1752 09:32:15.681618
1753 09:32:15.681692 Set Vref, RX VrefLevel [Byte0]: 69
1754 09:32:15.685008 [Byte1]: 69
1755 09:32:15.689162
1756 09:32:15.689274 Set Vref, RX VrefLevel [Byte0]: 70
1757 09:32:15.692456 [Byte1]: 70
1758 09:32:15.696414
1759 09:32:15.696530 Set Vref, RX VrefLevel [Byte0]: 71
1760 09:32:15.699838 [Byte1]: 71
1761 09:32:15.704343
1762 09:32:15.704448 Set Vref, RX VrefLevel [Byte0]: 72
1763 09:32:15.707529 [Byte1]: 72
1764 09:32:15.711659
1765 09:32:15.711767 Final RX Vref Byte 0 = 59 to rank0
1766 09:32:15.715011 Final RX Vref Byte 1 = 55 to rank0
1767 09:32:15.718312 Final RX Vref Byte 0 = 59 to rank1
1768 09:32:15.721670 Final RX Vref Byte 1 = 55 to rank1==
1769 09:32:15.725039 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 09:32:15.732011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 09:32:15.732094 ==
1772 09:32:15.732159 DQS Delay:
1773 09:32:15.732226 DQS0 = 0, DQS1 = 0
1774 09:32:15.735342 DQM Delay:
1775 09:32:15.735441 DQM0 = 96, DQM1 = 90
1776 09:32:15.738639 DQ Delay:
1777 09:32:15.741891 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1778 09:32:15.745090 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1779 09:32:15.748318 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1780 09:32:15.751622 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 09:32:15.751711
1782 09:32:15.751775
1783 09:32:15.758288 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1784 09:32:15.761583 CH1 RK0: MR19=606, MR18=2E4A
1785 09:32:15.768529 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1786 09:32:15.768613
1787 09:32:15.771382 ----->DramcWriteLeveling(PI) begin...
1788 09:32:15.771486 ==
1789 09:32:15.774952 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 09:32:15.778168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 09:32:15.778275 ==
1792 09:32:15.781368 Write leveling (Byte 0): 28 => 28
1793 09:32:15.784978 Write leveling (Byte 1): 29 => 29
1794 09:32:15.788410 DramcWriteLeveling(PI) end<-----
1795 09:32:15.788532
1796 09:32:15.788615 ==
1797 09:32:15.791579 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 09:32:15.795018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 09:32:15.795104 ==
1800 09:32:15.798541 [Gating] SW mode calibration
1801 09:32:15.804960 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 09:32:15.811625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 09:32:15.815009 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 09:32:15.818301 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1805 09:32:15.825081 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 09:32:15.828368 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 09:32:15.831690 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 09:32:15.838531 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 09:32:15.841802 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 09:32:15.845150 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 09:32:15.848888 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 09:32:15.855606 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 09:32:15.858903 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 09:32:15.862216 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:32:15.868983 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:32:15.872356 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:32:15.875788 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:32:15.882421 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:32:15.885734 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1820 09:32:15.888966 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1821 09:32:15.895616 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:32:15.898617 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:32:15.902181 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:32:15.908772 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:32:15.912387 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:32:15.915648 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:32:15.922289 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:32:15.925460 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1829 09:32:15.929384 0 9 8 | B1->B0 | 3434 3130 | 1 1 | (1 1) (1 1)
1830 09:32:15.932620 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 09:32:15.939262 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 09:32:15.942442 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 09:32:15.945750 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 09:32:15.952218 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 09:32:15.955613 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1836 09:32:15.958954 0 10 4 | B1->B0 | 2727 3030 | 1 1 | (1 0) (1 1)
1837 09:32:15.965765 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:32:15.969007 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:32:15.972353 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:32:15.979629 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:32:15.983051 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:32:15.985726 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:32:15.992885 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:32:15.996210 0 11 4 | B1->B0 | 3b3b 2727 | 0 0 | (0 0) (0 0)
1845 09:32:15.999575 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1846 09:32:16.002289 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 09:32:16.009429 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 09:32:16.012783 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 09:32:16.015902 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 09:32:16.022432 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 09:32:16.026303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 09:32:16.029458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1853 09:32:16.036143 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 09:32:16.039514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 09:32:16.042681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 09:32:16.049381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 09:32:16.052699 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 09:32:16.056318 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 09:32:16.062668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 09:32:16.066159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 09:32:16.069722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 09:32:16.076343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 09:32:16.079732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 09:32:16.083094 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:32:16.086423 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:32:16.092642 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:32:16.096110 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:32:16.100009 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1869 09:32:16.106594 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 09:32:16.106703 Total UI for P1: 0, mck2ui 16
1871 09:32:16.113181 best dqsien dly found for B0: ( 0, 14, 6)
1872 09:32:16.113264 Total UI for P1: 0, mck2ui 16
1873 09:32:16.119828 best dqsien dly found for B1: ( 0, 14, 4)
1874 09:32:16.122914 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1875 09:32:16.126254 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1876 09:32:16.126339
1877 09:32:16.129499 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1878 09:32:16.132830 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 09:32:16.136179 [Gating] SW calibration Done
1880 09:32:16.136266 ==
1881 09:32:16.139499 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 09:32:16.142914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 09:32:16.142998 ==
1884 09:32:16.146136 RX Vref Scan: 0
1885 09:32:16.146221
1886 09:32:16.146288 RX Vref 0 -> 0, step: 1
1887 09:32:16.146351
1888 09:32:16.149402 RX Delay -130 -> 252, step: 16
1889 09:32:16.153287 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1890 09:32:16.159672 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1891 09:32:16.163212 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1892 09:32:16.166689 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1893 09:32:16.169785 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1894 09:32:16.173581 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1895 09:32:16.176572 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1896 09:32:16.183522 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1897 09:32:16.186829 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1898 09:32:16.190264 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1899 09:32:16.193446 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1900 09:32:16.196914 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1901 09:32:16.203311 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1902 09:32:16.206622 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1903 09:32:16.210140 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1904 09:32:16.213389 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1905 09:32:16.213480 ==
1906 09:32:16.216749 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 09:32:16.223315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 09:32:16.223410 ==
1909 09:32:16.223477 DQS Delay:
1910 09:32:16.223539 DQS0 = 0, DQS1 = 0
1911 09:32:16.226591 DQM Delay:
1912 09:32:16.226665 DQM0 = 92, DQM1 = 89
1913 09:32:16.230467 DQ Delay:
1914 09:32:16.233093 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1915 09:32:16.236548 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1916 09:32:16.239743 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1917 09:32:16.243064 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1918 09:32:16.243149
1919 09:32:16.243214
1920 09:32:16.243274 ==
1921 09:32:16.246452 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 09:32:16.249863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 09:32:16.249954 ==
1924 09:32:16.250021
1925 09:32:16.250082
1926 09:32:16.253501 TX Vref Scan disable
1927 09:32:16.256292 == TX Byte 0 ==
1928 09:32:16.259669 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1929 09:32:16.263133 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1930 09:32:16.263220 == TX Byte 1 ==
1931 09:32:16.269801 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1932 09:32:16.273432 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1933 09:32:16.273516 ==
1934 09:32:16.276576 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 09:32:16.279769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 09:32:16.279867 ==
1937 09:32:16.294027 TX Vref=22, minBit 0, minWin=27, winSum=445
1938 09:32:16.297275 TX Vref=24, minBit 3, minWin=26, winSum=444
1939 09:32:16.300541 TX Vref=26, minBit 2, minWin=27, winSum=448
1940 09:32:16.304345 TX Vref=28, minBit 0, minWin=27, winSum=450
1941 09:32:16.307143 TX Vref=30, minBit 2, minWin=27, winSum=450
1942 09:32:16.310963 TX Vref=32, minBit 2, minWin=27, winSum=450
1943 09:32:16.317248 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 28
1944 09:32:16.317348
1945 09:32:16.320523 Final TX Range 1 Vref 28
1946 09:32:16.320616
1947 09:32:16.320681 ==
1948 09:32:16.324092 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 09:32:16.327322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 09:32:16.327432 ==
1951 09:32:16.327525
1952 09:32:16.327617
1953 09:32:16.330717 TX Vref Scan disable
1954 09:32:16.333910 == TX Byte 0 ==
1955 09:32:16.337772 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 09:32:16.341030 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 09:32:16.344556 == TX Byte 1 ==
1958 09:32:16.347804 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1959 09:32:16.351088 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1960 09:32:16.351168
1961 09:32:16.354419 [DATLAT]
1962 09:32:16.354499 Freq=800, CH1 RK1
1963 09:32:16.354571
1964 09:32:16.357545 DATLAT Default: 0xa
1965 09:32:16.357620 0, 0xFFFF, sum = 0
1966 09:32:16.360762 1, 0xFFFF, sum = 0
1967 09:32:16.360833 2, 0xFFFF, sum = 0
1968 09:32:16.364156 3, 0xFFFF, sum = 0
1969 09:32:16.364243 4, 0xFFFF, sum = 0
1970 09:32:16.367484 5, 0xFFFF, sum = 0
1971 09:32:16.367589 6, 0xFFFF, sum = 0
1972 09:32:16.370929 7, 0xFFFF, sum = 0
1973 09:32:16.371006 8, 0xFFFF, sum = 0
1974 09:32:16.374380 9, 0x0, sum = 1
1975 09:32:16.374482 10, 0x0, sum = 2
1976 09:32:16.377586 11, 0x0, sum = 3
1977 09:32:16.377685 12, 0x0, sum = 4
1978 09:32:16.380766 best_step = 10
1979 09:32:16.380881
1980 09:32:16.380978 ==
1981 09:32:16.384687 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 09:32:16.387931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 09:32:16.388027 ==
1984 09:32:16.391267 RX Vref Scan: 0
1985 09:32:16.391356
1986 09:32:16.391423 RX Vref 0 -> 0, step: 1
1987 09:32:16.391486
1988 09:32:16.394650 RX Delay -79 -> 252, step: 8
1989 09:32:16.398091 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1990 09:32:16.404242 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1991 09:32:16.407962 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1992 09:32:16.411157 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1993 09:32:16.414493 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1994 09:32:16.417761 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1995 09:32:16.424111 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1996 09:32:16.427613 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1997 09:32:16.430968 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1998 09:32:16.434272 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1999 09:32:16.437991 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2000 09:32:16.441058 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2001 09:32:16.447574 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2002 09:32:16.450976 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2003 09:32:16.454340 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2004 09:32:16.457708 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2005 09:32:16.457792 ==
2006 09:32:16.461025 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 09:32:16.467992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 09:32:16.468080 ==
2009 09:32:16.468146 DQS Delay:
2010 09:32:16.470753 DQS0 = 0, DQS1 = 0
2011 09:32:16.470828 DQM Delay:
2012 09:32:16.470890 DQM0 = 97, DQM1 = 91
2013 09:32:16.474065 DQ Delay:
2014 09:32:16.477423 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2015 09:32:16.480748 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2016 09:32:16.484741 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2017 09:32:16.487826 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2018 09:32:16.487974
2019 09:32:16.488145
2020 09:32:16.494309 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2021 09:32:16.497514 CH1 RK1: MR19=606, MR18=460F
2022 09:32:16.504771 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2023 09:32:16.507486 [RxdqsGatingPostProcess] freq 800
2024 09:32:16.510878 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 09:32:16.514722 Pre-setting of DQS Precalculation
2026 09:32:16.521508 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 09:32:16.528104 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 09:32:16.534676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 09:32:16.534778
2030 09:32:16.534868
2031 09:32:16.538192 [Calibration Summary] 1600 Mbps
2032 09:32:16.538307 CH 0, Rank 0
2033 09:32:16.541066 SW Impedance : PASS
2034 09:32:16.544576 DUTY Scan : NO K
2035 09:32:16.544681 ZQ Calibration : PASS
2036 09:32:16.547728 Jitter Meter : NO K
2037 09:32:16.551397 CBT Training : PASS
2038 09:32:16.551502 Write leveling : PASS
2039 09:32:16.554438 RX DQS gating : PASS
2040 09:32:16.557949 RX DQ/DQS(RDDQC) : PASS
2041 09:32:16.558045 TX DQ/DQS : PASS
2042 09:32:16.560867 RX DATLAT : PASS
2043 09:32:16.560991 RX DQ/DQS(Engine): PASS
2044 09:32:16.564759 TX OE : NO K
2045 09:32:16.564884 All Pass.
2046 09:32:16.564984
2047 09:32:16.567481 CH 0, Rank 1
2048 09:32:16.567599 SW Impedance : PASS
2049 09:32:16.571570 DUTY Scan : NO K
2050 09:32:16.574298 ZQ Calibration : PASS
2051 09:32:16.574428 Jitter Meter : NO K
2052 09:32:16.577600 CBT Training : PASS
2053 09:32:16.580957 Write leveling : PASS
2054 09:32:16.581064 RX DQS gating : PASS
2055 09:32:16.584297 RX DQ/DQS(RDDQC) : PASS
2056 09:32:16.587588 TX DQ/DQS : PASS
2057 09:32:16.587689 RX DATLAT : PASS
2058 09:32:16.591389 RX DQ/DQS(Engine): PASS
2059 09:32:16.594573 TX OE : NO K
2060 09:32:16.594692 All Pass.
2061 09:32:16.594765
2062 09:32:16.594875 CH 1, Rank 0
2063 09:32:16.597900 SW Impedance : PASS
2064 09:32:16.601260 DUTY Scan : NO K
2065 09:32:16.601383 ZQ Calibration : PASS
2066 09:32:16.604307 Jitter Meter : NO K
2067 09:32:16.607839 CBT Training : PASS
2068 09:32:16.607959 Write leveling : PASS
2069 09:32:16.611060 RX DQS gating : PASS
2070 09:32:16.611178 RX DQ/DQS(RDDQC) : PASS
2071 09:32:16.614317 TX DQ/DQS : PASS
2072 09:32:16.618203 RX DATLAT : PASS
2073 09:32:16.618310 RX DQ/DQS(Engine): PASS
2074 09:32:16.621411 TX OE : NO K
2075 09:32:16.621515 All Pass.
2076 09:32:16.621611
2077 09:32:16.624666 CH 1, Rank 1
2078 09:32:16.624770 SW Impedance : PASS
2079 09:32:16.628030 DUTY Scan : NO K
2080 09:32:16.631373 ZQ Calibration : PASS
2081 09:32:16.631476 Jitter Meter : NO K
2082 09:32:16.634736 CBT Training : PASS
2083 09:32:16.638097 Write leveling : PASS
2084 09:32:16.638212 RX DQS gating : PASS
2085 09:32:16.641472 RX DQ/DQS(RDDQC) : PASS
2086 09:32:16.644698 TX DQ/DQS : PASS
2087 09:32:16.644788 RX DATLAT : PASS
2088 09:32:16.647787 RX DQ/DQS(Engine): PASS
2089 09:32:16.647885 TX OE : NO K
2090 09:32:16.651708 All Pass.
2091 09:32:16.651816
2092 09:32:16.651911 DramC Write-DBI off
2093 09:32:16.654919 PER_BANK_REFRESH: Hybrid Mode
2094 09:32:16.658071 TX_TRACKING: ON
2095 09:32:16.661226 [GetDramInforAfterCalByMRR] Vendor 6.
2096 09:32:16.664512 [GetDramInforAfterCalByMRR] Revision 606.
2097 09:32:16.668193 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 09:32:16.668280 MR0 0x3b3b
2099 09:32:16.668367 MR8 0x5151
2100 09:32:16.674853 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 09:32:16.674938
2102 09:32:16.675046 MR0 0x3b3b
2103 09:32:16.675126 MR8 0x5151
2104 09:32:16.678387 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 09:32:16.678475
2106 09:32:16.688105 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 09:32:16.691494 [FAST_K] Save calibration result to emmc
2108 09:32:16.694835 [FAST_K] Save calibration result to emmc
2109 09:32:16.698051 dram_init: config_dvfs: 1
2110 09:32:16.701296 dramc_set_vcore_voltage set vcore to 662500
2111 09:32:16.704723 Read voltage for 1200, 2
2112 09:32:16.704813 Vio18 = 0
2113 09:32:16.704898 Vcore = 662500
2114 09:32:16.708018 Vdram = 0
2115 09:32:16.708103 Vddq = 0
2116 09:32:16.708196 Vmddr = 0
2117 09:32:16.715005 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 09:32:16.718195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 09:32:16.721789 MEM_TYPE=3, freq_sel=15
2120 09:32:16.725036 sv_algorithm_assistance_LP4_1600
2121 09:32:16.728407 ============ PULL DRAM RESETB DOWN ============
2122 09:32:16.731690 ========== PULL DRAM RESETB DOWN end =========
2123 09:32:16.738410 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 09:32:16.741873 ===================================
2125 09:32:16.741957 LPDDR4 DRAM CONFIGURATION
2126 09:32:16.745299 ===================================
2127 09:32:16.748665 EX_ROW_EN[0] = 0x0
2128 09:32:16.751994 EX_ROW_EN[1] = 0x0
2129 09:32:16.752072 LP4Y_EN = 0x0
2130 09:32:16.755304 WORK_FSP = 0x0
2131 09:32:16.755429 WL = 0x4
2132 09:32:16.758781 RL = 0x4
2133 09:32:16.758861 BL = 0x2
2134 09:32:16.761860 RPST = 0x0
2135 09:32:16.761944 RD_PRE = 0x0
2136 09:32:16.765143 WR_PRE = 0x1
2137 09:32:16.765233 WR_PST = 0x0
2138 09:32:16.768354 DBI_WR = 0x0
2139 09:32:16.768446 DBI_RD = 0x0
2140 09:32:16.771607 OTF = 0x1
2141 09:32:16.775012 ===================================
2142 09:32:16.778318 ===================================
2143 09:32:16.778442 ANA top config
2144 09:32:16.781622 ===================================
2145 09:32:16.785316 DLL_ASYNC_EN = 0
2146 09:32:16.788366 ALL_SLAVE_EN = 0
2147 09:32:16.788481 NEW_RANK_MODE = 1
2148 09:32:16.791857 DLL_IDLE_MODE = 1
2149 09:32:16.795086 LP45_APHY_COMB_EN = 1
2150 09:32:16.798361 TX_ODT_DIS = 1
2151 09:32:16.801651 NEW_8X_MODE = 1
2152 09:32:16.804913 ===================================
2153 09:32:16.808705 ===================================
2154 09:32:16.808789 data_rate = 2400
2155 09:32:16.812095 CKR = 1
2156 09:32:16.815334 DQ_P2S_RATIO = 8
2157 09:32:16.818636 ===================================
2158 09:32:16.821801 CA_P2S_RATIO = 8
2159 09:32:16.824939 DQ_CA_OPEN = 0
2160 09:32:16.828233 DQ_SEMI_OPEN = 0
2161 09:32:16.828312 CA_SEMI_OPEN = 0
2162 09:32:16.831732 CA_FULL_RATE = 0
2163 09:32:16.835449 DQ_CKDIV4_EN = 0
2164 09:32:16.838778 CA_CKDIV4_EN = 0
2165 09:32:16.842208 CA_PREDIV_EN = 0
2166 09:32:16.842287 PH8_DLY = 17
2167 09:32:16.845500 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 09:32:16.848268 DQ_AAMCK_DIV = 4
2169 09:32:16.851633 CA_AAMCK_DIV = 4
2170 09:32:16.854934 CA_ADMCK_DIV = 4
2171 09:32:16.858722 DQ_TRACK_CA_EN = 0
2172 09:32:16.862089 CA_PICK = 1200
2173 09:32:16.862167 CA_MCKIO = 1200
2174 09:32:16.865386 MCKIO_SEMI = 0
2175 09:32:16.868728 PLL_FREQ = 2366
2176 09:32:16.871878 DQ_UI_PI_RATIO = 32
2177 09:32:16.874966 CA_UI_PI_RATIO = 0
2178 09:32:16.878352 ===================================
2179 09:32:16.881539 ===================================
2180 09:32:16.884978 memory_type:LPDDR4
2181 09:32:16.885065 GP_NUM : 10
2182 09:32:16.888371 SRAM_EN : 1
2183 09:32:16.888461 MD32_EN : 0
2184 09:32:16.891815 ===================================
2185 09:32:16.895504 [ANA_INIT] >>>>>>>>>>>>>>
2186 09:32:16.898484 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 09:32:16.901661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 09:32:16.905069 ===================================
2189 09:32:16.908180 data_rate = 2400,PCW = 0X5b00
2190 09:32:16.911452 ===================================
2191 09:32:16.914830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 09:32:16.918215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 09:32:16.924917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 09:32:16.931441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 09:32:16.934893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 09:32:16.938186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 09:32:16.938270 [ANA_INIT] flow start
2198 09:32:16.941883 [ANA_INIT] PLL >>>>>>>>
2199 09:32:16.945339 [ANA_INIT] PLL <<<<<<<<
2200 09:32:16.945439 [ANA_INIT] MIDPI >>>>>>>>
2201 09:32:16.948348 [ANA_INIT] MIDPI <<<<<<<<
2202 09:32:16.951833 [ANA_INIT] DLL >>>>>>>>
2203 09:32:16.951931 [ANA_INIT] DLL <<<<<<<<
2204 09:32:16.955308 [ANA_INIT] flow end
2205 09:32:16.958730 ============ LP4 DIFF to SE enter ============
2206 09:32:16.961972 ============ LP4 DIFF to SE exit ============
2207 09:32:16.965249 [ANA_INIT] <<<<<<<<<<<<<
2208 09:32:16.968765 [Flow] Enable top DCM control >>>>>
2209 09:32:16.972009 [Flow] Enable top DCM control <<<<<
2210 09:32:16.975302 Enable DLL master slave shuffle
2211 09:32:16.981874 ==============================================================
2212 09:32:16.981976 Gating Mode config
2213 09:32:16.988918 ==============================================================
2214 09:32:16.989024 Config description:
2215 09:32:16.998797 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 09:32:17.005186 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 09:32:17.011713 SELPH_MODE 0: By rank 1: By Phase
2218 09:32:17.015046 ==============================================================
2219 09:32:17.018783 GAT_TRACK_EN = 1
2220 09:32:17.022040 RX_GATING_MODE = 2
2221 09:32:17.025418 RX_GATING_TRACK_MODE = 2
2222 09:32:17.028797 SELPH_MODE = 1
2223 09:32:17.031964 PICG_EARLY_EN = 1
2224 09:32:17.035290 VALID_LAT_VALUE = 1
2225 09:32:17.038570 ==============================================================
2226 09:32:17.041935 Enter into Gating configuration >>>>
2227 09:32:17.045251 Exit from Gating configuration <<<<
2228 09:32:17.048689 Enter into DVFS_PRE_config >>>>>
2229 09:32:17.062191 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 09:32:17.065087 Exit from DVFS_PRE_config <<<<<
2231 09:32:17.065177 Enter into PICG configuration >>>>
2232 09:32:17.068837 Exit from PICG configuration <<<<
2233 09:32:17.072229 [RX_INPUT] configuration >>>>>
2234 09:32:17.075657 [RX_INPUT] configuration <<<<<
2235 09:32:17.082302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 09:32:17.085495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 09:32:17.091889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 09:32:17.098901 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 09:32:17.105768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 09:32:17.112118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 09:32:17.115380 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 09:32:17.118697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 09:32:17.122047 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 09:32:17.128937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 09:32:17.132207 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 09:32:17.135530 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 09:32:17.138807 ===================================
2248 09:32:17.142291 LPDDR4 DRAM CONFIGURATION
2249 09:32:17.145663 ===================================
2250 09:32:17.145773 EX_ROW_EN[0] = 0x0
2251 09:32:17.149050 EX_ROW_EN[1] = 0x0
2252 09:32:17.149140 LP4Y_EN = 0x0
2253 09:32:17.152574 WORK_FSP = 0x0
2254 09:32:17.152659 WL = 0x4
2255 09:32:17.155936 RL = 0x4
2256 09:32:17.156034 BL = 0x2
2257 09:32:17.159148 RPST = 0x0
2258 09:32:17.162512 RD_PRE = 0x0
2259 09:32:17.162598 WR_PRE = 0x1
2260 09:32:17.165823 WR_PST = 0x0
2261 09:32:17.165948 DBI_WR = 0x0
2262 09:32:17.168984 DBI_RD = 0x0
2263 09:32:17.169077 OTF = 0x1
2264 09:32:17.172659 ===================================
2265 09:32:17.175695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 09:32:17.179245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 09:32:17.185868 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 09:32:17.189277 ===================================
2269 09:32:17.189374 LPDDR4 DRAM CONFIGURATION
2270 09:32:17.192712 ===================================
2271 09:32:17.196116 EX_ROW_EN[0] = 0x10
2272 09:32:17.199274 EX_ROW_EN[1] = 0x0
2273 09:32:17.199385 LP4Y_EN = 0x0
2274 09:32:17.202382 WORK_FSP = 0x0
2275 09:32:17.202504 WL = 0x4
2276 09:32:17.206007 RL = 0x4
2277 09:32:17.206101 BL = 0x2
2278 09:32:17.209060 RPST = 0x0
2279 09:32:17.209151 RD_PRE = 0x0
2280 09:32:17.212930 WR_PRE = 0x1
2281 09:32:17.213040 WR_PST = 0x0
2282 09:32:17.216137 DBI_WR = 0x0
2283 09:32:17.216223 DBI_RD = 0x0
2284 09:32:17.219187 OTF = 0x1
2285 09:32:17.222385 ===================================
2286 09:32:17.229053 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 09:32:17.229162 ==
2288 09:32:17.232377 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 09:32:17.235631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 09:32:17.235753 ==
2291 09:32:17.239339 [Duty_Offset_Calibration]
2292 09:32:17.239448 B0:2 B1:1 CA:1
2293 09:32:17.239546
2294 09:32:17.242343 [DutyScan_Calibration_Flow] k_type=0
2295 09:32:17.253135
2296 09:32:17.253267 ==CLK 0==
2297 09:32:17.256537 Final CLK duty delay cell = 0
2298 09:32:17.259885 [0] MAX Duty = 5187%(X100), DQS PI = 24
2299 09:32:17.263059 [0] MIN Duty = 4875%(X100), DQS PI = 0
2300 09:32:17.263148 [0] AVG Duty = 5031%(X100)
2301 09:32:17.263215
2302 09:32:17.266565 CH0 CLK Duty spec in!! Max-Min= 312%
2303 09:32:17.273214 [DutyScan_Calibration_Flow] ====Done====
2304 09:32:17.273312
2305 09:32:17.276317 [DutyScan_Calibration_Flow] k_type=1
2306 09:32:17.291091
2307 09:32:17.291227 ==DQS 0 ==
2308 09:32:17.294768 Final DQS duty delay cell = -4
2309 09:32:17.298222 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2310 09:32:17.301636 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2311 09:32:17.304227 [-4] AVG Duty = 4953%(X100)
2312 09:32:17.304329
2313 09:32:17.304396 ==DQS 1 ==
2314 09:32:17.307600 Final DQS duty delay cell = 0
2315 09:32:17.310877 [0] MAX Duty = 5156%(X100), DQS PI = 0
2316 09:32:17.314721 [0] MIN Duty = 5031%(X100), DQS PI = 34
2317 09:32:17.317807 [0] AVG Duty = 5093%(X100)
2318 09:32:17.317917
2319 09:32:17.320917 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2320 09:32:17.320998
2321 09:32:17.324546 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2322 09:32:17.327664 [DutyScan_Calibration_Flow] ====Done====
2323 09:32:17.327745
2324 09:32:17.331214 [DutyScan_Calibration_Flow] k_type=3
2325 09:32:17.348282
2326 09:32:17.348420 ==DQM 0 ==
2327 09:32:17.351244 Final DQM duty delay cell = 0
2328 09:32:17.354956 [0] MAX Duty = 5156%(X100), DQS PI = 30
2329 09:32:17.358291 [0] MIN Duty = 4906%(X100), DQS PI = 52
2330 09:32:17.361609 [0] AVG Duty = 5031%(X100)
2331 09:32:17.361714
2332 09:32:17.361808 ==DQM 1 ==
2333 09:32:17.364867 Final DQM duty delay cell = 0
2334 09:32:17.368138 [0] MAX Duty = 5124%(X100), DQS PI = 6
2335 09:32:17.371631 [0] MIN Duty = 5031%(X100), DQS PI = 36
2336 09:32:17.371721 [0] AVG Duty = 5077%(X100)
2337 09:32:17.375030
2338 09:32:17.378388 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2339 09:32:17.378503
2340 09:32:17.381670 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2341 09:32:17.385015 [DutyScan_Calibration_Flow] ====Done====
2342 09:32:17.385102
2343 09:32:17.387688 [DutyScan_Calibration_Flow] k_type=2
2344 09:32:17.404599
2345 09:32:17.404734 ==DQ 0 ==
2346 09:32:17.408242 Final DQ duty delay cell = 0
2347 09:32:17.411577 [0] MAX Duty = 5031%(X100), DQS PI = 26
2348 09:32:17.414839 [0] MIN Duty = 4844%(X100), DQS PI = 62
2349 09:32:17.414953 [0] AVG Duty = 4937%(X100)
2350 09:32:17.415054
2351 09:32:17.418233 ==DQ 1 ==
2352 09:32:17.421338 Final DQ duty delay cell = 0
2353 09:32:17.424877 [0] MAX Duty = 5093%(X100), DQS PI = 10
2354 09:32:17.428110 [0] MIN Duty = 4907%(X100), DQS PI = 36
2355 09:32:17.428195 [0] AVG Duty = 5000%(X100)
2356 09:32:17.428303
2357 09:32:17.431513 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2358 09:32:17.431622
2359 09:32:17.437878 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2360 09:32:17.441545 [DutyScan_Calibration_Flow] ====Done====
2361 09:32:17.441623 ==
2362 09:32:17.444333 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 09:32:17.448137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 09:32:17.448241 ==
2365 09:32:17.451520 [Duty_Offset_Calibration]
2366 09:32:17.451627 B0:1 B1:0 CA:0
2367 09:32:17.451735
2368 09:32:17.454818 [DutyScan_Calibration_Flow] k_type=0
2369 09:32:17.463715
2370 09:32:17.463867 ==CLK 0==
2371 09:32:17.467139 Final CLK duty delay cell = -4
2372 09:32:17.470423 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2373 09:32:17.474232 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2374 09:32:17.477606 [-4] AVG Duty = 4953%(X100)
2375 09:32:17.477717
2376 09:32:17.480915 CH1 CLK Duty spec in!! Max-Min= 93%
2377 09:32:17.484181 [DutyScan_Calibration_Flow] ====Done====
2378 09:32:17.484264
2379 09:32:17.486959 [DutyScan_Calibration_Flow] k_type=1
2380 09:32:17.503723
2381 09:32:17.503847 ==DQS 0 ==
2382 09:32:17.506859 Final DQS duty delay cell = 0
2383 09:32:17.510220 [0] MAX Duty = 5094%(X100), DQS PI = 24
2384 09:32:17.513444 [0] MIN Duty = 4844%(X100), DQS PI = 0
2385 09:32:17.513533 [0] AVG Duty = 4969%(X100)
2386 09:32:17.517198
2387 09:32:17.517282 ==DQS 1 ==
2388 09:32:17.520563 Final DQS duty delay cell = 0
2389 09:32:17.523843 [0] MAX Duty = 5218%(X100), DQS PI = 20
2390 09:32:17.527154 [0] MIN Duty = 4969%(X100), DQS PI = 8
2391 09:32:17.527267 [0] AVG Duty = 5093%(X100)
2392 09:32:17.527350
2393 09:32:17.533884 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2394 09:32:17.534016
2395 09:32:17.537298 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2396 09:32:17.540736 [DutyScan_Calibration_Flow] ====Done====
2397 09:32:17.540831
2398 09:32:17.543266 [DutyScan_Calibration_Flow] k_type=3
2399 09:32:17.560267
2400 09:32:17.560415 ==DQM 0 ==
2401 09:32:17.563297 Final DQM duty delay cell = 0
2402 09:32:17.566495 [0] MAX Duty = 5156%(X100), DQS PI = 6
2403 09:32:17.570233 [0] MIN Duty = 5031%(X100), DQS PI = 0
2404 09:32:17.570313 [0] AVG Duty = 5093%(X100)
2405 09:32:17.573525
2406 09:32:17.573603 ==DQM 1 ==
2407 09:32:17.577156 Final DQM duty delay cell = 0
2408 09:32:17.580110 [0] MAX Duty = 5031%(X100), DQS PI = 24
2409 09:32:17.583443 [0] MIN Duty = 4907%(X100), DQS PI = 36
2410 09:32:17.583555 [0] AVG Duty = 4969%(X100)
2411 09:32:17.583655
2412 09:32:17.590045 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2413 09:32:17.590198
2414 09:32:17.593571 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2415 09:32:17.596972 [DutyScan_Calibration_Flow] ====Done====
2416 09:32:17.597066
2417 09:32:17.600257 [DutyScan_Calibration_Flow] k_type=2
2418 09:32:17.615669
2419 09:32:17.615807 ==DQ 0 ==
2420 09:32:17.619028 Final DQ duty delay cell = -4
2421 09:32:17.622608 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2422 09:32:17.625799 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2423 09:32:17.629327 [-4] AVG Duty = 5000%(X100)
2424 09:32:17.629417
2425 09:32:17.629494 ==DQ 1 ==
2426 09:32:17.632589 Final DQ duty delay cell = 0
2427 09:32:17.635925 [0] MAX Duty = 5125%(X100), DQS PI = 20
2428 09:32:17.639368 [0] MIN Duty = 4938%(X100), DQS PI = 34
2429 09:32:17.639493 [0] AVG Duty = 5031%(X100)
2430 09:32:17.639593
2431 09:32:17.642656 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2432 09:32:17.645995
2433 09:32:17.649279 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2434 09:32:17.652668 [DutyScan_Calibration_Flow] ====Done====
2435 09:32:17.655999 nWR fixed to 30
2436 09:32:17.656097 [ModeRegInit_LP4] CH0 RK0
2437 09:32:17.659285 [ModeRegInit_LP4] CH0 RK1
2438 09:32:17.662502 [ModeRegInit_LP4] CH1 RK0
2439 09:32:17.662626 [ModeRegInit_LP4] CH1 RK1
2440 09:32:17.666334 match AC timing 7
2441 09:32:17.669500 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 09:32:17.672690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 09:32:17.679724 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 09:32:17.682942 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 09:32:17.689590 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 09:32:17.689738 ==
2447 09:32:17.692699 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 09:32:17.696586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 09:32:17.696697 ==
2450 09:32:17.702812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 09:32:17.706077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 09:32:17.716103 [CA 0] Center 39 (8~70) winsize 63
2453 09:32:17.719510 [CA 1] Center 39 (8~70) winsize 63
2454 09:32:17.722676 [CA 2] Center 35 (5~66) winsize 62
2455 09:32:17.726006 [CA 3] Center 34 (4~65) winsize 62
2456 09:32:17.729384 [CA 4] Center 33 (3~64) winsize 62
2457 09:32:17.732637 [CA 5] Center 32 (3~62) winsize 60
2458 09:32:17.732730
2459 09:32:17.735757 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2460 09:32:17.735850
2461 09:32:17.739366 [CATrainingPosCal] consider 1 rank data
2462 09:32:17.742997 u2DelayCellTimex100 = 270/100 ps
2463 09:32:17.746314 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 09:32:17.749650 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 09:32:17.755797 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2466 09:32:17.759207 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2467 09:32:17.762504 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2468 09:32:17.765910 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2469 09:32:17.766008
2470 09:32:17.769359 CA PerBit enable=1, Macro0, CA PI delay=32
2471 09:32:17.769439
2472 09:32:17.772666 [CBTSetCACLKResult] CA Dly = 32
2473 09:32:17.772741 CS Dly: 6 (0~37)
2474 09:32:17.772809 ==
2475 09:32:17.775938 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 09:32:17.782934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 09:32:17.783012 ==
2478 09:32:17.785916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 09:32:17.792721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 09:32:17.801980 [CA 0] Center 38 (8~69) winsize 62
2481 09:32:17.804983 [CA 1] Center 38 (8~69) winsize 62
2482 09:32:17.808236 [CA 2] Center 35 (5~66) winsize 62
2483 09:32:17.811613 [CA 3] Center 34 (4~65) winsize 62
2484 09:32:17.814910 [CA 4] Center 33 (3~64) winsize 62
2485 09:32:17.818256 [CA 5] Center 32 (3~62) winsize 60
2486 09:32:17.818342
2487 09:32:17.821507 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 09:32:17.821594
2489 09:32:17.824794 [CATrainingPosCal] consider 2 rank data
2490 09:32:17.828772 u2DelayCellTimex100 = 270/100 ps
2491 09:32:17.831535 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 09:32:17.834787 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 09:32:17.841592 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 09:32:17.845512 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 09:32:17.848627 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 09:32:17.852212 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 09:32:17.852333
2498 09:32:17.855403 CA PerBit enable=1, Macro0, CA PI delay=32
2499 09:32:17.855516
2500 09:32:17.858796 [CBTSetCACLKResult] CA Dly = 32
2501 09:32:17.858881 CS Dly: 6 (0~38)
2502 09:32:17.858948
2503 09:32:17.862078 ----->DramcWriteLeveling(PI) begin...
2504 09:32:17.865346 ==
2505 09:32:17.865429 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 09:32:17.871918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 09:32:17.872031 ==
2508 09:32:17.875275 Write leveling (Byte 0): 31 => 31
2509 09:32:17.878614 Write leveling (Byte 1): 29 => 29
2510 09:32:17.881915 DramcWriteLeveling(PI) end<-----
2511 09:32:17.882033
2512 09:32:17.882116 ==
2513 09:32:17.885195 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 09:32:17.888571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 09:32:17.888655 ==
2516 09:32:17.891887 [Gating] SW mode calibration
2517 09:32:17.898176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 09:32:17.901928 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 09:32:17.908621 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2520 09:32:17.911886 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2521 09:32:17.915343 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 09:32:17.921987 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 09:32:17.925190 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 09:32:17.928561 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 09:32:17.935160 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
2526 09:32:17.938621 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2527 09:32:17.942117 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2528 09:32:17.948854 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 09:32:17.952337 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 09:32:17.955607 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 09:32:17.958835 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 09:32:17.965358 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 09:32:17.968594 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2534 09:32:17.971957 1 0 28 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
2535 09:32:17.978550 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
2536 09:32:17.982570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 09:32:17.985819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 09:32:17.991941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 09:32:17.995216 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 09:32:17.998537 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 09:32:18.005724 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 09:32:18.009041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 09:32:18.012192 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 09:32:18.019106 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 09:32:18.022289 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 09:32:18.025577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 09:32:18.032183 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 09:32:18.035677 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 09:32:18.038653 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 09:32:18.042649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 09:32:18.049423 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 09:32:18.052838 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 09:32:18.055696 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 09:32:18.062337 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 09:32:18.065702 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:32:18.069095 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:32:18.076237 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 09:32:18.079277 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 09:32:18.082532 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 09:32:18.085931 Total UI for P1: 0, mck2ui 16
2561 09:32:18.089273 best dqsien dly found for B0: ( 1, 3, 26)
2562 09:32:18.092586 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 09:32:18.096129 Total UI for P1: 0, mck2ui 16
2564 09:32:18.099353 best dqsien dly found for B1: ( 1, 4, 0)
2565 09:32:18.102698 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2566 09:32:18.109384 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2567 09:32:18.109479
2568 09:32:18.112775 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2569 09:32:18.116167 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2570 09:32:18.119351 [Gating] SW calibration Done
2571 09:32:18.119460 ==
2572 09:32:18.122592 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 09:32:18.125868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 09:32:18.125985 ==
2575 09:32:18.126081 RX Vref Scan: 0
2576 09:32:18.126180
2577 09:32:18.129713 RX Vref 0 -> 0, step: 1
2578 09:32:18.129803
2579 09:32:18.132913 RX Delay -40 -> 252, step: 8
2580 09:32:18.136195 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2581 09:32:18.139183 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2582 09:32:18.146169 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2583 09:32:18.149744 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2584 09:32:18.153012 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2585 09:32:18.156414 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2586 09:32:18.159660 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2587 09:32:18.163023 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2588 09:32:18.169430 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2589 09:32:18.172697 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2590 09:32:18.176588 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2591 09:32:18.179219 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2592 09:32:18.182613 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2593 09:32:18.189620 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2594 09:32:18.192917 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2595 09:32:18.196269 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2596 09:32:18.196435 ==
2597 09:32:18.199576 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 09:32:18.203036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 09:32:18.203199 ==
2600 09:32:18.206277 DQS Delay:
2601 09:32:18.206388 DQS0 = 0, DQS1 = 0
2602 09:32:18.209660 DQM Delay:
2603 09:32:18.209802 DQM0 = 121, DQM1 = 114
2604 09:32:18.212965 DQ Delay:
2605 09:32:18.216256 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2606 09:32:18.219572 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2607 09:32:18.222892 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2608 09:32:18.226395 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2609 09:32:18.226535
2610 09:32:18.226662
2611 09:32:18.226786 ==
2612 09:32:18.229773 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 09:32:18.233133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 09:32:18.233270 ==
2615 09:32:18.233397
2616 09:32:18.233519
2617 09:32:18.236493 TX Vref Scan disable
2618 09:32:18.239668 == TX Byte 0 ==
2619 09:32:18.242888 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2620 09:32:18.246688 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2621 09:32:18.250066 == TX Byte 1 ==
2622 09:32:18.253289 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2623 09:32:18.256479 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2624 09:32:18.256618 ==
2625 09:32:18.260059 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 09:32:18.263344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 09:32:18.263461 ==
2628 09:32:18.276620 TX Vref=22, minBit 0, minWin=25, winSum=406
2629 09:32:18.279645 TX Vref=24, minBit 0, minWin=25, winSum=410
2630 09:32:18.283014 TX Vref=26, minBit 0, minWin=25, winSum=417
2631 09:32:18.286372 TX Vref=28, minBit 1, minWin=25, winSum=422
2632 09:32:18.289644 TX Vref=30, minBit 14, minWin=25, winSum=427
2633 09:32:18.293172 TX Vref=32, minBit 10, minWin=25, winSum=419
2634 09:32:18.299634 [TxChooseVref] Worse bit 14, Min win 25, Win sum 427, Final Vref 30
2635 09:32:18.299732
2636 09:32:18.302970 Final TX Range 1 Vref 30
2637 09:32:18.303050
2638 09:32:18.303116 ==
2639 09:32:18.306234 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 09:32:18.309478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 09:32:18.309585 ==
2642 09:32:18.312812
2643 09:32:18.312912
2644 09:32:18.313005 TX Vref Scan disable
2645 09:32:18.316011 == TX Byte 0 ==
2646 09:32:18.319313 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2647 09:32:18.323303 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2648 09:32:18.326569 == TX Byte 1 ==
2649 09:32:18.329563 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2650 09:32:18.332900 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2651 09:32:18.333011
2652 09:32:18.336263 [DATLAT]
2653 09:32:18.336367 Freq=1200, CH0 RK0
2654 09:32:18.336460
2655 09:32:18.339739 DATLAT Default: 0xd
2656 09:32:18.339842 0, 0xFFFF, sum = 0
2657 09:32:18.343041 1, 0xFFFF, sum = 0
2658 09:32:18.343151 2, 0xFFFF, sum = 0
2659 09:32:18.346200 3, 0xFFFF, sum = 0
2660 09:32:18.346277 4, 0xFFFF, sum = 0
2661 09:32:18.349500 5, 0xFFFF, sum = 0
2662 09:32:18.353258 6, 0xFFFF, sum = 0
2663 09:32:18.353355 7, 0xFFFF, sum = 0
2664 09:32:18.356323 8, 0xFFFF, sum = 0
2665 09:32:18.356434 9, 0xFFFF, sum = 0
2666 09:32:18.359861 10, 0xFFFF, sum = 0
2667 09:32:18.359962 11, 0xFFFF, sum = 0
2668 09:32:18.363021 12, 0x0, sum = 1
2669 09:32:18.363132 13, 0x0, sum = 2
2670 09:32:18.365987 14, 0x0, sum = 3
2671 09:32:18.366108 15, 0x0, sum = 4
2672 09:32:18.366206 best_step = 13
2673 09:32:18.366300
2674 09:32:18.369552 ==
2675 09:32:18.372733 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 09:32:18.376267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 09:32:18.376346 ==
2678 09:32:18.376413 RX Vref Scan: 1
2679 09:32:18.376506
2680 09:32:18.379586 Set Vref Range= 32 -> 127
2681 09:32:18.379700
2682 09:32:18.382788 RX Vref 32 -> 127, step: 1
2683 09:32:18.382885
2684 09:32:18.386064 RX Delay -13 -> 252, step: 4
2685 09:32:18.386172
2686 09:32:18.389497 Set Vref, RX VrefLevel [Byte0]: 32
2687 09:32:18.392853 [Byte1]: 32
2688 09:32:18.392962
2689 09:32:18.396071 Set Vref, RX VrefLevel [Byte0]: 33
2690 09:32:18.399998 [Byte1]: 33
2691 09:32:18.400083
2692 09:32:18.403053 Set Vref, RX VrefLevel [Byte0]: 34
2693 09:32:18.406696 [Byte1]: 34
2694 09:32:18.410576
2695 09:32:18.410683 Set Vref, RX VrefLevel [Byte0]: 35
2696 09:32:18.413831 [Byte1]: 35
2697 09:32:18.418609
2698 09:32:18.418684 Set Vref, RX VrefLevel [Byte0]: 36
2699 09:32:18.421763 [Byte1]: 36
2700 09:32:18.426503
2701 09:32:18.426606 Set Vref, RX VrefLevel [Byte0]: 37
2702 09:32:18.429298 [Byte1]: 37
2703 09:32:18.434498
2704 09:32:18.434601 Set Vref, RX VrefLevel [Byte0]: 38
2705 09:32:18.437685 [Byte1]: 38
2706 09:32:18.442319
2707 09:32:18.442423 Set Vref, RX VrefLevel [Byte0]: 39
2708 09:32:18.445771 [Byte1]: 39
2709 09:32:18.450377
2710 09:32:18.450494 Set Vref, RX VrefLevel [Byte0]: 40
2711 09:32:18.453093 [Byte1]: 40
2712 09:32:18.457577
2713 09:32:18.457653 Set Vref, RX VrefLevel [Byte0]: 41
2714 09:32:18.461133 [Byte1]: 41
2715 09:32:18.465657
2716 09:32:18.465731 Set Vref, RX VrefLevel [Byte0]: 42
2717 09:32:18.469139 [Byte1]: 42
2718 09:32:18.473785
2719 09:32:18.473889 Set Vref, RX VrefLevel [Byte0]: 43
2720 09:32:18.476926 [Byte1]: 43
2721 09:32:18.481676
2722 09:32:18.481755 Set Vref, RX VrefLevel [Byte0]: 44
2723 09:32:18.484893 [Byte1]: 44
2724 09:32:18.489291
2725 09:32:18.489368 Set Vref, RX VrefLevel [Byte0]: 45
2726 09:32:18.493023 [Byte1]: 45
2727 09:32:18.497431
2728 09:32:18.497512 Set Vref, RX VrefLevel [Byte0]: 46
2729 09:32:18.500841 [Byte1]: 46
2730 09:32:18.505277
2731 09:32:18.505387 Set Vref, RX VrefLevel [Byte0]: 47
2732 09:32:18.508625 [Byte1]: 47
2733 09:32:18.513000
2734 09:32:18.513077 Set Vref, RX VrefLevel [Byte0]: 48
2735 09:32:18.516187 [Byte1]: 48
2736 09:32:18.520712
2737 09:32:18.520789 Set Vref, RX VrefLevel [Byte0]: 49
2738 09:32:18.523980 [Byte1]: 49
2739 09:32:18.528728
2740 09:32:18.528808 Set Vref, RX VrefLevel [Byte0]: 50
2741 09:32:18.531983 [Byte1]: 50
2742 09:32:18.536758
2743 09:32:18.536837 Set Vref, RX VrefLevel [Byte0]: 51
2744 09:32:18.540051 [Byte1]: 51
2745 09:32:18.544658
2746 09:32:18.544737 Set Vref, RX VrefLevel [Byte0]: 52
2747 09:32:18.547896 [Byte1]: 52
2748 09:32:18.552556
2749 09:32:18.552630 Set Vref, RX VrefLevel [Byte0]: 53
2750 09:32:18.555923 [Byte1]: 53
2751 09:32:18.560649
2752 09:32:18.560784 Set Vref, RX VrefLevel [Byte0]: 54
2753 09:32:18.563951 [Byte1]: 54
2754 09:32:18.568347
2755 09:32:18.568472 Set Vref, RX VrefLevel [Byte0]: 55
2756 09:32:18.571499 [Byte1]: 55
2757 09:32:18.576353
2758 09:32:18.576471 Set Vref, RX VrefLevel [Byte0]: 56
2759 09:32:18.579770 [Byte1]: 56
2760 09:32:18.583779
2761 09:32:18.583879 Set Vref, RX VrefLevel [Byte0]: 57
2762 09:32:18.587379 [Byte1]: 57
2763 09:32:18.591718
2764 09:32:18.591826 Set Vref, RX VrefLevel [Byte0]: 58
2765 09:32:18.595308 [Byte1]: 58
2766 09:32:18.599793
2767 09:32:18.599869 Set Vref, RX VrefLevel [Byte0]: 59
2768 09:32:18.602930 [Byte1]: 59
2769 09:32:18.607667
2770 09:32:18.607787 Set Vref, RX VrefLevel [Byte0]: 60
2771 09:32:18.610852 [Byte1]: 60
2772 09:32:18.615560
2773 09:32:18.615681 Set Vref, RX VrefLevel [Byte0]: 61
2774 09:32:18.618683 [Byte1]: 61
2775 09:32:18.623342
2776 09:32:18.623468 Set Vref, RX VrefLevel [Byte0]: 62
2777 09:32:18.627004 [Byte1]: 62
2778 09:32:18.631561
2779 09:32:18.631684 Set Vref, RX VrefLevel [Byte0]: 63
2780 09:32:18.635015 [Byte1]: 63
2781 09:32:18.639090
2782 09:32:18.642321 Set Vref, RX VrefLevel [Byte0]: 64
2783 09:32:18.642437 [Byte1]: 64
2784 09:32:18.646986
2785 09:32:18.647067 Set Vref, RX VrefLevel [Byte0]: 65
2786 09:32:18.650417 [Byte1]: 65
2787 09:32:18.655121
2788 09:32:18.655223 Set Vref, RX VrefLevel [Byte0]: 66
2789 09:32:18.658647 [Byte1]: 66
2790 09:32:18.662806
2791 09:32:18.662908 Set Vref, RX VrefLevel [Byte0]: 67
2792 09:32:18.666186 [Byte1]: 67
2793 09:32:18.671034
2794 09:32:18.671141 Set Vref, RX VrefLevel [Byte0]: 68
2795 09:32:18.673821 [Byte1]: 68
2796 09:32:18.678858
2797 09:32:18.678975 Set Vref, RX VrefLevel [Byte0]: 69
2798 09:32:18.682057 [Byte1]: 69
2799 09:32:18.686598
2800 09:32:18.686711 Set Vref, RX VrefLevel [Byte0]: 70
2801 09:32:18.689988 [Byte1]: 70
2802 09:32:18.694588
2803 09:32:18.694704 Final RX Vref Byte 0 = 55 to rank0
2804 09:32:18.697772 Final RX Vref Byte 1 = 47 to rank0
2805 09:32:18.701293 Final RX Vref Byte 0 = 55 to rank1
2806 09:32:18.704584 Final RX Vref Byte 1 = 47 to rank1==
2807 09:32:18.707882 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 09:32:18.711111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 09:32:18.714704 ==
2810 09:32:18.714804 DQS Delay:
2811 09:32:18.714897 DQS0 = 0, DQS1 = 0
2812 09:32:18.717806 DQM Delay:
2813 09:32:18.717907 DQM0 = 120, DQM1 = 110
2814 09:32:18.721279 DQ Delay:
2815 09:32:18.724865 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2816 09:32:18.728476 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2817 09:32:18.731606 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
2818 09:32:18.735104 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2819 09:32:18.735223
2820 09:32:18.735321
2821 09:32:18.741251 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2822 09:32:18.745065 CH0 RK0: MR19=404, MR18=140D
2823 09:32:18.751524 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2824 09:32:18.751631
2825 09:32:18.754913 ----->DramcWriteLeveling(PI) begin...
2826 09:32:18.754997 ==
2827 09:32:18.758322 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 09:32:18.761729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 09:32:18.761834 ==
2830 09:32:18.765240 Write leveling (Byte 0): 32 => 32
2831 09:32:18.768674 Write leveling (Byte 1): 29 => 29
2832 09:32:18.772034 DramcWriteLeveling(PI) end<-----
2833 09:32:18.772144
2834 09:32:18.772238 ==
2835 09:32:18.774775 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 09:32:18.778111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 09:32:18.781521 ==
2838 09:32:18.781633 [Gating] SW mode calibration
2839 09:32:18.788250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 09:32:18.795213 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 09:32:18.798241 0 15 0 | B1->B0 | 3232 2e2d | 0 1 | (0 0) (0 0)
2842 09:32:18.805027 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 09:32:18.808653 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 09:32:18.811909 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 09:32:18.818539 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 09:32:18.821968 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 09:32:18.825194 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2848 09:32:18.832228 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 1)
2849 09:32:18.835214 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2850 09:32:18.838819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 09:32:18.841997 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 09:32:18.848778 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 09:32:18.851658 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 09:32:18.855048 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 09:32:18.861624 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
2856 09:32:18.865004 1 0 28 | B1->B0 | 3e3e 3f3f | 0 1 | (0 0) (0 0)
2857 09:32:18.868420 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2858 09:32:18.875265 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 09:32:18.878780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 09:32:18.882058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 09:32:18.888743 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 09:32:18.892137 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 09:32:18.895475 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 09:32:18.901980 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 09:32:18.905336 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 09:32:18.908630 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 09:32:18.911740 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 09:32:18.919000 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 09:32:18.922269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 09:32:18.925754 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 09:32:18.931927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 09:32:18.935820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 09:32:18.939151 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 09:32:18.945665 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 09:32:18.948672 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 09:32:18.952085 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 09:32:18.958869 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:32:18.961915 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:32:18.965751 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:32:18.972091 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2881 09:32:18.975680 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2882 09:32:18.978623 Total UI for P1: 0, mck2ui 16
2883 09:32:18.982143 best dqsien dly found for B1: ( 1, 3, 28)
2884 09:32:18.985438 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 09:32:18.988941 Total UI for P1: 0, mck2ui 16
2886 09:32:18.992309 best dqsien dly found for B0: ( 1, 3, 30)
2887 09:32:18.995669 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2888 09:32:18.999105 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2889 09:32:18.999191
2890 09:32:19.002292 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2891 09:32:19.005650 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2892 09:32:19.008876 [Gating] SW calibration Done
2893 09:32:19.008960 ==
2894 09:32:19.012120 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 09:32:19.019372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 09:32:19.019454 ==
2897 09:32:19.019524 RX Vref Scan: 0
2898 09:32:19.019587
2899 09:32:19.022447 RX Vref 0 -> 0, step: 1
2900 09:32:19.022519
2901 09:32:19.025397 RX Delay -40 -> 252, step: 8
2902 09:32:19.028699 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2903 09:32:19.032398 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2904 09:32:19.035724 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2905 09:32:19.038843 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2906 09:32:19.045601 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2907 09:32:19.048815 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2908 09:32:19.052140 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2909 09:32:19.055790 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2910 09:32:19.059098 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2911 09:32:19.065719 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2912 09:32:19.068943 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2913 09:32:19.072243 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2914 09:32:19.075384 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2915 09:32:19.078975 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2916 09:32:19.085555 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2917 09:32:19.088723 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2918 09:32:19.088849 ==
2919 09:32:19.092356 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 09:32:19.095599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 09:32:19.095697 ==
2922 09:32:19.099071 DQS Delay:
2923 09:32:19.099191 DQS0 = 0, DQS1 = 0
2924 09:32:19.099301 DQM Delay:
2925 09:32:19.102666 DQM0 = 122, DQM1 = 112
2926 09:32:19.102771 DQ Delay:
2927 09:32:19.105822 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2928 09:32:19.108673 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2929 09:32:19.112034 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2930 09:32:19.119216 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2931 09:32:19.119322
2932 09:32:19.119431
2933 09:32:19.119522 ==
2934 09:32:19.122663 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 09:32:19.125529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 09:32:19.125615 ==
2937 09:32:19.125681
2938 09:32:19.125743
2939 09:32:19.129046 TX Vref Scan disable
2940 09:32:19.129157 == TX Byte 0 ==
2941 09:32:19.135501 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2942 09:32:19.139092 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2943 09:32:19.139178 == TX Byte 1 ==
2944 09:32:19.145790 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2945 09:32:19.148848 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2946 09:32:19.148957 ==
2947 09:32:19.152563 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 09:32:19.155855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 09:32:19.155934 ==
2950 09:32:19.168429 TX Vref=22, minBit 1, minWin=25, winSum=410
2951 09:32:19.171896 TX Vref=24, minBit 3, minWin=25, winSum=415
2952 09:32:19.175254 TX Vref=26, minBit 3, minWin=25, winSum=420
2953 09:32:19.178432 TX Vref=28, minBit 1, minWin=26, winSum=424
2954 09:32:19.181601 TX Vref=30, minBit 0, minWin=26, winSum=424
2955 09:32:19.184938 TX Vref=32, minBit 10, minWin=25, winSum=418
2956 09:32:19.191620 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 28
2957 09:32:19.191717
2958 09:32:19.195002 Final TX Range 1 Vref 28
2959 09:32:19.195120
2960 09:32:19.195223 ==
2961 09:32:19.198892 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 09:32:19.201968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 09:32:19.202068 ==
2964 09:32:19.202161
2965 09:32:19.202248
2966 09:32:19.205036 TX Vref Scan disable
2967 09:32:19.208815 == TX Byte 0 ==
2968 09:32:19.212099 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2969 09:32:19.215535 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2970 09:32:19.218909 == TX Byte 1 ==
2971 09:32:19.222048 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2972 09:32:19.225377 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2973 09:32:19.225470
2974 09:32:19.228820 [DATLAT]
2975 09:32:19.228925 Freq=1200, CH0 RK1
2976 09:32:19.229018
2977 09:32:19.232315 DATLAT Default: 0xd
2978 09:32:19.232393 0, 0xFFFF, sum = 0
2979 09:32:19.235607 1, 0xFFFF, sum = 0
2980 09:32:19.235701 2, 0xFFFF, sum = 0
2981 09:32:19.239142 3, 0xFFFF, sum = 0
2982 09:32:19.239214 4, 0xFFFF, sum = 0
2983 09:32:19.242418 5, 0xFFFF, sum = 0
2984 09:32:19.242501 6, 0xFFFF, sum = 0
2985 09:32:19.245875 7, 0xFFFF, sum = 0
2986 09:32:19.245985 8, 0xFFFF, sum = 0
2987 09:32:19.248676 9, 0xFFFF, sum = 0
2988 09:32:19.248782 10, 0xFFFF, sum = 0
2989 09:32:19.252518 11, 0xFFFF, sum = 0
2990 09:32:19.252595 12, 0x0, sum = 1
2991 09:32:19.255384 13, 0x0, sum = 2
2992 09:32:19.255485 14, 0x0, sum = 3
2993 09:32:19.258765 15, 0x0, sum = 4
2994 09:32:19.258846 best_step = 13
2995 09:32:19.258909
2996 09:32:19.258968 ==
2997 09:32:19.262244 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 09:32:19.269084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 09:32:19.269202 ==
3000 09:32:19.269298 RX Vref Scan: 0
3001 09:32:19.269395
3002 09:32:19.272384 RX Vref 0 -> 0, step: 1
3003 09:32:19.272463
3004 09:32:19.275468 RX Delay -13 -> 252, step: 4
3005 09:32:19.278843 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3006 09:32:19.282601 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3007 09:32:19.285659 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3008 09:32:19.292344 iDelay=195, Bit 3, Center 120 (55 ~ 186) 132
3009 09:32:19.295676 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3010 09:32:19.298994 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3011 09:32:19.302386 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3012 09:32:19.305832 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3013 09:32:19.312370 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3014 09:32:19.315548 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3015 09:32:19.319071 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3016 09:32:19.322553 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3017 09:32:19.325910 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3018 09:32:19.332328 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3019 09:32:19.335609 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3020 09:32:19.338963 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3021 09:32:19.339071 ==
3022 09:32:19.342469 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 09:32:19.345769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 09:32:19.345862 ==
3025 09:32:19.349182 DQS Delay:
3026 09:32:19.349292 DQS0 = 0, DQS1 = 0
3027 09:32:19.352507 DQM Delay:
3028 09:32:19.352583 DQM0 = 121, DQM1 = 109
3029 09:32:19.352660 DQ Delay:
3030 09:32:19.359392 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
3031 09:32:19.362740 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3032 09:32:19.365835 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3033 09:32:19.369249 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3034 09:32:19.369331
3035 09:32:19.369395
3036 09:32:19.375570 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3037 09:32:19.378966 CH0 RK1: MR19=403, MR18=DEE
3038 09:32:19.385817 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3039 09:32:19.389305 [RxdqsGatingPostProcess] freq 1200
3040 09:32:19.392518 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3041 09:32:19.395704 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 09:32:19.399425 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 09:32:19.402785 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 09:32:19.406048 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 09:32:19.409440 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 09:32:19.412765 best DQS1 dly(2T, 0.5T) = (0, 11)
3047 09:32:19.416184 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 09:32:19.419398 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3049 09:32:19.422830 Pre-setting of DQS Precalculation
3050 09:32:19.426235 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3051 09:32:19.426353 ==
3052 09:32:19.429435 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 09:32:19.435851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 09:32:19.435963 ==
3055 09:32:19.439540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3056 09:32:19.445985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3057 09:32:19.454863 [CA 0] Center 37 (7~68) winsize 62
3058 09:32:19.457602 [CA 1] Center 37 (7~68) winsize 62
3059 09:32:19.460977 [CA 2] Center 35 (5~65) winsize 61
3060 09:32:19.464359 [CA 3] Center 34 (4~64) winsize 61
3061 09:32:19.467614 [CA 4] Center 34 (4~64) winsize 61
3062 09:32:19.471512 [CA 5] Center 33 (3~63) winsize 61
3063 09:32:19.471618
3064 09:32:19.474606 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3065 09:32:19.474710
3066 09:32:19.478151 [CATrainingPosCal] consider 1 rank data
3067 09:32:19.480975 u2DelayCellTimex100 = 270/100 ps
3068 09:32:19.484688 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 09:32:19.487977 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 09:32:19.494896 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3071 09:32:19.498129 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 09:32:19.501192 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3073 09:32:19.504926 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3074 09:32:19.505035
3075 09:32:19.508095 CA PerBit enable=1, Macro0, CA PI delay=33
3076 09:32:19.508199
3077 09:32:19.511747 [CBTSetCACLKResult] CA Dly = 33
3078 09:32:19.511853 CS Dly: 8 (0~39)
3079 09:32:19.511950 ==
3080 09:32:19.515005 Dram Type= 6, Freq= 0, CH_1, rank 1
3081 09:32:19.521163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 09:32:19.521282 ==
3083 09:32:19.524554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 09:32:19.531288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 09:32:19.539988 [CA 0] Center 37 (7~68) winsize 62
3086 09:32:19.543588 [CA 1] Center 38 (8~68) winsize 61
3087 09:32:19.546839 [CA 2] Center 35 (5~65) winsize 61
3088 09:32:19.550042 [CA 3] Center 34 (4~64) winsize 61
3089 09:32:19.553204 [CA 4] Center 34 (4~65) winsize 62
3090 09:32:19.557069 [CA 5] Center 34 (4~64) winsize 61
3091 09:32:19.557148
3092 09:32:19.560235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3093 09:32:19.560314
3094 09:32:19.563258 [CATrainingPosCal] consider 2 rank data
3095 09:32:19.567207 u2DelayCellTimex100 = 270/100 ps
3096 09:32:19.569951 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 09:32:19.573371 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3098 09:32:19.580188 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3099 09:32:19.583393 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 09:32:19.587124 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 09:32:19.590146 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3102 09:32:19.590312
3103 09:32:19.593593 CA PerBit enable=1, Macro0, CA PI delay=33
3104 09:32:19.593726
3105 09:32:19.597119 [CBTSetCACLKResult] CA Dly = 33
3106 09:32:19.597232 CS Dly: 8 (0~40)
3107 09:32:19.597329
3108 09:32:19.600236 ----->DramcWriteLeveling(PI) begin...
3109 09:32:19.600346 ==
3110 09:32:19.603282 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 09:32:19.610522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 09:32:19.610643 ==
3113 09:32:19.613818 Write leveling (Byte 0): 25 => 25
3114 09:32:19.617024 Write leveling (Byte 1): 28 => 28
3115 09:32:19.617138 DramcWriteLeveling(PI) end<-----
3116 09:32:19.620092
3117 09:32:19.620189 ==
3118 09:32:19.625644 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 09:32:19.627209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 09:32:19.627319 ==
3121 09:32:19.630564 [Gating] SW mode calibration
3122 09:32:19.637518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3123 09:32:19.640134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3124 09:32:19.646765 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 09:32:19.650651 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 09:32:19.654045 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 09:32:19.660828 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 09:32:19.664159 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 09:32:19.667370 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 09:32:19.674198 0 15 24 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
3131 09:32:19.677850 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3132 09:32:19.680557 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 09:32:19.683944 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 09:32:19.690668 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 09:32:19.693987 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 09:32:19.697187 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 09:32:19.704034 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 09:32:19.707509 1 0 24 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
3139 09:32:19.710602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 09:32:19.717721 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 09:32:19.720752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 09:32:19.724402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 09:32:19.730811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 09:32:19.734304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 09:32:19.737539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 09:32:19.744445 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 09:32:19.747610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 09:32:19.751085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 09:32:19.757645 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 09:32:19.760910 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 09:32:19.764437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 09:32:19.770956 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 09:32:19.773707 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 09:32:19.777635 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 09:32:19.780905 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 09:32:19.787555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 09:32:19.790703 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 09:32:19.794214 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 09:32:19.800762 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 09:32:19.804214 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:32:19.807439 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 09:32:19.814236 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3163 09:32:19.817690 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 09:32:19.820789 Total UI for P1: 0, mck2ui 16
3165 09:32:19.824036 best dqsien dly found for B0: ( 1, 3, 24)
3166 09:32:19.827262 Total UI for P1: 0, mck2ui 16
3167 09:32:19.830945 best dqsien dly found for B1: ( 1, 3, 26)
3168 09:32:19.834096 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3169 09:32:19.837359 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3170 09:32:19.837450
3171 09:32:19.840553 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3172 09:32:19.844204 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 09:32:19.847463 [Gating] SW calibration Done
3174 09:32:19.847579 ==
3175 09:32:19.850557 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 09:32:19.854505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 09:32:19.854589 ==
3178 09:32:19.857163 RX Vref Scan: 0
3179 09:32:19.857239
3180 09:32:19.860646 RX Vref 0 -> 0, step: 1
3181 09:32:19.860732
3182 09:32:19.860802 RX Delay -40 -> 252, step: 8
3183 09:32:19.867232 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3184 09:32:19.870620 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3185 09:32:19.873929 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3186 09:32:19.877230 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3187 09:32:19.881162 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3188 09:32:19.887882 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3189 09:32:19.890479 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3190 09:32:19.894386 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3191 09:32:19.897582 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3192 09:32:19.901323 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3193 09:32:19.907590 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3194 09:32:19.910993 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3195 09:32:19.914330 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3196 09:32:19.917671 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3197 09:32:19.920735 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3198 09:32:19.928176 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3199 09:32:19.928268 ==
3200 09:32:19.931342 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 09:32:19.934028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 09:32:19.934110 ==
3203 09:32:19.934194 DQS Delay:
3204 09:32:19.937895 DQS0 = 0, DQS1 = 0
3205 09:32:19.937986 DQM Delay:
3206 09:32:19.940945 DQM0 = 120, DQM1 = 116
3207 09:32:19.941053 DQ Delay:
3208 09:32:19.944067 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3209 09:32:19.947878 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3210 09:32:19.951048 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3211 09:32:19.954208 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3212 09:32:19.954287
3213 09:32:19.954355
3214 09:32:19.958091 ==
3215 09:32:19.960811 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 09:32:19.964655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 09:32:19.964739 ==
3218 09:32:19.964805
3219 09:32:19.964880
3220 09:32:19.967875 TX Vref Scan disable
3221 09:32:19.967960 == TX Byte 0 ==
3222 09:32:19.971375 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3223 09:32:19.977449 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3224 09:32:19.977532 == TX Byte 1 ==
3225 09:32:19.981338 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3226 09:32:19.987997 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3227 09:32:19.988081 ==
3228 09:32:19.991310 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 09:32:19.994012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 09:32:19.994092 ==
3231 09:32:20.006023 TX Vref=22, minBit 9, minWin=24, winSum=411
3232 09:32:20.009754 TX Vref=24, minBit 10, minWin=25, winSum=422
3233 09:32:20.012922 TX Vref=26, minBit 10, minWin=25, winSum=426
3234 09:32:20.015976 TX Vref=28, minBit 2, minWin=26, winSum=430
3235 09:32:20.019777 TX Vref=30, minBit 2, minWin=26, winSum=429
3236 09:32:20.026322 TX Vref=32, minBit 2, minWin=26, winSum=428
3237 09:32:20.029563 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 28
3238 09:32:20.029648
3239 09:32:20.033279 Final TX Range 1 Vref 28
3240 09:32:20.033363
3241 09:32:20.033428 ==
3242 09:32:20.036254 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 09:32:20.039457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 09:32:20.039575 ==
3245 09:32:20.039675
3246 09:32:20.042799
3247 09:32:20.042881 TX Vref Scan disable
3248 09:32:20.046582 == TX Byte 0 ==
3249 09:32:20.049629 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3250 09:32:20.052655 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3251 09:32:20.056346 == TX Byte 1 ==
3252 09:32:20.059421 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3253 09:32:20.063072 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3254 09:32:20.063152
3255 09:32:20.066296 [DATLAT]
3256 09:32:20.066372 Freq=1200, CH1 RK0
3257 09:32:20.066443
3258 09:32:20.069637 DATLAT Default: 0xd
3259 09:32:20.069731 0, 0xFFFF, sum = 0
3260 09:32:20.072870 1, 0xFFFF, sum = 0
3261 09:32:20.072968 2, 0xFFFF, sum = 0
3262 09:32:20.076001 3, 0xFFFF, sum = 0
3263 09:32:20.076081 4, 0xFFFF, sum = 0
3264 09:32:20.079876 5, 0xFFFF, sum = 0
3265 09:32:20.079966 6, 0xFFFF, sum = 0
3266 09:32:20.083069 7, 0xFFFF, sum = 0
3267 09:32:20.086556 8, 0xFFFF, sum = 0
3268 09:32:20.086650 9, 0xFFFF, sum = 0
3269 09:32:20.089787 10, 0xFFFF, sum = 0
3270 09:32:20.089885 11, 0xFFFF, sum = 0
3271 09:32:20.092585 12, 0x0, sum = 1
3272 09:32:20.092670 13, 0x0, sum = 2
3273 09:32:20.096411 14, 0x0, sum = 3
3274 09:32:20.096518 15, 0x0, sum = 4
3275 09:32:20.096586 best_step = 13
3276 09:32:20.096647
3277 09:32:20.099815 ==
3278 09:32:20.103164 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 09:32:20.105809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 09:32:20.105900 ==
3281 09:32:20.105974 RX Vref Scan: 1
3282 09:32:20.106048
3283 09:32:20.109152 Set Vref Range= 32 -> 127
3284 09:32:20.109229
3285 09:32:20.112563 RX Vref 32 -> 127, step: 1
3286 09:32:20.112649
3287 09:32:20.115894 RX Delay -5 -> 252, step: 4
3288 09:32:20.115985
3289 09:32:20.119261 Set Vref, RX VrefLevel [Byte0]: 32
3290 09:32:20.122513 [Byte1]: 32
3291 09:32:20.122596
3292 09:32:20.126173 Set Vref, RX VrefLevel [Byte0]: 33
3293 09:32:20.129147 [Byte1]: 33
3294 09:32:20.129251
3295 09:32:20.132398 Set Vref, RX VrefLevel [Byte0]: 34
3296 09:32:20.136326 [Byte1]: 34
3297 09:32:20.140313
3298 09:32:20.140395 Set Vref, RX VrefLevel [Byte0]: 35
3299 09:32:20.143499 [Byte1]: 35
3300 09:32:20.147845
3301 09:32:20.147931 Set Vref, RX VrefLevel [Byte0]: 36
3302 09:32:20.151307 [Byte1]: 36
3303 09:32:20.156496
3304 09:32:20.156591 Set Vref, RX VrefLevel [Byte0]: 37
3305 09:32:20.159001 [Byte1]: 37
3306 09:32:20.163584
3307 09:32:20.163680 Set Vref, RX VrefLevel [Byte0]: 38
3308 09:32:20.166726 [Byte1]: 38
3309 09:32:20.171584
3310 09:32:20.171677 Set Vref, RX VrefLevel [Byte0]: 39
3311 09:32:20.175039 [Byte1]: 39
3312 09:32:20.179227
3313 09:32:20.179316 Set Vref, RX VrefLevel [Byte0]: 40
3314 09:32:20.182332 [Byte1]: 40
3315 09:32:20.187630
3316 09:32:20.187725 Set Vref, RX VrefLevel [Byte0]: 41
3317 09:32:20.190674 [Byte1]: 41
3318 09:32:20.195080
3319 09:32:20.195168 Set Vref, RX VrefLevel [Byte0]: 42
3320 09:32:20.198363 [Byte1]: 42
3321 09:32:20.203220
3322 09:32:20.203323 Set Vref, RX VrefLevel [Byte0]: 43
3323 09:32:20.206602 [Byte1]: 43
3324 09:32:20.210640
3325 09:32:20.210744 Set Vref, RX VrefLevel [Byte0]: 44
3326 09:32:20.214067 [Byte1]: 44
3327 09:32:20.218806
3328 09:32:20.218882 Set Vref, RX VrefLevel [Byte0]: 45
3329 09:32:20.221661 [Byte1]: 45
3330 09:32:20.226548
3331 09:32:20.226657 Set Vref, RX VrefLevel [Byte0]: 46
3332 09:32:20.229939 [Byte1]: 46
3333 09:32:20.234546
3334 09:32:20.234667 Set Vref, RX VrefLevel [Byte0]: 47
3335 09:32:20.237754 [Byte1]: 47
3336 09:32:20.242320
3337 09:32:20.242396 Set Vref, RX VrefLevel [Byte0]: 48
3338 09:32:20.245249 [Byte1]: 48
3339 09:32:20.249897
3340 09:32:20.249996 Set Vref, RX VrefLevel [Byte0]: 49
3341 09:32:20.253518 [Byte1]: 49
3342 09:32:20.258059
3343 09:32:20.258173 Set Vref, RX VrefLevel [Byte0]: 50
3344 09:32:20.261400 [Byte1]: 50
3345 09:32:20.265891
3346 09:32:20.265985 Set Vref, RX VrefLevel [Byte0]: 51
3347 09:32:20.268763 [Byte1]: 51
3348 09:32:20.273462
3349 09:32:20.273549 Set Vref, RX VrefLevel [Byte0]: 52
3350 09:32:20.276743 [Byte1]: 52
3351 09:32:20.281141
3352 09:32:20.281250 Set Vref, RX VrefLevel [Byte0]: 53
3353 09:32:20.284865 [Byte1]: 53
3354 09:32:20.289143
3355 09:32:20.289261 Set Vref, RX VrefLevel [Byte0]: 54
3356 09:32:20.292842 [Byte1]: 54
3357 09:32:20.297354
3358 09:32:20.297484 Set Vref, RX VrefLevel [Byte0]: 55
3359 09:32:20.300422 [Byte1]: 55
3360 09:32:20.304986
3361 09:32:20.305077 Set Vref, RX VrefLevel [Byte0]: 56
3362 09:32:20.308305 [Byte1]: 56
3363 09:32:20.313083
3364 09:32:20.313170 Set Vref, RX VrefLevel [Byte0]: 57
3365 09:32:20.315839 [Byte1]: 57
3366 09:32:20.320579
3367 09:32:20.320691 Set Vref, RX VrefLevel [Byte0]: 58
3368 09:32:20.324087 [Byte1]: 58
3369 09:32:20.328711
3370 09:32:20.328800 Set Vref, RX VrefLevel [Byte0]: 59
3371 09:32:20.331989 [Byte1]: 59
3372 09:32:20.336194
3373 09:32:20.336292 Set Vref, RX VrefLevel [Byte0]: 60
3374 09:32:20.339527 [Byte1]: 60
3375 09:32:20.344351
3376 09:32:20.344438 Set Vref, RX VrefLevel [Byte0]: 61
3377 09:32:20.347616 [Byte1]: 61
3378 09:32:20.352000
3379 09:32:20.352086 Set Vref, RX VrefLevel [Byte0]: 62
3380 09:32:20.355417 [Byte1]: 62
3381 09:32:20.360464
3382 09:32:20.360573 Set Vref, RX VrefLevel [Byte0]: 63
3383 09:32:20.363295 [Byte1]: 63
3384 09:32:20.367860
3385 09:32:20.367941 Set Vref, RX VrefLevel [Byte0]: 64
3386 09:32:20.371427 [Byte1]: 64
3387 09:32:20.375766
3388 09:32:20.375845 Set Vref, RX VrefLevel [Byte0]: 65
3389 09:32:20.378862 [Byte1]: 65
3390 09:32:20.383429
3391 09:32:20.383534 Set Vref, RX VrefLevel [Byte0]: 66
3392 09:32:20.386881 [Byte1]: 66
3393 09:32:20.391371
3394 09:32:20.391451 Set Vref, RX VrefLevel [Byte0]: 67
3395 09:32:20.394567 [Byte1]: 67
3396 09:32:20.399355
3397 09:32:20.399438 Final RX Vref Byte 0 = 53 to rank0
3398 09:32:20.402573 Final RX Vref Byte 1 = 53 to rank0
3399 09:32:20.405673 Final RX Vref Byte 0 = 53 to rank1
3400 09:32:20.409397 Final RX Vref Byte 1 = 53 to rank1==
3401 09:32:20.412738 Dram Type= 6, Freq= 0, CH_1, rank 0
3402 09:32:20.415977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3403 09:32:20.419238 ==
3404 09:32:20.419327 DQS Delay:
3405 09:32:20.419429 DQS0 = 0, DQS1 = 0
3406 09:32:20.422609 DQM Delay:
3407 09:32:20.422691 DQM0 = 120, DQM1 = 117
3408 09:32:20.426153 DQ Delay:
3409 09:32:20.429317 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3410 09:32:20.432829 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3411 09:32:20.436211 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3412 09:32:20.439743 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3413 09:32:20.439828
3414 09:32:20.439895
3415 09:32:20.445720 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3416 09:32:20.449150 CH1 RK0: MR19=404, MR18=13
3417 09:32:20.456018 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3418 09:32:20.456107
3419 09:32:20.459410 ----->DramcWriteLeveling(PI) begin...
3420 09:32:20.459488 ==
3421 09:32:20.462761 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 09:32:20.465677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 09:32:20.465756 ==
3424 09:32:20.469225 Write leveling (Byte 0): 27 => 27
3425 09:32:20.472543 Write leveling (Byte 1): 29 => 29
3426 09:32:20.475744 DramcWriteLeveling(PI) end<-----
3427 09:32:20.475855
3428 09:32:20.475963 ==
3429 09:32:20.479241 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 09:32:20.482763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 09:32:20.482846 ==
3432 09:32:20.486193 [Gating] SW mode calibration
3433 09:32:20.492959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3434 09:32:20.499757 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3435 09:32:20.503164 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 09:32:20.509386 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 09:32:20.512634 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 09:32:20.516445 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 09:32:20.522555 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 09:32:20.526625 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3441 09:32:20.529775 0 15 24 | B1->B0 | 2424 3232 | 0 1 | (0 1) (1 0)
3442 09:32:20.532996 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3443 09:32:20.539961 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 09:32:20.542702 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 09:32:20.546661 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 09:32:20.552951 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 09:32:20.556286 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 09:32:20.559653 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3449 09:32:20.566378 1 0 24 | B1->B0 | 4646 2c2c | 0 0 | (0 0) (1 1)
3450 09:32:20.569774 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3451 09:32:20.572873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 09:32:20.579925 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 09:32:20.583109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 09:32:20.586446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 09:32:20.592844 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 09:32:20.596098 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 09:32:20.599889 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3458 09:32:20.606348 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3459 09:32:20.609308 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 09:32:20.613161 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 09:32:20.616221 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 09:32:20.622970 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 09:32:20.626565 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 09:32:20.629537 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 09:32:20.636450 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 09:32:20.639721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 09:32:20.643082 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 09:32:20.649689 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 09:32:20.652941 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 09:32:20.656294 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 09:32:20.662961 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 09:32:20.666204 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3473 09:32:20.669668 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3474 09:32:20.676384 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 09:32:20.676485 Total UI for P1: 0, mck2ui 16
3476 09:32:20.682930 best dqsien dly found for B0: ( 1, 3, 26)
3477 09:32:20.683052 Total UI for P1: 0, mck2ui 16
3478 09:32:20.689196 best dqsien dly found for B1: ( 1, 3, 22)
3479 09:32:20.692531 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3480 09:32:20.695831 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3481 09:32:20.695951
3482 09:32:20.699106 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3483 09:32:20.702525 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3484 09:32:20.705931 [Gating] SW calibration Done
3485 09:32:20.706051 ==
3486 09:32:20.709337 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 09:32:20.712633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 09:32:20.712740 ==
3489 09:32:20.715697 RX Vref Scan: 0
3490 09:32:20.715780
3491 09:32:20.715878 RX Vref 0 -> 0, step: 1
3492 09:32:20.715960
3493 09:32:20.718778 RX Delay -40 -> 252, step: 8
3494 09:32:20.725994 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 09:32:20.728754 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3496 09:32:20.731973 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3497 09:32:20.735602 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3498 09:32:20.738724 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3499 09:32:20.745408 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 09:32:20.749061 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 09:32:20.752057 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 09:32:20.755272 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3503 09:32:20.759165 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 09:32:20.762591 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 09:32:20.768508 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 09:32:20.772432 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 09:32:20.775816 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 09:32:20.779141 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 09:32:20.785513 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3510 09:32:20.785623 ==
3511 09:32:20.788866 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 09:32:20.792109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 09:32:20.792212 ==
3514 09:32:20.792318 DQS Delay:
3515 09:32:20.795207 DQS0 = 0, DQS1 = 0
3516 09:32:20.795321 DQM Delay:
3517 09:32:20.798635 DQM0 = 121, DQM1 = 117
3518 09:32:20.798740 DQ Delay:
3519 09:32:20.801777 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3520 09:32:20.805150 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3521 09:32:20.808426 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3522 09:32:20.812419 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3523 09:32:20.812527
3524 09:32:20.812624
3525 09:32:20.815559 ==
3526 09:32:20.818870 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 09:32:20.822138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 09:32:20.822247 ==
3529 09:32:20.822356
3530 09:32:20.822468
3531 09:32:20.825439 TX Vref Scan disable
3532 09:32:20.825543 == TX Byte 0 ==
3533 09:32:20.828862 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 09:32:20.835483 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 09:32:20.835599 == TX Byte 1 ==
3536 09:32:20.838412 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 09:32:20.845319 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 09:32:20.845408 ==
3539 09:32:20.848517 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 09:32:20.851841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 09:32:20.851927 ==
3542 09:32:20.863751 TX Vref=22, minBit 9, minWin=25, winSum=418
3543 09:32:20.866717 TX Vref=24, minBit 2, minWin=26, winSum=424
3544 09:32:20.870656 TX Vref=26, minBit 10, minWin=25, winSum=426
3545 09:32:20.873904 TX Vref=28, minBit 9, minWin=26, winSum=431
3546 09:32:20.877255 TX Vref=30, minBit 9, minWin=26, winSum=435
3547 09:32:20.883208 TX Vref=32, minBit 9, minWin=26, winSum=435
3548 09:32:20.886516 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3549 09:32:20.886601
3550 09:32:20.889879 Final TX Range 1 Vref 30
3551 09:32:20.889970
3552 09:32:20.890040 ==
3553 09:32:20.893298 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 09:32:20.896582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 09:32:20.896667 ==
3556 09:32:20.899984
3557 09:32:20.900083
3558 09:32:20.900151 TX Vref Scan disable
3559 09:32:20.903133 == TX Byte 0 ==
3560 09:32:20.906807 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 09:32:20.913407 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 09:32:20.913501 == TX Byte 1 ==
3563 09:32:20.916363 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 09:32:20.923021 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 09:32:20.923099
3566 09:32:20.923168 [DATLAT]
3567 09:32:20.923227 Freq=1200, CH1 RK1
3568 09:32:20.923285
3569 09:32:20.926244 DATLAT Default: 0xd
3570 09:32:20.929680 0, 0xFFFF, sum = 0
3571 09:32:20.929763 1, 0xFFFF, sum = 0
3572 09:32:20.933036 2, 0xFFFF, sum = 0
3573 09:32:20.933129 3, 0xFFFF, sum = 0
3574 09:32:20.936433 4, 0xFFFF, sum = 0
3575 09:32:20.936521 5, 0xFFFF, sum = 0
3576 09:32:20.939656 6, 0xFFFF, sum = 0
3577 09:32:20.939777 7, 0xFFFF, sum = 0
3578 09:32:20.942966 8, 0xFFFF, sum = 0
3579 09:32:20.943078 9, 0xFFFF, sum = 0
3580 09:32:20.946264 10, 0xFFFF, sum = 0
3581 09:32:20.946345 11, 0xFFFF, sum = 0
3582 09:32:20.949221 12, 0x0, sum = 1
3583 09:32:20.949303 13, 0x0, sum = 2
3584 09:32:20.953049 14, 0x0, sum = 3
3585 09:32:20.953138 15, 0x0, sum = 4
3586 09:32:20.956110 best_step = 13
3587 09:32:20.956196
3588 09:32:20.956261 ==
3589 09:32:20.959756 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 09:32:20.963120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 09:32:20.963213 ==
3592 09:32:20.966324 RX Vref Scan: 0
3593 09:32:20.966412
3594 09:32:20.966480 RX Vref 0 -> 0, step: 1
3595 09:32:20.966540
3596 09:32:20.969349 RX Delay -5 -> 252, step: 4
3597 09:32:20.973205 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 09:32:20.979331 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 09:32:20.982576 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 09:32:20.985932 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3601 09:32:20.989169 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 09:32:20.995661 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3603 09:32:20.999074 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 09:32:21.002665 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 09:32:21.005954 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3606 09:32:21.009250 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3607 09:32:21.015258 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3608 09:32:21.019141 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3609 09:32:21.022406 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 09:32:21.025514 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 09:32:21.028988 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3612 09:32:21.035443 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3613 09:32:21.035527 ==
3614 09:32:21.038710 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 09:32:21.042198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 09:32:21.042289 ==
3617 09:32:21.042362 DQS Delay:
3618 09:32:21.045058 DQS0 = 0, DQS1 = 0
3619 09:32:21.045176 DQM Delay:
3620 09:32:21.048900 DQM0 = 120, DQM1 = 118
3621 09:32:21.049006 DQ Delay:
3622 09:32:21.052282 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3623 09:32:21.055744 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3624 09:32:21.058904 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3625 09:32:21.062196 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3626 09:32:21.065002
3627 09:32:21.065111
3628 09:32:21.072229 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3629 09:32:21.075582 CH1 RK1: MR19=403, MR18=10ED
3630 09:32:21.082210 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 09:32:21.085246 [RxdqsGatingPostProcess] freq 1200
3632 09:32:21.088461 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 09:32:21.091739 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 09:32:21.095313 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 09:32:21.098632 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 09:32:21.101995 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 09:32:21.105313 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 09:32:21.108807 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 09:32:21.112094 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 09:32:21.115515 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 09:32:21.118775 Pre-setting of DQS Precalculation
3642 09:32:21.122119 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 09:32:21.128715 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 09:32:21.138197 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 09:32:21.138279
3646 09:32:21.138345
3647 09:32:21.141416 [Calibration Summary] 2400 Mbps
3648 09:32:21.141521 CH 0, Rank 0
3649 09:32:21.145270 SW Impedance : PASS
3650 09:32:21.145367 DUTY Scan : NO K
3651 09:32:21.148603 ZQ Calibration : PASS
3652 09:32:21.151916 Jitter Meter : NO K
3653 09:32:21.152038 CBT Training : PASS
3654 09:32:21.155109 Write leveling : PASS
3655 09:32:21.155201 RX DQS gating : PASS
3656 09:32:21.158500 RX DQ/DQS(RDDQC) : PASS
3657 09:32:21.161813 TX DQ/DQS : PASS
3658 09:32:21.161909 RX DATLAT : PASS
3659 09:32:21.165061 RX DQ/DQS(Engine): PASS
3660 09:32:21.168350 TX OE : NO K
3661 09:32:21.168425 All Pass.
3662 09:32:21.168502
3663 09:32:21.168563 CH 0, Rank 1
3664 09:32:21.171678 SW Impedance : PASS
3665 09:32:21.174790 DUTY Scan : NO K
3666 09:32:21.174876 ZQ Calibration : PASS
3667 09:32:21.178614 Jitter Meter : NO K
3668 09:32:21.181313 CBT Training : PASS
3669 09:32:21.181391 Write leveling : PASS
3670 09:32:21.184887 RX DQS gating : PASS
3671 09:32:21.188133 RX DQ/DQS(RDDQC) : PASS
3672 09:32:21.188227 TX DQ/DQS : PASS
3673 09:32:21.191484 RX DATLAT : PASS
3674 09:32:21.194859 RX DQ/DQS(Engine): PASS
3675 09:32:21.194933 TX OE : NO K
3676 09:32:21.195006 All Pass.
3677 09:32:21.198006
3678 09:32:21.198122 CH 1, Rank 0
3679 09:32:21.201796 SW Impedance : PASS
3680 09:32:21.201919 DUTY Scan : NO K
3681 09:32:21.204651 ZQ Calibration : PASS
3682 09:32:21.204731 Jitter Meter : NO K
3683 09:32:21.208155 CBT Training : PASS
3684 09:32:21.211466 Write leveling : PASS
3685 09:32:21.211568 RX DQS gating : PASS
3686 09:32:21.214791 RX DQ/DQS(RDDQC) : PASS
3687 09:32:21.218267 TX DQ/DQS : PASS
3688 09:32:21.218378 RX DATLAT : PASS
3689 09:32:21.221711 RX DQ/DQS(Engine): PASS
3690 09:32:21.224988 TX OE : NO K
3691 09:32:21.225119 All Pass.
3692 09:32:21.225230
3693 09:32:21.225353 CH 1, Rank 1
3694 09:32:21.228258 SW Impedance : PASS
3695 09:32:21.231803 DUTY Scan : NO K
3696 09:32:21.231878 ZQ Calibration : PASS
3697 09:32:21.234506 Jitter Meter : NO K
3698 09:32:21.238364 CBT Training : PASS
3699 09:32:21.238488 Write leveling : PASS
3700 09:32:21.241725 RX DQS gating : PASS
3701 09:32:21.244611 RX DQ/DQS(RDDQC) : PASS
3702 09:32:21.244705 TX DQ/DQS : PASS
3703 09:32:21.248049 RX DATLAT : PASS
3704 09:32:21.248179 RX DQ/DQS(Engine): PASS
3705 09:32:21.251267 TX OE : NO K
3706 09:32:21.251378 All Pass.
3707 09:32:21.251471
3708 09:32:21.254532 DramC Write-DBI off
3709 09:32:21.258125 PER_BANK_REFRESH: Hybrid Mode
3710 09:32:21.258234 TX_TRACKING: ON
3711 09:32:21.267974 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 09:32:21.271543 [FAST_K] Save calibration result to emmc
3713 09:32:21.274921 dramc_set_vcore_voltage set vcore to 650000
3714 09:32:21.278112 Read voltage for 600, 5
3715 09:32:21.278196 Vio18 = 0
3716 09:32:21.281429 Vcore = 650000
3717 09:32:21.281512 Vdram = 0
3718 09:32:21.281578 Vddq = 0
3719 09:32:21.281640 Vmddr = 0
3720 09:32:21.287645 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 09:32:21.294386 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 09:32:21.294471 MEM_TYPE=3, freq_sel=19
3723 09:32:21.297824 sv_algorithm_assistance_LP4_1600
3724 09:32:21.301155 ============ PULL DRAM RESETB DOWN ============
3725 09:32:21.307998 ========== PULL DRAM RESETB DOWN end =========
3726 09:32:21.311309 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 09:32:21.314419 ===================================
3728 09:32:21.317519 LPDDR4 DRAM CONFIGURATION
3729 09:32:21.321232 ===================================
3730 09:32:21.321356 EX_ROW_EN[0] = 0x0
3731 09:32:21.324290 EX_ROW_EN[1] = 0x0
3732 09:32:21.324394 LP4Y_EN = 0x0
3733 09:32:21.328018 WORK_FSP = 0x0
3734 09:32:21.328135 WL = 0x2
3735 09:32:21.331150 RL = 0x2
3736 09:32:21.331263 BL = 0x2
3737 09:32:21.334578 RPST = 0x0
3738 09:32:21.334692 RD_PRE = 0x0
3739 09:32:21.337825 WR_PRE = 0x1
3740 09:32:21.337913 WR_PST = 0x0
3741 09:32:21.341065 DBI_WR = 0x0
3742 09:32:21.341173 DBI_RD = 0x0
3743 09:32:21.344900 OTF = 0x1
3744 09:32:21.347719 ===================================
3745 09:32:21.350986 ===================================
3746 09:32:21.351104 ANA top config
3747 09:32:21.354401 ===================================
3748 09:32:21.357860 DLL_ASYNC_EN = 0
3749 09:32:21.361363 ALL_SLAVE_EN = 1
3750 09:32:21.364713 NEW_RANK_MODE = 1
3751 09:32:21.364829 DLL_IDLE_MODE = 1
3752 09:32:21.368064 LP45_APHY_COMB_EN = 1
3753 09:32:21.371274 TX_ODT_DIS = 1
3754 09:32:21.374738 NEW_8X_MODE = 1
3755 09:32:21.377789 ===================================
3756 09:32:21.381217 ===================================
3757 09:32:21.384501 data_rate = 1200
3758 09:32:21.387799 CKR = 1
3759 09:32:21.387880 DQ_P2S_RATIO = 8
3760 09:32:21.391209 ===================================
3761 09:32:21.394449 CA_P2S_RATIO = 8
3762 09:32:21.398063 DQ_CA_OPEN = 0
3763 09:32:21.400961 DQ_SEMI_OPEN = 0
3764 09:32:21.404792 CA_SEMI_OPEN = 0
3765 09:32:21.404881 CA_FULL_RATE = 0
3766 09:32:21.407481 DQ_CKDIV4_EN = 1
3767 09:32:21.410860 CA_CKDIV4_EN = 1
3768 09:32:21.414227 CA_PREDIV_EN = 0
3769 09:32:21.417601 PH8_DLY = 0
3770 09:32:21.420825 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 09:32:21.420909 DQ_AAMCK_DIV = 4
3772 09:32:21.424151 CA_AAMCK_DIV = 4
3773 09:32:21.427567 CA_ADMCK_DIV = 4
3774 09:32:21.430724 DQ_TRACK_CA_EN = 0
3775 09:32:21.434468 CA_PICK = 600
3776 09:32:21.437565 CA_MCKIO = 600
3777 09:32:21.440943 MCKIO_SEMI = 0
3778 09:32:21.441048 PLL_FREQ = 2288
3779 09:32:21.444057 DQ_UI_PI_RATIO = 32
3780 09:32:21.447408 CA_UI_PI_RATIO = 0
3781 09:32:21.450771 ===================================
3782 09:32:21.454175 ===================================
3783 09:32:21.457717 memory_type:LPDDR4
3784 09:32:21.461045 GP_NUM : 10
3785 09:32:21.461149 SRAM_EN : 1
3786 09:32:21.464390 MD32_EN : 0
3787 09:32:21.467701 ===================================
3788 09:32:21.467821 [ANA_INIT] >>>>>>>>>>>>>>
3789 09:32:21.471196 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 09:32:21.474002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 09:32:21.477420 ===================================
3792 09:32:21.480746 data_rate = 1200,PCW = 0X5800
3793 09:32:21.484142 ===================================
3794 09:32:21.487467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 09:32:21.493654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 09:32:21.500505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 09:32:21.503523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 09:32:21.507046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 09:32:21.510418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 09:32:21.513783 [ANA_INIT] flow start
3801 09:32:21.513904 [ANA_INIT] PLL >>>>>>>>
3802 09:32:21.517210 [ANA_INIT] PLL <<<<<<<<
3803 09:32:21.520612 [ANA_INIT] MIDPI >>>>>>>>
3804 09:32:21.520729 [ANA_INIT] MIDPI <<<<<<<<
3805 09:32:21.523872 [ANA_INIT] DLL >>>>>>>>
3806 09:32:21.527098 [ANA_INIT] flow end
3807 09:32:21.530428 ============ LP4 DIFF to SE enter ============
3808 09:32:21.533874 ============ LP4 DIFF to SE exit ============
3809 09:32:21.537225 [ANA_INIT] <<<<<<<<<<<<<
3810 09:32:21.540577 [Flow] Enable top DCM control >>>>>
3811 09:32:21.543803 [Flow] Enable top DCM control <<<<<
3812 09:32:21.547059 Enable DLL master slave shuffle
3813 09:32:21.550138 ==============================================================
3814 09:32:21.553675 Gating Mode config
3815 09:32:21.560382 ==============================================================
3816 09:32:21.560483 Config description:
3817 09:32:21.570353 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 09:32:21.577168 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 09:32:21.580548 SELPH_MODE 0: By rank 1: By Phase
3820 09:32:21.587213 ==============================================================
3821 09:32:21.590600 GAT_TRACK_EN = 1
3822 09:32:21.593376 RX_GATING_MODE = 2
3823 09:32:21.596720 RX_GATING_TRACK_MODE = 2
3824 09:32:21.600038 SELPH_MODE = 1
3825 09:32:21.603770 PICG_EARLY_EN = 1
3826 09:32:21.607048 VALID_LAT_VALUE = 1
3827 09:32:21.610413 ==============================================================
3828 09:32:21.613667 Enter into Gating configuration >>>>
3829 09:32:21.616937 Exit from Gating configuration <<<<
3830 09:32:21.620094 Enter into DVFS_PRE_config >>>>>
3831 09:32:21.629961 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 09:32:21.633563 Exit from DVFS_PRE_config <<<<<
3833 09:32:21.636514 Enter into PICG configuration >>>>
3834 09:32:21.639803 Exit from PICG configuration <<<<
3835 09:32:21.643145 [RX_INPUT] configuration >>>>>
3836 09:32:21.646575 [RX_INPUT] configuration <<<<<
3837 09:32:21.653490 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 09:32:21.656887 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 09:32:21.663199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 09:32:21.669746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 09:32:21.676718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 09:32:21.683283 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 09:32:21.686703 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 09:32:21.690041 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 09:32:21.693476 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 09:32:21.700242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 09:32:21.702933 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 09:32:21.706165 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 09:32:21.709994 ===================================
3850 09:32:21.713111 LPDDR4 DRAM CONFIGURATION
3851 09:32:21.716594 ===================================
3852 09:32:21.716707 EX_ROW_EN[0] = 0x0
3853 09:32:21.720004 EX_ROW_EN[1] = 0x0
3854 09:32:21.722734 LP4Y_EN = 0x0
3855 09:32:21.722837 WORK_FSP = 0x0
3856 09:32:21.726723 WL = 0x2
3857 09:32:21.726828 RL = 0x2
3858 09:32:21.729830 BL = 0x2
3859 09:32:21.729933 RPST = 0x0
3860 09:32:21.732860 RD_PRE = 0x0
3861 09:32:21.732945 WR_PRE = 0x1
3862 09:32:21.736290 WR_PST = 0x0
3863 09:32:21.736375 DBI_WR = 0x0
3864 09:32:21.739669 DBI_RD = 0x0
3865 09:32:21.739754 OTF = 0x1
3866 09:32:21.742894 ===================================
3867 09:32:21.746036 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 09:32:21.752807 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 09:32:21.756280 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 09:32:21.759304 ===================================
3871 09:32:21.762819 LPDDR4 DRAM CONFIGURATION
3872 09:32:21.766582 ===================================
3873 09:32:21.766666 EX_ROW_EN[0] = 0x10
3874 09:32:21.769257 EX_ROW_EN[1] = 0x0
3875 09:32:21.769339 LP4Y_EN = 0x0
3876 09:32:21.772698 WORK_FSP = 0x0
3877 09:32:21.776061 WL = 0x2
3878 09:32:21.776144 RL = 0x2
3879 09:32:21.779286 BL = 0x2
3880 09:32:21.779381 RPST = 0x0
3881 09:32:21.783001 RD_PRE = 0x0
3882 09:32:21.783084 WR_PRE = 0x1
3883 09:32:21.786534 WR_PST = 0x0
3884 09:32:21.786617 DBI_WR = 0x0
3885 09:32:21.789558 DBI_RD = 0x0
3886 09:32:21.789639 OTF = 0x1
3887 09:32:21.792804 ===================================
3888 09:32:21.799468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 09:32:21.803417 nWR fixed to 30
3890 09:32:21.806889 [ModeRegInit_LP4] CH0 RK0
3891 09:32:21.806971 [ModeRegInit_LP4] CH0 RK1
3892 09:32:21.810128 [ModeRegInit_LP4] CH1 RK0
3893 09:32:21.813470 [ModeRegInit_LP4] CH1 RK1
3894 09:32:21.813578 match AC timing 17
3895 09:32:21.820043 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 09:32:21.823380 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 09:32:21.826727 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 09:32:21.833286 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 09:32:21.836536 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 09:32:21.836640 ==
3901 09:32:21.839551 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 09:32:21.843006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 09:32:21.843108 ==
3904 09:32:21.849727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 09:32:21.856395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 09:32:21.859774 [CA 0] Center 35 (5~66) winsize 62
3907 09:32:21.862930 [CA 1] Center 35 (5~66) winsize 62
3908 09:32:21.866176 [CA 2] Center 33 (3~64) winsize 62
3909 09:32:21.869251 [CA 3] Center 33 (2~64) winsize 63
3910 09:32:21.872725 [CA 4] Center 33 (2~64) winsize 63
3911 09:32:21.876148 [CA 5] Center 32 (2~63) winsize 62
3912 09:32:21.876251
3913 09:32:21.879739 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 09:32:21.879846
3915 09:32:21.882717 [CATrainingPosCal] consider 1 rank data
3916 09:32:21.886019 u2DelayCellTimex100 = 270/100 ps
3917 09:32:21.889369 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3918 09:32:21.892491 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3919 09:32:21.896200 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3920 09:32:21.899404 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 09:32:21.905803 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 09:32:21.908998 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 09:32:21.909108
3924 09:32:21.912821 CA PerBit enable=1, Macro0, CA PI delay=32
3925 09:32:21.912926
3926 09:32:21.915462 [CBTSetCACLKResult] CA Dly = 32
3927 09:32:21.915578 CS Dly: 5 (0~36)
3928 09:32:21.915693 ==
3929 09:32:21.919379 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 09:32:21.922688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 09:32:21.925804 ==
3932 09:32:21.929298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 09:32:21.936038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 09:32:21.939469 [CA 0] Center 35 (5~66) winsize 62
3935 09:32:21.942874 [CA 1] Center 35 (5~66) winsize 62
3936 09:32:21.945951 [CA 2] Center 34 (3~65) winsize 63
3937 09:32:21.949381 [CA 3] Center 33 (3~64) winsize 62
3938 09:32:21.952686 [CA 4] Center 33 (2~64) winsize 63
3939 09:32:21.955956 [CA 5] Center 32 (2~63) winsize 62
3940 09:32:21.956088
3941 09:32:21.959518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 09:32:21.959629
3943 09:32:21.962295 [CATrainingPosCal] consider 2 rank data
3944 09:32:21.965795 u2DelayCellTimex100 = 270/100 ps
3945 09:32:21.969033 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 09:32:21.972365 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 09:32:21.975693 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 09:32:21.982180 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 09:32:21.985782 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 09:32:21.988889 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 09:32:21.988993
3952 09:32:21.992335 CA PerBit enable=1, Macro0, CA PI delay=32
3953 09:32:21.992443
3954 09:32:21.995366 [CBTSetCACLKResult] CA Dly = 32
3955 09:32:21.995470 CS Dly: 5 (0~37)
3956 09:32:21.995565
3957 09:32:21.999004 ----->DramcWriteLeveling(PI) begin...
3958 09:32:21.999114 ==
3959 09:32:22.002486 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 09:32:22.008735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 09:32:22.008843 ==
3962 09:32:22.012131 Write leveling (Byte 0): 32 => 32
3963 09:32:22.015361 Write leveling (Byte 1): 31 => 31
3964 09:32:22.015472 DramcWriteLeveling(PI) end<-----
3965 09:32:22.015570
3966 09:32:22.019240 ==
3967 09:32:22.022382 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 09:32:22.025439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 09:32:22.025544 ==
3970 09:32:22.029145 [Gating] SW mode calibration
3971 09:32:22.035400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 09:32:22.038711 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 09:32:22.045284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 09:32:22.048632 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 09:32:22.052502 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 09:32:22.058748 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
3977 09:32:22.062156 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
3978 09:32:22.065439 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 09:32:22.072207 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 09:32:22.075583 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 09:32:22.078942 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 09:32:22.085718 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 09:32:22.089007 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3984 09:32:22.092363 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
3985 09:32:22.098680 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3986 09:32:22.102277 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 09:32:22.105315 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 09:32:22.108519 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 09:32:22.115296 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 09:32:22.118843 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 09:32:22.122044 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 09:32:22.128716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 09:32:22.131874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3994 09:32:22.135500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 09:32:22.141862 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 09:32:22.145388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 09:32:22.148498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 09:32:22.155270 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 09:32:22.158608 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 09:32:22.161968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 09:32:22.168392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 09:32:22.171675 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 09:32:22.175064 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 09:32:22.181813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 09:32:22.185079 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 09:32:22.188341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 09:32:22.195130 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 09:32:22.198592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4009 09:32:22.201981 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4010 09:32:22.204751 Total UI for P1: 0, mck2ui 16
4011 09:32:22.208060 best dqsien dly found for B0: ( 0, 13, 12)
4012 09:32:22.214672 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 09:32:22.214782 Total UI for P1: 0, mck2ui 16
4014 09:32:22.221283 best dqsien dly found for B1: ( 0, 13, 18)
4015 09:32:22.224902 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 09:32:22.228488 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4017 09:32:22.228592
4018 09:32:22.231691 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 09:32:22.235094 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4020 09:32:22.238445 [Gating] SW calibration Done
4021 09:32:22.238550 ==
4022 09:32:22.241751 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 09:32:22.245008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 09:32:22.245114 ==
4025 09:32:22.248305 RX Vref Scan: 0
4026 09:32:22.248407
4027 09:32:22.248504 RX Vref 0 -> 0, step: 1
4028 09:32:22.248594
4029 09:32:22.251375 RX Delay -230 -> 252, step: 16
4030 09:32:22.257889 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 09:32:22.261317 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 09:32:22.264651 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 09:32:22.268205 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4034 09:32:22.271340 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4035 09:32:22.278259 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 09:32:22.281637 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 09:32:22.285006 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 09:32:22.288346 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 09:32:22.291704 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4040 09:32:22.298385 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4041 09:32:22.301727 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 09:32:22.304990 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 09:32:22.308427 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 09:32:22.314588 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 09:32:22.317897 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4046 09:32:22.318007 ==
4047 09:32:22.321004 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 09:32:22.324582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 09:32:22.324685 ==
4050 09:32:22.328005 DQS Delay:
4051 09:32:22.328108 DQS0 = 0, DQS1 = 0
4052 09:32:22.328204 DQM Delay:
4053 09:32:22.331052 DQM0 = 48, DQM1 = 46
4054 09:32:22.331156 DQ Delay:
4055 09:32:22.334723 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4056 09:32:22.337635 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4057 09:32:22.341514 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4058 09:32:22.344753 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4059 09:32:22.344859
4060 09:32:22.344954
4061 09:32:22.345044 ==
4062 09:32:22.348210 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 09:32:22.354285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 09:32:22.354373 ==
4065 09:32:22.354460
4066 09:32:22.354542
4067 09:32:22.354622 TX Vref Scan disable
4068 09:32:22.358229 == TX Byte 0 ==
4069 09:32:22.361497 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4070 09:32:22.368084 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4071 09:32:22.368171 == TX Byte 1 ==
4072 09:32:22.372045 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 09:32:22.378204 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 09:32:22.378290 ==
4075 09:32:22.381872 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 09:32:22.384894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 09:32:22.384980 ==
4078 09:32:22.385068
4079 09:32:22.385150
4080 09:32:22.388236 TX Vref Scan disable
4081 09:32:22.388346 == TX Byte 0 ==
4082 09:32:22.394996 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4083 09:32:22.397944 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4084 09:32:22.398058 == TX Byte 1 ==
4085 09:32:22.404613 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4086 09:32:22.407895 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4087 09:32:22.407990
4088 09:32:22.408061 [DATLAT]
4089 09:32:22.411197 Freq=600, CH0 RK0
4090 09:32:22.411276
4091 09:32:22.411337 DATLAT Default: 0x9
4092 09:32:22.414638 0, 0xFFFF, sum = 0
4093 09:32:22.414741 1, 0xFFFF, sum = 0
4094 09:32:22.418068 2, 0xFFFF, sum = 0
4095 09:32:22.421457 3, 0xFFFF, sum = 0
4096 09:32:22.421573 4, 0xFFFF, sum = 0
4097 09:32:22.424923 5, 0xFFFF, sum = 0
4098 09:32:22.425028 6, 0xFFFF, sum = 0
4099 09:32:22.428334 7, 0xFFFF, sum = 0
4100 09:32:22.428439 8, 0x0, sum = 1
4101 09:32:22.428535 9, 0x0, sum = 2
4102 09:32:22.431553 10, 0x0, sum = 3
4103 09:32:22.431662 11, 0x0, sum = 4
4104 09:32:22.434618 best_step = 9
4105 09:32:22.434691
4106 09:32:22.434751 ==
4107 09:32:22.437640 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 09:32:22.441353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 09:32:22.441458 ==
4110 09:32:22.444368 RX Vref Scan: 1
4111 09:32:22.444471
4112 09:32:22.444564 RX Vref 0 -> 0, step: 1
4113 09:32:22.444653
4114 09:32:22.447994 RX Delay -163 -> 252, step: 8
4115 09:32:22.448070
4116 09:32:22.451342 Set Vref, RX VrefLevel [Byte0]: 55
4117 09:32:22.454506 [Byte1]: 47
4118 09:32:22.458436
4119 09:32:22.458509 Final RX Vref Byte 0 = 55 to rank0
4120 09:32:22.461808 Final RX Vref Byte 1 = 47 to rank0
4121 09:32:22.465050 Final RX Vref Byte 0 = 55 to rank1
4122 09:32:22.468477 Final RX Vref Byte 1 = 47 to rank1==
4123 09:32:22.471825 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 09:32:22.478549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 09:32:22.478662 ==
4126 09:32:22.478741 DQS Delay:
4127 09:32:22.478814 DQS0 = 0, DQS1 = 0
4128 09:32:22.481917 DQM Delay:
4129 09:32:22.482023 DQM0 = 53, DQM1 = 46
4130 09:32:22.485301 DQ Delay:
4131 09:32:22.488658 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4132 09:32:22.488767 DQ4 =56, DQ5 =44, DQ6 =64, DQ7 =60
4133 09:32:22.491953 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4134 09:32:22.498527 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =52
4135 09:32:22.498641
4136 09:32:22.498729
4137 09:32:22.505308 [DQSOSCAuto] RK0, (LSB)MR18= 0x7165, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4138 09:32:22.508793 CH0 RK0: MR19=808, MR18=7165
4139 09:32:22.515255 CH0_RK0: MR19=0x808, MR18=0x7165, DQSOSC=388, MR23=63, INC=174, DEC=116
4140 09:32:22.515363
4141 09:32:22.518686 ----->DramcWriteLeveling(PI) begin...
4142 09:32:22.518763 ==
4143 09:32:22.521877 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 09:32:22.525129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 09:32:22.525234 ==
4146 09:32:22.528425 Write leveling (Byte 0): 35 => 35
4147 09:32:22.531886 Write leveling (Byte 1): 31 => 31
4148 09:32:22.535271 DramcWriteLeveling(PI) end<-----
4149 09:32:22.535375
4150 09:32:22.535466 ==
4151 09:32:22.538611 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 09:32:22.541974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 09:32:22.542092 ==
4154 09:32:22.544694 [Gating] SW mode calibration
4155 09:32:22.551772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 09:32:22.557952 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 09:32:22.561633 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 09:32:22.568195 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 09:32:22.571625 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4160 09:32:22.574942 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4161 09:32:22.578308 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4162 09:32:22.584489 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 09:32:22.587797 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 09:32:22.591123 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 09:32:22.598016 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 09:32:22.601428 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 09:32:22.604816 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 09:32:22.611403 0 10 12 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
4169 09:32:22.614697 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
4170 09:32:22.617912 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 09:32:22.624701 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 09:32:22.628131 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 09:32:22.631210 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 09:32:22.638084 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 09:32:22.641263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 09:32:22.644609 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4177 09:32:22.651058 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 09:32:22.654176 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 09:32:22.658104 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 09:32:22.664644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 09:32:22.667656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 09:32:22.671130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 09:32:22.677839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 09:32:22.681077 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 09:32:22.684394 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 09:32:22.691106 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 09:32:22.694499 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 09:32:22.697787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 09:32:22.704404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 09:32:22.707767 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 09:32:22.711047 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 09:32:22.717831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 09:32:22.721052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 09:32:22.724336 Total UI for P1: 0, mck2ui 16
4195 09:32:22.727596 best dqsien dly found for B0: ( 0, 13, 14)
4196 09:32:22.730843 Total UI for P1: 0, mck2ui 16
4197 09:32:22.734028 best dqsien dly found for B1: ( 0, 13, 14)
4198 09:32:22.737717 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4199 09:32:22.740852 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 09:32:22.740930
4201 09:32:22.744467 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4202 09:32:22.747607 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 09:32:22.751088 [Gating] SW calibration Done
4204 09:32:22.751190 ==
4205 09:32:22.754305 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 09:32:22.757719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 09:32:22.757828 ==
4208 09:32:22.760597 RX Vref Scan: 0
4209 09:32:22.760670
4210 09:32:22.764130 RX Vref 0 -> 0, step: 1
4211 09:32:22.764202
4212 09:32:22.764263 RX Delay -230 -> 252, step: 16
4213 09:32:22.770961 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 09:32:22.774093 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 09:32:22.777757 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 09:32:22.780862 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 09:32:22.787190 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4218 09:32:22.790426 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4219 09:32:22.793797 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 09:32:22.797889 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4221 09:32:22.800646 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4222 09:32:22.807281 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 09:32:22.810624 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 09:32:22.813911 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 09:32:22.817221 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 09:32:22.824102 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 09:32:22.827482 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4228 09:32:22.830780 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 09:32:22.830885 ==
4230 09:32:22.834222 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 09:32:22.837531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 09:32:22.837643 ==
4233 09:32:22.840943 DQS Delay:
4234 09:32:22.841044 DQS0 = 0, DQS1 = 0
4235 09:32:22.844247 DQM Delay:
4236 09:32:22.844349 DQM0 = 52, DQM1 = 44
4237 09:32:22.844455 DQ Delay:
4238 09:32:22.847351 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 09:32:22.851024 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4240 09:32:22.854543 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =33
4241 09:32:22.857712 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4242 09:32:22.857830
4243 09:32:22.857924
4244 09:32:22.860905 ==
4245 09:32:22.863912 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 09:32:22.867670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 09:32:22.867805 ==
4248 09:32:22.867906
4249 09:32:22.867998
4250 09:32:22.870803 TX Vref Scan disable
4251 09:32:22.870918 == TX Byte 0 ==
4252 09:32:22.877250 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4253 09:32:22.880686 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4254 09:32:22.880793 == TX Byte 1 ==
4255 09:32:22.887560 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 09:32:22.890541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 09:32:22.890655 ==
4258 09:32:22.894042 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 09:32:22.897256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 09:32:22.897359 ==
4261 09:32:22.897461
4262 09:32:22.897552
4263 09:32:22.900549 TX Vref Scan disable
4264 09:32:22.903870 == TX Byte 0 ==
4265 09:32:22.907361 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 09:32:22.910671 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 09:32:22.913488 == TX Byte 1 ==
4268 09:32:22.916873 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 09:32:22.920594 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 09:32:22.920762
4271 09:32:22.923327 [DATLAT]
4272 09:32:22.923434 Freq=600, CH0 RK1
4273 09:32:22.923569
4274 09:32:22.926772 DATLAT Default: 0x9
4275 09:32:22.926880 0, 0xFFFF, sum = 0
4276 09:32:22.930050 1, 0xFFFF, sum = 0
4277 09:32:22.930161 2, 0xFFFF, sum = 0
4278 09:32:22.933532 3, 0xFFFF, sum = 0
4279 09:32:22.933648 4, 0xFFFF, sum = 0
4280 09:32:22.936784 5, 0xFFFF, sum = 0
4281 09:32:22.936884 6, 0xFFFF, sum = 0
4282 09:32:22.940235 7, 0xFFFF, sum = 0
4283 09:32:22.940341 8, 0x0, sum = 1
4284 09:32:22.943580 9, 0x0, sum = 2
4285 09:32:22.943725 10, 0x0, sum = 3
4286 09:32:22.946895 11, 0x0, sum = 4
4287 09:32:22.947015 best_step = 9
4288 09:32:22.947143
4289 09:32:22.947267 ==
4290 09:32:22.950256 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 09:32:22.956711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 09:32:22.956819 ==
4293 09:32:22.956913 RX Vref Scan: 0
4294 09:32:22.957000
4295 09:32:22.960402 RX Vref 0 -> 0, step: 1
4296 09:32:22.960522
4297 09:32:22.963400 RX Delay -163 -> 252, step: 8
4298 09:32:22.966570 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 09:32:22.970429 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4300 09:32:22.977035 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 09:32:22.980335 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 09:32:22.983426 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4303 09:32:22.986916 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 09:32:22.990276 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4305 09:32:22.996450 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4306 09:32:23.000317 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4307 09:32:23.003565 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4308 09:32:23.006684 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 09:32:23.009693 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 09:32:23.016370 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4311 09:32:23.019785 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4312 09:32:23.023177 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4313 09:32:23.026331 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4314 09:32:23.026444 ==
4315 09:32:23.029793 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 09:32:23.036794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 09:32:23.036901 ==
4318 09:32:23.036999 DQS Delay:
4319 09:32:23.040104 DQS0 = 0, DQS1 = 0
4320 09:32:23.040214 DQM Delay:
4321 09:32:23.040312 DQM0 = 53, DQM1 = 46
4322 09:32:23.043402 DQ Delay:
4323 09:32:23.046771 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4324 09:32:23.050183 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4325 09:32:23.053516 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4326 09:32:23.056788 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4327 09:32:23.056871
4328 09:32:23.056938
4329 09:32:23.063469 [DQSOSCAuto] RK1, (LSB)MR18= 0x6828, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4330 09:32:23.066237 CH0 RK1: MR19=808, MR18=6828
4331 09:32:23.073227 CH0_RK1: MR19=0x808, MR18=0x6828, DQSOSC=390, MR23=63, INC=172, DEC=114
4332 09:32:23.076191 [RxdqsGatingPostProcess] freq 600
4333 09:32:23.079551 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 09:32:23.083289 Pre-setting of DQS Precalculation
4335 09:32:23.089559 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 09:32:23.089642 ==
4337 09:32:23.093367 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 09:32:23.096840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 09:32:23.096923 ==
4340 09:32:23.103411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 09:32:23.109493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4342 09:32:23.112980 [CA 0] Center 35 (5~66) winsize 62
4343 09:32:23.116335 [CA 1] Center 36 (6~67) winsize 62
4344 09:32:23.119681 [CA 2] Center 34 (4~65) winsize 62
4345 09:32:23.122880 [CA 3] Center 34 (4~65) winsize 62
4346 09:32:23.125986 [CA 4] Center 34 (4~65) winsize 62
4347 09:32:23.129681 [CA 5] Center 33 (3~64) winsize 62
4348 09:32:23.129762
4349 09:32:23.132660 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4350 09:32:23.132742
4351 09:32:23.136124 [CATrainingPosCal] consider 1 rank data
4352 09:32:23.139377 u2DelayCellTimex100 = 270/100 ps
4353 09:32:23.142983 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4354 09:32:23.146097 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4355 09:32:23.149425 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 09:32:23.152929 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 09:32:23.156258 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 09:32:23.159604 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 09:32:23.159702
4360 09:32:23.165711 CA PerBit enable=1, Macro0, CA PI delay=33
4361 09:32:23.165794
4362 09:32:23.165858 [CBTSetCACLKResult] CA Dly = 33
4363 09:32:23.169610 CS Dly: 6 (0~37)
4364 09:32:23.169692 ==
4365 09:32:23.172322 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 09:32:23.175764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 09:32:23.175846 ==
4368 09:32:23.182334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 09:32:23.189224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 09:32:23.192717 [CA 0] Center 36 (5~67) winsize 63
4371 09:32:23.195801 [CA 1] Center 36 (5~67) winsize 63
4372 09:32:23.199345 [CA 2] Center 34 (4~65) winsize 62
4373 09:32:23.202565 [CA 3] Center 34 (4~65) winsize 62
4374 09:32:23.205881 [CA 4] Center 35 (4~66) winsize 63
4375 09:32:23.209223 [CA 5] Center 34 (3~65) winsize 63
4376 09:32:23.209304
4377 09:32:23.212548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 09:32:23.212672
4379 09:32:23.215560 [CATrainingPosCal] consider 2 rank data
4380 09:32:23.219496 u2DelayCellTimex100 = 270/100 ps
4381 09:32:23.222741 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 09:32:23.225999 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4383 09:32:23.229407 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 09:32:23.232776 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 09:32:23.236059 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 09:32:23.239500 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 09:32:23.239599
4388 09:32:23.245892 CA PerBit enable=1, Macro0, CA PI delay=33
4389 09:32:23.245975
4390 09:32:23.248994 [CBTSetCACLKResult] CA Dly = 33
4391 09:32:23.249102 CS Dly: 6 (0~38)
4392 09:32:23.249204
4393 09:32:23.252442 ----->DramcWriteLeveling(PI) begin...
4394 09:32:23.252532 ==
4395 09:32:23.255881 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 09:32:23.258894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 09:32:23.259044 ==
4398 09:32:23.262601 Write leveling (Byte 0): 31 => 31
4399 09:32:23.265922 Write leveling (Byte 1): 31 => 31
4400 09:32:23.269208 DramcWriteLeveling(PI) end<-----
4401 09:32:23.269308
4402 09:32:23.269407 ==
4403 09:32:23.272472 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 09:32:23.279291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 09:32:23.279378 ==
4406 09:32:23.279495 [Gating] SW mode calibration
4407 09:32:23.288856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 09:32:23.292210 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 09:32:23.295372 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 09:32:23.302411 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 09:32:23.305428 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 09:32:23.308999 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
4413 09:32:23.315662 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 09:32:23.318542 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 09:32:23.322066 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 09:32:23.328774 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 09:32:23.332346 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 09:32:23.335666 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 09:32:23.342428 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4420 09:32:23.345851 0 10 12 | B1->B0 | 3535 4545 | 0 1 | (1 1) (0 0)
4421 09:32:23.349177 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4422 09:32:23.355583 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 09:32:23.358853 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 09:32:23.361880 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 09:32:23.368566 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 09:32:23.372205 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 09:32:23.375782 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4428 09:32:23.382633 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4429 09:32:23.385741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 09:32:23.389054 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 09:32:23.392408 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 09:32:23.398701 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 09:32:23.402079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 09:32:23.405271 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 09:32:23.411961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 09:32:23.415195 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 09:32:23.418561 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 09:32:23.425525 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 09:32:23.428543 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 09:32:23.432237 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 09:32:23.438412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 09:32:23.441933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 09:32:23.445528 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 09:32:23.452163 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4445 09:32:23.452271 Total UI for P1: 0, mck2ui 16
4446 09:32:23.458935 best dqsien dly found for B1: ( 0, 13, 10)
4447 09:32:23.462236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 09:32:23.465633 Total UI for P1: 0, mck2ui 16
4449 09:32:23.468766 best dqsien dly found for B0: ( 0, 13, 12)
4450 09:32:23.472122 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4451 09:32:23.475510 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4452 09:32:23.475605
4453 09:32:23.478767 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 09:32:23.481879 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4455 09:32:23.485012 [Gating] SW calibration Done
4456 09:32:23.485093 ==
4457 09:32:23.488827 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 09:32:23.492191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 09:32:23.495555 ==
4460 09:32:23.495688 RX Vref Scan: 0
4461 09:32:23.495818
4462 09:32:23.499006 RX Vref 0 -> 0, step: 1
4463 09:32:23.499087
4464 09:32:23.501784 RX Delay -230 -> 252, step: 16
4465 09:32:23.505167 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4466 09:32:23.508458 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4467 09:32:23.511801 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4468 09:32:23.515546 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4469 09:32:23.521918 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4470 09:32:23.525210 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4471 09:32:23.528494 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4472 09:32:23.531820 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4473 09:32:23.538741 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4474 09:32:23.542073 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4475 09:32:23.545279 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4476 09:32:23.548404 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4477 09:32:23.554748 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4478 09:32:23.558361 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4479 09:32:23.561854 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4480 09:32:23.564881 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4481 09:32:23.564962 ==
4482 09:32:23.568724 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 09:32:23.575350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 09:32:23.575434 ==
4485 09:32:23.575499 DQS Delay:
4486 09:32:23.578665 DQS0 = 0, DQS1 = 0
4487 09:32:23.578745 DQM Delay:
4488 09:32:23.578810 DQM0 = 52, DQM1 = 49
4489 09:32:23.581463 DQ Delay:
4490 09:32:23.584948 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4491 09:32:23.588296 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4492 09:32:23.591520 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4493 09:32:23.594709 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4494 09:32:23.594796
4495 09:32:23.594900
4496 09:32:23.595001 ==
4497 09:32:23.598349 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 09:32:23.601689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 09:32:23.601778 ==
4500 09:32:23.601865
4501 09:32:23.601947
4502 09:32:23.604933 TX Vref Scan disable
4503 09:32:23.605034 == TX Byte 0 ==
4504 09:32:23.611663 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4505 09:32:23.615106 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4506 09:32:23.615193 == TX Byte 1 ==
4507 09:32:23.621659 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 09:32:23.624945 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 09:32:23.625027 ==
4510 09:32:23.628127 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 09:32:23.631504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 09:32:23.631611 ==
4513 09:32:23.631707
4514 09:32:23.631788
4515 09:32:23.635460 TX Vref Scan disable
4516 09:32:23.638785 == TX Byte 0 ==
4517 09:32:23.641461 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4518 09:32:23.645357 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4519 09:32:23.648562 == TX Byte 1 ==
4520 09:32:23.651763 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4521 09:32:23.655077 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4522 09:32:23.655157
4523 09:32:23.658543 [DATLAT]
4524 09:32:23.658650 Freq=600, CH1 RK0
4525 09:32:23.658757
4526 09:32:23.661848 DATLAT Default: 0x9
4527 09:32:23.661949 0, 0xFFFF, sum = 0
4528 09:32:23.665159 1, 0xFFFF, sum = 0
4529 09:32:23.665262 2, 0xFFFF, sum = 0
4530 09:32:23.668315 3, 0xFFFF, sum = 0
4531 09:32:23.668393 4, 0xFFFF, sum = 0
4532 09:32:23.671390 5, 0xFFFF, sum = 0
4533 09:32:23.671496 6, 0xFFFF, sum = 0
4534 09:32:23.674823 7, 0xFFFF, sum = 0
4535 09:32:23.674930 8, 0x0, sum = 1
4536 09:32:23.678284 9, 0x0, sum = 2
4537 09:32:23.678393 10, 0x0, sum = 3
4538 09:32:23.681782 11, 0x0, sum = 4
4539 09:32:23.681891 best_step = 9
4540 09:32:23.681987
4541 09:32:23.682077 ==
4542 09:32:23.684979 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 09:32:23.691731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 09:32:23.691839 ==
4545 09:32:23.691938 RX Vref Scan: 1
4546 09:32:23.692032
4547 09:32:23.694588 RX Vref 0 -> 0, step: 1
4548 09:32:23.694697
4549 09:32:23.697964 RX Delay -147 -> 252, step: 8
4550 09:32:23.698076
4551 09:32:23.701273 Set Vref, RX VrefLevel [Byte0]: 53
4552 09:32:23.704944 [Byte1]: 53
4553 09:32:23.705048
4554 09:32:23.708006 Final RX Vref Byte 0 = 53 to rank0
4555 09:32:23.711410 Final RX Vref Byte 1 = 53 to rank0
4556 09:32:23.714901 Final RX Vref Byte 0 = 53 to rank1
4557 09:32:23.717687 Final RX Vref Byte 1 = 53 to rank1==
4558 09:32:23.721279 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 09:32:23.724838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 09:32:23.724942 ==
4561 09:32:23.728199 DQS Delay:
4562 09:32:23.728285 DQS0 = 0, DQS1 = 0
4563 09:32:23.728357 DQM Delay:
4564 09:32:23.731305 DQM0 = 48, DQM1 = 45
4565 09:32:23.731407 DQ Delay:
4566 09:32:23.734505 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4567 09:32:23.738240 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4568 09:32:23.741277 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4569 09:32:23.744537 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4570 09:32:23.744645
4571 09:32:23.744739
4572 09:32:23.754703 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4573 09:32:23.754787 CH1 RK0: MR19=808, MR18=4D73
4574 09:32:23.761686 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4575 09:32:23.761793
4576 09:32:23.765042 ----->DramcWriteLeveling(PI) begin...
4577 09:32:23.765160 ==
4578 09:32:23.767695 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 09:32:23.774574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 09:32:23.774680 ==
4581 09:32:23.777971 Write leveling (Byte 0): 30 => 30
4582 09:32:23.781180 Write leveling (Byte 1): 30 => 30
4583 09:32:23.781287 DramcWriteLeveling(PI) end<-----
4584 09:32:23.784295
4585 09:32:23.784393 ==
4586 09:32:23.787774 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 09:32:23.791275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 09:32:23.791389 ==
4589 09:32:23.794723 [Gating] SW mode calibration
4590 09:32:23.801540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 09:32:23.804254 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 09:32:23.811041 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 09:32:23.814408 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 09:32:23.817688 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4595 09:32:23.824628 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4596 09:32:23.828013 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4597 09:32:23.831449 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 09:32:23.837778 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 09:32:23.841284 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 09:32:23.844509 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 09:32:23.850961 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 09:32:23.854342 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4603 09:32:23.857624 0 10 12 | B1->B0 | 3a3a 3636 | 1 1 | (0 0) (0 0)
4604 09:32:23.864350 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 09:32:23.867833 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 09:32:23.871276 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 09:32:23.877431 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 09:32:23.880880 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 09:32:23.884300 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 09:32:23.891095 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 09:32:23.894498 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4612 09:32:23.897623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 09:32:23.904185 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 09:32:23.907263 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 09:32:23.910903 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 09:32:23.914516 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 09:32:23.921231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 09:32:23.924598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 09:32:23.927750 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 09:32:23.934261 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 09:32:23.937586 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 09:32:23.940850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 09:32:23.947690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 09:32:23.950986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 09:32:23.954285 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 09:32:23.960959 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4627 09:32:23.964172 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 09:32:23.967631 Total UI for P1: 0, mck2ui 16
4629 09:32:23.970978 best dqsien dly found for B0: ( 0, 13, 8)
4630 09:32:23.974247 Total UI for P1: 0, mck2ui 16
4631 09:32:23.977542 best dqsien dly found for B1: ( 0, 13, 8)
4632 09:32:23.981350 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4633 09:32:23.984115 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4634 09:32:23.984225
4635 09:32:23.987683 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4636 09:32:23.990905 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4637 09:32:23.994060 [Gating] SW calibration Done
4638 09:32:23.994153 ==
4639 09:32:23.998058 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 09:32:24.000784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 09:32:24.000866 ==
4642 09:32:24.004646 RX Vref Scan: 0
4643 09:32:24.004730
4644 09:32:24.007899 RX Vref 0 -> 0, step: 1
4645 09:32:24.008009
4646 09:32:24.008104 RX Delay -230 -> 252, step: 16
4647 09:32:24.014359 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4648 09:32:24.017677 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4649 09:32:24.020591 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4650 09:32:24.023982 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4651 09:32:24.030927 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4652 09:32:24.034270 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4653 09:32:24.037424 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4654 09:32:24.040620 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4655 09:32:24.044335 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4656 09:32:24.050544 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4657 09:32:24.054447 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4658 09:32:24.057138 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4659 09:32:24.060947 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4660 09:32:24.067547 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4661 09:32:24.071014 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4662 09:32:24.074356 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4663 09:32:24.074431 ==
4664 09:32:24.077660 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 09:32:24.081089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 09:32:24.081176 ==
4667 09:32:24.084275 DQS Delay:
4668 09:32:24.084347 DQS0 = 0, DQS1 = 0
4669 09:32:24.087568 DQM Delay:
4670 09:32:24.087660 DQM0 = 48, DQM1 = 48
4671 09:32:24.087729 DQ Delay:
4672 09:32:24.090784 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4673 09:32:24.094328 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4674 09:32:24.097493 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4675 09:32:24.100653 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4676 09:32:24.100736
4677 09:32:24.100802
4678 09:32:24.104297 ==
4679 09:32:24.107377 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 09:32:24.110778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 09:32:24.110861 ==
4682 09:32:24.110927
4683 09:32:24.110988
4684 09:32:24.114104 TX Vref Scan disable
4685 09:32:24.114188 == TX Byte 0 ==
4686 09:32:24.117703 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4687 09:32:24.124348 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4688 09:32:24.124433 == TX Byte 1 ==
4689 09:32:24.127652 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4690 09:32:24.133769 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4691 09:32:24.133885 ==
4692 09:32:24.137277 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 09:32:24.140699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 09:32:24.140783 ==
4695 09:32:24.140849
4696 09:32:24.140911
4697 09:32:24.144030 TX Vref Scan disable
4698 09:32:24.147267 == TX Byte 0 ==
4699 09:32:24.150469 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 09:32:24.154207 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 09:32:24.157426 == TX Byte 1 ==
4702 09:32:24.160921 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 09:32:24.164249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 09:32:24.164333
4705 09:32:24.167528 [DATLAT]
4706 09:32:24.167611 Freq=600, CH1 RK1
4707 09:32:24.167686
4708 09:32:24.170755 DATLAT Default: 0x9
4709 09:32:24.170837 0, 0xFFFF, sum = 0
4710 09:32:24.174098 1, 0xFFFF, sum = 0
4711 09:32:24.174182 2, 0xFFFF, sum = 0
4712 09:32:24.176966 3, 0xFFFF, sum = 0
4713 09:32:24.177051 4, 0xFFFF, sum = 0
4714 09:32:24.180282 5, 0xFFFF, sum = 0
4715 09:32:24.180367 6, 0xFFFF, sum = 0
4716 09:32:24.183672 7, 0xFFFF, sum = 0
4717 09:32:24.183756 8, 0x0, sum = 1
4718 09:32:24.187086 9, 0x0, sum = 2
4719 09:32:24.187171 10, 0x0, sum = 3
4720 09:32:24.190615 11, 0x0, sum = 4
4721 09:32:24.190697 best_step = 9
4722 09:32:24.190762
4723 09:32:24.190822 ==
4724 09:32:24.193952 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 09:32:24.197162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 09:32:24.200254 ==
4727 09:32:24.200334 RX Vref Scan: 0
4728 09:32:24.200428
4729 09:32:24.203518 RX Vref 0 -> 0, step: 1
4730 09:32:24.203628
4731 09:32:24.206872 RX Delay -163 -> 252, step: 8
4732 09:32:24.210235 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4733 09:32:24.213582 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4734 09:32:24.220311 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4735 09:32:24.223521 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4736 09:32:24.226555 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4737 09:32:24.230536 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4738 09:32:24.233875 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4739 09:32:24.240397 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4740 09:32:24.243515 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4741 09:32:24.246881 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4742 09:32:24.250238 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4743 09:32:24.253367 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4744 09:32:24.259867 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4745 09:32:24.263608 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4746 09:32:24.266830 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4747 09:32:24.270079 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4748 09:32:24.270161 ==
4749 09:32:24.273325 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 09:32:24.279824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 09:32:24.279906 ==
4752 09:32:24.279975 DQS Delay:
4753 09:32:24.283031 DQS0 = 0, DQS1 = 0
4754 09:32:24.283137 DQM Delay:
4755 09:32:24.283229 DQM0 = 49, DQM1 = 45
4756 09:32:24.286530 DQ Delay:
4757 09:32:24.289860 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4758 09:32:24.293194 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4759 09:32:24.296704 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4760 09:32:24.299973 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4761 09:32:24.300079
4762 09:32:24.300170
4763 09:32:24.306860 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4764 09:32:24.310226 CH1 RK1: MR19=808, MR18=6921
4765 09:32:24.316388 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4766 09:32:24.319659 [RxdqsGatingPostProcess] freq 600
4767 09:32:24.322963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4768 09:32:24.326214 Pre-setting of DQS Precalculation
4769 09:32:24.333089 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4770 09:32:24.339845 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4771 09:32:24.346843 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4772 09:32:24.346951
4773 09:32:24.347043
4774 09:32:24.350079 [Calibration Summary] 1200 Mbps
4775 09:32:24.350177 CH 0, Rank 0
4776 09:32:24.353415 SW Impedance : PASS
4777 09:32:24.356381 DUTY Scan : NO K
4778 09:32:24.356495 ZQ Calibration : PASS
4779 09:32:24.359731 Jitter Meter : NO K
4780 09:32:24.363250 CBT Training : PASS
4781 09:32:24.363354 Write leveling : PASS
4782 09:32:24.366542 RX DQS gating : PASS
4783 09:32:24.369627 RX DQ/DQS(RDDQC) : PASS
4784 09:32:24.369703 TX DQ/DQS : PASS
4785 09:32:24.373259 RX DATLAT : PASS
4786 09:32:24.373330 RX DQ/DQS(Engine): PASS
4787 09:32:24.376539 TX OE : NO K
4788 09:32:24.376663 All Pass.
4789 09:32:24.376769
4790 09:32:24.379632 CH 0, Rank 1
4791 09:32:24.379742 SW Impedance : PASS
4792 09:32:24.383335 DUTY Scan : NO K
4793 09:32:24.386706 ZQ Calibration : PASS
4794 09:32:24.386820 Jitter Meter : NO K
4795 09:32:24.390083 CBT Training : PASS
4796 09:32:24.393335 Write leveling : PASS
4797 09:32:24.393440 RX DQS gating : PASS
4798 09:32:24.396687 RX DQ/DQS(RDDQC) : PASS
4799 09:32:24.399990 TX DQ/DQS : PASS
4800 09:32:24.400095 RX DATLAT : PASS
4801 09:32:24.402801 RX DQ/DQS(Engine): PASS
4802 09:32:24.406189 TX OE : NO K
4803 09:32:24.406295 All Pass.
4804 09:32:24.406393
4805 09:32:24.406495 CH 1, Rank 0
4806 09:32:24.409538 SW Impedance : PASS
4807 09:32:24.412761 DUTY Scan : NO K
4808 09:32:24.412864 ZQ Calibration : PASS
4809 09:32:24.415847 Jitter Meter : NO K
4810 09:32:24.419772 CBT Training : PASS
4811 09:32:24.419874 Write leveling : PASS
4812 09:32:24.422536 RX DQS gating : PASS
4813 09:32:24.425864 RX DQ/DQS(RDDQC) : PASS
4814 09:32:24.425965 TX DQ/DQS : PASS
4815 09:32:24.429778 RX DATLAT : PASS
4816 09:32:24.429879 RX DQ/DQS(Engine): PASS
4817 09:32:24.432441 TX OE : NO K
4818 09:32:24.432516 All Pass.
4819 09:32:24.432625
4820 09:32:24.435875 CH 1, Rank 1
4821 09:32:24.435967 SW Impedance : PASS
4822 09:32:24.439149 DUTY Scan : NO K
4823 09:32:24.442328 ZQ Calibration : PASS
4824 09:32:24.442431 Jitter Meter : NO K
4825 09:32:24.446016 CBT Training : PASS
4826 09:32:24.449362 Write leveling : PASS
4827 09:32:24.449467 RX DQS gating : PASS
4828 09:32:24.452749 RX DQ/DQS(RDDQC) : PASS
4829 09:32:24.456055 TX DQ/DQS : PASS
4830 09:32:24.456141 RX DATLAT : PASS
4831 09:32:24.458776 RX DQ/DQS(Engine): PASS
4832 09:32:24.462679 TX OE : NO K
4833 09:32:24.462786 All Pass.
4834 09:32:24.462856
4835 09:32:24.465851 DramC Write-DBI off
4836 09:32:24.465961 PER_BANK_REFRESH: Hybrid Mode
4837 09:32:24.468945 TX_TRACKING: ON
4838 09:32:24.478812 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4839 09:32:24.481998 [FAST_K] Save calibration result to emmc
4840 09:32:24.485179 dramc_set_vcore_voltage set vcore to 662500
4841 09:32:24.485279 Read voltage for 933, 3
4842 09:32:24.489011 Vio18 = 0
4843 09:32:24.489120 Vcore = 662500
4844 09:32:24.489251 Vdram = 0
4845 09:32:24.492083 Vddq = 0
4846 09:32:24.492182 Vmddr = 0
4847 09:32:24.495715 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4848 09:32:24.502070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4849 09:32:24.505249 MEM_TYPE=3, freq_sel=17
4850 09:32:24.508565 sv_algorithm_assistance_LP4_1600
4851 09:32:24.511930 ============ PULL DRAM RESETB DOWN ============
4852 09:32:24.515150 ========== PULL DRAM RESETB DOWN end =========
4853 09:32:24.521702 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4854 09:32:24.525033 ===================================
4855 09:32:24.525142 LPDDR4 DRAM CONFIGURATION
4856 09:32:24.528348 ===================================
4857 09:32:24.531790 EX_ROW_EN[0] = 0x0
4858 09:32:24.531914 EX_ROW_EN[1] = 0x0
4859 09:32:24.535079 LP4Y_EN = 0x0
4860 09:32:24.535151 WORK_FSP = 0x0
4861 09:32:24.538368 WL = 0x3
4862 09:32:24.541819 RL = 0x3
4863 09:32:24.541956 BL = 0x2
4864 09:32:24.545093 RPST = 0x0
4865 09:32:24.545189 RD_PRE = 0x0
4866 09:32:24.548358 WR_PRE = 0x1
4867 09:32:24.548456 WR_PST = 0x0
4868 09:32:24.551574 DBI_WR = 0x0
4869 09:32:24.551694 DBI_RD = 0x0
4870 09:32:24.554963 OTF = 0x1
4871 09:32:24.558551 ===================================
4872 09:32:24.561601 ===================================
4873 09:32:24.561720 ANA top config
4874 09:32:24.564989 ===================================
4875 09:32:24.568284 DLL_ASYNC_EN = 0
4876 09:32:24.571592 ALL_SLAVE_EN = 1
4877 09:32:24.571703 NEW_RANK_MODE = 1
4878 09:32:24.575324 DLL_IDLE_MODE = 1
4879 09:32:24.578311 LP45_APHY_COMB_EN = 1
4880 09:32:24.582034 TX_ODT_DIS = 1
4881 09:32:24.582136 NEW_8X_MODE = 1
4882 09:32:24.585070 ===================================
4883 09:32:24.588514 ===================================
4884 09:32:24.591691 data_rate = 1866
4885 09:32:24.594973 CKR = 1
4886 09:32:24.598303 DQ_P2S_RATIO = 8
4887 09:32:24.601469 ===================================
4888 09:32:24.605136 CA_P2S_RATIO = 8
4889 09:32:24.608171 DQ_CA_OPEN = 0
4890 09:32:24.608251 DQ_SEMI_OPEN = 0
4891 09:32:24.611560 CA_SEMI_OPEN = 0
4892 09:32:24.615022 CA_FULL_RATE = 0
4893 09:32:24.618365 DQ_CKDIV4_EN = 1
4894 09:32:24.621682 CA_CKDIV4_EN = 1
4895 09:32:24.624669 CA_PREDIV_EN = 0
4896 09:32:24.624754 PH8_DLY = 0
4897 09:32:24.628106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4898 09:32:24.631359 DQ_AAMCK_DIV = 4
4899 09:32:24.634705 CA_AAMCK_DIV = 4
4900 09:32:24.638066 CA_ADMCK_DIV = 4
4901 09:32:24.641719 DQ_TRACK_CA_EN = 0
4902 09:32:24.645159 CA_PICK = 933
4903 09:32:24.645244 CA_MCKIO = 933
4904 09:32:24.648495 MCKIO_SEMI = 0
4905 09:32:24.651780 PLL_FREQ = 3732
4906 09:32:24.655273 DQ_UI_PI_RATIO = 32
4907 09:32:24.658522 CA_UI_PI_RATIO = 0
4908 09:32:24.661716 ===================================
4909 09:32:24.664768 ===================================
4910 09:32:24.668475 memory_type:LPDDR4
4911 09:32:24.668559 GP_NUM : 10
4912 09:32:24.671575 SRAM_EN : 1
4913 09:32:24.671692 MD32_EN : 0
4914 09:32:24.674974 ===================================
4915 09:32:24.678308 [ANA_INIT] >>>>>>>>>>>>>>
4916 09:32:24.681568 <<<<<< [CONFIGURE PHASE]: ANA_TX
4917 09:32:24.684986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4918 09:32:24.688104 ===================================
4919 09:32:24.691205 data_rate = 1866,PCW = 0X8f00
4920 09:32:24.694709 ===================================
4921 09:32:24.697678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4922 09:32:24.701504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 09:32:24.708119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 09:32:24.714578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4925 09:32:24.717642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4926 09:32:24.721688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4927 09:32:24.721839 [ANA_INIT] flow start
4928 09:32:24.724874 [ANA_INIT] PLL >>>>>>>>
4929 09:32:24.728214 [ANA_INIT] PLL <<<<<<<<
4930 09:32:24.728367 [ANA_INIT] MIDPI >>>>>>>>
4931 09:32:24.731343 [ANA_INIT] MIDPI <<<<<<<<
4932 09:32:24.734756 [ANA_INIT] DLL >>>>>>>>
4933 09:32:24.734902 [ANA_INIT] flow end
4934 09:32:24.738135 ============ LP4 DIFF to SE enter ============
4935 09:32:24.744815 ============ LP4 DIFF to SE exit ============
4936 09:32:24.744977 [ANA_INIT] <<<<<<<<<<<<<
4937 09:32:24.747536 [Flow] Enable top DCM control >>>>>
4938 09:32:24.751001 [Flow] Enable top DCM control <<<<<
4939 09:32:24.754298 Enable DLL master slave shuffle
4940 09:32:24.761028 ==============================================================
4941 09:32:24.764607 Gating Mode config
4942 09:32:24.767592 ==============================================================
4943 09:32:24.770985 Config description:
4944 09:32:24.781028 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4945 09:32:24.787556 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4946 09:32:24.790923 SELPH_MODE 0: By rank 1: By Phase
4947 09:32:24.797599 ==============================================================
4948 09:32:24.800810 GAT_TRACK_EN = 1
4949 09:32:24.804361 RX_GATING_MODE = 2
4950 09:32:24.804471 RX_GATING_TRACK_MODE = 2
4951 09:32:24.807998 SELPH_MODE = 1
4952 09:32:24.811201 PICG_EARLY_EN = 1
4953 09:32:24.814370 VALID_LAT_VALUE = 1
4954 09:32:24.820839 ==============================================================
4955 09:32:24.824617 Enter into Gating configuration >>>>
4956 09:32:24.827700 Exit from Gating configuration <<<<
4957 09:32:24.831058 Enter into DVFS_PRE_config >>>>>
4958 09:32:24.841070 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4959 09:32:24.844469 Exit from DVFS_PRE_config <<<<<
4960 09:32:24.847827 Enter into PICG configuration >>>>
4961 09:32:24.851259 Exit from PICG configuration <<<<
4962 09:32:24.853874 [RX_INPUT] configuration >>>>>
4963 09:32:24.857256 [RX_INPUT] configuration <<<<<
4964 09:32:24.860635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4965 09:32:24.867898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4966 09:32:24.874471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 09:32:24.877928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 09:32:24.884423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 09:32:24.891006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 09:32:24.894237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4971 09:32:24.900457 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4972 09:32:24.904045 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4973 09:32:24.907377 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4974 09:32:24.910543 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4975 09:32:24.917289 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 09:32:24.920253 ===================================
4977 09:32:24.920419 LPDDR4 DRAM CONFIGURATION
4978 09:32:24.923378 ===================================
4979 09:32:24.926918 EX_ROW_EN[0] = 0x0
4980 09:32:24.930269 EX_ROW_EN[1] = 0x0
4981 09:32:24.930352 LP4Y_EN = 0x0
4982 09:32:24.933368 WORK_FSP = 0x0
4983 09:32:24.933472 WL = 0x3
4984 09:32:24.937118 RL = 0x3
4985 09:32:24.937200 BL = 0x2
4986 09:32:24.940391 RPST = 0x0
4987 09:32:24.940508 RD_PRE = 0x0
4988 09:32:24.943578 WR_PRE = 0x1
4989 09:32:24.943714 WR_PST = 0x0
4990 09:32:24.946851 DBI_WR = 0x0
4991 09:32:24.946938 DBI_RD = 0x0
4992 09:32:24.950068 OTF = 0x1
4993 09:32:24.953267 ===================================
4994 09:32:24.956929 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4995 09:32:24.960427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4996 09:32:24.966260 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 09:32:24.969613 ===================================
4998 09:32:24.972997 LPDDR4 DRAM CONFIGURATION
4999 09:32:24.973084 ===================================
5000 09:32:24.976295 EX_ROW_EN[0] = 0x10
5001 09:32:24.979846 EX_ROW_EN[1] = 0x0
5002 09:32:24.979936 LP4Y_EN = 0x0
5003 09:32:24.983151 WORK_FSP = 0x0
5004 09:32:24.983233 WL = 0x3
5005 09:32:24.986479 RL = 0x3
5006 09:32:24.986605 BL = 0x2
5007 09:32:24.989817 RPST = 0x0
5008 09:32:24.989900 RD_PRE = 0x0
5009 09:32:24.993076 WR_PRE = 0x1
5010 09:32:24.993159 WR_PST = 0x0
5011 09:32:24.996130 DBI_WR = 0x0
5012 09:32:24.996213 DBI_RD = 0x0
5013 09:32:24.999244 OTF = 0x1
5014 09:32:25.002803 ===================================
5015 09:32:25.009170 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5016 09:32:25.012641 nWR fixed to 30
5017 09:32:25.015983 [ModeRegInit_LP4] CH0 RK0
5018 09:32:25.016068 [ModeRegInit_LP4] CH0 RK1
5019 09:32:25.019228 [ModeRegInit_LP4] CH1 RK0
5020 09:32:25.023041 [ModeRegInit_LP4] CH1 RK1
5021 09:32:25.023146 match AC timing 9
5022 09:32:25.029406 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5023 09:32:25.032771 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5024 09:32:25.036243 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5025 09:32:25.042673 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5026 09:32:25.046286 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5027 09:32:25.046389 ==
5028 09:32:25.049464 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 09:32:25.052509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5030 09:32:25.052594 ==
5031 09:32:25.059169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5032 09:32:25.065852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5033 09:32:25.069042 [CA 0] Center 37 (6~68) winsize 63
5034 09:32:25.072360 [CA 1] Center 37 (7~68) winsize 62
5035 09:32:25.075852 [CA 2] Center 34 (4~65) winsize 62
5036 09:32:25.079382 [CA 3] Center 34 (3~65) winsize 63
5037 09:32:25.082536 [CA 4] Center 33 (3~63) winsize 61
5038 09:32:25.085984 [CA 5] Center 32 (2~62) winsize 61
5039 09:32:25.086184
5040 09:32:25.089306 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5041 09:32:25.089388
5042 09:32:25.092728 [CATrainingPosCal] consider 1 rank data
5043 09:32:25.096080 u2DelayCellTimex100 = 270/100 ps
5044 09:32:25.098774 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5045 09:32:25.102256 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 09:32:25.105994 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5047 09:32:25.109166 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5048 09:32:25.112191 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5049 09:32:25.115533 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5050 09:32:25.119401
5051 09:32:25.122794 CA PerBit enable=1, Macro0, CA PI delay=32
5052 09:32:25.122884
5053 09:32:25.125966 [CBTSetCACLKResult] CA Dly = 32
5054 09:32:25.126051 CS Dly: 5 (0~36)
5055 09:32:25.126120 ==
5056 09:32:25.129170 Dram Type= 6, Freq= 0, CH_0, rank 1
5057 09:32:25.132407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 09:32:25.132489 ==
5059 09:32:25.138954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 09:32:25.145698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5061 09:32:25.149074 [CA 0] Center 37 (6~68) winsize 63
5062 09:32:25.152336 [CA 1] Center 37 (6~68) winsize 63
5063 09:32:25.155775 [CA 2] Center 34 (4~65) winsize 62
5064 09:32:25.159109 [CA 3] Center 34 (3~65) winsize 63
5065 09:32:25.162249 [CA 4] Center 32 (2~63) winsize 62
5066 09:32:25.165913 [CA 5] Center 32 (2~62) winsize 61
5067 09:32:25.165997
5068 09:32:25.168961 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5069 09:32:25.169070
5070 09:32:25.172746 [CATrainingPosCal] consider 2 rank data
5071 09:32:25.175529 u2DelayCellTimex100 = 270/100 ps
5072 09:32:25.179355 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5073 09:32:25.182596 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 09:32:25.185848 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5075 09:32:25.189170 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5076 09:32:25.192402 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5077 09:32:25.199021 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5078 09:32:25.199102
5079 09:32:25.202373 CA PerBit enable=1, Macro0, CA PI delay=32
5080 09:32:25.202456
5081 09:32:25.205803 [CBTSetCACLKResult] CA Dly = 32
5082 09:32:25.205886 CS Dly: 5 (0~37)
5083 09:32:25.205952
5084 09:32:25.209184 ----->DramcWriteLeveling(PI) begin...
5085 09:32:25.209267 ==
5086 09:32:25.212533 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 09:32:25.215983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 09:32:25.219178 ==
5089 09:32:25.222345 Write leveling (Byte 0): 31 => 31
5090 09:32:25.222427 Write leveling (Byte 1): 30 => 30
5091 09:32:25.225549 DramcWriteLeveling(PI) end<-----
5092 09:32:25.225631
5093 09:32:25.225696 ==
5094 09:32:25.228918 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 09:32:25.235863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 09:32:25.235946 ==
5097 09:32:25.239100 [Gating] SW mode calibration
5098 09:32:25.245277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5099 09:32:25.248666 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5100 09:32:25.255298 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5101 09:32:25.258671 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 09:32:25.261955 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 09:32:25.268712 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 09:32:25.271974 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 09:32:25.275312 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 09:32:25.282145 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5107 09:32:25.285313 0 14 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5108 09:32:25.288636 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5109 09:32:25.292197 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 09:32:25.298625 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 09:32:25.302190 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 09:32:25.305641 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 09:32:25.312392 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 09:32:25.315915 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5115 09:32:25.319119 0 15 28 | B1->B0 | 2929 3d3d | 0 1 | (1 1) (0 0)
5116 09:32:25.325841 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5117 09:32:25.328464 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 09:32:25.332011 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 09:32:25.338495 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 09:32:25.342089 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 09:32:25.345489 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 09:32:25.352261 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 09:32:25.355313 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 09:32:25.358371 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 09:32:25.365526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 09:32:25.368925 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 09:32:25.372302 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 09:32:25.379075 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 09:32:25.381784 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 09:32:25.385185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 09:32:25.388660 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 09:32:25.395296 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 09:32:25.398727 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 09:32:25.401970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 09:32:25.408437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 09:32:25.412009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 09:32:25.415528 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 09:32:25.422237 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 09:32:25.424881 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5140 09:32:25.428284 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 09:32:25.431566 Total UI for P1: 0, mck2ui 16
5142 09:32:25.435037 best dqsien dly found for B0: ( 1, 2, 24)
5143 09:32:25.438529 Total UI for P1: 0, mck2ui 16
5144 09:32:25.441849 best dqsien dly found for B1: ( 1, 2, 28)
5145 09:32:25.445286 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5146 09:32:25.448642 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5147 09:32:25.448724
5148 09:32:25.454909 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5149 09:32:25.458618 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5150 09:32:25.458694 [Gating] SW calibration Done
5151 09:32:25.461561 ==
5152 09:32:25.465082 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 09:32:25.468441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 09:32:25.468516 ==
5155 09:32:25.468579 RX Vref Scan: 0
5156 09:32:25.468639
5157 09:32:25.471788 RX Vref 0 -> 0, step: 1
5158 09:32:25.471860
5159 09:32:25.475425 RX Delay -80 -> 252, step: 8
5160 09:32:25.478278 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5161 09:32:25.481879 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5162 09:32:25.485022 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5163 09:32:25.491629 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5164 09:32:25.494891 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5165 09:32:25.498285 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5166 09:32:25.501489 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5167 09:32:25.504974 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5168 09:32:25.508384 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5169 09:32:25.515450 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5170 09:32:25.518658 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5171 09:32:25.522035 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5172 09:32:25.525146 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5173 09:32:25.528412 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5174 09:32:25.531566 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5175 09:32:25.538726 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5176 09:32:25.538805 ==
5177 09:32:25.541487 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 09:32:25.544895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 09:32:25.544985 ==
5180 09:32:25.545064 DQS Delay:
5181 09:32:25.548402 DQS0 = 0, DQS1 = 0
5182 09:32:25.548476 DQM Delay:
5183 09:32:25.551688 DQM0 = 103, DQM1 = 94
5184 09:32:25.551807 DQ Delay:
5185 09:32:25.555011 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5186 09:32:25.558368 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =115
5187 09:32:25.561718 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5188 09:32:25.564828 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5189 09:32:25.564913
5190 09:32:25.564984
5191 09:32:25.565045 ==
5192 09:32:25.568170 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 09:32:25.574866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 09:32:25.574970 ==
5195 09:32:25.575063
5196 09:32:25.575165
5197 09:32:25.575252 TX Vref Scan disable
5198 09:32:25.577957 == TX Byte 0 ==
5199 09:32:25.581198 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5200 09:32:25.584565 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5201 09:32:25.587842 == TX Byte 1 ==
5202 09:32:25.591518 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5203 09:32:25.594599 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5204 09:32:25.598301 ==
5205 09:32:25.601135 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 09:32:25.605000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 09:32:25.605111 ==
5208 09:32:25.605206
5209 09:32:25.605296
5210 09:32:25.607774 TX Vref Scan disable
5211 09:32:25.607877 == TX Byte 0 ==
5212 09:32:25.614775 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5213 09:32:25.618126 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5214 09:32:25.618237 == TX Byte 1 ==
5215 09:32:25.624887 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5216 09:32:25.628283 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5217 09:32:25.628384
5218 09:32:25.628476 [DATLAT]
5219 09:32:25.631528 Freq=933, CH0 RK0
5220 09:32:25.631657
5221 09:32:25.631766 DATLAT Default: 0xd
5222 09:32:25.634958 0, 0xFFFF, sum = 0
5223 09:32:25.635075 1, 0xFFFF, sum = 0
5224 09:32:25.637784 2, 0xFFFF, sum = 0
5225 09:32:25.637871 3, 0xFFFF, sum = 0
5226 09:32:25.641064 4, 0xFFFF, sum = 0
5227 09:32:25.641153 5, 0xFFFF, sum = 0
5228 09:32:25.644496 6, 0xFFFF, sum = 0
5229 09:32:25.644577 7, 0xFFFF, sum = 0
5230 09:32:25.648185 8, 0xFFFF, sum = 0
5231 09:32:25.648305 9, 0xFFFF, sum = 0
5232 09:32:25.651469 10, 0x0, sum = 1
5233 09:32:25.651606 11, 0x0, sum = 2
5234 09:32:25.654904 12, 0x0, sum = 3
5235 09:32:25.654985 13, 0x0, sum = 4
5236 09:32:25.658266 best_step = 11
5237 09:32:25.658342
5238 09:32:25.658406 ==
5239 09:32:25.661519 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 09:32:25.664946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 09:32:25.665019 ==
5242 09:32:25.667584 RX Vref Scan: 1
5243 09:32:25.667687
5244 09:32:25.667762 RX Vref 0 -> 0, step: 1
5245 09:32:25.667824
5246 09:32:25.670987 RX Delay -45 -> 252, step: 4
5247 09:32:25.671062
5248 09:32:25.674344 Set Vref, RX VrefLevel [Byte0]: 55
5249 09:32:25.677654 [Byte1]: 47
5250 09:32:25.681530
5251 09:32:25.681605 Final RX Vref Byte 0 = 55 to rank0
5252 09:32:25.685206 Final RX Vref Byte 1 = 47 to rank0
5253 09:32:25.688590 Final RX Vref Byte 0 = 55 to rank1
5254 09:32:25.691402 Final RX Vref Byte 1 = 47 to rank1==
5255 09:32:25.694782 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 09:32:25.701345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 09:32:25.701435 ==
5258 09:32:25.701509 DQS Delay:
5259 09:32:25.701572 DQS0 = 0, DQS1 = 0
5260 09:32:25.704692 DQM Delay:
5261 09:32:25.704799 DQM0 = 104, DQM1 = 95
5262 09:32:25.708234 DQ Delay:
5263 09:32:25.711680 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5264 09:32:25.714698 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5265 09:32:25.718491 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5266 09:32:25.721967 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5267 09:32:25.722051
5268 09:32:25.722118
5269 09:32:25.727948 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5270 09:32:25.731380 CH0 RK0: MR19=505, MR18=3028
5271 09:32:25.738306 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5272 09:32:25.738392
5273 09:32:25.741696 ----->DramcWriteLeveling(PI) begin...
5274 09:32:25.741781 ==
5275 09:32:25.745197 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 09:32:25.748430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 09:32:25.751315 ==
5278 09:32:25.751399 Write leveling (Byte 0): 35 => 35
5279 09:32:25.754550 Write leveling (Byte 1): 26 => 26
5280 09:32:25.758408 DramcWriteLeveling(PI) end<-----
5281 09:32:25.758493
5282 09:32:25.758565 ==
5283 09:32:25.761557 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 09:32:25.768129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 09:32:25.768252 ==
5286 09:32:25.768334 [Gating] SW mode calibration
5287 09:32:25.778112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 09:32:25.781329 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 09:32:25.784914 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5290 09:32:25.791266 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 09:32:25.794744 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 09:32:25.797998 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 09:32:25.805120 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 09:32:25.808437 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 09:32:25.811103 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5296 09:32:25.818245 0 14 28 | B1->B0 | 2727 2f2f | 0 0 | (1 0) (0 0)
5297 09:32:25.821362 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5298 09:32:25.824508 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 09:32:25.831218 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 09:32:25.834347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 09:32:25.837969 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 09:32:25.844362 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 09:32:25.847714 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5304 09:32:25.851150 0 15 28 | B1->B0 | 3636 3636 | 0 0 | (1 1) (0 0)
5305 09:32:25.857871 1 0 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
5306 09:32:25.861370 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 09:32:25.864677 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 09:32:25.871316 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 09:32:25.874517 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 09:32:25.877991 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 09:32:25.884370 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5312 09:32:25.887912 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5313 09:32:25.891019 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 09:32:25.897430 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 09:32:25.900843 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 09:32:25.904229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 09:32:25.911083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 09:32:25.914485 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 09:32:25.917824 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 09:32:25.924411 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 09:32:25.927795 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 09:32:25.931079 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 09:32:25.934001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 09:32:25.941001 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 09:32:25.944031 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 09:32:25.947288 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 09:32:25.954023 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 09:32:25.957325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5329 09:32:25.960930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 09:32:25.964035 Total UI for P1: 0, mck2ui 16
5331 09:32:25.967384 best dqsien dly found for B0: ( 1, 2, 28)
5332 09:32:25.970779 Total UI for P1: 0, mck2ui 16
5333 09:32:25.973752 best dqsien dly found for B1: ( 1, 2, 28)
5334 09:32:25.977260 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5335 09:32:25.980647 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5336 09:32:25.984093
5337 09:32:25.987351 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5338 09:32:25.990504 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5339 09:32:25.993807 [Gating] SW calibration Done
5340 09:32:25.993889 ==
5341 09:32:25.996924 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 09:32:26.000800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 09:32:26.000904 ==
5344 09:32:26.000997 RX Vref Scan: 0
5345 09:32:26.001087
5346 09:32:26.003699 RX Vref 0 -> 0, step: 1
5347 09:32:26.003775
5348 09:32:26.007096 RX Delay -80 -> 252, step: 8
5349 09:32:26.010312 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5350 09:32:26.013660 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5351 09:32:26.020615 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5352 09:32:26.024108 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5353 09:32:26.027387 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5354 09:32:26.030803 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5355 09:32:26.033560 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5356 09:32:26.036855 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5357 09:32:26.043845 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5358 09:32:26.047294 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5359 09:32:26.050583 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5360 09:32:26.053987 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5361 09:32:26.056702 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5362 09:32:26.060118 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5363 09:32:26.067137 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5364 09:32:26.070169 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5365 09:32:26.070285 ==
5366 09:32:26.073632 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 09:32:26.077179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 09:32:26.077305 ==
5369 09:32:26.077400 DQS Delay:
5370 09:32:26.080462 DQS0 = 0, DQS1 = 0
5371 09:32:26.080537 DQM Delay:
5372 09:32:26.083502 DQM0 = 103, DQM1 = 93
5373 09:32:26.083609 DQ Delay:
5374 09:32:26.086854 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5375 09:32:26.090330 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5376 09:32:26.093516 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5377 09:32:26.096740 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5378 09:32:26.096819
5379 09:32:26.096885
5380 09:32:26.096946 ==
5381 09:32:26.100111 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 09:32:26.106706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 09:32:26.106794 ==
5384 09:32:26.106860
5385 09:32:26.106921
5386 09:32:26.106980 TX Vref Scan disable
5387 09:32:26.110089 == TX Byte 0 ==
5388 09:32:26.113360 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5389 09:32:26.120055 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5390 09:32:26.120137 == TX Byte 1 ==
5391 09:32:26.123226 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5392 09:32:26.130099 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5393 09:32:26.130222 ==
5394 09:32:26.133415 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 09:32:26.136757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 09:32:26.136841 ==
5397 09:32:26.136908
5398 09:32:26.136970
5399 09:32:26.139790 TX Vref Scan disable
5400 09:32:26.143030 == TX Byte 0 ==
5401 09:32:26.146548 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5402 09:32:26.149871 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5403 09:32:26.153086 == TX Byte 1 ==
5404 09:32:26.156430 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5405 09:32:26.159602 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5406 09:32:26.159700
5407 09:32:26.159767 [DATLAT]
5408 09:32:26.163092 Freq=933, CH0 RK1
5409 09:32:26.163195
5410 09:32:26.166524 DATLAT Default: 0xb
5411 09:32:26.166600 0, 0xFFFF, sum = 0
5412 09:32:26.170075 1, 0xFFFF, sum = 0
5413 09:32:26.170163 2, 0xFFFF, sum = 0
5414 09:32:26.172851 3, 0xFFFF, sum = 0
5415 09:32:26.172938 4, 0xFFFF, sum = 0
5416 09:32:26.176356 5, 0xFFFF, sum = 0
5417 09:32:26.176442 6, 0xFFFF, sum = 0
5418 09:32:26.179666 7, 0xFFFF, sum = 0
5419 09:32:26.179781 8, 0xFFFF, sum = 0
5420 09:32:26.182849 9, 0xFFFF, sum = 0
5421 09:32:26.182964 10, 0x0, sum = 1
5422 09:32:26.185992 11, 0x0, sum = 2
5423 09:32:26.186106 12, 0x0, sum = 3
5424 09:32:26.189740 13, 0x0, sum = 4
5425 09:32:26.189855 best_step = 11
5426 09:32:26.189942
5427 09:32:26.190024 ==
5428 09:32:26.193533 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 09:32:26.196604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 09:32:26.196718 ==
5431 09:32:26.199741 RX Vref Scan: 0
5432 09:32:26.199859
5433 09:32:26.202622 RX Vref 0 -> 0, step: 1
5434 09:32:26.202734
5435 09:32:26.202804 RX Delay -53 -> 252, step: 4
5436 09:32:26.210358 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5437 09:32:26.213730 iDelay=195, Bit 1, Center 106 (23 ~ 190) 168
5438 09:32:26.217616 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5439 09:32:26.221011 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5440 09:32:26.224298 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5441 09:32:26.231016 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5442 09:32:26.234322 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5443 09:32:26.237074 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5444 09:32:26.240853 iDelay=195, Bit 8, Center 86 (3 ~ 170) 168
5445 09:32:26.243916 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5446 09:32:26.247393 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5447 09:32:26.254089 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5448 09:32:26.257094 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5449 09:32:26.260516 iDelay=195, Bit 13, Center 100 (19 ~ 182) 164
5450 09:32:26.263915 iDelay=195, Bit 14, Center 104 (23 ~ 186) 164
5451 09:32:26.270830 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5452 09:32:26.270940 ==
5453 09:32:26.274341 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 09:32:26.277111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 09:32:26.277187 ==
5456 09:32:26.277251 DQS Delay:
5457 09:32:26.280542 DQS0 = 0, DQS1 = 0
5458 09:32:26.280614 DQM Delay:
5459 09:32:26.283783 DQM0 = 104, DQM1 = 94
5460 09:32:26.283854 DQ Delay:
5461 09:32:26.287200 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5462 09:32:26.290347 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =110
5463 09:32:26.293811 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5464 09:32:26.297127 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5465 09:32:26.297201
5466 09:32:26.297265
5467 09:32:26.307016 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5468 09:32:26.307107 CH0 RK1: MR19=505, MR18=2C03
5469 09:32:26.313753 CH0_RK1: MR19=0x505, MR18=0x2C03, DQSOSC=408, MR23=63, INC=65, DEC=43
5470 09:32:26.317370 [RxdqsGatingPostProcess] freq 933
5471 09:32:26.323958 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 09:32:26.327118 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 09:32:26.330570 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 09:32:26.333930 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 09:32:26.337338 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 09:32:26.340675 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 09:32:26.340765 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 09:32:26.344062 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 09:32:26.347376 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 09:32:26.350802 Pre-setting of DQS Precalculation
5481 09:32:26.357255 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 09:32:26.357368 ==
5483 09:32:26.360725 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 09:32:26.364012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 09:32:26.364123 ==
5486 09:32:26.370558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 09:32:26.377296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5488 09:32:26.380351 [CA 0] Center 36 (6~67) winsize 62
5489 09:32:26.383687 [CA 1] Center 36 (6~67) winsize 62
5490 09:32:26.387203 [CA 2] Center 34 (4~65) winsize 62
5491 09:32:26.390047 [CA 3] Center 34 (4~65) winsize 62
5492 09:32:26.393256 [CA 4] Center 34 (4~65) winsize 62
5493 09:32:26.396792 [CA 5] Center 33 (3~64) winsize 62
5494 09:32:26.396867
5495 09:32:26.400137 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5496 09:32:26.400215
5497 09:32:26.403389 [CATrainingPosCal] consider 1 rank data
5498 09:32:26.406623 u2DelayCellTimex100 = 270/100 ps
5499 09:32:26.410487 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5500 09:32:26.413244 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 09:32:26.416672 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 09:32:26.420109 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 09:32:26.423189 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 09:32:26.426481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 09:32:26.426604
5506 09:32:26.433370 CA PerBit enable=1, Macro0, CA PI delay=33
5507 09:32:26.433476
5508 09:32:26.433580 [CBTSetCACLKResult] CA Dly = 33
5509 09:32:26.436421 CS Dly: 7 (0~38)
5510 09:32:26.436498 ==
5511 09:32:26.439918 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 09:32:26.443199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 09:32:26.443279 ==
5514 09:32:26.449998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 09:32:26.456596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5516 09:32:26.459802 [CA 0] Center 37 (6~68) winsize 63
5517 09:32:26.463017 [CA 1] Center 37 (7~68) winsize 62
5518 09:32:26.466365 [CA 2] Center 35 (4~66) winsize 63
5519 09:32:26.469822 [CA 3] Center 34 (4~65) winsize 62
5520 09:32:26.473205 [CA 4] Center 34 (4~65) winsize 62
5521 09:32:26.476639 [CA 5] Center 33 (3~64) winsize 62
5522 09:32:26.476748
5523 09:32:26.479899 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5524 09:32:26.479977
5525 09:32:26.483069 [CATrainingPosCal] consider 2 rank data
5526 09:32:26.486334 u2DelayCellTimex100 = 270/100 ps
5527 09:32:26.489850 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5528 09:32:26.492967 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5529 09:32:26.496679 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5530 09:32:26.500011 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 09:32:26.502846 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 09:32:26.506416 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5533 09:32:26.506526
5534 09:32:26.513100 CA PerBit enable=1, Macro0, CA PI delay=33
5535 09:32:26.513212
5536 09:32:26.516203 [CBTSetCACLKResult] CA Dly = 33
5537 09:32:26.516313 CS Dly: 8 (0~40)
5538 09:32:26.516407
5539 09:32:26.519762 ----->DramcWriteLeveling(PI) begin...
5540 09:32:26.519884 ==
5541 09:32:26.523265 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 09:32:26.526648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 09:32:26.526735 ==
5544 09:32:26.530024 Write leveling (Byte 0): 24 => 24
5545 09:32:26.532625 Write leveling (Byte 1): 29 => 29
5546 09:32:26.536113 DramcWriteLeveling(PI) end<-----
5547 09:32:26.536195
5548 09:32:26.536261 ==
5549 09:32:26.539548 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 09:32:26.545921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 09:32:26.546005 ==
5552 09:32:26.546072 [Gating] SW mode calibration
5553 09:32:26.555998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 09:32:26.559654 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 09:32:26.562943 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 09:32:26.569232 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 09:32:26.573115 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 09:32:26.575973 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 09:32:26.582648 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 09:32:26.585954 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5561 09:32:26.589222 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (1 0) (1 0)
5562 09:32:26.596159 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5563 09:32:26.599474 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 09:32:26.602815 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 09:32:26.609494 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 09:32:26.612683 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 09:32:26.616099 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 09:32:26.622666 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 09:32:26.626033 0 15 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5570 09:32:26.629537 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5571 09:32:26.635987 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 09:32:26.639381 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 09:32:26.642982 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 09:32:26.649753 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 09:32:26.652518 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 09:32:26.655925 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 09:32:26.662474 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5578 09:32:26.666099 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5579 09:32:26.669158 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 09:32:26.672912 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 09:32:26.679110 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 09:32:26.682966 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 09:32:26.686140 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 09:32:26.692404 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 09:32:26.695659 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 09:32:26.698996 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 09:32:26.705909 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 09:32:26.709170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 09:32:26.712440 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 09:32:26.718875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 09:32:26.722491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 09:32:26.725608 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 09:32:26.732425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5594 09:32:26.735751 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 09:32:26.738939 Total UI for P1: 0, mck2ui 16
5596 09:32:26.742323 best dqsien dly found for B0: ( 1, 2, 24)
5597 09:32:26.745713 Total UI for P1: 0, mck2ui 16
5598 09:32:26.749028 best dqsien dly found for B1: ( 1, 2, 24)
5599 09:32:26.752490 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5600 09:32:26.755840 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5601 09:32:26.755924
5602 09:32:26.759261 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5603 09:32:26.762776 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 09:32:26.765466 [Gating] SW calibration Done
5605 09:32:26.765549 ==
5606 09:32:26.769235 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 09:32:26.772660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 09:32:26.775806 ==
5609 09:32:26.775889 RX Vref Scan: 0
5610 09:32:26.775956
5611 09:32:26.779103 RX Vref 0 -> 0, step: 1
5612 09:32:26.779186
5613 09:32:26.779252 RX Delay -80 -> 252, step: 8
5614 09:32:26.785867 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5615 09:32:26.789614 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5616 09:32:26.792487 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5617 09:32:26.795961 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5618 09:32:26.799304 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5619 09:32:26.802589 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5620 09:32:26.809070 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5621 09:32:26.812427 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5622 09:32:26.815991 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5623 09:32:26.818816 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5624 09:32:26.822217 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5625 09:32:26.825718 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5626 09:32:26.832391 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5627 09:32:26.835577 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5628 09:32:26.839309 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5629 09:32:26.842203 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5630 09:32:26.842282 ==
5631 09:32:26.845698 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 09:32:26.852271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 09:32:26.852355 ==
5634 09:32:26.852420 DQS Delay:
5635 09:32:26.855656 DQS0 = 0, DQS1 = 0
5636 09:32:26.855750 DQM Delay:
5637 09:32:26.855815 DQM0 = 102, DQM1 = 99
5638 09:32:26.859081 DQ Delay:
5639 09:32:26.862491 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5640 09:32:26.865698 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5641 09:32:26.869270 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5642 09:32:26.872660 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5643 09:32:26.872805
5644 09:32:26.872874
5645 09:32:26.872934 ==
5646 09:32:26.875769 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 09:32:26.879138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 09:32:26.879220 ==
5649 09:32:26.879285
5650 09:32:26.879345
5651 09:32:26.882465 TX Vref Scan disable
5652 09:32:26.885813 == TX Byte 0 ==
5653 09:32:26.889030 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5654 09:32:26.892136 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5655 09:32:26.895603 == TX Byte 1 ==
5656 09:32:26.899173 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5657 09:32:26.901912 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5658 09:32:26.901994 ==
5659 09:32:26.905719 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 09:32:26.912137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 09:32:26.912220 ==
5662 09:32:26.912285
5663 09:32:26.912344
5664 09:32:26.912402 TX Vref Scan disable
5665 09:32:26.915959 == TX Byte 0 ==
5666 09:32:26.919628 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5667 09:32:26.922579 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5668 09:32:26.926183 == TX Byte 1 ==
5669 09:32:26.929236 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5670 09:32:26.935833 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5671 09:32:26.935915
5672 09:32:26.935980 [DATLAT]
5673 09:32:26.936041 Freq=933, CH1 RK0
5674 09:32:26.936100
5675 09:32:26.939523 DATLAT Default: 0xd
5676 09:32:26.939605 0, 0xFFFF, sum = 0
5677 09:32:26.942976 1, 0xFFFF, sum = 0
5678 09:32:26.943059 2, 0xFFFF, sum = 0
5679 09:32:26.945692 3, 0xFFFF, sum = 0
5680 09:32:26.945776 4, 0xFFFF, sum = 0
5681 09:32:26.948976 5, 0xFFFF, sum = 0
5682 09:32:26.952768 6, 0xFFFF, sum = 0
5683 09:32:26.952854 7, 0xFFFF, sum = 0
5684 09:32:26.955844 8, 0xFFFF, sum = 0
5685 09:32:26.955932 9, 0xFFFF, sum = 0
5686 09:32:26.959498 10, 0x0, sum = 1
5687 09:32:26.959581 11, 0x0, sum = 2
5688 09:32:26.959673 12, 0x0, sum = 3
5689 09:32:26.962703 13, 0x0, sum = 4
5690 09:32:26.962785 best_step = 11
5691 09:32:26.962849
5692 09:32:26.965741 ==
5693 09:32:26.965822 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 09:32:26.972420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 09:32:26.972503 ==
5696 09:32:26.972567 RX Vref Scan: 1
5697 09:32:26.972628
5698 09:32:26.975710 RX Vref 0 -> 0, step: 1
5699 09:32:26.975791
5700 09:32:26.979061 RX Delay -45 -> 252, step: 4
5701 09:32:26.979142
5702 09:32:26.982400 Set Vref, RX VrefLevel [Byte0]: 53
5703 09:32:26.985646 [Byte1]: 53
5704 09:32:26.985728
5705 09:32:26.988894 Final RX Vref Byte 0 = 53 to rank0
5706 09:32:26.992170 Final RX Vref Byte 1 = 53 to rank0
5707 09:32:26.995514 Final RX Vref Byte 0 = 53 to rank1
5708 09:32:26.998945 Final RX Vref Byte 1 = 53 to rank1==
5709 09:32:27.002494 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 09:32:27.005909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 09:32:27.005992 ==
5712 09:32:27.009254 DQS Delay:
5713 09:32:27.009336 DQS0 = 0, DQS1 = 0
5714 09:32:27.012426 DQM Delay:
5715 09:32:27.012534 DQM0 = 103, DQM1 = 100
5716 09:32:27.012607 DQ Delay:
5717 09:32:27.015863 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5718 09:32:27.019209 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =104
5719 09:32:27.022593 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5720 09:32:27.028794 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5721 09:32:27.028876
5722 09:32:27.028941
5723 09:32:27.035779 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5724 09:32:27.039100 CH1 RK0: MR19=505, MR18=1B33
5725 09:32:27.046147 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5726 09:32:27.046230
5727 09:32:27.049098 ----->DramcWriteLeveling(PI) begin...
5728 09:32:27.049182 ==
5729 09:32:27.052574 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 09:32:27.056129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 09:32:27.056211 ==
5732 09:32:27.059231 Write leveling (Byte 0): 26 => 26
5733 09:32:27.062428 Write leveling (Byte 1): 31 => 31
5734 09:32:27.065593 DramcWriteLeveling(PI) end<-----
5735 09:32:27.065674
5736 09:32:27.065738 ==
5737 09:32:27.069407 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 09:32:27.072680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 09:32:27.072773 ==
5740 09:32:27.075997 [Gating] SW mode calibration
5741 09:32:27.082471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5742 09:32:27.088953 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5743 09:32:27.092331 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 09:32:27.098960 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 09:32:27.102309 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 09:32:27.105843 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 09:32:27.111850 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 09:32:27.115590 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 09:32:27.118887 0 14 24 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 0)
5750 09:32:27.125560 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5751 09:32:27.128975 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 09:32:27.132101 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 09:32:27.138603 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 09:32:27.141671 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 09:32:27.145011 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 09:32:27.148431 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5757 09:32:27.155242 0 15 24 | B1->B0 | 3838 2b2b | 0 1 | (0 0) (0 0)
5758 09:32:27.158569 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5759 09:32:27.161699 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 09:32:27.168505 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 09:32:27.171557 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 09:32:27.174959 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 09:32:27.181655 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 09:32:27.184954 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 09:32:27.188616 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5766 09:32:27.195056 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5767 09:32:27.197967 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 09:32:27.201652 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 09:32:27.207893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 09:32:27.211269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 09:32:27.214586 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 09:32:27.221620 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 09:32:27.224872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 09:32:27.228309 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 09:32:27.234921 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 09:32:27.238092 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 09:32:27.241232 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 09:32:27.247904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 09:32:27.251321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 09:32:27.254812 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 09:32:27.261068 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5782 09:32:27.264431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 09:32:27.267775 Total UI for P1: 0, mck2ui 16
5784 09:32:27.271106 best dqsien dly found for B0: ( 1, 2, 24)
5785 09:32:27.274459 Total UI for P1: 0, mck2ui 16
5786 09:32:27.277885 best dqsien dly found for B1: ( 1, 2, 24)
5787 09:32:27.281262 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5788 09:32:27.284397 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5789 09:32:27.284474
5790 09:32:27.287464 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5791 09:32:27.291120 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5792 09:32:27.294131 [Gating] SW calibration Done
5793 09:32:27.294210 ==
5794 09:32:27.297734 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 09:32:27.300667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 09:32:27.304132 ==
5797 09:32:27.304210 RX Vref Scan: 0
5798 09:32:27.304291
5799 09:32:27.307440 RX Vref 0 -> 0, step: 1
5800 09:32:27.307547
5801 09:32:27.307673 RX Delay -80 -> 252, step: 8
5802 09:32:27.314639 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5803 09:32:27.317589 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5804 09:32:27.321316 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5805 09:32:27.324626 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5806 09:32:27.327810 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5807 09:32:27.331208 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5808 09:32:27.338005 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5809 09:32:27.341206 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5810 09:32:27.344442 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5811 09:32:27.347735 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5812 09:32:27.351044 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5813 09:32:27.354147 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5814 09:32:27.361065 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5815 09:32:27.364476 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5816 09:32:27.367853 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5817 09:32:27.371078 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5818 09:32:27.371180 ==
5819 09:32:27.374376 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 09:32:27.380890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 09:32:27.381015 ==
5822 09:32:27.381122 DQS Delay:
5823 09:32:27.384239 DQS0 = 0, DQS1 = 0
5824 09:32:27.384319 DQM Delay:
5825 09:32:27.384382 DQM0 = 102, DQM1 = 99
5826 09:32:27.387475 DQ Delay:
5827 09:32:27.390850 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5828 09:32:27.394041 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5829 09:32:27.397398 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5830 09:32:27.400642 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5831 09:32:27.400716
5832 09:32:27.400778
5833 09:32:27.400836 ==
5834 09:32:27.404549 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 09:32:27.407804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 09:32:27.407916 ==
5837 09:32:27.408008
5838 09:32:27.408097
5839 09:32:27.411192 TX Vref Scan disable
5840 09:32:27.414549 == TX Byte 0 ==
5841 09:32:27.417649 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5842 09:32:27.420654 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5843 09:32:27.424105 == TX Byte 1 ==
5844 09:32:27.427586 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5845 09:32:27.430660 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5846 09:32:27.430745 ==
5847 09:32:27.433897 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 09:32:27.437764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 09:32:27.440897 ==
5850 09:32:27.440981
5851 09:32:27.441062
5852 09:32:27.441137 TX Vref Scan disable
5853 09:32:27.444369 == TX Byte 0 ==
5854 09:32:27.447624 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 09:32:27.451456 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 09:32:27.454838 == TX Byte 1 ==
5857 09:32:27.457565 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5858 09:32:27.461409 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5859 09:32:27.464520
5860 09:32:27.464603 [DATLAT]
5861 09:32:27.464684 Freq=933, CH1 RK1
5862 09:32:27.464790
5863 09:32:27.467618 DATLAT Default: 0xb
5864 09:32:27.467766 0, 0xFFFF, sum = 0
5865 09:32:27.471020 1, 0xFFFF, sum = 0
5866 09:32:27.471104 2, 0xFFFF, sum = 0
5867 09:32:27.474237 3, 0xFFFF, sum = 0
5868 09:32:27.477613 4, 0xFFFF, sum = 0
5869 09:32:27.477693 5, 0xFFFF, sum = 0
5870 09:32:27.480986 6, 0xFFFF, sum = 0
5871 09:32:27.481062 7, 0xFFFF, sum = 0
5872 09:32:27.484478 8, 0xFFFF, sum = 0
5873 09:32:27.484567 9, 0xFFFF, sum = 0
5874 09:32:27.487908 10, 0x0, sum = 1
5875 09:32:27.487987 11, 0x0, sum = 2
5876 09:32:27.488069 12, 0x0, sum = 3
5877 09:32:27.491027 13, 0x0, sum = 4
5878 09:32:27.491128 best_step = 11
5879 09:32:27.491225
5880 09:32:27.494401 ==
5881 09:32:27.494483 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 09:32:27.500878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 09:32:27.500962 ==
5884 09:32:27.501048 RX Vref Scan: 0
5885 09:32:27.501125
5886 09:32:27.504228 RX Vref 0 -> 0, step: 1
5887 09:32:27.504327
5888 09:32:27.507406 RX Delay -45 -> 252, step: 4
5889 09:32:27.510727 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5890 09:32:27.517445 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5891 09:32:27.520768 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5892 09:32:27.524032 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5893 09:32:27.527373 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5894 09:32:27.530781 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5895 09:32:27.537329 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5896 09:32:27.540427 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5897 09:32:27.543855 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5898 09:32:27.547165 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5899 09:32:27.550408 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5900 09:32:27.553873 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5901 09:32:27.560695 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5902 09:32:27.563906 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5903 09:32:27.567041 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5904 09:32:27.570361 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5905 09:32:27.573859 ==
5906 09:32:27.573941 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 09:32:27.580508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 09:32:27.580591 ==
5909 09:32:27.580657 DQS Delay:
5910 09:32:27.583580 DQS0 = 0, DQS1 = 0
5911 09:32:27.583717 DQM Delay:
5912 09:32:27.586995 DQM0 = 105, DQM1 = 100
5913 09:32:27.587076 DQ Delay:
5914 09:32:27.590356 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5915 09:32:27.593739 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5916 09:32:27.597065 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5917 09:32:27.600427 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5918 09:32:27.600509
5919 09:32:27.600573
5920 09:32:27.610197 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5921 09:32:27.610343 CH1 RK1: MR19=505, MR18=3003
5922 09:32:27.616752 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5923 09:32:27.620178 [RxdqsGatingPostProcess] freq 933
5924 09:32:27.626882 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5925 09:32:27.630083 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 09:32:27.633560 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 09:32:27.636936 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 09:32:27.640287 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 09:32:27.643620 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 09:32:27.643742 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 09:32:27.646629 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 09:32:27.650154 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 09:32:27.653615 Pre-setting of DQS Precalculation
5934 09:32:27.659768 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5935 09:32:27.667104 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5936 09:32:27.673603 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5937 09:32:27.673698
5938 09:32:27.673763
5939 09:32:27.676654 [Calibration Summary] 1866 Mbps
5940 09:32:27.676749 CH 0, Rank 0
5941 09:32:27.680291 SW Impedance : PASS
5942 09:32:27.683323 DUTY Scan : NO K
5943 09:32:27.683430 ZQ Calibration : PASS
5944 09:32:27.687235 Jitter Meter : NO K
5945 09:32:27.690205 CBT Training : PASS
5946 09:32:27.690286 Write leveling : PASS
5947 09:32:27.693661 RX DQS gating : PASS
5948 09:32:27.696657 RX DQ/DQS(RDDQC) : PASS
5949 09:32:27.696758 TX DQ/DQS : PASS
5950 09:32:27.700239 RX DATLAT : PASS
5951 09:32:27.703597 RX DQ/DQS(Engine): PASS
5952 09:32:27.703757 TX OE : NO K
5953 09:32:27.703924 All Pass.
5954 09:32:27.706907
5955 09:32:27.707021 CH 0, Rank 1
5956 09:32:27.709745 SW Impedance : PASS
5957 09:32:27.709858 DUTY Scan : NO K
5958 09:32:27.712965 ZQ Calibration : PASS
5959 09:32:27.716361 Jitter Meter : NO K
5960 09:32:27.716480 CBT Training : PASS
5961 09:32:27.719678 Write leveling : PASS
5962 09:32:27.719771 RX DQS gating : PASS
5963 09:32:27.723019 RX DQ/DQS(RDDQC) : PASS
5964 09:32:27.726559 TX DQ/DQS : PASS
5965 09:32:27.726642 RX DATLAT : PASS
5966 09:32:27.729955 RX DQ/DQS(Engine): PASS
5967 09:32:27.733427 TX OE : NO K
5968 09:32:27.733508 All Pass.
5969 09:32:27.733571
5970 09:32:27.733631 CH 1, Rank 0
5971 09:32:27.736798 SW Impedance : PASS
5972 09:32:27.739492 DUTY Scan : NO K
5973 09:32:27.739575 ZQ Calibration : PASS
5974 09:32:27.742740 Jitter Meter : NO K
5975 09:32:27.746175 CBT Training : PASS
5976 09:32:27.746256 Write leveling : PASS
5977 09:32:27.749517 RX DQS gating : PASS
5978 09:32:27.753206 RX DQ/DQS(RDDQC) : PASS
5979 09:32:27.753287 TX DQ/DQS : PASS
5980 09:32:27.756647 RX DATLAT : PASS
5981 09:32:27.759401 RX DQ/DQS(Engine): PASS
5982 09:32:27.759508 TX OE : NO K
5983 09:32:27.759610 All Pass.
5984 09:32:27.762780
5985 09:32:27.762892 CH 1, Rank 1
5986 09:32:27.766040 SW Impedance : PASS
5987 09:32:27.766148 DUTY Scan : NO K
5988 09:32:27.769978 ZQ Calibration : PASS
5989 09:32:27.770101 Jitter Meter : NO K
5990 09:32:27.773104 CBT Training : PASS
5991 09:32:27.776673 Write leveling : PASS
5992 09:32:27.776754 RX DQS gating : PASS
5993 09:32:27.779872 RX DQ/DQS(RDDQC) : PASS
5994 09:32:27.783231 TX DQ/DQS : PASS
5995 09:32:27.783312 RX DATLAT : PASS
5996 09:32:27.786440 RX DQ/DQS(Engine): PASS
5997 09:32:27.789737 TX OE : NO K
5998 09:32:27.789850 All Pass.
5999 09:32:27.789936
6000 09:32:27.793054 DramC Write-DBI off
6001 09:32:27.793170 PER_BANK_REFRESH: Hybrid Mode
6002 09:32:27.796155 TX_TRACKING: ON
6003 09:32:27.802638 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6004 09:32:27.809234 [FAST_K] Save calibration result to emmc
6005 09:32:27.812818 dramc_set_vcore_voltage set vcore to 650000
6006 09:32:27.812902 Read voltage for 400, 6
6007 09:32:27.815893 Vio18 = 0
6008 09:32:27.816077 Vcore = 650000
6009 09:32:27.816215 Vdram = 0
6010 09:32:27.819429 Vddq = 0
6011 09:32:27.819569 Vmddr = 0
6012 09:32:27.822977 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6013 09:32:27.829467 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6014 09:32:27.832878 MEM_TYPE=3, freq_sel=20
6015 09:32:27.836054 sv_algorithm_assistance_LP4_800
6016 09:32:27.839066 ============ PULL DRAM RESETB DOWN ============
6017 09:32:27.843021 ========== PULL DRAM RESETB DOWN end =========
6018 09:32:27.846275 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6019 09:32:27.849696 ===================================
6020 09:32:27.852371 LPDDR4 DRAM CONFIGURATION
6021 09:32:27.855642 ===================================
6022 09:32:27.859004 EX_ROW_EN[0] = 0x0
6023 09:32:27.859080 EX_ROW_EN[1] = 0x0
6024 09:32:27.862540 LP4Y_EN = 0x0
6025 09:32:27.862614 WORK_FSP = 0x0
6026 09:32:27.865865 WL = 0x2
6027 09:32:27.865956 RL = 0x2
6028 09:32:27.869295 BL = 0x2
6029 09:32:27.869371 RPST = 0x0
6030 09:32:27.872709 RD_PRE = 0x0
6031 09:32:27.875775 WR_PRE = 0x1
6032 09:32:27.875848 WR_PST = 0x0
6033 09:32:27.878978 DBI_WR = 0x0
6034 09:32:27.879081 DBI_RD = 0x0
6035 09:32:27.882239 OTF = 0x1
6036 09:32:27.885631 ===================================
6037 09:32:27.889049 ===================================
6038 09:32:27.889135 ANA top config
6039 09:32:27.892557 ===================================
6040 09:32:27.895961 DLL_ASYNC_EN = 0
6041 09:32:27.899200 ALL_SLAVE_EN = 1
6042 09:32:27.899273 NEW_RANK_MODE = 1
6043 09:32:27.902986 DLL_IDLE_MODE = 1
6044 09:32:27.905719 LP45_APHY_COMB_EN = 1
6045 09:32:27.909103 TX_ODT_DIS = 1
6046 09:32:27.909213 NEW_8X_MODE = 1
6047 09:32:27.912549 ===================================
6048 09:32:27.915941 ===================================
6049 09:32:27.919282 data_rate = 800
6050 09:32:27.922776 CKR = 1
6051 09:32:27.926114 DQ_P2S_RATIO = 4
6052 09:32:27.929417 ===================================
6053 09:32:27.932718 CA_P2S_RATIO = 4
6054 09:32:27.935619 DQ_CA_OPEN = 0
6055 09:32:27.935712 DQ_SEMI_OPEN = 1
6056 09:32:27.938944 CA_SEMI_OPEN = 1
6057 09:32:27.942713 CA_FULL_RATE = 0
6058 09:32:27.945600 DQ_CKDIV4_EN = 0
6059 09:32:27.948944 CA_CKDIV4_EN = 1
6060 09:32:27.952318 CA_PREDIV_EN = 0
6061 09:32:27.952425 PH8_DLY = 0
6062 09:32:27.955833 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6063 09:32:27.958816 DQ_AAMCK_DIV = 0
6064 09:32:27.962249 CA_AAMCK_DIV = 0
6065 09:32:27.965849 CA_ADMCK_DIV = 4
6066 09:32:27.965967 DQ_TRACK_CA_EN = 0
6067 09:32:27.969117 CA_PICK = 800
6068 09:32:27.972685 CA_MCKIO = 400
6069 09:32:27.976031 MCKIO_SEMI = 400
6070 09:32:27.978687 PLL_FREQ = 3016
6071 09:32:27.982037 DQ_UI_PI_RATIO = 32
6072 09:32:27.985838 CA_UI_PI_RATIO = 32
6073 09:32:27.989071 ===================================
6074 09:32:27.992471 ===================================
6075 09:32:27.995991 memory_type:LPDDR4
6076 09:32:27.996092 GP_NUM : 10
6077 09:32:27.998567 SRAM_EN : 1
6078 09:32:27.998665 MD32_EN : 0
6079 09:32:28.002170 ===================================
6080 09:32:28.005391 [ANA_INIT] >>>>>>>>>>>>>>
6081 09:32:28.008614 <<<<<< [CONFIGURE PHASE]: ANA_TX
6082 09:32:28.012373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6083 09:32:28.015767 ===================================
6084 09:32:28.018633 data_rate = 800,PCW = 0X7400
6085 09:32:28.022048 ===================================
6086 09:32:28.025455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6087 09:32:28.028854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6088 09:32:28.042159 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 09:32:28.045561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6090 09:32:28.049025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6091 09:32:28.052238 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6092 09:32:28.055598 [ANA_INIT] flow start
6093 09:32:28.058894 [ANA_INIT] PLL >>>>>>>>
6094 09:32:28.058993 [ANA_INIT] PLL <<<<<<<<
6095 09:32:28.062115 [ANA_INIT] MIDPI >>>>>>>>
6096 09:32:28.065459 [ANA_INIT] MIDPI <<<<<<<<
6097 09:32:28.065560 [ANA_INIT] DLL >>>>>>>>
6098 09:32:28.068691 [ANA_INIT] flow end
6099 09:32:28.071977 ============ LP4 DIFF to SE enter ============
6100 09:32:28.075566 ============ LP4 DIFF to SE exit ============
6101 09:32:28.078623 [ANA_INIT] <<<<<<<<<<<<<
6102 09:32:28.082039 [Flow] Enable top DCM control >>>>>
6103 09:32:28.085387 [Flow] Enable top DCM control <<<<<
6104 09:32:28.089062 Enable DLL master slave shuffle
6105 09:32:28.095224 ==============================================================
6106 09:32:28.095333 Gating Mode config
6107 09:32:28.102146 ==============================================================
6108 09:32:28.102258 Config description:
6109 09:32:28.112247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6110 09:32:28.118806 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6111 09:32:28.125427 SELPH_MODE 0: By rank 1: By Phase
6112 09:32:28.128873 ==============================================================
6113 09:32:28.132138 GAT_TRACK_EN = 0
6114 09:32:28.135594 RX_GATING_MODE = 2
6115 09:32:28.138325 RX_GATING_TRACK_MODE = 2
6116 09:32:28.142305 SELPH_MODE = 1
6117 09:32:28.145541 PICG_EARLY_EN = 1
6118 09:32:28.149021 VALID_LAT_VALUE = 1
6119 09:32:28.155564 ==============================================================
6120 09:32:28.158307 Enter into Gating configuration >>>>
6121 09:32:28.162073 Exit from Gating configuration <<<<
6122 09:32:28.162198 Enter into DVFS_PRE_config >>>>>
6123 09:32:28.174850 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6124 09:32:28.178453 Exit from DVFS_PRE_config <<<<<
6125 09:32:28.181825 Enter into PICG configuration >>>>
6126 09:32:28.185195 Exit from PICG configuration <<<<
6127 09:32:28.185281 [RX_INPUT] configuration >>>>>
6128 09:32:28.188485 [RX_INPUT] configuration <<<<<
6129 09:32:28.194647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6130 09:32:28.201572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6131 09:32:28.204936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 09:32:28.211258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 09:32:28.218387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 09:32:28.224837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 09:32:28.228226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6136 09:32:28.231540 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6137 09:32:28.237794 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6138 09:32:28.241311 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6139 09:32:28.244528 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6140 09:32:28.248436 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6141 09:32:28.251757 ===================================
6142 09:32:28.254528 LPDDR4 DRAM CONFIGURATION
6143 09:32:28.257831 ===================================
6144 09:32:28.261245 EX_ROW_EN[0] = 0x0
6145 09:32:28.261329 EX_ROW_EN[1] = 0x0
6146 09:32:28.264748 LP4Y_EN = 0x0
6147 09:32:28.264828 WORK_FSP = 0x0
6148 09:32:28.267936 WL = 0x2
6149 09:32:28.268008 RL = 0x2
6150 09:32:28.271348 BL = 0x2
6151 09:32:28.271419 RPST = 0x0
6152 09:32:28.274521 RD_PRE = 0x0
6153 09:32:28.274595 WR_PRE = 0x1
6154 09:32:28.278440 WR_PST = 0x0
6155 09:32:28.278542 DBI_WR = 0x0
6156 09:32:28.281702 DBI_RD = 0x0
6157 09:32:28.284444 OTF = 0x1
6158 09:32:28.287811 ===================================
6159 09:32:28.291305 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6160 09:32:28.294658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6161 09:32:28.298504 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 09:32:28.301772 ===================================
6163 09:32:28.305149 LPDDR4 DRAM CONFIGURATION
6164 09:32:28.308488 ===================================
6165 09:32:28.311750 EX_ROW_EN[0] = 0x10
6166 09:32:28.311842 EX_ROW_EN[1] = 0x0
6167 09:32:28.315095 LP4Y_EN = 0x0
6168 09:32:28.315205 WORK_FSP = 0x0
6169 09:32:28.318156 WL = 0x2
6170 09:32:28.318240 RL = 0x2
6171 09:32:28.321670 BL = 0x2
6172 09:32:28.321754 RPST = 0x0
6173 09:32:28.324644 RD_PRE = 0x0
6174 09:32:28.324727 WR_PRE = 0x1
6175 09:32:28.328037 WR_PST = 0x0
6176 09:32:28.328147 DBI_WR = 0x0
6177 09:32:28.331670 DBI_RD = 0x0
6178 09:32:28.331770 OTF = 0x1
6179 09:32:28.334622 ===================================
6180 09:32:28.341674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6181 09:32:28.346097 nWR fixed to 30
6182 09:32:28.349306 [ModeRegInit_LP4] CH0 RK0
6183 09:32:28.349408 [ModeRegInit_LP4] CH0 RK1
6184 09:32:28.352713 [ModeRegInit_LP4] CH1 RK0
6185 09:32:28.356100 [ModeRegInit_LP4] CH1 RK1
6186 09:32:28.356180 match AC timing 19
6187 09:32:28.362927 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6188 09:32:28.366295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6189 09:32:28.369178 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6190 09:32:28.376116 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6191 09:32:28.379404 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6192 09:32:28.379508 ==
6193 09:32:28.382777 Dram Type= 6, Freq= 0, CH_0, rank 0
6194 09:32:28.386415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6195 09:32:28.386539 ==
6196 09:32:28.392277 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6197 09:32:28.399444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6198 09:32:28.402742 [CA 0] Center 36 (8~64) winsize 57
6199 09:32:28.406164 [CA 1] Center 36 (8~64) winsize 57
6200 09:32:28.409499 [CA 2] Center 36 (8~64) winsize 57
6201 09:32:28.409584 [CA 3] Center 36 (8~64) winsize 57
6202 09:32:28.412880 [CA 4] Center 36 (8~64) winsize 57
6203 09:32:28.415546 [CA 5] Center 36 (8~64) winsize 57
6204 09:32:28.415663
6205 09:32:28.418891 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6206 09:32:28.422523
6207 09:32:28.425905 [CATrainingPosCal] consider 1 rank data
6208 09:32:28.425988 u2DelayCellTimex100 = 270/100 ps
6209 09:32:28.432703 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 09:32:28.436090 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 09:32:28.439233 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 09:32:28.442371 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 09:32:28.445898 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 09:32:28.449267 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 09:32:28.449350
6216 09:32:28.452392 CA PerBit enable=1, Macro0, CA PI delay=36
6217 09:32:28.452475
6218 09:32:28.455571 [CBTSetCACLKResult] CA Dly = 36
6219 09:32:28.459077 CS Dly: 1 (0~32)
6220 09:32:28.459178 ==
6221 09:32:28.462420 Dram Type= 6, Freq= 0, CH_0, rank 1
6222 09:32:28.465869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 09:32:28.465969 ==
6224 09:32:28.472016 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 09:32:28.475415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6226 09:32:28.479061 [CA 0] Center 36 (8~64) winsize 57
6227 09:32:28.481942 [CA 1] Center 36 (8~64) winsize 57
6228 09:32:28.485752 [CA 2] Center 36 (8~64) winsize 57
6229 09:32:28.489129 [CA 3] Center 36 (8~64) winsize 57
6230 09:32:28.491836 [CA 4] Center 36 (8~64) winsize 57
6231 09:32:28.495211 [CA 5] Center 36 (8~64) winsize 57
6232 09:32:28.495297
6233 09:32:28.498560 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6234 09:32:28.498645
6235 09:32:28.502435 [CATrainingPosCal] consider 2 rank data
6236 09:32:28.505714 u2DelayCellTimex100 = 270/100 ps
6237 09:32:28.508994 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 09:32:28.511841 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 09:32:28.515285 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 09:32:28.522193 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 09:32:28.525558 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 09:32:28.529091 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 09:32:28.529176
6244 09:32:28.531726 CA PerBit enable=1, Macro0, CA PI delay=36
6245 09:32:28.531812
6246 09:32:28.535263 [CBTSetCACLKResult] CA Dly = 36
6247 09:32:28.535373 CS Dly: 1 (0~32)
6248 09:32:28.535477
6249 09:32:28.538760 ----->DramcWriteLeveling(PI) begin...
6250 09:32:28.538847 ==
6251 09:32:28.542108 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 09:32:28.548923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 09:32:28.549008 ==
6254 09:32:28.552197 Write leveling (Byte 0): 40 => 8
6255 09:32:28.555227 Write leveling (Byte 1): 40 => 8
6256 09:32:28.555338 DramcWriteLeveling(PI) end<-----
6257 09:32:28.555442
6258 09:32:28.558965 ==
6259 09:32:28.562414 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 09:32:28.565207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 09:32:28.565293 ==
6262 09:32:28.569105 [Gating] SW mode calibration
6263 09:32:28.576140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 09:32:28.578974 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6265 09:32:28.585069 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 09:32:28.588578 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 09:32:28.592024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 09:32:28.598663 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 09:32:28.602316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 09:32:28.605201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 09:32:28.612131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 09:32:28.615450 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 09:32:28.618615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 09:32:28.622159 Total UI for P1: 0, mck2ui 16
6275 09:32:28.625234 best dqsien dly found for B0: ( 0, 14, 24)
6276 09:32:28.628508 Total UI for P1: 0, mck2ui 16
6277 09:32:28.631971 best dqsien dly found for B1: ( 0, 14, 24)
6278 09:32:28.635390 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6279 09:32:28.638635 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6280 09:32:28.638745
6281 09:32:28.641993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6282 09:32:28.648823 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 09:32:28.648903 [Gating] SW calibration Done
6284 09:32:28.652118 ==
6285 09:32:28.652224 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 09:32:28.658267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 09:32:28.658375 ==
6288 09:32:28.658468 RX Vref Scan: 0
6289 09:32:28.658557
6290 09:32:28.661631 RX Vref 0 -> 0, step: 1
6291 09:32:28.661715
6292 09:32:28.665428 RX Delay -410 -> 252, step: 16
6293 09:32:28.668533 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6294 09:32:28.671811 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6295 09:32:28.678160 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6296 09:32:28.682231 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6297 09:32:28.684885 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6298 09:32:28.688368 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6299 09:32:28.694848 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6300 09:32:28.698061 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6301 09:32:28.702184 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6302 09:32:28.705346 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6303 09:32:28.711924 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6304 09:32:28.715210 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6305 09:32:28.718558 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6306 09:32:28.721734 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6307 09:32:28.728676 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6308 09:32:28.731427 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6309 09:32:28.731533 ==
6310 09:32:28.734941 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 09:32:28.738787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 09:32:28.738871 ==
6313 09:32:28.741711 DQS Delay:
6314 09:32:28.741817 DQS0 = 27, DQS1 = 35
6315 09:32:28.744709 DQM Delay:
6316 09:32:28.744788 DQM0 = 12, DQM1 = 12
6317 09:32:28.744857 DQ Delay:
6318 09:32:28.748473 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6319 09:32:28.751754 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6320 09:32:28.755048 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6321 09:32:28.758576 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6322 09:32:28.758656
6323 09:32:28.758718
6324 09:32:28.758776 ==
6325 09:32:28.761912 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 09:32:28.765092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 09:32:28.768498 ==
6328 09:32:28.768578
6329 09:32:28.768641
6330 09:32:28.768699 TX Vref Scan disable
6331 09:32:28.771553 == TX Byte 0 ==
6332 09:32:28.774847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 09:32:28.778020 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 09:32:28.781913 == TX Byte 1 ==
6335 09:32:28.784946 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 09:32:28.788278 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 09:32:28.788358 ==
6338 09:32:28.791756 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 09:32:28.794935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 09:32:28.798383 ==
6341 09:32:28.798462
6342 09:32:28.798524
6343 09:32:28.798583 TX Vref Scan disable
6344 09:32:28.801588 == TX Byte 0 ==
6345 09:32:28.805030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 09:32:28.808350 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 09:32:28.812138 == TX Byte 1 ==
6348 09:32:28.815189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 09:32:28.818275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 09:32:28.818355
6351 09:32:28.818418 [DATLAT]
6352 09:32:28.821485 Freq=400, CH0 RK0
6353 09:32:28.821565
6354 09:32:28.824877 DATLAT Default: 0xf
6355 09:32:28.824957 0, 0xFFFF, sum = 0
6356 09:32:28.828322 1, 0xFFFF, sum = 0
6357 09:32:28.828402 2, 0xFFFF, sum = 0
6358 09:32:28.831679 3, 0xFFFF, sum = 0
6359 09:32:28.831760 4, 0xFFFF, sum = 0
6360 09:32:28.834987 5, 0xFFFF, sum = 0
6361 09:32:28.835068 6, 0xFFFF, sum = 0
6362 09:32:28.838219 7, 0xFFFF, sum = 0
6363 09:32:28.838302 8, 0xFFFF, sum = 0
6364 09:32:28.841635 9, 0xFFFF, sum = 0
6365 09:32:28.841734 10, 0xFFFF, sum = 0
6366 09:32:28.845045 11, 0xFFFF, sum = 0
6367 09:32:28.845123 12, 0xFFFF, sum = 0
6368 09:32:28.848266 13, 0x0, sum = 1
6369 09:32:28.848350 14, 0x0, sum = 2
6370 09:32:28.851534 15, 0x0, sum = 3
6371 09:32:28.851662 16, 0x0, sum = 4
6372 09:32:28.855251 best_step = 14
6373 09:32:28.855410
6374 09:32:28.855503 ==
6375 09:32:28.858685 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 09:32:28.862065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 09:32:28.862172 ==
6378 09:32:28.865085 RX Vref Scan: 1
6379 09:32:28.865190
6380 09:32:28.865281 RX Vref 0 -> 0, step: 1
6381 09:32:28.865369
6382 09:32:28.868825 RX Delay -311 -> 252, step: 8
6383 09:32:28.868941
6384 09:32:28.871794 Set Vref, RX VrefLevel [Byte0]: 55
6385 09:32:28.874762 [Byte1]: 47
6386 09:32:28.879632
6387 09:32:28.879753 Final RX Vref Byte 0 = 55 to rank0
6388 09:32:28.882586 Final RX Vref Byte 1 = 47 to rank0
6389 09:32:28.885913 Final RX Vref Byte 0 = 55 to rank1
6390 09:32:28.889084 Final RX Vref Byte 1 = 47 to rank1==
6391 09:32:28.892705 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 09:32:28.899344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 09:32:28.899425 ==
6394 09:32:28.899488 DQS Delay:
6395 09:32:28.902718 DQS0 = 28, DQS1 = 36
6396 09:32:28.902798 DQM Delay:
6397 09:32:28.902862 DQM0 = 11, DQM1 = 13
6398 09:32:28.906017 DQ Delay:
6399 09:32:28.908803 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6400 09:32:28.908883 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6401 09:32:28.912349 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6402 09:32:28.915668 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6403 09:32:28.915762
6404 09:32:28.919088
6405 09:32:28.925918 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6406 09:32:28.928893 CH0 RK0: MR19=C0C, MR18=D2C1
6407 09:32:28.935466 CH0_RK0: MR19=0xC0C, MR18=0xD2C1, DQSOSC=383, MR23=63, INC=402, DEC=268
6408 09:32:28.935572 ==
6409 09:32:28.938937 Dram Type= 6, Freq= 0, CH_0, rank 1
6410 09:32:28.942222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 09:32:28.942302 ==
6412 09:32:28.945690 [Gating] SW mode calibration
6413 09:32:28.952481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6414 09:32:28.959345 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6415 09:32:28.961964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6416 09:32:28.965940 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 09:32:28.972487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 09:32:28.975558 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 09:32:28.978663 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 09:32:28.982226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 09:32:28.989004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 09:32:28.991860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 09:32:28.995264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 09:32:28.998424 Total UI for P1: 0, mck2ui 16
6425 09:32:29.002078 best dqsien dly found for B0: ( 0, 14, 24)
6426 09:32:29.005172 Total UI for P1: 0, mck2ui 16
6427 09:32:29.008426 best dqsien dly found for B1: ( 0, 14, 24)
6428 09:32:29.011863 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6429 09:32:29.018614 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6430 09:32:29.018696
6431 09:32:29.022003 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6432 09:32:29.025385 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 09:32:29.028722 [Gating] SW calibration Done
6434 09:32:29.028802 ==
6435 09:32:29.031990 Dram Type= 6, Freq= 0, CH_0, rank 1
6436 09:32:29.035081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 09:32:29.035161 ==
6438 09:32:29.035225 RX Vref Scan: 0
6439 09:32:29.038829
6440 09:32:29.038907 RX Vref 0 -> 0, step: 1
6441 09:32:29.038971
6442 09:32:29.041831 RX Delay -410 -> 252, step: 16
6443 09:32:29.045350 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6444 09:32:29.052013 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6445 09:32:29.055436 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6446 09:32:29.058779 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6447 09:32:29.062137 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6448 09:32:29.068812 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6449 09:32:29.072053 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6450 09:32:29.075457 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6451 09:32:29.078780 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6452 09:32:29.085562 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6453 09:32:29.088761 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6454 09:32:29.092107 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6455 09:32:29.095114 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6456 09:32:29.101630 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6457 09:32:29.105466 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6458 09:32:29.108722 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6459 09:32:29.108802 ==
6460 09:32:29.111796 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 09:32:29.115326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 09:32:29.118623 ==
6463 09:32:29.118702 DQS Delay:
6464 09:32:29.118765 DQS0 = 19, DQS1 = 35
6465 09:32:29.122133 DQM Delay:
6466 09:32:29.122212 DQM0 = 5, DQM1 = 12
6467 09:32:29.125281 DQ Delay:
6468 09:32:29.125360 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6469 09:32:29.128431 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6470 09:32:29.131625 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6471 09:32:29.135009 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6472 09:32:29.135089
6473 09:32:29.135152
6474 09:32:29.135210 ==
6475 09:32:29.138339 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 09:32:29.145320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 09:32:29.145409 ==
6478 09:32:29.145506
6479 09:32:29.145599
6480 09:32:29.145689 TX Vref Scan disable
6481 09:32:29.148359 == TX Byte 0 ==
6482 09:32:29.152197 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6483 09:32:29.155366 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6484 09:32:29.158742 == TX Byte 1 ==
6485 09:32:29.162476 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6486 09:32:29.165110 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6487 09:32:29.165190 ==
6488 09:32:29.168405 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 09:32:29.175828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 09:32:29.175930 ==
6491 09:32:29.176020
6492 09:32:29.176107
6493 09:32:29.176191 TX Vref Scan disable
6494 09:32:29.178617 == TX Byte 0 ==
6495 09:32:29.181769 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 09:32:29.185297 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 09:32:29.188588 == TX Byte 1 ==
6498 09:32:29.191749 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6499 09:32:29.195329 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6500 09:32:29.195428
6501 09:32:29.198514 [DATLAT]
6502 09:32:29.198594 Freq=400, CH0 RK1
6503 09:32:29.198657
6504 09:32:29.201670 DATLAT Default: 0xe
6505 09:32:29.201775 0, 0xFFFF, sum = 0
6506 09:32:29.205319 1, 0xFFFF, sum = 0
6507 09:32:29.205391 2, 0xFFFF, sum = 0
6508 09:32:29.208597 3, 0xFFFF, sum = 0
6509 09:32:29.208678 4, 0xFFFF, sum = 0
6510 09:32:29.211803 5, 0xFFFF, sum = 0
6511 09:32:29.211884 6, 0xFFFF, sum = 0
6512 09:32:29.215130 7, 0xFFFF, sum = 0
6513 09:32:29.215210 8, 0xFFFF, sum = 0
6514 09:32:29.218319 9, 0xFFFF, sum = 0
6515 09:32:29.218400 10, 0xFFFF, sum = 0
6516 09:32:29.221958 11, 0xFFFF, sum = 0
6517 09:32:29.222039 12, 0xFFFF, sum = 0
6518 09:32:29.225334 13, 0x0, sum = 1
6519 09:32:29.225415 14, 0x0, sum = 2
6520 09:32:29.228697 15, 0x0, sum = 3
6521 09:32:29.228777 16, 0x0, sum = 4
6522 09:32:29.231572 best_step = 14
6523 09:32:29.231719
6524 09:32:29.231785 ==
6525 09:32:29.235340 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 09:32:29.238492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 09:32:29.238572 ==
6528 09:32:29.241613 RX Vref Scan: 0
6529 09:32:29.241692
6530 09:32:29.241755 RX Vref 0 -> 0, step: 1
6531 09:32:29.241834
6532 09:32:29.245220 RX Delay -311 -> 252, step: 8
6533 09:32:29.253109 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6534 09:32:29.256726 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6535 09:32:29.259702 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6536 09:32:29.262782 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6537 09:32:29.269722 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6538 09:32:29.272702 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6539 09:32:29.276690 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6540 09:32:29.279404 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6541 09:32:29.286168 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6542 09:32:29.289497 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6543 09:32:29.292934 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6544 09:32:29.296170 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6545 09:32:29.302943 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6546 09:32:29.306271 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6547 09:32:29.309424 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6548 09:32:29.316303 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6549 09:32:29.316385 ==
6550 09:32:29.319407 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 09:32:29.322771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 09:32:29.322876 ==
6553 09:32:29.322968 DQS Delay:
6554 09:32:29.326030 DQS0 = 24, DQS1 = 36
6555 09:32:29.326125 DQM Delay:
6556 09:32:29.329669 DQM0 = 8, DQM1 = 13
6557 09:32:29.329762 DQ Delay:
6558 09:32:29.332976 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6559 09:32:29.336235 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6560 09:32:29.339531 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6561 09:32:29.342715 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6562 09:32:29.342790
6563 09:32:29.342851
6564 09:32:29.349419 [DQSOSCAuto] RK1, (LSB)MR18= 0xba59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6565 09:32:29.352815 CH0 RK1: MR19=C0C, MR18=BA59
6566 09:32:29.359128 CH0_RK1: MR19=0xC0C, MR18=0xBA59, DQSOSC=386, MR23=63, INC=396, DEC=264
6567 09:32:29.362873 [RxdqsGatingPostProcess] freq 400
6568 09:32:29.366246 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6569 09:32:29.369629 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 09:32:29.372906 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 09:32:29.376170 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 09:32:29.379198 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 09:32:29.382377 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 09:32:29.385787 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 09:32:29.389160 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 09:32:29.392193 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 09:32:29.395674 Pre-setting of DQS Precalculation
6578 09:32:29.398862 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6579 09:32:29.402188 ==
6580 09:32:29.405476 Dram Type= 6, Freq= 0, CH_1, rank 0
6581 09:32:29.408875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 09:32:29.408954 ==
6583 09:32:29.412280 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6584 09:32:29.418820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6585 09:32:29.421877 [CA 0] Center 36 (8~64) winsize 57
6586 09:32:29.425652 [CA 1] Center 36 (8~64) winsize 57
6587 09:32:29.428970 [CA 2] Center 36 (8~64) winsize 57
6588 09:32:29.432179 [CA 3] Center 36 (8~64) winsize 57
6589 09:32:29.435220 [CA 4] Center 36 (8~64) winsize 57
6590 09:32:29.438861 [CA 5] Center 36 (8~64) winsize 57
6591 09:32:29.438942
6592 09:32:29.442052 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6593 09:32:29.442132
6594 09:32:29.445375 [CATrainingPosCal] consider 1 rank data
6595 09:32:29.448634 u2DelayCellTimex100 = 270/100 ps
6596 09:32:29.451754 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 09:32:29.455023 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 09:32:29.458270 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 09:32:29.465021 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 09:32:29.468756 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 09:32:29.471904 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 09:32:29.471984
6603 09:32:29.475212 CA PerBit enable=1, Macro0, CA PI delay=36
6604 09:32:29.475292
6605 09:32:29.478560 [CBTSetCACLKResult] CA Dly = 36
6606 09:32:29.478640 CS Dly: 1 (0~32)
6607 09:32:29.478704 ==
6608 09:32:29.481307 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 09:32:29.488174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 09:32:29.488271 ==
6611 09:32:29.491578 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 09:32:29.498301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6613 09:32:29.501494 [CA 0] Center 36 (8~64) winsize 57
6614 09:32:29.504682 [CA 1] Center 36 (8~64) winsize 57
6615 09:32:29.507793 [CA 2] Center 36 (8~64) winsize 57
6616 09:32:29.511323 [CA 3] Center 36 (8~64) winsize 57
6617 09:32:29.514948 [CA 4] Center 36 (8~64) winsize 57
6618 09:32:29.518207 [CA 5] Center 36 (8~64) winsize 57
6619 09:32:29.518312
6620 09:32:29.521758 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6621 09:32:29.521839
6622 09:32:29.524950 [CATrainingPosCal] consider 2 rank data
6623 09:32:29.528293 u2DelayCellTimex100 = 270/100 ps
6624 09:32:29.531573 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 09:32:29.534695 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 09:32:29.538016 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 09:32:29.541316 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 09:32:29.544657 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 09:32:29.551433 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 09:32:29.551545
6631 09:32:29.554681 CA PerBit enable=1, Macro0, CA PI delay=36
6632 09:32:29.554780
6633 09:32:29.557955 [CBTSetCACLKResult] CA Dly = 36
6634 09:32:29.558035 CS Dly: 1 (0~32)
6635 09:32:29.558099
6636 09:32:29.561081 ----->DramcWriteLeveling(PI) begin...
6637 09:32:29.561163 ==
6638 09:32:29.564285 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 09:32:29.571029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 09:32:29.571110 ==
6641 09:32:29.571174 Write leveling (Byte 0): 40 => 8
6642 09:32:29.574074 Write leveling (Byte 1): 40 => 8
6643 09:32:29.577833 DramcWriteLeveling(PI) end<-----
6644 09:32:29.577913
6645 09:32:29.577976 ==
6646 09:32:29.580464 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 09:32:29.587324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 09:32:29.587436 ==
6649 09:32:29.590797 [Gating] SW mode calibration
6650 09:32:29.597605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6651 09:32:29.600889 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6652 09:32:29.607377 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 09:32:29.610560 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 09:32:29.613946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 09:32:29.620323 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 09:32:29.624017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 09:32:29.627081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 09:32:29.634077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 09:32:29.637390 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 09:32:29.640582 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 09:32:29.643901 Total UI for P1: 0, mck2ui 16
6662 09:32:29.647133 best dqsien dly found for B0: ( 0, 14, 24)
6663 09:32:29.650435 Total UI for P1: 0, mck2ui 16
6664 09:32:29.653752 best dqsien dly found for B1: ( 0, 14, 24)
6665 09:32:29.656730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6666 09:32:29.660740 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6667 09:32:29.660839
6668 09:32:29.663930 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6669 09:32:29.670233 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 09:32:29.670342 [Gating] SW calibration Done
6671 09:32:29.673939 ==
6672 09:32:29.674038 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 09:32:29.680310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 09:32:29.680390 ==
6675 09:32:29.680455 RX Vref Scan: 0
6676 09:32:29.680514
6677 09:32:29.683444 RX Vref 0 -> 0, step: 1
6678 09:32:29.683524
6679 09:32:29.686949 RX Delay -410 -> 252, step: 16
6680 09:32:29.690236 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6681 09:32:29.693697 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6682 09:32:29.700427 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6683 09:32:29.703077 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6684 09:32:29.707119 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6685 09:32:29.710194 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6686 09:32:29.716722 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6687 09:32:29.720076 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6688 09:32:29.723392 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6689 09:32:29.726667 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6690 09:32:29.733222 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6691 09:32:29.736733 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6692 09:32:29.740138 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6693 09:32:29.743548 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6694 09:32:29.749972 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6695 09:32:29.753077 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6696 09:32:29.753153 ==
6697 09:32:29.756421 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 09:32:29.759755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 09:32:29.759830 ==
6700 09:32:29.763523 DQS Delay:
6701 09:32:29.763620 DQS0 = 27, DQS1 = 27
6702 09:32:29.766479 DQM Delay:
6703 09:32:29.766552 DQM0 = 11, DQM1 = 8
6704 09:32:29.766614 DQ Delay:
6705 09:32:29.769719 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6706 09:32:29.772924 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6707 09:32:29.776443 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6708 09:32:29.779695 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6709 09:32:29.779780
6710 09:32:29.779841
6711 09:32:29.779897 ==
6712 09:32:29.783014 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 09:32:29.786499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 09:32:29.789678 ==
6715 09:32:29.789783
6716 09:32:29.789876
6717 09:32:29.789963 TX Vref Scan disable
6718 09:32:29.793340 == TX Byte 0 ==
6719 09:32:29.796516 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 09:32:29.799959 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 09:32:29.803302 == TX Byte 1 ==
6722 09:32:29.806014 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 09:32:29.809487 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 09:32:29.809566 ==
6725 09:32:29.812784 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 09:32:29.816563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 09:32:29.819782 ==
6728 09:32:29.819857
6729 09:32:29.819919
6730 09:32:29.819984 TX Vref Scan disable
6731 09:32:29.822955 == TX Byte 0 ==
6732 09:32:29.826107 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 09:32:29.829426 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 09:32:29.832815 == TX Byte 1 ==
6735 09:32:29.836229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 09:32:29.839560 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 09:32:29.839694
6738 09:32:29.842908 [DATLAT]
6739 09:32:29.843013 Freq=400, CH1 RK0
6740 09:32:29.843105
6741 09:32:29.846217 DATLAT Default: 0xf
6742 09:32:29.846297 0, 0xFFFF, sum = 0
6743 09:32:29.849494 1, 0xFFFF, sum = 0
6744 09:32:29.849575 2, 0xFFFF, sum = 0
6745 09:32:29.852915 3, 0xFFFF, sum = 0
6746 09:32:29.853023 4, 0xFFFF, sum = 0
6747 09:32:29.855944 5, 0xFFFF, sum = 0
6748 09:32:29.856025 6, 0xFFFF, sum = 0
6749 09:32:29.859347 7, 0xFFFF, sum = 0
6750 09:32:29.859454 8, 0xFFFF, sum = 0
6751 09:32:29.862701 9, 0xFFFF, sum = 0
6752 09:32:29.862793 10, 0xFFFF, sum = 0
6753 09:32:29.866137 11, 0xFFFF, sum = 0
6754 09:32:29.869240 12, 0xFFFF, sum = 0
6755 09:32:29.869321 13, 0x0, sum = 1
6756 09:32:29.869392 14, 0x0, sum = 2
6757 09:32:29.872550 15, 0x0, sum = 3
6758 09:32:29.872702 16, 0x0, sum = 4
6759 09:32:29.876121 best_step = 14
6760 09:32:29.876202
6761 09:32:29.876265 ==
6762 09:32:29.879057 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 09:32:29.882815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 09:32:29.882895 ==
6765 09:32:29.885771 RX Vref Scan: 1
6766 09:32:29.885859
6767 09:32:29.885925 RX Vref 0 -> 0, step: 1
6768 09:32:29.885991
6769 09:32:29.888941 RX Delay -295 -> 252, step: 8
6770 09:32:29.889034
6771 09:32:29.892819 Set Vref, RX VrefLevel [Byte0]: 53
6772 09:32:29.896092 [Byte1]: 53
6773 09:32:29.900303
6774 09:32:29.900382 Final RX Vref Byte 0 = 53 to rank0
6775 09:32:29.903736 Final RX Vref Byte 1 = 53 to rank0
6776 09:32:29.906995 Final RX Vref Byte 0 = 53 to rank1
6777 09:32:29.910352 Final RX Vref Byte 1 = 53 to rank1==
6778 09:32:29.913691 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 09:32:29.920290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 09:32:29.920398 ==
6781 09:32:29.920489 DQS Delay:
6782 09:32:29.923599 DQS0 = 32, DQS1 = 32
6783 09:32:29.923733 DQM Delay:
6784 09:32:29.923798 DQM0 = 13, DQM1 = 9
6785 09:32:29.926972 DQ Delay:
6786 09:32:29.930183 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6787 09:32:29.933799 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6788 09:32:29.933896 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6789 09:32:29.937005 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6790 09:32:29.937103
6791 09:32:29.940435
6792 09:32:29.946456 [DQSOSCAuto] RK0, (LSB)MR18= 0x91c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6793 09:32:29.949790 CH1 RK0: MR19=C0C, MR18=91C9
6794 09:32:29.957087 CH1_RK0: MR19=0xC0C, MR18=0x91C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6795 09:32:29.957167 ==
6796 09:32:29.960391 Dram Type= 6, Freq= 0, CH_1, rank 1
6797 09:32:29.963756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 09:32:29.963837 ==
6799 09:32:29.966897 [Gating] SW mode calibration
6800 09:32:29.973393 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6801 09:32:29.979884 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6802 09:32:29.983442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6803 09:32:29.986876 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 09:32:29.992982 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 09:32:29.996402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 09:32:29.999819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 09:32:30.006293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 09:32:30.009806 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 09:32:30.013303 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 09:32:30.020115 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 09:32:30.020196 Total UI for P1: 0, mck2ui 16
6812 09:32:30.023451 best dqsien dly found for B0: ( 0, 14, 24)
6813 09:32:30.026805 Total UI for P1: 0, mck2ui 16
6814 09:32:30.030117 best dqsien dly found for B1: ( 0, 14, 24)
6815 09:32:30.033426 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6816 09:32:30.040065 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6817 09:32:30.040145
6818 09:32:30.043213 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6819 09:32:30.046405 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 09:32:30.049686 [Gating] SW calibration Done
6821 09:32:30.049758 ==
6822 09:32:30.053034 Dram Type= 6, Freq= 0, CH_1, rank 1
6823 09:32:30.056312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 09:32:30.056382 ==
6825 09:32:30.059587 RX Vref Scan: 0
6826 09:32:30.059711
6827 09:32:30.059771 RX Vref 0 -> 0, step: 1
6828 09:32:30.059838
6829 09:32:30.062770 RX Delay -410 -> 252, step: 16
6830 09:32:30.066182 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6831 09:32:30.072841 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6832 09:32:30.076081 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6833 09:32:30.079404 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6834 09:32:30.083235 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6835 09:32:30.089747 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6836 09:32:30.092983 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6837 09:32:30.096119 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6838 09:32:30.099315 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6839 09:32:30.106503 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6840 09:32:30.109457 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6841 09:32:30.112997 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6842 09:32:30.116353 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6843 09:32:30.122929 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6844 09:32:30.125925 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6845 09:32:30.129581 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6846 09:32:30.129656 ==
6847 09:32:30.132980 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 09:32:30.139253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 09:32:30.139355 ==
6850 09:32:30.139454 DQS Delay:
6851 09:32:30.139570 DQS0 = 35, DQS1 = 35
6852 09:32:30.142458 DQM Delay:
6853 09:32:30.142529 DQM0 = 18, DQM1 = 14
6854 09:32:30.146322 DQ Delay:
6855 09:32:30.149510 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6856 09:32:30.152756 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6857 09:32:30.152838 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6858 09:32:30.155995 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6859 09:32:30.156073
6860 09:32:30.159280
6861 09:32:30.159352 ==
6862 09:32:30.162637 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 09:32:30.165922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 09:32:30.166002 ==
6865 09:32:30.166066
6866 09:32:30.166127
6867 09:32:30.169208 TX Vref Scan disable
6868 09:32:30.169304 == TX Byte 0 ==
6869 09:32:30.172433 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6870 09:32:30.179342 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6871 09:32:30.179428 == TX Byte 1 ==
6872 09:32:30.182806 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6873 09:32:30.189323 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6874 09:32:30.189415 ==
6875 09:32:30.192502 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 09:32:30.195984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 09:32:30.196064 ==
6878 09:32:30.196128
6879 09:32:30.196187
6880 09:32:30.199352 TX Vref Scan disable
6881 09:32:30.199431 == TX Byte 0 ==
6882 09:32:30.202687 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 09:32:30.209259 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 09:32:30.209342 == TX Byte 1 ==
6885 09:32:30.212743 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6886 09:32:30.218924 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6887 09:32:30.219004
6888 09:32:30.219122 [DATLAT]
6889 09:32:30.219200 Freq=400, CH1 RK1
6890 09:32:30.219295
6891 09:32:30.222108 DATLAT Default: 0xe
6892 09:32:30.226016 0, 0xFFFF, sum = 0
6893 09:32:30.226097 1, 0xFFFF, sum = 0
6894 09:32:30.228976 2, 0xFFFF, sum = 0
6895 09:32:30.229057 3, 0xFFFF, sum = 0
6896 09:32:30.232534 4, 0xFFFF, sum = 0
6897 09:32:30.232615 5, 0xFFFF, sum = 0
6898 09:32:30.235456 6, 0xFFFF, sum = 0
6899 09:32:30.235538 7, 0xFFFF, sum = 0
6900 09:32:30.239013 8, 0xFFFF, sum = 0
6901 09:32:30.239096 9, 0xFFFF, sum = 0
6902 09:32:30.242138 10, 0xFFFF, sum = 0
6903 09:32:30.242220 11, 0xFFFF, sum = 0
6904 09:32:30.245696 12, 0xFFFF, sum = 0
6905 09:32:30.245777 13, 0x0, sum = 1
6906 09:32:30.248971 14, 0x0, sum = 2
6907 09:32:30.249053 15, 0x0, sum = 3
6908 09:32:30.252206 16, 0x0, sum = 4
6909 09:32:30.252287 best_step = 14
6910 09:32:30.252351
6911 09:32:30.252410 ==
6912 09:32:30.255342 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 09:32:30.262496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 09:32:30.262577 ==
6915 09:32:30.262641 RX Vref Scan: 0
6916 09:32:30.262704
6917 09:32:30.265813 RX Vref 0 -> 0, step: 1
6918 09:32:30.265896
6919 09:32:30.268573 RX Delay -311 -> 252, step: 8
6920 09:32:30.275106 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6921 09:32:30.278467 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6922 09:32:30.281946 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6923 09:32:30.285311 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6924 09:32:30.292084 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6925 09:32:30.295519 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6926 09:32:30.298732 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6927 09:32:30.302187 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6928 09:32:30.305542 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6929 09:32:30.312456 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6930 09:32:30.315123 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6931 09:32:30.318604 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6932 09:32:30.321981 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6933 09:32:30.329107 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6934 09:32:30.332577 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6935 09:32:30.335871 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6936 09:32:30.335953 ==
6937 09:32:30.338893 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 09:32:30.345584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 09:32:30.345695 ==
6940 09:32:30.345791 DQS Delay:
6941 09:32:30.348675 DQS0 = 28, DQS1 = 36
6942 09:32:30.348756 DQM Delay:
6943 09:32:30.348820 DQM0 = 11, DQM1 = 15
6944 09:32:30.351971 DQ Delay:
6945 09:32:30.355490 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6946 09:32:30.355597 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6947 09:32:30.358642 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6948 09:32:30.362377 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6949 09:32:30.362487
6950 09:32:30.362580
6951 09:32:30.371966 [DQSOSCAuto] RK1, (LSB)MR18= 0xc659, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6952 09:32:30.375356 CH1 RK1: MR19=C0C, MR18=C659
6953 09:32:30.382006 CH1_RK1: MR19=0xC0C, MR18=0xC659, DQSOSC=385, MR23=63, INC=398, DEC=265
6954 09:32:30.385422 [RxdqsGatingPostProcess] freq 400
6955 09:32:30.388944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6956 09:32:30.392187 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 09:32:30.395520 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 09:32:30.398229 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 09:32:30.401619 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 09:32:30.405325 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 09:32:30.408686 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 09:32:30.412094 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 09:32:30.415442 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 09:32:30.418803 Pre-setting of DQS Precalculation
6965 09:32:30.422117 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6966 09:32:30.428779 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6967 09:32:30.438367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6968 09:32:30.438449
6969 09:32:30.438513
6970 09:32:30.438573 [Calibration Summary] 800 Mbps
6971 09:32:30.441658 CH 0, Rank 0
6972 09:32:30.441755 SW Impedance : PASS
6973 09:32:30.444965 DUTY Scan : NO K
6974 09:32:30.448473 ZQ Calibration : PASS
6975 09:32:30.448553 Jitter Meter : NO K
6976 09:32:30.451797 CBT Training : PASS
6977 09:32:30.455205 Write leveling : PASS
6978 09:32:30.455285 RX DQS gating : PASS
6979 09:32:30.458561 RX DQ/DQS(RDDQC) : PASS
6980 09:32:30.461754 TX DQ/DQS : PASS
6981 09:32:30.461835 RX DATLAT : PASS
6982 09:32:30.465326 RX DQ/DQS(Engine): PASS
6983 09:32:30.468166 TX OE : NO K
6984 09:32:30.468246 All Pass.
6985 09:32:30.468310
6986 09:32:30.468368 CH 0, Rank 1
6987 09:32:30.471969 SW Impedance : PASS
6988 09:32:30.475083 DUTY Scan : NO K
6989 09:32:30.475164 ZQ Calibration : PASS
6990 09:32:30.478226 Jitter Meter : NO K
6991 09:32:30.481687 CBT Training : PASS
6992 09:32:30.481768 Write leveling : NO K
6993 09:32:30.485044 RX DQS gating : PASS
6994 09:32:30.485124 RX DQ/DQS(RDDQC) : PASS
6995 09:32:30.488595 TX DQ/DQS : PASS
6996 09:32:30.491773 RX DATLAT : PASS
6997 09:32:30.491853 RX DQ/DQS(Engine): PASS
6998 09:32:30.495128 TX OE : NO K
6999 09:32:30.495208 All Pass.
7000 09:32:30.495272
7001 09:32:30.498508 CH 1, Rank 0
7002 09:32:30.498587 SW Impedance : PASS
7003 09:32:30.501783 DUTY Scan : NO K
7004 09:32:30.505222 ZQ Calibration : PASS
7005 09:32:30.505301 Jitter Meter : NO K
7006 09:32:30.508421 CBT Training : PASS
7007 09:32:30.511614 Write leveling : PASS
7008 09:32:30.511759 RX DQS gating : PASS
7009 09:32:30.515107 RX DQ/DQS(RDDQC) : PASS
7010 09:32:30.518461 TX DQ/DQS : PASS
7011 09:32:30.518542 RX DATLAT : PASS
7012 09:32:30.521764 RX DQ/DQS(Engine): PASS
7013 09:32:30.525106 TX OE : NO K
7014 09:32:30.525187 All Pass.
7015 09:32:30.525252
7016 09:32:30.525313 CH 1, Rank 1
7017 09:32:30.528365 SW Impedance : PASS
7018 09:32:30.531184 DUTY Scan : NO K
7019 09:32:30.531265 ZQ Calibration : PASS
7020 09:32:30.534429 Jitter Meter : NO K
7021 09:32:30.537760 CBT Training : PASS
7022 09:32:30.537861 Write leveling : NO K
7023 09:32:30.541261 RX DQS gating : PASS
7024 09:32:30.541342 RX DQ/DQS(RDDQC) : PASS
7025 09:32:30.544958 TX DQ/DQS : PASS
7026 09:32:30.547996 RX DATLAT : PASS
7027 09:32:30.548097 RX DQ/DQS(Engine): PASS
7028 09:32:30.551307 TX OE : NO K
7029 09:32:30.551404 All Pass.
7030 09:32:30.551491
7031 09:32:30.554429 DramC Write-DBI off
7032 09:32:30.557621 PER_BANK_REFRESH: Hybrid Mode
7033 09:32:30.557761 TX_TRACKING: ON
7034 09:32:30.567794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7035 09:32:30.570959 [FAST_K] Save calibration result to emmc
7036 09:32:30.574664 dramc_set_vcore_voltage set vcore to 725000
7037 09:32:30.577715 Read voltage for 1600, 0
7038 09:32:30.577868 Vio18 = 0
7039 09:32:30.578057 Vcore = 725000
7040 09:32:30.581386 Vdram = 0
7041 09:32:30.581467 Vddq = 0
7042 09:32:30.581532 Vmddr = 0
7043 09:32:30.587602 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7044 09:32:30.591421 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7045 09:32:30.594628 MEM_TYPE=3, freq_sel=13
7046 09:32:30.597716 sv_algorithm_assistance_LP4_3733
7047 09:32:30.601075 ============ PULL DRAM RESETB DOWN ============
7048 09:32:30.608057 ========== PULL DRAM RESETB DOWN end =========
7049 09:32:30.611471 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7050 09:32:30.614628 ===================================
7051 09:32:30.618014 LPDDR4 DRAM CONFIGURATION
7052 09:32:30.621354 ===================================
7053 09:32:30.621436 EX_ROW_EN[0] = 0x0
7054 09:32:30.624676 EX_ROW_EN[1] = 0x0
7055 09:32:30.624812 LP4Y_EN = 0x0
7056 09:32:30.627837 WORK_FSP = 0x1
7057 09:32:30.627920 WL = 0x5
7058 09:32:30.631215 RL = 0x5
7059 09:32:30.631295 BL = 0x2
7060 09:32:30.634435 RPST = 0x0
7061 09:32:30.634515 RD_PRE = 0x0
7062 09:32:30.637643 WR_PRE = 0x1
7063 09:32:30.637724 WR_PST = 0x1
7064 09:32:30.640993 DBI_WR = 0x0
7065 09:32:30.644404 DBI_RD = 0x0
7066 09:32:30.644484 OTF = 0x1
7067 09:32:30.647872 ===================================
7068 09:32:30.650993 ===================================
7069 09:32:30.651076 ANA top config
7070 09:32:30.654523 ===================================
7071 09:32:30.657719 DLL_ASYNC_EN = 0
7072 09:32:30.660730 ALL_SLAVE_EN = 0
7073 09:32:30.664237 NEW_RANK_MODE = 1
7074 09:32:30.664318 DLL_IDLE_MODE = 1
7075 09:32:30.667759 LP45_APHY_COMB_EN = 1
7076 09:32:30.671125 TX_ODT_DIS = 0
7077 09:32:30.674465 NEW_8X_MODE = 1
7078 09:32:30.677765 ===================================
7079 09:32:30.680881 ===================================
7080 09:32:30.684113 data_rate = 3200
7081 09:32:30.687657 CKR = 1
7082 09:32:30.687750 DQ_P2S_RATIO = 8
7083 09:32:30.691105 ===================================
7084 09:32:30.694557 CA_P2S_RATIO = 8
7085 09:32:30.697916 DQ_CA_OPEN = 0
7086 09:32:30.701244 DQ_SEMI_OPEN = 0
7087 09:32:30.704402 CA_SEMI_OPEN = 0
7088 09:32:30.704485 CA_FULL_RATE = 0
7089 09:32:30.707588 DQ_CKDIV4_EN = 0
7090 09:32:30.710678 CA_CKDIV4_EN = 0
7091 09:32:30.714228 CA_PREDIV_EN = 0
7092 09:32:30.717360 PH8_DLY = 12
7093 09:32:30.721185 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7094 09:32:30.721266 DQ_AAMCK_DIV = 4
7095 09:32:30.724411 CA_AAMCK_DIV = 4
7096 09:32:30.727572 CA_ADMCK_DIV = 4
7097 09:32:30.731024 DQ_TRACK_CA_EN = 0
7098 09:32:30.734460 CA_PICK = 1600
7099 09:32:30.737624 CA_MCKIO = 1600
7100 09:32:30.740839 MCKIO_SEMI = 0
7101 09:32:30.740920 PLL_FREQ = 3068
7102 09:32:30.744578 DQ_UI_PI_RATIO = 32
7103 09:32:30.747918 CA_UI_PI_RATIO = 0
7104 09:32:30.751227 ===================================
7105 09:32:30.754699 ===================================
7106 09:32:30.757955 memory_type:LPDDR4
7107 09:32:30.761191 GP_NUM : 10
7108 09:32:30.761271 SRAM_EN : 1
7109 09:32:30.764305 MD32_EN : 0
7110 09:32:30.767331 ===================================
7111 09:32:30.767411 [ANA_INIT] >>>>>>>>>>>>>>
7112 09:32:30.770898 <<<<<< [CONFIGURE PHASE]: ANA_TX
7113 09:32:30.774029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7114 09:32:30.777316 ===================================
7115 09:32:30.780736 data_rate = 3200,PCW = 0X7600
7116 09:32:30.784104 ===================================
7117 09:32:30.787369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7118 09:32:30.793806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7119 09:32:30.800643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 09:32:30.804155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7121 09:32:30.807569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7122 09:32:30.810168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7123 09:32:30.813657 [ANA_INIT] flow start
7124 09:32:30.813738 [ANA_INIT] PLL >>>>>>>>
7125 09:32:30.816930 [ANA_INIT] PLL <<<<<<<<
7126 09:32:30.820922 [ANA_INIT] MIDPI >>>>>>>>
7127 09:32:30.821006 [ANA_INIT] MIDPI <<<<<<<<
7128 09:32:30.824050 [ANA_INIT] DLL >>>>>>>>
7129 09:32:30.827281 [ANA_INIT] DLL <<<<<<<<
7130 09:32:30.827361 [ANA_INIT] flow end
7131 09:32:30.833953 ============ LP4 DIFF to SE enter ============
7132 09:32:30.836989 ============ LP4 DIFF to SE exit ============
7133 09:32:30.840579 [ANA_INIT] <<<<<<<<<<<<<
7134 09:32:30.843950 [Flow] Enable top DCM control >>>>>
7135 09:32:30.847176 [Flow] Enable top DCM control <<<<<
7136 09:32:30.847257 Enable DLL master slave shuffle
7137 09:32:30.853388 ==============================================================
7138 09:32:30.856829 Gating Mode config
7139 09:32:30.860074 ==============================================================
7140 09:32:30.863540 Config description:
7141 09:32:30.873612 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7142 09:32:30.880220 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7143 09:32:30.883507 SELPH_MODE 0: By rank 1: By Phase
7144 09:32:30.890080 ==============================================================
7145 09:32:30.893237 GAT_TRACK_EN = 1
7146 09:32:30.896492 RX_GATING_MODE = 2
7147 09:32:30.899924 RX_GATING_TRACK_MODE = 2
7148 09:32:30.903273 SELPH_MODE = 1
7149 09:32:30.903398 PICG_EARLY_EN = 1
7150 09:32:30.906453 VALID_LAT_VALUE = 1
7151 09:32:30.913356 ==============================================================
7152 09:32:30.916737 Enter into Gating configuration >>>>
7153 09:32:30.920112 Exit from Gating configuration <<<<
7154 09:32:30.923556 Enter into DVFS_PRE_config >>>>>
7155 09:32:30.933419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7156 09:32:30.936700 Exit from DVFS_PRE_config <<<<<
7157 09:32:30.939930 Enter into PICG configuration >>>>
7158 09:32:30.942993 Exit from PICG configuration <<<<
7159 09:32:30.946766 [RX_INPUT] configuration >>>>>
7160 09:32:30.950096 [RX_INPUT] configuration <<<<<
7161 09:32:30.953568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7162 09:32:30.959860 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7163 09:32:30.966078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 09:32:30.972684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 09:32:30.979978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 09:32:30.983151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 09:32:30.989315 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7168 09:32:30.993197 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7169 09:32:30.996509 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7170 09:32:30.999752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7171 09:32:31.006311 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7172 09:32:31.009629 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7173 09:32:31.012961 ===================================
7174 09:32:31.016207 LPDDR4 DRAM CONFIGURATION
7175 09:32:31.019310 ===================================
7176 09:32:31.019391 EX_ROW_EN[0] = 0x0
7177 09:32:31.022672 EX_ROW_EN[1] = 0x0
7178 09:32:31.022752 LP4Y_EN = 0x0
7179 09:32:31.026008 WORK_FSP = 0x1
7180 09:32:31.026089 WL = 0x5
7181 09:32:31.029349 RL = 0x5
7182 09:32:31.029429 BL = 0x2
7183 09:32:31.033041 RPST = 0x0
7184 09:32:31.033121 RD_PRE = 0x0
7185 09:32:31.036279 WR_PRE = 0x1
7186 09:32:31.036359 WR_PST = 0x1
7187 09:32:31.039318 DBI_WR = 0x0
7188 09:32:31.039398 DBI_RD = 0x0
7189 09:32:31.042678 OTF = 0x1
7190 09:32:31.045996 ===================================
7191 09:32:31.049251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7192 09:32:31.052964 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7193 09:32:31.059445 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 09:32:31.062714 ===================================
7195 09:32:31.065994 LPDDR4 DRAM CONFIGURATION
7196 09:32:31.069254 ===================================
7197 09:32:31.069335 EX_ROW_EN[0] = 0x10
7198 09:32:31.072710 EX_ROW_EN[1] = 0x0
7199 09:32:31.072790 LP4Y_EN = 0x0
7200 09:32:31.075798 WORK_FSP = 0x1
7201 09:32:31.075877 WL = 0x5
7202 09:32:31.079131 RL = 0x5
7203 09:32:31.079227 BL = 0x2
7204 09:32:31.082276 RPST = 0x0
7205 09:32:31.082401 RD_PRE = 0x0
7206 09:32:31.085754 WR_PRE = 0x1
7207 09:32:31.085924 WR_PST = 0x1
7208 09:32:31.089084 DBI_WR = 0x0
7209 09:32:31.089165 DBI_RD = 0x0
7210 09:32:31.092303 OTF = 0x1
7211 09:32:31.095922 ===================================
7212 09:32:31.102714 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7213 09:32:31.102796 ==
7214 09:32:31.106146 Dram Type= 6, Freq= 0, CH_0, rank 0
7215 09:32:31.109514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7216 09:32:31.109596 ==
7217 09:32:31.112355 [Duty_Offset_Calibration]
7218 09:32:31.112436 B0:2 B1:1 CA:1
7219 09:32:31.112501
7220 09:32:31.115801 [DutyScan_Calibration_Flow] k_type=0
7221 09:32:31.126788
7222 09:32:31.126870 ==CLK 0==
7223 09:32:31.129996 Final CLK duty delay cell = 0
7224 09:32:31.133306 [0] MAX Duty = 5156%(X100), DQS PI = 22
7225 09:32:31.136634 [0] MIN Duty = 4876%(X100), DQS PI = 48
7226 09:32:31.139862 [0] AVG Duty = 5016%(X100)
7227 09:32:31.139943
7228 09:32:31.143184 CH0 CLK Duty spec in!! Max-Min= 280%
7229 09:32:31.146371 [DutyScan_Calibration_Flow] ====Done====
7230 09:32:31.146453
7231 09:32:31.149828 [DutyScan_Calibration_Flow] k_type=1
7232 09:32:31.165783
7233 09:32:31.165865 ==DQS 0 ==
7234 09:32:31.169348 Final DQS duty delay cell = -4
7235 09:32:31.172623 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7236 09:32:31.176014 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7237 09:32:31.179371 [-4] AVG Duty = 4906%(X100)
7238 09:32:31.179453
7239 09:32:31.179518 ==DQS 1 ==
7240 09:32:31.182565 Final DQS duty delay cell = 0
7241 09:32:31.185739 [0] MAX Duty = 5187%(X100), DQS PI = 2
7242 09:32:31.189217 [0] MIN Duty = 5062%(X100), DQS PI = 32
7243 09:32:31.192746 [0] AVG Duty = 5124%(X100)
7244 09:32:31.192827
7245 09:32:31.196057 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7246 09:32:31.196137
7247 09:32:31.199254 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7248 09:32:31.202336 [DutyScan_Calibration_Flow] ====Done====
7249 09:32:31.202415
7250 09:32:31.205861 [DutyScan_Calibration_Flow] k_type=3
7251 09:32:31.222298
7252 09:32:31.222384 ==DQM 0 ==
7253 09:32:31.225620 Final DQM duty delay cell = 0
7254 09:32:31.228897 [0] MAX Duty = 5218%(X100), DQS PI = 34
7255 09:32:31.232450 [0] MIN Duty = 4876%(X100), DQS PI = 60
7256 09:32:31.235541 [0] AVG Duty = 5047%(X100)
7257 09:32:31.235622
7258 09:32:31.235730 ==DQM 1 ==
7259 09:32:31.239338 Final DQM duty delay cell = -4
7260 09:32:31.242009 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7261 09:32:31.245879 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7262 09:32:31.248730 [-4] AVG Duty = 4906%(X100)
7263 09:32:31.248810
7264 09:32:31.252475 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7265 09:32:31.252556
7266 09:32:31.255802 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7267 09:32:31.259083 [DutyScan_Calibration_Flow] ====Done====
7268 09:32:31.259163
7269 09:32:31.261928 [DutyScan_Calibration_Flow] k_type=2
7270 09:32:31.279936
7271 09:32:31.280016 ==DQ 0 ==
7272 09:32:31.283401 Final DQ duty delay cell = 0
7273 09:32:31.286792 [0] MAX Duty = 5062%(X100), DQS PI = 24
7274 09:32:31.290355 [0] MIN Duty = 4907%(X100), DQS PI = 0
7275 09:32:31.290435 [0] AVG Duty = 4984%(X100)
7276 09:32:31.290500
7277 09:32:31.293674 ==DQ 1 ==
7278 09:32:31.296727 Final DQ duty delay cell = 0
7279 09:32:31.299632 [0] MAX Duty = 5156%(X100), DQS PI = 22
7280 09:32:31.303155 [0] MIN Duty = 4907%(X100), DQS PI = 34
7281 09:32:31.303235 [0] AVG Duty = 5031%(X100)
7282 09:32:31.303299
7283 09:32:31.306409 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7284 09:32:31.310277
7285 09:32:31.313243 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7286 09:32:31.316739 [DutyScan_Calibration_Flow] ====Done====
7287 09:32:31.316884 ==
7288 09:32:31.320141 Dram Type= 6, Freq= 0, CH_1, rank 0
7289 09:32:31.323153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7290 09:32:31.323238 ==
7291 09:32:31.326636 [Duty_Offset_Calibration]
7292 09:32:31.326722 B0:1 B1:0 CA:0
7293 09:32:31.326795
7294 09:32:31.330110 [DutyScan_Calibration_Flow] k_type=0
7295 09:32:31.339482
7296 09:32:31.339564 ==CLK 0==
7297 09:32:31.342887 Final CLK duty delay cell = -4
7298 09:32:31.345913 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7299 09:32:31.349555 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7300 09:32:31.352804 [-4] AVG Duty = 4906%(X100)
7301 09:32:31.352908
7302 09:32:31.356131 CH1 CLK Duty spec in!! Max-Min= 125%
7303 09:32:31.359287 [DutyScan_Calibration_Flow] ====Done====
7304 09:32:31.359366
7305 09:32:31.362689 [DutyScan_Calibration_Flow] k_type=1
7306 09:32:31.379554
7307 09:32:31.379648 ==DQS 0 ==
7308 09:32:31.382790 Final DQS duty delay cell = 0
7309 09:32:31.386153 [0] MAX Duty = 5094%(X100), DQS PI = 8
7310 09:32:31.389296 [0] MIN Duty = 4875%(X100), DQS PI = 0
7311 09:32:31.389377 [0] AVG Duty = 4984%(X100)
7312 09:32:31.392409
7313 09:32:31.392489 ==DQS 1 ==
7314 09:32:31.396014 Final DQS duty delay cell = 0
7315 09:32:31.399321 [0] MAX Duty = 5281%(X100), DQS PI = 18
7316 09:32:31.402711 [0] MIN Duty = 4969%(X100), DQS PI = 6
7317 09:32:31.402822 [0] AVG Duty = 5125%(X100)
7318 09:32:31.406193
7319 09:32:31.409337 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7320 09:32:31.409423
7321 09:32:31.412528 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7322 09:32:31.416107 [DutyScan_Calibration_Flow] ====Done====
7323 09:32:31.416190
7324 09:32:31.419227 [DutyScan_Calibration_Flow] k_type=3
7325 09:32:31.436157
7326 09:32:31.436240 ==DQM 0 ==
7327 09:32:31.439457 Final DQM duty delay cell = 0
7328 09:32:31.442886 [0] MAX Duty = 5218%(X100), DQS PI = 18
7329 09:32:31.446343 [0] MIN Duty = 4969%(X100), DQS PI = 48
7330 09:32:31.449722 [0] AVG Duty = 5093%(X100)
7331 09:32:31.449804
7332 09:32:31.449869 ==DQM 1 ==
7333 09:32:31.453082 Final DQM duty delay cell = 0
7334 09:32:31.456090 [0] MAX Duty = 5093%(X100), DQS PI = 16
7335 09:32:31.459230 [0] MIN Duty = 4907%(X100), DQS PI = 52
7336 09:32:31.462964 [0] AVG Duty = 5000%(X100)
7337 09:32:31.463053
7338 09:32:31.466274 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7339 09:32:31.466360
7340 09:32:31.469622 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7341 09:32:31.473087 [DutyScan_Calibration_Flow] ====Done====
7342 09:32:31.473163
7343 09:32:31.475785 [DutyScan_Calibration_Flow] k_type=2
7344 09:32:31.492260
7345 09:32:31.492370 ==DQ 0 ==
7346 09:32:31.495801 Final DQ duty delay cell = -4
7347 09:32:31.498991 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7348 09:32:31.502334 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7349 09:32:31.505815 [-4] AVG Duty = 4968%(X100)
7350 09:32:31.505889
7351 09:32:31.505951 ==DQ 1 ==
7352 09:32:31.509150 Final DQ duty delay cell = 0
7353 09:32:31.512430 [0] MAX Duty = 5124%(X100), DQS PI = 16
7354 09:32:31.515933 [0] MIN Duty = 4938%(X100), DQS PI = 10
7355 09:32:31.519192 [0] AVG Duty = 5031%(X100)
7356 09:32:31.519292
7357 09:32:31.522296 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7358 09:32:31.522368
7359 09:32:31.525622 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7360 09:32:31.528622 [DutyScan_Calibration_Flow] ====Done====
7361 09:32:31.532513 nWR fixed to 30
7362 09:32:31.535823 [ModeRegInit_LP4] CH0 RK0
7363 09:32:31.535939 [ModeRegInit_LP4] CH0 RK1
7364 09:32:31.538903 [ModeRegInit_LP4] CH1 RK0
7365 09:32:31.541914 [ModeRegInit_LP4] CH1 RK1
7366 09:32:31.541994 match AC timing 5
7367 09:32:31.548630 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7368 09:32:31.551988 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7369 09:32:31.555305 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7370 09:32:31.561655 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7371 09:32:31.564972 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7372 09:32:31.565084 [MiockJmeterHQA]
7373 09:32:31.565184
7374 09:32:31.568749 [DramcMiockJmeter] u1RxGatingPI = 0
7375 09:32:31.572036 0 : 4257, 4030
7376 09:32:31.572117 4 : 4253, 4026
7377 09:32:31.575299 8 : 4252, 4027
7378 09:32:31.575380 12 : 4253, 4026
7379 09:32:31.578759 16 : 4252, 4027
7380 09:32:31.578839 20 : 4363, 4137
7381 09:32:31.578905 24 : 4252, 4026
7382 09:32:31.582063 28 : 4252, 4027
7383 09:32:31.582144 32 : 4253, 4027
7384 09:32:31.584801 36 : 4253, 4027
7385 09:32:31.584882 40 : 4253, 4027
7386 09:32:31.588869 44 : 4254, 4029
7387 09:32:31.588955 48 : 4363, 4138
7388 09:32:31.589020 52 : 4252, 4029
7389 09:32:31.592105 56 : 4252, 4026
7390 09:32:31.592180 60 : 4250, 4026
7391 09:32:31.595192 64 : 4252, 4029
7392 09:32:31.595264 68 : 4250, 4026
7393 09:32:31.598572 72 : 4361, 4137
7394 09:32:31.598645 76 : 4250, 4026
7395 09:32:31.602004 80 : 4249, 4027
7396 09:32:31.602086 84 : 4250, 4027
7397 09:32:31.602150 88 : 4250, 56
7398 09:32:31.605218 92 : 4252, 0
7399 09:32:31.605328 96 : 4363, 0
7400 09:32:31.605393 100 : 4250, 0
7401 09:32:31.608446 104 : 4252, 0
7402 09:32:31.608527 108 : 4253, 0
7403 09:32:31.611692 112 : 4361, 0
7404 09:32:31.611773 116 : 4250, 0
7405 09:32:31.611837 120 : 4250, 0
7406 09:32:31.615118 124 : 4255, 0
7407 09:32:31.615199 128 : 4250, 0
7408 09:32:31.618367 132 : 4363, 0
7409 09:32:31.618449 136 : 4250, 0
7410 09:32:31.618514 140 : 4250, 0
7411 09:32:31.621819 144 : 4250, 0
7412 09:32:31.621900 148 : 4255, 0
7413 09:32:31.621965 152 : 4250, 0
7414 09:32:31.625161 156 : 4250, 0
7415 09:32:31.625241 160 : 4250, 0
7416 09:32:31.628412 164 : 4360, 0
7417 09:32:31.628520 168 : 4250, 0
7418 09:32:31.628621 172 : 4250, 0
7419 09:32:31.631940 176 : 4250, 0
7420 09:32:31.632020 180 : 4360, 0
7421 09:32:31.635005 184 : 4361, 0
7422 09:32:31.635085 188 : 4250, 0
7423 09:32:31.635149 192 : 4360, 0
7424 09:32:31.638220 196 : 4250, 0
7425 09:32:31.638300 200 : 4250, 0
7426 09:32:31.641695 204 : 4250, 1198
7427 09:32:31.641802 208 : 4250, 4009
7428 09:32:31.644942 212 : 4363, 4140
7429 09:32:31.645024 216 : 4250, 4027
7430 09:32:31.648271 220 : 4250, 4027
7431 09:32:31.648352 224 : 4252, 4027
7432 09:32:31.648416 228 : 4253, 4029
7433 09:32:31.651432 232 : 4252, 4027
7434 09:32:31.651513 236 : 4250, 4027
7435 09:32:31.654949 240 : 4361, 4137
7436 09:32:31.655051 244 : 4250, 4026
7437 09:32:31.658504 248 : 4361, 4137
7438 09:32:31.658586 252 : 4361, 4137
7439 09:32:31.661962 256 : 4249, 4027
7440 09:32:31.662042 260 : 4250, 4027
7441 09:32:31.665112 264 : 4252, 4029
7442 09:32:31.665220 268 : 4250, 4027
7443 09:32:31.668611 272 : 4249, 4027
7444 09:32:31.668691 276 : 4250, 4027
7445 09:32:31.671906 280 : 4255, 4031
7446 09:32:31.671987 284 : 4250, 4026
7447 09:32:31.672051 288 : 4361, 4137
7448 09:32:31.674849 292 : 4360, 4137
7449 09:32:31.674962 296 : 4250, 4027
7450 09:32:31.678635 300 : 4250, 4026
7451 09:32:31.678738 304 : 4361, 4137
7452 09:32:31.681685 308 : 4250, 3963
7453 09:32:31.681782 312 : 4250, 1894
7454 09:32:31.681871
7455 09:32:31.685036 MIOCK jitter meter ch=0
7456 09:32:31.685120
7457 09:32:31.688371 1T = (312-88) = 224 dly cells
7458 09:32:31.695124 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7459 09:32:31.695205 ==
7460 09:32:31.698381 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 09:32:31.701580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 09:32:31.701663 ==
7463 09:32:31.708111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 09:32:31.711369 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 09:32:31.715246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 09:32:31.721793 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 09:32:31.729834 [CA 0] Center 42 (12~73) winsize 62
7468 09:32:31.733153 [CA 1] Center 42 (12~73) winsize 62
7469 09:32:31.736450 [CA 2] Center 38 (8~68) winsize 61
7470 09:32:31.739783 [CA 3] Center 37 (8~67) winsize 60
7471 09:32:31.743118 [CA 4] Center 36 (6~66) winsize 61
7472 09:32:31.746878 [CA 5] Center 35 (6~64) winsize 59
7473 09:32:31.746952
7474 09:32:31.749877 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7475 09:32:31.749990
7476 09:32:31.753015 [CATrainingPosCal] consider 1 rank data
7477 09:32:31.756883 u2DelayCellTimex100 = 290/100 ps
7478 09:32:31.759896 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7479 09:32:31.766374 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7480 09:32:31.769881 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7481 09:32:31.773337 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7482 09:32:31.776707 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7483 09:32:31.779891 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7484 09:32:31.779967
7485 09:32:31.783028 CA PerBit enable=1, Macro0, CA PI delay=35
7486 09:32:31.783098
7487 09:32:31.786631 [CBTSetCACLKResult] CA Dly = 35
7488 09:32:31.790000 CS Dly: 9 (0~40)
7489 09:32:31.793091 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 09:32:31.796336 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 09:32:31.796409 ==
7492 09:32:31.799752 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 09:32:31.803028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 09:32:31.803100 ==
7495 09:32:31.809561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 09:32:31.813444 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 09:32:31.819449 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 09:32:31.822830 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 09:32:31.833378 [CA 0] Center 42 (12~73) winsize 62
7500 09:32:31.836682 [CA 1] Center 42 (12~73) winsize 62
7501 09:32:31.839892 [CA 2] Center 38 (8~68) winsize 61
7502 09:32:31.843402 [CA 3] Center 37 (7~67) winsize 61
7503 09:32:31.846692 [CA 4] Center 36 (6~66) winsize 61
7504 09:32:31.849991 [CA 5] Center 34 (5~64) winsize 60
7505 09:32:31.850064
7506 09:32:31.853416 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 09:32:31.853487
7508 09:32:31.856575 [CATrainingPosCal] consider 2 rank data
7509 09:32:31.859593 u2DelayCellTimex100 = 290/100 ps
7510 09:32:31.863198 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7511 09:32:31.869850 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7512 09:32:31.873196 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7513 09:32:31.876546 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7514 09:32:31.879602 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7515 09:32:31.883169 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7516 09:32:31.883241
7517 09:32:31.886114 CA PerBit enable=1, Macro0, CA PI delay=35
7518 09:32:31.886190
7519 09:32:31.889404 [CBTSetCACLKResult] CA Dly = 35
7520 09:32:31.892942 CS Dly: 10 (0~42)
7521 09:32:31.896027 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 09:32:31.899794 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 09:32:31.899869
7524 09:32:31.903277 ----->DramcWriteLeveling(PI) begin...
7525 09:32:31.903352 ==
7526 09:32:31.906454 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 09:32:31.909742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 09:32:31.913043 ==
7529 09:32:31.913128 Write leveling (Byte 0): 37 => 37
7530 09:32:31.916205 Write leveling (Byte 1): 28 => 28
7531 09:32:31.919518 DramcWriteLeveling(PI) end<-----
7532 09:32:31.919630
7533 09:32:31.919721 ==
7534 09:32:31.923335 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 09:32:31.930019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 09:32:31.930145 ==
7537 09:32:31.930238 [Gating] SW mode calibration
7538 09:32:31.939619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 09:32:31.943026 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 09:32:31.949806 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 09:32:31.953161 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 09:32:31.956515 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
7543 09:32:31.959905 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7544 09:32:31.966251 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7545 09:32:31.969515 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7546 09:32:31.973306 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 09:32:31.979499 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 09:32:31.983024 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 09:32:31.986422 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 09:32:31.993466 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7551 09:32:31.996494 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7552 09:32:32.000093 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7553 09:32:32.006200 1 5 20 | B1->B0 | 2626 2524 | 0 1 | (1 0) (0 0)
7554 09:32:32.010116 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7555 09:32:32.013181 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7556 09:32:32.019344 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7557 09:32:32.022700 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7558 09:32:32.026041 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7559 09:32:32.033147 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 09:32:32.036231 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7561 09:32:32.039541 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7562 09:32:32.046424 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 09:32:32.049757 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 09:32:32.053104 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 09:32:32.056647 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 09:32:32.062983 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 09:32:32.066490 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 09:32:32.069654 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7569 09:32:32.076057 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 09:32:32.079417 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 09:32:32.082704 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 09:32:32.089174 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 09:32:32.093140 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 09:32:32.096431 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 09:32:32.103019 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 09:32:32.106378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 09:32:32.109525 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 09:32:32.116326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 09:32:32.119578 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 09:32:32.123029 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 09:32:32.129065 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 09:32:32.132986 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 09:32:32.136172 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 09:32:32.142622 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 09:32:32.146305 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 09:32:32.149468 Total UI for P1: 0, mck2ui 16
7587 09:32:32.152559 best dqsien dly found for B0: ( 1, 9, 12)
7588 09:32:32.156205 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 09:32:32.159532 Total UI for P1: 0, mck2ui 16
7590 09:32:32.162914 best dqsien dly found for B1: ( 1, 9, 20)
7591 09:32:32.165663 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7592 09:32:32.169130 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 09:32:32.169211
7594 09:32:32.172702 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7595 09:32:32.179079 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 09:32:32.179184 [Gating] SW calibration Done
7597 09:32:32.182308 ==
7598 09:32:32.182382 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 09:32:32.189419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 09:32:32.189501 ==
7601 09:32:32.189565 RX Vref Scan: 0
7602 09:32:32.189624
7603 09:32:32.192606 RX Vref 0 -> 0, step: 1
7604 09:32:32.192701
7605 09:32:32.195943 RX Delay 0 -> 252, step: 8
7606 09:32:32.199270 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7607 09:32:32.202510 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7608 09:32:32.205920 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7609 09:32:32.212503 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7610 09:32:32.215739 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7611 09:32:32.218899 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7612 09:32:32.222050 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7613 09:32:32.225964 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7614 09:32:32.232583 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7615 09:32:32.235883 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7616 09:32:32.238931 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7617 09:32:32.242073 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7618 09:32:32.245901 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7619 09:32:32.252364 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7620 09:32:32.255491 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7621 09:32:32.258581 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7622 09:32:32.258653 ==
7623 09:32:32.261916 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 09:32:32.265379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 09:32:32.265460 ==
7626 09:32:32.268680 DQS Delay:
7627 09:32:32.268752 DQS0 = 0, DQS1 = 0
7628 09:32:32.272034 DQM Delay:
7629 09:32:32.272105 DQM0 = 137, DQM1 = 129
7630 09:32:32.272165 DQ Delay:
7631 09:32:32.275341 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7632 09:32:32.282095 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7633 09:32:32.285868 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7634 09:32:32.288906 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7635 09:32:32.288986
7636 09:32:32.289083
7637 09:32:32.289145 ==
7638 09:32:32.292049 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 09:32:32.295444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 09:32:32.295517 ==
7641 09:32:32.295578
7642 09:32:32.295641
7643 09:32:32.299366 TX Vref Scan disable
7644 09:32:32.301950 == TX Byte 0 ==
7645 09:32:32.305939 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7646 09:32:32.309169 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7647 09:32:32.312294 == TX Byte 1 ==
7648 09:32:32.315624 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7649 09:32:32.319128 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7650 09:32:32.319209 ==
7651 09:32:32.322457 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 09:32:32.325798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 09:32:32.328392 ==
7654 09:32:32.340727
7655 09:32:32.343912 TX Vref early break, caculate TX vref
7656 09:32:32.347561 TX Vref=16, minBit 4, minWin=22, winSum=375
7657 09:32:32.350763 TX Vref=18, minBit 0, minWin=23, winSum=387
7658 09:32:32.354004 TX Vref=20, minBit 0, minWin=24, winSum=397
7659 09:32:32.357322 TX Vref=22, minBit 0, minWin=24, winSum=405
7660 09:32:32.360626 TX Vref=24, minBit 0, minWin=25, winSum=412
7661 09:32:32.367404 TX Vref=26, minBit 2, minWin=25, winSum=426
7662 09:32:32.370756 TX Vref=28, minBit 1, minWin=24, winSum=423
7663 09:32:32.374083 TX Vref=30, minBit 1, minWin=25, winSum=417
7664 09:32:32.377507 TX Vref=32, minBit 1, minWin=24, winSum=405
7665 09:32:32.380303 TX Vref=34, minBit 1, minWin=23, winSum=399
7666 09:32:32.387046 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 26
7667 09:32:32.387121
7668 09:32:32.390357 Final TX Range 0 Vref 26
7669 09:32:32.390429
7670 09:32:32.390490 ==
7671 09:32:32.394082 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 09:32:32.397160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 09:32:32.397262 ==
7674 09:32:32.397353
7675 09:32:32.397439
7676 09:32:32.400570 TX Vref Scan disable
7677 09:32:32.406985 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7678 09:32:32.407066 == TX Byte 0 ==
7679 09:32:32.410202 u2DelayCellOfst[0]=10 cells (3 PI)
7680 09:32:32.413536 u2DelayCellOfst[1]=13 cells (4 PI)
7681 09:32:32.417300 u2DelayCellOfst[2]=10 cells (3 PI)
7682 09:32:32.420618 u2DelayCellOfst[3]=6 cells (2 PI)
7683 09:32:32.423944 u2DelayCellOfst[4]=6 cells (2 PI)
7684 09:32:32.426559 u2DelayCellOfst[5]=0 cells (0 PI)
7685 09:32:32.430014 u2DelayCellOfst[6]=13 cells (4 PI)
7686 09:32:32.433813 u2DelayCellOfst[7]=16 cells (5 PI)
7687 09:32:32.437006 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7688 09:32:32.440012 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7689 09:32:32.440086 == TX Byte 1 ==
7690 09:32:32.443397 u2DelayCellOfst[8]=3 cells (1 PI)
7691 09:32:32.446851 u2DelayCellOfst[9]=0 cells (0 PI)
7692 09:32:32.450728 u2DelayCellOfst[10]=6 cells (2 PI)
7693 09:32:32.453806 u2DelayCellOfst[11]=3 cells (1 PI)
7694 09:32:32.456901 u2DelayCellOfst[12]=10 cells (3 PI)
7695 09:32:32.460314 u2DelayCellOfst[13]=10 cells (3 PI)
7696 09:32:32.463426 u2DelayCellOfst[14]=16 cells (5 PI)
7697 09:32:32.466716 u2DelayCellOfst[15]=10 cells (3 PI)
7698 09:32:32.470558 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7699 09:32:32.476918 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7700 09:32:32.477001 DramC Write-DBI on
7701 09:32:32.477067 ==
7702 09:32:32.480394 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 09:32:32.483201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 09:32:32.483273 ==
7705 09:32:32.486600
7706 09:32:32.486680
7707 09:32:32.486744 TX Vref Scan disable
7708 09:32:32.489882 == TX Byte 0 ==
7709 09:32:32.493206 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7710 09:32:32.497000 == TX Byte 1 ==
7711 09:32:32.500262 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7712 09:32:32.503582 DramC Write-DBI off
7713 09:32:32.503718
7714 09:32:32.503783 [DATLAT]
7715 09:32:32.503842 Freq=1600, CH0 RK0
7716 09:32:32.503900
7717 09:32:32.506923 DATLAT Default: 0xf
7718 09:32:32.510003 0, 0xFFFF, sum = 0
7719 09:32:32.510087 1, 0xFFFF, sum = 0
7720 09:32:32.513164 2, 0xFFFF, sum = 0
7721 09:32:32.513237 3, 0xFFFF, sum = 0
7722 09:32:32.516346 4, 0xFFFF, sum = 0
7723 09:32:32.516423 5, 0xFFFF, sum = 0
7724 09:32:32.519525 6, 0xFFFF, sum = 0
7725 09:32:32.519633 7, 0xFFFF, sum = 0
7726 09:32:32.523571 8, 0xFFFF, sum = 0
7727 09:32:32.523705 9, 0xFFFF, sum = 0
7728 09:32:32.526416 10, 0xFFFF, sum = 0
7729 09:32:32.526515 11, 0xFFFF, sum = 0
7730 09:32:32.529756 12, 0xFFFF, sum = 0
7731 09:32:32.529827 13, 0xFFFF, sum = 0
7732 09:32:32.533041 14, 0x0, sum = 1
7733 09:32:32.533118 15, 0x0, sum = 2
7734 09:32:32.536374 16, 0x0, sum = 3
7735 09:32:32.536444 17, 0x0, sum = 4
7736 09:32:32.539829 best_step = 15
7737 09:32:32.539898
7738 09:32:32.539956 ==
7739 09:32:32.542850 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 09:32:32.546666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 09:32:32.546741 ==
7742 09:32:32.550108 RX Vref Scan: 1
7743 09:32:32.550178
7744 09:32:32.550238 Set Vref Range= 24 -> 127
7745 09:32:32.550294
7746 09:32:32.553430 RX Vref 24 -> 127, step: 1
7747 09:32:32.553513
7748 09:32:32.556693 RX Delay 19 -> 252, step: 4
7749 09:32:32.556772
7750 09:32:32.559917 Set Vref, RX VrefLevel [Byte0]: 24
7751 09:32:32.563149 [Byte1]: 24
7752 09:32:32.563253
7753 09:32:32.566419 Set Vref, RX VrefLevel [Byte0]: 25
7754 09:32:32.569691 [Byte1]: 25
7755 09:32:32.569773
7756 09:32:32.573138 Set Vref, RX VrefLevel [Byte0]: 26
7757 09:32:32.576276 [Byte1]: 26
7758 09:32:32.580666
7759 09:32:32.580749 Set Vref, RX VrefLevel [Byte0]: 27
7760 09:32:32.583857 [Byte1]: 27
7761 09:32:32.587609
7762 09:32:32.587735 Set Vref, RX VrefLevel [Byte0]: 28
7763 09:32:32.591046 [Byte1]: 28
7764 09:32:32.595923
7765 09:32:32.595993 Set Vref, RX VrefLevel [Byte0]: 29
7766 09:32:32.599014 [Byte1]: 29
7767 09:32:32.603017
7768 09:32:32.603096 Set Vref, RX VrefLevel [Byte0]: 30
7769 09:32:32.606225 [Byte1]: 30
7770 09:32:32.610717
7771 09:32:32.610790 Set Vref, RX VrefLevel [Byte0]: 31
7772 09:32:32.613965 [Byte1]: 31
7773 09:32:32.617970
7774 09:32:32.618046 Set Vref, RX VrefLevel [Byte0]: 32
7775 09:32:32.621780 [Byte1]: 32
7776 09:32:32.625940
7777 09:32:32.626015 Set Vref, RX VrefLevel [Byte0]: 33
7778 09:32:32.629292 [Byte1]: 33
7779 09:32:32.633369
7780 09:32:32.633448 Set Vref, RX VrefLevel [Byte0]: 34
7781 09:32:32.636738 [Byte1]: 34
7782 09:32:32.641396
7783 09:32:32.641476 Set Vref, RX VrefLevel [Byte0]: 35
7784 09:32:32.644613 [Byte1]: 35
7785 09:32:32.648462
7786 09:32:32.648541 Set Vref, RX VrefLevel [Byte0]: 36
7787 09:32:32.651813 [Byte1]: 36
7788 09:32:32.656429
7789 09:32:32.656508 Set Vref, RX VrefLevel [Byte0]: 37
7790 09:32:32.659780 [Byte1]: 37
7791 09:32:32.663914
7792 09:32:32.663993 Set Vref, RX VrefLevel [Byte0]: 38
7793 09:32:32.667048 [Byte1]: 38
7794 09:32:32.670944
7795 09:32:32.671047 Set Vref, RX VrefLevel [Byte0]: 39
7796 09:32:32.674920 [Byte1]: 39
7797 09:32:32.678791
7798 09:32:32.681848 Set Vref, RX VrefLevel [Byte0]: 40
7799 09:32:32.685217 [Byte1]: 40
7800 09:32:32.685297
7801 09:32:32.688934 Set Vref, RX VrefLevel [Byte0]: 41
7802 09:32:32.692046 [Byte1]: 41
7803 09:32:32.692126
7804 09:32:32.695336 Set Vref, RX VrefLevel [Byte0]: 42
7805 09:32:32.698693 [Byte1]: 42
7806 09:32:32.698799
7807 09:32:32.701780 Set Vref, RX VrefLevel [Byte0]: 43
7808 09:32:32.704984 [Byte1]: 43
7809 09:32:32.709045
7810 09:32:32.709126 Set Vref, RX VrefLevel [Byte0]: 44
7811 09:32:32.712297 [Byte1]: 44
7812 09:32:32.716677
7813 09:32:32.716757 Set Vref, RX VrefLevel [Byte0]: 45
7814 09:32:32.720026 [Byte1]: 45
7815 09:32:32.724179
7816 09:32:32.724258 Set Vref, RX VrefLevel [Byte0]: 46
7817 09:32:32.727421 [Byte1]: 46
7818 09:32:32.732472
7819 09:32:32.732544 Set Vref, RX VrefLevel [Byte0]: 47
7820 09:32:32.734949 [Byte1]: 47
7821 09:32:32.739517
7822 09:32:32.739615 Set Vref, RX VrefLevel [Byte0]: 48
7823 09:32:32.742444 [Byte1]: 48
7824 09:32:32.747091
7825 09:32:32.747162 Set Vref, RX VrefLevel [Byte0]: 49
7826 09:32:32.750317 [Byte1]: 49
7827 09:32:32.754384
7828 09:32:32.754457 Set Vref, RX VrefLevel [Byte0]: 50
7829 09:32:32.758058 [Byte1]: 50
7830 09:32:32.761856
7831 09:32:32.761930 Set Vref, RX VrefLevel [Byte0]: 51
7832 09:32:32.765152 [Byte1]: 51
7833 09:32:32.769795
7834 09:32:32.769865 Set Vref, RX VrefLevel [Byte0]: 52
7835 09:32:32.772940 [Byte1]: 52
7836 09:32:32.777688
7837 09:32:32.777761 Set Vref, RX VrefLevel [Byte0]: 53
7838 09:32:32.780467 [Byte1]: 53
7839 09:32:32.785157
7840 09:32:32.785235 Set Vref, RX VrefLevel [Byte0]: 54
7841 09:32:32.788434 [Byte1]: 54
7842 09:32:32.792364
7843 09:32:32.792435 Set Vref, RX VrefLevel [Byte0]: 55
7844 09:32:32.795578 [Byte1]: 55
7845 09:32:32.800025
7846 09:32:32.800125 Set Vref, RX VrefLevel [Byte0]: 56
7847 09:32:32.803259 [Byte1]: 56
7848 09:32:32.807261
7849 09:32:32.807363 Set Vref, RX VrefLevel [Byte0]: 57
7850 09:32:32.810661 [Byte1]: 57
7851 09:32:32.815475
7852 09:32:32.815554 Set Vref, RX VrefLevel [Byte0]: 58
7853 09:32:32.818547 [Byte1]: 58
7854 09:32:32.822961
7855 09:32:32.823037 Set Vref, RX VrefLevel [Byte0]: 59
7856 09:32:32.825840 [Byte1]: 59
7857 09:32:32.830040
7858 09:32:32.830126 Set Vref, RX VrefLevel [Byte0]: 60
7859 09:32:32.833353 [Byte1]: 60
7860 09:32:32.838061
7861 09:32:32.838140 Set Vref, RX VrefLevel [Byte0]: 61
7862 09:32:32.841411 [Byte1]: 61
7863 09:32:32.845139
7864 09:32:32.845223 Set Vref, RX VrefLevel [Byte0]: 62
7865 09:32:32.848883 [Byte1]: 62
7866 09:32:32.852752
7867 09:32:32.852831 Set Vref, RX VrefLevel [Byte0]: 63
7868 09:32:32.856210 [Byte1]: 63
7869 09:32:32.860820
7870 09:32:32.860895 Set Vref, RX VrefLevel [Byte0]: 64
7871 09:32:32.864081 [Byte1]: 64
7872 09:32:32.868392
7873 09:32:32.868472 Set Vref, RX VrefLevel [Byte0]: 65
7874 09:32:32.871767 [Byte1]: 65
7875 09:32:32.875643
7876 09:32:32.875724 Set Vref, RX VrefLevel [Byte0]: 66
7877 09:32:32.878789 [Byte1]: 66
7878 09:32:32.883486
7879 09:32:32.883565 Set Vref, RX VrefLevel [Byte0]: 67
7880 09:32:32.886832 [Byte1]: 67
7881 09:32:32.890937
7882 09:32:32.891016 Set Vref, RX VrefLevel [Byte0]: 68
7883 09:32:32.893977 [Byte1]: 68
7884 09:32:32.898323
7885 09:32:32.898403 Set Vref, RX VrefLevel [Byte0]: 69
7886 09:32:32.901606 [Byte1]: 69
7887 09:32:32.906062
7888 09:32:32.906135 Set Vref, RX VrefLevel [Byte0]: 70
7889 09:32:32.909030 [Byte1]: 70
7890 09:32:32.913785
7891 09:32:32.913904 Set Vref, RX VrefLevel [Byte0]: 71
7892 09:32:32.917098 [Byte1]: 71
7893 09:32:32.921241
7894 09:32:32.921322 Set Vref, RX VrefLevel [Byte0]: 72
7895 09:32:32.924597 [Byte1]: 72
7896 09:32:32.928565
7897 09:32:32.928645 Set Vref, RX VrefLevel [Byte0]: 73
7898 09:32:32.931669 [Byte1]: 73
7899 09:32:32.936413
7900 09:32:32.936493 Set Vref, RX VrefLevel [Byte0]: 74
7901 09:32:32.939839 [Byte1]: 74
7902 09:32:32.944023
7903 09:32:32.944161 Final RX Vref Byte 0 = 58 to rank0
7904 09:32:32.947162 Final RX Vref Byte 1 = 59 to rank0
7905 09:32:32.950630 Final RX Vref Byte 0 = 58 to rank1
7906 09:32:32.953814 Final RX Vref Byte 1 = 59 to rank1==
7907 09:32:32.957148 Dram Type= 6, Freq= 0, CH_0, rank 0
7908 09:32:32.964153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7909 09:32:32.964244 ==
7910 09:32:32.964331 DQS Delay:
7911 09:32:32.964412 DQS0 = 0, DQS1 = 0
7912 09:32:32.967328 DQM Delay:
7913 09:32:32.967412 DQM0 = 134, DQM1 = 127
7914 09:32:32.970535 DQ Delay:
7915 09:32:32.973730 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7916 09:32:32.977586 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7917 09:32:32.980230 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7918 09:32:32.983974 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7919 09:32:32.984058
7920 09:32:32.984144
7921 09:32:32.984225
7922 09:32:32.986772 [DramC_TX_OE_Calibration] TA2
7923 09:32:32.990889 Original DQ_B0 (3 6) =30, OEN = 27
7924 09:32:32.994055 Original DQ_B1 (3 6) =30, OEN = 27
7925 09:32:32.997612 24, 0x0, End_B0=24 End_B1=24
7926 09:32:32.997701 25, 0x0, End_B0=25 End_B1=25
7927 09:32:33.000761 26, 0x0, End_B0=26 End_B1=26
7928 09:32:33.004027 27, 0x0, End_B0=27 End_B1=27
7929 09:32:33.007352 28, 0x0, End_B0=28 End_B1=28
7930 09:32:33.007438 29, 0x0, End_B0=29 End_B1=29
7931 09:32:33.010209 30, 0x0, End_B0=30 End_B1=30
7932 09:32:33.013471 31, 0x4141, End_B0=30 End_B1=30
7933 09:32:33.017190 Byte0 end_step=30 best_step=27
7934 09:32:33.020175 Byte1 end_step=30 best_step=27
7935 09:32:33.023771 Byte0 TX OE(2T, 0.5T) = (3, 3)
7936 09:32:33.023857 Byte1 TX OE(2T, 0.5T) = (3, 3)
7937 09:32:33.026931
7938 09:32:33.027015
7939 09:32:33.033570 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7940 09:32:33.037309 CH0 RK0: MR19=303, MR18=2420
7941 09:32:33.043798 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7942 09:32:33.043886
7943 09:32:33.047177 ----->DramcWriteLeveling(PI) begin...
7944 09:32:33.047263 ==
7945 09:32:33.050474 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 09:32:33.053210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 09:32:33.053296 ==
7948 09:32:33.057243 Write leveling (Byte 0): 37 => 37
7949 09:32:33.060415 Write leveling (Byte 1): 25 => 25
7950 09:32:33.063587 DramcWriteLeveling(PI) end<-----
7951 09:32:33.063708
7952 09:32:33.063793 ==
7953 09:32:33.066704 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 09:32:33.070036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 09:32:33.070123 ==
7956 09:32:33.073834 [Gating] SW mode calibration
7957 09:32:33.079775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7958 09:32:33.086489 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7959 09:32:33.090286 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 09:32:33.093792 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7961 09:32:33.099832 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 09:32:33.103168 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7963 09:32:33.107133 1 4 16 | B1->B0 | 3333 3838 | 0 0 | (0 0) (0 0)
7964 09:32:33.113823 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7965 09:32:33.116502 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7966 09:32:33.119902 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7967 09:32:33.126495 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7968 09:32:33.130165 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7969 09:32:33.133303 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7970 09:32:33.139899 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
7971 09:32:33.143007 1 5 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
7972 09:32:33.146655 1 5 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7973 09:32:33.153296 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7974 09:32:33.156558 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7975 09:32:33.160018 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7976 09:32:33.166786 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7977 09:32:33.170114 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 09:32:33.172701 1 6 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7979 09:32:33.179896 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7980 09:32:33.183160 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 09:32:33.186571 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 09:32:33.192813 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 09:32:33.196269 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 09:32:33.199765 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 09:32:33.206270 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 09:32:33.209625 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 09:32:33.212828 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7988 09:32:33.219345 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 09:32:33.222703 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 09:32:33.226089 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 09:32:33.229568 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 09:32:33.236268 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 09:32:33.239424 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 09:32:33.242780 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 09:32:33.249205 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 09:32:33.252682 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 09:32:33.255928 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 09:32:33.262548 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 09:32:33.266080 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 09:32:33.269570 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 09:32:33.276041 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 09:32:33.279202 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8003 09:32:33.282592 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8004 09:32:33.289197 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 09:32:33.289282 Total UI for P1: 0, mck2ui 16
8006 09:32:33.295998 best dqsien dly found for B0: ( 1, 9, 14)
8007 09:32:33.296097 Total UI for P1: 0, mck2ui 16
8008 09:32:33.302681 best dqsien dly found for B1: ( 1, 9, 14)
8009 09:32:33.306236 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8010 09:32:33.309164 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8011 09:32:33.309248
8012 09:32:33.312558 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8013 09:32:33.315919 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8014 09:32:33.319836 [Gating] SW calibration Done
8015 09:32:33.319921 ==
8016 09:32:33.323021 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 09:32:33.326359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 09:32:33.326444 ==
8019 09:32:33.329693 RX Vref Scan: 0
8020 09:32:33.329777
8021 09:32:33.329863 RX Vref 0 -> 0, step: 1
8022 09:32:33.329944
8023 09:32:33.332441 RX Delay 0 -> 252, step: 8
8024 09:32:33.335803 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8025 09:32:33.339926 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8026 09:32:33.345921 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8027 09:32:33.349741 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8028 09:32:33.352759 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8029 09:32:33.355975 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8030 09:32:33.359408 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8031 09:32:33.365800 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8032 09:32:33.369687 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8033 09:32:33.372867 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8034 09:32:33.375875 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8035 09:32:33.379127 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8036 09:32:33.385764 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8037 09:32:33.389223 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8038 09:32:33.392438 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8039 09:32:33.396242 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8040 09:32:33.396328 ==
8041 09:32:33.399227 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 09:32:33.406115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 09:32:33.406200 ==
8044 09:32:33.406286 DQS Delay:
8045 09:32:33.409439 DQS0 = 0, DQS1 = 0
8046 09:32:33.409523 DQM Delay:
8047 09:32:33.409610 DQM0 = 137, DQM1 = 128
8048 09:32:33.412588 DQ Delay:
8049 09:32:33.416165 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8050 09:32:33.419220 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8051 09:32:33.422413 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8052 09:32:33.425591 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8053 09:32:33.425675
8054 09:32:33.425761
8055 09:32:33.425841 ==
8056 09:32:33.429530 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 09:32:33.435678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 09:32:33.435764 ==
8059 09:32:33.435849
8060 09:32:33.435930
8061 09:32:33.436008 TX Vref Scan disable
8062 09:32:33.439022 == TX Byte 0 ==
8063 09:32:33.442398 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8064 09:32:33.445718 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8065 09:32:33.449137 == TX Byte 1 ==
8066 09:32:33.452426 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8067 09:32:33.455692 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8068 09:32:33.458872 ==
8069 09:32:33.462713 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 09:32:33.465820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 09:32:33.465905 ==
8072 09:32:33.479314
8073 09:32:33.482578 TX Vref early break, caculate TX vref
8074 09:32:33.485878 TX Vref=16, minBit 1, minWin=23, winSum=382
8075 09:32:33.489725 TX Vref=18, minBit 4, minWin=23, winSum=396
8076 09:32:33.492377 TX Vref=20, minBit 0, minWin=24, winSum=403
8077 09:32:33.496245 TX Vref=22, minBit 2, minWin=24, winSum=409
8078 09:32:33.499350 TX Vref=24, minBit 1, minWin=25, winSum=420
8079 09:32:33.505950 TX Vref=26, minBit 1, minWin=25, winSum=428
8080 09:32:33.509621 TX Vref=28, minBit 2, minWin=25, winSum=424
8081 09:32:33.512344 TX Vref=30, minBit 1, minWin=25, winSum=415
8082 09:32:33.515771 TX Vref=32, minBit 4, minWin=24, winSum=411
8083 09:32:33.518990 TX Vref=34, minBit 0, minWin=24, winSum=399
8084 09:32:33.525934 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8085 09:32:33.526049
8086 09:32:33.528996 Final TX Range 0 Vref 26
8087 09:32:33.529080
8088 09:32:33.529168 ==
8089 09:32:33.532264 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 09:32:33.535560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 09:32:33.535668 ==
8092 09:32:33.535767
8093 09:32:33.535847
8094 09:32:33.539309 TX Vref Scan disable
8095 09:32:33.545434 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8096 09:32:33.545516 == TX Byte 0 ==
8097 09:32:33.548770 u2DelayCellOfst[0]=13 cells (4 PI)
8098 09:32:33.552100 u2DelayCellOfst[1]=16 cells (5 PI)
8099 09:32:33.555522 u2DelayCellOfst[2]=13 cells (4 PI)
8100 09:32:33.559001 u2DelayCellOfst[3]=13 cells (4 PI)
8101 09:32:33.562101 u2DelayCellOfst[4]=10 cells (3 PI)
8102 09:32:33.565514 u2DelayCellOfst[5]=0 cells (0 PI)
8103 09:32:33.568707 u2DelayCellOfst[6]=20 cells (6 PI)
8104 09:32:33.572097 u2DelayCellOfst[7]=16 cells (5 PI)
8105 09:32:33.575475 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8106 09:32:33.578804 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8107 09:32:33.582056 == TX Byte 1 ==
8108 09:32:33.585179 u2DelayCellOfst[8]=3 cells (1 PI)
8109 09:32:33.585262 u2DelayCellOfst[9]=0 cells (0 PI)
8110 09:32:33.588703 u2DelayCellOfst[10]=6 cells (2 PI)
8111 09:32:33.592034 u2DelayCellOfst[11]=3 cells (1 PI)
8112 09:32:33.595229 u2DelayCellOfst[12]=10 cells (3 PI)
8113 09:32:33.598704 u2DelayCellOfst[13]=13 cells (4 PI)
8114 09:32:33.601977 u2DelayCellOfst[14]=13 cells (4 PI)
8115 09:32:33.605768 u2DelayCellOfst[15]=10 cells (3 PI)
8116 09:32:33.609067 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8117 09:32:33.615536 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8118 09:32:33.615669 DramC Write-DBI on
8119 09:32:33.615753 ==
8120 09:32:33.619097 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 09:32:33.622219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 09:32:33.625415 ==
8123 09:32:33.625497
8124 09:32:33.625561
8125 09:32:33.625621 TX Vref Scan disable
8126 09:32:33.629185 == TX Byte 0 ==
8127 09:32:33.632415 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8128 09:32:33.636072 == TX Byte 1 ==
8129 09:32:33.639335 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8130 09:32:33.642672 DramC Write-DBI off
8131 09:32:33.642755
8132 09:32:33.642820 [DATLAT]
8133 09:32:33.642881 Freq=1600, CH0 RK1
8134 09:32:33.642940
8135 09:32:33.645909 DATLAT Default: 0xf
8136 09:32:33.645991 0, 0xFFFF, sum = 0
8137 09:32:33.649329 1, 0xFFFF, sum = 0
8138 09:32:33.649412 2, 0xFFFF, sum = 0
8139 09:32:33.652751 3, 0xFFFF, sum = 0
8140 09:32:33.655505 4, 0xFFFF, sum = 0
8141 09:32:33.655615 5, 0xFFFF, sum = 0
8142 09:32:33.658855 6, 0xFFFF, sum = 0
8143 09:32:33.658938 7, 0xFFFF, sum = 0
8144 09:32:33.662283 8, 0xFFFF, sum = 0
8145 09:32:33.662401 9, 0xFFFF, sum = 0
8146 09:32:33.665748 10, 0xFFFF, sum = 0
8147 09:32:33.665832 11, 0xFFFF, sum = 0
8148 09:32:33.669013 12, 0xFFFF, sum = 0
8149 09:32:33.669097 13, 0xFFFF, sum = 0
8150 09:32:33.672760 14, 0x0, sum = 1
8151 09:32:33.672864 15, 0x0, sum = 2
8152 09:32:33.675848 16, 0x0, sum = 3
8153 09:32:33.675930 17, 0x0, sum = 4
8154 09:32:33.679150 best_step = 15
8155 09:32:33.679231
8156 09:32:33.679295 ==
8157 09:32:33.682242 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 09:32:33.685476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 09:32:33.685558 ==
8160 09:32:33.685624 RX Vref Scan: 0
8161 09:32:33.689265
8162 09:32:33.689346 RX Vref 0 -> 0, step: 1
8163 09:32:33.689412
8164 09:32:33.692126 RX Delay 19 -> 252, step: 4
8165 09:32:33.695536 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8166 09:32:33.702784 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8167 09:32:33.706090 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8168 09:32:33.709226 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8169 09:32:33.712404 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8170 09:32:33.715791 iDelay=191, Bit 5, Center 128 (75 ~ 182) 108
8171 09:32:33.719181 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8172 09:32:33.725689 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8173 09:32:33.728809 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8174 09:32:33.732440 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8175 09:32:33.735786 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8176 09:32:33.742122 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8177 09:32:33.745744 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8178 09:32:33.748755 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8179 09:32:33.752150 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8180 09:32:33.755333 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8181 09:32:33.755419 ==
8182 09:32:33.758652 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 09:32:33.765419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 09:32:33.765506 ==
8185 09:32:33.765609 DQS Delay:
8186 09:32:33.768594 DQS0 = 0, DQS1 = 0
8187 09:32:33.768678 DQM Delay:
8188 09:32:33.772319 DQM0 = 135, DQM1 = 128
8189 09:32:33.772403 DQ Delay:
8190 09:32:33.775463 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8191 09:32:33.778781 DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =140
8192 09:32:33.782149 DQ8 =118, DQ9 =118, DQ10 =130, DQ11 =118
8193 09:32:33.785236 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8194 09:32:33.785320
8195 09:32:33.785406
8196 09:32:33.785486
8197 09:32:33.788526 [DramC_TX_OE_Calibration] TA2
8198 09:32:33.792355 Original DQ_B0 (3 6) =30, OEN = 27
8199 09:32:33.795420 Original DQ_B1 (3 6) =30, OEN = 27
8200 09:32:33.799072 24, 0x0, End_B0=24 End_B1=24
8201 09:32:33.801940 25, 0x0, End_B0=25 End_B1=25
8202 09:32:33.802026 26, 0x0, End_B0=26 End_B1=26
8203 09:32:33.805170 27, 0x0, End_B0=27 End_B1=27
8204 09:32:33.809141 28, 0x0, End_B0=28 End_B1=28
8205 09:32:33.811979 29, 0x0, End_B0=29 End_B1=29
8206 09:32:33.812065 30, 0x0, End_B0=30 End_B1=30
8207 09:32:33.815136 31, 0x4141, End_B0=30 End_B1=30
8208 09:32:33.819037 Byte0 end_step=30 best_step=27
8209 09:32:33.821873 Byte1 end_step=30 best_step=27
8210 09:32:33.825206 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 09:32:33.828522 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 09:32:33.828608
8213 09:32:33.828694
8214 09:32:33.835242 [DQSOSCAuto] RK1, (LSB)MR18= 0x230c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
8215 09:32:33.838479 CH0 RK1: MR19=303, MR18=230C
8216 09:32:33.845384 CH0_RK1: MR19=0x303, MR18=0x230C, DQSOSC=392, MR23=63, INC=24, DEC=16
8217 09:32:33.848343 [RxdqsGatingPostProcess] freq 1600
8218 09:32:33.852087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 09:32:33.854965 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 09:32:33.858370 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 09:32:33.861714 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 09:32:33.865274 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 09:32:33.868317 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 09:32:33.871982 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 09:32:33.875384 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 09:32:33.878747 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 09:32:33.882044 Pre-setting of DQS Precalculation
8228 09:32:33.884732 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 09:32:33.884819 ==
8230 09:32:33.888677 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 09:32:33.895286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 09:32:33.895397 ==
8233 09:32:33.898009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 09:32:33.905102 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 09:32:33.908209 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 09:32:33.914439 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 09:32:33.922021 [CA 0] Center 42 (13~72) winsize 60
8238 09:32:33.925899 [CA 1] Center 42 (13~72) winsize 60
8239 09:32:33.929051 [CA 2] Center 39 (10~69) winsize 60
8240 09:32:33.931866 [CA 3] Center 38 (9~68) winsize 60
8241 09:32:33.935255 [CA 4] Center 38 (9~68) winsize 60
8242 09:32:33.938730 [CA 5] Center 37 (8~67) winsize 60
8243 09:32:33.938813
8244 09:32:33.942200 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 09:32:33.942283
8246 09:32:33.945686 [CATrainingPosCal] consider 1 rank data
8247 09:32:33.948851 u2DelayCellTimex100 = 290/100 ps
8248 09:32:33.952114 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8249 09:32:33.959036 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8250 09:32:33.962258 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8251 09:32:33.965304 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8252 09:32:33.968300 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8253 09:32:33.971883 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8254 09:32:33.971967
8255 09:32:33.974998 CA PerBit enable=1, Macro0, CA PI delay=37
8256 09:32:33.975081
8257 09:32:33.978248 [CBTSetCACLKResult] CA Dly = 37
8258 09:32:33.981909 CS Dly: 10 (0~41)
8259 09:32:33.985160 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 09:32:33.988662 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 09:32:33.988778 ==
8262 09:32:33.991619 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 09:32:33.995163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 09:32:33.998525 ==
8265 09:32:34.001908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 09:32:34.005261 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 09:32:34.011830 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 09:32:34.018321 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 09:32:34.025706 [CA 0] Center 42 (12~72) winsize 61
8270 09:32:34.028805 [CA 1] Center 42 (12~72) winsize 61
8271 09:32:34.032295 [CA 2] Center 38 (9~68) winsize 60
8272 09:32:34.035415 [CA 3] Center 38 (8~68) winsize 61
8273 09:32:34.038873 [CA 4] Center 38 (8~68) winsize 61
8274 09:32:34.042164 [CA 5] Center 37 (8~67) winsize 60
8275 09:32:34.042246
8276 09:32:34.045361 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 09:32:34.045443
8278 09:32:34.048758 [CATrainingPosCal] consider 2 rank data
8279 09:32:34.052111 u2DelayCellTimex100 = 290/100 ps
8280 09:32:34.055359 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8281 09:32:34.062093 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8282 09:32:34.065400 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8283 09:32:34.068847 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8284 09:32:34.072173 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 09:32:34.076002 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 09:32:34.076084
8287 09:32:34.078905 CA PerBit enable=1, Macro0, CA PI delay=37
8288 09:32:34.078993
8289 09:32:34.082252 [CBTSetCACLKResult] CA Dly = 37
8290 09:32:34.085657 CS Dly: 12 (0~45)
8291 09:32:34.088987 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 09:32:34.092427 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 09:32:34.092511
8294 09:32:34.095727 ----->DramcWriteLeveling(PI) begin...
8295 09:32:34.095811 ==
8296 09:32:34.098918 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 09:32:34.102019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 09:32:34.105437 ==
8299 09:32:34.105519 Write leveling (Byte 0): 24 => 24
8300 09:32:34.108862 Write leveling (Byte 1): 28 => 28
8301 09:32:34.111879 DramcWriteLeveling(PI) end<-----
8302 09:32:34.111960
8303 09:32:34.112025 ==
8304 09:32:34.115471 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 09:32:34.122169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 09:32:34.122257 ==
8307 09:32:34.125506 [Gating] SW mode calibration
8308 09:32:34.131603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 09:32:34.135421 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 09:32:34.141905 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 09:32:34.144962 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 09:32:34.148151 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8313 09:32:34.154820 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8314 09:32:34.158066 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 09:32:34.161371 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 09:32:34.168300 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 09:32:34.171584 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 09:32:34.175070 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 09:32:34.181506 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 09:32:34.184776 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8321 09:32:34.188146 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8322 09:32:34.191800 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 09:32:34.198376 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 09:32:34.201758 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 09:32:34.204499 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 09:32:34.211846 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 09:32:34.214922 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 09:32:34.218201 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8329 09:32:34.224940 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8330 09:32:34.228023 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 09:32:34.231441 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 09:32:34.237845 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 09:32:34.241459 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 09:32:34.244458 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 09:32:34.251317 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 09:32:34.254340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8337 09:32:34.257713 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 09:32:34.265009 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8339 09:32:34.267745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 09:32:34.271132 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 09:32:34.277924 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 09:32:34.281369 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 09:32:34.284749 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 09:32:34.291187 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 09:32:34.294565 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 09:32:34.297813 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 09:32:34.304473 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 09:32:34.307672 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 09:32:34.311133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 09:32:34.314409 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 09:32:34.321085 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 09:32:34.324317 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 09:32:34.327624 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 09:32:34.334849 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 09:32:34.338034 Total UI for P1: 0, mck2ui 16
8356 09:32:34.341404 best dqsien dly found for B0: ( 1, 9, 10)
8357 09:32:34.341485 Total UI for P1: 0, mck2ui 16
8358 09:32:34.347861 best dqsien dly found for B1: ( 1, 9, 10)
8359 09:32:34.351233 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8360 09:32:34.354747 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8361 09:32:34.354827
8362 09:32:34.357687 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8363 09:32:34.361169 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8364 09:32:34.364697 [Gating] SW calibration Done
8365 09:32:34.364777 ==
8366 09:32:34.368109 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 09:32:34.371585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 09:32:34.371719 ==
8369 09:32:34.374769 RX Vref Scan: 0
8370 09:32:34.374849
8371 09:32:34.374912 RX Vref 0 -> 0, step: 1
8372 09:32:34.374973
8373 09:32:34.377667 RX Delay 0 -> 252, step: 8
8374 09:32:34.381012 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8375 09:32:34.387773 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8376 09:32:34.390999 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8377 09:32:34.394151 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8378 09:32:34.398054 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8379 09:32:34.401265 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8380 09:32:34.407738 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8381 09:32:34.411184 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8382 09:32:34.414422 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8383 09:32:34.417682 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8384 09:32:34.420931 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8385 09:32:34.428078 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8386 09:32:34.431336 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8387 09:32:34.434758 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8388 09:32:34.437940 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8389 09:32:34.441174 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8390 09:32:34.441255 ==
8391 09:32:34.444930 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 09:32:34.451013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 09:32:34.451095 ==
8394 09:32:34.451175 DQS Delay:
8395 09:32:34.454286 DQS0 = 0, DQS1 = 0
8396 09:32:34.454366 DQM Delay:
8397 09:32:34.457702 DQM0 = 136, DQM1 = 132
8398 09:32:34.457782 DQ Delay:
8399 09:32:34.461503 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8400 09:32:34.464600 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8401 09:32:34.468036 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8402 09:32:34.471216 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8403 09:32:34.471297
8404 09:32:34.471361
8405 09:32:34.471420 ==
8406 09:32:34.474314 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 09:32:34.477737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 09:32:34.481085 ==
8409 09:32:34.481165
8410 09:32:34.481228
8411 09:32:34.481287 TX Vref Scan disable
8412 09:32:34.484607 == TX Byte 0 ==
8413 09:32:34.487857 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8414 09:32:34.491236 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8415 09:32:34.494615 == TX Byte 1 ==
8416 09:32:34.498038 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8417 09:32:34.501241 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8418 09:32:34.504305 ==
8419 09:32:34.507761 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 09:32:34.510970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 09:32:34.511050 ==
8422 09:32:34.524353
8423 09:32:34.527593 TX Vref early break, caculate TX vref
8424 09:32:34.530820 TX Vref=16, minBit 0, minWin=22, winSum=374
8425 09:32:34.534271 TX Vref=18, minBit 1, minWin=23, winSum=384
8426 09:32:34.537522 TX Vref=20, minBit 0, minWin=24, winSum=396
8427 09:32:34.540795 TX Vref=22, minBit 1, minWin=24, winSum=407
8428 09:32:34.544171 TX Vref=24, minBit 1, minWin=25, winSum=419
8429 09:32:34.551017 TX Vref=26, minBit 0, minWin=25, winSum=425
8430 09:32:34.554293 TX Vref=28, minBit 0, minWin=25, winSum=426
8431 09:32:34.557701 TX Vref=30, minBit 0, minWin=25, winSum=421
8432 09:32:34.561032 TX Vref=32, minBit 2, minWin=24, winSum=413
8433 09:32:34.564398 TX Vref=34, minBit 0, minWin=24, winSum=405
8434 09:32:34.567493 TX Vref=36, minBit 2, minWin=23, winSum=392
8435 09:32:34.574127 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8436 09:32:34.574208
8437 09:32:34.577412 Final TX Range 0 Vref 28
8438 09:32:34.577493
8439 09:32:34.577557 ==
8440 09:32:34.580773 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 09:32:34.583967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 09:32:34.584047 ==
8443 09:32:34.584111
8444 09:32:34.584170
8445 09:32:34.587612 TX Vref Scan disable
8446 09:32:34.594269 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8447 09:32:34.594350 == TX Byte 0 ==
8448 09:32:34.597163 u2DelayCellOfst[0]=16 cells (5 PI)
8449 09:32:34.600529 u2DelayCellOfst[1]=10 cells (3 PI)
8450 09:32:34.603835 u2DelayCellOfst[2]=0 cells (0 PI)
8451 09:32:34.607506 u2DelayCellOfst[3]=6 cells (2 PI)
8452 09:32:34.610768 u2DelayCellOfst[4]=10 cells (3 PI)
8453 09:32:34.614064 u2DelayCellOfst[5]=16 cells (5 PI)
8454 09:32:34.617371 u2DelayCellOfst[6]=16 cells (5 PI)
8455 09:32:34.620642 u2DelayCellOfst[7]=6 cells (2 PI)
8456 09:32:34.623975 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8457 09:32:34.627384 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8458 09:32:34.630829 == TX Byte 1 ==
8459 09:32:34.633991 u2DelayCellOfst[8]=0 cells (0 PI)
8460 09:32:34.634072 u2DelayCellOfst[9]=3 cells (1 PI)
8461 09:32:34.637303 u2DelayCellOfst[10]=13 cells (4 PI)
8462 09:32:34.640713 u2DelayCellOfst[11]=6 cells (2 PI)
8463 09:32:34.644027 u2DelayCellOfst[12]=16 cells (5 PI)
8464 09:32:34.647382 u2DelayCellOfst[13]=16 cells (5 PI)
8465 09:32:34.650716 u2DelayCellOfst[14]=16 cells (5 PI)
8466 09:32:34.653816 u2DelayCellOfst[15]=16 cells (5 PI)
8467 09:32:34.656912 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8468 09:32:34.663741 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 09:32:34.663851 DramC Write-DBI on
8470 09:32:34.663945 ==
8471 09:32:34.667121 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 09:32:34.673695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 09:32:34.673777 ==
8474 09:32:34.673842
8475 09:32:34.673901
8476 09:32:34.673958 TX Vref Scan disable
8477 09:32:34.677933 == TX Byte 0 ==
8478 09:32:34.681085 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8479 09:32:34.684398 == TX Byte 1 ==
8480 09:32:34.687839 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8481 09:32:34.691128 DramC Write-DBI off
8482 09:32:34.691208
8483 09:32:34.691272 [DATLAT]
8484 09:32:34.691331 Freq=1600, CH1 RK0
8485 09:32:34.691389
8486 09:32:34.694404 DATLAT Default: 0xf
8487 09:32:34.694484 0, 0xFFFF, sum = 0
8488 09:32:34.697962 1, 0xFFFF, sum = 0
8489 09:32:34.698044 2, 0xFFFF, sum = 0
8490 09:32:34.700706 3, 0xFFFF, sum = 0
8491 09:32:34.703972 4, 0xFFFF, sum = 0
8492 09:32:34.704054 5, 0xFFFF, sum = 0
8493 09:32:34.707763 6, 0xFFFF, sum = 0
8494 09:32:34.707845 7, 0xFFFF, sum = 0
8495 09:32:34.710571 8, 0xFFFF, sum = 0
8496 09:32:34.710653 9, 0xFFFF, sum = 0
8497 09:32:34.714234 10, 0xFFFF, sum = 0
8498 09:32:34.714315 11, 0xFFFF, sum = 0
8499 09:32:34.717590 12, 0xFFFF, sum = 0
8500 09:32:34.717672 13, 0xFFFF, sum = 0
8501 09:32:34.720432 14, 0x0, sum = 1
8502 09:32:34.720514 15, 0x0, sum = 2
8503 09:32:34.723942 16, 0x0, sum = 3
8504 09:32:34.724023 17, 0x0, sum = 4
8505 09:32:34.727199 best_step = 15
8506 09:32:34.727279
8507 09:32:34.727342 ==
8508 09:32:34.730833 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 09:32:34.734031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 09:32:34.734113 ==
8511 09:32:34.737164 RX Vref Scan: 1
8512 09:32:34.737245
8513 09:32:34.737308 Set Vref Range= 24 -> 127
8514 09:32:34.737369
8515 09:32:34.740462 RX Vref 24 -> 127, step: 1
8516 09:32:34.740543
8517 09:32:34.743871 RX Delay 27 -> 252, step: 4
8518 09:32:34.743952
8519 09:32:34.747237 Set Vref, RX VrefLevel [Byte0]: 24
8520 09:32:34.750460 [Byte1]: 24
8521 09:32:34.750540
8522 09:32:34.753899 Set Vref, RX VrefLevel [Byte0]: 25
8523 09:32:34.757126 [Byte1]: 25
8524 09:32:34.757206
8525 09:32:34.761066 Set Vref, RX VrefLevel [Byte0]: 26
8526 09:32:34.764094 [Byte1]: 26
8527 09:32:34.767788
8528 09:32:34.767869 Set Vref, RX VrefLevel [Byte0]: 27
8529 09:32:34.771092 [Byte1]: 27
8530 09:32:34.775612
8531 09:32:34.775742 Set Vref, RX VrefLevel [Byte0]: 28
8532 09:32:34.778430 [Byte1]: 28
8533 09:32:34.782869
8534 09:32:34.782949 Set Vref, RX VrefLevel [Byte0]: 29
8535 09:32:34.785938 [Byte1]: 29
8536 09:32:34.790529
8537 09:32:34.790609 Set Vref, RX VrefLevel [Byte0]: 30
8538 09:32:34.793964 [Byte1]: 30
8539 09:32:34.797851
8540 09:32:34.797933 Set Vref, RX VrefLevel [Byte0]: 31
8541 09:32:34.801226 [Byte1]: 31
8542 09:32:34.805283
8543 09:32:34.805389 Set Vref, RX VrefLevel [Byte0]: 32
8544 09:32:34.808875 [Byte1]: 32
8545 09:32:34.813269
8546 09:32:34.813365 Set Vref, RX VrefLevel [Byte0]: 33
8547 09:32:34.816546 [Byte1]: 33
8548 09:32:34.820588
8549 09:32:34.820690 Set Vref, RX VrefLevel [Byte0]: 34
8550 09:32:34.823893 [Byte1]: 34
8551 09:32:34.827627
8552 09:32:34.827765 Set Vref, RX VrefLevel [Byte0]: 35
8553 09:32:34.831432 [Byte1]: 35
8554 09:32:34.835843
8555 09:32:34.835923 Set Vref, RX VrefLevel [Byte0]: 36
8556 09:32:34.838832 [Byte1]: 36
8557 09:32:34.842792
8558 09:32:34.842873 Set Vref, RX VrefLevel [Byte0]: 37
8559 09:32:34.846503 [Byte1]: 37
8560 09:32:34.850616
8561 09:32:34.850697 Set Vref, RX VrefLevel [Byte0]: 38
8562 09:32:34.854125 [Byte1]: 38
8563 09:32:34.858561
8564 09:32:34.858642 Set Vref, RX VrefLevel [Byte0]: 39
8565 09:32:34.861257 [Byte1]: 39
8566 09:32:34.865775
8567 09:32:34.865861 Set Vref, RX VrefLevel [Byte0]: 40
8568 09:32:34.869143 [Byte1]: 40
8569 09:32:34.873551
8570 09:32:34.873643 Set Vref, RX VrefLevel [Byte0]: 41
8571 09:32:34.876473 [Byte1]: 41
8572 09:32:34.881152
8573 09:32:34.881262 Set Vref, RX VrefLevel [Byte0]: 42
8574 09:32:34.884463 [Byte1]: 42
8575 09:32:34.888411
8576 09:32:34.888531 Set Vref, RX VrefLevel [Byte0]: 43
8577 09:32:34.891702 [Byte1]: 43
8578 09:32:34.895936
8579 09:32:34.896086 Set Vref, RX VrefLevel [Byte0]: 44
8580 09:32:34.899197 [Byte1]: 44
8581 09:32:34.903094
8582 09:32:34.903263 Set Vref, RX VrefLevel [Byte0]: 45
8583 09:32:34.906495 [Byte1]: 45
8584 09:32:34.911132
8585 09:32:34.911367 Set Vref, RX VrefLevel [Byte0]: 46
8586 09:32:34.914607 [Byte1]: 46
8587 09:32:34.918501
8588 09:32:34.918798 Set Vref, RX VrefLevel [Byte0]: 47
8589 09:32:34.921866 [Byte1]: 47
8590 09:32:34.926287
8591 09:32:34.926638 Set Vref, RX VrefLevel [Byte0]: 48
8592 09:32:34.929838 [Byte1]: 48
8593 09:32:34.933806
8594 09:32:34.934209 Set Vref, RX VrefLevel [Byte0]: 49
8595 09:32:34.937208 [Byte1]: 49
8596 09:32:34.941384
8597 09:32:34.941732 Set Vref, RX VrefLevel [Byte0]: 50
8598 09:32:34.944714 [Byte1]: 50
8599 09:32:34.949095
8600 09:32:34.949449 Set Vref, RX VrefLevel [Byte0]: 51
8601 09:32:34.952477 [Byte1]: 51
8602 09:32:34.956519
8603 09:32:34.956871 Set Vref, RX VrefLevel [Byte0]: 52
8604 09:32:34.959728 [Byte1]: 52
8605 09:32:34.964073
8606 09:32:34.964548 Set Vref, RX VrefLevel [Byte0]: 53
8607 09:32:34.967058 [Byte1]: 53
8608 09:32:34.971750
8609 09:32:34.972104 Set Vref, RX VrefLevel [Byte0]: 54
8610 09:32:34.975115 [Byte1]: 54
8611 09:32:34.978802
8612 09:32:34.979154 Set Vref, RX VrefLevel [Byte0]: 55
8613 09:32:34.982033 [Byte1]: 55
8614 09:32:34.986550
8615 09:32:34.986902 Set Vref, RX VrefLevel [Byte0]: 56
8616 09:32:34.989484 [Byte1]: 56
8617 09:32:34.993886
8618 09:32:34.993967 Set Vref, RX VrefLevel [Byte0]: 57
8619 09:32:34.997424 [Byte1]: 57
8620 09:32:35.001265
8621 09:32:35.001356 Set Vref, RX VrefLevel [Byte0]: 58
8622 09:32:35.004779 [Byte1]: 58
8623 09:32:35.008795
8624 09:32:35.008902 Set Vref, RX VrefLevel [Byte0]: 59
8625 09:32:35.012061 [Byte1]: 59
8626 09:32:35.016110
8627 09:32:35.016230 Set Vref, RX VrefLevel [Byte0]: 60
8628 09:32:35.019437 [Byte1]: 60
8629 09:32:35.024074
8630 09:32:35.024209 Set Vref, RX VrefLevel [Byte0]: 61
8631 09:32:35.027244 [Byte1]: 61
8632 09:32:35.031437
8633 09:32:35.031764 Set Vref, RX VrefLevel [Byte0]: 62
8634 09:32:35.034886 [Byte1]: 62
8635 09:32:35.038911
8636 09:32:35.039109 Set Vref, RX VrefLevel [Byte0]: 63
8637 09:32:35.042432 [Byte1]: 63
8638 09:32:35.046584
8639 09:32:35.046877 Set Vref, RX VrefLevel [Byte0]: 64
8640 09:32:35.049778 [Byte1]: 64
8641 09:32:35.054569
8642 09:32:35.054919 Set Vref, RX VrefLevel [Byte0]: 65
8643 09:32:35.057988 [Byte1]: 65
8644 09:32:35.061691
8645 09:32:35.062041 Set Vref, RX VrefLevel [Byte0]: 66
8646 09:32:35.065220 [Byte1]: 66
8647 09:32:35.069300
8648 09:32:35.069649 Set Vref, RX VrefLevel [Byte0]: 67
8649 09:32:35.072615 [Byte1]: 67
8650 09:32:35.077149
8651 09:32:35.077498 Set Vref, RX VrefLevel [Byte0]: 68
8652 09:32:35.080369 [Byte1]: 68
8653 09:32:35.084668
8654 09:32:35.085017 Set Vref, RX VrefLevel [Byte0]: 69
8655 09:32:35.087588 [Byte1]: 69
8656 09:32:35.092058
8657 09:32:35.092493 Set Vref, RX VrefLevel [Byte0]: 70
8658 09:32:35.095429 [Byte1]: 70
8659 09:32:35.099685
8660 09:32:35.100069 Set Vref, RX VrefLevel [Byte0]: 71
8661 09:32:35.102569 [Byte1]: 71
8662 09:32:35.107030
8663 09:32:35.107493 Set Vref, RX VrefLevel [Byte0]: 72
8664 09:32:35.110255 [Byte1]: 72
8665 09:32:35.114725
8666 09:32:35.115076 Set Vref, RX VrefLevel [Byte0]: 73
8667 09:32:35.117662 [Byte1]: 73
8668 09:32:35.122240
8669 09:32:35.122593 Set Vref, RX VrefLevel [Byte0]: 74
8670 09:32:35.125621 [Byte1]: 74
8671 09:32:35.129357
8672 09:32:35.129729 Set Vref, RX VrefLevel [Byte0]: 75
8673 09:32:35.133128 [Byte1]: 75
8674 09:32:35.137276
8675 09:32:35.137623 Set Vref, RX VrefLevel [Byte0]: 76
8676 09:32:35.140658 [Byte1]: 76
8677 09:32:35.144667
8678 09:32:35.145017 Final RX Vref Byte 0 = 58 to rank0
8679 09:32:35.148056 Final RX Vref Byte 1 = 57 to rank0
8680 09:32:35.151441 Final RX Vref Byte 0 = 58 to rank1
8681 09:32:35.154591 Final RX Vref Byte 1 = 57 to rank1==
8682 09:32:35.157954 Dram Type= 6, Freq= 0, CH_1, rank 0
8683 09:32:35.164716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8684 09:32:35.165127 ==
8685 09:32:35.165413 DQS Delay:
8686 09:32:35.165677 DQS0 = 0, DQS1 = 0
8687 09:32:35.167897 DQM Delay:
8688 09:32:35.168248 DQM0 = 134, DQM1 = 130
8689 09:32:35.171227 DQ Delay:
8690 09:32:35.174514 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8691 09:32:35.177860 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8692 09:32:35.181275 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8693 09:32:35.184675 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8694 09:32:35.185027
8695 09:32:35.185305
8696 09:32:35.185564
8697 09:32:35.188047 [DramC_TX_OE_Calibration] TA2
8698 09:32:35.190679 Original DQ_B0 (3 6) =30, OEN = 27
8699 09:32:35.194262 Original DQ_B1 (3 6) =30, OEN = 27
8700 09:32:35.197753 24, 0x0, End_B0=24 End_B1=24
8701 09:32:35.198112 25, 0x0, End_B0=25 End_B1=25
8702 09:32:35.201005 26, 0x0, End_B0=26 End_B1=26
8703 09:32:35.204410 27, 0x0, End_B0=27 End_B1=27
8704 09:32:35.207571 28, 0x0, End_B0=28 End_B1=28
8705 09:32:35.210757 29, 0x0, End_B0=29 End_B1=29
8706 09:32:35.211249 30, 0x0, End_B0=30 End_B1=30
8707 09:32:35.213935 31, 0x4545, End_B0=30 End_B1=30
8708 09:32:35.217292 Byte0 end_step=30 best_step=27
8709 09:32:35.221191 Byte1 end_step=30 best_step=27
8710 09:32:35.224145 Byte0 TX OE(2T, 0.5T) = (3, 3)
8711 09:32:35.227626 Byte1 TX OE(2T, 0.5T) = (3, 3)
8712 09:32:35.228053
8713 09:32:35.228364
8714 09:32:35.234017 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8715 09:32:35.237636 CH1 RK0: MR19=303, MR18=1826
8716 09:32:35.244130 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8717 09:32:35.244511
8718 09:32:35.247206 ----->DramcWriteLeveling(PI) begin...
8719 09:32:35.247766 ==
8720 09:32:35.251002 Dram Type= 6, Freq= 0, CH_1, rank 1
8721 09:32:35.254421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 09:32:35.254804 ==
8723 09:32:35.257656 Write leveling (Byte 0): 25 => 25
8724 09:32:35.261000 Write leveling (Byte 1): 28 => 28
8725 09:32:35.264164 DramcWriteLeveling(PI) end<-----
8726 09:32:35.264619
8727 09:32:35.265069 ==
8728 09:32:35.267445 Dram Type= 6, Freq= 0, CH_1, rank 1
8729 09:32:35.270686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 09:32:35.271212 ==
8731 09:32:35.274202 [Gating] SW mode calibration
8732 09:32:35.280728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8733 09:32:35.287537 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8734 09:32:35.290869 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 09:32:35.294198 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 09:32:35.300932 1 4 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
8737 09:32:35.304062 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8738 09:32:35.307243 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 09:32:35.313740 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 09:32:35.316879 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 09:32:35.320907 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 09:32:35.326947 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 09:32:35.330459 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8744 09:32:35.333779 1 5 8 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
8745 09:32:35.340449 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 09:32:35.343739 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 09:32:35.346998 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 09:32:35.353639 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 09:32:35.357265 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 09:32:35.360375 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 09:32:35.367046 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 09:32:35.370158 1 6 8 | B1->B0 | 3838 2323 | 0 0 | (0 0) (0 0)
8753 09:32:35.373319 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 09:32:35.380611 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 09:32:35.383740 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 09:32:35.386972 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 09:32:35.393359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 09:32:35.396961 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 09:32:35.400200 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8760 09:32:35.406888 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8761 09:32:35.409670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8762 09:32:35.413752 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 09:32:35.420021 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 09:32:35.423360 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 09:32:35.426557 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 09:32:35.429868 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 09:32:35.436649 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 09:32:35.439967 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 09:32:35.443265 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 09:32:35.449985 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 09:32:35.453406 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 09:32:35.456563 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 09:32:35.463418 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 09:32:35.466750 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 09:32:35.469846 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8776 09:32:35.476715 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8777 09:32:35.480014 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8778 09:32:35.483173 Total UI for P1: 0, mck2ui 16
8779 09:32:35.486847 best dqsien dly found for B1: ( 1, 9, 6)
8780 09:32:35.490150 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8781 09:32:35.496643 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 09:32:35.496935 Total UI for P1: 0, mck2ui 16
8783 09:32:35.503583 best dqsien dly found for B0: ( 1, 9, 14)
8784 09:32:35.506431 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8785 09:32:35.510062 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8786 09:32:35.510402
8787 09:32:35.513246 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8788 09:32:35.516881 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8789 09:32:35.520189 [Gating] SW calibration Done
8790 09:32:35.520502 ==
8791 09:32:35.523205 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 09:32:35.526311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 09:32:35.526543 ==
8794 09:32:35.529629 RX Vref Scan: 0
8795 09:32:35.529804
8796 09:32:35.529969 RX Vref 0 -> 0, step: 1
8797 09:32:35.530081
8798 09:32:35.532840 RX Delay 0 -> 252, step: 8
8799 09:32:35.536115 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8800 09:32:35.542782 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8801 09:32:35.546704 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8802 09:32:35.550011 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8803 09:32:35.552916 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8804 09:32:35.556362 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8805 09:32:35.559661 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8806 09:32:35.566391 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8807 09:32:35.569763 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8808 09:32:35.573121 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8809 09:32:35.576424 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8810 09:32:35.579535 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8811 09:32:35.586204 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8812 09:32:35.589519 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8813 09:32:35.592809 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8814 09:32:35.596032 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8815 09:32:35.596140 ==
8816 09:32:35.599433 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 09:32:35.606452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 09:32:35.606560 ==
8819 09:32:35.606652 DQS Delay:
8820 09:32:35.609688 DQS0 = 0, DQS1 = 0
8821 09:32:35.609775 DQM Delay:
8822 09:32:35.609847 DQM0 = 136, DQM1 = 133
8823 09:32:35.612857 DQ Delay:
8824 09:32:35.616563 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8825 09:32:35.619632 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8826 09:32:35.623338 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8827 09:32:35.626222 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8828 09:32:35.626334
8829 09:32:35.626445
8830 09:32:35.626542 ==
8831 09:32:35.629969 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 09:32:35.632808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 09:32:35.636212 ==
8834 09:32:35.636293
8835 09:32:35.636356
8836 09:32:35.636441 TX Vref Scan disable
8837 09:32:35.639434 == TX Byte 0 ==
8838 09:32:35.643022 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8839 09:32:35.646255 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8840 09:32:35.649715 == TX Byte 1 ==
8841 09:32:35.652951 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8842 09:32:35.656207 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8843 09:32:35.656290 ==
8844 09:32:35.659715 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 09:32:35.666417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 09:32:35.666501 ==
8847 09:32:35.679008
8848 09:32:35.682324 TX Vref early break, caculate TX vref
8849 09:32:35.685537 TX Vref=16, minBit 0, minWin=23, winSum=385
8850 09:32:35.688812 TX Vref=18, minBit 0, minWin=24, winSum=395
8851 09:32:35.692069 TX Vref=20, minBit 0, minWin=24, winSum=399
8852 09:32:35.695568 TX Vref=22, minBit 0, minWin=25, winSum=413
8853 09:32:35.698884 TX Vref=24, minBit 0, minWin=25, winSum=420
8854 09:32:35.705795 TX Vref=26, minBit 0, minWin=26, winSum=427
8855 09:32:35.709029 TX Vref=28, minBit 0, minWin=25, winSum=427
8856 09:32:35.712203 TX Vref=30, minBit 0, minWin=25, winSum=418
8857 09:32:35.715556 TX Vref=32, minBit 0, minWin=25, winSum=416
8858 09:32:35.718903 TX Vref=34, minBit 0, minWin=24, winSum=406
8859 09:32:35.722271 TX Vref=36, minBit 0, minWin=24, winSum=397
8860 09:32:35.728885 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8861 09:32:35.728968
8862 09:32:35.732048 Final TX Range 0 Vref 26
8863 09:32:35.732166
8864 09:32:35.732269 ==
8865 09:32:35.735349 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 09:32:35.738872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 09:32:35.738953 ==
8868 09:32:35.739019
8869 09:32:35.739078
8870 09:32:35.742186 TX Vref Scan disable
8871 09:32:35.748550 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8872 09:32:35.748656 == TX Byte 0 ==
8873 09:32:35.752204 u2DelayCellOfst[0]=16 cells (5 PI)
8874 09:32:35.755570 u2DelayCellOfst[1]=10 cells (3 PI)
8875 09:32:35.758896 u2DelayCellOfst[2]=0 cells (0 PI)
8876 09:32:35.762274 u2DelayCellOfst[3]=6 cells (2 PI)
8877 09:32:35.765625 u2DelayCellOfst[4]=6 cells (2 PI)
8878 09:32:35.768693 u2DelayCellOfst[5]=16 cells (5 PI)
8879 09:32:35.771977 u2DelayCellOfst[6]=16 cells (5 PI)
8880 09:32:35.775458 u2DelayCellOfst[7]=6 cells (2 PI)
8881 09:32:35.778837 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8882 09:32:35.782116 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8883 09:32:35.785485 == TX Byte 1 ==
8884 09:32:35.788785 u2DelayCellOfst[8]=0 cells (0 PI)
8885 09:32:35.788897 u2DelayCellOfst[9]=6 cells (2 PI)
8886 09:32:35.792106 u2DelayCellOfst[10]=13 cells (4 PI)
8887 09:32:35.795871 u2DelayCellOfst[11]=10 cells (3 PI)
8888 09:32:35.799219 u2DelayCellOfst[12]=16 cells (5 PI)
8889 09:32:35.802321 u2DelayCellOfst[13]=16 cells (5 PI)
8890 09:32:35.805640 u2DelayCellOfst[14]=20 cells (6 PI)
8891 09:32:35.808781 u2DelayCellOfst[15]=20 cells (6 PI)
8892 09:32:35.811807 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8893 09:32:35.818364 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8894 09:32:35.818468 DramC Write-DBI on
8895 09:32:35.818560 ==
8896 09:32:35.821756 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 09:32:35.828581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 09:32:35.828663 ==
8899 09:32:35.828728
8900 09:32:35.828787
8901 09:32:35.828844 TX Vref Scan disable
8902 09:32:35.832653 == TX Byte 0 ==
8903 09:32:35.836009 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8904 09:32:35.839207 == TX Byte 1 ==
8905 09:32:35.842348 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8906 09:32:35.845871 DramC Write-DBI off
8907 09:32:35.845951
8908 09:32:35.846014 [DATLAT]
8909 09:32:35.846074 Freq=1600, CH1 RK1
8910 09:32:35.846133
8911 09:32:35.849182 DATLAT Default: 0xf
8912 09:32:35.849262 0, 0xFFFF, sum = 0
8913 09:32:35.852676 1, 0xFFFF, sum = 0
8914 09:32:35.852759 2, 0xFFFF, sum = 0
8915 09:32:35.855457 3, 0xFFFF, sum = 0
8916 09:32:35.858822 4, 0xFFFF, sum = 0
8917 09:32:35.858905 5, 0xFFFF, sum = 0
8918 09:32:35.862254 6, 0xFFFF, sum = 0
8919 09:32:35.862336 7, 0xFFFF, sum = 0
8920 09:32:35.865384 8, 0xFFFF, sum = 0
8921 09:32:35.865465 9, 0xFFFF, sum = 0
8922 09:32:35.869000 10, 0xFFFF, sum = 0
8923 09:32:35.869082 11, 0xFFFF, sum = 0
8924 09:32:35.872073 12, 0xFFFF, sum = 0
8925 09:32:35.872155 13, 0xFFFF, sum = 0
8926 09:32:35.875596 14, 0x0, sum = 1
8927 09:32:35.875728 15, 0x0, sum = 2
8928 09:32:35.878943 16, 0x0, sum = 3
8929 09:32:35.879024 17, 0x0, sum = 4
8930 09:32:35.881894 best_step = 15
8931 09:32:35.881974
8932 09:32:35.882038 ==
8933 09:32:35.885250 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 09:32:35.888926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 09:32:35.889008 ==
8936 09:32:35.892146 RX Vref Scan: 0
8937 09:32:35.892227
8938 09:32:35.892291 RX Vref 0 -> 0, step: 1
8939 09:32:35.892350
8940 09:32:35.895072 RX Delay 19 -> 252, step: 4
8941 09:32:35.898428 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8942 09:32:35.905201 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8943 09:32:35.908386 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8944 09:32:35.911825 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8945 09:32:35.915106 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8946 09:32:35.918788 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8947 09:32:35.921787 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8948 09:32:35.928274 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8949 09:32:35.931629 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8950 09:32:35.935000 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8951 09:32:35.938367 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8952 09:32:35.944690 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8953 09:32:35.948107 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8954 09:32:35.951246 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8955 09:32:35.954717 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8956 09:32:35.958344 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8957 09:32:35.961585 ==
8958 09:32:35.965018 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 09:32:35.968384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 09:32:35.968465 ==
8961 09:32:35.968529 DQS Delay:
8962 09:32:35.971872 DQS0 = 0, DQS1 = 0
8963 09:32:35.971958 DQM Delay:
8964 09:32:35.975184 DQM0 = 134, DQM1 = 130
8965 09:32:35.975322 DQ Delay:
8966 09:32:35.977999 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8967 09:32:35.981647 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8968 09:32:35.984757 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8969 09:32:35.988242 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8970 09:32:35.988431
8971 09:32:35.988528
8972 09:32:35.988614
8973 09:32:35.991329 [DramC_TX_OE_Calibration] TA2
8974 09:32:35.995325 Original DQ_B0 (3 6) =30, OEN = 27
8975 09:32:35.998384 Original DQ_B1 (3 6) =30, OEN = 27
8976 09:32:36.001257 24, 0x0, End_B0=24 End_B1=24
8977 09:32:36.005003 25, 0x0, End_B0=25 End_B1=25
8978 09:32:36.005264 26, 0x0, End_B0=26 End_B1=26
8979 09:32:36.008059 27, 0x0, End_B0=27 End_B1=27
8980 09:32:36.011503 28, 0x0, End_B0=28 End_B1=28
8981 09:32:36.014805 29, 0x0, End_B0=29 End_B1=29
8982 09:32:36.018352 30, 0x0, End_B0=30 End_B1=30
8983 09:32:36.018688 31, 0x4141, End_B0=30 End_B1=30
8984 09:32:36.021861 Byte0 end_step=30 best_step=27
8985 09:32:36.024521 Byte1 end_step=30 best_step=27
8986 09:32:36.028289 Byte0 TX OE(2T, 0.5T) = (3, 3)
8987 09:32:36.031385 Byte1 TX OE(2T, 0.5T) = (3, 3)
8988 09:32:36.031829
8989 09:32:36.032162
8990 09:32:36.037887 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8991 09:32:36.041241 CH1 RK1: MR19=303, MR18=2107
8992 09:32:36.048090 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
8993 09:32:36.051488 [RxdqsGatingPostProcess] freq 1600
8994 09:32:36.058141 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8995 09:32:36.061269 best DQS0 dly(2T, 0.5T) = (1, 1)
8996 09:32:36.061933 best DQS1 dly(2T, 0.5T) = (1, 1)
8997 09:32:36.064593 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8998 09:32:36.068009 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8999 09:32:36.071369 best DQS0 dly(2T, 0.5T) = (1, 1)
9000 09:32:36.074766 best DQS1 dly(2T, 0.5T) = (1, 1)
9001 09:32:36.078315 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9002 09:32:36.081700 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9003 09:32:36.085130 Pre-setting of DQS Precalculation
9004 09:32:36.088613 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9005 09:32:36.097977 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9006 09:32:36.104556 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9007 09:32:36.104974
9008 09:32:36.105301
9009 09:32:36.107924 [Calibration Summary] 3200 Mbps
9010 09:32:36.108342 CH 0, Rank 0
9011 09:32:36.111264 SW Impedance : PASS
9012 09:32:36.111703 DUTY Scan : NO K
9013 09:32:36.114229 ZQ Calibration : PASS
9014 09:32:36.117718 Jitter Meter : NO K
9015 09:32:36.118132 CBT Training : PASS
9016 09:32:36.120966 Write leveling : PASS
9017 09:32:36.124088 RX DQS gating : PASS
9018 09:32:36.124695 RX DQ/DQS(RDDQC) : PASS
9019 09:32:36.127338 TX DQ/DQS : PASS
9020 09:32:36.131243 RX DATLAT : PASS
9021 09:32:36.131698 RX DQ/DQS(Engine): PASS
9022 09:32:36.134405 TX OE : PASS
9023 09:32:36.134819 All Pass.
9024 09:32:36.135149
9025 09:32:36.137480 CH 0, Rank 1
9026 09:32:36.137892 SW Impedance : PASS
9027 09:32:36.141010 DUTY Scan : NO K
9028 09:32:36.141428 ZQ Calibration : PASS
9029 09:32:36.143889 Jitter Meter : NO K
9030 09:32:36.147400 CBT Training : PASS
9031 09:32:36.147845 Write leveling : PASS
9032 09:32:36.150761 RX DQS gating : PASS
9033 09:32:36.154351 RX DQ/DQS(RDDQC) : PASS
9034 09:32:36.154771 TX DQ/DQS : PASS
9035 09:32:36.157552 RX DATLAT : PASS
9036 09:32:36.160820 RX DQ/DQS(Engine): PASS
9037 09:32:36.161235 TX OE : PASS
9038 09:32:36.164152 All Pass.
9039 09:32:36.164621
9040 09:32:36.164957 CH 1, Rank 0
9041 09:32:36.167557 SW Impedance : PASS
9042 09:32:36.168020 DUTY Scan : NO K
9043 09:32:36.170877 ZQ Calibration : PASS
9044 09:32:36.174141 Jitter Meter : NO K
9045 09:32:36.174555 CBT Training : PASS
9046 09:32:36.177835 Write leveling : PASS
9047 09:32:36.180587 RX DQS gating : PASS
9048 09:32:36.181002 RX DQ/DQS(RDDQC) : PASS
9049 09:32:36.184017 TX DQ/DQS : PASS
9050 09:32:36.187142 RX DATLAT : PASS
9051 09:32:36.187552 RX DQ/DQS(Engine): PASS
9052 09:32:36.190572 TX OE : PASS
9053 09:32:36.190989 All Pass.
9054 09:32:36.191320
9055 09:32:36.193816 CH 1, Rank 1
9056 09:32:36.194233 SW Impedance : PASS
9057 09:32:36.197166 DUTY Scan : NO K
9058 09:32:36.197581 ZQ Calibration : PASS
9059 09:32:36.200433 Jitter Meter : NO K
9060 09:32:36.203812 CBT Training : PASS
9061 09:32:36.204227 Write leveling : PASS
9062 09:32:36.207271 RX DQS gating : PASS
9063 09:32:36.210622 RX DQ/DQS(RDDQC) : PASS
9064 09:32:36.211036 TX DQ/DQS : PASS
9065 09:32:36.213779 RX DATLAT : PASS
9066 09:32:36.217107 RX DQ/DQS(Engine): PASS
9067 09:32:36.217488 TX OE : PASS
9068 09:32:36.220390 All Pass.
9069 09:32:36.220768
9070 09:32:36.221071 DramC Write-DBI on
9071 09:32:36.223766 PER_BANK_REFRESH: Hybrid Mode
9072 09:32:36.224149 TX_TRACKING: ON
9073 09:32:36.234278 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9074 09:32:36.244234 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9075 09:32:36.250580 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9076 09:32:36.253988 [FAST_K] Save calibration result to emmc
9077 09:32:36.257197 sync common calibartion params.
9078 09:32:36.257649 sync cbt_mode0:1, 1:1
9079 09:32:36.260208 dram_init: ddr_geometry: 2
9080 09:32:36.264251 dram_init: ddr_geometry: 2
9081 09:32:36.264664 dram_init: ddr_geometry: 2
9082 09:32:36.267477 0:dram_rank_size:100000000
9083 09:32:36.270566 1:dram_rank_size:100000000
9084 09:32:36.277120 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9085 09:32:36.277558 DFS_SHUFFLE_HW_MODE: ON
9086 09:32:36.280816 dramc_set_vcore_voltage set vcore to 725000
9087 09:32:36.283712 Read voltage for 1600, 0
9088 09:32:36.284291 Vio18 = 0
9089 09:32:36.287160 Vcore = 725000
9090 09:32:36.287771 Vdram = 0
9091 09:32:36.288152 Vddq = 0
9092 09:32:36.290437 Vmddr = 0
9093 09:32:36.290870 switch to 3200 Mbps bootup
9094 09:32:36.293526 [DramcRunTimeConfig]
9095 09:32:36.294121 PHYPLL
9096 09:32:36.296951 DPM_CONTROL_AFTERK: ON
9097 09:32:36.297407 PER_BANK_REFRESH: ON
9098 09:32:36.300522 REFRESH_OVERHEAD_REDUCTION: ON
9099 09:32:36.303570 CMD_PICG_NEW_MODE: OFF
9100 09:32:36.304032 XRTWTW_NEW_MODE: ON
9101 09:32:36.307033 XRTRTR_NEW_MODE: ON
9102 09:32:36.307450 TX_TRACKING: ON
9103 09:32:36.310356 RDSEL_TRACKING: OFF
9104 09:32:36.313715 DQS Precalculation for DVFS: ON
9105 09:32:36.314131 RX_TRACKING: OFF
9106 09:32:36.317229 HW_GATING DBG: ON
9107 09:32:36.317765 ZQCS_ENABLE_LP4: ON
9108 09:32:36.320523 RX_PICG_NEW_MODE: ON
9109 09:32:36.320941 TX_PICG_NEW_MODE: ON
9110 09:32:36.323604 ENABLE_RX_DCM_DPHY: ON
9111 09:32:36.327174 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9112 09:32:36.330492 DUMMY_READ_FOR_TRACKING: OFF
9113 09:32:36.330911 !!! SPM_CONTROL_AFTERK: OFF
9114 09:32:36.333721 !!! SPM could not control APHY
9115 09:32:36.337127 IMPEDANCE_TRACKING: ON
9116 09:32:36.337567 TEMP_SENSOR: ON
9117 09:32:36.340219 HW_SAVE_FOR_SR: OFF
9118 09:32:36.343591 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9119 09:32:36.346848 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9120 09:32:36.347266 Read ODT Tracking: ON
9121 09:32:36.350245 Refresh Rate DeBounce: ON
9122 09:32:36.353310 DFS_NO_QUEUE_FLUSH: ON
9123 09:32:36.356654 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9124 09:32:36.357073 ENABLE_DFS_RUNTIME_MRW: OFF
9125 09:32:36.360080 DDR_RESERVE_NEW_MODE: ON
9126 09:32:36.363449 MR_CBT_SWITCH_FREQ: ON
9127 09:32:36.363900 =========================
9128 09:32:36.383607 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9129 09:32:36.387022 dram_init: ddr_geometry: 2
9130 09:32:36.405460 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9131 09:32:36.408867 dram_init: dram init end (result: 0)
9132 09:32:36.415530 DRAM-K: Full calibration passed in 24440 msecs
9133 09:32:36.418725 MRC: failed to locate region type 0.
9134 09:32:36.419140 DRAM rank0 size:0x100000000,
9135 09:32:36.421929 DRAM rank1 size=0x100000000
9136 09:32:36.432292 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9137 09:32:36.438351 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9138 09:32:36.445197 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9139 09:32:36.451750 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9140 09:32:36.455076 DRAM rank0 size:0x100000000,
9141 09:32:36.458335 DRAM rank1 size=0x100000000
9142 09:32:36.458752 CBMEM:
9143 09:32:36.462180 IMD: root @ 0xfffff000 254 entries.
9144 09:32:36.464959 IMD: root @ 0xffffec00 62 entries.
9145 09:32:36.468409 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9146 09:32:36.471592 WARNING: RO_VPD is uninitialized or empty.
9147 09:32:36.478175 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9148 09:32:36.485185 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9149 09:32:36.497768 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9150 09:32:36.509406 BS: romstage times (exec / console): total (unknown) / 23970 ms
9151 09:32:36.509853
9152 09:32:36.510195
9153 09:32:36.519335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9154 09:32:36.522345 ARM64: Exception handlers installed.
9155 09:32:36.526187 ARM64: Testing exception
9156 09:32:36.529420 ARM64: Done test exception
9157 09:32:36.529855 Enumerating buses...
9158 09:32:36.532857 Show all devs... Before device enumeration.
9159 09:32:36.535622 Root Device: enabled 1
9160 09:32:36.538943 CPU_CLUSTER: 0: enabled 1
9161 09:32:36.539362 CPU: 00: enabled 1
9162 09:32:36.542721 Compare with tree...
9163 09:32:36.543136 Root Device: enabled 1
9164 09:32:36.546044 CPU_CLUSTER: 0: enabled 1
9165 09:32:36.549573 CPU: 00: enabled 1
9166 09:32:36.549990 Root Device scanning...
9167 09:32:36.552894 scan_static_bus for Root Device
9168 09:32:36.555760 CPU_CLUSTER: 0 enabled
9169 09:32:36.559308 scan_static_bus for Root Device done
9170 09:32:36.562404 scan_bus: bus Root Device finished in 8 msecs
9171 09:32:36.562823 done
9172 09:32:36.569389 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9173 09:32:36.572869 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9174 09:32:36.579540 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9175 09:32:36.582714 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9176 09:32:36.586134 Allocating resources...
9177 09:32:36.589384 Reading resources...
9178 09:32:36.592429 Root Device read_resources bus 0 link: 0
9179 09:32:36.592847 DRAM rank0 size:0x100000000,
9180 09:32:36.595699 DRAM rank1 size=0x100000000
9181 09:32:36.599135 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9182 09:32:36.602509 CPU: 00 missing read_resources
9183 09:32:36.606090 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9184 09:32:36.612205 Root Device read_resources bus 0 link: 0 done
9185 09:32:36.612624 Done reading resources.
9186 09:32:36.618846 Show resources in subtree (Root Device)...After reading.
9187 09:32:36.622298 Root Device child on link 0 CPU_CLUSTER: 0
9188 09:32:36.625523 CPU_CLUSTER: 0 child on link 0 CPU: 00
9189 09:32:36.635386 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9190 09:32:36.635844 CPU: 00
9191 09:32:36.638771 Root Device assign_resources, bus 0 link: 0
9192 09:32:36.642303 CPU_CLUSTER: 0 missing set_resources
9193 09:32:36.649073 Root Device assign_resources, bus 0 link: 0 done
9194 09:32:36.649496 Done setting resources.
9195 09:32:36.655634 Show resources in subtree (Root Device)...After assigning values.
9196 09:32:36.658764 Root Device child on link 0 CPU_CLUSTER: 0
9197 09:32:36.692975 CPU_CLUSTER: 0 child on link 0 CPU: 00
9198 09:32:36.693434 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9199 09:32:36.693781 CPU: 00
9200 09:32:36.694240 Done allocating resources.
9201 09:32:36.694633 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9202 09:32:36.695048 Enabling resources...
9203 09:32:36.695357 done.
9204 09:32:36.695693 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9205 09:32:36.696004 Initializing devices...
9206 09:32:36.696292 Root Device init
9207 09:32:36.696580 init hardware done!
9208 09:32:36.697211 0x00000018: ctrlr->caps
9209 09:32:36.698257 52.000 MHz: ctrlr->f_max
9210 09:32:36.698687 0.400 MHz: ctrlr->f_min
9211 09:32:36.702049 0x40ff8080: ctrlr->voltages
9212 09:32:36.702479 sclk: 390625
9213 09:32:36.705226 Bus Width = 1
9214 09:32:36.705642 sclk: 390625
9215 09:32:36.708422 Bus Width = 1
9216 09:32:36.708840 Early init status = 3
9217 09:32:36.715355 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9218 09:32:36.718525 in-header: 03 fc 00 00 01 00 00 00
9219 09:32:36.718945 in-data: 00
9220 09:32:36.725112 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9221 09:32:36.728280 in-header: 03 fd 00 00 00 00 00 00
9222 09:32:36.731680 in-data:
9223 09:32:36.734866 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9224 09:32:36.738053 in-header: 03 fc 00 00 01 00 00 00
9225 09:32:36.741315 in-data: 00
9226 09:32:36.744879 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9227 09:32:36.750133 in-header: 03 fd 00 00 00 00 00 00
9228 09:32:36.753487 in-data:
9229 09:32:36.756399 [SSUSB] Setting up USB HOST controller...
9230 09:32:36.759495 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9231 09:32:36.762820 [SSUSB] phy power-on done.
9232 09:32:36.766626 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9233 09:32:36.772936 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9234 09:32:36.776056 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9235 09:32:36.782628 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9236 09:32:36.789606 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9237 09:32:36.795750 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9238 09:32:36.802265 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9239 09:32:36.830881 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9240 09:32:36.831077 SPM: binary array size = 0x9dc
9241 09:32:36.831149 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9242 09:32:36.831242 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9243 09:32:36.831301 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9244 09:32:36.832432 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9245 09:32:36.838963 configure_display: Starting display init
9246 09:32:36.872385 anx7625_power_on_init: Init interface.
9247 09:32:36.875760 anx7625_disable_pd_protocol: Disabled PD feature.
9248 09:32:36.879013 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9249 09:32:36.907129 anx7625_start_dp_work: Secure OCM version=00
9250 09:32:36.910511 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9251 09:32:36.924979 sp_tx_get_edid_block: EDID Block = 1
9252 09:32:37.027511 Extracted contents:
9253 09:32:37.030712 header: 00 ff ff ff ff ff ff 00
9254 09:32:37.034494 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9255 09:32:37.037790 version: 01 04
9256 09:32:37.040982 basic params: 95 1f 11 78 0a
9257 09:32:37.044194 chroma info: 76 90 94 55 54 90 27 21 50 54
9258 09:32:37.047554 established: 00 00 00
9259 09:32:37.054474 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9260 09:32:37.057626 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9261 09:32:37.064118 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9262 09:32:37.070702 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9263 09:32:37.077840 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9264 09:32:37.080790 extensions: 00
9265 09:32:37.080899 checksum: fb
9266 09:32:37.080980
9267 09:32:37.084545 Manufacturer: IVO Model 57d Serial Number 0
9268 09:32:37.087678 Made week 0 of 2020
9269 09:32:37.087756 EDID version: 1.4
9270 09:32:37.091123 Digital display
9271 09:32:37.094478 6 bits per primary color channel
9272 09:32:37.094562 DisplayPort interface
9273 09:32:37.097882 Maximum image size: 31 cm x 17 cm
9274 09:32:37.100611 Gamma: 220%
9275 09:32:37.100693 Check DPMS levels
9276 09:32:37.104564 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9277 09:32:37.107944 First detailed timing is preferred timing
9278 09:32:37.111124 Established timings supported:
9279 09:32:37.114411 Standard timings supported:
9280 09:32:37.114493 Detailed timings
9281 09:32:37.120790 Hex of detail: 383680a07038204018303c0035ae10000019
9282 09:32:37.124446 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9283 09:32:37.127557 0780 0798 07c8 0820 hborder 0
9284 09:32:37.134154 0438 043b 0447 0458 vborder 0
9285 09:32:37.134245 -hsync -vsync
9286 09:32:37.137297 Did detailed timing
9287 09:32:37.140785 Hex of detail: 000000000000000000000000000000000000
9288 09:32:37.144019 Manufacturer-specified data, tag 0
9289 09:32:37.150485 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9290 09:32:37.150568 ASCII string: InfoVision
9291 09:32:37.157180 Hex of detail: 000000fe00523134304e574635205248200a
9292 09:32:37.160986 ASCII string: R140NWF5 RH
9293 09:32:37.161068 Checksum
9294 09:32:37.161133 Checksum: 0xfb (valid)
9295 09:32:37.167475 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9296 09:32:37.170440 DSI data_rate: 832800000 bps
9297 09:32:37.174116 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9298 09:32:37.177642 anx7625_parse_edid: pixelclock(138800).
9299 09:32:37.183980 hactive(1920), hsync(48), hfp(24), hbp(88)
9300 09:32:37.187012 vactive(1080), vsync(12), vfp(3), vbp(17)
9301 09:32:37.190820 anx7625_dsi_config: config dsi.
9302 09:32:37.197282 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9303 09:32:37.209500 anx7625_dsi_config: success to config DSI
9304 09:32:37.213416 anx7625_dp_start: MIPI phy setup OK.
9305 09:32:37.216737 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9306 09:32:37.220083 mtk_ddp_mode_set invalid vrefresh 60
9307 09:32:37.223298 main_disp_path_setup
9308 09:32:37.223378 ovl_layer_smi_id_en
9309 09:32:37.226565 ovl_layer_smi_id_en
9310 09:32:37.226645 ccorr_config
9311 09:32:37.226709 aal_config
9312 09:32:37.229725 gamma_config
9313 09:32:37.229832 postmask_config
9314 09:32:37.229935 dither_config
9315 09:32:37.236602 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9316 09:32:37.243065 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9317 09:32:37.246388 Root Device init finished in 551 msecs
9318 09:32:37.246469 CPU_CLUSTER: 0 init
9319 09:32:37.256305 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9320 09:32:37.259528 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9321 09:32:37.262888 APU_MBOX 0x190000b0 = 0x10001
9322 09:32:37.266236 APU_MBOX 0x190001b0 = 0x10001
9323 09:32:37.269419 APU_MBOX 0x190005b0 = 0x10001
9324 09:32:37.272818 APU_MBOX 0x190006b0 = 0x10001
9325 09:32:37.276400 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9326 09:32:37.288307 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9327 09:32:37.301133 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9328 09:32:37.307584 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9329 09:32:37.319477 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9330 09:32:37.328728 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9331 09:32:37.332067 CPU_CLUSTER: 0 init finished in 81 msecs
9332 09:32:37.335599 Devices initialized
9333 09:32:37.338825 Show all devs... After init.
9334 09:32:37.338905 Root Device: enabled 1
9335 09:32:37.341810 CPU_CLUSTER: 0: enabled 1
9336 09:32:37.344903 CPU: 00: enabled 1
9337 09:32:37.348567 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9338 09:32:37.351612 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9339 09:32:37.355071 ELOG: NV offset 0x57f000 size 0x1000
9340 09:32:37.361533 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9341 09:32:37.368078 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9342 09:32:37.371424 ELOG: Event(17) added with size 13 at 2023-10-20 09:31:03 UTC
9343 09:32:37.374731 out: cmd=0x121: 03 db 21 01 00 00 00 00
9344 09:32:37.378778 in-header: 03 ee 00 00 2c 00 00 00
9345 09:32:37.392017 in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9346 09:32:37.398867 ELOG: Event(A1) added with size 10 at 2023-10-20 09:31:03 UTC
9347 09:32:37.405513 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9348 09:32:37.412074 ELOG: Event(A0) added with size 9 at 2023-10-20 09:31:03 UTC
9349 09:32:37.415425 elog_add_boot_reason: Logged dev mode boot
9350 09:32:37.418632 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9351 09:32:37.421810 Finalize devices...
9352 09:32:37.421887 Devices finalized
9353 09:32:37.428395 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9354 09:32:37.431583 Writing coreboot table at 0xffe64000
9355 09:32:37.435219 0. 000000000010a000-0000000000113fff: RAMSTAGE
9356 09:32:37.438799 1. 0000000040000000-00000000400fffff: RAM
9357 09:32:37.441628 2. 0000000040100000-000000004032afff: RAMSTAGE
9358 09:32:37.448529 3. 000000004032b000-00000000545fffff: RAM
9359 09:32:37.452127 4. 0000000054600000-000000005465ffff: BL31
9360 09:32:37.455254 5. 0000000054660000-00000000ffe63fff: RAM
9361 09:32:37.458298 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9362 09:32:37.464874 7. 0000000100000000-000000023fffffff: RAM
9363 09:32:37.464949 Passing 5 GPIOs to payload:
9364 09:32:37.471667 NAME | PORT | POLARITY | VALUE
9365 09:32:37.474963 EC in RW | 0x000000aa | low | undefined
9366 09:32:37.481602 EC interrupt | 0x00000005 | low | undefined
9367 09:32:37.484788 TPM interrupt | 0x000000ab | high | undefined
9368 09:32:37.488777 SD card detect | 0x00000011 | high | undefined
9369 09:32:37.494999 speaker enable | 0x00000093 | high | undefined
9370 09:32:37.498534 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9371 09:32:37.501652 in-header: 03 f9 00 00 02 00 00 00
9372 09:32:37.501735 in-data: 02 00
9373 09:32:37.504922 ADC[4]: Raw value=905096 ID=7
9374 09:32:37.508277 ADC[3]: Raw value=213441 ID=1
9375 09:32:37.508359 RAM Code: 0x71
9376 09:32:37.511576 ADC[6]: Raw value=75701 ID=0
9377 09:32:37.514920 ADC[5]: Raw value=213072 ID=1
9378 09:32:37.515020 SKU Code: 0x1
9379 09:32:37.521644 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 77d7
9380 09:32:37.524829 coreboot table: 964 bytes.
9381 09:32:37.528224 IMD ROOT 0. 0xfffff000 0x00001000
9382 09:32:37.531531 IMD SMALL 1. 0xffffe000 0x00001000
9383 09:32:37.534834 RO MCACHE 2. 0xffffc000 0x00001104
9384 09:32:37.538170 CONSOLE 3. 0xfff7c000 0x00080000
9385 09:32:37.541399 FMAP 4. 0xfff7b000 0x00000452
9386 09:32:37.544685 TIME STAMP 5. 0xfff7a000 0x00000910
9387 09:32:37.548003 VBOOT WORK 6. 0xfff66000 0x00014000
9388 09:32:37.551900 RAMOOPS 7. 0xffe66000 0x00100000
9389 09:32:37.554931 COREBOOT 8. 0xffe64000 0x00002000
9390 09:32:37.555006 IMD small region:
9391 09:32:37.557939 IMD ROOT 0. 0xffffec00 0x00000400
9392 09:32:37.561749 VPD 1. 0xffffeb80 0x0000006c
9393 09:32:37.564589 MMC STATUS 2. 0xffffeb60 0x00000004
9394 09:32:37.571664 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9395 09:32:37.574861 Probing TPM: done!
9396 09:32:37.577836 Connected to device vid:did:rid of 1ae0:0028:00
9397 09:32:37.588132 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9398 09:32:37.591413 Initialized TPM device CR50 revision 0
9399 09:32:37.594796 Checking cr50 for pending updates
9400 09:32:37.598130 Reading cr50 TPM mode
9401 09:32:37.606892 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9402 09:32:37.613825 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9403 09:32:37.653877 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9404 09:32:37.656986 Checking segment from ROM address 0x40100000
9405 09:32:37.660219 Checking segment from ROM address 0x4010001c
9406 09:32:37.667170 Loading segment from ROM address 0x40100000
9407 09:32:37.667270 code (compression=0)
9408 09:32:37.673947 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9409 09:32:37.684093 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9410 09:32:37.684171 it's not compressed!
9411 09:32:37.690385 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9412 09:32:37.694034 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9413 09:32:37.713990 Loading segment from ROM address 0x4010001c
9414 09:32:37.714077 Entry Point 0x80000000
9415 09:32:37.717283 Loaded segments
9416 09:32:37.720772 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9417 09:32:37.727413 Jumping to boot code at 0x80000000(0xffe64000)
9418 09:32:37.733970 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9419 09:32:37.740764 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9420 09:32:37.748566 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9421 09:32:37.751699 Checking segment from ROM address 0x40100000
9422 09:32:37.755168 Checking segment from ROM address 0x4010001c
9423 09:32:37.762253 Loading segment from ROM address 0x40100000
9424 09:32:37.762394 code (compression=1)
9425 09:32:37.768830 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9426 09:32:37.778558 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9427 09:32:37.778704 using LZMA
9428 09:32:37.786623 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9429 09:32:37.793145 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9430 09:32:37.796994 Loading segment from ROM address 0x4010001c
9431 09:32:37.800226 Entry Point 0x54601000
9432 09:32:37.800308 Loaded segments
9433 09:32:37.803221 NOTICE: MT8192 bl31_setup
9434 09:32:37.810563 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9435 09:32:37.814250 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9436 09:32:37.817217 WARNING: region 0:
9437 09:32:37.820428 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9438 09:32:37.820510 WARNING: region 1:
9439 09:32:37.827775 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9440 09:32:37.830947 WARNING: region 2:
9441 09:32:37.834033 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9442 09:32:37.837188 WARNING: region 3:
9443 09:32:37.840801 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9444 09:32:37.844243 WARNING: region 4:
9445 09:32:37.847412 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9446 09:32:37.850837 WARNING: region 5:
9447 09:32:37.854151 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 09:32:37.857304 WARNING: region 6:
9449 09:32:37.860735 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9450 09:32:37.860807 WARNING: region 7:
9451 09:32:37.867763 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 09:32:37.874488 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9453 09:32:37.877756 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9454 09:32:37.881116 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9455 09:32:37.887539 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9456 09:32:37.891162 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9457 09:32:37.894157 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9458 09:32:37.900627 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9459 09:32:37.903853 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9460 09:32:37.907624 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9461 09:32:37.914000 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9462 09:32:37.917761 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9463 09:32:37.923933 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9464 09:32:37.927629 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9465 09:32:37.930793 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9466 09:32:37.937280 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9467 09:32:37.941152 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9468 09:32:37.944346 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9469 09:32:37.951252 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9470 09:32:37.954609 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9471 09:32:37.958049 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9472 09:32:37.964087 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9473 09:32:37.967790 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9474 09:32:37.974348 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9475 09:32:37.977623 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9476 09:32:37.980871 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9477 09:32:37.987529 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9478 09:32:37.990870 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9479 09:32:37.998040 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9480 09:32:38.001380 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9481 09:32:38.004660 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9482 09:32:38.011258 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9483 09:32:38.014140 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9484 09:32:38.017704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9485 09:32:38.024494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9486 09:32:38.027488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9487 09:32:38.031058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9488 09:32:38.034197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9489 09:32:38.041058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9490 09:32:38.044228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9491 09:32:38.048179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9492 09:32:38.051512 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9493 09:32:38.057665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9494 09:32:38.061051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9495 09:32:38.064273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9496 09:32:38.067515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9497 09:32:38.074575 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9498 09:32:38.077833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9499 09:32:38.081003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9500 09:32:38.087634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9501 09:32:38.090935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9502 09:32:38.094322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9503 09:32:38.101563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9504 09:32:38.104813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9505 09:32:38.111537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9506 09:32:38.114651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9507 09:32:38.117798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9508 09:32:38.124615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9509 09:32:38.127723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9510 09:32:38.134504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9511 09:32:38.138121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9512 09:32:38.144702 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9513 09:32:38.148456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9514 09:32:38.151336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9515 09:32:38.158605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9516 09:32:38.161477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9517 09:32:38.168329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9518 09:32:38.171370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9519 09:32:38.178593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9520 09:32:38.181895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9521 09:32:38.185280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9522 09:32:38.191886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9523 09:32:38.195274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9524 09:32:38.202078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9525 09:32:38.205434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9526 09:32:38.211723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9527 09:32:38.215227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9528 09:32:38.218408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9529 09:32:38.225259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9530 09:32:38.228596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9531 09:32:38.235672 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9532 09:32:38.238857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9533 09:32:38.245398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9534 09:32:38.249285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9535 09:32:38.252102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9536 09:32:38.258939 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9537 09:32:38.262389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9538 09:32:38.268862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9539 09:32:38.272672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9540 09:32:38.275826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9541 09:32:38.282337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9542 09:32:38.285297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9543 09:32:38.292475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9544 09:32:38.295910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9545 09:32:38.302467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9546 09:32:38.305751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9547 09:32:38.312441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9548 09:32:38.315520 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9549 09:32:38.318897 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9550 09:32:38.322227 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9551 09:32:38.328667 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9552 09:32:38.332367 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9553 09:32:38.335592 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9554 09:32:38.342068 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9555 09:32:38.345307 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9556 09:32:38.352448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9557 09:32:38.355813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9558 09:32:38.358939 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9559 09:32:38.365424 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9560 09:32:38.369039 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9561 09:32:38.372107 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9562 09:32:38.378732 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9563 09:32:38.382053 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9564 09:32:38.389005 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9565 09:32:38.392275 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9566 09:32:38.395635 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9567 09:32:38.402294 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9568 09:32:38.405478 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9569 09:32:38.408828 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9570 09:32:38.415406 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9571 09:32:38.419311 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9572 09:32:38.422467 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9573 09:32:38.425808 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9574 09:32:38.429148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9575 09:32:38.436220 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9576 09:32:38.439474 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9577 09:32:38.445726 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9578 09:32:38.449073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9579 09:32:38.452892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9580 09:32:38.459151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9581 09:32:38.462456 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9582 09:32:38.465836 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9583 09:32:38.472826 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9584 09:32:38.475960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9585 09:32:38.482938 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9586 09:32:38.486395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9587 09:32:38.490105 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9588 09:32:38.496120 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9589 09:32:38.499846 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9590 09:32:38.502923 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9591 09:32:38.509733 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9592 09:32:38.513116 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9593 09:32:38.519632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9594 09:32:38.522958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9595 09:32:38.526170 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9596 09:32:38.533153 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9597 09:32:38.536493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9598 09:32:38.542899 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9599 09:32:38.546213 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9600 09:32:38.549388 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9601 09:32:38.556587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9602 09:32:38.559833 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9603 09:32:38.562939 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9604 09:32:38.570020 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9605 09:32:38.573356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9606 09:32:38.579700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9607 09:32:38.582894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9608 09:32:38.586292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9609 09:32:38.593091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9610 09:32:38.596102 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9611 09:32:38.602775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9612 09:32:38.606134 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9613 09:32:38.609515 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9614 09:32:38.616249 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9615 09:32:38.619398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9616 09:32:38.625888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9617 09:32:38.629657 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9618 09:32:38.632806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9619 09:32:38.639317 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9620 09:32:38.643037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9621 09:32:38.646252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9622 09:32:38.652853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9623 09:32:38.656164 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9624 09:32:38.662496 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9625 09:32:38.665668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9626 09:32:38.669433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9627 09:32:38.675852 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9628 09:32:38.679346 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9629 09:32:38.685765 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9630 09:32:38.689059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9631 09:32:38.692376 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9632 09:32:38.698973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9633 09:32:38.702356 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9634 09:32:38.708846 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9635 09:32:38.712288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9636 09:32:38.715489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9637 09:32:38.722165 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9638 09:32:38.726101 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9639 09:32:38.729471 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9640 09:32:38.735919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9641 09:32:38.738911 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9642 09:32:38.745986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9643 09:32:38.749024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9644 09:32:38.755630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9645 09:32:38.758859 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9646 09:32:38.762147 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9647 09:32:38.769185 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9648 09:32:38.772489 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9649 09:32:38.778973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9650 09:32:38.782010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9651 09:32:38.785446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9652 09:32:38.792378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9653 09:32:38.795551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9654 09:32:38.802029 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9655 09:32:38.805348 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9656 09:32:38.812237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9657 09:32:38.815512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9658 09:32:38.818534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9659 09:32:38.825481 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9660 09:32:38.828906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9661 09:32:38.835754 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9662 09:32:38.839001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9663 09:32:38.842120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9664 09:32:38.848460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9665 09:32:38.852148 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9666 09:32:38.858627 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9667 09:32:38.862159 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9668 09:32:38.868106 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9669 09:32:38.871843 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9670 09:32:38.874900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9671 09:32:38.881930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9672 09:32:38.885155 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9673 09:32:38.892028 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9674 09:32:38.895123 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9675 09:32:38.898221 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9676 09:32:38.904752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9677 09:32:38.908118 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9678 09:32:38.914730 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9679 09:32:38.918017 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9680 09:32:38.924756 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9681 09:32:38.928060 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9682 09:32:38.931285 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9683 09:32:38.934449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9684 09:32:38.937694 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9685 09:32:38.944357 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9686 09:32:38.947822 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9687 09:32:38.951093 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9688 09:32:38.957707 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9689 09:32:38.960985 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9690 09:32:38.964289 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9691 09:32:38.971546 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9692 09:32:38.974698 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9693 09:32:38.981381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9694 09:32:38.984774 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9695 09:32:38.987794 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9696 09:32:38.994367 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9697 09:32:38.997705 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9698 09:32:39.001329 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9699 09:32:39.007614 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9700 09:32:39.011284 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9701 09:32:39.014514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9702 09:32:39.021091 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9703 09:32:39.024515 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9704 09:32:39.031596 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9705 09:32:39.034276 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9706 09:32:39.037786 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9707 09:32:39.044611 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9708 09:32:39.047730 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9709 09:32:39.051387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9710 09:32:39.057972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9711 09:32:39.061284 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9712 09:32:39.064684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9713 09:32:39.071283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9714 09:32:39.074598 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9715 09:32:39.077945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9716 09:32:39.084805 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9717 09:32:39.088185 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9718 09:32:39.094806 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9719 09:32:39.097911 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9720 09:32:39.101298 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9721 09:32:39.108190 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9722 09:32:39.111153 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9723 09:32:39.114755 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9724 09:32:39.117779 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9725 09:32:39.121153 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9726 09:32:39.128034 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9727 09:32:39.131094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9728 09:32:39.134478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9729 09:32:39.138253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9730 09:32:39.144991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9731 09:32:39.148242 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9732 09:32:39.151620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9733 09:32:39.154714 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9734 09:32:39.161318 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9735 09:32:39.164533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9736 09:32:39.170780 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9737 09:32:39.174321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9738 09:32:39.180857 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9739 09:32:39.184728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9740 09:32:39.187877 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9741 09:32:39.194487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9742 09:32:39.197896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9743 09:32:39.204779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9744 09:32:39.208016 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9745 09:32:39.211453 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9746 09:32:39.218107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9747 09:32:39.221406 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9748 09:32:39.228042 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9749 09:32:39.231190 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9750 09:32:39.234548 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9751 09:32:39.240847 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9752 09:32:39.244370 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9753 09:32:39.250746 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9754 09:32:39.254052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9755 09:32:39.261359 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9756 09:32:39.264433 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9757 09:32:39.267596 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9758 09:32:39.274041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9759 09:32:39.277461 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9760 09:32:39.280846 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9761 09:32:39.287484 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9762 09:32:39.291147 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9763 09:32:39.297656 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9764 09:32:39.300650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9765 09:32:39.307177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9766 09:32:39.310624 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9767 09:32:39.314008 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9768 09:32:39.320849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9769 09:32:39.324271 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9770 09:32:39.330897 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9771 09:32:39.333703 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9772 09:32:39.337473 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9773 09:32:39.344013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9774 09:32:39.347220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9775 09:32:39.353834 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9776 09:32:39.357359 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9777 09:32:39.363668 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9778 09:32:39.367277 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9779 09:32:39.370163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9780 09:32:39.376610 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9781 09:32:39.379977 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9782 09:32:39.386391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9783 09:32:39.389607 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9784 09:32:39.392936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9785 09:32:39.399601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9786 09:32:39.403348 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9787 09:32:39.409957 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9788 09:32:39.412776 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9789 09:32:39.416557 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9790 09:32:39.423341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9791 09:32:39.426813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9792 09:32:39.433070 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9793 09:32:39.436449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9794 09:32:39.442938 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9795 09:32:39.446128 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9796 09:32:39.449958 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9797 09:32:39.456497 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9798 09:32:39.459288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9799 09:32:39.465839 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9800 09:32:39.469114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9801 09:32:39.473122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9802 09:32:39.479414 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9803 09:32:39.482614 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9804 09:32:39.489249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9805 09:32:39.493068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9806 09:32:39.495922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9807 09:32:39.502507 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9808 09:32:39.505959 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9809 09:32:39.512948 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9810 09:32:39.516339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9811 09:32:39.522474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9812 09:32:39.526114 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9813 09:32:39.529315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9814 09:32:39.536125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9815 09:32:39.539478 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9816 09:32:39.545847 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9817 09:32:39.549256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9818 09:32:39.556357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9819 09:32:39.559401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9820 09:32:39.562710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9821 09:32:39.569681 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9822 09:32:39.573000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9823 09:32:39.579118 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9824 09:32:39.582437 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9825 09:32:39.589091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9826 09:32:39.592853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9827 09:32:39.599379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9828 09:32:39.602647 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9829 09:32:39.605892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9830 09:32:39.612353 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9831 09:32:39.615863 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9832 09:32:39.622529 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9833 09:32:39.626080 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9834 09:32:39.632115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9835 09:32:39.635826 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9836 09:32:39.639125 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9837 09:32:39.645575 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9838 09:32:39.648710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9839 09:32:39.655569 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9840 09:32:39.659274 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9841 09:32:39.665939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9842 09:32:39.669161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9843 09:32:39.675831 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9844 09:32:39.678541 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9845 09:32:39.682474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9846 09:32:39.689050 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9847 09:32:39.692283 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9848 09:32:39.698747 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9849 09:32:39.702517 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9850 09:32:39.705965 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9851 09:32:39.712331 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9852 09:32:39.715898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9853 09:32:39.722072 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9854 09:32:39.725847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9855 09:32:39.728808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9856 09:32:39.735145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9857 09:32:39.738812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9858 09:32:39.745556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9859 09:32:39.749054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9860 09:32:39.755740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9861 09:32:39.758996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9862 09:32:39.765675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9863 09:32:39.768929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9864 09:32:39.775594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9865 09:32:39.778913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9866 09:32:39.785763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9867 09:32:39.789191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9868 09:32:39.795927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9869 09:32:39.798634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9870 09:32:39.805823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9871 09:32:39.808928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9872 09:32:39.928485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9873 09:32:39.928999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9874 09:32:39.929350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9875 09:32:39.929670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9876 09:32:39.929978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9877 09:32:39.930359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9878 09:32:39.930677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9879 09:32:39.930972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9880 09:32:39.931262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9881 09:32:39.931549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9882 09:32:39.931901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9883 09:32:39.932193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9884 09:32:39.932475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9885 09:32:39.932755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9886 09:32:39.933034 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9887 09:32:39.933313 INFO: [APUAPC] vio 0
9888 09:32:39.933595 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9889 09:32:39.933872 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9890 09:32:39.934150 INFO: [APUAPC] D0_APC_0: 0x400510
9891 09:32:39.934431 INFO: [APUAPC] D0_APC_1: 0x0
9892 09:32:39.934709 INFO: [APUAPC] D0_APC_2: 0x1540
9893 09:32:39.934986 INFO: [APUAPC] D0_APC_3: 0x0
9894 09:32:39.935256 INFO: [APUAPC] D1_APC_0: 0xffffffff
9895 09:32:39.935530 INFO: [APUAPC] D1_APC_1: 0xffffffff
9896 09:32:39.935871 INFO: [APUAPC] D1_APC_2: 0x3fffff
9897 09:32:39.936248 INFO: [APUAPC] D1_APC_3: 0x0
9898 09:32:39.936536 INFO: [APUAPC] D2_APC_0: 0xffffffff
9899 09:32:39.936837 INFO: [APUAPC] D2_APC_1: 0xffffffff
9900 09:32:39.937190 INFO: [APUAPC] D2_APC_2: 0x3fffff
9901 09:32:39.937544 INFO: [APUAPC] D2_APC_3: 0x0
9902 09:32:39.938086 INFO: [APUAPC] D3_APC_0: 0xffffffff
9903 09:32:39.938885 INFO: [APUAPC] D3_APC_1: 0xffffffff
9904 09:32:39.942116 INFO: [APUAPC] D3_APC_2: 0x3fffff
9905 09:32:39.945419 INFO: [APUAPC] D3_APC_3: 0x0
9906 09:32:39.948085 INFO: [APUAPC] D4_APC_0: 0xffffffff
9907 09:32:39.951425 INFO: [APUAPC] D4_APC_1: 0xffffffff
9908 09:32:39.955148 INFO: [APUAPC] D4_APC_2: 0x3fffff
9909 09:32:39.958169 INFO: [APUAPC] D4_APC_3: 0x0
9910 09:32:39.961740 INFO: [APUAPC] D5_APC_0: 0xffffffff
9911 09:32:39.964731 INFO: [APUAPC] D5_APC_1: 0xffffffff
9912 09:32:39.968125 INFO: [APUAPC] D5_APC_2: 0x3fffff
9913 09:32:39.971416 INFO: [APUAPC] D5_APC_3: 0x0
9914 09:32:39.974596 INFO: [APUAPC] D6_APC_0: 0xffffffff
9915 09:32:39.977867 INFO: [APUAPC] D6_APC_1: 0xffffffff
9916 09:32:39.981132 INFO: [APUAPC] D6_APC_2: 0x3fffff
9917 09:32:39.984423 INFO: [APUAPC] D6_APC_3: 0x0
9918 09:32:39.987616 INFO: [APUAPC] D7_APC_0: 0xffffffff
9919 09:32:39.991158 INFO: [APUAPC] D7_APC_1: 0xffffffff
9920 09:32:39.994296 INFO: [APUAPC] D7_APC_2: 0x3fffff
9921 09:32:39.997638 INFO: [APUAPC] D7_APC_3: 0x0
9922 09:32:40.000923 INFO: [APUAPC] D8_APC_0: 0xffffffff
9923 09:32:40.004265 INFO: [APUAPC] D8_APC_1: 0xffffffff
9924 09:32:40.007850 INFO: [APUAPC] D8_APC_2: 0x3fffff
9925 09:32:40.010899 INFO: [APUAPC] D8_APC_3: 0x0
9926 09:32:40.014488 INFO: [APUAPC] D9_APC_0: 0xffffffff
9927 09:32:40.017314 INFO: [APUAPC] D9_APC_1: 0xffffffff
9928 09:32:40.021222 INFO: [APUAPC] D9_APC_2: 0x3fffff
9929 09:32:40.024113 INFO: [APUAPC] D9_APC_3: 0x0
9930 09:32:40.027810 INFO: [APUAPC] D10_APC_0: 0xffffffff
9931 09:32:40.031025 INFO: [APUAPC] D10_APC_1: 0xffffffff
9932 09:32:40.034482 INFO: [APUAPC] D10_APC_2: 0x3fffff
9933 09:32:40.037649 INFO: [APUAPC] D10_APC_3: 0x0
9934 09:32:40.040882 INFO: [APUAPC] D11_APC_0: 0xffffffff
9935 09:32:40.044237 INFO: [APUAPC] D11_APC_1: 0xffffffff
9936 09:32:40.047492 INFO: [APUAPC] D11_APC_2: 0x3fffff
9937 09:32:40.050823 INFO: [APUAPC] D11_APC_3: 0x0
9938 09:32:40.054124 INFO: [APUAPC] D12_APC_0: 0xffffffff
9939 09:32:40.057528 INFO: [APUAPC] D12_APC_1: 0xffffffff
9940 09:32:40.060854 INFO: [APUAPC] D12_APC_2: 0x3fffff
9941 09:32:40.064222 INFO: [APUAPC] D12_APC_3: 0x0
9942 09:32:40.067408 INFO: [APUAPC] D13_APC_0: 0xffffffff
9943 09:32:40.070700 INFO: [APUAPC] D13_APC_1: 0xffffffff
9944 09:32:40.073920 INFO: [APUAPC] D13_APC_2: 0x3fffff
9945 09:32:40.077638 INFO: [APUAPC] D13_APC_3: 0x0
9946 09:32:40.081261 INFO: [APUAPC] D14_APC_0: 0xffffffff
9947 09:32:40.084034 INFO: [APUAPC] D14_APC_1: 0xffffffff
9948 09:32:40.087815 INFO: [APUAPC] D14_APC_2: 0x3fffff
9949 09:32:40.091007 INFO: [APUAPC] D14_APC_3: 0x0
9950 09:32:40.094276 INFO: [APUAPC] D15_APC_0: 0xffffffff
9951 09:32:40.097514 INFO: [APUAPC] D15_APC_1: 0xffffffff
9952 09:32:40.101083 INFO: [APUAPC] D15_APC_2: 0x3fffff
9953 09:32:40.104426 INFO: [APUAPC] D15_APC_3: 0x0
9954 09:32:40.107941 INFO: [APUAPC] APC_CON: 0x4
9955 09:32:40.111284 INFO: [NOCDAPC] D0_APC_0: 0x0
9956 09:32:40.114550 INFO: [NOCDAPC] D0_APC_1: 0x0
9957 09:32:40.115127 INFO: [NOCDAPC] D1_APC_0: 0x0
9958 09:32:40.117285 INFO: [NOCDAPC] D1_APC_1: 0xfff
9959 09:32:40.120943 INFO: [NOCDAPC] D2_APC_0: 0x0
9960 09:32:40.123926 INFO: [NOCDAPC] D2_APC_1: 0xfff
9961 09:32:40.127742 INFO: [NOCDAPC] D3_APC_0: 0x0
9962 09:32:40.130653 INFO: [NOCDAPC] D3_APC_1: 0xfff
9963 09:32:40.134356 INFO: [NOCDAPC] D4_APC_0: 0x0
9964 09:32:40.137503 INFO: [NOCDAPC] D4_APC_1: 0xfff
9965 09:32:40.140392 INFO: [NOCDAPC] D5_APC_0: 0x0
9966 09:32:40.144284 INFO: [NOCDAPC] D5_APC_1: 0xfff
9967 09:32:40.147601 INFO: [NOCDAPC] D6_APC_0: 0x0
9968 09:32:40.148178 INFO: [NOCDAPC] D6_APC_1: 0xfff
9969 09:32:40.151092 INFO: [NOCDAPC] D7_APC_0: 0x0
9970 09:32:40.153909 INFO: [NOCDAPC] D7_APC_1: 0xfff
9971 09:32:40.157118 INFO: [NOCDAPC] D8_APC_0: 0x0
9972 09:32:40.160428 INFO: [NOCDAPC] D8_APC_1: 0xfff
9973 09:32:40.163738 INFO: [NOCDAPC] D9_APC_0: 0x0
9974 09:32:40.167299 INFO: [NOCDAPC] D9_APC_1: 0xfff
9975 09:32:40.170712 INFO: [NOCDAPC] D10_APC_0: 0x0
9976 09:32:40.173627 INFO: [NOCDAPC] D10_APC_1: 0xfff
9977 09:32:40.177533 INFO: [NOCDAPC] D11_APC_0: 0x0
9978 09:32:40.181055 INFO: [NOCDAPC] D11_APC_1: 0xfff
9979 09:32:40.184318 INFO: [NOCDAPC] D12_APC_0: 0x0
9980 09:32:40.187554 INFO: [NOCDAPC] D12_APC_1: 0xfff
9981 09:32:40.188129 INFO: [NOCDAPC] D13_APC_0: 0x0
9982 09:32:40.190339 INFO: [NOCDAPC] D13_APC_1: 0xfff
9983 09:32:40.193171 INFO: [NOCDAPC] D14_APC_0: 0x0
9984 09:32:40.196700 INFO: [NOCDAPC] D14_APC_1: 0xfff
9985 09:32:40.200020 INFO: [NOCDAPC] D15_APC_0: 0x0
9986 09:32:40.203311 INFO: [NOCDAPC] D15_APC_1: 0xfff
9987 09:32:40.206644 INFO: [NOCDAPC] APC_CON: 0x4
9988 09:32:40.210000 INFO: [APUAPC] set_apusys_apc done
9989 09:32:40.213107 INFO: [DEVAPC] devapc_init done
9990 09:32:40.217099 INFO: GICv3 without legacy support detected.
9991 09:32:40.219683 INFO: ARM GICv3 driver initialized in EL3
9992 09:32:40.226439 INFO: Maximum SPI INTID supported: 639
9993 09:32:40.230227 INFO: BL31: Initializing runtime services
9994 09:32:40.236548 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9995 09:32:40.236970 INFO: SPM: enable CPC mode
9996 09:32:40.243334 INFO: mcdi ready for mcusys-off-idle and system suspend
9997 09:32:40.246728 INFO: BL31: Preparing for EL3 exit to normal world
9998 09:32:40.250162 INFO: Entry point address = 0x80000000
9999 09:32:40.253393 INFO: SPSR = 0x8
10000 09:32:40.259777
10001 09:32:40.260273
10002 09:32:40.260609
10003 09:32:40.260919 Starting depthcharge on Spherion...
10004 09:32:40.263364 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10005 09:32:40.263925 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10006 09:32:40.264324 Setting prompt string to ['asurada:']
10007 09:32:40.264717 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10008 09:32:40.265381
10009 09:32:40.265770 Wipe memory regions:
10010 09:32:40.266101
10011 09:32:40.266463 [0x00000040000000, 0x00000054600000)
10012 09:32:40.388346
10013 09:32:40.388862 [0x00000054660000, 0x00000080000000)
10014 09:32:40.648988
10015 09:32:40.649553 [0x000000821a7280, 0x000000ffe64000)
10016 09:32:41.393542
10017 09:32:41.394072 [0x00000100000000, 0x00000240000000)
10018 09:32:43.284285
10019 09:32:43.287221 Initializing XHCI USB controller at 0x11200000.
10020 09:32:44.325341
10021 09:32:44.328298 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10022 09:32:44.328727
10023 09:32:44.329064
10024 09:32:44.329381
10025 09:32:44.330192 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10027 09:32:44.431698 asurada: tftpboot 192.168.201.1 11826815/tftp-deploy-k85cv_7w/kernel/image.itb 11826815/tftp-deploy-k85cv_7w/kernel/cmdline
10028 09:32:44.432350 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10029 09:32:44.432818 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10030 09:32:44.437926 tftpboot 192.168.201.1 11826815/tftp-deploy-k85cv_7w/kernel/image.ittp-deploy-k85cv_7w/kernel/cmdline
10031 09:32:44.438529
10032 09:32:44.439009 Waiting for link
10033 09:32:44.598205
10034 09:32:44.598716 R8152: Initializing
10035 09:32:44.599059
10036 09:32:44.601880 Version 9 (ocp_data = 6010)
10037 09:32:44.602399
10038 09:32:44.605104 R8152: Done initializing
10039 09:32:44.605644
10040 09:32:44.606009 Adding net device
10041 09:32:46.473597
10042 09:32:46.474120 done.
10043 09:32:46.474470
10044 09:32:46.474786 MAC: 00:e0:4c:78:7a:aa
10045 09:32:46.475092
10046 09:32:46.476496 Sending DHCP discover... done.
10047 09:32:46.477102
10048 09:32:46.480295 Waiting for reply... done.
10049 09:32:46.480718
10050 09:32:46.483691 Sending DHCP request... done.
10051 09:32:46.484113
10052 09:32:46.487878 Waiting for reply... done.
10053 09:32:46.488400
10054 09:32:46.488743 My ip is 192.168.201.12
10055 09:32:46.489062
10056 09:32:46.490888 The DHCP server ip is 192.168.201.1
10057 09:32:46.491313
10058 09:32:46.497655 TFTP server IP predefined by user: 192.168.201.1
10059 09:32:46.498144
10060 09:32:46.504097 Bootfile predefined by user: 11826815/tftp-deploy-k85cv_7w/kernel/image.itb
10061 09:32:46.504522
10062 09:32:46.504859 Sending tftp read request... done.
10063 09:32:46.507167
10064 09:32:46.513489 Waiting for the transfer...
10065 09:32:46.514018
10066 09:32:46.874976 00000000 ################################################################
10067 09:32:46.875110
10068 09:32:47.157454 00080000 ################################################################
10069 09:32:47.157588
10070 09:32:47.435277 00100000 ################################################################
10071 09:32:47.435408
10072 09:32:47.722807 00180000 ################################################################
10073 09:32:47.722944
10074 09:32:48.019844 00200000 ################################################################
10075 09:32:48.019972
10076 09:32:48.315498 00280000 ################################################################
10077 09:32:48.315628
10078 09:32:48.614517 00300000 ################################################################
10079 09:32:48.614675
10080 09:32:48.916083 00380000 ################################################################
10081 09:32:48.916211
10082 09:32:49.217339 00400000 ################################################################
10083 09:32:49.217497
10084 09:32:49.509084 00480000 ################################################################
10085 09:32:49.509220
10086 09:32:49.759077 00500000 ################################################################
10087 09:32:49.759221
10088 09:32:50.008789 00580000 ################################################################
10089 09:32:50.008927
10090 09:32:50.282131 00600000 ################################################################
10091 09:32:50.282265
10092 09:32:50.558140 00680000 ################################################################
10093 09:32:50.558298
10094 09:32:50.797077 00700000 ################################################################
10095 09:32:50.797278
10096 09:32:51.034009 00780000 ################################################################
10097 09:32:51.034145
10098 09:32:51.279585 00800000 ################################################################
10099 09:32:51.279738
10100 09:32:51.531530 00880000 ################################################################
10101 09:32:51.531689
10102 09:32:51.787225 00900000 ################################################################
10103 09:32:51.787397
10104 09:32:52.049606 00980000 ################################################################
10105 09:32:52.049738
10106 09:32:52.318967 00a00000 ################################################################
10107 09:32:52.319103
10108 09:32:52.578158 00a80000 ################################################################
10109 09:32:52.578358
10110 09:32:52.835963 00b00000 ################################################################
10111 09:32:52.836099
10112 09:32:53.090855 00b80000 ################################################################
10113 09:32:53.090991
10114 09:32:53.342493 00c00000 ################################################################
10115 09:32:53.342649
10116 09:32:53.593373 00c80000 ################################################################
10117 09:32:53.593504
10118 09:32:53.849733 00d00000 ################################################################
10119 09:32:53.849860
10120 09:32:54.105756 00d80000 ################################################################
10121 09:32:54.105881
10122 09:32:54.356583 00e00000 ################################################################
10123 09:32:54.356722
10124 09:32:54.606380 00e80000 ################################################################
10125 09:32:54.606517
10126 09:32:54.888657 00f00000 ################################################################
10127 09:32:54.888795
10128 09:32:55.179315 00f80000 ################################################################
10129 09:32:55.179463
10130 09:32:55.464227 01000000 ################################################################
10131 09:32:55.464364
10132 09:32:55.739705 01080000 ################################################################
10133 09:32:55.739849
10134 09:32:55.992583 01100000 ################################################################
10135 09:32:55.992732
10136 09:32:56.242885 01180000 ################################################################
10137 09:32:56.243018
10138 09:32:56.491630 01200000 ################################################################
10139 09:32:56.491810
10140 09:32:56.755785 01280000 ################################################################
10141 09:32:56.755941
10142 09:32:57.010374 01300000 ################################################################
10143 09:32:57.010519
10144 09:32:57.286306 01380000 ################################################################
10145 09:32:57.286453
10146 09:32:57.551702 01400000 ################################################################
10147 09:32:57.551849
10148 09:32:57.802191 01480000 ################################################################
10149 09:32:57.802327
10150 09:32:58.060202 01500000 ################################################################
10151 09:32:58.060349
10152 09:32:58.320224 01580000 ################################################################
10153 09:32:58.320374
10154 09:32:58.587621 01600000 ################################################################
10155 09:32:58.587803
10156 09:32:58.844024 01680000 ################################################################
10157 09:32:58.844178
10158 09:32:59.089050 01700000 ################################################################
10159 09:32:59.089234
10160 09:32:59.340052 01780000 ################################################################
10161 09:32:59.340202
10162 09:32:59.588732 01800000 ################################################################
10163 09:32:59.588882
10164 09:32:59.838875 01880000 ################################################################
10165 09:32:59.839023
10166 09:33:00.096560 01900000 ################################################################
10167 09:33:00.096734
10168 09:33:00.360487 01980000 ################################################################
10169 09:33:00.360647
10170 09:33:00.632871 01a00000 ################################################################
10171 09:33:00.633030
10172 09:33:00.898217 01a80000 ################################################################
10173 09:33:00.898389
10174 09:33:01.144498 01b00000 ################################################################
10175 09:33:01.144674
10176 09:33:01.387703 01b80000 ################################################################
10177 09:33:01.387874
10178 09:33:01.634933 01c00000 ################################################################
10179 09:33:01.635094
10180 09:33:01.884080 01c80000 ################################################################
10181 09:33:01.884246
10182 09:33:02.129533 01d00000 ################################################################
10183 09:33:02.129679
10184 09:33:02.374494 01d80000 ################################################################
10185 09:33:02.374638
10186 09:33:02.622126 01e00000 ################################################################
10187 09:33:02.622297
10188 09:33:02.872382 01e80000 ################################################################
10189 09:33:02.872557
10190 09:33:03.118594 01f00000 ################################################################
10191 09:33:03.118750
10192 09:33:03.375246 01f80000 ################################################################
10193 09:33:03.375404
10194 09:33:03.623633 02000000 ################################################################
10195 09:33:03.623814
10196 09:33:03.881835 02080000 ################################################################
10197 09:33:03.881973
10198 09:33:04.136701 02100000 ################################################################
10199 09:33:04.136850
10200 09:33:04.390862 02180000 ################################################################
10201 09:33:04.390999
10202 09:33:04.663878 02200000 ################################################################
10203 09:33:04.664020
10204 09:33:04.922208 02280000 ################################################################
10205 09:33:04.922340
10206 09:33:05.191539 02300000 ################################################################
10207 09:33:05.191710
10208 09:33:05.472813 02380000 ################################################################
10209 09:33:05.472951
10210 09:33:05.739024 02400000 ################################################################
10211 09:33:05.739162
10212 09:33:05.999216 02480000 ################################################################
10213 09:33:05.999386
10214 09:33:06.277339 02500000 ################################################################
10215 09:33:06.277477
10216 09:33:06.554892 02580000 ################################################################
10217 09:33:06.555034
10218 09:33:06.821582 02600000 ################################################################
10219 09:33:06.821751
10220 09:33:07.091093 02680000 ################################################################
10221 09:33:07.091240
10222 09:33:07.339746 02700000 ################################################################
10223 09:33:07.339893
10224 09:33:07.617018 02780000 ################################################################
10225 09:33:07.617192
10226 09:33:07.878663 02800000 ################################################################
10227 09:33:07.878810
10228 09:33:08.135118 02880000 ################################################################
10229 09:33:08.135266
10230 09:33:08.400066 02900000 ################################################################
10231 09:33:08.400203
10232 09:33:08.650162 02980000 ################################################################
10233 09:33:08.650300
10234 09:33:08.901715 02a00000 ################################################################
10235 09:33:08.901875
10236 09:33:09.152167 02a80000 ################################################################
10237 09:33:09.152303
10238 09:33:09.403139 02b00000 ################################################################
10239 09:33:09.403269
10240 09:33:09.656065 02b80000 ################################################################
10241 09:33:09.656204
10242 09:33:09.917644 02c00000 ################################################################
10243 09:33:09.917781
10244 09:33:10.186103 02c80000 ################################################################
10245 09:33:10.186262
10246 09:33:10.478494 02d00000 ################################################################
10247 09:33:10.478663
10248 09:33:10.765159 02d80000 ################################################################
10249 09:33:10.765291
10250 09:33:11.017585 02e00000 ################################################################
10251 09:33:11.017758
10252 09:33:11.278469 02e80000 ################################################################
10253 09:33:11.278604
10254 09:33:11.538809 02f00000 ################################################################
10255 09:33:11.538944
10256 09:33:11.789279 02f80000 ################################################################
10257 09:33:11.789419
10258 09:33:11.840680 03000000 ############## done.
10259 09:33:11.840828
10260 09:33:11.843797 The bootfile was 50443318 bytes long.
10261 09:33:11.843882
10262 09:33:11.847550 Sending tftp read request... done.
10263 09:33:11.847659
10264 09:33:11.850692 Waiting for the transfer...
10265 09:33:11.850777
10266 09:33:11.854247 00000000 # done.
10267 09:33:11.854332
10268 09:33:11.861003 Command line loaded dynamically from TFTP file: 11826815/tftp-deploy-k85cv_7w/kernel/cmdline
10269 09:33:11.861092
10270 09:33:11.873955 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10271 09:33:11.874059
10272 09:33:11.874127 Loading FIT.
10273 09:33:11.877580
10274 09:33:11.877906 Image ramdisk-1 has 39349745 bytes.
10275 09:33:11.878170
10276 09:33:11.880732 Image fdt-1 has 47278 bytes.
10277 09:33:11.880973
10278 09:33:11.884117 Image kernel-1 has 11044258 bytes.
10279 09:33:11.884360
10280 09:33:11.893963 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10281 09:33:11.894207
10282 09:33:11.910718 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10283 09:33:11.910986
10284 09:33:11.917251 Choosing best match conf-1 for compat google,spherion-rev2.
10285 09:33:11.917495
10286 09:33:11.925159 Connected to device vid:did:rid of 1ae0:0028:00
10287 09:33:11.932303
10288 09:33:11.935428 tpm_get_response: command 0x17b, return code 0x0
10289 09:33:11.935619
10290 09:33:11.938635 ec_init: CrosEC protocol v3 supported (256, 248)
10291 09:33:11.942865
10292 09:33:11.945977 tpm_cleanup: add release locality here.
10293 09:33:11.946131
10294 09:33:11.946267 Shutting down all USB controllers.
10295 09:33:11.946399
10296 09:33:11.948979 Removing current net device
10297 09:33:11.949074
10298 09:33:11.955824 Exiting depthcharge with code 4 at timestamp: 60956776
10299 09:33:11.955908
10300 09:33:11.959027 LZMA decompressing kernel-1 to 0x821a6718
10301 09:33:11.959110
10302 09:33:11.962698 LZMA decompressing kernel-1 to 0x40000000
10303 09:33:13.351789
10304 09:33:13.351945 jumping to kernel
10305 09:33:13.352482 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10306 09:33:13.352583 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10307 09:33:13.352661 Setting prompt string to ['Linux version [0-9]']
10308 09:33:13.352731 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10309 09:33:13.352798 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10310 09:33:13.433390
10311 09:33:13.437379 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10312 09:33:13.440841 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10313 09:33:13.440931 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10314 09:33:13.441003 Setting prompt string to []
10315 09:33:13.441083 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10316 09:33:13.441159 Using line separator: #'\n'#
10317 09:33:13.441219 No login prompt set.
10318 09:33:13.441282 Parsing kernel messages
10319 09:33:13.441338 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10320 09:33:13.441439 [login-action] Waiting for messages, (timeout 00:03:52)
10321 09:33:13.460213 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10322 09:33:13.463480 [ 0.000000] random: crng init done
10323 09:33:13.466735 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10324 09:33:13.469937 [ 0.000000] efi: UEFI not found.
10325 09:33:13.480507 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10326 09:33:13.487018 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10327 09:33:13.496862 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10328 09:33:13.506718 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10329 09:33:13.513407 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10330 09:33:13.516915 [ 0.000000] printk: bootconsole [mtk8250] enabled
10331 09:33:13.525599 [ 0.000000] NUMA: No NUMA configuration found
10332 09:33:13.532178 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10333 09:33:13.538892 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10334 09:33:13.538975 [ 0.000000] Zone ranges:
10335 09:33:13.545204 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10336 09:33:13.548501 [ 0.000000] DMA32 empty
10337 09:33:13.555103 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10338 09:33:13.558523 [ 0.000000] Movable zone start for each node
10339 09:33:13.561718 [ 0.000000] Early memory node ranges
10340 09:33:13.568525 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10341 09:33:13.574953 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10342 09:33:13.581587 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10343 09:33:13.588329 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10344 09:33:13.594798 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10345 09:33:13.601702 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10346 09:33:13.658063 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10347 09:33:13.664597 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10348 09:33:13.671296 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10349 09:33:13.674555 [ 0.000000] psci: probing for conduit method from DT.
10350 09:33:13.681150 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10351 09:33:13.684796 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10352 09:33:13.691199 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10353 09:33:13.694355 [ 0.000000] psci: SMC Calling Convention v1.2
10354 09:33:13.701263 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10355 09:33:13.704150 [ 0.000000] Detected VIPT I-cache on CPU0
10356 09:33:13.711346 [ 0.000000] CPU features: detected: GIC system register CPU interface
10357 09:33:13.718128 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10358 09:33:13.724545 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10359 09:33:13.730699 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10360 09:33:13.737400 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10361 09:33:13.747368 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10362 09:33:13.750735 [ 0.000000] alternatives: applying boot alternatives
10363 09:33:13.757351 [ 0.000000] Fallback order for Node 0: 0
10364 09:33:13.764538 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10365 09:33:13.767420 [ 0.000000] Policy zone: Normal
10366 09:33:13.780647 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10367 09:33:13.790598 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10368 09:33:13.802313 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10369 09:33:13.812691 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10370 09:33:13.818903 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10371 09:33:13.822484 <6>[ 0.000000] software IO TLB: area num 8.
10372 09:33:13.878636 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10373 09:33:14.028502 <6>[ 0.000000] Memory: 7931068K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 421700K reserved, 32768K cma-reserved)
10374 09:33:14.035178 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10375 09:33:14.041533 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10376 09:33:14.044853 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10377 09:33:14.051631 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10378 09:33:14.058149 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10379 09:33:14.061854 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10380 09:33:14.071773 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10381 09:33:14.077988 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10382 09:33:14.081353 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10383 09:33:14.089385 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10384 09:33:14.092691 <6>[ 0.000000] GICv3: 608 SPIs implemented
10385 09:33:14.099179 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10386 09:33:14.102236 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10387 09:33:14.105916 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10388 09:33:14.115799 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10389 09:33:14.126067 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10390 09:33:14.138670 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10391 09:33:14.145835 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10392 09:33:14.154667 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10393 09:33:14.168182 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10394 09:33:14.174735 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10395 09:33:14.181173 <6>[ 0.009177] Console: colour dummy device 80x25
10396 09:33:14.191145 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10397 09:33:14.194741 <6>[ 0.024409] pid_max: default: 32768 minimum: 301
10398 09:33:14.201115 <6>[ 0.029280] LSM: Security Framework initializing
10399 09:33:14.208111 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 09:33:14.217872 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10401 09:33:14.224352 <6>[ 0.051451] cblist_init_generic: Setting adjustable number of callback queues.
10402 09:33:14.230920 <6>[ 0.058894] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 09:33:14.241485 <6>[ 0.065271] cblist_init_generic: Setting adjustable number of callback queues.
10404 09:33:14.244632 <6>[ 0.072744] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 09:33:14.251137 <6>[ 0.079143] rcu: Hierarchical SRCU implementation.
10406 09:33:14.257864 <6>[ 0.084159] rcu: Max phase no-delay instances is 1000.
10407 09:33:14.263915 <6>[ 0.091186] EFI services will not be available.
10408 09:33:14.267330 <6>[ 0.096146] smp: Bringing up secondary CPUs ...
10409 09:33:14.275616 <6>[ 0.101225] Detected VIPT I-cache on CPU1
10410 09:33:14.282434 <6>[ 0.101294] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10411 09:33:14.288621 <6>[ 0.101325] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10412 09:33:14.292069 <6>[ 0.101655] Detected VIPT I-cache on CPU2
10413 09:33:14.302089 <6>[ 0.101703] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10414 09:33:14.308376 <6>[ 0.101718] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10415 09:33:14.312043 <6>[ 0.101974] Detected VIPT I-cache on CPU3
10416 09:33:14.318531 <6>[ 0.102020] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10417 09:33:14.324978 <6>[ 0.102034] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10418 09:33:14.331607 <6>[ 0.102335] CPU features: detected: Spectre-v4
10419 09:33:14.334792 <6>[ 0.102342] CPU features: detected: Spectre-BHB
10420 09:33:14.338287 <6>[ 0.102346] Detected PIPT I-cache on CPU4
10421 09:33:14.344583 <6>[ 0.102402] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10422 09:33:14.351053 <6>[ 0.102418] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10423 09:33:14.358334 <6>[ 0.102711] Detected PIPT I-cache on CPU5
10424 09:33:14.364252 <6>[ 0.102773] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10425 09:33:14.370894 <6>[ 0.102790] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10426 09:33:14.374800 <6>[ 0.103060] Detected PIPT I-cache on CPU6
10427 09:33:14.381165 <6>[ 0.103118] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10428 09:33:14.387756 <6>[ 0.103134] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10429 09:33:14.394634 <6>[ 0.103421] Detected PIPT I-cache on CPU7
10430 09:33:14.401275 <6>[ 0.103486] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10431 09:33:14.407654 <6>[ 0.103502] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10432 09:33:14.411066 <6>[ 0.103549] smp: Brought up 1 node, 8 CPUs
10433 09:33:14.417469 <6>[ 0.244891] SMP: Total of 8 processors activated.
10434 09:33:14.420794 <6>[ 0.249842] CPU features: detected: 32-bit EL0 Support
10435 09:33:14.430581 <6>[ 0.255204] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10436 09:33:14.437396 <6>[ 0.264005] CPU features: detected: Common not Private translations
10437 09:33:14.443948 <6>[ 0.270482] CPU features: detected: CRC32 instructions
10438 09:33:14.447109 <6>[ 0.275866] CPU features: detected: RCpc load-acquire (LDAPR)
10439 09:33:14.453998 <6>[ 0.281826] CPU features: detected: LSE atomic instructions
10440 09:33:14.460419 <6>[ 0.287643] CPU features: detected: Privileged Access Never
10441 09:33:14.467248 <6>[ 0.293423] CPU features: detected: RAS Extension Support
10442 09:33:14.473631 <6>[ 0.299033] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10443 09:33:14.477130 <6>[ 0.306296] CPU: All CPU(s) started at EL2
10444 09:33:14.483892 <6>[ 0.310613] alternatives: applying system-wide alternatives
10445 09:33:14.493359 <6>[ 0.321262] devtmpfs: initialized
10446 09:33:14.509121 <6>[ 0.330387] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10447 09:33:14.515580 <6>[ 0.340348] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10448 09:33:14.522063 <6>[ 0.348513] pinctrl core: initialized pinctrl subsystem
10449 09:33:14.525419 <6>[ 0.355150] DMI not present or invalid.
10450 09:33:14.531802 <6>[ 0.359559] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10451 09:33:14.542036 <6>[ 0.366404] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10452 09:33:14.548671 <6>[ 0.373986] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10453 09:33:14.558025 <6>[ 0.382209] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10454 09:33:14.561355 <6>[ 0.390447] audit: initializing netlink subsys (disabled)
10455 09:33:14.571549 <5>[ 0.396137] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10456 09:33:14.577891 <6>[ 0.396840] thermal_sys: Registered thermal governor 'step_wise'
10457 09:33:14.584988 <6>[ 0.404102] thermal_sys: Registered thermal governor 'power_allocator'
10458 09:33:14.588300 <6>[ 0.410359] cpuidle: using governor menu
10459 09:33:14.594898 <6>[ 0.421321] NET: Registered PF_QIPCRTR protocol family
10460 09:33:14.601556 <6>[ 0.426797] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10461 09:33:14.604711 <6>[ 0.433900] ASID allocator initialised with 32768 entries
10462 09:33:14.612019 <6>[ 0.440466] Serial: AMBA PL011 UART driver
10463 09:33:14.621355 <4>[ 0.449206] Trying to register duplicate clock ID: 134
10464 09:33:14.675368 <6>[ 0.506855] KASLR enabled
10465 09:33:14.689696 <6>[ 0.514583] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10466 09:33:14.696273 <6>[ 0.521597] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10467 09:33:14.702914 <6>[ 0.528085] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10468 09:33:14.709885 <6>[ 0.535090] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10469 09:33:14.716030 <6>[ 0.541578] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10470 09:33:14.722713 <6>[ 0.548582] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10471 09:33:14.729241 <6>[ 0.555071] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10472 09:33:14.736045 <6>[ 0.562075] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10473 09:33:14.739310 <6>[ 0.569593] ACPI: Interpreter disabled.
10474 09:33:14.747741 <6>[ 0.576015] iommu: Default domain type: Translated
10475 09:33:14.754738 <6>[ 0.581129] iommu: DMA domain TLB invalidation policy: strict mode
10476 09:33:14.758049 <5>[ 0.587779] SCSI subsystem initialized
10477 09:33:14.764607 <6>[ 0.591947] usbcore: registered new interface driver usbfs
10478 09:33:14.770943 <6>[ 0.597677] usbcore: registered new interface driver hub
10479 09:33:14.774157 <6>[ 0.603230] usbcore: registered new device driver usb
10480 09:33:14.780968 <6>[ 0.609328] pps_core: LinuxPPS API ver. 1 registered
10481 09:33:14.790841 <6>[ 0.614524] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10482 09:33:14.794753 <6>[ 0.623869] PTP clock support registered
10483 09:33:14.797851 <6>[ 0.628110] EDAC MC: Ver: 3.0.0
10484 09:33:14.805230 <6>[ 0.633273] FPGA manager framework
10485 09:33:14.811502 <6>[ 0.636952] Advanced Linux Sound Architecture Driver Initialized.
10486 09:33:14.815162 <6>[ 0.643729] vgaarb: loaded
10487 09:33:14.822030 <6>[ 0.646891] clocksource: Switched to clocksource arch_sys_counter
10488 09:33:14.825208 <5>[ 0.653326] VFS: Disk quotas dquot_6.6.0
10489 09:33:14.831772 <6>[ 0.657512] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10490 09:33:14.834990 <6>[ 0.664700] pnp: PnP ACPI: disabled
10491 09:33:14.843586 <6>[ 0.671364] NET: Registered PF_INET protocol family
10492 09:33:14.853219 <6>[ 0.676952] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10493 09:33:14.864340 <6>[ 0.689250] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10494 09:33:14.874804 <6>[ 0.698062] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10495 09:33:14.881365 <6>[ 0.706031] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10496 09:33:14.887907 <6>[ 0.714734] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10497 09:33:14.899601 <6>[ 0.724452] TCP: Hash tables configured (established 65536 bind 65536)
10498 09:33:14.906147 <6>[ 0.731310] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10499 09:33:14.913082 <6>[ 0.738507] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10500 09:33:14.919640 <6>[ 0.746202] NET: Registered PF_UNIX/PF_LOCAL protocol family
10501 09:33:14.925826 <6>[ 0.752363] RPC: Registered named UNIX socket transport module.
10502 09:33:14.929400 <6>[ 0.758514] RPC: Registered udp transport module.
10503 09:33:14.936175 <6>[ 0.763447] RPC: Registered tcp transport module.
10504 09:33:14.942625 <6>[ 0.768377] RPC: Registered tcp NFSv4.1 backchannel transport module.
10505 09:33:14.945933 <6>[ 0.775043] PCI: CLS 0 bytes, default 64
10506 09:33:14.949307 <6>[ 0.779431] Unpacking initramfs...
10507 09:33:14.966650 <6>[ 0.791501] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10508 09:33:14.976583 <6>[ 0.800170] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10509 09:33:14.979795 <6>[ 0.809028] kvm [1]: IPA Size Limit: 40 bits
10510 09:33:14.986810 <6>[ 0.813558] kvm [1]: GICv3: no GICV resource entry
10511 09:33:14.990091 <6>[ 0.818579] kvm [1]: disabling GICv2 emulation
10512 09:33:14.996647 <6>[ 0.823265] kvm [1]: GIC system register CPU interface enabled
10513 09:33:14.999766 <6>[ 0.829426] kvm [1]: vgic interrupt IRQ18
10514 09:33:15.006761 <6>[ 0.833780] kvm [1]: VHE mode initialized successfully
10515 09:33:15.013339 <5>[ 0.840302] Initialise system trusted keyrings
10516 09:33:15.019534 <6>[ 0.845089] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10517 09:33:15.027139 <6>[ 0.855063] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10518 09:33:15.033619 <5>[ 0.861430] NFS: Registering the id_resolver key type
10519 09:33:15.036732 <5>[ 0.866730] Key type id_resolver registered
10520 09:33:15.043586 <5>[ 0.871144] Key type id_legacy registered
10521 09:33:15.050435 <6>[ 0.875424] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10522 09:33:15.056738 <6>[ 0.882346] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10523 09:33:15.063226 <6>[ 0.890055] 9p: Installing v9fs 9p2000 file system support
10524 09:33:15.099375 <5>[ 0.927212] Key type asymmetric registered
10525 09:33:15.102762 <5>[ 0.931543] Asymmetric key parser 'x509' registered
10526 09:33:15.112609 <6>[ 0.936682] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10527 09:33:15.115592 <6>[ 0.944294] io scheduler mq-deadline registered
10528 09:33:15.118681 <6>[ 0.949069] io scheduler kyber registered
10529 09:33:15.137584 <6>[ 0.966117] EINJ: ACPI disabled.
10530 09:33:15.170121 <4>[ 0.991782] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 09:33:15.180139 <4>[ 1.002417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 09:33:15.195267 <6>[ 1.023207] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10533 09:33:15.203110 <6>[ 1.031272] printk: console [ttyS0] disabled
10534 09:33:15.231129 <6>[ 1.055943] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10535 09:33:15.237903 <6>[ 1.065416] printk: console [ttyS0] enabled
10536 09:33:15.241020 <6>[ 1.065416] printk: console [ttyS0] enabled
10537 09:33:15.248067 <6>[ 1.074310] printk: bootconsole [mtk8250] disabled
10538 09:33:15.250973 <6>[ 1.074310] printk: bootconsole [mtk8250] disabled
10539 09:33:15.257699 <6>[ 1.085579] SuperH (H)SCI(F) driver initialized
10540 09:33:15.260697 <6>[ 1.090848] msm_serial: driver initialized
10541 09:33:15.274591 <6>[ 1.099830] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10542 09:33:15.285031 <6>[ 1.108377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10543 09:33:15.291714 <6>[ 1.116918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10544 09:33:15.301432 <6>[ 1.125547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10545 09:33:15.311812 <6>[ 1.134253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10546 09:33:15.318437 <6>[ 1.142975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10547 09:33:15.327774 <6>[ 1.151514] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10548 09:33:15.334886 <6>[ 1.160310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10549 09:33:15.344579 <6>[ 1.168852] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10550 09:33:15.356367 <6>[ 1.184401] loop: module loaded
10551 09:33:15.363008 <6>[ 1.190294] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10552 09:33:15.385332 <4>[ 1.213625] mtk-pmic-keys: Failed to locate of_node [id: -1]
10553 09:33:15.392654 <6>[ 1.220485] megasas: 07.719.03.00-rc1
10554 09:33:15.401849 <6>[ 1.229971] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10555 09:33:15.414325 <6>[ 1.242284] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10556 09:33:15.430847 <6>[ 1.259045] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10557 09:33:15.488126 <6>[ 1.309378] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10558 09:33:16.532993 <6>[ 2.361392] Freeing initrd memory: 38420K
10559 09:33:16.543581 <6>[ 2.371808] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10560 09:33:16.554805 <6>[ 2.382599] tun: Universal TUN/TAP device driver, 1.6
10561 09:33:16.558101 <6>[ 2.388655] thunder_xcv, ver 1.0
10562 09:33:16.561397 <6>[ 2.392158] thunder_bgx, ver 1.0
10563 09:33:16.564122 <6>[ 2.395651] nicpf, ver 1.0
10564 09:33:16.574851 <6>[ 2.399663] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10565 09:33:16.577926 <6>[ 2.407139] hns3: Copyright (c) 2017 Huawei Corporation.
10566 09:33:16.581391 <6>[ 2.412727] hclge is initializing
10567 09:33:16.588384 <6>[ 2.416303] e1000: Intel(R) PRO/1000 Network Driver
10568 09:33:16.594578 <6>[ 2.421432] e1000: Copyright (c) 1999-2006 Intel Corporation.
10569 09:33:16.597894 <6>[ 2.427446] e1000e: Intel(R) PRO/1000 Network Driver
10570 09:33:16.605000 <6>[ 2.432661] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10571 09:33:16.611300 <6>[ 2.438849] igb: Intel(R) Gigabit Ethernet Network Driver
10572 09:33:16.617999 <6>[ 2.444500] igb: Copyright (c) 2007-2014 Intel Corporation.
10573 09:33:16.624512 <6>[ 2.450335] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10574 09:33:16.630960 <6>[ 2.456854] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10575 09:33:16.634305 <6>[ 2.463316] sky2: driver version 1.30
10576 09:33:16.640862 <6>[ 2.468306] VFIO - User Level meta-driver version: 0.3
10577 09:33:16.648191 <6>[ 2.476563] usbcore: registered new interface driver usb-storage
10578 09:33:16.654812 <6>[ 2.483005] usbcore: registered new device driver onboard-usb-hub
10579 09:33:16.664023 <6>[ 2.492125] mt6397-rtc mt6359-rtc: registered as rtc0
10580 09:33:16.673816 <6>[ 2.497592] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:31:42 UTC (1697794302)
10581 09:33:16.677158 <6>[ 2.507167] i2c_dev: i2c /dev entries driver
10582 09:33:16.694113 <6>[ 2.518891] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10583 09:33:16.713674 <6>[ 2.541880] cpu cpu0: EM: created perf domain
10584 09:33:16.716888 <6>[ 2.546816] cpu cpu4: EM: created perf domain
10585 09:33:16.724163 <6>[ 2.552371] sdhci: Secure Digital Host Controller Interface driver
10586 09:33:16.730625 <6>[ 2.558804] sdhci: Copyright(c) Pierre Ossman
10587 09:33:16.737251 <6>[ 2.563756] Synopsys Designware Multimedia Card Interface Driver
10588 09:33:16.743939 <6>[ 2.570385] sdhci-pltfm: SDHCI platform and OF driver helper
10589 09:33:16.747451 <6>[ 2.570526] mmc0: CQHCI version 5.10
10590 09:33:16.753576 <6>[ 2.580489] ledtrig-cpu: registered to indicate activity on CPUs
10591 09:33:16.760247 <6>[ 2.587509] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10592 09:33:16.766950 <6>[ 2.594561] usbcore: registered new interface driver usbhid
10593 09:33:16.770641 <6>[ 2.600384] usbhid: USB HID core driver
10594 09:33:16.777104 <6>[ 2.604573] spi_master spi0: will run message pump with realtime priority
10595 09:33:16.823604 <6>[ 2.645536] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10596 09:33:16.843833 <6>[ 2.662115] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10597 09:33:16.846986 <6>[ 2.675699] mmc0: Command Queue Engine enabled
10598 09:33:16.853900 <6>[ 2.680463] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10599 09:33:16.860919 <6>[ 2.687604] cros-ec-spi spi0.0: Chrome EC device registered
10600 09:33:16.863916 <6>[ 2.687852] mmcblk0: mmc0:0001 DA4128 116 GiB
10601 09:33:16.877687 <6>[ 2.706254] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10602 09:33:16.885417 <6>[ 2.713908] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10603 09:33:16.895581 <6>[ 2.718538] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 09:33:16.898932 <6>[ 2.719984] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 09:33:16.905830 <6>[ 2.729758] NET: Registered PF_PACKET protocol family
10606 09:33:16.912326 <6>[ 2.734411] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 09:33:16.915615 <6>[ 2.739085] 9pnet: Installing 9P2000 support
10608 09:33:16.922419 <5>[ 2.750076] Key type dns_resolver registered
10609 09:33:16.925167 <6>[ 2.755167] registered taskstats version 1
10610 09:33:16.932038 <5>[ 2.759567] Loading compiled-in X.509 certificates
10611 09:33:16.960640 <4>[ 2.782323] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 09:33:16.971029 <4>[ 2.793067] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 09:33:16.977200 <3>[ 2.803600] debugfs: File 'uA_load' in directory '/' already present!
10614 09:33:16.984201 <3>[ 2.810364] debugfs: File 'min_uV' in directory '/' already present!
10615 09:33:16.990802 <3>[ 2.816981] debugfs: File 'max_uV' in directory '/' already present!
10616 09:33:16.997300 <3>[ 2.823594] debugfs: File 'constraint_flags' in directory '/' already present!
10617 09:33:17.008078 <3>[ 2.833152] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10618 09:33:17.024487 <6>[ 2.852459] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10619 09:33:17.031067 <6>[ 2.859348] xhci-mtk 11200000.usb: xHCI Host Controller
10620 09:33:17.037363 <6>[ 2.864848] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10621 09:33:17.047815 <6>[ 2.872701] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10622 09:33:17.054278 <6>[ 2.882120] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10623 09:33:17.060941 <6>[ 2.888189] xhci-mtk 11200000.usb: xHCI Host Controller
10624 09:33:17.068027 <6>[ 2.893663] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10625 09:33:17.074767 <6>[ 2.901309] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10626 09:33:17.081415 <6>[ 2.908974] hub 1-0:1.0: USB hub found
10627 09:33:17.084664 <6>[ 2.912991] hub 1-0:1.0: 1 port detected
10628 09:33:17.090801 <6>[ 2.917255] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10629 09:33:17.097632 <6>[ 2.925814] hub 2-0:1.0: USB hub found
10630 09:33:17.100806 <6>[ 2.929821] hub 2-0:1.0: 1 port detected
10631 09:33:17.109909 <6>[ 2.938273] mtk-msdc 11f70000.mmc: Got CD GPIO
10632 09:33:17.119957 <6>[ 2.944749] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10633 09:33:17.126643 <6>[ 2.952776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10634 09:33:17.136341 <4>[ 2.960684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10635 09:33:17.146122 <6>[ 2.970207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10636 09:33:17.152761 <6>[ 2.978287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10637 09:33:17.159332 <6>[ 2.986354] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10638 09:33:17.169791 <6>[ 2.994272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10639 09:33:17.176378 <6>[ 3.002090] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10640 09:33:17.185701 <6>[ 3.009907] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10641 09:33:17.196178 <6>[ 3.020040] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10642 09:33:17.202611 <6>[ 3.028401] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10643 09:33:17.212535 <6>[ 3.036742] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10644 09:33:17.219211 <6>[ 3.045080] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10645 09:33:17.229321 <6>[ 3.053420] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10646 09:33:17.235507 <6>[ 3.061759] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10647 09:33:17.245763 <6>[ 3.070097] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10648 09:33:17.252159 <6>[ 3.078436] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10649 09:33:17.262109 <6>[ 3.086773] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10650 09:33:17.268474 <6>[ 3.095111] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10651 09:33:17.278558 <6>[ 3.103450] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10652 09:33:17.285098 <6>[ 3.111788] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10653 09:33:17.295051 <6>[ 3.120138] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10654 09:33:17.301606 <6>[ 3.128478] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10655 09:33:17.311977 <6>[ 3.136817] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10656 09:33:17.318499 <6>[ 3.145701] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10657 09:33:17.325037 <6>[ 3.153019] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10658 09:33:17.331900 <6>[ 3.159974] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10659 09:33:17.341989 <6>[ 3.166912] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10660 09:33:17.348380 <6>[ 3.173996] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10661 09:33:17.355019 <6>[ 3.180871] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10662 09:33:17.364719 <6>[ 3.190003] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10663 09:33:17.374580 <6>[ 3.199123] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10664 09:33:17.384868 <6>[ 3.208417] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10665 09:33:17.394287 <6>[ 3.217885] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10666 09:33:17.404903 <6>[ 3.227353] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10667 09:33:17.411409 <6>[ 3.236473] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10668 09:33:17.420882 <6>[ 3.245969] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10669 09:33:17.431113 <6>[ 3.255090] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10670 09:33:17.441167 <6>[ 3.264385] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10671 09:33:17.450763 <6>[ 3.274546] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10672 09:33:17.461105 <6>[ 3.286504] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10673 09:33:17.490081 <6>[ 3.315492] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10674 09:33:17.518375 <6>[ 3.347076] hub 2-1:1.0: USB hub found
10675 09:33:17.521752 <6>[ 3.351580] hub 2-1:1.0: 3 ports detected
10676 09:33:17.642072 <6>[ 3.467157] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10677 09:33:17.796966 <6>[ 3.625314] hub 1-1:1.0: USB hub found
10678 09:33:17.800041 <6>[ 3.629832] hub 1-1:1.0: 4 ports detected
10679 09:33:17.874319 <6>[ 3.699489] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10680 09:33:18.121847 <6>[ 3.947248] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10681 09:33:18.254862 <6>[ 4.083384] hub 1-1.4:1.0: USB hub found
10682 09:33:18.258037 <6>[ 4.088077] hub 1-1.4:1.0: 2 ports detected
10683 09:33:18.557950 <6>[ 4.383202] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10684 09:33:18.750114 <6>[ 4.575201] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10685 09:33:29.735355 <6>[ 15.568256] ALSA device list:
10686 09:33:29.741600 <6>[ 15.571556] No soundcards found.
10687 09:33:29.749654 <6>[ 15.579679] Freeing unused kernel memory: 8384K
10688 09:33:29.753545 <6>[ 15.584718] Run /init as init process
10689 09:33:29.808300 <6>[ 15.637840] NET: Registered PF_INET6 protocol family
10690 09:33:29.814976 <6>[ 15.644405] Segment Routing with IPv6
10691 09:33:29.818323 <6>[ 15.648360] In-situ OAM (IOAM) with IPv6
10692 09:33:29.850978 <30>[ 15.664116] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10693 09:33:29.857970 <30>[ 15.687879] systemd[1]: Detected architecture arm64.
10694 09:33:29.858084
10695 09:33:29.864354 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10696 09:33:29.864446
10697 09:33:29.877473 <30>[ 15.707323] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10698 09:33:30.005623 <30>[ 15.832108] systemd[1]: Queued start job for default target Graphical Interface.
10699 09:33:30.046073 <30>[ 15.875888] systemd[1]: Created slice system-getty.slice.
10700 09:33:30.052998 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10701 09:33:30.070157 <30>[ 15.899635] systemd[1]: Created slice system-modprobe.slice.
10702 09:33:30.076484 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10703 09:33:30.093845 <30>[ 15.923786] systemd[1]: Created slice system-serial\x2dgetty.slice.
10704 09:33:30.104292 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10705 09:33:30.118576 <30>[ 15.948390] systemd[1]: Created slice User and Session Slice.
10706 09:33:30.125346 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10707 09:33:30.145277 <30>[ 15.971857] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10708 09:33:30.155368 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10709 09:33:30.173489 <30>[ 15.999941] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10710 09:33:30.179852 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10711 09:33:30.204788 <30>[ 16.027682] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10712 09:33:30.211240 <30>[ 16.040043] systemd[1]: Reached target Local Encrypted Volumes.
10713 09:33:30.218068 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10714 09:33:30.234336 <30>[ 16.063767] systemd[1]: Reached target Paths.
10715 09:33:30.240248 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10716 09:33:30.253552 <30>[ 16.083235] systemd[1]: Reached target Remote File Systems.
10717 09:33:30.259983 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10718 09:33:30.277654 <30>[ 16.107232] systemd[1]: Reached target Slices.
10719 09:33:30.284086 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10720 09:33:30.297280 <30>[ 16.127270] systemd[1]: Reached target Swap.
10721 09:33:30.300674 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10722 09:33:30.321056 <30>[ 16.147705] systemd[1]: Listening on initctl Compatibility Named Pipe.
10723 09:33:30.327456 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10724 09:33:30.334697 <30>[ 16.163148] systemd[1]: Listening on Journal Audit Socket.
10725 09:33:30.341093 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10726 09:33:30.358251 <30>[ 16.188457] systemd[1]: Listening on Journal Socket (/dev/log).
10727 09:33:30.365719 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10728 09:33:30.382103 <30>[ 16.211824] systemd[1]: Listening on Journal Socket.
10729 09:33:30.388523 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10730 09:33:30.405289 <30>[ 16.232015] systemd[1]: Listening on Network Service Netlink Socket.
10731 09:33:30.412080 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10732 09:33:30.425884 <30>[ 16.255810] systemd[1]: Listening on udev Control Socket.
10733 09:33:30.432490 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10734 09:33:30.449907 <30>[ 16.279686] systemd[1]: Listening on udev Kernel Socket.
10735 09:33:30.456296 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10736 09:33:30.509712 <30>[ 16.339492] systemd[1]: Mounting Huge Pages File System...
10737 09:33:30.516096 Mounting [0;1;39mHuge Pages File System[0m...
10738 09:33:30.534115 <30>[ 16.363738] systemd[1]: Mounting POSIX Message Queue File System...
10739 09:33:30.541005 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10740 09:33:30.577352 <30>[ 16.407292] systemd[1]: Mounting Kernel Debug File System...
10741 09:33:30.583892 Mounting [0;1;39mKernel Debug File System[0m...
10742 09:33:30.601030 <30>[ 16.427785] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10743 09:33:30.614855 <30>[ 16.441258] systemd[1]: Starting Create list of static device nodes for the current kernel...
10744 09:33:30.621328 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10745 09:33:30.642328 <30>[ 16.472167] systemd[1]: Starting Load Kernel Module configfs...
10746 09:33:30.648782 Starting [0;1;39mLoad Kernel Module configfs[0m...
10747 09:33:30.709734 <30>[ 16.539756] systemd[1]: Starting Load Kernel Module drm...
10748 09:33:30.716425 Starting [0;1;39mLoad Kernel Module drm[0m...
10749 09:33:30.732973 <30>[ 16.559359] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10750 09:33:30.748000 <30>[ 16.577903] systemd[1]: Starting Journal Service...
10751 09:33:30.751149 Starting [0;1;39mJournal Service[0m...
10752 09:33:30.772216 <30>[ 16.601911] systemd[1]: Starting Load Kernel Modules...
10753 09:33:30.778470 Starting [0;1;39mLoad Kernel Modules[0m...
10754 09:33:30.802522 <30>[ 16.629061] systemd[1]: Starting Remount Root and Kernel File Systems...
10755 09:33:30.808991 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10756 09:33:30.825920 <30>[ 16.655407] systemd[1]: Starting Coldplug All udev Devices...
10757 09:33:30.832403 Starting [0;1;39mColdplug All udev Devices[0m...
10758 09:33:30.850738 <30>[ 16.680704] systemd[1]: Started Journal Service.
10759 09:33:30.857192 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10760 09:33:30.871931 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10761 09:33:30.890431 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10762 09:33:30.906229 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10763 09:33:30.926551 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10764 09:33:30.942981 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10765 09:33:30.959506 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10766 09:33:30.974521 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10767 09:33:30.993969 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10768 09:33:31.013752 See 'systemctl status systemd-remount-fs.service' for details.
10769 09:33:31.058206 Mounting [0;1;39mKernel Configuration File System[0m...
10770 09:33:31.083061 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10771 09:33:31.096112 <46>[ 16.922586] systemd-journald[185]: Received client request to flush runtime journal.
10772 09:33:31.107857 Starting [0;1;39mLoad/Save Random Seed[0m...
10773 09:33:31.126902 Starting [0;1;39mApply Kernel Variables[0m...
10774 09:33:31.149001 Starting [0;1;39mCreate System Users[0m...
10775 09:33:31.175055 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10776 09:33:31.194936 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10777 09:33:31.214590 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10778 09:33:31.227299 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10779 09:33:31.243513 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10780 09:33:31.262949 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10781 09:33:31.305755 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10782 09:33:31.327548 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10783 09:33:31.345426 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10784 09:33:31.365683 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10785 09:33:31.426538 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10786 09:33:31.450102 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10787 09:33:31.470910 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10788 09:33:31.490821 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10789 09:33:31.563063 Starting [0;1;39mNetwork Service[0m...
10790 09:33:31.586301 Starting [0;1;39mNetwork Time Synchronization[0m...
10791 09:33:31.614141 Starting [0;1;39mUpdate UTMP about System Boot/Shutdow<6>[ 17.442274] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10792 09:33:31.617264 n[0m...
10793 09:33:31.627028 <6>[ 17.456767] remoteproc remoteproc0: scp is available
10794 09:33:31.633648 <6>[ 17.462286] remoteproc remoteproc0: powering up scp
10795 09:33:31.640167 <6>[ 17.467493] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10796 09:33:31.662104 <6>[ 17.491666] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10797 09:33:31.668194 <6>[ 17.492502] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10798 09:33:31.678521 <6>[ 17.505149] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10799 09:33:31.688286 [[0;32m OK [<6>[ 17.514544] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10800 09:33:31.691716 0m] Found device [0;1;39m/dev/ttyS0[0m.
10801 09:33:31.710285 <6>[ 17.540268] usbcore: registered new interface driver r8152
10802 09:33:31.717234 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10803 09:33:31.726491 <6>[ 17.556188] mc: Linux media interface: v0.10
10804 09:33:31.734269 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10805 09:33:31.741305 <4>[ 17.570384] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10806 09:33:31.753338 <3>[ 17.579640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 09:33:31.759522 <3>[ 17.587885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 09:33:31.769422 <4>[ 17.594476] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10809 09:33:31.776392 <3>[ 17.596046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 09:33:31.786668 [[0;32m OK [<3>[ 17.612796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 09:33:31.796318 0m] Finished [0<3>[ 17.622502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 09:33:31.803067 ;1;39mUpdate UTM<6>[ 17.624217] videodev: Linux video capture interface: v2.00
10813 09:33:31.812758 P about System B<6>[ 17.631811] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10814 09:33:31.822690 oot/Shutdown[0m<6>[ 17.631819] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10815 09:33:31.822789 .
10816 09:33:31.829322 <3>[ 17.632143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 09:33:31.839322 <3>[ 17.632168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 09:33:31.845531 <3>[ 17.632175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 09:33:31.855626 <3>[ 17.634397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 09:33:31.862695 <3>[ 17.635275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 09:33:31.872328 <3>[ 17.635341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 09:33:31.878809 <3>[ 17.635352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 09:33:31.889043 <3>[ 17.641907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 09:33:31.895228 <6>[ 17.647547] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10825 09:33:31.899098 <6>[ 17.647555] pci_bus 0000:00: root bus resource [bus 00-ff]
10826 09:33:31.908977 <6>[ 17.647559] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10827 09:33:31.915354 <6>[ 17.647562] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10828 09:33:31.922007 <6>[ 17.647590] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10829 09:33:31.932327 <6>[ 17.647605] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10830 09:33:31.935327 <6>[ 17.647671] pci 0000:00:00.0: supports D1 D2
10831 09:33:31.942429 <6>[ 17.647673] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10832 09:33:31.948897 <6>[ 17.648624] remoteproc remoteproc0: remote processor scp is now up
10833 09:33:31.958651 <6>[ 17.648655] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10834 09:33:31.965611 <3>[ 17.657219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 09:33:31.971870 <6>[ 17.673913] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10836 09:33:31.978513 <3>[ 17.681755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 09:33:31.988772 <6>[ 17.683709] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10838 09:33:31.995211 <6>[ 17.684282] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10839 09:33:32.002086 <6>[ 17.690681] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10840 09:33:32.011634 <6>[ 17.693006] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10841 09:33:32.022103 <3>[ 17.697931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 09:33:32.028097 <3>[ 17.697939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 09:33:32.038347 <4>[ 17.708012] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10844 09:33:32.041544 <4>[ 17.708012] Fallback method does not support PEC.
10845 09:33:32.048660 <6>[ 17.714217] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10846 09:33:32.058565 <3>[ 17.715565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 09:33:32.068164 <6>[ 17.716123] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10848 09:33:32.075137 <4>[ 17.726641] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10849 09:33:32.084556 <6>[ 17.729243] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10850 09:33:32.088063 <6>[ 17.729411] pci 0000:01:00.0: supports D1 D2
10851 09:33:32.095060 <4>[ 17.735106] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10852 09:33:32.104737 <6>[ 17.735342] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10853 09:33:32.111061 <6>[ 17.743124] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10854 09:33:32.117917 <6>[ 17.753221] usbcore: registered new interface driver cdc_ether
10855 09:33:32.124646 <6>[ 17.771764] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10856 09:33:32.127913 <6>[ 17.786326] Bluetooth: Core ver 2.22
10857 09:33:32.134454 <6>[ 17.786845] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10858 09:33:32.147553 <6>[ 17.788422] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10859 09:33:32.154243 <6>[ 17.788520] usbcore: registered new interface driver uvcvideo
10860 09:33:32.161242 <6>[ 17.793044] usbcore: registered new interface driver r8153_ecm
10861 09:33:32.167793 <6>[ 17.795654] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10862 09:33:32.177493 <6>[ 17.795666] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10863 09:33:32.183926 <6>[ 17.795676] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10864 09:33:32.191047 <6>[ 17.795690] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10865 09:33:32.200736 <6>[ 17.795703] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10866 09:33:32.204246 <6>[ 17.795715] pci 0000:00:00.0: PCI bridge to [bus 01]
10867 09:33:32.213844 <6>[ 17.795720] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10868 09:33:32.220528 <6>[ 17.796012] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10869 09:33:32.227562 <6>[ 17.796597] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10870 09:33:32.230689 <6>[ 17.801528] NET: Registered PF_BLUETOOTH protocol family
10871 09:33:32.237183 <6>[ 17.802812] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10872 09:33:32.245003 <6>[ 17.806357] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10873 09:33:32.255033 <6>[ 17.813910] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10874 09:33:32.262477 <6>[ 17.815125] Bluetooth: HCI device and connection manager initialized
10875 09:33:32.269552 <5>[ 17.824821] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10876 09:33:32.272766 <6>[ 17.830220] Bluetooth: HCI socket layer initialized
10877 09:33:32.279451 <6>[ 17.830605] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10878 09:33:32.285942 <5>[ 17.848657] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10879 09:33:32.292964 <6>[ 17.855623] Bluetooth: L2CAP socket layer initialized
10880 09:33:32.296376 <6>[ 17.859165] r8152 2-1.3:1.0 eth0: v1.12.13
10881 09:33:32.306533 <4>[ 17.863759] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10882 09:33:32.313267 <6>[ 17.869378] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10883 09:33:32.316947 <6>[ 17.877378] Bluetooth: SCO socket layer initialized
10884 09:33:32.323482 <6>[ 17.884894] cfg80211: failed to load regulatory.db
10885 09:33:32.326656 <6>[ 17.964537] usbcore: registered new interface driver btusb
10886 09:33:32.339657 <4>[ 17.965436] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10887 09:33:32.343432 <3>[ 17.965444] Bluetooth: hci0: Failed to load firmware file (-2)
10888 09:33:32.350645 <3>[ 17.965447] Bluetooth: hci0: Failed to set up firmware (-2)
10889 09:33:32.360440 <4>[ 17.965450] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10890 09:33:32.367098 <6>[ 18.054279] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10891 09:33:32.376929 <3>[ 18.090465] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 09:33:32.386883 <3>[ 18.092211] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10893 09:33:32.390211 <6>[ 18.095828] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10894 09:33:32.399897 <3>[ 18.101195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 09:33:32.410306 <3>[ 18.132630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 09:33:32.417028 <3>[ 18.135062] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10897 09:33:32.423147 <6>[ 18.159115] mt7921e 0000:01:00.0: ASIC revision: 79610010
10898 09:33:32.433215 <3>[ 18.183819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 09:33:32.440149 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10900 09:33:32.456280 <4>[ 18.279131] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10901 09:33:32.466107 <3>[ 18.291892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 09:33:32.472697 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10903 09:33:32.500283 [[0;32m OK [0m] Reached targ<3>[ 18.324600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 09:33:32.503351 et [0;1;39mSystem Time Synchronized[0m.
10905 09:33:32.530098 <3>[ 18.356909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 09:33:32.549251 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10907 09:33:32.560947 <3>[ 18.387709] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 09:33:32.576789 <4>[ 18.400195] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10909 09:33:32.590974 Starting [0;1;39mNetwork Name Resolution[0m...
10910 09:33:32.611931 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10911 09:33:32.651815 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10912 09:33:32.701371 <4>[ 18.525026] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10913 09:33:32.731736 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10914 09:33:32.745587 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10915 09:33:32.764635 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10916 09:33:32.777058 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10917 09:33:32.797546 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10918 09:33:32.823103 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary <4>[ 18.645542] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10919 09:33:32.823243 Directories[0m.
10920 09:33:32.837817 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10921 09:33:32.857519 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10922 09:33:32.869262 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10923 09:33:32.885701 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10924 09:33:32.905109 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10925 09:33:32.942771 <4>[ 18.766136] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10926 09:33:32.962936 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10927 09:33:32.992570 Starting [0;1;39mUser Login Management[0m...
10928 09:33:33.010836 Starting [0;1;39mPermit User Sessions[0m...
10929 09:33:33.032328 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10930 09:33:33.065256 <4>[ 18.888431] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10931 09:33:33.071792 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10932 09:33:33.078429 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10933 09:33:33.098614 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10934 09:33:33.112952 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10935 09:33:33.133619 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10936 09:33:33.154414 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10937 09:33:33.181410 [[0;32m OK [<4>[ 19.005802] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10938 09:33:33.187803 0m] Reached target [0;1;39mMulti-User System[0m.
10939 09:33:33.195026 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10940 09:33:33.263399 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10941 09:33:33.302854 <4>[ 19.125980] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 09:33:33.309159 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10943 09:33:33.355674
10944 09:33:33.355833
10945 09:33:33.359063 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10946 09:33:33.359146
10947 09:33:33.362245 debian-bullseye-arm64 login: root (automatic login)
10948 09:33:33.362327
10949 09:33:33.362392
10950 09:33:33.393634 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
10951 09:33:33.393747
10952 09:33:33.399996 The programs included with the Debian GNU/Linux system are free software;
10953 09:33:33.407195 the exact distribution terms for each program are described in the
10954 09:33:33.410330 individual files in /usr/share/doc/*/copyright.
10955 09:33:33.410413
10956 09:33:33.426585 Debian GNU/Linux comes with ABSOLUTELY NO WARRA<4>[ 19.249440] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 09:33:33.426683 NTY, to the extent
10958 09:33:33.430269 permitted by applicable law.
10959 09:33:33.430651 Matched prompt #10: / #
10961 09:33:33.430858 Setting prompt string to ['/ #']
10962 09:33:33.430952 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10964 09:33:33.431149 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10965 09:33:33.431238 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10966 09:33:33.431309 Setting prompt string to ['/ #']
10967 09:33:33.431370 Forcing a shell prompt, looking for ['/ #']
10969 09:33:33.481596 / #
10970 09:33:33.481746 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10971 09:33:33.481855 Waiting using forced prompt support (timeout 00:02:30)
10972 09:33:33.486957
10973 09:33:33.487239 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10974 09:33:33.487339 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10975 09:33:33.487432 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10976 09:33:33.487516 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10977 09:33:33.487602 end: 2 depthcharge-action (duration 00:01:28) [common]
10978 09:33:33.487733 start: 3 lava-test-retry (timeout 00:08:12) [common]
10979 09:33:33.487821 start: 3.1 lava-test-shell (timeout 00:08:12) [common]
10980 09:33:33.487896 Using namespace: common
10982 09:33:33.588260 / # #
10983 09:33:33.588450 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10984 09:33:33.588584 <4>[ 19.369492] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 09:33:33.593007 #
10986 09:33:33.593276 Using /lava-11826815
10988 09:33:33.693649 / # export SHELL=/bin/sh
10989 09:33:33.693888 <6>[ 19.474683] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10990 09:33:33.693969 export SHEL<6>[ 19.482563] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10991 09:33:33.694033 L=/bin/sh<3>[ 19.494946] mt7921e 0000:01:00.0: hardware init failed
10992 09:33:33.699337
10994 09:33:33.799932 / # . /lava-11826815/environment
10995 09:33:33.804986 . /lava-11826815/environment
10997 09:33:33.905594 / # /lava-11826815/bin/lava-test-runner /lava-11826815/0
10998 09:33:33.905783 Test shell timeout: 10s (minimum of the action and connection timeout)
10999 09:33:33.911202 /lava-11826815/bin/lava-test-runner /lava-11826815/0
11000 09:33:33.934849 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11001 09:33:33.941422 + cd /lava-11826815/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11002 09:33:33.941576 + cat uuid
11003 09:33:33.945270 + UUID=11826815_1.5.2.3.1
11004 09:33:33.945368 + set +x
11005 09:33:33.952109 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11826815_1.5.2.3.1>
11006 09:33:33.952420 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11826815_1.5.2.3.1
11007 09:33:33.952502 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11826815_1.5.2.3.1)
11008 09:33:33.952598 Skipping test definition patterns.
11009 09:33:33.955228 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11010 09:33:33.961755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11011 09:33:33.961847 device: /dev/video2
11012 09:33:33.962086 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11014 09:33:33.971257 <4>[ 19.797430] use of bytesused == 0 is deprecated and will be removed in the future,
11015 09:33:33.974989 <4>[ 19.805510] use the actual size instead.
11016 09:33:33.990327 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11017 09:33:34.002433 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11018 09:33:34.008965
11019 09:33:34.023885 Compliance test for mtk-vcodec-enc device /dev/video2:
11020 09:33:34.032553
11021 09:33:34.043270 Driver Info:
11022 09:33:34.053923 Driver name : mtk-vcodec-enc
11023 09:33:34.067426 Card type : MT8192 video encoder
11024 09:33:34.079543 Bus info : platform:17020000.vcodec
11025 09:33:34.088252 Driver version : 6.1.58
11026 09:33:34.099617 Capabilities : 0x84204000
11027 09:33:34.111694 Video Memory-to-Memory Multiplanar
11028 09:33:34.121402 Streaming
11029 09:33:34.133645 Extended Pix Format
11030 09:33:34.148066 Device Capabilities
11031 09:33:34.159677 Device Caps : 0x04204000
11032 09:33:34.170494 Video Memory-to-Memory Multiplanar
11033 09:33:34.186582 Streaming
11034 09:33:34.198654 Extended Pix Format
11035 09:33:34.215363 Detected Stateful Encoder
11036 09:33:34.227056
11037 09:33:34.241984 Required ioctls:
11038 09:33:34.259081 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11039 09:33:34.259200 test VIDIOC_QUERYCAP: OK
11040 09:33:34.259448 Received signal: <TESTSET> START Required-ioctls
11041 09:33:34.259523 Starting test_set Required-ioctls
11042 09:33:34.285052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11043 09:33:34.285345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11045 09:33:34.288273 test invalid ioctls: OK
11046 09:33:34.314799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11047 09:33:34.314911
11048 09:33:34.315155 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11050 09:33:34.326060 Allow for multiple opens:
11051 09:33:34.332395 <LAVA_SIGNAL_TESTSET STOP>
11052 09:33:34.332666 Received signal: <TESTSET> STOP
11053 09:33:34.332754 Closing test_set Required-ioctls
11054 09:33:34.341610 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11055 09:33:34.341868 Received signal: <TESTSET> START Allow-for-multiple-opens
11056 09:33:34.341939 Starting test_set Allow-for-multiple-opens
11057 09:33:34.344759 test second /dev/video2 open: OK
11058 09:33:34.366296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11059 09:33:34.366585 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11061 09:33:34.369595 test VIDIOC_QUERYCAP: OK
11062 09:33:34.389870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11063 09:33:34.390140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11065 09:33:34.393053 test VIDIOC_G/S_PRIORITY: OK
11066 09:33:34.414694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11067 09:33:34.414964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11069 09:33:34.417964 test for unlimited opens: OK
11070 09:33:34.438717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11071 09:33:34.438818
11072 09:33:34.439060 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11074 09:33:34.450565 Debug ioctls:
11075 09:33:34.457203 <LAVA_SIGNAL_TESTSET STOP>
11076 09:33:34.457463 Received signal: <TESTSET> STOP
11077 09:33:34.457534 Closing test_set Allow-for-multiple-opens
11078 09:33:34.466732 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11079 09:33:34.466995 Received signal: <TESTSET> START Debug-ioctls
11080 09:33:34.467066 Starting test_set Debug-ioctls
11081 09:33:34.469879 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11082 09:33:34.491786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11083 09:33:34.492072 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11085 09:33:34.498391 test VIDIOC_LOG_STATUS: OK (Not Supported)
11086 09:33:34.517871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11087 09:33:34.517978
11088 09:33:34.518220 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11090 09:33:34.529769 Input ioctls:
11091 09:33:34.539608 <LAVA_SIGNAL_TESTSET STOP>
11092 09:33:34.539878 Received signal: <TESTSET> STOP
11093 09:33:34.539950 Closing test_set Debug-ioctls
11094 09:33:34.549577 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11095 09:33:34.549855 Received signal: <TESTSET> START Input-ioctls
11096 09:33:34.549927 Starting test_set Input-ioctls
11097 09:33:34.552819 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11098 09:33:34.582121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11099 09:33:34.582429 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11101 09:33:34.584871 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11102 09:33:34.611758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11103 09:33:34.612064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11105 09:33:34.617681 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11106 09:33:34.636504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11107 09:33:34.636778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11109 09:33:34.639765 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11110 09:33:34.660334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11111 09:33:34.660651 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11113 09:33:34.663517 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11114 09:33:34.690724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11115 09:33:34.691044 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11117 09:33:34.693904 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11118 09:33:34.715446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11119 09:33:34.715744 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11121 09:33:34.718811 Inputs: 0 Audio Inputs: 0 Tuners: 0
11122 09:33:34.731089
11123 09:33:34.748722 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11124 09:33:34.770623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11125 09:33:34.770934 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11127 09:33:34.777277 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11128 09:33:34.801918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11129 09:33:34.802196 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11131 09:33:34.805684 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11132 09:33:34.827408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11133 09:33:34.827664 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11135 09:33:34.833812 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11136 09:33:34.855013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11137 09:33:34.855285 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11139 09:33:34.861742 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11140 09:33:34.880936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11141 09:33:34.881061
11142 09:33:34.881302 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11144 09:33:34.898991 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11145 09:33:34.927558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11146 09:33:34.927875 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11148 09:33:34.933783 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11149 09:33:34.957022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11150 09:33:34.957303 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11152 09:33:34.960170 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11153 09:33:34.979311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11154 09:33:34.979610 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11156 09:33:34.982601 test VIDIOC_G/S_EDID: OK (Not Supported)
11157 09:33:35.004748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11158 09:33:35.004874
11159 09:33:35.005148 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11161 09:33:35.015925 Control ioctls:
11162 09:33:35.022840 <LAVA_SIGNAL_TESTSET STOP>
11163 09:33:35.023100 Received signal: <TESTSET> STOP
11164 09:33:35.023169 Closing test_set Input-ioctls
11165 09:33:35.032353 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11166 09:33:35.032611 Received signal: <TESTSET> START Control-ioctls
11167 09:33:35.032680 Starting test_set Control-ioctls
11168 09:33:35.035713 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11169 09:33:35.062805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11170 09:33:35.062902 test VIDIOC_QUERYCTRL: OK
11171 09:33:35.063156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11173 09:33:35.083322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11174 09:33:35.083611 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11176 09:33:35.086518 test VIDIOC_G/S_CTRL: OK
11177 09:33:35.107920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11178 09:33:35.108183 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11180 09:33:35.111471 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11181 09:33:35.131875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11182 09:33:35.132147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11184 09:33:35.141831 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11185 09:33:35.145158 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11186 09:33:35.171102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11187 09:33:35.171389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11189 09:33:35.174298 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11190 09:33:35.194166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11191 09:33:35.194446 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11193 09:33:35.197562 Standard Controls: 16 Private Controls: 0
11194 09:33:35.204899
11195 09:33:35.216137 Format ioctls:
11196 09:33:35.224262 <LAVA_SIGNAL_TESTSET STOP>
11197 09:33:35.224563 Received signal: <TESTSET> STOP
11198 09:33:35.224636 Closing test_set Control-ioctls
11199 09:33:35.233141 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11200 09:33:35.233393 Received signal: <TESTSET> START Format-ioctls
11201 09:33:35.233529 Starting test_set Format-ioctls
11202 09:33:35.236591 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11203 09:33:35.260768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11204 09:33:35.261046 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11206 09:33:35.263822 test VIDIOC_G/S_PARM: OK
11207 09:33:35.282978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11208 09:33:35.283234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11210 09:33:35.285663 test VIDIOC_G_FBUF: OK (Not Supported)
11211 09:33:35.309953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11212 09:33:35.310234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11214 09:33:35.312667 test VIDIOC_G_FMT: OK
11215 09:33:35.335341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11216 09:33:35.335595 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11218 09:33:35.337964 test VIDIOC_TRY_FMT: OK
11219 09:33:35.359258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11220 09:33:35.359541 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11222 09:33:35.368861 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11223 09:33:35.372494 test VIDIOC_S_FMT: FAIL
11224 09:33:35.399411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11225 09:33:35.399693 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11227 09:33:35.402671 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11228 09:33:35.424670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11229 09:33:35.424923 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11231 09:33:35.427961 test Cropping: OK
11232 09:33:35.452002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11233 09:33:35.452256 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11235 09:33:35.454688 test Composing: OK (Not Supported)
11236 09:33:35.478533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11237 09:33:35.479283 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11239 09:33:35.481438 test Scaling: OK (Not Supported)
11240 09:33:35.503659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11241 09:33:35.503741
11242 09:33:35.503980 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11244 09:33:35.519513 Codec ioctls:
11245 09:33:35.526888 <LAVA_SIGNAL_TESTSET STOP>
11246 09:33:35.527139 Received signal: <TESTSET> STOP
11247 09:33:35.527208 Closing test_set Format-ioctls
11248 09:33:35.536407 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11249 09:33:35.536662 Received signal: <TESTSET> START Codec-ioctls
11250 09:33:35.536731 Starting test_set Codec-ioctls
11251 09:33:35.539507 test VIDIOC_(TRY_)ENCODER_CMD: OK
11252 09:33:35.561968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11253 09:33:35.562245 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11255 09:33:35.568132 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11256 09:33:35.587517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11257 09:33:35.587834 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11259 09:33:35.594039 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11260 09:33:35.611806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11261 09:33:35.611891
11262 09:33:35.612127 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11264 09:33:35.622323 Buffer ioctls:
11265 09:33:35.639540 <LAVA_SIGNAL_TESTSET STOP>
11266 09:33:35.640088 Received signal: <TESTSET> STOP
11267 09:33:35.640157 Closing test_set Codec-ioctls
11268 09:33:35.654265 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11269 09:33:35.654631 Received signal: <TESTSET> START Buffer-ioctls
11270 09:33:35.654745 Starting test_set Buffer-ioctls
11271 09:33:35.657858 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11272 09:33:35.692525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11273 09:33:35.692665 test VIDIOC_EXPBUF: OK
11274 09:33:35.692907 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11276 09:33:35.712332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11277 09:33:35.712584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11279 09:33:35.715495 test Requests: OK (Not Supported)
11280 09:33:35.739685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11281 09:33:35.740403 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11283 09:33:35.743591
11284 09:33:35.760037 Test input 0:
11285 09:33:35.770088
11286 09:33:35.780587 Streaming ioctls:
11287 09:33:35.788203 <LAVA_SIGNAL_TESTSET STOP>
11288 09:33:35.788447 Received signal: <TESTSET> STOP
11289 09:33:35.788516 Closing test_set Buffer-ioctls
11290 09:33:35.797636 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11291 09:33:35.797887 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11292 09:33:35.797955 Starting test_set Streaming-ioctls_Test-input-0
11293 09:33:35.801041 test read/write: OK (Not Supported)
11294 09:33:35.821774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11295 09:33:35.822029 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11297 09:33:35.828303 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11298 09:33:35.840079 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11299 09:33:35.845535 test blocking wait: FAIL
11300 09:33:35.869706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11301 09:33:35.869961 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11303 09:33:35.876442 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11304 09:33:35.879613 test MMAP (select): FAIL
11305 09:33:35.904798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11306 09:33:35.905186 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11308 09:33:35.911292 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11309 09:33:35.915910 test MMAP (epoll): FAIL
11310 09:33:35.947346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11311 09:33:35.947680 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11313 09:33:35.954115 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11314 09:33:35.964216 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11315 09:33:35.970269 test USERPTR (select): FAIL
11316 09:33:35.995762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11317 09:33:35.996025 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11319 09:33:36.002198 test DMABUF: Cannot test, specify --expbuf-device
11320 09:33:36.006868
11321 09:33:36.028512 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11322 09:33:36.031692 <LAVA_TEST_RUNNER EXIT>
11323 09:33:36.031950 ok: lava_test_shell seems to have completed
11324 09:33:36.032025 Marking unfinished test run as failed
11326 09:33:36.032901 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11327 09:33:36.033024 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11328 09:33:36.033111 end: 3 lava-test-retry (duration 00:00:03) [common]
11329 09:33:36.033194 start: 4 finalize (timeout 00:08:09) [common]
11330 09:33:36.033284 start: 4.1 power-off (timeout 00:00:30) [common]
11331 09:33:36.033438 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11332 09:33:36.111118 >> Command sent successfully.
11333 09:33:36.113599 Returned 0 in 0 seconds
11334 09:33:36.214014 end: 4.1 power-off (duration 00:00:00) [common]
11336 09:33:36.214352 start: 4.2 read-feedback (timeout 00:08:09) [common]
11337 09:33:36.214623 Listened to connection for namespace 'common' for up to 1s
11338 09:33:37.215552 Finalising connection for namespace 'common'
11339 09:33:37.215784 Disconnecting from shell: Finalise
11340 09:33:37.215880 / #
11341 09:33:37.316241 end: 4.2 read-feedback (duration 00:00:01) [common]
11342 09:33:37.316438 end: 4 finalize (duration 00:00:01) [common]
11343 09:33:37.316581 Cleaning after the job
11344 09:33:37.316722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/ramdisk
11345 09:33:37.322046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/kernel
11346 09:33:37.330251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/dtb
11347 09:33:37.330434 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826815/tftp-deploy-k85cv_7w/modules
11348 09:33:37.337445 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826815
11349 09:33:37.405431 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826815
11350 09:33:37.405614 Job finished correctly