Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 19
- Kernel Errors: 27
- Errors: 1
- Boot result: PASS
1 09:26:54.877375 lava-dispatcher, installed at version: 2023.08
2 09:26:54.877571 start: 0 validate
3 09:26:54.877695 Start time: 2023-10-20 09:26:54.877688+00:00 (UTC)
4 09:26:54.877815 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:26:54.877945 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:26:55.146359 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:26:55.147164 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:27:22.907164 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:27:22.907336 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:23.174785 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:23.175536 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:27:26.447748 validate duration: 31.57
14 09:27:26.448028 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:27:26.448127 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:27:26.448216 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:27:26.448341 Not decompressing ramdisk as can be used compressed.
18 09:27:26.448430 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 09:27:26.448498 saving as /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/ramdisk/rootfs.cpio.gz
20 09:27:26.448565 total size: 8181372 (7 MB)
21 09:27:26.713732 progress 0 % (0 MB)
22 09:27:26.716107 progress 5 % (0 MB)
23 09:27:26.718259 progress 10 % (0 MB)
24 09:27:26.720487 progress 15 % (1 MB)
25 09:27:26.722610 progress 20 % (1 MB)
26 09:27:26.724864 progress 25 % (1 MB)
27 09:27:26.727003 progress 30 % (2 MB)
28 09:27:26.729309 progress 35 % (2 MB)
29 09:27:26.731447 progress 40 % (3 MB)
30 09:27:26.733748 progress 45 % (3 MB)
31 09:27:26.735780 progress 50 % (3 MB)
32 09:27:26.737998 progress 55 % (4 MB)
33 09:27:26.740077 progress 60 % (4 MB)
34 09:27:26.742309 progress 65 % (5 MB)
35 09:27:26.744329 progress 70 % (5 MB)
36 09:27:26.746532 progress 75 % (5 MB)
37 09:27:26.748549 progress 80 % (6 MB)
38 09:27:26.750760 progress 85 % (6 MB)
39 09:27:26.752827 progress 90 % (7 MB)
40 09:27:26.755029 progress 95 % (7 MB)
41 09:27:26.757098 progress 100 % (7 MB)
42 09:27:26.757293 7 MB downloaded in 0.31 s (25.27 MB/s)
43 09:27:26.757454 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:27:26.757693 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:27:26.757782 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:27:26.757867 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:27:26.758002 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:27:26.758071 saving as /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/kernel/Image
50 09:27:26.758136 total size: 49236480 (46 MB)
51 09:27:26.758198 No compression specified
52 09:27:26.759293 progress 0 % (0 MB)
53 09:27:26.771848 progress 5 % (2 MB)
54 09:27:26.784503 progress 10 % (4 MB)
55 09:27:26.797237 progress 15 % (7 MB)
56 09:27:26.809878 progress 20 % (9 MB)
57 09:27:26.822546 progress 25 % (11 MB)
58 09:27:26.835085 progress 30 % (14 MB)
59 09:27:26.847704 progress 35 % (16 MB)
60 09:27:26.860376 progress 40 % (18 MB)
61 09:27:26.872872 progress 45 % (21 MB)
62 09:27:26.885462 progress 50 % (23 MB)
63 09:27:26.898143 progress 55 % (25 MB)
64 09:27:26.910767 progress 60 % (28 MB)
65 09:27:26.923380 progress 65 % (30 MB)
66 09:27:26.935919 progress 70 % (32 MB)
67 09:27:26.948402 progress 75 % (35 MB)
68 09:27:26.961084 progress 80 % (37 MB)
69 09:27:26.973587 progress 85 % (39 MB)
70 09:27:26.986079 progress 90 % (42 MB)
71 09:27:26.998629 progress 95 % (44 MB)
72 09:27:27.011014 progress 100 % (46 MB)
73 09:27:27.011250 46 MB downloaded in 0.25 s (185.51 MB/s)
74 09:27:27.011409 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:27:27.011649 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:27:27.011739 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:27:27.011833 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:27:27.011977 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:27:27.012050 saving as /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/dtb/mt8192-asurada-spherion-r0.dtb
81 09:27:27.012114 total size: 47278 (0 MB)
82 09:27:27.012178 No compression specified
83 09:27:27.013365 progress 69 % (0 MB)
84 09:27:27.013642 progress 100 % (0 MB)
85 09:27:27.013800 0 MB downloaded in 0.00 s (26.77 MB/s)
86 09:27:27.013926 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:27:27.014153 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:27:27.014240 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:27:27.014326 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:27:27.014442 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:27:27.014511 saving as /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/modules/modules.tar
93 09:27:27.014573 total size: 8614716 (8 MB)
94 09:27:27.014636 Using unxz to decompress xz
95 09:27:27.018092 progress 0 % (0 MB)
96 09:27:27.039254 progress 5 % (0 MB)
97 09:27:27.062489 progress 10 % (0 MB)
98 09:27:27.085795 progress 15 % (1 MB)
99 09:27:27.109513 progress 20 % (1 MB)
100 09:27:27.133194 progress 25 % (2 MB)
101 09:27:27.158617 progress 30 % (2 MB)
102 09:27:27.184534 progress 35 % (2 MB)
103 09:27:27.207919 progress 40 % (3 MB)
104 09:27:27.231750 progress 45 % (3 MB)
105 09:27:27.256769 progress 50 % (4 MB)
106 09:27:27.280882 progress 55 % (4 MB)
107 09:27:27.305587 progress 60 % (4 MB)
108 09:27:27.330892 progress 65 % (5 MB)
109 09:27:27.357612 progress 70 % (5 MB)
110 09:27:27.380954 progress 75 % (6 MB)
111 09:27:27.407618 progress 80 % (6 MB)
112 09:27:27.432962 progress 85 % (7 MB)
113 09:27:27.457674 progress 90 % (7 MB)
114 09:27:27.486893 progress 95 % (7 MB)
115 09:27:27.514458 progress 100 % (8 MB)
116 09:27:27.520719 8 MB downloaded in 0.51 s (16.23 MB/s)
117 09:27:27.521017 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:27:27.521415 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:27:27.521513 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:27:27.521612 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:27:27.521697 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:27:27.521785 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:27:27.522005 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg
125 09:27:27.522136 makedir: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin
126 09:27:27.522244 makedir: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/tests
127 09:27:27.522342 makedir: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/results
128 09:27:27.522459 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-add-keys
129 09:27:27.522601 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-add-sources
130 09:27:27.522731 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-background-process-start
131 09:27:27.522859 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-background-process-stop
132 09:27:27.522983 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-common-functions
133 09:27:27.523107 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-echo-ipv4
134 09:27:27.523231 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-install-packages
135 09:27:27.523352 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-installed-packages
136 09:27:27.523473 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-os-build
137 09:27:27.523595 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-probe-channel
138 09:27:27.523716 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-probe-ip
139 09:27:27.523837 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-target-ip
140 09:27:27.523964 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-target-mac
141 09:27:27.524085 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-target-storage
142 09:27:27.524212 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-case
143 09:27:27.524335 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-event
144 09:27:27.524458 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-feedback
145 09:27:27.524579 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-raise
146 09:27:27.524702 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-reference
147 09:27:27.524825 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-runner
148 09:27:27.524953 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-set
149 09:27:27.525077 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-test-shell
150 09:27:27.525204 Updating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-install-packages (oe)
151 09:27:27.525351 Updating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/bin/lava-installed-packages (oe)
152 09:27:27.525472 Creating /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/environment
153 09:27:27.525571 LAVA metadata
154 09:27:27.525646 - LAVA_JOB_ID=11826788
155 09:27:27.525711 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:27:27.525815 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:27:27.525884 skipped lava-vland-overlay
158 09:27:27.525960 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:27:27.526042 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:27:27.526108 skipped lava-multinode-overlay
161 09:27:27.526182 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:27:27.526265 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:27:27.526340 Loading test definitions
164 09:27:27.526436 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:27:27.526514 Using /lava-11826788 at stage 0
166 09:27:27.526826 uuid=11826788_1.5.2.3.1 testdef=None
167 09:27:27.526928 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:27:27.527016 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:27:27.527541 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:27:27.527769 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:27:27.528411 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:27:27.528649 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:27:27.529321 runner path: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/0/tests/0_dmesg test_uuid 11826788_1.5.2.3.1
176 09:27:27.529475 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:27:27.529703 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 09:27:27.529777 Using /lava-11826788 at stage 1
180 09:27:27.530064 uuid=11826788_1.5.2.3.5 testdef=None
181 09:27:27.530155 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 09:27:27.530241 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 09:27:27.530712 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 09:27:27.530944 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 09:27:27.532045 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 09:27:27.532281 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 09:27:27.532938 runner path: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/1/tests/1_bootrr test_uuid 11826788_1.5.2.3.5
190 09:27:27.533155 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 09:27:27.533368 Creating lava-test-runner.conf files
193 09:27:27.533434 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/0 for stage 0
194 09:27:27.533524 - 0_dmesg
195 09:27:27.533605 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826788/lava-overlay-vtwgwweg/lava-11826788/1 for stage 1
196 09:27:27.533695 - 1_bootrr
197 09:27:27.533790 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 09:27:27.533879 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 09:27:27.541774 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 09:27:27.541886 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 09:27:27.541975 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 09:27:27.542064 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 09:27:27.542156 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 09:27:27.774087 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 09:27:27.774444 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 09:27:27.774561 extracting modules file /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826788/extract-overlay-ramdisk-n9ak02ld/ramdisk
207 09:27:27.979779 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 09:27:27.979957 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 09:27:27.980056 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826788/compress-overlay-a339j8yo/overlay-1.5.2.4.tar.gz to ramdisk
210 09:27:27.980128 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826788/compress-overlay-a339j8yo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826788/extract-overlay-ramdisk-n9ak02ld/ramdisk
211 09:27:27.988081 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 09:27:27.988203 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 09:27:27.988292 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 09:27:27.988378 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 09:27:27.988458 Building ramdisk /var/lib/lava/dispatcher/tmp/11826788/extract-overlay-ramdisk-n9ak02ld/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826788/extract-overlay-ramdisk-n9ak02ld/ramdisk
216 09:27:28.358919 >> 145280 blocks
217 09:27:30.611052 rename /var/lib/lava/dispatcher/tmp/11826788/extract-overlay-ramdisk-n9ak02ld/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/ramdisk/ramdisk.cpio.gz
218 09:27:30.611465 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 09:27:30.611593 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 09:27:30.611693 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 09:27:30.611805 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/kernel/Image'
222 09:27:42.937365 Returned 0 in 12 seconds
223 09:27:43.037961 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/kernel/image.itb
224 09:27:43.415124 output: FIT description: Kernel Image image with one or more FDT blobs
225 09:27:43.415479 output: Created: Fri Oct 20 10:27:43 2023
226 09:27:43.415556 output: Image 0 (kernel-1)
227 09:27:43.415623 output: Description:
228 09:27:43.415686 output: Created: Fri Oct 20 10:27:43 2023
229 09:27:43.415748 output: Type: Kernel Image
230 09:27:43.415812 output: Compression: lzma compressed
231 09:27:43.415871 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
232 09:27:43.415930 output: Architecture: AArch64
233 09:27:43.415991 output: OS: Linux
234 09:27:43.416049 output: Load Address: 0x00000000
235 09:27:43.416107 output: Entry Point: 0x00000000
236 09:27:43.416165 output: Hash algo: crc32
237 09:27:43.416228 output: Hash value: 05d3904e
238 09:27:43.416287 output: Image 1 (fdt-1)
239 09:27:43.416350 output: Description: mt8192-asurada-spherion-r0
240 09:27:43.416405 output: Created: Fri Oct 20 10:27:43 2023
241 09:27:43.416460 output: Type: Flat Device Tree
242 09:27:43.416515 output: Compression: uncompressed
243 09:27:43.416569 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 09:27:43.416624 output: Architecture: AArch64
245 09:27:43.416678 output: Hash algo: crc32
246 09:27:43.416732 output: Hash value: cc4352de
247 09:27:43.416786 output: Image 2 (ramdisk-1)
248 09:27:43.416839 output: Description: unavailable
249 09:27:43.416893 output: Created: Fri Oct 20 10:27:43 2023
250 09:27:43.416976 output: Type: RAMDisk Image
251 09:27:43.417044 output: Compression: Unknown Compression
252 09:27:43.417099 output: Data Size: 21392073 Bytes = 20890.70 KiB = 20.40 MiB
253 09:27:43.417154 output: Architecture: AArch64
254 09:27:43.417208 output: OS: Linux
255 09:27:43.417262 output: Load Address: unavailable
256 09:27:43.417316 output: Entry Point: unavailable
257 09:27:43.417370 output: Hash algo: crc32
258 09:27:43.417424 output: Hash value: 96227f46
259 09:27:43.417478 output: Default Configuration: 'conf-1'
260 09:27:43.417532 output: Configuration 0 (conf-1)
261 09:27:43.417586 output: Description: mt8192-asurada-spherion-r0
262 09:27:43.417640 output: Kernel: kernel-1
263 09:27:43.417694 output: Init Ramdisk: ramdisk-1
264 09:27:43.417748 output: FDT: fdt-1
265 09:27:43.417801 output: Loadables: kernel-1
266 09:27:43.417855 output:
267 09:27:43.418042 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 09:27:43.418141 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 09:27:43.418246 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 09:27:43.418343 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 09:27:43.418418 No LXC device requested
272 09:27:43.418498 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 09:27:43.418584 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 09:27:43.418662 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 09:27:43.418731 Checking files for TFTP limit of 4294967296 bytes.
276 09:27:43.419221 end: 1 tftp-deploy (duration 00:00:17) [common]
277 09:27:43.419324 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 09:27:43.419419 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 09:27:43.419540 substitutions:
280 09:27:43.419608 - {DTB}: 11826788/tftp-deploy-zdaz8vpz/dtb/mt8192-asurada-spherion-r0.dtb
281 09:27:43.419674 - {INITRD}: 11826788/tftp-deploy-zdaz8vpz/ramdisk/ramdisk.cpio.gz
282 09:27:43.419735 - {KERNEL}: 11826788/tftp-deploy-zdaz8vpz/kernel/Image
283 09:27:43.419794 - {LAVA_MAC}: None
284 09:27:43.419852 - {PRESEED_CONFIG}: None
285 09:27:43.419910 - {PRESEED_LOCAL}: None
286 09:27:43.419967 - {RAMDISK}: 11826788/tftp-deploy-zdaz8vpz/ramdisk/ramdisk.cpio.gz
287 09:27:43.420023 - {ROOT_PART}: None
288 09:27:43.420078 - {ROOT}: None
289 09:27:43.420134 - {SERVER_IP}: 192.168.201.1
290 09:27:43.420189 - {TEE}: None
291 09:27:43.420244 Parsed boot commands:
292 09:27:43.420299 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 09:27:43.420473 Parsed boot commands: tftpboot 192.168.201.1 11826788/tftp-deploy-zdaz8vpz/kernel/image.itb 11826788/tftp-deploy-zdaz8vpz/kernel/cmdline
294 09:27:43.420565 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 09:27:43.420653 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 09:27:43.420749 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 09:27:43.420839 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 09:27:43.420910 Not connected, no need to disconnect.
299 09:27:43.421037 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 09:27:43.421119 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 09:27:43.421189 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
302 09:27:43.424444 Setting prompt string to ['lava-test: # ']
303 09:27:43.424783 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 09:27:43.424888 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 09:27:43.425014 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 09:27:43.425284 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 09:27:43.425484 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 09:27:48.557658 >> Command sent successfully.
309 09:27:48.560173 Returned 0 in 5 seconds
310 09:27:48.660642 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 09:27:48.661000 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 09:27:48.661121 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 09:27:48.661209 Setting prompt string to 'Starting depthcharge on Spherion...'
315 09:27:48.661278 Changing prompt to 'Starting depthcharge on Spherion...'
316 09:27:48.661347 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 09:27:48.661605 [Enter `^Ec?' for help]
318 09:27:48.833783
319 09:27:48.833943
320 09:27:48.834017 F0: 102B 0000
321 09:27:48.834085
322 09:27:48.834149 F3: 1001 0000 [0200]
323 09:27:48.834209
324 09:27:48.837259 F3: 1001 0000
325 09:27:48.837360
326 09:27:48.837440 F7: 102D 0000
327 09:27:48.837503
328 09:27:48.837562 F1: 0000 0000
329 09:27:48.841144
330 09:27:48.841226 V0: 0000 0000 [0001]
331 09:27:48.841293
332 09:27:48.841371 00: 0007 8000
333 09:27:48.841533
334 09:27:48.844856 01: 0000 0000
335 09:27:48.844961
336 09:27:48.845045 BP: 0C00 0209 [0000]
337 09:27:48.845137
338 09:27:48.848215 G0: 1182 0000
339 09:27:48.848297
340 09:27:48.848363 EC: 0000 0021 [4000]
341 09:27:48.848424
342 09:27:48.852211 S7: 0000 0000 [0000]
343 09:27:48.852294
344 09:27:48.852360 CC: 0000 0000 [0001]
345 09:27:48.852421
346 09:27:48.855424 T0: 0000 0040 [010F]
347 09:27:48.855523
348 09:27:48.855653 Jump to BL
349 09:27:48.855720
350 09:27:48.880251
351 09:27:48.880364
352 09:27:48.880459
353 09:27:48.887458 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 09:27:48.891393 ARM64: Exception handlers installed.
355 09:27:48.895197 ARM64: Testing exception
356 09:27:48.899307 ARM64: Done test exception
357 09:27:48.906278 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 09:27:48.913138 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 09:27:48.920283 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 09:27:48.931295 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 09:27:48.937746 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 09:27:48.947952 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 09:27:48.958564 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 09:27:48.964976 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 09:27:48.983269 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 09:27:48.986638 WDT: Last reset was cold boot
367 09:27:48.989645 SPI1(PAD0) initialized at 2873684 Hz
368 09:27:48.993368 SPI5(PAD0) initialized at 992727 Hz
369 09:27:48.996470 VBOOT: Loading verstage.
370 09:27:49.003185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 09:27:49.006911 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 09:27:49.009814 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 09:27:49.013671 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 09:27:49.020831 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 09:27:49.027398 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 09:27:49.038015 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 09:27:49.038148
378 09:27:49.038218
379 09:27:49.048349 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 09:27:49.051565 ARM64: Exception handlers installed.
381 09:27:49.054947 ARM64: Testing exception
382 09:27:49.055037 ARM64: Done test exception
383 09:27:49.061610 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 09:27:49.065253 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 09:27:49.078970 Probing TPM: . done!
386 09:27:49.079070 TPM ready after 0 ms
387 09:27:49.085749 Connected to device vid:did:rid of 1ae0:0028:00
388 09:27:49.093577 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 09:27:49.151158 Initialized TPM device CR50 revision 0
390 09:27:49.163213 tlcl_send_startup: Startup return code is 0
391 09:27:49.163311 TPM: setup succeeded
392 09:27:49.174468 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 09:27:49.183344 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 09:27:49.193677 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 09:27:49.202689 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 09:27:49.206555 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 09:27:49.213712 in-header: 03 07 00 00 08 00 00 00
398 09:27:49.217629 in-data: aa e4 47 04 13 02 00 00
399 09:27:49.220904 Chrome EC: UHEPI supported
400 09:27:49.227856 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 09:27:49.232132 in-header: 03 ad 00 00 08 00 00 00
402 09:27:49.235759 in-data: 00 20 20 08 00 00 00 00
403 09:27:49.235904 Phase 1
404 09:27:49.239335 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 09:27:49.246639 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 09:27:49.250563 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 09:27:49.254097 Recovery requested (1009000e)
408 09:27:49.262564 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 09:27:49.268192 tlcl_extend: response is 0
410 09:27:49.277621 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 09:27:49.283221 tlcl_extend: response is 0
412 09:27:49.290683 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 09:27:49.310780 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 09:27:49.317952 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 09:27:49.318041
416 09:27:49.318107
417 09:27:49.328589 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 09:27:49.331337 ARM64: Exception handlers installed.
419 09:27:49.331422 ARM64: Testing exception
420 09:27:49.334917 ARM64: Done test exception
421 09:27:49.356070 pmic_efuse_setting: Set efuses in 11 msecs
422 09:27:49.359623 pmwrap_interface_init: Select PMIF_VLD_RDY
423 09:27:49.366144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 09:27:49.369744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 09:27:49.373093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 09:27:49.379973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 09:27:49.383597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 09:27:49.390748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 09:27:49.394747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 09:27:49.398420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 09:27:49.401981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 09:27:49.409466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 09:27:49.413251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 09:27:49.416539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 09:27:49.419788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 09:27:49.427528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 09:27:49.434319 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 09:27:49.441561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 09:27:49.445039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 09:27:49.452378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 09:27:49.455836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 09:27:49.462404 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 09:27:49.466200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 09:27:49.473025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 09:27:49.479923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 09:27:49.483143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 09:27:49.489785 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 09:27:49.496916 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 09:27:49.500019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 09:27:49.506582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 09:27:49.510199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 09:27:49.513245 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 09:27:49.519745 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 09:27:49.523334 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 09:27:49.530037 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 09:27:49.533352 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 09:27:49.539818 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 09:27:49.543594 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 09:27:49.550080 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 09:27:49.553418 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 09:27:49.559967 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 09:27:49.563390 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 09:27:49.566909 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 09:27:49.573464 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 09:27:49.576605 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 09:27:49.580934 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 09:27:49.584703 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 09:27:49.591010 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 09:27:49.594497 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 09:27:49.597696 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 09:27:49.601201 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 09:27:49.607902 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 09:27:49.611159 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 09:27:49.617824 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 09:27:49.627902 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 09:27:49.631499 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 09:27:49.641437 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 09:27:49.648393 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 09:27:49.651620 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 09:27:49.658223 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 09:27:49.661463 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 09:27:49.668364 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x32
483 09:27:49.675107 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 09:27:49.678501 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 09:27:49.681740 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 09:27:49.693197 [RTC]rtc_get_frequency_meter,154: input=15, output=772
487 09:27:49.702842 [RTC]rtc_get_frequency_meter,154: input=23, output=958
488 09:27:49.711860 [RTC]rtc_get_frequency_meter,154: input=19, output=865
489 09:27:49.721788 [RTC]rtc_get_frequency_meter,154: input=17, output=819
490 09:27:49.731262 [RTC]rtc_get_frequency_meter,154: input=16, output=796
491 09:27:49.734307 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 09:27:49.741292 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 09:27:49.744422 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
494 09:27:49.748265 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 09:27:49.751303 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
496 09:27:49.754336 ADC[4]: Raw value=902876 ID=7
497 09:27:49.758477 ADC[3]: Raw value=213179 ID=1
498 09:27:49.758562 RAM Code: 0x71
499 09:27:49.764439 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 09:27:49.768269 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 09:27:49.778101 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 09:27:49.784701 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 09:27:49.788368 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 09:27:49.791445 in-header: 03 07 00 00 08 00 00 00
505 09:27:49.794958 in-data: aa e4 47 04 13 02 00 00
506 09:27:49.797889 Chrome EC: UHEPI supported
507 09:27:49.804629 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 09:27:49.808859 in-header: 03 ed 00 00 08 00 00 00
509 09:27:49.811469 in-data: 80 20 60 08 00 00 00 00
510 09:27:49.814595 MRC: failed to locate region type 0.
511 09:27:49.821282 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 09:27:49.821459 DRAM-K: Running full calibration
513 09:27:49.828245 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 09:27:49.831558 header.status = 0x0
515 09:27:49.835076 header.version = 0x6 (expected: 0x6)
516 09:27:49.838258 header.size = 0xd00 (expected: 0xd00)
517 09:27:49.838342 header.flags = 0x0
518 09:27:49.844840 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 09:27:49.863344 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
520 09:27:49.870172 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 09:27:49.873540 dram_init: ddr_geometry: 2
522 09:27:49.876564 [EMI] MDL number = 2
523 09:27:49.876648 [EMI] Get MDL freq = 0
524 09:27:49.880115 dram_init: ddr_type: 0
525 09:27:49.880197 is_discrete_lpddr4: 1
526 09:27:49.883617 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 09:27:49.883700
528 09:27:49.883766
529 09:27:49.886612 [Bian_co] ETT version 0.0.0.1
530 09:27:49.893269 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 09:27:49.893353
532 09:27:49.896699 dramc_set_vcore_voltage set vcore to 650000
533 09:27:49.896782 Read voltage for 800, 4
534 09:27:49.899966 Vio18 = 0
535 09:27:49.900048 Vcore = 650000
536 09:27:49.900114 Vdram = 0
537 09:27:49.903233 Vddq = 0
538 09:27:49.903315 Vmddr = 0
539 09:27:49.907091 dram_init: config_dvfs: 1
540 09:27:49.910552 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 09:27:49.917556 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 09:27:49.921555 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
543 09:27:49.924919 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
544 09:27:49.928450 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 09:27:49.932291 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 09:27:49.932375 MEM_TYPE=3, freq_sel=18
547 09:27:49.935830 sv_algorithm_assistance_LP4_1600
548 09:27:49.939150 ============ PULL DRAM RESETB DOWN ============
549 09:27:49.946527 ========== PULL DRAM RESETB DOWN end =========
550 09:27:49.950519 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 09:27:49.954485 ===================================
552 09:27:49.954569 LPDDR4 DRAM CONFIGURATION
553 09:27:49.957771 ===================================
554 09:27:49.961793 EX_ROW_EN[0] = 0x0
555 09:27:49.961876 EX_ROW_EN[1] = 0x0
556 09:27:49.965294 LP4Y_EN = 0x0
557 09:27:49.965415 WORK_FSP = 0x0
558 09:27:49.969492 WL = 0x2
559 09:27:49.969576 RL = 0x2
560 09:27:49.972838 BL = 0x2
561 09:27:49.972978 RPST = 0x0
562 09:27:49.973087 RD_PRE = 0x0
563 09:27:49.976290 WR_PRE = 0x1
564 09:27:49.976373 WR_PST = 0x0
565 09:27:49.979605 DBI_WR = 0x0
566 09:27:49.982910 DBI_RD = 0x0
567 09:27:49.982992 OTF = 0x1
568 09:27:49.986608 ===================================
569 09:27:49.989797 ===================================
570 09:27:49.989880 ANA top config
571 09:27:49.992913 ===================================
572 09:27:49.996312 DLL_ASYNC_EN = 0
573 09:27:49.999710 ALL_SLAVE_EN = 1
574 09:27:50.003013 NEW_RANK_MODE = 1
575 09:27:50.003098 DLL_IDLE_MODE = 1
576 09:27:50.006499 LP45_APHY_COMB_EN = 1
577 09:27:50.009559 TX_ODT_DIS = 1
578 09:27:50.012917 NEW_8X_MODE = 1
579 09:27:50.016465 ===================================
580 09:27:50.019628 ===================================
581 09:27:50.023331 data_rate = 1600
582 09:27:50.026469 CKR = 1
583 09:27:50.026553 DQ_P2S_RATIO = 8
584 09:27:50.029697 ===================================
585 09:27:50.033632 CA_P2S_RATIO = 8
586 09:27:50.037117 DQ_CA_OPEN = 0
587 09:27:50.040819 DQ_SEMI_OPEN = 0
588 09:27:50.040937 CA_SEMI_OPEN = 0
589 09:27:50.044825 CA_FULL_RATE = 0
590 09:27:50.048241 DQ_CKDIV4_EN = 1
591 09:27:50.051947 CA_CKDIV4_EN = 1
592 09:27:50.052036 CA_PREDIV_EN = 0
593 09:27:50.055502 PH8_DLY = 0
594 09:27:50.058446 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 09:27:50.061729 DQ_AAMCK_DIV = 4
596 09:27:50.065521 CA_AAMCK_DIV = 4
597 09:27:50.065605 CA_ADMCK_DIV = 4
598 09:27:50.068444 DQ_TRACK_CA_EN = 0
599 09:27:50.071904 CA_PICK = 800
600 09:27:50.075447 CA_MCKIO = 800
601 09:27:50.078505 MCKIO_SEMI = 0
602 09:27:50.082656 PLL_FREQ = 3068
603 09:27:50.085655 DQ_UI_PI_RATIO = 32
604 09:27:50.085738 CA_UI_PI_RATIO = 0
605 09:27:50.088742 ===================================
606 09:27:50.092141 ===================================
607 09:27:50.095419 memory_type:LPDDR4
608 09:27:50.098968 GP_NUM : 10
609 09:27:50.099053 SRAM_EN : 1
610 09:27:50.102151 MD32_EN : 0
611 09:27:50.105610 ===================================
612 09:27:50.105694 [ANA_INIT] >>>>>>>>>>>>>>
613 09:27:50.109142 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 09:27:50.112912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 09:27:50.117287 ===================================
616 09:27:50.120424 data_rate = 1600,PCW = 0X7600
617 09:27:50.124852 ===================================
618 09:27:50.128017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 09:27:50.132053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 09:27:50.139004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 09:27:50.142820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 09:27:50.146396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 09:27:50.149399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 09:27:50.149486 [ANA_INIT] flow start
625 09:27:50.152903 [ANA_INIT] PLL >>>>>>>>
626 09:27:50.156213 [ANA_INIT] PLL <<<<<<<<
627 09:27:50.156300 [ANA_INIT] MIDPI >>>>>>>>
628 09:27:50.159733 [ANA_INIT] MIDPI <<<<<<<<
629 09:27:50.162836 [ANA_INIT] DLL >>>>>>>>
630 09:27:50.162922 [ANA_INIT] flow end
631 09:27:50.170073 ============ LP4 DIFF to SE enter ============
632 09:27:50.172959 ============ LP4 DIFF to SE exit ============
633 09:27:50.176514 [ANA_INIT] <<<<<<<<<<<<<
634 09:27:50.179492 [Flow] Enable top DCM control >>>>>
635 09:27:50.183049 [Flow] Enable top DCM control <<<<<
636 09:27:50.183137 Enable DLL master slave shuffle
637 09:27:50.189986 ==============================================================
638 09:27:50.193157 Gating Mode config
639 09:27:50.196337 ==============================================================
640 09:27:50.199983 Config description:
641 09:27:50.209886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 09:27:50.216594 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 09:27:50.220294 SELPH_MODE 0: By rank 1: By Phase
644 09:27:50.226396 ==============================================================
645 09:27:50.229843 GAT_TRACK_EN = 1
646 09:27:50.233159 RX_GATING_MODE = 2
647 09:27:50.233246 RX_GATING_TRACK_MODE = 2
648 09:27:50.236876 SELPH_MODE = 1
649 09:27:50.239909 PICG_EARLY_EN = 1
650 09:27:50.243450 VALID_LAT_VALUE = 1
651 09:27:50.249959 ==============================================================
652 09:27:50.253272 Enter into Gating configuration >>>>
653 09:27:50.256610 Exit from Gating configuration <<<<
654 09:27:50.259865 Enter into DVFS_PRE_config >>>>>
655 09:27:50.270266 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 09:27:50.273352 Exit from DVFS_PRE_config <<<<<
657 09:27:50.276839 Enter into PICG configuration >>>>
658 09:27:50.280161 Exit from PICG configuration <<<<
659 09:27:50.283644 [RX_INPUT] configuration >>>>>
660 09:27:50.286711 [RX_INPUT] configuration <<<<<
661 09:27:50.289895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 09:27:50.296864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 09:27:50.300326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 09:27:50.307612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 09:27:50.314813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 09:27:50.321499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 09:27:50.324892 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 09:27:50.328566 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 09:27:50.332158 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 09:27:50.335733 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 09:27:50.339515 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 09:27:50.346761 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 09:27:50.350452 ===================================
674 09:27:50.350538 LPDDR4 DRAM CONFIGURATION
675 09:27:50.353826 ===================================
676 09:27:50.357976 EX_ROW_EN[0] = 0x0
677 09:27:50.358059 EX_ROW_EN[1] = 0x0
678 09:27:50.361221 LP4Y_EN = 0x0
679 09:27:50.361305 WORK_FSP = 0x0
680 09:27:50.365442 WL = 0x2
681 09:27:50.365526 RL = 0x2
682 09:27:50.368844 BL = 0x2
683 09:27:50.368936 RPST = 0x0
684 09:27:50.369050 RD_PRE = 0x0
685 09:27:50.372515 WR_PRE = 0x1
686 09:27:50.372599 WR_PST = 0x0
687 09:27:50.376391 DBI_WR = 0x0
688 09:27:50.376475 DBI_RD = 0x0
689 09:27:50.379825 OTF = 0x1
690 09:27:50.383425 ===================================
691 09:27:50.386925 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 09:27:50.390776 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 09:27:50.394605 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 09:27:50.398375 ===================================
695 09:27:50.402347 LPDDR4 DRAM CONFIGURATION
696 09:27:50.406170 ===================================
697 09:27:50.406256 EX_ROW_EN[0] = 0x10
698 09:27:50.409665 EX_ROW_EN[1] = 0x0
699 09:27:50.409769 LP4Y_EN = 0x0
700 09:27:50.409862 WORK_FSP = 0x0
701 09:27:50.413519 WL = 0x2
702 09:27:50.413599 RL = 0x2
703 09:27:50.417608 BL = 0x2
704 09:27:50.417693 RPST = 0x0
705 09:27:50.421173 RD_PRE = 0x0
706 09:27:50.421259 WR_PRE = 0x1
707 09:27:50.424650 WR_PST = 0x0
708 09:27:50.424752 DBI_WR = 0x0
709 09:27:50.428702 DBI_RD = 0x0
710 09:27:50.428788 OTF = 0x1
711 09:27:50.432290 ===================================
712 09:27:50.439347 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 09:27:50.443489 nWR fixed to 40
714 09:27:50.443579 [ModeRegInit_LP4] CH0 RK0
715 09:27:50.446637 [ModeRegInit_LP4] CH0 RK1
716 09:27:50.450434 [ModeRegInit_LP4] CH1 RK0
717 09:27:50.450520 [ModeRegInit_LP4] CH1 RK1
718 09:27:50.454683 match AC timing 13
719 09:27:50.458289 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 09:27:50.462235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 09:27:50.465740 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 09:27:50.469365 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 09:27:50.476991 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 09:27:50.477244 [EMI DOE] emi_dcm 0
725 09:27:50.480587 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 09:27:50.480835 ==
727 09:27:50.484016 Dram Type= 6, Freq= 0, CH_0, rank 0
728 09:27:50.487807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 09:27:50.488056 ==
730 09:27:50.495486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 09:27:50.499104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 09:27:50.510021 [CA 0] Center 38 (7~69) winsize 63
733 09:27:50.513785 [CA 1] Center 38 (7~69) winsize 63
734 09:27:50.516891 [CA 2] Center 35 (5~66) winsize 62
735 09:27:50.520815 [CA 3] Center 35 (5~66) winsize 62
736 09:27:50.524684 [CA 4] Center 34 (4~65) winsize 62
737 09:27:50.528710 [CA 5] Center 34 (4~64) winsize 61
738 09:27:50.529162
739 09:27:50.531831 [CmdBusTrainingLP45] Vref(ca) range 1: 32
740 09:27:50.532308
741 09:27:50.535620 [CATrainingPosCal] consider 1 rank data
742 09:27:50.539523 u2DelayCellTimex100 = 270/100 ps
743 09:27:50.539891 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
744 09:27:50.542941 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
745 09:27:50.546950 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
746 09:27:50.550404 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
747 09:27:50.554266 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
748 09:27:50.558060 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
749 09:27:50.558461
750 09:27:50.561552 CA PerBit enable=1, Macro0, CA PI delay=34
751 09:27:50.561948
752 09:27:50.565317 [CBTSetCACLKResult] CA Dly = 34
753 09:27:50.569395 CS Dly: 5 (0~36)
754 09:27:50.569920 ==
755 09:27:50.572666 Dram Type= 6, Freq= 0, CH_0, rank 1
756 09:27:50.576749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 09:27:50.577190 ==
758 09:27:50.580341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 09:27:50.587553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 09:27:50.596787 [CA 0] Center 38 (7~69) winsize 63
761 09:27:50.600541 [CA 1] Center 38 (8~69) winsize 62
762 09:27:50.604463 [CA 2] Center 35 (5~66) winsize 62
763 09:27:50.608107 [CA 3] Center 35 (5~66) winsize 62
764 09:27:50.611464 [CA 4] Center 35 (5~66) winsize 62
765 09:27:50.611990 [CA 5] Center 34 (4~65) winsize 62
766 09:27:50.612316
767 09:27:50.618295 [CmdBusTrainingLP45] Vref(ca) range 1: 30
768 09:27:50.618577
769 09:27:50.621253 [CATrainingPosCal] consider 2 rank data
770 09:27:50.624502 u2DelayCellTimex100 = 270/100 ps
771 09:27:50.628353 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
772 09:27:50.631299 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
773 09:27:50.634672 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
774 09:27:50.637970 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 09:27:50.641426 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
776 09:27:50.644408 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 09:27:50.644522
778 09:27:50.648280 CA PerBit enable=1, Macro0, CA PI delay=34
779 09:27:50.648382
780 09:27:50.651107 [CBTSetCACLKResult] CA Dly = 34
781 09:27:50.654563 CS Dly: 5 (0~37)
782 09:27:50.654654
783 09:27:50.658079 ----->DramcWriteLeveling(PI) begin...
784 09:27:50.658164 ==
785 09:27:50.661768 Dram Type= 6, Freq= 0, CH_0, rank 0
786 09:27:50.664899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 09:27:50.664989 ==
788 09:27:50.667945 Write leveling (Byte 0): 32 => 32
789 09:27:50.671102 Write leveling (Byte 1): 30 => 30
790 09:27:50.674617 DramcWriteLeveling(PI) end<-----
791 09:27:50.674700
792 09:27:50.674766 ==
793 09:27:50.678070 Dram Type= 6, Freq= 0, CH_0, rank 0
794 09:27:50.681156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 09:27:50.681241 ==
796 09:27:50.684904 [Gating] SW mode calibration
797 09:27:50.692470 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 09:27:50.696175 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 09:27:50.699909 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
800 09:27:50.706823 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
801 09:27:50.710274 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 09:27:50.713773 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:27:50.717318 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:27:50.724355 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:27:50.728095 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:27:50.731650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:27:50.738422 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:27:50.741248 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:27:50.744588 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:27:50.751436 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:27:50.754529 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:27:50.758025 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 09:27:50.761194 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 09:27:50.768205 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 09:27:50.771276 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:27:50.774518 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
817 09:27:50.781994 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
818 09:27:50.785253 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:27:50.788427 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:27:50.794821 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:27:50.798214 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:27:50.801543 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:27:50.808611 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:27:50.812010 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
825 09:27:50.815192 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
826 09:27:50.818431 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
827 09:27:50.824864 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 09:27:50.828204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 09:27:50.831587 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 09:27:50.838573 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 09:27:50.841992 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 09:27:50.845349 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
833 09:27:50.852053 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
834 09:27:50.855177 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
835 09:27:50.858933 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 09:27:50.865211 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 09:27:50.868404 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 09:27:50.871580 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 09:27:50.878619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 09:27:50.882293 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
841 09:27:50.884938 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
842 09:27:50.891927 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
843 09:27:50.895025 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 09:27:50.898420 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 09:27:50.902519 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 09:27:50.908648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 09:27:50.912221 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 09:27:50.915225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
849 09:27:50.921800 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
850 09:27:50.925342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:27:50.928524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 09:27:50.935352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 09:27:50.938714 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 09:27:50.942068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 09:27:50.948608 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 09:27:50.952482 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 09:27:50.955764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 09:27:50.962098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 09:27:50.965644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 09:27:50.968916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 09:27:50.972485 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 09:27:50.979111 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 09:27:50.982194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 09:27:50.985956 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 09:27:50.992320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
866 09:27:50.995884 Total UI for P1: 0, mck2ui 16
867 09:27:50.999141 best dqsien dly found for B0: ( 0, 14, 6)
868 09:27:51.002972 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 09:27:51.005761 Total UI for P1: 0, mck2ui 16
870 09:27:51.008896 best dqsien dly found for B1: ( 0, 14, 8)
871 09:27:51.012780 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
872 09:27:51.016011 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
873 09:27:51.016096
874 09:27:51.018945 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
875 09:27:51.022450 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
876 09:27:51.025831 [Gating] SW calibration Done
877 09:27:51.025929 ==
878 09:27:51.029068 Dram Type= 6, Freq= 0, CH_0, rank 0
879 09:27:51.032518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
880 09:27:51.032602 ==
881 09:27:51.035693 RX Vref Scan: 0
882 09:27:51.035776
883 09:27:51.038965 RX Vref 0 -> 0, step: 1
884 09:27:51.039048
885 09:27:51.039152 RX Delay -130 -> 252, step: 16
886 09:27:51.046386 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
887 09:27:51.049456 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
888 09:27:51.052533 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
889 09:27:51.056220 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
890 09:27:51.059250 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
891 09:27:51.065993 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
892 09:27:51.069476 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
893 09:27:51.072577 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
894 09:27:51.076088 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
895 09:27:51.079309 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
896 09:27:51.085831 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
897 09:27:51.089371 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
898 09:27:51.092723 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
899 09:27:51.096643 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
900 09:27:51.099703 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
901 09:27:51.106218 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
902 09:27:51.106301 ==
903 09:27:51.109355 Dram Type= 6, Freq= 0, CH_0, rank 0
904 09:27:51.112773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 09:27:51.112856 ==
906 09:27:51.112923 DQS Delay:
907 09:27:51.116014 DQS0 = 0, DQS1 = 0
908 09:27:51.116111 DQM Delay:
909 09:27:51.119589 DQM0 = 89, DQM1 = 78
910 09:27:51.119672 DQ Delay:
911 09:27:51.122993 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
912 09:27:51.126483 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
913 09:27:51.129355 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
914 09:27:51.132786 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
915 09:27:51.132870
916 09:27:51.132966
917 09:27:51.133046 ==
918 09:27:51.136502 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:27:51.139653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:27:51.139741 ==
921 09:27:51.143101
922 09:27:51.143183
923 09:27:51.143248 TX Vref Scan disable
924 09:27:51.146258 == TX Byte 0 ==
925 09:27:51.149678 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
926 09:27:51.153146 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
927 09:27:51.156093 == TX Byte 1 ==
928 09:27:51.159714 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
929 09:27:51.163119 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
930 09:27:51.163214 ==
931 09:27:51.166730 Dram Type= 6, Freq= 0, CH_0, rank 0
932 09:27:51.172880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 09:27:51.173019 ==
934 09:27:51.184887 TX Vref=22, minBit 11, minWin=26, winSum=440
935 09:27:51.188305 TX Vref=24, minBit 6, minWin=27, winSum=441
936 09:27:51.191740 TX Vref=26, minBit 8, minWin=27, winSum=447
937 09:27:51.195057 TX Vref=28, minBit 8, minWin=27, winSum=449
938 09:27:51.198172 TX Vref=30, minBit 6, minWin=28, winSum=456
939 09:27:51.201430 TX Vref=32, minBit 3, minWin=28, winSum=455
940 09:27:51.208342 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 30
941 09:27:51.208425
942 09:27:51.211357 Final TX Range 1 Vref 30
943 09:27:51.211440
944 09:27:51.211506 ==
945 09:27:51.215166 Dram Type= 6, Freq= 0, CH_0, rank 0
946 09:27:51.218600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
947 09:27:51.218684 ==
948 09:27:51.218750
949 09:27:51.218811
950 09:27:51.221859 TX Vref Scan disable
951 09:27:51.225189 == TX Byte 0 ==
952 09:27:51.228284 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
953 09:27:51.231656 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
954 09:27:51.235206 == TX Byte 1 ==
955 09:27:51.238265 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
956 09:27:51.241740 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
957 09:27:51.241823
958 09:27:51.245235 [DATLAT]
959 09:27:51.245318 Freq=800, CH0 RK0
960 09:27:51.245385
961 09:27:51.248266 DATLAT Default: 0xa
962 09:27:51.248348 0, 0xFFFF, sum = 0
963 09:27:51.251781 1, 0xFFFF, sum = 0
964 09:27:51.251865 2, 0xFFFF, sum = 0
965 09:27:51.255192 3, 0xFFFF, sum = 0
966 09:27:51.255280 4, 0xFFFF, sum = 0
967 09:27:51.258219 5, 0xFFFF, sum = 0
968 09:27:51.258303 6, 0xFFFF, sum = 0
969 09:27:51.261908 7, 0xFFFF, sum = 0
970 09:27:51.261993 8, 0xFFFF, sum = 0
971 09:27:51.265492 9, 0x0, sum = 1
972 09:27:51.265578 10, 0x0, sum = 2
973 09:27:51.268647 11, 0x0, sum = 3
974 09:27:51.268732 12, 0x0, sum = 4
975 09:27:51.271751 best_step = 10
976 09:27:51.271834
977 09:27:51.271900 ==
978 09:27:51.275330 Dram Type= 6, Freq= 0, CH_0, rank 0
979 09:27:51.278555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 09:27:51.278639 ==
981 09:27:51.281709 RX Vref Scan: 1
982 09:27:51.281792
983 09:27:51.281859 Set Vref Range= 32 -> 127
984 09:27:51.281922
985 09:27:51.285497 RX Vref 32 -> 127, step: 1
986 09:27:51.285580
987 09:27:51.288467 RX Delay -79 -> 252, step: 8
988 09:27:51.288550
989 09:27:51.291907 Set Vref, RX VrefLevel [Byte0]: 32
990 09:27:51.295622 [Byte1]: 32
991 09:27:51.295705
992 09:27:51.298381 Set Vref, RX VrefLevel [Byte0]: 33
993 09:27:51.301854 [Byte1]: 33
994 09:27:51.301937
995 09:27:51.305169 Set Vref, RX VrefLevel [Byte0]: 34
996 09:27:51.308815 [Byte1]: 34
997 09:27:51.312448
998 09:27:51.312531 Set Vref, RX VrefLevel [Byte0]: 35
999 09:27:51.315966 [Byte1]: 35
1000 09:27:51.319833
1001 09:27:51.319915 Set Vref, RX VrefLevel [Byte0]: 36
1002 09:27:51.323459 [Byte1]: 36
1003 09:27:51.327511
1004 09:27:51.327593 Set Vref, RX VrefLevel [Byte0]: 37
1005 09:27:51.330984 [Byte1]: 37
1006 09:27:51.334950
1007 09:27:51.335048 Set Vref, RX VrefLevel [Byte0]: 38
1008 09:27:51.338889 [Byte1]: 38
1009 09:27:51.342896
1010 09:27:51.342979 Set Vref, RX VrefLevel [Byte0]: 39
1011 09:27:51.345996 [Byte1]: 39
1012 09:27:51.350851
1013 09:27:51.350934 Set Vref, RX VrefLevel [Byte0]: 40
1014 09:27:51.354009 [Byte1]: 40
1015 09:27:51.357882
1016 09:27:51.357965 Set Vref, RX VrefLevel [Byte0]: 41
1017 09:27:51.361222 [Byte1]: 41
1018 09:27:51.365922
1019 09:27:51.366004 Set Vref, RX VrefLevel [Byte0]: 42
1020 09:27:51.368882 [Byte1]: 42
1021 09:27:51.374002
1022 09:27:51.374084 Set Vref, RX VrefLevel [Byte0]: 43
1023 09:27:51.377904 [Byte1]: 43
1024 09:27:51.377987
1025 09:27:51.381400 Set Vref, RX VrefLevel [Byte0]: 44
1026 09:27:51.384561 [Byte1]: 44
1027 09:27:51.388565
1028 09:27:51.388646 Set Vref, RX VrefLevel [Byte0]: 45
1029 09:27:51.391561 [Byte1]: 45
1030 09:27:51.395393
1031 09:27:51.395476 Set Vref, RX VrefLevel [Byte0]: 46
1032 09:27:51.398667 [Byte1]: 46
1033 09:27:51.403188
1034 09:27:51.403271 Set Vref, RX VrefLevel [Byte0]: 47
1035 09:27:51.406170 [Byte1]: 47
1036 09:27:51.410446
1037 09:27:51.410529 Set Vref, RX VrefLevel [Byte0]: 48
1038 09:27:51.414022 [Byte1]: 48
1039 09:27:51.418175
1040 09:27:51.418258 Set Vref, RX VrefLevel [Byte0]: 49
1041 09:27:51.421676 [Byte1]: 49
1042 09:27:51.425840
1043 09:27:51.425923 Set Vref, RX VrefLevel [Byte0]: 50
1044 09:27:51.428981 [Byte1]: 50
1045 09:27:51.433349
1046 09:27:51.433433 Set Vref, RX VrefLevel [Byte0]: 51
1047 09:27:51.436668 [Byte1]: 51
1048 09:27:51.440765
1049 09:27:51.440848 Set Vref, RX VrefLevel [Byte0]: 52
1050 09:27:51.444041 [Byte1]: 52
1051 09:27:51.448330
1052 09:27:51.448444 Set Vref, RX VrefLevel [Byte0]: 53
1053 09:27:51.451524 [Byte1]: 53
1054 09:27:51.455918
1055 09:27:51.456004 Set Vref, RX VrefLevel [Byte0]: 54
1056 09:27:51.459014 [Byte1]: 54
1057 09:27:51.463632
1058 09:27:51.463715 Set Vref, RX VrefLevel [Byte0]: 55
1059 09:27:51.466798 [Byte1]: 55
1060 09:27:51.471072
1061 09:27:51.471200 Set Vref, RX VrefLevel [Byte0]: 56
1062 09:27:51.474225 [Byte1]: 56
1063 09:27:51.478798
1064 09:27:51.478882 Set Vref, RX VrefLevel [Byte0]: 57
1065 09:27:51.481893 [Byte1]: 57
1066 09:27:51.486530
1067 09:27:51.486614 Set Vref, RX VrefLevel [Byte0]: 58
1068 09:27:51.489468 [Byte1]: 58
1069 09:27:51.493501
1070 09:27:51.493585 Set Vref, RX VrefLevel [Byte0]: 59
1071 09:27:51.496843 [Byte1]: 59
1072 09:27:51.501005
1073 09:27:51.501089 Set Vref, RX VrefLevel [Byte0]: 60
1074 09:27:51.504420 [Byte1]: 60
1075 09:27:51.508638
1076 09:27:51.508721 Set Vref, RX VrefLevel [Byte0]: 61
1077 09:27:51.511980 [Byte1]: 61
1078 09:27:51.516413
1079 09:27:51.516496 Set Vref, RX VrefLevel [Byte0]: 62
1080 09:27:51.519982 [Byte1]: 62
1081 09:27:51.523660
1082 09:27:51.523743 Set Vref, RX VrefLevel [Byte0]: 63
1083 09:27:51.527450 [Byte1]: 63
1084 09:27:51.531146
1085 09:27:51.531229 Set Vref, RX VrefLevel [Byte0]: 64
1086 09:27:51.534551 [Byte1]: 64
1087 09:27:51.539307
1088 09:27:51.539390 Set Vref, RX VrefLevel [Byte0]: 65
1089 09:27:51.542363 [Byte1]: 65
1090 09:27:51.546446
1091 09:27:51.546530 Set Vref, RX VrefLevel [Byte0]: 66
1092 09:27:51.549817 [Byte1]: 66
1093 09:27:51.554439
1094 09:27:51.554522 Set Vref, RX VrefLevel [Byte0]: 67
1095 09:27:51.557550 [Byte1]: 67
1096 09:27:51.561675
1097 09:27:51.561758 Set Vref, RX VrefLevel [Byte0]: 68
1098 09:27:51.564730 [Byte1]: 68
1099 09:27:51.569330
1100 09:27:51.569413 Set Vref, RX VrefLevel [Byte0]: 69
1101 09:27:51.572483 [Byte1]: 69
1102 09:27:51.576509
1103 09:27:51.576599 Set Vref, RX VrefLevel [Byte0]: 70
1104 09:27:51.580193 [Byte1]: 70
1105 09:27:51.584250
1106 09:27:51.584333 Set Vref, RX VrefLevel [Byte0]: 71
1107 09:27:51.587607 [Byte1]: 71
1108 09:27:51.591635
1109 09:27:51.591718 Set Vref, RX VrefLevel [Byte0]: 72
1110 09:27:51.594894 [Byte1]: 72
1111 09:27:51.599322
1112 09:27:51.599404 Set Vref, RX VrefLevel [Byte0]: 73
1113 09:27:51.602783 [Byte1]: 73
1114 09:27:51.606938
1115 09:27:51.607020 Set Vref, RX VrefLevel [Byte0]: 74
1116 09:27:51.610055 [Byte1]: 74
1117 09:27:51.614447
1118 09:27:51.614534 Set Vref, RX VrefLevel [Byte0]: 75
1119 09:27:51.617654 [Byte1]: 75
1120 09:27:51.621930
1121 09:27:51.622011 Set Vref, RX VrefLevel [Byte0]: 76
1122 09:27:51.625603 [Byte1]: 76
1123 09:27:51.629278
1124 09:27:51.629360 Set Vref, RX VrefLevel [Byte0]: 77
1125 09:27:51.633044 [Byte1]: 77
1126 09:27:51.636845
1127 09:27:51.636933 Set Vref, RX VrefLevel [Byte0]: 78
1128 09:27:51.640201 [Byte1]: 78
1129 09:27:51.644853
1130 09:27:51.644963 Final RX Vref Byte 0 = 61 to rank0
1131 09:27:51.647803 Final RX Vref Byte 1 = 57 to rank0
1132 09:27:51.651662 Final RX Vref Byte 0 = 61 to rank1
1133 09:27:51.654616 Final RX Vref Byte 1 = 57 to rank1==
1134 09:27:51.658008 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 09:27:51.661594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 09:27:51.664740 ==
1137 09:27:51.664822 DQS Delay:
1138 09:27:51.664888 DQS0 = 0, DQS1 = 0
1139 09:27:51.668089 DQM Delay:
1140 09:27:51.668171 DQM0 = 93, DQM1 = 83
1141 09:27:51.671288 DQ Delay:
1142 09:27:51.674765 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1143 09:27:51.677899 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1144 09:27:51.677982 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1145 09:27:51.685257 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1146 09:27:51.685340
1147 09:27:51.685405
1148 09:27:51.691328 [DQSOSCAuto] RK0, (LSB)MR18= 0x403c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1149 09:27:51.694653 CH0 RK0: MR19=606, MR18=403C
1150 09:27:51.701671 CH0_RK0: MR19=0x606, MR18=0x403C, DQSOSC=393, MR23=63, INC=95, DEC=63
1151 09:27:51.701753
1152 09:27:51.704621 ----->DramcWriteLeveling(PI) begin...
1153 09:27:51.704704 ==
1154 09:27:51.708039 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 09:27:51.711376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 09:27:51.711458 ==
1157 09:27:51.715023 Write leveling (Byte 0): 32 => 32
1158 09:27:51.718493 Write leveling (Byte 1): 28 => 28
1159 09:27:51.721599 DramcWriteLeveling(PI) end<-----
1160 09:27:51.721681
1161 09:27:51.721746 ==
1162 09:27:51.724791 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 09:27:51.728044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 09:27:51.728127 ==
1165 09:27:51.731306 [Gating] SW mode calibration
1166 09:27:51.738421 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 09:27:51.745067 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 09:27:51.748232 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 09:27:51.751478 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 09:27:51.758510 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:27:51.761584 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:27:51.805567 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:27:51.806076 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:27:51.806388 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:27:51.806487 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:27:51.806699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:27:51.806835 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:27:51.807172 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:27:51.807263 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:27:51.807327 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:27:51.807806 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:27:51.818071 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:27:51.818395 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:27:51.821280 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:27:51.821363 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1186 09:27:51.827945 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:27:51.831330 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:27:51.834962 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:27:51.841377 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:27:51.844909 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:27:51.847962 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:27:51.855237 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:27:51.858350 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1194 09:27:51.861645 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (0 0)
1195 09:27:51.868456 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 09:27:51.871726 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 09:27:51.875079 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 09:27:51.878521 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 09:27:51.885129 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 09:27:51.888576 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 09:27:51.892046 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
1202 09:27:51.898918 0 10 8 | B1->B0 | 2c2c 2727 | 0 0 | (1 1) (0 0)
1203 09:27:51.901706 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 09:27:51.905434 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 09:27:51.911508 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 09:27:51.915198 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 09:27:51.918209 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 09:27:51.925424 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 09:27:51.928314 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1210 09:27:51.931961 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1211 09:27:51.938597 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 09:27:51.942192 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 09:27:51.945762 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 09:27:51.950210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 09:27:51.953815 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 09:27:51.960407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 09:27:51.963590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1218 09:27:51.967209 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1219 09:27:51.971287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:27:51.977895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 09:27:51.981048 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 09:27:51.984387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 09:27:51.991391 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 09:27:51.994544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 09:27:51.997939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 09:27:52.004569 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 09:27:52.008010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 09:27:52.011187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 09:27:52.014543 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 09:27:52.021866 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 09:27:52.024546 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 09:27:52.028387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 09:27:52.034832 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1234 09:27:52.038362 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 09:27:52.041275 Total UI for P1: 0, mck2ui 16
1236 09:27:52.045096 best dqsien dly found for B0: ( 0, 14, 4)
1237 09:27:52.048271 Total UI for P1: 0, mck2ui 16
1238 09:27:52.051330 best dqsien dly found for B1: ( 0, 14, 6)
1239 09:27:52.054750 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1240 09:27:52.058376 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1241 09:27:52.058459
1242 09:27:52.061457 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1243 09:27:52.065262 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1244 09:27:52.067987 [Gating] SW calibration Done
1245 09:27:52.068069 ==
1246 09:27:52.071746 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 09:27:52.074966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 09:27:52.075055 ==
1249 09:27:52.078701 RX Vref Scan: 0
1250 09:27:52.078783
1251 09:27:52.081837 RX Vref 0 -> 0, step: 1
1252 09:27:52.081919
1253 09:27:52.081984 RX Delay -130 -> 252, step: 16
1254 09:27:52.088059 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1255 09:27:52.091258 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1256 09:27:52.094902 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1257 09:27:52.098277 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1258 09:27:52.101651 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1259 09:27:52.108452 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1260 09:27:52.111276 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1261 09:27:52.114667 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1262 09:27:52.118287 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1263 09:27:52.121788 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1264 09:27:52.128469 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1265 09:27:52.131908 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1266 09:27:52.135219 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1267 09:27:52.138543 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1268 09:27:52.141452 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1269 09:27:52.148404 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1270 09:27:52.148485 ==
1271 09:27:52.151520 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 09:27:52.154776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 09:27:52.154857 ==
1274 09:27:52.154923 DQS Delay:
1275 09:27:52.158304 DQS0 = 0, DQS1 = 0
1276 09:27:52.158385 DQM Delay:
1277 09:27:52.161594 DQM0 = 89, DQM1 = 80
1278 09:27:52.161674 DQ Delay:
1279 09:27:52.165083 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1280 09:27:52.168411 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1281 09:27:52.172239 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1282 09:27:52.175023 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =93
1283 09:27:52.175104
1284 09:27:52.175205
1285 09:27:52.175264 ==
1286 09:27:52.178121 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 09:27:52.181593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 09:27:52.185134 ==
1289 09:27:52.185215
1290 09:27:52.185279
1291 09:27:52.185364 TX Vref Scan disable
1292 09:27:52.188541 == TX Byte 0 ==
1293 09:27:52.191491 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1294 09:27:52.194741 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1295 09:27:52.198363 == TX Byte 1 ==
1296 09:27:52.201684 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1297 09:27:52.204778 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1298 09:27:52.204897 ==
1299 09:27:52.208303 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 09:27:52.215079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 09:27:52.215176 ==
1302 09:27:52.227197 TX Vref=22, minBit 8, minWin=27, winSum=446
1303 09:27:52.230747 TX Vref=24, minBit 8, minWin=27, winSum=449
1304 09:27:52.233888 TX Vref=26, minBit 8, minWin=27, winSum=452
1305 09:27:52.237463 TX Vref=28, minBit 8, minWin=27, winSum=452
1306 09:27:52.240754 TX Vref=30, minBit 8, minWin=27, winSum=456
1307 09:27:52.244119 TX Vref=32, minBit 8, minWin=28, winSum=458
1308 09:27:52.250688 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1309 09:27:52.250771
1310 09:27:52.254116 Final TX Range 1 Vref 32
1311 09:27:52.254198
1312 09:27:52.254263 ==
1313 09:27:52.257526 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 09:27:52.260751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 09:27:52.260834 ==
1316 09:27:52.260899
1317 09:27:52.264225
1318 09:27:52.264305 TX Vref Scan disable
1319 09:27:52.267944 == TX Byte 0 ==
1320 09:27:52.270702 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1321 09:27:52.274040 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1322 09:27:52.278142 == TX Byte 1 ==
1323 09:27:52.280871 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1324 09:27:52.284198 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1325 09:27:52.287518
1326 09:27:52.287599 [DATLAT]
1327 09:27:52.287663 Freq=800, CH0 RK1
1328 09:27:52.287723
1329 09:27:52.290651 DATLAT Default: 0xa
1330 09:27:52.290733 0, 0xFFFF, sum = 0
1331 09:27:52.294155 1, 0xFFFF, sum = 0
1332 09:27:52.294238 2, 0xFFFF, sum = 0
1333 09:27:52.297875 3, 0xFFFF, sum = 0
1334 09:27:52.297958 4, 0xFFFF, sum = 0
1335 09:27:52.300938 5, 0xFFFF, sum = 0
1336 09:27:52.301021 6, 0xFFFF, sum = 0
1337 09:27:52.304061 7, 0xFFFF, sum = 0
1338 09:27:52.307287 8, 0xFFFF, sum = 0
1339 09:27:52.307370 9, 0x0, sum = 1
1340 09:27:52.307436 10, 0x0, sum = 2
1341 09:27:52.310679 11, 0x0, sum = 3
1342 09:27:52.310762 12, 0x0, sum = 4
1343 09:27:52.314134 best_step = 10
1344 09:27:52.314215
1345 09:27:52.314280 ==
1346 09:27:52.317529 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 09:27:52.320852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 09:27:52.320958 ==
1349 09:27:52.324264 RX Vref Scan: 0
1350 09:27:52.324345
1351 09:27:52.324410 RX Vref 0 -> 0, step: 1
1352 09:27:52.324471
1353 09:27:52.327381 RX Delay -79 -> 252, step: 8
1354 09:27:52.334114 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1355 09:27:52.337965 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1356 09:27:52.340955 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1357 09:27:52.344195 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1358 09:27:52.347426 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1359 09:27:52.354214 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1360 09:27:52.357471 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1361 09:27:52.360810 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1362 09:27:52.364064 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1363 09:27:52.367431 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1364 09:27:52.374244 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1365 09:27:52.377641 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1366 09:27:52.380833 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1367 09:27:52.384217 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1368 09:27:52.387721 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1369 09:27:52.394552 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1370 09:27:52.394632 ==
1371 09:27:52.398077 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 09:27:52.400887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 09:27:52.401019 ==
1374 09:27:52.401083 DQS Delay:
1375 09:27:52.404631 DQS0 = 0, DQS1 = 0
1376 09:27:52.404711 DQM Delay:
1377 09:27:52.407435 DQM0 = 91, DQM1 = 81
1378 09:27:52.407514 DQ Delay:
1379 09:27:52.410818 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1380 09:27:52.414299 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1381 09:27:52.417575 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1382 09:27:52.420986 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1383 09:27:52.421067
1384 09:27:52.421130
1385 09:27:52.427899 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1386 09:27:52.431054 CH0 RK1: MR19=606, MR18=421D
1387 09:27:52.437669 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1388 09:27:52.440971 [RxdqsGatingPostProcess] freq 800
1389 09:27:52.447789 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1390 09:27:52.447871 Pre-setting of DQS Precalculation
1391 09:27:52.454471 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1392 09:27:52.454554 ==
1393 09:27:52.457817 Dram Type= 6, Freq= 0, CH_1, rank 0
1394 09:27:52.460878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 09:27:52.461010 ==
1396 09:27:52.467844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 09:27:52.474223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 09:27:52.482315 [CA 0] Center 36 (6~67) winsize 62
1399 09:27:52.485850 [CA 1] Center 36 (6~67) winsize 62
1400 09:27:52.489156 [CA 2] Center 35 (5~65) winsize 61
1401 09:27:52.492497 [CA 3] Center 34 (4~65) winsize 62
1402 09:27:52.496279 [CA 4] Center 34 (4~65) winsize 62
1403 09:27:52.499243 [CA 5] Center 33 (3~64) winsize 62
1404 09:27:52.499327
1405 09:27:52.502653 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1406 09:27:52.502763
1407 09:27:52.505936 [CATrainingPosCal] consider 1 rank data
1408 09:27:52.509517 u2DelayCellTimex100 = 270/100 ps
1409 09:27:52.512462 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1410 09:27:52.515840 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 09:27:52.522978 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1412 09:27:52.525994 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 09:27:52.529402 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 09:27:52.532599 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 09:27:52.532683
1416 09:27:52.535964 CA PerBit enable=1, Macro0, CA PI delay=33
1417 09:27:52.536048
1418 09:27:52.539476 [CBTSetCACLKResult] CA Dly = 33
1419 09:27:52.539560 CS Dly: 5 (0~36)
1420 09:27:52.539626 ==
1421 09:27:52.543025 Dram Type= 6, Freq= 0, CH_1, rank 1
1422 09:27:52.549248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 09:27:52.549333 ==
1424 09:27:52.552875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 09:27:52.559394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 09:27:52.568866 [CA 0] Center 37 (7~67) winsize 61
1427 09:27:52.572054 [CA 1] Center 37 (6~68) winsize 63
1428 09:27:52.575613 [CA 2] Center 35 (5~66) winsize 62
1429 09:27:52.578716 [CA 3] Center 34 (4~65) winsize 62
1430 09:27:52.582224 [CA 4] Center 34 (4~65) winsize 62
1431 09:27:52.585586 [CA 5] Center 34 (4~64) winsize 61
1432 09:27:52.585682
1433 09:27:52.588916 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 09:27:52.589039
1435 09:27:52.592067 [CATrainingPosCal] consider 2 rank data
1436 09:27:52.595443 u2DelayCellTimex100 = 270/100 ps
1437 09:27:52.599134 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1438 09:27:52.601963 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 09:27:52.606232 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1440 09:27:52.609961 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 09:27:52.613375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 09:27:52.617236 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1443 09:27:52.617321
1444 09:27:52.620909 CA PerBit enable=1, Macro0, CA PI delay=34
1445 09:27:52.621031
1446 09:27:52.624381 [CBTSetCACLKResult] CA Dly = 34
1447 09:27:52.628124 CS Dly: 5 (0~37)
1448 09:27:52.628208
1449 09:27:52.631658 ----->DramcWriteLeveling(PI) begin...
1450 09:27:52.631744 ==
1451 09:27:52.635541 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 09:27:52.639482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 09:27:52.639571 ==
1454 09:27:52.642877 Write leveling (Byte 0): 28 => 28
1455 09:27:52.642966 Write leveling (Byte 1): 29 => 29
1456 09:27:52.646214 DramcWriteLeveling(PI) end<-----
1457 09:27:52.646308
1458 09:27:52.646375 ==
1459 09:27:52.649908 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 09:27:52.656517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 09:27:52.656606 ==
1462 09:27:52.656673 [Gating] SW mode calibration
1463 09:27:52.666306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1464 09:27:52.669725 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1465 09:27:52.673188 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1466 09:27:52.679725 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:27:52.683244 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:27:52.686822 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:27:52.693782 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:27:52.696569 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:27:52.700078 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:27:52.706836 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:27:52.709757 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:27:52.713256 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:27:52.719864 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:27:52.723799 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:27:52.726347 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:27:52.729793 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:27:52.736667 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:27:52.740168 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:27:52.743463 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1482 09:27:52.749988 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1483 09:27:52.753270 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:27:52.756869 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:27:52.763124 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:27:52.766923 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:27:52.770295 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:27:52.776887 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:27:52.779945 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:27:52.783385 0 9 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1491 09:27:52.790106 0 9 8 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
1492 09:27:52.793465 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 09:27:52.796793 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 09:27:52.803463 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 09:27:52.806741 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 09:27:52.809969 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 09:27:52.813569 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1498 09:27:52.820054 0 10 4 | B1->B0 | 2e2e 2c2c | 0 0 | (0 1) (1 1)
1499 09:27:52.823376 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:27:52.826705 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 09:27:52.833523 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 09:27:52.836763 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 09:27:52.840147 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 09:27:52.846884 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 09:27:52.850209 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 09:27:52.854107 0 11 4 | B1->B0 | 3333 3636 | 0 0 | (0 0) (0 0)
1507 09:27:52.860077 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1508 09:27:52.863397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 09:27:52.867103 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 09:27:52.874148 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 09:27:52.877174 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 09:27:52.880650 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 09:27:52.887158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1514 09:27:52.890556 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1515 09:27:52.893631 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1516 09:27:52.897204 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:27:52.903981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:27:52.907070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 09:27:52.910719 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 09:27:52.916942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 09:27:52.920639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 09:27:52.923692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 09:27:52.930516 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 09:27:52.933754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 09:27:52.937528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 09:27:52.943949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 09:27:52.947061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 09:27:52.950923 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 09:27:52.957949 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1530 09:27:52.960323 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1531 09:27:52.963930 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 09:27:52.967221 Total UI for P1: 0, mck2ui 16
1533 09:27:52.970519 best dqsien dly found for B0: ( 0, 14, 2)
1534 09:27:52.973913 Total UI for P1: 0, mck2ui 16
1535 09:27:52.977328 best dqsien dly found for B1: ( 0, 14, 4)
1536 09:27:52.980879 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1537 09:27:52.983827 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1538 09:27:52.983912
1539 09:27:52.987622 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1540 09:27:52.990866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 09:27:52.993783 [Gating] SW calibration Done
1542 09:27:52.993868 ==
1543 09:27:52.997262 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 09:27:53.000610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 09:27:53.003817 ==
1546 09:27:53.003901 RX Vref Scan: 0
1547 09:27:53.003967
1548 09:27:53.007439 RX Vref 0 -> 0, step: 1
1549 09:27:53.007522
1550 09:27:53.010456 RX Delay -130 -> 252, step: 16
1551 09:27:53.014321 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1552 09:27:53.017575 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1553 09:27:53.020781 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1554 09:27:53.024093 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1555 09:27:53.030912 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1556 09:27:53.034230 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1557 09:27:53.037467 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1558 09:27:53.040756 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1559 09:27:53.043884 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1560 09:27:53.050988 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1561 09:27:53.054131 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1562 09:27:53.057615 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1563 09:27:53.061059 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1564 09:27:53.064020 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1565 09:27:53.071106 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1566 09:27:53.074870 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1567 09:27:53.074991 ==
1568 09:27:53.077746 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 09:27:53.080812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 09:27:53.080963 ==
1571 09:27:53.081061 DQS Delay:
1572 09:27:53.084441 DQS0 = 0, DQS1 = 0
1573 09:27:53.084525 DQM Delay:
1574 09:27:53.087850 DQM0 = 91, DQM1 = 82
1575 09:27:53.087934 DQ Delay:
1576 09:27:53.090987 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1577 09:27:53.094384 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1578 09:27:53.097961 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1579 09:27:53.101351 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
1580 09:27:53.101438
1581 09:27:53.101506
1582 09:27:53.101568 ==
1583 09:27:53.104195 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 09:27:53.107890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 09:27:53.111262 ==
1586 09:27:53.111354
1587 09:27:53.111422
1588 09:27:53.111483 TX Vref Scan disable
1589 09:27:53.114132 == TX Byte 0 ==
1590 09:27:53.117576 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1591 09:27:53.120893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1592 09:27:53.124650 == TX Byte 1 ==
1593 09:27:53.127867 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1594 09:27:53.131208 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1595 09:27:53.134423 ==
1596 09:27:53.134511 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 09:27:53.141161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 09:27:53.141272 ==
1599 09:27:53.152889 TX Vref=22, minBit 10, minWin=26, winSum=446
1600 09:27:53.156605 TX Vref=24, minBit 8, minWin=27, winSum=449
1601 09:27:53.159542 TX Vref=26, minBit 8, minWin=27, winSum=452
1602 09:27:53.163021 TX Vref=28, minBit 8, minWin=27, winSum=457
1603 09:27:53.166178 TX Vref=30, minBit 8, minWin=27, winSum=456
1604 09:27:53.170195 TX Vref=32, minBit 8, minWin=27, winSum=455
1605 09:27:53.176848 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 28
1606 09:27:53.176960
1607 09:27:53.179998 Final TX Range 1 Vref 28
1608 09:27:53.180087
1609 09:27:53.180155 ==
1610 09:27:53.183283 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 09:27:53.186668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 09:27:53.186759 ==
1613 09:27:53.186827
1614 09:27:53.186889
1615 09:27:53.190551 TX Vref Scan disable
1616 09:27:53.193869 == TX Byte 0 ==
1617 09:27:53.197531 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1618 09:27:53.200728 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1619 09:27:53.204411 == TX Byte 1 ==
1620 09:27:53.207222 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1621 09:27:53.210825 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1622 09:27:53.210915
1623 09:27:53.210983 [DATLAT]
1624 09:27:53.214042 Freq=800, CH1 RK0
1625 09:27:53.214128
1626 09:27:53.217259 DATLAT Default: 0xa
1627 09:27:53.217344 0, 0xFFFF, sum = 0
1628 09:27:53.221541 1, 0xFFFF, sum = 0
1629 09:27:53.221628 2, 0xFFFF, sum = 0
1630 09:27:53.224131 3, 0xFFFF, sum = 0
1631 09:27:53.224217 4, 0xFFFF, sum = 0
1632 09:27:53.227329 5, 0xFFFF, sum = 0
1633 09:27:53.227417 6, 0xFFFF, sum = 0
1634 09:27:53.231118 7, 0xFFFF, sum = 0
1635 09:27:53.231205 8, 0xFFFF, sum = 0
1636 09:27:53.234046 9, 0x0, sum = 1
1637 09:27:53.234133 10, 0x0, sum = 2
1638 09:27:53.237471 11, 0x0, sum = 3
1639 09:27:53.237558 12, 0x0, sum = 4
1640 09:27:53.237626 best_step = 10
1641 09:27:53.241119
1642 09:27:53.241235 ==
1643 09:27:53.244287 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 09:27:53.247514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 09:27:53.247602 ==
1646 09:27:53.247670 RX Vref Scan: 1
1647 09:27:53.247733
1648 09:27:53.250760 Set Vref Range= 32 -> 127
1649 09:27:53.250846
1650 09:27:53.254288 RX Vref 32 -> 127, step: 1
1651 09:27:53.254376
1652 09:27:53.257661 RX Delay -95 -> 252, step: 8
1653 09:27:53.257748
1654 09:27:53.260739 Set Vref, RX VrefLevel [Byte0]: 32
1655 09:27:53.264208 [Byte1]: 32
1656 09:27:53.264296
1657 09:27:53.267377 Set Vref, RX VrefLevel [Byte0]: 33
1658 09:27:53.271187 [Byte1]: 33
1659 09:27:53.271275
1660 09:27:53.274581 Set Vref, RX VrefLevel [Byte0]: 34
1661 09:27:53.277805 [Byte1]: 34
1662 09:27:53.280757
1663 09:27:53.280845 Set Vref, RX VrefLevel [Byte0]: 35
1664 09:27:53.284383 [Byte1]: 35
1665 09:27:53.288690
1666 09:27:53.288778 Set Vref, RX VrefLevel [Byte0]: 36
1667 09:27:53.291837 [Byte1]: 36
1668 09:27:53.295996
1669 09:27:53.296096 Set Vref, RX VrefLevel [Byte0]: 37
1670 09:27:53.299205 [Byte1]: 37
1671 09:27:53.303833
1672 09:27:53.303923 Set Vref, RX VrefLevel [Byte0]: 38
1673 09:27:53.306808 [Byte1]: 38
1674 09:27:53.311558
1675 09:27:53.311646 Set Vref, RX VrefLevel [Byte0]: 39
1676 09:27:53.314326 [Byte1]: 39
1677 09:27:53.318858
1678 09:27:53.318946 Set Vref, RX VrefLevel [Byte0]: 40
1679 09:27:53.322263 [Byte1]: 40
1680 09:27:53.326473
1681 09:27:53.326561 Set Vref, RX VrefLevel [Byte0]: 41
1682 09:27:53.329641 [Byte1]: 41
1683 09:27:53.334064
1684 09:27:53.334151 Set Vref, RX VrefLevel [Byte0]: 42
1685 09:27:53.337588 [Byte1]: 42
1686 09:27:53.341641
1687 09:27:53.341735 Set Vref, RX VrefLevel [Byte0]: 43
1688 09:27:53.344860 [Byte1]: 43
1689 09:27:53.349617
1690 09:27:53.349706 Set Vref, RX VrefLevel [Byte0]: 44
1691 09:27:53.352415 [Byte1]: 44
1692 09:27:53.357145
1693 09:27:53.357241 Set Vref, RX VrefLevel [Byte0]: 45
1694 09:27:53.360215 [Byte1]: 45
1695 09:27:53.364402
1696 09:27:53.364490 Set Vref, RX VrefLevel [Byte0]: 46
1697 09:27:53.368091 [Byte1]: 46
1698 09:27:53.371816
1699 09:27:53.371904 Set Vref, RX VrefLevel [Byte0]: 47
1700 09:27:53.375357 [Byte1]: 47
1701 09:27:53.380350
1702 09:27:53.380444 Set Vref, RX VrefLevel [Byte0]: 48
1703 09:27:53.382909 [Byte1]: 48
1704 09:27:53.387123
1705 09:27:53.387211 Set Vref, RX VrefLevel [Byte0]: 49
1706 09:27:53.390705 [Byte1]: 49
1707 09:27:53.394790
1708 09:27:53.394881 Set Vref, RX VrefLevel [Byte0]: 50
1709 09:27:53.398176 [Byte1]: 50
1710 09:27:53.402566
1711 09:27:53.402656 Set Vref, RX VrefLevel [Byte0]: 51
1712 09:27:53.405534 [Byte1]: 51
1713 09:27:53.409867
1714 09:27:53.409972 Set Vref, RX VrefLevel [Byte0]: 52
1715 09:27:53.413445 [Byte1]: 52
1716 09:27:53.417584
1717 09:27:53.417672 Set Vref, RX VrefLevel [Byte0]: 53
1718 09:27:53.420735 [Byte1]: 53
1719 09:27:53.425523
1720 09:27:53.425614 Set Vref, RX VrefLevel [Byte0]: 54
1721 09:27:53.428560 [Byte1]: 54
1722 09:27:53.432719
1723 09:27:53.432809 Set Vref, RX VrefLevel [Byte0]: 55
1724 09:27:53.436267 [Byte1]: 55
1725 09:27:53.440255
1726 09:27:53.440359 Set Vref, RX VrefLevel [Byte0]: 56
1727 09:27:53.443860 [Byte1]: 56
1728 09:27:53.448107
1729 09:27:53.448198 Set Vref, RX VrefLevel [Byte0]: 57
1730 09:27:53.451296 [Byte1]: 57
1731 09:27:53.455458
1732 09:27:53.455546 Set Vref, RX VrefLevel [Byte0]: 58
1733 09:27:53.459043 [Byte1]: 58
1734 09:27:53.463243
1735 09:27:53.463362 Set Vref, RX VrefLevel [Byte0]: 59
1736 09:27:53.466608 [Byte1]: 59
1737 09:27:53.470932
1738 09:27:53.471023 Set Vref, RX VrefLevel [Byte0]: 60
1739 09:27:53.474319 [Byte1]: 60
1740 09:27:53.478432
1741 09:27:53.478521 Set Vref, RX VrefLevel [Byte0]: 61
1742 09:27:53.481839 [Byte1]: 61
1743 09:27:53.485986
1744 09:27:53.486074 Set Vref, RX VrefLevel [Byte0]: 62
1745 09:27:53.489207 [Byte1]: 62
1746 09:27:53.494150
1747 09:27:53.494242 Set Vref, RX VrefLevel [Byte0]: 63
1748 09:27:53.497023 [Byte1]: 63
1749 09:27:53.501005
1750 09:27:53.501092 Set Vref, RX VrefLevel [Byte0]: 64
1751 09:27:53.504676 [Byte1]: 64
1752 09:27:53.509098
1753 09:27:53.509201 Set Vref, RX VrefLevel [Byte0]: 65
1754 09:27:53.511968 [Byte1]: 65
1755 09:27:53.516337
1756 09:27:53.516428 Set Vref, RX VrefLevel [Byte0]: 66
1757 09:27:53.519898 [Byte1]: 66
1758 09:27:53.523906
1759 09:27:53.524041 Set Vref, RX VrefLevel [Byte0]: 67
1760 09:27:53.527161 [Byte1]: 67
1761 09:27:53.531599
1762 09:27:53.531707 Set Vref, RX VrefLevel [Byte0]: 68
1763 09:27:53.535003 [Byte1]: 68
1764 09:27:53.539103
1765 09:27:53.539208 Set Vref, RX VrefLevel [Byte0]: 69
1766 09:27:53.542655 [Byte1]: 69
1767 09:27:53.546867
1768 09:27:53.546960 Set Vref, RX VrefLevel [Byte0]: 70
1769 09:27:53.550395 [Byte1]: 70
1770 09:27:53.554381
1771 09:27:53.554469 Set Vref, RX VrefLevel [Byte0]: 71
1772 09:27:53.557577 [Byte1]: 71
1773 09:27:53.561794
1774 09:27:53.561882 Set Vref, RX VrefLevel [Byte0]: 72
1775 09:27:53.565318 [Byte1]: 72
1776 09:27:53.569378
1777 09:27:53.569488 Set Vref, RX VrefLevel [Byte0]: 73
1778 09:27:53.573191 [Byte1]: 73
1779 09:27:53.577366
1780 09:27:53.577454 Set Vref, RX VrefLevel [Byte0]: 74
1781 09:27:53.580369 [Byte1]: 74
1782 09:27:53.584959
1783 09:27:53.585077 Final RX Vref Byte 0 = 52 to rank0
1784 09:27:53.588131 Final RX Vref Byte 1 = 63 to rank0
1785 09:27:53.592090 Final RX Vref Byte 0 = 52 to rank1
1786 09:27:53.595220 Final RX Vref Byte 1 = 63 to rank1==
1787 09:27:53.598254 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 09:27:53.601483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 09:27:53.604886 ==
1790 09:27:53.604993 DQS Delay:
1791 09:27:53.605062 DQS0 = 0, DQS1 = 0
1792 09:27:53.608233 DQM Delay:
1793 09:27:53.608318 DQM0 = 93, DQM1 = 84
1794 09:27:53.611641 DQ Delay:
1795 09:27:53.614887 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1796 09:27:53.614976 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1797 09:27:53.618184 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1798 09:27:53.621537 DQ12 =96, DQ13 =88, DQ14 =88, DQ15 =88
1799 09:27:53.624899
1800 09:27:53.625030
1801 09:27:53.632304 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 398 ps
1802 09:27:53.635385 CH1 RK0: MR19=606, MR18=2E4C
1803 09:27:53.641735 CH1_RK0: MR19=0x606, MR18=0x2E4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1804 09:27:53.641845
1805 09:27:53.645292 ----->DramcWriteLeveling(PI) begin...
1806 09:27:53.645384 ==
1807 09:27:53.648588 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 09:27:53.651960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 09:27:53.652046 ==
1810 09:27:53.655024 Write leveling (Byte 0): 26 => 26
1811 09:27:53.658464 Write leveling (Byte 1): 32 => 32
1812 09:27:53.661732 DramcWriteLeveling(PI) end<-----
1813 09:27:53.661817
1814 09:27:53.661884 ==
1815 09:27:53.665147 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 09:27:53.668700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 09:27:53.668786 ==
1818 09:27:53.671945 [Gating] SW mode calibration
1819 09:27:53.678366 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 09:27:53.684848 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 09:27:53.688296 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1822 09:27:53.691922 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1823 09:27:53.698611 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:27:53.701742 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:27:53.705157 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:27:53.711716 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:27:53.715121 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:27:53.718711 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:27:53.722063 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:27:53.728666 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:27:53.731975 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:27:53.735582 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:27:53.742102 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:27:53.745460 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:27:53.748736 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:27:53.755174 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:27:53.758678 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:27:53.762212 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1839 09:27:53.768581 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:27:53.772246 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:27:53.775985 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:27:53.778833 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:27:53.785522 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:27:53.789126 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:27:53.792632 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:27:53.799760 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1847 09:27:53.802481 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1848 09:27:53.805858 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 09:27:53.812437 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 09:27:53.815944 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 09:27:53.819207 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 09:27:53.825992 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 09:27:53.829291 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1854 09:27:53.832393 0 10 4 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 1)
1855 09:27:53.839225 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:27:53.842362 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:27:53.845751 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:27:53.849178 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:27:53.855785 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:27:53.859412 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:27:53.862492 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 09:27:53.869329 0 11 4 | B1->B0 | 3636 2e2e | 1 1 | (0 0) (0 0)
1863 09:27:53.872827 0 11 8 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (1 1)
1864 09:27:53.875950 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 09:27:53.882886 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 09:27:53.886180 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 09:27:53.889305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 09:27:53.895866 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 09:27:53.899245 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 09:27:53.903263 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1871 09:27:53.909512 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 09:27:53.912587 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:27:53.915859 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 09:27:53.922816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 09:27:53.925993 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 09:27:53.929543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 09:27:53.933023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 09:27:53.939703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 09:27:53.942801 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 09:27:53.946212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 09:27:53.952777 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 09:27:53.956303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 09:27:53.959693 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 09:27:53.966133 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 09:27:53.969607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1886 09:27:53.972735 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 09:27:53.979987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 09:27:53.980097 Total UI for P1: 0, mck2ui 16
1889 09:27:53.986163 best dqsien dly found for B0: ( 0, 14, 4)
1890 09:27:53.986259 Total UI for P1: 0, mck2ui 16
1891 09:27:53.990270 best dqsien dly found for B1: ( 0, 14, 6)
1892 09:27:53.996377 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1893 09:27:53.999493 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1894 09:27:53.999589
1895 09:27:54.002886 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1896 09:27:54.006394 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 09:27:54.009882 [Gating] SW calibration Done
1898 09:27:54.009973 ==
1899 09:27:54.012905 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 09:27:54.016445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 09:27:54.016556 ==
1902 09:27:54.016654 RX Vref Scan: 0
1903 09:27:54.016746
1904 09:27:54.020075 RX Vref 0 -> 0, step: 1
1905 09:27:54.020160
1906 09:27:54.023076 RX Delay -130 -> 252, step: 16
1907 09:27:54.026499 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1908 09:27:54.029846 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1909 09:27:54.037230 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1910 09:27:54.039761 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1911 09:27:54.043652 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1912 09:27:54.046666 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1913 09:27:54.049866 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 09:27:54.053263 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1915 09:27:54.060158 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1916 09:27:54.063192 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1917 09:27:54.066816 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1918 09:27:54.070003 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1919 09:27:54.073447 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1920 09:27:54.080521 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1921 09:27:54.083475 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1922 09:27:54.086734 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1923 09:27:54.086824 ==
1924 09:27:54.090113 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 09:27:54.093350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 09:27:54.096682 ==
1927 09:27:54.096772 DQS Delay:
1928 09:27:54.096841 DQS0 = 0, DQS1 = 0
1929 09:27:54.100140 DQM Delay:
1930 09:27:54.100253 DQM0 = 90, DQM1 = 82
1931 09:27:54.103285 DQ Delay:
1932 09:27:54.103398 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1933 09:27:54.106772 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1934 09:27:54.110317 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1935 09:27:54.113277 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1936 09:27:54.116646
1937 09:27:54.116735
1938 09:27:54.116802 ==
1939 09:27:54.119974 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 09:27:54.123182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 09:27:54.123272 ==
1942 09:27:54.123340
1943 09:27:54.123401
1944 09:27:54.126634 TX Vref Scan disable
1945 09:27:54.126720 == TX Byte 0 ==
1946 09:27:54.133246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1947 09:27:54.136740 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1948 09:27:54.136832 == TX Byte 1 ==
1949 09:27:54.143227 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1950 09:27:54.146653 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1951 09:27:54.146748 ==
1952 09:27:54.150008 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 09:27:54.153575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 09:27:54.153690 ==
1955 09:27:54.167239 TX Vref=22, minBit 13, minWin=27, winSum=452
1956 09:27:54.170959 TX Vref=24, minBit 8, minWin=27, winSum=452
1957 09:27:54.174518 TX Vref=26, minBit 13, minWin=27, winSum=456
1958 09:27:54.177548 TX Vref=28, minBit 9, minWin=28, winSum=462
1959 09:27:54.180782 TX Vref=30, minBit 8, minWin=28, winSum=463
1960 09:27:54.187645 TX Vref=32, minBit 8, minWin=28, winSum=461
1961 09:27:54.190846 [TxChooseVref] Worse bit 8, Min win 28, Win sum 463, Final Vref 30
1962 09:27:54.190938
1963 09:27:54.194274 Final TX Range 1 Vref 30
1964 09:27:54.194360
1965 09:27:54.194427 ==
1966 09:27:54.197671 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 09:27:54.200888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 09:27:54.201021 ==
1969 09:27:54.201089
1970 09:27:54.204146
1971 09:27:54.204229 TX Vref Scan disable
1972 09:27:54.207452 == TX Byte 0 ==
1973 09:27:54.210919 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1974 09:27:54.214130 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1975 09:27:54.217436 == TX Byte 1 ==
1976 09:27:54.220841 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1977 09:27:54.224209 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1978 09:27:54.227349
1979 09:27:54.227439 [DATLAT]
1980 09:27:54.227506 Freq=800, CH1 RK1
1981 09:27:54.227569
1982 09:27:54.231038 DATLAT Default: 0xa
1983 09:27:54.231125 0, 0xFFFF, sum = 0
1984 09:27:54.234273 1, 0xFFFF, sum = 0
1985 09:27:54.234360 2, 0xFFFF, sum = 0
1986 09:27:54.237578 3, 0xFFFF, sum = 0
1987 09:27:54.237682 4, 0xFFFF, sum = 0
1988 09:27:54.241145 5, 0xFFFF, sum = 0
1989 09:27:54.241233 6, 0xFFFF, sum = 0
1990 09:27:54.244618 7, 0xFFFF, sum = 0
1991 09:27:54.247815 8, 0xFFFF, sum = 0
1992 09:27:54.247906 9, 0x0, sum = 1
1993 09:27:54.247975 10, 0x0, sum = 2
1994 09:27:54.251277 11, 0x0, sum = 3
1995 09:27:54.251364 12, 0x0, sum = 4
1996 09:27:54.254197 best_step = 10
1997 09:27:54.254288
1998 09:27:54.254355 ==
1999 09:27:54.257803 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 09:27:54.261188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 09:27:54.261276 ==
2002 09:27:54.264450 RX Vref Scan: 0
2003 09:27:54.264533
2004 09:27:54.264600 RX Vref 0 -> 0, step: 1
2005 09:27:54.264660
2006 09:27:54.267821 RX Delay -95 -> 252, step: 8
2007 09:27:54.274627 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2008 09:27:54.278277 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2009 09:27:54.281488 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2010 09:27:54.284720 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2011 09:27:54.288222 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2012 09:27:54.291951 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2013 09:27:54.298306 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2014 09:27:54.301748 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2015 09:27:54.304636 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
2016 09:27:54.308696 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2017 09:27:54.311515 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2018 09:27:54.318133 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2019 09:27:54.321439 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2020 09:27:54.324842 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2021 09:27:54.328086 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2022 09:27:54.331321 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2023 09:27:54.334920 ==
2024 09:27:54.335010 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 09:27:54.341271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 09:27:54.341393 ==
2027 09:27:54.341466 DQS Delay:
2028 09:27:54.344740 DQS0 = 0, DQS1 = 0
2029 09:27:54.344831 DQM Delay:
2030 09:27:54.348155 DQM0 = 92, DQM1 = 84
2031 09:27:54.348245 DQ Delay:
2032 09:27:54.351479 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2033 09:27:54.354950 DQ4 =96, DQ5 =104, DQ6 =96, DQ7 =88
2034 09:27:54.358066 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =80
2035 09:27:54.361447 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2036 09:27:54.361538
2037 09:27:54.361606
2038 09:27:54.368633 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2039 09:27:54.371655 CH1 RK1: MR19=606, MR18=3D12
2040 09:27:54.378208 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2041 09:27:54.381638 [RxdqsGatingPostProcess] freq 800
2042 09:27:54.384899 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 09:27:54.388604 Pre-setting of DQS Precalculation
2044 09:27:54.394996 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 09:27:54.401735 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 09:27:54.408421 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 09:27:54.408530
2048 09:27:54.408600
2049 09:27:54.412252 [Calibration Summary] 1600 Mbps
2050 09:27:54.412346 CH 0, Rank 0
2051 09:27:54.415057 SW Impedance : PASS
2052 09:27:54.418518 DUTY Scan : NO K
2053 09:27:54.418609 ZQ Calibration : PASS
2054 09:27:54.421592 Jitter Meter : NO K
2055 09:27:54.425436 CBT Training : PASS
2056 09:27:54.425526 Write leveling : PASS
2057 09:27:54.428577 RX DQS gating : PASS
2058 09:27:54.431782 RX DQ/DQS(RDDQC) : PASS
2059 09:27:54.431871 TX DQ/DQS : PASS
2060 09:27:54.435767 RX DATLAT : PASS
2061 09:27:54.435870 RX DQ/DQS(Engine): PASS
2062 09:27:54.438503 TX OE : NO K
2063 09:27:54.438591 All Pass.
2064 09:27:54.438659
2065 09:27:54.441734 CH 0, Rank 1
2066 09:27:54.441826 SW Impedance : PASS
2067 09:27:54.445047 DUTY Scan : NO K
2068 09:27:54.448348 ZQ Calibration : PASS
2069 09:27:54.448440 Jitter Meter : NO K
2070 09:27:54.452007 CBT Training : PASS
2071 09:27:54.455302 Write leveling : PASS
2072 09:27:54.455392 RX DQS gating : PASS
2073 09:27:54.458493 RX DQ/DQS(RDDQC) : PASS
2074 09:27:54.461715 TX DQ/DQS : PASS
2075 09:27:54.461806 RX DATLAT : PASS
2076 09:27:54.465505 RX DQ/DQS(Engine): PASS
2077 09:27:54.465593 TX OE : NO K
2078 09:27:54.468632 All Pass.
2079 09:27:54.468720
2080 09:27:54.468788 CH 1, Rank 0
2081 09:27:54.472078 SW Impedance : PASS
2082 09:27:54.472165 DUTY Scan : NO K
2083 09:27:54.475173 ZQ Calibration : PASS
2084 09:27:54.478542 Jitter Meter : NO K
2085 09:27:54.478629 CBT Training : PASS
2086 09:27:54.481964 Write leveling : PASS
2087 09:27:54.485466 RX DQS gating : PASS
2088 09:27:54.485554 RX DQ/DQS(RDDQC) : PASS
2089 09:27:54.489096 TX DQ/DQS : PASS
2090 09:27:54.492039 RX DATLAT : PASS
2091 09:27:54.492126 RX DQ/DQS(Engine): PASS
2092 09:27:54.495553 TX OE : NO K
2093 09:27:54.495640 All Pass.
2094 09:27:54.495706
2095 09:27:54.499095 CH 1, Rank 1
2096 09:27:54.499180 SW Impedance : PASS
2097 09:27:54.502482 DUTY Scan : NO K
2098 09:27:54.505309 ZQ Calibration : PASS
2099 09:27:54.505393 Jitter Meter : NO K
2100 09:27:54.508701 CBT Training : PASS
2101 09:27:54.508786 Write leveling : PASS
2102 09:27:54.512600 RX DQS gating : PASS
2103 09:27:54.515618 RX DQ/DQS(RDDQC) : PASS
2104 09:27:54.515705 TX DQ/DQS : PASS
2105 09:27:54.518934 RX DATLAT : PASS
2106 09:27:54.522121 RX DQ/DQS(Engine): PASS
2107 09:27:54.522205 TX OE : NO K
2108 09:27:54.525937 All Pass.
2109 09:27:54.526024
2110 09:27:54.526091 DramC Write-DBI off
2111 09:27:54.528864 PER_BANK_REFRESH: Hybrid Mode
2112 09:27:54.532226 TX_TRACKING: ON
2113 09:27:54.532319 [GetDramInforAfterCalByMRR] Vendor 6.
2114 09:27:54.538638 [GetDramInforAfterCalByMRR] Revision 606.
2115 09:27:54.542413 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 09:27:54.542510 MR0 0x3b3b
2117 09:27:54.542578 MR8 0x5151
2118 09:27:54.545717 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 09:27:54.545806
2120 09:27:54.548730 MR0 0x3b3b
2121 09:27:54.548816 MR8 0x5151
2122 09:27:54.552188 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 09:27:54.552376
2124 09:27:54.562266 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 09:27:54.565602 [FAST_K] Save calibration result to emmc
2126 09:27:54.569270 [FAST_K] Save calibration result to emmc
2127 09:27:54.572225 dram_init: config_dvfs: 1
2128 09:27:54.575292 dramc_set_vcore_voltage set vcore to 662500
2129 09:27:54.578819 Read voltage for 1200, 2
2130 09:27:54.578909 Vio18 = 0
2131 09:27:54.578976 Vcore = 662500
2132 09:27:54.582755 Vdram = 0
2133 09:27:54.582856 Vddq = 0
2134 09:27:54.582951 Vmddr = 0
2135 09:27:54.589281 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 09:27:54.592150 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 09:27:54.595777 MEM_TYPE=3, freq_sel=15
2138 09:27:54.599440 sv_algorithm_assistance_LP4_1600
2139 09:27:54.602053 ============ PULL DRAM RESETB DOWN ============
2140 09:27:54.605397 ========== PULL DRAM RESETB DOWN end =========
2141 09:27:54.612259 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 09:27:54.615725 ===================================
2143 09:27:54.615822 LPDDR4 DRAM CONFIGURATION
2144 09:27:54.619168 ===================================
2145 09:27:54.622436 EX_ROW_EN[0] = 0x0
2146 09:27:54.625645 EX_ROW_EN[1] = 0x0
2147 09:27:54.625734 LP4Y_EN = 0x0
2148 09:27:54.628880 WORK_FSP = 0x0
2149 09:27:54.629004 WL = 0x4
2150 09:27:54.632429 RL = 0x4
2151 09:27:54.632521 BL = 0x2
2152 09:27:54.635828 RPST = 0x0
2153 09:27:54.635950 RD_PRE = 0x0
2154 09:27:54.639198 WR_PRE = 0x1
2155 09:27:54.639300 WR_PST = 0x0
2156 09:27:54.642619 DBI_WR = 0x0
2157 09:27:54.642732 DBI_RD = 0x0
2158 09:27:54.646338 OTF = 0x1
2159 09:27:54.649174 ===================================
2160 09:27:54.652494 ===================================
2161 09:27:54.652605 ANA top config
2162 09:27:54.655955 ===================================
2163 09:27:54.658734 DLL_ASYNC_EN = 0
2164 09:27:54.662259 ALL_SLAVE_EN = 0
2165 09:27:54.662370 NEW_RANK_MODE = 1
2166 09:27:54.665586 DLL_IDLE_MODE = 1
2167 09:27:54.668796 LP45_APHY_COMB_EN = 1
2168 09:27:54.672191 TX_ODT_DIS = 1
2169 09:27:54.672299 NEW_8X_MODE = 1
2170 09:27:54.675670 ===================================
2171 09:27:54.679099 ===================================
2172 09:27:54.682393 data_rate = 2400
2173 09:27:54.685930 CKR = 1
2174 09:27:54.688906 DQ_P2S_RATIO = 8
2175 09:27:54.692205 ===================================
2176 09:27:54.695661 CA_P2S_RATIO = 8
2177 09:27:54.699081 DQ_CA_OPEN = 0
2178 09:27:54.699194 DQ_SEMI_OPEN = 0
2179 09:27:54.702964 CA_SEMI_OPEN = 0
2180 09:27:54.705791 CA_FULL_RATE = 0
2181 09:27:54.709228 DQ_CKDIV4_EN = 0
2182 09:27:54.712555 CA_CKDIV4_EN = 0
2183 09:27:54.715905 CA_PREDIV_EN = 0
2184 09:27:54.716015 PH8_DLY = 17
2185 09:27:54.719555 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 09:27:54.722398 DQ_AAMCK_DIV = 4
2187 09:27:54.726291 CA_AAMCK_DIV = 4
2188 09:27:54.729233 CA_ADMCK_DIV = 4
2189 09:27:54.732666 DQ_TRACK_CA_EN = 0
2190 09:27:54.732852 CA_PICK = 1200
2191 09:27:54.736099 CA_MCKIO = 1200
2192 09:27:54.739127 MCKIO_SEMI = 0
2193 09:27:54.742803 PLL_FREQ = 2366
2194 09:27:54.745810 DQ_UI_PI_RATIO = 32
2195 09:27:54.749575 CA_UI_PI_RATIO = 0
2196 09:27:54.752793 ===================================
2197 09:27:54.756142 ===================================
2198 09:27:54.756255 memory_type:LPDDR4
2199 09:27:54.759127 GP_NUM : 10
2200 09:27:54.762454 SRAM_EN : 1
2201 09:27:54.762575 MD32_EN : 0
2202 09:27:54.765912 ===================================
2203 09:27:54.769252 [ANA_INIT] >>>>>>>>>>>>>>
2204 09:27:54.772461 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 09:27:54.776186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 09:27:54.779472 ===================================
2207 09:27:54.782507 data_rate = 2400,PCW = 0X5b00
2208 09:27:54.786137 ===================================
2209 09:27:54.789166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 09:27:54.792551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 09:27:54.799591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 09:27:54.803331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 09:27:54.806182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 09:27:54.809442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 09:27:54.812962 [ANA_INIT] flow start
2216 09:27:54.816195 [ANA_INIT] PLL >>>>>>>>
2217 09:27:54.816303 [ANA_INIT] PLL <<<<<<<<
2218 09:27:54.819483 [ANA_INIT] MIDPI >>>>>>>>
2219 09:27:54.822905 [ANA_INIT] MIDPI <<<<<<<<
2220 09:27:54.822998 [ANA_INIT] DLL >>>>>>>>
2221 09:27:54.826177 [ANA_INIT] DLL <<<<<<<<
2222 09:27:54.829389 [ANA_INIT] flow end
2223 09:27:54.832969 ============ LP4 DIFF to SE enter ============
2224 09:27:54.836467 ============ LP4 DIFF to SE exit ============
2225 09:27:54.839407 [ANA_INIT] <<<<<<<<<<<<<
2226 09:27:54.842861 [Flow] Enable top DCM control >>>>>
2227 09:27:54.846468 [Flow] Enable top DCM control <<<<<
2228 09:27:54.849858 Enable DLL master slave shuffle
2229 09:27:54.852851 ==============================================================
2230 09:27:54.856536 Gating Mode config
2231 09:27:54.862691 ==============================================================
2232 09:27:54.862793 Config description:
2233 09:27:54.872799 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 09:27:54.879523 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 09:27:54.882828 SELPH_MODE 0: By rank 1: By Phase
2236 09:27:54.889800 ==============================================================
2237 09:27:54.892635 GAT_TRACK_EN = 1
2238 09:27:54.896383 RX_GATING_MODE = 2
2239 09:27:54.899358 RX_GATING_TRACK_MODE = 2
2240 09:27:54.902950 SELPH_MODE = 1
2241 09:27:54.906341 PICG_EARLY_EN = 1
2242 09:27:54.909660 VALID_LAT_VALUE = 1
2243 09:27:54.912793 ==============================================================
2244 09:27:54.916531 Enter into Gating configuration >>>>
2245 09:27:54.919876 Exit from Gating configuration <<<<
2246 09:27:54.923126 Enter into DVFS_PRE_config >>>>>
2247 09:27:54.932943 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 09:27:54.936203 Exit from DVFS_PRE_config <<<<<
2249 09:27:54.939500 Enter into PICG configuration >>>>
2250 09:27:54.942879 Exit from PICG configuration <<<<
2251 09:27:54.946317 [RX_INPUT] configuration >>>>>
2252 09:27:54.949808 [RX_INPUT] configuration <<<<<
2253 09:27:54.956572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 09:27:54.959331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 09:27:54.966094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 09:27:54.973239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 09:27:54.979654 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 09:27:54.986268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 09:27:54.989898 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 09:27:54.992889 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 09:27:54.996307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 09:27:54.999430 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 09:27:55.006215 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 09:27:55.009647 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 09:27:55.012911 ===================================
2266 09:27:55.016787 LPDDR4 DRAM CONFIGURATION
2267 09:27:55.019643 ===================================
2268 09:27:55.019733 EX_ROW_EN[0] = 0x0
2269 09:27:55.022861 EX_ROW_EN[1] = 0x0
2270 09:27:55.022945 LP4Y_EN = 0x0
2271 09:27:55.027211 WORK_FSP = 0x0
2272 09:27:55.027297 WL = 0x4
2273 09:27:55.029865 RL = 0x4
2274 09:27:55.029969 BL = 0x2
2275 09:27:55.033171 RPST = 0x0
2276 09:27:55.033254 RD_PRE = 0x0
2277 09:27:55.036481 WR_PRE = 0x1
2278 09:27:55.036564 WR_PST = 0x0
2279 09:27:55.039842 DBI_WR = 0x0
2280 09:27:55.039927 DBI_RD = 0x0
2281 09:27:55.043044 OTF = 0x1
2282 09:27:55.046499 ===================================
2283 09:27:55.049924 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 09:27:55.053865 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 09:27:55.060292 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 09:27:55.063342 ===================================
2287 09:27:55.063433 LPDDR4 DRAM CONFIGURATION
2288 09:27:55.066324 ===================================
2289 09:27:55.069917 EX_ROW_EN[0] = 0x10
2290 09:27:55.073167 EX_ROW_EN[1] = 0x0
2291 09:27:55.073253 LP4Y_EN = 0x0
2292 09:27:55.076764 WORK_FSP = 0x0
2293 09:27:55.076847 WL = 0x4
2294 09:27:55.079922 RL = 0x4
2295 09:27:55.080005 BL = 0x2
2296 09:27:55.083268 RPST = 0x0
2297 09:27:55.083352 RD_PRE = 0x0
2298 09:27:55.086313 WR_PRE = 0x1
2299 09:27:55.086408 WR_PST = 0x0
2300 09:27:55.089905 DBI_WR = 0x0
2301 09:27:55.089989 DBI_RD = 0x0
2302 09:27:55.093298 OTF = 0x1
2303 09:27:55.096509 ===================================
2304 09:27:55.103411 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 09:27:55.103514 ==
2306 09:27:55.106662 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 09:27:55.110199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 09:27:55.110303 ==
2309 09:27:55.113268 [Duty_Offset_Calibration]
2310 09:27:55.113351 B0:2 B1:0 CA:1
2311 09:27:55.113415
2312 09:27:55.116428 [DutyScan_Calibration_Flow] k_type=0
2313 09:27:55.126222
2314 09:27:55.126350 ==CLK 0==
2315 09:27:55.129598 Final CLK duty delay cell = -4
2316 09:27:55.132807 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2317 09:27:55.135925 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2318 09:27:55.138939 [-4] AVG Duty = 4953%(X100)
2319 09:27:55.139022
2320 09:27:55.142314 CH0 CLK Duty spec in!! Max-Min= 156%
2321 09:27:55.145847 [DutyScan_Calibration_Flow] ====Done====
2322 09:27:55.145949
2323 09:27:55.149123 [DutyScan_Calibration_Flow] k_type=1
2324 09:27:55.164678
2325 09:27:55.164820 ==DQS 0 ==
2326 09:27:55.167822 Final DQS duty delay cell = 0
2327 09:27:55.171357 [0] MAX Duty = 5187%(X100), DQS PI = 30
2328 09:27:55.174811 [0] MIN Duty = 4938%(X100), DQS PI = 0
2329 09:27:55.174896 [0] AVG Duty = 5062%(X100)
2330 09:27:55.178415
2331 09:27:55.178498 ==DQS 1 ==
2332 09:27:55.181754 Final DQS duty delay cell = -4
2333 09:27:55.184615 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2334 09:27:55.187895 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2335 09:27:55.191383 [-4] AVG Duty = 5015%(X100)
2336 09:27:55.191468
2337 09:27:55.194599 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2338 09:27:55.194685
2339 09:27:55.198482 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2340 09:27:55.201450 [DutyScan_Calibration_Flow] ====Done====
2341 09:27:55.201538
2342 09:27:55.204896 [DutyScan_Calibration_Flow] k_type=3
2343 09:27:55.221720
2344 09:27:55.221870 ==DQM 0 ==
2345 09:27:55.224819 Final DQM duty delay cell = 0
2346 09:27:55.228014 [0] MAX Duty = 5062%(X100), DQS PI = 24
2347 09:27:55.231655 [0] MIN Duty = 4844%(X100), DQS PI = 0
2348 09:27:55.231743 [0] AVG Duty = 4953%(X100)
2349 09:27:55.234681
2350 09:27:55.234761 ==DQM 1 ==
2351 09:27:55.238195 Final DQM duty delay cell = 0
2352 09:27:55.241375 [0] MAX Duty = 5187%(X100), DQS PI = 46
2353 09:27:55.244990 [0] MIN Duty = 5000%(X100), DQS PI = 22
2354 09:27:55.245091 [0] AVG Duty = 5093%(X100)
2355 09:27:55.248386
2356 09:27:55.251574 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2357 09:27:55.251661
2358 09:27:55.255243 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 09:27:55.258609 [DutyScan_Calibration_Flow] ====Done====
2360 09:27:55.258706
2361 09:27:55.261563 [DutyScan_Calibration_Flow] k_type=2
2362 09:27:55.278328
2363 09:27:55.278476 ==DQ 0 ==
2364 09:27:55.281832 Final DQ duty delay cell = -4
2365 09:27:55.285185 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2366 09:27:55.287941 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2367 09:27:55.291601 [-4] AVG Duty = 4953%(X100)
2368 09:27:55.291688
2369 09:27:55.291752 ==DQ 1 ==
2370 09:27:55.295272 Final DQ duty delay cell = 4
2371 09:27:55.298172 [4] MAX Duty = 5124%(X100), DQS PI = 54
2372 09:27:55.301835 [4] MIN Duty = 5031%(X100), DQS PI = 0
2373 09:27:55.301925 [4] AVG Duty = 5077%(X100)
2374 09:27:55.301990
2375 09:27:55.305009 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2376 09:27:55.308271
2377 09:27:55.311416 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2378 09:27:55.314878 [DutyScan_Calibration_Flow] ====Done====
2379 09:27:55.314984 ==
2380 09:27:55.318080 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 09:27:55.321447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 09:27:55.321535 ==
2383 09:27:55.324958 [Duty_Offset_Calibration]
2384 09:27:55.325103 B0:0 B1:-1 CA:2
2385 09:27:55.325169
2386 09:27:55.328891 [DutyScan_Calibration_Flow] k_type=0
2387 09:27:55.338424
2388 09:27:55.338540 ==CLK 0==
2389 09:27:55.341662 Final CLK duty delay cell = 0
2390 09:27:55.344846 [0] MAX Duty = 5156%(X100), DQS PI = 16
2391 09:27:55.348284 [0] MIN Duty = 4938%(X100), DQS PI = 44
2392 09:27:55.348376 [0] AVG Duty = 5047%(X100)
2393 09:27:55.352004
2394 09:27:55.354842 CH1 CLK Duty spec in!! Max-Min= 218%
2395 09:27:55.358260 [DutyScan_Calibration_Flow] ====Done====
2396 09:27:55.358346
2397 09:27:55.361706 [DutyScan_Calibration_Flow] k_type=1
2398 09:27:55.377768
2399 09:27:55.377904 ==DQS 0 ==
2400 09:27:55.380813 Final DQS duty delay cell = 0
2401 09:27:55.384478 [0] MAX Duty = 5093%(X100), DQS PI = 24
2402 09:27:55.387518 [0] MIN Duty = 4969%(X100), DQS PI = 0
2403 09:27:55.387607 [0] AVG Duty = 5031%(X100)
2404 09:27:55.391106
2405 09:27:55.391203 ==DQS 1 ==
2406 09:27:55.394325 Final DQS duty delay cell = 0
2407 09:27:55.397566 [0] MAX Duty = 5156%(X100), DQS PI = 0
2408 09:27:55.401122 [0] MIN Duty = 4875%(X100), DQS PI = 34
2409 09:27:55.401230 [0] AVG Duty = 5015%(X100)
2410 09:27:55.401317
2411 09:27:55.407660 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2412 09:27:55.407757
2413 09:27:55.410917 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2414 09:27:55.414341 [DutyScan_Calibration_Flow] ====Done====
2415 09:27:55.414430
2416 09:27:55.417989 [DutyScan_Calibration_Flow] k_type=3
2417 09:27:55.434288
2418 09:27:55.434437 ==DQM 0 ==
2419 09:27:55.437684 Final DQM duty delay cell = 4
2420 09:27:55.440598 [4] MAX Duty = 5093%(X100), DQS PI = 4
2421 09:27:55.443953 [4] MIN Duty = 4969%(X100), DQS PI = 28
2422 09:27:55.444048 [4] AVG Duty = 5031%(X100)
2423 09:27:55.447500
2424 09:27:55.447589 ==DQM 1 ==
2425 09:27:55.450778 Final DQM duty delay cell = -4
2426 09:27:55.453993 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2427 09:27:55.457524 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2428 09:27:55.460863 [-4] AVG Duty = 4860%(X100)
2429 09:27:55.461018
2430 09:27:55.464197 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2431 09:27:55.464284
2432 09:27:55.467969 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2433 09:27:55.470821 [DutyScan_Calibration_Flow] ====Done====
2434 09:27:55.470906
2435 09:27:55.474189 [DutyScan_Calibration_Flow] k_type=2
2436 09:27:55.490819
2437 09:27:55.490969 ==DQ 0 ==
2438 09:27:55.494223 Final DQ duty delay cell = 0
2439 09:27:55.498079 [0] MAX Duty = 5062%(X100), DQS PI = 18
2440 09:27:55.501298 [0] MIN Duty = 4938%(X100), DQS PI = 46
2441 09:27:55.501392 [0] AVG Duty = 5000%(X100)
2442 09:27:55.501458
2443 09:27:55.504377 ==DQ 1 ==
2444 09:27:55.507894 Final DQ duty delay cell = 0
2445 09:27:55.510840 [0] MAX Duty = 5031%(X100), DQS PI = 2
2446 09:27:55.514982 [0] MIN Duty = 4813%(X100), DQS PI = 34
2447 09:27:55.515076 [0] AVG Duty = 4922%(X100)
2448 09:27:55.515143
2449 09:27:55.517882 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2450 09:27:55.517969
2451 09:27:55.521186 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2452 09:27:55.527982 [DutyScan_Calibration_Flow] ====Done====
2453 09:27:55.530915 nWR fixed to 30
2454 09:27:55.531013 [ModeRegInit_LP4] CH0 RK0
2455 09:27:55.534322 [ModeRegInit_LP4] CH0 RK1
2456 09:27:55.537692 [ModeRegInit_LP4] CH1 RK0
2457 09:27:55.537781 [ModeRegInit_LP4] CH1 RK1
2458 09:27:55.541741 match AC timing 7
2459 09:27:55.544436 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 09:27:55.547571 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 09:27:55.554286 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 09:27:55.557881 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 09:27:55.564269 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 09:27:55.564381 ==
2465 09:27:55.567755 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 09:27:55.571376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 09:27:55.571467 ==
2468 09:27:55.578026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 09:27:55.580862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2470 09:27:55.590748 [CA 0] Center 38 (8~69) winsize 62
2471 09:27:55.594223 [CA 1] Center 38 (8~69) winsize 62
2472 09:27:55.597326 [CA 2] Center 35 (4~66) winsize 63
2473 09:27:55.600937 [CA 3] Center 35 (4~66) winsize 63
2474 09:27:55.603969 [CA 4] Center 34 (4~65) winsize 62
2475 09:27:55.607525 [CA 5] Center 33 (3~63) winsize 61
2476 09:27:55.607623
2477 09:27:55.611027 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 09:27:55.611116
2479 09:27:55.614526 [CATrainingPosCal] consider 1 rank data
2480 09:27:55.617525 u2DelayCellTimex100 = 270/100 ps
2481 09:27:55.620814 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2482 09:27:55.624575 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2483 09:27:55.627727 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2484 09:27:55.634386 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2485 09:27:55.637764 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2486 09:27:55.641274 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 09:27:55.641373
2488 09:27:55.644617 CA PerBit enable=1, Macro0, CA PI delay=33
2489 09:27:55.644709
2490 09:27:55.647997 [CBTSetCACLKResult] CA Dly = 33
2491 09:27:55.648092 CS Dly: 6 (0~37)
2492 09:27:55.648160 ==
2493 09:27:55.651435 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 09:27:55.657645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 09:27:55.657748 ==
2496 09:27:55.661122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 09:27:55.669245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2498 09:27:55.676405 [CA 0] Center 39 (8~70) winsize 63
2499 09:27:55.679923 [CA 1] Center 38 (8~69) winsize 62
2500 09:27:55.683106 [CA 2] Center 35 (5~66) winsize 62
2501 09:27:55.686611 [CA 3] Center 35 (5~66) winsize 62
2502 09:27:55.690075 [CA 4] Center 34 (4~65) winsize 62
2503 09:27:55.693271 [CA 5] Center 34 (4~64) winsize 61
2504 09:27:55.693364
2505 09:27:55.696758 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2506 09:27:55.696848
2507 09:27:55.699896 [CATrainingPosCal] consider 2 rank data
2508 09:27:55.703876 u2DelayCellTimex100 = 270/100 ps
2509 09:27:55.706779 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2510 09:27:55.709918 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2511 09:27:55.713428 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 09:27:55.720016 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 09:27:55.723708 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2514 09:27:55.726691 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2515 09:27:55.726784
2516 09:27:55.729983 CA PerBit enable=1, Macro0, CA PI delay=33
2517 09:27:55.730072
2518 09:27:55.733603 [CBTSetCACLKResult] CA Dly = 33
2519 09:27:55.733692 CS Dly: 7 (0~39)
2520 09:27:55.733760
2521 09:27:55.736843 ----->DramcWriteLeveling(PI) begin...
2522 09:27:55.736941 ==
2523 09:27:55.740001 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 09:27:55.746971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 09:27:55.747094 ==
2526 09:27:55.750034 Write leveling (Byte 0): 36 => 36
2527 09:27:55.753400 Write leveling (Byte 1): 31 => 31
2528 09:27:55.753495 DramcWriteLeveling(PI) end<-----
2529 09:27:55.753565
2530 09:27:55.756830 ==
2531 09:27:55.760103 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 09:27:55.763339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 09:27:55.763431 ==
2534 09:27:55.766994 [Gating] SW mode calibration
2535 09:27:55.773632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 09:27:55.776520 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 09:27:55.783515 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2538 09:27:55.786729 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2539 09:27:55.790296 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 09:27:55.796868 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 09:27:55.800245 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 09:27:55.803362 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 09:27:55.810578 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2544 09:27:55.813721 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
2545 09:27:55.817351 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2546 09:27:55.820388 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 09:27:55.826974 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 09:27:55.830566 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 09:27:55.833609 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 09:27:55.840276 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 09:27:55.843778 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
2552 09:27:55.847269 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2553 09:27:55.853975 1 1 0 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
2554 09:27:55.857278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 09:27:55.860718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 09:27:55.867715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 09:27:55.870819 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 09:27:55.873850 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 09:27:55.880682 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 09:27:55.884175 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 09:27:55.887563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 09:27:55.894189 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:27:55.897636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:27:55.900594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 09:27:55.903802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 09:27:55.910488 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 09:27:55.913996 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 09:27:55.916905 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 09:27:55.923851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 09:27:55.927434 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 09:27:55.930779 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 09:27:55.937251 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 09:27:55.940296 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 09:27:55.943867 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 09:27:55.950870 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 09:27:55.953691 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2577 09:27:55.957254 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 09:27:55.960569 Total UI for P1: 0, mck2ui 16
2579 09:27:55.964239 best dqsien dly found for B0: ( 1, 3, 28)
2580 09:27:55.970420 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 09:27:55.970526 Total UI for P1: 0, mck2ui 16
2582 09:27:55.973687 best dqsien dly found for B1: ( 1, 3, 30)
2583 09:27:55.980943 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2584 09:27:55.983859 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2585 09:27:55.983954
2586 09:27:55.987272 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2587 09:27:55.990943 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2588 09:27:55.994359 [Gating] SW calibration Done
2589 09:27:55.994449 ==
2590 09:27:55.997152 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 09:27:56.000836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 09:27:56.000926 ==
2593 09:27:56.001001 RX Vref Scan: 0
2594 09:27:56.004439
2595 09:27:56.004524 RX Vref 0 -> 0, step: 1
2596 09:27:56.004589
2597 09:27:56.007183 RX Delay -40 -> 252, step: 8
2598 09:27:56.010647 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2599 09:27:56.013883 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2600 09:27:56.021187 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2601 09:27:56.024410 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2602 09:27:56.027560 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2603 09:27:56.030676 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2604 09:27:56.034151 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2605 09:27:56.040716 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2606 09:27:56.044330 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2607 09:27:56.047770 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2608 09:27:56.050595 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2609 09:27:56.054753 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2610 09:27:56.060794 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2611 09:27:56.064432 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2612 09:27:56.067705 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2613 09:27:56.070886 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2614 09:27:56.070978 ==
2615 09:27:56.074289 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 09:27:56.077462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 09:27:56.081037 ==
2618 09:27:56.081133 DQS Delay:
2619 09:27:56.081202 DQS0 = 0, DQS1 = 0
2620 09:27:56.084312 DQM Delay:
2621 09:27:56.084415 DQM0 = 122, DQM1 = 110
2622 09:27:56.087563 DQ Delay:
2623 09:27:56.091028 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2624 09:27:56.094139 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2625 09:27:56.097708 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2626 09:27:56.100875 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2627 09:27:56.100970
2628 09:27:56.101037
2629 09:27:56.101098 ==
2630 09:27:56.104419 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 09:27:56.108121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 09:27:56.108208 ==
2633 09:27:56.108275
2634 09:27:56.108336
2635 09:27:56.110880 TX Vref Scan disable
2636 09:27:56.114480 == TX Byte 0 ==
2637 09:27:56.117412 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2638 09:27:56.120886 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2639 09:27:56.124249 == TX Byte 1 ==
2640 09:27:56.127934 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2641 09:27:56.131553 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2642 09:27:56.131647 ==
2643 09:27:56.134183 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 09:27:56.137922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 09:27:56.140887 ==
2646 09:27:56.151470 TX Vref=22, minBit 4, minWin=24, winSum=411
2647 09:27:56.155091 TX Vref=24, minBit 1, minWin=25, winSum=417
2648 09:27:56.158201 TX Vref=26, minBit 0, minWin=24, winSum=420
2649 09:27:56.161594 TX Vref=28, minBit 0, minWin=26, winSum=426
2650 09:27:56.164975 TX Vref=30, minBit 5, minWin=25, winSum=426
2651 09:27:56.168354 TX Vref=32, minBit 0, minWin=25, winSum=416
2652 09:27:56.174899 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
2653 09:27:56.175014
2654 09:27:56.178238 Final TX Range 1 Vref 28
2655 09:27:56.178326
2656 09:27:56.178393 ==
2657 09:27:56.181486 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 09:27:56.185532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 09:27:56.185624 ==
2660 09:27:56.185691
2661 09:27:56.185751
2662 09:27:56.188405 TX Vref Scan disable
2663 09:27:56.191686 == TX Byte 0 ==
2664 09:27:56.195213 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2665 09:27:56.198696 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2666 09:27:56.201640 == TX Byte 1 ==
2667 09:27:56.205178 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2668 09:27:56.208741 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2669 09:27:56.208832
2670 09:27:56.211877 [DATLAT]
2671 09:27:56.211963 Freq=1200, CH0 RK0
2672 09:27:56.212030
2673 09:27:56.214985 DATLAT Default: 0xd
2674 09:27:56.215070 0, 0xFFFF, sum = 0
2675 09:27:56.218842 1, 0xFFFF, sum = 0
2676 09:27:56.218932 2, 0xFFFF, sum = 0
2677 09:27:56.222317 3, 0xFFFF, sum = 0
2678 09:27:56.222405 4, 0xFFFF, sum = 0
2679 09:27:56.225368 5, 0xFFFF, sum = 0
2680 09:27:56.225454 6, 0xFFFF, sum = 0
2681 09:27:56.228723 7, 0xFFFF, sum = 0
2682 09:27:56.228811 8, 0xFFFF, sum = 0
2683 09:27:56.231760 9, 0xFFFF, sum = 0
2684 09:27:56.231848 10, 0xFFFF, sum = 0
2685 09:27:56.235174 11, 0xFFFF, sum = 0
2686 09:27:56.235261 12, 0x0, sum = 1
2687 09:27:56.238696 13, 0x0, sum = 2
2688 09:27:56.238783 14, 0x0, sum = 3
2689 09:27:56.241685 15, 0x0, sum = 4
2690 09:27:56.241771 best_step = 13
2691 09:27:56.241837
2692 09:27:56.241898 ==
2693 09:27:56.245413 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 09:27:56.252115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 09:27:56.252228 ==
2696 09:27:56.252298 RX Vref Scan: 1
2697 09:27:56.252362
2698 09:27:56.255341 Set Vref Range= 32 -> 127
2699 09:27:56.255428
2700 09:27:56.258597 RX Vref 32 -> 127, step: 1
2701 09:27:56.258684
2702 09:27:56.258752 RX Delay -13 -> 252, step: 4
2703 09:27:56.261990
2704 09:27:56.262079 Set Vref, RX VrefLevel [Byte0]: 32
2705 09:27:56.265605 [Byte1]: 32
2706 09:27:56.269529
2707 09:27:56.269624 Set Vref, RX VrefLevel [Byte0]: 33
2708 09:27:56.272922 [Byte1]: 33
2709 09:27:56.277449
2710 09:27:56.277545 Set Vref, RX VrefLevel [Byte0]: 34
2711 09:27:56.284011 [Byte1]: 34
2712 09:27:56.284114
2713 09:27:56.287277 Set Vref, RX VrefLevel [Byte0]: 35
2714 09:27:56.290767 [Byte1]: 35
2715 09:27:56.290861
2716 09:27:56.294191 Set Vref, RX VrefLevel [Byte0]: 36
2717 09:27:56.297264 [Byte1]: 36
2718 09:27:56.301337
2719 09:27:56.301433 Set Vref, RX VrefLevel [Byte0]: 37
2720 09:27:56.304815 [Byte1]: 37
2721 09:27:56.309310
2722 09:27:56.309406 Set Vref, RX VrefLevel [Byte0]: 38
2723 09:27:56.312786 [Byte1]: 38
2724 09:27:56.317222
2725 09:27:56.317318 Set Vref, RX VrefLevel [Byte0]: 39
2726 09:27:56.320368 [Byte1]: 39
2727 09:27:56.324790
2728 09:27:56.324877 Set Vref, RX VrefLevel [Byte0]: 40
2729 09:27:56.328212 [Byte1]: 40
2730 09:27:56.332889
2731 09:27:56.332993 Set Vref, RX VrefLevel [Byte0]: 41
2732 09:27:56.336331 [Byte1]: 41
2733 09:27:56.340809
2734 09:27:56.340901 Set Vref, RX VrefLevel [Byte0]: 42
2735 09:27:56.344173 [Byte1]: 42
2736 09:27:56.348479
2737 09:27:56.348579 Set Vref, RX VrefLevel [Byte0]: 43
2738 09:27:56.352258 [Byte1]: 43
2739 09:27:56.356940
2740 09:27:56.357048 Set Vref, RX VrefLevel [Byte0]: 44
2741 09:27:56.360031 [Byte1]: 44
2742 09:27:56.364849
2743 09:27:56.364953 Set Vref, RX VrefLevel [Byte0]: 45
2744 09:27:56.367901 [Byte1]: 45
2745 09:27:56.372469
2746 09:27:56.372558 Set Vref, RX VrefLevel [Byte0]: 46
2747 09:27:56.375349 [Byte1]: 46
2748 09:27:56.379890
2749 09:27:56.383370 Set Vref, RX VrefLevel [Byte0]: 47
2750 09:27:56.383468 [Byte1]: 47
2751 09:27:56.387933
2752 09:27:56.388027 Set Vref, RX VrefLevel [Byte0]: 48
2753 09:27:56.391603 [Byte1]: 48
2754 09:27:56.395866
2755 09:27:56.395957 Set Vref, RX VrefLevel [Byte0]: 49
2756 09:27:56.399585 [Byte1]: 49
2757 09:27:56.403848
2758 09:27:56.403941 Set Vref, RX VrefLevel [Byte0]: 50
2759 09:27:56.407009 [Byte1]: 50
2760 09:27:56.411983
2761 09:27:56.412083 Set Vref, RX VrefLevel [Byte0]: 51
2762 09:27:56.415364 [Byte1]: 51
2763 09:27:56.419658
2764 09:27:56.419757 Set Vref, RX VrefLevel [Byte0]: 52
2765 09:27:56.423208 [Byte1]: 52
2766 09:27:56.427706
2767 09:27:56.427800 Set Vref, RX VrefLevel [Byte0]: 53
2768 09:27:56.430686 [Byte1]: 53
2769 09:27:56.435350
2770 09:27:56.435445 Set Vref, RX VrefLevel [Byte0]: 54
2771 09:27:56.438415 [Byte1]: 54
2772 09:27:56.443282
2773 09:27:56.443377 Set Vref, RX VrefLevel [Byte0]: 55
2774 09:27:56.446744 [Byte1]: 55
2775 09:27:56.451607
2776 09:27:56.451710 Set Vref, RX VrefLevel [Byte0]: 56
2777 09:27:56.454434 [Byte1]: 56
2778 09:27:56.458942
2779 09:27:56.459034 Set Vref, RX VrefLevel [Byte0]: 57
2780 09:27:56.462404 [Byte1]: 57
2781 09:27:56.467142
2782 09:27:56.467239 Set Vref, RX VrefLevel [Byte0]: 58
2783 09:27:56.470219 [Byte1]: 58
2784 09:27:56.474926
2785 09:27:56.475017 Set Vref, RX VrefLevel [Byte0]: 59
2786 09:27:56.478201 [Byte1]: 59
2787 09:27:56.483455
2788 09:27:56.483553 Set Vref, RX VrefLevel [Byte0]: 60
2789 09:27:56.486312 [Byte1]: 60
2790 09:27:56.490791
2791 09:27:56.490884 Set Vref, RX VrefLevel [Byte0]: 61
2792 09:27:56.494122 [Byte1]: 61
2793 09:27:56.498534
2794 09:27:56.498627 Set Vref, RX VrefLevel [Byte0]: 62
2795 09:27:56.501628 [Byte1]: 62
2796 09:27:56.506208
2797 09:27:56.506298 Set Vref, RX VrefLevel [Byte0]: 63
2798 09:27:56.509884 [Byte1]: 63
2799 09:27:56.514304
2800 09:27:56.514414 Set Vref, RX VrefLevel [Byte0]: 64
2801 09:27:56.517647 [Byte1]: 64
2802 09:27:56.522090
2803 09:27:56.522185 Set Vref, RX VrefLevel [Byte0]: 65
2804 09:27:56.525502 [Byte1]: 65
2805 09:27:56.529839
2806 09:27:56.529930 Set Vref, RX VrefLevel [Byte0]: 66
2807 09:27:56.533812 [Byte1]: 66
2808 09:27:56.537935
2809 09:27:56.538026 Set Vref, RX VrefLevel [Byte0]: 67
2810 09:27:56.541330 [Byte1]: 67
2811 09:27:56.545814
2812 09:27:56.545952 Set Vref, RX VrefLevel [Byte0]: 68
2813 09:27:56.549197 [Byte1]: 68
2814 09:27:56.553678
2815 09:27:56.553767 Set Vref, RX VrefLevel [Byte0]: 69
2816 09:27:56.557069 [Byte1]: 69
2817 09:27:56.561529
2818 09:27:56.561676 Set Vref, RX VrefLevel [Byte0]: 70
2819 09:27:56.565256 [Byte1]: 70
2820 09:27:56.569688
2821 09:27:56.569779 Final RX Vref Byte 0 = 60 to rank0
2822 09:27:56.572987 Final RX Vref Byte 1 = 51 to rank0
2823 09:27:56.576023 Final RX Vref Byte 0 = 60 to rank1
2824 09:27:56.579373 Final RX Vref Byte 1 = 51 to rank1==
2825 09:27:56.583640 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 09:27:56.589262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 09:27:56.589427 ==
2828 09:27:56.589497 DQS Delay:
2829 09:27:56.589558 DQS0 = 0, DQS1 = 0
2830 09:27:56.592980 DQM Delay:
2831 09:27:56.593067 DQM0 = 123, DQM1 = 109
2832 09:27:56.596249 DQ Delay:
2833 09:27:56.599392 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2834 09:27:56.602794 DQ4 =126, DQ5 =116, DQ6 =132, DQ7 =128
2835 09:27:56.606473 DQ8 =102, DQ9 =96, DQ10 =110, DQ11 =106
2836 09:27:56.609695 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2837 09:27:56.609786
2838 09:27:56.609852
2839 09:27:56.616191 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2840 09:27:56.619662 CH0 RK0: MR19=404, MR18=906
2841 09:27:56.626706 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2842 09:27:56.626847
2843 09:27:56.629322 ----->DramcWriteLeveling(PI) begin...
2844 09:27:56.629435 ==
2845 09:27:56.633081 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 09:27:56.636530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 09:27:56.636619 ==
2848 09:27:56.639410 Write leveling (Byte 0): 33 => 33
2849 09:27:56.642854 Write leveling (Byte 1): 32 => 32
2850 09:27:56.646323 DramcWriteLeveling(PI) end<-----
2851 09:27:56.646415
2852 09:27:56.646482 ==
2853 09:27:56.649548 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 09:27:56.652945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 09:27:56.656343 ==
2856 09:27:56.656431 [Gating] SW mode calibration
2857 09:27:56.666372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 09:27:56.669699 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 09:27:56.673145 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2860 09:27:56.679780 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 09:27:56.683017 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 09:27:56.686501 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 09:27:56.693053 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 09:27:56.696423 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 09:27:56.699782 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2866 09:27:56.706295 0 15 28 | B1->B0 | 2e2e 2a2a | 1 1 | (1 1) (1 0)
2867 09:27:56.709723 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2868 09:27:56.713216 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 09:27:56.716357 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 09:27:56.723332 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 09:27:56.726240 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 09:27:56.729808 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 09:27:56.736465 1 0 24 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
2874 09:27:56.739989 1 0 28 | B1->B0 | 3636 3c3c | 0 1 | (0 0) (0 0)
2875 09:27:56.743432 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 09:27:56.750534 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 09:27:56.753620 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 09:27:56.756583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 09:27:56.763295 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 09:27:56.766737 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 09:27:56.770316 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 09:27:56.776725 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 09:27:56.779865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 09:27:56.783381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 09:27:56.786900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 09:27:56.793207 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 09:27:56.796825 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 09:27:56.800059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 09:27:56.807275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 09:27:56.810500 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 09:27:56.813387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 09:27:56.820133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 09:27:56.823593 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 09:27:56.827040 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 09:27:56.833658 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 09:27:56.837059 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 09:27:56.840368 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 09:27:56.847021 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2899 09:27:56.850393 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 09:27:56.853514 Total UI for P1: 0, mck2ui 16
2901 09:27:56.856894 best dqsien dly found for B0: ( 1, 3, 28)
2902 09:27:56.860446 Total UI for P1: 0, mck2ui 16
2903 09:27:56.863577 best dqsien dly found for B1: ( 1, 3, 28)
2904 09:27:56.866940 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2905 09:27:56.870457 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2906 09:27:56.870544
2907 09:27:56.873529 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 09:27:56.877058 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2909 09:27:56.880305 [Gating] SW calibration Done
2910 09:27:56.880392 ==
2911 09:27:56.883981 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 09:27:56.887309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 09:27:56.887399 ==
2914 09:27:56.890509 RX Vref Scan: 0
2915 09:27:56.890595
2916 09:27:56.893540 RX Vref 0 -> 0, step: 1
2917 09:27:56.893656
2918 09:27:56.893768 RX Delay -40 -> 252, step: 8
2919 09:27:56.900586 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2920 09:27:56.904033 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2921 09:27:56.907239 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2922 09:27:56.910158 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2923 09:27:56.913625 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2924 09:27:56.920185 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2925 09:27:56.923564 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2926 09:27:56.927202 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2927 09:27:56.930260 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2928 09:27:56.933575 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2929 09:27:56.936822 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2930 09:27:56.944324 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2931 09:27:56.947347 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2932 09:27:56.950911 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2933 09:27:56.954023 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2934 09:27:56.957481 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2935 09:27:56.961238 ==
2936 09:27:56.961334 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 09:27:56.967663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 09:27:56.967760 ==
2939 09:27:56.967829 DQS Delay:
2940 09:27:56.970492 DQS0 = 0, DQS1 = 0
2941 09:27:56.970576 DQM Delay:
2942 09:27:56.973923 DQM0 = 120, DQM1 = 108
2943 09:27:56.974008 DQ Delay:
2944 09:27:56.977518 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2945 09:27:56.980382 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2946 09:27:56.984100 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2947 09:27:56.987285 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2948 09:27:56.987373
2949 09:27:56.987439
2950 09:27:56.987502 ==
2951 09:27:56.990806 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 09:27:56.997133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 09:27:56.997236 ==
2954 09:27:56.997304
2955 09:27:56.997365
2956 09:27:56.997423 TX Vref Scan disable
2957 09:27:57.000440 == TX Byte 0 ==
2958 09:27:57.003807 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2959 09:27:57.010495 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2960 09:27:57.010593 == TX Byte 1 ==
2961 09:27:57.013897 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2962 09:27:57.017480 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2963 09:27:57.020434 ==
2964 09:27:57.023829 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 09:27:57.027297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 09:27:57.027389 ==
2967 09:27:57.038314 TX Vref=22, minBit 1, minWin=24, winSum=411
2968 09:27:57.041923 TX Vref=24, minBit 1, minWin=24, winSum=415
2969 09:27:57.044955 TX Vref=26, minBit 1, minWin=24, winSum=416
2970 09:27:57.048538 TX Vref=28, minBit 1, minWin=25, winSum=420
2971 09:27:57.051795 TX Vref=30, minBit 1, minWin=25, winSum=419
2972 09:27:57.055122 TX Vref=32, minBit 1, minWin=25, winSum=419
2973 09:27:57.061683 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
2974 09:27:57.061788
2975 09:27:57.065218 Final TX Range 1 Vref 28
2976 09:27:57.065307
2977 09:27:57.065373 ==
2978 09:27:57.068530 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 09:27:57.072302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 09:27:57.072392 ==
2981 09:27:57.072458
2982 09:27:57.072517
2983 09:27:57.075234 TX Vref Scan disable
2984 09:27:57.078611 == TX Byte 0 ==
2985 09:27:57.081726 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 09:27:57.084943 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 09:27:57.088811 == TX Byte 1 ==
2988 09:27:57.091874 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2989 09:27:57.094959 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2990 09:27:57.095048
2991 09:27:57.098477 [DATLAT]
2992 09:27:57.098561 Freq=1200, CH0 RK1
2993 09:27:57.098626
2994 09:27:57.101954 DATLAT Default: 0xd
2995 09:27:57.102075 0, 0xFFFF, sum = 0
2996 09:27:57.105211 1, 0xFFFF, sum = 0
2997 09:27:57.105296 2, 0xFFFF, sum = 0
2998 09:27:57.108590 3, 0xFFFF, sum = 0
2999 09:27:57.108676 4, 0xFFFF, sum = 0
3000 09:27:57.112133 5, 0xFFFF, sum = 0
3001 09:27:57.112231 6, 0xFFFF, sum = 0
3002 09:27:57.115355 7, 0xFFFF, sum = 0
3003 09:27:57.115442 8, 0xFFFF, sum = 0
3004 09:27:57.119086 9, 0xFFFF, sum = 0
3005 09:27:57.119176 10, 0xFFFF, sum = 0
3006 09:27:57.122525 11, 0xFFFF, sum = 0
3007 09:27:57.122613 12, 0x0, sum = 1
3008 09:27:57.125543 13, 0x0, sum = 2
3009 09:27:57.125629 14, 0x0, sum = 3
3010 09:27:57.128501 15, 0x0, sum = 4
3011 09:27:57.128588 best_step = 13
3012 09:27:57.128653
3013 09:27:57.128713 ==
3014 09:27:57.132217 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 09:27:57.138875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 09:27:57.138984 ==
3017 09:27:57.139054 RX Vref Scan: 0
3018 09:27:57.139115
3019 09:27:57.142282 RX Vref 0 -> 0, step: 1
3020 09:27:57.142424
3021 09:27:57.145389 RX Delay -21 -> 252, step: 4
3022 09:27:57.148824 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3023 09:27:57.152019 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3024 09:27:57.155950 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3025 09:27:57.162129 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3026 09:27:57.165409 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3027 09:27:57.168738 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3028 09:27:57.172643 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3029 09:27:57.175646 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3030 09:27:57.182001 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3031 09:27:57.185447 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3032 09:27:57.188915 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3033 09:27:57.192279 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3034 09:27:57.195377 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3035 09:27:57.202699 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3036 09:27:57.205612 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3037 09:27:57.208853 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3038 09:27:57.209021 ==
3039 09:27:57.212566 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 09:27:57.215434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 09:27:57.215525 ==
3042 09:27:57.218763 DQS Delay:
3043 09:27:57.218865 DQS0 = 0, DQS1 = 0
3044 09:27:57.222407 DQM Delay:
3045 09:27:57.222495 DQM0 = 119, DQM1 = 107
3046 09:27:57.222581 DQ Delay:
3047 09:27:57.228878 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3048 09:27:57.232576 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3049 09:27:57.235454 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3050 09:27:57.239010 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3051 09:27:57.239104
3052 09:27:57.239188
3053 09:27:57.245669 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3054 09:27:57.249118 CH0 RK1: MR19=403, MR18=12FA
3055 09:27:57.256240 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3056 09:27:57.259018 [RxdqsGatingPostProcess] freq 1200
3057 09:27:57.262524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 09:27:57.265878 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 09:27:57.268904 best DQS1 dly(2T, 0.5T) = (0, 11)
3060 09:27:57.272325 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 09:27:57.275690 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3062 09:27:57.278902 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 09:27:57.282592 best DQS1 dly(2T, 0.5T) = (0, 11)
3064 09:27:57.285969 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 09:27:57.289531 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3066 09:27:57.292089 Pre-setting of DQS Precalculation
3067 09:27:57.295600 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 09:27:57.295693 ==
3069 09:27:57.299098 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 09:27:57.305721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 09:27:57.305825 ==
3072 09:27:57.309009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 09:27:57.315671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3074 09:27:57.324344 [CA 0] Center 37 (7~68) winsize 62
3075 09:27:57.327704 [CA 1] Center 37 (7~68) winsize 62
3076 09:27:57.331337 [CA 2] Center 35 (5~65) winsize 61
3077 09:27:57.334474 [CA 3] Center 34 (4~65) winsize 62
3078 09:27:57.337949 [CA 4] Center 33 (3~64) winsize 62
3079 09:27:57.341158 [CA 5] Center 33 (3~64) winsize 62
3080 09:27:57.341252
3081 09:27:57.344722 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 09:27:57.344827
3083 09:27:57.347849 [CATrainingPosCal] consider 1 rank data
3084 09:27:57.351044 u2DelayCellTimex100 = 270/100 ps
3085 09:27:57.354677 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 09:27:57.357854 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 09:27:57.364452 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 09:27:57.367756 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3089 09:27:57.371062 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 09:27:57.374690 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3091 09:27:57.374784
3092 09:27:57.377941 CA PerBit enable=1, Macro0, CA PI delay=33
3093 09:27:57.378033
3094 09:27:57.381363 [CBTSetCACLKResult] CA Dly = 33
3095 09:27:57.381452 CS Dly: 5 (0~36)
3096 09:27:57.381538 ==
3097 09:27:57.384626 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 09:27:57.391186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 09:27:57.391286 ==
3100 09:27:57.394666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 09:27:57.401042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3102 09:27:57.410159 [CA 0] Center 38 (8~69) winsize 62
3103 09:27:57.413554 [CA 1] Center 38 (7~69) winsize 63
3104 09:27:57.416751 [CA 2] Center 35 (5~66) winsize 62
3105 09:27:57.419958 [CA 3] Center 35 (5~65) winsize 61
3106 09:27:57.423362 [CA 4] Center 34 (5~64) winsize 60
3107 09:27:57.426893 [CA 5] Center 34 (4~64) winsize 61
3108 09:27:57.426989
3109 09:27:57.430162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3110 09:27:57.430251
3111 09:27:57.433601 [CATrainingPosCal] consider 2 rank data
3112 09:27:57.436791 u2DelayCellTimex100 = 270/100 ps
3113 09:27:57.440041 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3114 09:27:57.443508 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3115 09:27:57.449970 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3116 09:27:57.453523 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 09:27:57.456879 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3118 09:27:57.460111 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3119 09:27:57.460225
3120 09:27:57.463701 CA PerBit enable=1, Macro0, CA PI delay=34
3121 09:27:57.463809
3122 09:27:57.467331 [CBTSetCACLKResult] CA Dly = 34
3123 09:27:57.467441 CS Dly: 6 (0~39)
3124 09:27:57.467534
3125 09:27:57.470799 ----->DramcWriteLeveling(PI) begin...
3126 09:27:57.470918 ==
3127 09:27:57.473683 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 09:27:57.480449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 09:27:57.480584 ==
3130 09:27:57.483838 Write leveling (Byte 0): 27 => 27
3131 09:27:57.483951 Write leveling (Byte 1): 27 => 27
3132 09:27:57.487314 DramcWriteLeveling(PI) end<-----
3133 09:27:57.487421
3134 09:27:57.490435 ==
3135 09:27:57.490522 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 09:27:57.497327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 09:27:57.497515 ==
3138 09:27:57.500463 [Gating] SW mode calibration
3139 09:27:57.506714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 09:27:57.510440 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 09:27:57.516924 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 09:27:57.520262 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 09:27:57.523408 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 09:27:57.530580 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 09:27:57.533519 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 09:27:57.536862 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3147 09:27:57.543460 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
3148 09:27:57.547254 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3149 09:27:57.550351 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 09:27:57.557227 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 09:27:57.560567 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 09:27:57.563540 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 09:27:57.567067 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 09:27:57.573666 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 09:27:57.577168 1 0 24 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
3156 09:27:57.580377 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 09:27:57.587056 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 09:27:57.590412 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 09:27:57.593708 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 09:27:57.600175 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 09:27:57.603575 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 09:27:57.607203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 09:27:57.613971 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 09:27:57.617103 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 09:27:57.620699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 09:27:57.627117 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 09:27:57.630393 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 09:27:57.633635 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 09:27:57.640357 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 09:27:57.643741 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 09:27:57.647344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 09:27:57.654005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 09:27:57.657186 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 09:27:57.660651 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 09:27:57.663659 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 09:27:57.670830 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 09:27:57.673836 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 09:27:57.677113 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3179 09:27:57.683529 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 09:27:57.686908 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3181 09:27:57.690640 Total UI for P1: 0, mck2ui 16
3182 09:27:57.693781 best dqsien dly found for B0: ( 1, 3, 22)
3183 09:27:57.697272 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 09:27:57.700277 Total UI for P1: 0, mck2ui 16
3185 09:27:57.703699 best dqsien dly found for B1: ( 1, 3, 26)
3186 09:27:57.706907 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3187 09:27:57.710408 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3188 09:27:57.710534
3189 09:27:57.717077 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3190 09:27:57.720661 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3191 09:27:57.720793 [Gating] SW calibration Done
3192 09:27:57.724004 ==
3193 09:27:57.727233 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 09:27:57.730464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 09:27:57.730583 ==
3196 09:27:57.730670 RX Vref Scan: 0
3197 09:27:57.730734
3198 09:27:57.733807 RX Vref 0 -> 0, step: 1
3199 09:27:57.733936
3200 09:27:57.736869 RX Delay -40 -> 252, step: 8
3201 09:27:57.740668 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3202 09:27:57.743757 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3203 09:27:57.747103 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3204 09:27:57.753823 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3205 09:27:57.757439 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3206 09:27:57.760268 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3207 09:27:57.763763 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3208 09:27:57.767219 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3209 09:27:57.774598 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 09:27:57.777234 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3211 09:27:57.780439 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3212 09:27:57.784177 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 09:27:57.787208 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3214 09:27:57.793961 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3215 09:27:57.797321 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3216 09:27:57.801032 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3217 09:27:57.801158 ==
3218 09:27:57.804030 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 09:27:57.807305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 09:27:57.807404 ==
3221 09:27:57.810897 DQS Delay:
3222 09:27:57.811017 DQS0 = 0, DQS1 = 0
3223 09:27:57.811114 DQM Delay:
3224 09:27:57.813886 DQM0 = 119, DQM1 = 112
3225 09:27:57.813993 DQ Delay:
3226 09:27:57.817590 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3227 09:27:57.820875 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3228 09:27:57.824236 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3229 09:27:57.831660 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3230 09:27:57.831857
3231 09:27:57.831989
3232 09:27:57.832108 ==
3233 09:27:57.834040 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 09:27:57.837433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 09:27:57.837584 ==
3236 09:27:57.837712
3237 09:27:57.837829
3238 09:27:57.840917 TX Vref Scan disable
3239 09:27:57.841100 == TX Byte 0 ==
3240 09:27:57.847468 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 09:27:57.851166 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 09:27:57.851308 == TX Byte 1 ==
3243 09:27:57.857492 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3244 09:27:57.860696 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3245 09:27:57.860826 ==
3246 09:27:57.864194 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 09:27:57.867558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 09:27:57.867674 ==
3249 09:27:57.879855 TX Vref=22, minBit 1, minWin=24, winSum=406
3250 09:27:57.883411 TX Vref=24, minBit 1, minWin=25, winSum=411
3251 09:27:57.886288 TX Vref=26, minBit 1, minWin=25, winSum=414
3252 09:27:57.889869 TX Vref=28, minBit 9, minWin=25, winSum=421
3253 09:27:57.893209 TX Vref=30, minBit 10, minWin=25, winSum=423
3254 09:27:57.899939 TX Vref=32, minBit 9, minWin=24, winSum=423
3255 09:27:57.903226 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 30
3256 09:27:57.903376
3257 09:27:57.906902 Final TX Range 1 Vref 30
3258 09:27:57.906996
3259 09:27:57.907065 ==
3260 09:27:57.909883 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 09:27:57.913125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 09:27:57.913220 ==
3263 09:27:57.916631
3264 09:27:57.916722
3265 09:27:57.916793 TX Vref Scan disable
3266 09:27:57.920238 == TX Byte 0 ==
3267 09:27:57.923423 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 09:27:57.926860 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 09:27:57.930644 == TX Byte 1 ==
3270 09:27:57.933337 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 09:27:57.936842 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 09:27:57.937006
3273 09:27:57.939823 [DATLAT]
3274 09:27:57.939925 Freq=1200, CH1 RK0
3275 09:27:57.940020
3276 09:27:57.943217 DATLAT Default: 0xd
3277 09:27:57.943357 0, 0xFFFF, sum = 0
3278 09:27:57.946800 1, 0xFFFF, sum = 0
3279 09:27:57.946948 2, 0xFFFF, sum = 0
3280 09:27:57.950272 3, 0xFFFF, sum = 0
3281 09:27:57.950399 4, 0xFFFF, sum = 0
3282 09:27:57.953374 5, 0xFFFF, sum = 0
3283 09:27:57.953482 6, 0xFFFF, sum = 0
3284 09:27:57.956748 7, 0xFFFF, sum = 0
3285 09:27:57.956856 8, 0xFFFF, sum = 0
3286 09:27:57.960000 9, 0xFFFF, sum = 0
3287 09:27:57.963541 10, 0xFFFF, sum = 0
3288 09:27:57.963656 11, 0xFFFF, sum = 0
3289 09:27:57.966713 12, 0x0, sum = 1
3290 09:27:57.966819 13, 0x0, sum = 2
3291 09:27:57.966912 14, 0x0, sum = 3
3292 09:27:57.970268 15, 0x0, sum = 4
3293 09:27:57.970386 best_step = 13
3294 09:27:57.970481
3295 09:27:57.970553 ==
3296 09:27:57.973355 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 09:27:57.980561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 09:27:57.980677 ==
3299 09:27:57.980782 RX Vref Scan: 1
3300 09:27:57.980845
3301 09:27:57.983413 Set Vref Range= 32 -> 127
3302 09:27:57.983501
3303 09:27:57.987235 RX Vref 32 -> 127, step: 1
3304 09:27:57.987325
3305 09:27:57.990419 RX Delay -13 -> 252, step: 4
3306 09:27:57.990509
3307 09:27:57.990576 Set Vref, RX VrefLevel [Byte0]: 32
3308 09:27:57.993956 [Byte1]: 32
3309 09:27:57.998559
3310 09:27:57.998666 Set Vref, RX VrefLevel [Byte0]: 33
3311 09:27:58.001672 [Byte1]: 33
3312 09:27:58.006148
3313 09:27:58.006256 Set Vref, RX VrefLevel [Byte0]: 34
3314 09:27:58.009384 [Byte1]: 34
3315 09:27:58.013921
3316 09:27:58.014021 Set Vref, RX VrefLevel [Byte0]: 35
3317 09:27:58.017324 [Byte1]: 35
3318 09:27:58.022215
3319 09:27:58.022318 Set Vref, RX VrefLevel [Byte0]: 36
3320 09:27:58.025158 [Byte1]: 36
3321 09:27:58.029979
3322 09:27:58.030082 Set Vref, RX VrefLevel [Byte0]: 37
3323 09:27:58.033454 [Byte1]: 37
3324 09:27:58.037525
3325 09:27:58.037621 Set Vref, RX VrefLevel [Byte0]: 38
3326 09:27:58.040862 [Byte1]: 38
3327 09:27:58.045529
3328 09:27:58.045625 Set Vref, RX VrefLevel [Byte0]: 39
3329 09:27:58.049122 [Byte1]: 39
3330 09:27:58.053695
3331 09:27:58.053800 Set Vref, RX VrefLevel [Byte0]: 40
3332 09:27:58.056719 [Byte1]: 40
3333 09:27:58.061654
3334 09:27:58.061747 Set Vref, RX VrefLevel [Byte0]: 41
3335 09:27:58.064604 [Byte1]: 41
3336 09:27:58.069371
3337 09:27:58.069472 Set Vref, RX VrefLevel [Byte0]: 42
3338 09:27:58.073151 [Byte1]: 42
3339 09:27:58.077167
3340 09:27:58.077286 Set Vref, RX VrefLevel [Byte0]: 43
3341 09:27:58.080744 [Byte1]: 43
3342 09:27:58.084869
3343 09:27:58.085000 Set Vref, RX VrefLevel [Byte0]: 44
3344 09:27:58.088497 [Byte1]: 44
3345 09:27:58.093374
3346 09:27:58.093478 Set Vref, RX VrefLevel [Byte0]: 45
3347 09:27:58.096240 [Byte1]: 45
3348 09:27:58.101026
3349 09:27:58.101122 Set Vref, RX VrefLevel [Byte0]: 46
3350 09:27:58.104078 [Byte1]: 46
3351 09:27:58.109105
3352 09:27:58.109206 Set Vref, RX VrefLevel [Byte0]: 47
3353 09:27:58.112107 [Byte1]: 47
3354 09:27:58.116309
3355 09:27:58.116403 Set Vref, RX VrefLevel [Byte0]: 48
3356 09:27:58.119956 [Byte1]: 48
3357 09:27:58.124346
3358 09:27:58.124449 Set Vref, RX VrefLevel [Byte0]: 49
3359 09:27:58.127950 [Byte1]: 49
3360 09:27:58.132422
3361 09:27:58.132550 Set Vref, RX VrefLevel [Byte0]: 50
3362 09:27:58.135639 [Byte1]: 50
3363 09:27:58.140411
3364 09:27:58.140536 Set Vref, RX VrefLevel [Byte0]: 51
3365 09:27:58.143672 [Byte1]: 51
3366 09:27:58.148096
3367 09:27:58.148211 Set Vref, RX VrefLevel [Byte0]: 52
3368 09:27:58.151235 [Byte1]: 52
3369 09:27:58.156071
3370 09:27:58.156171 Set Vref, RX VrefLevel [Byte0]: 53
3371 09:27:58.159098 [Byte1]: 53
3372 09:27:58.163847
3373 09:27:58.163951 Set Vref, RX VrefLevel [Byte0]: 54
3374 09:27:58.167330 [Byte1]: 54
3375 09:27:58.172005
3376 09:27:58.172101 Set Vref, RX VrefLevel [Byte0]: 55
3377 09:27:58.175239 [Byte1]: 55
3378 09:27:58.180050
3379 09:27:58.180145 Set Vref, RX VrefLevel [Byte0]: 56
3380 09:27:58.183145 [Byte1]: 56
3381 09:27:58.187446
3382 09:27:58.187537 Set Vref, RX VrefLevel [Byte0]: 57
3383 09:27:58.191162 [Byte1]: 57
3384 09:27:58.195220
3385 09:27:58.195316 Set Vref, RX VrefLevel [Byte0]: 58
3386 09:27:58.198636 [Byte1]: 58
3387 09:27:58.203458
3388 09:27:58.203588 Set Vref, RX VrefLevel [Byte0]: 59
3389 09:27:58.206406 [Byte1]: 59
3390 09:27:58.211243
3391 09:27:58.211378 Set Vref, RX VrefLevel [Byte0]: 60
3392 09:27:58.214322 [Byte1]: 60
3393 09:27:58.219162
3394 09:27:58.219259 Set Vref, RX VrefLevel [Byte0]: 61
3395 09:27:58.222826 [Byte1]: 61
3396 09:27:58.226854
3397 09:27:58.226952 Set Vref, RX VrefLevel [Byte0]: 62
3398 09:27:58.230314 [Byte1]: 62
3399 09:27:58.235173
3400 09:27:58.235278 Set Vref, RX VrefLevel [Byte0]: 63
3401 09:27:58.238488 [Byte1]: 63
3402 09:27:58.242784
3403 09:27:58.242879 Set Vref, RX VrefLevel [Byte0]: 64
3404 09:27:58.246243 [Byte1]: 64
3405 09:27:58.250802
3406 09:27:58.250910 Set Vref, RX VrefLevel [Byte0]: 65
3407 09:27:58.254114 [Byte1]: 65
3408 09:27:58.258556
3409 09:27:58.258649 Set Vref, RX VrefLevel [Byte0]: 66
3410 09:27:58.262153 [Byte1]: 66
3411 09:27:58.266580
3412 09:27:58.266679 Set Vref, RX VrefLevel [Byte0]: 67
3413 09:27:58.269912 [Byte1]: 67
3414 09:27:58.274217
3415 09:27:58.274300 Set Vref, RX VrefLevel [Byte0]: 68
3416 09:27:58.277867 [Byte1]: 68
3417 09:27:58.282086
3418 09:27:58.282185 Final RX Vref Byte 0 = 54 to rank0
3419 09:27:58.285415 Final RX Vref Byte 1 = 52 to rank0
3420 09:27:58.289076 Final RX Vref Byte 0 = 54 to rank1
3421 09:27:58.292243 Final RX Vref Byte 1 = 52 to rank1==
3422 09:27:58.295943 Dram Type= 6, Freq= 0, CH_1, rank 0
3423 09:27:58.302204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 09:27:58.302326 ==
3425 09:27:58.302395 DQS Delay:
3426 09:27:58.302457 DQS0 = 0, DQS1 = 0
3427 09:27:58.305930 DQM Delay:
3428 09:27:58.306021 DQM0 = 119, DQM1 = 112
3429 09:27:58.308710 DQ Delay:
3430 09:27:58.312734 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3431 09:27:58.315410 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3432 09:27:58.319374 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3433 09:27:58.322128 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3434 09:27:58.322231
3435 09:27:58.322300
3436 09:27:58.328875 [DQSOSCAuto] RK0, (LSB)MR18= 0x61a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3437 09:27:58.332124 CH1 RK0: MR19=404, MR18=61A
3438 09:27:58.339204 CH1_RK0: MR19=0x404, MR18=0x61A, DQSOSC=400, MR23=63, INC=40, DEC=27
3439 09:27:58.339338
3440 09:27:58.342123 ----->DramcWriteLeveling(PI) begin...
3441 09:27:58.342236 ==
3442 09:27:58.345505 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 09:27:58.349240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 09:27:58.349349 ==
3445 09:27:58.352413 Write leveling (Byte 0): 25 => 25
3446 09:27:58.355922 Write leveling (Byte 1): 29 => 29
3447 09:27:58.358969 DramcWriteLeveling(PI) end<-----
3448 09:27:58.359080
3449 09:27:58.359149 ==
3450 09:27:58.362658 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 09:27:58.365717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 09:27:58.369133 ==
3453 09:27:58.369246 [Gating] SW mode calibration
3454 09:27:58.376061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3455 09:27:58.382924 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3456 09:27:58.385843 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3457 09:27:58.392364 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 09:27:58.396363 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 09:27:58.399344 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 09:27:58.406198 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 09:27:58.409523 0 15 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3462 09:27:58.412985 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (0 1) (1 0)
3463 09:27:58.416055 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3464 09:27:58.422584 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 09:27:58.426185 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 09:27:58.429702 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 09:27:58.435952 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 09:27:58.439292 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 09:27:58.442579 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 09:27:58.450001 1 0 24 | B1->B0 | 3737 2c2c | 0 0 | (0 0) (0 0)
3471 09:27:58.452843 1 0 28 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
3472 09:27:58.455960 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 09:27:58.462881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 09:27:58.466291 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 09:27:58.469646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 09:27:58.476386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 09:27:58.479553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 09:27:58.482814 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 09:27:58.486283 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3480 09:27:58.493202 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 09:27:58.496172 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 09:27:58.500016 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 09:27:58.506796 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 09:27:58.509485 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 09:27:58.513263 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 09:27:58.519378 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 09:27:58.522939 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 09:27:58.526717 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 09:27:58.532872 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 09:27:58.536598 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 09:27:58.539983 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 09:27:58.546115 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 09:27:58.549469 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 09:27:58.552885 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3495 09:27:58.559472 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 09:27:58.559606 Total UI for P1: 0, mck2ui 16
3497 09:27:58.566485 best dqsien dly found for B0: ( 1, 3, 24)
3498 09:27:58.566613 Total UI for P1: 0, mck2ui 16
3499 09:27:58.572856 best dqsien dly found for B1: ( 1, 3, 24)
3500 09:27:58.576046 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3501 09:27:58.579463 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3502 09:27:58.579561
3503 09:27:58.582791 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3504 09:27:58.586342 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3505 09:27:58.589713 [Gating] SW calibration Done
3506 09:27:58.589811 ==
3507 09:27:58.593297 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 09:27:58.596225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 09:27:58.596322 ==
3510 09:27:58.599257 RX Vref Scan: 0
3511 09:27:58.599345
3512 09:27:58.599413 RX Vref 0 -> 0, step: 1
3513 09:27:58.599476
3514 09:27:58.602895 RX Delay -40 -> 252, step: 8
3515 09:27:58.606093 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3516 09:27:58.613041 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3517 09:27:58.616023 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3518 09:27:58.619582 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3519 09:27:58.622545 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3520 09:27:58.626568 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3521 09:27:58.632712 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3522 09:27:58.635766 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3523 09:27:58.639339 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3524 09:27:58.642490 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3525 09:27:58.645910 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3526 09:27:58.652341 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3527 09:27:58.655664 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3528 09:27:58.659876 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3529 09:27:58.662402 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3530 09:27:58.665840 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3531 09:27:58.669038 ==
3532 09:27:58.669142 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 09:27:58.675719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 09:27:58.675864 ==
3535 09:27:58.675938 DQS Delay:
3536 09:27:58.679254 DQS0 = 0, DQS1 = 0
3537 09:27:58.679363 DQM Delay:
3538 09:27:58.682183 DQM0 = 120, DQM1 = 112
3539 09:27:58.682277 DQ Delay:
3540 09:27:58.685835 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3541 09:27:58.689099 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3542 09:27:58.692314 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3543 09:27:58.695440 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3544 09:27:58.695538
3545 09:27:58.695608
3546 09:27:58.695671 ==
3547 09:27:58.698841 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 09:27:58.705739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 09:27:58.705864 ==
3550 09:27:58.705934
3551 09:27:58.705998
3552 09:27:58.706058 TX Vref Scan disable
3553 09:27:58.709124 == TX Byte 0 ==
3554 09:27:58.712365 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 09:27:58.719396 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 09:27:58.719519 == TX Byte 1 ==
3557 09:27:58.722415 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 09:27:58.725881 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 09:27:58.729363 ==
3560 09:27:58.732704 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 09:27:58.735402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 09:27:58.735496 ==
3563 09:27:58.747014 TX Vref=22, minBit 0, minWin=25, winSum=418
3564 09:27:58.750299 TX Vref=24, minBit 7, minWin=25, winSum=422
3565 09:27:58.753621 TX Vref=26, minBit 1, minWin=26, winSum=427
3566 09:27:58.757141 TX Vref=28, minBit 8, minWin=26, winSum=430
3567 09:27:58.760191 TX Vref=30, minBit 1, minWin=26, winSum=431
3568 09:27:58.764781 TX Vref=32, minBit 8, minWin=26, winSum=431
3569 09:27:58.770141 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3570 09:27:58.770282
3571 09:27:58.773441 Final TX Range 1 Vref 30
3572 09:27:58.773531
3573 09:27:58.773641 ==
3574 09:27:58.776942 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 09:27:58.780183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 09:27:58.780278 ==
3577 09:27:58.783541
3578 09:27:58.783631
3579 09:27:58.783699 TX Vref Scan disable
3580 09:27:58.786606 == TX Byte 0 ==
3581 09:27:58.790065 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3582 09:27:58.793564 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3583 09:27:58.797103 == TX Byte 1 ==
3584 09:27:58.800463 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3585 09:27:58.803718 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3586 09:27:58.806903
3587 09:27:58.806996 [DATLAT]
3588 09:27:58.807064 Freq=1200, CH1 RK1
3589 09:27:58.807127
3590 09:27:58.810016 DATLAT Default: 0xd
3591 09:27:58.810103 0, 0xFFFF, sum = 0
3592 09:27:58.813604 1, 0xFFFF, sum = 0
3593 09:27:58.813693 2, 0xFFFF, sum = 0
3594 09:27:58.816717 3, 0xFFFF, sum = 0
3595 09:27:58.820054 4, 0xFFFF, sum = 0
3596 09:27:58.820147 5, 0xFFFF, sum = 0
3597 09:27:58.823149 6, 0xFFFF, sum = 0
3598 09:27:58.823240 7, 0xFFFF, sum = 0
3599 09:27:58.826797 8, 0xFFFF, sum = 0
3600 09:27:58.826886 9, 0xFFFF, sum = 0
3601 09:27:58.829971 10, 0xFFFF, sum = 0
3602 09:27:58.830062 11, 0xFFFF, sum = 0
3603 09:27:58.833495 12, 0x0, sum = 1
3604 09:27:58.833588 13, 0x0, sum = 2
3605 09:27:58.836788 14, 0x0, sum = 3
3606 09:27:58.836877 15, 0x0, sum = 4
3607 09:27:58.836986 best_step = 13
3608 09:27:58.840090
3609 09:27:58.840177 ==
3610 09:27:58.843381 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 09:27:58.846441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 09:27:58.846533 ==
3613 09:27:58.846619 RX Vref Scan: 0
3614 09:27:58.846699
3615 09:27:58.849936 RX Vref 0 -> 0, step: 1
3616 09:27:58.850060
3617 09:27:58.853456 RX Delay -13 -> 252, step: 4
3618 09:27:58.856520 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3619 09:27:58.863139 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3620 09:27:58.866728 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3621 09:27:58.870045 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3622 09:27:58.873248 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3623 09:27:58.876232 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3624 09:27:58.882964 iDelay=191, Bit 6, Center 128 (67 ~ 190) 124
3625 09:27:58.886548 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3626 09:27:58.889561 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3627 09:27:58.892810 iDelay=191, Bit 9, Center 100 (35 ~ 166) 132
3628 09:27:58.896468 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3629 09:27:58.902692 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3630 09:27:58.906706 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3631 09:27:58.909778 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3632 09:27:58.912970 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3633 09:27:58.916235 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3634 09:27:58.919524 ==
3635 09:27:58.923235 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 09:27:58.926166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 09:27:58.926267 ==
3638 09:27:58.926354 DQS Delay:
3639 09:27:58.929949 DQS0 = 0, DQS1 = 0
3640 09:27:58.930042 DQM Delay:
3641 09:27:58.933004 DQM0 = 119, DQM1 = 112
3642 09:27:58.933093 DQ Delay:
3643 09:27:58.936078 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3644 09:27:58.939578 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =116
3645 09:27:58.943002 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
3646 09:27:58.945963 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3647 09:27:58.946061
3648 09:27:58.946147
3649 09:27:58.956280 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3650 09:27:58.956421 CH1 RK1: MR19=403, MR18=CF0
3651 09:27:58.962869 CH1_RK1: MR19=0x403, MR18=0xCF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3652 09:27:58.966144 [RxdqsGatingPostProcess] freq 1200
3653 09:27:58.972772 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 09:27:58.975954 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 09:27:58.979270 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 09:27:58.982508 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 09:27:58.986278 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 09:27:58.989224 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 09:27:58.992588 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 09:27:58.996040 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 09:27:58.996143 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 09:27:58.999350 Pre-setting of DQS Precalculation
3663 09:27:59.006121 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 09:27:59.012720 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 09:27:59.019380 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 09:27:59.019505
3667 09:27:59.019579
3668 09:27:59.022980 [Calibration Summary] 2400 Mbps
3669 09:27:59.026026 CH 0, Rank 0
3670 09:27:59.026117 SW Impedance : PASS
3671 09:27:59.029957 DUTY Scan : NO K
3672 09:27:59.030050 ZQ Calibration : PASS
3673 09:27:59.032710 Jitter Meter : NO K
3674 09:27:59.036008 CBT Training : PASS
3675 09:27:59.036099 Write leveling : PASS
3676 09:27:59.039448 RX DQS gating : PASS
3677 09:27:59.042860 RX DQ/DQS(RDDQC) : PASS
3678 09:27:59.042960 TX DQ/DQS : PASS
3679 09:27:59.045972 RX DATLAT : PASS
3680 09:27:59.049606 RX DQ/DQS(Engine): PASS
3681 09:27:59.049716 TX OE : NO K
3682 09:27:59.052505 All Pass.
3683 09:27:59.052626
3684 09:27:59.052735 CH 0, Rank 1
3685 09:27:59.055888 SW Impedance : PASS
3686 09:27:59.055977 DUTY Scan : NO K
3687 09:27:59.059186 ZQ Calibration : PASS
3688 09:27:59.062499 Jitter Meter : NO K
3689 09:27:59.062595 CBT Training : PASS
3690 09:27:59.065766 Write leveling : PASS
3691 09:27:59.069312 RX DQS gating : PASS
3692 09:27:59.069408 RX DQ/DQS(RDDQC) : PASS
3693 09:27:59.072708 TX DQ/DQS : PASS
3694 09:27:59.072799 RX DATLAT : PASS
3695 09:27:59.075790 RX DQ/DQS(Engine): PASS
3696 09:27:59.079654 TX OE : NO K
3697 09:27:59.079750 All Pass.
3698 09:27:59.079818
3699 09:27:59.079880 CH 1, Rank 0
3700 09:27:59.082489 SW Impedance : PASS
3701 09:27:59.086307 DUTY Scan : NO K
3702 09:27:59.086405 ZQ Calibration : PASS
3703 09:27:59.089199 Jitter Meter : NO K
3704 09:27:59.092574 CBT Training : PASS
3705 09:27:59.092671 Write leveling : PASS
3706 09:27:59.095784 RX DQS gating : PASS
3707 09:27:59.099107 RX DQ/DQS(RDDQC) : PASS
3708 09:27:59.099218 TX DQ/DQS : PASS
3709 09:27:59.102649 RX DATLAT : PASS
3710 09:27:59.105690 RX DQ/DQS(Engine): PASS
3711 09:27:59.105789 TX OE : NO K
3712 09:27:59.109632 All Pass.
3713 09:27:59.109728
3714 09:27:59.109798 CH 1, Rank 1
3715 09:27:59.112560 SW Impedance : PASS
3716 09:27:59.112649 DUTY Scan : NO K
3717 09:27:59.115585 ZQ Calibration : PASS
3718 09:27:59.119093 Jitter Meter : NO K
3719 09:27:59.119190 CBT Training : PASS
3720 09:27:59.122439 Write leveling : PASS
3721 09:27:59.122532 RX DQS gating : PASS
3722 09:27:59.125629 RX DQ/DQS(RDDQC) : PASS
3723 09:27:59.128980 TX DQ/DQS : PASS
3724 09:27:59.129107 RX DATLAT : PASS
3725 09:27:59.132290 RX DQ/DQS(Engine): PASS
3726 09:27:59.135955 TX OE : NO K
3727 09:27:59.136051 All Pass.
3728 09:27:59.136120
3729 09:27:59.139343 DramC Write-DBI off
3730 09:27:59.139433 PER_BANK_REFRESH: Hybrid Mode
3731 09:27:59.142599 TX_TRACKING: ON
3732 09:27:59.149154 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 09:27:59.156011 [FAST_K] Save calibration result to emmc
3734 09:27:59.159182 dramc_set_vcore_voltage set vcore to 650000
3735 09:27:59.159293 Read voltage for 600, 5
3736 09:27:59.162527 Vio18 = 0
3737 09:27:59.162619 Vcore = 650000
3738 09:27:59.162687 Vdram = 0
3739 09:27:59.165976 Vddq = 0
3740 09:27:59.166069 Vmddr = 0
3741 09:27:59.169412 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 09:27:59.176129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 09:27:59.179308 MEM_TYPE=3, freq_sel=19
3744 09:27:59.182431 sv_algorithm_assistance_LP4_1600
3745 09:27:59.185905 ============ PULL DRAM RESETB DOWN ============
3746 09:27:59.189117 ========== PULL DRAM RESETB DOWN end =========
3747 09:27:59.196294 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 09:27:59.196420 ===================================
3749 09:27:59.198962 LPDDR4 DRAM CONFIGURATION
3750 09:27:59.202498 ===================================
3751 09:27:59.205862 EX_ROW_EN[0] = 0x0
3752 09:27:59.205965 EX_ROW_EN[1] = 0x0
3753 09:27:59.209101 LP4Y_EN = 0x0
3754 09:27:59.209194 WORK_FSP = 0x0
3755 09:27:59.212257 WL = 0x2
3756 09:27:59.212348 RL = 0x2
3757 09:27:59.215678 BL = 0x2
3758 09:27:59.215769 RPST = 0x0
3759 09:27:59.218956 RD_PRE = 0x0
3760 09:27:59.222136 WR_PRE = 0x1
3761 09:27:59.222230 WR_PST = 0x0
3762 09:27:59.225664 DBI_WR = 0x0
3763 09:27:59.225756 DBI_RD = 0x0
3764 09:27:59.228768 OTF = 0x1
3765 09:27:59.231996 ===================================
3766 09:27:59.235740 ===================================
3767 09:27:59.235841 ANA top config
3768 09:27:59.238678 ===================================
3769 09:27:59.242175 DLL_ASYNC_EN = 0
3770 09:27:59.245331 ALL_SLAVE_EN = 1
3771 09:27:59.245424 NEW_RANK_MODE = 1
3772 09:27:59.249237 DLL_IDLE_MODE = 1
3773 09:27:59.252306 LP45_APHY_COMB_EN = 1
3774 09:27:59.255387 TX_ODT_DIS = 1
3775 09:27:59.255486 NEW_8X_MODE = 1
3776 09:27:59.259261 ===================================
3777 09:27:59.262074 ===================================
3778 09:27:59.265699 data_rate = 1200
3779 09:27:59.268738 CKR = 1
3780 09:27:59.271890 DQ_P2S_RATIO = 8
3781 09:27:59.275466 ===================================
3782 09:27:59.278872 CA_P2S_RATIO = 8
3783 09:27:59.281879 DQ_CA_OPEN = 0
3784 09:27:59.281970 DQ_SEMI_OPEN = 0
3785 09:27:59.285775 CA_SEMI_OPEN = 0
3786 09:27:59.288779 CA_FULL_RATE = 0
3787 09:27:59.292101 DQ_CKDIV4_EN = 1
3788 09:27:59.295276 CA_CKDIV4_EN = 1
3789 09:27:59.298808 CA_PREDIV_EN = 0
3790 09:27:59.298909 PH8_DLY = 0
3791 09:27:59.302160 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 09:27:59.305264 DQ_AAMCK_DIV = 4
3793 09:27:59.308703 CA_AAMCK_DIV = 4
3794 09:27:59.311724 CA_ADMCK_DIV = 4
3795 09:27:59.315188 DQ_TRACK_CA_EN = 0
3796 09:27:59.315284 CA_PICK = 600
3797 09:27:59.318476 CA_MCKIO = 600
3798 09:27:59.321789 MCKIO_SEMI = 0
3799 09:27:59.325224 PLL_FREQ = 2288
3800 09:27:59.328627 DQ_UI_PI_RATIO = 32
3801 09:27:59.331817 CA_UI_PI_RATIO = 0
3802 09:27:59.335277 ===================================
3803 09:27:59.338570 ===================================
3804 09:27:59.341562 memory_type:LPDDR4
3805 09:27:59.341646 GP_NUM : 10
3806 09:27:59.345061 SRAM_EN : 1
3807 09:27:59.345146 MD32_EN : 0
3808 09:27:59.348242 ===================================
3809 09:27:59.351472 [ANA_INIT] >>>>>>>>>>>>>>
3810 09:27:59.355044 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 09:27:59.358598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 09:27:59.361584 ===================================
3813 09:27:59.365615 data_rate = 1200,PCW = 0X5800
3814 09:27:59.368352 ===================================
3815 09:27:59.371430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 09:27:59.374780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 09:27:59.381305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 09:27:59.388245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 09:27:59.391431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 09:27:59.394785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 09:27:59.394873 [ANA_INIT] flow start
3822 09:27:59.398083 [ANA_INIT] PLL >>>>>>>>
3823 09:27:59.401502 [ANA_INIT] PLL <<<<<<<<
3824 09:27:59.401588 [ANA_INIT] MIDPI >>>>>>>>
3825 09:27:59.404892 [ANA_INIT] MIDPI <<<<<<<<
3826 09:27:59.408069 [ANA_INIT] DLL >>>>>>>>
3827 09:27:59.408152 [ANA_INIT] flow end
3828 09:27:59.411410 ============ LP4 DIFF to SE enter ============
3829 09:27:59.418365 ============ LP4 DIFF to SE exit ============
3830 09:27:59.418453 [ANA_INIT] <<<<<<<<<<<<<
3831 09:27:59.421368 [Flow] Enable top DCM control >>>>>
3832 09:27:59.424503 [Flow] Enable top DCM control <<<<<
3833 09:27:59.427799 Enable DLL master slave shuffle
3834 09:27:59.434594 ==============================================================
3835 09:27:59.438296 Gating Mode config
3836 09:27:59.441289 ==============================================================
3837 09:27:59.445109 Config description:
3838 09:27:59.454461 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 09:27:59.461303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 09:27:59.464415 SELPH_MODE 0: By rank 1: By Phase
3841 09:27:59.471636 ==============================================================
3842 09:27:59.474492 GAT_TRACK_EN = 1
3843 09:27:59.477988 RX_GATING_MODE = 2
3844 09:27:59.478073 RX_GATING_TRACK_MODE = 2
3845 09:27:59.481311 SELPH_MODE = 1
3846 09:27:59.484719 PICG_EARLY_EN = 1
3847 09:27:59.487772 VALID_LAT_VALUE = 1
3848 09:27:59.494602 ==============================================================
3849 09:27:59.498099 Enter into Gating configuration >>>>
3850 09:27:59.500958 Exit from Gating configuration <<<<
3851 09:27:59.504610 Enter into DVFS_PRE_config >>>>>
3852 09:27:59.514318 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 09:27:59.517480 Exit from DVFS_PRE_config <<<<<
3854 09:27:59.520813 Enter into PICG configuration >>>>
3855 09:27:59.524287 Exit from PICG configuration <<<<
3856 09:27:59.527939 [RX_INPUT] configuration >>>>>
3857 09:27:59.530991 [RX_INPUT] configuration <<<<<
3858 09:27:59.534443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 09:27:59.541501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 09:27:59.547732 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 09:27:59.554226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 09:27:59.557955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 09:27:59.564600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 09:27:59.567945 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 09:27:59.574240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 09:27:59.577471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 09:27:59.580892 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 09:27:59.584308 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 09:27:59.591003 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 09:27:59.594323 ===================================
3871 09:27:59.594413 LPDDR4 DRAM CONFIGURATION
3872 09:27:59.597338 ===================================
3873 09:27:59.601182 EX_ROW_EN[0] = 0x0
3874 09:27:59.604477 EX_ROW_EN[1] = 0x0
3875 09:27:59.604561 LP4Y_EN = 0x0
3876 09:27:59.607510 WORK_FSP = 0x0
3877 09:27:59.607595 WL = 0x2
3878 09:27:59.611254 RL = 0x2
3879 09:27:59.611339 BL = 0x2
3880 09:27:59.614182 RPST = 0x0
3881 09:27:59.614266 RD_PRE = 0x0
3882 09:27:59.617701 WR_PRE = 0x1
3883 09:27:59.617787 WR_PST = 0x0
3884 09:27:59.620656 DBI_WR = 0x0
3885 09:27:59.620741 DBI_RD = 0x0
3886 09:27:59.624119 OTF = 0x1
3887 09:27:59.627550 ===================================
3888 09:27:59.630767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 09:27:59.634328 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 09:27:59.640871 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 09:27:59.644166 ===================================
3892 09:27:59.644253 LPDDR4 DRAM CONFIGURATION
3893 09:27:59.647386 ===================================
3894 09:27:59.650687 EX_ROW_EN[0] = 0x10
3895 09:27:59.650775 EX_ROW_EN[1] = 0x0
3896 09:27:59.654164 LP4Y_EN = 0x0
3897 09:27:59.657795 WORK_FSP = 0x0
3898 09:27:59.657881 WL = 0x2
3899 09:27:59.661109 RL = 0x2
3900 09:27:59.661193 BL = 0x2
3901 09:27:59.664235 RPST = 0x0
3902 09:27:59.664319 RD_PRE = 0x0
3903 09:27:59.667481 WR_PRE = 0x1
3904 09:27:59.667566 WR_PST = 0x0
3905 09:27:59.670663 DBI_WR = 0x0
3906 09:27:59.670747 DBI_RD = 0x0
3907 09:27:59.674167 OTF = 0x1
3908 09:27:59.677725 ===================================
3909 09:27:59.683967 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 09:27:59.687890 nWR fixed to 30
3911 09:27:59.687977 [ModeRegInit_LP4] CH0 RK0
3912 09:27:59.690694 [ModeRegInit_LP4] CH0 RK1
3913 09:27:59.694045 [ModeRegInit_LP4] CH1 RK0
3914 09:27:59.694130 [ModeRegInit_LP4] CH1 RK1
3915 09:27:59.697644 match AC timing 17
3916 09:27:59.700535 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 09:27:59.704158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 09:27:59.710836 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 09:27:59.713795 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 09:27:59.720649 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 09:27:59.720774 ==
3922 09:27:59.724222 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 09:27:59.727270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 09:27:59.727356 ==
3925 09:27:59.733975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 09:27:59.737113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3927 09:27:59.741600 [CA 0] Center 36 (6~67) winsize 62
3928 09:27:59.744801 [CA 1] Center 36 (6~67) winsize 62
3929 09:27:59.748465 [CA 2] Center 34 (4~65) winsize 62
3930 09:27:59.751534 [CA 3] Center 34 (3~65) winsize 63
3931 09:27:59.754845 [CA 4] Center 34 (3~65) winsize 63
3932 09:27:59.758321 [CA 5] Center 33 (3~64) winsize 62
3933 09:27:59.758409
3934 09:27:59.761338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3935 09:27:59.761423
3936 09:27:59.764839 [CATrainingPosCal] consider 1 rank data
3937 09:27:59.768287 u2DelayCellTimex100 = 270/100 ps
3938 09:27:59.771490 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 09:27:59.774826 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3940 09:27:59.781580 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 09:27:59.785041 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3942 09:27:59.788016 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3943 09:27:59.791617 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 09:27:59.791703
3945 09:27:59.794981 CA PerBit enable=1, Macro0, CA PI delay=33
3946 09:27:59.795065
3947 09:27:59.798320 [CBTSetCACLKResult] CA Dly = 33
3948 09:27:59.798404 CS Dly: 5 (0~36)
3949 09:27:59.798472 ==
3950 09:27:59.801514 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 09:27:59.807991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 09:27:59.808082 ==
3953 09:27:59.811738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 09:27:59.818123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3955 09:27:59.821539 [CA 0] Center 36 (6~67) winsize 62
3956 09:27:59.825106 [CA 1] Center 36 (6~67) winsize 62
3957 09:27:59.828178 [CA 2] Center 35 (4~66) winsize 63
3958 09:27:59.831537 [CA 3] Center 35 (4~66) winsize 63
3959 09:27:59.834895 [CA 4] Center 34 (3~65) winsize 63
3960 09:27:59.838230 [CA 5] Center 33 (3~64) winsize 62
3961 09:27:59.838314
3962 09:27:59.841834 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3963 09:27:59.841918
3964 09:27:59.844984 [CATrainingPosCal] consider 2 rank data
3965 09:27:59.848342 u2DelayCellTimex100 = 270/100 ps
3966 09:27:59.851484 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3967 09:27:59.855123 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3968 09:27:59.861521 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 09:27:59.865288 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 09:27:59.868332 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3971 09:27:59.871449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 09:27:59.871534
3973 09:27:59.874965 CA PerBit enable=1, Macro0, CA PI delay=33
3974 09:27:59.875049
3975 09:27:59.878612 [CBTSetCACLKResult] CA Dly = 33
3976 09:27:59.878696 CS Dly: 5 (0~37)
3977 09:27:59.878763
3978 09:27:59.881725 ----->DramcWriteLeveling(PI) begin...
3979 09:27:59.884765 ==
3980 09:27:59.888461 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 09:27:59.891744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 09:27:59.891830 ==
3983 09:27:59.895485 Write leveling (Byte 0): 33 => 33
3984 09:27:59.898177 Write leveling (Byte 1): 29 => 29
3985 09:27:59.901649 DramcWriteLeveling(PI) end<-----
3986 09:27:59.901733
3987 09:27:59.901799 ==
3988 09:27:59.904735 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 09:27:59.908436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 09:27:59.908520 ==
3991 09:27:59.911593 [Gating] SW mode calibration
3992 09:27:59.918325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 09:27:59.921437 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 09:27:59.928261 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 09:27:59.931705 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 09:27:59.935181 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 09:27:59.941947 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
3998 09:27:59.944681 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3999 09:27:59.948360 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 09:27:59.954843 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 09:27:59.958380 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 09:27:59.961326 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 09:27:59.968140 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 09:27:59.971241 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 09:27:59.974898 0 10 12 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
4006 09:27:59.981543 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4007 09:27:59.985000 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 09:27:59.988035 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 09:27:59.995048 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 09:27:59.997906 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 09:28:00.001235 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 09:28:00.008703 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 09:28:00.011509 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4014 09:28:00.014692 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4015 09:28:00.021532 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 09:28:00.024446 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 09:28:00.028120 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 09:28:00.034819 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 09:28:00.037847 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 09:28:00.041109 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 09:28:00.044472 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 09:28:00.051159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 09:28:00.054747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 09:28:00.058368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 09:28:00.064688 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 09:28:00.068144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 09:28:00.071080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 09:28:00.077789 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 09:28:00.080911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4030 09:28:00.084371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4031 09:28:00.087822 Total UI for P1: 0, mck2ui 16
4032 09:28:00.091254 best dqsien dly found for B0: ( 0, 13, 12)
4033 09:28:00.097791 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:28:00.097917 Total UI for P1: 0, mck2ui 16
4035 09:28:00.104951 best dqsien dly found for B1: ( 0, 13, 14)
4036 09:28:00.108088 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4037 09:28:00.111069 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4038 09:28:00.111160
4039 09:28:00.114493 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4040 09:28:00.117607 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4041 09:28:00.121052 [Gating] SW calibration Done
4042 09:28:00.121138 ==
4043 09:28:00.124497 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 09:28:00.127667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 09:28:00.127763 ==
4046 09:28:00.131394 RX Vref Scan: 0
4047 09:28:00.131482
4048 09:28:00.131550 RX Vref 0 -> 0, step: 1
4049 09:28:00.131614
4050 09:28:00.134634 RX Delay -230 -> 252, step: 16
4051 09:28:00.141121 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4052 09:28:00.144207 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4053 09:28:00.147452 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4054 09:28:00.150821 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4055 09:28:00.154175 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4056 09:28:00.160775 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4057 09:28:00.164262 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4058 09:28:00.167673 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4059 09:28:00.171058 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4060 09:28:00.174254 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4061 09:28:00.180893 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4062 09:28:00.184496 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4063 09:28:00.187885 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4064 09:28:00.190932 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4065 09:28:00.197493 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4066 09:28:00.200828 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4067 09:28:00.200923 ==
4068 09:28:00.204426 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 09:28:00.207708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 09:28:00.207828 ==
4071 09:28:00.210854 DQS Delay:
4072 09:28:00.210947 DQS0 = 0, DQS1 = 0
4073 09:28:00.211017 DQM Delay:
4074 09:28:00.214256 DQM0 = 53, DQM1 = 42
4075 09:28:00.214350 DQ Delay:
4076 09:28:00.218239 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4077 09:28:00.220856 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4078 09:28:00.224634 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4079 09:28:00.227400 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4080 09:28:00.227526
4081 09:28:00.227596
4082 09:28:00.227666 ==
4083 09:28:00.230937 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 09:28:00.237498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 09:28:00.237620 ==
4086 09:28:00.237694
4087 09:28:00.237757
4088 09:28:00.237818 TX Vref Scan disable
4089 09:28:00.241618 == TX Byte 0 ==
4090 09:28:00.244533 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4091 09:28:00.247886 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4092 09:28:00.251003 == TX Byte 1 ==
4093 09:28:00.255027 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4094 09:28:00.261069 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4095 09:28:00.261201 ==
4096 09:28:00.264265 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 09:28:00.267819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 09:28:00.267932 ==
4099 09:28:00.268003
4100 09:28:00.268066
4101 09:28:00.270969 TX Vref Scan disable
4102 09:28:00.274470 == TX Byte 0 ==
4103 09:28:00.277715 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4104 09:28:00.281284 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4105 09:28:00.284543 == TX Byte 1 ==
4106 09:28:00.287710 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4107 09:28:00.291396 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4108 09:28:00.291513
4109 09:28:00.291617 [DATLAT]
4110 09:28:00.294805 Freq=600, CH0 RK0
4111 09:28:00.294920
4112 09:28:00.295017 DATLAT Default: 0x9
4113 09:28:00.298102 0, 0xFFFF, sum = 0
4114 09:28:00.298208 1, 0xFFFF, sum = 0
4115 09:28:00.301275 2, 0xFFFF, sum = 0
4116 09:28:00.304745 3, 0xFFFF, sum = 0
4117 09:28:00.304835 4, 0xFFFF, sum = 0
4118 09:28:00.307685 5, 0xFFFF, sum = 0
4119 09:28:00.307772 6, 0xFFFF, sum = 0
4120 09:28:00.311364 7, 0xFFFF, sum = 0
4121 09:28:00.311451 8, 0x0, sum = 1
4122 09:28:00.311537 9, 0x0, sum = 2
4123 09:28:00.314395 10, 0x0, sum = 3
4124 09:28:00.314482 11, 0x0, sum = 4
4125 09:28:00.318019 best_step = 9
4126 09:28:00.318104
4127 09:28:00.318189 ==
4128 09:28:00.321129 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 09:28:00.324370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 09:28:00.324457 ==
4131 09:28:00.327708 RX Vref Scan: 1
4132 09:28:00.327794
4133 09:28:00.327878 RX Vref 0 -> 0, step: 1
4134 09:28:00.327957
4135 09:28:00.331181 RX Delay -179 -> 252, step: 8
4136 09:28:00.331265
4137 09:28:00.335111 Set Vref, RX VrefLevel [Byte0]: 60
4138 09:28:00.337794 [Byte1]: 51
4139 09:28:00.341552
4140 09:28:00.341637 Final RX Vref Byte 0 = 60 to rank0
4141 09:28:00.345498 Final RX Vref Byte 1 = 51 to rank0
4142 09:28:00.348532 Final RX Vref Byte 0 = 60 to rank1
4143 09:28:00.351780 Final RX Vref Byte 1 = 51 to rank1==
4144 09:28:00.355526 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 09:28:00.358528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 09:28:00.361790 ==
4147 09:28:00.361879 DQS Delay:
4148 09:28:00.361964 DQS0 = 0, DQS1 = 0
4149 09:28:00.365079 DQM Delay:
4150 09:28:00.365164 DQM0 = 48, DQM1 = 40
4151 09:28:00.368361 DQ Delay:
4152 09:28:00.371689 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4153 09:28:00.371777 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4154 09:28:00.375125 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =36
4155 09:28:00.381548 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4156 09:28:00.381638
4157 09:28:00.381726
4158 09:28:00.388580 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4159 09:28:00.391703 CH0 RK0: MR19=808, MR18=5C56
4160 09:28:00.398226 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4161 09:28:00.398324
4162 09:28:00.401498 ----->DramcWriteLeveling(PI) begin...
4163 09:28:00.401587 ==
4164 09:28:00.405021 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 09:28:00.408711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 09:28:00.408799 ==
4167 09:28:00.411276 Write leveling (Byte 0): 33 => 33
4168 09:28:00.414836 Write leveling (Byte 1): 31 => 31
4169 09:28:00.418231 DramcWriteLeveling(PI) end<-----
4170 09:28:00.418318
4171 09:28:00.418404 ==
4172 09:28:00.421363 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 09:28:00.424811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 09:28:00.424923 ==
4175 09:28:00.428024 [Gating] SW mode calibration
4176 09:28:00.434876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 09:28:00.441417 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 09:28:00.444514 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 09:28:00.451341 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 09:28:00.454674 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 09:28:00.457924 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4182 09:28:00.464601 0 9 16 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4183 09:28:00.467613 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 09:28:00.471022 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 09:28:00.474298 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 09:28:00.481089 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 09:28:00.484117 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 09:28:00.487531 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 09:28:00.494108 0 10 12 | B1->B0 | 2f2e 3534 | 1 1 | (0 0) (0 0)
4190 09:28:00.497842 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4191 09:28:00.500909 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 09:28:00.507572 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 09:28:00.510960 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 09:28:00.514522 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 09:28:00.520819 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 09:28:00.524291 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 09:28:00.527697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4198 09:28:00.534093 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 09:28:00.537747 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 09:28:00.540808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 09:28:00.547921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 09:28:00.550950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 09:28:00.554276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 09:28:00.560763 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 09:28:00.564019 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 09:28:00.567603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 09:28:00.574333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 09:28:00.577676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 09:28:00.580877 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 09:28:00.587447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 09:28:00.591292 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 09:28:00.594007 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 09:28:00.597671 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4214 09:28:00.604109 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 09:28:00.607414 Total UI for P1: 0, mck2ui 16
4216 09:28:00.611329 best dqsien dly found for B0: ( 0, 13, 12)
4217 09:28:00.614209 Total UI for P1: 0, mck2ui 16
4218 09:28:00.617707 best dqsien dly found for B1: ( 0, 13, 12)
4219 09:28:00.620745 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4220 09:28:00.623979 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4221 09:28:00.624057
4222 09:28:00.627368 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4223 09:28:00.630841 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4224 09:28:00.635033 [Gating] SW calibration Done
4225 09:28:00.635119 ==
4226 09:28:00.637261 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 09:28:00.640537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 09:28:00.640623 ==
4229 09:28:00.644571 RX Vref Scan: 0
4230 09:28:00.644656
4231 09:28:00.647506 RX Vref 0 -> 0, step: 1
4232 09:28:00.647591
4233 09:28:00.647676 RX Delay -230 -> 252, step: 16
4234 09:28:00.653974 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 09:28:00.657355 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4236 09:28:00.660460 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4237 09:28:00.664089 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4238 09:28:00.670908 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4239 09:28:00.674181 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4240 09:28:00.677163 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4241 09:28:00.680194 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4242 09:28:00.684095 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4243 09:28:00.690619 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4244 09:28:00.693839 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4245 09:28:00.697022 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4246 09:28:00.700212 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4247 09:28:00.706918 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4248 09:28:00.710228 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4249 09:28:00.713585 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4250 09:28:00.713673 ==
4251 09:28:00.716713 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 09:28:00.720036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 09:28:00.724010 ==
4254 09:28:00.724119 DQS Delay:
4255 09:28:00.724206 DQS0 = 0, DQS1 = 0
4256 09:28:00.726993 DQM Delay:
4257 09:28:00.727080 DQM0 = 48, DQM1 = 43
4258 09:28:00.730279 DQ Delay:
4259 09:28:00.733627 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4260 09:28:00.733710 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4261 09:28:00.736589 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4262 09:28:00.740618 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4263 09:28:00.743743
4264 09:28:00.743829
4265 09:28:00.743915 ==
4266 09:28:00.746616 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 09:28:00.750551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 09:28:00.750640 ==
4269 09:28:00.750726
4270 09:28:00.750805
4271 09:28:00.753313 TX Vref Scan disable
4272 09:28:00.753399 == TX Byte 0 ==
4273 09:28:00.760011 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4274 09:28:00.763473 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4275 09:28:00.763563 == TX Byte 1 ==
4276 09:28:00.770426 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4277 09:28:00.773359 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4278 09:28:00.773448 ==
4279 09:28:00.776746 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 09:28:00.779912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 09:28:00.779999 ==
4282 09:28:00.780085
4283 09:28:00.780164
4284 09:28:00.783553 TX Vref Scan disable
4285 09:28:00.786692 == TX Byte 0 ==
4286 09:28:00.790577 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4287 09:28:00.793277 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4288 09:28:00.796806 == TX Byte 1 ==
4289 09:28:00.800416 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 09:28:00.803560 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 09:28:00.803648
4292 09:28:00.806564 [DATLAT]
4293 09:28:00.806650 Freq=600, CH0 RK1
4294 09:28:00.806747
4295 09:28:00.810042 DATLAT Default: 0x9
4296 09:28:00.810127 0, 0xFFFF, sum = 0
4297 09:28:00.813418 1, 0xFFFF, sum = 0
4298 09:28:00.813504 2, 0xFFFF, sum = 0
4299 09:28:00.816871 3, 0xFFFF, sum = 0
4300 09:28:00.817014 4, 0xFFFF, sum = 0
4301 09:28:00.819866 5, 0xFFFF, sum = 0
4302 09:28:00.819953 6, 0xFFFF, sum = 0
4303 09:28:00.823164 7, 0xFFFF, sum = 0
4304 09:28:00.823251 8, 0x0, sum = 1
4305 09:28:00.827079 9, 0x0, sum = 2
4306 09:28:00.827169 10, 0x0, sum = 3
4307 09:28:00.830665 11, 0x0, sum = 4
4308 09:28:00.830782 best_step = 9
4309 09:28:00.830855
4310 09:28:00.830918 ==
4311 09:28:00.833437 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 09:28:00.836966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 09:28:00.840219 ==
4314 09:28:00.840295 RX Vref Scan: 0
4315 09:28:00.840358
4316 09:28:00.843450 RX Vref 0 -> 0, step: 1
4317 09:28:00.843532
4318 09:28:00.846690 RX Delay -163 -> 252, step: 8
4319 09:28:00.849769 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4320 09:28:00.853102 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4321 09:28:00.860072 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4322 09:28:00.863221 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4323 09:28:00.867070 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4324 09:28:00.870168 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4325 09:28:00.873128 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4326 09:28:00.879676 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4327 09:28:00.883768 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4328 09:28:00.886472 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4329 09:28:00.889994 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4330 09:28:00.896741 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4331 09:28:00.899807 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4332 09:28:00.903261 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4333 09:28:00.906834 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4334 09:28:00.909887 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4335 09:28:00.909972 ==
4336 09:28:00.913307 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 09:28:00.920292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 09:28:00.920390 ==
4339 09:28:00.920462 DQS Delay:
4340 09:28:00.923576 DQS0 = 0, DQS1 = 0
4341 09:28:00.923660 DQM Delay:
4342 09:28:00.923726 DQM0 = 49, DQM1 = 41
4343 09:28:00.926410 DQ Delay:
4344 09:28:00.929820 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4345 09:28:00.933322 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4346 09:28:00.936334 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4347 09:28:00.939948 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4348 09:28:00.940034
4349 09:28:00.940101
4350 09:28:00.946289 [DQSOSCAuto] RK1, (LSB)MR18= 0x6633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4351 09:28:00.949634 CH0 RK1: MR19=808, MR18=6633
4352 09:28:00.956368 CH0_RK1: MR19=0x808, MR18=0x6633, DQSOSC=390, MR23=63, INC=172, DEC=114
4353 09:28:00.959690 [RxdqsGatingPostProcess] freq 600
4354 09:28:00.963017 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 09:28:00.966412 Pre-setting of DQS Precalculation
4356 09:28:00.973116 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 09:28:00.973213 ==
4358 09:28:00.976779 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 09:28:00.980041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 09:28:00.980127 ==
4361 09:28:00.986923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 09:28:00.989902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4363 09:28:00.994553 [CA 0] Center 35 (5~66) winsize 62
4364 09:28:00.997634 [CA 1] Center 35 (5~66) winsize 62
4365 09:28:01.000873 [CA 2] Center 34 (4~65) winsize 62
4366 09:28:01.004252 [CA 3] Center 33 (3~64) winsize 62
4367 09:28:01.007547 [CA 4] Center 34 (3~65) winsize 63
4368 09:28:01.010808 [CA 5] Center 33 (3~64) winsize 62
4369 09:28:01.010904
4370 09:28:01.014196 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4371 09:28:01.014282
4372 09:28:01.017563 [CATrainingPosCal] consider 1 rank data
4373 09:28:01.020840 u2DelayCellTimex100 = 270/100 ps
4374 09:28:01.024307 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 09:28:01.030703 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 09:28:01.034053 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 09:28:01.037700 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 09:28:01.040774 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4379 09:28:01.044065 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 09:28:01.044152
4381 09:28:01.047617 CA PerBit enable=1, Macro0, CA PI delay=33
4382 09:28:01.047702
4383 09:28:01.050917 [CBTSetCACLKResult] CA Dly = 33
4384 09:28:01.051002 CS Dly: 4 (0~35)
4385 09:28:01.054021 ==
4386 09:28:01.057957 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 09:28:01.060787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 09:28:01.060875 ==
4389 09:28:01.064078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 09:28:01.070943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4391 09:28:01.074624 [CA 0] Center 35 (5~66) winsize 62
4392 09:28:01.077701 [CA 1] Center 35 (5~66) winsize 62
4393 09:28:01.081051 [CA 2] Center 34 (4~65) winsize 62
4394 09:28:01.084195 [CA 3] Center 34 (4~65) winsize 62
4395 09:28:01.087766 [CA 4] Center 34 (4~65) winsize 62
4396 09:28:01.091097 [CA 5] Center 34 (4~65) winsize 62
4397 09:28:01.091182
4398 09:28:01.094832 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4399 09:28:01.094920
4400 09:28:01.097864 [CATrainingPosCal] consider 2 rank data
4401 09:28:01.100856 u2DelayCellTimex100 = 270/100 ps
4402 09:28:01.104713 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4403 09:28:01.107498 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4404 09:28:01.114823 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 09:28:01.117736 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4406 09:28:01.121817 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 09:28:01.124329 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4408 09:28:01.124420
4409 09:28:01.127582 CA PerBit enable=1, Macro0, CA PI delay=34
4410 09:28:01.127707
4411 09:28:01.130794 [CBTSetCACLKResult] CA Dly = 34
4412 09:28:01.130882 CS Dly: 5 (0~37)
4413 09:28:01.130949
4414 09:28:01.134359 ----->DramcWriteLeveling(PI) begin...
4415 09:28:01.137503 ==
4416 09:28:01.137592 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 09:28:01.144318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 09:28:01.144420 ==
4419 09:28:01.147843 Write leveling (Byte 0): 29 => 29
4420 09:28:01.150995 Write leveling (Byte 1): 30 => 30
4421 09:28:01.154492 DramcWriteLeveling(PI) end<-----
4422 09:28:01.154602
4423 09:28:01.154684 ==
4424 09:28:01.157914 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 09:28:01.161213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 09:28:01.161301 ==
4427 09:28:01.164534 [Gating] SW mode calibration
4428 09:28:01.171282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 09:28:01.174420 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 09:28:01.180871 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 09:28:01.184268 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 09:28:01.187546 0 9 8 | B1->B0 | 3333 3333 | 1 0 | (1 0) (0 0)
4433 09:28:01.194565 0 9 12 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
4434 09:28:01.198130 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 09:28:01.201797 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 09:28:01.207864 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 09:28:01.210965 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 09:28:01.214563 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 09:28:01.220879 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 09:28:01.224400 0 10 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4441 09:28:01.227823 0 10 12 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
4442 09:28:01.234324 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 09:28:01.237407 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 09:28:01.241066 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 09:28:01.247676 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 09:28:01.250964 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 09:28:01.254148 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 09:28:01.260735 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4449 09:28:01.263890 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 09:28:01.267648 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 09:28:01.273943 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 09:28:01.277477 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 09:28:01.280841 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 09:28:01.283928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 09:28:01.290524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 09:28:01.293884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 09:28:01.297564 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 09:28:01.303709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:28:01.307204 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 09:28:01.310658 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 09:28:01.317225 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 09:28:01.320388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 09:28:01.323877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 09:28:01.330488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4465 09:28:01.333780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4466 09:28:01.337288 Total UI for P1: 0, mck2ui 16
4467 09:28:01.340774 best dqsien dly found for B0: ( 0, 13, 8)
4468 09:28:01.343864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 09:28:01.346905 Total UI for P1: 0, mck2ui 16
4470 09:28:01.350765 best dqsien dly found for B1: ( 0, 13, 12)
4471 09:28:01.353556 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4472 09:28:01.356827 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4473 09:28:01.356988
4474 09:28:01.363830 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4475 09:28:01.366878 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 09:28:01.366970 [Gating] SW calibration Done
4477 09:28:01.370343 ==
4478 09:28:01.373699 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 09:28:01.377117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 09:28:01.377206 ==
4481 09:28:01.377274 RX Vref Scan: 0
4482 09:28:01.377337
4483 09:28:01.380126 RX Vref 0 -> 0, step: 1
4484 09:28:01.380211
4485 09:28:01.383470 RX Delay -230 -> 252, step: 16
4486 09:28:01.386837 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4487 09:28:01.390223 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4488 09:28:01.396865 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4489 09:28:01.400275 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4490 09:28:01.403952 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4491 09:28:01.407421 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4492 09:28:01.410274 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4493 09:28:01.417169 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4494 09:28:01.420352 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4495 09:28:01.423723 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4496 09:28:01.426845 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4497 09:28:01.433376 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4498 09:28:01.436911 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4499 09:28:01.440507 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4500 09:28:01.443741 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4501 09:28:01.450690 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4502 09:28:01.450789 ==
4503 09:28:01.453442 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 09:28:01.456835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 09:28:01.456951 ==
4506 09:28:01.457074 DQS Delay:
4507 09:28:01.460017 DQS0 = 0, DQS1 = 0
4508 09:28:01.460104 DQM Delay:
4509 09:28:01.463355 DQM0 = 45, DQM1 = 43
4510 09:28:01.463443 DQ Delay:
4511 09:28:01.466875 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4512 09:28:01.470126 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4513 09:28:01.473626 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4514 09:28:01.476963 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4515 09:28:01.477067
4516 09:28:01.477136
4517 09:28:01.477200 ==
4518 09:28:01.480309 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 09:28:01.483224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 09:28:01.483310 ==
4521 09:28:01.483377
4522 09:28:01.486592
4523 09:28:01.486676 TX Vref Scan disable
4524 09:28:01.490227 == TX Byte 0 ==
4525 09:28:01.493310 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4526 09:28:01.496588 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4527 09:28:01.500020 == TX Byte 1 ==
4528 09:28:01.503227 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4529 09:28:01.507150 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4530 09:28:01.507237 ==
4531 09:28:01.510134 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 09:28:01.516556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 09:28:01.516646 ==
4534 09:28:01.516714
4535 09:28:01.516775
4536 09:28:01.516834 TX Vref Scan disable
4537 09:28:01.521192 == TX Byte 0 ==
4538 09:28:01.524602 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4539 09:28:01.527912 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4540 09:28:01.530992 == TX Byte 1 ==
4541 09:28:01.534091 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4542 09:28:01.540897 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4543 09:28:01.541003
4544 09:28:01.541073 [DATLAT]
4545 09:28:01.541137 Freq=600, CH1 RK0
4546 09:28:01.541198
4547 09:28:01.544210 DATLAT Default: 0x9
4548 09:28:01.544297 0, 0xFFFF, sum = 0
4549 09:28:01.547501 1, 0xFFFF, sum = 0
4550 09:28:01.547589 2, 0xFFFF, sum = 0
4551 09:28:01.551041 3, 0xFFFF, sum = 0
4552 09:28:01.554257 4, 0xFFFF, sum = 0
4553 09:28:01.554347 5, 0xFFFF, sum = 0
4554 09:28:01.557745 6, 0xFFFF, sum = 0
4555 09:28:01.557837 7, 0xFFFF, sum = 0
4556 09:28:01.560836 8, 0x0, sum = 1
4557 09:28:01.560984 9, 0x0, sum = 2
4558 09:28:01.561055 10, 0x0, sum = 3
4559 09:28:01.564387 11, 0x0, sum = 4
4560 09:28:01.564474 best_step = 9
4561 09:28:01.564541
4562 09:28:01.564602 ==
4563 09:28:01.567661 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 09:28:01.574381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 09:28:01.574477 ==
4566 09:28:01.574545 RX Vref Scan: 1
4567 09:28:01.574605
4568 09:28:01.578030 RX Vref 0 -> 0, step: 1
4569 09:28:01.578118
4570 09:28:01.581127 RX Delay -179 -> 252, step: 8
4571 09:28:01.581212
4572 09:28:01.584804 Set Vref, RX VrefLevel [Byte0]: 54
4573 09:28:01.587740 [Byte1]: 52
4574 09:28:01.587825
4575 09:28:01.591292 Final RX Vref Byte 0 = 54 to rank0
4576 09:28:01.594364 Final RX Vref Byte 1 = 52 to rank0
4577 09:28:01.598130 Final RX Vref Byte 0 = 54 to rank1
4578 09:28:01.601115 Final RX Vref Byte 1 = 52 to rank1==
4579 09:28:01.604497 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 09:28:01.607837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 09:28:01.607925 ==
4582 09:28:01.611350 DQS Delay:
4583 09:28:01.611436 DQS0 = 0, DQS1 = 0
4584 09:28:01.611502 DQM Delay:
4585 09:28:01.614564 DQM0 = 44, DQM1 = 39
4586 09:28:01.614648 DQ Delay:
4587 09:28:01.617843 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4588 09:28:01.620948 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4589 09:28:01.624669 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4590 09:28:01.627633 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4591 09:28:01.627721
4592 09:28:01.627788
4593 09:28:01.638056 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f76, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4594 09:28:01.638172 CH1 RK0: MR19=808, MR18=4F76
4595 09:28:01.644590 CH1_RK0: MR19=0x808, MR18=0x4F76, DQSOSC=387, MR23=63, INC=175, DEC=116
4596 09:28:01.644687
4597 09:28:01.648244 ----->DramcWriteLeveling(PI) begin...
4598 09:28:01.648332 ==
4599 09:28:01.651265 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 09:28:01.657517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 09:28:01.657627 ==
4602 09:28:01.661170 Write leveling (Byte 0): 30 => 30
4603 09:28:01.664448 Write leveling (Byte 1): 28 => 28
4604 09:28:01.664537 DramcWriteLeveling(PI) end<-----
4605 09:28:01.667422
4606 09:28:01.667508 ==
4607 09:28:01.670769 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 09:28:01.674154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 09:28:01.674245 ==
4610 09:28:01.677339 [Gating] SW mode calibration
4611 09:28:01.683764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 09:28:01.687145 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 09:28:01.693931 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 09:28:01.697244 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 09:28:01.700764 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4616 09:28:01.707371 0 9 12 | B1->B0 | 2a2a 2f2f | 0 0 | (1 1) (0 1)
4617 09:28:01.710501 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 09:28:01.714078 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 09:28:01.720966 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 09:28:01.723895 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 09:28:01.727482 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 09:28:01.733716 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 09:28:01.737041 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4624 09:28:01.740163 0 10 12 | B1->B0 | 3b3b 3535 | 0 0 | (1 1) (0 0)
4625 09:28:01.746609 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 09:28:01.750202 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 09:28:01.753525 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 09:28:01.760294 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 09:28:01.763778 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 09:28:01.767019 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 09:28:01.773381 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 09:28:01.776872 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4633 09:28:01.780090 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 09:28:01.786601 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 09:28:01.790096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 09:28:01.793583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 09:28:01.799950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 09:28:01.803296 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 09:28:01.806931 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 09:28:01.813341 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 09:28:01.816817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 09:28:01.820445 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 09:28:01.823497 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 09:28:01.830198 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 09:28:01.833379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 09:28:01.837212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 09:28:01.843730 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 09:28:01.846899 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4649 09:28:01.849785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 09:28:01.853445 Total UI for P1: 0, mck2ui 16
4651 09:28:01.857157 best dqsien dly found for B0: ( 0, 13, 12)
4652 09:28:01.859812 Total UI for P1: 0, mck2ui 16
4653 09:28:01.863494 best dqsien dly found for B1: ( 0, 13, 12)
4654 09:28:01.866633 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4655 09:28:01.873391 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4656 09:28:01.873516
4657 09:28:01.876565 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4658 09:28:01.879762 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4659 09:28:01.883379 [Gating] SW calibration Done
4660 09:28:01.883475 ==
4661 09:28:01.886467 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 09:28:01.890018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 09:28:01.890111 ==
4664 09:28:01.890180 RX Vref Scan: 0
4665 09:28:01.893231
4666 09:28:01.893318 RX Vref 0 -> 0, step: 1
4667 09:28:01.893385
4668 09:28:01.896459 RX Delay -230 -> 252, step: 16
4669 09:28:01.900640 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4670 09:28:01.906488 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4671 09:28:01.909700 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4672 09:28:01.913493 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4673 09:28:01.916470 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4674 09:28:01.919728 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4675 09:28:01.926136 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4676 09:28:01.929576 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4677 09:28:01.933119 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4678 09:28:01.936358 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4679 09:28:01.943076 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4680 09:28:01.946444 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4681 09:28:01.949881 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4682 09:28:01.953045 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4683 09:28:01.959779 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4684 09:28:01.962811 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4685 09:28:01.962902 ==
4686 09:28:01.966185 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 09:28:01.969833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 09:28:01.969919 ==
4689 09:28:01.969985 DQS Delay:
4690 09:28:01.973145 DQS0 = 0, DQS1 = 0
4691 09:28:01.973230 DQM Delay:
4692 09:28:01.976096 DQM0 = 49, DQM1 = 45
4693 09:28:01.976178 DQ Delay:
4694 09:28:01.979699 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4695 09:28:01.982771 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4696 09:28:01.986282 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4697 09:28:01.989495 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4698 09:28:01.989583
4699 09:28:01.989649
4700 09:28:01.989709 ==
4701 09:28:01.992616 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 09:28:01.996362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 09:28:01.999540 ==
4704 09:28:01.999628
4705 09:28:01.999694
4706 09:28:01.999754 TX Vref Scan disable
4707 09:28:02.002857 == TX Byte 0 ==
4708 09:28:02.006702 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4709 09:28:02.012692 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4710 09:28:02.012818 == TX Byte 1 ==
4711 09:28:02.016282 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4712 09:28:02.022950 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4713 09:28:02.023052 ==
4714 09:28:02.026025 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 09:28:02.029522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 09:28:02.029616 ==
4717 09:28:02.029705
4718 09:28:02.029787
4719 09:28:02.032670 TX Vref Scan disable
4720 09:28:02.036390 == TX Byte 0 ==
4721 09:28:02.039058 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 09:28:02.042545 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 09:28:02.045719 == TX Byte 1 ==
4724 09:28:02.048943 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4725 09:28:02.052900 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4726 09:28:02.053029
4727 09:28:02.053115 [DATLAT]
4728 09:28:02.055855 Freq=600, CH1 RK1
4729 09:28:02.055962
4730 09:28:02.056049 DATLAT Default: 0x9
4731 09:28:02.059197 0, 0xFFFF, sum = 0
4732 09:28:02.062391 1, 0xFFFF, sum = 0
4733 09:28:02.062482 2, 0xFFFF, sum = 0
4734 09:28:02.065704 3, 0xFFFF, sum = 0
4735 09:28:02.065794 4, 0xFFFF, sum = 0
4736 09:28:02.069110 5, 0xFFFF, sum = 0
4737 09:28:02.069198 6, 0xFFFF, sum = 0
4738 09:28:02.072361 7, 0xFFFF, sum = 0
4739 09:28:02.072449 8, 0x0, sum = 1
4740 09:28:02.072537 9, 0x0, sum = 2
4741 09:28:02.075652 10, 0x0, sum = 3
4742 09:28:02.075740 11, 0x0, sum = 4
4743 09:28:02.079168 best_step = 9
4744 09:28:02.079254
4745 09:28:02.079341 ==
4746 09:28:02.082532 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 09:28:02.085762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 09:28:02.085854 ==
4749 09:28:02.089369 RX Vref Scan: 0
4750 09:28:02.089456
4751 09:28:02.089542 RX Vref 0 -> 0, step: 1
4752 09:28:02.089624
4753 09:28:02.092380 RX Delay -179 -> 252, step: 8
4754 09:28:02.099740 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4755 09:28:02.103102 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4756 09:28:02.106671 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4757 09:28:02.109728 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4758 09:28:02.116250 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4759 09:28:02.119936 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4760 09:28:02.122990 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4761 09:28:02.126441 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4762 09:28:02.129597 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4763 09:28:02.136086 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4764 09:28:02.139451 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4765 09:28:02.143203 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4766 09:28:02.146306 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4767 09:28:02.149618 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4768 09:28:02.156259 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4769 09:28:02.159554 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4770 09:28:02.159650 ==
4771 09:28:02.162984 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 09:28:02.165957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 09:28:02.166044 ==
4774 09:28:02.169825 DQS Delay:
4775 09:28:02.169912 DQS0 = 0, DQS1 = 0
4776 09:28:02.169979 DQM Delay:
4777 09:28:02.172628 DQM0 = 46, DQM1 = 41
4778 09:28:02.172713 DQ Delay:
4779 09:28:02.175988 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4780 09:28:02.179395 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4781 09:28:02.182664 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =36
4782 09:28:02.186170 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =52
4783 09:28:02.186256
4784 09:28:02.186324
4785 09:28:02.196252 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4786 09:28:02.196346 CH1 RK1: MR19=808, MR18=5D23
4787 09:28:02.203118 CH1_RK1: MR19=0x808, MR18=0x5D23, DQSOSC=392, MR23=63, INC=170, DEC=113
4788 09:28:02.205898 [RxdqsGatingPostProcess] freq 600
4789 09:28:02.212709 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 09:28:02.215849 Pre-setting of DQS Precalculation
4791 09:28:02.219252 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 09:28:02.226060 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 09:28:02.235824 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 09:28:02.235942
4795 09:28:02.236010
4796 09:28:02.239228 [Calibration Summary] 1200 Mbps
4797 09:28:02.239314 CH 0, Rank 0
4798 09:28:02.242759 SW Impedance : PASS
4799 09:28:02.242843 DUTY Scan : NO K
4800 09:28:02.245663 ZQ Calibration : PASS
4801 09:28:02.249391 Jitter Meter : NO K
4802 09:28:02.249476 CBT Training : PASS
4803 09:28:02.252599 Write leveling : PASS
4804 09:28:02.252682 RX DQS gating : PASS
4805 09:28:02.255906 RX DQ/DQS(RDDQC) : PASS
4806 09:28:02.259616 TX DQ/DQS : PASS
4807 09:28:02.259706 RX DATLAT : PASS
4808 09:28:02.262899 RX DQ/DQS(Engine): PASS
4809 09:28:02.266080 TX OE : NO K
4810 09:28:02.266166 All Pass.
4811 09:28:02.266232
4812 09:28:02.266294 CH 0, Rank 1
4813 09:28:02.269459 SW Impedance : PASS
4814 09:28:02.272756 DUTY Scan : NO K
4815 09:28:02.272840 ZQ Calibration : PASS
4816 09:28:02.275790 Jitter Meter : NO K
4817 09:28:02.279404 CBT Training : PASS
4818 09:28:02.279487 Write leveling : PASS
4819 09:28:02.282508 RX DQS gating : PASS
4820 09:28:02.286002 RX DQ/DQS(RDDQC) : PASS
4821 09:28:02.286085 TX DQ/DQS : PASS
4822 09:28:02.289248 RX DATLAT : PASS
4823 09:28:02.293076 RX DQ/DQS(Engine): PASS
4824 09:28:02.293158 TX OE : NO K
4825 09:28:02.293225 All Pass.
4826 09:28:02.295861
4827 09:28:02.295942 CH 1, Rank 0
4828 09:28:02.299163 SW Impedance : PASS
4829 09:28:02.299247 DUTY Scan : NO K
4830 09:28:02.302824 ZQ Calibration : PASS
4831 09:28:02.302906 Jitter Meter : NO K
4832 09:28:02.306041 CBT Training : PASS
4833 09:28:02.309693 Write leveling : PASS
4834 09:28:02.309776 RX DQS gating : PASS
4835 09:28:02.312877 RX DQ/DQS(RDDQC) : PASS
4836 09:28:02.315795 TX DQ/DQS : PASS
4837 09:28:02.315878 RX DATLAT : PASS
4838 09:28:02.319379 RX DQ/DQS(Engine): PASS
4839 09:28:02.323220 TX OE : NO K
4840 09:28:02.323306 All Pass.
4841 09:28:02.323372
4842 09:28:02.323434 CH 1, Rank 1
4843 09:28:02.325947 SW Impedance : PASS
4844 09:28:02.329446 DUTY Scan : NO K
4845 09:28:02.329531 ZQ Calibration : PASS
4846 09:28:02.332576 Jitter Meter : NO K
4847 09:28:02.335830 CBT Training : PASS
4848 09:28:02.335912 Write leveling : PASS
4849 09:28:02.339062 RX DQS gating : PASS
4850 09:28:02.339146 RX DQ/DQS(RDDQC) : PASS
4851 09:28:02.342680 TX DQ/DQS : PASS
4852 09:28:02.346084 RX DATLAT : PASS
4853 09:28:02.346168 RX DQ/DQS(Engine): PASS
4854 09:28:02.349510 TX OE : NO K
4855 09:28:02.349593 All Pass.
4856 09:28:02.349659
4857 09:28:02.352529 DramC Write-DBI off
4858 09:28:02.355805 PER_BANK_REFRESH: Hybrid Mode
4859 09:28:02.355891 TX_TRACKING: ON
4860 09:28:02.365958 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 09:28:02.368873 [FAST_K] Save calibration result to emmc
4862 09:28:02.372259 dramc_set_vcore_voltage set vcore to 662500
4863 09:28:02.375933 Read voltage for 933, 3
4864 09:28:02.376018 Vio18 = 0
4865 09:28:02.378825 Vcore = 662500
4866 09:28:02.378909 Vdram = 0
4867 09:28:02.378975 Vddq = 0
4868 09:28:02.379036 Vmddr = 0
4869 09:28:02.385571 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 09:28:02.388774 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 09:28:02.392087 MEM_TYPE=3, freq_sel=17
4872 09:28:02.395528 sv_algorithm_assistance_LP4_1600
4873 09:28:02.399307 ============ PULL DRAM RESETB DOWN ============
4874 09:28:02.405600 ========== PULL DRAM RESETB DOWN end =========
4875 09:28:02.408903 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 09:28:02.412128 ===================================
4877 09:28:02.415643 LPDDR4 DRAM CONFIGURATION
4878 09:28:02.418549 ===================================
4879 09:28:02.418635 EX_ROW_EN[0] = 0x0
4880 09:28:02.422260 EX_ROW_EN[1] = 0x0
4881 09:28:02.422345 LP4Y_EN = 0x0
4882 09:28:02.425118 WORK_FSP = 0x0
4883 09:28:02.425203 WL = 0x3
4884 09:28:02.428527 RL = 0x3
4885 09:28:02.428612 BL = 0x2
4886 09:28:02.432010 RPST = 0x0
4887 09:28:02.432094 RD_PRE = 0x0
4888 09:28:02.435253 WR_PRE = 0x1
4889 09:28:02.439459 WR_PST = 0x0
4890 09:28:02.439544 DBI_WR = 0x0
4891 09:28:02.441909 DBI_RD = 0x0
4892 09:28:02.441994 OTF = 0x1
4893 09:28:02.445344 ===================================
4894 09:28:02.449037 ===================================
4895 09:28:02.449122 ANA top config
4896 09:28:02.452084 ===================================
4897 09:28:02.455307 DLL_ASYNC_EN = 0
4898 09:28:02.459105 ALL_SLAVE_EN = 1
4899 09:28:02.462231 NEW_RANK_MODE = 1
4900 09:28:02.465271 DLL_IDLE_MODE = 1
4901 09:28:02.465358 LP45_APHY_COMB_EN = 1
4902 09:28:02.468779 TX_ODT_DIS = 1
4903 09:28:02.471889 NEW_8X_MODE = 1
4904 09:28:02.475337 ===================================
4905 09:28:02.478394 ===================================
4906 09:28:02.481787 data_rate = 1866
4907 09:28:02.485151 CKR = 1
4908 09:28:02.485237 DQ_P2S_RATIO = 8
4909 09:28:02.488445 ===================================
4910 09:28:02.491974 CA_P2S_RATIO = 8
4911 09:28:02.495282 DQ_CA_OPEN = 0
4912 09:28:02.498484 DQ_SEMI_OPEN = 0
4913 09:28:02.501755 CA_SEMI_OPEN = 0
4914 09:28:02.505035 CA_FULL_RATE = 0
4915 09:28:02.505121 DQ_CKDIV4_EN = 1
4916 09:28:02.508627 CA_CKDIV4_EN = 1
4917 09:28:02.511812 CA_PREDIV_EN = 0
4918 09:28:02.515219 PH8_DLY = 0
4919 09:28:02.519027 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 09:28:02.521946 DQ_AAMCK_DIV = 4
4921 09:28:02.522030 CA_AAMCK_DIV = 4
4922 09:28:02.525077 CA_ADMCK_DIV = 4
4923 09:28:02.528641 DQ_TRACK_CA_EN = 0
4924 09:28:02.531919 CA_PICK = 933
4925 09:28:02.535385 CA_MCKIO = 933
4926 09:28:02.538618 MCKIO_SEMI = 0
4927 09:28:02.538703 PLL_FREQ = 3732
4928 09:28:02.541908 DQ_UI_PI_RATIO = 32
4929 09:28:02.545118 CA_UI_PI_RATIO = 0
4930 09:28:02.548202 ===================================
4931 09:28:02.551675 ===================================
4932 09:28:02.554992 memory_type:LPDDR4
4933 09:28:02.558709 GP_NUM : 10
4934 09:28:02.558795 SRAM_EN : 1
4935 09:28:02.561760 MD32_EN : 0
4936 09:28:02.565178 ===================================
4937 09:28:02.565263 [ANA_INIT] >>>>>>>>>>>>>>
4938 09:28:02.568585 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 09:28:02.571661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 09:28:02.574912 ===================================
4941 09:28:02.578549 data_rate = 1866,PCW = 0X8f00
4942 09:28:02.581484 ===================================
4943 09:28:02.585083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 09:28:02.592278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 09:28:02.594976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 09:28:02.601535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 09:28:02.604982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 09:28:02.608196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 09:28:02.611612 [ANA_INIT] flow start
4950 09:28:02.611696 [ANA_INIT] PLL >>>>>>>>
4951 09:28:02.614940 [ANA_INIT] PLL <<<<<<<<
4952 09:28:02.617977 [ANA_INIT] MIDPI >>>>>>>>
4953 09:28:02.618060 [ANA_INIT] MIDPI <<<<<<<<
4954 09:28:02.621305 [ANA_INIT] DLL >>>>>>>>
4955 09:28:02.624858 [ANA_INIT] flow end
4956 09:28:02.628249 ============ LP4 DIFF to SE enter ============
4957 09:28:02.631432 ============ LP4 DIFF to SE exit ============
4958 09:28:02.634672 [ANA_INIT] <<<<<<<<<<<<<
4959 09:28:02.638192 [Flow] Enable top DCM control >>>>>
4960 09:28:02.641265 [Flow] Enable top DCM control <<<<<
4961 09:28:02.644821 Enable DLL master slave shuffle
4962 09:28:02.647993 ==============================================================
4963 09:28:02.651232 Gating Mode config
4964 09:28:02.658233 ==============================================================
4965 09:28:02.658330 Config description:
4966 09:28:02.668180 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 09:28:02.674923 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 09:28:02.678095 SELPH_MODE 0: By rank 1: By Phase
4969 09:28:02.684785 ==============================================================
4970 09:28:02.688407 GAT_TRACK_EN = 1
4971 09:28:02.691398 RX_GATING_MODE = 2
4972 09:28:02.694848 RX_GATING_TRACK_MODE = 2
4973 09:28:02.698291 SELPH_MODE = 1
4974 09:28:02.701471 PICG_EARLY_EN = 1
4975 09:28:02.701554 VALID_LAT_VALUE = 1
4976 09:28:02.707966 ==============================================================
4977 09:28:02.712109 Enter into Gating configuration >>>>
4978 09:28:02.715079 Exit from Gating configuration <<<<
4979 09:28:02.717930 Enter into DVFS_PRE_config >>>>>
4980 09:28:02.727830 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 09:28:02.731453 Exit from DVFS_PRE_config <<<<<
4982 09:28:02.734321 Enter into PICG configuration >>>>
4983 09:28:02.738155 Exit from PICG configuration <<<<
4984 09:28:02.741140 [RX_INPUT] configuration >>>>>
4985 09:28:02.744712 [RX_INPUT] configuration <<<<<
4986 09:28:02.751325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 09:28:02.754749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 09:28:02.761427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 09:28:02.767993 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 09:28:02.774762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 09:28:02.781064 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 09:28:02.784702 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 09:28:02.787842 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 09:28:02.790922 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 09:28:02.794309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 09:28:02.801141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 09:28:02.804395 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 09:28:02.807869 ===================================
4999 09:28:02.810953 LPDDR4 DRAM CONFIGURATION
5000 09:28:02.814894 ===================================
5001 09:28:02.814975 EX_ROW_EN[0] = 0x0
5002 09:28:02.817698 EX_ROW_EN[1] = 0x0
5003 09:28:02.817783 LP4Y_EN = 0x0
5004 09:28:02.821120 WORK_FSP = 0x0
5005 09:28:02.821205 WL = 0x3
5006 09:28:02.824486 RL = 0x3
5007 09:28:02.824571 BL = 0x2
5008 09:28:02.827783 RPST = 0x0
5009 09:28:02.831217 RD_PRE = 0x0
5010 09:28:02.831302 WR_PRE = 0x1
5011 09:28:02.834530 WR_PST = 0x0
5012 09:28:02.834614 DBI_WR = 0x0
5013 09:28:02.837872 DBI_RD = 0x0
5014 09:28:02.837958 OTF = 0x1
5015 09:28:02.841231 ===================================
5016 09:28:02.844484 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 09:28:02.848118 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 09:28:02.854572 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 09:28:02.857883 ===================================
5020 09:28:02.861172 LPDDR4 DRAM CONFIGURATION
5021 09:28:02.861264 ===================================
5022 09:28:02.864667 EX_ROW_EN[0] = 0x10
5023 09:28:02.867769 EX_ROW_EN[1] = 0x0
5024 09:28:02.867855 LP4Y_EN = 0x0
5025 09:28:02.871261 WORK_FSP = 0x0
5026 09:28:02.871347 WL = 0x3
5027 09:28:02.874970 RL = 0x3
5028 09:28:02.875057 BL = 0x2
5029 09:28:02.877951 RPST = 0x0
5030 09:28:02.878037 RD_PRE = 0x0
5031 09:28:02.881026 WR_PRE = 0x1
5032 09:28:02.881110 WR_PST = 0x0
5033 09:28:02.884672 DBI_WR = 0x0
5034 09:28:02.884757 DBI_RD = 0x0
5035 09:28:02.888099 OTF = 0x1
5036 09:28:02.891313 ===================================
5037 09:28:02.897762 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 09:28:02.900974 nWR fixed to 30
5039 09:28:02.904606 [ModeRegInit_LP4] CH0 RK0
5040 09:28:02.904692 [ModeRegInit_LP4] CH0 RK1
5041 09:28:02.907678 [ModeRegInit_LP4] CH1 RK0
5042 09:28:02.911450 [ModeRegInit_LP4] CH1 RK1
5043 09:28:02.911536 match AC timing 9
5044 09:28:02.917823 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 09:28:02.921259 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 09:28:02.924429 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 09:28:02.931179 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 09:28:02.934499 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 09:28:02.934587 ==
5050 09:28:02.937948 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 09:28:02.941214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 09:28:02.941299 ==
5053 09:28:02.948004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 09:28:02.954950 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5055 09:28:02.957959 [CA 0] Center 38 (7~69) winsize 63
5056 09:28:02.961132 [CA 1] Center 38 (8~69) winsize 62
5057 09:28:02.964915 [CA 2] Center 35 (5~66) winsize 62
5058 09:28:02.967779 [CA 3] Center 34 (4~65) winsize 62
5059 09:28:02.971047 [CA 4] Center 34 (4~65) winsize 62
5060 09:28:02.974323 [CA 5] Center 33 (3~64) winsize 62
5061 09:28:02.974410
5062 09:28:02.977566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5063 09:28:02.977650
5064 09:28:02.980893 [CATrainingPosCal] consider 1 rank data
5065 09:28:02.984594 u2DelayCellTimex100 = 270/100 ps
5066 09:28:02.987827 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5067 09:28:02.990975 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5068 09:28:02.994511 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5069 09:28:02.998047 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5070 09:28:03.001280 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5071 09:28:03.004371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5072 09:28:03.004454
5073 09:28:03.007708 CA PerBit enable=1, Macro0, CA PI delay=33
5074 09:28:03.011569
5075 09:28:03.011652 [CBTSetCACLKResult] CA Dly = 33
5076 09:28:03.014295 CS Dly: 7 (0~38)
5077 09:28:03.014379 ==
5078 09:28:03.017756 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 09:28:03.021425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 09:28:03.021510 ==
5081 09:28:03.027840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 09:28:03.034284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5083 09:28:03.037586 [CA 0] Center 38 (7~69) winsize 63
5084 09:28:03.041329 [CA 1] Center 38 (8~69) winsize 62
5085 09:28:03.044298 [CA 2] Center 35 (5~66) winsize 62
5086 09:28:03.047599 [CA 3] Center 35 (5~66) winsize 62
5087 09:28:03.051221 [CA 4] Center 34 (4~65) winsize 62
5088 09:28:03.054398 [CA 5] Center 34 (4~65) winsize 62
5089 09:28:03.054483
5090 09:28:03.057406 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5091 09:28:03.057491
5092 09:28:03.060836 [CATrainingPosCal] consider 2 rank data
5093 09:28:03.064430 u2DelayCellTimex100 = 270/100 ps
5094 09:28:03.068081 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5095 09:28:03.070926 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5096 09:28:03.074390 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5097 09:28:03.077600 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5098 09:28:03.080836 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5099 09:28:03.084278 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 09:28:03.084366
5101 09:28:03.091202 CA PerBit enable=1, Macro0, CA PI delay=34
5102 09:28:03.091289
5103 09:28:03.091356 [CBTSetCACLKResult] CA Dly = 34
5104 09:28:03.094681 CS Dly: 7 (0~39)
5105 09:28:03.094765
5106 09:28:03.097555 ----->DramcWriteLeveling(PI) begin...
5107 09:28:03.097664 ==
5108 09:28:03.101076 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 09:28:03.104341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 09:28:03.104426 ==
5111 09:28:03.107929 Write leveling (Byte 0): 30 => 30
5112 09:28:03.110828 Write leveling (Byte 1): 29 => 29
5113 09:28:03.114103 DramcWriteLeveling(PI) end<-----
5114 09:28:03.114186
5115 09:28:03.114251 ==
5116 09:28:03.117511 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 09:28:03.121113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 09:28:03.124427 ==
5119 09:28:03.124510 [Gating] SW mode calibration
5120 09:28:03.130686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 09:28:03.137593 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 09:28:03.141189 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5123 09:28:03.147702 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 09:28:03.151223 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 09:28:03.154200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 09:28:03.160757 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 09:28:03.164109 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 09:28:03.167476 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5129 09:28:03.174334 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5130 09:28:03.177485 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5131 09:28:03.180644 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 09:28:03.187350 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 09:28:03.191125 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 09:28:03.194049 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 09:28:03.197275 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 09:28:03.204155 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5137 09:28:03.207498 0 15 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5138 09:28:03.210625 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5139 09:28:03.217486 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 09:28:03.220893 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 09:28:03.224176 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 09:28:03.230572 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 09:28:03.233986 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 09:28:03.237607 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5145 09:28:03.244136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5146 09:28:03.247426 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 09:28:03.250456 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 09:28:03.257109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 09:28:03.260916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 09:28:03.263776 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 09:28:03.270710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 09:28:03.273802 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 09:28:03.277070 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 09:28:03.283771 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 09:28:03.287015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 09:28:03.290269 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 09:28:03.296983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 09:28:03.300868 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 09:28:03.304255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 09:28:03.310867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5161 09:28:03.314182 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5162 09:28:03.317120 Total UI for P1: 0, mck2ui 16
5163 09:28:03.320307 best dqsien dly found for B0: ( 1, 2, 24)
5164 09:28:03.324178 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 09:28:03.326931 Total UI for P1: 0, mck2ui 16
5166 09:28:03.330649 best dqsien dly found for B1: ( 1, 2, 28)
5167 09:28:03.333695 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5168 09:28:03.337097 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5169 09:28:03.337183
5170 09:28:03.340726 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5171 09:28:03.346891 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5172 09:28:03.346979 [Gating] SW calibration Done
5173 09:28:03.347048 ==
5174 09:28:03.350500 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 09:28:03.357130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 09:28:03.357219 ==
5177 09:28:03.357288 RX Vref Scan: 0
5178 09:28:03.357351
5179 09:28:03.360744 RX Vref 0 -> 0, step: 1
5180 09:28:03.360864
5181 09:28:03.363583 RX Delay -80 -> 252, step: 8
5182 09:28:03.367161 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5183 09:28:03.370469 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5184 09:28:03.373772 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5185 09:28:03.377619 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5186 09:28:03.383613 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5187 09:28:03.387043 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5188 09:28:03.390232 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5189 09:28:03.393709 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5190 09:28:03.396863 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5191 09:28:03.400112 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5192 09:28:03.407104 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5193 09:28:03.410443 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5194 09:28:03.413375 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5195 09:28:03.417035 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5196 09:28:03.420557 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5197 09:28:03.423430 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5198 09:28:03.426818 ==
5199 09:28:03.430216 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 09:28:03.433823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 09:28:03.433935 ==
5202 09:28:03.434032 DQS Delay:
5203 09:28:03.436699 DQS0 = 0, DQS1 = 0
5204 09:28:03.436806 DQM Delay:
5205 09:28:03.439992 DQM0 = 106, DQM1 = 90
5206 09:28:03.440100 DQ Delay:
5207 09:28:03.443455 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5208 09:28:03.447148 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5209 09:28:03.450077 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5210 09:28:03.453732 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5211 09:28:03.453842
5212 09:28:03.453938
5213 09:28:03.454031 ==
5214 09:28:03.456828 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 09:28:03.460202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 09:28:03.460312 ==
5217 09:28:03.460407
5218 09:28:03.460498
5219 09:28:03.463644 TX Vref Scan disable
5220 09:28:03.467394 == TX Byte 0 ==
5221 09:28:03.470100 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5222 09:28:03.473534 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5223 09:28:03.477218 == TX Byte 1 ==
5224 09:28:03.480296 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5225 09:28:03.483386 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5226 09:28:03.483494 ==
5227 09:28:03.486673 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 09:28:03.493554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 09:28:03.493669 ==
5230 09:28:03.493765
5231 09:28:03.493859
5232 09:28:03.493949 TX Vref Scan disable
5233 09:28:03.497335 == TX Byte 0 ==
5234 09:28:03.500865 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5235 09:28:03.507238 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5236 09:28:03.507350 == TX Byte 1 ==
5237 09:28:03.510616 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5238 09:28:03.518064 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5239 09:28:03.518178
5240 09:28:03.518274 [DATLAT]
5241 09:28:03.518366 Freq=933, CH0 RK0
5242 09:28:03.518457
5243 09:28:03.520685 DATLAT Default: 0xd
5244 09:28:03.520791 0, 0xFFFF, sum = 0
5245 09:28:03.524032 1, 0xFFFF, sum = 0
5246 09:28:03.524141 2, 0xFFFF, sum = 0
5247 09:28:03.527768 3, 0xFFFF, sum = 0
5248 09:28:03.527879 4, 0xFFFF, sum = 0
5249 09:28:03.530915 5, 0xFFFF, sum = 0
5250 09:28:03.531025 6, 0xFFFF, sum = 0
5251 09:28:03.534221 7, 0xFFFF, sum = 0
5252 09:28:03.534333 8, 0xFFFF, sum = 0
5253 09:28:03.537469 9, 0xFFFF, sum = 0
5254 09:28:03.537579 10, 0x0, sum = 1
5255 09:28:03.540883 11, 0x0, sum = 2
5256 09:28:03.540999 12, 0x0, sum = 3
5257 09:28:03.544190 13, 0x0, sum = 4
5258 09:28:03.544299 best_step = 11
5259 09:28:03.544394
5260 09:28:03.544487 ==
5261 09:28:03.547485 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 09:28:03.553770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 09:28:03.553883 ==
5264 09:28:03.553980 RX Vref Scan: 1
5265 09:28:03.554074
5266 09:28:03.557344 RX Vref 0 -> 0, step: 1
5267 09:28:03.557451
5268 09:28:03.560336 RX Delay -53 -> 252, step: 4
5269 09:28:03.560448
5270 09:28:03.563908 Set Vref, RX VrefLevel [Byte0]: 60
5271 09:28:03.567206 [Byte1]: 51
5272 09:28:03.567316
5273 09:28:03.570475 Final RX Vref Byte 0 = 60 to rank0
5274 09:28:03.573838 Final RX Vref Byte 1 = 51 to rank0
5275 09:28:03.577476 Final RX Vref Byte 0 = 60 to rank1
5276 09:28:03.580253 Final RX Vref Byte 1 = 51 to rank1==
5277 09:28:03.583879 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 09:28:03.586725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 09:28:03.590060 ==
5280 09:28:03.590169 DQS Delay:
5281 09:28:03.590266 DQS0 = 0, DQS1 = 0
5282 09:28:03.593660 DQM Delay:
5283 09:28:03.593767 DQM0 = 108, DQM1 = 91
5284 09:28:03.596783 DQ Delay:
5285 09:28:03.600508 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5286 09:28:03.603873 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =116
5287 09:28:03.606849 DQ8 =88, DQ9 =76, DQ10 =90, DQ11 =90
5288 09:28:03.610558 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =100
5289 09:28:03.610670
5290 09:28:03.610766
5291 09:28:03.616836 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5292 09:28:03.620128 CH0 RK0: MR19=505, MR18=2824
5293 09:28:03.626798 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5294 09:28:03.626916
5295 09:28:03.629964 ----->DramcWriteLeveling(PI) begin...
5296 09:28:03.630075 ==
5297 09:28:03.633488 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 09:28:03.636741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 09:28:03.636851 ==
5300 09:28:03.639788 Write leveling (Byte 0): 30 => 30
5301 09:28:03.643402 Write leveling (Byte 1): 29 => 29
5302 09:28:03.646751 DramcWriteLeveling(PI) end<-----
5303 09:28:03.646860
5304 09:28:03.646956 ==
5305 09:28:03.649753 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 09:28:03.653482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 09:28:03.653591 ==
5308 09:28:03.656418 [Gating] SW mode calibration
5309 09:28:03.663130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5310 09:28:03.669909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5311 09:28:03.673151 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 09:28:03.680047 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 09:28:03.683219 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 09:28:03.686847 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 09:28:03.693429 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 09:28:03.696580 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 09:28:03.699979 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5318 09:28:03.706575 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (1 0)
5319 09:28:03.710350 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5320 09:28:03.713198 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 09:28:03.716373 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 09:28:03.723309 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 09:28:03.726604 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 09:28:03.729740 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 09:28:03.736781 0 15 24 | B1->B0 | 2b2a 3030 | 1 0 | (0 0) (1 1)
5326 09:28:03.739951 0 15 28 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
5327 09:28:03.743246 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 09:28:03.749970 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 09:28:03.753825 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 09:28:03.756400 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 09:28:03.763078 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 09:28:03.766291 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 09:28:03.769755 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 09:28:03.776442 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5335 09:28:03.779800 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 09:28:03.782835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 09:28:03.789497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 09:28:03.793262 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 09:28:03.796419 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 09:28:03.803140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 09:28:03.806298 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 09:28:03.809963 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 09:28:03.816238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:28:03.819582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:28:03.823251 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 09:28:03.829740 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 09:28:03.833118 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 09:28:03.836044 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 09:28:03.839828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5350 09:28:03.846159 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5351 09:28:03.849626 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 09:28:03.853128 Total UI for P1: 0, mck2ui 16
5353 09:28:03.856045 best dqsien dly found for B0: ( 1, 2, 26)
5354 09:28:03.859909 Total UI for P1: 0, mck2ui 16
5355 09:28:03.862689 best dqsien dly found for B1: ( 1, 2, 28)
5356 09:28:03.866383 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5357 09:28:03.869518 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5358 09:28:03.869606
5359 09:28:03.873223 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5360 09:28:03.876248 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5361 09:28:03.879616 [Gating] SW calibration Done
5362 09:28:03.879701 ==
5363 09:28:03.883417 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 09:28:03.889581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 09:28:03.889668 ==
5366 09:28:03.889737 RX Vref Scan: 0
5367 09:28:03.889799
5368 09:28:03.892573 RX Vref 0 -> 0, step: 1
5369 09:28:03.892657
5370 09:28:03.896146 RX Delay -80 -> 252, step: 8
5371 09:28:03.899358 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5372 09:28:03.902922 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5373 09:28:03.906018 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5374 09:28:03.909303 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5375 09:28:03.913040 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5376 09:28:03.919769 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5377 09:28:03.922908 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5378 09:28:03.926208 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5379 09:28:03.929624 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5380 09:28:03.932702 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5381 09:28:03.936072 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5382 09:28:03.943168 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5383 09:28:03.946285 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5384 09:28:03.949613 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5385 09:28:03.952919 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5386 09:28:03.956450 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5387 09:28:03.956537 ==
5388 09:28:03.959498 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 09:28:03.966437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 09:28:03.966535 ==
5391 09:28:03.966604 DQS Delay:
5392 09:28:03.969271 DQS0 = 0, DQS1 = 0
5393 09:28:03.969356 DQM Delay:
5394 09:28:03.969424 DQM0 = 104, DQM1 = 91
5395 09:28:03.973134 DQ Delay:
5396 09:28:03.976671 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5397 09:28:03.979738 DQ4 =103, DQ5 =99, DQ6 =115, DQ7 =111
5398 09:28:03.983109 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5399 09:28:03.986152 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5400 09:28:03.986236
5401 09:28:03.986303
5402 09:28:03.986366 ==
5403 09:28:03.989927 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 09:28:03.992733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 09:28:03.992820 ==
5406 09:28:03.992887
5407 09:28:03.992986
5408 09:28:03.996475 TX Vref Scan disable
5409 09:28:03.999829 == TX Byte 0 ==
5410 09:28:04.002942 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5411 09:28:04.006298 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5412 09:28:04.009400 == TX Byte 1 ==
5413 09:28:04.012731 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5414 09:28:04.015795 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5415 09:28:04.015881 ==
5416 09:28:04.019167 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 09:28:04.022766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 09:28:04.025856 ==
5419 09:28:04.025941
5420 09:28:04.026008
5421 09:28:04.026096 TX Vref Scan disable
5422 09:28:04.029386 == TX Byte 0 ==
5423 09:28:04.032585 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5424 09:28:04.039267 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5425 09:28:04.039360 == TX Byte 1 ==
5426 09:28:04.042589 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5427 09:28:04.049352 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5428 09:28:04.049438
5429 09:28:04.049504 [DATLAT]
5430 09:28:04.049564 Freq=933, CH0 RK1
5431 09:28:04.049623
5432 09:28:04.052494 DATLAT Default: 0xb
5433 09:28:04.052577 0, 0xFFFF, sum = 0
5434 09:28:04.055945 1, 0xFFFF, sum = 0
5435 09:28:04.056029 2, 0xFFFF, sum = 0
5436 09:28:04.059071 3, 0xFFFF, sum = 0
5437 09:28:04.062565 4, 0xFFFF, sum = 0
5438 09:28:04.062652 5, 0xFFFF, sum = 0
5439 09:28:04.065652 6, 0xFFFF, sum = 0
5440 09:28:04.065753 7, 0xFFFF, sum = 0
5441 09:28:04.069160 8, 0xFFFF, sum = 0
5442 09:28:04.069246 9, 0xFFFF, sum = 0
5443 09:28:04.072542 10, 0x0, sum = 1
5444 09:28:04.072627 11, 0x0, sum = 2
5445 09:28:04.075775 12, 0x0, sum = 3
5446 09:28:04.075859 13, 0x0, sum = 4
5447 09:28:04.075926 best_step = 11
5448 09:28:04.075987
5449 09:28:04.079047 ==
5450 09:28:04.079130 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 09:28:04.085659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 09:28:04.085745 ==
5453 09:28:04.085811 RX Vref Scan: 0
5454 09:28:04.085872
5455 09:28:04.089155 RX Vref 0 -> 0, step: 1
5456 09:28:04.089237
5457 09:28:04.092366 RX Delay -53 -> 252, step: 4
5458 09:28:04.096039 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5459 09:28:04.102309 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5460 09:28:04.105976 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5461 09:28:04.109110 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5462 09:28:04.112238 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5463 09:28:04.115905 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5464 09:28:04.122601 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5465 09:28:04.125463 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5466 09:28:04.129284 iDelay=203, Bit 8, Center 86 (3 ~ 170) 168
5467 09:28:04.132495 iDelay=203, Bit 9, Center 82 (-1 ~ 166) 168
5468 09:28:04.135579 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5469 09:28:04.139166 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5470 09:28:04.146110 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5471 09:28:04.148868 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5472 09:28:04.152321 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5473 09:28:04.155717 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5474 09:28:04.155803 ==
5475 09:28:04.159898 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 09:28:04.165569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 09:28:04.165660 ==
5478 09:28:04.165726 DQS Delay:
5479 09:28:04.165788 DQS0 = 0, DQS1 = 0
5480 09:28:04.169029 DQM Delay:
5481 09:28:04.169112 DQM0 = 104, DQM1 = 93
5482 09:28:04.172149 DQ Delay:
5483 09:28:04.175571 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5484 09:28:04.178950 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5485 09:28:04.182162 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =92
5486 09:28:04.185216 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5487 09:28:04.185299
5488 09:28:04.185364
5489 09:28:04.192098 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5490 09:28:04.195639 CH0 RK1: MR19=505, MR18=2E0F
5491 09:28:04.202057 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5492 09:28:04.205352 [RxdqsGatingPostProcess] freq 933
5493 09:28:04.212314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5494 09:28:04.212402 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 09:28:04.215582 best DQS1 dly(2T, 0.5T) = (0, 10)
5496 09:28:04.218536 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 09:28:04.221831 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5498 09:28:04.225346 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 09:28:04.228823 best DQS1 dly(2T, 0.5T) = (0, 10)
5500 09:28:04.231869 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 09:28:04.235686 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5502 09:28:04.238745 Pre-setting of DQS Precalculation
5503 09:28:04.241676 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5504 09:28:04.245828 ==
5505 09:28:04.248948 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 09:28:04.252217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 09:28:04.252327 ==
5508 09:28:04.255343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 09:28:04.261688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5510 09:28:04.265584 [CA 0] Center 37 (7~68) winsize 62
5511 09:28:04.268698 [CA 1] Center 37 (7~68) winsize 62
5512 09:28:04.272073 [CA 2] Center 35 (5~66) winsize 62
5513 09:28:04.275800 [CA 3] Center 34 (4~65) winsize 62
5514 09:28:04.278934 [CA 4] Center 35 (4~66) winsize 63
5515 09:28:04.282365 [CA 5] Center 34 (4~64) winsize 61
5516 09:28:04.282450
5517 09:28:04.285552 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5518 09:28:04.285636
5519 09:28:04.288954 [CATrainingPosCal] consider 1 rank data
5520 09:28:04.292296 u2DelayCellTimex100 = 270/100 ps
5521 09:28:04.295827 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5522 09:28:04.299027 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5523 09:28:04.305701 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5524 09:28:04.309143 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5525 09:28:04.312273 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5526 09:28:04.315894 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5527 09:28:04.315978
5528 09:28:04.319109 CA PerBit enable=1, Macro0, CA PI delay=34
5529 09:28:04.319192
5530 09:28:04.322220 [CBTSetCACLKResult] CA Dly = 34
5531 09:28:04.322304 CS Dly: 6 (0~37)
5532 09:28:04.322371 ==
5533 09:28:04.325872 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 09:28:04.332286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 09:28:04.332377 ==
5536 09:28:04.335625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 09:28:04.342291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5538 09:28:04.345387 [CA 0] Center 37 (7~68) winsize 62
5539 09:28:04.348807 [CA 1] Center 38 (7~69) winsize 63
5540 09:28:04.352573 [CA 2] Center 36 (6~66) winsize 61
5541 09:28:04.355863 [CA 3] Center 35 (6~65) winsize 60
5542 09:28:04.358775 [CA 4] Center 35 (5~65) winsize 61
5543 09:28:04.362136 [CA 5] Center 34 (5~64) winsize 60
5544 09:28:04.362223
5545 09:28:04.365768 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5546 09:28:04.365855
5547 09:28:04.369052 [CATrainingPosCal] consider 2 rank data
5548 09:28:04.372211 u2DelayCellTimex100 = 270/100 ps
5549 09:28:04.375346 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5550 09:28:04.381996 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5551 09:28:04.385319 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5552 09:28:04.388838 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5553 09:28:04.392116 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5554 09:28:04.395323 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5555 09:28:04.395414
5556 09:28:04.398764 CA PerBit enable=1, Macro0, CA PI delay=34
5557 09:28:04.398881
5558 09:28:04.402062 [CBTSetCACLKResult] CA Dly = 34
5559 09:28:04.402175 CS Dly: 7 (0~40)
5560 09:28:04.405412
5561 09:28:04.408873 ----->DramcWriteLeveling(PI) begin...
5562 09:28:04.409001 ==
5563 09:28:04.411995 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 09:28:04.415180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 09:28:04.415295 ==
5566 09:28:04.418460 Write leveling (Byte 0): 26 => 26
5567 09:28:04.421904 Write leveling (Byte 1): 30 => 30
5568 09:28:04.425044 DramcWriteLeveling(PI) end<-----
5569 09:28:04.425131
5570 09:28:04.425236 ==
5571 09:28:04.428601 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 09:28:04.431781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 09:28:04.431879 ==
5574 09:28:04.435018 [Gating] SW mode calibration
5575 09:28:04.442161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5576 09:28:04.448529 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5577 09:28:04.451683 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 09:28:04.455112 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 09:28:04.461636 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 09:28:04.465127 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 09:28:04.468538 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 09:28:04.475300 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 09:28:04.478466 0 14 24 | B1->B0 | 3030 3131 | 1 0 | (1 0) (0 1)
5584 09:28:04.481967 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5585 09:28:04.488225 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 09:28:04.491726 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 09:28:04.494846 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 09:28:04.498484 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 09:28:04.504821 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 09:28:04.508168 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 09:28:04.511757 0 15 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5592 09:28:04.518274 0 15 28 | B1->B0 | 4242 4141 | 0 1 | (0 0) (0 0)
5593 09:28:04.521450 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 09:28:04.524988 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 09:28:04.531529 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 09:28:04.534771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 09:28:04.538059 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 09:28:04.544805 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 09:28:04.548380 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5600 09:28:04.551335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5601 09:28:04.558148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 09:28:04.561311 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 09:28:04.564470 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 09:28:04.571058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 09:28:04.574616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 09:28:04.578194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 09:28:04.584659 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:28:04.588102 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:28:04.591191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:28:04.598070 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:28:04.601573 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:28:04.604360 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:28:04.607919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 09:28:04.614613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5615 09:28:04.618301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5616 09:28:04.621407 Total UI for P1: 0, mck2ui 16
5617 09:28:04.624972 best dqsien dly found for B0: ( 1, 2, 20)
5618 09:28:04.627856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 09:28:04.631159 Total UI for P1: 0, mck2ui 16
5620 09:28:04.634734 best dqsien dly found for B1: ( 1, 2, 24)
5621 09:28:04.638176 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5622 09:28:04.641336 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5623 09:28:04.644671
5624 09:28:04.648228 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5625 09:28:04.651067 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5626 09:28:04.654470 [Gating] SW calibration Done
5627 09:28:04.654555 ==
5628 09:28:04.657582 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 09:28:04.661103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 09:28:04.661190 ==
5631 09:28:04.661259 RX Vref Scan: 0
5632 09:28:04.661323
5633 09:28:04.664844 RX Vref 0 -> 0, step: 1
5634 09:28:04.664986
5635 09:28:04.667984 RX Delay -80 -> 252, step: 8
5636 09:28:04.671264 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5637 09:28:04.674682 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5638 09:28:04.680957 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5639 09:28:04.684547 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5640 09:28:04.687563 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5641 09:28:04.691060 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5642 09:28:04.694673 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5643 09:28:04.698177 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5644 09:28:04.700970 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5645 09:28:04.708064 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5646 09:28:04.711206 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5647 09:28:04.714668 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5648 09:28:04.717789 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5649 09:28:04.721206 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5650 09:28:04.727776 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5651 09:28:04.731340 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5652 09:28:04.731427 ==
5653 09:28:04.734640 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 09:28:04.738032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 09:28:04.738118 ==
5656 09:28:04.738185 DQS Delay:
5657 09:28:04.741128 DQS0 = 0, DQS1 = 0
5658 09:28:04.741239 DQM Delay:
5659 09:28:04.744994 DQM0 = 101, DQM1 = 95
5660 09:28:04.745069 DQ Delay:
5661 09:28:04.747871 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5662 09:28:04.751599 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5663 09:28:04.754355 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5664 09:28:04.758217 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5665 09:28:04.758292
5666 09:28:04.758360
5667 09:28:04.758418 ==
5668 09:28:04.761118 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 09:28:04.767700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 09:28:04.767811 ==
5671 09:28:04.767904
5672 09:28:04.767991
5673 09:28:04.768079 TX Vref Scan disable
5674 09:28:04.771480 == TX Byte 0 ==
5675 09:28:04.774642 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5676 09:28:04.777630 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5677 09:28:04.781108 == TX Byte 1 ==
5678 09:28:04.784407 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5679 09:28:04.787913 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5680 09:28:04.791078 ==
5681 09:28:04.794386 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 09:28:04.797813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 09:28:04.797910 ==
5684 09:28:04.797975
5685 09:28:04.798036
5686 09:28:04.801946 TX Vref Scan disable
5687 09:28:04.802023 == TX Byte 0 ==
5688 09:28:04.807629 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 09:28:04.811634 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 09:28:04.811716 == TX Byte 1 ==
5691 09:28:04.817789 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5692 09:28:04.820858 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5693 09:28:04.820971
5694 09:28:04.821038 [DATLAT]
5695 09:28:04.824959 Freq=933, CH1 RK0
5696 09:28:04.825043
5697 09:28:04.825109 DATLAT Default: 0xd
5698 09:28:04.828032 0, 0xFFFF, sum = 0
5699 09:28:04.828116 1, 0xFFFF, sum = 0
5700 09:28:04.831110 2, 0xFFFF, sum = 0
5701 09:28:04.831199 3, 0xFFFF, sum = 0
5702 09:28:05.456705 4, 0xFFFF, sum = 0
5703 09:28:05.457321 5, 0xFFFF, sum = 0
5704 09:28:05.458204 6, 0xFFFF, sum = 0
5705 09:28:05.458747 7, 0xFFFF, sum = 0
5706 09:28:05.459329 8, 0xFFFF, sum = 0
5707 09:28:05.459883 9, 0xFFFF, sum = 0
5708 09:28:05.460494 10, 0x0, sum = 1
5709 09:28:05.461147 11, 0x0, sum = 2
5710 09:28:05.461771 12, 0x0, sum = 3
5711 09:28:05.462211 13, 0x0, sum = 4
5712 09:28:05.462329 best_step = 11
5713 09:28:05.462431
5714 09:28:05.462602 ==
5715 09:28:05.462735 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 09:28:05.462864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 09:28:05.462928 ==
5718 09:28:05.462985 RX Vref Scan: 1
5719 09:28:05.463043
5720 09:28:05.463098 RX Vref 0 -> 0, step: 1
5721 09:28:05.463153
5722 09:28:05.463207 RX Delay -53 -> 252, step: 4
5723 09:28:05.463262
5724 09:28:05.463316 Set Vref, RX VrefLevel [Byte0]: 54
5725 09:28:05.463371 [Byte1]: 52
5726 09:28:05.463425
5727 09:28:05.463480 Final RX Vref Byte 0 = 54 to rank0
5728 09:28:05.463534 Final RX Vref Byte 1 = 52 to rank0
5729 09:28:05.463634 Final RX Vref Byte 0 = 54 to rank1
5730 09:28:05.463741 Final RX Vref Byte 1 = 52 to rank1==
5731 09:28:05.463845 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 09:28:05.463961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 09:28:05.464064 ==
5734 09:28:05.464160 DQS Delay:
5735 09:28:05.464258 DQS0 = 0, DQS1 = 0
5736 09:28:05.464360 DQM Delay:
5737 09:28:05.464473 DQM0 = 104, DQM1 = 97
5738 09:28:05.464609 DQ Delay:
5739 09:28:05.464712 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5740 09:28:05.464814 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5741 09:28:05.464910 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =90
5742 09:28:05.465085 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =104
5743 09:28:05.465208
5744 09:28:05.465324
5745 09:28:05.465392 [DQSOSCAuto] RK0, (LSB)MR18= 0x1831, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5746 09:28:05.465503 CH1 RK0: MR19=505, MR18=1831
5747 09:28:05.465611 CH1_RK0: MR19=0x505, MR18=0x1831, DQSOSC=406, MR23=63, INC=65, DEC=43
5748 09:28:05.465722
5749 09:28:05.465831 ----->DramcWriteLeveling(PI) begin...
5750 09:28:05.465960 ==
5751 09:28:05.466080 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 09:28:05.466190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 09:28:05.466300 ==
5754 09:28:05.466390 Write leveling (Byte 0): 28 => 28
5755 09:28:05.466477 Write leveling (Byte 1): 28 => 28
5756 09:28:05.466592 DramcWriteLeveling(PI) end<-----
5757 09:28:05.466684
5758 09:28:05.466770 ==
5759 09:28:05.466874 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 09:28:05.466965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 09:28:05.467050 ==
5762 09:28:05.467125 [Gating] SW mode calibration
5763 09:28:05.467186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5764 09:28:05.467245 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5765 09:28:05.467305 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 09:28:05.467364 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 09:28:05.467422 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 09:28:05.467479 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 09:28:05.467537 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 09:28:05.467595 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 09:28:05.467659 0 14 24 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 1)
5772 09:28:05.467718 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
5773 09:28:05.467776 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 09:28:05.467835 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 09:28:05.467893 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 09:28:05.467951 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 09:28:05.468009 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 09:28:05.468067 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 09:28:05.468125 0 15 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5780 09:28:05.468217 0 15 28 | B1->B0 | 3f3f 3939 | 0 0 | (0 0) (0 0)
5781 09:28:05.468306 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 09:28:05.468389 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 09:28:05.468461 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 09:28:05.468519 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 09:28:05.468577 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 09:28:05.468634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 09:28:05.468712 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5788 09:28:05.468802 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5789 09:28:05.468891 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 09:28:05.468974 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 09:28:05.469034 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 09:28:05.469092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 09:28:05.469151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 09:28:05.469214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 09:28:05.469272 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 09:28:05.469329 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 09:28:05.469387 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 09:28:05.469445 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:28:05.469503 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:28:05.469561 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:28:05.469619 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 09:28:05.469677 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 09:28:05.469735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5804 09:28:05.469799 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5805 09:28:05.469858 Total UI for P1: 0, mck2ui 16
5806 09:28:05.469916 best dqsien dly found for B1: ( 1, 2, 26)
5807 09:28:05.469975 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 09:28:05.470032 Total UI for P1: 0, mck2ui 16
5809 09:28:05.470090 best dqsien dly found for B0: ( 1, 2, 26)
5810 09:28:05.470148 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5811 09:28:05.470206 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5812 09:28:05.470264
5813 09:28:05.470321 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5814 09:28:05.470407 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5815 09:28:05.470496 [Gating] SW calibration Done
5816 09:28:05.470579 ==
5817 09:28:05.470651 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 09:28:05.470919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 09:28:05.470990 ==
5820 09:28:05.471050 RX Vref Scan: 0
5821 09:28:05.471108
5822 09:28:05.471165 RX Vref 0 -> 0, step: 1
5823 09:28:05.471223
5824 09:28:05.471281 RX Delay -80 -> 252, step: 8
5825 09:28:05.471339 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5826 09:28:05.471397 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5827 09:28:05.471455 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5828 09:28:05.471512 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5829 09:28:05.471573 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5830 09:28:05.471632 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5831 09:28:05.471689 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5832 09:28:05.471747 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5833 09:28:05.471805 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5834 09:28:05.471862 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5835 09:28:05.471919 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5836 09:28:05.471976 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5837 09:28:05.472034 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5838 09:28:05.472091 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5839 09:28:05.472154 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5840 09:28:05.472212 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5841 09:28:05.472271 ==
5842 09:28:05.472329 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 09:28:05.472386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 09:28:05.472443 ==
5845 09:28:05.472501 DQS Delay:
5846 09:28:05.472558 DQS0 = 0, DQS1 = 0
5847 09:28:05.472616 DQM Delay:
5848 09:28:05.472673 DQM0 = 103, DQM1 = 96
5849 09:28:05.472731 DQ Delay:
5850 09:28:05.472788 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5851 09:28:05.472847 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5852 09:28:05.472904 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5853 09:28:05.472994 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5854 09:28:05.473055
5855 09:28:05.473114
5856 09:28:05.473171 ==
5857 09:28:05.473229 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 09:28:05.473287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 09:28:05.473346 ==
5860 09:28:05.473404
5861 09:28:05.473461
5862 09:28:05.473518 TX Vref Scan disable
5863 09:28:05.473576 == TX Byte 0 ==
5864 09:28:05.473634 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5865 09:28:05.473693 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5866 09:28:05.473750 == TX Byte 1 ==
5867 09:28:05.473808 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 09:28:05.473866 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 09:28:05.473924 ==
5870 09:28:05.473981 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 09:28:05.474040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 09:28:05.474098 ==
5873 09:28:05.474156
5874 09:28:05.474213
5875 09:28:05.474271 TX Vref Scan disable
5876 09:28:05.474328 == TX Byte 0 ==
5877 09:28:05.474386 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5878 09:28:05.474444 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5879 09:28:05.474502 == TX Byte 1 ==
5880 09:28:05.474559 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5881 09:28:05.474617 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5882 09:28:05.474675
5883 09:28:05.474732 [DATLAT]
5884 09:28:05.474789 Freq=933, CH1 RK1
5885 09:28:05.474847
5886 09:28:05.474904 DATLAT Default: 0xb
5887 09:28:05.474961 0, 0xFFFF, sum = 0
5888 09:28:05.475021 1, 0xFFFF, sum = 0
5889 09:28:05.475079 2, 0xFFFF, sum = 0
5890 09:28:05.475138 3, 0xFFFF, sum = 0
5891 09:28:05.475196 4, 0xFFFF, sum = 0
5892 09:28:05.475254 5, 0xFFFF, sum = 0
5893 09:28:05.475313 6, 0xFFFF, sum = 0
5894 09:28:05.475371 7, 0xFFFF, sum = 0
5895 09:28:05.475430 8, 0xFFFF, sum = 0
5896 09:28:05.475489 9, 0xFFFF, sum = 0
5897 09:28:05.475547 10, 0x0, sum = 1
5898 09:28:05.475606 11, 0x0, sum = 2
5899 09:28:05.475665 12, 0x0, sum = 3
5900 09:28:05.475723 13, 0x0, sum = 4
5901 09:28:05.475781 best_step = 11
5902 09:28:05.475838
5903 09:28:05.475895 ==
5904 09:28:05.475953 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 09:28:05.476011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 09:28:05.476069 ==
5907 09:28:05.476127 RX Vref Scan: 0
5908 09:28:05.476184
5909 09:28:05.476241 RX Vref 0 -> 0, step: 1
5910 09:28:05.476299
5911 09:28:05.476356 RX Delay -53 -> 252, step: 4
5912 09:28:05.476414 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5913 09:28:05.476472 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5914 09:28:05.476530 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5915 09:28:05.476588 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5916 09:28:05.476646 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5917 09:28:05.476704 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5918 09:28:05.476761 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5919 09:28:05.476819 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5920 09:28:05.476877 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5921 09:28:05.476945 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5922 09:28:05.477007 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5923 09:28:05.477065 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5924 09:28:05.477123 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5925 09:28:05.477181 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5926 09:28:05.477239 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5927 09:28:05.477296 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5928 09:28:05.477353 ==
5929 09:28:05.477411 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 09:28:05.477486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 09:28:05.477547 ==
5932 09:28:05.477606 DQS Delay:
5933 09:28:05.477663 DQS0 = 0, DQS1 = 0
5934 09:28:05.477721 DQM Delay:
5935 09:28:05.478104 DQM0 = 104, DQM1 = 97
5936 09:28:05.478191 DQ Delay:
5937 09:28:05.481382 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5938 09:28:05.485131 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =100
5939 09:28:05.488310 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5940 09:28:05.491425 DQ12 =108, DQ13 =102, DQ14 =104, DQ15 =106
5941 09:28:05.491507
5942 09:28:05.491572
5943 09:28:05.501686 [DQSOSCAuto] RK1, (LSB)MR18= 0x2603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5944 09:28:05.501781 CH1 RK1: MR19=505, MR18=2603
5945 09:28:05.508390 CH1_RK1: MR19=0x505, MR18=0x2603, DQSOSC=409, MR23=63, INC=64, DEC=43
5946 09:28:05.511279 [RxdqsGatingPostProcess] freq 933
5947 09:28:05.518127 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5948 09:28:05.521452 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 09:28:05.524935 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 09:28:05.528230 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 09:28:05.531483 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 09:28:05.534461 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 09:28:05.534544 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 09:28:05.537884 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 09:28:05.541118 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 09:28:05.544695 Pre-setting of DQS Precalculation
5957 09:28:05.551149 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5958 09:28:05.558207 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5959 09:28:05.564551 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5960 09:28:05.564665
5961 09:28:05.564738
5962 09:28:05.568121 [Calibration Summary] 1866 Mbps
5963 09:28:05.571325 CH 0, Rank 0
5964 09:28:05.571409 SW Impedance : PASS
5965 09:28:05.574453 DUTY Scan : NO K
5966 09:28:05.574536 ZQ Calibration : PASS
5967 09:28:05.577813 Jitter Meter : NO K
5968 09:28:05.581257 CBT Training : PASS
5969 09:28:05.581340 Write leveling : PASS
5970 09:28:05.584633 RX DQS gating : PASS
5971 09:28:05.588219 RX DQ/DQS(RDDQC) : PASS
5972 09:28:05.588302 TX DQ/DQS : PASS
5973 09:28:05.590973 RX DATLAT : PASS
5974 09:28:05.594752 RX DQ/DQS(Engine): PASS
5975 09:28:05.594835 TX OE : NO K
5976 09:28:05.598428 All Pass.
5977 09:28:05.598511
5978 09:28:05.598576 CH 0, Rank 1
5979 09:28:05.600850 SW Impedance : PASS
5980 09:28:05.600993 DUTY Scan : NO K
5981 09:28:05.604389 ZQ Calibration : PASS
5982 09:28:05.607683 Jitter Meter : NO K
5983 09:28:05.607765 CBT Training : PASS
5984 09:28:05.611081 Write leveling : PASS
5985 09:28:05.614446 RX DQS gating : PASS
5986 09:28:05.614529 RX DQ/DQS(RDDQC) : PASS
5987 09:28:05.618079 TX DQ/DQS : PASS
5988 09:28:05.618162 RX DATLAT : PASS
5989 09:28:05.620874 RX DQ/DQS(Engine): PASS
5990 09:28:05.624855 TX OE : NO K
5991 09:28:05.624943 All Pass.
5992 09:28:05.625009
5993 09:28:05.625068 CH 1, Rank 0
5994 09:28:05.627697 SW Impedance : PASS
5995 09:28:05.631081 DUTY Scan : NO K
5996 09:28:05.631163 ZQ Calibration : PASS
5997 09:28:05.634269 Jitter Meter : NO K
5998 09:28:05.637752 CBT Training : PASS
5999 09:28:05.637835 Write leveling : PASS
6000 09:28:05.640799 RX DQS gating : PASS
6001 09:28:05.644364 RX DQ/DQS(RDDQC) : PASS
6002 09:28:05.644447 TX DQ/DQS : PASS
6003 09:28:05.647556 RX DATLAT : PASS
6004 09:28:05.651340 RX DQ/DQS(Engine): PASS
6005 09:28:05.651438 TX OE : NO K
6006 09:28:05.654245 All Pass.
6007 09:28:05.654327
6008 09:28:05.654392 CH 1, Rank 1
6009 09:28:05.657796 SW Impedance : PASS
6010 09:28:05.657878 DUTY Scan : NO K
6011 09:28:05.661658 ZQ Calibration : PASS
6012 09:28:05.661740 Jitter Meter : NO K
6013 09:28:05.664670 CBT Training : PASS
6014 09:28:05.667829 Write leveling : PASS
6015 09:28:05.667915 RX DQS gating : PASS
6016 09:28:05.671561 RX DQ/DQS(RDDQC) : PASS
6017 09:28:05.674855 TX DQ/DQS : PASS
6018 09:28:05.675033 RX DATLAT : PASS
6019 09:28:05.677890 RX DQ/DQS(Engine): PASS
6020 09:28:05.681092 TX OE : NO K
6021 09:28:05.681211 All Pass.
6022 09:28:05.681286
6023 09:28:05.684717 DramC Write-DBI off
6024 09:28:05.684817 PER_BANK_REFRESH: Hybrid Mode
6025 09:28:05.687690 TX_TRACKING: ON
6026 09:28:05.694379 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6027 09:28:05.700915 [FAST_K] Save calibration result to emmc
6028 09:28:05.704365 dramc_set_vcore_voltage set vcore to 650000
6029 09:28:05.704478 Read voltage for 400, 6
6030 09:28:05.707874 Vio18 = 0
6031 09:28:05.707981 Vcore = 650000
6032 09:28:05.708048 Vdram = 0
6033 09:28:05.710859 Vddq = 0
6034 09:28:05.710953 Vmddr = 0
6035 09:28:05.714264 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6036 09:28:05.720742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6037 09:28:05.724457 MEM_TYPE=3, freq_sel=20
6038 09:28:05.727472 sv_algorithm_assistance_LP4_800
6039 09:28:05.730612 ============ PULL DRAM RESETB DOWN ============
6040 09:28:05.734255 ========== PULL DRAM RESETB DOWN end =========
6041 09:28:05.737574 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6042 09:28:05.740815 ===================================
6043 09:28:05.744086 LPDDR4 DRAM CONFIGURATION
6044 09:28:05.747337 ===================================
6045 09:28:05.750690 EX_ROW_EN[0] = 0x0
6046 09:28:05.750774 EX_ROW_EN[1] = 0x0
6047 09:28:05.754040 LP4Y_EN = 0x0
6048 09:28:05.754123 WORK_FSP = 0x0
6049 09:28:05.757471 WL = 0x2
6050 09:28:05.757554 RL = 0x2
6051 09:28:05.761015 BL = 0x2
6052 09:28:05.761098 RPST = 0x0
6053 09:28:05.764222 RD_PRE = 0x0
6054 09:28:05.764307 WR_PRE = 0x1
6055 09:28:05.767543 WR_PST = 0x0
6056 09:28:05.770853 DBI_WR = 0x0
6057 09:28:05.770937 DBI_RD = 0x0
6058 09:28:05.774128 OTF = 0x1
6059 09:28:05.777574 ===================================
6060 09:28:05.781139 ===================================
6061 09:28:05.781223 ANA top config
6062 09:28:05.784061 ===================================
6063 09:28:05.787687 DLL_ASYNC_EN = 0
6064 09:28:05.787770 ALL_SLAVE_EN = 1
6065 09:28:05.791005 NEW_RANK_MODE = 1
6066 09:28:05.794395 DLL_IDLE_MODE = 1
6067 09:28:05.797663 LP45_APHY_COMB_EN = 1
6068 09:28:05.800894 TX_ODT_DIS = 1
6069 09:28:05.801045 NEW_8X_MODE = 1
6070 09:28:05.804071 ===================================
6071 09:28:05.807390 ===================================
6072 09:28:05.810497 data_rate = 800
6073 09:28:05.814103 CKR = 1
6074 09:28:05.817599 DQ_P2S_RATIO = 4
6075 09:28:05.820661 ===================================
6076 09:28:05.823992 CA_P2S_RATIO = 4
6077 09:28:05.827193 DQ_CA_OPEN = 0
6078 09:28:05.827276 DQ_SEMI_OPEN = 1
6079 09:28:05.830458 CA_SEMI_OPEN = 1
6080 09:28:05.833683 CA_FULL_RATE = 0
6081 09:28:05.837169 DQ_CKDIV4_EN = 0
6082 09:28:05.840279 CA_CKDIV4_EN = 1
6083 09:28:05.843594 CA_PREDIV_EN = 0
6084 09:28:05.843677 PH8_DLY = 0
6085 09:28:05.847258 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6086 09:28:05.851027 DQ_AAMCK_DIV = 0
6087 09:28:05.853592 CA_AAMCK_DIV = 0
6088 09:28:05.856796 CA_ADMCK_DIV = 4
6089 09:28:05.860511 DQ_TRACK_CA_EN = 0
6090 09:28:05.860593 CA_PICK = 800
6091 09:28:05.863556 CA_MCKIO = 400
6092 09:28:05.866604 MCKIO_SEMI = 400
6093 09:28:05.870042 PLL_FREQ = 3016
6094 09:28:05.873541 DQ_UI_PI_RATIO = 32
6095 09:28:05.876615 CA_UI_PI_RATIO = 32
6096 09:28:05.879963 ===================================
6097 09:28:05.883393 ===================================
6098 09:28:05.886987 memory_type:LPDDR4
6099 09:28:05.887096 GP_NUM : 10
6100 09:28:05.890048 SRAM_EN : 1
6101 09:28:05.890131 MD32_EN : 0
6102 09:28:05.893290 ===================================
6103 09:28:05.896418 [ANA_INIT] >>>>>>>>>>>>>>
6104 09:28:05.899983 <<<<<< [CONFIGURE PHASE]: ANA_TX
6105 09:28:05.903191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6106 09:28:05.906873 ===================================
6107 09:28:05.909848 data_rate = 800,PCW = 0X7400
6108 09:28:05.913485 ===================================
6109 09:28:05.916646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6110 09:28:05.923133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 09:28:05.933294 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6112 09:28:05.936424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6113 09:28:05.939883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6114 09:28:05.943218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6115 09:28:05.946766 [ANA_INIT] flow start
6116 09:28:05.950212 [ANA_INIT] PLL >>>>>>>>
6117 09:28:05.950306 [ANA_INIT] PLL <<<<<<<<
6118 09:28:05.953261 [ANA_INIT] MIDPI >>>>>>>>
6119 09:28:05.956517 [ANA_INIT] MIDPI <<<<<<<<
6120 09:28:05.959874 [ANA_INIT] DLL >>>>>>>>
6121 09:28:05.959998 [ANA_INIT] flow end
6122 09:28:05.963118 ============ LP4 DIFF to SE enter ============
6123 09:28:05.969591 ============ LP4 DIFF to SE exit ============
6124 09:28:05.969755 [ANA_INIT] <<<<<<<<<<<<<
6125 09:28:05.972798 [Flow] Enable top DCM control >>>>>
6126 09:28:05.976120 [Flow] Enable top DCM control <<<<<
6127 09:28:05.979768 Enable DLL master slave shuffle
6128 09:28:05.986715 ==============================================================
6129 09:28:05.986800 Gating Mode config
6130 09:28:05.993141 ==============================================================
6131 09:28:05.996577 Config description:
6132 09:28:06.002859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6133 09:28:06.010266 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6134 09:28:06.016568 SELPH_MODE 0: By rank 1: By Phase
6135 09:28:06.023195 ==============================================================
6136 09:28:06.023278 GAT_TRACK_EN = 0
6137 09:28:06.026875 RX_GATING_MODE = 2
6138 09:28:06.029888 RX_GATING_TRACK_MODE = 2
6139 09:28:06.032992 SELPH_MODE = 1
6140 09:28:06.036212 PICG_EARLY_EN = 1
6141 09:28:06.039848 VALID_LAT_VALUE = 1
6142 09:28:06.046821 ==============================================================
6143 09:28:06.049955 Enter into Gating configuration >>>>
6144 09:28:06.052991 Exit from Gating configuration <<<<
6145 09:28:06.056259 Enter into DVFS_PRE_config >>>>>
6146 09:28:06.066638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6147 09:28:06.069889 Exit from DVFS_PRE_config <<<<<
6148 09:28:06.073332 Enter into PICG configuration >>>>
6149 09:28:06.076787 Exit from PICG configuration <<<<
6150 09:28:06.079437 [RX_INPUT] configuration >>>>>
6151 09:28:06.079520 [RX_INPUT] configuration <<<<<
6152 09:28:06.086218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6153 09:28:06.093177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6154 09:28:06.096628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 09:28:06.102861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 09:28:06.109312 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 09:28:06.116275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 09:28:06.119596 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6159 09:28:06.123064 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6160 09:28:06.130091 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6161 09:28:06.132813 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6162 09:28:06.136512 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6163 09:28:06.142854 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 09:28:06.146137 ===================================
6165 09:28:06.146218 LPDDR4 DRAM CONFIGURATION
6166 09:28:06.149469 ===================================
6167 09:28:06.152819 EX_ROW_EN[0] = 0x0
6168 09:28:06.152899 EX_ROW_EN[1] = 0x0
6169 09:28:06.155988 LP4Y_EN = 0x0
6170 09:28:06.156068 WORK_FSP = 0x0
6171 09:28:06.159108 WL = 0x2
6172 09:28:06.159188 RL = 0x2
6173 09:28:06.162728 BL = 0x2
6174 09:28:06.166040 RPST = 0x0
6175 09:28:06.166136 RD_PRE = 0x0
6176 09:28:06.169936 WR_PRE = 0x1
6177 09:28:06.170016 WR_PST = 0x0
6178 09:28:06.172785 DBI_WR = 0x0
6179 09:28:06.172890 DBI_RD = 0x0
6180 09:28:06.175884 OTF = 0x1
6181 09:28:06.179308 ===================================
6182 09:28:06.182815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6183 09:28:06.185929 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6184 09:28:06.189254 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 09:28:06.192579 ===================================
6186 09:28:06.195908 LPDDR4 DRAM CONFIGURATION
6187 09:28:06.199239 ===================================
6188 09:28:06.202539 EX_ROW_EN[0] = 0x10
6189 09:28:06.202620 EX_ROW_EN[1] = 0x0
6190 09:28:06.205913 LP4Y_EN = 0x0
6191 09:28:06.205993 WORK_FSP = 0x0
6192 09:28:06.209230 WL = 0x2
6193 09:28:06.209311 RL = 0x2
6194 09:28:06.212794 BL = 0x2
6195 09:28:06.212913 RPST = 0x0
6196 09:28:06.215669 RD_PRE = 0x0
6197 09:28:06.215749 WR_PRE = 0x1
6198 09:28:06.219038 WR_PST = 0x0
6199 09:28:06.219119 DBI_WR = 0x0
6200 09:28:06.222456 DBI_RD = 0x0
6201 09:28:06.226085 OTF = 0x1
6202 09:28:06.226166 ===================================
6203 09:28:06.232450 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6204 09:28:06.237416 nWR fixed to 30
6205 09:28:06.240890 [ModeRegInit_LP4] CH0 RK0
6206 09:28:06.241010 [ModeRegInit_LP4] CH0 RK1
6207 09:28:06.244525 [ModeRegInit_LP4] CH1 RK0
6208 09:28:06.247413 [ModeRegInit_LP4] CH1 RK1
6209 09:28:06.247494 match AC timing 19
6210 09:28:06.254153 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6211 09:28:06.257603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6212 09:28:06.260890 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6213 09:28:06.267256 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6214 09:28:06.270943 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6215 09:28:06.271024 ==
6216 09:28:06.273883 Dram Type= 6, Freq= 0, CH_0, rank 0
6217 09:28:06.277489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 09:28:06.277571 ==
6219 09:28:06.283789 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 09:28:06.290624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6221 09:28:06.294082 [CA 0] Center 36 (8~64) winsize 57
6222 09:28:06.297260 [CA 1] Center 36 (8~64) winsize 57
6223 09:28:06.300530 [CA 2] Center 36 (8~64) winsize 57
6224 09:28:06.304238 [CA 3] Center 36 (8~64) winsize 57
6225 09:28:06.304386 [CA 4] Center 36 (8~64) winsize 57
6226 09:28:06.307482 [CA 5] Center 36 (8~64) winsize 57
6227 09:28:06.307563
6228 09:28:06.314153 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6229 09:28:06.314250
6230 09:28:06.316969 [CATrainingPosCal] consider 1 rank data
6231 09:28:06.320869 u2DelayCellTimex100 = 270/100 ps
6232 09:28:06.323911 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 09:28:06.327239 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 09:28:06.330584 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 09:28:06.334124 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 09:28:06.337467 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 09:28:06.340768 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 09:28:06.340849
6239 09:28:06.344168 CA PerBit enable=1, Macro0, CA PI delay=36
6240 09:28:06.344249
6241 09:28:06.347579 [CBTSetCACLKResult] CA Dly = 36
6242 09:28:06.350664 CS Dly: 1 (0~32)
6243 09:28:06.350746 ==
6244 09:28:06.353902 Dram Type= 6, Freq= 0, CH_0, rank 1
6245 09:28:06.357320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 09:28:06.357402 ==
6247 09:28:06.364685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 09:28:06.367167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6249 09:28:06.370624 [CA 0] Center 36 (8~64) winsize 57
6250 09:28:06.373829 [CA 1] Center 36 (8~64) winsize 57
6251 09:28:06.377139 [CA 2] Center 36 (8~64) winsize 57
6252 09:28:06.380780 [CA 3] Center 36 (8~64) winsize 57
6253 09:28:06.383991 [CA 4] Center 36 (8~64) winsize 57
6254 09:28:06.387041 [CA 5] Center 36 (8~64) winsize 57
6255 09:28:06.387122
6256 09:28:06.390273 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6257 09:28:06.390376
6258 09:28:06.393983 [CATrainingPosCal] consider 2 rank data
6259 09:28:06.397261 u2DelayCellTimex100 = 270/100 ps
6260 09:28:06.400701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:28:06.404077 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:28:06.407374 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:28:06.410564 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:28:06.417008 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 09:28:06.420405 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 09:28:06.420559
6267 09:28:06.423880 CA PerBit enable=1, Macro0, CA PI delay=36
6268 09:28:06.423961
6269 09:28:06.427063 [CBTSetCACLKResult] CA Dly = 36
6270 09:28:06.427144 CS Dly: 1 (0~32)
6271 09:28:06.427209
6272 09:28:06.430626 ----->DramcWriteLeveling(PI) begin...
6273 09:28:06.430709 ==
6274 09:28:06.434029 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 09:28:06.440321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 09:28:06.440403 ==
6277 09:28:06.443795 Write leveling (Byte 0): 40 => 8
6278 09:28:06.443877 Write leveling (Byte 1): 32 => 0
6279 09:28:06.447263 DramcWriteLeveling(PI) end<-----
6280 09:28:06.447344
6281 09:28:06.447408 ==
6282 09:28:06.450710 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 09:28:06.457367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 09:28:06.457449 ==
6285 09:28:06.460786 [Gating] SW mode calibration
6286 09:28:06.467117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6287 09:28:06.470378 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6288 09:28:06.477172 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 09:28:06.480773 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6290 09:28:06.484048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 09:28:06.490248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 09:28:06.493609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 09:28:06.497429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 09:28:06.503800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 09:28:06.507330 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 09:28:06.510061 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 09:28:06.513676 Total UI for P1: 0, mck2ui 16
6298 09:28:06.516966 best dqsien dly found for B0: ( 0, 14, 24)
6299 09:28:06.520736 Total UI for P1: 0, mck2ui 16
6300 09:28:06.523489 best dqsien dly found for B1: ( 0, 14, 24)
6301 09:28:06.527131 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6302 09:28:06.530433 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6303 09:28:06.530555
6304 09:28:06.533706 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 09:28:06.540307 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6306 09:28:06.540416 [Gating] SW calibration Done
6307 09:28:06.540509 ==
6308 09:28:06.543237 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 09:28:06.550277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 09:28:06.550366 ==
6311 09:28:06.550430 RX Vref Scan: 0
6312 09:28:06.550489
6313 09:28:06.553289 RX Vref 0 -> 0, step: 1
6314 09:28:06.553368
6315 09:28:06.556769 RX Delay -410 -> 252, step: 16
6316 09:28:06.560103 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6317 09:28:06.563322 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6318 09:28:06.570029 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6319 09:28:06.573250 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6320 09:28:06.576683 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6321 09:28:06.580144 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6322 09:28:06.586660 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6323 09:28:06.590210 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6324 09:28:06.593254 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6325 09:28:06.596831 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6326 09:28:06.603338 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6327 09:28:06.606690 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6328 09:28:06.610115 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6329 09:28:06.613895 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6330 09:28:06.620110 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6331 09:28:06.623086 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6332 09:28:06.623167 ==
6333 09:28:06.626505 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 09:28:06.629690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 09:28:06.629770 ==
6336 09:28:06.633031 DQS Delay:
6337 09:28:06.633111 DQS0 = 27, DQS1 = 43
6338 09:28:06.636480 DQM Delay:
6339 09:28:06.636560 DQM0 = 12, DQM1 = 13
6340 09:28:06.636624 DQ Delay:
6341 09:28:06.639693 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =0
6342 09:28:06.642991 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6343 09:28:06.646642 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6344 09:28:06.649703 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6345 09:28:06.649783
6346 09:28:06.649846
6347 09:28:06.649905 ==
6348 09:28:06.653161 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 09:28:06.659714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 09:28:06.659795 ==
6351 09:28:06.659859
6352 09:28:06.659917
6353 09:28:06.659974 TX Vref Scan disable
6354 09:28:06.663324 == TX Byte 0 ==
6355 09:28:06.666230 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 09:28:06.669537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 09:28:06.672892 == TX Byte 1 ==
6358 09:28:06.676090 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6359 09:28:06.679627 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6360 09:28:06.682603 ==
6361 09:28:06.682684 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 09:28:06.689169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 09:28:06.689250 ==
6364 09:28:06.689314
6365 09:28:06.689372
6366 09:28:06.692677 TX Vref Scan disable
6367 09:28:06.692756 == TX Byte 0 ==
6368 09:28:06.696091 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 09:28:06.702578 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 09:28:06.702658 == TX Byte 1 ==
6371 09:28:06.705951 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6372 09:28:06.712606 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6373 09:28:06.712686
6374 09:28:06.712748 [DATLAT]
6375 09:28:06.712807 Freq=400, CH0 RK0
6376 09:28:06.712863
6377 09:28:06.715959 DATLAT Default: 0xf
6378 09:28:06.716038 0, 0xFFFF, sum = 0
6379 09:28:06.719178 1, 0xFFFF, sum = 0
6380 09:28:06.719259 2, 0xFFFF, sum = 0
6381 09:28:06.722513 3, 0xFFFF, sum = 0
6382 09:28:06.726191 4, 0xFFFF, sum = 0
6383 09:28:06.726273 5, 0xFFFF, sum = 0
6384 09:28:06.729491 6, 0xFFFF, sum = 0
6385 09:28:06.729571 7, 0xFFFF, sum = 0
6386 09:28:06.732645 8, 0xFFFF, sum = 0
6387 09:28:06.732725 9, 0xFFFF, sum = 0
6388 09:28:06.736090 10, 0xFFFF, sum = 0
6389 09:28:06.736171 11, 0xFFFF, sum = 0
6390 09:28:06.739199 12, 0xFFFF, sum = 0
6391 09:28:06.739279 13, 0x0, sum = 1
6392 09:28:06.742690 14, 0x0, sum = 2
6393 09:28:06.742775 15, 0x0, sum = 3
6394 09:28:06.745772 16, 0x0, sum = 4
6395 09:28:06.745857 best_step = 14
6396 09:28:06.745940
6397 09:28:06.746018 ==
6398 09:28:06.749285 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 09:28:06.752401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 09:28:06.752484 ==
6401 09:28:06.755917 RX Vref Scan: 1
6402 09:28:06.756001
6403 09:28:06.759418 RX Vref 0 -> 0, step: 1
6404 09:28:06.759502
6405 09:28:06.759585 RX Delay -327 -> 252, step: 8
6406 09:28:06.762394
6407 09:28:06.762477 Set Vref, RX VrefLevel [Byte0]: 60
6408 09:28:06.765817 [Byte1]: 51
6409 09:28:06.771235
6410 09:28:06.771319 Final RX Vref Byte 0 = 60 to rank0
6411 09:28:06.774922 Final RX Vref Byte 1 = 51 to rank0
6412 09:28:06.778021 Final RX Vref Byte 0 = 60 to rank1
6413 09:28:06.781174 Final RX Vref Byte 1 = 51 to rank1==
6414 09:28:06.784676 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 09:28:06.791286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 09:28:06.791371 ==
6417 09:28:06.791456 DQS Delay:
6418 09:28:06.794686 DQS0 = 28, DQS1 = 48
6419 09:28:06.794770 DQM Delay:
6420 09:28:06.794853 DQM0 = 12, DQM1 = 15
6421 09:28:06.797978 DQ Delay:
6422 09:28:06.801461 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6423 09:28:06.804545 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6424 09:28:06.804629 DQ8 =12, DQ9 =0, DQ10 =12, DQ11 =8
6425 09:28:06.807695 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6426 09:28:06.810950
6427 09:28:06.811062
6428 09:28:06.817845 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6429 09:28:06.821315 CH0 RK0: MR19=C0C, MR18=B0A8
6430 09:28:06.828460 CH0_RK0: MR19=0xC0C, MR18=0xB0A8, DQSOSC=387, MR23=63, INC=394, DEC=262
6431 09:28:06.828546 ==
6432 09:28:06.831022 Dram Type= 6, Freq= 0, CH_0, rank 1
6433 09:28:06.834613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 09:28:06.834698 ==
6435 09:28:06.837591 [Gating] SW mode calibration
6436 09:28:06.844326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6437 09:28:06.850925 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6438 09:28:06.854265 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 09:28:06.857443 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 09:28:06.864284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 09:28:06.867772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 09:28:06.871041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 09:28:06.877887 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 09:28:06.881069 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 09:28:06.884359 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 09:28:06.890967 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 09:28:06.891051 Total UI for P1: 0, mck2ui 16
6448 09:28:06.894651 best dqsien dly found for B0: ( 0, 14, 24)
6449 09:28:06.897815 Total UI for P1: 0, mck2ui 16
6450 09:28:06.900840 best dqsien dly found for B1: ( 0, 14, 24)
6451 09:28:06.903957 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6452 09:28:06.910906 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6453 09:28:06.911030
6454 09:28:06.914152 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 09:28:06.917505 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6456 09:28:06.920878 [Gating] SW calibration Done
6457 09:28:06.921038 ==
6458 09:28:06.924080 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 09:28:06.927500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 09:28:06.927583 ==
6461 09:28:06.930997 RX Vref Scan: 0
6462 09:28:06.931092
6463 09:28:06.931157 RX Vref 0 -> 0, step: 1
6464 09:28:06.931219
6465 09:28:06.934522 RX Delay -410 -> 252, step: 16
6466 09:28:06.937444 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6467 09:28:06.944382 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6468 09:28:06.947350 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6469 09:28:06.950735 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6470 09:28:06.953941 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6471 09:28:06.960623 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6472 09:28:06.963740 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6473 09:28:06.967194 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6474 09:28:06.970619 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6475 09:28:06.977253 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6476 09:28:06.980685 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6477 09:28:06.983970 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6478 09:28:06.987240 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6479 09:28:06.993711 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6480 09:28:06.997217 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6481 09:28:07.000604 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6482 09:28:07.000688 ==
6483 09:28:07.004324 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 09:28:07.010549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 09:28:07.010636 ==
6486 09:28:07.010702 DQS Delay:
6487 09:28:07.014049 DQS0 = 27, DQS1 = 43
6488 09:28:07.014132 DQM Delay:
6489 09:28:07.014198 DQM0 = 9, DQM1 = 14
6490 09:28:07.017234 DQ Delay:
6491 09:28:07.020535 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6492 09:28:07.020618 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6493 09:28:07.023668 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6494 09:28:07.026983 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6495 09:28:07.027067
6496 09:28:07.030301
6497 09:28:07.030383 ==
6498 09:28:07.033749 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 09:28:07.037341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 09:28:07.037425 ==
6501 09:28:07.037491
6502 09:28:07.037551
6503 09:28:07.040488 TX Vref Scan disable
6504 09:28:07.040571 == TX Byte 0 ==
6505 09:28:07.043924 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 09:28:07.050351 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 09:28:07.050434 == TX Byte 1 ==
6508 09:28:07.053788 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6509 09:28:07.060157 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6510 09:28:07.060241 ==
6511 09:28:07.063828 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 09:28:07.066702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 09:28:07.066786 ==
6514 09:28:07.066851
6515 09:28:07.066911
6516 09:28:07.069996 TX Vref Scan disable
6517 09:28:07.070078 == TX Byte 0 ==
6518 09:28:07.073475 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 09:28:07.080168 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 09:28:07.080251 == TX Byte 1 ==
6521 09:28:07.083505 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6522 09:28:07.090062 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6523 09:28:07.090149
6524 09:28:07.090215 [DATLAT]
6525 09:28:07.090275 Freq=400, CH0 RK1
6526 09:28:07.090334
6527 09:28:07.093268 DATLAT Default: 0xe
6528 09:28:07.097510 0, 0xFFFF, sum = 0
6529 09:28:07.097593 1, 0xFFFF, sum = 0
6530 09:28:07.100006 2, 0xFFFF, sum = 0
6531 09:28:07.100088 3, 0xFFFF, sum = 0
6532 09:28:07.103131 4, 0xFFFF, sum = 0
6533 09:28:07.103213 5, 0xFFFF, sum = 0
6534 09:28:07.106411 6, 0xFFFF, sum = 0
6535 09:28:07.106493 7, 0xFFFF, sum = 0
6536 09:28:07.110109 8, 0xFFFF, sum = 0
6537 09:28:07.110190 9, 0xFFFF, sum = 0
6538 09:28:07.113151 10, 0xFFFF, sum = 0
6539 09:28:07.113234 11, 0xFFFF, sum = 0
6540 09:28:07.116730 12, 0xFFFF, sum = 0
6541 09:28:07.116811 13, 0x0, sum = 1
6542 09:28:07.119831 14, 0x0, sum = 2
6543 09:28:07.119913 15, 0x0, sum = 3
6544 09:28:07.123222 16, 0x0, sum = 4
6545 09:28:07.123304 best_step = 14
6546 09:28:07.123368
6547 09:28:07.123428 ==
6548 09:28:07.126377 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 09:28:07.129871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 09:28:07.132940 ==
6551 09:28:07.133042 RX Vref Scan: 0
6552 09:28:07.133110
6553 09:28:07.136536 RX Vref 0 -> 0, step: 1
6554 09:28:07.136617
6555 09:28:07.140107 RX Delay -327 -> 252, step: 8
6556 09:28:07.146711 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6557 09:28:07.149901 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6558 09:28:07.152872 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6559 09:28:07.156281 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6560 09:28:07.163009 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6561 09:28:07.166179 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6562 09:28:07.169624 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6563 09:28:07.172759 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6564 09:28:07.176589 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6565 09:28:07.182736 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6566 09:28:07.186320 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6567 09:28:07.189820 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6568 09:28:07.196274 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6569 09:28:07.199724 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6570 09:28:07.202805 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6571 09:28:07.206235 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6572 09:28:07.206319 ==
6573 09:28:07.209707 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 09:28:07.216374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 09:28:07.216463 ==
6576 09:28:07.216528 DQS Delay:
6577 09:28:07.219503 DQS0 = 28, DQS1 = 44
6578 09:28:07.219588 DQM Delay:
6579 09:28:07.219687 DQM0 = 10, DQM1 = 16
6580 09:28:07.222646 DQ Delay:
6581 09:28:07.226195 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6582 09:28:07.229506 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6583 09:28:07.229594 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6584 09:28:07.236503 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6585 09:28:07.236593
6586 09:28:07.236660
6587 09:28:07.243126 [DQSOSCAuto] RK1, (LSB)MR18= 0xba6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6588 09:28:07.245935 CH0 RK1: MR19=C0C, MR18=BA6D
6589 09:28:07.252887 CH0_RK1: MR19=0xC0C, MR18=0xBA6D, DQSOSC=386, MR23=63, INC=396, DEC=264
6590 09:28:07.256252 [RxdqsGatingPostProcess] freq 400
6591 09:28:07.259359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6592 09:28:07.262966 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 09:28:07.265957 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 09:28:07.269460 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 09:28:07.272651 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 09:28:07.276008 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 09:28:07.279291 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 09:28:07.282555 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 09:28:07.285894 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 09:28:07.289537 Pre-setting of DQS Precalculation
6601 09:28:07.292682 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6602 09:28:07.292767 ==
6603 09:28:07.296055 Dram Type= 6, Freq= 0, CH_1, rank 0
6604 09:28:07.302513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 09:28:07.302598 ==
6606 09:28:07.305843 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 09:28:07.312741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6608 09:28:07.315919 [CA 0] Center 36 (8~64) winsize 57
6609 09:28:07.319187 [CA 1] Center 36 (8~64) winsize 57
6610 09:28:07.322764 [CA 2] Center 36 (8~64) winsize 57
6611 09:28:07.325786 [CA 3] Center 36 (8~64) winsize 57
6612 09:28:07.329134 [CA 4] Center 36 (8~64) winsize 57
6613 09:28:07.332806 [CA 5] Center 36 (8~64) winsize 57
6614 09:28:07.332890
6615 09:28:07.336297 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6616 09:28:07.336381
6617 09:28:07.339757 [CATrainingPosCal] consider 1 rank data
6618 09:28:07.342448 u2DelayCellTimex100 = 270/100 ps
6619 09:28:07.345905 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 09:28:07.349052 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 09:28:07.352275 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 09:28:07.355774 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 09:28:07.358911 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 09:28:07.362104 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 09:28:07.362209
6626 09:28:07.368844 CA PerBit enable=1, Macro0, CA PI delay=36
6627 09:28:07.369007
6628 09:28:07.372590 [CBTSetCACLKResult] CA Dly = 36
6629 09:28:07.372684 CS Dly: 1 (0~32)
6630 09:28:07.372753 ==
6631 09:28:07.376227 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 09:28:07.379099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 09:28:07.379186 ==
6634 09:28:07.385502 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 09:28:07.392226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6636 09:28:07.395782 [CA 0] Center 36 (8~64) winsize 57
6637 09:28:07.399112 [CA 1] Center 36 (8~64) winsize 57
6638 09:28:07.402349 [CA 2] Center 36 (8~64) winsize 57
6639 09:28:07.402451 [CA 3] Center 36 (8~64) winsize 57
6640 09:28:07.405663 [CA 4] Center 36 (8~64) winsize 57
6641 09:28:07.409205 [CA 5] Center 36 (8~64) winsize 57
6642 09:28:07.409292
6643 09:28:07.415493 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6644 09:28:07.415575
6645 09:28:07.418878 [CATrainingPosCal] consider 2 rank data
6646 09:28:07.422172 u2DelayCellTimex100 = 270/100 ps
6647 09:28:07.425649 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:28:07.428871 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:28:07.432461 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:28:07.435680 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:28:07.439126 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 09:28:07.442481 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 09:28:07.442566
6654 09:28:07.445602 CA PerBit enable=1, Macro0, CA PI delay=36
6655 09:28:07.445685
6656 09:28:07.449259 [CBTSetCACLKResult] CA Dly = 36
6657 09:28:07.452361 CS Dly: 1 (0~32)
6658 09:28:07.452443
6659 09:28:07.455833 ----->DramcWriteLeveling(PI) begin...
6660 09:28:07.455931 ==
6661 09:28:07.458903 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 09:28:07.462094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 09:28:07.462180 ==
6664 09:28:07.465710 Write leveling (Byte 0): 40 => 8
6665 09:28:07.468774 Write leveling (Byte 1): 32 => 0
6666 09:28:07.472440 DramcWriteLeveling(PI) end<-----
6667 09:28:07.472544
6668 09:28:07.472614 ==
6669 09:28:07.475370 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 09:28:07.478778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 09:28:07.478870 ==
6672 09:28:07.482386 [Gating] SW mode calibration
6673 09:28:07.488794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6674 09:28:07.495747 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6675 09:28:07.498978 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 09:28:07.502391 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6677 09:28:07.509149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 09:28:07.512307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 09:28:07.515510 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 09:28:07.522361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 09:28:07.525408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 09:28:07.528872 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 09:28:07.535348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 09:28:07.535465 Total UI for P1: 0, mck2ui 16
6685 09:28:07.538730 best dqsien dly found for B0: ( 0, 14, 24)
6686 09:28:07.541944 Total UI for P1: 0, mck2ui 16
6687 09:28:07.545744 best dqsien dly found for B1: ( 0, 14, 24)
6688 09:28:07.552155 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6689 09:28:07.555243 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6690 09:28:07.555341
6691 09:28:07.558477 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 09:28:07.562206 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 09:28:07.565246 [Gating] SW calibration Done
6694 09:28:07.565328 ==
6695 09:28:07.568312 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 09:28:07.571811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 09:28:07.571896 ==
6698 09:28:07.575542 RX Vref Scan: 0
6699 09:28:07.575626
6700 09:28:07.575691 RX Vref 0 -> 0, step: 1
6701 09:28:07.575751
6702 09:28:07.578682 RX Delay -410 -> 252, step: 16
6703 09:28:07.585567 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6704 09:28:07.588331 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6705 09:28:07.591482 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6706 09:28:07.594946 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6707 09:28:07.601560 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6708 09:28:07.605197 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6709 09:28:07.608255 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6710 09:28:07.611686 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6711 09:28:07.618187 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6712 09:28:07.621183 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6713 09:28:07.624592 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6714 09:28:07.628112 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6715 09:28:07.634695 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6716 09:28:07.637966 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6717 09:28:07.641361 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6718 09:28:07.644542 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6719 09:28:07.647535 ==
6720 09:28:07.651249 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 09:28:07.654713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 09:28:07.654803 ==
6723 09:28:07.654870 DQS Delay:
6724 09:28:07.657884 DQS0 = 27, DQS1 = 43
6725 09:28:07.657968 DQM Delay:
6726 09:28:07.661201 DQM0 = 5, DQM1 = 15
6727 09:28:07.661285 DQ Delay:
6728 09:28:07.664482 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6729 09:28:07.667633 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6730 09:28:07.671127 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6731 09:28:07.674388 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6732 09:28:07.674484
6733 09:28:07.674551
6734 09:28:07.674610 ==
6735 09:28:07.677902 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 09:28:07.681549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 09:28:07.681644 ==
6738 09:28:07.681714
6739 09:28:07.681774
6740 09:28:07.684892 TX Vref Scan disable
6741 09:28:07.685027 == TX Byte 0 ==
6742 09:28:07.691332 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 09:28:07.694434 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 09:28:07.694549 == TX Byte 1 ==
6745 09:28:07.698016 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6746 09:28:07.704606 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6747 09:28:07.704703 ==
6748 09:28:07.707558 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 09:28:07.710932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 09:28:07.711021 ==
6751 09:28:07.711087
6752 09:28:07.711148
6753 09:28:07.714282 TX Vref Scan disable
6754 09:28:07.714405 == TX Byte 0 ==
6755 09:28:07.721189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 09:28:07.724756 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 09:28:07.724843 == TX Byte 1 ==
6758 09:28:07.731339 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6759 09:28:07.734555 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6760 09:28:07.734645
6761 09:28:07.734712 [DATLAT]
6762 09:28:07.737885 Freq=400, CH1 RK0
6763 09:28:07.737973
6764 09:28:07.738040 DATLAT Default: 0xf
6765 09:28:07.740911 0, 0xFFFF, sum = 0
6766 09:28:07.741073 1, 0xFFFF, sum = 0
6767 09:28:07.744288 2, 0xFFFF, sum = 0
6768 09:28:07.744378 3, 0xFFFF, sum = 0
6769 09:28:07.747838 4, 0xFFFF, sum = 0
6770 09:28:07.747928 5, 0xFFFF, sum = 0
6771 09:28:07.751132 6, 0xFFFF, sum = 0
6772 09:28:07.751223 7, 0xFFFF, sum = 0
6773 09:28:07.754151 8, 0xFFFF, sum = 0
6774 09:28:07.757893 9, 0xFFFF, sum = 0
6775 09:28:07.757990 10, 0xFFFF, sum = 0
6776 09:28:07.760823 11, 0xFFFF, sum = 0
6777 09:28:07.760911 12, 0xFFFF, sum = 0
6778 09:28:07.764260 13, 0x0, sum = 1
6779 09:28:07.764366 14, 0x0, sum = 2
6780 09:28:07.767758 15, 0x0, sum = 3
6781 09:28:07.767849 16, 0x0, sum = 4
6782 09:28:07.767917 best_step = 14
6783 09:28:07.767978
6784 09:28:07.771026 ==
6785 09:28:07.771116 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 09:28:07.777653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 09:28:07.777762 ==
6788 09:28:07.777830 RX Vref Scan: 1
6789 09:28:07.777892
6790 09:28:07.781066 RX Vref 0 -> 0, step: 1
6791 09:28:07.781153
6792 09:28:07.784388 RX Delay -327 -> 252, step: 8
6793 09:28:07.784475
6794 09:28:07.787431 Set Vref, RX VrefLevel [Byte0]: 54
6795 09:28:07.790915 [Byte1]: 52
6796 09:28:07.794344
6797 09:28:07.794462 Final RX Vref Byte 0 = 54 to rank0
6798 09:28:07.797749 Final RX Vref Byte 1 = 52 to rank0
6799 09:28:07.801050 Final RX Vref Byte 0 = 54 to rank1
6800 09:28:07.804633 Final RX Vref Byte 1 = 52 to rank1==
6801 09:28:07.807800 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 09:28:07.814389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 09:28:07.814485 ==
6804 09:28:07.814554 DQS Delay:
6805 09:28:07.814617 DQS0 = 28, DQS1 = 40
6806 09:28:07.817856 DQM Delay:
6807 09:28:07.817940 DQM0 = 8, DQM1 = 12
6808 09:28:07.820896 DQ Delay:
6809 09:28:07.821017 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6810 09:28:07.824376 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6811 09:28:07.827722 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6812 09:28:07.831092 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6813 09:28:07.831176
6814 09:28:07.831242
6815 09:28:07.840770 [DQSOSCAuto] RK0, (LSB)MR18= 0x9cd7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6816 09:28:07.844200 CH1 RK0: MR19=C0C, MR18=9CD7
6817 09:28:07.851353 CH1_RK0: MR19=0xC0C, MR18=0x9CD7, DQSOSC=383, MR23=63, INC=402, DEC=268
6818 09:28:07.851485 ==
6819 09:28:07.854360 Dram Type= 6, Freq= 0, CH_1, rank 1
6820 09:28:07.857353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 09:28:07.857450 ==
6822 09:28:07.861336 [Gating] SW mode calibration
6823 09:28:07.867638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6824 09:28:07.871641 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6825 09:28:07.877828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6826 09:28:07.880988 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6827 09:28:07.884344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 09:28:07.891198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 09:28:07.894388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 09:28:07.897554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 09:28:07.904129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 09:28:07.907511 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 09:28:07.911272 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 09:28:07.914455 Total UI for P1: 0, mck2ui 16
6835 09:28:07.917778 best dqsien dly found for B0: ( 0, 14, 24)
6836 09:28:07.920823 Total UI for P1: 0, mck2ui 16
6837 09:28:07.924212 best dqsien dly found for B1: ( 0, 14, 24)
6838 09:28:07.927497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6839 09:28:07.931066 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6840 09:28:07.931153
6841 09:28:07.934468 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 09:28:07.940778 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6843 09:28:07.940868 [Gating] SW calibration Done
6844 09:28:07.944067 ==
6845 09:28:07.944158 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 09:28:07.950741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 09:28:07.950835 ==
6848 09:28:07.950904 RX Vref Scan: 0
6849 09:28:07.950966
6850 09:28:07.954037 RX Vref 0 -> 0, step: 1
6851 09:28:07.954121
6852 09:28:07.957690 RX Delay -410 -> 252, step: 16
6853 09:28:07.960891 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6854 09:28:07.963995 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6855 09:28:07.970694 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6856 09:28:07.974163 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6857 09:28:07.977612 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6858 09:28:07.981033 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6859 09:28:07.987472 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6860 09:28:07.991119 iDelay=230, Bit 7, Center -11 (-234 ~ 213) 448
6861 09:28:07.994523 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6862 09:28:07.997358 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6863 09:28:08.003851 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6864 09:28:08.007228 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6865 09:28:08.010666 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6866 09:28:08.013867 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6867 09:28:08.020777 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6868 09:28:08.023930 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6869 09:28:08.024014 ==
6870 09:28:08.027317 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 09:28:08.031004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 09:28:08.031089 ==
6873 09:28:08.034027 DQS Delay:
6874 09:28:08.034111 DQS0 = 35, DQS1 = 43
6875 09:28:08.037437 DQM Delay:
6876 09:28:08.037524 DQM0 = 21, DQM1 = 20
6877 09:28:08.037591 DQ Delay:
6878 09:28:08.040516 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =24
6879 09:28:08.043904 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =24
6880 09:28:08.047075 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6881 09:28:08.050891 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =32
6882 09:28:08.050974
6883 09:28:08.051041
6884 09:28:08.051101 ==
6885 09:28:08.054178 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 09:28:08.060644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 09:28:08.060729 ==
6888 09:28:08.060796
6889 09:28:08.060857
6890 09:28:08.060915 TX Vref Scan disable
6891 09:28:08.064072 == TX Byte 0 ==
6892 09:28:08.067241 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 09:28:08.070839 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 09:28:08.074210 == TX Byte 1 ==
6895 09:28:08.077795 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6896 09:28:08.081059 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6897 09:28:08.081141 ==
6898 09:28:08.083995 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 09:28:08.090801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 09:28:08.090933 ==
6901 09:28:08.091011
6902 09:28:08.091070
6903 09:28:08.091128 TX Vref Scan disable
6904 09:28:08.094148 == TX Byte 0 ==
6905 09:28:08.097246 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 09:28:08.100430 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 09:28:08.103784 == TX Byte 1 ==
6908 09:28:08.107244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6909 09:28:08.110474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6910 09:28:08.110555
6911 09:28:08.114132 [DATLAT]
6912 09:28:08.114213 Freq=400, CH1 RK1
6913 09:28:08.114277
6914 09:28:08.117325 DATLAT Default: 0xe
6915 09:28:08.117406 0, 0xFFFF, sum = 0
6916 09:28:08.120482 1, 0xFFFF, sum = 0
6917 09:28:08.120564 2, 0xFFFF, sum = 0
6918 09:28:08.124028 3, 0xFFFF, sum = 0
6919 09:28:08.124110 4, 0xFFFF, sum = 0
6920 09:28:08.127570 5, 0xFFFF, sum = 0
6921 09:28:08.127652 6, 0xFFFF, sum = 0
6922 09:28:08.131124 7, 0xFFFF, sum = 0
6923 09:28:08.131206 8, 0xFFFF, sum = 0
6924 09:28:08.133688 9, 0xFFFF, sum = 0
6925 09:28:08.133769 10, 0xFFFF, sum = 0
6926 09:28:08.137459 11, 0xFFFF, sum = 0
6927 09:28:08.140659 12, 0xFFFF, sum = 0
6928 09:28:08.140743 13, 0x0, sum = 1
6929 09:28:08.140824 14, 0x0, sum = 2
6930 09:28:08.143906 15, 0x0, sum = 3
6931 09:28:08.143989 16, 0x0, sum = 4
6932 09:28:08.147229 best_step = 14
6933 09:28:08.147311
6934 09:28:08.147375 ==
6935 09:28:08.150502 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 09:28:08.153661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 09:28:08.153745 ==
6938 09:28:08.157300 RX Vref Scan: 0
6939 09:28:08.157387
6940 09:28:08.157472 RX Vref 0 -> 0, step: 1
6941 09:28:08.157551
6942 09:28:08.160428 RX Delay -327 -> 252, step: 8
6943 09:28:08.168509 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6944 09:28:08.172083 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6945 09:28:08.175185 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6946 09:28:08.178385 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6947 09:28:08.185213 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6948 09:28:08.188558 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6949 09:28:08.191729 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6950 09:28:08.195122 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6951 09:28:08.201715 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6952 09:28:08.204918 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6953 09:28:08.208524 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6954 09:28:08.211935 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6955 09:28:08.218415 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6956 09:28:08.221555 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6957 09:28:08.224974 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6958 09:28:08.231561 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6959 09:28:08.231642 ==
6960 09:28:08.234751 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 09:28:08.238371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 09:28:08.238455 ==
6963 09:28:08.238521 DQS Delay:
6964 09:28:08.241883 DQS0 = 32, DQS1 = 36
6965 09:28:08.241966 DQM Delay:
6966 09:28:08.244785 DQM0 = 13, DQM1 = 11
6967 09:28:08.244867 DQ Delay:
6968 09:28:08.248110 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6969 09:28:08.251581 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6970 09:28:08.254964 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6971 09:28:08.258123 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6972 09:28:08.258210
6973 09:28:08.258276
6974 09:28:08.265401 [DQSOSCAuto] RK1, (LSB)MR18= 0xb35a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6975 09:28:08.268344 CH1 RK1: MR19=C0C, MR18=B35A
6976 09:28:08.275046 CH1_RK1: MR19=0xC0C, MR18=0xB35A, DQSOSC=387, MR23=63, INC=394, DEC=262
6977 09:28:08.278304 [RxdqsGatingPostProcess] freq 400
6978 09:28:08.284596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6979 09:28:08.284699 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 09:28:08.288377 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 09:28:08.291401 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 09:28:08.295189 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 09:28:08.298483 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 09:28:08.301491 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 09:28:08.304897 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 09:28:08.308060 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 09:28:08.311491 Pre-setting of DQS Precalculation
6988 09:28:08.317828 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6989 09:28:08.324767 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6990 09:28:08.331155 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6991 09:28:08.331239
6992 09:28:08.331303
6993 09:28:08.334523 [Calibration Summary] 800 Mbps
6994 09:28:08.334605 CH 0, Rank 0
6995 09:28:08.338202 SW Impedance : PASS
6996 09:28:08.341228 DUTY Scan : NO K
6997 09:28:08.341310 ZQ Calibration : PASS
6998 09:28:08.344282 Jitter Meter : NO K
6999 09:28:08.344363 CBT Training : PASS
7000 09:28:08.347716 Write leveling : PASS
7001 09:28:08.350925 RX DQS gating : PASS
7002 09:28:08.351007 RX DQ/DQS(RDDQC) : PASS
7003 09:28:08.354419 TX DQ/DQS : PASS
7004 09:28:08.357742 RX DATLAT : PASS
7005 09:28:08.357823 RX DQ/DQS(Engine): PASS
7006 09:28:08.361159 TX OE : NO K
7007 09:28:08.361240 All Pass.
7008 09:28:08.361306
7009 09:28:08.364242 CH 0, Rank 1
7010 09:28:08.364322 SW Impedance : PASS
7011 09:28:08.367810 DUTY Scan : NO K
7012 09:28:08.371050 ZQ Calibration : PASS
7013 09:28:08.371131 Jitter Meter : NO K
7014 09:28:08.374176 CBT Training : PASS
7015 09:28:08.377573 Write leveling : NO K
7016 09:28:08.377655 RX DQS gating : PASS
7017 09:28:08.381068 RX DQ/DQS(RDDQC) : PASS
7018 09:28:08.384573 TX DQ/DQS : PASS
7019 09:28:08.384679 RX DATLAT : PASS
7020 09:28:08.387907 RX DQ/DQS(Engine): PASS
7021 09:28:08.387988 TX OE : NO K
7022 09:28:08.390999 All Pass.
7023 09:28:08.391083
7024 09:28:08.391157 CH 1, Rank 0
7025 09:28:08.394339 SW Impedance : PASS
7026 09:28:08.394448 DUTY Scan : NO K
7027 09:28:08.397549 ZQ Calibration : PASS
7028 09:28:08.400976 Jitter Meter : NO K
7029 09:28:08.401072 CBT Training : PASS
7030 09:28:08.404163 Write leveling : PASS
7031 09:28:08.407497 RX DQS gating : PASS
7032 09:28:08.407580 RX DQ/DQS(RDDQC) : PASS
7033 09:28:08.410982 TX DQ/DQS : PASS
7034 09:28:08.414219 RX DATLAT : PASS
7035 09:28:08.414302 RX DQ/DQS(Engine): PASS
7036 09:28:08.417662 TX OE : NO K
7037 09:28:08.417745 All Pass.
7038 09:28:08.417810
7039 09:28:08.420887 CH 1, Rank 1
7040 09:28:08.420977 SW Impedance : PASS
7041 09:28:08.424196 DUTY Scan : NO K
7042 09:28:08.427566 ZQ Calibration : PASS
7043 09:28:08.427650 Jitter Meter : NO K
7044 09:28:08.431196 CBT Training : PASS
7045 09:28:08.434338 Write leveling : NO K
7046 09:28:08.434420 RX DQS gating : PASS
7047 09:28:08.437638 RX DQ/DQS(RDDQC) : PASS
7048 09:28:08.437720 TX DQ/DQS : PASS
7049 09:28:08.440641 RX DATLAT : PASS
7050 09:28:08.443899 RX DQ/DQS(Engine): PASS
7051 09:28:08.443982 TX OE : NO K
7052 09:28:08.447377 All Pass.
7053 09:28:08.447460
7054 09:28:08.447525 DramC Write-DBI off
7055 09:28:08.450701 PER_BANK_REFRESH: Hybrid Mode
7056 09:28:08.454296 TX_TRACKING: ON
7057 09:28:08.460601 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7058 09:28:08.463931 [FAST_K] Save calibration result to emmc
7059 09:28:08.467185 dramc_set_vcore_voltage set vcore to 725000
7060 09:28:08.470986 Read voltage for 1600, 0
7061 09:28:08.471069 Vio18 = 0
7062 09:28:08.474209 Vcore = 725000
7063 09:28:08.474292 Vdram = 0
7064 09:28:08.474358 Vddq = 0
7065 09:28:08.477250 Vmddr = 0
7066 09:28:08.480958 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7067 09:28:08.487198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7068 09:28:08.487281 MEM_TYPE=3, freq_sel=13
7069 09:28:08.490555 sv_algorithm_assistance_LP4_3733
7070 09:28:08.497499 ============ PULL DRAM RESETB DOWN ============
7071 09:28:08.500816 ========== PULL DRAM RESETB DOWN end =========
7072 09:28:08.503774 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7073 09:28:08.507247 ===================================
7074 09:28:08.510675 LPDDR4 DRAM CONFIGURATION
7075 09:28:08.514198 ===================================
7076 09:28:08.517257 EX_ROW_EN[0] = 0x0
7077 09:28:08.517352 EX_ROW_EN[1] = 0x0
7078 09:28:08.524272 LP4Y_EN = 0x0
7079 09:28:08.524432 WORK_FSP = 0x1
7080 09:28:08.524526 WL = 0x5
7081 09:28:08.524647 RL = 0x5
7082 09:28:08.527055 BL = 0x2
7083 09:28:08.527136 RPST = 0x0
7084 09:28:08.530597 RD_PRE = 0x0
7085 09:28:08.530678 WR_PRE = 0x1
7086 09:28:08.533861 WR_PST = 0x1
7087 09:28:08.533941 DBI_WR = 0x0
7088 09:28:08.536861 DBI_RD = 0x0
7089 09:28:08.537020 OTF = 0x1
7090 09:28:08.540478 ===================================
7091 09:28:08.543636 ===================================
7092 09:28:08.547461 ANA top config
7093 09:28:08.550400 ===================================
7094 09:28:08.553611 DLL_ASYNC_EN = 0
7095 09:28:08.553707 ALL_SLAVE_EN = 0
7096 09:28:08.557226 NEW_RANK_MODE = 1
7097 09:28:08.560328 DLL_IDLE_MODE = 1
7098 09:28:08.563920 LP45_APHY_COMB_EN = 1
7099 09:28:08.564016 TX_ODT_DIS = 0
7100 09:28:08.567011 NEW_8X_MODE = 1
7101 09:28:08.570513 ===================================
7102 09:28:08.573903 ===================================
7103 09:28:08.577213 data_rate = 3200
7104 09:28:08.580601 CKR = 1
7105 09:28:08.583977 DQ_P2S_RATIO = 8
7106 09:28:08.586933 ===================================
7107 09:28:08.590433 CA_P2S_RATIO = 8
7108 09:28:08.590527 DQ_CA_OPEN = 0
7109 09:28:08.594107 DQ_SEMI_OPEN = 0
7110 09:28:08.597310 CA_SEMI_OPEN = 0
7111 09:28:08.600841 CA_FULL_RATE = 0
7112 09:28:08.603793 DQ_CKDIV4_EN = 0
7113 09:28:08.603874 CA_CKDIV4_EN = 0
7114 09:28:08.606927 CA_PREDIV_EN = 0
7115 09:28:08.610340 PH8_DLY = 12
7116 09:28:08.613721 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7117 09:28:08.617184 DQ_AAMCK_DIV = 4
7118 09:28:08.620251 CA_AAMCK_DIV = 4
7119 09:28:08.620333 CA_ADMCK_DIV = 4
7120 09:28:08.623757 DQ_TRACK_CA_EN = 0
7121 09:28:08.627218 CA_PICK = 1600
7122 09:28:08.630471 CA_MCKIO = 1600
7123 09:28:08.634010 MCKIO_SEMI = 0
7124 09:28:08.637280 PLL_FREQ = 3068
7125 09:28:08.640824 DQ_UI_PI_RATIO = 32
7126 09:28:08.643656 CA_UI_PI_RATIO = 0
7127 09:28:08.646990 ===================================
7128 09:28:08.647072 ===================================
7129 09:28:08.650429 memory_type:LPDDR4
7130 09:28:08.654049 GP_NUM : 10
7131 09:28:08.654139 SRAM_EN : 1
7132 09:28:08.657221 MD32_EN : 0
7133 09:28:08.660117 ===================================
7134 09:28:08.663759 [ANA_INIT] >>>>>>>>>>>>>>
7135 09:28:08.666787 <<<<<< [CONFIGURE PHASE]: ANA_TX
7136 09:28:08.670312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7137 09:28:08.673707 ===================================
7138 09:28:08.673790 data_rate = 3200,PCW = 0X7600
7139 09:28:08.676708 ===================================
7140 09:28:08.683539 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7141 09:28:08.686826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 09:28:08.693267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7143 09:28:08.696621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7144 09:28:08.699924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7145 09:28:08.703301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7146 09:28:08.706916 [ANA_INIT] flow start
7147 09:28:08.709848 [ANA_INIT] PLL >>>>>>>>
7148 09:28:08.709928 [ANA_INIT] PLL <<<<<<<<
7149 09:28:08.713747 [ANA_INIT] MIDPI >>>>>>>>
7150 09:28:08.716536 [ANA_INIT] MIDPI <<<<<<<<
7151 09:28:08.716646 [ANA_INIT] DLL >>>>>>>>
7152 09:28:08.720085 [ANA_INIT] DLL <<<<<<<<
7153 09:28:08.723272 [ANA_INIT] flow end
7154 09:28:08.726572 ============ LP4 DIFF to SE enter ============
7155 09:28:08.730045 ============ LP4 DIFF to SE exit ============
7156 09:28:08.733280 [ANA_INIT] <<<<<<<<<<<<<
7157 09:28:08.736398 [Flow] Enable top DCM control >>>>>
7158 09:28:08.740097 [Flow] Enable top DCM control <<<<<
7159 09:28:08.743061 Enable DLL master slave shuffle
7160 09:28:08.746810 ==============================================================
7161 09:28:08.749963 Gating Mode config
7162 09:28:08.756452 ==============================================================
7163 09:28:08.756533 Config description:
7164 09:28:08.766531 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7165 09:28:08.773285 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7166 09:28:08.776408 SELPH_MODE 0: By rank 1: By Phase
7167 09:28:08.783154 ==============================================================
7168 09:28:08.786430 GAT_TRACK_EN = 1
7169 09:28:08.789729 RX_GATING_MODE = 2
7170 09:28:08.793115 RX_GATING_TRACK_MODE = 2
7171 09:28:08.796690 SELPH_MODE = 1
7172 09:28:08.799866 PICG_EARLY_EN = 1
7173 09:28:08.803084 VALID_LAT_VALUE = 1
7174 09:28:08.806198 ==============================================================
7175 09:28:08.809913 Enter into Gating configuration >>>>
7176 09:28:08.813271 Exit from Gating configuration <<<<
7177 09:28:08.816449 Enter into DVFS_PRE_config >>>>>
7178 09:28:08.829835 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7179 09:28:08.829918 Exit from DVFS_PRE_config <<<<<
7180 09:28:08.833111 Enter into PICG configuration >>>>
7181 09:28:08.836511 Exit from PICG configuration <<<<
7182 09:28:08.839482 [RX_INPUT] configuration >>>>>
7183 09:28:08.843034 [RX_INPUT] configuration <<<<<
7184 09:28:08.849356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7185 09:28:08.852705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7186 09:28:08.859660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 09:28:08.866054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 09:28:08.872651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 09:28:08.879319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 09:28:08.882699 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7191 09:28:08.886059 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7192 09:28:08.889157 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7193 09:28:08.895808 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7194 09:28:08.899293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7195 09:28:08.902720 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 09:28:08.905948 ===================================
7197 09:28:08.909135 LPDDR4 DRAM CONFIGURATION
7198 09:28:08.912476 ===================================
7199 09:28:08.912557 EX_ROW_EN[0] = 0x0
7200 09:28:08.915755 EX_ROW_EN[1] = 0x0
7201 09:28:08.918924 LP4Y_EN = 0x0
7202 09:28:08.919004 WORK_FSP = 0x1
7203 09:28:08.922602 WL = 0x5
7204 09:28:08.922683 RL = 0x5
7205 09:28:08.925739 BL = 0x2
7206 09:28:08.925834 RPST = 0x0
7207 09:28:08.928927 RD_PRE = 0x0
7208 09:28:08.929040 WR_PRE = 0x1
7209 09:28:08.932599 WR_PST = 0x1
7210 09:28:08.932679 DBI_WR = 0x0
7211 09:28:08.935766 DBI_RD = 0x0
7212 09:28:08.935847 OTF = 0x1
7213 09:28:08.939357 ===================================
7214 09:28:08.942427 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7215 09:28:08.949143 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7216 09:28:08.952319 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 09:28:08.955715 ===================================
7218 09:28:08.958696 LPDDR4 DRAM CONFIGURATION
7219 09:28:08.961915 ===================================
7220 09:28:08.961996 EX_ROW_EN[0] = 0x10
7221 09:28:08.965314 EX_ROW_EN[1] = 0x0
7222 09:28:08.968750 LP4Y_EN = 0x0
7223 09:28:08.968845 WORK_FSP = 0x1
7224 09:28:08.972479 WL = 0x5
7225 09:28:08.972586 RL = 0x5
7226 09:28:08.975409 BL = 0x2
7227 09:28:08.975499 RPST = 0x0
7228 09:28:08.978695 RD_PRE = 0x0
7229 09:28:08.978820 WR_PRE = 0x1
7230 09:28:08.982184 WR_PST = 0x1
7231 09:28:08.982281 DBI_WR = 0x0
7232 09:28:08.985293 DBI_RD = 0x0
7233 09:28:08.985465 OTF = 0x1
7234 09:28:08.989157 ===================================
7235 09:28:08.995445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7236 09:28:08.995528 ==
7237 09:28:08.998664 Dram Type= 6, Freq= 0, CH_0, rank 0
7238 09:28:09.002147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7239 09:28:09.002230 ==
7240 09:28:09.005518 [Duty_Offset_Calibration]
7241 09:28:09.008774 B0:2 B1:0 CA:1
7242 09:28:09.008882
7243 09:28:09.012270 [DutyScan_Calibration_Flow] k_type=0
7244 09:28:09.019948
7245 09:28:09.020030 ==CLK 0==
7246 09:28:09.023179 Final CLK duty delay cell = -4
7247 09:28:09.026404 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7248 09:28:09.030026 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7249 09:28:09.033361 [-4] AVG Duty = 4906%(X100)
7250 09:28:09.033443
7251 09:28:09.036345 CH0 CLK Duty spec in!! Max-Min= 187%
7252 09:28:09.040210 [DutyScan_Calibration_Flow] ====Done====
7253 09:28:09.040292
7254 09:28:09.042973 [DutyScan_Calibration_Flow] k_type=1
7255 09:28:09.059509
7256 09:28:09.059590 ==DQS 0 ==
7257 09:28:09.062755 Final DQS duty delay cell = 0
7258 09:28:09.066136 [0] MAX Duty = 5249%(X100), DQS PI = 32
7259 09:28:09.069397 [0] MIN Duty = 4969%(X100), DQS PI = 0
7260 09:28:09.069493 [0] AVG Duty = 5109%(X100)
7261 09:28:09.072571
7262 09:28:09.072653 ==DQS 1 ==
7263 09:28:09.076279 Final DQS duty delay cell = -4
7264 09:28:09.079394 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7265 09:28:09.082351 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7266 09:28:09.085854 [-4] AVG Duty = 5000%(X100)
7267 09:28:09.085937
7268 09:28:09.089195 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7269 09:28:09.089277
7270 09:28:09.092467 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7271 09:28:09.095468 [DutyScan_Calibration_Flow] ====Done====
7272 09:28:09.095558
7273 09:28:09.098798 [DutyScan_Calibration_Flow] k_type=3
7274 09:28:09.116666
7275 09:28:09.116809 ==DQM 0 ==
7276 09:28:09.119989 Final DQM duty delay cell = 0
7277 09:28:09.123560 [0] MAX Duty = 5124%(X100), DQS PI = 26
7278 09:28:09.126625 [0] MIN Duty = 4844%(X100), DQS PI = 0
7279 09:28:09.126707 [0] AVG Duty = 4984%(X100)
7280 09:28:09.130134
7281 09:28:09.130216 ==DQM 1 ==
7282 09:28:09.133211 Final DQM duty delay cell = 0
7283 09:28:09.136670 [0] MAX Duty = 5249%(X100), DQS PI = 28
7284 09:28:09.139795 [0] MIN Duty = 5000%(X100), DQS PI = 20
7285 09:28:09.143334 [0] AVG Duty = 5124%(X100)
7286 09:28:09.143416
7287 09:28:09.146606 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7288 09:28:09.146688
7289 09:28:09.150027 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7290 09:28:09.153674 [DutyScan_Calibration_Flow] ====Done====
7291 09:28:09.153756
7292 09:28:09.156676 [DutyScan_Calibration_Flow] k_type=2
7293 09:28:09.173894
7294 09:28:09.173976 ==DQ 0 ==
7295 09:28:09.177229 Final DQ duty delay cell = 0
7296 09:28:09.180401 [0] MAX Duty = 5156%(X100), DQS PI = 38
7297 09:28:09.184044 [0] MIN Duty = 5000%(X100), DQS PI = 0
7298 09:28:09.184126 [0] AVG Duty = 5078%(X100)
7299 09:28:09.186965
7300 09:28:09.187048 ==DQ 1 ==
7301 09:28:09.190323 Final DQ duty delay cell = 0
7302 09:28:09.193724 [0] MAX Duty = 4969%(X100), DQS PI = 42
7303 09:28:09.196869 [0] MIN Duty = 4875%(X100), DQS PI = 10
7304 09:28:09.196975 [0] AVG Duty = 4922%(X100)
7305 09:28:09.200305
7306 09:28:09.203574 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7307 09:28:09.203682
7308 09:28:09.206709 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7309 09:28:09.210205 [DutyScan_Calibration_Flow] ====Done====
7310 09:28:09.210285 ==
7311 09:28:09.213381 Dram Type= 6, Freq= 0, CH_1, rank 0
7312 09:28:09.216847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7313 09:28:09.216988 ==
7314 09:28:09.220249 [Duty_Offset_Calibration]
7315 09:28:09.220330 B0:0 B1:-1 CA:2
7316 09:28:09.220393
7317 09:28:09.223510 [DutyScan_Calibration_Flow] k_type=0
7318 09:28:09.233956
7319 09:28:09.234036 ==CLK 0==
7320 09:28:09.237213 Final CLK duty delay cell = 0
7321 09:28:09.240770 [0] MAX Duty = 5156%(X100), DQS PI = 10
7322 09:28:09.244015 [0] MIN Duty = 4938%(X100), DQS PI = 46
7323 09:28:09.244142 [0] AVG Duty = 5047%(X100)
7324 09:28:09.247328
7325 09:28:09.250494 CH1 CLK Duty spec in!! Max-Min= 218%
7326 09:28:09.253954 [DutyScan_Calibration_Flow] ====Done====
7327 09:28:09.254034
7328 09:28:09.257320 [DutyScan_Calibration_Flow] k_type=1
7329 09:28:09.273735
7330 09:28:09.273815 ==DQS 0 ==
7331 09:28:09.276907 Final DQS duty delay cell = 0
7332 09:28:09.280061 [0] MAX Duty = 5124%(X100), DQS PI = 26
7333 09:28:09.283842 [0] MIN Duty = 5000%(X100), DQS PI = 0
7334 09:28:09.283923 [0] AVG Duty = 5062%(X100)
7335 09:28:09.286972
7336 09:28:09.287051 ==DQS 1 ==
7337 09:28:09.290085 Final DQS duty delay cell = 0
7338 09:28:09.293672 [0] MAX Duty = 5187%(X100), DQS PI = 0
7339 09:28:09.297027 [0] MIN Duty = 4844%(X100), DQS PI = 32
7340 09:28:09.297107 [0] AVG Duty = 5015%(X100)
7341 09:28:09.300369
7342 09:28:09.303713 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7343 09:28:09.303802
7344 09:28:09.306993 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7345 09:28:09.310120 [DutyScan_Calibration_Flow] ====Done====
7346 09:28:09.310200
7347 09:28:09.313381 [DutyScan_Calibration_Flow] k_type=3
7348 09:28:09.331032
7349 09:28:09.331112 ==DQM 0 ==
7350 09:28:09.334568 Final DQM duty delay cell = 4
7351 09:28:09.338199 [4] MAX Duty = 5125%(X100), DQS PI = 8
7352 09:28:09.341215 [4] MIN Duty = 5000%(X100), DQS PI = 30
7353 09:28:09.344698 [4] AVG Duty = 5062%(X100)
7354 09:28:09.344780
7355 09:28:09.344846 ==DQM 1 ==
7356 09:28:09.347625 Final DQM duty delay cell = 0
7357 09:28:09.350998 [0] MAX Duty = 5281%(X100), DQS PI = 58
7358 09:28:09.354466 [0] MIN Duty = 4876%(X100), DQS PI = 34
7359 09:28:09.357709 [0] AVG Duty = 5078%(X100)
7360 09:28:09.357788
7361 09:28:09.361142 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7362 09:28:09.361222
7363 09:28:09.364155 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7364 09:28:09.367782 [DutyScan_Calibration_Flow] ====Done====
7365 09:28:09.367863
7366 09:28:09.370993 [DutyScan_Calibration_Flow] k_type=2
7367 09:28:09.388169
7368 09:28:09.388249 ==DQ 0 ==
7369 09:28:09.391299 Final DQ duty delay cell = 0
7370 09:28:09.394602 [0] MAX Duty = 5093%(X100), DQS PI = 22
7371 09:28:09.398190 [0] MIN Duty = 4969%(X100), DQS PI = 48
7372 09:28:09.398269 [0] AVG Duty = 5031%(X100)
7373 09:28:09.401526
7374 09:28:09.401619 ==DQ 1 ==
7375 09:28:09.404513 Final DQ duty delay cell = 0
7376 09:28:09.407713 [0] MAX Duty = 5062%(X100), DQS PI = 0
7377 09:28:09.411483 [0] MIN Duty = 4813%(X100), DQS PI = 34
7378 09:28:09.411562 [0] AVG Duty = 4937%(X100)
7379 09:28:09.411624
7380 09:28:09.414526 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7381 09:28:09.418000
7382 09:28:09.421163 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7383 09:28:09.424763 [DutyScan_Calibration_Flow] ====Done====
7384 09:28:09.427798 nWR fixed to 30
7385 09:28:09.427877 [ModeRegInit_LP4] CH0 RK0
7386 09:28:09.431093 [ModeRegInit_LP4] CH0 RK1
7387 09:28:09.434325 [ModeRegInit_LP4] CH1 RK0
7388 09:28:09.437924 [ModeRegInit_LP4] CH1 RK1
7389 09:28:09.438002 match AC timing 5
7390 09:28:09.441283 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7391 09:28:09.447655 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7392 09:28:09.450971 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7393 09:28:09.457583 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7394 09:28:09.460971 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7395 09:28:09.461066 [MiockJmeterHQA]
7396 09:28:09.461128
7397 09:28:09.464200 [DramcMiockJmeter] u1RxGatingPI = 0
7398 09:28:09.467607 0 : 4260, 4031
7399 09:28:09.467688 4 : 4254, 4029
7400 09:28:09.470774 8 : 4257, 4029
7401 09:28:09.470856 12 : 4252, 4027
7402 09:28:09.470922 16 : 4252, 4027
7403 09:28:09.474305 20 : 4252, 4027
7404 09:28:09.474387 24 : 4252, 4027
7405 09:28:09.477711 28 : 4252, 4027
7406 09:28:09.477792 32 : 4253, 4026
7407 09:28:09.480868 36 : 4253, 4026
7408 09:28:09.481001 40 : 4252, 4027
7409 09:28:09.481068 44 : 4363, 4137
7410 09:28:09.484135 48 : 4363, 4138
7411 09:28:09.484216 52 : 4252, 4026
7412 09:28:09.487420 56 : 4255, 4029
7413 09:28:09.487501 60 : 4252, 4029
7414 09:28:09.490645 64 : 4250, 4026
7415 09:28:09.490726 68 : 4252, 4030
7416 09:28:09.493956 72 : 4252, 4029
7417 09:28:09.494038 76 : 4250, 4027
7418 09:28:09.494103 80 : 4250, 4027
7419 09:28:09.497377 84 : 4250, 4027
7420 09:28:09.497460 88 : 4250, 3475
7421 09:28:09.501160 92 : 4252, 0
7422 09:28:09.501244 96 : 4363, 0
7423 09:28:09.501311 100 : 4250, 0
7424 09:28:09.503834 104 : 4250, 0
7425 09:28:09.503932 108 : 4360, 0
7426 09:28:09.507145 112 : 4252, 0
7427 09:28:09.507230 116 : 4360, 0
7428 09:28:09.507299 120 : 4361, 0
7429 09:28:09.510634 124 : 4249, 0
7430 09:28:09.510733 128 : 4250, 0
7431 09:28:09.513940 132 : 4250, 0
7432 09:28:09.514024 136 : 4249, 0
7433 09:28:09.514093 140 : 4252, 0
7434 09:28:09.517336 144 : 4250, 0
7435 09:28:09.517436 148 : 4255, 0
7436 09:28:09.520441 152 : 4253, 0
7437 09:28:09.520553 156 : 4250, 0
7438 09:28:09.520650 160 : 4250, 0
7439 09:28:09.523766 164 : 4252, 0
7440 09:28:09.523879 168 : 4363, 0
7441 09:28:09.523947 172 : 4250, 0
7442 09:28:09.527115 176 : 4363, 0
7443 09:28:09.527228 180 : 4252, 0
7444 09:28:09.530525 184 : 4250, 0
7445 09:28:09.530638 188 : 4249, 0
7446 09:28:09.530733 192 : 4255, 0
7447 09:28:09.533974 196 : 4250, 0
7448 09:28:09.534061 200 : 4249, 3
7449 09:28:09.537363 204 : 4253, 2228
7450 09:28:09.537476 208 : 4250, 4027
7451 09:28:09.540506 212 : 4361, 4138
7452 09:28:09.540606 216 : 4360, 4138
7453 09:28:09.543923 220 : 4250, 4027
7454 09:28:09.544047 224 : 4250, 4027
7455 09:28:09.544145 228 : 4252, 4029
7456 09:28:09.547441 232 : 4250, 4026
7457 09:28:09.547551 236 : 4250, 4026
7458 09:28:09.550660 240 : 4363, 4140
7459 09:28:09.550766 244 : 4250, 4027
7460 09:28:09.554289 248 : 4250, 4026
7461 09:28:09.554381 252 : 4363, 4140
7462 09:28:09.557047 256 : 4250, 4027
7463 09:28:09.557120 260 : 4250, 4027
7464 09:28:09.560843 264 : 4361, 4138
7465 09:28:09.560965 268 : 4361, 4137
7466 09:28:09.564164 272 : 4250, 4027
7467 09:28:09.564262 276 : 4249, 4027
7468 09:28:09.564382 280 : 4252, 4029
7469 09:28:09.567223 284 : 4250, 4026
7470 09:28:09.567302 288 : 4250, 4026
7471 09:28:09.570409 292 : 4363, 4140
7472 09:28:09.570544 296 : 4250, 4027
7473 09:28:09.573821 300 : 4250, 4026
7474 09:28:09.573927 304 : 4363, 4139
7475 09:28:09.577461 308 : 4250, 4027
7476 09:28:09.577564 312 : 4250, 3901
7477 09:28:09.580634 316 : 4363, 2382
7478 09:28:09.580742 320 : 4361, 1
7479 09:28:09.580806
7480 09:28:09.583961 MIOCK jitter meter ch=0
7481 09:28:09.584071
7482 09:28:09.587292 1T = (320-92) = 228 dly cells
7483 09:28:09.590649 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7484 09:28:09.590734 ==
7485 09:28:09.594287 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 09:28:09.600685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 09:28:09.600795 ==
7488 09:28:09.603967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 09:28:09.610652 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 09:28:09.613794 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 09:28:09.620537 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 09:28:09.628170 [CA 0] Center 42 (12~72) winsize 61
7493 09:28:09.631665 [CA 1] Center 42 (12~72) winsize 61
7494 09:28:09.634780 [CA 2] Center 37 (7~67) winsize 61
7495 09:28:09.638403 [CA 3] Center 37 (7~67) winsize 61
7496 09:28:09.641432 [CA 4] Center 36 (6~66) winsize 61
7497 09:28:09.645121 [CA 5] Center 35 (5~65) winsize 61
7498 09:28:09.645204
7499 09:28:09.648174 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 09:28:09.648258
7501 09:28:09.651540 [CATrainingPosCal] consider 1 rank data
7502 09:28:09.654757 u2DelayCellTimex100 = 285/100 ps
7503 09:28:09.658196 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7504 09:28:09.665129 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7505 09:28:09.668283 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7506 09:28:09.671494 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7507 09:28:09.674802 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7508 09:28:09.678147 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7509 09:28:09.678250
7510 09:28:09.681373 CA PerBit enable=1, Macro0, CA PI delay=35
7511 09:28:09.681449
7512 09:28:09.684717 [CBTSetCACLKResult] CA Dly = 35
7513 09:28:09.684814 CS Dly: 9 (0~40)
7514 09:28:09.691296 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 09:28:09.694832 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 09:28:09.694916 ==
7517 09:28:09.698216 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 09:28:09.701192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 09:28:09.701277 ==
7520 09:28:09.707984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 09:28:09.711082 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 09:28:09.717862 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 09:28:09.721101 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 09:28:09.731443 [CA 0] Center 43 (13~74) winsize 62
7525 09:28:09.734781 [CA 1] Center 43 (13~73) winsize 61
7526 09:28:09.737977 [CA 2] Center 38 (9~68) winsize 60
7527 09:28:09.741101 [CA 3] Center 38 (9~68) winsize 60
7528 09:28:09.744799 [CA 4] Center 36 (7~66) winsize 60
7529 09:28:09.747886 [CA 5] Center 36 (6~66) winsize 61
7530 09:28:09.747969
7531 09:28:09.751455 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 09:28:09.751538
7533 09:28:09.755404 [CATrainingPosCal] consider 2 rank data
7534 09:28:09.758324 u2DelayCellTimex100 = 285/100 ps
7535 09:28:09.761316 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7536 09:28:09.767816 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7537 09:28:09.771035 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7538 09:28:09.774942 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7539 09:28:09.777879 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7540 09:28:09.781655 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7541 09:28:09.781737
7542 09:28:09.784835 CA PerBit enable=1, Macro0, CA PI delay=35
7543 09:28:09.784918
7544 09:28:09.787949 [CBTSetCACLKResult] CA Dly = 35
7545 09:28:09.791477 CS Dly: 10 (0~43)
7546 09:28:09.795224 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 09:28:09.798212 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 09:28:09.798295
7549 09:28:09.801553 ----->DramcWriteLeveling(PI) begin...
7550 09:28:09.801636 ==
7551 09:28:09.804884 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 09:28:09.808064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 09:28:09.811537 ==
7554 09:28:09.811632 Write leveling (Byte 0): 37 => 37
7555 09:28:09.814656 Write leveling (Byte 1): 31 => 31
7556 09:28:09.817983 DramcWriteLeveling(PI) end<-----
7557 09:28:09.818103
7558 09:28:09.818205 ==
7559 09:28:09.821319 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 09:28:09.827821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 09:28:09.827965 ==
7562 09:28:09.828054 [Gating] SW mode calibration
7563 09:28:09.838269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 09:28:09.841528 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 09:28:09.848100 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 09:28:09.851388 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 09:28:09.854455 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7568 09:28:09.857773 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7569 09:28:09.864405 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7570 09:28:09.867931 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 09:28:09.870840 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 09:28:09.878252 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 09:28:09.881188 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 09:28:09.884564 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 09:28:09.891240 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7576 09:28:09.894440 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7577 09:28:09.897741 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7578 09:28:09.904607 1 5 20 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
7579 09:28:09.907848 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 09:28:09.911062 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 09:28:09.918009 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 09:28:09.920943 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 09:28:09.924413 1 6 8 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7584 09:28:09.931387 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7585 09:28:09.934305 1 6 16 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
7586 09:28:09.937668 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7587 09:28:09.944475 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 09:28:09.947632 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 09:28:09.950997 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 09:28:09.957571 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 09:28:09.960858 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 09:28:09.964439 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 09:28:09.970880 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7594 09:28:09.974148 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 09:28:09.977715 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 09:28:09.980875 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 09:28:09.987526 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 09:28:09.991209 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 09:28:09.994095 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 09:28:10.000898 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 09:28:10.004028 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 09:28:10.007758 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 09:28:10.014328 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 09:28:10.017729 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 09:28:10.020910 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 09:28:10.027606 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 09:28:10.031046 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 09:28:10.034061 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 09:28:10.041176 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 09:28:10.041725 Total UI for P1: 0, mck2ui 16
7611 09:28:10.047784 best dqsien dly found for B0: ( 1, 9, 10)
7612 09:28:10.051182 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 09:28:10.054371 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 09:28:10.057722 Total UI for P1: 0, mck2ui 16
7615 09:28:10.060812 best dqsien dly found for B1: ( 1, 9, 18)
7616 09:28:10.064526 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7617 09:28:10.067597 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7618 09:28:10.068188
7619 09:28:10.074163 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7620 09:28:10.077480 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7621 09:28:10.077876 [Gating] SW calibration Done
7622 09:28:10.081159 ==
7623 09:28:10.084265 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 09:28:10.087488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 09:28:10.087884 ==
7626 09:28:10.088204 RX Vref Scan: 0
7627 09:28:10.088529
7628 09:28:10.090966 RX Vref 0 -> 0, step: 1
7629 09:28:10.091372
7630 09:28:10.094445 RX Delay 0 -> 252, step: 8
7631 09:28:10.097375 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7632 09:28:10.100750 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7633 09:28:10.104507 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7634 09:28:10.111181 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7635 09:28:10.114314 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7636 09:28:10.117521 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7637 09:28:10.121135 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7638 09:28:10.124638 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7639 09:28:10.131498 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7640 09:28:10.134516 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7641 09:28:10.137835 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7642 09:28:10.141250 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7643 09:28:10.144375 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7644 09:28:10.151060 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7645 09:28:10.154208 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7646 09:28:10.157768 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7647 09:28:10.158197 ==
7648 09:28:10.160974 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 09:28:10.163984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 09:28:10.164432 ==
7651 09:28:10.167469 DQS Delay:
7652 09:28:10.167897 DQS0 = 0, DQS1 = 0
7653 09:28:10.170933 DQM Delay:
7654 09:28:10.171361 DQM0 = 138, DQM1 = 126
7655 09:28:10.171705 DQ Delay:
7656 09:28:10.174102 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7657 09:28:10.177555 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7658 09:28:10.183986 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7659 09:28:10.187676 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7660 09:28:10.188105
7661 09:28:10.188448
7662 09:28:10.188763 ==
7663 09:28:10.191119 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 09:28:10.194270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 09:28:10.194796 ==
7666 09:28:10.195236
7667 09:28:10.195722
7668 09:28:10.197606 TX Vref Scan disable
7669 09:28:10.201195 == TX Byte 0 ==
7670 09:28:10.204756 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7671 09:28:10.208007 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7672 09:28:10.210676 == TX Byte 1 ==
7673 09:28:10.214216 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7674 09:28:10.217537 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7675 09:28:10.217967 ==
7676 09:28:10.221298 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 09:28:10.224094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 09:28:10.224546 ==
7679 09:28:10.238655
7680 09:28:10.242146 TX Vref early break, caculate TX vref
7681 09:28:10.245295 TX Vref=16, minBit 0, minWin=23, winSum=375
7682 09:28:10.248625 TX Vref=18, minBit 6, minWin=23, winSum=389
7683 09:28:10.252054 TX Vref=20, minBit 1, minWin=24, winSum=398
7684 09:28:10.255388 TX Vref=22, minBit 7, minWin=24, winSum=407
7685 09:28:10.258646 TX Vref=24, minBit 7, minWin=24, winSum=413
7686 09:28:10.265166 TX Vref=26, minBit 2, minWin=25, winSum=423
7687 09:28:10.268317 TX Vref=28, minBit 0, minWin=26, winSum=432
7688 09:28:10.271723 TX Vref=30, minBit 0, minWin=25, winSum=422
7689 09:28:10.275573 TX Vref=32, minBit 0, minWin=25, winSum=414
7690 09:28:10.278576 TX Vref=34, minBit 7, minWin=24, winSum=408
7691 09:28:10.285537 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7692 09:28:10.286125
7693 09:28:10.288358 Final TX Range 0 Vref 28
7694 09:28:10.288789
7695 09:28:10.289157 ==
7696 09:28:10.291754 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 09:28:10.295556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 09:28:10.296082 ==
7699 09:28:10.296433
7700 09:28:10.296753
7701 09:28:10.298579 TX Vref Scan disable
7702 09:28:10.305268 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7703 09:28:10.305795 == TX Byte 0 ==
7704 09:28:10.308761 u2DelayCellOfst[0]=13 cells (4 PI)
7705 09:28:10.311991 u2DelayCellOfst[1]=13 cells (4 PI)
7706 09:28:10.315216 u2DelayCellOfst[2]=10 cells (3 PI)
7707 09:28:10.318380 u2DelayCellOfst[3]=10 cells (3 PI)
7708 09:28:10.322062 u2DelayCellOfst[4]=6 cells (2 PI)
7709 09:28:10.324914 u2DelayCellOfst[5]=0 cells (0 PI)
7710 09:28:10.328652 u2DelayCellOfst[6]=17 cells (5 PI)
7711 09:28:10.329227 u2DelayCellOfst[7]=17 cells (5 PI)
7712 09:28:10.335157 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7713 09:28:10.338353 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7714 09:28:10.338784 == TX Byte 1 ==
7715 09:28:10.341760 u2DelayCellOfst[8]=0 cells (0 PI)
7716 09:28:10.345241 u2DelayCellOfst[9]=3 cells (1 PI)
7717 09:28:10.348524 u2DelayCellOfst[10]=6 cells (2 PI)
7718 09:28:10.352130 u2DelayCellOfst[11]=3 cells (1 PI)
7719 09:28:10.354942 u2DelayCellOfst[12]=13 cells (4 PI)
7720 09:28:10.358600 u2DelayCellOfst[13]=13 cells (4 PI)
7721 09:28:10.361863 u2DelayCellOfst[14]=13 cells (4 PI)
7722 09:28:10.365444 u2DelayCellOfst[15]=10 cells (3 PI)
7723 09:28:10.368736 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7724 09:28:10.374756 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7725 09:28:10.375268 DramC Write-DBI on
7726 09:28:10.375608 ==
7727 09:28:10.378265 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 09:28:10.381836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 09:28:10.382269 ==
7730 09:28:10.384902
7731 09:28:10.385375
7732 09:28:10.385720 TX Vref Scan disable
7733 09:28:10.388325 == TX Byte 0 ==
7734 09:28:10.391357 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7735 09:28:10.394647 == TX Byte 1 ==
7736 09:28:10.398765 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7737 09:28:10.399288 DramC Write-DBI off
7738 09:28:10.401975
7739 09:28:10.402436 [DATLAT]
7740 09:28:10.402783 Freq=1600, CH0 RK0
7741 09:28:10.403109
7742 09:28:10.404765 DATLAT Default: 0xf
7743 09:28:10.405326 0, 0xFFFF, sum = 0
7744 09:28:10.408566 1, 0xFFFF, sum = 0
7745 09:28:10.409044 2, 0xFFFF, sum = 0
7746 09:28:10.412195 3, 0xFFFF, sum = 0
7747 09:28:10.412722 4, 0xFFFF, sum = 0
7748 09:28:10.415041 5, 0xFFFF, sum = 0
7749 09:28:10.415569 6, 0xFFFF, sum = 0
7750 09:28:10.418211 7, 0xFFFF, sum = 0
7751 09:28:10.421849 8, 0xFFFF, sum = 0
7752 09:28:10.422378 9, 0xFFFF, sum = 0
7753 09:28:10.425145 10, 0xFFFF, sum = 0
7754 09:28:10.425677 11, 0xFFFF, sum = 0
7755 09:28:10.428859 12, 0xFFFF, sum = 0
7756 09:28:10.429428 13, 0xFFFF, sum = 0
7757 09:28:10.431487 14, 0x0, sum = 1
7758 09:28:10.431920 15, 0x0, sum = 2
7759 09:28:10.435073 16, 0x0, sum = 3
7760 09:28:10.435608 17, 0x0, sum = 4
7761 09:28:10.435964 best_step = 15
7762 09:28:10.438349
7763 09:28:10.438839 ==
7764 09:28:10.441843 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 09:28:10.445143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 09:28:10.445679 ==
7767 09:28:10.446035 RX Vref Scan: 1
7768 09:28:10.446357
7769 09:28:10.448382 Set Vref Range= 24 -> 127
7770 09:28:10.448908
7771 09:28:10.451590 RX Vref 24 -> 127, step: 1
7772 09:28:10.452017
7773 09:28:10.454959 RX Delay 19 -> 252, step: 4
7774 09:28:10.455387
7775 09:28:10.458854 Set Vref, RX VrefLevel [Byte0]: 24
7776 09:28:10.461926 [Byte1]: 24
7777 09:28:10.462355
7778 09:28:10.465117 Set Vref, RX VrefLevel [Byte0]: 25
7779 09:28:10.468498 [Byte1]: 25
7780 09:28:10.468945
7781 09:28:10.472080 Set Vref, RX VrefLevel [Byte0]: 26
7782 09:28:10.474705 [Byte1]: 26
7783 09:28:10.478327
7784 09:28:10.478758 Set Vref, RX VrefLevel [Byte0]: 27
7785 09:28:10.481790 [Byte1]: 27
7786 09:28:10.486615
7787 09:28:10.487141 Set Vref, RX VrefLevel [Byte0]: 28
7788 09:28:10.489189 [Byte1]: 28
7789 09:28:10.493567
7790 09:28:10.494091 Set Vref, RX VrefLevel [Byte0]: 29
7791 09:28:10.497094 [Byte1]: 29
7792 09:28:10.501120
7793 09:28:10.501662 Set Vref, RX VrefLevel [Byte0]: 30
7794 09:28:10.504330 [Byte1]: 30
7795 09:28:10.508809
7796 09:28:10.509394 Set Vref, RX VrefLevel [Byte0]: 31
7797 09:28:10.512296 [Byte1]: 31
7798 09:28:10.516782
7799 09:28:10.517362 Set Vref, RX VrefLevel [Byte0]: 32
7800 09:28:10.519518 [Byte1]: 32
7801 09:28:10.524146
7802 09:28:10.524674 Set Vref, RX VrefLevel [Byte0]: 33
7803 09:28:10.527444 [Byte1]: 33
7804 09:28:10.531710
7805 09:28:10.532239 Set Vref, RX VrefLevel [Byte0]: 34
7806 09:28:10.535424 [Byte1]: 34
7807 09:28:10.538954
7808 09:28:10.539484 Set Vref, RX VrefLevel [Byte0]: 35
7809 09:28:10.542528 [Byte1]: 35
7810 09:28:10.546711
7811 09:28:10.547242 Set Vref, RX VrefLevel [Byte0]: 36
7812 09:28:10.549928 [Byte1]: 36
7813 09:28:10.554607
7814 09:28:10.555140 Set Vref, RX VrefLevel [Byte0]: 37
7815 09:28:10.557348 [Byte1]: 37
7816 09:28:10.561606
7817 09:28:10.562028 Set Vref, RX VrefLevel [Byte0]: 38
7818 09:28:10.565262 [Byte1]: 38
7819 09:28:10.569474
7820 09:28:10.570007 Set Vref, RX VrefLevel [Byte0]: 39
7821 09:28:10.572705 [Byte1]: 39
7822 09:28:10.576822
7823 09:28:10.577301 Set Vref, RX VrefLevel [Byte0]: 40
7824 09:28:10.580047 [Byte1]: 40
7825 09:28:10.584237
7826 09:28:10.584662 Set Vref, RX VrefLevel [Byte0]: 41
7827 09:28:10.587427 [Byte1]: 41
7828 09:28:10.592243
7829 09:28:10.592771 Set Vref, RX VrefLevel [Byte0]: 42
7830 09:28:10.595591 [Byte1]: 42
7831 09:28:10.599788
7832 09:28:10.600323 Set Vref, RX VrefLevel [Byte0]: 43
7833 09:28:10.602742 [Byte1]: 43
7834 09:28:10.607244
7835 09:28:10.607777 Set Vref, RX VrefLevel [Byte0]: 44
7836 09:28:10.610130 [Byte1]: 44
7837 09:28:10.614739
7838 09:28:10.615270 Set Vref, RX VrefLevel [Byte0]: 45
7839 09:28:10.618308 [Byte1]: 45
7840 09:28:10.622365
7841 09:28:10.622898 Set Vref, RX VrefLevel [Byte0]: 46
7842 09:28:10.625823 [Byte1]: 46
7843 09:28:10.630162
7844 09:28:10.630697 Set Vref, RX VrefLevel [Byte0]: 47
7845 09:28:10.633664 [Byte1]: 47
7846 09:28:10.637559
7847 09:28:10.638090 Set Vref, RX VrefLevel [Byte0]: 48
7848 09:28:10.640866 [Byte1]: 48
7849 09:28:10.645391
7850 09:28:10.645917 Set Vref, RX VrefLevel [Byte0]: 49
7851 09:28:10.648877 [Byte1]: 49
7852 09:28:10.652691
7853 09:28:10.653267 Set Vref, RX VrefLevel [Byte0]: 50
7854 09:28:10.655821 [Byte1]: 50
7855 09:28:10.660443
7856 09:28:10.660992 Set Vref, RX VrefLevel [Byte0]: 51
7857 09:28:10.663831 [Byte1]: 51
7858 09:28:10.668058
7859 09:28:10.668649 Set Vref, RX VrefLevel [Byte0]: 52
7860 09:28:10.671303 [Byte1]: 52
7861 09:28:10.675442
7862 09:28:10.675896 Set Vref, RX VrefLevel [Byte0]: 53
7863 09:28:10.678558 [Byte1]: 53
7864 09:28:10.682976
7865 09:28:10.683403 Set Vref, RX VrefLevel [Byte0]: 54
7866 09:28:10.685932 [Byte1]: 54
7867 09:28:10.690364
7868 09:28:10.690892 Set Vref, RX VrefLevel [Byte0]: 55
7869 09:28:10.693481 [Byte1]: 55
7870 09:28:10.698040
7871 09:28:10.698578 Set Vref, RX VrefLevel [Byte0]: 56
7872 09:28:10.701666 [Byte1]: 56
7873 09:28:10.705627
7874 09:28:10.706156 Set Vref, RX VrefLevel [Byte0]: 57
7875 09:28:10.708870 [Byte1]: 57
7876 09:28:10.713195
7877 09:28:10.713718 Set Vref, RX VrefLevel [Byte0]: 58
7878 09:28:10.716369 [Byte1]: 58
7879 09:28:10.720863
7880 09:28:10.721418 Set Vref, RX VrefLevel [Byte0]: 59
7881 09:28:10.724222 [Byte1]: 59
7882 09:28:10.728636
7883 09:28:10.729197 Set Vref, RX VrefLevel [Byte0]: 60
7884 09:28:10.732182 [Byte1]: 60
7885 09:28:10.735988
7886 09:28:10.736506 Set Vref, RX VrefLevel [Byte0]: 61
7887 09:28:10.738950 [Byte1]: 61
7888 09:28:10.743652
7889 09:28:10.744180 Set Vref, RX VrefLevel [Byte0]: 62
7890 09:28:10.746621 [Byte1]: 62
7891 09:28:10.751244
7892 09:28:10.751767 Set Vref, RX VrefLevel [Byte0]: 63
7893 09:28:10.754715 [Byte1]: 63
7894 09:28:10.758640
7895 09:28:10.759166 Set Vref, RX VrefLevel [Byte0]: 64
7896 09:28:10.761585 [Byte1]: 64
7897 09:28:10.766380
7898 09:28:10.766904 Set Vref, RX VrefLevel [Byte0]: 65
7899 09:28:10.769761 [Byte1]: 65
7900 09:28:10.773826
7901 09:28:10.774353 Set Vref, RX VrefLevel [Byte0]: 66
7902 09:28:10.777044 [Byte1]: 66
7903 09:28:10.781365
7904 09:28:10.781885 Set Vref, RX VrefLevel [Byte0]: 67
7905 09:28:10.784696 [Byte1]: 67
7906 09:28:10.788806
7907 09:28:10.789375 Set Vref, RX VrefLevel [Byte0]: 68
7908 09:28:10.792322 [Byte1]: 68
7909 09:28:10.796479
7910 09:28:10.797053 Set Vref, RX VrefLevel [Byte0]: 69
7911 09:28:10.799813 [Byte1]: 69
7912 09:28:10.804238
7913 09:28:10.804777 Set Vref, RX VrefLevel [Byte0]: 70
7914 09:28:10.807147 [Byte1]: 70
7915 09:28:10.811520
7916 09:28:10.811949 Set Vref, RX VrefLevel [Byte0]: 71
7917 09:28:10.814950 [Byte1]: 71
7918 09:28:10.819169
7919 09:28:10.819597 Set Vref, RX VrefLevel [Byte0]: 72
7920 09:28:10.822670 [Byte1]: 72
7921 09:28:10.826802
7922 09:28:10.827325 Set Vref, RX VrefLevel [Byte0]: 73
7923 09:28:10.830431 [Byte1]: 73
7924 09:28:10.834886
7925 09:28:10.835409 Set Vref, RX VrefLevel [Byte0]: 74
7926 09:28:10.837732 [Byte1]: 74
7927 09:28:10.842203
7928 09:28:10.842724 Set Vref, RX VrefLevel [Byte0]: 75
7929 09:28:10.845387 [Byte1]: 75
7930 09:28:10.849553
7931 09:28:10.850079 Set Vref, RX VrefLevel [Byte0]: 76
7932 09:28:10.853111 [Byte1]: 76
7933 09:28:10.857307
7934 09:28:10.857832 Set Vref, RX VrefLevel [Byte0]: 77
7935 09:28:10.860559 [Byte1]: 77
7936 09:28:10.865265
7937 09:28:10.865781 Final RX Vref Byte 0 = 61 to rank0
7938 09:28:10.868384 Final RX Vref Byte 1 = 63 to rank0
7939 09:28:10.871261 Final RX Vref Byte 0 = 61 to rank1
7940 09:28:10.874820 Final RX Vref Byte 1 = 63 to rank1==
7941 09:28:10.878147 Dram Type= 6, Freq= 0, CH_0, rank 0
7942 09:28:10.885350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 09:28:10.885881 ==
7944 09:28:10.886230 DQS Delay:
7945 09:28:10.886549 DQS0 = 0, DQS1 = 0
7946 09:28:10.888101 DQM Delay:
7947 09:28:10.888530 DQM0 = 136, DQM1 = 124
7948 09:28:10.891441 DQ Delay:
7949 09:28:10.895019 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7950 09:28:10.898525 DQ4 =138, DQ5 =124, DQ6 =146, DQ7 =142
7951 09:28:10.901631 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7952 09:28:10.904729 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7953 09:28:10.905268
7954 09:28:10.905623
7955 09:28:10.905940
7956 09:28:10.907691 [DramC_TX_OE_Calibration] TA2
7957 09:28:10.911095 Original DQ_B0 (3 6) =30, OEN = 27
7958 09:28:10.914574 Original DQ_B1 (3 6) =30, OEN = 27
7959 09:28:10.917448 24, 0x0, End_B0=24 End_B1=24
7960 09:28:10.917882 25, 0x0, End_B0=25 End_B1=25
7961 09:28:10.920887 26, 0x0, End_B0=26 End_B1=26
7962 09:28:10.924630 27, 0x0, End_B0=27 End_B1=27
7963 09:28:10.928078 28, 0x0, End_B0=28 End_B1=28
7964 09:28:10.931478 29, 0x0, End_B0=29 End_B1=29
7965 09:28:10.932022 30, 0x0, End_B0=30 End_B1=30
7966 09:28:10.934418 31, 0x4141, End_B0=30 End_B1=30
7967 09:28:10.937755 Byte0 end_step=30 best_step=27
7968 09:28:10.941007 Byte1 end_step=30 best_step=27
7969 09:28:10.944367 Byte0 TX OE(2T, 0.5T) = (3, 3)
7970 09:28:10.948115 Byte1 TX OE(2T, 0.5T) = (3, 3)
7971 09:28:10.948656
7972 09:28:10.949163
7973 09:28:10.954339 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7974 09:28:10.957798 CH0 RK0: MR19=303, MR18=1E1C
7975 09:28:10.964656 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7976 09:28:10.965247
7977 09:28:10.967731 ----->DramcWriteLeveling(PI) begin...
7978 09:28:10.968273 ==
7979 09:28:10.971057 Dram Type= 6, Freq= 0, CH_0, rank 1
7980 09:28:10.974538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 09:28:10.975025 ==
7982 09:28:10.977440 Write leveling (Byte 0): 39 => 39
7983 09:28:10.980763 Write leveling (Byte 1): 30 => 30
7984 09:28:10.983822 DramcWriteLeveling(PI) end<-----
7985 09:28:10.984358
7986 09:28:10.984705 ==
7987 09:28:10.987272 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 09:28:10.990443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 09:28:10.990879 ==
7990 09:28:10.993591 [Gating] SW mode calibration
7991 09:28:11.000574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7992 09:28:11.007061 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7993 09:28:11.010173 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 09:28:11.016844 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 09:28:11.020561 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7996 09:28:11.023882 1 4 12 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
7997 09:28:11.030735 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 09:28:11.033566 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 09:28:11.037058 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 09:28:11.043998 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 09:28:11.046571 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 09:28:11.049955 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 09:28:11.056758 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 09:28:11.059666 1 5 12 | B1->B0 | 3333 2929 | 0 0 | (0 1) (1 0)
8005 09:28:11.063164 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8006 09:28:11.066874 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 09:28:11.073645 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 09:28:11.076692 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 09:28:11.080061 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 09:28:11.086555 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 09:28:11.089643 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8012 09:28:11.093116 1 6 12 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
8013 09:28:11.100260 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 09:28:11.103180 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 09:28:11.106736 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 09:28:11.113233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 09:28:11.116297 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 09:28:11.119683 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 09:28:11.126370 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 09:28:11.129738 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8021 09:28:11.133352 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8022 09:28:11.139636 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 09:28:11.142989 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 09:28:11.146620 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 09:28:11.152969 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 09:28:11.156561 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 09:28:11.159842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 09:28:11.166724 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 09:28:11.169802 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 09:28:11.173048 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 09:28:11.179776 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 09:28:11.183156 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 09:28:11.186234 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 09:28:11.193171 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 09:28:11.196601 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8036 09:28:11.199760 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8037 09:28:11.203171 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8038 09:28:11.209641 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 09:28:11.212862 Total UI for P1: 0, mck2ui 16
8040 09:28:11.215890 best dqsien dly found for B0: ( 1, 9, 12)
8041 09:28:11.219064 Total UI for P1: 0, mck2ui 16
8042 09:28:11.222611 best dqsien dly found for B1: ( 1, 9, 14)
8043 09:28:11.225639 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8044 09:28:11.229337 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8045 09:28:11.229871
8046 09:28:11.232595 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8047 09:28:11.236134 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8048 09:28:11.239022 [Gating] SW calibration Done
8049 09:28:11.239411 ==
8050 09:28:11.242364 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 09:28:11.246240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 09:28:11.246762 ==
8053 09:28:11.249103 RX Vref Scan: 0
8054 09:28:11.249525
8055 09:28:11.252340 RX Vref 0 -> 0, step: 1
8056 09:28:11.252758
8057 09:28:11.253144 RX Delay 0 -> 252, step: 8
8058 09:28:11.259477 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8059 09:28:11.262656 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8060 09:28:11.266011 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8061 09:28:11.269348 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8062 09:28:11.272795 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8063 09:28:11.279289 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8064 09:28:11.282465 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8065 09:28:11.285714 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8066 09:28:11.289472 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8067 09:28:11.292717 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8068 09:28:11.299279 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8069 09:28:11.302726 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8070 09:28:11.305556 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8071 09:28:11.309348 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8072 09:28:11.312441 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8073 09:28:11.319049 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8074 09:28:11.319617 ==
8075 09:28:11.322210 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 09:28:11.326021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 09:28:11.326546 ==
8078 09:28:11.326885 DQS Delay:
8079 09:28:11.329543 DQS0 = 0, DQS1 = 0
8080 09:28:11.330072 DQM Delay:
8081 09:28:11.332471 DQM0 = 136, DQM1 = 125
8082 09:28:11.333036 DQ Delay:
8083 09:28:11.335464 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8084 09:28:11.338716 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8085 09:28:11.341887 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8086 09:28:11.345686 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8087 09:28:11.348761
8088 09:28:11.349227
8089 09:28:11.349566 ==
8090 09:28:11.351845 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 09:28:11.355623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 09:28:11.356158 ==
8093 09:28:11.356500
8094 09:28:11.356813
8095 09:28:11.358786 TX Vref Scan disable
8096 09:28:11.359205 == TX Byte 0 ==
8097 09:28:11.365393 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8098 09:28:11.368739 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8099 09:28:11.369312 == TX Byte 1 ==
8100 09:28:11.375819 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8101 09:28:11.378412 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8102 09:28:11.378900 ==
8103 09:28:11.381974 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 09:28:11.385555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 09:28:11.386072 ==
8106 09:28:11.399792
8107 09:28:11.403150 TX Vref early break, caculate TX vref
8108 09:28:11.406491 TX Vref=16, minBit 3, minWin=23, winSum=387
8109 09:28:11.409821 TX Vref=18, minBit 8, minWin=23, winSum=396
8110 09:28:11.413380 TX Vref=20, minBit 8, minWin=24, winSum=404
8111 09:28:11.416853 TX Vref=22, minBit 0, minWin=25, winSum=412
8112 09:28:11.419952 TX Vref=24, minBit 0, minWin=25, winSum=420
8113 09:28:11.426480 TX Vref=26, minBit 0, minWin=25, winSum=434
8114 09:28:11.429640 TX Vref=28, minBit 0, minWin=26, winSum=435
8115 09:28:11.432923 TX Vref=30, minBit 0, minWin=26, winSum=426
8116 09:28:11.436314 TX Vref=32, minBit 0, minWin=26, winSum=423
8117 09:28:11.439416 TX Vref=34, minBit 4, minWin=24, winSum=408
8118 09:28:11.446216 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 28
8119 09:28:11.446743
8120 09:28:11.449281 Final TX Range 0 Vref 28
8121 09:28:11.449727
8122 09:28:11.450060 ==
8123 09:28:11.452794 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 09:28:11.456242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 09:28:11.456666 ==
8126 09:28:11.457044
8127 09:28:11.457361
8128 09:28:11.459728 TX Vref Scan disable
8129 09:28:11.466172 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8130 09:28:11.466687 == TX Byte 0 ==
8131 09:28:11.469280 u2DelayCellOfst[0]=13 cells (4 PI)
8132 09:28:11.472858 u2DelayCellOfst[1]=20 cells (6 PI)
8133 09:28:11.476390 u2DelayCellOfst[2]=13 cells (4 PI)
8134 09:28:11.479374 u2DelayCellOfst[3]=13 cells (4 PI)
8135 09:28:11.482822 u2DelayCellOfst[4]=10 cells (3 PI)
8136 09:28:11.486176 u2DelayCellOfst[5]=0 cells (0 PI)
8137 09:28:11.489364 u2DelayCellOfst[6]=20 cells (6 PI)
8138 09:28:11.492899 u2DelayCellOfst[7]=20 cells (6 PI)
8139 09:28:11.496076 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8140 09:28:11.499498 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8141 09:28:11.502984 == TX Byte 1 ==
8142 09:28:11.503511 u2DelayCellOfst[8]=0 cells (0 PI)
8143 09:28:11.506352 u2DelayCellOfst[9]=3 cells (1 PI)
8144 09:28:11.509471 u2DelayCellOfst[10]=6 cells (2 PI)
8145 09:28:11.513107 u2DelayCellOfst[11]=3 cells (1 PI)
8146 09:28:11.516526 u2DelayCellOfst[12]=13 cells (4 PI)
8147 09:28:11.519118 u2DelayCellOfst[13]=13 cells (4 PI)
8148 09:28:11.522586 u2DelayCellOfst[14]=17 cells (5 PI)
8149 09:28:11.525635 u2DelayCellOfst[15]=10 cells (3 PI)
8150 09:28:11.529171 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8151 09:28:11.536275 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8152 09:28:11.536852 DramC Write-DBI on
8153 09:28:11.537255 ==
8154 09:28:11.539288 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 09:28:11.542874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 09:28:11.545480 ==
8157 09:28:11.545925
8158 09:28:11.546378
8159 09:28:11.546748 TX Vref Scan disable
8160 09:28:11.549523 == TX Byte 0 ==
8161 09:28:11.552357 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8162 09:28:11.555761 == TX Byte 1 ==
8163 09:28:11.559033 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8164 09:28:11.562762 DramC Write-DBI off
8165 09:28:11.563196
8166 09:28:11.563539 [DATLAT]
8167 09:28:11.563857 Freq=1600, CH0 RK1
8168 09:28:11.564225
8169 09:28:11.565902 DATLAT Default: 0xf
8170 09:28:11.566374 0, 0xFFFF, sum = 0
8171 09:28:11.568994 1, 0xFFFF, sum = 0
8172 09:28:11.572768 2, 0xFFFF, sum = 0
8173 09:28:11.573276 3, 0xFFFF, sum = 0
8174 09:28:11.575723 4, 0xFFFF, sum = 0
8175 09:28:11.576157 5, 0xFFFF, sum = 0
8176 09:28:11.579051 6, 0xFFFF, sum = 0
8177 09:28:11.579625 7, 0xFFFF, sum = 0
8178 09:28:11.582383 8, 0xFFFF, sum = 0
8179 09:28:11.582823 9, 0xFFFF, sum = 0
8180 09:28:11.585425 10, 0xFFFF, sum = 0
8181 09:28:11.585972 11, 0xFFFF, sum = 0
8182 09:28:11.589376 12, 0xFFFF, sum = 0
8183 09:28:11.589927 13, 0xFFFF, sum = 0
8184 09:28:11.592232 14, 0x0, sum = 1
8185 09:28:11.592777 15, 0x0, sum = 2
8186 09:28:11.595772 16, 0x0, sum = 3
8187 09:28:11.596208 17, 0x0, sum = 4
8188 09:28:11.599123 best_step = 15
8189 09:28:11.599548
8190 09:28:11.599890 ==
8191 09:28:11.602910 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 09:28:11.605642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 09:28:11.606076 ==
8194 09:28:11.608888 RX Vref Scan: 0
8195 09:28:11.609348
8196 09:28:11.609695 RX Vref 0 -> 0, step: 1
8197 09:28:11.610017
8198 09:28:11.613095 RX Delay 11 -> 252, step: 4
8199 09:28:11.616117 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8200 09:28:11.622429 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8201 09:28:11.625393 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8202 09:28:11.628560 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8203 09:28:11.631907 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8204 09:28:11.635214 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8205 09:28:11.642053 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8206 09:28:11.645214 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8207 09:28:11.648613 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8208 09:28:11.652037 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8209 09:28:11.655356 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8210 09:28:11.662175 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8211 09:28:11.665199 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8212 09:28:11.668753 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8213 09:28:11.672119 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8214 09:28:11.675321 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8215 09:28:11.678374 ==
8216 09:28:11.682105 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 09:28:11.685190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 09:28:11.685755 ==
8219 09:28:11.686176 DQS Delay:
8220 09:28:11.688385 DQS0 = 0, DQS1 = 0
8221 09:28:11.688815 DQM Delay:
8222 09:28:11.692007 DQM0 = 133, DQM1 = 123
8223 09:28:11.692434 DQ Delay:
8224 09:28:11.695260 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8225 09:28:11.698717 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8226 09:28:11.701931 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8227 09:28:11.705342 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8228 09:28:11.705770
8229 09:28:11.706145
8230 09:28:11.706467
8231 09:28:11.708978 [DramC_TX_OE_Calibration] TA2
8232 09:28:11.711751 Original DQ_B0 (3 6) =30, OEN = 27
8233 09:28:11.715088 Original DQ_B1 (3 6) =30, OEN = 27
8234 09:28:11.718638 24, 0x0, End_B0=24 End_B1=24
8235 09:28:11.721793 25, 0x0, End_B0=25 End_B1=25
8236 09:28:11.722222 26, 0x0, End_B0=26 End_B1=26
8237 09:28:11.725278 27, 0x0, End_B0=27 End_B1=27
8238 09:28:11.728795 28, 0x0, End_B0=28 End_B1=28
8239 09:28:11.732234 29, 0x0, End_B0=29 End_B1=29
8240 09:28:11.732666 30, 0x0, End_B0=30 End_B1=30
8241 09:28:11.735355 31, 0x4141, End_B0=30 End_B1=30
8242 09:28:11.738562 Byte0 end_step=30 best_step=27
8243 09:28:11.742022 Byte1 end_step=30 best_step=27
8244 09:28:11.745369 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 09:28:11.748575 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 09:28:11.749032
8247 09:28:11.749379
8248 09:28:11.755306 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8249 09:28:11.758452 CH0 RK1: MR19=303, MR18=210E
8250 09:28:11.765200 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8251 09:28:11.768383 [RxdqsGatingPostProcess] freq 1600
8252 09:28:11.775089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 09:28:11.775517 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 09:28:11.778672 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 09:28:11.781854 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 09:28:11.785086 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 09:28:11.788222 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 09:28:11.791961 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 09:28:11.795153 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 09:28:11.798253 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 09:28:11.801565 Pre-setting of DQS Precalculation
8262 09:28:11.804901 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 09:28:11.805372 ==
8264 09:28:11.808518 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 09:28:11.814957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 09:28:11.815388 ==
8267 09:28:11.818659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 09:28:11.825535 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 09:28:11.828795 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 09:28:11.835277 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 09:28:11.842167 [CA 0] Center 40 (11~70) winsize 60
8272 09:28:11.845667 [CA 1] Center 41 (11~71) winsize 61
8273 09:28:11.848957 [CA 2] Center 37 (8~67) winsize 60
8274 09:28:11.852221 [CA 3] Center 36 (7~66) winsize 60
8275 09:28:11.855830 [CA 4] Center 36 (7~66) winsize 60
8276 09:28:11.858857 [CA 5] Center 36 (6~66) winsize 61
8277 09:28:11.859289
8278 09:28:11.862420 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 09:28:11.862891
8280 09:28:11.865642 [CATrainingPosCal] consider 1 rank data
8281 09:28:11.868911 u2DelayCellTimex100 = 285/100 ps
8282 09:28:11.872811 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8283 09:28:11.879250 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8284 09:28:11.882267 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 09:28:11.885487 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 09:28:11.888907 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8287 09:28:11.892242 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8288 09:28:11.892679
8289 09:28:11.895446 CA PerBit enable=1, Macro0, CA PI delay=36
8290 09:28:11.895866
8291 09:28:11.899045 [CBTSetCACLKResult] CA Dly = 36
8292 09:28:11.899470 CS Dly: 9 (0~40)
8293 09:28:11.905620 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 09:28:11.908756 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 09:28:11.909204 ==
8296 09:28:11.912044 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 09:28:11.915438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 09:28:11.915863 ==
8299 09:28:11.922328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 09:28:11.925821 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 09:28:11.932380 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 09:28:11.935624 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 09:28:11.945728 [CA 0] Center 42 (12~72) winsize 61
8304 09:28:11.948751 [CA 1] Center 42 (12~72) winsize 61
8305 09:28:11.952147 [CA 2] Center 37 (8~67) winsize 60
8306 09:28:11.955653 [CA 3] Center 37 (8~66) winsize 59
8307 09:28:11.958860 [CA 4] Center 37 (8~67) winsize 60
8308 09:28:11.961926 [CA 5] Center 36 (7~66) winsize 60
8309 09:28:11.962344
8310 09:28:11.965202 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8311 09:28:11.965615
8312 09:28:11.968842 [CATrainingPosCal] consider 2 rank data
8313 09:28:11.972435 u2DelayCellTimex100 = 285/100 ps
8314 09:28:11.975297 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8315 09:28:11.981892 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8316 09:28:11.985156 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8317 09:28:11.988673 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8318 09:28:11.991881 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8319 09:28:11.995968 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8320 09:28:11.996481
8321 09:28:11.999114 CA PerBit enable=1, Macro0, CA PI delay=36
8322 09:28:11.999525
8323 09:28:12.002450 [CBTSetCACLKResult] CA Dly = 36
8324 09:28:12.002860 CS Dly: 10 (0~43)
8325 09:28:12.008832 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 09:28:12.012501 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 09:28:12.012917
8328 09:28:12.015200 ----->DramcWriteLeveling(PI) begin...
8329 09:28:12.015614 ==
8330 09:28:12.018897 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 09:28:12.021948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 09:28:12.022367 ==
8333 09:28:12.025336 Write leveling (Byte 0): 23 => 23
8334 09:28:12.028699 Write leveling (Byte 1): 30 => 30
8335 09:28:12.032083 DramcWriteLeveling(PI) end<-----
8336 09:28:12.032498
8337 09:28:12.032829 ==
8338 09:28:12.035418 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 09:28:12.041877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 09:28:12.042293 ==
8341 09:28:12.042624 [Gating] SW mode calibration
8342 09:28:12.052343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 09:28:12.055695 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 09:28:12.058985 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 09:28:12.065327 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 09:28:12.068564 1 4 8 | B1->B0 | 2727 3232 | 1 1 | (1 1) (1 1)
8347 09:28:12.071782 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8348 09:28:12.078165 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 09:28:12.081835 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 09:28:12.085015 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 09:28:12.091830 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 09:28:12.094755 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 09:28:12.098477 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8354 09:28:12.105215 1 5 8 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 0)
8355 09:28:12.108321 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8356 09:28:12.111563 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 09:28:12.118137 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 09:28:12.121496 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 09:28:12.124698 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 09:28:12.131500 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 09:28:12.134432 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8362 09:28:12.137945 1 6 8 | B1->B0 | 3333 4444 | 0 0 | (1 1) (0 0)
8363 09:28:12.144281 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8364 09:28:12.147885 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 09:28:12.151336 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 09:28:12.158145 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 09:28:12.161324 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 09:28:12.164809 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 09:28:12.171289 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8370 09:28:12.174636 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 09:28:12.177772 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 09:28:12.184445 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 09:28:12.188026 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 09:28:12.191444 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 09:28:12.198123 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 09:28:12.201106 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 09:28:12.204424 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 09:28:12.207679 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 09:28:12.214323 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 09:28:12.218038 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 09:28:12.221127 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 09:28:12.227637 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 09:28:12.231099 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 09:28:12.234302 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 09:28:12.240719 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8386 09:28:12.244155 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 09:28:12.247762 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 09:28:12.250707 Total UI for P1: 0, mck2ui 16
8389 09:28:12.254147 best dqsien dly found for B0: ( 1, 9, 6)
8390 09:28:12.257564 Total UI for P1: 0, mck2ui 16
8391 09:28:12.260913 best dqsien dly found for B1: ( 1, 9, 8)
8392 09:28:12.264557 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8393 09:28:12.267876 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8394 09:28:12.268317
8395 09:28:12.274647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8396 09:28:12.277475 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8397 09:28:12.277927 [Gating] SW calibration Done
8398 09:28:12.280798 ==
8399 09:28:12.284387 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 09:28:12.287355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 09:28:12.287852 ==
8402 09:28:12.288304 RX Vref Scan: 0
8403 09:28:12.288696
8404 09:28:12.290784 RX Vref 0 -> 0, step: 1
8405 09:28:12.291294
8406 09:28:12.294258 RX Delay 0 -> 252, step: 8
8407 09:28:12.297525 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8408 09:28:12.300829 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8409 09:28:12.304237 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8410 09:28:12.310547 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8411 09:28:12.314367 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8412 09:28:12.317651 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8413 09:28:12.321035 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8414 09:28:12.324329 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8415 09:28:12.327953 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8416 09:28:12.334055 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8417 09:28:12.337381 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8418 09:28:12.341300 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8419 09:28:12.344306 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8420 09:28:12.347346 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8421 09:28:12.354251 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8422 09:28:12.357624 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 09:28:12.358056 ==
8424 09:28:12.361360 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 09:28:12.363919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 09:28:12.364360 ==
8427 09:28:12.367151 DQS Delay:
8428 09:28:12.367581 DQS0 = 0, DQS1 = 0
8429 09:28:12.367927 DQM Delay:
8430 09:28:12.370724 DQM0 = 139, DQM1 = 130
8431 09:28:12.371154 DQ Delay:
8432 09:28:12.374022 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8433 09:28:12.377534 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8434 09:28:12.380995 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8435 09:28:12.387608 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8436 09:28:12.388039
8437 09:28:12.388382
8438 09:28:12.388697 ==
8439 09:28:12.391032 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 09:28:12.394041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 09:28:12.394477 ==
8442 09:28:12.394822
8443 09:28:12.395138
8444 09:28:12.397362 TX Vref Scan disable
8445 09:28:12.397791 == TX Byte 0 ==
8446 09:28:12.403907 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8447 09:28:12.407585 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8448 09:28:12.408020 == TX Byte 1 ==
8449 09:28:12.413984 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8450 09:28:12.417687 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8451 09:28:12.418253 ==
8452 09:28:12.420719 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 09:28:12.424321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 09:28:12.424846 ==
8455 09:28:12.439667
8456 09:28:12.442615 TX Vref early break, caculate TX vref
8457 09:28:12.446424 TX Vref=16, minBit 15, minWin=21, winSum=367
8458 09:28:12.449410 TX Vref=18, minBit 15, minWin=21, winSum=379
8459 09:28:12.452506 TX Vref=20, minBit 15, minWin=22, winSum=383
8460 09:28:12.455785 TX Vref=22, minBit 15, minWin=23, winSum=398
8461 09:28:12.462815 TX Vref=24, minBit 15, minWin=23, winSum=405
8462 09:28:12.465748 TX Vref=26, minBit 9, minWin=25, winSum=416
8463 09:28:12.469481 TX Vref=28, minBit 15, minWin=24, winSum=418
8464 09:28:12.472920 TX Vref=30, minBit 9, minWin=25, winSum=418
8465 09:28:12.475884 TX Vref=32, minBit 10, minWin=23, winSum=405
8466 09:28:12.478967 TX Vref=34, minBit 12, minWin=23, winSum=402
8467 09:28:12.485625 TX Vref=36, minBit 10, minWin=22, winSum=382
8468 09:28:12.489177 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 30
8469 09:28:12.489606
8470 09:28:12.492455 Final TX Range 0 Vref 30
8471 09:28:12.492886
8472 09:28:12.493274 ==
8473 09:28:12.495640 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 09:28:12.499273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 09:28:12.502322 ==
8476 09:28:12.502753
8477 09:28:12.503095
8478 09:28:12.503409 TX Vref Scan disable
8479 09:28:12.509627 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8480 09:28:12.510056 == TX Byte 0 ==
8481 09:28:12.513041 u2DelayCellOfst[0]=13 cells (4 PI)
8482 09:28:12.515994 u2DelayCellOfst[1]=10 cells (3 PI)
8483 09:28:12.519277 u2DelayCellOfst[2]=0 cells (0 PI)
8484 09:28:12.523034 u2DelayCellOfst[3]=3 cells (1 PI)
8485 09:28:12.526243 u2DelayCellOfst[4]=6 cells (2 PI)
8486 09:28:12.529208 u2DelayCellOfst[5]=17 cells (5 PI)
8487 09:28:12.532531 u2DelayCellOfst[6]=17 cells (5 PI)
8488 09:28:12.536028 u2DelayCellOfst[7]=6 cells (2 PI)
8489 09:28:12.539340 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8490 09:28:12.542565 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8491 09:28:12.546218 == TX Byte 1 ==
8492 09:28:12.549161 u2DelayCellOfst[8]=0 cells (0 PI)
8493 09:28:12.552658 u2DelayCellOfst[9]=3 cells (1 PI)
8494 09:28:12.556213 u2DelayCellOfst[10]=10 cells (3 PI)
8495 09:28:12.556641 u2DelayCellOfst[11]=3 cells (1 PI)
8496 09:28:12.559608 u2DelayCellOfst[12]=17 cells (5 PI)
8497 09:28:12.562592 u2DelayCellOfst[13]=13 cells (4 PI)
8498 09:28:12.565819 u2DelayCellOfst[14]=17 cells (5 PI)
8499 09:28:12.569508 u2DelayCellOfst[15]=13 cells (4 PI)
8500 09:28:12.576243 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8501 09:28:12.579456 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8502 09:28:12.579981 DramC Write-DBI on
8503 09:28:12.580324 ==
8504 09:28:12.582617 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 09:28:12.589608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 09:28:12.590133 ==
8507 09:28:12.590479
8508 09:28:12.590790
8509 09:28:12.591094 TX Vref Scan disable
8510 09:28:12.593351 == TX Byte 0 ==
8511 09:28:12.597095 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8512 09:28:12.600365 == TX Byte 1 ==
8513 09:28:12.603460 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8514 09:28:12.606654 DramC Write-DBI off
8515 09:28:12.607237
8516 09:28:12.607596 [DATLAT]
8517 09:28:12.607916 Freq=1600, CH1 RK0
8518 09:28:12.608229
8519 09:28:12.609870 DATLAT Default: 0xf
8520 09:28:12.613130 0, 0xFFFF, sum = 0
8521 09:28:12.613559 1, 0xFFFF, sum = 0
8522 09:28:12.616503 2, 0xFFFF, sum = 0
8523 09:28:12.617098 3, 0xFFFF, sum = 0
8524 09:28:12.620075 4, 0xFFFF, sum = 0
8525 09:28:12.620600 5, 0xFFFF, sum = 0
8526 09:28:12.622807 6, 0xFFFF, sum = 0
8527 09:28:12.623239 7, 0xFFFF, sum = 0
8528 09:28:12.626316 8, 0xFFFF, sum = 0
8529 09:28:12.626746 9, 0xFFFF, sum = 0
8530 09:28:12.629802 10, 0xFFFF, sum = 0
8531 09:28:12.630325 11, 0xFFFF, sum = 0
8532 09:28:12.633676 12, 0xFFFF, sum = 0
8533 09:28:12.634207 13, 0xFFFF, sum = 0
8534 09:28:12.636209 14, 0x0, sum = 1
8535 09:28:12.636636 15, 0x0, sum = 2
8536 09:28:12.639478 16, 0x0, sum = 3
8537 09:28:12.639904 17, 0x0, sum = 4
8538 09:28:12.642979 best_step = 15
8539 09:28:12.643440
8540 09:28:12.643780 ==
8541 09:28:12.646119 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 09:28:12.649389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 09:28:12.649815 ==
8544 09:28:12.652994 RX Vref Scan: 1
8545 09:28:12.653523
8546 09:28:12.653865 Set Vref Range= 24 -> 127
8547 09:28:12.654185
8548 09:28:12.656235 RX Vref 24 -> 127, step: 1
8549 09:28:12.656659
8550 09:28:12.659508 RX Delay 19 -> 252, step: 4
8551 09:28:12.660033
8552 09:28:12.662883 Set Vref, RX VrefLevel [Byte0]: 24
8553 09:28:12.666002 [Byte1]: 24
8554 09:28:12.666443
8555 09:28:12.669829 Set Vref, RX VrefLevel [Byte0]: 25
8556 09:28:12.672572 [Byte1]: 25
8557 09:28:12.676129
8558 09:28:12.676653 Set Vref, RX VrefLevel [Byte0]: 26
8559 09:28:12.679670 [Byte1]: 26
8560 09:28:12.683483
8561 09:28:12.684074 Set Vref, RX VrefLevel [Byte0]: 27
8562 09:28:12.687072 [Byte1]: 27
8563 09:28:12.690909
8564 09:28:12.691471 Set Vref, RX VrefLevel [Byte0]: 28
8565 09:28:12.694420 [Byte1]: 28
8566 09:28:12.698645
8567 09:28:12.699118 Set Vref, RX VrefLevel [Byte0]: 29
8568 09:28:12.705296 [Byte1]: 29
8569 09:28:12.705718
8570 09:28:12.708508 Set Vref, RX VrefLevel [Byte0]: 30
8571 09:28:12.711982 [Byte1]: 30
8572 09:28:12.712490
8573 09:28:12.715331 Set Vref, RX VrefLevel [Byte0]: 31
8574 09:28:12.718723 [Byte1]: 31
8575 09:28:12.719308
8576 09:28:12.722026 Set Vref, RX VrefLevel [Byte0]: 32
8577 09:28:12.724896 [Byte1]: 32
8578 09:28:12.728705
8579 09:28:12.729156 Set Vref, RX VrefLevel [Byte0]: 33
8580 09:28:12.732110 [Byte1]: 33
8581 09:28:12.737046
8582 09:28:12.737582 Set Vref, RX VrefLevel [Byte0]: 34
8583 09:28:12.740034 [Byte1]: 34
8584 09:28:12.744576
8585 09:28:12.745054 Set Vref, RX VrefLevel [Byte0]: 35
8586 09:28:12.747703 [Byte1]: 35
8587 09:28:12.751469
8588 09:28:12.751899 Set Vref, RX VrefLevel [Byte0]: 36
8589 09:28:12.755059 [Byte1]: 36
8590 09:28:12.758999
8591 09:28:12.759429 Set Vref, RX VrefLevel [Byte0]: 37
8592 09:28:12.762380 [Byte1]: 37
8593 09:28:12.766789
8594 09:28:12.767277 Set Vref, RX VrefLevel [Byte0]: 38
8595 09:28:12.770579 [Byte1]: 38
8596 09:28:12.774458
8597 09:28:12.774952 Set Vref, RX VrefLevel [Byte0]: 39
8598 09:28:12.777743 [Byte1]: 39
8599 09:28:12.781917
8600 09:28:12.782344 Set Vref, RX VrefLevel [Byte0]: 40
8601 09:28:12.785444 [Byte1]: 40
8602 09:28:12.789388
8603 09:28:12.789988 Set Vref, RX VrefLevel [Byte0]: 41
8604 09:28:12.793036 [Byte1]: 41
8605 09:28:12.796904
8606 09:28:12.797481 Set Vref, RX VrefLevel [Byte0]: 42
8607 09:28:12.800558 [Byte1]: 42
8608 09:28:12.804739
8609 09:28:12.805380 Set Vref, RX VrefLevel [Byte0]: 43
8610 09:28:12.807833 [Byte1]: 43
8611 09:28:12.811924
8612 09:28:12.812482 Set Vref, RX VrefLevel [Byte0]: 44
8613 09:28:12.815259 [Byte1]: 44
8614 09:28:12.819710
8615 09:28:12.820310 Set Vref, RX VrefLevel [Byte0]: 45
8616 09:28:12.822929 [Byte1]: 45
8617 09:28:12.827546
8618 09:28:12.828164 Set Vref, RX VrefLevel [Byte0]: 46
8619 09:28:12.830879 [Byte1]: 46
8620 09:28:12.834926
8621 09:28:12.835423 Set Vref, RX VrefLevel [Byte0]: 47
8622 09:28:12.838560 [Byte1]: 47
8623 09:28:12.842289
8624 09:28:12.842870 Set Vref, RX VrefLevel [Byte0]: 48
8625 09:28:12.845891 [Byte1]: 48
8626 09:28:12.850344
8627 09:28:12.850915 Set Vref, RX VrefLevel [Byte0]: 49
8628 09:28:12.853606 [Byte1]: 49
8629 09:28:12.857647
8630 09:28:12.858302 Set Vref, RX VrefLevel [Byte0]: 50
8631 09:28:12.860821 [Byte1]: 50
8632 09:28:12.865177
8633 09:28:12.865261 Set Vref, RX VrefLevel [Byte0]: 51
8634 09:28:12.868040 [Byte1]: 51
8635 09:28:12.872484
8636 09:28:12.872600 Set Vref, RX VrefLevel [Byte0]: 52
8637 09:28:12.876139 [Byte1]: 52
8638 09:28:12.880030
8639 09:28:12.880143 Set Vref, RX VrefLevel [Byte0]: 53
8640 09:28:12.883616 [Byte1]: 53
8641 09:28:12.887755
8642 09:28:12.887921 Set Vref, RX VrefLevel [Byte0]: 54
8643 09:28:12.891174 [Byte1]: 54
8644 09:28:12.895218
8645 09:28:12.895396 Set Vref, RX VrefLevel [Byte0]: 55
8646 09:28:12.898541 [Byte1]: 55
8647 09:28:12.902956
8648 09:28:12.903072 Set Vref, RX VrefLevel [Byte0]: 56
8649 09:28:12.906011 [Byte1]: 56
8650 09:28:12.910139
8651 09:28:12.910255 Set Vref, RX VrefLevel [Byte0]: 57
8652 09:28:12.913833 [Byte1]: 57
8653 09:28:12.918080
8654 09:28:12.918194 Set Vref, RX VrefLevel [Byte0]: 58
8655 09:28:12.921339 [Byte1]: 58
8656 09:28:12.925764
8657 09:28:12.925848 Set Vref, RX VrefLevel [Byte0]: 59
8658 09:28:12.928997 [Byte1]: 59
8659 09:28:12.932804
8660 09:28:12.932888 Set Vref, RX VrefLevel [Byte0]: 60
8661 09:28:12.936524 [Byte1]: 60
8662 09:28:12.940665
8663 09:28:12.940749 Set Vref, RX VrefLevel [Byte0]: 61
8664 09:28:12.943763 [Byte1]: 61
8665 09:28:12.947989
8666 09:28:12.948072 Set Vref, RX VrefLevel [Byte0]: 62
8667 09:28:12.951483 [Byte1]: 62
8668 09:28:12.955782
8669 09:28:12.955897 Set Vref, RX VrefLevel [Byte0]: 63
8670 09:28:12.958979 [Byte1]: 63
8671 09:28:12.963343
8672 09:28:12.963420 Set Vref, RX VrefLevel [Byte0]: 64
8673 09:28:12.966825 [Byte1]: 64
8674 09:28:12.970947
8675 09:28:12.971023 Set Vref, RX VrefLevel [Byte0]: 65
8676 09:28:12.974408 [Byte1]: 65
8677 09:28:12.978488
8678 09:28:12.978563 Set Vref, RX VrefLevel [Byte0]: 66
8679 09:28:12.982163 [Byte1]: 66
8680 09:28:12.986069
8681 09:28:12.986144 Set Vref, RX VrefLevel [Byte0]: 67
8682 09:28:12.989417 [Byte1]: 67
8683 09:28:12.993880
8684 09:28:12.993955 Set Vref, RX VrefLevel [Byte0]: 68
8685 09:28:12.996875 [Byte1]: 68
8686 09:28:13.001263
8687 09:28:13.001338 Set Vref, RX VrefLevel [Byte0]: 69
8688 09:28:13.004392 [Byte1]: 69
8689 09:28:13.008867
8690 09:28:13.009000 Set Vref, RX VrefLevel [Byte0]: 70
8691 09:28:13.012135 [Byte1]: 70
8692 09:28:13.016354
8693 09:28:13.016432 Set Vref, RX VrefLevel [Byte0]: 71
8694 09:28:13.019877 [Byte1]: 71
8695 09:28:13.024056
8696 09:28:13.024131 Set Vref, RX VrefLevel [Byte0]: 72
8697 09:28:13.027165 [Byte1]: 72
8698 09:28:13.031621
8699 09:28:13.031711 Set Vref, RX VrefLevel [Byte0]: 73
8700 09:28:13.034980 [Byte1]: 73
8701 09:28:13.039227
8702 09:28:13.039302 Set Vref, RX VrefLevel [Byte0]: 74
8703 09:28:13.042558 [Byte1]: 74
8704 09:28:13.046492
8705 09:28:13.046576 Final RX Vref Byte 0 = 60 to rank0
8706 09:28:13.049873 Final RX Vref Byte 1 = 62 to rank0
8707 09:28:13.053330 Final RX Vref Byte 0 = 60 to rank1
8708 09:28:13.056452 Final RX Vref Byte 1 = 62 to rank1==
8709 09:28:13.060080 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 09:28:13.066656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 09:28:13.066763 ==
8712 09:28:13.066857 DQS Delay:
8713 09:28:13.066947 DQS0 = 0, DQS1 = 0
8714 09:28:13.070095 DQM Delay:
8715 09:28:13.070174 DQM0 = 135, DQM1 = 128
8716 09:28:13.073017 DQ Delay:
8717 09:28:13.076462 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8718 09:28:13.080241 DQ4 =132, DQ5 =146, DQ6 =148, DQ7 =132
8719 09:28:13.083190 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8720 09:28:13.086693 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8721 09:28:13.086794
8722 09:28:13.086868
8723 09:28:13.086950
8724 09:28:13.089624 [DramC_TX_OE_Calibration] TA2
8725 09:28:13.093419 Original DQ_B0 (3 6) =30, OEN = 27
8726 09:28:13.096836 Original DQ_B1 (3 6) =30, OEN = 27
8727 09:28:13.100049 24, 0x0, End_B0=24 End_B1=24
8728 09:28:13.100161 25, 0x0, End_B0=25 End_B1=25
8729 09:28:13.103421 26, 0x0, End_B0=26 End_B1=26
8730 09:28:13.106851 27, 0x0, End_B0=27 End_B1=27
8731 09:28:13.109859 28, 0x0, End_B0=28 End_B1=28
8732 09:28:13.109970 29, 0x0, End_B0=29 End_B1=29
8733 09:28:13.113190 30, 0x0, End_B0=30 End_B1=30
8734 09:28:13.116678 31, 0x4141, End_B0=30 End_B1=30
8735 09:28:13.119884 Byte0 end_step=30 best_step=27
8736 09:28:13.123443 Byte1 end_step=30 best_step=27
8737 09:28:13.126600 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 09:28:13.126739 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 09:28:13.130196
8740 09:28:13.130616
8741 09:28:13.137193 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a29, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8742 09:28:13.140543 CH1 RK0: MR19=303, MR18=1A29
8743 09:28:13.147075 CH1_RK0: MR19=0x303, MR18=0x1A29, DQSOSC=389, MR23=63, INC=24, DEC=16
8744 09:28:13.147514
8745 09:28:13.150454 ----->DramcWriteLeveling(PI) begin...
8746 09:28:13.150924 ==
8747 09:28:13.153788 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 09:28:13.156976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 09:28:13.157531 ==
8750 09:28:13.160216 Write leveling (Byte 0): 23 => 23
8751 09:28:13.163603 Write leveling (Byte 1): 30 => 30
8752 09:28:13.166950 DramcWriteLeveling(PI) end<-----
8753 09:28:13.167371
8754 09:28:13.167701 ==
8755 09:28:13.170276 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 09:28:13.173501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 09:28:13.173923 ==
8758 09:28:13.177211 [Gating] SW mode calibration
8759 09:28:13.183590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 09:28:13.190203 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 09:28:13.193464 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 09:28:13.196734 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 09:28:13.203807 1 4 8 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
8764 09:28:13.206805 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8765 09:28:13.209987 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 09:28:13.217073 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 09:28:13.220087 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 09:28:13.223690 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 09:28:13.230137 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 09:28:13.233720 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 09:28:13.237165 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8772 09:28:13.243598 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (1 0) (0 1)
8773 09:28:13.247387 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8774 09:28:13.250171 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 09:28:13.257129 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 09:28:13.260197 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 09:28:13.263661 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 09:28:13.269703 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 09:28:13.273073 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
8780 09:28:13.276737 1 6 12 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
8781 09:28:13.283223 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 09:28:13.286496 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 09:28:13.289616 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 09:28:13.293339 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 09:28:13.299609 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 09:28:13.303070 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 09:28:13.309806 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8788 09:28:13.313085 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 09:28:13.316737 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 09:28:13.319606 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 09:28:13.326286 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 09:28:13.329446 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 09:28:13.336009 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 09:28:13.339451 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 09:28:13.342829 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 09:28:13.346245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 09:28:13.352667 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 09:28:13.356035 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 09:28:13.359122 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 09:28:13.365683 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 09:28:13.369084 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 09:28:13.372270 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8803 09:28:13.378721 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8804 09:28:13.382007 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8805 09:28:13.385429 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 09:28:13.388727 Total UI for P1: 0, mck2ui 16
8807 09:28:13.392184 best dqsien dly found for B0: ( 1, 9, 8)
8808 09:28:13.395099 Total UI for P1: 0, mck2ui 16
8809 09:28:13.398817 best dqsien dly found for B1: ( 1, 9, 10)
8810 09:28:13.401947 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8811 09:28:13.408543 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8812 09:28:13.409124
8813 09:28:13.411960 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8814 09:28:13.415452 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8815 09:28:13.418552 [Gating] SW calibration Done
8816 09:28:13.418974 ==
8817 09:28:13.421685 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 09:28:13.425076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 09:28:13.425604 ==
8820 09:28:13.428733 RX Vref Scan: 0
8821 09:28:13.429291
8822 09:28:13.429640 RX Vref 0 -> 0, step: 1
8823 09:28:13.429957
8824 09:28:13.432056 RX Delay 0 -> 252, step: 8
8825 09:28:13.435182 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8826 09:28:13.438475 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8827 09:28:13.444836 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8828 09:28:13.448467 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8829 09:28:13.451997 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8830 09:28:13.454696 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8831 09:28:13.458397 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8832 09:28:13.464758 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8833 09:28:13.468033 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8834 09:28:13.471357 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8835 09:28:13.474693 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8836 09:28:13.478297 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8837 09:28:13.484773 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8838 09:28:13.488102 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8839 09:28:13.491154 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8840 09:28:13.494433 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8841 09:28:13.494901 ==
8842 09:28:13.497734 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 09:28:13.504408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 09:28:13.504840 ==
8845 09:28:13.505232 DQS Delay:
8846 09:28:13.505556 DQS0 = 0, DQS1 = 0
8847 09:28:13.507996 DQM Delay:
8848 09:28:13.508441 DQM0 = 139, DQM1 = 132
8849 09:28:13.511278 DQ Delay:
8850 09:28:13.514541 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8851 09:28:13.517694 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =139
8852 09:28:13.521043 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8853 09:28:13.524541 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =139
8854 09:28:13.525111
8855 09:28:13.525505
8856 09:28:13.525857 ==
8857 09:28:13.528110 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 09:28:13.531138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 09:28:13.534523 ==
8860 09:28:13.534987
8861 09:28:13.535380
8862 09:28:13.535713 TX Vref Scan disable
8863 09:28:13.537643 == TX Byte 0 ==
8864 09:28:13.541232 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8865 09:28:13.544619 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8866 09:28:13.548012 == TX Byte 1 ==
8867 09:28:13.550944 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8868 09:28:13.554299 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8869 09:28:13.557794 ==
8870 09:28:13.558226 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 09:28:13.564203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 09:28:13.564632 ==
8873 09:28:13.576443
8874 09:28:13.579660 TX Vref early break, caculate TX vref
8875 09:28:13.583227 TX Vref=16, minBit 9, minWin=22, winSum=378
8876 09:28:13.586798 TX Vref=18, minBit 13, minWin=22, winSum=388
8877 09:28:13.590021 TX Vref=20, minBit 15, minWin=23, winSum=399
8878 09:28:13.593278 TX Vref=22, minBit 9, minWin=24, winSum=408
8879 09:28:13.596653 TX Vref=24, minBit 9, minWin=24, winSum=414
8880 09:28:13.603386 TX Vref=26, minBit 9, minWin=24, winSum=420
8881 09:28:13.606754 TX Vref=28, minBit 14, minWin=25, winSum=423
8882 09:28:13.609846 TX Vref=30, minBit 10, minWin=24, winSum=417
8883 09:28:13.613536 TX Vref=32, minBit 10, minWin=23, winSum=408
8884 09:28:13.616655 TX Vref=34, minBit 9, minWin=24, winSum=400
8885 09:28:13.623371 [TxChooseVref] Worse bit 14, Min win 25, Win sum 423, Final Vref 28
8886 09:28:13.623918
8887 09:28:13.626448 Final TX Range 0 Vref 28
8888 09:28:13.626879
8889 09:28:13.627226 ==
8890 09:28:13.629851 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 09:28:13.633135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 09:28:13.633446 ==
8893 09:28:13.633513
8894 09:28:13.633574
8895 09:28:13.636168 TX Vref Scan disable
8896 09:28:13.642861 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8897 09:28:13.642945 == TX Byte 0 ==
8898 09:28:13.646413 u2DelayCellOfst[0]=17 cells (5 PI)
8899 09:28:13.649666 u2DelayCellOfst[1]=13 cells (4 PI)
8900 09:28:13.652890 u2DelayCellOfst[2]=0 cells (0 PI)
8901 09:28:13.656251 u2DelayCellOfst[3]=6 cells (2 PI)
8902 09:28:13.659784 u2DelayCellOfst[4]=10 cells (3 PI)
8903 09:28:13.662666 u2DelayCellOfst[5]=20 cells (6 PI)
8904 09:28:13.666037 u2DelayCellOfst[6]=17 cells (5 PI)
8905 09:28:13.669442 u2DelayCellOfst[7]=6 cells (2 PI)
8906 09:28:13.672693 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8907 09:28:13.676050 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8908 09:28:13.679282 == TX Byte 1 ==
8909 09:28:13.682606 u2DelayCellOfst[8]=0 cells (0 PI)
8910 09:28:13.682714 u2DelayCellOfst[9]=3 cells (1 PI)
8911 09:28:13.686148 u2DelayCellOfst[10]=10 cells (3 PI)
8912 09:28:13.689353 u2DelayCellOfst[11]=3 cells (1 PI)
8913 09:28:13.692316 u2DelayCellOfst[12]=13 cells (4 PI)
8914 09:28:13.695636 u2DelayCellOfst[13]=13 cells (4 PI)
8915 09:28:13.699065 u2DelayCellOfst[14]=17 cells (5 PI)
8916 09:28:13.702546 u2DelayCellOfst[15]=17 cells (5 PI)
8917 09:28:13.705813 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8918 09:28:13.712762 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8919 09:28:13.713041 DramC Write-DBI on
8920 09:28:13.713379 ==
8921 09:28:13.715970 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 09:28:13.722796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 09:28:13.723230 ==
8924 09:28:13.723624
8925 09:28:13.723945
8926 09:28:13.724323 TX Vref Scan disable
8927 09:28:13.726719 == TX Byte 0 ==
8928 09:28:13.729886 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8929 09:28:13.733144 == TX Byte 1 ==
8930 09:28:13.736489 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8931 09:28:13.739936 DramC Write-DBI off
8932 09:28:13.740363
8933 09:28:13.740746 [DATLAT]
8934 09:28:13.741131 Freq=1600, CH1 RK1
8935 09:28:13.741500
8936 09:28:13.742844 DATLAT Default: 0xf
8937 09:28:13.743230 0, 0xFFFF, sum = 0
8938 09:28:13.746484 1, 0xFFFF, sum = 0
8939 09:28:13.746928 2, 0xFFFF, sum = 0
8940 09:28:13.749765 3, 0xFFFF, sum = 0
8941 09:28:13.752965 4, 0xFFFF, sum = 0
8942 09:28:13.753394 5, 0xFFFF, sum = 0
8943 09:28:13.756359 6, 0xFFFF, sum = 0
8944 09:28:13.756769 7, 0xFFFF, sum = 0
8945 09:28:13.759783 8, 0xFFFF, sum = 0
8946 09:28:13.760199 9, 0xFFFF, sum = 0
8947 09:28:13.763228 10, 0xFFFF, sum = 0
8948 09:28:13.763553 11, 0xFFFF, sum = 0
8949 09:28:13.766330 12, 0xFFFF, sum = 0
8950 09:28:13.766738 13, 0xFFFF, sum = 0
8951 09:28:13.769674 14, 0x0, sum = 1
8952 09:28:13.770077 15, 0x0, sum = 2
8953 09:28:13.772839 16, 0x0, sum = 3
8954 09:28:13.773169 17, 0x0, sum = 4
8955 09:28:13.776129 best_step = 15
8956 09:28:13.776433
8957 09:28:13.776675 ==
8958 09:28:13.779747 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 09:28:13.783218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 09:28:13.783539 ==
8961 09:28:13.783787 RX Vref Scan: 0
8962 09:28:13.786708
8963 09:28:13.787083 RX Vref 0 -> 0, step: 1
8964 09:28:13.787415
8965 09:28:13.789690 RX Delay 19 -> 252, step: 4
8966 09:28:13.793303 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8967 09:28:13.799973 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8968 09:28:13.803035 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8969 09:28:13.806641 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8970 09:28:13.810271 iDelay=195, Bit 4, Center 136 (91 ~ 182) 92
8971 09:28:13.813208 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8972 09:28:13.816866 iDelay=195, Bit 6, Center 146 (99 ~ 194) 96
8973 09:28:13.823653 iDelay=195, Bit 7, Center 134 (87 ~ 182) 96
8974 09:28:13.826775 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8975 09:28:13.829925 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8976 09:28:13.833244 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8977 09:28:13.836593 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8978 09:28:13.843222 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8979 09:28:13.846369 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8980 09:28:13.849869 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8981 09:28:13.852859 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8982 09:28:13.852965 ==
8983 09:28:13.856217 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 09:28:13.862679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 09:28:13.862763 ==
8986 09:28:13.862830 DQS Delay:
8987 09:28:13.862891 DQS0 = 0, DQS1 = 0
8988 09:28:13.866182 DQM Delay:
8989 09:28:13.866267 DQM0 = 135, DQM1 = 129
8990 09:28:13.869557 DQ Delay:
8991 09:28:13.872905 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8992 09:28:13.876265 DQ4 =136, DQ5 =144, DQ6 =146, DQ7 =134
8993 09:28:13.879584 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8994 09:28:13.882977 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8995 09:28:13.883128
8996 09:28:13.883220
8997 09:28:13.883316
8998 09:28:13.886342 [DramC_TX_OE_Calibration] TA2
8999 09:28:13.889604 Original DQ_B0 (3 6) =30, OEN = 27
9000 09:28:13.892522 Original DQ_B1 (3 6) =30, OEN = 27
9001 09:28:13.896153 24, 0x0, End_B0=24 End_B1=24
9002 09:28:13.896321 25, 0x0, End_B0=25 End_B1=25
9003 09:28:13.899277 26, 0x0, End_B0=26 End_B1=26
9004 09:28:13.902829 27, 0x0, End_B0=27 End_B1=27
9005 09:28:13.906296 28, 0x0, End_B0=28 End_B1=28
9006 09:28:13.906473 29, 0x0, End_B0=29 End_B1=29
9007 09:28:13.909255 30, 0x0, End_B0=30 End_B1=30
9008 09:28:13.912523 31, 0x4141, End_B0=30 End_B1=30
9009 09:28:13.916351 Byte0 end_step=30 best_step=27
9010 09:28:13.919580 Byte1 end_step=30 best_step=27
9011 09:28:13.922501 Byte0 TX OE(2T, 0.5T) = (3, 3)
9012 09:28:13.922615 Byte1 TX OE(2T, 0.5T) = (3, 3)
9013 09:28:13.925847
9014 09:28:13.925949
9015 09:28:13.932264 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9016 09:28:13.935535 CH1 RK1: MR19=303, MR18=1B07
9017 09:28:13.942533 CH1_RK1: MR19=0x303, MR18=0x1B07, DQSOSC=396, MR23=63, INC=23, DEC=15
9018 09:28:13.945947 [RxdqsGatingPostProcess] freq 1600
9019 09:28:13.949211 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9020 09:28:13.952567 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 09:28:13.955795 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 09:28:13.958820 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 09:28:13.962378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 09:28:13.965543 best DQS0 dly(2T, 0.5T) = (1, 1)
9025 09:28:13.968926 best DQS1 dly(2T, 0.5T) = (1, 1)
9026 09:28:13.972404 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9027 09:28:13.975542 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9028 09:28:13.979019 Pre-setting of DQS Precalculation
9029 09:28:13.982340 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9030 09:28:13.988863 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9031 09:28:13.995939 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9032 09:28:13.996150
9033 09:28:13.999363
9034 09:28:13.999596 [Calibration Summary] 3200 Mbps
9035 09:28:14.002529 CH 0, Rank 0
9036 09:28:14.002761 SW Impedance : PASS
9037 09:28:14.006219 DUTY Scan : NO K
9038 09:28:14.009012 ZQ Calibration : PASS
9039 09:28:14.009276 Jitter Meter : NO K
9040 09:28:14.012495 CBT Training : PASS
9041 09:28:14.015902 Write leveling : PASS
9042 09:28:14.016231 RX DQS gating : PASS
9043 09:28:14.019701 RX DQ/DQS(RDDQC) : PASS
9044 09:28:14.022470 TX DQ/DQS : PASS
9045 09:28:14.022888 RX DATLAT : PASS
9046 09:28:14.025591 RX DQ/DQS(Engine): PASS
9047 09:28:14.029444 TX OE : PASS
9048 09:28:14.029967 All Pass.
9049 09:28:14.030310
9050 09:28:14.030676 CH 0, Rank 1
9051 09:28:14.032268 SW Impedance : PASS
9052 09:28:14.036194 DUTY Scan : NO K
9053 09:28:14.036715 ZQ Calibration : PASS
9054 09:28:14.039076 Jitter Meter : NO K
9055 09:28:14.039692 CBT Training : PASS
9056 09:28:14.042396 Write leveling : PASS
9057 09:28:14.045732 RX DQS gating : PASS
9058 09:28:14.046184 RX DQ/DQS(RDDQC) : PASS
9059 09:28:14.049305 TX DQ/DQS : PASS
9060 09:28:14.052545 RX DATLAT : PASS
9061 09:28:14.052990 RX DQ/DQS(Engine): PASS
9062 09:28:14.055814 TX OE : PASS
9063 09:28:14.056237 All Pass.
9064 09:28:14.056572
9065 09:28:14.059271 CH 1, Rank 0
9066 09:28:14.059691 SW Impedance : PASS
9067 09:28:14.062673 DUTY Scan : NO K
9068 09:28:14.065855 ZQ Calibration : PASS
9069 09:28:14.066330 Jitter Meter : NO K
9070 09:28:14.069309 CBT Training : PASS
9071 09:28:14.072592 Write leveling : PASS
9072 09:28:14.073055 RX DQS gating : PASS
9073 09:28:14.076318 RX DQ/DQS(RDDQC) : PASS
9074 09:28:14.076846 TX DQ/DQS : PASS
9075 09:28:14.079683 RX DATLAT : PASS
9076 09:28:14.082407 RX DQ/DQS(Engine): PASS
9077 09:28:14.082830 TX OE : PASS
9078 09:28:14.085691 All Pass.
9079 09:28:14.086111
9080 09:28:14.086446 CH 1, Rank 1
9081 09:28:14.089037 SW Impedance : PASS
9082 09:28:14.089633 DUTY Scan : NO K
9083 09:28:14.092452 ZQ Calibration : PASS
9084 09:28:14.095726 Jitter Meter : NO K
9085 09:28:14.096145 CBT Training : PASS
9086 09:28:14.098990 Write leveling : PASS
9087 09:28:14.102305 RX DQS gating : PASS
9088 09:28:14.102877 RX DQ/DQS(RDDQC) : PASS
9089 09:28:14.105524 TX DQ/DQS : PASS
9090 09:28:14.108845 RX DATLAT : PASS
9091 09:28:14.109475 RX DQ/DQS(Engine): PASS
9092 09:28:14.112297 TX OE : PASS
9093 09:28:14.112821 All Pass.
9094 09:28:14.113212
9095 09:28:14.115966 DramC Write-DBI on
9096 09:28:14.118994 PER_BANK_REFRESH: Hybrid Mode
9097 09:28:14.119511 TX_TRACKING: ON
9098 09:28:14.129059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9099 09:28:14.135519 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9100 09:28:14.142269 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 09:28:14.148369 [FAST_K] Save calibration result to emmc
9102 09:28:14.148806 sync common calibartion params.
9103 09:28:14.151696 sync cbt_mode0:1, 1:1
9104 09:28:14.155093 dram_init: ddr_geometry: 2
9105 09:28:14.155772 dram_init: ddr_geometry: 2
9106 09:28:14.158008 dram_init: ddr_geometry: 2
9107 09:28:14.161736 0:dram_rank_size:100000000
9108 09:28:14.164832 1:dram_rank_size:100000000
9109 09:28:14.168572 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9110 09:28:14.171831 DFS_SHUFFLE_HW_MODE: ON
9111 09:28:14.174897 dramc_set_vcore_voltage set vcore to 725000
9112 09:28:14.178531 Read voltage for 1600, 0
9113 09:28:14.179057 Vio18 = 0
9114 09:28:14.179396 Vcore = 725000
9115 09:28:14.181860 Vdram = 0
9116 09:28:14.182387 Vddq = 0
9117 09:28:14.182731 Vmddr = 0
9118 09:28:14.185087 switch to 3200 Mbps bootup
9119 09:28:14.188424 [DramcRunTimeConfig]
9120 09:28:14.189049 PHYPLL
9121 09:28:14.189404 DPM_CONTROL_AFTERK: ON
9122 09:28:14.191414 PER_BANK_REFRESH: ON
9123 09:28:14.194903 REFRESH_OVERHEAD_REDUCTION: ON
9124 09:28:14.195327 CMD_PICG_NEW_MODE: OFF
9125 09:28:14.198184 XRTWTW_NEW_MODE: ON
9126 09:28:14.201623 XRTRTR_NEW_MODE: ON
9127 09:28:14.202047 TX_TRACKING: ON
9128 09:28:14.205364 RDSEL_TRACKING: OFF
9129 09:28:14.205895 DQS Precalculation for DVFS: ON
9130 09:28:14.208567 RX_TRACKING: OFF
9131 09:28:14.209050 HW_GATING DBG: ON
9132 09:28:14.211961 ZQCS_ENABLE_LP4: ON
9133 09:28:14.212496 RX_PICG_NEW_MODE: ON
9134 09:28:14.215226 TX_PICG_NEW_MODE: ON
9135 09:28:14.218692 ENABLE_RX_DCM_DPHY: ON
9136 09:28:14.222172 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9137 09:28:14.222746 DUMMY_READ_FOR_TRACKING: OFF
9138 09:28:14.225061 !!! SPM_CONTROL_AFTERK: OFF
9139 09:28:14.228553 !!! SPM could not control APHY
9140 09:28:14.231783 IMPEDANCE_TRACKING: ON
9141 09:28:14.232415 TEMP_SENSOR: ON
9142 09:28:14.235725 HW_SAVE_FOR_SR: OFF
9143 09:28:14.236303 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9144 09:28:14.241736 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9145 09:28:14.242225 Read ODT Tracking: ON
9146 09:28:14.244691 Refresh Rate DeBounce: ON
9147 09:28:14.245295 DFS_NO_QUEUE_FLUSH: ON
9148 09:28:14.248681 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9149 09:28:14.251698 ENABLE_DFS_RUNTIME_MRW: OFF
9150 09:28:14.255218 DDR_RESERVE_NEW_MODE: ON
9151 09:28:14.258542 MR_CBT_SWITCH_FREQ: ON
9152 09:28:14.259118 =========================
9153 09:28:14.277910 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9154 09:28:14.281179 dram_init: ddr_geometry: 2
9155 09:28:14.299096 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9156 09:28:14.302736 dram_init: dram init end (result: 0)
9157 09:28:14.309589 DRAM-K: Full calibration passed in 24474 msecs
9158 09:28:14.313117 MRC: failed to locate region type 0.
9159 09:28:14.313678 DRAM rank0 size:0x100000000,
9160 09:28:14.315794 DRAM rank1 size=0x100000000
9161 09:28:14.325654 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9162 09:28:14.332505 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9163 09:28:14.339367 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9164 09:28:14.345778 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9165 09:28:14.349184 DRAM rank0 size:0x100000000,
9166 09:28:14.352239 DRAM rank1 size=0x100000000
9167 09:28:14.352812 CBMEM:
9168 09:28:14.355797 IMD: root @ 0xfffff000 254 entries.
9169 09:28:14.359387 IMD: root @ 0xffffec00 62 entries.
9170 09:28:14.362348 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9171 09:28:14.365728 WARNING: RO_VPD is uninitialized or empty.
9172 09:28:14.372321 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9173 09:28:14.379524 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9174 09:28:14.391782 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9175 09:28:14.403849 BS: romstage times (exec / console): total (unknown) / 23976 ms
9176 09:28:14.404414
9177 09:28:14.404791
9178 09:28:14.413885 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9179 09:28:14.417127 ARM64: Exception handlers installed.
9180 09:28:14.420064 ARM64: Testing exception
9181 09:28:14.423945 ARM64: Done test exception
9182 09:28:14.424518 Enumerating buses...
9183 09:28:14.427259 Show all devs... Before device enumeration.
9184 09:28:14.430359 Root Device: enabled 1
9185 09:28:14.433825 CPU_CLUSTER: 0: enabled 1
9186 09:28:14.434390 CPU: 00: enabled 1
9187 09:28:14.436999 Compare with tree...
9188 09:28:14.437574 Root Device: enabled 1
9189 09:28:14.440126 CPU_CLUSTER: 0: enabled 1
9190 09:28:14.443646 CPU: 00: enabled 1
9191 09:28:14.444215 Root Device scanning...
9192 09:28:14.446721 scan_static_bus for Root Device
9193 09:28:14.450374 CPU_CLUSTER: 0 enabled
9194 09:28:14.453642 scan_static_bus for Root Device done
9195 09:28:14.456598 scan_bus: bus Root Device finished in 8 msecs
9196 09:28:14.457095 done
9197 09:28:14.463427 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9198 09:28:14.466555 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9199 09:28:14.473283 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9200 09:28:14.476588 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9201 09:28:14.480523 Allocating resources...
9202 09:28:14.481130 Reading resources...
9203 09:28:14.486745 Root Device read_resources bus 0 link: 0
9204 09:28:14.487215 DRAM rank0 size:0x100000000,
9205 09:28:14.489883 DRAM rank1 size=0x100000000
9206 09:28:14.493240 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9207 09:28:14.496975 CPU: 00 missing read_resources
9208 09:28:14.500199 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9209 09:28:14.506724 Root Device read_resources bus 0 link: 0 done
9210 09:28:14.507279 Done reading resources.
9211 09:28:14.513383 Show resources in subtree (Root Device)...After reading.
9212 09:28:14.516575 Root Device child on link 0 CPU_CLUSTER: 0
9213 09:28:14.520037 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 09:28:14.529911 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 09:28:14.530445 CPU: 00
9216 09:28:14.533071 Root Device assign_resources, bus 0 link: 0
9217 09:28:14.536459 CPU_CLUSTER: 0 missing set_resources
9218 09:28:14.539749 Root Device assign_resources, bus 0 link: 0 done
9219 09:28:14.543305 Done setting resources.
9220 09:28:14.549958 Show resources in subtree (Root Device)...After assigning values.
9221 09:28:14.553535 Root Device child on link 0 CPU_CLUSTER: 0
9222 09:28:14.556174 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 09:28:14.566285 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 09:28:14.566855 CPU: 00
9225 09:28:14.569526 Done allocating resources.
9226 09:28:14.572745 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9227 09:28:14.576156 Enabling resources...
9228 09:28:14.576578 done.
9229 09:28:14.583028 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9230 09:28:14.583555 Initializing devices...
9231 09:28:14.586000 Root Device init
9232 09:28:14.586426 init hardware done!
9233 09:28:14.589513 0x00000018: ctrlr->caps
9234 09:28:14.592910 52.000 MHz: ctrlr->f_max
9235 09:28:14.593564 0.400 MHz: ctrlr->f_min
9236 09:28:14.596489 0x40ff8080: ctrlr->voltages
9237 09:28:14.597081 sclk: 390625
9238 09:28:14.599795 Bus Width = 1
9239 09:28:14.600312 sclk: 390625
9240 09:28:14.603264 Bus Width = 1
9241 09:28:14.603786 Early init status = 3
9242 09:28:14.609461 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9243 09:28:14.612565 in-header: 03 fc 00 00 01 00 00 00
9244 09:28:14.613037 in-data: 00
9245 09:28:14.619543 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9246 09:28:14.622812 in-header: 03 fd 00 00 00 00 00 00
9247 09:28:14.625967 in-data:
9248 09:28:14.629059 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9249 09:28:14.633033 in-header: 03 fc 00 00 01 00 00 00
9250 09:28:14.636727 in-data: 00
9251 09:28:14.639749 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9252 09:28:14.645059 in-header: 03 fd 00 00 00 00 00 00
9253 09:28:14.648807 in-data:
9254 09:28:14.651838 [SSUSB] Setting up USB HOST controller...
9255 09:28:14.655345 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9256 09:28:14.658323 [SSUSB] phy power-on done.
9257 09:28:14.661750 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9258 09:28:14.668631 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9259 09:28:14.671871 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9260 09:28:14.678484 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9261 09:28:14.684834 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9262 09:28:14.691766 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9263 09:28:14.698145 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9264 09:28:14.704480 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9265 09:28:14.707812 SPM: binary array size = 0x9dc
9266 09:28:14.711129 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9267 09:28:14.717825 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9268 09:28:14.724583 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9269 09:28:14.727920 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9270 09:28:14.734345 configure_display: Starting display init
9271 09:28:14.767936 anx7625_power_on_init: Init interface.
9272 09:28:14.771435 anx7625_disable_pd_protocol: Disabled PD feature.
9273 09:28:14.774592 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9274 09:28:14.802540 anx7625_start_dp_work: Secure OCM version=00
9275 09:28:14.805983 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9276 09:28:14.820955 sp_tx_get_edid_block: EDID Block = 1
9277 09:28:14.923383 Extracted contents:
9278 09:28:14.926552 header: 00 ff ff ff ff ff ff 00
9279 09:28:14.929798 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9280 09:28:14.933130 version: 01 04
9281 09:28:14.936521 basic params: 95 1f 11 78 0a
9282 09:28:14.939676 chroma info: 76 90 94 55 54 90 27 21 50 54
9283 09:28:14.943189 established: 00 00 00
9284 09:28:14.949559 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9285 09:28:14.953134 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9286 09:28:14.959406 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9287 09:28:14.966312 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9288 09:28:14.973262 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9289 09:28:14.976420 extensions: 00
9290 09:28:14.976670 checksum: fb
9291 09:28:14.976814
9292 09:28:14.979431 Manufacturer: IVO Model 57d Serial Number 0
9293 09:28:14.983316 Made week 0 of 2020
9294 09:28:14.983595 EDID version: 1.4
9295 09:28:14.986365 Digital display
9296 09:28:14.989557 6 bits per primary color channel
9297 09:28:14.989806 DisplayPort interface
9298 09:28:14.992875 Maximum image size: 31 cm x 17 cm
9299 09:28:14.996730 Gamma: 220%
9300 09:28:14.997243 Check DPMS levels
9301 09:28:14.999902 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9302 09:28:15.006272 First detailed timing is preferred timing
9303 09:28:15.006837 Established timings supported:
9304 09:28:15.009639 Standard timings supported:
9305 09:28:15.013357 Detailed timings
9306 09:28:15.016626 Hex of detail: 383680a07038204018303c0035ae10000019
9307 09:28:15.019210 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9308 09:28:15.025986 0780 0798 07c8 0820 hborder 0
9309 09:28:15.029353 0438 043b 0447 0458 vborder 0
9310 09:28:15.032611 -hsync -vsync
9311 09:28:15.033042 Did detailed timing
9312 09:28:15.039297 Hex of detail: 000000000000000000000000000000000000
9313 09:28:15.042902 Manufacturer-specified data, tag 0
9314 09:28:15.045896 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9315 09:28:15.049476 ASCII string: InfoVision
9316 09:28:15.052543 Hex of detail: 000000fe00523134304e574635205248200a
9317 09:28:15.055815 ASCII string: R140NWF5 RH
9318 09:28:15.056229 Checksum
9319 09:28:15.059587 Checksum: 0xfb (valid)
9320 09:28:15.062576 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9321 09:28:15.065625 DSI data_rate: 832800000 bps
9322 09:28:15.072772 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9323 09:28:15.076180 anx7625_parse_edid: pixelclock(138800).
9324 09:28:15.078862 hactive(1920), hsync(48), hfp(24), hbp(88)
9325 09:28:15.082333 vactive(1080), vsync(12), vfp(3), vbp(17)
9326 09:28:15.085543 anx7625_dsi_config: config dsi.
9327 09:28:15.092540 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9328 09:28:15.105603 anx7625_dsi_config: success to config DSI
9329 09:28:15.109002 anx7625_dp_start: MIPI phy setup OK.
9330 09:28:15.112410 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9331 09:28:15.115512 mtk_ddp_mode_set invalid vrefresh 60
9332 09:28:15.119434 main_disp_path_setup
9333 09:28:15.120141 ovl_layer_smi_id_en
9334 09:28:15.122281 ovl_layer_smi_id_en
9335 09:28:15.122737 ccorr_config
9336 09:28:15.123097 aal_config
9337 09:28:15.125653 gamma_config
9338 09:28:15.126173 postmask_config
9339 09:28:15.128891 dither_config
9340 09:28:15.131889 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9341 09:28:15.138436 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9342 09:28:15.142252 Root Device init finished in 553 msecs
9343 09:28:15.144891 CPU_CLUSTER: 0 init
9344 09:28:15.151812 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9345 09:28:15.158452 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9346 09:28:15.158991 APU_MBOX 0x190000b0 = 0x10001
9347 09:28:15.161781 APU_MBOX 0x190001b0 = 0x10001
9348 09:28:15.164908 APU_MBOX 0x190005b0 = 0x10001
9349 09:28:15.168242 APU_MBOX 0x190006b0 = 0x10001
9350 09:28:15.174972 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9351 09:28:15.184586 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9352 09:28:15.196643 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9353 09:28:15.203438 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9354 09:28:15.215004 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9355 09:28:15.224247 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9356 09:28:15.227619 CPU_CLUSTER: 0 init finished in 81 msecs
9357 09:28:15.231256 Devices initialized
9358 09:28:15.234252 Show all devs... After init.
9359 09:28:15.234668 Root Device: enabled 1
9360 09:28:15.237451 CPU_CLUSTER: 0: enabled 1
9361 09:28:15.240989 CPU: 00: enabled 1
9362 09:28:15.244185 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9363 09:28:15.247568 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9364 09:28:15.250515 ELOG: NV offset 0x57f000 size 0x1000
9365 09:28:15.257423 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9366 09:28:15.264150 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9367 09:28:15.267213 ELOG: Event(17) added with size 13 at 2023-10-20 09:27:53 UTC
9368 09:28:15.270832 out: cmd=0x121: 03 db 21 01 00 00 00 00
9369 09:28:15.274329 in-header: 03 52 00 00 2c 00 00 00
9370 09:28:15.287541 in-data: 0d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9371 09:28:15.294397 ELOG: Event(A1) added with size 10 at 2023-10-20 09:27:53 UTC
9372 09:28:15.301355 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9373 09:28:15.307941 ELOG: Event(A0) added with size 9 at 2023-10-20 09:27:53 UTC
9374 09:28:15.311131 elog_add_boot_reason: Logged dev mode boot
9375 09:28:15.314606 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9376 09:28:15.317781 Finalize devices...
9377 09:28:15.318197 Devices finalized
9378 09:28:15.324707 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9379 09:28:15.327859 Writing coreboot table at 0xffe64000
9380 09:28:15.330956 0. 000000000010a000-0000000000113fff: RAMSTAGE
9381 09:28:15.334340 1. 0000000040000000-00000000400fffff: RAM
9382 09:28:15.338165 2. 0000000040100000-000000004032afff: RAMSTAGE
9383 09:28:15.344453 3. 000000004032b000-00000000545fffff: RAM
9384 09:28:15.347713 4. 0000000054600000-000000005465ffff: BL31
9385 09:28:15.350979 5. 0000000054660000-00000000ffe63fff: RAM
9386 09:28:15.354544 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9387 09:28:15.361331 7. 0000000100000000-000000023fffffff: RAM
9388 09:28:15.361843 Passing 5 GPIOs to payload:
9389 09:28:15.367391 NAME | PORT | POLARITY | VALUE
9390 09:28:15.371033 EC in RW | 0x000000aa | low | undefined
9391 09:28:15.377430 EC interrupt | 0x00000005 | low | undefined
9392 09:28:15.380983 TPM interrupt | 0x000000ab | high | undefined
9393 09:28:15.383975 SD card detect | 0x00000011 | high | undefined
9394 09:28:15.390656 speaker enable | 0x00000093 | high | undefined
9395 09:28:15.393848 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9396 09:28:15.397414 in-header: 03 f9 00 00 02 00 00 00
9397 09:28:15.397828 in-data: 02 00
9398 09:28:15.400542 ADC[4]: Raw value=901401 ID=7
9399 09:28:15.404136 ADC[3]: Raw value=213179 ID=1
9400 09:28:15.404656 RAM Code: 0x71
9401 09:28:15.407348 ADC[6]: Raw value=74502 ID=0
9402 09:28:15.411068 ADC[5]: Raw value=212072 ID=1
9403 09:28:15.411581 SKU Code: 0x1
9404 09:28:15.417203 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7bf8
9405 09:28:15.420827 coreboot table: 964 bytes.
9406 09:28:15.423987 IMD ROOT 0. 0xfffff000 0x00001000
9407 09:28:15.427308 IMD SMALL 1. 0xffffe000 0x00001000
9408 09:28:15.430393 RO MCACHE 2. 0xffffc000 0x00001104
9409 09:28:15.434007 CONSOLE 3. 0xfff7c000 0x00080000
9410 09:28:15.437536 FMAP 4. 0xfff7b000 0x00000452
9411 09:28:15.440732 TIME STAMP 5. 0xfff7a000 0x00000910
9412 09:28:15.443655 VBOOT WORK 6. 0xfff66000 0x00014000
9413 09:28:15.447108 RAMOOPS 7. 0xffe66000 0x00100000
9414 09:28:15.450597 COREBOOT 8. 0xffe64000 0x00002000
9415 09:28:15.451153 IMD small region:
9416 09:28:15.453621 IMD ROOT 0. 0xffffec00 0x00000400
9417 09:28:15.456901 VPD 1. 0xffffeb80 0x0000006c
9418 09:28:15.460215 MMC STATUS 2. 0xffffeb60 0x00000004
9419 09:28:15.467174 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9420 09:28:15.470375 Probing TPM: done!
9421 09:28:15.473760 Connected to device vid:did:rid of 1ae0:0028:00
9422 09:28:15.483892 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9423 09:28:15.487753 Initialized TPM device CR50 revision 0
9424 09:28:15.491044 Checking cr50 for pending updates
9425 09:28:15.494258 Reading cr50 TPM mode
9426 09:28:15.502987 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9427 09:28:15.509503 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9428 09:28:15.549618 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9429 09:28:15.553116 Checking segment from ROM address 0x40100000
9430 09:28:15.556316 Checking segment from ROM address 0x4010001c
9431 09:28:15.563180 Loading segment from ROM address 0x40100000
9432 09:28:15.563734 code (compression=0)
9433 09:28:15.569780 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9434 09:28:15.579570 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9435 09:28:15.580127 it's not compressed!
9436 09:28:15.586219 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9437 09:28:15.589369 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9438 09:28:15.609730 Loading segment from ROM address 0x4010001c
9439 09:28:15.610211 Entry Point 0x80000000
9440 09:28:15.612891 Loaded segments
9441 09:28:15.616622 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9442 09:28:15.623329 Jumping to boot code at 0x80000000(0xffe64000)
9443 09:28:15.629661 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9444 09:28:15.636522 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9445 09:28:15.644568 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9446 09:28:15.647246 Checking segment from ROM address 0x40100000
9447 09:28:15.650589 Checking segment from ROM address 0x4010001c
9448 09:28:15.657527 Loading segment from ROM address 0x40100000
9449 09:28:15.658098 code (compression=1)
9450 09:28:15.664281 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9451 09:28:15.674094 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9452 09:28:15.674647 using LZMA
9453 09:28:15.682682 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9454 09:28:15.689362 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9455 09:28:15.692702 Loading segment from ROM address 0x4010001c
9456 09:28:15.693263 Entry Point 0x54601000
9457 09:28:15.695948 Loaded segments
9458 09:28:15.699633 NOTICE: MT8192 bl31_setup
9459 09:28:15.706343 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9460 09:28:15.709335 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9461 09:28:15.712864 WARNING: region 0:
9462 09:28:15.716208 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 09:28:15.716664 WARNING: region 1:
9464 09:28:15.722977 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9465 09:28:15.726289 WARNING: region 2:
9466 09:28:15.729866 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9467 09:28:15.733088 WARNING: region 3:
9468 09:28:15.736398 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 09:28:15.739566 WARNING: region 4:
9470 09:28:15.746729 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 09:28:15.747289 WARNING: region 5:
9472 09:28:15.750079 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 09:28:15.753090 WARNING: region 6:
9474 09:28:15.756366 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 09:28:15.759689 WARNING: region 7:
9476 09:28:15.762883 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 09:28:15.769458 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9478 09:28:15.773075 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9479 09:28:15.776473 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9480 09:28:15.783377 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9481 09:28:15.786325 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9482 09:28:15.789601 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9483 09:28:15.796856 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9484 09:28:15.799607 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9485 09:28:15.806005 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9486 09:28:15.809494 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9487 09:28:15.812728 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9488 09:28:15.819783 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9489 09:28:15.823190 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9490 09:28:15.826723 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9491 09:28:15.832760 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9492 09:28:15.836472 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9493 09:28:15.839763 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9494 09:28:15.846319 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9495 09:28:15.849620 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9496 09:28:15.856638 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9497 09:28:15.859567 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9498 09:28:15.863091 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9499 09:28:15.869631 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9500 09:28:15.872810 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9501 09:28:15.879743 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9502 09:28:15.883468 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9503 09:28:15.886126 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9504 09:28:15.893146 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9505 09:28:15.896329 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9506 09:28:15.899591 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9507 09:28:15.906383 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9508 09:28:15.909595 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9509 09:28:15.916346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9510 09:28:15.919257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9511 09:28:15.923041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9512 09:28:15.926217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9513 09:28:15.929612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9514 09:28:15.936236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9515 09:28:15.939531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9516 09:28:15.942757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9517 09:28:15.946613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9518 09:28:15.952962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9519 09:28:15.956173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9520 09:28:15.960142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9521 09:28:15.963015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9522 09:28:15.969899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9523 09:28:15.973387 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9524 09:28:15.976914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9525 09:28:15.983309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9526 09:28:15.986464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9527 09:28:15.989886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9528 09:28:15.996727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9529 09:28:15.999976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9530 09:28:16.006502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9531 09:28:16.010098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9532 09:28:16.016921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9533 09:28:16.019780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9534 09:28:16.023611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9535 09:28:16.029772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9536 09:28:16.033117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9537 09:28:16.039512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9538 09:28:16.043012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9539 09:28:16.049753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9540 09:28:16.053385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9541 09:28:16.059457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9542 09:28:16.062987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9543 09:28:16.066430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9544 09:28:16.072728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9545 09:28:16.076161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9546 09:28:16.082922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9547 09:28:16.086038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9548 09:28:16.093008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9549 09:28:16.096612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9550 09:28:16.099619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9551 09:28:16.106399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9552 09:28:16.109427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9553 09:28:16.116477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9554 09:28:16.119290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9555 09:28:16.125912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9556 09:28:16.129310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9557 09:28:16.135894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9558 09:28:16.139286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9559 09:28:16.142703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9560 09:28:16.149219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9561 09:28:16.152650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9562 09:28:16.159255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9563 09:28:16.162581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9564 09:28:16.165805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9565 09:28:16.172496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9566 09:28:16.175880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9567 09:28:16.182749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9568 09:28:16.186029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9569 09:28:16.192728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9570 09:28:16.196159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9571 09:28:16.202877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9572 09:28:16.206163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9573 09:28:16.209238 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9574 09:28:16.212772 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9575 09:28:16.219407 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9576 09:28:16.222724 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9577 09:28:16.225963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9578 09:28:16.232650 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9579 09:28:16.235689 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9580 09:28:16.242740 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9581 09:28:16.246195 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9582 09:28:16.249231 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9583 09:28:16.256395 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9584 09:28:16.258988 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9585 09:28:16.262537 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9586 09:28:16.269154 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9587 09:28:16.272624 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9588 09:28:16.279340 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9589 09:28:16.282824 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9590 09:28:16.286227 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9591 09:28:16.292371 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9592 09:28:16.296009 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9593 09:28:16.299418 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9594 09:28:16.306044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9595 09:28:16.309417 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9596 09:28:16.312641 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9597 09:28:16.319271 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9598 09:28:16.322502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9599 09:28:16.325859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9600 09:28:16.329173 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9601 09:28:16.336446 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9602 09:28:16.339627 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9603 09:28:16.342891 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9604 09:28:16.349688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9605 09:28:16.352624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9606 09:28:16.359790 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9607 09:28:16.363033 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9608 09:28:16.366331 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9609 09:28:16.373034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9610 09:28:16.376007 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9611 09:28:16.382888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9612 09:28:16.385829 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9613 09:28:16.389525 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9614 09:28:16.396516 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9615 09:28:16.399710 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9616 09:28:16.402915 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9617 09:28:16.409377 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9618 09:28:16.412770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9619 09:28:16.419318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9620 09:28:16.422770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9621 09:28:16.426292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9622 09:28:16.433136 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9623 09:28:16.436137 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9624 09:28:16.439572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9625 09:28:16.446338 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9626 09:28:16.449784 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9627 09:28:16.456096 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9628 09:28:16.459988 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9629 09:28:16.462977 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9630 09:28:16.469717 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9631 09:28:16.473145 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9632 09:28:16.479726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9633 09:28:16.483394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9634 09:28:16.486210 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9635 09:28:16.493356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9636 09:28:16.496336 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9637 09:28:16.499861 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9638 09:28:16.506480 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9639 09:28:16.509441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9640 09:28:16.516229 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9641 09:28:16.519465 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9642 09:28:16.522910 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9643 09:28:16.529402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9644 09:28:16.532645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9645 09:28:16.539284 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9646 09:28:16.542611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9647 09:28:16.545871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9648 09:28:16.552567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9649 09:28:16.555994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9650 09:28:16.559353 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9651 09:28:16.565984 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9652 09:28:16.569245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9653 09:28:16.575705 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9654 09:28:16.578985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9655 09:28:16.582343 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9656 09:28:16.588958 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9657 09:28:16.592328 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9658 09:28:16.599040 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9659 09:28:16.602350 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9660 09:28:16.605605 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9661 09:28:16.612149 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9662 09:28:16.615528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9663 09:28:16.622126 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9664 09:28:16.625517 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9665 09:28:16.628899 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9666 09:28:16.635336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9667 09:28:16.638693 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9668 09:28:16.645207 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9669 09:28:16.648616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9670 09:28:16.651887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9671 09:28:16.658406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9672 09:28:16.661940 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9673 09:28:16.668745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9674 09:28:16.671743 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9675 09:28:16.678476 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9676 09:28:16.681882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9677 09:28:16.684917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9678 09:28:16.691630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9679 09:28:16.694854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9680 09:28:16.701937 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9681 09:28:16.705205 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9682 09:28:16.711629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9683 09:28:16.714992 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9684 09:28:16.718538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9685 09:28:16.725085 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9686 09:28:16.728423 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9687 09:28:16.735278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9688 09:28:16.738494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9689 09:28:16.742213 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9690 09:28:16.748097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9691 09:28:16.751475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9692 09:28:16.758072 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9693 09:28:16.761440 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9694 09:28:16.764819 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9695 09:28:16.771334 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9696 09:28:16.774762 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9697 09:28:16.781535 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9698 09:28:16.784774 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9699 09:28:16.791270 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9700 09:28:16.794814 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9701 09:28:16.798013 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9702 09:28:16.804513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9703 09:28:16.808142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9704 09:28:16.814856 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9705 09:28:16.817978 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9706 09:28:16.821469 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9707 09:28:16.824695 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9708 09:28:16.831699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9709 09:28:16.834960 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9710 09:28:16.837932 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9711 09:28:16.841193 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9712 09:28:16.848122 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9713 09:28:16.851418 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9714 09:28:16.858354 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9715 09:28:16.861380 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9716 09:28:16.864604 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9717 09:28:16.870930 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9718 09:28:16.874249 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9719 09:28:16.880840 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9720 09:28:16.884360 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9721 09:28:16.887436 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9722 09:28:16.894409 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9723 09:28:16.897820 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9724 09:28:16.901042 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9725 09:28:16.907747 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9726 09:28:16.910958 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9727 09:28:16.914183 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9728 09:28:16.920764 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9729 09:28:16.924279 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9730 09:28:16.930696 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9731 09:28:16.933854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9732 09:28:16.937026 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9733 09:28:16.943781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9734 09:28:16.947334 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9735 09:28:16.950517 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9736 09:28:16.957311 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9737 09:28:16.960554 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9738 09:28:16.967245 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9739 09:28:16.970561 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9740 09:28:16.973978 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9741 09:28:16.980487 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9742 09:28:16.983702 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9743 09:28:16.987337 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9744 09:28:16.993705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9745 09:28:16.996965 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9746 09:28:17.000717 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9747 09:28:17.003631 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9748 09:28:17.010417 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9749 09:28:17.013592 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9750 09:28:17.016741 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9751 09:28:17.020413 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9752 09:28:17.026964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9753 09:28:17.030355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9754 09:28:17.033305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9755 09:28:17.036694 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9756 09:28:17.043654 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9757 09:28:17.046739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9758 09:28:17.050135 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9759 09:28:17.056718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9760 09:28:17.060222 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9761 09:28:17.063549 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9762 09:28:17.069965 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9763 09:28:17.073495 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9764 09:28:17.080203 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9765 09:28:17.083458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9766 09:28:17.086890 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9767 09:28:17.093457 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9768 09:28:17.096875 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9769 09:28:17.103409 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9770 09:28:17.106551 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9771 09:28:17.113239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9772 09:28:17.116699 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9773 09:28:17.120473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9774 09:28:17.126458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9775 09:28:17.129960 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9776 09:28:17.136823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9777 09:28:17.139975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9778 09:28:17.143423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9779 09:28:17.149926 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9780 09:28:17.153340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9781 09:28:17.159811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9782 09:28:17.163072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9783 09:28:17.166468 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9784 09:28:17.173014 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9785 09:28:17.176356 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9786 09:28:17.182943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9787 09:28:17.186562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9788 09:28:17.192941 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9789 09:28:17.196449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9790 09:28:17.199551 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9791 09:28:17.206360 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9792 09:28:17.209825 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9793 09:28:17.216235 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9794 09:28:17.219374 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9795 09:28:17.222656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9796 09:28:17.229644 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9797 09:28:17.233107 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9798 09:28:17.239272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9799 09:28:17.242766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9800 09:28:17.246070 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9801 09:28:17.252765 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9802 09:28:17.256505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9803 09:28:17.262697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9804 09:28:17.266332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9805 09:28:17.269201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9806 09:28:17.276039 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9807 09:28:17.279348 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9808 09:28:17.286082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9809 09:28:17.289274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9810 09:28:17.292510 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9811 09:28:17.299308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9812 09:28:17.302668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9813 09:28:17.309393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9814 09:28:17.312551 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9815 09:28:17.315994 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9816 09:28:17.322464 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9817 09:28:17.325740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9818 09:28:17.332362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9819 09:28:17.335822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9820 09:28:17.342217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9821 09:28:17.345624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9822 09:28:17.349002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9823 09:28:17.355465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9824 09:28:17.358995 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9825 09:28:17.365647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9826 09:28:17.369109 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9827 09:28:17.372256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9828 09:28:17.379016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9829 09:28:17.382173 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9830 09:28:17.388851 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9831 09:28:17.392163 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9832 09:28:17.395536 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9833 09:28:17.402076 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9834 09:28:17.405396 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9835 09:28:17.412133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9836 09:28:17.415691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9837 09:28:17.422355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9838 09:28:17.425288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9839 09:28:17.429006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9840 09:28:17.435260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9841 09:28:17.439032 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9842 09:28:17.445588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9843 09:28:17.448841 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9844 09:28:17.455193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9845 09:28:17.458593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9846 09:28:17.461944 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9847 09:28:17.469079 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9848 09:28:17.472074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9849 09:28:17.479071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9850 09:28:17.481957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9851 09:28:17.488875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9852 09:28:17.491932 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9853 09:28:17.498533 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9854 09:28:17.501723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9855 09:28:17.505111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9856 09:28:17.511775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9857 09:28:17.515118 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9858 09:28:17.521827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9859 09:28:17.524759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9860 09:28:17.531420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9861 09:28:17.534849 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9862 09:28:17.538083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9863 09:28:17.544866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9864 09:28:17.548263 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9865 09:28:17.554430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9866 09:28:17.558003 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9867 09:28:17.564739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9868 09:28:17.567944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9869 09:28:17.574339 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9870 09:28:17.577961 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9871 09:28:17.581535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9872 09:28:17.587477 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9873 09:28:17.591149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9874 09:28:17.597816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9875 09:28:17.601148 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9876 09:28:17.607420 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9877 09:28:17.610775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9878 09:28:17.617679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9879 09:28:17.621098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9880 09:28:17.624454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9881 09:28:17.631166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9882 09:28:17.634504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9883 09:28:17.641099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9884 09:28:17.644230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9885 09:28:17.651093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9886 09:28:17.654018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9887 09:28:17.660856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9888 09:28:17.664086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9889 09:28:17.671065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9890 09:28:17.674285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9891 09:28:17.680710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9892 09:28:17.684128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9893 09:28:17.690605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9894 09:28:17.693693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9895 09:28:17.700436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9896 09:28:17.703745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9897 09:28:17.706894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9898 09:28:17.714108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9899 09:28:17.717058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9900 09:28:17.723724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9901 09:28:17.727041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9902 09:28:17.733895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9903 09:28:17.736871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9904 09:28:17.743540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9905 09:28:17.746904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9906 09:28:17.753522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9907 09:28:17.756998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9908 09:28:17.763766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9909 09:28:17.766920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9910 09:28:17.773618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9911 09:28:17.776952 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9912 09:28:17.780174 INFO: [APUAPC] vio 0
9913 09:28:17.783429 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9914 09:28:17.790211 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9915 09:28:17.793677 INFO: [APUAPC] D0_APC_0: 0x400510
9916 09:28:17.796813 INFO: [APUAPC] D0_APC_1: 0x0
9917 09:28:17.800032 INFO: [APUAPC] D0_APC_2: 0x1540
9918 09:28:17.800117 INFO: [APUAPC] D0_APC_3: 0x0
9919 09:28:17.803757 INFO: [APUAPC] D1_APC_0: 0xffffffff
9920 09:28:17.807068 INFO: [APUAPC] D1_APC_1: 0xffffffff
9921 09:28:17.810245 INFO: [APUAPC] D1_APC_2: 0x3fffff
9922 09:28:17.813587 INFO: [APUAPC] D1_APC_3: 0x0
9923 09:28:17.817087 INFO: [APUAPC] D2_APC_0: 0xffffffff
9924 09:28:17.820214 INFO: [APUAPC] D2_APC_1: 0xffffffff
9925 09:28:17.823494 INFO: [APUAPC] D2_APC_2: 0x3fffff
9926 09:28:17.827111 INFO: [APUAPC] D2_APC_3: 0x0
9927 09:28:17.830056 INFO: [APUAPC] D3_APC_0: 0xffffffff
9928 09:28:17.833747 INFO: [APUAPC] D3_APC_1: 0xffffffff
9929 09:28:17.836868 INFO: [APUAPC] D3_APC_2: 0x3fffff
9930 09:28:17.840395 INFO: [APUAPC] D3_APC_3: 0x0
9931 09:28:17.843639 INFO: [APUAPC] D4_APC_0: 0xffffffff
9932 09:28:17.846759 INFO: [APUAPC] D4_APC_1: 0xffffffff
9933 09:28:17.850193 INFO: [APUAPC] D4_APC_2: 0x3fffff
9934 09:28:17.853620 INFO: [APUAPC] D4_APC_3: 0x0
9935 09:28:17.856926 INFO: [APUAPC] D5_APC_0: 0xffffffff
9936 09:28:17.860402 INFO: [APUAPC] D5_APC_1: 0xffffffff
9937 09:28:17.863600 INFO: [APUAPC] D5_APC_2: 0x3fffff
9938 09:28:17.866734 INFO: [APUAPC] D5_APC_3: 0x0
9939 09:28:17.869975 INFO: [APUAPC] D6_APC_0: 0xffffffff
9940 09:28:17.873528 INFO: [APUAPC] D6_APC_1: 0xffffffff
9941 09:28:17.876664 INFO: [APUAPC] D6_APC_2: 0x3fffff
9942 09:28:17.880126 INFO: [APUAPC] D6_APC_3: 0x0
9943 09:28:17.883071 INFO: [APUAPC] D7_APC_0: 0xffffffff
9944 09:28:17.886500 INFO: [APUAPC] D7_APC_1: 0xffffffff
9945 09:28:17.890135 INFO: [APUAPC] D7_APC_2: 0x3fffff
9946 09:28:17.893464 INFO: [APUAPC] D7_APC_3: 0x0
9947 09:28:17.896496 INFO: [APUAPC] D8_APC_0: 0xffffffff
9948 09:28:17.899867 INFO: [APUAPC] D8_APC_1: 0xffffffff
9949 09:28:17.903053 INFO: [APUAPC] D8_APC_2: 0x3fffff
9950 09:28:17.906417 INFO: [APUAPC] D8_APC_3: 0x0
9951 09:28:17.909863 INFO: [APUAPC] D9_APC_0: 0xffffffff
9952 09:28:17.913131 INFO: [APUAPC] D9_APC_1: 0xffffffff
9953 09:28:17.916407 INFO: [APUAPC] D9_APC_2: 0x3fffff
9954 09:28:17.920027 INFO: [APUAPC] D9_APC_3: 0x0
9955 09:28:17.923360 INFO: [APUAPC] D10_APC_0: 0xffffffff
9956 09:28:17.926348 INFO: [APUAPC] D10_APC_1: 0xffffffff
9957 09:28:17.929487 INFO: [APUAPC] D10_APC_2: 0x3fffff
9958 09:28:17.932853 INFO: [APUAPC] D10_APC_3: 0x0
9959 09:28:17.936146 INFO: [APUAPC] D11_APC_0: 0xffffffff
9960 09:28:17.939463 INFO: [APUAPC] D11_APC_1: 0xffffffff
9961 09:28:17.942991 INFO: [APUAPC] D11_APC_2: 0x3fffff
9962 09:28:17.946548 INFO: [APUAPC] D11_APC_3: 0x0
9963 09:28:17.949887 INFO: [APUAPC] D12_APC_0: 0xffffffff
9964 09:28:17.953137 INFO: [APUAPC] D12_APC_1: 0xffffffff
9965 09:28:17.956062 INFO: [APUAPC] D12_APC_2: 0x3fffff
9966 09:28:17.959422 INFO: [APUAPC] D12_APC_3: 0x0
9967 09:28:17.962945 INFO: [APUAPC] D13_APC_0: 0xffffffff
9968 09:28:17.966103 INFO: [APUAPC] D13_APC_1: 0xffffffff
9969 09:28:17.969342 INFO: [APUAPC] D13_APC_2: 0x3fffff
9970 09:28:17.972817 INFO: [APUAPC] D13_APC_3: 0x0
9971 09:28:17.975987 INFO: [APUAPC] D14_APC_0: 0xffffffff
9972 09:28:17.979303 INFO: [APUAPC] D14_APC_1: 0xffffffff
9973 09:28:17.982853 INFO: [APUAPC] D14_APC_2: 0x3fffff
9974 09:28:17.986107 INFO: [APUAPC] D14_APC_3: 0x0
9975 09:28:17.989694 INFO: [APUAPC] D15_APC_0: 0xffffffff
9976 09:28:17.993063 INFO: [APUAPC] D15_APC_1: 0xffffffff
9977 09:28:17.996339 INFO: [APUAPC] D15_APC_2: 0x3fffff
9978 09:28:17.999365 INFO: [APUAPC] D15_APC_3: 0x0
9979 09:28:18.002719 INFO: [APUAPC] APC_CON: 0x4
9980 09:28:18.002804 INFO: [NOCDAPC] D0_APC_0: 0x0
9981 09:28:18.005931 INFO: [NOCDAPC] D0_APC_1: 0x0
9982 09:28:18.009244 INFO: [NOCDAPC] D1_APC_0: 0x0
9983 09:28:18.012750 INFO: [NOCDAPC] D1_APC_1: 0xfff
9984 09:28:18.016162 INFO: [NOCDAPC] D2_APC_0: 0x0
9985 09:28:18.019407 INFO: [NOCDAPC] D2_APC_1: 0xfff
9986 09:28:18.022667 INFO: [NOCDAPC] D3_APC_0: 0x0
9987 09:28:18.026008 INFO: [NOCDAPC] D3_APC_1: 0xfff
9988 09:28:18.029069 INFO: [NOCDAPC] D4_APC_0: 0x0
9989 09:28:18.032494 INFO: [NOCDAPC] D4_APC_1: 0xfff
9990 09:28:18.035688 INFO: [NOCDAPC] D5_APC_0: 0x0
9991 09:28:18.035773 INFO: [NOCDAPC] D5_APC_1: 0xfff
9992 09:28:18.039076 INFO: [NOCDAPC] D6_APC_0: 0x0
9993 09:28:18.042412 INFO: [NOCDAPC] D6_APC_1: 0xfff
9994 09:28:18.045707 INFO: [NOCDAPC] D7_APC_0: 0x0
9995 09:28:18.048889 INFO: [NOCDAPC] D7_APC_1: 0xfff
9996 09:28:18.052408 INFO: [NOCDAPC] D8_APC_0: 0x0
9997 09:28:18.055927 INFO: [NOCDAPC] D8_APC_1: 0xfff
9998 09:28:18.059027 INFO: [NOCDAPC] D9_APC_0: 0x0
9999 09:28:18.062542 INFO: [NOCDAPC] D9_APC_1: 0xfff
10000 09:28:18.065962 INFO: [NOCDAPC] D10_APC_0: 0x0
10001 09:28:18.069060 INFO: [NOCDAPC] D10_APC_1: 0xfff
10002 09:28:18.072420 INFO: [NOCDAPC] D11_APC_0: 0x0
10003 09:28:18.072506 INFO: [NOCDAPC] D11_APC_1: 0xfff
10004 09:28:18.075600 INFO: [NOCDAPC] D12_APC_0: 0x0
10005 09:28:18.078917 INFO: [NOCDAPC] D12_APC_1: 0xfff
10006 09:28:18.082114 INFO: [NOCDAPC] D13_APC_0: 0x0
10007 09:28:18.085805 INFO: [NOCDAPC] D13_APC_1: 0xfff
10008 09:28:18.088983 INFO: [NOCDAPC] D14_APC_0: 0x0
10009 09:28:18.092227 INFO: [NOCDAPC] D14_APC_1: 0xfff
10010 09:28:18.095644 INFO: [NOCDAPC] D15_APC_0: 0x0
10011 09:28:18.098942 INFO: [NOCDAPC] D15_APC_1: 0xfff
10012 09:28:18.102246 INFO: [NOCDAPC] APC_CON: 0x4
10013 09:28:18.105599 INFO: [APUAPC] set_apusys_apc done
10014 09:28:18.108779 INFO: [DEVAPC] devapc_init done
10015 09:28:18.112055 INFO: GICv3 without legacy support detected.
10016 09:28:18.115941 INFO: ARM GICv3 driver initialized in EL3
10017 09:28:18.118876 INFO: Maximum SPI INTID supported: 639
10018 09:28:18.122341 INFO: BL31: Initializing runtime services
10019 09:28:18.129157 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10020 09:28:18.132526 INFO: SPM: enable CPC mode
10021 09:28:18.138860 INFO: mcdi ready for mcusys-off-idle and system suspend
10022 09:28:18.142320 INFO: BL31: Preparing for EL3 exit to normal world
10023 09:28:18.145512 INFO: Entry point address = 0x80000000
10024 09:28:18.148949 INFO: SPSR = 0x8
10025 09:28:18.153868
10026 09:28:18.153952
10027 09:28:18.154019
10028 09:28:18.156814 Starting depthcharge on Spherion...
10029 09:28:18.156923
10030 09:28:18.157040 Wipe memory regions:
10031 09:28:18.157105
10032 09:28:18.157745 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10033 09:28:18.157850 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10034 09:28:18.157933 Setting prompt string to ['asurada:']
10035 09:28:18.158015 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10036 09:28:18.160187 [0x00000040000000, 0x00000054600000)
10037 09:28:18.282783
10038 09:28:18.282930 [0x00000054660000, 0x00000080000000)
10039 09:28:18.543284
10040 09:28:18.543435 [0x000000821a7280, 0x000000ffe64000)
10041 09:28:19.288256
10042 09:28:19.288405 [0x00000100000000, 0x00000240000000)
10043 09:28:21.178713
10044 09:28:21.181721 Initializing XHCI USB controller at 0x11200000.
10045 09:28:22.219611
10046 09:28:22.222999 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10047 09:28:22.223100
10048 09:28:22.223167
10049 09:28:22.223230
10050 09:28:22.223512 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 09:28:22.323872 asurada: tftpboot 192.168.201.1 11826788/tftp-deploy-zdaz8vpz/kernel/image.itb 11826788/tftp-deploy-zdaz8vpz/kernel/cmdline
10053 09:28:22.324059 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 09:28:22.324168 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10055 09:28:22.328565 tftpboot 192.168.201.1 11826788/tftp-deploy-zdaz8vpz/kernel/image.ittp-deploy-zdaz8vpz/kernel/cmdline
10056 09:28:22.328651
10057 09:28:22.328719 Waiting for link
10058 09:28:22.488538
10059 09:28:22.488673 R8152: Initializing
10060 09:28:22.488745
10061 09:28:22.492003 Version 9 (ocp_data = 6010)
10062 09:28:22.492114
10063 09:28:22.495230 R8152: Done initializing
10064 09:28:22.495315
10065 09:28:22.495382 Adding net device
10066 09:28:24.378044
10067 09:28:24.378185 done.
10068 09:28:24.378257
10069 09:28:24.378320 MAC: 00:e0:4c:72:2d:d6
10070 09:28:24.378380
10071 09:28:24.381493 Sending DHCP discover... done.
10072 09:28:24.381579
10073 09:28:24.384609 Waiting for reply... done.
10074 09:28:24.384694
10075 09:28:24.387872 Sending DHCP request... done.
10076 09:28:24.387984
10077 09:28:24.391495 Waiting for reply... done.
10078 09:28:24.391580
10079 09:28:24.391647 My ip is 192.168.201.21
10080 09:28:24.391710
10081 09:28:24.394701 The DHCP server ip is 192.168.201.1
10082 09:28:24.394786
10083 09:28:24.401098 TFTP server IP predefined by user: 192.168.201.1
10084 09:28:24.401185
10085 09:28:24.407975 Bootfile predefined by user: 11826788/tftp-deploy-zdaz8vpz/kernel/image.itb
10086 09:28:24.408060
10087 09:28:24.408128 Sending tftp read request... done.
10088 09:28:24.411191
10089 09:28:24.411301 Waiting for the transfer...
10090 09:28:24.411400
10091 09:28:24.667674 00000000 ################################################################
10092 09:28:24.667822
10093 09:28:24.916389 00080000 ################################################################
10094 09:28:24.916556
10095 09:28:25.182935 00100000 ################################################################
10096 09:28:25.183102
10097 09:28:25.449561 00180000 ################################################################
10098 09:28:25.449715
10099 09:28:25.712082 00200000 ################################################################
10100 09:28:25.712218
10101 09:28:25.970094 00280000 ################################################################
10102 09:28:25.970287
10103 09:28:26.234026 00300000 ################################################################
10104 09:28:26.234167
10105 09:28:26.493661 00380000 ################################################################
10106 09:28:26.493795
10107 09:28:26.748213 00400000 ################################################################
10108 09:28:26.748364
10109 09:28:27.008743 00480000 ################################################################
10110 09:28:27.008868
10111 09:28:27.256701 00500000 ################################################################
10112 09:28:27.256852
10113 09:28:27.520409 00580000 ################################################################
10114 09:28:27.520561
10115 09:28:27.791076 00600000 ################################################################
10116 09:28:27.791256
10117 09:28:28.045342 00680000 ################################################################
10118 09:28:28.045493
10119 09:28:28.291883 00700000 ################################################################
10120 09:28:28.292039
10121 09:28:28.543889 00780000 ################################################################
10122 09:28:28.544072
10123 09:28:28.797499 00800000 ################################################################
10124 09:28:28.797764
10125 09:28:29.047980 00880000 ################################################################
10126 09:28:29.048119
10127 09:28:29.298431 00900000 ################################################################
10128 09:28:29.298585
10129 09:28:29.556473 00980000 ################################################################
10130 09:28:29.556625
10131 09:28:29.815982 00a00000 ################################################################
10132 09:28:29.816132
10133 09:28:30.068908 00a80000 ################################################################
10134 09:28:30.069068
10135 09:28:30.320755 00b00000 ################################################################
10136 09:28:30.320935
10137 09:28:30.569689 00b80000 ################################################################
10138 09:28:30.569846
10139 09:28:30.816279 00c00000 ################################################################
10140 09:28:30.816426
10141 09:28:31.075483 00c80000 ################################################################
10142 09:28:31.075626
10143 09:28:31.320517 00d00000 ################################################################
10144 09:28:31.320673
10145 09:28:31.566397 00d80000 ################################################################
10146 09:28:31.566538
10147 09:28:31.818189 00e00000 ################################################################
10148 09:28:31.818367
10149 09:28:32.098466 00e80000 ################################################################
10150 09:28:32.098614
10151 09:28:32.359535 00f00000 ################################################################
10152 09:28:32.359701
10153 09:28:32.617231 00f80000 ################################################################
10154 09:28:32.617398
10155 09:28:32.859947 01000000 ################################################################
10156 09:28:32.860112
10157 09:28:33.124762 01080000 ################################################################
10158 09:28:33.124935
10159 09:28:33.370852 01100000 ################################################################
10160 09:28:33.370986
10161 09:28:33.626361 01180000 ################################################################
10162 09:28:33.626498
10163 09:28:33.881615 01200000 ################################################################
10164 09:28:33.881756
10165 09:28:34.131825 01280000 ################################################################
10166 09:28:34.131966
10167 09:28:34.377614 01300000 ################################################################
10168 09:28:34.377755
10169 09:28:34.624626 01380000 ################################################################
10170 09:28:34.624785
10171 09:28:34.876328 01400000 ################################################################
10172 09:28:34.876489
10173 09:28:35.132461 01480000 ################################################################
10174 09:28:35.132635
10175 09:28:35.390499 01500000 ################################################################
10176 09:28:35.390641
10177 09:28:35.652507 01580000 ################################################################
10178 09:28:35.652669
10179 09:28:35.910116 01600000 ################################################################
10180 09:28:35.910288
10181 09:28:36.159113 01680000 ################################################################
10182 09:28:36.159269
10183 09:28:36.414742 01700000 ################################################################
10184 09:28:36.414923
10185 09:28:36.673558 01780000 ################################################################
10186 09:28:36.673719
10187 09:28:36.920410 01800000 ################################################################
10188 09:28:36.920563
10189 09:28:37.182295 01880000 ################################################################
10190 09:28:37.182477
10191 09:28:37.442784 01900000 ################################################################
10192 09:28:37.442975
10193 09:28:37.711899 01980000 ################################################################
10194 09:28:37.712061
10195 09:28:37.977507 01a00000 ################################################################
10196 09:28:37.977662
10197 09:28:38.236134 01a80000 ################################################################
10198 09:28:38.236284
10199 09:28:38.488432 01b00000 ################################################################
10200 09:28:38.488598
10201 09:28:38.749076 01b80000 ################################################################
10202 09:28:38.749247
10203 09:28:39.009256 01c00000 ################################################################
10204 09:28:39.009479
10205 09:28:39.262607 01c80000 ################################################################
10206 09:28:39.262797
10207 09:28:39.537408 01d00000 ################################################################
10208 09:28:39.537636
10209 09:28:39.790507 01d80000 ################################################################
10210 09:28:39.790687
10211 09:28:40.049503 01e00000 ################################################################
10212 09:28:40.049688
10213 09:28:40.291273 01e80000 ############################################################## done.
10214 09:28:40.291469
10215 09:28:40.294766 The bootfile was 32485646 bytes long.
10216 09:28:40.294880
10217 09:28:40.298356 Sending tftp read request... done.
10218 09:28:40.298469
10219 09:28:40.301395 Waiting for the transfer...
10220 09:28:40.301510
10221 09:28:40.301612 00000000 # done.
10222 09:28:40.301715
10223 09:28:40.311501 Command line loaded dynamically from TFTP file: 11826788/tftp-deploy-zdaz8vpz/kernel/cmdline
10224 09:28:40.311617
10225 09:28:40.324727 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10226 09:28:40.324851
10227 09:28:40.324995 Loading FIT.
10228 09:28:40.325097
10229 09:28:40.327816 Image ramdisk-1 has 21392073 bytes.
10230 09:28:40.327925
10231 09:28:40.331310 Image fdt-1 has 47278 bytes.
10232 09:28:40.331421
10233 09:28:40.334725 Image kernel-1 has 11044258 bytes.
10234 09:28:40.334837
10235 09:28:40.344666 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10236 09:28:40.344789
10237 09:28:40.361434 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10238 09:28:40.361568
10239 09:28:40.367710 Choosing best match conf-1 for compat google,spherion-rev2.
10240 09:28:40.367827
10241 09:28:40.375417 Connected to device vid:did:rid of 1ae0:0028:00
10242 09:28:40.383158
10243 09:28:40.386515 tpm_get_response: command 0x17b, return code 0x0
10244 09:28:40.386633
10245 09:28:40.389752 ec_init: CrosEC protocol v3 supported (256, 248)
10246 09:28:40.393919
10247 09:28:40.397266 tpm_cleanup: add release locality here.
10248 09:28:40.397379
10249 09:28:40.397484 Shutting down all USB controllers.
10250 09:28:40.400371
10251 09:28:40.400481 Removing current net device
10252 09:28:40.400584
10253 09:28:40.407293 Exiting depthcharge with code 4 at timestamp: 51523365
10254 09:28:40.407409
10255 09:28:40.410323 LZMA decompressing kernel-1 to 0x821a6718
10256 09:28:40.410436
10257 09:28:40.413802 LZMA decompressing kernel-1 to 0x40000000
10258 09:28:41.803902
10259 09:28:41.804042 jumping to kernel
10260 09:28:41.804506 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10261 09:28:41.804606 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10262 09:28:41.804683 Setting prompt string to ['Linux version [0-9]']
10263 09:28:41.804751 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10264 09:28:41.804821 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10265 09:28:41.885814
10266 09:28:41.889333 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10267 09:28:41.892487 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10268 09:28:41.892606 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10269 09:28:41.892679 Setting prompt string to []
10270 09:28:41.892761 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10271 09:28:41.892837 Using line separator: #'\n'#
10272 09:28:41.892897 No login prompt set.
10273 09:28:41.893000 Parsing kernel messages
10274 09:28:41.893056 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10275 09:28:41.893160 [login-action] Waiting for messages, (timeout 00:04:02)
10276 09:28:41.912256 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10277 09:28:41.916079 [ 0.000000] random: crng init done
10278 09:28:41.919354 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10279 09:28:41.922705 [ 0.000000] efi: UEFI not found.
10280 09:28:41.932486 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10281 09:28:41.938974 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10282 09:28:41.949147 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10283 09:28:41.958949 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10284 09:28:41.965824 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10285 09:28:41.968812 [ 0.000000] printk: bootconsole [mtk8250] enabled
10286 09:28:41.977316 [ 0.000000] NUMA: No NUMA configuration found
10287 09:28:41.984193 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10288 09:28:41.990679 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10289 09:28:41.990798 [ 0.000000] Zone ranges:
10290 09:28:41.997172 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10291 09:28:42.001056 [ 0.000000] DMA32 empty
10292 09:28:42.007422 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10293 09:28:42.010959 [ 0.000000] Movable zone start for each node
10294 09:28:42.014124 [ 0.000000] Early memory node ranges
10295 09:28:42.020492 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10296 09:28:42.027244 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10297 09:28:42.033801 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10298 09:28:42.040622 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10299 09:28:42.047048 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10300 09:28:42.053642 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10301 09:28:42.109983 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10302 09:28:42.116841 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10303 09:28:42.123308 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10304 09:28:42.126725 [ 0.000000] psci: probing for conduit method from DT.
10305 09:28:42.133245 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10306 09:28:42.136590 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10307 09:28:42.143325 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10308 09:28:42.146684 [ 0.000000] psci: SMC Calling Convention v1.2
10309 09:28:42.153308 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10310 09:28:42.156670 [ 0.000000] Detected VIPT I-cache on CPU0
10311 09:28:42.163320 [ 0.000000] CPU features: detected: GIC system register CPU interface
10312 09:28:42.170170 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10313 09:28:42.176692 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10314 09:28:42.183258 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10315 09:28:42.190066 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10316 09:28:42.196578 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10317 09:28:42.202961 [ 0.000000] alternatives: applying boot alternatives
10318 09:28:42.206369 [ 0.000000] Fallback order for Node 0: 0
10319 09:28:42.216228 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10320 09:28:42.216337 [ 0.000000] Policy zone: Normal
10321 09:28:42.233135 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10322 09:28:42.242855 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10323 09:28:42.253751 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10324 09:28:42.263405 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10325 09:28:42.270034 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10326 09:28:42.273279 <6>[ 0.000000] software IO TLB: area num 8.
10327 09:28:42.330407 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10328 09:28:42.479319 <6>[ 0.000000] Memory: 7948604K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 404164K reserved, 32768K cma-reserved)
10329 09:28:42.485914 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10330 09:28:42.492847 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10331 09:28:42.496172 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10332 09:28:42.502521 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10333 09:28:42.509354 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10334 09:28:42.512877 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10335 09:28:42.522905 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10336 09:28:42.529438 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10337 09:28:42.532370 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10338 09:28:42.540242 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10339 09:28:42.543587 <6>[ 0.000000] GICv3: 608 SPIs implemented
10340 09:28:42.550375 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10341 09:28:42.553826 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10342 09:28:42.557130 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10343 09:28:42.566993 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10344 09:28:42.576599 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10345 09:28:42.589909 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10346 09:28:42.596421 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10347 09:28:42.605876 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10348 09:28:42.619421 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10349 09:28:42.625947 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10350 09:28:42.632447 <6>[ 0.009236] Console: colour dummy device 80x25
10351 09:28:42.642661 <6>[ 0.013961] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10352 09:28:42.649094 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10353 09:28:42.652383 <6>[ 0.029267] LSM: Security Framework initializing
10354 09:28:42.659124 <6>[ 0.034203] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10355 09:28:42.669303 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10356 09:28:42.675893 <6>[ 0.051420] cblist_init_generic: Setting adjustable number of callback queues.
10357 09:28:42.682418 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10358 09:28:42.692337 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10359 09:28:42.695817 <6>[ 0.072674] cblist_init_generic: Setting shift to 3 and lim to 1.
10360 09:28:42.702193 <6>[ 0.079074] rcu: Hierarchical SRCU implementation.
10361 09:28:42.709223 <6>[ 0.084121] rcu: Max phase no-delay instances is 1000.
10362 09:28:42.715981 <6>[ 0.091153] EFI services will not be available.
10363 09:28:42.718922 <6>[ 0.096091] smp: Bringing up secondary CPUs ...
10364 09:28:42.726988 <6>[ 0.101141] Detected VIPT I-cache on CPU1
10365 09:28:42.733379 <6>[ 0.101209] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10366 09:28:42.739955 <6>[ 0.101239] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10367 09:28:42.743220 <6>[ 0.101572] Detected VIPT I-cache on CPU2
10368 09:28:42.753364 <6>[ 0.101623] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10369 09:28:42.759942 <6>[ 0.101638] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10370 09:28:42.763255 <6>[ 0.101892] Detected VIPT I-cache on CPU3
10371 09:28:42.769884 <6>[ 0.101937] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10372 09:28:42.776444 <6>[ 0.101951] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10373 09:28:42.779761 <6>[ 0.102254] CPU features: detected: Spectre-v4
10374 09:28:42.786333 <6>[ 0.102260] CPU features: detected: Spectre-BHB
10375 09:28:42.789643 <6>[ 0.102265] Detected PIPT I-cache on CPU4
10376 09:28:42.796199 <6>[ 0.102321] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10377 09:28:42.803151 <6>[ 0.102337] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10378 09:28:42.809694 <6>[ 0.102626] Detected PIPT I-cache on CPU5
10379 09:28:42.816056 <6>[ 0.102687] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10380 09:28:42.822935 <6>[ 0.102704] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10381 09:28:42.826195 <6>[ 0.102985] Detected PIPT I-cache on CPU6
10382 09:28:42.832804 <6>[ 0.103049] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10383 09:28:42.839362 <6>[ 0.103066] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10384 09:28:42.845829 <6>[ 0.103360] Detected PIPT I-cache on CPU7
10385 09:28:42.852531 <6>[ 0.103424] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10386 09:28:42.859432 <6>[ 0.103440] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10387 09:28:42.862336 <6>[ 0.103487] smp: Brought up 1 node, 8 CPUs
10388 09:28:42.869350 <6>[ 0.244985] SMP: Total of 8 processors activated.
10389 09:28:42.872636 <6>[ 0.249906] CPU features: detected: 32-bit EL0 Support
10390 09:28:42.882522 <6>[ 0.255268] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10391 09:28:42.889271 <6>[ 0.264124] CPU features: detected: Common not Private translations
10392 09:28:42.895932 <6>[ 0.270599] CPU features: detected: CRC32 instructions
10393 09:28:42.899191 <6>[ 0.275984] CPU features: detected: RCpc load-acquire (LDAPR)
10394 09:28:42.905525 <6>[ 0.281981] CPU features: detected: LSE atomic instructions
10395 09:28:42.912350 <6>[ 0.287762] CPU features: detected: Privileged Access Never
10396 09:28:42.918895 <6>[ 0.293542] CPU features: detected: RAS Extension Support
10397 09:28:42.925637 <6>[ 0.299150] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10398 09:28:42.929140 <6>[ 0.306369] CPU: All CPU(s) started at EL2
10399 09:28:42.935452 <6>[ 0.310713] alternatives: applying system-wide alternatives
10400 09:28:42.944772 <6>[ 0.321421] devtmpfs: initialized
10401 09:28:42.957187 <6>[ 0.330606] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10402 09:28:42.967328 <6>[ 0.340567] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10403 09:28:42.973695 <6>[ 0.348587] pinctrl core: initialized pinctrl subsystem
10404 09:28:42.976933 <6>[ 0.355225] DMI not present or invalid.
10405 09:28:42.983865 <6>[ 0.359634] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10406 09:28:42.993587 <6>[ 0.366509] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10407 09:28:43.000304 <6>[ 0.374086] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10408 09:28:43.010327 <6>[ 0.382310] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10409 09:28:43.013401 <6>[ 0.390550] audit: initializing netlink subsys (disabled)
10410 09:28:43.023282 <5>[ 0.396239] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10411 09:28:43.030216 <6>[ 0.396936] thermal_sys: Registered thermal governor 'step_wise'
10412 09:28:43.036704 <6>[ 0.404202] thermal_sys: Registered thermal governor 'power_allocator'
10413 09:28:43.040165 <6>[ 0.410459] cpuidle: using governor menu
10414 09:28:43.046670 <6>[ 0.421420] NET: Registered PF_QIPCRTR protocol family
10415 09:28:43.053073 <6>[ 0.426898] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10416 09:28:43.056457 <6>[ 0.434002] ASID allocator initialised with 32768 entries
10417 09:28:43.063864 <6>[ 0.440566] Serial: AMBA PL011 UART driver
10418 09:28:43.072616 <4>[ 0.449326] Trying to register duplicate clock ID: 134
10419 09:28:43.127363 <6>[ 0.507217] KASLR enabled
10420 09:28:43.141380 <6>[ 0.514950] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10421 09:28:43.148375 <6>[ 0.521964] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10422 09:28:43.154867 <6>[ 0.528454] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10423 09:28:43.161853 <6>[ 0.535459] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10424 09:28:43.167866 <6>[ 0.541947] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10425 09:28:43.174599 <6>[ 0.548952] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10426 09:28:43.181287 <6>[ 0.555439] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10427 09:28:43.187724 <6>[ 0.562443] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10428 09:28:43.191033 <6>[ 0.569964] ACPI: Interpreter disabled.
10429 09:28:43.199833 <6>[ 0.576381] iommu: Default domain type: Translated
10430 09:28:43.206076 <6>[ 0.581493] iommu: DMA domain TLB invalidation policy: strict mode
10431 09:28:43.209702 <5>[ 0.588147] SCSI subsystem initialized
10432 09:28:43.216358 <6>[ 0.592316] usbcore: registered new interface driver usbfs
10433 09:28:43.222764 <6>[ 0.598049] usbcore: registered new interface driver hub
10434 09:28:43.226215 <6>[ 0.603601] usbcore: registered new device driver usb
10435 09:28:43.233040 <6>[ 0.609698] pps_core: LinuxPPS API ver. 1 registered
10436 09:28:43.242899 <6>[ 0.614892] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10437 09:28:43.246373 <6>[ 0.624233] PTP clock support registered
10438 09:28:43.249330 <6>[ 0.628476] EDAC MC: Ver: 3.0.0
10439 09:28:43.256772 <6>[ 0.633617] FPGA manager framework
10440 09:28:43.263679 <6>[ 0.637296] Advanced Linux Sound Architecture Driver Initialized.
10441 09:28:43.266999 <6>[ 0.644075] vgaarb: loaded
10442 09:28:43.273413 <6>[ 0.647237] clocksource: Switched to clocksource arch_sys_counter
10443 09:28:43.276756 <5>[ 0.653667] VFS: Disk quotas dquot_6.6.0
10444 09:28:43.283585 <6>[ 0.657854] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10445 09:28:43.286848 <6>[ 0.665043] pnp: PnP ACPI: disabled
10446 09:28:43.294842 <6>[ 0.671722] NET: Registered PF_INET protocol family
10447 09:28:43.304997 <6>[ 0.677308] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10448 09:28:43.316110 <6>[ 0.689599] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10449 09:28:43.326215 <6>[ 0.698412] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10450 09:28:43.332672 <6>[ 0.706384] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10451 09:28:43.342414 <6>[ 0.715085] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10452 09:28:43.349387 <6>[ 0.724835] TCP: Hash tables configured (established 65536 bind 65536)
10453 09:28:43.355809 <6>[ 0.731691] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10454 09:28:43.365378 <6>[ 0.738889] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10455 09:28:43.372256 <6>[ 0.746581] NET: Registered PF_UNIX/PF_LOCAL protocol family
10456 09:28:43.378537 <6>[ 0.752752] RPC: Registered named UNIX socket transport module.
10457 09:28:43.381891 <6>[ 0.758902] RPC: Registered udp transport module.
10458 09:28:43.385263 <6>[ 0.763833] RPC: Registered tcp transport module.
10459 09:28:43.391834 <6>[ 0.768765] RPC: Registered tcp NFSv4.1 backchannel transport module.
10460 09:28:43.398391 <6>[ 0.775434] PCI: CLS 0 bytes, default 64
10461 09:28:43.401808 <6>[ 0.779821] Unpacking initramfs...
10462 09:28:43.418399 <6>[ 0.791826] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10463 09:28:43.428287 <6>[ 0.800460] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10464 09:28:43.431830 <6>[ 0.809315] kvm [1]: IPA Size Limit: 40 bits
10465 09:28:43.438302 <6>[ 0.813844] kvm [1]: GICv3: no GICV resource entry
10466 09:28:43.441593 <6>[ 0.818863] kvm [1]: disabling GICv2 emulation
10467 09:28:43.448502 <6>[ 0.823549] kvm [1]: GIC system register CPU interface enabled
10468 09:28:43.451392 <6>[ 0.829717] kvm [1]: vgic interrupt IRQ18
10469 09:28:43.458052 <6>[ 0.834073] kvm [1]: VHE mode initialized successfully
10470 09:28:43.464769 <5>[ 0.840506] Initialise system trusted keyrings
10471 09:28:43.471286 <6>[ 0.845302] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10472 09:28:43.478451 <6>[ 0.855331] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10473 09:28:43.485396 <5>[ 0.861799] NFS: Registering the id_resolver key type
10474 09:28:43.488547 <5>[ 0.867103] Key type id_resolver registered
10475 09:28:43.495170 <5>[ 0.871518] Key type id_legacy registered
10476 09:28:43.501639 <6>[ 0.875795] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10477 09:28:43.508235 <6>[ 0.882714] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10478 09:28:43.514700 <6>[ 0.890461] 9p: Installing v9fs 9p2000 file system support
10479 09:28:43.551243 <5>[ 0.928078] Key type asymmetric registered
10480 09:28:43.554830 <5>[ 0.932412] Asymmetric key parser 'x509' registered
10481 09:28:43.565057 <6>[ 0.937584] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10482 09:28:43.567849 <6>[ 0.945198] io scheduler mq-deadline registered
10483 09:28:43.571316 <6>[ 0.949983] io scheduler kyber registered
10484 09:28:43.590043 <6>[ 0.966956] EINJ: ACPI disabled.
10485 09:28:43.622354 <4>[ 0.992453] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10486 09:28:43.632315 <4>[ 1.003081] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10487 09:28:43.646970 <6>[ 1.023771] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10488 09:28:43.655028 <6>[ 1.031826] printk: console [ttyS0] disabled
10489 09:28:43.683231 <6>[ 1.056472] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10490 09:28:43.689557 <6>[ 1.065952] printk: console [ttyS0] enabled
10491 09:28:43.693108 <6>[ 1.065952] printk: console [ttyS0] enabled
10492 09:28:43.699764 <6>[ 1.074843] printk: bootconsole [mtk8250] disabled
10493 09:28:43.703071 <6>[ 1.074843] printk: bootconsole [mtk8250] disabled
10494 09:28:43.709529 <6>[ 1.086075] SuperH (H)SCI(F) driver initialized
10495 09:28:43.712972 <6>[ 1.091390] msm_serial: driver initialized
10496 09:28:43.726766 <6>[ 1.100350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10497 09:28:43.736933 <6>[ 1.108900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10498 09:28:43.743305 <6>[ 1.117442] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10499 09:28:43.753270 <6>[ 1.126070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10500 09:28:43.763348 <6>[ 1.134777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10501 09:28:43.769930 <6>[ 1.143491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10502 09:28:43.779880 <6>[ 1.152031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10503 09:28:43.786474 <6>[ 1.160847] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10504 09:28:43.796192 <6>[ 1.169396] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10505 09:28:43.808040 <6>[ 1.185011] loop: module loaded
10506 09:28:43.814581 <6>[ 1.190991] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10507 09:28:43.837372 <4>[ 1.214216] mtk-pmic-keys: Failed to locate of_node [id: -1]
10508 09:28:43.844198 <6>[ 1.221024] megasas: 07.719.03.00-rc1
10509 09:28:43.853601 <6>[ 1.230568] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10510 09:28:43.862298 <6>[ 1.238623] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10511 09:28:43.878766 <6>[ 1.255295] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10512 09:28:43.935453 <6>[ 1.305381] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10513 09:28:44.304315 <6>[ 1.681332] Freeing initrd memory: 20884K
10514 09:28:44.320197 <6>[ 1.697004] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10515 09:28:44.331602 <6>[ 1.707881] tun: Universal TUN/TAP device driver, 1.6
10516 09:28:44.334654 <6>[ 1.713931] thunder_xcv, ver 1.0
10517 09:28:44.337487 <6>[ 1.717433] thunder_bgx, ver 1.0
10518 09:28:44.341108 <6>[ 1.720932] nicpf, ver 1.0
10519 09:28:44.351537 <6>[ 1.724941] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10520 09:28:44.354851 <6>[ 1.732418] hns3: Copyright (c) 2017 Huawei Corporation.
10521 09:28:44.358327 <6>[ 1.738010] hclge is initializing
10522 09:28:44.365256 <6>[ 1.741592] e1000: Intel(R) PRO/1000 Network Driver
10523 09:28:44.371579 <6>[ 1.746721] e1000: Copyright (c) 1999-2006 Intel Corporation.
10524 09:28:44.374992 <6>[ 1.752734] e1000e: Intel(R) PRO/1000 Network Driver
10525 09:28:44.381735 <6>[ 1.757949] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10526 09:28:44.388068 <6>[ 1.764135] igb: Intel(R) Gigabit Ethernet Network Driver
10527 09:28:44.395059 <6>[ 1.769784] igb: Copyright (c) 2007-2014 Intel Corporation.
10528 09:28:44.401464 <6>[ 1.775620] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10529 09:28:44.404984 <6>[ 1.782138] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10530 09:28:44.411845 <6>[ 1.788599] sky2: driver version 1.30
10531 09:28:44.418336 <6>[ 1.793586] VFIO - User Level meta-driver version: 0.3
10532 09:28:44.424860 <6>[ 1.801826] usbcore: registered new interface driver usb-storage
10533 09:28:44.431646 <6>[ 1.808270] usbcore: registered new device driver onboard-usb-hub
10534 09:28:44.440339 <6>[ 1.817339] mt6397-rtc mt6359-rtc: registered as rtc0
10535 09:28:44.450433 <6>[ 1.822802] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:28:23 UTC (1697794103)
10536 09:28:44.454000 <6>[ 1.832364] i2c_dev: i2c /dev entries driver
10537 09:28:44.470710 <6>[ 1.844011] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10538 09:28:44.490309 <6>[ 1.866991] cpu cpu0: EM: created perf domain
10539 09:28:44.493584 <6>[ 1.871917] cpu cpu4: EM: created perf domain
10540 09:28:44.500592 <6>[ 1.877500] sdhci: Secure Digital Host Controller Interface driver
10541 09:28:44.507425 <6>[ 1.883932] sdhci: Copyright(c) Pierre Ossman
10542 09:28:44.514386 <6>[ 1.888885] Synopsys Designware Multimedia Card Interface Driver
10543 09:28:44.520878 <6>[ 1.895520] sdhci-pltfm: SDHCI platform and OF driver helper
10544 09:28:44.523786 <6>[ 1.895655] mmc0: CQHCI version 5.10
10545 09:28:44.530828 <6>[ 1.905498] ledtrig-cpu: registered to indicate activity on CPUs
10546 09:28:44.537227 <6>[ 1.912511] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10547 09:28:44.543990 <6>[ 1.919580] usbcore: registered new interface driver usbhid
10548 09:28:44.547142 <6>[ 1.925403] usbhid: USB HID core driver
10549 09:28:44.553880 <6>[ 1.929593] spi_master spi0: will run message pump with realtime priority
10550 09:28:44.599088 <6>[ 1.968936] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10551 09:28:44.618775 <6>[ 1.985630] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10552 09:28:44.622210 <6>[ 1.999281] mmc0: Command Queue Engine enabled
10553 09:28:44.629229 <6>[ 2.004050] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10554 09:28:44.635839 <6>[ 2.011245] cros-ec-spi spi0.0: Chrome EC device registered
10555 09:28:44.638856 <6>[ 2.011608] mmcblk0: mmc0:0001 DA4128 116 GiB
10556 09:28:44.650121 <6>[ 2.027091] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10557 09:28:44.657977 <6>[ 2.034902] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10558 09:28:44.664900 <6>[ 2.040791] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10559 09:28:44.671635 <6>[ 2.046919] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10560 09:28:44.684904 <6>[ 2.058610] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10561 09:28:44.692648 <6>[ 2.069439] NET: Registered PF_PACKET protocol family
10562 09:28:44.695909 <6>[ 2.074892] 9pnet: Installing 9P2000 support
10563 09:28:44.702476 <5>[ 2.079482] Key type dns_resolver registered
10564 09:28:44.705889 <6>[ 2.084636] registered taskstats version 1
10565 09:28:44.712426 <5>[ 2.089055] Loading compiled-in X.509 certificates
10566 09:28:44.742686 <4>[ 2.112833] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 09:28:44.752657 <4>[ 2.123673] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 09:28:44.759292 <3>[ 2.134259] debugfs: File 'uA_load' in directory '/' already present!
10569 09:28:44.765714 <3>[ 2.140965] debugfs: File 'min_uV' in directory '/' already present!
10570 09:28:44.772330 <3>[ 2.147576] debugfs: File 'max_uV' in directory '/' already present!
10571 09:28:44.779021 <3>[ 2.154186] debugfs: File 'constraint_flags' in directory '/' already present!
10572 09:28:44.790307 <3>[ 2.163940] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10573 09:28:44.804257 <6>[ 2.180984] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10574 09:28:44.811145 <6>[ 2.187804] xhci-mtk 11200000.usb: xHCI Host Controller
10575 09:28:44.817557 <6>[ 2.193320] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10576 09:28:44.827858 <6>[ 2.201198] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10577 09:28:44.834475 <6>[ 2.210650] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10578 09:28:44.840845 <6>[ 2.216762] xhci-mtk 11200000.usb: xHCI Host Controller
10579 09:28:44.848099 <6>[ 2.222263] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10580 09:28:44.854095 <6>[ 2.229925] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10581 09:28:44.861209 <6>[ 2.237954] hub 1-0:1.0: USB hub found
10582 09:28:44.864644 <6>[ 2.241986] hub 1-0:1.0: 1 port detected
10583 09:28:44.874412 <6>[ 2.246307] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10584 09:28:44.877827 <6>[ 2.255155] hub 2-0:1.0: USB hub found
10585 09:28:44.881073 <6>[ 2.259185] hub 2-0:1.0: 1 port detected
10586 09:28:44.890676 <6>[ 2.267421] mtk-msdc 11f70000.mmc: Got CD GPIO
10587 09:28:44.900272 <6>[ 2.273975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10588 09:28:44.907004 <6>[ 2.282033] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10589 09:28:44.917386 <4>[ 2.289952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10590 09:28:44.926864 <6>[ 2.299522] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10591 09:28:44.933794 <6>[ 2.307606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10592 09:28:44.940329 <6>[ 2.315621] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10593 09:28:44.950229 <6>[ 2.323545] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10594 09:28:44.956685 <6>[ 2.331363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10595 09:28:44.966665 <6>[ 2.339180] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10596 09:28:44.976649 <6>[ 2.349464] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10597 09:28:44.983270 <6>[ 2.357843] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10598 09:28:44.993427 <6>[ 2.366184] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10599 09:28:44.999839 <6>[ 2.374523] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10600 09:28:45.009899 <6>[ 2.382861] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10601 09:28:45.016347 <6>[ 2.391208] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10602 09:28:45.026254 <6>[ 2.399545] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10603 09:28:45.033210 <6>[ 2.407884] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10604 09:28:45.043017 <6>[ 2.416223] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10605 09:28:45.049836 <6>[ 2.424561] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10606 09:28:45.059588 <6>[ 2.432899] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10607 09:28:45.066261 <6>[ 2.441237] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10608 09:28:45.075968 <6>[ 2.449576] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10609 09:28:45.082633 <6>[ 2.457914] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10610 09:28:45.092706 <6>[ 2.466252] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10611 09:28:45.099215 <6>[ 2.474996] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10612 09:28:45.105888 <6>[ 2.482197] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10613 09:28:45.112817 <6>[ 2.489016] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10614 09:28:45.119201 <6>[ 2.495789] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10615 09:28:45.129526 <6>[ 2.502727] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10616 09:28:45.135974 <6>[ 2.509507] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10617 09:28:45.146058 <6>[ 2.518633] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10618 09:28:45.155863 <6>[ 2.527753] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10619 09:28:45.165620 <6>[ 2.537048] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10620 09:28:45.175251 <6>[ 2.546516] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10621 09:28:45.181864 <6>[ 2.555983] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10622 09:28:45.191695 <6>[ 2.565104] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10623 09:28:45.201916 <6>[ 2.574571] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10624 09:28:45.211960 <6>[ 2.583690] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10625 09:28:45.221663 <6>[ 2.592986] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10626 09:28:45.231551 <6>[ 2.603149] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10627 09:28:45.241446 <6>[ 2.614665] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10628 09:28:45.293751 <6>[ 2.667508] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10629 09:28:45.448686 <6>[ 2.825391] hub 1-1:1.0: USB hub found
10630 09:28:45.451760 <6>[ 2.829932] hub 1-1:1.0: 4 ports detected
10631 09:28:45.573925 <6>[ 2.947850] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10632 09:28:45.600549 <6>[ 2.977391] hub 2-1:1.0: USB hub found
10633 09:28:45.603901 <6>[ 2.981914] hub 2-1:1.0: 3 ports detected
10634 09:28:45.774120 <6>[ 3.147535] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10635 09:28:45.906542 <6>[ 3.283499] hub 1-1.4:1.0: USB hub found
10636 09:28:45.909867 <6>[ 3.288174] hub 1-1.4:1.0: 2 ports detected
10637 09:28:45.990007 <6>[ 3.363798] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10638 09:28:46.209887 <6>[ 3.583556] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10639 09:28:46.401712 <6>[ 3.775565] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10640 09:28:57.515017 <6>[ 14.896529] ALSA device list:
10641 09:28:57.521408 <6>[ 14.899821] No soundcards found.
10642 09:28:57.529443 <6>[ 14.907776] Freeing unused kernel memory: 8384K
10643 09:28:57.532554 <6>[ 14.912799] Run /init as init process
10644 09:28:57.567382 Starting syslogd: OK
10645 09:28:57.571859 Starting klogd: OK
10646 09:28:57.580559 Running sysctl: OK
10647 09:28:57.587387 Populating /dev using udev: <30>[ 14.967710] udevd[184]: starting version 3.2.9
10648 09:28:57.595901 <27>[ 14.974565] udevd[184]: specified user 'tss' unknown
10649 09:28:57.602694 <27>[ 14.980009] udevd[184]: specified group 'tss' unknown
10650 09:28:57.606157 <30>[ 14.986191] udevd[185]: starting eudev-3.2.9
10651 09:28:57.624228 <27>[ 15.002866] udevd[185]: specified user 'tss' unknown
10652 09:28:57.631119 <27>[ 15.008264] udevd[185]: specified group 'tss' unknown
10653 09:28:57.733676 <6>[ 15.108606] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10654 09:28:57.743513 <6>[ 15.116552] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10655 09:28:57.749957 <6>[ 15.126045] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10656 09:28:57.797257 <6>[ 15.172374] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10657 09:28:57.800406 <6>[ 15.179533] mc: Linux media interface: v0.10
10658 09:28:57.813332 <6>[ 15.191918] remoteproc remoteproc0: scp is available
10659 09:28:57.820332 <6>[ 15.197380] remoteproc remoteproc0: powering up scp
10660 09:28:57.823710 <6>[ 15.199327] videodev: Linux video capture interface: v2.00
10661 09:28:57.833252 <6>[ 15.202519] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10662 09:28:57.840302 <6>[ 15.216710] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10663 09:28:57.855753 <3>[ 15.230897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 09:28:57.862729 <4>[ 15.231456] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10665 09:28:57.872497 <3>[ 15.239051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 09:28:57.879290 <4>[ 15.247727] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10667 09:28:57.885682 <6>[ 15.251453] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10668 09:28:57.892162 <3>[ 15.254468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 09:28:57.899085 <6>[ 15.259766] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10670 09:28:57.905572 <6>[ 15.259771] pci_bus 0000:00: root bus resource [bus 00-ff]
10671 09:28:57.912497 <6>[ 15.259776] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10672 09:28:57.922197 <6>[ 15.259778] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10673 09:28:57.928417 <6>[ 15.259804] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10674 09:28:57.935182 <6>[ 15.259817] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10675 09:28:57.941732 <6>[ 15.259888] pci 0000:00:00.0: supports D1 D2
10676 09:28:57.948216 <6>[ 15.259890] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10677 09:28:57.955136 <6>[ 15.260797] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10678 09:28:57.961745 <6>[ 15.260872] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10679 09:28:57.971928 <6>[ 15.260896] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10680 09:28:57.978231 <6>[ 15.260913] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10681 09:28:57.984778 <6>[ 15.260928] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10682 09:28:57.988203 <6>[ 15.261031] pci 0000:01:00.0: supports D1 D2
10683 09:28:57.997793 <6>[ 15.261032] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10684 09:28:58.004746 <6>[ 15.268144] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 09:28:58.011378 <3>[ 15.268971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 09:28:58.017709 <6>[ 15.271415] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10687 09:28:58.028054 <6>[ 15.271456] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10688 09:28:58.034734 <6>[ 15.271460] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10689 09:28:58.044995 <6>[ 15.271468] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10690 09:28:58.051895 <6>[ 15.271481] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10691 09:28:58.058133 <6>[ 15.271494] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10692 09:28:58.065025 <6>[ 15.271506] pci 0000:00:00.0: PCI bridge to [bus 01]
10693 09:28:58.072480 <6>[ 15.271511] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10694 09:28:58.079352 <6>[ 15.271690] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10695 09:28:58.085691 <6>[ 15.272288] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10696 09:28:58.095465 <4>[ 15.274834] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10697 09:28:58.102124 <4>[ 15.274845] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10698 09:28:58.108960 <6>[ 15.275532] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10699 09:28:58.118383 <6>[ 15.327799] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10700 09:28:58.121897 <6>[ 15.331404] r8152 2-1.3:1.0 eth0: v1.12.13
10701 09:28:58.128604 <6>[ 15.331874] usbcore: registered new interface driver r8152
10702 09:28:58.134950 <3>[ 15.333870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 09:28:58.144948 <3>[ 15.333882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 09:28:58.151696 <3>[ 15.333887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 09:28:58.162030 <3>[ 15.333892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 09:28:58.168367 <3>[ 15.333960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 09:28:58.178259 <3>[ 15.334007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 09:28:58.184662 <3>[ 15.334010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 09:28:58.191427 <3>[ 15.334012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 09:28:58.201236 <3>[ 15.334081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 09:28:58.207785 <3>[ 15.334085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 09:28:58.217960 <3>[ 15.334089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 09:28:58.224382 <3>[ 15.334096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 09:28:58.234337 <3>[ 15.334101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 09:28:58.241081 <3>[ 15.334117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 09:28:58.251156 <6>[ 15.340609] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10717 09:28:58.257484 <6>[ 15.347765] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10718 09:28:58.267732 <6>[ 15.347778] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10719 09:28:58.274204 <4>[ 15.373067] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10720 09:28:58.280643 <4>[ 15.373067] Fallback method does not support PEC.
10721 09:28:58.287689 <6>[ 15.373202] remoteproc remoteproc0: remote processor scp is now up
10722 09:28:58.294320 <6>[ 15.377803] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10723 09:28:58.300787 <6>[ 15.404761] Bluetooth: Core ver 2.22
10724 09:28:58.304317 <6>[ 15.405627] usbcore: registered new interface driver cdc_ether
10725 09:28:58.313896 <6>[ 15.414845] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10726 09:28:58.317237 <6>[ 15.419158] NET: Registered PF_BLUETOOTH protocol family
10727 09:28:58.323710 <6>[ 15.421462] usbcore: registered new interface driver r8153_ecm
10728 09:28:58.333956 <5>[ 15.422886] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10729 09:28:58.340420 <6>[ 15.428391] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10730 09:28:58.353516 <6>[ 15.429016] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10731 09:28:58.360136 <6>[ 15.429222] usbcore: registered new interface driver uvcvideo
10732 09:28:58.367297 <3>[ 15.430294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 09:28:58.373403 <6>[ 15.435093] Bluetooth: HCI device and connection manager initialized
10734 09:28:58.379878 <6>[ 15.435142] Bluetooth: HCI socket layer initialized
10735 09:28:58.386776 <6>[ 15.445164] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10736 09:28:58.393133 <6>[ 15.448343] Bluetooth: L2CAP socket layer initialized
10737 09:28:58.399906 <5>[ 15.449332] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10738 09:28:58.409717 <4>[ 15.449466] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10739 09:28:58.413105 <6>[ 15.449476] cfg80211: failed to load regulatory.db
10740 09:28:58.423240 <3>[ 15.462680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10741 09:28:58.426805 <6>[ 15.468767] Bluetooth: SCO socket layer initialized
10742 09:28:58.433117 <6>[ 15.476031] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10743 09:28:58.439927 <6>[ 15.546807] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10744 09:28:58.446249 <6>[ 15.617547] usbcore: registered new interface driver btusb
10745 09:28:58.456001 <4>[ 15.618426] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10746 09:28:58.462610 <3>[ 15.618433] Bluetooth: hci0: Failed to load firmware file (-2)
10747 09:28:58.469454 <3>[ 15.618434] Bluetooth: hci0: Failed to set up firmware (-2)
10748 09:28:58.479143 <4>[ 15.618437] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10749 09:28:58.485984 <6>[ 15.625406] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10750 09:28:58.509060 <6>[ 15.887405] mt7921e 0000:01:00.0: ASIC revision: 79610010
10751 09:28:58.615740 <4>[ 15.987649] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 09:28:58.615884 done
10753 09:28:58.637224 Saving random seed: OK
10754 09:28:58.653133 Starting network: OK
10755 09:28:58.695168 Starting dropbear sshd: <6>[ 16.073914] NET: Registered PF_INET6 protocol family
10756 09:28:58.702341 <6>[ 16.080794] Segment Routing with IPv6
10757 09:28:58.705604 <6>[ 16.084731] In-situ OAM (IOAM) with IPv6
10758 09:28:58.708948 OK
10759 09:28:58.721465 /bin/sh: can't access tty; job control turned off
10760 09:28:58.721803 Matched prompt #10: / #
10762 09:28:58.722015 Setting prompt string to ['/ #']
10763 09:28:58.722107 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10765 09:28:58.722300 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10766 09:28:58.722387 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10767 09:28:58.722457 Setting prompt string to ['/ #']
10768 09:28:58.722532 Forcing a shell prompt, looking for ['/ #']
10770 09:28:58.772777 / #
10771 09:28:58.773011 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10772 09:28:58.773134 Waiting using forced prompt support (timeout 00:02:30)
10773 09:28:58.773236 <4>[ 16.110412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 09:28:58.778675
10775 09:28:58.778969 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10776 09:28:58.779071 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10777 09:28:58.779166 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10778 09:28:58.779257 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10779 09:28:58.779345 end: 2 depthcharge-action (duration 00:01:15) [common]
10780 09:28:58.779431 start: 3 lava-test-retry (timeout 00:01:00) [common]
10781 09:28:58.779515 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10782 09:28:58.779589 Using namespace: common
10784 09:28:58.879952 / # #
10785 09:28:58.880131 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10786 09:28:58.880255 #<4>[ 16.230120] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 09:28:58.885618
10788 09:28:58.885922 Using /lava-11826788
10790 09:28:58.986364 / # export SHELL=/bin/sh
10791 09:28:58.986553 export SHELL=/bin/sh<4>[ 16.349722] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 09:28:58.992029
10794 09:28:59.092520 / # . /lava-11826788/environment
10795 09:28:59.137043 . /lava-11826788/environment<4>[ 16.470031] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 09:28:59.137202
10798 09:28:59.237707 / # /lava-11826788/bin/lava-test-runner /lava-11826788/0
10799 09:28:59.237878 Test shell timeout: 10s (minimum of the action and connection timeout)
10800 09:28:59.238254 /lava-11826788/bin/lava-test-runner /lava-11826788/0<4>[ 16.590085] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 09:28:59.242618
10802 09:28:59.285032 + export 'TESTRUN_ID=0_dmesg'
10803 09:28:59.285198 +<8>[ 16.648084] <LAVA_SIGNAL_STARTRUN 0_dmesg 11826788_1.5.2.3.1>
10804 09:28:59.285274 cd /lava-11826788/0/tests/0_dmesg
10805 09:28:59.285370 + cat uuid
10806 09:28:59.285655 Received signal: <STARTRUN> 0_dmesg 11826788_1.5.2.3.1
10807 09:28:59.285748 Starting test lava.0_dmesg (11826788_1.5.2.3.1)
10808 09:28:59.285867 Skipping test definition patterns.
10809 09:28:59.286008 + UUID=11826788_1.5.2.3.1
10810 09:28:59.286106 + set +x
10811 09:28:59.286171 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10812 09:28:59.293319 <8>[ 16.667380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10813 09:28:59.293577 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10815 09:28:59.312521 <8>[ 16.687524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10816 09:28:59.312812 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10818 09:28:59.340132 <4>[ 16.711937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 09:28:59.346580 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10821 09:28:59.349880 <8>[ 16.717943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10822 09:28:59.353074 + set +x
10823 09:28:59.356677 Received signal: <ENDRUN> 0_dmesg 11826788_1.5.2.3.1
10824 09:28:59.356777 Ending use of test pattern.
10825 09:28:59.356845 Ending test lava.0_dmesg (11826788_1.5.2.3.1), duration 0.07
10827 09:28:59.359948 <8>[ 16.735174] <LAVA_SIGNAL_ENDRUN 0_dmesg 11826788_1.5.2.3.1>
10828 09:28:59.360034 <LAVA_TEST_RUNNER EXIT>
10829 09:28:59.360270 ok: lava_test_shell seems to have completed
10830 09:28:59.360373 alert: pass
crit: pass
emerg: pass
10831 09:28:59.360464 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10832 09:28:59.360551 end: 3 lava-test-retry (duration 00:00:01) [common]
10833 09:28:59.360637 start: 4 lava-test-retry (timeout 00:01:00) [common]
10834 09:28:59.360721 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10835 09:28:59.360789 Using namespace: common
10837 09:28:59.461128 /#
10838 09:28:59.461304 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10839 09:28:59.461424 # #<4>[ 16.830004] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 09:28:59.461697 Using /lava-11826788
10842 09:28:59.562014 export SHELL=/bin/sh
10843 09:28:59.562217
10845 09:28:59.662717 / # export SHELL=/bin/sh. /lava-11826788/environment
10846 09:28:59.662910
10847 09:28:59.662988 / # <4>[ 16.950065] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10849 09:28:59.763465 . /lava-11826788/environment/lava-11826788/bin/lava-test-runner /lava-11826788/1
10850 09:28:59.763634 Test shell timeout: 10s (minimum of the action and connection timeout)
10851 09:28:59.763756
10852 09:28:59.763824 / # <4>[ 17.070022] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 09:28:59.768543 /lava-11826788/bin/lava-test-runner /lava-11826788/1
10854 09:28:59.809099 + export 'TESTRUN_ID=1_bootrr'
10855 09:28:59.809258 <8>[ 17.172427] <LAVA_SIGNAL_STARTRUN 1_bootrr 11826788_1.5.2.3.5>
10856 09:28:59.809332 + cd /lava-11826788/1/tests/1_bootrr
10857 09:28:59.809395 + cat uuid
10858 09:28:59.809456 + UUID=11826788_1.5.2.3.5
10859 09:28:59.809516 + set +x
10860 09:28:59.809754 Received signal: <STARTRUN> 1_bootrr 11826788_1.5.2.3.5
10861 09:28:59.809821 Starting test lava.1_bootrr (11826788_1.5.2.3.5)
10862 09:28:59.809898 Skipping test definition patterns.
10863 09:28:59.811319 + export 'PATH=/opt/bootrr/libexec/bootrr<3>[ 17.189609] mt7921e 0000:01:00.0: hardware init failed
10864 09:28:59.817584 /helpers:/lava-11826788/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10865 09:28:59.820902 + cd /opt/bootrr/libexec/bootrr
10866 09:28:59.828300 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10868 09:28:59.831259 + sh helpers/b<8>[ 17.205527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10869 09:28:59.831355 ootrr-auto
10870 09:28:59.834217 /lava-11826788/1/../bin/lava-test-case
10871 09:28:59.843185 /lava-11826788/1/../bin/lava-test-case
10872 09:28:59.849573 <8>[ 17.225528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10873 09:28:59.849827 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10875 09:28:59.856270 /usr/bin/tpm2_getcap
10876 09:28:59.888277 /lava-11826788/1/../bin/lava-test-case
10877 09:28:59.894722 <8>[ 17.270665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10878 09:28:59.894997 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10880 09:28:59.914788 /lava-11826788/1/../bin/lava-test-case
10881 09:28:59.921757 <8>[ 17.298131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10882 09:28:59.922014 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10884 09:28:59.933819 /lava-11826788/1/../bin/lava-test-case
10885 09:28:59.940362 <8>[ 17.316489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10886 09:28:59.940618 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10888 09:28:59.953888 /lava-11826788/1/../bin/lava-test-case
10889 09:28:59.960284 <8>[ 17.336205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10890 09:28:59.960541 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10892 09:28:59.972905 /lava-11826788/1/../bin/lava-test-case
10893 09:28:59.979370 <8>[ 17.354844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10894 09:28:59.979653 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10896 09:28:59.991797 /lava-11826788/1/../bin/lava-test-case
10897 09:28:59.998259 <8>[ 17.374323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10898 09:28:59.998518 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10900 09:29:00.008063 /lava-11826788/1/../bin/lava-test-case
10901 09:29:00.015071 <8>[ 17.389853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10902 09:29:00.015352 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10904 09:29:00.027186 /lava-11826788/1/../bin/lava-test-case
10905 09:29:00.033778 <8>[ 17.409414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10906 09:29:00.034035 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10908 09:29:00.043482 /lava-11826788/1/../bin/lava-test-case
10909 09:29:00.050105 <8>[ 17.426112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10910 09:29:00.050364 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10912 09:29:00.063221 /lava-11826788/1/../bin/lava-test-case
10913 09:29:00.069672 <8>[ 17.445633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10914 09:29:00.069928 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10916 09:29:00.084945 /lava-11826788/1/../bin/lava-test-case
10917 09:29:00.091954 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10919 09:29:00.094957 <8>[ 17.468399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10920 09:29:00.108885 /lava-11826788/1/../bin/lava-test-case
10921 09:29:00.116061 <8>[ 17.491844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10922 09:29:00.116319 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10924 09:29:00.127406 /lava-11826788/1/../bin/lava-test-case
10925 09:29:00.133891 <8>[ 17.509306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10926 09:29:00.134147 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10928 09:29:00.151503 /lava-11826788/1/../bin/lava-tes<8>[ 17.526134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10929 09:29:00.151617 t-case
10930 09:29:00.151856 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10932 09:29:00.162552 /lava-11826788/1/../bin/lava-test-case
10933 09:29:00.169230 <8>[ 17.544813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10934 09:29:00.169486 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10936 09:29:00.184966 /lava-11826788/1/../bin/lava-tes<8>[ 17.559736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10937 09:29:00.185079 t-case
10938 09:29:00.185317 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10940 09:29:00.195039 /lava-11826788/1/../bin/lava-test-case
10941 09:29:00.201868 <8>[ 17.578890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10942 09:29:00.202146 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10944 09:29:00.211592 /lava-11826788/1/../bin/lava-test-case
10945 09:29:00.218307 <8>[ 17.594531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10946 09:29:00.218568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10948 09:29:00.231125 /lava-11826788/1/../bin/lava-test-case
10949 09:29:00.237659 <8>[ 17.613574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10950 09:29:00.237918 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10952 09:29:00.256487 /lava-11826788/1/../bin/lava-tes<8>[ 17.631047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10953 09:29:00.256580 t-case
10954 09:29:00.256818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10956 09:29:00.267526 /lava-11826788/1/../bin/lava-test-case
10957 09:29:00.274366 <8>[ 17.650729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10958 09:29:00.274634 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10960 09:29:00.284222 /lava-11826788/1/../bin/lava-test-case
10961 09:29:00.294139 <8>[ 17.668841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10962 09:29:00.294428 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10964 09:29:00.303978 /lava-11826788/1/../bin/lava-test-case
10965 09:29:00.310804 <8>[ 17.687536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10966 09:29:00.311403 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10968 09:29:00.323352 /lava-11826788/1/../bin/lava-test-case
10969 09:29:00.329878 <8>[ 17.705941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10970 09:29:00.330488 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10972 09:29:00.338953 /lava-11826788/1/../bin/lava-test-case
10973 09:29:00.345688 <8>[ 17.721874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10974 09:29:00.346299 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10976 09:29:00.359145 /lava-11826788/1/../bin/lava-test-case
10977 09:29:00.365629 <8>[ 17.741599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10978 09:29:00.366340 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10980 09:29:00.374710 /lava-11826788/1/../bin/lava-test-case
10981 09:29:00.381183 <8>[ 17.757758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10982 09:29:00.381900 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10984 09:29:00.395441 /lava-11826788/1/../bin/lava-test-case
10985 09:29:00.402287 <8>[ 17.776767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10986 09:29:00.402991 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10988 09:29:00.413064 /lava-11826788/1/../bin/lava-test-case
10989 09:29:00.420149 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10991 09:29:00.422810 <8>[ 17.796935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10992 09:29:00.434061 /lava-11826788/1/../bin/lava-test-case
10993 09:29:00.440308 <8>[ 17.816070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10994 09:29:00.440702 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10996 09:29:00.451170 /lava-11826788/1/../bin/lava-test-case
10997 09:29:00.457674 <8>[ 17.833907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10998 09:29:00.457934 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11000 09:29:00.468089 /lava-11826788/1/../bin/lava-test-case
11001 09:29:00.474491 <8>[ 17.850568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11002 09:29:00.474746 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11004 09:29:00.485722 /lava-11826788/1/../bin/lava-test-case
11005 09:29:00.495572 <8>[ 17.870432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11006 09:29:00.495826 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11008 09:29:00.505785 /lava-11826788/1/../bin/lava-test-case
11009 09:29:00.511911 <8>[ 17.887972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11010 09:29:00.512165 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11012 09:29:00.520955 /lava-11826788/1/../bin/lava-test-case
11013 09:29:00.527394 <8>[ 17.902628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11014 09:29:00.527648 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11016 09:29:00.540309 /lava-11826788/1/../bin/lava-test-case
11017 09:29:00.546731 <8>[ 17.923626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11018 09:29:00.546986 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11020 09:29:00.557236 /lava-11826788/1/../bin/lava-test-case
11021 09:29:00.623033 <8>[ 17.939070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11022 09:29:00.623209 /lava-11826788/1/../bin/lava-test-case
11023 09:29:00.623317 <8>[ 17.957904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11024 09:29:00.623410 /lava-11826788/1/../bin/lava-test-case
11025 09:29:00.623500 <8>[ 17.973679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11026 09:29:00.623588 /lava-11826788/1/../bin/lava-test-case
11027 09:29:00.623675 <8>[ 17.991312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11028 09:29:00.623925 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11030 09:29:00.624154 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11032 09:29:00.624339 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11034 09:29:00.624521 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11036 09:29:00.632204 /lava-11826788/1/../bin/lava-tes<8>[ 18.006725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11037 09:29:00.632289 t-case
11038 09:29:00.632525 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11040 09:29:00.645312 /lava-11826788/1/../bin/lava-test-case
11041 09:29:00.652220 <8>[ 18.027514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11042 09:29:00.652474 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11044 09:29:00.660906 /lava-11826788/1/../bin/lava-test-case
11045 09:29:00.671414 <8>[ 18.046874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11046 09:29:00.671667 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11048 09:29:00.683716 /lava-11826788/1/../bin/lava-test-case
11049 09:29:00.690547 <8>[ 18.068024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11050 09:29:00.690801 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11052 09:29:00.701833 /lava-11826788/1/../bin/lava-test-case
11053 09:29:00.708413 <8>[ 18.085049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11054 09:29:00.708667 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11056 09:29:00.723268 /lava-11826788/1/../bin/lava-test-case
11057 09:29:00.726136 <8>[ 18.101689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11058 09:29:00.726425 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11060 09:29:00.741357 /lava-11826788/1/../bin/lava-tes<8>[ 18.116464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11061 09:29:00.741611 t-case
11062 09:29:00.741906 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11064 09:29:00.753548 /lava-11826788/1/../bin/lava-test-case
11065 09:29:00.763581 <8>[ 18.138559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11066 09:29:00.763884 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11068 09:29:00.773189 /lava-11826788/1/../bin/lava-test-case
11069 09:29:00.779717 <8>[ 18.156093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11070 09:29:00.780017 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11072 09:29:00.789816 /lava-11826788/1/../bin/lava-test-case
11073 09:29:00.796388 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11075 09:29:00.799706 <8>[ 18.173541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11076 09:29:00.808779 /lava-11826788/1/../bin/lava-test-case
11077 09:29:00.815237 <8>[ 18.191100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11078 09:29:00.815542 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11080 09:29:00.825660 /lava-11826788/1/../bin/lava-test-case
11081 09:29:00.832336 <8>[ 18.208004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11082 09:29:00.832642 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11084 09:29:00.842802 /lava-11826788/1/../bin/lava-test-case
11085 09:29:00.852593 <8>[ 18.227814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11086 09:29:00.852927 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11088 09:29:00.865308 /lava-11826788/1/../bin/lava-test-case
11089 09:29:00.874723 <8>[ 18.249901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11090 09:29:00.874983 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11092 09:29:00.884540 /lava-11826788/1/../bin/lava-test-case
11093 09:29:00.890624 <8>[ 18.266431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11094 09:29:00.890893 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11096 09:29:00.909333 /lava-11826788/1/../bin/lava-tes<8>[ 18.283993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11097 09:29:00.909422 t-case
11098 09:29:00.909658 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11100 09:29:00.919520 /lava-11826788/1/../bin/lava-test-case
11101 09:29:00.926544 <8>[ 18.301332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11102 09:29:00.926805 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11104 09:29:00.934543 /lava-11826788/1/../bin/lava-test-case
11105 09:29:00.941187 <8>[ 18.316525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11106 09:29:00.941441 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11108 09:29:00.952285 /lava-11826788/1/../bin/lava-test-case
11109 09:29:00.959197 <8>[ 18.334795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11110 09:29:00.959463 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11112 09:29:00.968147 /lava-11826788/1/../bin/lava-test-case
11113 09:29:00.978771 <8>[ 18.354244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11114 09:29:00.979032 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11116 09:29:00.986476 /lava-11826788/1/../bin/lava-test-case
11117 09:29:00.992779 <8>[ 18.369715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11118 09:29:00.993041 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11120 09:29:01.005495 /lava-11826788/1/../bin/lava-test-case
11121 09:29:01.011702 <8>[ 18.387750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11122 09:29:01.011956 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11124 09:29:01.020436 /lava-11826788/1/../bin/lava-test-case
11125 09:29:01.030444 <8>[ 18.404642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11126 09:29:01.030699 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11128 09:29:01.041749 /lava-11826788/1/../bin/lava-test-case
11129 09:29:01.048348 <8>[ 18.424482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11130 09:29:01.048602 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11132 09:29:01.056798 /lava-11826788/1/../bin/lava-test-case
11133 09:29:01.063713 <8>[ 18.439186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11134 09:29:01.063969 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11136 09:29:01.076541 /lava-11826788/1/../bin/lava-test-case
11137 09:29:01.082925 <8>[ 18.460519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11138 09:29:01.083184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11140 09:29:01.096259 /lava-11826788/1/../bin/lava-test-case
11141 09:29:01.102464 <8>[ 18.477878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11142 09:29:01.102715 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11144 09:29:01.114072 /lava-11826788/1/../bin/lava-test-case
11145 09:29:01.120701 <8>[ 18.497595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11146 09:29:01.120966 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11148 09:29:01.132849 /lava-11826788/1/../bin/lava-test-case
11149 09:29:01.139085 <8>[ 18.515865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11150 09:29:01.139406 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11152 09:29:01.151616 /lava-11826788/1/../bin/lava-test-case
11153 09:29:01.158802 <8>[ 18.534336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11154 09:29:01.159048 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11156 09:29:01.169441 /lava-11826788/1/../bin/lava-test-case
11157 09:29:01.176048 <8>[ 18.551792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11158 09:29:01.176312 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11160 09:29:01.188998 /lava-11826788/1/../bin/lava-test-case
11161 09:29:01.195615 <8>[ 18.571074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11162 09:29:01.195925 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11164 09:29:01.207626 /lava-11826788/1/../bin/lava-test-case
11165 09:29:01.214244 <8>[ 18.590843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11166 09:29:01.214659 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11168 09:29:01.226802 /lava-11826788/1/../bin/lava-test-case
11169 09:29:01.237007 <8>[ 18.612425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11170 09:29:01.237692 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11172 09:29:01.249329 /lava-11826788/1/../bin/lava-test-case
11173 09:29:01.255692 <8>[ 18.631847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11174 09:29:01.256368 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11176 09:29:01.267595 /lava-11826788/1/../bin/lava-test-case
11177 09:29:01.274246 <8>[ 18.649757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11178 09:29:01.274920 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11180 09:29:01.284182 /lava-11826788/1/../bin/lava-test-case
11181 09:29:01.291150 <8>[ 18.666592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11182 09:29:01.291834 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11184 09:29:01.302845 /lava-11826788/1/../bin/lava-test-case
11185 09:29:01.309276 <8>[ 18.684463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11186 09:29:01.310017 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11188 09:29:01.326630 /lava-11826788/1/../bin/lava-tes<8>[ 18.701457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11189 09:29:01.327132 t-case
11190 09:29:01.327714 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11192 09:29:01.340249 /lava-11826788/1/../bin/lava-test-case
11193 09:29:01.346594 <8>[ 18.722044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11194 09:29:01.347280 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11196 09:29:01.355358 /lava-11826788/1/../bin/lava-test-case
11197 09:29:01.362067 <8>[ 18.737477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11198 09:29:01.363194 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11200 09:29:01.375679 /lava-11826788/1/../bin/lava-test-case
11201 09:29:01.381879 <8>[ 18.757552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11202 09:29:01.382577 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11204 09:29:01.391104 /lava-11826788/1/../bin/lava-test-case
11205 09:29:01.397481 <8>[ 18.773976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11206 09:29:01.398282 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11208 09:29:01.409381 /lava-11826788/1/../bin/lava-test-case
11209 09:29:01.415998 <8>[ 18.791100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11210 09:29:01.416666 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11212 09:29:01.423877 /lava-11826788/1/../bin/lava-test-case
11213 09:29:01.430581 <8>[ 18.806948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11214 09:29:01.431258 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11216 09:29:01.443709 /lava-11826788/1/../bin/lava-test-case
11217 09:29:01.450145 <8>[ 18.824953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11218 09:29:01.450940 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11220 09:29:01.459871 /lava-11826788/1/../bin/lava-test-case
11221 09:29:01.466431 <8>[ 18.841529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11222 09:29:01.467273 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11224 09:29:01.478611 /lava-11826788/1/../bin/lava-test-case
11225 09:29:01.485268 <8>[ 18.862067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11226 09:29:01.485556 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11228 09:29:01.496197 /lava-11826788/1/../bin/lava-test-case
11229 09:29:01.502779 <8>[ 18.878013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11230 09:29:01.503055 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11232 09:29:01.522058 /lava-11826788/1/../bin/lava-tes<8>[ 18.896359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11233 09:29:01.522635 t-case
11234 09:29:01.523391 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11236 09:29:01.535952 /lava-11826788/1/../bin/lava-tes<8>[ 18.910485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11237 09:29:01.536359 t-case
11238 09:29:01.537039 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11240 09:29:01.548827 /lava-11826788/1/../bin/lava-test-case
11241 09:29:01.555353 <8>[ 18.930564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11242 09:29:01.556279 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11244 09:29:01.570299 /lava-11826788/1/../bin/lava-test-case
11245 09:29:01.576700 <8>[ 18.952077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11246 09:29:01.577373 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11248 09:29:01.585388 /lava-11826788/1/../bin/lava-test-case
11249 09:29:01.591943 <8>[ 18.969379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11250 09:29:01.592359 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11252 09:29:01.606704 /lava-11826788/1/../bin/lava-test-case
11253 09:29:01.613335 <8>[ 18.988827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11254 09:29:01.613659 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11256 09:29:01.623018 /lava-11826788/1/../bin/lava-test-case
11257 09:29:01.629466 <8>[ 19.005424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11258 09:29:01.629716 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11260 09:29:01.641627 /lava-11826788/1/../bin/lava-test-case
11261 09:29:01.648840 <8>[ 19.025064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11262 09:29:01.649150 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11264 09:29:01.656862 /lava-11826788/1/../bin/lava-test-case
11265 09:29:01.663821 <8>[ 19.040627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11266 09:29:01.664127 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11268 09:29:02.680110 /lava-11826788/1/../bin/lava-test-case
11269 09:29:02.686396 <8>[ 20.063091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11270 09:29:02.686679 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11272 09:29:02.694565 /lava-11826788/1/../bin/lava-test-case
11273 09:29:02.705103 <8>[ 20.081099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11274 09:29:02.705420 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11276 09:29:03.718843 /lava-11826788/1/../bin/lava-test-case
11277 09:29:03.725311 <8>[ 21.101026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11278 09:29:03.726175 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11280 09:29:03.733622 /lava-11826788/1/../bin/lava-test-case
11281 09:29:03.743606 <8>[ 21.119379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11282 09:29:03.744465 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11284 09:29:04.757315 /lava-11826788/1/../bin/lava-test-case
11285 09:29:04.763885 <8>[ 22.139731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11286 09:29:04.764574 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11288 09:29:04.774128 /lava-11826788/1/../bin/lava-test-case
11289 09:29:04.780542 <8>[ 22.156838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11290 09:29:04.781256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11292 09:29:05.888885 /lava-11826788/1/../bin/lava-test-case
11293 09:29:05.889675 <8>[ 23.176383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11294 09:29:05.890295 /lava-11826788/1/../bin/lava-test-case
11295 09:29:05.890897 <8>[ 23.193462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11296 09:29:05.891746 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11298 09:29:05.893609 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11300 09:29:06.829960 /lava-11826788/1/../bin/lava-test-case
11301 09:29:06.836187 <8>[ 24.214659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11302 09:29:06.836456 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11304 09:29:06.844313 /lava-11826788/1/../bin/lava-test-case
11305 09:29:06.858116 <8>[ 24.234234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11306 09:29:06.858382 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11308 09:29:07.873560 /lava-11826788/1/../bin/lava-test-case
11309 09:29:07.880242 <8>[ 25.256965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11310 09:29:07.880509 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11312 09:29:07.889393 /lava-11826788/1/../bin/lava-test-case
11313 09:29:07.899557 <8>[ 25.275988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11314 09:29:07.899813 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11316 09:29:08.912699 /lava-11826788/1/../bin/lava-test-case
11317 09:29:08.919532 <8>[ 26.296072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11318 09:29:08.919856 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11320 09:29:08.929959 /lava-11826788/1/../bin/lava-test-case
11321 09:29:08.939930 <8>[ 26.316572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11322 09:29:08.940205 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11324 09:29:08.948683 /lava-11826788/1/../bin/lava-test-case
11325 09:29:08.955227 <8>[ 26.331893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11326 09:29:08.955495 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11328 09:29:09.968814 /lava-11826788/1/../bin/lava-test-case
11329 09:29:09.975327 <8>[ 27.351781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11330 09:29:09.976121 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11332 09:29:09.986288 /lava-11826788/1/../bin/lava-test-case
11333 09:29:09.993227 <8>[ 27.369526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11334 09:29:09.993961 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11336 09:29:10.011589 /lava-11826788/1/../bin/lava-tes<8>[ 27.387060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11337 09:29:10.012090 t-case
11338 09:29:10.012973 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11340 09:29:10.021063 /lava-11826788/1/../bin/lava-test-case
11341 09:29:10.031238 <8>[ 27.405920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11342 09:29:10.031973 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11344 09:29:10.043899 /lava-11826788/1/../bin/lava-test-case
11345 09:29:10.053455 <8>[ 27.428929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11346 09:29:10.054186 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11348 09:29:10.067136 /lava-11826788/1/../bin/lava-test-case
11349 09:29:10.073577 <8>[ 27.450645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11350 09:29:10.074312 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11352 09:29:10.085183 /lava-11826788/1/../bin/lava-test-case
11353 09:29:10.091707 <8>[ 27.468229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11354 09:29:10.092441 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11356 09:29:10.103017 /lava-11826788/1/../bin/lava-test-case
11357 09:29:10.109428 <8>[ 27.485829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11358 09:29:10.110161 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11360 09:29:10.120538 /lava-11826788/1/../bin/lava-test-case
11361 09:29:10.127570 <8>[ 27.503065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11362 09:29:10.128300 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11364 09:29:10.141469 /lava-11826788/1/../bin/lava-test-case
11365 09:29:10.148068 <8>[ 27.525509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11366 09:29:10.148825 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11368 09:29:10.158412 /lava-11826788/1/../bin/lava-test-case
11369 09:29:10.164409 <8>[ 27.541029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11370 09:29:10.165137 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11372 09:29:10.175266 /lava-11826788/1/../bin/lava-test-case
11373 09:29:10.185615 <8>[ 27.561864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11374 09:29:10.186361 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11376 09:29:10.194205 /lava-11826788/1/../bin/lava-test-case
11377 09:29:10.201119 <8>[ 27.577256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11378 09:29:10.201853 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11380 09:29:10.214015 /lava-11826788/1/../bin/lava-test-case
11381 09:29:10.223983 <8>[ 27.598646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11382 09:29:10.224718 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11384 09:29:10.231089 /lava-11826788/1/../bin/lava-test-case
11385 09:29:10.237732 <8>[ 27.613887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11386 09:29:10.238462 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11388 09:29:10.248746 /lava-11826788/1/../bin/lava-test-case
11389 09:29:10.258810 <8>[ 27.635259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11390 09:29:10.259542 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11392 09:29:10.268511 /lava-11826788/1/../bin/lava-test-case
11393 09:29:10.275299 <8>[ 27.651430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11394 09:29:10.276030 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11396 09:29:10.290353 /lava-11826788/1/../bin/lava-test-case
11397 09:29:10.297014 <8>[ 27.674238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11398 09:29:10.297762 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11400 09:29:10.307091 /lava-11826788/1/../bin/lava-test-case
11401 09:29:10.313562 <8>[ 27.689816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11402 09:29:10.314316 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11404 09:29:10.337319 /lava-11826788/1/../bin/lava-tes<8>[ 27.713166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11405 09:29:10.337798 t-case
11406 09:29:10.338439 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11408 09:29:10.346515 /lava-11826788/1/../bin/lava-test-case
11409 09:29:10.352821 <8>[ 27.728815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11410 09:29:10.353639 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11412 09:29:11.367467 /lava-11826788/1/../bin/lava-test-case
11413 09:29:11.374383 <8>[ 28.752476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11414 09:29:11.375078 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11416 09:29:12.389316 /lava-11826788/1/../bin/lava-test-case
11417 09:29:12.395954 <8>[ 29.772392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11418 09:29:12.396655 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11420 09:29:12.403846 /lava-11826788/1/../bin/lava-test-case
11421 09:29:12.414077 <8>[ 29.790662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11422 09:29:12.414801 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11424 09:29:12.424376 /lava-11826788/1/../bin/lava-test-case
11425 09:29:12.431221 <8>[ 29.808816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11426 09:29:12.431904 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11428 09:29:12.441665 /lava-11826788/1/../bin/lava-test-case
11429 09:29:12.448148 <8>[ 29.824526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11430 09:29:12.448827 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11432 09:29:12.458798 /lava-11826788/1/../bin/lava-test-case
11433 09:29:12.469449 <8>[ 29.845706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11434 09:29:12.470122 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11436 09:29:12.478069 /lava-11826788/1/../bin/lava-test-case
11437 09:29:12.484709 <8>[ 29.861835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11438 09:29:12.485423 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11440 09:29:12.494977 /lava-11826788/1/../bin/lava-test-case
11441 09:29:12.501989 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11443 09:29:12.505060 <8>[ 29.881191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11444 09:29:12.512218 /lava-11826788/1/../bin/lava-test-case
11445 09:29:12.518834 <8>[ 29.896318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11446 09:29:12.519550 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11448 09:29:12.530155 /lava-11826788/1/../bin/lava-test-case
11449 09:29:12.536695 <8>[ 29.914057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11450 09:29:12.537425 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11452 09:29:12.545507 /lava-11826788/1/../bin/lava-test-case
11453 09:29:12.551998 <8>[ 29.929681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11454 09:29:12.552673 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11456 09:29:12.564307 /lava-11826788/1/../bin/lava-test-case
11457 09:29:12.570790 <8>[ 29.948095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11458 09:29:12.571451 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11460 09:29:12.579567 /lava-11826788/1/../bin/lava-test-case
11461 09:29:12.586070 <8>[ 29.962192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11462 09:29:12.586756 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11464 09:29:12.598455 /lava-11826788/1/../bin/lava-test-case
11465 09:29:12.604703 <8>[ 29.982694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11466 09:29:12.605410 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11468 09:29:12.614584 /lava-11826788/1/../bin/lava-test-case
11469 09:29:12.621306 <8>[ 29.999028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11470 09:29:12.622044 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11472 09:29:12.633619 /lava-11826788/1/../bin/lava-test-case
11473 09:29:12.640029 <8>[ 30.016785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11474 09:29:12.640724 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11476 09:29:12.649975 /lava-11826788/1/../bin/lava-test-case
11477 09:29:12.656927 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11479 09:29:12.659683 <8>[ 30.035213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11480 09:29:12.670532 /lava-11826788/1/../bin/lava-test-case
11481 09:29:12.676976 <8>[ 30.053131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11482 09:29:12.677691 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11484 09:29:12.685346 /lava-11826788/1/../bin/lava-test-case
11485 09:29:12.692074 <8>[ 30.069822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11486 09:29:12.692777 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11488 09:29:12.704140 /lava-11826788/1/../bin/lava-test-case
11489 09:29:12.710745 <8>[ 30.087440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11490 09:29:12.711435 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11492 09:29:12.718667 /lava-11826788/1/../bin/lava-test-case
11493 09:29:12.725396 <8>[ 30.102654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11494 09:29:12.726082 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11496 09:29:12.737627 /lava-11826788/1/../bin/lava-test-case
11497 09:29:12.744449 <8>[ 30.121110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11498 09:29:12.745135 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11500 09:29:13.755568 /lava-11826788/1/../bin/lava-test-case
11501 09:29:13.762011 <8>[ 31.139453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11502 09:29:13.762716 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11504 09:29:14.773676 /lava-11826788/1/../bin/lava-test-case
11505 09:29:14.780202 <8>[ 32.157467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11506 09:29:14.780894 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11507 09:29:14.781371 Bad test result: blocked
11508 09:29:14.797960 /lava-11826788/1/../bin/lava-tes<8>[ 32.173956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11509 09:29:14.798427 t-case
11510 09:29:14.799011 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11512 09:29:15.813023 /lava-11826788/1/../bin/lava-test-case
11513 09:29:15.819659 <8>[ 33.197538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11514 09:29:15.820426 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11516 09:29:15.828362 /lava-11826788/1/../bin/lava-test-case
11517 09:29:15.838409 <8>[ 33.215554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11518 09:29:15.839085 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11520 09:29:15.848511 /lava-11826788/1/../bin/lava-test-case
11521 09:29:15.855313 <8>[ 33.233233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11522 09:29:15.856079 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11524 09:29:15.866621 /lava-11826788/1/../bin/lava-test-case
11525 09:29:15.873165 <8>[ 33.250747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11526 09:29:15.873849 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11528 09:29:15.881774 /lava-11826788/1/../bin/lava-test-case
11529 09:29:15.888505 <8>[ 33.265434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11530 09:29:15.889195 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11532 09:29:15.903153 /lava-11826788/1/../bin/lava-test-case
11533 09:29:15.909503 <8>[ 33.288105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11534 09:29:15.910192 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11536 09:29:15.920085 /lava-11826788/1/../bin/lava-test-case
11537 09:29:15.925844 <8>[ 33.303779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11538 09:29:15.926519 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11540 09:29:16.940361 /lava-11826788/1/../bin/lava-test-case
11541 09:29:16.946869 <8>[ 34.323762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11542 09:29:16.947557 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11544 09:29:16.956980 /lava-11826788/1/../bin/lava-test-case
11545 09:29:16.963444 <8>[ 34.340857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11546 09:29:16.964118 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11548 09:29:17.973674 /lava-11826788/1/../bin/lava-test-case
11549 09:29:17.983343 <8>[ 35.361048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11550 09:29:17.983613 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11552 09:29:17.990903 /lava-11826788/1/../bin/lava-test-case
11553 09:29:17.997704 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11555 09:29:18.000807 <8>[ 35.377222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11556 09:29:19.013631 /lava-11826788/1/../bin/lava-test-case
11557 09:29:19.020388 <8>[ 36.397966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11558 09:29:19.021049 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11560 09:29:19.028325 /lava-11826788/1/../bin/lava-test-case
11561 09:29:19.038755 <8>[ 36.416027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11562 09:29:19.039432 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11564 09:29:20.051823 /lava-11826788/1/../bin/lava-test-case
11565 09:29:20.058126 <8>[ 37.435853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11566 09:29:20.058401 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11568 09:29:20.068633 /lava-11826788/1/../bin/lava-test-case
11569 09:29:20.074832 <8>[ 37.454619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11570 09:29:20.075086 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11572 09:29:20.088546 /lava-11826788/1/../bin/lava-test-case
11573 09:29:20.095552 <8>[ 37.472584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11574 09:29:20.095807 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11576 09:29:20.105873 /lava-11826788/1/../bin/lava-test-case
11577 09:29:20.112719 <8>[ 37.490836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11578 09:29:20.112967 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11580 09:29:20.121164 /lava-11826788/1/../bin/lava-test-case
11581 09:29:20.127612 <8>[ 37.505746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11582 09:29:20.127869 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11584 09:29:20.138044 /lava-11826788/1/../bin/lava-test-case
11585 09:29:20.144913 <8>[ 37.523723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11586 09:29:20.145232 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11588 09:29:20.153367 /lava-11826788/1/../bin/lava-test-case
11589 09:29:20.160104 <8>[ 37.538599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11590 09:29:20.160388 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11592 09:29:20.172385 /lava-11826788/1/../bin/lava-test-case
11593 09:29:20.178832 <8>[ 37.557678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11594 09:29:20.179109 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11596 09:29:20.188563 /lava-11826788/1/../bin/lava-test-case
11597 09:29:20.195015 <8>[ 37.572795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11598 09:29:20.195291 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11600 09:29:20.205342 /lava-11826788/1/../bin/lava-test-case
11601 09:29:20.216006 <8>[ 37.593557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11602 09:29:20.216285 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11604 09:29:20.219588 + set +x
11605 09:29:20.222862 Received signal: <ENDRUN> 1_bootrr 11826788_1.5.2.3.5
11606 09:29:20.222968 Ending use of test pattern.
11607 09:29:20.223060 Ending test lava.1_bootrr (11826788_1.5.2.3.5), duration 20.41
11609 09:29:20.225736 <8>[ 37.603631] <LAVA_SIGNAL_ENDRUN 1_bootrr 11826788_1.5.2.3.5>
11610 09:29:20.225978 ok: lava_test_shell seems to have completed
11611 09:29:20.226958 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11612 09:29:20.227104 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11613 09:29:20.227194 end: 4 lava-test-retry (duration 00:00:21) [common]
11614 09:29:20.227282 start: 5 finalize (timeout 00:08:06) [common]
11615 09:29:20.227376 start: 5.1 power-off (timeout 00:00:30) [common]
11616 09:29:20.227614 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11617 09:29:20.303130 >> Command sent successfully.
11618 09:29:20.305678 Returned 0 in 0 seconds
11619 09:29:20.406043 end: 5.1 power-off (duration 00:00:00) [common]
11621 09:29:20.406476 start: 5.2 read-feedback (timeout 00:08:06) [common]
11623 09:29:20.407095 Listened to connection for namespace 'common' for up to 1s
11624 09:29:21.407700 Finalising connection for namespace 'common'
11625 09:29:21.407887 Disconnecting from shell: Finalise
11626 09:29:21.407999 / #
11627 09:29:21.508333 end: 5.2 read-feedback (duration 00:00:01) [common]
11628 09:29:21.508501 end: 5 finalize (duration 00:00:01) [common]
11629 09:29:21.508614 Cleaning after the job
11630 09:29:21.508728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/ramdisk
11631 09:29:21.511124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/kernel
11632 09:29:21.517563 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/dtb
11633 09:29:21.517735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826788/tftp-deploy-zdaz8vpz/modules
11634 09:29:21.523218 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826788
11635 09:29:21.563512 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826788
11636 09:29:21.563677 Job finished correctly