Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 38
- Errors: 1
- Boot result: PASS
1 09:26:25.542842 lava-dispatcher, installed at version: 2023.08
2 09:26:25.543059 start: 0 validate
3 09:26:25.543193 Start time: 2023-10-20 09:26:25.543185+00:00 (UTC)
4 09:26:25.543317 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:26:25.543456 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:26:26.829069 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:26:26.829299 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:27:04.136824 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:27:04.137597 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:04.406886 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:04.407616 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:27:04.937607 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:27:04.938420 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:27:07.454198 validate duration: 41.91
16 09:27:07.454457 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:27:07.454557 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:27:07.454645 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:27:07.454774 Not decompressing ramdisk as can be used compressed.
20 09:27:07.454858 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 09:27:07.454922 saving as /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/ramdisk/initrd.cpio.gz
22 09:27:07.454985 total size: 4665412 (4 MB)
23 09:27:07.720228 progress 0 % (0 MB)
24 09:27:07.721751 progress 5 % (0 MB)
25 09:27:07.723007 progress 10 % (0 MB)
26 09:27:07.724276 progress 15 % (0 MB)
27 09:27:07.725590 progress 20 % (0 MB)
28 09:27:07.726800 progress 25 % (1 MB)
29 09:27:07.728018 progress 30 % (1 MB)
30 09:27:07.729292 progress 35 % (1 MB)
31 09:27:07.730536 progress 40 % (1 MB)
32 09:27:07.732117 progress 45 % (2 MB)
33 09:27:07.733462 progress 50 % (2 MB)
34 09:27:07.734695 progress 55 % (2 MB)
35 09:27:07.735952 progress 60 % (2 MB)
36 09:27:07.737340 progress 65 % (2 MB)
37 09:27:07.738553 progress 70 % (3 MB)
38 09:27:07.739760 progress 75 % (3 MB)
39 09:27:07.741017 progress 80 % (3 MB)
40 09:27:07.742407 progress 85 % (3 MB)
41 09:27:07.743611 progress 90 % (4 MB)
42 09:27:07.744878 progress 95 % (4 MB)
43 09:27:07.746183 progress 100 % (4 MB)
44 09:27:07.746337 4 MB downloaded in 0.29 s (15.27 MB/s)
45 09:27:07.746490 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:27:07.746728 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:27:07.746815 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:27:07.746900 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:27:07.747033 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:27:07.747101 saving as /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/kernel/Image
52 09:27:07.747161 total size: 49236480 (46 MB)
53 09:27:07.747221 No compression specified
54 09:27:07.748405 progress 0 % (0 MB)
55 09:27:07.761016 progress 5 % (2 MB)
56 09:27:07.774003 progress 10 % (4 MB)
57 09:27:07.786837 progress 15 % (7 MB)
58 09:27:07.799792 progress 20 % (9 MB)
59 09:27:07.812630 progress 25 % (11 MB)
60 09:27:07.825177 progress 30 % (14 MB)
61 09:27:07.837994 progress 35 % (16 MB)
62 09:27:07.851116 progress 40 % (18 MB)
63 09:27:07.863822 progress 45 % (21 MB)
64 09:27:07.876520 progress 50 % (23 MB)
65 09:27:07.889473 progress 55 % (25 MB)
66 09:27:07.902654 progress 60 % (28 MB)
67 09:27:07.915570 progress 65 % (30 MB)
68 09:27:07.928235 progress 70 % (32 MB)
69 09:27:07.941162 progress 75 % (35 MB)
70 09:27:07.954117 progress 80 % (37 MB)
71 09:27:07.966994 progress 85 % (39 MB)
72 09:27:07.979632 progress 90 % (42 MB)
73 09:27:07.992244 progress 95 % (44 MB)
74 09:27:08.004751 progress 100 % (46 MB)
75 09:27:08.004971 46 MB downloaded in 0.26 s (182.14 MB/s)
76 09:27:08.005122 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:27:08.005356 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:27:08.005444 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:27:08.005529 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:27:08.005671 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:27:08.005746 saving as /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/dtb/mt8192-asurada-spherion-r0.dtb
83 09:27:08.005808 total size: 47278 (0 MB)
84 09:27:08.005870 No compression specified
85 09:27:08.007058 progress 69 % (0 MB)
86 09:27:08.007336 progress 100 % (0 MB)
87 09:27:08.007509 0 MB downloaded in 0.00 s (26.54 MB/s)
88 09:27:08.007633 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:27:08.007858 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:27:08.007943 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:27:08.008026 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:27:08.008140 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 09:27:08.008222 saving as /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/nfsrootfs/full.rootfs.tar
95 09:27:08.008285 total size: 125290964 (119 MB)
96 09:27:08.008348 Using unxz to decompress xz
97 09:27:08.012468 progress 0 % (0 MB)
98 09:27:08.333342 progress 5 % (6 MB)
99 09:27:08.663355 progress 10 % (11 MB)
100 09:27:08.990420 progress 15 % (17 MB)
101 09:27:09.173030 progress 20 % (23 MB)
102 09:27:09.344793 progress 25 % (29 MB)
103 09:27:09.691912 progress 30 % (35 MB)
104 09:27:10.048713 progress 35 % (41 MB)
105 09:27:10.427487 progress 40 % (47 MB)
106 09:27:10.796803 progress 45 % (53 MB)
107 09:27:11.177846 progress 50 % (59 MB)
108 09:27:11.524739 progress 55 % (65 MB)
109 09:27:11.882061 progress 60 % (71 MB)
110 09:27:12.211411 progress 65 % (77 MB)
111 09:27:12.567566 progress 70 % (83 MB)
112 09:27:12.941420 progress 75 % (89 MB)
113 09:27:13.350351 progress 80 % (95 MB)
114 09:27:13.759756 progress 85 % (101 MB)
115 09:27:14.000493 progress 90 % (107 MB)
116 09:27:14.335558 progress 95 % (113 MB)
117 09:27:14.707025 progress 100 % (119 MB)
118 09:27:14.712808 119 MB downloaded in 6.70 s (17.82 MB/s)
119 09:27:14.713098 end: 1.4.1 http-download (duration 00:00:07) [common]
121 09:27:14.713367 end: 1.4 download-retry (duration 00:00:07) [common]
122 09:27:14.713458 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:27:14.713547 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:27:14.713699 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:27:14.713770 saving as /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/modules/modules.tar
126 09:27:14.713832 total size: 8614716 (8 MB)
127 09:27:14.713901 Using unxz to decompress xz
128 09:27:14.718291 progress 0 % (0 MB)
129 09:27:14.740585 progress 5 % (0 MB)
130 09:27:14.767751 progress 10 % (0 MB)
131 09:27:14.795345 progress 15 % (1 MB)
132 09:27:14.822683 progress 20 % (1 MB)
133 09:27:14.851461 progress 25 % (2 MB)
134 09:27:14.880830 progress 30 % (2 MB)
135 09:27:14.911168 progress 35 % (2 MB)
136 09:27:14.938461 progress 40 % (3 MB)
137 09:27:14.967349 progress 45 % (3 MB)
138 09:27:14.993231 progress 50 % (4 MB)
139 09:27:15.018220 progress 55 % (4 MB)
140 09:27:15.043191 progress 60 % (4 MB)
141 09:27:15.069191 progress 65 % (5 MB)
142 09:27:15.096198 progress 70 % (5 MB)
143 09:27:15.120027 progress 75 % (6 MB)
144 09:27:15.146934 progress 80 % (6 MB)
145 09:27:15.172988 progress 85 % (7 MB)
146 09:27:15.197975 progress 90 % (7 MB)
147 09:27:15.227678 progress 95 % (7 MB)
148 09:27:15.255835 progress 100 % (8 MB)
149 09:27:15.262184 8 MB downloaded in 0.55 s (14.98 MB/s)
150 09:27:15.262539 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:27:15.262937 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:27:15.263069 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 09:27:15.263205 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 09:27:17.401169 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin
156 09:27:17.401380 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:27:17.401479 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 09:27:17.401654 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw
159 09:27:17.401785 makedir: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin
160 09:27:17.401889 makedir: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/tests
161 09:27:17.401988 makedir: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/results
162 09:27:17.402092 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-add-keys
163 09:27:17.402237 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-add-sources
164 09:27:17.402364 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-background-process-start
165 09:27:17.402491 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-background-process-stop
166 09:27:17.402616 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-common-functions
167 09:27:17.402739 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-echo-ipv4
168 09:27:17.402862 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-install-packages
169 09:27:17.402984 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-installed-packages
170 09:27:17.403106 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-os-build
171 09:27:17.403229 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-probe-channel
172 09:27:17.403351 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-probe-ip
173 09:27:17.403473 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-target-ip
174 09:27:17.403593 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-target-mac
175 09:27:17.403716 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-target-storage
176 09:27:17.403839 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-case
177 09:27:17.403965 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-event
178 09:27:17.404086 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-feedback
179 09:27:17.404213 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-raise
180 09:27:17.404336 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-reference
181 09:27:17.404458 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-runner
182 09:27:17.404580 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-set
183 09:27:17.404701 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-test-shell
184 09:27:17.404824 Updating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-install-packages (oe)
185 09:27:17.404977 Updating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/bin/lava-installed-packages (oe)
186 09:27:17.405108 Creating /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/environment
187 09:27:17.405205 LAVA metadata
188 09:27:17.405277 - LAVA_JOB_ID=11826831
189 09:27:17.405341 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:27:17.405447 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 09:27:17.405514 skipped lava-vland-overlay
192 09:27:17.405589 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:27:17.405668 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 09:27:17.405728 skipped lava-multinode-overlay
195 09:27:17.405800 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:27:17.405877 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 09:27:17.405951 Loading test definitions
198 09:27:17.406040 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 09:27:17.406110 Using /lava-11826831 at stage 0
200 09:27:17.406416 uuid=11826831_1.6.2.3.1 testdef=None
201 09:27:17.406504 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:27:17.406587 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 09:27:17.407102 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:27:17.407320 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 09:27:17.407972 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:27:17.408349 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 09:27:17.408968 runner path: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/0/tests/0_dmesg test_uuid 11826831_1.6.2.3.1
210 09:27:17.409135 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:27:17.409442 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 09:27:17.409514 Using /lava-11826831 at stage 1
214 09:27:17.409817 uuid=11826831_1.6.2.3.5 testdef=None
215 09:27:17.409905 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 09:27:17.409988 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 09:27:17.410462 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 09:27:17.410675 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 09:27:17.411312 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 09:27:17.411539 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 09:27:17.412155 runner path: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/1/tests/1_bootrr test_uuid 11826831_1.6.2.3.5
224 09:27:17.412373 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 09:27:17.412576 Creating lava-test-runner.conf files
227 09:27:17.412655 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/0 for stage 0
228 09:27:17.412747 - 0_dmesg
229 09:27:17.412826 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826831/lava-overlay-tic_4rtw/lava-11826831/1 for stage 1
230 09:27:17.412916 - 1_bootrr
231 09:27:17.413010 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 09:27:17.413092 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 09:27:17.420546 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 09:27:17.420680 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 09:27:17.420768 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 09:27:17.420854 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 09:27:17.420944 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 09:27:17.541555 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 09:27:17.541944 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 09:27:17.542072 extracting modules file /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin
241 09:27:17.764682 extracting modules file /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826831/extract-overlay-ramdisk-2kq8rf4d/ramdisk
242 09:27:17.994247 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 09:27:17.994431 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 09:27:17.994525 [common] Applying overlay to NFS
245 09:27:17.994598 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826831/compress-overlay-t6d4tyig/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin
246 09:27:18.002728 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 09:27:18.002865 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 09:27:18.002954 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 09:27:18.003037 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 09:27:18.003121 Building ramdisk /var/lib/lava/dispatcher/tmp/11826831/extract-overlay-ramdisk-2kq8rf4d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826831/extract-overlay-ramdisk-2kq8rf4d/ramdisk
251 09:27:18.304768 >> 119368 blocks
252 09:27:20.267809 rename /var/lib/lava/dispatcher/tmp/11826831/extract-overlay-ramdisk-2kq8rf4d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/ramdisk/ramdisk.cpio.gz
253 09:27:20.268308 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 09:27:20.268437 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 09:27:20.268537 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 09:27:20.268645 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/kernel/Image'
257 09:27:32.462826 Returned 0 in 12 seconds
258 09:27:32.563961 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/kernel/image.itb
259 09:27:32.923143 output: FIT description: Kernel Image image with one or more FDT blobs
260 09:27:32.923508 output: Created: Fri Oct 20 10:27:32 2023
261 09:27:32.923584 output: Image 0 (kernel-1)
262 09:27:32.923650 output: Description:
263 09:27:32.923712 output: Created: Fri Oct 20 10:27:32 2023
264 09:27:32.923768 output: Type: Kernel Image
265 09:27:32.923829 output: Compression: lzma compressed
266 09:27:32.923897 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
267 09:27:32.923955 output: Architecture: AArch64
268 09:27:32.924014 output: OS: Linux
269 09:27:32.924070 output: Load Address: 0x00000000
270 09:27:32.924129 output: Entry Point: 0x00000000
271 09:27:32.924191 output: Hash algo: crc32
272 09:27:32.924288 output: Hash value: 05d3904e
273 09:27:32.924345 output: Image 1 (fdt-1)
274 09:27:32.924402 output: Description: mt8192-asurada-spherion-r0
275 09:27:32.924454 output: Created: Fri Oct 20 10:27:32 2023
276 09:27:32.924506 output: Type: Flat Device Tree
277 09:27:32.924558 output: Compression: uncompressed
278 09:27:32.924610 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 09:27:32.924662 output: Architecture: AArch64
280 09:27:32.924713 output: Hash algo: crc32
281 09:27:32.924765 output: Hash value: cc4352de
282 09:27:32.924816 output: Image 2 (ramdisk-1)
283 09:27:32.924867 output: Description: unavailable
284 09:27:32.924918 output: Created: Fri Oct 20 10:27:32 2023
285 09:27:32.924970 output: Type: RAMDisk Image
286 09:27:32.925022 output: Compression: Unknown Compression
287 09:27:32.925074 output: Data Size: 17790701 Bytes = 17373.73 KiB = 16.97 MiB
288 09:27:32.925126 output: Architecture: AArch64
289 09:27:32.925176 output: OS: Linux
290 09:27:32.925228 output: Load Address: unavailable
291 09:27:32.925279 output: Entry Point: unavailable
292 09:27:32.925330 output: Hash algo: crc32
293 09:27:32.925382 output: Hash value: 5280bd26
294 09:27:32.925433 output: Default Configuration: 'conf-1'
295 09:27:32.925484 output: Configuration 0 (conf-1)
296 09:27:32.925535 output: Description: mt8192-asurada-spherion-r0
297 09:27:32.925587 output: Kernel: kernel-1
298 09:27:32.925638 output: Init Ramdisk: ramdisk-1
299 09:27:32.925689 output: FDT: fdt-1
300 09:27:32.925743 output: Loadables: kernel-1
301 09:27:32.925795 output:
302 09:27:32.926028 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 09:27:32.926130 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 09:27:32.926231 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 09:27:32.926323 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
306 09:27:32.926401 No LXC device requested
307 09:27:32.926478 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 09:27:32.926565 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
309 09:27:32.926644 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 09:27:32.926713 Checking files for TFTP limit of 4294967296 bytes.
311 09:27:32.927218 end: 1 tftp-deploy (duration 00:00:25) [common]
312 09:27:32.927320 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 09:27:32.927413 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 09:27:32.927541 substitutions:
315 09:27:32.927608 - {DTB}: 11826831/tftp-deploy-_m38mr1m/dtb/mt8192-asurada-spherion-r0.dtb
316 09:27:32.927672 - {INITRD}: 11826831/tftp-deploy-_m38mr1m/ramdisk/ramdisk.cpio.gz
317 09:27:32.927738 - {KERNEL}: 11826831/tftp-deploy-_m38mr1m/kernel/Image
318 09:27:32.927799 - {LAVA_MAC}: None
319 09:27:32.927867 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin
320 09:27:32.927922 - {NFS_SERVER_IP}: 192.168.201.1
321 09:27:32.927977 - {PRESEED_CONFIG}: None
322 09:27:32.928031 - {PRESEED_LOCAL}: None
323 09:27:32.928085 - {RAMDISK}: 11826831/tftp-deploy-_m38mr1m/ramdisk/ramdisk.cpio.gz
324 09:27:32.928140 - {ROOT_PART}: None
325 09:27:32.928238 - {ROOT}: None
326 09:27:32.928294 - {SERVER_IP}: 192.168.201.1
327 09:27:32.928347 - {TEE}: None
328 09:27:32.928401 Parsed boot commands:
329 09:27:32.928454 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 09:27:32.928640 Parsed boot commands: tftpboot 192.168.201.1 11826831/tftp-deploy-_m38mr1m/kernel/image.itb 11826831/tftp-deploy-_m38mr1m/kernel/cmdline
331 09:27:32.928730 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 09:27:32.928812 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 09:27:32.928904 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 09:27:32.928990 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 09:27:32.929062 Not connected, no need to disconnect.
336 09:27:32.929139 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 09:27:32.929225 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 09:27:32.929293 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
339 09:27:32.933272 Setting prompt string to ['lava-test: # ']
340 09:27:32.933643 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 09:27:32.933749 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 09:27:32.933862 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 09:27:32.934022 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 09:27:32.934247 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
345 09:27:38.070416 >> Command sent successfully.
346 09:27:38.072805 Returned 0 in 5 seconds
347 09:27:38.173162 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 09:27:38.173612 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 09:27:38.173742 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 09:27:38.173865 Setting prompt string to 'Starting depthcharge on Spherion...'
352 09:27:38.173965 Changing prompt to 'Starting depthcharge on Spherion...'
353 09:27:38.174063 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 09:27:38.174452 [Enter `^Ec?' for help]
355 09:27:38.352849
356 09:27:38.352995
357 09:27:38.353098 F0: 102B 0000
358 09:27:38.353195
359 09:27:38.353290 F3: 1001 0000 [0200]
360 09:27:38.353379
361 09:27:38.355742 F3: 1001 0000
362 09:27:38.355841
363 09:27:38.355930 F7: 102D 0000
364 09:27:38.356021
365 09:27:38.359318 F1: 0000 0000
366 09:27:38.359414
367 09:27:38.359506 V0: 0000 0000 [0001]
368 09:27:38.359588
369 09:27:38.359654 00: 0007 8000
370 09:27:38.359720
371 09:27:38.362964 01: 0000 0000
372 09:27:38.363031
373 09:27:38.363090 BP: 0C00 0209 [0000]
374 09:27:38.363151
375 09:27:38.366240 G0: 1182 0000
376 09:27:38.366335
377 09:27:38.366423 EC: 0000 0021 [4000]
378 09:27:38.366509
379 09:27:38.369902 S7: 0000 0000 [0000]
380 09:27:38.369995
381 09:27:38.370088 CC: 0000 0000 [0001]
382 09:27:38.370173
383 09:27:38.373073 T0: 0000 0040 [010F]
384 09:27:38.373171
385 09:27:38.373265 Jump to BL
386 09:27:38.373352
387 09:27:38.399718
388 09:27:38.399825
389 09:27:38.399918
390 09:27:38.406877 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 09:27:38.410328 ARM64: Exception handlers installed.
392 09:27:38.413968 ARM64: Testing exception
393 09:27:38.417897 ARM64: Done test exception
394 09:27:38.425118 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 09:27:38.432076 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 09:27:38.439517 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 09:27:38.450086 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 09:27:38.456652 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 09:27:38.466759 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 09:27:38.477301 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 09:27:38.484132 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 09:27:38.502217 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 09:27:38.505261 WDT: Last reset was cold boot
404 09:27:38.508674 SPI1(PAD0) initialized at 2873684 Hz
405 09:27:38.511977 SPI5(PAD0) initialized at 992727 Hz
406 09:27:38.515256 VBOOT: Loading verstage.
407 09:27:38.522098 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 09:27:38.525642 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 09:27:38.528865 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 09:27:38.531900 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 09:27:38.539573 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 09:27:38.546143 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 09:27:38.556964 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 09:27:38.557042
415 09:27:38.557111
416 09:27:38.566939 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 09:27:38.570278 ARM64: Exception handlers installed.
418 09:27:38.573536 ARM64: Testing exception
419 09:27:38.573606 ARM64: Done test exception
420 09:27:38.580740 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 09:27:38.583732 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:27:38.598147 Probing TPM: . done!
423 09:27:38.598250 TPM ready after 0 ms
424 09:27:38.605256 Connected to device vid:did:rid of 1ae0:0028:00
425 09:27:38.612120 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
426 09:27:38.661965 Initialized TPM device CR50 revision 0
427 09:27:38.665537 tlcl_send_startup: Startup return code is 0
428 09:27:38.675343 TPM: setup succeeded
429 09:27:38.686698 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 09:27:38.694943 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 09:27:38.704226 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 09:27:38.713470 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 09:27:38.716531 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 09:27:38.719900 in-header: 03 07 00 00 08 00 00 00
435 09:27:38.723214 in-data: aa e4 47 04 13 02 00 00
436 09:27:38.726292 Chrome EC: UHEPI supported
437 09:27:38.733321 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 09:27:38.736764 in-header: 03 95 00 00 08 00 00 00
439 09:27:38.740238 in-data: 18 20 20 08 00 00 00 00
440 09:27:38.740320 Phase 1
441 09:27:38.744360 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 09:27:38.751598 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 09:27:38.755173 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 09:27:38.758813 Recovery requested (1009000e)
445 09:27:38.767967 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 09:27:38.774233 tlcl_extend: response is 0
447 09:27:38.782795 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 09:27:38.788473 tlcl_extend: response is 0
449 09:27:38.795654 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 09:27:38.816357 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 09:27:38.823333 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 09:27:38.823410
453 09:27:38.823474
454 09:27:38.833908 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 09:27:38.833986 ARM64: Exception handlers installed.
456 09:27:38.837831 ARM64: Testing exception
457 09:27:38.841041 ARM64: Done test exception
458 09:27:38.861145 pmic_efuse_setting: Set efuses in 11 msecs
459 09:27:38.864538 pmwrap_interface_init: Select PMIF_VLD_RDY
460 09:27:38.871363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 09:27:38.874403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 09:27:38.881040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 09:27:38.884433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 09:27:38.891491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 09:27:38.894147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 09:27:38.897769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 09:27:38.904493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 09:27:38.907647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 09:27:38.914404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 09:27:38.917815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 09:27:38.920891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 09:27:38.927558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 09:27:38.934672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 09:27:38.938063 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 09:27:38.945353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 09:27:38.948975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 09:27:38.956441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 09:27:38.960230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 09:27:38.967663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 09:27:38.971107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 09:27:38.979018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 09:27:38.986061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 09:27:38.989729 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 09:27:38.993428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 09:27:39.000759 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 09:27:39.004503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 09:27:39.011900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 09:27:39.015523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 09:27:39.019081 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 09:27:39.026302 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 09:27:39.030585 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 09:27:39.033966 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 09:27:39.041239 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 09:27:39.044967 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 09:27:39.052589 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 09:27:39.056488 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 09:27:39.059696 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 09:27:39.063609 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 09:27:39.070319 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 09:27:39.074478 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 09:27:39.077917 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 09:27:39.081600 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 09:27:39.085657 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 09:27:39.092788 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 09:27:39.096143 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 09:27:39.099836 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 09:27:39.103660 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 09:27:39.108049 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 09:27:39.111029 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 09:27:39.114726 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 09:27:39.125707 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 09:27:39.133024 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 09:27:39.136527 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 09:27:39.143926 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 09:27:39.155208 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 09:27:39.158384 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 09:27:39.162298 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 09:27:39.165551 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 09:27:39.174570 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
520 09:27:39.178205 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 09:27:39.186560 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 09:27:39.189711 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 09:27:39.198676 [RTC]rtc_get_frequency_meter,154: input=15, output=765
524 09:27:39.208092 [RTC]rtc_get_frequency_meter,154: input=23, output=949
525 09:27:39.217554 [RTC]rtc_get_frequency_meter,154: input=19, output=857
526 09:27:39.227287 [RTC]rtc_get_frequency_meter,154: input=17, output=811
527 09:27:39.236863 [RTC]rtc_get_frequency_meter,154: input=16, output=787
528 09:27:39.246368 [RTC]rtc_get_frequency_meter,154: input=16, output=787
529 09:27:39.256105 [RTC]rtc_get_frequency_meter,154: input=17, output=811
530 09:27:39.259867 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 09:27:39.263792 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 09:27:39.267341 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 09:27:39.274532 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 09:27:39.278070 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 09:27:39.281825 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 09:27:39.286024 ADC[4]: Raw value=670800 ID=5
537 09:27:39.286108 ADC[3]: Raw value=212917 ID=1
538 09:27:39.289701 RAM Code: 0x51
539 09:27:39.293300 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 09:27:39.297274 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 09:27:39.308114 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
542 09:27:39.311961 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
543 09:27:39.315560 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 09:27:39.319139 in-header: 03 07 00 00 08 00 00 00
545 09:27:39.322724 in-data: aa e4 47 04 13 02 00 00
546 09:27:39.326700 Chrome EC: UHEPI supported
547 09:27:39.330331 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 09:27:39.334777 in-header: 03 95 00 00 08 00 00 00
549 09:27:39.338583 in-data: 18 20 20 08 00 00 00 00
550 09:27:39.342472 MRC: failed to locate region type 0.
551 09:27:39.349968 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 09:27:39.353564 DRAM-K: Running full calibration
553 09:27:39.356905 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
554 09:27:39.360273 header.status = 0x0
555 09:27:39.363742 header.version = 0x6 (expected: 0x6)
556 09:27:39.367668 header.size = 0xd00 (expected: 0xd00)
557 09:27:39.367751 header.flags = 0x0
558 09:27:39.374000 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 09:27:39.392871 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 09:27:39.400612 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 09:27:39.400697 dram_init: ddr_geometry: 0
562 09:27:39.404071 [EMI] MDL number = 0
563 09:27:39.404154 [EMI] Get MDL freq = 0
564 09:27:39.408145 dram_init: ddr_type: 0
565 09:27:39.411413 is_discrete_lpddr4: 1
566 09:27:39.411497 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 09:27:39.415325
568 09:27:39.415408
569 09:27:39.415474 [Bian_co] ETT version 0.0.0.1
570 09:27:39.422448 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
571 09:27:39.422541
572 09:27:39.426468 dramc_set_vcore_voltage set vcore to 650000
573 09:27:39.426552 Read voltage for 800, 4
574 09:27:39.426618 Vio18 = 0
575 09:27:39.430081 Vcore = 650000
576 09:27:39.430164 Vdram = 0
577 09:27:39.430231 Vddq = 0
578 09:27:39.433570 Vmddr = 0
579 09:27:39.433652 dram_init: config_dvfs: 1
580 09:27:39.440905 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 09:27:39.444900 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 09:27:39.448236 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 09:27:39.451686 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 09:27:39.455605 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 09:27:39.459114 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 09:27:39.463058 MEM_TYPE=3, freq_sel=18
587 09:27:39.466572 sv_algorithm_assistance_LP4_1600
588 09:27:39.470328 ============ PULL DRAM RESETB DOWN ============
589 09:27:39.473837 ========== PULL DRAM RESETB DOWN end =========
590 09:27:39.477695 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 09:27:39.481408 ===================================
592 09:27:39.485068 LPDDR4 DRAM CONFIGURATION
593 09:27:39.488495 ===================================
594 09:27:39.488573 EX_ROW_EN[0] = 0x0
595 09:27:39.492516 EX_ROW_EN[1] = 0x0
596 09:27:39.492601 LP4Y_EN = 0x0
597 09:27:39.496480 WORK_FSP = 0x0
598 09:27:39.496562 WL = 0x2
599 09:27:39.496628 RL = 0x2
600 09:27:39.500041 BL = 0x2
601 09:27:39.500150 RPST = 0x0
602 09:27:39.503948 RD_PRE = 0x0
603 09:27:39.504031 WR_PRE = 0x1
604 09:27:39.507305 WR_PST = 0x0
605 09:27:39.507416 DBI_WR = 0x0
606 09:27:39.510907 DBI_RD = 0x0
607 09:27:39.510990 OTF = 0x1
608 09:27:39.514280 ===================================
609 09:27:39.517897 ===================================
610 09:27:39.517981 ANA top config
611 09:27:39.521705 ===================================
612 09:27:39.525519 DLL_ASYNC_EN = 0
613 09:27:39.529021 ALL_SLAVE_EN = 1
614 09:27:39.529104 NEW_RANK_MODE = 1
615 09:27:39.532384 DLL_IDLE_MODE = 1
616 09:27:39.535673 LP45_APHY_COMB_EN = 1
617 09:27:39.539135 TX_ODT_DIS = 1
618 09:27:39.542022 NEW_8X_MODE = 1
619 09:27:39.545476 ===================================
620 09:27:39.549230 ===================================
621 09:27:39.549314 data_rate = 1600
622 09:27:39.552665 CKR = 1
623 09:27:39.556181 DQ_P2S_RATIO = 8
624 09:27:39.559673 ===================================
625 09:27:39.563418 CA_P2S_RATIO = 8
626 09:27:39.563502 DQ_CA_OPEN = 0
627 09:27:39.566932 DQ_SEMI_OPEN = 0
628 09:27:39.570399 CA_SEMI_OPEN = 0
629 09:27:39.573771 CA_FULL_RATE = 0
630 09:27:39.576907 DQ_CKDIV4_EN = 1
631 09:27:39.576990 CA_CKDIV4_EN = 1
632 09:27:39.580366 CA_PREDIV_EN = 0
633 09:27:39.583632 PH8_DLY = 0
634 09:27:39.586989 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 09:27:39.590865 DQ_AAMCK_DIV = 4
636 09:27:39.590948 CA_AAMCK_DIV = 4
637 09:27:39.594366 CA_ADMCK_DIV = 4
638 09:27:39.597695 DQ_TRACK_CA_EN = 0
639 09:27:39.601507 CA_PICK = 800
640 09:27:39.605106 CA_MCKIO = 800
641 09:27:39.605193 MCKIO_SEMI = 0
642 09:27:39.608618 PLL_FREQ = 3068
643 09:27:39.611809 DQ_UI_PI_RATIO = 32
644 09:27:39.615238 CA_UI_PI_RATIO = 0
645 09:27:39.618966 ===================================
646 09:27:39.622699 ===================================
647 09:27:39.622782 memory_type:LPDDR4
648 09:27:39.626140 GP_NUM : 10
649 09:27:39.629472 SRAM_EN : 1
650 09:27:39.629555 MD32_EN : 0
651 09:27:39.633596 ===================================
652 09:27:39.637174 [ANA_INIT] >>>>>>>>>>>>>>
653 09:27:39.637258 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 09:27:39.640465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 09:27:39.644313 ===================================
656 09:27:39.648005 data_rate = 1600,PCW = 0X7600
657 09:27:39.651781 ===================================
658 09:27:39.655663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 09:27:39.661828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 09:27:39.665427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 09:27:39.672040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 09:27:39.675187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 09:27:39.678573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 09:27:39.678656 [ANA_INIT] flow start
665 09:27:39.681861 [ANA_INIT] PLL >>>>>>>>
666 09:27:39.685492 [ANA_INIT] PLL <<<<<<<<
667 09:27:39.685575 [ANA_INIT] MIDPI >>>>>>>>
668 09:27:39.688502 [ANA_INIT] MIDPI <<<<<<<<
669 09:27:39.691884 [ANA_INIT] DLL >>>>>>>>
670 09:27:39.691967 [ANA_INIT] flow end
671 09:27:39.698516 ============ LP4 DIFF to SE enter ============
672 09:27:39.701933 ============ LP4 DIFF to SE exit ============
673 09:27:39.702017 [ANA_INIT] <<<<<<<<<<<<<
674 09:27:39.705231 [Flow] Enable top DCM control >>>>>
675 09:27:39.708778 [Flow] Enable top DCM control <<<<<
676 09:27:39.712023 Enable DLL master slave shuffle
677 09:27:39.718551 ==============================================================
678 09:27:39.718635 Gating Mode config
679 09:27:39.725345 ==============================================================
680 09:27:39.728564 Config description:
681 09:27:39.738509 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 09:27:39.745243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 09:27:39.748837 SELPH_MODE 0: By rank 1: By Phase
684 09:27:39.755298 ==============================================================
685 09:27:39.758923 GAT_TRACK_EN = 1
686 09:27:39.759006 RX_GATING_MODE = 2
687 09:27:39.761748 RX_GATING_TRACK_MODE = 2
688 09:27:39.765173 SELPH_MODE = 1
689 09:27:39.768522 PICG_EARLY_EN = 1
690 09:27:39.771915 VALID_LAT_VALUE = 1
691 09:27:39.778609 ==============================================================
692 09:27:39.781996 Enter into Gating configuration >>>>
693 09:27:39.785206 Exit from Gating configuration <<<<
694 09:27:39.788653 Enter into DVFS_PRE_config >>>>>
695 09:27:39.798950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 09:27:39.802235 Exit from DVFS_PRE_config <<<<<
697 09:27:39.805198 Enter into PICG configuration >>>>
698 09:27:39.808442 Exit from PICG configuration <<<<
699 09:27:39.811859 [RX_INPUT] configuration >>>>>
700 09:27:39.815079 [RX_INPUT] configuration <<<<<
701 09:27:39.818464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 09:27:39.825386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 09:27:39.831785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 09:27:39.835261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 09:27:39.841798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 09:27:39.848495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 09:27:39.852022 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 09:27:39.855084 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 09:27:39.861902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 09:27:39.865154 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 09:27:39.868512 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 09:27:39.875365 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 09:27:39.878803 ===================================
714 09:27:39.878890 LPDDR4 DRAM CONFIGURATION
715 09:27:39.881901 ===================================
716 09:27:39.885339 EX_ROW_EN[0] = 0x0
717 09:27:39.885425 EX_ROW_EN[1] = 0x0
718 09:27:39.888782 LP4Y_EN = 0x0
719 09:27:39.888868 WORK_FSP = 0x0
720 09:27:39.892117 WL = 0x2
721 09:27:39.895167 RL = 0x2
722 09:27:39.895252 BL = 0x2
723 09:27:39.898455 RPST = 0x0
724 09:27:39.898540 RD_PRE = 0x0
725 09:27:39.901890 WR_PRE = 0x1
726 09:27:39.901977 WR_PST = 0x0
727 09:27:39.905351 DBI_WR = 0x0
728 09:27:39.905437 DBI_RD = 0x0
729 09:27:39.908652 OTF = 0x1
730 09:27:39.912065 ===================================
731 09:27:39.915349 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 09:27:39.918510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 09:27:39.922000 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 09:27:39.925233 ===================================
735 09:27:39.928552 LPDDR4 DRAM CONFIGURATION
736 09:27:39.931737 ===================================
737 09:27:39.935132 EX_ROW_EN[0] = 0x10
738 09:27:39.935218 EX_ROW_EN[1] = 0x0
739 09:27:39.938258 LP4Y_EN = 0x0
740 09:27:39.938344 WORK_FSP = 0x0
741 09:27:39.941742 WL = 0x2
742 09:27:39.941828 RL = 0x2
743 09:27:39.945377 BL = 0x2
744 09:27:39.945463 RPST = 0x0
745 09:27:39.948326 RD_PRE = 0x0
746 09:27:39.948412 WR_PRE = 0x1
747 09:27:39.952165 WR_PST = 0x0
748 09:27:39.955210 DBI_WR = 0x0
749 09:27:39.955296 DBI_RD = 0x0
750 09:27:39.958602 OTF = 0x1
751 09:27:39.958689 ===================================
752 09:27:39.965016 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 09:27:39.970344 nWR fixed to 40
754 09:27:39.973693 [ModeRegInit_LP4] CH0 RK0
755 09:27:39.973780 [ModeRegInit_LP4] CH0 RK1
756 09:27:39.977033 [ModeRegInit_LP4] CH1 RK0
757 09:27:39.980499 [ModeRegInit_LP4] CH1 RK1
758 09:27:39.980585 match AC timing 12
759 09:27:39.986989 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
760 09:27:39.990257 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 09:27:39.993638 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 09:27:40.000352 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 09:27:40.003965 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 09:27:40.004052 [EMI DOE] emi_dcm 0
765 09:27:40.010293 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 09:27:40.010379 ==
767 09:27:40.013630 Dram Type= 6, Freq= 0, CH_0, rank 0
768 09:27:40.016846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
769 09:27:40.016930 ==
770 09:27:40.023434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 09:27:40.030088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 09:27:40.037427 [CA 0] Center 37 (7~68) winsize 62
773 09:27:40.041126 [CA 1] Center 37 (7~68) winsize 62
774 09:27:40.044059 [CA 2] Center 35 (5~66) winsize 62
775 09:27:40.047503 [CA 3] Center 35 (5~66) winsize 62
776 09:27:40.050674 [CA 4] Center 34 (4~65) winsize 62
777 09:27:40.054264 [CA 5] Center 33 (3~64) winsize 62
778 09:27:40.054377
779 09:27:40.057430 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 09:27:40.057514
781 09:27:40.060786 [CATrainingPosCal] consider 1 rank data
782 09:27:40.064104 u2DelayCellTimex100 = 270/100 ps
783 09:27:40.067365 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 09:27:40.070767 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 09:27:40.077455 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 09:27:40.080798 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
787 09:27:40.084257 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
788 09:27:40.087535 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 09:27:40.087618
790 09:27:40.091072 CA PerBit enable=1, Macro0, CA PI delay=33
791 09:27:40.091179
792 09:27:40.094128 [CBTSetCACLKResult] CA Dly = 33
793 09:27:40.094211 CS Dly: 5 (0~36)
794 09:27:40.097675 ==
795 09:27:40.100888 Dram Type= 6, Freq= 0, CH_0, rank 1
796 09:27:40.104128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
797 09:27:40.104221 ==
798 09:27:40.107377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 09:27:40.114121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 09:27:40.123406 [CA 0] Center 37 (7~68) winsize 62
801 09:27:40.126917 [CA 1] Center 37 (6~68) winsize 63
802 09:27:40.130300 [CA 2] Center 35 (4~66) winsize 63
803 09:27:40.133412 [CA 3] Center 34 (4~65) winsize 62
804 09:27:40.136940 [CA 4] Center 33 (3~64) winsize 62
805 09:27:40.140169 [CA 5] Center 33 (3~64) winsize 62
806 09:27:40.140273
807 09:27:40.143559 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 09:27:40.143642
809 09:27:40.147228 [CATrainingPosCal] consider 2 rank data
810 09:27:40.150211 u2DelayCellTimex100 = 270/100 ps
811 09:27:40.153500 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 09:27:40.156814 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 09:27:40.163334 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 09:27:40.166889 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
815 09:27:40.170323 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
816 09:27:40.173753 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 09:27:40.173836
818 09:27:40.176668 CA PerBit enable=1, Macro0, CA PI delay=33
819 09:27:40.176751
820 09:27:40.180165 [CBTSetCACLKResult] CA Dly = 33
821 09:27:40.180287 CS Dly: 6 (0~38)
822 09:27:40.180354
823 09:27:40.186710 ----->DramcWriteLeveling(PI) begin...
824 09:27:40.186794 ==
825 09:27:40.190290 Dram Type= 6, Freq= 0, CH_0, rank 0
826 09:27:40.193345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
827 09:27:40.193428 ==
828 09:27:40.197016 Write leveling (Byte 0): 31 => 31
829 09:27:40.200401 Write leveling (Byte 1): 28 => 28
830 09:27:40.200484 DramcWriteLeveling(PI) end<-----
831 09:27:40.204073
832 09:27:40.204155 ==
833 09:27:40.204262 Dram Type= 6, Freq= 0, CH_0, rank 0
834 09:27:40.211789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
835 09:27:40.211874 ==
836 09:27:40.211940 [Gating] SW mode calibration
837 09:27:40.218672 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 09:27:40.225253 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 09:27:40.229181 0 6 0 | B1->B0 | 3434 3333 | 0 0 | (1 0) (1 0)
840 09:27:40.232838 0 6 4 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
841 09:27:40.239558 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 09:27:40.243030 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 09:27:40.245977 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 09:27:40.252533 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 09:27:40.255939 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 09:27:40.259268 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 09:27:40.265879 0 7 0 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
848 09:27:40.269661 0 7 4 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
849 09:27:40.272715 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 09:27:40.279340 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 09:27:40.283042 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 09:27:40.285987 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 09:27:40.292942 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 09:27:40.295923 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 09:27:40.299184 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
856 09:27:40.302608 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 09:27:40.309260 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 09:27:40.312770 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 09:27:40.316073 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 09:27:40.322644 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 09:27:40.326341 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 09:27:40.329332 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 09:27:40.336065 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 09:27:40.339458 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 09:27:40.342612 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 09:27:40.349320 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 09:27:40.353405 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 09:27:40.356279 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 09:27:40.362897 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 09:27:40.366449 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
871 09:27:40.369631 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
872 09:27:40.373352 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 09:27:40.376569 Total UI for P1: 0, mck2ui 16
874 09:27:40.379549 best dqsien dly found for B0: ( 0, 10, 0)
875 09:27:40.383003 Total UI for P1: 0, mck2ui 16
876 09:27:40.386441 best dqsien dly found for B1: ( 0, 9, 30)
877 09:27:40.389837 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
878 09:27:40.393038 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
879 09:27:40.393121
880 09:27:40.400077 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
881 09:27:40.403143 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
882 09:27:40.406497 [Gating] SW calibration Done
883 09:27:40.406590 ==
884 09:27:40.409805 Dram Type= 6, Freq= 0, CH_0, rank 0
885 09:27:40.413384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 09:27:40.413467 ==
887 09:27:40.413534 RX Vref Scan: 0
888 09:27:40.413596
889 09:27:40.416661 RX Vref 0 -> 0, step: 1
890 09:27:40.416745
891 09:27:40.419830 RX Delay -130 -> 252, step: 16
892 09:27:40.423345 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
893 09:27:40.426424 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
894 09:27:40.433339 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
895 09:27:40.436640 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
896 09:27:40.439817 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
897 09:27:40.442923 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
898 09:27:40.446537 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
899 09:27:40.453034 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
900 09:27:40.456456 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
901 09:27:40.459717 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
902 09:27:40.463365 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
903 09:27:40.466561 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
904 09:27:40.473378 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
905 09:27:40.476535 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
906 09:27:40.479733 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
907 09:27:40.483225 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
908 09:27:40.483309 ==
909 09:27:40.486865 Dram Type= 6, Freq= 0, CH_0, rank 0
910 09:27:40.493010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
911 09:27:40.493094 ==
912 09:27:40.493162 DQS Delay:
913 09:27:40.493224 DQS0 = 0, DQS1 = 0
914 09:27:40.496386 DQM Delay:
915 09:27:40.496469 DQM0 = 84, DQM1 = 74
916 09:27:40.499679 DQ Delay:
917 09:27:40.503128 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
918 09:27:40.506663 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
919 09:27:40.506746 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
920 09:27:40.513019 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
921 09:27:40.513101
922 09:27:40.513167
923 09:27:40.513228 ==
924 09:27:40.516520 Dram Type= 6, Freq= 0, CH_0, rank 0
925 09:27:40.519836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
926 09:27:40.519919 ==
927 09:27:40.519986
928 09:27:40.520048
929 09:27:40.523291 TX Vref Scan disable
930 09:27:40.523374 == TX Byte 0 ==
931 09:27:40.529849 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
932 09:27:40.533348 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
933 09:27:40.533458 == TX Byte 1 ==
934 09:27:40.539941 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
935 09:27:40.543263 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
936 09:27:40.543346 ==
937 09:27:40.546800 Dram Type= 6, Freq= 0, CH_0, rank 0
938 09:27:40.549940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 09:27:40.550023 ==
940 09:27:40.563803 TX Vref=22, minBit 0, minWin=27, winSum=442
941 09:27:40.566918 TX Vref=24, minBit 5, minWin=27, winSum=450
942 09:27:40.570673 TX Vref=26, minBit 2, minWin=28, winSum=456
943 09:27:40.573836 TX Vref=28, minBit 4, minWin=27, winSum=455
944 09:27:40.577201 TX Vref=30, minBit 5, minWin=27, winSum=456
945 09:27:40.580317 TX Vref=32, minBit 0, minWin=28, winSum=453
946 09:27:40.586999 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 26
947 09:27:40.587082
948 09:27:40.590531 Final TX Range 1 Vref 26
949 09:27:40.590614
950 09:27:40.590680 ==
951 09:27:40.593729 Dram Type= 6, Freq= 0, CH_0, rank 0
952 09:27:40.597662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 09:27:40.597745 ==
954 09:27:40.597811
955 09:27:40.597872
956 09:27:40.600968 TX Vref Scan disable
957 09:27:40.604687 == TX Byte 0 ==
958 09:27:40.608069 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
959 09:27:40.611225 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
960 09:27:40.614419 == TX Byte 1 ==
961 09:27:40.618189 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
962 09:27:40.621221 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
963 09:27:40.621305
964 09:27:40.624658 [DATLAT]
965 09:27:40.624741 Freq=800, CH0 RK0
966 09:27:40.624807
967 09:27:40.628122 DATLAT Default: 0xa
968 09:27:40.628243 0, 0xFFFF, sum = 0
969 09:27:40.631439 1, 0xFFFF, sum = 0
970 09:27:40.631526 2, 0xFFFF, sum = 0
971 09:27:40.634702 3, 0xFFFF, sum = 0
972 09:27:40.634786 4, 0xFFFF, sum = 0
973 09:27:40.637956 5, 0xFFFF, sum = 0
974 09:27:40.638041 6, 0xFFFF, sum = 0
975 09:27:40.641406 7, 0xFFFF, sum = 0
976 09:27:40.641491 8, 0x0, sum = 1
977 09:27:40.644741 9, 0x0, sum = 2
978 09:27:40.644840 10, 0x0, sum = 3
979 09:27:40.647860 11, 0x0, sum = 4
980 09:27:40.647944 best_step = 9
981 09:27:40.648010
982 09:27:40.648070 ==
983 09:27:40.651236 Dram Type= 6, Freq= 0, CH_0, rank 0
984 09:27:40.654550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
985 09:27:40.654634 ==
986 09:27:40.658044 RX Vref Scan: 1
987 09:27:40.658126
988 09:27:40.661158 Set Vref Range= 32 -> 127
989 09:27:40.661241
990 09:27:40.661307 RX Vref 32 -> 127, step: 1
991 09:27:40.661370
992 09:27:40.664723 RX Delay -111 -> 252, step: 8
993 09:27:40.664806
994 09:27:40.667747 Set Vref, RX VrefLevel [Byte0]: 32
995 09:27:40.671031 [Byte1]: 32
996 09:27:40.674761
997 09:27:40.674865 Set Vref, RX VrefLevel [Byte0]: 33
998 09:27:40.677944 [Byte1]: 33
999 09:27:40.682491
1000 09:27:40.682574 Set Vref, RX VrefLevel [Byte0]: 34
1001 09:27:40.685388 [Byte1]: 34
1002 09:27:40.689794
1003 09:27:40.689876 Set Vref, RX VrefLevel [Byte0]: 35
1004 09:27:40.693098 [Byte1]: 35
1005 09:27:40.697695
1006 09:27:40.697778 Set Vref, RX VrefLevel [Byte0]: 36
1007 09:27:40.701155 [Byte1]: 36
1008 09:27:40.705474
1009 09:27:40.705558 Set Vref, RX VrefLevel [Byte0]: 37
1010 09:27:40.708551 [Byte1]: 37
1011 09:27:40.713036
1012 09:27:40.713141 Set Vref, RX VrefLevel [Byte0]: 38
1013 09:27:40.716328 [Byte1]: 38
1014 09:27:40.720524
1015 09:27:40.720608 Set Vref, RX VrefLevel [Byte0]: 39
1016 09:27:40.723758 [Byte1]: 39
1017 09:27:40.728077
1018 09:27:40.728161 Set Vref, RX VrefLevel [Byte0]: 40
1019 09:27:40.731451 [Byte1]: 40
1020 09:27:40.735776
1021 09:27:40.735859 Set Vref, RX VrefLevel [Byte0]: 41
1022 09:27:40.739122 [Byte1]: 41
1023 09:27:40.743599
1024 09:27:40.743690 Set Vref, RX VrefLevel [Byte0]: 42
1025 09:27:40.746708 [Byte1]: 42
1026 09:27:40.751130
1027 09:27:40.751211 Set Vref, RX VrefLevel [Byte0]: 43
1028 09:27:40.754462 [Byte1]: 43
1029 09:27:40.758825
1030 09:27:40.758924 Set Vref, RX VrefLevel [Byte0]: 44
1031 09:27:40.761976 [Byte1]: 44
1032 09:27:40.766439
1033 09:27:40.766520 Set Vref, RX VrefLevel [Byte0]: 45
1034 09:27:40.769744 [Byte1]: 45
1035 09:27:40.774226
1036 09:27:40.774310 Set Vref, RX VrefLevel [Byte0]: 46
1037 09:27:40.777429 [Byte1]: 46
1038 09:27:40.781765
1039 09:27:40.781845 Set Vref, RX VrefLevel [Byte0]: 47
1040 09:27:40.784998 [Byte1]: 47
1041 09:27:40.789261
1042 09:27:40.789342 Set Vref, RX VrefLevel [Byte0]: 48
1043 09:27:40.792685 [Byte1]: 48
1044 09:27:40.797166
1045 09:27:40.797247 Set Vref, RX VrefLevel [Byte0]: 49
1046 09:27:40.800508 [Byte1]: 49
1047 09:27:40.804907
1048 09:27:40.804989 Set Vref, RX VrefLevel [Byte0]: 50
1049 09:27:40.807952 [Byte1]: 50
1050 09:27:40.812311
1051 09:27:40.812392 Set Vref, RX VrefLevel [Byte0]: 51
1052 09:27:40.818841 [Byte1]: 51
1053 09:27:40.818924
1054 09:27:40.822143 Set Vref, RX VrefLevel [Byte0]: 52
1055 09:27:40.825734 [Byte1]: 52
1056 09:27:40.825816
1057 09:27:40.828835 Set Vref, RX VrefLevel [Byte0]: 53
1058 09:27:40.832137 [Byte1]: 53
1059 09:27:40.832269
1060 09:27:40.835548 Set Vref, RX VrefLevel [Byte0]: 54
1061 09:27:40.838850 [Byte1]: 54
1062 09:27:40.843184
1063 09:27:40.843273 Set Vref, RX VrefLevel [Byte0]: 55
1064 09:27:40.846418 [Byte1]: 55
1065 09:27:40.850490
1066 09:27:40.850571 Set Vref, RX VrefLevel [Byte0]: 56
1067 09:27:40.853950 [Byte1]: 56
1068 09:27:40.858444
1069 09:27:40.858525 Set Vref, RX VrefLevel [Byte0]: 57
1070 09:27:40.861302 [Byte1]: 57
1071 09:27:40.866359
1072 09:27:40.866441 Set Vref, RX VrefLevel [Byte0]: 58
1073 09:27:40.869550 [Byte1]: 58
1074 09:27:40.873768
1075 09:27:40.873850 Set Vref, RX VrefLevel [Byte0]: 59
1076 09:27:40.877354 [Byte1]: 59
1077 09:27:40.881519
1078 09:27:40.881600 Set Vref, RX VrefLevel [Byte0]: 60
1079 09:27:40.885444 [Byte1]: 60
1080 09:27:40.888943
1081 09:27:40.889024 Set Vref, RX VrefLevel [Byte0]: 61
1082 09:27:40.892106 [Byte1]: 61
1083 09:27:40.896674
1084 09:27:40.896755 Set Vref, RX VrefLevel [Byte0]: 62
1085 09:27:40.900060 [Byte1]: 62
1086 09:27:40.903758
1087 09:27:40.903840 Set Vref, RX VrefLevel [Byte0]: 63
1088 09:27:40.907317 [Byte1]: 63
1089 09:27:40.911768
1090 09:27:40.911849 Set Vref, RX VrefLevel [Byte0]: 64
1091 09:27:40.918106 [Byte1]: 64
1092 09:27:40.918188
1093 09:27:40.921213 Set Vref, RX VrefLevel [Byte0]: 65
1094 09:27:40.924579 [Byte1]: 65
1095 09:27:40.924661
1096 09:27:40.928089 Set Vref, RX VrefLevel [Byte0]: 66
1097 09:27:40.931253 [Byte1]: 66
1098 09:27:40.934703
1099 09:27:40.934784 Set Vref, RX VrefLevel [Byte0]: 67
1100 09:27:40.938024 [Byte1]: 67
1101 09:27:40.942471
1102 09:27:40.942553 Set Vref, RX VrefLevel [Byte0]: 68
1103 09:27:40.945566 [Byte1]: 68
1104 09:27:40.949898
1105 09:27:40.949978 Set Vref, RX VrefLevel [Byte0]: 69
1106 09:27:40.953458 [Byte1]: 69
1107 09:27:40.957478
1108 09:27:40.957562 Set Vref, RX VrefLevel [Byte0]: 70
1109 09:27:40.960794 [Byte1]: 70
1110 09:27:40.965266
1111 09:27:40.965348 Set Vref, RX VrefLevel [Byte0]: 71
1112 09:27:40.968291 [Byte1]: 71
1113 09:27:40.972773
1114 09:27:40.972854 Set Vref, RX VrefLevel [Byte0]: 72
1115 09:27:40.976340 [Byte1]: 72
1116 09:27:40.980405
1117 09:27:40.980514 Set Vref, RX VrefLevel [Byte0]: 73
1118 09:27:40.983767 [Byte1]: 73
1119 09:27:40.988056
1120 09:27:40.988167 Set Vref, RX VrefLevel [Byte0]: 74
1121 09:27:40.991395 [Byte1]: 74
1122 09:27:40.995822
1123 09:27:40.995931 Set Vref, RX VrefLevel [Byte0]: 75
1124 09:27:40.998926 [Byte1]: 75
1125 09:27:41.003381
1126 09:27:41.003463 Final RX Vref Byte 0 = 52 to rank0
1127 09:27:41.006717 Final RX Vref Byte 1 = 48 to rank0
1128 09:27:41.010234 Final RX Vref Byte 0 = 52 to rank1
1129 09:27:41.013624 Final RX Vref Byte 1 = 48 to rank1==
1130 09:27:41.017176 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 09:27:41.020171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1132 09:27:41.023532 ==
1133 09:27:41.023613 DQS Delay:
1134 09:27:41.023679 DQS0 = 0, DQS1 = 0
1135 09:27:41.026909 DQM Delay:
1136 09:27:41.026992 DQM0 = 83, DQM1 = 73
1137 09:27:41.030427 DQ Delay:
1138 09:27:41.033545 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1139 09:27:41.033627 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1140 09:27:41.036762 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1141 09:27:41.040067 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1142 09:27:41.040149
1143 09:27:41.043553
1144 09:27:41.050295 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1145 09:27:41.053344 CH0 RK0: MR19=606, MR18=3A3A
1146 09:27:41.059870 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1147 09:27:41.059952
1148 09:27:41.063381 ----->DramcWriteLeveling(PI) begin...
1149 09:27:41.063464 ==
1150 09:27:41.066770 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 09:27:41.070063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 09:27:41.070145 ==
1153 09:27:41.073128 Write leveling (Byte 0): 30 => 30
1154 09:27:41.076573 Write leveling (Byte 1): 30 => 30
1155 09:27:41.079882 DramcWriteLeveling(PI) end<-----
1156 09:27:41.079964
1157 09:27:41.080027 ==
1158 09:27:41.083156 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 09:27:41.086567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 09:27:41.086649 ==
1161 09:27:41.090015 [Gating] SW mode calibration
1162 09:27:41.096453 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 09:27:41.103336 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 09:27:41.106601 0 6 0 | B1->B0 | 3030 3131 | 0 0 | (0 1) (1 0)
1165 09:27:41.109934 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1166 09:27:41.116480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:27:41.119799 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:27:41.123252 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:27:41.130142 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:27:41.133511 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:27:41.136865 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:27:41.143457 0 7 0 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
1173 09:27:41.146447 0 7 4 | B1->B0 | 4444 4545 | 1 0 | (0 0) (0 0)
1174 09:27:41.150055 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1175 09:27:41.156633 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1176 09:27:41.159887 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1177 09:27:41.163273 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1178 09:27:41.166591 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1179 09:27:41.173320 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 09:27:41.176976 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1181 09:27:41.180367 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1182 09:27:41.186780 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1183 09:27:41.189873 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1184 09:27:41.193531 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1185 09:27:41.200140 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1186 09:27:41.203345 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 09:27:41.207038 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 09:27:41.213483 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 09:27:41.216851 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 09:27:41.220511 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 09:27:41.226676 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 09:27:41.230226 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 09:27:41.233789 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 09:27:41.240040 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 09:27:41.243357 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1196 09:27:41.246724 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1197 09:27:41.249926 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 09:27:41.253530 Total UI for P1: 0, mck2ui 16
1199 09:27:41.256696 best dqsien dly found for B0: ( 0, 9, 30)
1200 09:27:41.259909 Total UI for P1: 0, mck2ui 16
1201 09:27:41.263663 best dqsien dly found for B1: ( 0, 10, 0)
1202 09:27:41.266816 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1203 09:27:41.270208 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1204 09:27:41.273300
1205 09:27:41.276670 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1206 09:27:41.280049 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1207 09:27:41.323851 [Gating] SW calibration Done
1208 09:27:41.323944 ==
1209 09:27:41.324011 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 09:27:41.324308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1211 09:27:41.324379 ==
1212 09:27:41.324440 RX Vref Scan: 0
1213 09:27:41.324499
1214 09:27:41.324557 RX Vref 0 -> 0, step: 1
1215 09:27:41.324613
1216 09:27:41.324697 RX Delay -130 -> 252, step: 16
1217 09:27:41.324768 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1218 09:27:41.324828 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1219 09:27:41.324884 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1220 09:27:41.325138 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1221 09:27:41.325227 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1222 09:27:41.325651 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1223 09:27:41.325733 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1224 09:27:41.328451 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1225 09:27:41.331937 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1226 09:27:41.335223 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1227 09:27:41.341927 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1228 09:27:41.345206 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1229 09:27:41.348541 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1230 09:27:41.352131 iDelay=222, Bit 13, Center 69 (-50 ~ 189) 240
1231 09:27:41.355337 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1232 09:27:41.361930 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1233 09:27:41.362011 ==
1234 09:27:41.365536 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 09:27:41.368828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1236 09:27:41.368910 ==
1237 09:27:41.368975 DQS Delay:
1238 09:27:41.371945 DQS0 = 0, DQS1 = 0
1239 09:27:41.372055 DQM Delay:
1240 09:27:41.375427 DQM0 = 82, DQM1 = 69
1241 09:27:41.375512 DQ Delay:
1242 09:27:41.378493 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1243 09:27:41.381853 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1244 09:27:41.385484 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1245 09:27:41.388888 DQ12 =77, DQ13 =69, DQ14 =85, DQ15 =77
1246 09:27:41.388970
1247 09:27:41.389034
1248 09:27:41.389094 ==
1249 09:27:41.392045 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 09:27:41.395526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 09:27:41.395621 ==
1252 09:27:41.398549
1253 09:27:41.398630
1254 09:27:41.398695 TX Vref Scan disable
1255 09:27:41.401852 == TX Byte 0 ==
1256 09:27:41.405251 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1257 09:27:41.408506 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1258 09:27:41.412068 == TX Byte 1 ==
1259 09:27:41.415452 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1260 09:27:41.418715 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1261 09:27:41.418797 ==
1262 09:27:41.422385 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 09:27:41.428567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1264 09:27:41.428650 ==
1265 09:27:41.440511 TX Vref=22, minBit 5, minWin=27, winSum=450
1266 09:27:41.443911 TX Vref=24, minBit 2, minWin=28, winSum=453
1267 09:27:41.447469 TX Vref=26, minBit 2, minWin=28, winSum=457
1268 09:27:41.451449 TX Vref=28, minBit 2, minWin=28, winSum=459
1269 09:27:41.455540 TX Vref=30, minBit 2, minWin=28, winSum=459
1270 09:27:41.459098 TX Vref=32, minBit 2, minWin=28, winSum=458
1271 09:27:41.465758 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1272 09:27:41.465841
1273 09:27:41.465906 Final TX Range 1 Vref 28
1274 09:27:41.465967
1275 09:27:41.466025 ==
1276 09:27:41.468938 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 09:27:41.476071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1278 09:27:41.476153 ==
1279 09:27:41.476257
1280 09:27:41.476317
1281 09:27:41.476375 TX Vref Scan disable
1282 09:27:41.480075 == TX Byte 0 ==
1283 09:27:41.483883 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1284 09:27:41.486764 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1285 09:27:41.489945 == TX Byte 1 ==
1286 09:27:41.493500 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1287 09:27:41.496795 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1288 09:27:41.500714
1289 09:27:41.500794 [DATLAT]
1290 09:27:41.500858 Freq=800, CH0 RK1
1291 09:27:41.500920
1292 09:27:41.503620 DATLAT Default: 0x9
1293 09:27:41.503700 0, 0xFFFF, sum = 0
1294 09:27:41.506765 1, 0xFFFF, sum = 0
1295 09:27:41.506848 2, 0xFFFF, sum = 0
1296 09:27:41.510215 3, 0xFFFF, sum = 0
1297 09:27:41.510298 4, 0xFFFF, sum = 0
1298 09:27:41.513647 5, 0xFFFF, sum = 0
1299 09:27:41.516826 6, 0xFFFF, sum = 0
1300 09:27:41.516909 7, 0xFFFF, sum = 0
1301 09:27:41.516975 8, 0x0, sum = 1
1302 09:27:41.520031 9, 0x0, sum = 2
1303 09:27:41.520114 10, 0x0, sum = 3
1304 09:27:41.523394 11, 0x0, sum = 4
1305 09:27:41.523476 best_step = 9
1306 09:27:41.523541
1307 09:27:41.523601 ==
1308 09:27:41.526566 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 09:27:41.533177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1310 09:27:41.533259 ==
1311 09:27:41.533324 RX Vref Scan: 0
1312 09:27:41.533384
1313 09:27:41.537101 RX Vref 0 -> 0, step: 1
1314 09:27:41.537183
1315 09:27:41.539902 RX Delay -111 -> 252, step: 8
1316 09:27:41.543342 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1317 09:27:41.546531 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1318 09:27:41.553249 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1319 09:27:41.556658 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1320 09:27:41.560026 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1321 09:27:41.563204 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1322 09:27:41.566465 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1323 09:27:41.573188 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1324 09:27:41.576471 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1325 09:27:41.579810 iDelay=217, Bit 9, Center 56 (-55 ~ 168) 224
1326 09:27:41.583397 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1327 09:27:41.586670 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1328 09:27:41.593318 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1329 09:27:41.596419 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1330 09:27:41.599808 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1331 09:27:41.603265 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1332 09:27:41.603347 ==
1333 09:27:41.606563 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 09:27:41.613196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1335 09:27:41.613278 ==
1336 09:27:41.613343 DQS Delay:
1337 09:27:41.613403 DQS0 = 0, DQS1 = 0
1338 09:27:41.616412 DQM Delay:
1339 09:27:41.616493 DQM0 = 86, DQM1 = 73
1340 09:27:41.620123 DQ Delay:
1341 09:27:41.623168 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1342 09:27:41.623249 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1343 09:27:41.626706 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1344 09:27:41.629914 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1345 09:27:41.633332
1346 09:27:41.633413
1347 09:27:41.639868 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1348 09:27:41.643216 CH0 RK1: MR19=606, MR18=4C4C
1349 09:27:41.650042 CH0_RK1: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1350 09:27:41.653124 [RxdqsGatingPostProcess] freq 800
1351 09:27:41.656444 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1352 09:27:41.659741 Pre-setting of DQS Precalculation
1353 09:27:41.663300 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1354 09:27:41.666946 ==
1355 09:27:41.669948 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 09:27:41.673091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 09:27:41.673172 ==
1358 09:27:41.676486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1359 09:27:41.683314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1360 09:27:41.692998 [CA 0] Center 36 (6~67) winsize 62
1361 09:27:41.696324 [CA 1] Center 36 (6~67) winsize 62
1362 09:27:41.699458 [CA 2] Center 34 (4~65) winsize 62
1363 09:27:41.702832 [CA 3] Center 34 (3~65) winsize 63
1364 09:27:41.706106 [CA 4] Center 33 (3~64) winsize 62
1365 09:27:41.709526 [CA 5] Center 33 (3~64) winsize 62
1366 09:27:41.709607
1367 09:27:41.712759 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1368 09:27:41.712840
1369 09:27:41.716476 [CATrainingPosCal] consider 1 rank data
1370 09:27:41.719488 u2DelayCellTimex100 = 270/100 ps
1371 09:27:41.722741 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1372 09:27:41.729314 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1373 09:27:41.732887 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1374 09:27:41.735889 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1375 09:27:41.739192 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1376 09:27:41.742445 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1377 09:27:41.742526
1378 09:27:41.746038 CA PerBit enable=1, Macro0, CA PI delay=33
1379 09:27:41.746119
1380 09:27:41.749501 [CBTSetCACLKResult] CA Dly = 33
1381 09:27:41.749581 CS Dly: 4 (0~35)
1382 09:27:41.752634 ==
1383 09:27:41.755899 Dram Type= 6, Freq= 0, CH_1, rank 1
1384 09:27:41.759240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1385 09:27:41.759323 ==
1386 09:27:41.762441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1387 09:27:41.769187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1388 09:27:41.778645 [CA 0] Center 36 (6~67) winsize 62
1389 09:27:41.782128 [CA 1] Center 36 (5~67) winsize 63
1390 09:27:41.785625 [CA 2] Center 34 (4~65) winsize 62
1391 09:27:41.788563 [CA 3] Center 33 (3~64) winsize 62
1392 09:27:41.792553 [CA 4] Center 33 (3~64) winsize 62
1393 09:27:41.795308 [CA 5] Center 33 (3~64) winsize 62
1394 09:27:41.795389
1395 09:27:41.798961 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1396 09:27:41.799042
1397 09:27:41.802043 [CATrainingPosCal] consider 2 rank data
1398 09:27:41.805873 u2DelayCellTimex100 = 270/100 ps
1399 09:27:41.808726 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1400 09:27:41.812150 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1401 09:27:41.815312 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 09:27:41.822130 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 09:27:41.825678 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 09:27:41.828788 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1405 09:27:41.828869
1406 09:27:41.832350 CA PerBit enable=1, Macro0, CA PI delay=33
1407 09:27:41.832432
1408 09:27:41.835648 [CBTSetCACLKResult] CA Dly = 33
1409 09:27:41.835730 CS Dly: 4 (0~36)
1410 09:27:41.835795
1411 09:27:41.838826 ----->DramcWriteLeveling(PI) begin...
1412 09:27:41.838909 ==
1413 09:27:41.842454 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 09:27:41.848986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 09:27:41.849068 ==
1416 09:27:41.851712 Write leveling (Byte 0): 25 => 25
1417 09:27:41.855479 Write leveling (Byte 1): 25 => 25
1418 09:27:41.858765 DramcWriteLeveling(PI) end<-----
1419 09:27:41.858846
1420 09:27:41.858911 ==
1421 09:27:41.861731 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 09:27:41.865018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1423 09:27:41.865099 ==
1424 09:27:41.868475 [Gating] SW mode calibration
1425 09:27:41.875230 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1426 09:27:41.878476 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1427 09:27:41.885089 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
1428 09:27:41.888488 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1429 09:27:41.891655 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1430 09:27:41.898497 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1431 09:27:41.901895 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1432 09:27:41.905112 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1433 09:27:41.911885 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1434 09:27:41.915151 0 6 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1435 09:27:41.918597 0 7 0 | B1->B0 | 3131 3f3f | 0 1 | (0 0) (0 0)
1436 09:27:41.925212 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1437 09:27:41.928360 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1438 09:27:41.932124 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1439 09:27:41.938782 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1440 09:27:41.942011 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1441 09:27:41.945108 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1442 09:27:41.951835 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 09:27:41.955025 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1444 09:27:41.958353 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1445 09:27:41.965134 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1446 09:27:41.968512 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1447 09:27:41.971744 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1448 09:27:41.975016 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1449 09:27:41.981589 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 09:27:41.985059 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 09:27:41.988637 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 09:27:41.994981 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 09:27:41.998380 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 09:27:42.001778 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 09:27:42.008470 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 09:27:42.011647 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 09:27:42.015494 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 09:27:42.021819 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1459 09:27:42.025201 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1460 09:27:42.028633 Total UI for P1: 0, mck2ui 16
1461 09:27:42.031786 best dqsien dly found for B1: ( 0, 9, 28)
1462 09:27:42.035033 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1463 09:27:42.038521 Total UI for P1: 0, mck2ui 16
1464 09:27:42.041801 best dqsien dly found for B0: ( 0, 10, 0)
1465 09:27:42.045453 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1466 09:27:42.048304 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1467 09:27:42.048384
1468 09:27:42.054780 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1469 09:27:42.058400 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1470 09:27:42.058516 [Gating] SW calibration Done
1471 09:27:42.062157 ==
1472 09:27:42.064890 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 09:27:42.068288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1474 09:27:42.068369 ==
1475 09:27:42.068433 RX Vref Scan: 0
1476 09:27:42.068493
1477 09:27:42.072036 RX Vref 0 -> 0, step: 1
1478 09:27:42.072116
1479 09:27:42.074849 RX Delay -130 -> 252, step: 16
1480 09:27:42.078172 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1481 09:27:42.081436 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1482 09:27:42.084858 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1483 09:27:42.091464 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1484 09:27:42.094769 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1485 09:27:42.098413 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1486 09:27:42.101954 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1487 09:27:42.104845 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1488 09:27:42.112067 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1489 09:27:42.115967 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1490 09:27:42.119293 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1491 09:27:42.122981 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1492 09:27:42.126797 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1493 09:27:42.130407 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1494 09:27:42.134134 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1495 09:27:42.137892 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1496 09:27:42.137974 ==
1497 09:27:42.141342 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 09:27:42.145181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1499 09:27:42.145263 ==
1500 09:27:42.148610 DQS Delay:
1501 09:27:42.148691 DQS0 = 0, DQS1 = 0
1502 09:27:42.151930 DQM Delay:
1503 09:27:42.152012 DQM0 = 81, DQM1 = 72
1504 09:27:42.152077 DQ Delay:
1505 09:27:42.155292 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1506 09:27:42.158449 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1507 09:27:42.161683 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1508 09:27:42.165121 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1509 09:27:42.165203
1510 09:27:42.165267
1511 09:27:42.168375 ==
1512 09:27:42.168456 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 09:27:42.174878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 09:27:42.174960 ==
1515 09:27:42.175025
1516 09:27:42.175085
1517 09:27:42.178156 TX Vref Scan disable
1518 09:27:42.178238 == TX Byte 0 ==
1519 09:27:42.181852 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1520 09:27:42.188345 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1521 09:27:42.188427 == TX Byte 1 ==
1522 09:27:42.191802 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1523 09:27:42.198577 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1524 09:27:42.198659 ==
1525 09:27:42.202102 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 09:27:42.205036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1527 09:27:42.205118 ==
1528 09:27:42.217809 TX Vref=22, minBit 3, minWin=27, winSum=447
1529 09:27:42.221687 TX Vref=24, minBit 3, minWin=27, winSum=449
1530 09:27:42.224349 TX Vref=26, minBit 0, minWin=28, winSum=454
1531 09:27:42.227842 TX Vref=28, minBit 0, minWin=28, winSum=453
1532 09:27:42.231355 TX Vref=30, minBit 0, minWin=28, winSum=455
1533 09:27:42.234430 TX Vref=32, minBit 2, minWin=28, winSum=454
1534 09:27:42.241061 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1535 09:27:42.241144
1536 09:27:42.244714 Final TX Range 1 Vref 30
1537 09:27:42.244796
1538 09:27:42.244860 ==
1539 09:27:42.247975 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 09:27:42.251205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1541 09:27:42.251286 ==
1542 09:27:42.251351
1543 09:27:42.251411
1544 09:27:42.254859 TX Vref Scan disable
1545 09:27:42.257979 == TX Byte 0 ==
1546 09:27:42.261141 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1547 09:27:42.264470 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1548 09:27:42.268047 == TX Byte 1 ==
1549 09:27:42.271757 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1550 09:27:42.274744 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1551 09:27:42.274830
1552 09:27:42.277857 [DATLAT]
1553 09:27:42.277938 Freq=800, CH1 RK0
1554 09:27:42.278003
1555 09:27:42.281049 DATLAT Default: 0xa
1556 09:27:42.281130 0, 0xFFFF, sum = 0
1557 09:27:42.284505 1, 0xFFFF, sum = 0
1558 09:27:42.284587 2, 0xFFFF, sum = 0
1559 09:27:42.287868 3, 0xFFFF, sum = 0
1560 09:27:42.287950 4, 0xFFFF, sum = 0
1561 09:27:42.290968 5, 0xFFFF, sum = 0
1562 09:27:42.291060 6, 0xFFFF, sum = 0
1563 09:27:42.294672 7, 0xFFFF, sum = 0
1564 09:27:42.294755 8, 0x0, sum = 1
1565 09:27:42.297611 9, 0x0, sum = 2
1566 09:27:42.297693 10, 0x0, sum = 3
1567 09:27:42.301237 11, 0x0, sum = 4
1568 09:27:42.301319 best_step = 9
1569 09:27:42.301384
1570 09:27:42.301445 ==
1571 09:27:42.304463 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 09:27:42.311461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1573 09:27:42.311542 ==
1574 09:27:42.311608 RX Vref Scan: 1
1575 09:27:42.311668
1576 09:27:42.314206 Set Vref Range= 32 -> 127
1577 09:27:42.314288
1578 09:27:42.317594 RX Vref 32 -> 127, step: 1
1579 09:27:42.317675
1580 09:27:42.320721 RX Delay -111 -> 252, step: 8
1581 09:27:42.320803
1582 09:27:42.320868 Set Vref, RX VrefLevel [Byte0]: 32
1583 09:27:42.324085 [Byte1]: 32
1584 09:27:42.328988
1585 09:27:42.329069 Set Vref, RX VrefLevel [Byte0]: 33
1586 09:27:42.331736 [Byte1]: 33
1587 09:27:42.336089
1588 09:27:42.336233 Set Vref, RX VrefLevel [Byte0]: 34
1589 09:27:42.339762 [Byte1]: 34
1590 09:27:42.343859
1591 09:27:42.343941 Set Vref, RX VrefLevel [Byte0]: 35
1592 09:27:42.347268 [Byte1]: 35
1593 09:27:42.351357
1594 09:27:42.351439 Set Vref, RX VrefLevel [Byte0]: 36
1595 09:27:42.354748 [Byte1]: 36
1596 09:27:42.359395
1597 09:27:42.359475 Set Vref, RX VrefLevel [Byte0]: 37
1598 09:27:42.362321 [Byte1]: 37
1599 09:27:42.366632
1600 09:27:42.366713 Set Vref, RX VrefLevel [Byte0]: 38
1601 09:27:42.370224 [Byte1]: 38
1602 09:27:42.374417
1603 09:27:42.374498 Set Vref, RX VrefLevel [Byte0]: 39
1604 09:27:42.377607 [Byte1]: 39
1605 09:27:42.382212
1606 09:27:42.382293 Set Vref, RX VrefLevel [Byte0]: 40
1607 09:27:42.385285 [Byte1]: 40
1608 09:27:42.389695
1609 09:27:42.389776 Set Vref, RX VrefLevel [Byte0]: 41
1610 09:27:42.393199 [Byte1]: 41
1611 09:27:42.397368
1612 09:27:42.397449 Set Vref, RX VrefLevel [Byte0]: 42
1613 09:27:42.400825 [Byte1]: 42
1614 09:27:42.404984
1615 09:27:42.405065 Set Vref, RX VrefLevel [Byte0]: 43
1616 09:27:42.408390 [Byte1]: 43
1617 09:27:42.412804
1618 09:27:42.412884 Set Vref, RX VrefLevel [Byte0]: 44
1619 09:27:42.416341 [Byte1]: 44
1620 09:27:42.420432
1621 09:27:42.420513 Set Vref, RX VrefLevel [Byte0]: 45
1622 09:27:42.424024 [Byte1]: 45
1623 09:27:42.428082
1624 09:27:42.428213 Set Vref, RX VrefLevel [Byte0]: 46
1625 09:27:42.431262 [Byte1]: 46
1626 09:27:42.435885
1627 09:27:42.435991 Set Vref, RX VrefLevel [Byte0]: 47
1628 09:27:42.438742 [Byte1]: 47
1629 09:27:42.443294
1630 09:27:42.443376 Set Vref, RX VrefLevel [Byte0]: 48
1631 09:27:42.446477 [Byte1]: 48
1632 09:27:42.450773
1633 09:27:42.450856 Set Vref, RX VrefLevel [Byte0]: 49
1634 09:27:42.454784 [Byte1]: 49
1635 09:27:42.458465
1636 09:27:42.458546 Set Vref, RX VrefLevel [Byte0]: 50
1637 09:27:42.461907 [Byte1]: 50
1638 09:27:42.466186
1639 09:27:42.466265 Set Vref, RX VrefLevel [Byte0]: 51
1640 09:27:42.469348 [Byte1]: 51
1641 09:27:42.474019
1642 09:27:42.474100 Set Vref, RX VrefLevel [Byte0]: 52
1643 09:27:42.477326 [Byte1]: 52
1644 09:27:42.481636
1645 09:27:42.481717 Set Vref, RX VrefLevel [Byte0]: 53
1646 09:27:42.484806 [Byte1]: 53
1647 09:27:42.489202
1648 09:27:42.489283 Set Vref, RX VrefLevel [Byte0]: 54
1649 09:27:42.492488 [Byte1]: 54
1650 09:27:42.496804
1651 09:27:42.496885 Set Vref, RX VrefLevel [Byte0]: 55
1652 09:27:42.500020 [Byte1]: 55
1653 09:27:42.504757
1654 09:27:42.504838 Set Vref, RX VrefLevel [Byte0]: 56
1655 09:27:42.507864 [Byte1]: 56
1656 09:27:42.512283
1657 09:27:42.512363 Set Vref, RX VrefLevel [Byte0]: 57
1658 09:27:42.515209 [Byte1]: 57
1659 09:27:42.519806
1660 09:27:42.519886 Set Vref, RX VrefLevel [Byte0]: 58
1661 09:27:42.523127 [Byte1]: 58
1662 09:27:42.527277
1663 09:27:42.527357 Set Vref, RX VrefLevel [Byte0]: 59
1664 09:27:42.530532 [Byte1]: 59
1665 09:27:42.535032
1666 09:27:42.535155 Set Vref, RX VrefLevel [Byte0]: 60
1667 09:27:42.538242 [Byte1]: 60
1668 09:27:42.542531
1669 09:27:42.542612 Set Vref, RX VrefLevel [Byte0]: 61
1670 09:27:42.545862 [Byte1]: 61
1671 09:27:42.550503
1672 09:27:42.550584 Set Vref, RX VrefLevel [Byte0]: 62
1673 09:27:42.553493 [Byte1]: 62
1674 09:27:42.557843
1675 09:27:42.557924 Set Vref, RX VrefLevel [Byte0]: 63
1676 09:27:42.561418 [Byte1]: 63
1677 09:27:42.565620
1678 09:27:42.565701 Set Vref, RX VrefLevel [Byte0]: 64
1679 09:27:42.568933 [Byte1]: 64
1680 09:27:42.573291
1681 09:27:42.573372 Set Vref, RX VrefLevel [Byte0]: 65
1682 09:27:42.576760 [Byte1]: 65
1683 09:27:42.581010
1684 09:27:42.581091 Set Vref, RX VrefLevel [Byte0]: 66
1685 09:27:42.584227 [Byte1]: 66
1686 09:27:42.588438
1687 09:27:42.588519 Set Vref, RX VrefLevel [Byte0]: 67
1688 09:27:42.591946 [Byte1]: 67
1689 09:27:42.596333
1690 09:27:42.596414 Set Vref, RX VrefLevel [Byte0]: 68
1691 09:27:42.599441 [Byte1]: 68
1692 09:27:42.603800
1693 09:27:42.603881 Set Vref, RX VrefLevel [Byte0]: 69
1694 09:27:42.607110 [Byte1]: 69
1695 09:27:42.611885
1696 09:27:42.611966 Set Vref, RX VrefLevel [Byte0]: 70
1697 09:27:42.614892 [Byte1]: 70
1698 09:27:42.619270
1699 09:27:42.619352 Set Vref, RX VrefLevel [Byte0]: 71
1700 09:27:42.622350 [Byte1]: 71
1701 09:27:42.626636
1702 09:27:42.626717 Set Vref, RX VrefLevel [Byte0]: 72
1703 09:27:42.630280 [Byte1]: 72
1704 09:27:42.634476
1705 09:27:42.634557 Set Vref, RX VrefLevel [Byte0]: 73
1706 09:27:42.637589 [Byte1]: 73
1707 09:27:42.642000
1708 09:27:42.642081 Final RX Vref Byte 0 = 60 to rank0
1709 09:27:42.645782 Final RX Vref Byte 1 = 59 to rank0
1710 09:27:42.648818 Final RX Vref Byte 0 = 60 to rank1
1711 09:27:42.652148 Final RX Vref Byte 1 = 59 to rank1==
1712 09:27:42.655832 Dram Type= 6, Freq= 0, CH_1, rank 0
1713 09:27:42.662087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1714 09:27:42.662169 ==
1715 09:27:42.662234 DQS Delay:
1716 09:27:42.662295 DQS0 = 0, DQS1 = 0
1717 09:27:42.665534 DQM Delay:
1718 09:27:42.665615 DQM0 = 79, DQM1 = 72
1719 09:27:42.668787 DQ Delay:
1720 09:27:42.671889 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1721 09:27:42.671970 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1722 09:27:42.675619 DQ8 =56, DQ9 =64, DQ10 =76, DQ11 =64
1723 09:27:42.682176 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1724 09:27:42.682282
1725 09:27:42.682374
1726 09:27:42.688899 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1727 09:27:42.692559 CH1 RK0: MR19=606, MR18=5252
1728 09:27:42.696048 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1729 09:27:42.699636
1730 09:27:42.702698 ----->DramcWriteLeveling(PI) begin...
1731 09:27:42.702781 ==
1732 09:27:42.706124 Dram Type= 6, Freq= 0, CH_1, rank 1
1733 09:27:42.709396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1734 09:27:42.709478 ==
1735 09:27:42.712699 Write leveling (Byte 0): 26 => 26
1736 09:27:42.716008 Write leveling (Byte 1): 25 => 25
1737 09:27:42.719405 DramcWriteLeveling(PI) end<-----
1738 09:27:42.719487
1739 09:27:42.719551 ==
1740 09:27:42.723052 Dram Type= 6, Freq= 0, CH_1, rank 1
1741 09:27:42.726130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 09:27:42.726217 ==
1743 09:27:42.729402 [Gating] SW mode calibration
1744 09:27:42.736296 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1745 09:27:42.739587 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1746 09:27:42.746332 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1747 09:27:42.749978 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1748 09:27:42.752898 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1749 09:27:42.759320 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1750 09:27:42.762764 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1751 09:27:42.766011 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1752 09:27:42.772729 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1753 09:27:42.776171 0 6 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1754 09:27:42.779546 0 7 0 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1755 09:27:42.785997 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1756 09:27:42.789433 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1757 09:27:42.793149 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1758 09:27:42.799468 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1759 09:27:42.802797 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1760 09:27:42.806298 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1761 09:27:42.812984 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1762 09:27:42.816406 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1763 09:27:42.819432 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1764 09:27:42.825926 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1765 09:27:42.829454 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1766 09:27:42.832809 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1767 09:27:42.836366 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1768 09:27:42.843034 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1769 09:27:42.846116 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1770 09:27:42.849815 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1771 09:27:42.856719 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1772 09:27:42.860034 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1773 09:27:42.863138 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1774 09:27:42.869657 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 09:27:42.872655 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 09:27:42.876110 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 09:27:42.882819 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1778 09:27:42.882907 Total UI for P1: 0, mck2ui 16
1779 09:27:42.889597 best dqsien dly found for B0: ( 0, 9, 26)
1780 09:27:42.892667 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1781 09:27:42.896003 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 09:27:42.899599 Total UI for P1: 0, mck2ui 16
1783 09:27:42.902777 best dqsien dly found for B1: ( 0, 9, 30)
1784 09:27:42.906137 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1785 09:27:42.909269 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1786 09:27:42.909350
1787 09:27:42.916069 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1788 09:27:42.919327 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1789 09:27:42.919409 [Gating] SW calibration Done
1790 09:27:42.922864 ==
1791 09:27:42.925932 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 09:27:42.929197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 09:27:42.929279 ==
1794 09:27:42.929344 RX Vref Scan: 0
1795 09:27:42.929405
1796 09:27:42.932485 RX Vref 0 -> 0, step: 1
1797 09:27:42.932566
1798 09:27:42.935842 RX Delay -130 -> 252, step: 16
1799 09:27:42.939353 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1800 09:27:42.942553 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1801 09:27:42.949272 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1802 09:27:42.952588 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1803 09:27:42.956098 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1804 09:27:42.959101 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1805 09:27:42.962554 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1806 09:27:42.965867 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1807 09:27:42.972528 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1808 09:27:42.975768 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1809 09:27:42.979065 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1810 09:27:42.982519 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1811 09:27:42.989375 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1812 09:27:42.992510 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1813 09:27:42.995774 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1814 09:27:42.999111 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1815 09:27:42.999193 ==
1816 09:27:43.002302 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 09:27:43.006011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1818 09:27:43.009317 ==
1819 09:27:43.009398 DQS Delay:
1820 09:27:43.009463 DQS0 = 0, DQS1 = 0
1821 09:27:43.013015 DQM Delay:
1822 09:27:43.013096 DQM0 = 80, DQM1 = 70
1823 09:27:43.015956 DQ Delay:
1824 09:27:43.016037 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1825 09:27:43.019085 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1826 09:27:43.022399 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1827 09:27:43.025874 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1828 09:27:43.025955
1829 09:27:43.029226
1830 09:27:43.029307 ==
1831 09:27:43.032494 Dram Type= 6, Freq= 0, CH_1, rank 1
1832 09:27:43.035692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1833 09:27:43.035773 ==
1834 09:27:43.035837
1835 09:27:43.035897
1836 09:27:43.039101 TX Vref Scan disable
1837 09:27:43.039183 == TX Byte 0 ==
1838 09:27:43.046014 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1839 09:27:43.049297 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1840 09:27:43.049378 == TX Byte 1 ==
1841 09:27:43.055842 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1842 09:27:43.058989 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1843 09:27:43.059071 ==
1844 09:27:43.062359 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 09:27:43.065571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1846 09:27:43.065653 ==
1847 09:27:43.079318 TX Vref=22, minBit 10, minWin=27, winSum=451
1848 09:27:43.082700 TX Vref=24, minBit 0, minWin=28, winSum=454
1849 09:27:43.085704 TX Vref=26, minBit 0, minWin=28, winSum=457
1850 09:27:43.089312 TX Vref=28, minBit 0, minWin=28, winSum=461
1851 09:27:43.092434 TX Vref=30, minBit 0, minWin=28, winSum=456
1852 09:27:43.099076 TX Vref=32, minBit 0, minWin=28, winSum=457
1853 09:27:43.102525 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 28
1854 09:27:43.102607
1855 09:27:43.105747 Final TX Range 1 Vref 28
1856 09:27:43.105829
1857 09:27:43.105893 ==
1858 09:27:43.109198 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 09:27:43.112444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1860 09:27:43.112526 ==
1861 09:27:43.112589
1862 09:27:43.115957
1863 09:27:43.116039 TX Vref Scan disable
1864 09:27:43.119336 == TX Byte 0 ==
1865 09:27:43.122476 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1866 09:27:43.125762 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1867 09:27:43.129182 == TX Byte 1 ==
1868 09:27:43.132402 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1869 09:27:43.135899 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1870 09:27:43.139043
1871 09:27:43.139123 [DATLAT]
1872 09:27:43.139188 Freq=800, CH1 RK1
1873 09:27:43.139249
1874 09:27:43.142435 DATLAT Default: 0x9
1875 09:27:43.142516 0, 0xFFFF, sum = 0
1876 09:27:43.145688 1, 0xFFFF, sum = 0
1877 09:27:43.145771 2, 0xFFFF, sum = 0
1878 09:27:43.148998 3, 0xFFFF, sum = 0
1879 09:27:43.149081 4, 0xFFFF, sum = 0
1880 09:27:43.152208 5, 0xFFFF, sum = 0
1881 09:27:43.155648 6, 0xFFFF, sum = 0
1882 09:27:43.155731 7, 0xFFFF, sum = 0
1883 09:27:43.155796 8, 0x0, sum = 1
1884 09:27:43.159245 9, 0x0, sum = 2
1885 09:27:43.159328 10, 0x0, sum = 3
1886 09:27:43.162590 11, 0x0, sum = 4
1887 09:27:43.162672 best_step = 9
1888 09:27:43.162736
1889 09:27:43.162796 ==
1890 09:27:43.165709 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 09:27:43.172437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1892 09:27:43.172519 ==
1893 09:27:43.172583 RX Vref Scan: 0
1894 09:27:43.172644
1895 09:27:43.175805 RX Vref 0 -> 0, step: 1
1896 09:27:43.175886
1897 09:27:43.178952 RX Delay -111 -> 252, step: 8
1898 09:27:43.182392 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1899 09:27:43.185997 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1900 09:27:43.192318 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1901 09:27:43.195531 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1902 09:27:43.199083 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1903 09:27:43.202300 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1904 09:27:43.205623 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1905 09:27:43.209320 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1906 09:27:43.215967 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1907 09:27:43.219167 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1908 09:27:43.222333 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1909 09:27:43.225679 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1910 09:27:43.232298 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1911 09:27:43.235777 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1912 09:27:43.239129 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1913 09:27:43.242452 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1914 09:27:43.242561 ==
1915 09:27:43.245659 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 09:27:43.249116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1917 09:27:43.252368 ==
1918 09:27:43.252449 DQS Delay:
1919 09:27:43.252513 DQS0 = 0, DQS1 = 0
1920 09:27:43.255620 DQM Delay:
1921 09:27:43.255700 DQM0 = 83, DQM1 = 72
1922 09:27:43.259015 DQ Delay:
1923 09:27:43.259097 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1924 09:27:43.262453 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1925 09:27:43.265692 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1926 09:27:43.268995 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1927 09:27:43.269076
1928 09:27:43.272428
1929 09:27:43.279066 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1930 09:27:43.282553 CH1 RK1: MR19=606, MR18=3E3E
1931 09:27:43.289191 CH1_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1932 09:27:43.289299 [RxdqsGatingPostProcess] freq 800
1933 09:27:43.296183 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1934 09:27:43.299450 Pre-setting of DQS Precalculation
1935 09:27:43.302609 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1936 09:27:43.312676 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1937 09:27:43.319146 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1938 09:27:43.319228
1939 09:27:43.319293
1940 09:27:43.322757 [Calibration Summary] 1600 Mbps
1941 09:27:43.322838 CH 0, Rank 0
1942 09:27:43.325968 SW Impedance : PASS
1943 09:27:43.326049 DUTY Scan : NO K
1944 09:27:43.329491 ZQ Calibration : PASS
1945 09:27:43.332658 Jitter Meter : NO K
1946 09:27:43.332739 CBT Training : PASS
1947 09:27:43.336156 Write leveling : PASS
1948 09:27:43.339095 RX DQS gating : PASS
1949 09:27:43.339176 RX DQ/DQS(RDDQC) : PASS
1950 09:27:43.342729 TX DQ/DQS : PASS
1951 09:27:43.345670 RX DATLAT : PASS
1952 09:27:43.345752 RX DQ/DQS(Engine): PASS
1953 09:27:43.349308 TX OE : NO K
1954 09:27:43.349389 All Pass.
1955 09:27:43.349454
1956 09:27:43.349513 CH 0, Rank 1
1957 09:27:43.352887 SW Impedance : PASS
1958 09:27:43.355858 DUTY Scan : NO K
1959 09:27:43.355940 ZQ Calibration : PASS
1960 09:27:43.359216 Jitter Meter : NO K
1961 09:27:43.362467 CBT Training : PASS
1962 09:27:43.362548 Write leveling : PASS
1963 09:27:43.365749 RX DQS gating : PASS
1964 09:27:43.369014 RX DQ/DQS(RDDQC) : PASS
1965 09:27:43.369096 TX DQ/DQS : PASS
1966 09:27:43.372878 RX DATLAT : PASS
1967 09:27:43.375730 RX DQ/DQS(Engine): PASS
1968 09:27:43.375810 TX OE : NO K
1969 09:27:43.379232 All Pass.
1970 09:27:43.379313
1971 09:27:43.379377 CH 1, Rank 0
1972 09:27:43.382815 SW Impedance : PASS
1973 09:27:43.382896 DUTY Scan : NO K
1974 09:27:43.385710 ZQ Calibration : PASS
1975 09:27:43.389119 Jitter Meter : NO K
1976 09:27:43.389200 CBT Training : PASS
1977 09:27:43.392526 Write leveling : PASS
1978 09:27:43.392607 RX DQS gating : PASS
1979 09:27:43.395888 RX DQ/DQS(RDDQC) : PASS
1980 09:27:43.399407 TX DQ/DQS : PASS
1981 09:27:43.399488 RX DATLAT : PASS
1982 09:27:43.402419 RX DQ/DQS(Engine): PASS
1983 09:27:43.405888 TX OE : NO K
1984 09:27:43.405970 All Pass.
1985 09:27:43.406035
1986 09:27:43.406095 CH 1, Rank 1
1987 09:27:43.409231 SW Impedance : PASS
1988 09:27:43.412580 DUTY Scan : NO K
1989 09:27:43.412661 ZQ Calibration : PASS
1990 09:27:43.416315 Jitter Meter : NO K
1991 09:27:43.419403 CBT Training : PASS
1992 09:27:43.419485 Write leveling : PASS
1993 09:27:43.422517 RX DQS gating : PASS
1994 09:27:43.426010 RX DQ/DQS(RDDQC) : PASS
1995 09:27:43.426092 TX DQ/DQS : PASS
1996 09:27:43.429842 RX DATLAT : PASS
1997 09:27:43.429924 RX DQ/DQS(Engine): PASS
1998 09:27:43.432385 TX OE : NO K
1999 09:27:43.432466 All Pass.
2000 09:27:43.432531
2001 09:27:43.435927 DramC Write-DBI off
2002 09:27:43.439147 PER_BANK_REFRESH: Hybrid Mode
2003 09:27:43.439229 TX_TRACKING: ON
2004 09:27:43.442438 [GetDramInforAfterCalByMRR] Vendor 6.
2005 09:27:43.445817 [GetDramInforAfterCalByMRR] Revision 606.
2006 09:27:43.452560 [GetDramInforAfterCalByMRR] Revision 2 0.
2007 09:27:43.452645 MR0 0x3939
2008 09:27:43.452710 MR8 0x1111
2009 09:27:43.456102 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2010 09:27:43.456190
2011 09:27:43.459296 MR0 0x3939
2012 09:27:43.459377 MR8 0x1111
2013 09:27:43.462864 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2014 09:27:43.462945
2015 09:27:43.472905 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2016 09:27:43.475784 [FAST_K] Save calibration result to emmc
2017 09:27:43.479259 [FAST_K] Save calibration result to emmc
2018 09:27:43.482550 dram_init: config_dvfs: 1
2019 09:27:43.485791 dramc_set_vcore_voltage set vcore to 662500
2020 09:27:43.485873 Read voltage for 1200, 2
2021 09:27:43.489274 Vio18 = 0
2022 09:27:43.489355 Vcore = 662500
2023 09:27:43.489420 Vdram = 0
2024 09:27:43.492586 Vddq = 0
2025 09:27:43.492667 Vmddr = 0
2026 09:27:43.495959 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2027 09:27:43.502666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2028 09:27:43.505775 MEM_TYPE=3, freq_sel=15
2029 09:27:43.509458 sv_algorithm_assistance_LP4_1600
2030 09:27:43.512487 ============ PULL DRAM RESETB DOWN ============
2031 09:27:43.515652 ========== PULL DRAM RESETB DOWN end =========
2032 09:27:43.522601 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2033 09:27:43.525871 ===================================
2034 09:27:43.525952 LPDDR4 DRAM CONFIGURATION
2035 09:27:43.529124 ===================================
2036 09:27:43.532586 EX_ROW_EN[0] = 0x0
2037 09:27:43.532667 EX_ROW_EN[1] = 0x0
2038 09:27:43.535935 LP4Y_EN = 0x0
2039 09:27:43.536016 WORK_FSP = 0x0
2040 09:27:43.539041 WL = 0x4
2041 09:27:43.539122 RL = 0x4
2042 09:27:43.542718 BL = 0x2
2043 09:27:43.545620 RPST = 0x0
2044 09:27:43.545701 RD_PRE = 0x0
2045 09:27:43.549014 WR_PRE = 0x1
2046 09:27:43.549096 WR_PST = 0x0
2047 09:27:43.552458 DBI_WR = 0x0
2048 09:27:43.552538 DBI_RD = 0x0
2049 09:27:43.555855 OTF = 0x1
2050 09:27:43.559326 ===================================
2051 09:27:43.562489 ===================================
2052 09:27:43.562571 ANA top config
2053 09:27:43.566003 ===================================
2054 09:27:43.569009 DLL_ASYNC_EN = 0
2055 09:27:43.572580 ALL_SLAVE_EN = 0
2056 09:27:43.572662 NEW_RANK_MODE = 1
2057 09:27:43.575876 DLL_IDLE_MODE = 1
2058 09:27:43.579061 LP45_APHY_COMB_EN = 1
2059 09:27:43.582411 TX_ODT_DIS = 1
2060 09:27:43.582493 NEW_8X_MODE = 1
2061 09:27:43.585586 ===================================
2062 09:27:43.589427 ===================================
2063 09:27:43.592585 data_rate = 2400
2064 09:27:43.595742 CKR = 1
2065 09:27:43.599097 DQ_P2S_RATIO = 8
2066 09:27:43.602387 ===================================
2067 09:27:43.605597 CA_P2S_RATIO = 8
2068 09:27:43.609045 DQ_CA_OPEN = 0
2069 09:27:43.609124 DQ_SEMI_OPEN = 0
2070 09:27:43.612126 CA_SEMI_OPEN = 0
2071 09:27:43.615635 CA_FULL_RATE = 0
2072 09:27:43.618905 DQ_CKDIV4_EN = 0
2073 09:27:43.622399 CA_CKDIV4_EN = 0
2074 09:27:43.625599 CA_PREDIV_EN = 0
2075 09:27:43.625702 PH8_DLY = 17
2076 09:27:43.628867 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2077 09:27:43.632100 DQ_AAMCK_DIV = 4
2078 09:27:43.635526 CA_AAMCK_DIV = 4
2079 09:27:43.638855 CA_ADMCK_DIV = 4
2080 09:27:43.642364 DQ_TRACK_CA_EN = 0
2081 09:27:43.642469 CA_PICK = 1200
2082 09:27:43.645598 CA_MCKIO = 1200
2083 09:27:43.649084 MCKIO_SEMI = 0
2084 09:27:43.652342 PLL_FREQ = 2366
2085 09:27:43.655599 DQ_UI_PI_RATIO = 32
2086 09:27:43.659059 CA_UI_PI_RATIO = 0
2087 09:27:43.662268 ===================================
2088 09:27:43.665883 ===================================
2089 09:27:43.669067 memory_type:LPDDR4
2090 09:27:43.669159 GP_NUM : 10
2091 09:27:43.672475 SRAM_EN : 1
2092 09:27:43.672562 MD32_EN : 0
2093 09:27:43.675823 ===================================
2094 09:27:43.679076 [ANA_INIT] >>>>>>>>>>>>>>
2095 09:27:43.682304 <<<<<< [CONFIGURE PHASE]: ANA_TX
2096 09:27:43.685779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2097 09:27:43.689076 ===================================
2098 09:27:43.692343 data_rate = 2400,PCW = 0X5b00
2099 09:27:43.695545 ===================================
2100 09:27:43.699025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2101 09:27:43.702085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2102 09:27:43.708750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2103 09:27:43.712008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2104 09:27:43.719158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2105 09:27:43.722097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2106 09:27:43.722180 [ANA_INIT] flow start
2107 09:27:43.725398 [ANA_INIT] PLL >>>>>>>>
2108 09:27:43.728709 [ANA_INIT] PLL <<<<<<<<
2109 09:27:43.728790 [ANA_INIT] MIDPI >>>>>>>>
2110 09:27:43.732047 [ANA_INIT] MIDPI <<<<<<<<
2111 09:27:43.735219 [ANA_INIT] DLL >>>>>>>>
2112 09:27:43.735300 [ANA_INIT] DLL <<<<<<<<
2113 09:27:43.738548 [ANA_INIT] flow end
2114 09:27:43.741695 ============ LP4 DIFF to SE enter ============
2115 09:27:43.745066 ============ LP4 DIFF to SE exit ============
2116 09:27:43.748302 [ANA_INIT] <<<<<<<<<<<<<
2117 09:27:43.752058 [Flow] Enable top DCM control >>>>>
2118 09:27:43.755015 [Flow] Enable top DCM control <<<<<
2119 09:27:43.758659 Enable DLL master slave shuffle
2120 09:27:43.764905 ==============================================================
2121 09:27:43.764987 Gating Mode config
2122 09:27:43.771818 ==============================================================
2123 09:27:43.771899 Config description:
2124 09:27:43.781801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2125 09:27:43.788241 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2126 09:27:43.794746 SELPH_MODE 0: By rank 1: By Phase
2127 09:27:43.798137 ==============================================================
2128 09:27:43.801635 GAT_TRACK_EN = 1
2129 09:27:43.804879 RX_GATING_MODE = 2
2130 09:27:43.808386 RX_GATING_TRACK_MODE = 2
2131 09:27:43.811491 SELPH_MODE = 1
2132 09:27:43.814875 PICG_EARLY_EN = 1
2133 09:27:43.818093 VALID_LAT_VALUE = 1
2134 09:27:43.824841 ==============================================================
2135 09:27:43.828146 Enter into Gating configuration >>>>
2136 09:27:43.831570 Exit from Gating configuration <<<<
2137 09:27:43.831652 Enter into DVFS_PRE_config >>>>>
2138 09:27:43.844709 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2139 09:27:43.848221 Exit from DVFS_PRE_config <<<<<
2140 09:27:43.851792 Enter into PICG configuration >>>>
2141 09:27:43.854771 Exit from PICG configuration <<<<
2142 09:27:43.854863 [RX_INPUT] configuration >>>>>
2143 09:27:43.858157 [RX_INPUT] configuration <<<<<
2144 09:27:43.864727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2145 09:27:43.868213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2146 09:27:43.874898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2147 09:27:43.881390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2148 09:27:43.888244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2149 09:27:43.895199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2150 09:27:43.898089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2151 09:27:43.901362 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2152 09:27:43.908067 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2153 09:27:43.911430 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2154 09:27:43.914515 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2155 09:27:43.917978 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 09:27:43.921419 ===================================
2157 09:27:43.924789 LPDDR4 DRAM CONFIGURATION
2158 09:27:43.928295 ===================================
2159 09:27:43.931597 EX_ROW_EN[0] = 0x0
2160 09:27:43.931676 EX_ROW_EN[1] = 0x0
2161 09:27:43.934728 LP4Y_EN = 0x0
2162 09:27:43.934809 WORK_FSP = 0x0
2163 09:27:43.938214 WL = 0x4
2164 09:27:43.938294 RL = 0x4
2165 09:27:43.941689 BL = 0x2
2166 09:27:43.941769 RPST = 0x0
2167 09:27:43.944830 RD_PRE = 0x0
2168 09:27:43.944910 WR_PRE = 0x1
2169 09:27:43.948143 WR_PST = 0x0
2170 09:27:43.948278 DBI_WR = 0x0
2171 09:27:43.951252 DBI_RD = 0x0
2172 09:27:43.951332 OTF = 0x1
2173 09:27:43.954663 ===================================
2174 09:27:43.961381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2175 09:27:43.964734 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2176 09:27:43.968007 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2177 09:27:43.971329 ===================================
2178 09:27:43.974755 LPDDR4 DRAM CONFIGURATION
2179 09:27:43.978241 ===================================
2180 09:27:43.978321 EX_ROW_EN[0] = 0x10
2181 09:27:43.981674 EX_ROW_EN[1] = 0x0
2182 09:27:43.984933 LP4Y_EN = 0x0
2183 09:27:43.985063 WORK_FSP = 0x0
2184 09:27:43.988036 WL = 0x4
2185 09:27:43.988115 RL = 0x4
2186 09:27:43.991780 BL = 0x2
2187 09:27:43.991860 RPST = 0x0
2188 09:27:43.994811 RD_PRE = 0x0
2189 09:27:43.994890 WR_PRE = 0x1
2190 09:27:43.998106 WR_PST = 0x0
2191 09:27:43.998185 DBI_WR = 0x0
2192 09:27:44.001747 DBI_RD = 0x0
2193 09:27:44.001826 OTF = 0x1
2194 09:27:44.005243 ===================================
2195 09:27:44.011419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2196 09:27:44.011502 ==
2197 09:27:44.015087 Dram Type= 6, Freq= 0, CH_0, rank 0
2198 09:27:44.018147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2199 09:27:44.018228 ==
2200 09:27:44.021789 [Duty_Offset_Calibration]
2201 09:27:44.025004 B0:0 B1:2 CA:1
2202 09:27:44.025086
2203 09:27:44.028183 [DutyScan_Calibration_Flow] k_type=0
2204 09:27:44.036320
2205 09:27:44.036404 ==CLK 0==
2206 09:27:44.039848 Final CLK duty delay cell = 0
2207 09:27:44.043109 [0] MAX Duty = 5093%(X100), DQS PI = 12
2208 09:27:44.046388 [0] MIN Duty = 4938%(X100), DQS PI = 52
2209 09:27:44.046470 [0] AVG Duty = 5015%(X100)
2210 09:27:44.049625
2211 09:27:44.053248 CH0 CLK Duty spec in!! Max-Min= 155%
2212 09:27:44.056719 [DutyScan_Calibration_Flow] ====Done====
2213 09:27:44.056800
2214 09:27:44.059727 [DutyScan_Calibration_Flow] k_type=1
2215 09:27:44.075906
2216 09:27:44.075987 ==DQS 0 ==
2217 09:27:44.078942 Final DQS duty delay cell = 0
2218 09:27:44.082358 [0] MAX Duty = 5125%(X100), DQS PI = 28
2219 09:27:44.085824 [0] MIN Duty = 5031%(X100), DQS PI = 6
2220 09:27:44.085906 [0] AVG Duty = 5078%(X100)
2221 09:27:44.089031
2222 09:27:44.089112 ==DQS 1 ==
2223 09:27:44.092719 Final DQS duty delay cell = 0
2224 09:27:44.095581 [0] MAX Duty = 5031%(X100), DQS PI = 10
2225 09:27:44.099162 [0] MIN Duty = 4906%(X100), DQS PI = 16
2226 09:27:44.102291 [0] AVG Duty = 4968%(X100)
2227 09:27:44.102372
2228 09:27:44.105629 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2229 09:27:44.105711
2230 09:27:44.109191 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2231 09:27:44.112140 [DutyScan_Calibration_Flow] ====Done====
2232 09:27:44.112237
2233 09:27:44.115668 [DutyScan_Calibration_Flow] k_type=3
2234 09:27:44.132036
2235 09:27:44.132142 ==DQM 0 ==
2236 09:27:44.135752 Final DQM duty delay cell = 0
2237 09:27:44.138671 [0] MAX Duty = 5156%(X100), DQS PI = 22
2238 09:27:44.142194 [0] MIN Duty = 4969%(X100), DQS PI = 54
2239 09:27:44.142276 [0] AVG Duty = 5062%(X100)
2240 09:27:44.145394
2241 09:27:44.145475 ==DQM 1 ==
2242 09:27:44.148894 Final DQM duty delay cell = 0
2243 09:27:44.152071 [0] MAX Duty = 5000%(X100), DQS PI = 56
2244 09:27:44.155477 [0] MIN Duty = 4844%(X100), DQS PI = 0
2245 09:27:44.155558 [0] AVG Duty = 4922%(X100)
2246 09:27:44.158651
2247 09:27:44.162090 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2248 09:27:44.162171
2249 09:27:44.165358 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2250 09:27:44.168729 [DutyScan_Calibration_Flow] ====Done====
2251 09:27:44.168810
2252 09:27:44.172056 [DutyScan_Calibration_Flow] k_type=2
2253 09:27:44.187033
2254 09:27:44.187114 ==DQ 0 ==
2255 09:27:44.190528 Final DQ duty delay cell = -4
2256 09:27:44.193715 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2257 09:27:44.197006 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2258 09:27:44.200563 [-4] AVG Duty = 4937%(X100)
2259 09:27:44.200645
2260 09:27:44.200709 ==DQ 1 ==
2261 09:27:44.203878 Final DQ duty delay cell = -4
2262 09:27:44.207041 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2263 09:27:44.210498 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2264 09:27:44.213657 [-4] AVG Duty = 4969%(X100)
2265 09:27:44.213738
2266 09:27:44.216929 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2267 09:27:44.217010
2268 09:27:44.220494 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2269 09:27:44.223750 [DutyScan_Calibration_Flow] ====Done====
2270 09:27:44.223831 ==
2271 09:27:44.227130 Dram Type= 6, Freq= 0, CH_1, rank 0
2272 09:27:44.230702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2273 09:27:44.230784 ==
2274 09:27:44.233981 [Duty_Offset_Calibration]
2275 09:27:44.234062 B0:0 B1:5 CA:-5
2276 09:27:44.234127
2277 09:27:44.237478 [DutyScan_Calibration_Flow] k_type=0
2278 09:27:44.247768
2279 09:27:44.247850 ==CLK 0==
2280 09:27:44.250849 Final CLK duty delay cell = 0
2281 09:27:44.254036 [0] MAX Duty = 5125%(X100), DQS PI = 10
2282 09:27:44.257650 [0] MIN Duty = 4875%(X100), DQS PI = 46
2283 09:27:44.257732 [0] AVG Duty = 5000%(X100)
2284 09:27:44.261285
2285 09:27:44.261366 CH1 CLK Duty spec in!! Max-Min= 250%
2286 09:27:44.267926 [DutyScan_Calibration_Flow] ====Done====
2287 09:27:44.268007
2288 09:27:44.271088 [DutyScan_Calibration_Flow] k_type=1
2289 09:27:44.286034
2290 09:27:44.286115 ==DQS 0 ==
2291 09:27:44.289248 Final DQS duty delay cell = 0
2292 09:27:44.292775 [0] MAX Duty = 5125%(X100), DQS PI = 16
2293 09:27:44.296061 [0] MIN Duty = 4875%(X100), DQS PI = 40
2294 09:27:44.296143 [0] AVG Duty = 5000%(X100)
2295 09:27:44.299767
2296 09:27:44.299848 ==DQS 1 ==
2297 09:27:44.302849 Final DQS duty delay cell = -4
2298 09:27:44.306046 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2299 09:27:44.309353 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2300 09:27:44.312819 [-4] AVG Duty = 4953%(X100)
2301 09:27:44.312901
2302 09:27:44.316248 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2303 09:27:44.316330
2304 09:27:44.319288 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2305 09:27:44.322769 [DutyScan_Calibration_Flow] ====Done====
2306 09:27:44.322851
2307 09:27:44.325897 [DutyScan_Calibration_Flow] k_type=3
2308 09:27:44.341627
2309 09:27:44.341708 ==DQM 0 ==
2310 09:27:44.344486 Final DQM duty delay cell = -4
2311 09:27:44.348158 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2312 09:27:44.351644 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2313 09:27:44.355039 [-4] AVG Duty = 4969%(X100)
2314 09:27:44.355121
2315 09:27:44.355185 ==DQM 1 ==
2316 09:27:44.357996 Final DQM duty delay cell = -4
2317 09:27:44.361201 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2318 09:27:44.364583 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2319 09:27:44.367881 [-4] AVG Duty = 5000%(X100)
2320 09:27:44.367962
2321 09:27:44.371269 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2322 09:27:44.371351
2323 09:27:44.374552 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2324 09:27:44.377973 [DutyScan_Calibration_Flow] ====Done====
2325 09:27:44.378054
2326 09:27:44.381198 [DutyScan_Calibration_Flow] k_type=2
2327 09:27:44.398897
2328 09:27:44.398978 ==DQ 0 ==
2329 09:27:44.401644 Final DQ duty delay cell = 0
2330 09:27:44.405097 [0] MAX Duty = 5062%(X100), DQS PI = 0
2331 09:27:44.408648 [0] MIN Duty = 4969%(X100), DQS PI = 42
2332 09:27:44.408730 [0] AVG Duty = 5015%(X100)
2333 09:27:44.408795
2334 09:27:44.411942 ==DQ 1 ==
2335 09:27:44.414982 Final DQ duty delay cell = 0
2336 09:27:44.418783 [0] MAX Duty = 5031%(X100), DQS PI = 8
2337 09:27:44.421762 [0] MIN Duty = 4907%(X100), DQS PI = 0
2338 09:27:44.421844 [0] AVG Duty = 4969%(X100)
2339 09:27:44.421909
2340 09:27:44.425195 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2341 09:27:44.425276
2342 09:27:44.428761 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2343 09:27:44.431662 [DutyScan_Calibration_Flow] ====Done====
2344 09:27:44.437353 nWR fixed to 30
2345 09:27:44.440740 [ModeRegInit_LP4] CH0 RK0
2346 09:27:44.440820 [ModeRegInit_LP4] CH0 RK1
2347 09:27:44.444071 [ModeRegInit_LP4] CH1 RK0
2348 09:27:44.447169 [ModeRegInit_LP4] CH1 RK1
2349 09:27:44.447251 match AC timing 6
2350 09:27:44.454075 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2351 09:27:44.457197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2352 09:27:44.460889 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2353 09:27:44.467146 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2354 09:27:44.470521 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2355 09:27:44.470602 ==
2356 09:27:44.473858 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 09:27:44.477390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2358 09:27:44.477471 ==
2359 09:27:44.484268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2360 09:27:44.490741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2361 09:27:44.498026 [CA 0] Center 39 (9~70) winsize 62
2362 09:27:44.501270 [CA 1] Center 39 (9~70) winsize 62
2363 09:27:44.504732 [CA 2] Center 36 (5~67) winsize 63
2364 09:27:44.507765 [CA 3] Center 35 (4~66) winsize 63
2365 09:27:44.511153 [CA 4] Center 34 (3~65) winsize 63
2366 09:27:44.514492 [CA 5] Center 33 (3~64) winsize 62
2367 09:27:44.514572
2368 09:27:44.517928 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2369 09:27:44.518009
2370 09:27:44.521421 [CATrainingPosCal] consider 1 rank data
2371 09:27:44.524452 u2DelayCellTimex100 = 270/100 ps
2372 09:27:44.527967 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2373 09:27:44.531223 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2374 09:27:44.538114 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2375 09:27:44.541305 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2376 09:27:44.544586 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2377 09:27:44.548397 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2378 09:27:44.548478
2379 09:27:44.551303 CA PerBit enable=1, Macro0, CA PI delay=33
2380 09:27:44.551413
2381 09:27:44.554492 [CBTSetCACLKResult] CA Dly = 33
2382 09:27:44.554573 CS Dly: 7 (0~38)
2383 09:27:44.554637 ==
2384 09:27:44.558015 Dram Type= 6, Freq= 0, CH_0, rank 1
2385 09:27:44.564542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2386 09:27:44.564623 ==
2387 09:27:44.567827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2388 09:27:44.574526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2389 09:27:44.583489 [CA 0] Center 39 (8~70) winsize 63
2390 09:27:44.586695 [CA 1] Center 39 (8~70) winsize 63
2391 09:27:44.589943 [CA 2] Center 35 (5~66) winsize 62
2392 09:27:44.593601 [CA 3] Center 35 (4~66) winsize 63
2393 09:27:44.596986 [CA 4] Center 33 (3~64) winsize 62
2394 09:27:44.599956 [CA 5] Center 33 (3~64) winsize 62
2395 09:27:44.600036
2396 09:27:44.603329 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2397 09:27:44.603410
2398 09:27:44.606704 [CATrainingPosCal] consider 2 rank data
2399 09:27:44.609810 u2DelayCellTimex100 = 270/100 ps
2400 09:27:44.613270 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2401 09:27:44.616658 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2402 09:27:44.623677 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2403 09:27:44.626951 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2404 09:27:44.630095 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2405 09:27:44.633174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2406 09:27:44.633256
2407 09:27:44.636493 CA PerBit enable=1, Macro0, CA PI delay=33
2408 09:27:44.636575
2409 09:27:44.639909 [CBTSetCACLKResult] CA Dly = 33
2410 09:27:44.639991 CS Dly: 7 (0~39)
2411 09:27:44.640055
2412 09:27:44.643278 ----->DramcWriteLeveling(PI) begin...
2413 09:27:44.646628 ==
2414 09:27:44.650006 Dram Type= 6, Freq= 0, CH_0, rank 0
2415 09:27:44.653203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2416 09:27:44.653285 ==
2417 09:27:44.656543 Write leveling (Byte 0): 26 => 26
2418 09:27:44.659962 Write leveling (Byte 1): 26 => 26
2419 09:27:44.663068 DramcWriteLeveling(PI) end<-----
2420 09:27:44.663150
2421 09:27:44.663214 ==
2422 09:27:44.666444 Dram Type= 6, Freq= 0, CH_0, rank 0
2423 09:27:44.670095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2424 09:27:44.670178 ==
2425 09:27:44.673344 [Gating] SW mode calibration
2426 09:27:44.679991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2427 09:27:44.683263 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2428 09:27:44.689950 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2429 09:27:44.693651 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2430 09:27:44.696544 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2431 09:27:44.703266 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2432 09:27:44.706495 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2433 09:27:44.709916 0 11 20 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 1)
2434 09:27:44.716578 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2435 09:27:44.720104 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2436 09:27:44.723651 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2437 09:27:44.730043 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2438 09:27:44.733249 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2439 09:27:44.736242 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2440 09:27:44.743334 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2441 09:27:44.746543 0 12 20 | B1->B0 | 3636 3b3b | 0 0 | (0 0) (1 1)
2442 09:27:44.749850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2443 09:27:44.756577 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2444 09:27:44.760202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2445 09:27:44.763172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2446 09:27:44.769937 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2447 09:27:44.773360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2448 09:27:44.776587 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2449 09:27:44.779967 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2450 09:27:44.786565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2451 09:27:44.789805 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2452 09:27:44.793354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2453 09:27:44.800376 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2454 09:27:44.803384 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2455 09:27:44.806974 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2456 09:27:44.813508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2457 09:27:44.816606 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2458 09:27:44.819902 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2459 09:27:44.826678 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 09:27:44.830210 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 09:27:44.833599 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 09:27:44.839977 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 09:27:44.843386 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 09:27:44.846453 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2465 09:27:44.853056 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2466 09:27:44.856535 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 09:27:44.860045 Total UI for P1: 0, mck2ui 16
2468 09:27:44.863420 best dqsien dly found for B0: ( 0, 15, 18)
2469 09:27:44.866533 Total UI for P1: 0, mck2ui 16
2470 09:27:44.870091 best dqsien dly found for B1: ( 0, 15, 20)
2471 09:27:44.873226 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2472 09:27:44.876561 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2473 09:27:44.876643
2474 09:27:44.880129 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2475 09:27:44.883108 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2476 09:27:44.886514 [Gating] SW calibration Done
2477 09:27:44.886595 ==
2478 09:27:44.889902 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 09:27:44.893215 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 09:27:44.893297 ==
2481 09:27:44.896713 RX Vref Scan: 0
2482 09:27:44.896794
2483 09:27:44.899808 RX Vref 0 -> 0, step: 1
2484 09:27:44.899890
2485 09:27:44.899954 RX Delay -40 -> 252, step: 8
2486 09:27:44.906605 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2487 09:27:44.910147 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2488 09:27:44.913116 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2489 09:27:44.916653 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2490 09:27:44.919956 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2491 09:27:44.926523 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2492 09:27:44.929731 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2493 09:27:44.933211 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2494 09:27:44.936500 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2495 09:27:44.939730 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2496 09:27:44.946589 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2497 09:27:44.949673 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2498 09:27:44.953245 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2499 09:27:44.956709 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2500 09:27:44.960001 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2501 09:27:44.966681 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2502 09:27:44.966761 ==
2503 09:27:44.969859 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 09:27:44.973301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2505 09:27:44.973382 ==
2506 09:27:44.973445 DQS Delay:
2507 09:27:44.976476 DQS0 = 0, DQS1 = 0
2508 09:27:44.976556 DQM Delay:
2509 09:27:44.979788 DQM0 = 115, DQM1 = 106
2510 09:27:44.979869 DQ Delay:
2511 09:27:44.983254 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2512 09:27:44.986711 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2513 09:27:44.989660 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2514 09:27:44.993423 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2515 09:27:44.993504
2516 09:27:44.993590
2517 09:27:44.996474 ==
2518 09:27:44.996554 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 09:27:45.003656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2520 09:27:45.003737 ==
2521 09:27:45.003801
2522 09:27:45.003860
2523 09:27:45.006523 TX Vref Scan disable
2524 09:27:45.006604 == TX Byte 0 ==
2525 09:27:45.009743 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2526 09:27:45.016289 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2527 09:27:45.016369 == TX Byte 1 ==
2528 09:27:45.019977 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2529 09:27:45.026370 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2530 09:27:45.026452 ==
2531 09:27:45.029515 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 09:27:45.032901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 09:27:45.032983 ==
2534 09:27:45.044737 TX Vref=22, minBit 12, minWin=24, winSum=410
2535 09:27:45.048057 TX Vref=24, minBit 4, minWin=25, winSum=419
2536 09:27:45.051332 TX Vref=26, minBit 12, minWin=25, winSum=423
2537 09:27:45.054563 TX Vref=28, minBit 8, minWin=26, winSum=429
2538 09:27:45.058180 TX Vref=30, minBit 5, minWin=26, winSum=427
2539 09:27:45.064428 TX Vref=32, minBit 9, minWin=26, winSum=430
2540 09:27:45.067869 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 32
2541 09:27:45.067951
2542 09:27:45.071207 Final TX Range 1 Vref 32
2543 09:27:45.071289
2544 09:27:45.071354 ==
2545 09:27:45.074595 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 09:27:45.077889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2547 09:27:45.077971 ==
2548 09:27:45.081061
2549 09:27:45.081142
2550 09:27:45.081207 TX Vref Scan disable
2551 09:27:45.084582 == TX Byte 0 ==
2552 09:27:45.087959 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2553 09:27:45.091201 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2554 09:27:45.094730 == TX Byte 1 ==
2555 09:27:45.097769 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2556 09:27:45.101255 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2557 09:27:45.104824
2558 09:27:45.104906 [DATLAT]
2559 09:27:45.104971 Freq=1200, CH0 RK0
2560 09:27:45.105033
2561 09:27:45.108286 DATLAT Default: 0xd
2562 09:27:45.108367 0, 0xFFFF, sum = 0
2563 09:27:45.111249 1, 0xFFFF, sum = 0
2564 09:27:45.111332 2, 0xFFFF, sum = 0
2565 09:27:45.114511 3, 0xFFFF, sum = 0
2566 09:27:45.114594 4, 0xFFFF, sum = 0
2567 09:27:45.117694 5, 0xFFFF, sum = 0
2568 09:27:45.121030 6, 0xFFFF, sum = 0
2569 09:27:45.121139 7, 0xFFFF, sum = 0
2570 09:27:45.124785 8, 0xFFFF, sum = 0
2571 09:27:45.124868 9, 0xFFFF, sum = 0
2572 09:27:45.127765 10, 0xFFFF, sum = 0
2573 09:27:45.127848 11, 0x0, sum = 1
2574 09:27:45.131513 12, 0x0, sum = 2
2575 09:27:45.131596 13, 0x0, sum = 3
2576 09:27:45.131662 14, 0x0, sum = 4
2577 09:27:45.134454 best_step = 12
2578 09:27:45.134536
2579 09:27:45.134600 ==
2580 09:27:45.137863 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 09:27:45.141179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2582 09:27:45.141262 ==
2583 09:27:45.144567 RX Vref Scan: 1
2584 09:27:45.144649
2585 09:27:45.147791 Set Vref Range= 32 -> 127
2586 09:27:45.147873
2587 09:27:45.147940 RX Vref 32 -> 127, step: 1
2588 09:27:45.148002
2589 09:27:45.151554 RX Delay -21 -> 252, step: 4
2590 09:27:45.151636
2591 09:27:45.154470 Set Vref, RX VrefLevel [Byte0]: 32
2592 09:27:45.157863 [Byte1]: 32
2593 09:27:45.161106
2594 09:27:45.161187 Set Vref, RX VrefLevel [Byte0]: 33
2595 09:27:45.164488 [Byte1]: 33
2596 09:27:45.169218
2597 09:27:45.169299 Set Vref, RX VrefLevel [Byte0]: 34
2598 09:27:45.172657 [Byte1]: 34
2599 09:27:45.177117
2600 09:27:45.177198 Set Vref, RX VrefLevel [Byte0]: 35
2601 09:27:45.180439 [Byte1]: 35
2602 09:27:45.185004
2603 09:27:45.185089 Set Vref, RX VrefLevel [Byte0]: 36
2604 09:27:45.188632 [Byte1]: 36
2605 09:27:45.193655
2606 09:27:45.193736 Set Vref, RX VrefLevel [Byte0]: 37
2607 09:27:45.196419 [Byte1]: 37
2608 09:27:45.200735
2609 09:27:45.200816 Set Vref, RX VrefLevel [Byte0]: 38
2610 09:27:45.204482 [Byte1]: 38
2611 09:27:45.208814
2612 09:27:45.208895 Set Vref, RX VrefLevel [Byte0]: 39
2613 09:27:45.211959 [Byte1]: 39
2614 09:27:45.216785
2615 09:27:45.216867 Set Vref, RX VrefLevel [Byte0]: 40
2616 09:27:45.219980 [Byte1]: 40
2617 09:27:45.224586
2618 09:27:45.224668 Set Vref, RX VrefLevel [Byte0]: 41
2619 09:27:45.227839 [Byte1]: 41
2620 09:27:45.232727
2621 09:27:45.232808 Set Vref, RX VrefLevel [Byte0]: 42
2622 09:27:45.236069 [Byte1]: 42
2623 09:27:45.240452
2624 09:27:45.240534 Set Vref, RX VrefLevel [Byte0]: 43
2625 09:27:45.243583 [Byte1]: 43
2626 09:27:45.248322
2627 09:27:45.248403 Set Vref, RX VrefLevel [Byte0]: 44
2628 09:27:45.251826 [Byte1]: 44
2629 09:27:45.256332
2630 09:27:45.256413 Set Vref, RX VrefLevel [Byte0]: 45
2631 09:27:45.259661 [Byte1]: 45
2632 09:27:45.264382
2633 09:27:45.264463 Set Vref, RX VrefLevel [Byte0]: 46
2634 09:27:45.267342 [Byte1]: 46
2635 09:27:45.272041
2636 09:27:45.272148 Set Vref, RX VrefLevel [Byte0]: 47
2637 09:27:45.275454 [Byte1]: 47
2638 09:27:45.279985
2639 09:27:45.280066 Set Vref, RX VrefLevel [Byte0]: 48
2640 09:27:45.283283 [Byte1]: 48
2641 09:27:45.287773
2642 09:27:45.287854 Set Vref, RX VrefLevel [Byte0]: 49
2643 09:27:45.291243 [Byte1]: 49
2644 09:27:45.296075
2645 09:27:45.296157 Set Vref, RX VrefLevel [Byte0]: 50
2646 09:27:45.299074 [Byte1]: 50
2647 09:27:45.303934
2648 09:27:45.304015 Set Vref, RX VrefLevel [Byte0]: 51
2649 09:27:45.307231 [Byte1]: 51
2650 09:27:45.311780
2651 09:27:45.311861 Set Vref, RX VrefLevel [Byte0]: 52
2652 09:27:45.314993 [Byte1]: 52
2653 09:27:45.319974
2654 09:27:45.320055 Set Vref, RX VrefLevel [Byte0]: 53
2655 09:27:45.323147 [Byte1]: 53
2656 09:27:45.327430
2657 09:27:45.327511 Set Vref, RX VrefLevel [Byte0]: 54
2658 09:27:45.330707 [Byte1]: 54
2659 09:27:45.335311
2660 09:27:45.335392 Set Vref, RX VrefLevel [Byte0]: 55
2661 09:27:45.338717 [Byte1]: 55
2662 09:27:45.343242
2663 09:27:45.343323 Set Vref, RX VrefLevel [Byte0]: 56
2664 09:27:45.346673 [Byte1]: 56
2665 09:27:45.351898
2666 09:27:45.351983 Set Vref, RX VrefLevel [Byte0]: 57
2667 09:27:45.357538 [Byte1]: 57
2668 09:27:45.357620
2669 09:27:45.360820 Set Vref, RX VrefLevel [Byte0]: 58
2670 09:27:45.364136 [Byte1]: 58
2671 09:27:45.364223
2672 09:27:45.367665 Set Vref, RX VrefLevel [Byte0]: 59
2673 09:27:45.370900 [Byte1]: 59
2674 09:27:45.375213
2675 09:27:45.375294 Set Vref, RX VrefLevel [Byte0]: 60
2676 09:27:45.378326 [Byte1]: 60
2677 09:27:45.382998
2678 09:27:45.383079 Set Vref, RX VrefLevel [Byte0]: 61
2679 09:27:45.386245 [Byte1]: 61
2680 09:27:45.391107
2681 09:27:45.391189 Set Vref, RX VrefLevel [Byte0]: 62
2682 09:27:45.394196 [Byte1]: 62
2683 09:27:45.398805
2684 09:27:45.398886 Set Vref, RX VrefLevel [Byte0]: 63
2685 09:27:45.401982 [Byte1]: 63
2686 09:27:45.406878
2687 09:27:45.406959 Set Vref, RX VrefLevel [Byte0]: 64
2688 09:27:45.410001 [Byte1]: 64
2689 09:27:45.414797
2690 09:27:45.414878 Set Vref, RX VrefLevel [Byte0]: 65
2691 09:27:45.418331 [Byte1]: 65
2692 09:27:45.422457
2693 09:27:45.422539 Set Vref, RX VrefLevel [Byte0]: 66
2694 09:27:45.425744 [Byte1]: 66
2695 09:27:45.430399
2696 09:27:45.430480 Final RX Vref Byte 0 = 47 to rank0
2697 09:27:45.433682 Final RX Vref Byte 1 = 47 to rank0
2698 09:27:45.437477 Final RX Vref Byte 0 = 47 to rank1
2699 09:27:45.440564 Final RX Vref Byte 1 = 47 to rank1==
2700 09:27:45.443867 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 09:27:45.450736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2702 09:27:45.450818 ==
2703 09:27:45.450884 DQS Delay:
2704 09:27:45.450945 DQS0 = 0, DQS1 = 0
2705 09:27:45.453809 DQM Delay:
2706 09:27:45.453891 DQM0 = 114, DQM1 = 105
2707 09:27:45.457038 DQ Delay:
2708 09:27:45.460488 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2709 09:27:45.463894 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2710 09:27:45.467133 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2711 09:27:45.470299 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2712 09:27:45.470381
2713 09:27:45.470446
2714 09:27:45.477224 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2715 09:27:45.480397 CH0 RK0: MR19=404, MR18=707
2716 09:27:45.486923 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2717 09:27:45.487006
2718 09:27:45.490103 ----->DramcWriteLeveling(PI) begin...
2719 09:27:45.490186 ==
2720 09:27:45.493645 Dram Type= 6, Freq= 0, CH_0, rank 1
2721 09:27:45.496828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2722 09:27:45.496910 ==
2723 09:27:45.500123 Write leveling (Byte 0): 26 => 26
2724 09:27:45.503604 Write leveling (Byte 1): 24 => 24
2725 09:27:45.506822 DramcWriteLeveling(PI) end<-----
2726 09:27:45.506903
2727 09:27:45.506968 ==
2728 09:27:45.510236 Dram Type= 6, Freq= 0, CH_0, rank 1
2729 09:27:45.516834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2730 09:27:45.516916 ==
2731 09:27:45.516982 [Gating] SW mode calibration
2732 09:27:45.526958 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2733 09:27:45.530117 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2734 09:27:45.533491 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2735 09:27:45.540099 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2736 09:27:45.543460 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2737 09:27:45.546768 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2738 09:27:45.553598 0 11 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
2739 09:27:45.556807 0 11 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2740 09:27:45.560302 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2741 09:27:45.567090 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2742 09:27:45.570163 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2743 09:27:45.573840 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2744 09:27:45.580135 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2745 09:27:45.583812 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2746 09:27:45.586952 0 12 16 | B1->B0 | 2727 3939 | 0 1 | (0 0) (0 0)
2747 09:27:45.593794 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2748 09:27:45.596902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2749 09:27:45.600431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2750 09:27:45.607007 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2751 09:27:45.610275 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2752 09:27:45.613589 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2753 09:27:45.617083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2754 09:27:45.623787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2755 09:27:45.627137 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2756 09:27:45.630413 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2757 09:27:45.637189 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2758 09:27:45.640367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2759 09:27:45.643836 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2760 09:27:45.650213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2761 09:27:45.653712 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2762 09:27:45.656975 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2763 09:27:45.663870 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2764 09:27:45.667354 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2765 09:27:45.670905 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2766 09:27:45.677182 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 09:27:45.680440 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 09:27:45.683735 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 09:27:45.690425 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2770 09:27:45.693933 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2771 09:27:45.697056 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2772 09:27:45.700433 Total UI for P1: 0, mck2ui 16
2773 09:27:45.703844 best dqsien dly found for B0: ( 0, 15, 14)
2774 09:27:45.707157 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 09:27:45.710429 Total UI for P1: 0, mck2ui 16
2776 09:27:45.713781 best dqsien dly found for B1: ( 0, 15, 18)
2777 09:27:45.716992 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2778 09:27:45.720467 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2779 09:27:45.723886
2780 09:27:45.727610 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2781 09:27:45.730564 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2782 09:27:45.733833 [Gating] SW calibration Done
2783 09:27:45.733916 ==
2784 09:27:45.737423 Dram Type= 6, Freq= 0, CH_0, rank 1
2785 09:27:45.740663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2786 09:27:45.740745 ==
2787 09:27:45.740811 RX Vref Scan: 0
2788 09:27:45.740872
2789 09:27:45.743815 RX Vref 0 -> 0, step: 1
2790 09:27:45.743896
2791 09:27:45.747148 RX Delay -40 -> 252, step: 8
2792 09:27:45.751097 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2793 09:27:45.754592 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2794 09:27:45.757612 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2795 09:27:45.764101 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2796 09:27:45.767482 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2797 09:27:45.770844 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2798 09:27:45.774133 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2799 09:27:45.777448 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2800 09:27:45.784044 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2801 09:27:45.787291 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2802 09:27:45.790531 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2803 09:27:45.794022 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2804 09:27:45.797186 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2805 09:27:45.803799 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2806 09:27:45.807412 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2807 09:27:45.810770 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2808 09:27:45.810852 ==
2809 09:27:45.813721 Dram Type= 6, Freq= 0, CH_0, rank 1
2810 09:27:45.817033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2811 09:27:45.820415 ==
2812 09:27:45.820497 DQS Delay:
2813 09:27:45.820562 DQS0 = 0, DQS1 = 0
2814 09:27:45.823633 DQM Delay:
2815 09:27:45.823714 DQM0 = 114, DQM1 = 106
2816 09:27:45.827091 DQ Delay:
2817 09:27:45.830343 DQ0 =107, DQ1 =119, DQ2 =111, DQ3 =107
2818 09:27:45.833746 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2819 09:27:45.837011 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2820 09:27:45.840425 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2821 09:27:45.840506
2822 09:27:45.840570
2823 09:27:45.840629 ==
2824 09:27:45.843601 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 09:27:45.847050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2826 09:27:45.847133 ==
2827 09:27:45.847198
2828 09:27:45.847258
2829 09:27:45.850474 TX Vref Scan disable
2830 09:27:45.853680 == TX Byte 0 ==
2831 09:27:45.857125 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2832 09:27:45.860344 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2833 09:27:45.863707 == TX Byte 1 ==
2834 09:27:45.867076 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2835 09:27:45.870651 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2836 09:27:45.870732 ==
2837 09:27:45.873926 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 09:27:45.877023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 09:27:45.880206 ==
2840 09:27:45.890447 TX Vref=22, minBit 1, minWin=25, winSum=414
2841 09:27:45.894065 TX Vref=24, minBit 8, minWin=25, winSum=421
2842 09:27:45.897132 TX Vref=26, minBit 8, minWin=25, winSum=423
2843 09:27:45.900352 TX Vref=28, minBit 0, minWin=26, winSum=427
2844 09:27:45.903758 TX Vref=30, minBit 8, minWin=25, winSum=427
2845 09:27:45.907173 TX Vref=32, minBit 4, minWin=26, winSum=430
2846 09:27:45.913716 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 32
2847 09:27:45.913798
2848 09:27:45.917048 Final TX Range 1 Vref 32
2849 09:27:45.917130
2850 09:27:45.917194 ==
2851 09:27:45.920539 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 09:27:45.923633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2853 09:27:45.923716 ==
2854 09:27:45.926858
2855 09:27:45.926938
2856 09:27:45.927003 TX Vref Scan disable
2857 09:27:45.930400 == TX Byte 0 ==
2858 09:27:45.933638 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2859 09:27:45.936873 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2860 09:27:45.940530 == TX Byte 1 ==
2861 09:27:45.943678 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2862 09:27:45.946892 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2863 09:27:45.950572
2864 09:27:45.950654 [DATLAT]
2865 09:27:45.950719 Freq=1200, CH0 RK1
2866 09:27:45.950779
2867 09:27:45.953458 DATLAT Default: 0xc
2868 09:27:45.953539 0, 0xFFFF, sum = 0
2869 09:27:45.957106 1, 0xFFFF, sum = 0
2870 09:27:45.957189 2, 0xFFFF, sum = 0
2871 09:27:45.960330 3, 0xFFFF, sum = 0
2872 09:27:45.960414 4, 0xFFFF, sum = 0
2873 09:27:45.963816 5, 0xFFFF, sum = 0
2874 09:27:45.966933 6, 0xFFFF, sum = 0
2875 09:27:45.967017 7, 0xFFFF, sum = 0
2876 09:27:45.970248 8, 0xFFFF, sum = 0
2877 09:27:45.970331 9, 0xFFFF, sum = 0
2878 09:27:45.973562 10, 0xFFFF, sum = 0
2879 09:27:45.973645 11, 0x0, sum = 1
2880 09:27:45.977151 12, 0x0, sum = 2
2881 09:27:45.977234 13, 0x0, sum = 3
2882 09:27:45.977300 14, 0x0, sum = 4
2883 09:27:45.980118 best_step = 12
2884 09:27:45.980236
2885 09:27:45.980300 ==
2886 09:27:45.983886 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 09:27:45.986942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2888 09:27:45.987025 ==
2889 09:27:45.990192 RX Vref Scan: 0
2890 09:27:45.990274
2891 09:27:45.990338 RX Vref 0 -> 0, step: 1
2892 09:27:45.993745
2893 09:27:45.993826 RX Delay -21 -> 252, step: 4
2894 09:27:46.000735 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2895 09:27:46.003837 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2896 09:27:46.007404 iDelay=199, Bit 2, Center 112 (43 ~ 182) 140
2897 09:27:46.010569 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2898 09:27:46.014227 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2899 09:27:46.020365 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2900 09:27:46.024014 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2901 09:27:46.027284 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2902 09:27:46.030505 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2903 09:27:46.034069 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2904 09:27:46.040424 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2905 09:27:46.043941 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2906 09:27:46.047530 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2907 09:27:46.050424 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2908 09:27:46.053906 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2909 09:27:46.060555 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2910 09:27:46.060638 ==
2911 09:27:46.063793 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 09:27:46.067202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2913 09:27:46.067284 ==
2914 09:27:46.067349 DQS Delay:
2915 09:27:46.070493 DQS0 = 0, DQS1 = 0
2916 09:27:46.070574 DQM Delay:
2917 09:27:46.073805 DQM0 = 115, DQM1 = 105
2918 09:27:46.073887 DQ Delay:
2919 09:27:46.077149 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2920 09:27:46.080701 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2921 09:27:46.083965 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2922 09:27:46.087481 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2923 09:27:46.087564
2924 09:27:46.087628
2925 09:27:46.097771 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2926 09:27:46.100668 CH0 RK1: MR19=404, MR18=1111
2927 09:27:46.103911 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2928 09:27:46.107409 [RxdqsGatingPostProcess] freq 1200
2929 09:27:46.113847 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2930 09:27:46.117077 Pre-setting of DQS Precalculation
2931 09:27:46.120796 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2932 09:27:46.120878 ==
2933 09:27:46.123832 Dram Type= 6, Freq= 0, CH_1, rank 0
2934 09:27:46.130496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2935 09:27:46.130578 ==
2936 09:27:46.134292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2937 09:27:46.140243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2938 09:27:46.149140 [CA 0] Center 37 (7~68) winsize 62
2939 09:27:46.152478 [CA 1] Center 37 (7~68) winsize 62
2940 09:27:46.155848 [CA 2] Center 34 (4~65) winsize 62
2941 09:27:46.159037 [CA 3] Center 33 (3~64) winsize 62
2942 09:27:46.162635 [CA 4] Center 32 (2~63) winsize 62
2943 09:27:46.166277 [CA 5] Center 32 (2~63) winsize 62
2944 09:27:46.166358
2945 09:27:46.169202 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2946 09:27:46.169284
2947 09:27:46.172521 [CATrainingPosCal] consider 1 rank data
2948 09:27:46.175784 u2DelayCellTimex100 = 270/100 ps
2949 09:27:46.179354 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2950 09:27:46.182917 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2951 09:27:46.189371 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2952 09:27:46.192935 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2953 09:27:46.195964 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2954 09:27:46.199385 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2955 09:27:46.199468
2956 09:27:46.202765 CA PerBit enable=1, Macro0, CA PI delay=32
2957 09:27:46.202847
2958 09:27:46.206223 [CBTSetCACLKResult] CA Dly = 32
2959 09:27:46.206305 CS Dly: 5 (0~36)
2960 09:27:46.206371 ==
2961 09:27:46.209245 Dram Type= 6, Freq= 0, CH_1, rank 1
2962 09:27:46.215769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2963 09:27:46.215852 ==
2964 09:27:46.219233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2965 09:27:46.225856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2966 09:27:46.234463 [CA 0] Center 37 (7~68) winsize 62
2967 09:27:46.238009 [CA 1] Center 37 (6~68) winsize 63
2968 09:27:46.241416 [CA 2] Center 34 (3~65) winsize 63
2969 09:27:46.244454 [CA 3] Center 33 (3~64) winsize 62
2970 09:27:46.247854 [CA 4] Center 32 (2~63) winsize 62
2971 09:27:46.251100 [CA 5] Center 31 (1~62) winsize 62
2972 09:27:46.251182
2973 09:27:46.254361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2974 09:27:46.254443
2975 09:27:46.258015 [CATrainingPosCal] consider 2 rank data
2976 09:27:46.261078 u2DelayCellTimex100 = 270/100 ps
2977 09:27:46.264346 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2978 09:27:46.267821 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2979 09:27:46.274516 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2980 09:27:46.277709 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2981 09:27:46.281275 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2982 09:27:46.284793 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2983 09:27:46.284874
2984 09:27:46.287722 CA PerBit enable=1, Macro0, CA PI delay=32
2985 09:27:46.287804
2986 09:27:46.291547 [CBTSetCACLKResult] CA Dly = 32
2987 09:27:46.291629 CS Dly: 6 (0~38)
2988 09:27:46.291695
2989 09:27:46.294484 ----->DramcWriteLeveling(PI) begin...
2990 09:27:46.297833 ==
2991 09:27:46.301394 Dram Type= 6, Freq= 0, CH_1, rank 0
2992 09:27:46.304497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2993 09:27:46.304591 ==
2994 09:27:46.307689 Write leveling (Byte 0): 22 => 22
2995 09:27:46.310950 Write leveling (Byte 1): 22 => 22
2996 09:27:46.314293 DramcWriteLeveling(PI) end<-----
2997 09:27:46.314375
2998 09:27:46.314439 ==
2999 09:27:46.317675 Dram Type= 6, Freq= 0, CH_1, rank 0
3000 09:27:46.321088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3001 09:27:46.321170 ==
3002 09:27:46.324466 [Gating] SW mode calibration
3003 09:27:46.331051 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3004 09:27:46.334555 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3005 09:27:46.341084 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3006 09:27:46.344662 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3007 09:27:46.347720 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3008 09:27:46.354644 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3009 09:27:46.357850 0 11 16 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 1)
3010 09:27:46.361483 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3011 09:27:46.367646 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3012 09:27:46.370884 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3013 09:27:46.374401 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3014 09:27:46.381000 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3015 09:27:46.384486 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3016 09:27:46.387696 0 12 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
3017 09:27:46.394439 0 12 16 | B1->B0 | 3434 3f3f | 0 0 | (0 0) (1 1)
3018 09:27:46.397667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3019 09:27:46.401091 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3020 09:27:46.407774 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3021 09:27:46.410836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3022 09:27:46.414406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3023 09:27:46.420812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3024 09:27:46.424492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3025 09:27:46.427724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3026 09:27:46.434480 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3027 09:27:46.437631 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3028 09:27:46.440865 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3029 09:27:46.444325 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3030 09:27:46.450996 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3031 09:27:46.454280 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3032 09:27:46.457858 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3033 09:27:46.464279 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3034 09:27:46.467824 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3035 09:27:46.471054 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3036 09:27:46.477791 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3037 09:27:46.481362 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 09:27:46.484504 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 09:27:46.491154 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 09:27:46.494578 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3041 09:27:46.498150 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3042 09:27:46.504700 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3043 09:27:46.504782 Total UI for P1: 0, mck2ui 16
3044 09:27:46.507912 best dqsien dly found for B0: ( 0, 15, 14)
3045 09:27:46.514675 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 09:27:46.517859 Total UI for P1: 0, mck2ui 16
3047 09:27:46.521141 best dqsien dly found for B1: ( 0, 15, 18)
3048 09:27:46.524898 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3049 09:27:46.527929 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3050 09:27:46.528011
3051 09:27:46.531272 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3052 09:27:46.534554 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3053 09:27:46.537874 [Gating] SW calibration Done
3054 09:27:46.537955 ==
3055 09:27:46.541127 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 09:27:46.544609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3057 09:27:46.544691 ==
3058 09:27:46.548317 RX Vref Scan: 0
3059 09:27:46.548399
3060 09:27:46.551426 RX Vref 0 -> 0, step: 1
3061 09:27:46.551507
3062 09:27:46.551572 RX Delay -40 -> 252, step: 8
3063 09:27:46.557978 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3064 09:27:46.561878 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3065 09:27:46.564817 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3066 09:27:46.568082 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3067 09:27:46.571778 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3068 09:27:46.577905 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3069 09:27:46.581581 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3070 09:27:46.584698 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3071 09:27:46.587949 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3072 09:27:46.591541 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3073 09:27:46.594723 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3074 09:27:46.601615 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3075 09:27:46.604441 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3076 09:27:46.607774 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3077 09:27:46.611266 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3078 09:27:46.617922 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3079 09:27:46.618023 ==
3080 09:27:46.621358 Dram Type= 6, Freq= 0, CH_1, rank 0
3081 09:27:46.624485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3082 09:27:46.624569 ==
3083 09:27:46.624635 DQS Delay:
3084 09:27:46.628067 DQS0 = 0, DQS1 = 0
3085 09:27:46.628148 DQM Delay:
3086 09:27:46.631362 DQM0 = 116, DQM1 = 109
3087 09:27:46.631444 DQ Delay:
3088 09:27:46.634886 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3089 09:27:46.638010 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3090 09:27:46.641299 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =99
3091 09:27:46.644816 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3092 09:27:46.644898
3093 09:27:46.644963
3094 09:27:46.645023 ==
3095 09:27:46.647870 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 09:27:46.654681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3097 09:27:46.654800 ==
3098 09:27:46.654894
3099 09:27:46.654993
3100 09:27:46.655082 TX Vref Scan disable
3101 09:27:46.657840 == TX Byte 0 ==
3102 09:27:46.661603 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3103 09:27:46.664958 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3104 09:27:46.668036 == TX Byte 1 ==
3105 09:27:46.671289 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3106 09:27:46.674806 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3107 09:27:46.678102 ==
3108 09:27:46.681105 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 09:27:46.684619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 09:27:46.684701 ==
3111 09:27:46.695366 TX Vref=22, minBit 9, minWin=25, winSum=419
3112 09:27:46.698895 TX Vref=24, minBit 8, minWin=25, winSum=423
3113 09:27:46.702282 TX Vref=26, minBit 1, minWin=26, winSum=430
3114 09:27:46.705654 TX Vref=28, minBit 8, minWin=26, winSum=433
3115 09:27:46.709779 TX Vref=30, minBit 0, minWin=26, winSum=432
3116 09:27:46.712585 TX Vref=32, minBit 8, minWin=26, winSum=430
3117 09:27:46.719200 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3118 09:27:46.719282
3119 09:27:46.722548 Final TX Range 1 Vref 28
3120 09:27:46.722630
3121 09:27:46.722694 ==
3122 09:27:46.725975 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 09:27:46.729286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3124 09:27:46.729368 ==
3125 09:27:46.729433
3126 09:27:46.729492
3127 09:27:46.732432 TX Vref Scan disable
3128 09:27:46.735810 == TX Byte 0 ==
3129 09:27:46.739090 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3130 09:27:46.742308 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3131 09:27:46.745609 == TX Byte 1 ==
3132 09:27:46.749185 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3133 09:27:46.752444 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3134 09:27:46.752526
3135 09:27:46.755896 [DATLAT]
3136 09:27:46.755989 Freq=1200, CH1 RK0
3137 09:27:46.756055
3138 09:27:46.758949 DATLAT Default: 0xd
3139 09:27:46.759046 0, 0xFFFF, sum = 0
3140 09:27:46.762351 1, 0xFFFF, sum = 0
3141 09:27:46.762456 2, 0xFFFF, sum = 0
3142 09:27:46.765831 3, 0xFFFF, sum = 0
3143 09:27:46.765928 4, 0xFFFF, sum = 0
3144 09:27:46.769121 5, 0xFFFF, sum = 0
3145 09:27:46.769200 6, 0xFFFF, sum = 0
3146 09:27:46.772641 7, 0xFFFF, sum = 0
3147 09:27:46.772741 8, 0xFFFF, sum = 0
3148 09:27:46.775493 9, 0xFFFF, sum = 0
3149 09:27:46.775588 10, 0xFFFF, sum = 0
3150 09:27:46.779219 11, 0x0, sum = 1
3151 09:27:46.779317 12, 0x0, sum = 2
3152 09:27:46.782623 13, 0x0, sum = 3
3153 09:27:46.782726 14, 0x0, sum = 4
3154 09:27:46.785815 best_step = 12
3155 09:27:46.785883
3156 09:27:46.785956 ==
3157 09:27:46.789226 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 09:27:46.792397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3159 09:27:46.792484 ==
3160 09:27:46.795792 RX Vref Scan: 1
3161 09:27:46.795894
3162 09:27:46.795984 Set Vref Range= 32 -> 127
3163 09:27:46.796070
3164 09:27:46.799317 RX Vref 32 -> 127, step: 1
3165 09:27:46.799419
3166 09:27:46.802573 RX Delay -29 -> 252, step: 4
3167 09:27:46.802667
3168 09:27:46.805505 Set Vref, RX VrefLevel [Byte0]: 32
3169 09:27:46.808751 [Byte1]: 32
3170 09:27:46.808824
3171 09:27:46.812432 Set Vref, RX VrefLevel [Byte0]: 33
3172 09:27:46.815609 [Byte1]: 33
3173 09:27:46.819910
3174 09:27:46.820014 Set Vref, RX VrefLevel [Byte0]: 34
3175 09:27:46.823036 [Byte1]: 34
3176 09:27:46.827958
3177 09:27:46.828057 Set Vref, RX VrefLevel [Byte0]: 35
3178 09:27:46.831443 [Byte1]: 35
3179 09:27:46.835671
3180 09:27:46.835769 Set Vref, RX VrefLevel [Byte0]: 36
3181 09:27:46.839056 [Byte1]: 36
3182 09:27:46.844090
3183 09:27:46.844211 Set Vref, RX VrefLevel [Byte0]: 37
3184 09:27:46.846964 [Byte1]: 37
3185 09:27:46.851829
3186 09:27:46.851927 Set Vref, RX VrefLevel [Byte0]: 38
3187 09:27:46.854923 [Byte1]: 38
3188 09:27:46.859733
3189 09:27:46.859816 Set Vref, RX VrefLevel [Byte0]: 39
3190 09:27:46.863133 [Byte1]: 39
3191 09:27:46.867940
3192 09:27:46.868021 Set Vref, RX VrefLevel [Byte0]: 40
3193 09:27:46.870988 [Byte1]: 40
3194 09:27:46.875609
3195 09:27:46.875691 Set Vref, RX VrefLevel [Byte0]: 41
3196 09:27:46.878824 [Byte1]: 41
3197 09:27:46.883464
3198 09:27:46.883545 Set Vref, RX VrefLevel [Byte0]: 42
3199 09:27:46.887175 [Byte1]: 42
3200 09:27:46.891436
3201 09:27:46.891517 Set Vref, RX VrefLevel [Byte0]: 43
3202 09:27:46.894681 [Byte1]: 43
3203 09:27:46.899311
3204 09:27:46.899392 Set Vref, RX VrefLevel [Byte0]: 44
3205 09:27:46.902685 [Byte1]: 44
3206 09:27:46.907256
3207 09:27:46.907337 Set Vref, RX VrefLevel [Byte0]: 45
3208 09:27:46.910560 [Byte1]: 45
3209 09:27:46.915268
3210 09:27:46.915350 Set Vref, RX VrefLevel [Byte0]: 46
3211 09:27:46.918856 [Byte1]: 46
3212 09:27:46.923290
3213 09:27:46.923372 Set Vref, RX VrefLevel [Byte0]: 47
3214 09:27:46.926595 [Byte1]: 47
3215 09:27:46.931453
3216 09:27:46.931534 Set Vref, RX VrefLevel [Byte0]: 48
3217 09:27:46.934668 [Byte1]: 48
3218 09:27:46.939260
3219 09:27:46.939341 Set Vref, RX VrefLevel [Byte0]: 49
3220 09:27:46.942558 [Byte1]: 49
3221 09:27:46.947183
3222 09:27:46.947264 Set Vref, RX VrefLevel [Byte0]: 50
3223 09:27:46.950443 [Byte1]: 50
3224 09:27:46.955367
3225 09:27:46.955453 Set Vref, RX VrefLevel [Byte0]: 51
3226 09:27:46.958364 [Byte1]: 51
3227 09:27:46.963528
3228 09:27:46.963610 Set Vref, RX VrefLevel [Byte0]: 52
3229 09:27:46.966292 [Byte1]: 52
3230 09:27:46.971029
3231 09:27:46.971110 Set Vref, RX VrefLevel [Byte0]: 53
3232 09:27:46.974421 [Byte1]: 53
3233 09:27:46.979277
3234 09:27:46.979361 Set Vref, RX VrefLevel [Byte0]: 54
3235 09:27:46.982475 [Byte1]: 54
3236 09:27:46.987070
3237 09:27:46.987151 Set Vref, RX VrefLevel [Byte0]: 55
3238 09:27:46.990280 [Byte1]: 55
3239 09:27:46.995390
3240 09:27:46.995471 Set Vref, RX VrefLevel [Byte0]: 56
3241 09:27:46.998256 [Byte1]: 56
3242 09:27:47.002964
3243 09:27:47.003045 Set Vref, RX VrefLevel [Byte0]: 57
3244 09:27:47.006469 [Byte1]: 57
3245 09:27:47.011021
3246 09:27:47.011102 Set Vref, RX VrefLevel [Byte0]: 58
3247 09:27:47.014100 [Byte1]: 58
3248 09:27:47.019070
3249 09:27:47.019151 Set Vref, RX VrefLevel [Byte0]: 59
3250 09:27:47.022355 [Byte1]: 59
3251 09:27:47.026730
3252 09:27:47.026811 Set Vref, RX VrefLevel [Byte0]: 60
3253 09:27:47.030295 [Byte1]: 60
3254 09:27:47.034962
3255 09:27:47.035044 Set Vref, RX VrefLevel [Byte0]: 61
3256 09:27:47.037917 [Byte1]: 61
3257 09:27:47.042585
3258 09:27:47.042666 Set Vref, RX VrefLevel [Byte0]: 62
3259 09:27:47.046040 [Byte1]: 62
3260 09:27:47.050710
3261 09:27:47.050790 Set Vref, RX VrefLevel [Byte0]: 63
3262 09:27:47.053935 [Byte1]: 63
3263 09:27:47.058586
3264 09:27:47.058667 Set Vref, RX VrefLevel [Byte0]: 64
3265 09:27:47.063400 [Byte1]: 64
3266 09:27:47.066864
3267 09:27:47.066945 Set Vref, RX VrefLevel [Byte0]: 65
3268 09:27:47.070180 [Byte1]: 65
3269 09:27:47.074695
3270 09:27:47.074776 Final RX Vref Byte 0 = 54 to rank0
3271 09:27:47.078207 Final RX Vref Byte 1 = 48 to rank0
3272 09:27:47.081379 Final RX Vref Byte 0 = 54 to rank1
3273 09:27:47.084587 Final RX Vref Byte 1 = 48 to rank1==
3274 09:27:47.087897 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 09:27:47.094532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3276 09:27:47.094614 ==
3277 09:27:47.094678 DQS Delay:
3278 09:27:47.094739 DQS0 = 0, DQS1 = 0
3279 09:27:47.098303 DQM Delay:
3280 09:27:47.098385 DQM0 = 115, DQM1 = 106
3281 09:27:47.101722 DQ Delay:
3282 09:27:47.104685 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3283 09:27:47.108171 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3284 09:27:47.111522 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3285 09:27:47.115091 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3286 09:27:47.115173
3287 09:27:47.115237
3288 09:27:47.121335 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3289 09:27:47.124601 CH1 RK0: MR19=404, MR18=1919
3290 09:27:47.131276 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3291 09:27:47.131359
3292 09:27:47.134762 ----->DramcWriteLeveling(PI) begin...
3293 09:27:47.134845 ==
3294 09:27:47.138271 Dram Type= 6, Freq= 0, CH_1, rank 1
3295 09:27:47.141336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3296 09:27:47.141418 ==
3297 09:27:47.144738 Write leveling (Byte 0): 22 => 22
3298 09:27:47.147921 Write leveling (Byte 1): 22 => 22
3299 09:27:47.151654 DramcWriteLeveling(PI) end<-----
3300 09:27:47.151735
3301 09:27:47.151800 ==
3302 09:27:47.154617 Dram Type= 6, Freq= 0, CH_1, rank 1
3303 09:27:47.158036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3304 09:27:47.161258 ==
3305 09:27:47.161340 [Gating] SW mode calibration
3306 09:27:47.171479 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3307 09:27:47.174869 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3308 09:27:47.178298 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3309 09:27:47.184555 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3310 09:27:47.187931 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3311 09:27:47.191239 0 11 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
3312 09:27:47.197891 0 11 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3313 09:27:47.201297 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3314 09:27:47.204511 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3315 09:27:47.211358 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3316 09:27:47.214444 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3317 09:27:47.218095 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3318 09:27:47.224679 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3319 09:27:47.228255 0 12 12 | B1->B0 | 2525 4040 | 0 1 | (0 0) (0 0)
3320 09:27:47.231109 0 12 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3321 09:27:47.237885 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3322 09:27:47.241300 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3323 09:27:47.244835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3324 09:27:47.247972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3325 09:27:47.254482 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3326 09:27:47.257943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3327 09:27:47.261323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3328 09:27:47.268136 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3329 09:27:47.271372 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3330 09:27:47.274640 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 09:27:47.281097 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3332 09:27:47.284486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3333 09:27:47.287958 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3334 09:27:47.294642 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3335 09:27:47.297994 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3336 09:27:47.301258 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3337 09:27:47.307885 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3338 09:27:47.311286 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 09:27:47.314596 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3340 09:27:47.321331 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3341 09:27:47.324753 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 09:27:47.328139 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 09:27:47.334669 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3344 09:27:47.337916 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3345 09:27:47.341409 Total UI for P1: 0, mck2ui 16
3346 09:27:47.344881 best dqsien dly found for B0: ( 0, 15, 12)
3347 09:27:47.348083 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 09:27:47.351456 Total UI for P1: 0, mck2ui 16
3349 09:27:47.354673 best dqsien dly found for B1: ( 0, 15, 16)
3350 09:27:47.358392 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3351 09:27:47.361351 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3352 09:27:47.361432
3353 09:27:47.364554 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3354 09:27:47.371275 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3355 09:27:47.371356 [Gating] SW calibration Done
3356 09:27:47.371421 ==
3357 09:27:47.375047 Dram Type= 6, Freq= 0, CH_1, rank 1
3358 09:27:47.381234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3359 09:27:47.381316 ==
3360 09:27:47.381380 RX Vref Scan: 0
3361 09:27:47.381440
3362 09:27:47.384694 RX Vref 0 -> 0, step: 1
3363 09:27:47.384776
3364 09:27:47.388145 RX Delay -40 -> 252, step: 8
3365 09:27:47.391357 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3366 09:27:47.394614 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3367 09:27:47.397927 iDelay=200, Bit 2, Center 103 (24 ~ 183) 160
3368 09:27:47.401648 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3369 09:27:47.408275 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3370 09:27:47.411357 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3371 09:27:47.414734 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3372 09:27:47.417936 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3373 09:27:47.421739 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3374 09:27:47.428067 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3375 09:27:47.431353 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3376 09:27:47.434777 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3377 09:27:47.438610 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3378 09:27:47.441274 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3379 09:27:47.447969 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3380 09:27:47.451473 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3381 09:27:47.451555 ==
3382 09:27:47.454563 Dram Type= 6, Freq= 0, CH_1, rank 1
3383 09:27:47.457929 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3384 09:27:47.458012 ==
3385 09:27:47.461454 DQS Delay:
3386 09:27:47.461534 DQS0 = 0, DQS1 = 0
3387 09:27:47.461598 DQM Delay:
3388 09:27:47.464504 DQM0 = 115, DQM1 = 105
3389 09:27:47.464585 DQ Delay:
3390 09:27:47.467904 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3391 09:27:47.471328 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3392 09:27:47.474716 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3393 09:27:47.477935 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3394 09:27:47.481200
3395 09:27:47.481281
3396 09:27:47.481344 ==
3397 09:27:47.484764 Dram Type= 6, Freq= 0, CH_1, rank 1
3398 09:27:47.487778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3399 09:27:47.487859 ==
3400 09:27:47.487923
3401 09:27:47.487983
3402 09:27:47.491255 TX Vref Scan disable
3403 09:27:47.491336 == TX Byte 0 ==
3404 09:27:47.497860 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3405 09:27:47.501304 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3406 09:27:47.501385 == TX Byte 1 ==
3407 09:27:47.507888 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3408 09:27:47.511204 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3409 09:27:47.511286 ==
3410 09:27:47.514523 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 09:27:47.518352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3412 09:27:47.518434 ==
3413 09:27:47.530001 TX Vref=22, minBit 0, minWin=25, winSum=419
3414 09:27:47.533124 TX Vref=24, minBit 1, minWin=26, winSum=426
3415 09:27:47.537011 TX Vref=26, minBit 3, minWin=26, winSum=428
3416 09:27:47.540237 TX Vref=28, minBit 3, minWin=26, winSum=430
3417 09:27:47.543583 TX Vref=30, minBit 0, minWin=26, winSum=433
3418 09:27:47.546509 TX Vref=32, minBit 0, minWin=26, winSum=432
3419 09:27:47.553122 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
3420 09:27:47.553205
3421 09:27:47.556540 Final TX Range 1 Vref 30
3422 09:27:47.556623
3423 09:27:47.556687 ==
3424 09:27:47.560192 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 09:27:47.563313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 09:27:47.563398 ==
3427 09:27:47.563463
3428 09:27:47.566449
3429 09:27:47.566530 TX Vref Scan disable
3430 09:27:47.569963 == TX Byte 0 ==
3431 09:27:47.573659 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3432 09:27:47.576676 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3433 09:27:47.579959 == TX Byte 1 ==
3434 09:27:47.583227 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3435 09:27:47.586577 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3436 09:27:47.586659
3437 09:27:47.590565 [DATLAT]
3438 09:27:47.590646 Freq=1200, CH1 RK1
3439 09:27:47.590712
3440 09:27:47.593308 DATLAT Default: 0xc
3441 09:27:47.593390 0, 0xFFFF, sum = 0
3442 09:27:47.596573 1, 0xFFFF, sum = 0
3443 09:27:47.596657 2, 0xFFFF, sum = 0
3444 09:27:47.600132 3, 0xFFFF, sum = 0
3445 09:27:47.600221 4, 0xFFFF, sum = 0
3446 09:27:47.603171 5, 0xFFFF, sum = 0
3447 09:27:47.603254 6, 0xFFFF, sum = 0
3448 09:27:47.606477 7, 0xFFFF, sum = 0
3449 09:27:47.609793 8, 0xFFFF, sum = 0
3450 09:27:47.609876 9, 0xFFFF, sum = 0
3451 09:27:47.613235 10, 0xFFFF, sum = 0
3452 09:27:47.613318 11, 0x0, sum = 1
3453 09:27:47.613384 12, 0x0, sum = 2
3454 09:27:47.616563 13, 0x0, sum = 3
3455 09:27:47.616646 14, 0x0, sum = 4
3456 09:27:47.620052 best_step = 12
3457 09:27:47.620133
3458 09:27:47.620203 ==
3459 09:27:47.623065 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 09:27:47.626607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3461 09:27:47.626690 ==
3462 09:27:47.629878 RX Vref Scan: 0
3463 09:27:47.629960
3464 09:27:47.630025 RX Vref 0 -> 0, step: 1
3465 09:27:47.630086
3466 09:27:47.633066 RX Delay -29 -> 252, step: 4
3467 09:27:47.640541 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3468 09:27:47.643705 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3469 09:27:47.646809 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3470 09:27:47.650079 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3471 09:27:47.653443 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3472 09:27:47.660151 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3473 09:27:47.663672 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3474 09:27:47.667064 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3475 09:27:47.670231 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3476 09:27:47.673604 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3477 09:27:47.680394 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3478 09:27:47.683590 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3479 09:27:47.686939 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3480 09:27:47.690354 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3481 09:27:47.693578 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3482 09:27:47.700477 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3483 09:27:47.700554 ==
3484 09:27:47.703630 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 09:27:47.706945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3486 09:27:47.707047 ==
3487 09:27:47.707147 DQS Delay:
3488 09:27:47.710402 DQS0 = 0, DQS1 = 0
3489 09:27:47.710500 DQM Delay:
3490 09:27:47.713414 DQM0 = 115, DQM1 = 103
3491 09:27:47.713486 DQ Delay:
3492 09:27:47.716912 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3493 09:27:47.720239 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3494 09:27:47.723925 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3495 09:27:47.726836 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3496 09:27:47.726935
3497 09:27:47.727035
3498 09:27:47.736935 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3499 09:27:47.737019 CH1 RK1: MR19=404, MR18=808
3500 09:27:47.743704 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3501 09:27:47.746980 [RxdqsGatingPostProcess] freq 1200
3502 09:27:47.753662 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3503 09:27:47.757264 Pre-setting of DQS Precalculation
3504 09:27:47.760448 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3505 09:27:47.770051 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3506 09:27:47.776709 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3507 09:27:47.776792
3508 09:27:47.776856
3509 09:27:47.780344 [Calibration Summary] 2400 Mbps
3510 09:27:47.780426 CH 0, Rank 0
3511 09:27:47.783434 SW Impedance : PASS
3512 09:27:47.783516 DUTY Scan : NO K
3513 09:27:47.786867 ZQ Calibration : PASS
3514 09:27:47.790149 Jitter Meter : NO K
3515 09:27:47.790231 CBT Training : PASS
3516 09:27:47.793967 Write leveling : PASS
3517 09:27:47.796742 RX DQS gating : PASS
3518 09:27:47.796824 RX DQ/DQS(RDDQC) : PASS
3519 09:27:47.800499 TX DQ/DQS : PASS
3520 09:27:47.800582 RX DATLAT : PASS
3521 09:27:47.803408 RX DQ/DQS(Engine): PASS
3522 09:27:47.806562 TX OE : NO K
3523 09:27:47.806643 All Pass.
3524 09:27:47.806708
3525 09:27:47.806768 CH 0, Rank 1
3526 09:27:47.810176 SW Impedance : PASS
3527 09:27:47.813838 DUTY Scan : NO K
3528 09:27:47.813920 ZQ Calibration : PASS
3529 09:27:47.816688 Jitter Meter : NO K
3530 09:27:47.819988 CBT Training : PASS
3531 09:27:47.820069 Write leveling : PASS
3532 09:27:47.823376 RX DQS gating : PASS
3533 09:27:47.826615 RX DQ/DQS(RDDQC) : PASS
3534 09:27:47.826697 TX DQ/DQS : PASS
3535 09:27:47.830270 RX DATLAT : PASS
3536 09:27:47.833394 RX DQ/DQS(Engine): PASS
3537 09:27:47.833475 TX OE : NO K
3538 09:27:47.836877 All Pass.
3539 09:27:47.836958
3540 09:27:47.837021 CH 1, Rank 0
3541 09:27:47.839868 SW Impedance : PASS
3542 09:27:47.839949 DUTY Scan : NO K
3543 09:27:47.843358 ZQ Calibration : PASS
3544 09:27:47.846554 Jitter Meter : NO K
3545 09:27:47.846636 CBT Training : PASS
3546 09:27:47.850182 Write leveling : PASS
3547 09:27:47.850264 RX DQS gating : PASS
3548 09:27:47.853357 RX DQ/DQS(RDDQC) : PASS
3549 09:27:47.856692 TX DQ/DQS : PASS
3550 09:27:47.856774 RX DATLAT : PASS
3551 09:27:47.859825 RX DQ/DQS(Engine): PASS
3552 09:27:47.863477 TX OE : NO K
3553 09:27:47.863559 All Pass.
3554 09:27:47.863624
3555 09:27:47.863684 CH 1, Rank 1
3556 09:27:47.866671 SW Impedance : PASS
3557 09:27:47.870142 DUTY Scan : NO K
3558 09:27:47.870224 ZQ Calibration : PASS
3559 09:27:47.873334 Jitter Meter : NO K
3560 09:27:47.876700 CBT Training : PASS
3561 09:27:47.876782 Write leveling : PASS
3562 09:27:47.880072 RX DQS gating : PASS
3563 09:27:47.883298 RX DQ/DQS(RDDQC) : PASS
3564 09:27:47.883418 TX DQ/DQS : PASS
3565 09:27:47.886676 RX DATLAT : PASS
3566 09:27:47.886757 RX DQ/DQS(Engine): PASS
3567 09:27:47.890512 TX OE : NO K
3568 09:27:47.890594 All Pass.
3569 09:27:47.890658
3570 09:27:47.893282 DramC Write-DBI off
3571 09:27:47.896608 PER_BANK_REFRESH: Hybrid Mode
3572 09:27:47.896690 TX_TRACKING: ON
3573 09:27:47.906636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3574 09:27:47.909782 [FAST_K] Save calibration result to emmc
3575 09:27:47.913029 dramc_set_vcore_voltage set vcore to 650000
3576 09:27:47.916409 Read voltage for 600, 5
3577 09:27:47.916490 Vio18 = 0
3578 09:27:47.919727 Vcore = 650000
3579 09:27:47.919808 Vdram = 0
3580 09:27:47.919872 Vddq = 0
3581 09:27:47.919932 Vmddr = 0
3582 09:27:47.926494 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3583 09:27:47.933386 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3584 09:27:47.933468 MEM_TYPE=3, freq_sel=19
3585 09:27:47.936393 sv_algorithm_assistance_LP4_1600
3586 09:27:47.939849 ============ PULL DRAM RESETB DOWN ============
3587 09:27:47.946538 ========== PULL DRAM RESETB DOWN end =========
3588 09:27:47.949655 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3589 09:27:47.953152 ===================================
3590 09:27:47.956652 LPDDR4 DRAM CONFIGURATION
3591 09:27:47.959858 ===================================
3592 09:27:47.959940 EX_ROW_EN[0] = 0x0
3593 09:27:47.963110 EX_ROW_EN[1] = 0x0
3594 09:27:47.963191 LP4Y_EN = 0x0
3595 09:27:47.966359 WORK_FSP = 0x0
3596 09:27:47.966441 WL = 0x2
3597 09:27:47.969894 RL = 0x2
3598 09:27:47.969975 BL = 0x2
3599 09:27:47.973037 RPST = 0x0
3600 09:27:47.973123 RD_PRE = 0x0
3601 09:27:47.976570 WR_PRE = 0x1
3602 09:27:47.976651 WR_PST = 0x0
3603 09:27:47.979881 DBI_WR = 0x0
3604 09:27:47.983158 DBI_RD = 0x0
3605 09:27:47.983331 OTF = 0x1
3606 09:27:47.986313 ===================================
3607 09:27:47.989481 ===================================
3608 09:27:47.989563 ANA top config
3609 09:27:47.993176 ===================================
3610 09:27:47.996206 DLL_ASYNC_EN = 0
3611 09:27:47.999661 ALL_SLAVE_EN = 1
3612 09:27:48.003184 NEW_RANK_MODE = 1
3613 09:27:48.006375 DLL_IDLE_MODE = 1
3614 09:27:48.006457 LP45_APHY_COMB_EN = 1
3615 09:27:48.009756 TX_ODT_DIS = 1
3616 09:27:48.012982 NEW_8X_MODE = 1
3617 09:27:48.016229 ===================================
3618 09:27:48.019692 ===================================
3619 09:27:48.023127 data_rate = 1200
3620 09:27:48.026433 CKR = 1
3621 09:27:48.026515 DQ_P2S_RATIO = 8
3622 09:27:48.029668 ===================================
3623 09:27:48.032791 CA_P2S_RATIO = 8
3624 09:27:48.036269 DQ_CA_OPEN = 0
3625 09:27:48.039465 DQ_SEMI_OPEN = 0
3626 09:27:48.042634 CA_SEMI_OPEN = 0
3627 09:27:48.046095 CA_FULL_RATE = 0
3628 09:27:48.046177 DQ_CKDIV4_EN = 1
3629 09:27:48.049258 CA_CKDIV4_EN = 1
3630 09:27:48.052757 CA_PREDIV_EN = 0
3631 09:27:48.056109 PH8_DLY = 0
3632 09:27:48.059193 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3633 09:27:48.062714 DQ_AAMCK_DIV = 4
3634 09:27:48.062795 CA_AAMCK_DIV = 4
3635 09:27:48.065892 CA_ADMCK_DIV = 4
3636 09:27:48.069488 DQ_TRACK_CA_EN = 0
3637 09:27:48.072768 CA_PICK = 600
3638 09:27:48.075981 CA_MCKIO = 600
3639 09:27:48.079646 MCKIO_SEMI = 0
3640 09:27:48.082677 PLL_FREQ = 2288
3641 09:27:48.082759 DQ_UI_PI_RATIO = 32
3642 09:27:48.085819 CA_UI_PI_RATIO = 0
3643 09:27:48.089445 ===================================
3644 09:27:48.092684 ===================================
3645 09:27:48.095764 memory_type:LPDDR4
3646 09:27:48.099134 GP_NUM : 10
3647 09:27:48.099216 SRAM_EN : 1
3648 09:27:48.102511 MD32_EN : 0
3649 09:27:48.105942 ===================================
3650 09:27:48.106025 [ANA_INIT] >>>>>>>>>>>>>>
3651 09:27:48.109251 <<<<<< [CONFIGURE PHASE]: ANA_TX
3652 09:27:48.112746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3653 09:27:48.115865 ===================================
3654 09:27:48.119107 data_rate = 1200,PCW = 0X5800
3655 09:27:48.122340 ===================================
3656 09:27:48.125811 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3657 09:27:48.132349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3658 09:27:48.139391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3659 09:27:48.142589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3660 09:27:48.145756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3661 09:27:48.149069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3662 09:27:48.152333 [ANA_INIT] flow start
3663 09:27:48.152415 [ANA_INIT] PLL >>>>>>>>
3664 09:27:48.155613 [ANA_INIT] PLL <<<<<<<<
3665 09:27:48.158873 [ANA_INIT] MIDPI >>>>>>>>
3666 09:27:48.158954 [ANA_INIT] MIDPI <<<<<<<<
3667 09:27:48.162375 [ANA_INIT] DLL >>>>>>>>
3668 09:27:48.165579 [ANA_INIT] flow end
3669 09:27:48.168957 ============ LP4 DIFF to SE enter ============
3670 09:27:48.172308 ============ LP4 DIFF to SE exit ============
3671 09:27:48.175976 [ANA_INIT] <<<<<<<<<<<<<
3672 09:27:48.179170 [Flow] Enable top DCM control >>>>>
3673 09:27:48.182546 [Flow] Enable top DCM control <<<<<
3674 09:27:48.185646 Enable DLL master slave shuffle
3675 09:27:48.189076 ==============================================================
3676 09:27:48.192350 Gating Mode config
3677 09:27:48.199255 ==============================================================
3678 09:27:48.199337 Config description:
3679 09:27:48.208843 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3680 09:27:48.215758 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3681 09:27:48.218776 SELPH_MODE 0: By rank 1: By Phase
3682 09:27:48.225228 ==============================================================
3683 09:27:48.229011 GAT_TRACK_EN = 1
3684 09:27:48.232108 RX_GATING_MODE = 2
3685 09:27:48.235498 RX_GATING_TRACK_MODE = 2
3686 09:27:48.238676 SELPH_MODE = 1
3687 09:27:48.241853 PICG_EARLY_EN = 1
3688 09:27:48.245324 VALID_LAT_VALUE = 1
3689 09:27:48.248510 ==============================================================
3690 09:27:48.252035 Enter into Gating configuration >>>>
3691 09:27:48.255273 Exit from Gating configuration <<<<
3692 09:27:48.258511 Enter into DVFS_PRE_config >>>>>
3693 09:27:48.271885 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3694 09:27:48.271969 Exit from DVFS_PRE_config <<<<<
3695 09:27:48.275026 Enter into PICG configuration >>>>
3696 09:27:48.278569 Exit from PICG configuration <<<<
3697 09:27:48.281643 [RX_INPUT] configuration >>>>>
3698 09:27:48.285026 [RX_INPUT] configuration <<<<<
3699 09:27:48.291668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3700 09:27:48.294796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3701 09:27:48.301667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3702 09:27:48.308222 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3703 09:27:48.314692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3704 09:27:48.321385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3705 09:27:48.325018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3706 09:27:48.328085 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3707 09:27:48.331582 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3708 09:27:48.338180 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3709 09:27:48.341377 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3710 09:27:48.345012 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3711 09:27:48.347934 ===================================
3712 09:27:48.351214 LPDDR4 DRAM CONFIGURATION
3713 09:27:48.354846 ===================================
3714 09:27:48.357990 EX_ROW_EN[0] = 0x0
3715 09:27:48.358070 EX_ROW_EN[1] = 0x0
3716 09:27:48.361361 LP4Y_EN = 0x0
3717 09:27:48.361438 WORK_FSP = 0x0
3718 09:27:48.364431 WL = 0x2
3719 09:27:48.364522 RL = 0x2
3720 09:27:48.367733 BL = 0x2
3721 09:27:48.367832 RPST = 0x0
3722 09:27:48.370978 RD_PRE = 0x0
3723 09:27:48.371051 WR_PRE = 0x1
3724 09:27:48.374203 WR_PST = 0x0
3725 09:27:48.374301 DBI_WR = 0x0
3726 09:27:48.377543 DBI_RD = 0x0
3727 09:27:48.377649 OTF = 0x1
3728 09:27:48.380924 ===================================
3729 09:27:48.387807 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3730 09:27:48.390937 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3731 09:27:48.394726 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3732 09:27:48.397628 ===================================
3733 09:27:48.401098 LPDDR4 DRAM CONFIGURATION
3734 09:27:48.404252 ===================================
3735 09:27:48.407400 EX_ROW_EN[0] = 0x10
3736 09:27:48.407496 EX_ROW_EN[1] = 0x0
3737 09:27:48.410767 LP4Y_EN = 0x0
3738 09:27:48.410865 WORK_FSP = 0x0
3739 09:27:48.414113 WL = 0x2
3740 09:27:48.414181 RL = 0x2
3741 09:27:48.417422 BL = 0x2
3742 09:27:48.417494 RPST = 0x0
3743 09:27:48.420732 RD_PRE = 0x0
3744 09:27:48.420830 WR_PRE = 0x1
3745 09:27:48.424170 WR_PST = 0x0
3746 09:27:48.424272 DBI_WR = 0x0
3747 09:27:48.427169 DBI_RD = 0x0
3748 09:27:48.427263 OTF = 0x1
3749 09:27:48.430479 ===================================
3750 09:27:48.437138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3751 09:27:48.442010 nWR fixed to 30
3752 09:27:48.445140 [ModeRegInit_LP4] CH0 RK0
3753 09:27:48.445210 [ModeRegInit_LP4] CH0 RK1
3754 09:27:48.448432 [ModeRegInit_LP4] CH1 RK0
3755 09:27:48.451859 [ModeRegInit_LP4] CH1 RK1
3756 09:27:48.451954 match AC timing 16
3757 09:27:48.458681 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3758 09:27:48.461708 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3759 09:27:48.465221 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3760 09:27:48.471887 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3761 09:27:48.474972 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3762 09:27:48.475069 ==
3763 09:27:48.478291 Dram Type= 6, Freq= 0, CH_0, rank 0
3764 09:27:48.481707 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3765 09:27:48.481776 ==
3766 09:27:48.488756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3767 09:27:48.495065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3768 09:27:48.498297 [CA 0] Center 35 (5~66) winsize 62
3769 09:27:48.501497 [CA 1] Center 35 (5~66) winsize 62
3770 09:27:48.504767 [CA 2] Center 34 (4~65) winsize 62
3771 09:27:48.508200 [CA 3] Center 34 (3~65) winsize 63
3772 09:27:48.511527 [CA 4] Center 33 (3~64) winsize 62
3773 09:27:48.515054 [CA 5] Center 33 (3~64) winsize 62
3774 09:27:48.515146
3775 09:27:48.518488 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3776 09:27:48.518565
3777 09:27:48.521292 [CATrainingPosCal] consider 1 rank data
3778 09:27:48.524662 u2DelayCellTimex100 = 270/100 ps
3779 09:27:48.528053 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3780 09:27:48.531381 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3781 09:27:48.534632 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3782 09:27:48.538262 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3783 09:27:48.541350 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3784 09:27:48.548132 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3785 09:27:48.548243
3786 09:27:48.551197 CA PerBit enable=1, Macro0, CA PI delay=33
3787 09:27:48.551297
3788 09:27:48.554896 [CBTSetCACLKResult] CA Dly = 33
3789 09:27:48.554997 CS Dly: 5 (0~36)
3790 09:27:48.555087 ==
3791 09:27:48.557831 Dram Type= 6, Freq= 0, CH_0, rank 1
3792 09:27:48.561336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3793 09:27:48.564509 ==
3794 09:27:48.567985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3795 09:27:48.574528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3796 09:27:48.578018 [CA 0] Center 35 (5~66) winsize 62
3797 09:27:48.581000 [CA 1] Center 35 (5~66) winsize 62
3798 09:27:48.584421 [CA 2] Center 34 (4~65) winsize 62
3799 09:27:48.587673 [CA 3] Center 34 (3~65) winsize 63
3800 09:27:48.591399 [CA 4] Center 33 (3~64) winsize 62
3801 09:27:48.594705 [CA 5] Center 33 (3~64) winsize 62
3802 09:27:48.594809
3803 09:27:48.598049 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3804 09:27:48.598147
3805 09:27:48.601088 [CATrainingPosCal] consider 2 rank data
3806 09:27:48.604377 u2DelayCellTimex100 = 270/100 ps
3807 09:27:48.607874 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3808 09:27:48.611008 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3809 09:27:48.614316 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3810 09:27:48.617764 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3811 09:27:48.624660 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3812 09:27:48.627803 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3813 09:27:48.627901
3814 09:27:48.630950 CA PerBit enable=1, Macro0, CA PI delay=33
3815 09:27:48.631051
3816 09:27:48.634380 [CBTSetCACLKResult] CA Dly = 33
3817 09:27:48.634484 CS Dly: 5 (0~36)
3818 09:27:48.634577
3819 09:27:48.637762 ----->DramcWriteLeveling(PI) begin...
3820 09:27:48.637862 ==
3821 09:27:48.641044 Dram Type= 6, Freq= 0, CH_0, rank 0
3822 09:27:48.647548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3823 09:27:48.647625 ==
3824 09:27:48.650851 Write leveling (Byte 0): 29 => 29
3825 09:27:48.654216 Write leveling (Byte 1): 29 => 29
3826 09:27:48.654319 DramcWriteLeveling(PI) end<-----
3827 09:27:48.654409
3828 09:27:48.657486 ==
3829 09:27:48.660785 Dram Type= 6, Freq= 0, CH_0, rank 0
3830 09:27:48.664317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3831 09:27:48.664388 ==
3832 09:27:48.667626 [Gating] SW mode calibration
3833 09:27:48.674256 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3834 09:27:48.678185 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3835 09:27:48.684246 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3836 09:27:48.687403 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3837 09:27:48.691190 0 5 8 | B1->B0 | 3232 3232 | 1 0 | (1 1) (0 0)
3838 09:27:48.697655 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3839 09:27:48.701199 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3840 09:27:48.704250 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3841 09:27:48.710657 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3842 09:27:48.714176 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3843 09:27:48.717246 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3844 09:27:48.724327 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3845 09:27:48.727437 0 6 8 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (1 1)
3846 09:27:48.730924 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3847 09:27:48.737262 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3848 09:27:48.740734 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3849 09:27:48.743868 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3850 09:27:48.750944 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3851 09:27:48.754363 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3852 09:27:48.757129 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3853 09:27:48.760657 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3854 09:27:48.767384 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3855 09:27:48.770413 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3856 09:27:48.774224 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3857 09:27:48.780648 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3858 09:27:48.784091 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3859 09:27:48.787121 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3860 09:27:48.793954 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3861 09:27:48.797100 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3862 09:27:48.800773 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3863 09:27:48.807267 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3864 09:27:48.810591 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3865 09:27:48.813914 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 09:27:48.820352 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 09:27:48.823732 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 09:27:48.827154 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 09:27:48.833742 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3870 09:27:48.837250 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 09:27:48.840098 Total UI for P1: 0, mck2ui 16
3872 09:27:48.843615 best dqsien dly found for B0: ( 0, 9, 8)
3873 09:27:48.847192 Total UI for P1: 0, mck2ui 16
3874 09:27:48.850197 best dqsien dly found for B1: ( 0, 9, 8)
3875 09:27:48.853455 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3876 09:27:48.856742 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3877 09:27:48.856814
3878 09:27:48.860143 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3879 09:27:48.863200 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3880 09:27:48.866697 [Gating] SW calibration Done
3881 09:27:48.866796 ==
3882 09:27:48.870219 Dram Type= 6, Freq= 0, CH_0, rank 0
3883 09:27:48.873304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3884 09:27:48.873403 ==
3885 09:27:48.876813 RX Vref Scan: 0
3886 09:27:48.876910
3887 09:27:48.879828 RX Vref 0 -> 0, step: 1
3888 09:27:48.879926
3889 09:27:48.883219 RX Delay -230 -> 252, step: 16
3890 09:27:48.886491 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3891 09:27:48.889851 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3892 09:27:48.893088 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3893 09:27:48.896431 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3894 09:27:48.902965 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3895 09:27:48.906416 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3896 09:27:48.909630 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
3897 09:27:48.913374 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
3898 09:27:48.919789 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3899 09:27:48.923164 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3900 09:27:48.926383 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3901 09:27:48.929606 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3902 09:27:48.936562 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3903 09:27:48.939601 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3904 09:27:48.943105 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3905 09:27:48.946470 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3906 09:27:48.946553 ==
3907 09:27:48.949764 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 09:27:48.956443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3909 09:27:48.956525 ==
3910 09:27:48.956590 DQS Delay:
3911 09:27:48.956652 DQS0 = 0, DQS1 = 0
3912 09:27:48.960149 DQM Delay:
3913 09:27:48.960274 DQM0 = 40, DQM1 = 33
3914 09:27:48.962873 DQ Delay:
3915 09:27:48.966427 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3916 09:27:48.969611 DQ4 =49, DQ5 =25, DQ6 =57, DQ7 =57
3917 09:27:48.969696 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3918 09:27:48.976493 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3919 09:27:48.976575
3920 09:27:48.976640
3921 09:27:48.976700 ==
3922 09:27:48.979668 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 09:27:48.982926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3924 09:27:48.983021 ==
3925 09:27:48.983088
3926 09:27:48.983148
3927 09:27:48.986543 TX Vref Scan disable
3928 09:27:48.986641 == TX Byte 0 ==
3929 09:27:48.992677 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3930 09:27:48.996260 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3931 09:27:48.996335 == TX Byte 1 ==
3932 09:27:49.002673 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3933 09:27:49.005958 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3934 09:27:49.006034 ==
3935 09:27:49.009236 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 09:27:49.012662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3937 09:27:49.012738 ==
3938 09:27:49.012801
3939 09:27:49.015837
3940 09:27:49.015906 TX Vref Scan disable
3941 09:27:49.019589 == TX Byte 0 ==
3942 09:27:49.022831 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3943 09:27:49.025950 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3944 09:27:49.029339 == TX Byte 1 ==
3945 09:27:49.032874 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3946 09:27:49.035928 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3947 09:27:49.039511
3948 09:27:49.039609 [DATLAT]
3949 09:27:49.039699 Freq=600, CH0 RK0
3950 09:27:49.039789
3951 09:27:49.042503 DATLAT Default: 0x9
3952 09:27:49.042600 0, 0xFFFF, sum = 0
3953 09:27:49.046088 1, 0xFFFF, sum = 0
3954 09:27:49.046187 2, 0xFFFF, sum = 0
3955 09:27:49.049378 3, 0xFFFF, sum = 0
3956 09:27:49.052831 4, 0xFFFF, sum = 0
3957 09:27:49.052907 5, 0xFFFF, sum = 0
3958 09:27:49.055814 6, 0xFFFF, sum = 0
3959 09:27:49.055909 7, 0x0, sum = 1
3960 09:27:49.056001 8, 0x0, sum = 2
3961 09:27:49.059058 9, 0x0, sum = 3
3962 09:27:49.059157 10, 0x0, sum = 4
3963 09:27:49.062516 best_step = 8
3964 09:27:49.062592
3965 09:27:49.062655 ==
3966 09:27:49.065921 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 09:27:49.069458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3968 09:27:49.069555 ==
3969 09:27:49.072983 RX Vref Scan: 1
3970 09:27:49.073080
3971 09:27:49.073172 RX Vref 0 -> 0, step: 1
3972 09:27:49.073259
3973 09:27:49.075922 RX Delay -195 -> 252, step: 8
3974 09:27:49.076015
3975 09:27:49.079262 Set Vref, RX VrefLevel [Byte0]: 47
3976 09:27:49.082440 [Byte1]: 47
3977 09:27:49.086496
3978 09:27:49.086569 Final RX Vref Byte 0 = 47 to rank0
3979 09:27:49.089507 Final RX Vref Byte 1 = 47 to rank0
3980 09:27:49.093229 Final RX Vref Byte 0 = 47 to rank1
3981 09:27:49.096114 Final RX Vref Byte 1 = 47 to rank1==
3982 09:27:49.099443 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 09:27:49.106201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3984 09:27:49.106278 ==
3985 09:27:49.106346 DQS Delay:
3986 09:27:49.106407 DQS0 = 0, DQS1 = 0
3987 09:27:49.109366 DQM Delay:
3988 09:27:49.109464 DQM0 = 38, DQM1 = 29
3989 09:27:49.112912 DQ Delay:
3990 09:27:49.116329 DQ0 =32, DQ1 =40, DQ2 =36, DQ3 =36
3991 09:27:49.119608 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
3992 09:27:49.122968 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3993 09:27:49.125962 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3994 09:27:49.126043
3995 09:27:49.126106
3996 09:27:49.132617 [DQSOSCAuto] RK0, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3997 09:27:49.136145 CH0 RK0: MR19=808, MR18=5858
3998 09:27:49.142802 CH0_RK0: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
3999 09:27:49.142904
4000 09:27:49.146008 ----->DramcWriteLeveling(PI) begin...
4001 09:27:49.146110 ==
4002 09:27:49.149242 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 09:27:49.152400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4004 09:27:49.152503 ==
4005 09:27:49.156294 Write leveling (Byte 0): 29 => 29
4006 09:27:49.159215 Write leveling (Byte 1): 31 => 31
4007 09:27:49.162646 DramcWriteLeveling(PI) end<-----
4008 09:27:49.162747
4009 09:27:49.162837 ==
4010 09:27:49.165998 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 09:27:49.169137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4012 09:27:49.169236 ==
4013 09:27:49.172491 [Gating] SW mode calibration
4014 09:27:49.179075 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4015 09:27:49.185835 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4016 09:27:49.188895 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 09:27:49.195558 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 09:27:49.199069 0 5 8 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 0)
4019 09:27:49.202359 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4020 09:27:49.209170 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 09:27:49.212112 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 09:27:49.215763 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 09:27:49.222241 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 09:27:49.225572 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 09:27:49.228731 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 09:27:49.235312 0 6 8 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
4027 09:27:49.238898 0 6 12 | B1->B0 | 4444 4444 | 1 0 | (0 0) (0 0)
4028 09:27:49.242130 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 09:27:49.245256 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 09:27:49.251985 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 09:27:49.255136 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 09:27:49.258633 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 09:27:49.265225 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:27:49.268692 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 09:27:49.271819 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 09:27:49.278472 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 09:27:49.281737 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 09:27:49.285136 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 09:27:49.291864 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 09:27:49.294994 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 09:27:49.298588 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 09:27:49.305185 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 09:27:49.308298 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 09:27:49.311780 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:27:49.318416 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:27:49.321717 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:27:49.324888 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:27:49.331421 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:27:49.334948 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:27:49.338202 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4051 09:27:49.344925 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 09:27:49.345033 Total UI for P1: 0, mck2ui 16
4053 09:27:49.351539 best dqsien dly found for B0: ( 0, 9, 8)
4054 09:27:49.351620 Total UI for P1: 0, mck2ui 16
4055 09:27:49.358264 best dqsien dly found for B1: ( 0, 9, 10)
4056 09:27:49.361394 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4057 09:27:49.364557 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4058 09:27:49.364646
4059 09:27:49.367859 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4060 09:27:49.371322 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4061 09:27:49.374567 [Gating] SW calibration Done
4062 09:27:49.374648 ==
4063 09:27:49.377764 Dram Type= 6, Freq= 0, CH_0, rank 1
4064 09:27:49.381074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4065 09:27:49.381157 ==
4066 09:27:49.384714 RX Vref Scan: 0
4067 09:27:49.384795
4068 09:27:49.384860 RX Vref 0 -> 0, step: 1
4069 09:27:49.384921
4070 09:27:49.387699 RX Delay -230 -> 252, step: 16
4071 09:27:49.394569 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4072 09:27:49.397807 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4073 09:27:49.400916 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4074 09:27:49.404449 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4075 09:27:49.407815 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4076 09:27:49.414317 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4077 09:27:49.417854 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4078 09:27:49.420880 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4079 09:27:49.424386 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4080 09:27:49.430762 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4081 09:27:49.434296 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4082 09:27:49.437477 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4083 09:27:49.440862 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4084 09:27:49.447611 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4085 09:27:49.450706 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4086 09:27:49.454268 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4087 09:27:49.454350 ==
4088 09:27:49.457397 Dram Type= 6, Freq= 0, CH_0, rank 1
4089 09:27:49.461092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4090 09:27:49.461175 ==
4091 09:27:49.463988 DQS Delay:
4092 09:27:49.464069 DQS0 = 0, DQS1 = 0
4093 09:27:49.467277 DQM Delay:
4094 09:27:49.467358 DQM0 = 40, DQM1 = 32
4095 09:27:49.467423 DQ Delay:
4096 09:27:49.470535 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4097 09:27:49.473924 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4098 09:27:49.477371 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4099 09:27:49.480566 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4100 09:27:49.480648
4101 09:27:49.480713
4102 09:27:49.484162 ==
4103 09:27:49.487291 Dram Type= 6, Freq= 0, CH_0, rank 1
4104 09:27:49.490456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4105 09:27:49.490539 ==
4106 09:27:49.490604
4107 09:27:49.490663
4108 09:27:49.493889 TX Vref Scan disable
4109 09:27:49.493974 == TX Byte 0 ==
4110 09:27:49.500332 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4111 09:27:49.503490 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4112 09:27:49.503572 == TX Byte 1 ==
4113 09:27:49.510309 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4114 09:27:49.513599 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4115 09:27:49.513681 ==
4116 09:27:49.516919 Dram Type= 6, Freq= 0, CH_0, rank 1
4117 09:27:49.520404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4118 09:27:49.520486 ==
4119 09:27:49.520551
4120 09:27:49.520611
4121 09:27:49.523404 TX Vref Scan disable
4122 09:27:49.526929 == TX Byte 0 ==
4123 09:27:49.530066 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4124 09:27:49.533535 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4125 09:27:49.536808 == TX Byte 1 ==
4126 09:27:49.540099 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4127 09:27:49.543426 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4128 09:27:49.543506
4129 09:27:49.546755 [DATLAT]
4130 09:27:49.546836 Freq=600, CH0 RK1
4131 09:27:49.546901
4132 09:27:49.549947 DATLAT Default: 0x8
4133 09:27:49.550029 0, 0xFFFF, sum = 0
4134 09:27:49.553661 1, 0xFFFF, sum = 0
4135 09:27:49.553744 2, 0xFFFF, sum = 0
4136 09:27:49.557114 3, 0xFFFF, sum = 0
4137 09:27:49.557197 4, 0xFFFF, sum = 0
4138 09:27:49.560197 5, 0xFFFF, sum = 0
4139 09:27:49.560280 6, 0xFFFF, sum = 0
4140 09:27:49.563372 7, 0x0, sum = 1
4141 09:27:49.563454 8, 0x0, sum = 2
4142 09:27:49.566725 9, 0x0, sum = 3
4143 09:27:49.566808 10, 0x0, sum = 4
4144 09:27:49.569825 best_step = 8
4145 09:27:49.569906
4146 09:27:49.569970 ==
4147 09:27:49.573634 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 09:27:49.576815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4149 09:27:49.576897 ==
4150 09:27:49.579784 RX Vref Scan: 0
4151 09:27:49.579866
4152 09:27:49.579931 RX Vref 0 -> 0, step: 1
4153 09:27:49.579993
4154 09:27:49.583085 RX Delay -195 -> 252, step: 8
4155 09:27:49.590001 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4156 09:27:49.593341 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4157 09:27:49.597013 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4158 09:27:49.599870 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4159 09:27:49.606599 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4160 09:27:49.609734 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4161 09:27:49.613092 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4162 09:27:49.616417 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4163 09:27:49.622961 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4164 09:27:49.626601 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4165 09:27:49.629750 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4166 09:27:49.632852 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4167 09:27:49.636347 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4168 09:27:49.643412 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4169 09:27:49.646181 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4170 09:27:49.649607 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4171 09:27:49.649689 ==
4172 09:27:49.652826 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 09:27:49.659494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4174 09:27:49.659576 ==
4175 09:27:49.659641 DQS Delay:
4176 09:27:49.659701 DQS0 = 0, DQS1 = 0
4177 09:27:49.662849 DQM Delay:
4178 09:27:49.662931 DQM0 = 41, DQM1 = 32
4179 09:27:49.666284 DQ Delay:
4180 09:27:49.669413 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4181 09:27:49.672721 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4182 09:27:49.675873 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4183 09:27:49.679389 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4184 09:27:49.679472
4185 09:27:49.679537
4186 09:27:49.685952 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4187 09:27:49.689149 CH0 RK1: MR19=808, MR18=6B6B
4188 09:27:49.695784 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4189 09:27:49.699103 [RxdqsGatingPostProcess] freq 600
4190 09:27:49.702497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4191 09:27:49.705700 Pre-setting of DQS Precalculation
4192 09:27:49.712726 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4193 09:27:49.712807 ==
4194 09:27:49.715513 Dram Type= 6, Freq= 0, CH_1, rank 0
4195 09:27:49.719016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4196 09:27:49.719089 ==
4197 09:27:49.725317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4198 09:27:49.732273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4199 09:27:49.735518 [CA 0] Center 35 (5~66) winsize 62
4200 09:27:49.738858 [CA 1] Center 35 (5~66) winsize 62
4201 09:27:49.741971 [CA 2] Center 33 (3~64) winsize 62
4202 09:27:49.745282 [CA 3] Center 33 (3~64) winsize 62
4203 09:27:49.748593 [CA 4] Center 33 (2~64) winsize 63
4204 09:27:49.751927 [CA 5] Center 33 (2~64) winsize 63
4205 09:27:49.752034
4206 09:27:49.755301 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4207 09:27:49.755377
4208 09:27:49.758608 [CATrainingPosCal] consider 1 rank data
4209 09:27:49.762078 u2DelayCellTimex100 = 270/100 ps
4210 09:27:49.765718 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4211 09:27:49.768638 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4212 09:27:49.771991 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4213 09:27:49.775414 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4214 09:27:49.778735 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4215 09:27:49.781873 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4216 09:27:49.781943
4217 09:27:49.785440 CA PerBit enable=1, Macro0, CA PI delay=33
4218 09:27:49.788614
4219 09:27:49.788710 [CBTSetCACLKResult] CA Dly = 33
4220 09:27:49.791836 CS Dly: 4 (0~35)
4221 09:27:49.791911 ==
4222 09:27:49.795151 Dram Type= 6, Freq= 0, CH_1, rank 1
4223 09:27:49.798478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4224 09:27:49.798561 ==
4225 09:27:49.805309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4226 09:27:49.811761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4227 09:27:49.815004 [CA 0] Center 35 (5~66) winsize 62
4228 09:27:49.818189 [CA 1] Center 34 (4~65) winsize 62
4229 09:27:49.821579 [CA 2] Center 33 (3~64) winsize 62
4230 09:27:49.825077 [CA 3] Center 33 (3~64) winsize 62
4231 09:27:49.828212 [CA 4] Center 32 (2~63) winsize 62
4232 09:27:49.831432 [CA 5] Center 33 (2~64) winsize 63
4233 09:27:49.831543
4234 09:27:49.834947 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4235 09:27:49.835029
4236 09:27:49.838296 [CATrainingPosCal] consider 2 rank data
4237 09:27:49.841495 u2DelayCellTimex100 = 270/100 ps
4238 09:27:49.845175 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4239 09:27:49.848147 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4240 09:27:49.851316 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4241 09:27:49.854737 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4242 09:27:49.858027 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4243 09:27:49.861640 CA5 delay=33 (2~64),Diff = 1 PI (9 cell)
4244 09:27:49.864687
4245 09:27:49.867975 CA PerBit enable=1, Macro0, CA PI delay=32
4246 09:27:49.868056
4247 09:27:49.871594 [CBTSetCACLKResult] CA Dly = 32
4248 09:27:49.871676 CS Dly: 4 (0~36)
4249 09:27:49.871741
4250 09:27:49.874593 ----->DramcWriteLeveling(PI) begin...
4251 09:27:49.874676 ==
4252 09:27:49.878004 Dram Type= 6, Freq= 0, CH_1, rank 0
4253 09:27:49.884281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4254 09:27:49.884363 ==
4255 09:27:49.887810 Write leveling (Byte 0): 27 => 27
4256 09:27:49.887892 Write leveling (Byte 1): 27 => 27
4257 09:27:49.890876 DramcWriteLeveling(PI) end<-----
4258 09:27:49.890958
4259 09:27:49.891022 ==
4260 09:27:49.894246 Dram Type= 6, Freq= 0, CH_1, rank 0
4261 09:27:49.900881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4262 09:27:49.900963 ==
4263 09:27:49.904410 [Gating] SW mode calibration
4264 09:27:49.911172 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4265 09:27:49.914233 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4266 09:27:49.921071 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4267 09:27:49.923987 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4268 09:27:49.927737 0 5 8 | B1->B0 | 2f2f 2929 | 1 1 | (1 1) (1 0)
4269 09:27:49.934253 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 09:27:49.937501 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 09:27:49.940652 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 09:27:49.947406 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 09:27:49.950649 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 09:27:49.953969 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 09:27:49.957364 0 6 4 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
4276 09:27:49.963976 0 6 8 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
4277 09:27:49.967269 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 09:27:49.970442 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 09:27:49.977238 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 09:27:49.980477 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 09:27:49.983785 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 09:27:49.990220 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 09:27:49.993679 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4284 09:27:49.997248 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 09:27:50.003689 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 09:27:50.006905 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 09:27:50.010288 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 09:27:50.017004 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 09:27:50.020265 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 09:27:50.023605 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 09:27:50.030022 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 09:27:50.033561 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 09:27:50.036737 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 09:27:50.043495 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 09:27:50.046874 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 09:27:50.050119 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 09:27:50.056849 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 09:27:50.060063 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 09:27:50.063445 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4300 09:27:50.066952 Total UI for P1: 0, mck2ui 16
4301 09:27:50.069899 best dqsien dly found for B0: ( 0, 9, 2)
4302 09:27:50.076934 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4303 09:27:50.079954 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4304 09:27:50.083183 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 09:27:50.086466 Total UI for P1: 0, mck2ui 16
4306 09:27:50.089711 best dqsien dly found for B1: ( 0, 9, 10)
4307 09:27:50.093387 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4308 09:27:50.096706 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4309 09:27:50.096788
4310 09:27:50.100121 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4311 09:27:50.106556 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4312 09:27:50.106639 [Gating] SW calibration Done
4313 09:27:50.109911 ==
4314 09:27:50.109993 Dram Type= 6, Freq= 0, CH_1, rank 0
4315 09:27:50.116458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4316 09:27:50.116545 ==
4317 09:27:50.116610 RX Vref Scan: 0
4318 09:27:50.116670
4319 09:27:50.119810 RX Vref 0 -> 0, step: 1
4320 09:27:50.119891
4321 09:27:50.122996 RX Delay -230 -> 252, step: 16
4322 09:27:50.126348 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4323 09:27:50.129935 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4324 09:27:50.136416 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4325 09:27:50.139729 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4326 09:27:50.143608 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4327 09:27:50.146513 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4328 09:27:50.149725 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4329 09:27:50.156358 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4330 09:27:50.159557 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4331 09:27:50.162985 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4332 09:27:50.166469 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4333 09:27:50.172975 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4334 09:27:50.176051 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4335 09:27:50.179559 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4336 09:27:50.182714 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4337 09:27:50.189397 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4338 09:27:50.189479 ==
4339 09:27:50.192585 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 09:27:50.196039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4341 09:27:50.196121 ==
4342 09:27:50.196212 DQS Delay:
4343 09:27:50.199197 DQS0 = 0, DQS1 = 0
4344 09:27:50.199278 DQM Delay:
4345 09:27:50.202491 DQM0 = 38, DQM1 = 30
4346 09:27:50.202572 DQ Delay:
4347 09:27:50.206090 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4348 09:27:50.209719 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4349 09:27:50.212485 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4350 09:27:50.216072 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4351 09:27:50.216153
4352 09:27:50.216255
4353 09:27:50.216316 ==
4354 09:27:50.219057 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 09:27:50.222629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4356 09:27:50.222710 ==
4357 09:27:50.226267
4358 09:27:50.226348
4359 09:27:50.226411 TX Vref Scan disable
4360 09:27:50.229075 == TX Byte 0 ==
4361 09:27:50.232865 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4362 09:27:50.235880 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4363 09:27:50.239140 == TX Byte 1 ==
4364 09:27:50.242440 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4365 09:27:50.245672 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4366 09:27:50.245753 ==
4367 09:27:50.249412 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 09:27:50.255812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4369 09:27:50.255898 ==
4370 09:27:50.255962
4371 09:27:50.256022
4372 09:27:50.256080 TX Vref Scan disable
4373 09:27:50.260193 == TX Byte 0 ==
4374 09:27:50.263699 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4375 09:27:50.270226 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4376 09:27:50.270307 == TX Byte 1 ==
4377 09:27:50.273691 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4378 09:27:50.280122 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4379 09:27:50.280240
4380 09:27:50.280304 [DATLAT]
4381 09:27:50.280364 Freq=600, CH1 RK0
4382 09:27:50.280424
4383 09:27:50.283446 DATLAT Default: 0x9
4384 09:27:50.283527 0, 0xFFFF, sum = 0
4385 09:27:50.286687 1, 0xFFFF, sum = 0
4386 09:27:50.286770 2, 0xFFFF, sum = 0
4387 09:27:50.289948 3, 0xFFFF, sum = 0
4388 09:27:50.293504 4, 0xFFFF, sum = 0
4389 09:27:50.293588 5, 0xFFFF, sum = 0
4390 09:27:50.296860 6, 0xFFFF, sum = 0
4391 09:27:50.296942 7, 0x0, sum = 1
4392 09:27:50.297008 8, 0x0, sum = 2
4393 09:27:50.300281 9, 0x0, sum = 3
4394 09:27:50.300364 10, 0x0, sum = 4
4395 09:27:50.303238 best_step = 8
4396 09:27:50.303318
4397 09:27:50.303382 ==
4398 09:27:50.306891 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 09:27:50.310031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4400 09:27:50.310112 ==
4401 09:27:50.313655 RX Vref Scan: 1
4402 09:27:50.313735
4403 09:27:50.313799 RX Vref 0 -> 0, step: 1
4404 09:27:50.313859
4405 09:27:50.316749 RX Delay -195 -> 252, step: 8
4406 09:27:50.316830
4407 09:27:50.319977 Set Vref, RX VrefLevel [Byte0]: 54
4408 09:27:50.323320 [Byte1]: 48
4409 09:27:50.327377
4410 09:27:50.327457 Final RX Vref Byte 0 = 54 to rank0
4411 09:27:50.330582 Final RX Vref Byte 1 = 48 to rank0
4412 09:27:50.333843 Final RX Vref Byte 0 = 54 to rank1
4413 09:27:50.337145 Final RX Vref Byte 1 = 48 to rank1==
4414 09:27:50.340928 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 09:27:50.347024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4416 09:27:50.347105 ==
4417 09:27:50.347169 DQS Delay:
4418 09:27:50.347228 DQS0 = 0, DQS1 = 0
4419 09:27:50.350642 DQM Delay:
4420 09:27:50.350723 DQM0 = 38, DQM1 = 31
4421 09:27:50.353874 DQ Delay:
4422 09:27:50.357318 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4423 09:27:50.360935 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4424 09:27:50.364191 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4425 09:27:50.367124 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4426 09:27:50.367205
4427 09:27:50.367269
4428 09:27:50.373951 [DQSOSCAuto] RK0, (LSB)MR18= 0x7878, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4429 09:27:50.377163 CH1 RK0: MR19=808, MR18=7878
4430 09:27:50.383634 CH1_RK0: MR19=0x808, MR18=0x7878, DQSOSC=387, MR23=63, INC=175, DEC=116
4431 09:27:50.383715
4432 09:27:50.386958 ----->DramcWriteLeveling(PI) begin...
4433 09:27:50.387040 ==
4434 09:27:50.390124 Dram Type= 6, Freq= 0, CH_1, rank 1
4435 09:27:50.393651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4436 09:27:50.393733 ==
4437 09:27:50.396845 Write leveling (Byte 0): 27 => 27
4438 09:27:50.400418 Write leveling (Byte 1): 27 => 27
4439 09:27:50.403706 DramcWriteLeveling(PI) end<-----
4440 09:27:50.403787
4441 09:27:50.403850 ==
4442 09:27:50.407147 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 09:27:50.410280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4444 09:27:50.410362 ==
4445 09:27:50.413549 [Gating] SW mode calibration
4446 09:27:50.420109 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 09:27:50.426737 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4448 09:27:50.430005 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 09:27:50.436735 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4450 09:27:50.440449 0 5 8 | B1->B0 | 3030 2929 | 0 1 | (0 1) (1 0)
4451 09:27:50.443475 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 09:27:50.446843 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 09:27:50.453285 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 09:27:50.457053 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 09:27:50.460362 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 09:27:50.466753 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 09:27:50.470057 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4458 09:27:50.473246 0 6 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
4459 09:27:50.480139 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 09:27:50.483229 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 09:27:50.486819 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 09:27:50.493085 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 09:27:50.497036 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 09:27:50.499937 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 09:27:50.506354 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4466 09:27:50.509897 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4467 09:27:50.513069 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 09:27:50.520082 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 09:27:50.523202 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 09:27:50.526236 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 09:27:50.532972 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 09:27:50.536319 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 09:27:50.539507 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 09:27:50.546529 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 09:27:50.549441 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 09:27:50.553059 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 09:27:50.559214 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:27:50.562663 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:27:50.566183 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:27:50.572889 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:27:50.575971 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4482 09:27:50.579203 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 09:27:50.582875 Total UI for P1: 0, mck2ui 16
4484 09:27:50.585914 best dqsien dly found for B0: ( 0, 9, 4)
4485 09:27:50.589363 Total UI for P1: 0, mck2ui 16
4486 09:27:50.592834 best dqsien dly found for B1: ( 0, 9, 6)
4487 09:27:50.596110 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4488 09:27:50.599489 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4489 09:27:50.599563
4490 09:27:50.602577 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4491 09:27:50.609232 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4492 09:27:50.609332 [Gating] SW calibration Done
4493 09:27:50.609423 ==
4494 09:27:50.612534 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 09:27:50.619286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4496 09:27:50.619397 ==
4497 09:27:50.619489 RX Vref Scan: 0
4498 09:27:50.619577
4499 09:27:50.622491 RX Vref 0 -> 0, step: 1
4500 09:27:50.622585
4501 09:27:50.626201 RX Delay -230 -> 252, step: 16
4502 09:27:50.629377 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4503 09:27:50.632743 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4504 09:27:50.635751 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4505 09:27:50.642255 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4506 09:27:50.645832 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4507 09:27:50.649003 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4508 09:27:50.652366 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4509 09:27:50.658957 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4510 09:27:50.662138 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4511 09:27:50.665583 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4512 09:27:50.668937 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4513 09:27:50.675364 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4514 09:27:50.678764 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4515 09:27:50.682308 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4516 09:27:50.685621 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4517 09:27:50.692091 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4518 09:27:50.692182 ==
4519 09:27:50.695380 Dram Type= 6, Freq= 0, CH_1, rank 1
4520 09:27:50.698782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4521 09:27:50.698868 ==
4522 09:27:50.698955 DQS Delay:
4523 09:27:50.702161 DQS0 = 0, DQS1 = 0
4524 09:27:50.702246 DQM Delay:
4525 09:27:50.705140 DQM0 = 39, DQM1 = 35
4526 09:27:50.705221 DQ Delay:
4527 09:27:50.708572 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4528 09:27:50.712209 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4529 09:27:50.715158 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4530 09:27:50.718670 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4531 09:27:50.718755
4532 09:27:50.718841
4533 09:27:50.718922 ==
4534 09:27:50.721882 Dram Type= 6, Freq= 0, CH_1, rank 1
4535 09:27:50.725302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4536 09:27:50.725387 ==
4537 09:27:50.725473
4538 09:27:50.725554
4539 09:27:50.728809 TX Vref Scan disable
4540 09:27:50.732089 == TX Byte 0 ==
4541 09:27:50.735027 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4542 09:27:50.738627 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4543 09:27:50.742012 == TX Byte 1 ==
4544 09:27:50.745437 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4545 09:27:50.748646 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4546 09:27:50.748730 ==
4547 09:27:50.751829 Dram Type= 6, Freq= 0, CH_1, rank 1
4548 09:27:50.758440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4549 09:27:50.758548 ==
4550 09:27:50.758640
4551 09:27:50.758726
4552 09:27:50.758821 TX Vref Scan disable
4553 09:27:50.762977 == TX Byte 0 ==
4554 09:27:50.766001 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4555 09:27:50.772669 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4556 09:27:50.772741 == TX Byte 1 ==
4557 09:27:50.775992 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4558 09:27:50.782699 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4559 09:27:50.782784
4560 09:27:50.782847 [DATLAT]
4561 09:27:50.782906 Freq=600, CH1 RK1
4562 09:27:50.782977
4563 09:27:50.785762 DATLAT Default: 0x8
4564 09:27:50.785833 0, 0xFFFF, sum = 0
4565 09:27:50.789379 1, 0xFFFF, sum = 0
4566 09:27:50.792465 2, 0xFFFF, sum = 0
4567 09:27:50.792564 3, 0xFFFF, sum = 0
4568 09:27:50.795758 4, 0xFFFF, sum = 0
4569 09:27:50.795856 5, 0xFFFF, sum = 0
4570 09:27:50.799335 6, 0xFFFF, sum = 0
4571 09:27:50.799433 7, 0x0, sum = 1
4572 09:27:50.799522 8, 0x0, sum = 2
4573 09:27:50.802635 9, 0x0, sum = 3
4574 09:27:50.802734 10, 0x0, sum = 4
4575 09:27:50.806239 best_step = 8
4576 09:27:50.806312
4577 09:27:50.806371 ==
4578 09:27:50.809204 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 09:27:50.812445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4580 09:27:50.812518 ==
4581 09:27:50.815838 RX Vref Scan: 0
4582 09:27:50.815935
4583 09:27:50.816035 RX Vref 0 -> 0, step: 1
4584 09:27:50.816122
4585 09:27:50.818858 RX Delay -195 -> 252, step: 8
4586 09:27:50.826248 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4587 09:27:50.829600 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4588 09:27:50.833196 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4589 09:27:50.836209 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4590 09:27:50.842774 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4591 09:27:50.846144 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4592 09:27:50.849627 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4593 09:27:50.852617 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4594 09:27:50.859249 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4595 09:27:50.862718 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4596 09:27:50.866027 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4597 09:27:50.869292 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4598 09:27:50.872463 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4599 09:27:50.879523 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4600 09:27:50.882677 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4601 09:27:50.885833 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4602 09:27:50.885907 ==
4603 09:27:50.889619 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 09:27:50.896068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4605 09:27:50.896170 ==
4606 09:27:50.896250 DQS Delay:
4607 09:27:50.896310 DQS0 = 0, DQS1 = 0
4608 09:27:50.899395 DQM Delay:
4609 09:27:50.899467 DQM0 = 37, DQM1 = 29
4610 09:27:50.902800 DQ Delay:
4611 09:27:50.906146 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4612 09:27:50.906249 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4613 09:27:50.909128 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4614 09:27:50.912703 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4615 09:27:50.915710
4616 09:27:50.915783
4617 09:27:50.922583 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4618 09:27:50.926009 CH1 RK1: MR19=808, MR18=6464
4619 09:27:50.932518 CH1_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4620 09:27:50.935710 [RxdqsGatingPostProcess] freq 600
4621 09:27:50.939427 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4622 09:27:50.942324 Pre-setting of DQS Precalculation
4623 09:27:50.949134 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4624 09:27:50.955544 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4625 09:27:50.962480 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4626 09:27:50.962579
4627 09:27:50.962670
4628 09:27:50.965561 [Calibration Summary] 1200 Mbps
4629 09:27:50.965660 CH 0, Rank 0
4630 09:27:50.969285 SW Impedance : PASS
4631 09:27:50.972410 DUTY Scan : NO K
4632 09:27:50.972512 ZQ Calibration : PASS
4633 09:27:50.975684 Jitter Meter : NO K
4634 09:27:50.979234 CBT Training : PASS
4635 09:27:50.979310 Write leveling : PASS
4636 09:27:50.982319 RX DQS gating : PASS
4637 09:27:50.982421 RX DQ/DQS(RDDQC) : PASS
4638 09:27:50.985711 TX DQ/DQS : PASS
4639 09:27:50.988974 RX DATLAT : PASS
4640 09:27:50.989049 RX DQ/DQS(Engine): PASS
4641 09:27:50.992209 TX OE : NO K
4642 09:27:50.992301 All Pass.
4643 09:27:50.992364
4644 09:27:50.995656 CH 0, Rank 1
4645 09:27:50.995731 SW Impedance : PASS
4646 09:27:50.998822 DUTY Scan : NO K
4647 09:27:51.002175 ZQ Calibration : PASS
4648 09:27:51.002278 Jitter Meter : NO K
4649 09:27:51.005956 CBT Training : PASS
4650 09:27:51.008811 Write leveling : PASS
4651 09:27:51.008907 RX DQS gating : PASS
4652 09:27:51.012061 RX DQ/DQS(RDDQC) : PASS
4653 09:27:51.015418 TX DQ/DQS : PASS
4654 09:27:51.015493 RX DATLAT : PASS
4655 09:27:51.018778 RX DQ/DQS(Engine): PASS
4656 09:27:51.022043 TX OE : NO K
4657 09:27:51.022118 All Pass.
4658 09:27:51.022187
4659 09:27:51.022246 CH 1, Rank 0
4660 09:27:51.025345 SW Impedance : PASS
4661 09:27:51.028979 DUTY Scan : NO K
4662 09:27:51.029082 ZQ Calibration : PASS
4663 09:27:51.031968 Jitter Meter : NO K
4664 09:27:51.032070 CBT Training : PASS
4665 09:27:51.035272 Write leveling : PASS
4666 09:27:51.039091 RX DQS gating : PASS
4667 09:27:51.039197 RX DQ/DQS(RDDQC) : PASS
4668 09:27:51.041951 TX DQ/DQS : PASS
4669 09:27:51.045079 RX DATLAT : PASS
4670 09:27:51.045152 RX DQ/DQS(Engine): PASS
4671 09:27:51.048411 TX OE : NO K
4672 09:27:51.048485 All Pass.
4673 09:27:51.048547
4674 09:27:51.052139 CH 1, Rank 1
4675 09:27:51.052276 SW Impedance : PASS
4676 09:27:51.055169 DUTY Scan : NO K
4677 09:27:51.058730 ZQ Calibration : PASS
4678 09:27:51.058838 Jitter Meter : NO K
4679 09:27:51.061713 CBT Training : PASS
4680 09:27:51.065223 Write leveling : PASS
4681 09:27:51.065325 RX DQS gating : PASS
4682 09:27:51.068392 RX DQ/DQS(RDDQC) : PASS
4683 09:27:51.071648 TX DQ/DQS : PASS
4684 09:27:51.071785 RX DATLAT : PASS
4685 09:27:51.075176 RX DQ/DQS(Engine): PASS
4686 09:27:51.078399 TX OE : NO K
4687 09:27:51.078502 All Pass.
4688 09:27:51.078596
4689 09:27:51.078684 DramC Write-DBI off
4690 09:27:51.081891 PER_BANK_REFRESH: Hybrid Mode
4691 09:27:51.085261 TX_TRACKING: ON
4692 09:27:51.091688 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4693 09:27:51.095171 [FAST_K] Save calibration result to emmc
4694 09:27:51.101966 dramc_set_vcore_voltage set vcore to 662500
4695 09:27:51.102067 Read voltage for 933, 3
4696 09:27:51.104901 Vio18 = 0
4697 09:27:51.104971 Vcore = 662500
4698 09:27:51.105032 Vdram = 0
4699 09:27:51.105093 Vddq = 0
4700 09:27:51.108676 Vmddr = 0
4701 09:27:51.111668 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4702 09:27:51.118071 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4703 09:27:51.121638 MEM_TYPE=3, freq_sel=17
4704 09:27:51.124855 sv_algorithm_assistance_LP4_1600
4705 09:27:51.128224 ============ PULL DRAM RESETB DOWN ============
4706 09:27:51.131483 ========== PULL DRAM RESETB DOWN end =========
4707 09:27:51.134719 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4708 09:27:51.138105 ===================================
4709 09:27:51.141262 LPDDR4 DRAM CONFIGURATION
4710 09:27:51.144735 ===================================
4711 09:27:51.147881 EX_ROW_EN[0] = 0x0
4712 09:27:51.147965 EX_ROW_EN[1] = 0x0
4713 09:27:51.151366 LP4Y_EN = 0x0
4714 09:27:51.151451 WORK_FSP = 0x0
4715 09:27:51.154447 WL = 0x3
4716 09:27:51.154531 RL = 0x3
4717 09:27:51.157903 BL = 0x2
4718 09:27:51.157987 RPST = 0x0
4719 09:27:51.161171 RD_PRE = 0x0
4720 09:27:51.161255 WR_PRE = 0x1
4721 09:27:51.164433 WR_PST = 0x0
4722 09:27:51.164521 DBI_WR = 0x0
4723 09:27:51.167979 DBI_RD = 0x0
4724 09:27:51.171419 OTF = 0x1
4725 09:27:51.174530 ===================================
4726 09:27:51.177958 ===================================
4727 09:27:51.178043 ANA top config
4728 09:27:51.180990 ===================================
4729 09:27:51.184486 DLL_ASYNC_EN = 0
4730 09:27:51.187846 ALL_SLAVE_EN = 1
4731 09:27:51.187930 NEW_RANK_MODE = 1
4732 09:27:51.191464 DLL_IDLE_MODE = 1
4733 09:27:51.194430 LP45_APHY_COMB_EN = 1
4734 09:27:51.197541 TX_ODT_DIS = 1
4735 09:27:51.197626 NEW_8X_MODE = 1
4736 09:27:51.200922 ===================================
4737 09:27:51.204150 ===================================
4738 09:27:51.207514 data_rate = 1866
4739 09:27:51.211138 CKR = 1
4740 09:27:51.214108 DQ_P2S_RATIO = 8
4741 09:27:51.217874 ===================================
4742 09:27:51.220862 CA_P2S_RATIO = 8
4743 09:27:51.224005 DQ_CA_OPEN = 0
4744 09:27:51.224103 DQ_SEMI_OPEN = 0
4745 09:27:51.227588 CA_SEMI_OPEN = 0
4746 09:27:51.230927 CA_FULL_RATE = 0
4747 09:27:51.234246 DQ_CKDIV4_EN = 1
4748 09:27:51.237399 CA_CKDIV4_EN = 1
4749 09:27:51.240730 CA_PREDIV_EN = 0
4750 09:27:51.240806 PH8_DLY = 0
4751 09:27:51.243905 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4752 09:27:51.247219 DQ_AAMCK_DIV = 4
4753 09:27:51.250651 CA_AAMCK_DIV = 4
4754 09:27:51.253952 CA_ADMCK_DIV = 4
4755 09:27:51.257675 DQ_TRACK_CA_EN = 0
4756 09:27:51.257748 CA_PICK = 933
4757 09:27:51.260710 CA_MCKIO = 933
4758 09:27:51.263898 MCKIO_SEMI = 0
4759 09:27:51.267441 PLL_FREQ = 3732
4760 09:27:51.270534 DQ_UI_PI_RATIO = 32
4761 09:27:51.273875 CA_UI_PI_RATIO = 0
4762 09:27:51.277093 ===================================
4763 09:27:51.280363 ===================================
4764 09:27:51.280437 memory_type:LPDDR4
4765 09:27:51.284021 GP_NUM : 10
4766 09:27:51.287016 SRAM_EN : 1
4767 09:27:51.287149 MD32_EN : 0
4768 09:27:51.290487 ===================================
4769 09:27:51.293641 [ANA_INIT] >>>>>>>>>>>>>>
4770 09:27:51.297252 <<<<<< [CONFIGURE PHASE]: ANA_TX
4771 09:27:51.300621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4772 09:27:51.303647 ===================================
4773 09:27:51.307225 data_rate = 1866,PCW = 0X8f00
4774 09:27:51.310531 ===================================
4775 09:27:51.313759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4776 09:27:51.317064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4777 09:27:51.323588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4778 09:27:51.326981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4779 09:27:51.333458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4780 09:27:51.336917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4781 09:27:51.337020 [ANA_INIT] flow start
4782 09:27:51.340291 [ANA_INIT] PLL >>>>>>>>
4783 09:27:51.343511 [ANA_INIT] PLL <<<<<<<<
4784 09:27:51.343586 [ANA_INIT] MIDPI >>>>>>>>
4785 09:27:51.346872 [ANA_INIT] MIDPI <<<<<<<<
4786 09:27:51.350092 [ANA_INIT] DLL >>>>>>>>
4787 09:27:51.350189 [ANA_INIT] flow end
4788 09:27:51.353495 ============ LP4 DIFF to SE enter ============
4789 09:27:51.360019 ============ LP4 DIFF to SE exit ============
4790 09:27:51.360121 [ANA_INIT] <<<<<<<<<<<<<
4791 09:27:51.363417 [Flow] Enable top DCM control >>>>>
4792 09:27:51.366561 [Flow] Enable top DCM control <<<<<
4793 09:27:51.370367 Enable DLL master slave shuffle
4794 09:27:51.376872 ==============================================================
4795 09:27:51.380081 Gating Mode config
4796 09:27:51.383157 ==============================================================
4797 09:27:51.386572 Config description:
4798 09:27:51.396630 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4799 09:27:51.403307 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4800 09:27:51.406281 SELPH_MODE 0: By rank 1: By Phase
4801 09:27:51.412913 ==============================================================
4802 09:27:51.416325 GAT_TRACK_EN = 1
4803 09:27:51.419705 RX_GATING_MODE = 2
4804 09:27:51.422909 RX_GATING_TRACK_MODE = 2
4805 09:27:51.423008 SELPH_MODE = 1
4806 09:27:51.426209 PICG_EARLY_EN = 1
4807 09:27:51.429668 VALID_LAT_VALUE = 1
4808 09:27:51.436411 ==============================================================
4809 09:27:51.439981 Enter into Gating configuration >>>>
4810 09:27:51.442765 Exit from Gating configuration <<<<
4811 09:27:51.446060 Enter into DVFS_PRE_config >>>>>
4812 09:27:51.456420 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4813 09:27:51.459482 Exit from DVFS_PRE_config <<<<<
4814 09:27:51.463113 Enter into PICG configuration >>>>
4815 09:27:51.466265 Exit from PICG configuration <<<<
4816 09:27:51.469493 [RX_INPUT] configuration >>>>>
4817 09:27:51.472812 [RX_INPUT] configuration <<<<<
4818 09:27:51.476284 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4819 09:27:51.482855 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4820 09:27:51.489627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4821 09:27:51.496134 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4822 09:27:51.499269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4823 09:27:51.505990 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4824 09:27:51.509533 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4825 09:27:51.516061 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4826 09:27:51.519514 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4827 09:27:51.522484 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4828 09:27:51.525817 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4829 09:27:51.532652 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4830 09:27:51.535714 ===================================
4831 09:27:51.539023 LPDDR4 DRAM CONFIGURATION
4832 09:27:51.542376 ===================================
4833 09:27:51.542461 EX_ROW_EN[0] = 0x0
4834 09:27:51.545944 EX_ROW_EN[1] = 0x0
4835 09:27:51.546029 LP4Y_EN = 0x0
4836 09:27:51.549105 WORK_FSP = 0x0
4837 09:27:51.549189 WL = 0x3
4838 09:27:51.552345 RL = 0x3
4839 09:27:51.552429 BL = 0x2
4840 09:27:51.555503 RPST = 0x0
4841 09:27:51.555603 RD_PRE = 0x0
4842 09:27:51.558951 WR_PRE = 0x1
4843 09:27:51.559035 WR_PST = 0x0
4844 09:27:51.562361 DBI_WR = 0x0
4845 09:27:51.562445 DBI_RD = 0x0
4846 09:27:51.565349 OTF = 0x1
4847 09:27:51.569043 ===================================
4848 09:27:51.572256 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4849 09:27:51.575604 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4850 09:27:51.582331 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4851 09:27:51.585807 ===================================
4852 09:27:51.585893 LPDDR4 DRAM CONFIGURATION
4853 09:27:51.588675 ===================================
4854 09:27:51.592201 EX_ROW_EN[0] = 0x10
4855 09:27:51.595553 EX_ROW_EN[1] = 0x0
4856 09:27:51.595637 LP4Y_EN = 0x0
4857 09:27:51.598520 WORK_FSP = 0x0
4858 09:27:51.598605 WL = 0x3
4859 09:27:51.601946 RL = 0x3
4860 09:27:51.602030 BL = 0x2
4861 09:27:51.605174 RPST = 0x0
4862 09:27:51.605259 RD_PRE = 0x0
4863 09:27:51.608601 WR_PRE = 0x1
4864 09:27:51.608686 WR_PST = 0x0
4865 09:27:51.611999 DBI_WR = 0x0
4866 09:27:51.612083 DBI_RD = 0x0
4867 09:27:51.615343 OTF = 0x1
4868 09:27:51.618596 ===================================
4869 09:27:51.625011 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4870 09:27:51.628540 nWR fixed to 30
4871 09:27:51.631705 [ModeRegInit_LP4] CH0 RK0
4872 09:27:51.631789 [ModeRegInit_LP4] CH0 RK1
4873 09:27:51.635196 [ModeRegInit_LP4] CH1 RK0
4874 09:27:51.638185 [ModeRegInit_LP4] CH1 RK1
4875 09:27:51.638270 match AC timing 8
4876 09:27:51.645124 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4877 09:27:51.648312 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4878 09:27:51.651515 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4879 09:27:51.658185 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4880 09:27:51.661418 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4881 09:27:51.661504 ==
4882 09:27:51.664798 Dram Type= 6, Freq= 0, CH_0, rank 0
4883 09:27:51.668062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4884 09:27:51.668181 ==
4885 09:27:51.674728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4886 09:27:51.681231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4887 09:27:51.684397 [CA 0] Center 38 (8~69) winsize 62
4888 09:27:51.688031 [CA 1] Center 38 (8~69) winsize 62
4889 09:27:51.691254 [CA 2] Center 36 (6~67) winsize 62
4890 09:27:51.694502 [CA 3] Center 36 (6~66) winsize 61
4891 09:27:51.697720 [CA 4] Center 34 (4~65) winsize 62
4892 09:27:51.701064 [CA 5] Center 34 (4~65) winsize 62
4893 09:27:51.701150
4894 09:27:51.704778 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4895 09:27:51.704864
4896 09:27:51.707638 [CATrainingPosCal] consider 1 rank data
4897 09:27:51.710767 u2DelayCellTimex100 = 270/100 ps
4898 09:27:51.714530 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4899 09:27:51.717822 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4900 09:27:51.720886 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4901 09:27:51.724135 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4902 09:27:51.731066 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4903 09:27:51.734396 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4904 09:27:51.734481
4905 09:27:51.737701 CA PerBit enable=1, Macro0, CA PI delay=34
4906 09:27:51.737786
4907 09:27:51.740776 [CBTSetCACLKResult] CA Dly = 34
4908 09:27:51.740861 CS Dly: 7 (0~38)
4909 09:27:51.740947 ==
4910 09:27:51.744162 Dram Type= 6, Freq= 0, CH_0, rank 1
4911 09:27:51.747610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4912 09:27:51.750987 ==
4913 09:27:51.754096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4914 09:27:51.760797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4915 09:27:51.764491 [CA 0] Center 38 (8~69) winsize 62
4916 09:27:51.767422 [CA 1] Center 38 (8~69) winsize 62
4917 09:27:51.770677 [CA 2] Center 36 (5~67) winsize 63
4918 09:27:51.774068 [CA 3] Center 35 (5~66) winsize 62
4919 09:27:51.777369 [CA 4] Center 34 (4~65) winsize 62
4920 09:27:51.780999 [CA 5] Center 34 (4~65) winsize 62
4921 09:27:51.781115
4922 09:27:51.784131 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4923 09:27:51.784254
4924 09:27:51.787479 [CATrainingPosCal] consider 2 rank data
4925 09:27:51.790913 u2DelayCellTimex100 = 270/100 ps
4926 09:27:51.794362 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4927 09:27:51.797499 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4928 09:27:51.800562 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4929 09:27:51.807124 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4930 09:27:51.810516 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4931 09:27:51.813699 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4932 09:27:51.813784
4933 09:27:51.817143 CA PerBit enable=1, Macro0, CA PI delay=34
4934 09:27:51.817228
4935 09:27:51.820611 [CBTSetCACLKResult] CA Dly = 34
4936 09:27:51.820696 CS Dly: 7 (0~39)
4937 09:27:51.820783
4938 09:27:51.823899 ----->DramcWriteLeveling(PI) begin...
4939 09:27:51.826974 ==
4940 09:27:51.827060 Dram Type= 6, Freq= 0, CH_0, rank 0
4941 09:27:51.833639 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4942 09:27:51.833726 ==
4943 09:27:51.837040 Write leveling (Byte 0): 28 => 28
4944 09:27:51.840155 Write leveling (Byte 1): 26 => 26
4945 09:27:51.843718 DramcWriteLeveling(PI) end<-----
4946 09:27:51.843802
4947 09:27:51.843887 ==
4948 09:27:51.847012 Dram Type= 6, Freq= 0, CH_0, rank 0
4949 09:27:51.850277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4950 09:27:51.850363 ==
4951 09:27:51.853560 [Gating] SW mode calibration
4952 09:27:51.860158 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4953 09:27:51.863430 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4954 09:27:51.870255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4955 09:27:51.873553 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4956 09:27:51.876856 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4957 09:27:51.883359 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4958 09:27:51.886752 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4959 09:27:51.890013 0 10 20 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
4960 09:27:51.896498 0 10 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
4961 09:27:51.899942 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4962 09:27:51.903233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4963 09:27:51.910011 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4964 09:27:51.913076 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4965 09:27:51.916465 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4966 09:27:51.923270 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4967 09:27:51.926714 0 11 20 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
4968 09:27:51.929763 0 11 24 | B1->B0 | 3535 4141 | 0 0 | (0 0) (0 0)
4969 09:27:51.935965 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4970 09:27:51.939257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4971 09:27:51.943045 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4972 09:27:51.949464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4973 09:27:51.952881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4974 09:27:51.956112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4975 09:27:51.962704 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4976 09:27:51.965898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4977 09:27:51.969059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4978 09:27:51.975691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4979 09:27:51.979180 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4980 09:27:51.982705 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4981 09:27:51.989322 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4982 09:27:51.992166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4983 09:27:51.995246 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4984 09:27:52.002292 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4985 09:27:52.005617 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4986 09:27:52.008704 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4987 09:27:52.015514 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 09:27:52.018539 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 09:27:52.021955 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 09:27:52.028655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 09:27:52.031860 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4992 09:27:52.035012 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 09:27:52.038428 Total UI for P1: 0, mck2ui 16
4994 09:27:52.041729 best dqsien dly found for B0: ( 0, 14, 20)
4995 09:27:52.045098 Total UI for P1: 0, mck2ui 16
4996 09:27:52.048611 best dqsien dly found for B1: ( 0, 14, 20)
4997 09:27:52.051611 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4998 09:27:52.054859 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4999 09:27:52.058218
5000 09:27:52.065564 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5001 09:27:52.065649 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5002 09:27:52.068018 [Gating] SW calibration Done
5003 09:27:52.068127 ==
5004 09:27:52.071170 Dram Type= 6, Freq= 0, CH_0, rank 0
5005 09:27:52.074649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5006 09:27:52.074744 ==
5007 09:27:52.078001 RX Vref Scan: 0
5008 09:27:52.078087
5009 09:27:52.078174 RX Vref 0 -> 0, step: 1
5010 09:27:52.078256
5011 09:27:52.081148 RX Delay -80 -> 252, step: 8
5012 09:27:52.084781 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5013 09:27:52.087961 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5014 09:27:52.094438 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5015 09:27:52.098136 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5016 09:27:52.101101 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5017 09:27:52.104650 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5018 09:27:52.108327 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5019 09:27:52.111012 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5020 09:27:52.117880 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5021 09:27:52.121141 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5022 09:27:52.124406 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5023 09:27:52.127479 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5024 09:27:52.131074 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5025 09:27:52.137581 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5026 09:27:52.140775 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5027 09:27:52.144212 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5028 09:27:52.144311 ==
5029 09:27:52.147381 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 09:27:52.150883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5031 09:27:52.150969 ==
5032 09:27:52.154101 DQS Delay:
5033 09:27:52.154186 DQS0 = 0, DQS1 = 0
5034 09:27:52.157271 DQM Delay:
5035 09:27:52.157356 DQM0 = 96, DQM1 = 86
5036 09:27:52.157442 DQ Delay:
5037 09:27:52.161029 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
5038 09:27:52.163953 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5039 09:27:52.167379 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5040 09:27:52.170465 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5041 09:27:52.170550
5042 09:27:52.170637
5043 09:27:52.174211 ==
5044 09:27:52.174296 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 09:27:52.180597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5046 09:27:52.180682 ==
5047 09:27:52.180767
5048 09:27:52.180849
5049 09:27:52.183859 TX Vref Scan disable
5050 09:27:52.183944 == TX Byte 0 ==
5051 09:27:52.187085 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5052 09:27:52.193994 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5053 09:27:52.194080 == TX Byte 1 ==
5054 09:27:52.197075 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5055 09:27:52.203756 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5056 09:27:52.203840 ==
5057 09:27:52.207366 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 09:27:52.210539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5059 09:27:52.210624 ==
5060 09:27:52.210711
5061 09:27:52.210791
5062 09:27:52.213818 TX Vref Scan disable
5063 09:27:52.217253 == TX Byte 0 ==
5064 09:27:52.220662 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5065 09:27:52.223714 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5066 09:27:52.227071 == TX Byte 1 ==
5067 09:27:52.230526 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5068 09:27:52.233641 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5069 09:27:52.233726
5070 09:27:52.236984 [DATLAT]
5071 09:27:52.237068 Freq=933, CH0 RK0
5072 09:27:52.237153
5073 09:27:52.240180 DATLAT Default: 0xd
5074 09:27:52.240302 0, 0xFFFF, sum = 0
5075 09:27:52.243533 1, 0xFFFF, sum = 0
5076 09:27:52.243610 2, 0xFFFF, sum = 0
5077 09:27:52.246865 3, 0xFFFF, sum = 0
5078 09:27:52.246951 4, 0xFFFF, sum = 0
5079 09:27:52.250379 5, 0xFFFF, sum = 0
5080 09:27:52.250465 6, 0xFFFF, sum = 0
5081 09:27:52.253796 7, 0xFFFF, sum = 0
5082 09:27:52.253881 8, 0xFFFF, sum = 0
5083 09:27:52.256804 9, 0xFFFF, sum = 0
5084 09:27:52.256890 10, 0x0, sum = 1
5085 09:27:52.260458 11, 0x0, sum = 2
5086 09:27:52.260544 12, 0x0, sum = 3
5087 09:27:52.263565 13, 0x0, sum = 4
5088 09:27:52.263651 best_step = 11
5089 09:27:52.263736
5090 09:27:52.263818 ==
5091 09:27:52.266971 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 09:27:52.270113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5093 09:27:52.273498 ==
5094 09:27:52.273582 RX Vref Scan: 1
5095 09:27:52.273667
5096 09:27:52.276947 RX Vref 0 -> 0, step: 1
5097 09:27:52.277031
5098 09:27:52.280017 RX Delay -69 -> 252, step: 4
5099 09:27:52.280101
5100 09:27:52.283599 Set Vref, RX VrefLevel [Byte0]: 47
5101 09:27:52.283684 [Byte1]: 47
5102 09:27:52.288867
5103 09:27:52.288950 Final RX Vref Byte 0 = 47 to rank0
5104 09:27:52.291799 Final RX Vref Byte 1 = 47 to rank0
5105 09:27:52.295093 Final RX Vref Byte 0 = 47 to rank1
5106 09:27:52.298655 Final RX Vref Byte 1 = 47 to rank1==
5107 09:27:52.302099 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 09:27:52.308327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5109 09:27:52.308412 ==
5110 09:27:52.308499 DQS Delay:
5111 09:27:52.308581 DQS0 = 0, DQS1 = 0
5112 09:27:52.311995 DQM Delay:
5113 09:27:52.312079 DQM0 = 97, DQM1 = 86
5114 09:27:52.315330 DQ Delay:
5115 09:27:52.318385 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5116 09:27:52.321760 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =102
5117 09:27:52.324842 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5118 09:27:52.328289 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =96
5119 09:27:52.328373
5120 09:27:52.328459
5121 09:27:52.334897 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5122 09:27:52.338241 CH0 RK0: MR19=505, MR18=2323
5123 09:27:52.345041 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5124 09:27:52.345126
5125 09:27:52.348308 ----->DramcWriteLeveling(PI) begin...
5126 09:27:52.348394 ==
5127 09:27:52.351832 Dram Type= 6, Freq= 0, CH_0, rank 1
5128 09:27:52.354769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5129 09:27:52.354854 ==
5130 09:27:52.358022 Write leveling (Byte 0): 29 => 29
5131 09:27:52.361644 Write leveling (Byte 1): 27 => 27
5132 09:27:52.364781 DramcWriteLeveling(PI) end<-----
5133 09:27:52.364865
5134 09:27:52.364951 ==
5135 09:27:52.368474 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 09:27:52.371309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5137 09:27:52.371394 ==
5138 09:27:52.374795 [Gating] SW mode calibration
5139 09:27:52.381248 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5140 09:27:52.387897 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5141 09:27:52.391441 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 09:27:52.397986 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 09:27:52.401582 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 09:27:52.405076 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 09:27:52.411503 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 09:27:52.414680 0 10 20 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
5147 09:27:52.418274 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 09:27:52.424566 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 09:27:52.428302 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 09:27:52.431640 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 09:27:52.437902 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 09:27:52.441185 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 09:27:52.444368 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 09:27:52.450864 0 11 20 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)
5155 09:27:52.454416 0 11 24 | B1->B0 | 3c3c 4545 | 0 0 | (1 1) (0 0)
5156 09:27:52.457978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 09:27:52.464213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 09:27:52.467799 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 09:27:52.471171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 09:27:52.474136 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 09:27:52.481064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 09:27:52.484357 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5163 09:27:52.487930 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5164 09:27:52.493956 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 09:27:52.497285 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 09:27:52.500898 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 09:27:52.507295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 09:27:52.510610 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 09:27:52.513907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 09:27:52.520634 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 09:27:52.523597 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 09:27:52.527324 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 09:27:52.533985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:27:52.537135 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:27:52.540571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:27:52.547060 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:27:52.550241 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:27:52.553682 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5179 09:27:52.560360 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 09:27:52.563357 Total UI for P1: 0, mck2ui 16
5181 09:27:52.566842 best dqsien dly found for B0: ( 0, 14, 20)
5182 09:27:52.570334 Total UI for P1: 0, mck2ui 16
5183 09:27:52.573323 best dqsien dly found for B1: ( 0, 14, 22)
5184 09:27:52.576977 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5185 09:27:52.579968 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5186 09:27:52.580053
5187 09:27:52.583422 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5188 09:27:52.586575 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5189 09:27:52.589991 [Gating] SW calibration Done
5190 09:27:52.590075 ==
5191 09:27:52.592905 Dram Type= 6, Freq= 0, CH_0, rank 1
5192 09:27:52.596293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5193 09:27:52.596378 ==
5194 09:27:52.599963 RX Vref Scan: 0
5195 09:27:52.600048
5196 09:27:52.602896 RX Vref 0 -> 0, step: 1
5197 09:27:52.602977
5198 09:27:52.603042 RX Delay -80 -> 252, step: 8
5199 09:27:52.610001 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5200 09:27:52.612897 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5201 09:27:52.616370 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5202 09:27:52.619686 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5203 09:27:52.622810 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5204 09:27:52.626189 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5205 09:27:52.632803 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5206 09:27:52.636030 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5207 09:27:52.639484 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5208 09:27:52.642906 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5209 09:27:52.646263 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5210 09:27:52.652660 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5211 09:27:52.656359 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5212 09:27:52.659563 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5213 09:27:52.662780 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5214 09:27:52.665966 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5215 09:27:52.666048 ==
5216 09:27:52.669158 Dram Type= 6, Freq= 0, CH_0, rank 1
5217 09:27:52.675732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5218 09:27:52.675845 ==
5219 09:27:52.675937 DQS Delay:
5220 09:27:52.676028 DQS0 = 0, DQS1 = 0
5221 09:27:52.679183 DQM Delay:
5222 09:27:52.679265 DQM0 = 97, DQM1 = 88
5223 09:27:52.682691 DQ Delay:
5224 09:27:52.685722 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5225 09:27:52.689031 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5226 09:27:52.692459 DQ8 =75, DQ9 =71, DQ10 =91, DQ11 =79
5227 09:27:52.695821 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5228 09:27:52.695934
5229 09:27:52.696005
5230 09:27:52.696065 ==
5231 09:27:52.699014 Dram Type= 6, Freq= 0, CH_0, rank 1
5232 09:27:52.702411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5233 09:27:52.702493 ==
5234 09:27:52.702559
5235 09:27:52.702619
5236 09:27:52.705890 TX Vref Scan disable
5237 09:27:52.705974 == TX Byte 0 ==
5238 09:27:52.712479 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5239 09:27:52.715652 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5240 09:27:52.715734 == TX Byte 1 ==
5241 09:27:52.722389 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5242 09:27:52.725593 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5243 09:27:52.725674 ==
5244 09:27:52.728716 Dram Type= 6, Freq= 0, CH_0, rank 1
5245 09:27:52.731995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5246 09:27:52.732077 ==
5247 09:27:52.732141
5248 09:27:52.735839
5249 09:27:52.735919 TX Vref Scan disable
5250 09:27:52.738850 == TX Byte 0 ==
5251 09:27:52.742381 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5252 09:27:52.745496 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5253 09:27:52.748926 == TX Byte 1 ==
5254 09:27:52.752158 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5255 09:27:52.758682 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5256 09:27:52.758764
5257 09:27:52.758829 [DATLAT]
5258 09:27:52.758889 Freq=933, CH0 RK1
5259 09:27:52.758948
5260 09:27:52.761776 DATLAT Default: 0xb
5261 09:27:52.761858 0, 0xFFFF, sum = 0
5262 09:27:52.765793 1, 0xFFFF, sum = 0
5263 09:27:52.765876 2, 0xFFFF, sum = 0
5264 09:27:52.768451 3, 0xFFFF, sum = 0
5265 09:27:52.771808 4, 0xFFFF, sum = 0
5266 09:27:52.771890 5, 0xFFFF, sum = 0
5267 09:27:52.775031 6, 0xFFFF, sum = 0
5268 09:27:52.775136 7, 0xFFFF, sum = 0
5269 09:27:52.778524 8, 0xFFFF, sum = 0
5270 09:27:52.778607 9, 0xFFFF, sum = 0
5271 09:27:52.781876 10, 0x0, sum = 1
5272 09:27:52.781959 11, 0x0, sum = 2
5273 09:27:52.785011 12, 0x0, sum = 3
5274 09:27:52.785094 13, 0x0, sum = 4
5275 09:27:52.785161 best_step = 11
5276 09:27:52.785220
5277 09:27:52.788482 ==
5278 09:27:52.791610 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 09:27:52.795009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5280 09:27:52.795091 ==
5281 09:27:52.795156 RX Vref Scan: 0
5282 09:27:52.795217
5283 09:27:52.798221 RX Vref 0 -> 0, step: 1
5284 09:27:52.798303
5285 09:27:52.801895 RX Delay -69 -> 252, step: 4
5286 09:27:52.805101 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5287 09:27:52.811544 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5288 09:27:52.814776 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5289 09:27:52.818599 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5290 09:27:52.821456 iDelay=199, Bit 4, Center 104 (15 ~ 194) 180
5291 09:27:52.824773 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5292 09:27:52.828064 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5293 09:27:52.834977 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5294 09:27:52.838259 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5295 09:27:52.841319 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5296 09:27:52.844822 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5297 09:27:52.848070 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5298 09:27:52.854801 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5299 09:27:52.857980 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5300 09:27:52.861116 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5301 09:27:52.864610 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5302 09:27:52.864692 ==
5303 09:27:52.867758 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 09:27:52.871404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5305 09:27:52.874534 ==
5306 09:27:52.874616 DQS Delay:
5307 09:27:52.874680 DQS0 = 0, DQS1 = 0
5308 09:27:52.877790 DQM Delay:
5309 09:27:52.877871 DQM0 = 97, DQM1 = 86
5310 09:27:52.881204 DQ Delay:
5311 09:27:52.884683 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5312 09:27:52.888019 DQ4 =104, DQ5 =88, DQ6 =102, DQ7 =106
5313 09:27:52.890906 DQ8 =74, DQ9 =72, DQ10 =90, DQ11 =80
5314 09:27:52.894184 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5315 09:27:52.894266
5316 09:27:52.894330
5317 09:27:52.900853 [DQSOSCAuto] RK1, (LSB)MR18= 0x3030, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5318 09:27:52.903941 CH0 RK1: MR19=505, MR18=3030
5319 09:27:52.910824 CH0_RK1: MR19=0x505, MR18=0x3030, DQSOSC=406, MR23=63, INC=65, DEC=43
5320 09:27:52.914215 [RxdqsGatingPostProcess] freq 933
5321 09:27:52.917425 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5322 09:27:52.920925 Pre-setting of DQS Precalculation
5323 09:27:52.927337 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5324 09:27:52.927420 ==
5325 09:27:52.930513 Dram Type= 6, Freq= 0, CH_1, rank 0
5326 09:27:52.933706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5327 09:27:52.933788 ==
5328 09:27:52.940293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5329 09:27:52.946779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5330 09:27:52.950550 [CA 0] Center 37 (7~68) winsize 62
5331 09:27:52.953215 [CA 1] Center 37 (6~68) winsize 63
5332 09:27:52.956956 [CA 2] Center 34 (4~65) winsize 62
5333 09:27:52.960338 [CA 3] Center 34 (4~65) winsize 62
5334 09:27:52.963350 [CA 4] Center 33 (2~64) winsize 63
5335 09:27:52.966823 [CA 5] Center 33 (3~64) winsize 62
5336 09:27:52.966904
5337 09:27:52.970264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5338 09:27:52.970370
5339 09:27:52.973523 [CATrainingPosCal] consider 1 rank data
5340 09:27:52.977053 u2DelayCellTimex100 = 270/100 ps
5341 09:27:52.980145 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5342 09:27:52.983475 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5343 09:27:52.986752 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5344 09:27:52.990040 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5345 09:27:52.993359 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5346 09:27:52.996602 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5347 09:27:52.996683
5348 09:27:53.003526 CA PerBit enable=1, Macro0, CA PI delay=33
5349 09:27:53.003608
5350 09:27:53.006485 [CBTSetCACLKResult] CA Dly = 33
5351 09:27:53.006566 CS Dly: 5 (0~36)
5352 09:27:53.006630 ==
5353 09:27:53.009947 Dram Type= 6, Freq= 0, CH_1, rank 1
5354 09:27:53.012897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5355 09:27:53.012978 ==
5356 09:27:53.019597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5357 09:27:53.026341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5358 09:27:53.029398 [CA 0] Center 37 (6~68) winsize 63
5359 09:27:53.032729 [CA 1] Center 37 (6~68) winsize 63
5360 09:27:53.035945 [CA 2] Center 34 (4~65) winsize 62
5361 09:27:53.039368 [CA 3] Center 34 (4~65) winsize 62
5362 09:27:53.042726 [CA 4] Center 33 (2~64) winsize 63
5363 09:27:53.046045 [CA 5] Center 32 (2~63) winsize 62
5364 09:27:53.046127
5365 09:27:53.049238 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5366 09:27:53.049319
5367 09:27:53.052671 [CATrainingPosCal] consider 2 rank data
5368 09:27:53.056037 u2DelayCellTimex100 = 270/100 ps
5369 09:27:53.059277 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5370 09:27:53.062646 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5371 09:27:53.065784 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5372 09:27:53.069040 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5373 09:27:53.075792 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5374 09:27:53.079059 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5375 09:27:53.079140
5376 09:27:53.082445 CA PerBit enable=1, Macro0, CA PI delay=33
5377 09:27:53.082526
5378 09:27:53.085761 [CBTSetCACLKResult] CA Dly = 33
5379 09:27:53.085867 CS Dly: 5 (0~37)
5380 09:27:53.085963
5381 09:27:53.088942 ----->DramcWriteLeveling(PI) begin...
5382 09:27:53.089024 ==
5383 09:27:53.092385 Dram Type= 6, Freq= 0, CH_1, rank 0
5384 09:27:53.098874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5385 09:27:53.098956 ==
5386 09:27:53.102307 Write leveling (Byte 0): 24 => 24
5387 09:27:53.102388 Write leveling (Byte 1): 25 => 25
5388 09:27:53.105640 DramcWriteLeveling(PI) end<-----
5389 09:27:53.105721
5390 09:27:53.108854 ==
5391 09:27:53.112349 Dram Type= 6, Freq= 0, CH_1, rank 0
5392 09:27:53.115414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5393 09:27:53.115495 ==
5394 09:27:53.118894 [Gating] SW mode calibration
5395 09:27:53.125445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5396 09:27:53.128741 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5397 09:27:53.135520 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 09:27:53.138659 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 09:27:53.141925 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 09:27:53.148813 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 09:27:53.151893 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5402 09:27:53.155404 0 10 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
5403 09:27:53.161788 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5404 09:27:53.165107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 09:27:53.168541 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 09:27:53.175156 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 09:27:53.178290 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 09:27:53.181674 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 09:27:53.188380 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5410 09:27:53.191535 0 11 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5411 09:27:53.195207 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5412 09:27:53.201516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 09:27:53.205066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 09:27:53.208029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 09:27:53.214705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 09:27:53.217921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 09:27:53.221524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5418 09:27:53.227779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5419 09:27:53.231471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 09:27:53.234939 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 09:27:53.241431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 09:27:53.244400 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 09:27:53.247768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 09:27:53.254478 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 09:27:53.257888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 09:27:53.261439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 09:27:53.267450 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 09:27:53.270799 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 09:27:53.274149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 09:27:53.280814 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 09:27:53.284342 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 09:27:53.287485 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 09:27:53.294249 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5434 09:27:53.297338 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5435 09:27:53.300642 Total UI for P1: 0, mck2ui 16
5436 09:27:53.303802 best dqsien dly found for B0: ( 0, 14, 16)
5437 09:27:53.307374 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 09:27:53.310585 Total UI for P1: 0, mck2ui 16
5439 09:27:53.313638 best dqsien dly found for B1: ( 0, 14, 18)
5440 09:27:53.317096 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5441 09:27:53.320557 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5442 09:27:53.320641
5443 09:27:53.323790 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5444 09:27:53.330451 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5445 09:27:53.330537 [Gating] SW calibration Done
5446 09:27:53.330624 ==
5447 09:27:53.334151 Dram Type= 6, Freq= 0, CH_1, rank 0
5448 09:27:53.340425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5449 09:27:53.340510 ==
5450 09:27:53.340597 RX Vref Scan: 0
5451 09:27:53.340678
5452 09:27:53.344222 RX Vref 0 -> 0, step: 1
5453 09:27:53.344307
5454 09:27:53.347858 RX Delay -80 -> 252, step: 8
5455 09:27:53.350329 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5456 09:27:53.353804 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5457 09:27:53.357106 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5458 09:27:53.363650 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5459 09:27:53.367185 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5460 09:27:53.370519 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5461 09:27:53.373462 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5462 09:27:53.376978 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5463 09:27:53.380350 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5464 09:27:53.386636 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5465 09:27:53.390313 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5466 09:27:53.393370 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5467 09:27:53.396594 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5468 09:27:53.400350 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5469 09:27:53.406620 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5470 09:27:53.410166 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5471 09:27:53.410278 ==
5472 09:27:53.413177 Dram Type= 6, Freq= 0, CH_1, rank 0
5473 09:27:53.416848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5474 09:27:53.416932 ==
5475 09:27:53.417018 DQS Delay:
5476 09:27:53.419905 DQS0 = 0, DQS1 = 0
5477 09:27:53.419989 DQM Delay:
5478 09:27:53.423180 DQM0 = 95, DQM1 = 87
5479 09:27:53.423265 DQ Delay:
5480 09:27:53.426511 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5481 09:27:53.429807 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =95
5482 09:27:53.433113 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =75
5483 09:27:53.436334 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5484 09:27:53.436419
5485 09:27:53.436504
5486 09:27:53.436586 ==
5487 09:27:53.439874 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 09:27:53.442936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5489 09:27:53.446770 ==
5490 09:27:53.446854
5491 09:27:53.446939
5492 09:27:53.447020 TX Vref Scan disable
5493 09:27:53.449745 == TX Byte 0 ==
5494 09:27:53.452932 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5495 09:27:53.456221 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5496 09:27:53.459698 == TX Byte 1 ==
5497 09:27:53.463296 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5498 09:27:53.466847 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5499 09:27:53.469602 ==
5500 09:27:53.472929 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 09:27:53.476246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5502 09:27:53.476331 ==
5503 09:27:53.476417
5504 09:27:53.476498
5505 09:27:53.479579 TX Vref Scan disable
5506 09:27:53.479664 == TX Byte 0 ==
5507 09:27:53.486169 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5508 09:27:53.489293 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5509 09:27:53.489375 == TX Byte 1 ==
5510 09:27:53.496027 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5511 09:27:53.499236 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5512 09:27:53.499309
5513 09:27:53.499372 [DATLAT]
5514 09:27:53.502625 Freq=933, CH1 RK0
5515 09:27:53.502724
5516 09:27:53.502813 DATLAT Default: 0xd
5517 09:27:53.506093 0, 0xFFFF, sum = 0
5518 09:27:53.506165 1, 0xFFFF, sum = 0
5519 09:27:53.509367 2, 0xFFFF, sum = 0
5520 09:27:53.509464 3, 0xFFFF, sum = 0
5521 09:27:53.512916 4, 0xFFFF, sum = 0
5522 09:27:53.512989 5, 0xFFFF, sum = 0
5523 09:27:53.516067 6, 0xFFFF, sum = 0
5524 09:27:53.516168 7, 0xFFFF, sum = 0
5525 09:27:53.519484 8, 0xFFFF, sum = 0
5526 09:27:53.519583 9, 0xFFFF, sum = 0
5527 09:27:53.522773 10, 0x0, sum = 1
5528 09:27:53.522874 11, 0x0, sum = 2
5529 09:27:53.526164 12, 0x0, sum = 3
5530 09:27:53.526262 13, 0x0, sum = 4
5531 09:27:53.529247 best_step = 11
5532 09:27:53.529343
5533 09:27:53.529441 ==
5534 09:27:53.532653 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 09:27:53.535950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5536 09:27:53.536050 ==
5537 09:27:53.539163 RX Vref Scan: 1
5538 09:27:53.539263
5539 09:27:53.539327 RX Vref 0 -> 0, step: 1
5540 09:27:53.539386
5541 09:27:53.542766 RX Delay -69 -> 252, step: 4
5542 09:27:53.542863
5543 09:27:53.545781 Set Vref, RX VrefLevel [Byte0]: 54
5544 09:27:53.549057 [Byte1]: 48
5545 09:27:53.553776
5546 09:27:53.553877 Final RX Vref Byte 0 = 54 to rank0
5547 09:27:53.556811 Final RX Vref Byte 1 = 48 to rank0
5548 09:27:53.560303 Final RX Vref Byte 0 = 54 to rank1
5549 09:27:53.563374 Final RX Vref Byte 1 = 48 to rank1==
5550 09:27:53.567009 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 09:27:53.573528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5552 09:27:53.573604 ==
5553 09:27:53.573666 DQS Delay:
5554 09:27:53.573724 DQS0 = 0, DQS1 = 0
5555 09:27:53.576955 DQM Delay:
5556 09:27:53.577030 DQM0 = 94, DQM1 = 88
5557 09:27:53.579923 DQ Delay:
5558 09:27:53.583329 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5559 09:27:53.586890 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5560 09:27:53.590163 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5561 09:27:53.593189 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5562 09:27:53.593261
5563 09:27:53.593329
5564 09:27:53.599858 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5565 09:27:53.603511 CH1 RK0: MR19=505, MR18=3939
5566 09:27:53.609721 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5567 09:27:53.609800
5568 09:27:53.613442 ----->DramcWriteLeveling(PI) begin...
5569 09:27:53.613543 ==
5570 09:27:53.616418 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 09:27:53.619961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5572 09:27:53.620036 ==
5573 09:27:53.623479 Write leveling (Byte 0): 24 => 24
5574 09:27:53.626492 Write leveling (Byte 1): 25 => 25
5575 09:27:53.629902 DramcWriteLeveling(PI) end<-----
5576 09:27:53.630001
5577 09:27:53.630065 ==
5578 09:27:53.633260 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 09:27:53.636510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5580 09:27:53.636594 ==
5581 09:27:53.640230 [Gating] SW mode calibration
5582 09:27:53.646603 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 09:27:53.653143 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5584 09:27:53.656410 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 09:27:53.663119 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 09:27:53.666223 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 09:27:53.669911 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5588 09:27:53.672849 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 1)
5589 09:27:53.679770 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5590 09:27:53.683199 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 09:27:53.686241 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 09:27:53.693172 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 09:27:53.696196 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 09:27:53.699432 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 09:27:53.706040 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5596 09:27:53.709458 0 11 16 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
5597 09:27:53.712694 0 11 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5598 09:27:53.719397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 09:27:53.722687 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 09:27:53.726134 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 09:27:53.732858 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 09:27:53.736170 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 09:27:53.739408 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5604 09:27:53.746064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5605 09:27:53.749570 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 09:27:53.752868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 09:27:53.759204 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:27:53.762583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:27:53.765702 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:27:53.772509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:27:53.775945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:27:53.779251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:27:53.785626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 09:27:53.789080 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 09:27:53.792439 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 09:27:53.798956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 09:27:53.802393 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 09:27:53.805950 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 09:27:53.812267 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5620 09:27:53.815815 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5621 09:27:53.818830 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5622 09:27:53.822532 Total UI for P1: 0, mck2ui 16
5623 09:27:53.825614 best dqsien dly found for B0: ( 0, 14, 14)
5624 09:27:53.832097 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 09:27:53.832236 Total UI for P1: 0, mck2ui 16
5626 09:27:53.835685 best dqsien dly found for B1: ( 0, 14, 18)
5627 09:27:53.841985 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5628 09:27:53.845381 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5629 09:27:53.845452
5630 09:27:53.848802 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5631 09:27:53.852286 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5632 09:27:53.855336 [Gating] SW calibration Done
5633 09:27:53.855433 ==
5634 09:27:53.858743 Dram Type= 6, Freq= 0, CH_1, rank 1
5635 09:27:53.861803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5636 09:27:53.861879 ==
5637 09:27:53.865282 RX Vref Scan: 0
5638 09:27:53.865358
5639 09:27:53.865419 RX Vref 0 -> 0, step: 1
5640 09:27:53.865478
5641 09:27:53.868665 RX Delay -80 -> 252, step: 8
5642 09:27:53.872145 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5643 09:27:53.878611 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5644 09:27:53.882164 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5645 09:27:53.885183 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5646 09:27:53.888661 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5647 09:27:53.891721 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5648 09:27:53.895001 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5649 09:27:53.901837 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5650 09:27:53.905074 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5651 09:27:53.908453 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5652 09:27:53.911636 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5653 09:27:53.914819 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5654 09:27:53.921901 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5655 09:27:53.924811 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5656 09:27:53.928298 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5657 09:27:53.931423 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5658 09:27:53.931505 ==
5659 09:27:53.934869 Dram Type= 6, Freq= 0, CH_1, rank 1
5660 09:27:53.938100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5661 09:27:53.941607 ==
5662 09:27:53.941688 DQS Delay:
5663 09:27:53.941753 DQS0 = 0, DQS1 = 0
5664 09:27:53.945071 DQM Delay:
5665 09:27:53.945152 DQM0 = 95, DQM1 = 85
5666 09:27:53.948209 DQ Delay:
5667 09:27:53.951443 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5668 09:27:53.951552 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5669 09:27:53.954599 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5670 09:27:53.961264 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5671 09:27:53.961346
5672 09:27:53.961411
5673 09:27:53.961471 ==
5674 09:27:53.964786 Dram Type= 6, Freq= 0, CH_1, rank 1
5675 09:27:53.968394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5676 09:27:53.968477 ==
5677 09:27:53.968541
5678 09:27:53.968601
5679 09:27:53.971368 TX Vref Scan disable
5680 09:27:53.971450 == TX Byte 0 ==
5681 09:27:53.978067 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5682 09:27:53.981153 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5683 09:27:53.981234 == TX Byte 1 ==
5684 09:27:53.987880 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5685 09:27:53.991150 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5686 09:27:53.991295 ==
5687 09:27:53.994252 Dram Type= 6, Freq= 0, CH_1, rank 1
5688 09:27:53.997856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5689 09:27:53.997938 ==
5690 09:27:53.998004
5691 09:27:53.998063
5692 09:27:54.001265 TX Vref Scan disable
5693 09:27:54.004194 == TX Byte 0 ==
5694 09:27:54.007703 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5695 09:27:54.011102 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5696 09:27:54.014516 == TX Byte 1 ==
5697 09:27:54.017592 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5698 09:27:54.020865 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5699 09:27:54.020947
5700 09:27:54.024299 [DATLAT]
5701 09:27:54.024380 Freq=933, CH1 RK1
5702 09:27:54.024446
5703 09:27:54.027829 DATLAT Default: 0xb
5704 09:27:54.027911 0, 0xFFFF, sum = 0
5705 09:27:54.030930 1, 0xFFFF, sum = 0
5706 09:27:54.031013 2, 0xFFFF, sum = 0
5707 09:27:54.034626 3, 0xFFFF, sum = 0
5708 09:27:54.034709 4, 0xFFFF, sum = 0
5709 09:27:54.037432 5, 0xFFFF, sum = 0
5710 09:27:54.037516 6, 0xFFFF, sum = 0
5711 09:27:54.040914 7, 0xFFFF, sum = 0
5712 09:27:54.044073 8, 0xFFFF, sum = 0
5713 09:27:54.044156 9, 0xFFFF, sum = 0
5714 09:27:54.047631 10, 0x0, sum = 1
5715 09:27:54.047714 11, 0x0, sum = 2
5716 09:27:54.047780 12, 0x0, sum = 3
5717 09:27:54.050872 13, 0x0, sum = 4
5718 09:27:54.050955 best_step = 11
5719 09:27:54.051019
5720 09:27:54.051079 ==
5721 09:27:54.054036 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 09:27:54.060516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5723 09:27:54.060598 ==
5724 09:27:54.060664 RX Vref Scan: 0
5725 09:27:54.060724
5726 09:27:54.063999 RX Vref 0 -> 0, step: 1
5727 09:27:54.064080
5728 09:27:54.067892 RX Delay -69 -> 252, step: 4
5729 09:27:54.070941 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5730 09:27:54.073833 iDelay=203, Bit 1, Center 94 (3 ~ 186) 184
5731 09:27:54.080738 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5732 09:27:54.084076 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5733 09:27:54.087378 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5734 09:27:54.090885 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5735 09:27:54.093732 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5736 09:27:54.100487 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5737 09:27:54.103732 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5738 09:27:54.107325 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5739 09:27:54.110595 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5740 09:27:54.113595 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5741 09:27:54.116843 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5742 09:27:54.123432 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5743 09:27:54.127057 iDelay=203, Bit 14, Center 98 (3 ~ 194) 192
5744 09:27:54.130231 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5745 09:27:54.130313 ==
5746 09:27:54.133721 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 09:27:54.136683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5748 09:27:54.136766 ==
5749 09:27:54.140227 DQS Delay:
5750 09:27:54.140309 DQS0 = 0, DQS1 = 0
5751 09:27:54.143514 DQM Delay:
5752 09:27:54.143619 DQM0 = 96, DQM1 = 88
5753 09:27:54.143686 DQ Delay:
5754 09:27:54.146849 DQ0 =98, DQ1 =94, DQ2 =88, DQ3 =92
5755 09:27:54.150135 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =96
5756 09:27:54.153471 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =82
5757 09:27:54.156745 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5758 09:27:54.156827
5759 09:27:54.156892
5760 09:27:54.166899 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5761 09:27:54.170258 CH1 RK1: MR19=505, MR18=2222
5762 09:27:54.176536 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5763 09:27:54.176619 [RxdqsGatingPostProcess] freq 933
5764 09:27:54.183343 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5765 09:27:54.186407 Pre-setting of DQS Precalculation
5766 09:27:54.193543 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5767 09:27:54.199971 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5768 09:27:54.207082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5769 09:27:54.207164
5770 09:27:54.207229
5771 09:27:54.209731 [Calibration Summary] 1866 Mbps
5772 09:27:54.209813 CH 0, Rank 0
5773 09:27:54.213097 SW Impedance : PASS
5774 09:27:54.216445 DUTY Scan : NO K
5775 09:27:54.216526 ZQ Calibration : PASS
5776 09:27:54.219633 Jitter Meter : NO K
5777 09:27:54.219714 CBT Training : PASS
5778 09:27:54.222910 Write leveling : PASS
5779 09:27:54.226203 RX DQS gating : PASS
5780 09:27:54.226312 RX DQ/DQS(RDDQC) : PASS
5781 09:27:54.229756 TX DQ/DQS : PASS
5782 09:27:54.232905 RX DATLAT : PASS
5783 09:27:54.232987 RX DQ/DQS(Engine): PASS
5784 09:27:54.236377 TX OE : NO K
5785 09:27:54.236460 All Pass.
5786 09:27:54.236524
5787 09:27:54.239418 CH 0, Rank 1
5788 09:27:54.239568 SW Impedance : PASS
5789 09:27:54.242926 DUTY Scan : NO K
5790 09:27:54.246100 ZQ Calibration : PASS
5791 09:27:54.246184 Jitter Meter : NO K
5792 09:27:54.249659 CBT Training : PASS
5793 09:27:54.253181 Write leveling : PASS
5794 09:27:54.253265 RX DQS gating : PASS
5795 09:27:54.256421 RX DQ/DQS(RDDQC) : PASS
5796 09:27:54.259429 TX DQ/DQS : PASS
5797 09:27:54.259514 RX DATLAT : PASS
5798 09:27:54.262956 RX DQ/DQS(Engine): PASS
5799 09:27:54.263041 TX OE : NO K
5800 09:27:54.266108 All Pass.
5801 09:27:54.266192
5802 09:27:54.266279 CH 1, Rank 0
5803 09:27:54.269458 SW Impedance : PASS
5804 09:27:54.269542 DUTY Scan : NO K
5805 09:27:54.272805 ZQ Calibration : PASS
5806 09:27:54.276391 Jitter Meter : NO K
5807 09:27:54.276476 CBT Training : PASS
5808 09:27:54.279737 Write leveling : PASS
5809 09:27:54.283035 RX DQS gating : PASS
5810 09:27:54.283119 RX DQ/DQS(RDDQC) : PASS
5811 09:27:54.286150 TX DQ/DQS : PASS
5812 09:27:54.290048 RX DATLAT : PASS
5813 09:27:54.290133 RX DQ/DQS(Engine): PASS
5814 09:27:54.292931 TX OE : NO K
5815 09:27:54.293016 All Pass.
5816 09:27:54.293101
5817 09:27:54.296085 CH 1, Rank 1
5818 09:27:54.296169 SW Impedance : PASS
5819 09:27:54.299727 DUTY Scan : NO K
5820 09:27:54.302832 ZQ Calibration : PASS
5821 09:27:54.302916 Jitter Meter : NO K
5822 09:27:54.306056 CBT Training : PASS
5823 09:27:54.309379 Write leveling : PASS
5824 09:27:54.309463 RX DQS gating : PASS
5825 09:27:54.312675 RX DQ/DQS(RDDQC) : PASS
5826 09:27:54.315949 TX DQ/DQS : PASS
5827 09:27:54.316033 RX DATLAT : PASS
5828 09:27:54.319486 RX DQ/DQS(Engine): PASS
5829 09:27:54.319570 TX OE : NO K
5830 09:27:54.322662 All Pass.
5831 09:27:54.322746
5832 09:27:54.322832 DramC Write-DBI off
5833 09:27:54.325949 PER_BANK_REFRESH: Hybrid Mode
5834 09:27:54.329347 TX_TRACKING: ON
5835 09:27:54.335774 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5836 09:27:54.339179 [FAST_K] Save calibration result to emmc
5837 09:27:54.345651 dramc_set_vcore_voltage set vcore to 650000
5838 09:27:54.345755 Read voltage for 400, 6
5839 09:27:54.345846 Vio18 = 0
5840 09:27:54.349050 Vcore = 650000
5841 09:27:54.349146 Vdram = 0
5842 09:27:54.349240 Vddq = 0
5843 09:27:54.352308 Vmddr = 0
5844 09:27:54.355664 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5845 09:27:54.362646 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5846 09:27:54.362751 MEM_TYPE=3, freq_sel=20
5847 09:27:54.365770 sv_algorithm_assistance_LP4_800
5848 09:27:54.372506 ============ PULL DRAM RESETB DOWN ============
5849 09:27:54.375721 ========== PULL DRAM RESETB DOWN end =========
5850 09:27:54.378887 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5851 09:27:54.382124 ===================================
5852 09:27:54.385545 LPDDR4 DRAM CONFIGURATION
5853 09:27:54.389057 ===================================
5854 09:27:54.392426 EX_ROW_EN[0] = 0x0
5855 09:27:54.392495 EX_ROW_EN[1] = 0x0
5856 09:27:54.395575 LP4Y_EN = 0x0
5857 09:27:54.395670 WORK_FSP = 0x0
5858 09:27:54.398852 WL = 0x2
5859 09:27:54.398945 RL = 0x2
5860 09:27:54.402127 BL = 0x2
5861 09:27:54.402202 RPST = 0x0
5862 09:27:54.405651 RD_PRE = 0x0
5863 09:27:54.405734 WR_PRE = 0x1
5864 09:27:54.409181 WR_PST = 0x0
5865 09:27:54.409251 DBI_WR = 0x0
5866 09:27:54.412326 DBI_RD = 0x0
5867 09:27:54.412392 OTF = 0x1
5868 09:27:54.415587 ===================================
5869 09:27:54.418854 ===================================
5870 09:27:54.421908 ANA top config
5871 09:27:54.425430 ===================================
5872 09:27:54.428699 DLL_ASYNC_EN = 0
5873 09:27:54.428773 ALL_SLAVE_EN = 1
5874 09:27:54.432304 NEW_RANK_MODE = 1
5875 09:27:54.435630 DLL_IDLE_MODE = 1
5876 09:27:54.438751 LP45_APHY_COMB_EN = 1
5877 09:27:54.438850 TX_ODT_DIS = 1
5878 09:27:54.442127 NEW_8X_MODE = 1
5879 09:27:54.445482 ===================================
5880 09:27:54.448686 ===================================
5881 09:27:54.452079 data_rate = 800
5882 09:27:54.455180 CKR = 1
5883 09:27:54.458579 DQ_P2S_RATIO = 4
5884 09:27:54.461956 ===================================
5885 09:27:54.465460 CA_P2S_RATIO = 4
5886 09:27:54.465541 DQ_CA_OPEN = 0
5887 09:27:54.468634 DQ_SEMI_OPEN = 1
5888 09:27:54.471901 CA_SEMI_OPEN = 1
5889 09:27:54.475316 CA_FULL_RATE = 0
5890 09:27:54.478565 DQ_CKDIV4_EN = 0
5891 09:27:54.481828 CA_CKDIV4_EN = 1
5892 09:27:54.481901 CA_PREDIV_EN = 0
5893 09:27:54.485232 PH8_DLY = 0
5894 09:27:54.488441 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5895 09:27:54.491834 DQ_AAMCK_DIV = 0
5896 09:27:54.495477 CA_AAMCK_DIV = 0
5897 09:27:54.498333 CA_ADMCK_DIV = 4
5898 09:27:54.498429 DQ_TRACK_CA_EN = 0
5899 09:27:54.501830 CA_PICK = 800
5900 09:27:54.505213 CA_MCKIO = 400
5901 09:27:54.508667 MCKIO_SEMI = 400
5902 09:27:54.511797 PLL_FREQ = 3016
5903 09:27:54.515317 DQ_UI_PI_RATIO = 32
5904 09:27:54.518573 CA_UI_PI_RATIO = 32
5905 09:27:54.521921 ===================================
5906 09:27:54.525109 ===================================
5907 09:27:54.525176 memory_type:LPDDR4
5908 09:27:54.528339 GP_NUM : 10
5909 09:27:54.532107 SRAM_EN : 1
5910 09:27:54.532247 MD32_EN : 0
5911 09:27:54.535218 ===================================
5912 09:27:54.538392 [ANA_INIT] >>>>>>>>>>>>>>
5913 09:27:54.541667 <<<<<< [CONFIGURE PHASE]: ANA_TX
5914 09:27:54.545086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5915 09:27:54.548323 ===================================
5916 09:27:54.551638 data_rate = 800,PCW = 0X7400
5917 09:27:54.555017 ===================================
5918 09:27:54.558318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5919 09:27:54.561667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5920 09:27:54.574843 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5921 09:27:54.578303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5922 09:27:54.581806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5923 09:27:54.584835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5924 09:27:54.588380 [ANA_INIT] flow start
5925 09:27:54.588457 [ANA_INIT] PLL >>>>>>>>
5926 09:27:54.591772 [ANA_INIT] PLL <<<<<<<<
5927 09:27:54.594850 [ANA_INIT] MIDPI >>>>>>>>
5928 09:27:54.598128 [ANA_INIT] MIDPI <<<<<<<<
5929 09:27:54.598204 [ANA_INIT] DLL >>>>>>>>
5930 09:27:54.601512 [ANA_INIT] flow end
5931 09:27:54.604756 ============ LP4 DIFF to SE enter ============
5932 09:27:54.608277 ============ LP4 DIFF to SE exit ============
5933 09:27:54.611497 [ANA_INIT] <<<<<<<<<<<<<
5934 09:27:54.614872 [Flow] Enable top DCM control >>>>>
5935 09:27:54.618283 [Flow] Enable top DCM control <<<<<
5936 09:27:54.621791 Enable DLL master slave shuffle
5937 09:27:54.628056 ==============================================================
5938 09:27:54.628157 Gating Mode config
5939 09:27:54.634721 ==============================================================
5940 09:27:54.634825 Config description:
5941 09:27:54.644693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5942 09:27:54.651274 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5943 09:27:54.657860 SELPH_MODE 0: By rank 1: By Phase
5944 09:27:54.661292 ==============================================================
5945 09:27:54.664632 GAT_TRACK_EN = 0
5946 09:27:54.668290 RX_GATING_MODE = 2
5947 09:27:54.671220 RX_GATING_TRACK_MODE = 2
5948 09:27:54.674484 SELPH_MODE = 1
5949 09:27:54.677631 PICG_EARLY_EN = 1
5950 09:27:54.681139 VALID_LAT_VALUE = 1
5951 09:27:54.684381 ==============================================================
5952 09:27:54.690911 Enter into Gating configuration >>>>
5953 09:27:54.694615 Exit from Gating configuration <<<<
5954 09:27:54.694692 Enter into DVFS_PRE_config >>>>>
5955 09:27:54.707764 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5956 09:27:54.710822 Exit from DVFS_PRE_config <<<<<
5957 09:27:54.714415 Enter into PICG configuration >>>>
5958 09:27:54.717455 Exit from PICG configuration <<<<
5959 09:27:54.717533 [RX_INPUT] configuration >>>>>
5960 09:27:54.720822 [RX_INPUT] configuration <<<<<
5961 09:27:54.727695 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5962 09:27:54.731359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5963 09:27:54.737497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5964 09:27:54.744342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5965 09:27:54.750917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5966 09:27:54.757539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5967 09:27:54.760834 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5968 09:27:54.763977 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5969 09:27:54.770889 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5970 09:27:54.774279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5971 09:27:54.777485 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5972 09:27:54.780648 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5973 09:27:54.784267 ===================================
5974 09:27:54.787694 LPDDR4 DRAM CONFIGURATION
5975 09:27:54.791232 ===================================
5976 09:27:54.794569 EX_ROW_EN[0] = 0x0
5977 09:27:54.794638 EX_ROW_EN[1] = 0x0
5978 09:27:54.797479 LP4Y_EN = 0x0
5979 09:27:54.797547 WORK_FSP = 0x0
5980 09:27:54.800635 WL = 0x2
5981 09:27:54.800702 RL = 0x2
5982 09:27:54.804309 BL = 0x2
5983 09:27:54.804378 RPST = 0x0
5984 09:27:54.807605 RD_PRE = 0x0
5985 09:27:54.807678 WR_PRE = 0x1
5986 09:27:54.810689 WR_PST = 0x0
5987 09:27:54.810784 DBI_WR = 0x0
5988 09:27:54.813955 DBI_RD = 0x0
5989 09:27:54.814025 OTF = 0x1
5990 09:27:54.817364 ===================================
5991 09:27:54.824124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5992 09:27:54.827310 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5993 09:27:54.830497 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5994 09:27:54.833820 ===================================
5995 09:27:54.837199 LPDDR4 DRAM CONFIGURATION
5996 09:27:54.840606 ===================================
5997 09:27:54.843641 EX_ROW_EN[0] = 0x10
5998 09:27:54.843717 EX_ROW_EN[1] = 0x0
5999 09:27:54.847189 LP4Y_EN = 0x0
6000 09:27:54.847267 WORK_FSP = 0x0
6001 09:27:54.850548 WL = 0x2
6002 09:27:54.850646 RL = 0x2
6003 09:27:54.853630 BL = 0x2
6004 09:27:54.853724 RPST = 0x0
6005 09:27:54.857056 RD_PRE = 0x0
6006 09:27:54.857154 WR_PRE = 0x1
6007 09:27:54.860782 WR_PST = 0x0
6008 09:27:54.860853 DBI_WR = 0x0
6009 09:27:54.863411 DBI_RD = 0x0
6010 09:27:54.863485 OTF = 0x1
6011 09:27:54.866974 ===================================
6012 09:27:54.873799 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6013 09:27:54.878177 nWR fixed to 30
6014 09:27:54.881429 [ModeRegInit_LP4] CH0 RK0
6015 09:27:54.881527 [ModeRegInit_LP4] CH0 RK1
6016 09:27:54.884886 [ModeRegInit_LP4] CH1 RK0
6017 09:27:54.888277 [ModeRegInit_LP4] CH1 RK1
6018 09:27:54.888354 match AC timing 18
6019 09:27:54.894726 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6020 09:27:54.898424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6021 09:27:54.901683 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6022 09:27:54.908499 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6023 09:27:54.912083 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6024 09:27:54.912191 ==
6025 09:27:54.914870 Dram Type= 6, Freq= 0, CH_0, rank 0
6026 09:27:54.918598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6027 09:27:54.918705 ==
6028 09:27:54.924897 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6029 09:27:54.931687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6030 09:27:54.934912 [CA 0] Center 36 (8~64) winsize 57
6031 09:27:54.938410 [CA 1] Center 36 (8~64) winsize 57
6032 09:27:54.941406 [CA 2] Center 36 (8~64) winsize 57
6033 09:27:54.941481 [CA 3] Center 36 (8~64) winsize 57
6034 09:27:54.944960 [CA 4] Center 36 (8~64) winsize 57
6035 09:27:54.948264 [CA 5] Center 36 (8~64) winsize 57
6036 09:27:54.948340
6037 09:27:54.955157 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6038 09:27:54.955264
6039 09:27:54.958242 [CATrainingPosCal] consider 1 rank data
6040 09:27:54.961568 u2DelayCellTimex100 = 270/100 ps
6041 09:27:54.964739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 09:27:54.968341 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6043 09:27:54.971287 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6044 09:27:54.974787 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6045 09:27:54.977953 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6046 09:27:54.981541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6047 09:27:54.981639
6048 09:27:54.984745 CA PerBit enable=1, Macro0, CA PI delay=36
6049 09:27:54.984817
6050 09:27:54.988491 [CBTSetCACLKResult] CA Dly = 36
6051 09:27:54.991465 CS Dly: 1 (0~32)
6052 09:27:54.991536 ==
6053 09:27:54.995089 Dram Type= 6, Freq= 0, CH_0, rank 1
6054 09:27:54.998233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 09:27:54.998330 ==
6056 09:27:55.004959 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6057 09:27:55.007948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6058 09:27:55.011799 [CA 0] Center 36 (8~64) winsize 57
6059 09:27:55.014834 [CA 1] Center 36 (8~64) winsize 57
6060 09:27:55.018104 [CA 2] Center 36 (8~64) winsize 57
6061 09:27:55.021427 [CA 3] Center 36 (8~64) winsize 57
6062 09:27:55.024546 [CA 4] Center 36 (8~64) winsize 57
6063 09:27:55.028426 [CA 5] Center 36 (8~64) winsize 57
6064 09:27:55.028493
6065 09:27:55.031283 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6066 09:27:55.031383
6067 09:27:55.034838 [CATrainingPosCal] consider 2 rank data
6068 09:27:55.037820 u2DelayCellTimex100 = 270/100 ps
6069 09:27:55.041198 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 09:27:55.044563 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 09:27:55.048028 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 09:27:55.054474 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 09:27:55.057708 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 09:27:55.061389 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 09:27:55.061461
6076 09:27:55.064453 CA PerBit enable=1, Macro0, CA PI delay=36
6077 09:27:55.064525
6078 09:27:55.067875 [CBTSetCACLKResult] CA Dly = 36
6079 09:27:55.067947 CS Dly: 1 (0~32)
6080 09:27:55.068015
6081 09:27:55.071147 ----->DramcWriteLeveling(PI) begin...
6082 09:27:55.071254 ==
6083 09:27:55.074568 Dram Type= 6, Freq= 0, CH_0, rank 0
6084 09:27:55.081181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6085 09:27:55.081289 ==
6086 09:27:55.084398 Write leveling (Byte 0): 32 => 0
6087 09:27:55.087691 Write leveling (Byte 1): 32 => 0
6088 09:27:55.087791 DramcWriteLeveling(PI) end<-----
6089 09:27:55.087880
6090 09:27:55.090913 ==
6091 09:27:55.094238 Dram Type= 6, Freq= 0, CH_0, rank 0
6092 09:27:55.097925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6093 09:27:55.098003 ==
6094 09:27:55.100915 [Gating] SW mode calibration
6095 09:27:55.107483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6096 09:27:55.110770 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6097 09:27:55.117535 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6098 09:27:55.121149 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6099 09:27:55.124120 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6100 09:27:55.130908 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6101 09:27:55.134436 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6102 09:27:55.137520 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6103 09:27:55.144116 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6104 09:27:55.147368 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6105 09:27:55.150854 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6106 09:27:55.154203 Total UI for P1: 0, mck2ui 16
6107 09:27:55.157769 best dqsien dly found for B0: ( 0, 10, 16)
6108 09:27:55.160990 Total UI for P1: 0, mck2ui 16
6109 09:27:55.164286 best dqsien dly found for B1: ( 0, 10, 16)
6110 09:27:55.167764 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6111 09:27:55.170700 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6112 09:27:55.170794
6113 09:27:55.177507 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6114 09:27:55.180582 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6115 09:27:55.180683 [Gating] SW calibration Done
6116 09:27:55.184179 ==
6117 09:27:55.187399 Dram Type= 6, Freq= 0, CH_0, rank 0
6118 09:27:55.191024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6119 09:27:55.191109 ==
6120 09:27:55.191196 RX Vref Scan: 0
6121 09:27:55.191277
6122 09:27:55.194153 RX Vref 0 -> 0, step: 1
6123 09:27:55.194237
6124 09:27:55.197134 RX Delay -410 -> 252, step: 16
6125 09:27:55.200780 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6126 09:27:55.207107 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6127 09:27:55.210612 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6128 09:27:55.213884 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6129 09:27:55.217298 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6130 09:27:55.223797 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6131 09:27:55.226956 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6132 09:27:55.230475 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6133 09:27:55.233562 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6134 09:27:55.240333 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6135 09:27:55.243505 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6136 09:27:55.247090 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6137 09:27:55.250111 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6138 09:27:55.256983 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6139 09:27:55.260074 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6140 09:27:55.263293 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6141 09:27:55.263378 ==
6142 09:27:55.267006 Dram Type= 6, Freq= 0, CH_0, rank 0
6143 09:27:55.273630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6144 09:27:55.273714 ==
6145 09:27:55.273801 DQS Delay:
6146 09:27:55.276519 DQS0 = 51, DQS1 = 59
6147 09:27:55.276604 DQM Delay:
6148 09:27:55.276691 DQM0 = 12, DQM1 = 15
6149 09:27:55.280055 DQ Delay:
6150 09:27:55.283109 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6151 09:27:55.283193 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6152 09:27:55.286279 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6153 09:27:55.289852 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6154 09:27:55.289937
6155 09:27:55.290022
6156 09:27:55.293222 ==
6157 09:27:55.296338 Dram Type= 6, Freq= 0, CH_0, rank 0
6158 09:27:55.299571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6159 09:27:55.299656 ==
6160 09:27:55.299742
6161 09:27:55.299824
6162 09:27:55.302946 TX Vref Scan disable
6163 09:27:55.303031 == TX Byte 0 ==
6164 09:27:55.306179 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6165 09:27:55.313086 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6166 09:27:55.313171 == TX Byte 1 ==
6167 09:27:55.316287 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6168 09:27:55.323043 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6169 09:27:55.323128 ==
6170 09:27:55.326013 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 09:27:55.329213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 09:27:55.329297 ==
6173 09:27:55.329384
6174 09:27:55.329465
6175 09:27:55.332743 TX Vref Scan disable
6176 09:27:55.332827 == TX Byte 0 ==
6177 09:27:55.339181 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6178 09:27:55.342513 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6179 09:27:55.342597 == TX Byte 1 ==
6180 09:27:55.349177 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6181 09:27:55.352673 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6182 09:27:55.352757
6183 09:27:55.352843 [DATLAT]
6184 09:27:55.355859 Freq=400, CH0 RK0
6185 09:27:55.355944
6186 09:27:55.356046 DATLAT Default: 0xf
6187 09:27:55.359563 0, 0xFFFF, sum = 0
6188 09:27:55.359649 1, 0xFFFF, sum = 0
6189 09:27:55.362421 2, 0xFFFF, sum = 0
6190 09:27:55.362507 3, 0xFFFF, sum = 0
6191 09:27:55.365654 4, 0xFFFF, sum = 0
6192 09:27:55.365740 5, 0xFFFF, sum = 0
6193 09:27:55.368986 6, 0xFFFF, sum = 0
6194 09:27:55.369072 7, 0xFFFF, sum = 0
6195 09:27:55.372487 8, 0xFFFF, sum = 0
6196 09:27:55.372573 9, 0xFFFF, sum = 0
6197 09:27:55.375559 10, 0xFFFF, sum = 0
6198 09:27:55.379083 11, 0xFFFF, sum = 0
6199 09:27:55.379169 12, 0x0, sum = 1
6200 09:27:55.382409 13, 0x0, sum = 2
6201 09:27:55.382495 14, 0x0, sum = 3
6202 09:27:55.382582 15, 0x0, sum = 4
6203 09:27:55.385746 best_step = 13
6204 09:27:55.385829
6205 09:27:55.385915 ==
6206 09:27:55.389162 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 09:27:55.392344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6208 09:27:55.392429 ==
6209 09:27:55.395877 RX Vref Scan: 1
6210 09:27:55.395961
6211 09:27:55.396062 RX Vref 0 -> 0, step: 1
6212 09:27:55.398640
6213 09:27:55.398746 RX Delay -359 -> 252, step: 8
6214 09:27:55.398844
6215 09:27:55.402005 Set Vref, RX VrefLevel [Byte0]: 47
6216 09:27:55.405255 [Byte1]: 47
6217 09:27:55.410825
6218 09:27:55.410907 Final RX Vref Byte 0 = 47 to rank0
6219 09:27:55.414304 Final RX Vref Byte 1 = 47 to rank0
6220 09:27:55.417439 Final RX Vref Byte 0 = 47 to rank1
6221 09:27:55.420671 Final RX Vref Byte 1 = 47 to rank1==
6222 09:27:55.423865 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 09:27:55.430927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6224 09:27:55.431009 ==
6225 09:27:55.431074 DQS Delay:
6226 09:27:55.433979 DQS0 = 52, DQS1 = 68
6227 09:27:55.434064 DQM Delay:
6228 09:27:55.434150 DQM0 = 9, DQM1 = 17
6229 09:27:55.437502 DQ Delay:
6230 09:27:55.440692 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6231 09:27:55.440777 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6232 09:27:55.444085 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6233 09:27:55.447105 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6234 09:27:55.447190
6235 09:27:55.447275
6236 09:27:55.457206 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6237 09:27:55.460435 CH0 RK0: MR19=C0C, MR18=AEAE
6238 09:27:55.467014 CH0_RK0: MR19=0xC0C, MR18=0xAEAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6239 09:27:55.467099 ==
6240 09:27:55.470672 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 09:27:55.473803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6242 09:27:55.473892 ==
6243 09:27:55.477096 [Gating] SW mode calibration
6244 09:27:55.483811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6245 09:27:55.487092 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6246 09:27:55.493813 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6247 09:27:55.497116 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6248 09:27:55.500423 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6249 09:27:55.507227 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6250 09:27:55.510432 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6251 09:27:55.513776 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6252 09:27:55.520212 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6253 09:27:55.523617 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6254 09:27:55.527018 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6255 09:27:55.530258 Total UI for P1: 0, mck2ui 16
6256 09:27:55.533941 best dqsien dly found for B0: ( 0, 10, 16)
6257 09:27:55.537131 Total UI for P1: 0, mck2ui 16
6258 09:27:55.540343 best dqsien dly found for B1: ( 0, 10, 24)
6259 09:27:55.543684 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6260 09:27:55.546870 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6261 09:27:55.546954
6262 09:27:55.553650 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6263 09:27:55.557021 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6264 09:27:55.560153 [Gating] SW calibration Done
6265 09:27:55.560278 ==
6266 09:27:55.563663 Dram Type= 6, Freq= 0, CH_0, rank 1
6267 09:27:55.567212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6268 09:27:55.567321 ==
6269 09:27:55.567419 RX Vref Scan: 0
6270 09:27:55.567513
6271 09:27:55.570372 RX Vref 0 -> 0, step: 1
6272 09:27:55.570468
6273 09:27:55.573607 RX Delay -410 -> 252, step: 16
6274 09:27:55.577072 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6275 09:27:55.583590 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6276 09:27:55.586961 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6277 09:27:55.590024 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6278 09:27:55.593593 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6279 09:27:55.600078 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6280 09:27:55.603531 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6281 09:27:55.606753 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6282 09:27:55.610542 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6283 09:27:55.616915 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6284 09:27:55.620616 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6285 09:27:55.623358 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6286 09:27:55.626743 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6287 09:27:55.633399 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6288 09:27:55.636661 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6289 09:27:55.640200 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6290 09:27:55.640289 ==
6291 09:27:55.643223 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 09:27:55.649926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6293 09:27:55.650026 ==
6294 09:27:55.650118 DQS Delay:
6295 09:27:55.650206 DQS0 = 43, DQS1 = 59
6296 09:27:55.653148 DQM Delay:
6297 09:27:55.653218 DQM0 = 7, DQM1 = 15
6298 09:27:55.656827 DQ Delay:
6299 09:27:55.656927 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6300 09:27:55.659640 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6301 09:27:55.663278 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6302 09:27:55.666275 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6303 09:27:55.666373
6304 09:27:55.666462
6305 09:27:55.669596 ==
6306 09:27:55.673062 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 09:27:55.676452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6308 09:27:55.676529 ==
6309 09:27:55.676591
6310 09:27:55.676648
6311 09:27:55.679934 TX Vref Scan disable
6312 09:27:55.680032 == TX Byte 0 ==
6313 09:27:55.682898 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6314 09:27:55.689639 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6315 09:27:55.689711 == TX Byte 1 ==
6316 09:27:55.692991 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6317 09:27:55.699599 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6318 09:27:55.699685 ==
6319 09:27:55.702666 Dram Type= 6, Freq= 0, CH_0, rank 1
6320 09:27:55.705824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6321 09:27:55.705909 ==
6322 09:27:55.705996
6323 09:27:55.706078
6324 09:27:55.709250 TX Vref Scan disable
6325 09:27:55.709335 == TX Byte 0 ==
6326 09:27:55.712736 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6327 09:27:55.719345 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6328 09:27:55.719429 == TX Byte 1 ==
6329 09:27:55.722506 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6330 09:27:55.729185 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6331 09:27:55.729270
6332 09:27:55.729356 [DATLAT]
6333 09:27:55.729438 Freq=400, CH0 RK1
6334 09:27:55.729518
6335 09:27:55.732555 DATLAT Default: 0xd
6336 09:27:55.736218 0, 0xFFFF, sum = 0
6337 09:27:55.736304 1, 0xFFFF, sum = 0
6338 09:27:55.738931 2, 0xFFFF, sum = 0
6339 09:27:55.739016 3, 0xFFFF, sum = 0
6340 09:27:55.742385 4, 0xFFFF, sum = 0
6341 09:27:55.742470 5, 0xFFFF, sum = 0
6342 09:27:55.745604 6, 0xFFFF, sum = 0
6343 09:27:55.745689 7, 0xFFFF, sum = 0
6344 09:27:55.748840 8, 0xFFFF, sum = 0
6345 09:27:55.748926 9, 0xFFFF, sum = 0
6346 09:27:55.752307 10, 0xFFFF, sum = 0
6347 09:27:55.752413 11, 0xFFFF, sum = 0
6348 09:27:55.755974 12, 0x0, sum = 1
6349 09:27:55.756083 13, 0x0, sum = 2
6350 09:27:55.758893 14, 0x0, sum = 3
6351 09:27:55.758975 15, 0x0, sum = 4
6352 09:27:55.762228 best_step = 13
6353 09:27:55.762309
6354 09:27:55.762372 ==
6355 09:27:55.765743 Dram Type= 6, Freq= 0, CH_0, rank 1
6356 09:27:55.768874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6357 09:27:55.768955 ==
6358 09:27:55.772330 RX Vref Scan: 0
6359 09:27:55.772411
6360 09:27:55.772475 RX Vref 0 -> 0, step: 1
6361 09:27:55.772535
6362 09:27:55.775326 RX Delay -359 -> 252, step: 8
6363 09:27:55.783503 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6364 09:27:55.786341 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6365 09:27:55.789583 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6366 09:27:55.793695 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6367 09:27:55.799875 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6368 09:27:55.803028 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6369 09:27:55.806106 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6370 09:27:55.809513 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6371 09:27:55.816766 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6372 09:27:55.819759 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6373 09:27:55.822806 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6374 09:27:55.829549 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6375 09:27:55.832799 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6376 09:27:55.835983 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6377 09:27:55.839387 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6378 09:27:55.845835 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6379 09:27:55.845916 ==
6380 09:27:55.849234 Dram Type= 6, Freq= 0, CH_0, rank 1
6381 09:27:55.852767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6382 09:27:55.852848 ==
6383 09:27:55.852912 DQS Delay:
6384 09:27:55.855801 DQS0 = 52, DQS1 = 64
6385 09:27:55.855881 DQM Delay:
6386 09:27:55.859339 DQM0 = 9, DQM1 = 13
6387 09:27:55.859420 DQ Delay:
6388 09:27:55.862558 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6389 09:27:55.865874 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6390 09:27:55.869366 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6391 09:27:55.872772 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6392 09:27:55.872853
6393 09:27:55.872935
6394 09:27:55.879079 [DQSOSCAuto] RK1, (LSB)MR18= 0xcaca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6395 09:27:55.882693 CH0 RK1: MR19=C0C, MR18=CACA
6396 09:27:55.889199 CH0_RK1: MR19=0xC0C, MR18=0xCACA, DQSOSC=384, MR23=63, INC=400, DEC=267
6397 09:27:55.892857 [RxdqsGatingPostProcess] freq 400
6398 09:27:55.899050 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6399 09:27:55.899134 Pre-setting of DQS Precalculation
6400 09:27:55.905757 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6401 09:27:55.905838 ==
6402 09:27:55.909362 Dram Type= 6, Freq= 0, CH_1, rank 0
6403 09:27:55.912238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6404 09:27:55.912319 ==
6405 09:27:55.918862 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6406 09:27:55.925440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6407 09:27:55.928899 [CA 0] Center 36 (8~64) winsize 57
6408 09:27:55.932198 [CA 1] Center 36 (8~64) winsize 57
6409 09:27:55.935293 [CA 2] Center 36 (8~64) winsize 57
6410 09:27:55.938553 [CA 3] Center 36 (8~64) winsize 57
6411 09:27:55.942044 [CA 4] Center 36 (8~64) winsize 57
6412 09:27:55.942151 [CA 5] Center 36 (8~64) winsize 57
6413 09:27:55.942242
6414 09:27:55.948800 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6415 09:27:55.948879
6416 09:27:55.951985 [CATrainingPosCal] consider 1 rank data
6417 09:27:55.955530 u2DelayCellTimex100 = 270/100 ps
6418 09:27:55.958625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 09:27:55.962110 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6420 09:27:55.965227 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6421 09:27:55.968386 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6422 09:27:55.972171 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6423 09:27:55.975168 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6424 09:27:55.975249
6425 09:27:55.978690 CA PerBit enable=1, Macro0, CA PI delay=36
6426 09:27:55.978793
6427 09:27:55.982215 [CBTSetCACLKResult] CA Dly = 36
6428 09:27:55.985084 CS Dly: 1 (0~32)
6429 09:27:55.985154 ==
6430 09:27:55.988667 Dram Type= 6, Freq= 0, CH_1, rank 1
6431 09:27:55.992016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 09:27:55.992108 ==
6433 09:27:55.998520 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6434 09:27:56.005210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6435 09:27:56.005287 [CA 0] Center 36 (8~64) winsize 57
6436 09:27:56.008610 [CA 1] Center 36 (8~64) winsize 57
6437 09:27:56.011964 [CA 2] Center 36 (8~64) winsize 57
6438 09:27:56.015131 [CA 3] Center 36 (8~64) winsize 57
6439 09:27:56.018656 [CA 4] Center 36 (8~64) winsize 57
6440 09:27:56.021703 [CA 5] Center 36 (8~64) winsize 57
6441 09:27:56.021802
6442 09:27:56.025265 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6443 09:27:56.025357
6444 09:27:56.028387 [CATrainingPosCal] consider 2 rank data
6445 09:27:56.031556 u2DelayCellTimex100 = 270/100 ps
6446 09:27:56.035093 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 09:27:56.038432 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 09:27:56.044854 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 09:27:56.048194 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 09:27:56.051848 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 09:27:56.055156 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 09:27:56.055252
6453 09:27:56.058205 CA PerBit enable=1, Macro0, CA PI delay=36
6454 09:27:56.058301
6455 09:27:56.061527 [CBTSetCACLKResult] CA Dly = 36
6456 09:27:56.061596 CS Dly: 1 (0~32)
6457 09:27:56.064633
6458 09:27:56.068136 ----->DramcWriteLeveling(PI) begin...
6459 09:27:56.068294 ==
6460 09:27:56.071234 Dram Type= 6, Freq= 0, CH_1, rank 0
6461 09:27:56.074587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6462 09:27:56.074681 ==
6463 09:27:56.078170 Write leveling (Byte 0): 32 => 0
6464 09:27:56.081342 Write leveling (Byte 1): 32 => 0
6465 09:27:56.084524 DramcWriteLeveling(PI) end<-----
6466 09:27:56.084593
6467 09:27:56.084653 ==
6468 09:27:56.087726 Dram Type= 6, Freq= 0, CH_1, rank 0
6469 09:27:56.091162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6470 09:27:56.091232 ==
6471 09:27:56.094446 [Gating] SW mode calibration
6472 09:27:56.101231 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6473 09:27:56.107754 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6474 09:27:56.111128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 09:27:56.114473 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 09:27:56.121237 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 09:27:56.124596 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6478 09:27:56.127906 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 09:27:56.131217 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 09:27:56.137547 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 09:27:56.140726 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6482 09:27:56.144138 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 09:27:56.147697 Total UI for P1: 0, mck2ui 16
6484 09:27:56.150853 best dqsien dly found for B0: ( 0, 10, 16)
6485 09:27:56.154182 Total UI for P1: 0, mck2ui 16
6486 09:27:56.157518 best dqsien dly found for B1: ( 0, 10, 16)
6487 09:27:56.160715 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6488 09:27:56.167447 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6489 09:27:56.167531
6490 09:27:56.170766 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6491 09:27:56.174108 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6492 09:27:56.177232 [Gating] SW calibration Done
6493 09:27:56.177317 ==
6494 09:27:56.180750 Dram Type= 6, Freq= 0, CH_1, rank 0
6495 09:27:56.184045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6496 09:27:56.184130 ==
6497 09:27:56.187318 RX Vref Scan: 0
6498 09:27:56.187402
6499 09:27:56.187488 RX Vref 0 -> 0, step: 1
6500 09:27:56.187570
6501 09:27:56.190493 RX Delay -410 -> 252, step: 16
6502 09:27:56.197236 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6503 09:27:56.200518 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6504 09:27:56.203735 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6505 09:27:56.207074 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6506 09:27:56.213929 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6507 09:27:56.216951 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6508 09:27:56.220414 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6509 09:27:56.223727 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6510 09:27:56.227231 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6511 09:27:56.233655 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6512 09:27:56.237119 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6513 09:27:56.240372 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6514 09:27:56.246883 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6515 09:27:56.250276 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6516 09:27:56.253644 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6517 09:27:56.257164 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6518 09:27:56.257249 ==
6519 09:27:56.260325 Dram Type= 6, Freq= 0, CH_1, rank 0
6520 09:27:56.267236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6521 09:27:56.267338 ==
6522 09:27:56.267429 DQS Delay:
6523 09:27:56.270512 DQS0 = 43, DQS1 = 59
6524 09:27:56.270610 DQM Delay:
6525 09:27:56.270699 DQM0 = 6, DQM1 = 14
6526 09:27:56.273408 DQ Delay:
6527 09:27:56.277086 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6528 09:27:56.280530 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6529 09:27:56.280597 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6530 09:27:56.283517 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =32
6531 09:27:56.286993
6532 09:27:56.287086
6533 09:27:56.287172 ==
6534 09:27:56.290052 Dram Type= 6, Freq= 0, CH_1, rank 0
6535 09:27:56.293285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6536 09:27:56.293353 ==
6537 09:27:56.293413
6538 09:27:56.293470
6539 09:27:56.296773 TX Vref Scan disable
6540 09:27:56.296839 == TX Byte 0 ==
6541 09:27:56.303206 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6542 09:27:56.306643 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6543 09:27:56.306737 == TX Byte 1 ==
6544 09:27:56.313326 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6545 09:27:56.316487 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6546 09:27:56.316582 ==
6547 09:27:56.319770 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 09:27:56.323154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 09:27:56.323227 ==
6550 09:27:56.323288
6551 09:27:56.323346
6552 09:27:56.326340 TX Vref Scan disable
6553 09:27:56.326434 == TX Byte 0 ==
6554 09:27:56.333048 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6555 09:27:56.336440 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6556 09:27:56.336515 == TX Byte 1 ==
6557 09:27:56.343043 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6558 09:27:56.346133 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6559 09:27:56.346227
6560 09:27:56.346315 [DATLAT]
6561 09:27:56.349727 Freq=400, CH1 RK0
6562 09:27:56.349801
6563 09:27:56.349863 DATLAT Default: 0xf
6564 09:27:56.352803 0, 0xFFFF, sum = 0
6565 09:27:56.352876 1, 0xFFFF, sum = 0
6566 09:27:56.356371 2, 0xFFFF, sum = 0
6567 09:27:56.356439 3, 0xFFFF, sum = 0
6568 09:27:56.359581 4, 0xFFFF, sum = 0
6569 09:27:56.362897 5, 0xFFFF, sum = 0
6570 09:27:56.362993 6, 0xFFFF, sum = 0
6571 09:27:56.366305 7, 0xFFFF, sum = 0
6572 09:27:56.366401 8, 0xFFFF, sum = 0
6573 09:27:56.369366 9, 0xFFFF, sum = 0
6574 09:27:56.369437 10, 0xFFFF, sum = 0
6575 09:27:56.372640 11, 0xFFFF, sum = 0
6576 09:27:56.372705 12, 0x0, sum = 1
6577 09:27:56.376508 13, 0x0, sum = 2
6578 09:27:56.376609 14, 0x0, sum = 3
6579 09:27:56.379564 15, 0x0, sum = 4
6580 09:27:56.379661 best_step = 13
6581 09:27:56.379751
6582 09:27:56.379836 ==
6583 09:27:56.383043 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 09:27:56.386097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6585 09:27:56.386171 ==
6586 09:27:56.389754 RX Vref Scan: 1
6587 09:27:56.389826
6588 09:27:56.392991 RX Vref 0 -> 0, step: 1
6589 09:27:56.393063
6590 09:27:56.393124 RX Delay -359 -> 252, step: 8
6591 09:27:56.393184
6592 09:27:56.396371 Set Vref, RX VrefLevel [Byte0]: 54
6593 09:27:56.399533 [Byte1]: 48
6594 09:27:56.404956
6595 09:27:56.405030 Final RX Vref Byte 0 = 54 to rank0
6596 09:27:56.408049 Final RX Vref Byte 1 = 48 to rank0
6597 09:27:56.411199 Final RX Vref Byte 0 = 54 to rank1
6598 09:27:56.414776 Final RX Vref Byte 1 = 48 to rank1==
6599 09:27:56.418165 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 09:27:56.424487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6601 09:27:56.424565 ==
6602 09:27:56.424631 DQS Delay:
6603 09:27:56.427797 DQS0 = 48, DQS1 = 64
6604 09:27:56.427896 DQM Delay:
6605 09:27:56.427986 DQM0 = 9, DQM1 = 16
6606 09:27:56.431456 DQ Delay:
6607 09:27:56.434507 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6608 09:27:56.434606 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6609 09:27:56.437913 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6610 09:27:56.441324 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6611 09:27:56.441431
6612 09:27:56.444375
6613 09:27:56.451197 [DQSOSCAuto] RK0, (LSB)MR18= 0xdbdb, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6614 09:27:56.454297 CH1 RK0: MR19=C0C, MR18=DBDB
6615 09:27:56.461127 CH1_RK0: MR19=0xC0C, MR18=0xDBDB, DQSOSC=382, MR23=63, INC=404, DEC=269
6616 09:27:56.461208 ==
6617 09:27:56.464626 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 09:27:56.467608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6619 09:27:56.467707 ==
6620 09:27:56.470893 [Gating] SW mode calibration
6621 09:27:56.477835 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6622 09:27:56.484438 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6623 09:27:56.487820 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6624 09:27:56.491120 0 7 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6625 09:27:56.494638 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6626 09:27:56.500922 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6627 09:27:56.504477 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6628 09:27:56.507596 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6629 09:27:56.514337 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6630 09:27:56.517561 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6631 09:27:56.521076 Total UI for P1: 0, mck2ui 16
6632 09:27:56.524144 best dqsien dly found for B0: ( 0, 10, 8)
6633 09:27:56.527395 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6634 09:27:56.530888 Total UI for P1: 0, mck2ui 16
6635 09:27:56.534282 best dqsien dly found for B1: ( 0, 10, 16)
6636 09:27:56.537774 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6637 09:27:56.541212 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6638 09:27:56.544327
6639 09:27:56.547348 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6640 09:27:56.551000 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6641 09:27:56.554205 [Gating] SW calibration Done
6642 09:27:56.554290 ==
6643 09:27:56.557490 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 09:27:56.561190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6645 09:27:56.561275 ==
6646 09:27:56.561361 RX Vref Scan: 0
6647 09:27:56.564499
6648 09:27:56.564583 RX Vref 0 -> 0, step: 1
6649 09:27:56.564669
6650 09:27:56.567264 RX Delay -410 -> 252, step: 16
6651 09:27:56.570837 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6652 09:27:56.577488 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6653 09:27:56.581096 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6654 09:27:56.583958 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6655 09:27:56.587092 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6656 09:27:56.594507 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6657 09:27:56.597211 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6658 09:27:56.600513 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6659 09:27:56.603670 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6660 09:27:56.610593 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6661 09:27:56.613925 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6662 09:27:56.617390 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6663 09:27:56.620535 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6664 09:27:56.627000 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6665 09:27:56.630708 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6666 09:27:56.633605 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6667 09:27:56.633686 ==
6668 09:27:56.636948 Dram Type= 6, Freq= 0, CH_1, rank 1
6669 09:27:56.643765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6670 09:27:56.643848 ==
6671 09:27:56.643914 DQS Delay:
6672 09:27:56.646968 DQS0 = 35, DQS1 = 59
6673 09:27:56.647049 DQM Delay:
6674 09:27:56.647115 DQM0 = 3, DQM1 = 18
6675 09:27:56.650503 DQ Delay:
6676 09:27:56.650583 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6677 09:27:56.653697 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6678 09:27:56.657264 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6679 09:27:56.660689 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6680 09:27:56.660771
6681 09:27:56.660835
6682 09:27:56.660895 ==
6683 09:27:56.663926 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 09:27:56.670292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6685 09:27:56.670374 ==
6686 09:27:56.670439
6687 09:27:56.670499
6688 09:27:56.670557 TX Vref Scan disable
6689 09:27:56.673671 == TX Byte 0 ==
6690 09:27:56.677168 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6691 09:27:56.680353 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6692 09:27:56.683502 == TX Byte 1 ==
6693 09:27:56.687109 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6694 09:27:56.690146 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6695 09:27:56.693458 ==
6696 09:27:56.693540 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 09:27:56.700564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6698 09:27:56.700656 ==
6699 09:27:56.700722
6700 09:27:56.700783
6701 09:27:56.703371 TX Vref Scan disable
6702 09:27:56.703452 == TX Byte 0 ==
6703 09:27:56.706707 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6704 09:27:56.713510 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6705 09:27:56.713592 == TX Byte 1 ==
6706 09:27:56.716887 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6707 09:27:56.720295 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6708 09:27:56.723472
6709 09:27:56.723552 [DATLAT]
6710 09:27:56.723617 Freq=400, CH1 RK1
6711 09:27:56.723679
6712 09:27:56.726646 DATLAT Default: 0xd
6713 09:27:56.726728 0, 0xFFFF, sum = 0
6714 09:27:56.730022 1, 0xFFFF, sum = 0
6715 09:27:56.730105 2, 0xFFFF, sum = 0
6716 09:27:56.733121 3, 0xFFFF, sum = 0
6717 09:27:56.736843 4, 0xFFFF, sum = 0
6718 09:27:56.736927 5, 0xFFFF, sum = 0
6719 09:27:56.739816 6, 0xFFFF, sum = 0
6720 09:27:56.739899 7, 0xFFFF, sum = 0
6721 09:27:56.743268 8, 0xFFFF, sum = 0
6722 09:27:56.743352 9, 0xFFFF, sum = 0
6723 09:27:56.746867 10, 0xFFFF, sum = 0
6724 09:27:56.746950 11, 0xFFFF, sum = 0
6725 09:27:56.749900 12, 0x0, sum = 1
6726 09:27:56.749983 13, 0x0, sum = 2
6727 09:27:56.752974 14, 0x0, sum = 3
6728 09:27:56.753057 15, 0x0, sum = 4
6729 09:27:56.756442 best_step = 13
6730 09:27:56.756524
6731 09:27:56.756588 ==
6732 09:27:56.759668 Dram Type= 6, Freq= 0, CH_1, rank 1
6733 09:27:56.763216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6734 09:27:56.763298 ==
6735 09:27:56.763410 RX Vref Scan: 0
6736 09:27:56.763477
6737 09:27:56.766457 RX Vref 0 -> 0, step: 1
6738 09:27:56.766541
6739 09:27:56.769669 RX Delay -359 -> 252, step: 8
6740 09:27:56.776841 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6741 09:27:56.780069 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6742 09:27:56.783742 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6743 09:27:56.786815 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6744 09:27:56.793512 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6745 09:27:56.796670 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6746 09:27:56.799919 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6747 09:27:56.803374 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6748 09:27:56.809830 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6749 09:27:56.813242 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6750 09:27:56.816630 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6751 09:27:56.823289 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6752 09:27:56.826507 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6753 09:27:56.829826 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6754 09:27:56.833299 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6755 09:27:56.839953 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6756 09:27:56.840035 ==
6757 09:27:56.843236 Dram Type= 6, Freq= 0, CH_1, rank 1
6758 09:27:56.846839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6759 09:27:56.846921 ==
6760 09:27:56.846986 DQS Delay:
6761 09:27:56.850053 DQS0 = 48, DQS1 = 64
6762 09:27:56.850135 DQM Delay:
6763 09:27:56.853142 DQM0 = 9, DQM1 = 15
6764 09:27:56.853223 DQ Delay:
6765 09:27:56.856633 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6766 09:27:56.859909 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6767 09:27:56.863076 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6768 09:27:56.866324 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6769 09:27:56.866406
6770 09:27:56.866471
6771 09:27:56.872965 [DQSOSCAuto] RK1, (LSB)MR18= 0xbcbc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6772 09:27:56.876555 CH1 RK1: MR19=C0C, MR18=BCBC
6773 09:27:56.883039 CH1_RK1: MR19=0xC0C, MR18=0xBCBC, DQSOSC=386, MR23=63, INC=396, DEC=264
6774 09:27:56.886149 [RxdqsGatingPostProcess] freq 400
6775 09:27:56.893042 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6776 09:27:56.893124 Pre-setting of DQS Precalculation
6777 09:27:56.899777 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6778 09:27:56.906064 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6779 09:27:56.912760 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6780 09:27:56.912842
6781 09:27:56.912906
6782 09:27:56.916101 [Calibration Summary] 800 Mbps
6783 09:27:56.919352 CH 0, Rank 0
6784 09:27:56.919433 SW Impedance : PASS
6785 09:27:56.922715 DUTY Scan : NO K
6786 09:27:56.926100 ZQ Calibration : PASS
6787 09:27:56.926181 Jitter Meter : NO K
6788 09:27:56.929581 CBT Training : PASS
6789 09:27:56.929662 Write leveling : PASS
6790 09:27:56.932762 RX DQS gating : PASS
6791 09:27:56.936384 RX DQ/DQS(RDDQC) : PASS
6792 09:27:56.936465 TX DQ/DQS : PASS
6793 09:27:56.939258 RX DATLAT : PASS
6794 09:27:56.942945 RX DQ/DQS(Engine): PASS
6795 09:27:56.943027 TX OE : NO K
6796 09:27:56.946155 All Pass.
6797 09:27:56.946236
6798 09:27:56.946300 CH 0, Rank 1
6799 09:27:56.949179 SW Impedance : PASS
6800 09:27:56.949261 DUTY Scan : NO K
6801 09:27:56.952566 ZQ Calibration : PASS
6802 09:27:56.956390 Jitter Meter : NO K
6803 09:27:56.956472 CBT Training : PASS
6804 09:27:56.959351 Write leveling : NO K
6805 09:27:56.962468 RX DQS gating : PASS
6806 09:27:56.962550 RX DQ/DQS(RDDQC) : PASS
6807 09:27:56.965830 TX DQ/DQS : PASS
6808 09:27:56.969178 RX DATLAT : PASS
6809 09:27:56.969260 RX DQ/DQS(Engine): PASS
6810 09:27:56.972463 TX OE : NO K
6811 09:27:56.972544 All Pass.
6812 09:27:56.972609
6813 09:27:56.975796 CH 1, Rank 0
6814 09:27:56.975877 SW Impedance : PASS
6815 09:27:56.979545 DUTY Scan : NO K
6816 09:27:56.982365 ZQ Calibration : PASS
6817 09:27:56.982447 Jitter Meter : NO K
6818 09:27:56.986053 CBT Training : PASS
6819 09:27:56.986135 Write leveling : PASS
6820 09:27:56.989199 RX DQS gating : PASS
6821 09:27:56.992498 RX DQ/DQS(RDDQC) : PASS
6822 09:27:56.992580 TX DQ/DQS : PASS
6823 09:27:56.995638 RX DATLAT : PASS
6824 09:27:56.999195 RX DQ/DQS(Engine): PASS
6825 09:27:56.999276 TX OE : NO K
6826 09:27:57.002470 All Pass.
6827 09:27:57.002551
6828 09:27:57.002616 CH 1, Rank 1
6829 09:27:57.005848 SW Impedance : PASS
6830 09:27:57.005929 DUTY Scan : NO K
6831 09:27:57.009058 ZQ Calibration : PASS
6832 09:27:57.012525 Jitter Meter : NO K
6833 09:27:57.012607 CBT Training : PASS
6834 09:27:57.015562 Write leveling : NO K
6835 09:27:57.018970 RX DQS gating : PASS
6836 09:27:57.019052 RX DQ/DQS(RDDQC) : PASS
6837 09:27:57.022335 TX DQ/DQS : PASS
6838 09:27:57.025557 RX DATLAT : PASS
6839 09:27:57.025639 RX DQ/DQS(Engine): PASS
6840 09:27:57.029087 TX OE : NO K
6841 09:27:57.029168 All Pass.
6842 09:27:57.029233
6843 09:27:57.032230 DramC Write-DBI off
6844 09:27:57.035691 PER_BANK_REFRESH: Hybrid Mode
6845 09:27:57.035774 TX_TRACKING: ON
6846 09:27:57.045559 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6847 09:27:57.048901 [FAST_K] Save calibration result to emmc
6848 09:27:57.052269 dramc_set_vcore_voltage set vcore to 725000
6849 09:27:57.055524 Read voltage for 1600, 0
6850 09:27:57.055606 Vio18 = 0
6851 09:27:57.055670 Vcore = 725000
6852 09:27:57.059054 Vdram = 0
6853 09:27:57.059136 Vddq = 0
6854 09:27:57.059201 Vmddr = 0
6855 09:27:57.065991 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6856 09:27:57.068814 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6857 09:27:57.072119 MEM_TYPE=3, freq_sel=13
6858 09:27:57.075235 sv_algorithm_assistance_LP4_3733
6859 09:27:57.078945 ============ PULL DRAM RESETB DOWN ============
6860 09:27:57.082054 ========== PULL DRAM RESETB DOWN end =========
6861 09:27:57.088851 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6862 09:27:57.092015 ===================================
6863 09:27:57.092123 LPDDR4 DRAM CONFIGURATION
6864 09:27:57.095335 ===================================
6865 09:27:57.098711 EX_ROW_EN[0] = 0x0
6866 09:27:57.102041 EX_ROW_EN[1] = 0x0
6867 09:27:57.102149 LP4Y_EN = 0x0
6868 09:27:57.105226 WORK_FSP = 0x1
6869 09:27:57.105307 WL = 0x5
6870 09:27:57.108690 RL = 0x5
6871 09:27:57.108772 BL = 0x2
6872 09:27:57.111976 RPST = 0x0
6873 09:27:57.112057 RD_PRE = 0x0
6874 09:27:57.115413 WR_PRE = 0x1
6875 09:27:57.115495 WR_PST = 0x1
6876 09:27:57.118501 DBI_WR = 0x0
6877 09:27:57.118583 DBI_RD = 0x0
6878 09:27:57.122103 OTF = 0x1
6879 09:27:57.125248 ===================================
6880 09:27:57.128354 ===================================
6881 09:27:57.128436 ANA top config
6882 09:27:57.132031 ===================================
6883 09:27:57.135351 DLL_ASYNC_EN = 0
6884 09:27:57.138746 ALL_SLAVE_EN = 0
6885 09:27:57.141864 NEW_RANK_MODE = 1
6886 09:27:57.141947 DLL_IDLE_MODE = 1
6887 09:27:57.145383 LP45_APHY_COMB_EN = 1
6888 09:27:57.148499 TX_ODT_DIS = 0
6889 09:27:57.151714 NEW_8X_MODE = 1
6890 09:27:57.154995 ===================================
6891 09:27:57.158188 ===================================
6892 09:27:57.161947 data_rate = 3200
6893 09:27:57.162030 CKR = 1
6894 09:27:57.165209 DQ_P2S_RATIO = 8
6895 09:27:57.168413 ===================================
6896 09:27:57.171642 CA_P2S_RATIO = 8
6897 09:27:57.174966 DQ_CA_OPEN = 0
6898 09:27:57.178296 DQ_SEMI_OPEN = 0
6899 09:27:57.181534 CA_SEMI_OPEN = 0
6900 09:27:57.181616 CA_FULL_RATE = 0
6901 09:27:57.184710 DQ_CKDIV4_EN = 0
6902 09:27:57.188303 CA_CKDIV4_EN = 0
6903 09:27:57.191772 CA_PREDIV_EN = 0
6904 09:27:57.194764 PH8_DLY = 12
6905 09:27:57.198020 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6906 09:27:57.198101 DQ_AAMCK_DIV = 4
6907 09:27:57.201451 CA_AAMCK_DIV = 4
6908 09:27:57.204870 CA_ADMCK_DIV = 4
6909 09:27:57.208064 DQ_TRACK_CA_EN = 0
6910 09:27:57.211483 CA_PICK = 1600
6911 09:27:57.214838 CA_MCKIO = 1600
6912 09:27:57.218269 MCKIO_SEMI = 0
6913 09:27:57.218350 PLL_FREQ = 3068
6914 09:27:57.221435 DQ_UI_PI_RATIO = 32
6915 09:27:57.224672 CA_UI_PI_RATIO = 0
6916 09:27:57.227905 ===================================
6917 09:27:57.231547 ===================================
6918 09:27:57.234552 memory_type:LPDDR4
6919 09:27:57.234633 GP_NUM : 10
6920 09:27:57.237946 SRAM_EN : 1
6921 09:27:57.241502 MD32_EN : 0
6922 09:27:57.244631 ===================================
6923 09:27:57.244713 [ANA_INIT] >>>>>>>>>>>>>>
6924 09:27:57.247798 <<<<<< [CONFIGURE PHASE]: ANA_TX
6925 09:27:57.251199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6926 09:27:57.254407 ===================================
6927 09:27:57.257790 data_rate = 3200,PCW = 0X7600
6928 09:27:57.260908 ===================================
6929 09:27:57.264130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6930 09:27:57.271057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6931 09:27:57.277609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6932 09:27:57.280892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6933 09:27:57.284236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6934 09:27:57.287505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6935 09:27:57.290679 [ANA_INIT] flow start
6936 09:27:57.290763 [ANA_INIT] PLL >>>>>>>>
6937 09:27:57.294068 [ANA_INIT] PLL <<<<<<<<
6938 09:27:57.297337 [ANA_INIT] MIDPI >>>>>>>>
6939 09:27:57.297421 [ANA_INIT] MIDPI <<<<<<<<
6940 09:27:57.300656 [ANA_INIT] DLL >>>>>>>>
6941 09:27:57.303936 [ANA_INIT] DLL <<<<<<<<
6942 09:27:57.304021 [ANA_INIT] flow end
6943 09:27:57.310711 ============ LP4 DIFF to SE enter ============
6944 09:27:57.314014 ============ LP4 DIFF to SE exit ============
6945 09:27:57.317251 [ANA_INIT] <<<<<<<<<<<<<
6946 09:27:57.317335 [Flow] Enable top DCM control >>>>>
6947 09:27:57.321144 [Flow] Enable top DCM control <<<<<
6948 09:27:57.324163 Enable DLL master slave shuffle
6949 09:27:57.330540 ==============================================================
6950 09:27:57.334212 Gating Mode config
6951 09:27:57.337162 ==============================================================
6952 09:27:57.340527 Config description:
6953 09:27:57.350517 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6954 09:27:57.357273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6955 09:27:57.360418 SELPH_MODE 0: By rank 1: By Phase
6956 09:27:57.366878 ==============================================================
6957 09:27:57.370245 GAT_TRACK_EN = 1
6958 09:27:57.373776 RX_GATING_MODE = 2
6959 09:27:57.376848 RX_GATING_TRACK_MODE = 2
6960 09:27:57.376933 SELPH_MODE = 1
6961 09:27:57.380505 PICG_EARLY_EN = 1
6962 09:27:57.383602 VALID_LAT_VALUE = 1
6963 09:27:57.390482 ==============================================================
6964 09:27:57.393584 Enter into Gating configuration >>>>
6965 09:27:57.396829 Exit from Gating configuration <<<<
6966 09:27:57.400389 Enter into DVFS_PRE_config >>>>>
6967 09:27:57.410318 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6968 09:27:57.413432 Exit from DVFS_PRE_config <<<<<
6969 09:27:57.416932 Enter into PICG configuration >>>>
6970 09:27:57.419970 Exit from PICG configuration <<<<
6971 09:27:57.423670 [RX_INPUT] configuration >>>>>
6972 09:27:57.426873 [RX_INPUT] configuration <<<<<
6973 09:27:57.430185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6974 09:27:57.436981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6975 09:27:57.443778 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6976 09:27:57.450132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6977 09:27:57.456535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6978 09:27:57.460054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6979 09:27:57.466705 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6980 09:27:57.469651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6981 09:27:57.473208 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6982 09:27:57.476653 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6983 09:27:57.482924 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6984 09:27:57.486349 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6985 09:27:57.489669 ===================================
6986 09:27:57.493196 LPDDR4 DRAM CONFIGURATION
6987 09:27:57.496210 ===================================
6988 09:27:57.496317 EX_ROW_EN[0] = 0x0
6989 09:27:57.499847 EX_ROW_EN[1] = 0x0
6990 09:27:57.499938 LP4Y_EN = 0x0
6991 09:27:57.503016 WORK_FSP = 0x1
6992 09:27:57.503103 WL = 0x5
6993 09:27:57.506472 RL = 0x5
6994 09:27:57.506557 BL = 0x2
6995 09:27:57.509644 RPST = 0x0
6996 09:27:57.509728 RD_PRE = 0x0
6997 09:27:57.513041 WR_PRE = 0x1
6998 09:27:57.516383 WR_PST = 0x1
6999 09:27:57.516468 DBI_WR = 0x0
7000 09:27:57.519588 DBI_RD = 0x0
7001 09:27:57.519673 OTF = 0x1
7002 09:27:57.522700 ===================================
7003 09:27:57.526095 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7004 09:27:57.529831 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7005 09:27:57.536116 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7006 09:27:57.539351 ===================================
7007 09:27:57.542962 LPDDR4 DRAM CONFIGURATION
7008 09:27:57.545921 ===================================
7009 09:27:57.546005 EX_ROW_EN[0] = 0x10
7010 09:27:57.548993 EX_ROW_EN[1] = 0x0
7011 09:27:57.549077 LP4Y_EN = 0x0
7012 09:27:57.552599 WORK_FSP = 0x1
7013 09:27:57.552683 WL = 0x5
7014 09:27:57.555629 RL = 0x5
7015 09:27:57.555714 BL = 0x2
7016 09:27:57.559134 RPST = 0x0
7017 09:27:57.559218 RD_PRE = 0x0
7018 09:27:57.562625 WR_PRE = 0x1
7019 09:27:57.565716 WR_PST = 0x1
7020 09:27:57.565801 DBI_WR = 0x0
7021 09:27:57.569077 DBI_RD = 0x0
7022 09:27:57.569161 OTF = 0x1
7023 09:27:57.572416 ===================================
7024 09:27:57.578927 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7025 09:27:57.579012 ==
7026 09:27:57.582168 Dram Type= 6, Freq= 0, CH_0, rank 0
7027 09:27:57.585634 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7028 09:27:57.585719 ==
7029 09:27:57.588730 [Duty_Offset_Calibration]
7030 09:27:57.588815 B0:0 B1:2 CA:1
7031 09:27:57.592013
7032 09:27:57.595253 [DutyScan_Calibration_Flow] k_type=0
7033 09:27:57.603585
7034 09:27:57.603669 ==CLK 0==
7035 09:27:57.607273 Final CLK duty delay cell = 0
7036 09:27:57.610200 [0] MAX Duty = 5156%(X100), DQS PI = 22
7037 09:27:57.613726 [0] MIN Duty = 4907%(X100), DQS PI = 52
7038 09:27:57.613810 [0] AVG Duty = 5031%(X100)
7039 09:27:57.616849
7040 09:27:57.620385 CH0 CLK Duty spec in!! Max-Min= 249%
7041 09:27:57.623919 [DutyScan_Calibration_Flow] ====Done====
7042 09:27:57.624003
7043 09:27:57.627202 [DutyScan_Calibration_Flow] k_type=1
7044 09:27:57.643598
7045 09:27:57.643682 ==DQS 0 ==
7046 09:27:57.647046 Final DQS duty delay cell = 0
7047 09:27:57.650226 [0] MAX Duty = 5156%(X100), DQS PI = 34
7048 09:27:57.654261 [0] MIN Duty = 5031%(X100), DQS PI = 10
7049 09:27:57.656926 [0] AVG Duty = 5093%(X100)
7050 09:27:57.657011
7051 09:27:57.657097 ==DQS 1 ==
7052 09:27:57.660518 Final DQS duty delay cell = 0
7053 09:27:57.663733 [0] MAX Duty = 5031%(X100), DQS PI = 4
7054 09:27:57.666999 [0] MIN Duty = 4876%(X100), DQS PI = 16
7055 09:27:57.670293 [0] AVG Duty = 4953%(X100)
7056 09:27:57.670377
7057 09:27:57.673435 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7058 09:27:57.673520
7059 09:27:57.676978 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7060 09:27:57.680467 [DutyScan_Calibration_Flow] ====Done====
7061 09:27:57.680551
7062 09:27:57.683174 [DutyScan_Calibration_Flow] k_type=3
7063 09:27:57.701006
7064 09:27:57.701090 ==DQM 0 ==
7065 09:27:57.704342 Final DQM duty delay cell = 0
7066 09:27:57.707578 [0] MAX Duty = 5187%(X100), DQS PI = 22
7067 09:27:57.710862 [0] MIN Duty = 4907%(X100), DQS PI = 56
7068 09:27:57.710946 [0] AVG Duty = 5047%(X100)
7069 09:27:57.714259
7070 09:27:57.714367 ==DQM 1 ==
7071 09:27:57.717354 Final DQM duty delay cell = 0
7072 09:27:57.720903 [0] MAX Duty = 5031%(X100), DQS PI = 50
7073 09:27:57.724278 [0] MIN Duty = 4782%(X100), DQS PI = 12
7074 09:27:57.727329 [0] AVG Duty = 4906%(X100)
7075 09:27:57.727414
7076 09:27:57.730684 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7077 09:27:57.730768
7078 09:27:57.733985 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7079 09:27:57.737296 [DutyScan_Calibration_Flow] ====Done====
7080 09:27:57.737381
7081 09:27:57.740699 [DutyScan_Calibration_Flow] k_type=2
7082 09:27:57.757241
7083 09:27:57.757326 ==DQ 0 ==
7084 09:27:57.760582 Final DQ duty delay cell = 0
7085 09:27:57.764312 [0] MAX Duty = 5218%(X100), DQS PI = 18
7086 09:27:57.767373 [0] MIN Duty = 4938%(X100), DQS PI = 56
7087 09:27:57.767458 [0] AVG Duty = 5078%(X100)
7088 09:27:57.767543
7089 09:27:57.770897 ==DQ 1 ==
7090 09:27:57.774359 Final DQ duty delay cell = -4
7091 09:27:57.777392 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7092 09:27:57.780804 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7093 09:27:57.783705 [-4] AVG Duty = 4969%(X100)
7094 09:27:57.783790
7095 09:27:57.787596 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7096 09:27:57.787680
7097 09:27:57.790650 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7098 09:27:57.793735 [DutyScan_Calibration_Flow] ====Done====
7099 09:27:57.793820 ==
7100 09:27:57.797262 Dram Type= 6, Freq= 0, CH_1, rank 0
7101 09:27:57.800414 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7102 09:27:57.800505 ==
7103 09:27:57.803775 [Duty_Offset_Calibration]
7104 09:27:57.803859 B0:0 B1:4 CA:-5
7105 09:27:57.803945
7106 09:27:57.806884 [DutyScan_Calibration_Flow] k_type=0
7107 09:27:57.817924
7108 09:27:57.818008 ==CLK 0==
7109 09:27:57.821413 Final CLK duty delay cell = 0
7110 09:27:57.824477 [0] MAX Duty = 5156%(X100), DQS PI = 20
7111 09:27:57.827638 [0] MIN Duty = 4875%(X100), DQS PI = 50
7112 09:27:57.827723 [0] AVG Duty = 5015%(X100)
7113 09:27:57.830969
7114 09:27:57.834284 CH1 CLK Duty spec in!! Max-Min= 281%
7115 09:27:57.837806 [DutyScan_Calibration_Flow] ====Done====
7116 09:27:57.837891
7117 09:27:57.840964 [DutyScan_Calibration_Flow] k_type=1
7118 09:27:57.856628
7119 09:27:57.856713 ==DQS 0 ==
7120 09:27:57.860170 Final DQS duty delay cell = 0
7121 09:27:57.863454 [0] MAX Duty = 5156%(X100), DQS PI = 18
7122 09:27:57.866590 [0] MIN Duty = 4844%(X100), DQS PI = 44
7123 09:27:57.870695 [0] AVG Duty = 5000%(X100)
7124 09:27:57.870779
7125 09:27:57.870865 ==DQS 1 ==
7126 09:27:57.873617 Final DQS duty delay cell = -4
7127 09:27:57.876855 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7128 09:27:57.880191 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7129 09:27:57.883567 [-4] AVG Duty = 4922%(X100)
7130 09:27:57.883652
7131 09:27:57.886546 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7132 09:27:57.886630
7133 09:27:57.890062 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7134 09:27:57.893224 [DutyScan_Calibration_Flow] ====Done====
7135 09:27:57.893308
7136 09:27:57.896799 [DutyScan_Calibration_Flow] k_type=3
7137 09:27:57.912438
7138 09:27:57.912522 ==DQM 0 ==
7139 09:27:57.916000 Final DQM duty delay cell = -4
7140 09:27:57.918924 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7141 09:27:57.922615 [-4] MIN Duty = 4813%(X100), DQS PI = 40
7142 09:27:57.925683 [-4] AVG Duty = 4937%(X100)
7143 09:27:57.925767
7144 09:27:57.925854 ==DQM 1 ==
7145 09:27:57.929438 Final DQM duty delay cell = -4
7146 09:27:57.932551 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7147 09:27:57.935501 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7148 09:27:57.939045 [-4] AVG Duty = 5000%(X100)
7149 09:27:57.939129
7150 09:27:57.942133 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7151 09:27:57.942218
7152 09:27:57.945508 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7153 09:27:57.948843 [DutyScan_Calibration_Flow] ====Done====
7154 09:27:57.948928
7155 09:27:57.952085 [DutyScan_Calibration_Flow] k_type=2
7156 09:27:57.970068
7157 09:27:57.970151 ==DQ 0 ==
7158 09:27:57.973419 Final DQ duty delay cell = 0
7159 09:27:57.976911 [0] MAX Duty = 5093%(X100), DQS PI = 20
7160 09:27:57.980131 [0] MIN Duty = 4969%(X100), DQS PI = 46
7161 09:27:57.980255 [0] AVG Duty = 5031%(X100)
7162 09:27:57.983440
7163 09:27:57.983524 ==DQ 1 ==
7164 09:27:57.986689 Final DQ duty delay cell = 0
7165 09:27:57.990041 [0] MAX Duty = 5031%(X100), DQS PI = 2
7166 09:27:57.993518 [0] MIN Duty = 4876%(X100), DQS PI = 26
7167 09:27:57.993603 [0] AVG Duty = 4953%(X100)
7168 09:27:57.993689
7169 09:27:57.996611 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7170 09:27:58.000063
7171 09:27:58.003129 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7172 09:27:58.006870 [DutyScan_Calibration_Flow] ====Done====
7173 09:27:58.009725 nWR fixed to 30
7174 09:27:58.009811 [ModeRegInit_LP4] CH0 RK0
7175 09:27:58.013112 [ModeRegInit_LP4] CH0 RK1
7176 09:27:58.016457 [ModeRegInit_LP4] CH1 RK0
7177 09:27:58.019604 [ModeRegInit_LP4] CH1 RK1
7178 09:27:58.019689 match AC timing 4
7179 09:27:58.026355 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7180 09:27:58.029417 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7181 09:27:58.032691 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7182 09:27:58.039657 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7183 09:27:58.043003 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7184 09:27:58.043088 [MiockJmeterHQA]
7185 09:27:58.043176
7186 09:27:58.046014 [DramcMiockJmeter] u1RxGatingPI = 0
7187 09:27:58.049609 0 : 4253, 4026
7188 09:27:58.049696 4 : 4363, 4137
7189 09:27:58.052770 8 : 4252, 4027
7190 09:27:58.052856 12 : 4253, 4026
7191 09:27:58.052943 16 : 4252, 4027
7192 09:27:58.056035 20 : 4255, 4029
7193 09:27:58.056120 24 : 4363, 4137
7194 09:27:58.059400 28 : 4252, 4026
7195 09:27:58.059486 32 : 4363, 4138
7196 09:27:58.062671 36 : 4252, 4027
7197 09:27:58.062756 40 : 4252, 4027
7198 09:27:58.066036 44 : 4253, 4027
7199 09:27:58.066122 48 : 4363, 4137
7200 09:27:58.066225 52 : 4252, 4027
7201 09:27:58.069322 56 : 4252, 4027
7202 09:27:58.069404 60 : 4253, 4026
7203 09:27:58.072637 64 : 4253, 4027
7204 09:27:58.072719 68 : 4252, 4030
7205 09:27:58.076435 72 : 4252, 4027
7206 09:27:58.076518 76 : 4361, 4137
7207 09:27:58.079019 80 : 4250, 4026
7208 09:27:58.079102 84 : 4360, 4138
7209 09:27:58.079167 88 : 4250, 4027
7210 09:27:58.082557 92 : 4250, 4027
7211 09:27:58.082640 96 : 4250, 4027
7212 09:27:58.085897 100 : 4361, 3691
7213 09:27:58.085980 104 : 4250, 0
7214 09:27:58.089264 108 : 4250, 0
7215 09:27:58.089347 112 : 4250, 0
7216 09:27:58.089413 116 : 4250, 0
7217 09:27:58.092418 120 : 4361, 0
7218 09:27:58.092500 124 : 4250, 0
7219 09:27:58.092566 128 : 4250, 0
7220 09:27:58.095757 132 : 4252, 0
7221 09:27:58.095843 136 : 4360, 0
7222 09:27:58.099348 140 : 4361, 0
7223 09:27:58.099433 144 : 4250, 0
7224 09:27:58.099521 148 : 4361, 0
7225 09:27:58.102654 152 : 4250, 0
7226 09:27:58.102739 156 : 4250, 0
7227 09:27:58.106210 160 : 4250, 0
7228 09:27:58.106295 164 : 4250, 0
7229 09:27:58.106383 168 : 4252, 0
7230 09:27:58.109544 172 : 4250, 0
7231 09:27:58.109629 176 : 4250, 0
7232 09:27:58.112427 180 : 4253, 0
7233 09:27:58.112513 184 : 4250, 0
7234 09:27:58.112600 188 : 4361, 0
7235 09:27:58.115725 192 : 4360, 0
7236 09:27:58.115811 196 : 4250, 0
7237 09:27:58.115899 200 : 4360, 0
7238 09:27:58.119115 204 : 4250, 0
7239 09:27:58.119200 208 : 4250, 0
7240 09:27:58.122359 212 : 4250, 0
7241 09:27:58.122469 216 : 4250, 0
7242 09:27:58.122556 220 : 4252, 81
7243 09:27:58.125852 224 : 4250, 3763
7244 09:27:58.125937 228 : 4361, 4137
7245 09:27:58.129069 232 : 4250, 4026
7246 09:27:58.129154 236 : 4250, 4027
7247 09:27:58.132213 240 : 4360, 4138
7248 09:27:58.132299 244 : 4361, 4137
7249 09:27:58.135535 248 : 4250, 4026
7250 09:27:58.135620 252 : 4363, 4140
7251 09:27:58.139099 256 : 4361, 4137
7252 09:27:58.139184 260 : 4249, 4027
7253 09:27:58.142159 264 : 4250, 4026
7254 09:27:58.142245 268 : 4253, 4029
7255 09:27:58.145551 272 : 4250, 4027
7256 09:27:58.145637 276 : 4250, 4027
7257 09:27:58.145724 280 : 4250, 4026
7258 09:27:58.148824 284 : 4253, 4029
7259 09:27:58.148910 288 : 4250, 4027
7260 09:27:58.152201 292 : 4361, 4137
7261 09:27:58.152299 296 : 4360, 4137
7262 09:27:58.155596 300 : 4250, 4026
7263 09:27:58.155682 304 : 4363, 4140
7264 09:27:58.158985 308 : 4250, 4027
7265 09:27:58.159070 312 : 4249, 4027
7266 09:27:58.162280 316 : 4250, 4027
7267 09:27:58.162366 320 : 4253, 4029
7268 09:27:58.165523 324 : 4250, 4027
7269 09:27:58.165609 328 : 4249, 4027
7270 09:27:58.168777 332 : 4250, 4026
7271 09:27:58.168863 336 : 4253, 4012
7272 09:27:58.168950 340 : 4250, 2260
7273 09:27:58.172035 344 : 4360, 0
7274 09:27:58.172120
7275 09:27:58.175801 MIOCK jitter meter ch=0
7276 09:27:58.175886
7277 09:27:58.175972 1T = (344-104) = 240 dly cells
7278 09:27:58.182481 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7279 09:27:58.182566 ==
7280 09:27:58.185360 Dram Type= 6, Freq= 0, CH_0, rank 0
7281 09:27:58.188903 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7282 09:27:58.192125 ==
7283 09:27:58.195305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7284 09:27:58.199049 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7285 09:27:58.205209 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7286 09:27:58.211811 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7287 09:27:58.218420 [CA 0] Center 42 (12~72) winsize 61
7288 09:27:58.221628 [CA 1] Center 41 (11~72) winsize 62
7289 09:27:58.225280 [CA 2] Center 37 (7~68) winsize 62
7290 09:27:58.228466 [CA 3] Center 37 (7~67) winsize 61
7291 09:27:58.231929 [CA 4] Center 35 (5~66) winsize 62
7292 09:27:58.235087 [CA 5] Center 35 (5~65) winsize 61
7293 09:27:58.235187
7294 09:27:58.238872 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7295 09:27:58.238956
7296 09:27:58.241697 [CATrainingPosCal] consider 1 rank data
7297 09:27:58.244923 u2DelayCellTimex100 = 271/100 ps
7298 09:27:58.248546 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7299 09:27:58.255125 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7300 09:27:58.258471 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7301 09:27:58.261751 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7302 09:27:58.265227 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7303 09:27:58.268343 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7304 09:27:58.268428
7305 09:27:58.271703 CA PerBit enable=1, Macro0, CA PI delay=35
7306 09:27:58.271787
7307 09:27:58.275189 [CBTSetCACLKResult] CA Dly = 35
7308 09:27:58.278370 CS Dly: 11 (0~42)
7309 09:27:58.281686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7310 09:27:58.284743 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7311 09:27:58.284827 ==
7312 09:27:58.288387 Dram Type= 6, Freq= 0, CH_0, rank 1
7313 09:27:58.291388 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7314 09:27:58.294929 ==
7315 09:27:58.298154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7316 09:27:58.301396 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7317 09:27:58.307972 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7318 09:27:58.311817 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7319 09:27:58.321043 [CA 0] Center 42 (12~73) winsize 62
7320 09:27:58.324518 [CA 1] Center 41 (11~72) winsize 62
7321 09:27:58.327616 [CA 2] Center 38 (9~68) winsize 60
7322 09:27:58.330786 [CA 3] Center 37 (8~67) winsize 60
7323 09:27:58.334383 [CA 4] Center 35 (5~65) winsize 61
7324 09:27:58.337416 [CA 5] Center 35 (5~66) winsize 62
7325 09:27:58.337500
7326 09:27:58.340988 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7327 09:27:58.341072
7328 09:27:58.344404 [CATrainingPosCal] consider 2 rank data
7329 09:27:58.347351 u2DelayCellTimex100 = 271/100 ps
7330 09:27:58.350796 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7331 09:27:58.357459 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7332 09:27:58.360716 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7333 09:27:58.364338 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7334 09:27:58.367422 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7335 09:27:58.370641 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7336 09:27:58.370722
7337 09:27:58.374214 CA PerBit enable=1, Macro0, CA PI delay=35
7338 09:27:58.374295
7339 09:27:58.377509 [CBTSetCACLKResult] CA Dly = 35
7340 09:27:58.380575 CS Dly: 11 (0~43)
7341 09:27:58.384045 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7342 09:27:58.387278 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7343 09:27:58.387360
7344 09:27:58.390997 ----->DramcWriteLeveling(PI) begin...
7345 09:27:58.391080 ==
7346 09:27:58.394040 Dram Type= 6, Freq= 0, CH_0, rank 0
7347 09:27:58.400767 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7348 09:27:58.400849 ==
7349 09:27:58.403918 Write leveling (Byte 0): 28 => 28
7350 09:27:58.404002 Write leveling (Byte 1): 25 => 25
7351 09:27:58.407321 DramcWriteLeveling(PI) end<-----
7352 09:27:58.407403
7353 09:27:58.410656 ==
7354 09:27:58.410737 Dram Type= 6, Freq= 0, CH_0, rank 0
7355 09:27:58.417367 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7356 09:27:58.417448 ==
7357 09:27:58.420442 [Gating] SW mode calibration
7358 09:27:58.427329 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7359 09:27:58.430833 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7360 09:27:58.437275 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7361 09:27:58.440804 0 12 4 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
7362 09:27:58.444203 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7363 09:27:58.450506 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7364 09:27:58.453769 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7365 09:27:58.457211 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7366 09:27:58.463908 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7367 09:27:58.467100 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7368 09:27:58.470298 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7369 09:27:58.477060 0 13 4 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 1)
7370 09:27:58.480351 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7371 09:27:58.483618 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7372 09:27:58.487265 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7373 09:27:58.493705 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7374 09:27:58.497058 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7375 09:27:58.500321 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7376 09:27:58.506877 0 14 0 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7377 09:27:58.510458 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
7378 09:27:58.513290 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7379 09:27:58.520518 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7380 09:27:58.523567 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7381 09:27:58.526683 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7382 09:27:58.533816 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7383 09:27:58.536571 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7384 09:27:58.540040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7385 09:27:58.546373 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7386 09:27:58.549710 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7387 09:27:58.553310 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7388 09:27:58.559950 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7389 09:27:58.563184 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7390 09:27:58.566548 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7391 09:27:58.573003 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7392 09:27:58.576276 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7393 09:27:58.579668 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7394 09:27:58.586358 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7395 09:27:58.589526 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7396 09:27:58.592882 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 09:27:58.599661 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 09:27:58.602881 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 09:27:58.606183 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7400 09:27:58.612890 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7401 09:27:58.615755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7402 09:27:58.619102 Total UI for P1: 0, mck2ui 16
7403 09:27:58.622474 best dqsien dly found for B0: ( 1, 0, 30)
7404 09:27:58.626016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7405 09:27:58.632471 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 09:27:58.632554 Total UI for P1: 0, mck2ui 16
7407 09:27:58.639063 best dqsien dly found for B1: ( 1, 1, 6)
7408 09:27:58.642184 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7409 09:27:58.645625 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7410 09:27:58.645707
7411 09:27:58.649189 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7412 09:27:58.652271 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7413 09:27:58.655764 [Gating] SW calibration Done
7414 09:27:58.655870 ==
7415 09:27:58.658909 Dram Type= 6, Freq= 0, CH_0, rank 0
7416 09:27:58.662352 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7417 09:27:58.662435 ==
7418 09:27:58.665405 RX Vref Scan: 0
7419 09:27:58.665486
7420 09:27:58.665550 RX Vref 0 -> 0, step: 1
7421 09:27:58.665611
7422 09:27:58.668921 RX Delay 0 -> 252, step: 8
7423 09:27:58.671969 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7424 09:27:58.678482 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7425 09:27:58.681911 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7426 09:27:58.685140 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7427 09:27:58.688835 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7428 09:27:58.691943 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7429 09:27:58.698480 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7430 09:27:58.701972 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7431 09:27:58.705151 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7432 09:27:58.708596 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7433 09:27:58.711932 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7434 09:27:58.718451 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7435 09:27:58.721852 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7436 09:27:58.724970 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7437 09:27:58.728339 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7438 09:27:58.735011 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7439 09:27:58.735092 ==
7440 09:27:58.738257 Dram Type= 6, Freq= 0, CH_0, rank 0
7441 09:27:58.742153 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7442 09:27:58.742236 ==
7443 09:27:58.742301 DQS Delay:
7444 09:27:58.744988 DQS0 = 0, DQS1 = 0
7445 09:27:58.745070 DQM Delay:
7446 09:27:58.748212 DQM0 = 130, DQM1 = 124
7447 09:27:58.748307 DQ Delay:
7448 09:27:58.751730 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7449 09:27:58.755081 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7450 09:27:58.758141 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7451 09:27:58.761536 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7452 09:27:58.761650
7453 09:27:58.761717
7454 09:27:58.764742 ==
7455 09:27:58.764823 Dram Type= 6, Freq= 0, CH_0, rank 0
7456 09:27:58.771246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7457 09:27:58.771329 ==
7458 09:27:58.771404
7459 09:27:58.771469
7460 09:27:58.774446 TX Vref Scan disable
7461 09:27:58.774528 == TX Byte 0 ==
7462 09:27:58.777640 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7463 09:27:58.784665 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7464 09:27:58.784747 == TX Byte 1 ==
7465 09:27:58.791293 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7466 09:27:58.794133 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7467 09:27:58.794215 ==
7468 09:27:58.797628 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 09:27:58.800629 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7470 09:27:58.800711 ==
7471 09:27:58.814398
7472 09:27:58.817636 TX Vref early break, caculate TX vref
7473 09:27:58.821106 TX Vref=16, minBit 8, minWin=21, winSum=367
7474 09:27:58.824303 TX Vref=18, minBit 4, minWin=23, winSum=380
7475 09:27:58.827474 TX Vref=20, minBit 8, minWin=23, winSum=389
7476 09:27:58.830886 TX Vref=22, minBit 8, minWin=24, winSum=396
7477 09:27:58.833900 TX Vref=24, minBit 8, minWin=24, winSum=408
7478 09:27:58.840609 TX Vref=26, minBit 8, minWin=25, winSum=414
7479 09:27:58.843795 TX Vref=28, minBit 8, minWin=25, winSum=419
7480 09:27:58.847435 TX Vref=30, minBit 6, minWin=24, winSum=412
7481 09:27:58.850647 TX Vref=32, minBit 1, minWin=24, winSum=402
7482 09:27:58.853653 TX Vref=34, minBit 3, minWin=24, winSum=396
7483 09:27:58.860350 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
7484 09:27:58.860432
7485 09:27:58.863973 Final TX Range 0 Vref 28
7486 09:27:58.864080
7487 09:27:58.864178 ==
7488 09:27:58.866994 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 09:27:58.870145 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7490 09:27:58.870228 ==
7491 09:27:58.870293
7492 09:27:58.870353
7493 09:27:58.873618 TX Vref Scan disable
7494 09:27:58.880372 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7495 09:27:58.880454 == TX Byte 0 ==
7496 09:27:58.883351 u2DelayCellOfst[0]=14 cells (4 PI)
7497 09:27:58.886743 u2DelayCellOfst[1]=21 cells (6 PI)
7498 09:27:58.890258 u2DelayCellOfst[2]=18 cells (5 PI)
7499 09:27:58.893192 u2DelayCellOfst[3]=14 cells (4 PI)
7500 09:27:58.896676 u2DelayCellOfst[4]=10 cells (3 PI)
7501 09:27:58.900112 u2DelayCellOfst[5]=0 cells (0 PI)
7502 09:27:58.903489 u2DelayCellOfst[6]=21 cells (6 PI)
7503 09:27:58.906451 u2DelayCellOfst[7]=21 cells (6 PI)
7504 09:27:58.909810 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7505 09:27:58.913412 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7506 09:27:58.916490 == TX Byte 1 ==
7507 09:27:58.919836 u2DelayCellOfst[8]=3 cells (1 PI)
7508 09:27:58.923193 u2DelayCellOfst[9]=0 cells (0 PI)
7509 09:27:58.926407 u2DelayCellOfst[10]=10 cells (3 PI)
7510 09:27:58.926489 u2DelayCellOfst[11]=3 cells (1 PI)
7511 09:27:58.929749 u2DelayCellOfst[12]=14 cells (4 PI)
7512 09:27:58.933150 u2DelayCellOfst[13]=14 cells (4 PI)
7513 09:27:58.936568 u2DelayCellOfst[14]=18 cells (5 PI)
7514 09:27:58.939698 u2DelayCellOfst[15]=14 cells (4 PI)
7515 09:27:58.946134 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7516 09:27:58.949656 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7517 09:27:58.949738 DramC Write-DBI on
7518 09:27:58.949803 ==
7519 09:27:58.952766 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 09:27:58.959478 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7521 09:27:58.959563 ==
7522 09:27:58.959649
7523 09:27:58.959730
7524 09:27:58.963087 TX Vref Scan disable
7525 09:27:58.963171 == TX Byte 0 ==
7526 09:27:58.969421 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7527 09:27:58.969506 == TX Byte 1 ==
7528 09:27:58.972632 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7529 09:27:58.975941 DramC Write-DBI off
7530 09:27:58.976023
7531 09:27:58.976087 [DATLAT]
7532 09:27:58.979292 Freq=1600, CH0 RK0
7533 09:27:58.979374
7534 09:27:58.979439 DATLAT Default: 0xf
7535 09:27:58.982539 0, 0xFFFF, sum = 0
7536 09:27:58.982622 1, 0xFFFF, sum = 0
7537 09:27:58.985717 2, 0xFFFF, sum = 0
7538 09:27:58.985800 3, 0xFFFF, sum = 0
7539 09:27:58.989084 4, 0xFFFF, sum = 0
7540 09:27:58.989167 5, 0xFFFF, sum = 0
7541 09:27:58.992372 6, 0xFFFF, sum = 0
7542 09:27:58.992455 7, 0xFFFF, sum = 0
7543 09:27:58.995638 8, 0xFFFF, sum = 0
7544 09:27:58.995721 9, 0xFFFF, sum = 0
7545 09:27:58.999187 10, 0xFFFF, sum = 0
7546 09:27:59.002422 11, 0xFFFF, sum = 0
7547 09:27:59.002505 12, 0xFFF, sum = 0
7548 09:27:59.006013 13, 0x0, sum = 1
7549 09:27:59.006095 14, 0x0, sum = 2
7550 09:27:59.008939 15, 0x0, sum = 3
7551 09:27:59.009021 16, 0x0, sum = 4
7552 09:27:59.009087 best_step = 14
7553 09:27:59.009148
7554 09:27:59.012350 ==
7555 09:27:59.016039 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 09:27:59.019078 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7557 09:27:59.019160 ==
7558 09:27:59.019225 RX Vref Scan: 1
7559 09:27:59.019286
7560 09:27:59.022314 Set Vref Range= 24 -> 127
7561 09:27:59.022399
7562 09:27:59.025819 RX Vref 24 -> 127, step: 1
7563 09:27:59.025900
7564 09:27:59.029109 RX Delay 11 -> 252, step: 4
7565 09:27:59.029191
7566 09:27:59.032125 Set Vref, RX VrefLevel [Byte0]: 24
7567 09:27:59.035449 [Byte1]: 24
7568 09:27:59.035530
7569 09:27:59.038787 Set Vref, RX VrefLevel [Byte0]: 25
7570 09:27:59.042082 [Byte1]: 25
7571 09:27:59.042164
7572 09:27:59.045512 Set Vref, RX VrefLevel [Byte0]: 26
7573 09:27:59.048903 [Byte1]: 26
7574 09:27:59.052667
7575 09:27:59.052748 Set Vref, RX VrefLevel [Byte0]: 27
7576 09:27:59.055703 [Byte1]: 27
7577 09:27:59.060133
7578 09:27:59.060252 Set Vref, RX VrefLevel [Byte0]: 28
7579 09:27:59.063170 [Byte1]: 28
7580 09:27:59.067427
7581 09:27:59.067508 Set Vref, RX VrefLevel [Byte0]: 29
7582 09:27:59.071235 [Byte1]: 29
7583 09:27:59.075171
7584 09:27:59.075252 Set Vref, RX VrefLevel [Byte0]: 30
7585 09:27:59.078542 [Byte1]: 30
7586 09:27:59.082679
7587 09:27:59.082760 Set Vref, RX VrefLevel [Byte0]: 31
7588 09:27:59.085873 [Byte1]: 31
7589 09:27:59.090451
7590 09:27:59.090532 Set Vref, RX VrefLevel [Byte0]: 32
7591 09:27:59.093651 [Byte1]: 32
7592 09:27:59.098387
7593 09:27:59.098468 Set Vref, RX VrefLevel [Byte0]: 33
7594 09:27:59.101592 [Byte1]: 33
7595 09:27:59.105659
7596 09:27:59.105740 Set Vref, RX VrefLevel [Byte0]: 34
7597 09:27:59.108768 [Byte1]: 34
7598 09:27:59.113020
7599 09:27:59.113102 Set Vref, RX VrefLevel [Byte0]: 35
7600 09:27:59.116379 [Byte1]: 35
7601 09:27:59.120772
7602 09:27:59.120853 Set Vref, RX VrefLevel [Byte0]: 36
7603 09:27:59.124327 [Byte1]: 36
7604 09:27:59.128350
7605 09:27:59.128431 Set Vref, RX VrefLevel [Byte0]: 37
7606 09:27:59.134741 [Byte1]: 37
7607 09:27:59.134823
7608 09:27:59.138621 Set Vref, RX VrefLevel [Byte0]: 38
7609 09:27:59.141501 [Byte1]: 38
7610 09:27:59.141583
7611 09:27:59.144832 Set Vref, RX VrefLevel [Byte0]: 39
7612 09:27:59.148181 [Byte1]: 39
7613 09:27:59.148277
7614 09:27:59.151536 Set Vref, RX VrefLevel [Byte0]: 40
7615 09:27:59.154741 [Byte1]: 40
7616 09:27:59.158882
7617 09:27:59.158980 Set Vref, RX VrefLevel [Byte0]: 41
7618 09:27:59.162024 [Byte1]: 41
7619 09:27:59.166329
7620 09:27:59.166411 Set Vref, RX VrefLevel [Byte0]: 42
7621 09:27:59.169610 [Byte1]: 42
7622 09:27:59.173877
7623 09:27:59.173958 Set Vref, RX VrefLevel [Byte0]: 43
7624 09:27:59.177468 [Byte1]: 43
7625 09:27:59.181833
7626 09:27:59.181914 Set Vref, RX VrefLevel [Byte0]: 44
7627 09:27:59.184993 [Byte1]: 44
7628 09:27:59.189443
7629 09:27:59.189524 Set Vref, RX VrefLevel [Byte0]: 45
7630 09:27:59.192871 [Byte1]: 45
7631 09:27:59.196810
7632 09:27:59.196891 Set Vref, RX VrefLevel [Byte0]: 46
7633 09:27:59.200394 [Byte1]: 46
7634 09:27:59.204606
7635 09:27:59.204687 Set Vref, RX VrefLevel [Byte0]: 47
7636 09:27:59.207630 [Byte1]: 47
7637 09:27:59.212003
7638 09:27:59.212084 Set Vref, RX VrefLevel [Byte0]: 48
7639 09:27:59.215237 [Byte1]: 48
7640 09:27:59.219689
7641 09:27:59.219770 Set Vref, RX VrefLevel [Byte0]: 49
7642 09:27:59.223062 [Byte1]: 49
7643 09:27:59.227711
7644 09:27:59.227792 Set Vref, RX VrefLevel [Byte0]: 50
7645 09:27:59.233681 [Byte1]: 50
7646 09:27:59.233763
7647 09:27:59.237478 Set Vref, RX VrefLevel [Byte0]: 51
7648 09:27:59.240434 [Byte1]: 51
7649 09:27:59.240516
7650 09:27:59.244084 Set Vref, RX VrefLevel [Byte0]: 52
7651 09:27:59.247103 [Byte1]: 52
7652 09:27:59.247184
7653 09:27:59.250398 Set Vref, RX VrefLevel [Byte0]: 53
7654 09:27:59.253648 [Byte1]: 53
7655 09:27:59.257910
7656 09:27:59.257991 Set Vref, RX VrefLevel [Byte0]: 54
7657 09:27:59.261084 [Byte1]: 54
7658 09:27:59.265373
7659 09:27:59.265453 Set Vref, RX VrefLevel [Byte0]: 55
7660 09:27:59.268757 [Byte1]: 55
7661 09:27:59.272932
7662 09:27:59.273013 Set Vref, RX VrefLevel [Byte0]: 56
7663 09:27:59.276331 [Byte1]: 56
7664 09:27:59.280830
7665 09:27:59.280911 Set Vref, RX VrefLevel [Byte0]: 57
7666 09:27:59.283858 [Byte1]: 57
7667 09:27:59.288125
7668 09:27:59.288213 Set Vref, RX VrefLevel [Byte0]: 58
7669 09:27:59.291840 [Byte1]: 58
7670 09:27:59.296062
7671 09:27:59.296143 Set Vref, RX VrefLevel [Byte0]: 59
7672 09:27:59.299077 [Byte1]: 59
7673 09:27:59.303411
7674 09:27:59.303492 Set Vref, RX VrefLevel [Byte0]: 60
7675 09:27:59.306866 [Byte1]: 60
7676 09:27:59.311055
7677 09:27:59.311136 Set Vref, RX VrefLevel [Byte0]: 61
7678 09:27:59.314499 [Byte1]: 61
7679 09:27:59.318718
7680 09:27:59.318799 Set Vref, RX VrefLevel [Byte0]: 62
7681 09:27:59.322166 [Byte1]: 62
7682 09:27:59.327162
7683 09:27:59.327243 Set Vref, RX VrefLevel [Byte0]: 63
7684 09:27:59.329960 [Byte1]: 63
7685 09:27:59.333958
7686 09:27:59.334039 Set Vref, RX VrefLevel [Byte0]: 64
7687 09:27:59.337181 [Byte1]: 64
7688 09:27:59.341368
7689 09:27:59.341449 Set Vref, RX VrefLevel [Byte0]: 65
7690 09:27:59.344790 [Byte1]: 65
7691 09:27:59.349202
7692 09:27:59.349283 Set Vref, RX VrefLevel [Byte0]: 66
7693 09:27:59.352365 [Byte1]: 66
7694 09:27:59.357141
7695 09:27:59.357222 Set Vref, RX VrefLevel [Byte0]: 67
7696 09:27:59.360228 [Byte1]: 67
7697 09:27:59.364225
7698 09:27:59.364306 Set Vref, RX VrefLevel [Byte0]: 68
7699 09:27:59.367745 [Byte1]: 68
7700 09:27:59.372465
7701 09:27:59.372546 Set Vref, RX VrefLevel [Byte0]: 69
7702 09:27:59.375598 [Byte1]: 69
7703 09:27:59.379677
7704 09:27:59.379758 Final RX Vref Byte 0 = 51 to rank0
7705 09:27:59.382891 Final RX Vref Byte 1 = 55 to rank0
7706 09:27:59.386448 Final RX Vref Byte 0 = 51 to rank1
7707 09:27:59.389992 Final RX Vref Byte 1 = 55 to rank1==
7708 09:27:59.393186 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 09:27:59.399633 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7710 09:27:59.399715 ==
7711 09:27:59.399780 DQS Delay:
7712 09:27:59.399840 DQS0 = 0, DQS1 = 0
7713 09:27:59.402614 DQM Delay:
7714 09:27:59.402695 DQM0 = 126, DQM1 = 121
7715 09:27:59.405942 DQ Delay:
7716 09:27:59.409635 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7717 09:27:59.412912 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7718 09:27:59.416559 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7719 09:27:59.419302 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7720 09:27:59.419384
7721 09:27:59.419448
7722 09:27:59.419508
7723 09:27:59.422450 [DramC_TX_OE_Calibration] TA2
7724 09:27:59.426037 Original DQ_B0 (3 6) =30, OEN = 27
7725 09:27:59.429323 Original DQ_B1 (3 6) =30, OEN = 27
7726 09:27:59.432678 24, 0x0, End_B0=24 End_B1=24
7727 09:27:59.432760 25, 0x0, End_B0=25 End_B1=25
7728 09:27:59.435943 26, 0x0, End_B0=26 End_B1=26
7729 09:27:59.439689 27, 0x0, End_B0=27 End_B1=27
7730 09:27:59.442513 28, 0x0, End_B0=28 End_B1=28
7731 09:27:59.445867 29, 0x0, End_B0=29 End_B1=29
7732 09:27:59.445950 30, 0x0, End_B0=30 End_B1=30
7733 09:27:59.449121 31, 0x4141, End_B0=30 End_B1=30
7734 09:27:59.452358 Byte0 end_step=30 best_step=27
7735 09:27:59.455638 Byte1 end_step=30 best_step=27
7736 09:27:59.459072 Byte0 TX OE(2T, 0.5T) = (3, 3)
7737 09:27:59.462590 Byte1 TX OE(2T, 0.5T) = (3, 3)
7738 09:27:59.462672
7739 09:27:59.462736
7740 09:27:59.468922 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7741 09:27:59.472425 CH0 RK0: MR19=303, MR18=1C1C
7742 09:27:59.479010 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7743 09:27:59.479092
7744 09:27:59.482252 ----->DramcWriteLeveling(PI) begin...
7745 09:27:59.482336 ==
7746 09:27:59.486074 Dram Type= 6, Freq= 0, CH_0, rank 1
7747 09:27:59.488914 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7748 09:27:59.488996 ==
7749 09:27:59.492449 Write leveling (Byte 0): 28 => 28
7750 09:27:59.495529 Write leveling (Byte 1): 26 => 26
7751 09:27:59.499101 DramcWriteLeveling(PI) end<-----
7752 09:27:59.499183
7753 09:27:59.499247 ==
7754 09:27:59.502224 Dram Type= 6, Freq= 0, CH_0, rank 1
7755 09:27:59.505475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7756 09:27:59.505557 ==
7757 09:27:59.508881 [Gating] SW mode calibration
7758 09:27:59.515486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7759 09:27:59.522619 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7760 09:27:59.525442 0 12 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7761 09:27:59.532237 0 12 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7762 09:27:59.535315 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7763 09:27:59.538771 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7764 09:27:59.545354 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7765 09:27:59.548719 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7766 09:27:59.552098 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7767 09:27:59.555324 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7768 09:27:59.561879 0 13 0 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
7769 09:27:59.565253 0 13 4 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7770 09:27:59.568356 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7771 09:27:59.575249 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7772 09:27:59.578779 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7773 09:27:59.581616 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7774 09:27:59.588321 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7775 09:27:59.591838 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7776 09:27:59.595622 0 14 0 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
7777 09:27:59.601867 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7778 09:27:59.605116 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7779 09:27:59.608396 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7780 09:27:59.614959 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7781 09:27:59.618941 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7782 09:27:59.621590 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7783 09:27:59.628131 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7784 09:27:59.631503 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7785 09:27:59.634882 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7786 09:27:59.641334 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7787 09:27:59.644722 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7788 09:27:59.647966 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7789 09:27:59.654758 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7790 09:27:59.658039 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7791 09:27:59.661400 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7792 09:27:59.667791 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7793 09:27:59.671174 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7794 09:27:59.674531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7795 09:27:59.681217 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7796 09:27:59.684486 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7797 09:27:59.688366 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7798 09:27:59.694251 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7799 09:27:59.697761 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7800 09:27:59.701177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7801 09:27:59.707879 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7802 09:27:59.707961 Total UI for P1: 0, mck2ui 16
7803 09:27:59.714341 best dqsien dly found for B0: ( 1, 0, 30)
7804 09:27:59.717500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 09:27:59.720841 Total UI for P1: 0, mck2ui 16
7806 09:27:59.724270 best dqsien dly found for B1: ( 1, 1, 2)
7807 09:27:59.727614 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7808 09:27:59.730733 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7809 09:27:59.730814
7810 09:27:59.733985 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7811 09:27:59.737473 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7812 09:27:59.740990 [Gating] SW calibration Done
7813 09:27:59.741072 ==
7814 09:27:59.744336 Dram Type= 6, Freq= 0, CH_0, rank 1
7815 09:27:59.747521 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7816 09:27:59.747607 ==
7817 09:27:59.750785 RX Vref Scan: 0
7818 09:27:59.750867
7819 09:27:59.754548 RX Vref 0 -> 0, step: 1
7820 09:27:59.754629
7821 09:27:59.754694 RX Delay 0 -> 252, step: 8
7822 09:27:59.760959 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7823 09:27:59.764016 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7824 09:27:59.767411 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7825 09:27:59.770837 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7826 09:27:59.773903 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7827 09:27:59.780604 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7828 09:27:59.784020 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7829 09:27:59.787284 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7830 09:27:59.790907 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7831 09:27:59.794389 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7832 09:27:59.800570 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7833 09:27:59.803781 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7834 09:27:59.807214 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7835 09:27:59.810588 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7836 09:27:59.813661 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7837 09:27:59.820563 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7838 09:27:59.820657 ==
7839 09:27:59.823714 Dram Type= 6, Freq= 0, CH_0, rank 1
7840 09:27:59.826962 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7841 09:27:59.827045 ==
7842 09:27:59.827110 DQS Delay:
7843 09:27:59.830254 DQS0 = 0, DQS1 = 0
7844 09:27:59.830335 DQM Delay:
7845 09:27:59.833623 DQM0 = 131, DQM1 = 124
7846 09:27:59.833704 DQ Delay:
7847 09:27:59.836898 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
7848 09:27:59.840427 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7849 09:27:59.843786 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7850 09:27:59.847145 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7851 09:27:59.847226
7852 09:27:59.850488
7853 09:27:59.850569 ==
7854 09:27:59.853678 Dram Type= 6, Freq= 0, CH_0, rank 1
7855 09:27:59.857077 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7856 09:27:59.857160 ==
7857 09:27:59.857224
7858 09:27:59.857284
7859 09:27:59.860531 TX Vref Scan disable
7860 09:27:59.860613 == TX Byte 0 ==
7861 09:27:59.863623 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7862 09:27:59.870386 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7863 09:27:59.870469 == TX Byte 1 ==
7864 09:27:59.876738 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7865 09:27:59.879994 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7866 09:27:59.880078 ==
7867 09:27:59.883325 Dram Type= 6, Freq= 0, CH_0, rank 1
7868 09:27:59.886617 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7869 09:27:59.886702 ==
7870 09:27:59.901045
7871 09:27:59.904336 TX Vref early break, caculate TX vref
7872 09:27:59.907983 TX Vref=16, minBit 1, minWin=22, winSum=374
7873 09:27:59.910969 TX Vref=18, minBit 1, minWin=23, winSum=381
7874 09:27:59.914578 TX Vref=20, minBit 9, minWin=23, winSum=393
7875 09:27:59.917444 TX Vref=22, minBit 11, minWin=23, winSum=401
7876 09:27:59.920796 TX Vref=24, minBit 1, minWin=24, winSum=402
7877 09:27:59.927582 TX Vref=26, minBit 8, minWin=24, winSum=410
7878 09:27:59.931067 TX Vref=28, minBit 8, minWin=24, winSum=414
7879 09:27:59.934024 TX Vref=30, minBit 11, minWin=24, winSum=410
7880 09:27:59.937273 TX Vref=32, minBit 1, minWin=24, winSum=402
7881 09:27:59.940730 TX Vref=34, minBit 1, minWin=24, winSum=396
7882 09:27:59.947195 TX Vref=36, minBit 8, minWin=23, winSum=387
7883 09:27:59.950792 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
7884 09:27:59.950877
7885 09:27:59.953667 Final TX Range 0 Vref 28
7886 09:27:59.953776
7887 09:27:59.953877 ==
7888 09:27:59.957261 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 09:27:59.960335 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 09:27:59.963750 ==
7891 09:27:59.963834
7892 09:27:59.963920
7893 09:27:59.964001 TX Vref Scan disable
7894 09:27:59.970727 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7895 09:27:59.970812 == TX Byte 0 ==
7896 09:27:59.973805 u2DelayCellOfst[0]=14 cells (4 PI)
7897 09:27:59.977015 u2DelayCellOfst[1]=18 cells (5 PI)
7898 09:27:59.980531 u2DelayCellOfst[2]=10 cells (3 PI)
7899 09:27:59.984018 u2DelayCellOfst[3]=14 cells (4 PI)
7900 09:27:59.987048 u2DelayCellOfst[4]=10 cells (3 PI)
7901 09:27:59.990445 u2DelayCellOfst[5]=0 cells (0 PI)
7902 09:27:59.994000 u2DelayCellOfst[6]=18 cells (5 PI)
7903 09:27:59.997047 u2DelayCellOfst[7]=18 cells (5 PI)
7904 09:28:00.000500 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7905 09:28:00.003863 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7906 09:28:00.006936 == TX Byte 1 ==
7907 09:28:00.010545 u2DelayCellOfst[8]=3 cells (1 PI)
7908 09:28:00.013806 u2DelayCellOfst[9]=0 cells (0 PI)
7909 09:28:00.017346 u2DelayCellOfst[10]=14 cells (4 PI)
7910 09:28:00.020413 u2DelayCellOfst[11]=7 cells (2 PI)
7911 09:28:00.020498 u2DelayCellOfst[12]=18 cells (5 PI)
7912 09:28:00.023458 u2DelayCellOfst[13]=18 cells (5 PI)
7913 09:28:00.027009 u2DelayCellOfst[14]=21 cells (6 PI)
7914 09:28:00.030226 u2DelayCellOfst[15]=14 cells (4 PI)
7915 09:28:00.037113 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7916 09:28:00.040080 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7917 09:28:00.040164 DramC Write-DBI on
7918 09:28:00.043371 ==
7919 09:28:00.046830 Dram Type= 6, Freq= 0, CH_0, rank 1
7920 09:28:00.050215 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7921 09:28:00.050300 ==
7922 09:28:00.050387
7923 09:28:00.050468
7924 09:28:00.053609 TX Vref Scan disable
7925 09:28:00.053694 == TX Byte 0 ==
7926 09:28:00.059620 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7927 09:28:00.059704 == TX Byte 1 ==
7928 09:28:00.063065 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7929 09:28:00.066403 DramC Write-DBI off
7930 09:28:00.066488
7931 09:28:00.066573 [DATLAT]
7932 09:28:00.069734 Freq=1600, CH0 RK1
7933 09:28:00.069818
7934 09:28:00.069905 DATLAT Default: 0xe
7935 09:28:00.073199 0, 0xFFFF, sum = 0
7936 09:28:00.073285 1, 0xFFFF, sum = 0
7937 09:28:00.076354 2, 0xFFFF, sum = 0
7938 09:28:00.076439 3, 0xFFFF, sum = 0
7939 09:28:00.079658 4, 0xFFFF, sum = 0
7940 09:28:00.079744 5, 0xFFFF, sum = 0
7941 09:28:00.083007 6, 0xFFFF, sum = 0
7942 09:28:00.086540 7, 0xFFFF, sum = 0
7943 09:28:00.086626 8, 0xFFFF, sum = 0
7944 09:28:00.089840 9, 0xFFFF, sum = 0
7945 09:28:00.089926 10, 0xFFFF, sum = 0
7946 09:28:00.093306 11, 0xFFFF, sum = 0
7947 09:28:00.093392 12, 0x8FFF, sum = 0
7948 09:28:00.096318 13, 0x0, sum = 1
7949 09:28:00.096403 14, 0x0, sum = 2
7950 09:28:00.099684 15, 0x0, sum = 3
7951 09:28:00.099770 16, 0x0, sum = 4
7952 09:28:00.099858 best_step = 14
7953 09:28:00.102949
7954 09:28:00.103032 ==
7955 09:28:00.106124 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 09:28:00.109824 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7957 09:28:00.109909 ==
7958 09:28:00.109996 RX Vref Scan: 0
7959 09:28:00.110077
7960 09:28:00.113034 RX Vref 0 -> 0, step: 1
7961 09:28:00.113118
7962 09:28:00.116207 RX Delay 11 -> 252, step: 4
7963 09:28:00.119436 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7964 09:28:00.126449 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7965 09:28:00.129285 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7966 09:28:00.132691 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7967 09:28:00.136148 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7968 09:28:00.139329 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7969 09:28:00.142829 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7970 09:28:00.149447 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7971 09:28:00.152789 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7972 09:28:00.156032 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7973 09:28:00.159522 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7974 09:28:00.163047 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7975 09:28:00.169597 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7976 09:28:00.173466 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7977 09:28:00.176268 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7978 09:28:00.179423 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7979 09:28:00.179507 ==
7980 09:28:00.182766 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 09:28:00.189480 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 09:28:00.189566 ==
7983 09:28:00.189653 DQS Delay:
7984 09:28:00.192746 DQS0 = 0, DQS1 = 0
7985 09:28:00.192831 DQM Delay:
7986 09:28:00.192917 DQM0 = 128, DQM1 = 120
7987 09:28:00.196280 DQ Delay:
7988 09:28:00.199350 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7989 09:28:00.202817 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
7990 09:28:00.206123 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7991 09:28:00.209358 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7992 09:28:00.209443
7993 09:28:00.209529
7994 09:28:00.209611
7995 09:28:00.212680 [DramC_TX_OE_Calibration] TA2
7996 09:28:00.215857 Original DQ_B0 (3 6) =30, OEN = 27
7997 09:28:00.219176 Original DQ_B1 (3 6) =30, OEN = 27
7998 09:28:00.222516 24, 0x0, End_B0=24 End_B1=24
7999 09:28:00.226046 25, 0x0, End_B0=25 End_B1=25
8000 09:28:00.226138 26, 0x0, End_B0=26 End_B1=26
8001 09:28:00.229310 27, 0x0, End_B0=27 End_B1=27
8002 09:28:00.232820 28, 0x0, End_B0=28 End_B1=28
8003 09:28:00.235954 29, 0x0, End_B0=29 End_B1=29
8004 09:28:00.236040 30, 0x0, End_B0=30 End_B1=30
8005 09:28:00.239456 31, 0x4141, End_B0=30 End_B1=30
8006 09:28:00.242703 Byte0 end_step=30 best_step=27
8007 09:28:00.245669 Byte1 end_step=30 best_step=27
8008 09:28:00.249262 Byte0 TX OE(2T, 0.5T) = (3, 3)
8009 09:28:00.252366 Byte1 TX OE(2T, 0.5T) = (3, 3)
8010 09:28:00.252452
8011 09:28:00.252537
8012 09:28:00.259237 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8013 09:28:00.262272 CH0 RK1: MR19=303, MR18=2323
8014 09:28:00.269002 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8015 09:28:00.272355 [RxdqsGatingPostProcess] freq 1600
8016 09:28:00.275999 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8017 09:28:00.279233 Pre-setting of DQS Precalculation
8018 09:28:00.285773 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8019 09:28:00.285858 ==
8020 09:28:00.289014 Dram Type= 6, Freq= 0, CH_1, rank 0
8021 09:28:00.292146 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8022 09:28:00.292270 ==
8023 09:28:00.298846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8024 09:28:00.302287 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8025 09:28:00.305408 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8026 09:28:00.312077 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8027 09:28:00.320512 [CA 0] Center 41 (11~71) winsize 61
8028 09:28:00.323755 [CA 1] Center 40 (10~71) winsize 62
8029 09:28:00.326980 [CA 2] Center 36 (6~66) winsize 61
8030 09:28:00.330442 [CA 3] Center 35 (5~65) winsize 61
8031 09:28:00.333826 [CA 4] Center 33 (4~63) winsize 60
8032 09:28:00.336962 [CA 5] Center 33 (4~63) winsize 60
8033 09:28:00.337046
8034 09:28:00.340473 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8035 09:28:00.340558
8036 09:28:00.343764 [CATrainingPosCal] consider 1 rank data
8037 09:28:00.347088 u2DelayCellTimex100 = 271/100 ps
8038 09:28:00.350451 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8039 09:28:00.356690 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8040 09:28:00.360317 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8041 09:28:00.363422 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
8042 09:28:00.366824 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8043 09:28:00.370061 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8044 09:28:00.370142
8045 09:28:00.373250 CA PerBit enable=1, Macro0, CA PI delay=33
8046 09:28:00.373332
8047 09:28:00.376830 [CBTSetCACLKResult] CA Dly = 33
8048 09:28:00.380588 CS Dly: 8 (0~39)
8049 09:28:00.383329 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8050 09:28:00.386842 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8051 09:28:00.386924 ==
8052 09:28:00.389839 Dram Type= 6, Freq= 0, CH_1, rank 1
8053 09:28:00.396533 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8054 09:28:00.396615 ==
8055 09:28:00.400014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8056 09:28:00.406595 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8057 09:28:00.409608 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8058 09:28:00.416119 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8059 09:28:00.422909 [CA 0] Center 41 (11~71) winsize 61
8060 09:28:00.426301 [CA 1] Center 41 (11~71) winsize 61
8061 09:28:00.429863 [CA 2] Center 36 (7~66) winsize 60
8062 09:28:00.432838 [CA 3] Center 36 (7~65) winsize 59
8063 09:28:00.436232 [CA 4] Center 34 (5~64) winsize 60
8064 09:28:00.439969 [CA 5] Center 33 (4~63) winsize 60
8065 09:28:00.440050
8066 09:28:00.443258 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8067 09:28:00.443340
8068 09:28:00.446443 [CATrainingPosCal] consider 2 rank data
8069 09:28:00.449647 u2DelayCellTimex100 = 271/100 ps
8070 09:28:00.453117 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8071 09:28:00.459656 CA1 delay=41 (11~71),Diff = 8 PI (28 cell)
8072 09:28:00.463284 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8073 09:28:00.466507 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8074 09:28:00.469966 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8075 09:28:00.473063 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8076 09:28:00.473144
8077 09:28:00.476340 CA PerBit enable=1, Macro0, CA PI delay=33
8078 09:28:00.476421
8079 09:28:00.479600 [CBTSetCACLKResult] CA Dly = 33
8080 09:28:00.482833 CS Dly: 9 (0~41)
8081 09:28:00.486204 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8082 09:28:00.489444 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8083 09:28:00.489526
8084 09:28:00.492832 ----->DramcWriteLeveling(PI) begin...
8085 09:28:00.492915 ==
8086 09:28:00.496184 Dram Type= 6, Freq= 0, CH_1, rank 0
8087 09:28:00.499413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8088 09:28:00.502878 ==
8089 09:28:00.506163 Write leveling (Byte 0): 22 => 22
8090 09:28:00.506245 Write leveling (Byte 1): 23 => 23
8091 09:28:00.509313 DramcWriteLeveling(PI) end<-----
8092 09:28:00.509394
8093 09:28:00.509459 ==
8094 09:28:00.512660 Dram Type= 6, Freq= 0, CH_1, rank 0
8095 09:28:00.519315 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8096 09:28:00.519397 ==
8097 09:28:00.522880 [Gating] SW mode calibration
8098 09:28:00.529210 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8099 09:28:00.532638 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8100 09:28:00.539358 0 12 0 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
8101 09:28:00.542458 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8102 09:28:00.546218 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 09:28:00.552397 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 09:28:00.555985 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 09:28:00.559107 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 09:28:00.565972 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8107 09:28:00.569143 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8108 09:28:00.572382 0 13 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8109 09:28:00.579098 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8110 09:28:00.582642 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 09:28:00.585920 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 09:28:00.589048 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 09:28:00.595827 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 09:28:00.598924 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8115 09:28:00.602423 0 13 28 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
8116 09:28:00.609213 0 14 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8117 09:28:00.612347 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 09:28:00.615477 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 09:28:00.622177 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 09:28:00.625594 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 09:28:00.628574 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 09:28:00.635285 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8123 09:28:00.638874 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8124 09:28:00.642078 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8125 09:28:00.648620 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8126 09:28:00.651920 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 09:28:00.655520 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 09:28:00.661992 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 09:28:00.665071 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 09:28:00.668863 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 09:28:00.675256 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 09:28:00.678339 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 09:28:00.681733 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 09:28:00.688526 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 09:28:00.691770 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 09:28:00.695404 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 09:28:00.701669 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 09:28:00.705010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8139 09:28:00.708313 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8140 09:28:00.714810 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8141 09:28:00.714916 Total UI for P1: 0, mck2ui 16
8142 09:28:00.721420 best dqsien dly found for B0: ( 1, 0, 26)
8143 09:28:00.724714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8144 09:28:00.728183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 09:28:00.731677 Total UI for P1: 0, mck2ui 16
8146 09:28:00.734711 best dqsien dly found for B1: ( 1, 1, 2)
8147 09:28:00.738318 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8148 09:28:00.741311 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8149 09:28:00.741393
8150 09:28:00.744731 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8151 09:28:00.751390 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8152 09:28:00.751472 [Gating] SW calibration Done
8153 09:28:00.751538 ==
8154 09:28:00.754501 Dram Type= 6, Freq= 0, CH_1, rank 0
8155 09:28:00.761650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8156 09:28:00.761733 ==
8157 09:28:00.761797 RX Vref Scan: 0
8158 09:28:00.761858
8159 09:28:00.764887 RX Vref 0 -> 0, step: 1
8160 09:28:00.764969
8161 09:28:00.768209 RX Delay 0 -> 252, step: 8
8162 09:28:00.771341 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8163 09:28:00.774474 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8164 09:28:00.777830 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8165 09:28:00.784905 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8166 09:28:00.787961 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8167 09:28:00.791158 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8168 09:28:00.794425 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8169 09:28:00.797755 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8170 09:28:00.804392 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8171 09:28:00.807904 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8172 09:28:00.811024 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8173 09:28:00.814430 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8174 09:28:00.817766 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8175 09:28:00.824318 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8176 09:28:00.827567 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8177 09:28:00.830820 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8178 09:28:00.830902 ==
8179 09:28:00.834328 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 09:28:00.837672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 09:28:00.837754 ==
8182 09:28:00.840774 DQS Delay:
8183 09:28:00.840856 DQS0 = 0, DQS1 = 0
8184 09:28:00.844077 DQM Delay:
8185 09:28:00.844161 DQM0 = 129, DQM1 = 126
8186 09:28:00.847696 DQ Delay:
8187 09:28:00.851053 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8188 09:28:00.854409 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8189 09:28:00.857313 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8190 09:28:00.860582 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8191 09:28:00.860664
8192 09:28:00.860729
8193 09:28:00.860789 ==
8194 09:28:00.864257 Dram Type= 6, Freq= 0, CH_1, rank 0
8195 09:28:00.867278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8196 09:28:00.867361 ==
8197 09:28:00.867426
8198 09:28:00.867485
8199 09:28:00.870855 TX Vref Scan disable
8200 09:28:00.874214 == TX Byte 0 ==
8201 09:28:00.877620 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8202 09:28:00.880624 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8203 09:28:00.883885 == TX Byte 1 ==
8204 09:28:00.887278 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8205 09:28:00.890791 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8206 09:28:00.890873 ==
8207 09:28:00.894273 Dram Type= 6, Freq= 0, CH_1, rank 0
8208 09:28:00.897266 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8209 09:28:00.900854 ==
8210 09:28:00.911473
8211 09:28:00.914929 TX Vref early break, caculate TX vref
8212 09:28:00.917962 TX Vref=16, minBit 3, minWin=21, winSum=367
8213 09:28:00.921599 TX Vref=18, minBit 0, minWin=22, winSum=373
8214 09:28:00.924683 TX Vref=20, minBit 3, minWin=22, winSum=380
8215 09:28:00.928066 TX Vref=22, minBit 3, minWin=23, winSum=393
8216 09:28:00.931106 TX Vref=24, minBit 3, minWin=24, winSum=405
8217 09:28:00.937785 TX Vref=26, minBit 3, minWin=24, winSum=411
8218 09:28:00.941271 TX Vref=28, minBit 3, minWin=24, winSum=409
8219 09:28:00.944449 TX Vref=30, minBit 0, minWin=24, winSum=403
8220 09:28:00.948069 TX Vref=32, minBit 1, minWin=23, winSum=391
8221 09:28:00.951087 TX Vref=34, minBit 0, minWin=23, winSum=385
8222 09:28:00.958270 [TxChooseVref] Worse bit 3, Min win 24, Win sum 411, Final Vref 26
8223 09:28:00.958353
8224 09:28:00.961343 Final TX Range 0 Vref 26
8225 09:28:00.961425
8226 09:28:00.961490 ==
8227 09:28:00.964513 Dram Type= 6, Freq= 0, CH_1, rank 0
8228 09:28:00.968129 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8229 09:28:00.968253 ==
8230 09:28:00.968319
8231 09:28:00.968379
8232 09:28:00.971489 TX Vref Scan disable
8233 09:28:00.977747 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8234 09:28:00.977829 == TX Byte 0 ==
8235 09:28:00.981291 u2DelayCellOfst[0]=18 cells (5 PI)
8236 09:28:00.984487 u2DelayCellOfst[1]=10 cells (3 PI)
8237 09:28:00.987917 u2DelayCellOfst[2]=0 cells (0 PI)
8238 09:28:00.991095 u2DelayCellOfst[3]=7 cells (2 PI)
8239 09:28:00.994428 u2DelayCellOfst[4]=10 cells (3 PI)
8240 09:28:00.998025 u2DelayCellOfst[5]=18 cells (5 PI)
8241 09:28:01.001052 u2DelayCellOfst[6]=18 cells (5 PI)
8242 09:28:01.001133 u2DelayCellOfst[7]=10 cells (3 PI)
8243 09:28:01.008144 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8244 09:28:01.010995 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8245 09:28:01.011102 == TX Byte 1 ==
8246 09:28:01.014274 u2DelayCellOfst[8]=0 cells (0 PI)
8247 09:28:01.018044 u2DelayCellOfst[9]=3 cells (1 PI)
8248 09:28:01.021046 u2DelayCellOfst[10]=10 cells (3 PI)
8249 09:28:01.024420 u2DelayCellOfst[11]=7 cells (2 PI)
8250 09:28:01.027549 u2DelayCellOfst[12]=18 cells (5 PI)
8251 09:28:01.031188 u2DelayCellOfst[13]=21 cells (6 PI)
8252 09:28:01.034408 u2DelayCellOfst[14]=21 cells (6 PI)
8253 09:28:01.037357 u2DelayCellOfst[15]=18 cells (5 PI)
8254 09:28:01.040688 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8255 09:28:01.047392 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8256 09:28:01.047478 DramC Write-DBI on
8257 09:28:01.047564 ==
8258 09:28:01.050686 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 09:28:01.054151 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8260 09:28:01.057042 ==
8261 09:28:01.057125
8262 09:28:01.057211
8263 09:28:01.057291 TX Vref Scan disable
8264 09:28:01.060698 == TX Byte 0 ==
8265 09:28:01.063987 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8266 09:28:01.067654 == TX Byte 1 ==
8267 09:28:01.070819 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8268 09:28:01.073800 DramC Write-DBI off
8269 09:28:01.073884
8270 09:28:01.073970 [DATLAT]
8271 09:28:01.074052 Freq=1600, CH1 RK0
8272 09:28:01.074133
8273 09:28:01.077280 DATLAT Default: 0xf
8274 09:28:01.077365 0, 0xFFFF, sum = 0
8275 09:28:01.080712 1, 0xFFFF, sum = 0
8276 09:28:01.084000 2, 0xFFFF, sum = 0
8277 09:28:01.084086 3, 0xFFFF, sum = 0
8278 09:28:01.087734 4, 0xFFFF, sum = 0
8279 09:28:01.087820 5, 0xFFFF, sum = 0
8280 09:28:01.090847 6, 0xFFFF, sum = 0
8281 09:28:01.090934 7, 0xFFFF, sum = 0
8282 09:28:01.094084 8, 0xFFFF, sum = 0
8283 09:28:01.094170 9, 0xFFFF, sum = 0
8284 09:28:01.097393 10, 0xFFFF, sum = 0
8285 09:28:01.097479 11, 0xFFFF, sum = 0
8286 09:28:01.101215 12, 0xF7F, sum = 0
8287 09:28:01.101300 13, 0x0, sum = 1
8288 09:28:01.103841 14, 0x0, sum = 2
8289 09:28:01.103927 15, 0x0, sum = 3
8290 09:28:01.107347 16, 0x0, sum = 4
8291 09:28:01.107432 best_step = 14
8292 09:28:01.107518
8293 09:28:01.107600 ==
8294 09:28:01.110670 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 09:28:01.114088 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8296 09:28:01.116999 ==
8297 09:28:01.117083 RX Vref Scan: 1
8298 09:28:01.117170
8299 09:28:01.120167 Set Vref Range= 24 -> 127
8300 09:28:01.120260
8301 09:28:01.123484 RX Vref 24 -> 127, step: 1
8302 09:28:01.123569
8303 09:28:01.123655 RX Delay 3 -> 252, step: 4
8304 09:28:01.123754
8305 09:28:01.126931 Set Vref, RX VrefLevel [Byte0]: 24
8306 09:28:01.130575 [Byte1]: 24
8307 09:28:01.133956
8308 09:28:01.134037 Set Vref, RX VrefLevel [Byte0]: 25
8309 09:28:01.137313 [Byte1]: 25
8310 09:28:01.141514
8311 09:28:01.141594 Set Vref, RX VrefLevel [Byte0]: 26
8312 09:28:01.145167 [Byte1]: 26
8313 09:28:01.149794
8314 09:28:01.149875 Set Vref, RX VrefLevel [Byte0]: 27
8315 09:28:01.152500 [Byte1]: 27
8316 09:28:01.156890
8317 09:28:01.156971 Set Vref, RX VrefLevel [Byte0]: 28
8318 09:28:01.160294 [Byte1]: 28
8319 09:28:01.164496
8320 09:28:01.164577 Set Vref, RX VrefLevel [Byte0]: 29
8321 09:28:01.168045 [Byte1]: 29
8322 09:28:01.172131
8323 09:28:01.172275 Set Vref, RX VrefLevel [Byte0]: 30
8324 09:28:01.175393 [Byte1]: 30
8325 09:28:01.179811
8326 09:28:01.179892 Set Vref, RX VrefLevel [Byte0]: 31
8327 09:28:01.183318 [Byte1]: 31
8328 09:28:01.187544
8329 09:28:01.187656 Set Vref, RX VrefLevel [Byte0]: 32
8330 09:28:01.190775 [Byte1]: 32
8331 09:28:01.195108
8332 09:28:01.195205 Set Vref, RX VrefLevel [Byte0]: 33
8333 09:28:01.198595 [Byte1]: 33
8334 09:28:01.202932
8335 09:28:01.203013 Set Vref, RX VrefLevel [Byte0]: 34
8336 09:28:01.206390 [Byte1]: 34
8337 09:28:01.210994
8338 09:28:01.211077 Set Vref, RX VrefLevel [Byte0]: 35
8339 09:28:01.214153 [Byte1]: 35
8340 09:28:01.218237
8341 09:28:01.218318 Set Vref, RX VrefLevel [Byte0]: 36
8342 09:28:01.221739 [Byte1]: 36
8343 09:28:01.225744
8344 09:28:01.225824 Set Vref, RX VrefLevel [Byte0]: 37
8345 09:28:01.229321 [Byte1]: 37
8346 09:28:01.234196
8347 09:28:01.234276 Set Vref, RX VrefLevel [Byte0]: 38
8348 09:28:01.236703 [Byte1]: 38
8349 09:28:01.240996
8350 09:28:01.241077 Set Vref, RX VrefLevel [Byte0]: 39
8351 09:28:01.244331 [Byte1]: 39
8352 09:28:01.248699
8353 09:28:01.248780 Set Vref, RX VrefLevel [Byte0]: 40
8354 09:28:01.252067 [Byte1]: 40
8355 09:28:01.256652
8356 09:28:01.256733 Set Vref, RX VrefLevel [Byte0]: 41
8357 09:28:01.259651 [Byte1]: 41
8358 09:28:01.264016
8359 09:28:01.264096 Set Vref, RX VrefLevel [Byte0]: 42
8360 09:28:01.267498 [Byte1]: 42
8361 09:28:01.271672
8362 09:28:01.271753 Set Vref, RX VrefLevel [Byte0]: 43
8363 09:28:01.274993 [Byte1]: 43
8364 09:28:01.279348
8365 09:28:01.279428 Set Vref, RX VrefLevel [Byte0]: 44
8366 09:28:01.282638 [Byte1]: 44
8367 09:28:01.286907
8368 09:28:01.286987 Set Vref, RX VrefLevel [Byte0]: 45
8369 09:28:01.290540 [Byte1]: 45
8370 09:28:01.294786
8371 09:28:01.294867 Set Vref, RX VrefLevel [Byte0]: 46
8372 09:28:01.297959 [Byte1]: 46
8373 09:28:01.302337
8374 09:28:01.302418 Set Vref, RX VrefLevel [Byte0]: 47
8375 09:28:01.305843 [Byte1]: 47
8376 09:28:01.310171
8377 09:28:01.310252 Set Vref, RX VrefLevel [Byte0]: 48
8378 09:28:01.313275 [Byte1]: 48
8379 09:28:01.317526
8380 09:28:01.317607 Set Vref, RX VrefLevel [Byte0]: 49
8381 09:28:01.321013 [Byte1]: 49
8382 09:28:01.325596
8383 09:28:01.325676 Set Vref, RX VrefLevel [Byte0]: 50
8384 09:28:01.328591 [Byte1]: 50
8385 09:28:01.333019
8386 09:28:01.333099 Set Vref, RX VrefLevel [Byte0]: 51
8387 09:28:01.336435 [Byte1]: 51
8388 09:28:01.340579
8389 09:28:01.340676 Set Vref, RX VrefLevel [Byte0]: 52
8390 09:28:01.343721 [Byte1]: 52
8391 09:28:01.348345
8392 09:28:01.348426 Set Vref, RX VrefLevel [Byte0]: 53
8393 09:28:01.351515 [Byte1]: 53
8394 09:28:01.355745
8395 09:28:01.355825 Set Vref, RX VrefLevel [Byte0]: 54
8396 09:28:01.359241 [Byte1]: 54
8397 09:28:01.363607
8398 09:28:01.363687 Set Vref, RX VrefLevel [Byte0]: 55
8399 09:28:01.366759 [Byte1]: 55
8400 09:28:01.371221
8401 09:28:01.371305 Set Vref, RX VrefLevel [Byte0]: 56
8402 09:28:01.374703 [Byte1]: 56
8403 09:28:01.378999
8404 09:28:01.379079 Set Vref, RX VrefLevel [Byte0]: 57
8405 09:28:01.381986 [Byte1]: 57
8406 09:28:01.386565
8407 09:28:01.386645 Set Vref, RX VrefLevel [Byte0]: 58
8408 09:28:01.389819 [Byte1]: 58
8409 09:28:01.394184
8410 09:28:01.394264 Set Vref, RX VrefLevel [Byte0]: 59
8411 09:28:01.397354 [Byte1]: 59
8412 09:28:01.401827
8413 09:28:01.401907 Set Vref, RX VrefLevel [Byte0]: 60
8414 09:28:01.405215 [Byte1]: 60
8415 09:28:01.409474
8416 09:28:01.409555 Set Vref, RX VrefLevel [Byte0]: 61
8417 09:28:01.413035 [Byte1]: 61
8418 09:28:01.416976
8419 09:28:01.417057 Set Vref, RX VrefLevel [Byte0]: 62
8420 09:28:01.420378 [Byte1]: 62
8421 09:28:01.424988
8422 09:28:01.425069 Set Vref, RX VrefLevel [Byte0]: 63
8423 09:28:01.428011 [Byte1]: 63
8424 09:28:01.432577
8425 09:28:01.432657 Set Vref, RX VrefLevel [Byte0]: 64
8426 09:28:01.435817 [Byte1]: 64
8427 09:28:01.439938
8428 09:28:01.440018 Set Vref, RX VrefLevel [Byte0]: 65
8429 09:28:01.443364 [Byte1]: 65
8430 09:28:01.447832
8431 09:28:01.447942 Set Vref, RX VrefLevel [Byte0]: 66
8432 09:28:01.451027 [Byte1]: 66
8433 09:28:01.455397
8434 09:28:01.455477 Set Vref, RX VrefLevel [Byte0]: 67
8435 09:28:01.458773 [Byte1]: 67
8436 09:28:01.462918
8437 09:28:01.462998 Set Vref, RX VrefLevel [Byte0]: 68
8438 09:28:01.466094 [Byte1]: 68
8439 09:28:01.470512
8440 09:28:01.470593 Set Vref, RX VrefLevel [Byte0]: 69
8441 09:28:01.473995 [Byte1]: 69
8442 09:28:01.478255
8443 09:28:01.478335 Set Vref, RX VrefLevel [Byte0]: 70
8444 09:28:01.481772 [Byte1]: 70
8445 09:28:01.485794
8446 09:28:01.485875 Set Vref, RX VrefLevel [Byte0]: 71
8447 09:28:01.489273 [Byte1]: 71
8448 09:28:01.493402
8449 09:28:01.493482 Set Vref, RX VrefLevel [Byte0]: 72
8450 09:28:01.496786 [Byte1]: 72
8451 09:28:01.501380
8452 09:28:01.501461 Set Vref, RX VrefLevel [Byte0]: 73
8453 09:28:01.504596 [Byte1]: 73
8454 09:28:01.508892
8455 09:28:01.508971 Set Vref, RX VrefLevel [Byte0]: 74
8456 09:28:01.512203 [Byte1]: 74
8457 09:28:01.516374
8458 09:28:01.516455 Set Vref, RX VrefLevel [Byte0]: 75
8459 09:28:01.519992 [Byte1]: 75
8460 09:28:01.524159
8461 09:28:01.524250 Final RX Vref Byte 0 = 61 to rank0
8462 09:28:01.527639 Final RX Vref Byte 1 = 54 to rank0
8463 09:28:01.530942 Final RX Vref Byte 0 = 61 to rank1
8464 09:28:01.534320 Final RX Vref Byte 1 = 54 to rank1==
8465 09:28:01.537317 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 09:28:01.544206 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8467 09:28:01.544288 ==
8468 09:28:01.544354 DQS Delay:
8469 09:28:01.547337 DQS0 = 0, DQS1 = 0
8470 09:28:01.547451 DQM Delay:
8471 09:28:01.547542 DQM0 = 128, DQM1 = 124
8472 09:28:01.550935 DQ Delay:
8473 09:28:01.554208 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8474 09:28:01.557465 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =124
8475 09:28:01.560857 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8476 09:28:01.563883 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8477 09:28:01.563964
8478 09:28:01.564027
8479 09:28:01.564087
8480 09:28:01.567232 [DramC_TX_OE_Calibration] TA2
8481 09:28:01.570675 Original DQ_B0 (3 6) =30, OEN = 27
8482 09:28:01.574329 Original DQ_B1 (3 6) =30, OEN = 27
8483 09:28:01.577097 24, 0x0, End_B0=24 End_B1=24
8484 09:28:01.577179 25, 0x0, End_B0=25 End_B1=25
8485 09:28:01.580448 26, 0x0, End_B0=26 End_B1=26
8486 09:28:01.583822 27, 0x0, End_B0=27 End_B1=27
8487 09:28:01.587312 28, 0x0, End_B0=28 End_B1=28
8488 09:28:01.590879 29, 0x0, End_B0=29 End_B1=29
8489 09:28:01.590962 30, 0x0, End_B0=30 End_B1=30
8490 09:28:01.594212 31, 0x4141, End_B0=30 End_B1=30
8491 09:28:01.597209 Byte0 end_step=30 best_step=27
8492 09:28:01.600283 Byte1 end_step=30 best_step=27
8493 09:28:01.603783 Byte0 TX OE(2T, 0.5T) = (3, 3)
8494 09:28:01.607186 Byte1 TX OE(2T, 0.5T) = (3, 3)
8495 09:28:01.607267
8496 09:28:01.607331
8497 09:28:01.613625 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8498 09:28:01.617046 CH1 RK0: MR19=303, MR18=2828
8499 09:28:01.623717 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8500 09:28:01.623799
8501 09:28:01.627012 ----->DramcWriteLeveling(PI) begin...
8502 09:28:01.627094 ==
8503 09:28:01.630173 Dram Type= 6, Freq= 0, CH_1, rank 1
8504 09:28:01.633545 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8505 09:28:01.633626 ==
8506 09:28:01.636879 Write leveling (Byte 0): 22 => 22
8507 09:28:01.640049 Write leveling (Byte 1): 21 => 21
8508 09:28:01.643869 DramcWriteLeveling(PI) end<-----
8509 09:28:01.643978
8510 09:28:01.644071 ==
8511 09:28:01.646964 Dram Type= 6, Freq= 0, CH_1, rank 1
8512 09:28:01.650223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8513 09:28:01.650306 ==
8514 09:28:01.653819 [Gating] SW mode calibration
8515 09:28:01.660072 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8516 09:28:01.666919 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8517 09:28:01.669981 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8518 09:28:01.676643 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8519 09:28:01.680389 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8520 09:28:01.683405 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8521 09:28:01.690167 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8522 09:28:01.693296 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8523 09:28:01.696423 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8524 09:28:01.699827 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8525 09:28:01.706436 0 13 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8526 09:28:01.709713 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8527 09:28:01.713139 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8528 09:28:01.719765 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8529 09:28:01.722884 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8530 09:28:01.726191 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8531 09:28:01.733203 0 13 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8532 09:28:01.736223 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8533 09:28:01.739849 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8534 09:28:01.746208 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8535 09:28:01.749596 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8536 09:28:01.752983 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8537 09:28:01.759734 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8538 09:28:01.762864 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8539 09:28:01.766143 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8540 09:28:01.772969 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8541 09:28:01.776262 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8542 09:28:01.779459 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8543 09:28:01.786274 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8544 09:28:01.789288 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8545 09:28:01.792595 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8546 09:28:01.799335 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8547 09:28:01.802665 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8548 09:28:01.806131 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8549 09:28:01.812810 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8550 09:28:01.815857 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8551 09:28:01.819388 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8552 09:28:01.825847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8553 09:28:01.829177 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 09:28:01.832428 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 09:28:01.839087 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8556 09:28:01.842640 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8557 09:28:01.845969 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8558 09:28:01.849123 Total UI for P1: 0, mck2ui 16
8559 09:28:01.852343 best dqsien dly found for B0: ( 1, 0, 26)
8560 09:28:01.856132 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 09:28:01.859272 Total UI for P1: 0, mck2ui 16
8562 09:28:01.862791 best dqsien dly found for B1: ( 1, 1, 0)
8563 09:28:01.865928 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8564 09:28:01.872297 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8565 09:28:01.872382
8566 09:28:01.875988 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8567 09:28:01.879153 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8568 09:28:01.882308 [Gating] SW calibration Done
8569 09:28:01.882393 ==
8570 09:28:01.885615 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 09:28:01.889237 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 09:28:01.889322 ==
8573 09:28:01.889408 RX Vref Scan: 0
8574 09:28:01.892422
8575 09:28:01.892505 RX Vref 0 -> 0, step: 1
8576 09:28:01.892591
8577 09:28:01.895541 RX Delay 0 -> 252, step: 8
8578 09:28:01.899066 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8579 09:28:01.902085 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8580 09:28:01.909167 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8581 09:28:01.912164 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8582 09:28:01.915894 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8583 09:28:01.918882 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8584 09:28:01.922384 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8585 09:28:01.925740 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8586 09:28:01.932394 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8587 09:28:01.936004 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8588 09:28:01.938703 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8589 09:28:01.941871 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8590 09:28:01.948624 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8591 09:28:01.952110 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8592 09:28:01.955360 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8593 09:28:01.958460 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8594 09:28:01.958545 ==
8595 09:28:01.962311 Dram Type= 6, Freq= 0, CH_1, rank 1
8596 09:28:01.968625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8597 09:28:01.968710 ==
8598 09:28:01.968797 DQS Delay:
8599 09:28:01.972022 DQS0 = 0, DQS1 = 0
8600 09:28:01.972106 DQM Delay:
8601 09:28:01.972246 DQM0 = 131, DQM1 = 125
8602 09:28:01.975170 DQ Delay:
8603 09:28:01.979027 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8604 09:28:01.981787 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8605 09:28:01.985019 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8606 09:28:01.988699 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8607 09:28:01.988784
8608 09:28:01.988871
8609 09:28:01.988953 ==
8610 09:28:01.991878 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 09:28:01.995088 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 09:28:01.998438 ==
8613 09:28:01.998522
8614 09:28:01.998609
8615 09:28:01.998691 TX Vref Scan disable
8616 09:28:02.001935 == TX Byte 0 ==
8617 09:28:02.005000 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8618 09:28:02.008640 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8619 09:28:02.011589 == TX Byte 1 ==
8620 09:28:02.015099 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8621 09:28:02.018330 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8622 09:28:02.021616 ==
8623 09:28:02.024988 Dram Type= 6, Freq= 0, CH_1, rank 1
8624 09:28:02.028140 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8625 09:28:02.028231 ==
8626 09:28:02.039915
8627 09:28:02.043406 TX Vref early break, caculate TX vref
8628 09:28:02.046330 TX Vref=16, minBit 2, minWin=22, winSum=377
8629 09:28:02.049940 TX Vref=18, minBit 7, minWin=22, winSum=385
8630 09:28:02.053104 TX Vref=20, minBit 3, minWin=23, winSum=394
8631 09:28:02.056460 TX Vref=22, minBit 5, minWin=23, winSum=402
8632 09:28:02.059703 TX Vref=24, minBit 3, minWin=24, winSum=410
8633 09:28:02.066167 TX Vref=26, minBit 0, minWin=25, winSum=419
8634 09:28:02.069676 TX Vref=28, minBit 0, minWin=25, winSum=421
8635 09:28:02.073254 TX Vref=30, minBit 7, minWin=24, winSum=413
8636 09:28:02.076112 TX Vref=32, minBit 1, minWin=24, winSum=409
8637 09:28:02.079571 TX Vref=34, minBit 0, minWin=22, winSum=394
8638 09:28:02.086209 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8639 09:28:02.086292
8640 09:28:02.089409 Final TX Range 0 Vref 28
8641 09:28:02.089491
8642 09:28:02.089556 ==
8643 09:28:02.092636 Dram Type= 6, Freq= 0, CH_1, rank 1
8644 09:28:02.095992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8645 09:28:02.096075 ==
8646 09:28:02.096139
8647 09:28:02.096212
8648 09:28:02.099479 TX Vref Scan disable
8649 09:28:02.105949 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8650 09:28:02.106030 == TX Byte 0 ==
8651 09:28:02.109152 u2DelayCellOfst[0]=14 cells (4 PI)
8652 09:28:02.112598 u2DelayCellOfst[1]=7 cells (2 PI)
8653 09:28:02.116301 u2DelayCellOfst[2]=0 cells (0 PI)
8654 09:28:02.119175 u2DelayCellOfst[3]=7 cells (2 PI)
8655 09:28:02.122597 u2DelayCellOfst[4]=7 cells (2 PI)
8656 09:28:02.125827 u2DelayCellOfst[5]=14 cells (4 PI)
8657 09:28:02.129328 u2DelayCellOfst[6]=10 cells (3 PI)
8658 09:28:02.129410 u2DelayCellOfst[7]=3 cells (1 PI)
8659 09:28:02.135856 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8660 09:28:02.139288 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8661 09:28:02.139370 == TX Byte 1 ==
8662 09:28:02.142635 u2DelayCellOfst[8]=0 cells (0 PI)
8663 09:28:02.145915 u2DelayCellOfst[9]=3 cells (1 PI)
8664 09:28:02.149319 u2DelayCellOfst[10]=10 cells (3 PI)
8665 09:28:02.152441 u2DelayCellOfst[11]=3 cells (1 PI)
8666 09:28:02.155810 u2DelayCellOfst[12]=14 cells (4 PI)
8667 09:28:02.159409 u2DelayCellOfst[13]=18 cells (5 PI)
8668 09:28:02.162486 u2DelayCellOfst[14]=18 cells (5 PI)
8669 09:28:02.165834 u2DelayCellOfst[15]=18 cells (5 PI)
8670 09:28:02.169058 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8671 09:28:02.175448 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8672 09:28:02.175534 DramC Write-DBI on
8673 09:28:02.175621 ==
8674 09:28:02.179084 Dram Type= 6, Freq= 0, CH_1, rank 1
8675 09:28:02.182277 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8676 09:28:02.185487 ==
8677 09:28:02.185571
8678 09:28:02.185657
8679 09:28:02.185739 TX Vref Scan disable
8680 09:28:02.188996 == TX Byte 0 ==
8681 09:28:02.192184 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8682 09:28:02.195498 == TX Byte 1 ==
8683 09:28:02.199006 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8684 09:28:02.202165 DramC Write-DBI off
8685 09:28:02.202250
8686 09:28:02.202336 [DATLAT]
8687 09:28:02.202417 Freq=1600, CH1 RK1
8688 09:28:02.202497
8689 09:28:02.205752 DATLAT Default: 0xe
8690 09:28:02.205836 0, 0xFFFF, sum = 0
8691 09:28:02.209078 1, 0xFFFF, sum = 0
8692 09:28:02.212137 2, 0xFFFF, sum = 0
8693 09:28:02.212232 3, 0xFFFF, sum = 0
8694 09:28:02.215411 4, 0xFFFF, sum = 0
8695 09:28:02.215497 5, 0xFFFF, sum = 0
8696 09:28:02.218765 6, 0xFFFF, sum = 0
8697 09:28:02.218851 7, 0xFFFF, sum = 0
8698 09:28:02.222085 8, 0xFFFF, sum = 0
8699 09:28:02.222171 9, 0xFFFF, sum = 0
8700 09:28:02.225173 10, 0xFFFF, sum = 0
8701 09:28:02.225259 11, 0xFFFF, sum = 0
8702 09:28:02.228545 12, 0x8FFF, sum = 0
8703 09:28:02.228630 13, 0x0, sum = 1
8704 09:28:02.232100 14, 0x0, sum = 2
8705 09:28:02.232193 15, 0x0, sum = 3
8706 09:28:02.235484 16, 0x0, sum = 4
8707 09:28:02.235569 best_step = 14
8708 09:28:02.235655
8709 09:28:02.235736 ==
8710 09:28:02.238526 Dram Type= 6, Freq= 0, CH_1, rank 1
8711 09:28:02.241940 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8712 09:28:02.245338 ==
8713 09:28:02.245423 RX Vref Scan: 0
8714 09:28:02.245510
8715 09:28:02.248591 RX Vref 0 -> 0, step: 1
8716 09:28:02.248676
8717 09:28:02.248762 RX Delay 3 -> 252, step: 4
8718 09:28:02.256095 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8719 09:28:02.259083 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8720 09:28:02.262780 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8721 09:28:02.266013 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8722 09:28:02.269346 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8723 09:28:02.275787 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8724 09:28:02.279091 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8725 09:28:02.282681 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8726 09:28:02.285774 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8727 09:28:02.289125 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8728 09:28:02.295762 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8729 09:28:02.299634 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8730 09:28:02.302525 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8731 09:28:02.305698 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8732 09:28:02.312244 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8733 09:28:02.315741 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8734 09:28:02.315826 ==
8735 09:28:02.318673 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 09:28:02.322236 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8737 09:28:02.322321 ==
8738 09:28:02.325688 DQS Delay:
8739 09:28:02.325772 DQS0 = 0, DQS1 = 0
8740 09:28:02.325859 DQM Delay:
8741 09:28:02.328911 DQM0 = 126, DQM1 = 123
8742 09:28:02.328996 DQ Delay:
8743 09:28:02.332296 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8744 09:28:02.335661 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8745 09:28:02.339052 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =114
8746 09:28:02.345335 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8747 09:28:02.345419
8748 09:28:02.345505
8749 09:28:02.345586
8750 09:28:02.349000 [DramC_TX_OE_Calibration] TA2
8751 09:28:02.349085 Original DQ_B0 (3 6) =30, OEN = 27
8752 09:28:02.352049 Original DQ_B1 (3 6) =30, OEN = 27
8753 09:28:02.355367 24, 0x0, End_B0=24 End_B1=24
8754 09:28:02.358703 25, 0x0, End_B0=25 End_B1=25
8755 09:28:02.361849 26, 0x0, End_B0=26 End_B1=26
8756 09:28:02.365431 27, 0x0, End_B0=27 End_B1=27
8757 09:28:02.365517 28, 0x0, End_B0=28 End_B1=28
8758 09:28:02.368432 29, 0x0, End_B0=29 End_B1=29
8759 09:28:02.372017 30, 0x0, End_B0=30 End_B1=30
8760 09:28:02.375010 31, 0x4545, End_B0=30 End_B1=30
8761 09:28:02.378928 Byte0 end_step=30 best_step=27
8762 09:28:02.379014 Byte1 end_step=30 best_step=27
8763 09:28:02.382041 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 09:28:02.385435 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 09:28:02.385520
8766 09:28:02.385606
8767 09:28:02.394913 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8768 09:28:02.394997 CH1 RK1: MR19=303, MR18=1E1E
8769 09:28:02.401536 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8770 09:28:02.404899 [RxdqsGatingPostProcess] freq 1600
8771 09:28:02.411404 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8772 09:28:02.414737 Pre-setting of DQS Precalculation
8773 09:28:02.417984 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8774 09:28:02.427965 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8775 09:28:02.434551 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8776 09:28:02.434701
8777 09:28:02.434810
8778 09:28:02.438155 [Calibration Summary] 3200 Mbps
8779 09:28:02.438342 CH 0, Rank 0
8780 09:28:02.441726 SW Impedance : PASS
8781 09:28:02.441944 DUTY Scan : NO K
8782 09:28:02.444613 ZQ Calibration : PASS
8783 09:28:02.447978 Jitter Meter : NO K
8784 09:28:02.448153 CBT Training : PASS
8785 09:28:02.451304 Write leveling : PASS
8786 09:28:02.454601 RX DQS gating : PASS
8787 09:28:02.454766 RX DQ/DQS(RDDQC) : PASS
8788 09:28:02.458111 TX DQ/DQS : PASS
8789 09:28:02.461120 RX DATLAT : PASS
8790 09:28:02.461330 RX DQ/DQS(Engine): PASS
8791 09:28:02.464642 TX OE : PASS
8792 09:28:02.464849 All Pass.
8793 09:28:02.465035
8794 09:28:02.468088 CH 0, Rank 1
8795 09:28:02.468321 SW Impedance : PASS
8796 09:28:02.471062 DUTY Scan : NO K
8797 09:28:02.474577 ZQ Calibration : PASS
8798 09:28:02.474780 Jitter Meter : NO K
8799 09:28:02.477950 CBT Training : PASS
8800 09:28:02.478286 Write leveling : PASS
8801 09:28:02.481247 RX DQS gating : PASS
8802 09:28:02.484728 RX DQ/DQS(RDDQC) : PASS
8803 09:28:02.485110 TX DQ/DQS : PASS
8804 09:28:02.488048 RX DATLAT : PASS
8805 09:28:02.491936 RX DQ/DQS(Engine): PASS
8806 09:28:02.492541 TX OE : PASS
8807 09:28:02.494626 All Pass.
8808 09:28:02.495104
8809 09:28:02.495591 CH 1, Rank 0
8810 09:28:02.498411 SW Impedance : PASS
8811 09:28:02.499002 DUTY Scan : NO K
8812 09:28:02.501217 ZQ Calibration : PASS
8813 09:28:02.504752 Jitter Meter : NO K
8814 09:28:02.505239 CBT Training : PASS
8815 09:28:02.507723 Write leveling : PASS
8816 09:28:02.511277 RX DQS gating : PASS
8817 09:28:02.511756 RX DQ/DQS(RDDQC) : PASS
8818 09:28:02.514431 TX DQ/DQS : PASS
8819 09:28:02.517915 RX DATLAT : PASS
8820 09:28:02.518400 RX DQ/DQS(Engine): PASS
8821 09:28:02.521043 TX OE : PASS
8822 09:28:02.521615 All Pass.
8823 09:28:02.522121
8824 09:28:02.524584 CH 1, Rank 1
8825 09:28:02.525166 SW Impedance : PASS
8826 09:28:02.527607 DUTY Scan : NO K
8827 09:28:02.531175 ZQ Calibration : PASS
8828 09:28:02.531740 Jitter Meter : NO K
8829 09:28:02.534809 CBT Training : PASS
8830 09:28:02.537709 Write leveling : PASS
8831 09:28:02.538192 RX DQS gating : PASS
8832 09:28:02.541198 RX DQ/DQS(RDDQC) : PASS
8833 09:28:02.544289 TX DQ/DQS : PASS
8834 09:28:02.544803 RX DATLAT : PASS
8835 09:28:02.547713 RX DQ/DQS(Engine): PASS
8836 09:28:02.548216 TX OE : PASS
8837 09:28:02.550683 All Pass.
8838 09:28:02.551147
8839 09:28:02.551513 DramC Write-DBI on
8840 09:28:02.554374 PER_BANK_REFRESH: Hybrid Mode
8841 09:28:02.557262 TX_TRACKING: ON
8842 09:28:02.564369 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8843 09:28:02.573762 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8844 09:28:02.580492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8845 09:28:02.584065 [FAST_K] Save calibration result to emmc
8846 09:28:02.587337 sync common calibartion params.
8847 09:28:02.587898 sync cbt_mode0:0, 1:0
8848 09:28:02.590618 dram_init: ddr_geometry: 0
8849 09:28:02.593652 dram_init: ddr_geometry: 0
8850 09:28:02.597415 dram_init: ddr_geometry: 0
8851 09:28:02.597982 0:dram_rank_size:80000000
8852 09:28:02.600816 1:dram_rank_size:80000000
8853 09:28:02.607120 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8854 09:28:02.607734 DFS_SHUFFLE_HW_MODE: ON
8855 09:28:02.613954 dramc_set_vcore_voltage set vcore to 725000
8856 09:28:02.614524 Read voltage for 1600, 0
8857 09:28:02.616751 Vio18 = 0
8858 09:28:02.617214 Vcore = 725000
8859 09:28:02.617585 Vdram = 0
8860 09:28:02.617930 Vddq = 0
8861 09:28:02.620157 Vmddr = 0
8862 09:28:02.620651 switch to 3200 Mbps bootup
8863 09:28:02.623438 [DramcRunTimeConfig]
8864 09:28:02.623916 PHYPLL
8865 09:28:02.627001 DPM_CONTROL_AFTERK: ON
8866 09:28:02.627477 PER_BANK_REFRESH: ON
8867 09:28:02.630370 REFRESH_OVERHEAD_REDUCTION: ON
8868 09:28:02.633667 CMD_PICG_NEW_MODE: OFF
8869 09:28:02.634249 XRTWTW_NEW_MODE: ON
8870 09:28:02.637101 XRTRTR_NEW_MODE: ON
8871 09:28:02.637676 TX_TRACKING: ON
8872 09:28:02.640584 RDSEL_TRACKING: OFF
8873 09:28:02.643676 DQS Precalculation for DVFS: ON
8874 09:28:02.644162 RX_TRACKING: OFF
8875 09:28:02.646735 HW_GATING DBG: ON
8876 09:28:02.647215 ZQCS_ENABLE_LP4: ON
8877 09:28:02.650134 RX_PICG_NEW_MODE: ON
8878 09:28:02.650616 TX_PICG_NEW_MODE: ON
8879 09:28:02.653592 ENABLE_RX_DCM_DPHY: ON
8880 09:28:02.656901 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8881 09:28:02.660296 DUMMY_READ_FOR_TRACKING: OFF
8882 09:28:02.663525 !!! SPM_CONTROL_AFTERK: OFF
8883 09:28:02.664164 !!! SPM could not control APHY
8884 09:28:02.666293 IMPEDANCE_TRACKING: ON
8885 09:28:02.669775 TEMP_SENSOR: ON
8886 09:28:02.670278 HW_SAVE_FOR_SR: OFF
8887 09:28:02.673230 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8888 09:28:02.676846 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8889 09:28:02.680279 Read ODT Tracking: ON
8890 09:28:02.680869 Refresh Rate DeBounce: ON
8891 09:28:02.683551 DFS_NO_QUEUE_FLUSH: ON
8892 09:28:02.686618 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8893 09:28:02.689892 ENABLE_DFS_RUNTIME_MRW: OFF
8894 09:28:02.690474 DDR_RESERVE_NEW_MODE: ON
8895 09:28:02.693369 MR_CBT_SWITCH_FREQ: ON
8896 09:28:02.696382 =========================
8897 09:28:02.714119 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8898 09:28:02.717179 dram_init: ddr_geometry: 0
8899 09:28:02.735787 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8900 09:28:02.739029 dram_init: dram init end (result: 0)
8901 09:28:02.745458 DRAM-K: Full calibration passed in 23381 msecs
8902 09:28:02.748681 MRC: failed to locate region type 0.
8903 09:28:02.749150 DRAM rank0 size:0x80000000,
8904 09:28:02.752163 DRAM rank1 size=0x80000000
8905 09:28:02.761979 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8906 09:28:02.768603 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8907 09:28:02.775071 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8908 09:28:02.782160 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8909 09:28:02.785377 DRAM rank0 size:0x80000000,
8910 09:28:02.788679 DRAM rank1 size=0x80000000
8911 09:28:02.789147 CBMEM:
8912 09:28:02.792027 IMD: root @ 0xfffff000 254 entries.
8913 09:28:02.795268 IMD: root @ 0xffffec00 62 entries.
8914 09:28:02.798583 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8915 09:28:02.802050 WARNING: RO_VPD is uninitialized or empty.
8916 09:28:02.808557 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8917 09:28:02.815428 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8918 09:28:02.827660 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8919 09:28:02.839429 BS: romstage times (exec / console): total (unknown) / 22928 ms
8920 09:28:02.840014
8921 09:28:02.840560
8922 09:28:02.848938 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8923 09:28:02.852260 ARM64: Exception handlers installed.
8924 09:28:02.855890 ARM64: Testing exception
8925 09:28:02.859393 ARM64: Done test exception
8926 09:28:02.859872 Enumerating buses...
8927 09:28:02.862254 Show all devs... Before device enumeration.
8928 09:28:02.866161 Root Device: enabled 1
8929 09:28:02.868877 CPU_CLUSTER: 0: enabled 1
8930 09:28:02.869359 CPU: 00: enabled 1
8931 09:28:02.872645 Compare with tree...
8932 09:28:02.873296 Root Device: enabled 1
8933 09:28:02.875860 CPU_CLUSTER: 0: enabled 1
8934 09:28:02.878858 CPU: 00: enabled 1
8935 09:28:02.879338 Root Device scanning...
8936 09:28:02.882509 scan_static_bus for Root Device
8937 09:28:02.885924 CPU_CLUSTER: 0 enabled
8938 09:28:02.889184 scan_static_bus for Root Device done
8939 09:28:02.892527 scan_bus: bus Root Device finished in 8 msecs
8940 09:28:02.893115 done
8941 09:28:02.899133 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8942 09:28:02.902418 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8943 09:28:02.908963 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8944 09:28:02.912119 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8945 09:28:02.915840 Allocating resources...
8946 09:28:02.918915 Reading resources...
8947 09:28:02.922379 Root Device read_resources bus 0 link: 0
8948 09:28:02.922960 DRAM rank0 size:0x80000000,
8949 09:28:02.925278 DRAM rank1 size=0x80000000
8950 09:28:02.928856 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8951 09:28:02.932230 CPU: 00 missing read_resources
8952 09:28:02.935416 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8953 09:28:02.942294 Root Device read_resources bus 0 link: 0 done
8954 09:28:02.942879 Done reading resources.
8955 09:28:02.948497 Show resources in subtree (Root Device)...After reading.
8956 09:28:02.951952 Root Device child on link 0 CPU_CLUSTER: 0
8957 09:28:02.955354 CPU_CLUSTER: 0 child on link 0 CPU: 00
8958 09:28:02.964956 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8959 09:28:02.965451 CPU: 00
8960 09:28:02.968292 Root Device assign_resources, bus 0 link: 0
8961 09:28:02.971570 CPU_CLUSTER: 0 missing set_resources
8962 09:28:02.978230 Root Device assign_resources, bus 0 link: 0 done
8963 09:28:02.978699 Done setting resources.
8964 09:28:02.985675 Show resources in subtree (Root Device)...After assigning values.
8965 09:28:02.988531 Root Device child on link 0 CPU_CLUSTER: 0
8966 09:28:02.991947 CPU_CLUSTER: 0 child on link 0 CPU: 00
8967 09:28:03.001918 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8968 09:28:03.002489 CPU: 00
8969 09:28:03.004813 Done allocating resources.
8970 09:28:03.008420 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8971 09:28:03.011748 Enabling resources...
8972 09:28:03.012207 done.
8973 09:28:03.018405 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8974 09:28:03.018972 Initializing devices...
8975 09:28:03.021619 Root Device init
8976 09:28:03.022189 init hardware done!
8977 09:28:03.024672 0x00000018: ctrlr->caps
8978 09:28:03.027922 52.000 MHz: ctrlr->f_max
8979 09:28:03.028532 0.400 MHz: ctrlr->f_min
8980 09:28:03.031215 0x40ff8080: ctrlr->voltages
8981 09:28:03.031689 sclk: 390625
8982 09:28:03.034638 Bus Width = 1
8983 09:28:03.035103 sclk: 390625
8984 09:28:03.038035 Bus Width = 1
8985 09:28:03.038605 Early init status = 3
8986 09:28:03.044911 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8987 09:28:03.047760 in-header: 03 fc 00 00 01 00 00 00
8988 09:28:03.050995 in-data: 00
8989 09:28:03.054760 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8990 09:28:03.058928 in-header: 03 fd 00 00 00 00 00 00
8991 09:28:03.062395 in-data:
8992 09:28:03.065313 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8993 09:28:03.069531 in-header: 03 fc 00 00 01 00 00 00
8994 09:28:03.073067 in-data: 00
8995 09:28:03.076046 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8996 09:28:03.081963 in-header: 03 fd 00 00 00 00 00 00
8997 09:28:03.085216 in-data:
8998 09:28:03.088595 [SSUSB] Setting up USB HOST controller...
8999 09:28:03.092247 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9000 09:28:03.095054 [SSUSB] phy power-on done.
9001 09:28:03.098710 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9002 09:28:03.105184 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9003 09:28:03.108893 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9004 09:28:03.115413 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9005 09:28:03.121951 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9006 09:28:03.128418 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9007 09:28:03.135163 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9008 09:28:03.141804 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9009 09:28:03.145143 SPM: binary array size = 0x9dc
9010 09:28:03.148015 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9011 09:28:03.155181 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9012 09:28:03.161486 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9013 09:28:03.168089 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9014 09:28:03.171259 configure_display: Starting display init
9015 09:28:03.205269 anx7625_power_on_init: Init interface.
9016 09:28:03.208719 anx7625_disable_pd_protocol: Disabled PD feature.
9017 09:28:03.211827 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9018 09:28:03.240222 anx7625_start_dp_work: Secure OCM version=00
9019 09:28:03.243159 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9020 09:28:03.258171 sp_tx_get_edid_block: EDID Block = 1
9021 09:28:03.360314 Extracted contents:
9022 09:28:03.363630 header: 00 ff ff ff ff ff ff 00
9023 09:28:03.366983 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9024 09:28:03.370069 version: 01 04
9025 09:28:03.373281 basic params: 95 1f 11 78 0a
9026 09:28:03.376547 chroma info: 76 90 94 55 54 90 27 21 50 54
9027 09:28:03.380098 established: 00 00 00
9028 09:28:03.387163 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9029 09:28:03.393329 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9030 09:28:03.396828 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9031 09:28:03.403329 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9032 09:28:03.409673 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9033 09:28:03.412895 extensions: 00
9034 09:28:03.413361 checksum: fb
9035 09:28:03.413740
9036 09:28:03.416647 Manufacturer: IVO Model 57d Serial Number 0
9037 09:28:03.419859 Made week 0 of 2020
9038 09:28:03.422983 EDID version: 1.4
9039 09:28:03.423445 Digital display
9040 09:28:03.426759 6 bits per primary color channel
9041 09:28:03.427467 DisplayPort interface
9042 09:28:03.429595 Maximum image size: 31 cm x 17 cm
9043 09:28:03.432991 Gamma: 220%
9044 09:28:03.433452 Check DPMS levels
9045 09:28:03.436434 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9046 09:28:03.443277 First detailed timing is preferred timing
9047 09:28:03.443866 Established timings supported:
9048 09:28:03.446973 Standard timings supported:
9049 09:28:03.449665 Detailed timings
9050 09:28:03.452875 Hex of detail: 383680a07038204018303c0035ae10000019
9051 09:28:03.456113 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9052 09:28:03.462623 0780 0798 07c8 0820 hborder 0
9053 09:28:03.466568 0438 043b 0447 0458 vborder 0
9054 09:28:03.469520 -hsync -vsync
9055 09:28:03.469986 Did detailed timing
9056 09:28:03.476311 Hex of detail: 000000000000000000000000000000000000
9057 09:28:03.479616 Manufacturer-specified data, tag 0
9058 09:28:03.482713 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9059 09:28:03.486035 ASCII string: InfoVision
9060 09:28:03.489795 Hex of detail: 000000fe00523134304e574635205248200a
9061 09:28:03.493154 ASCII string: R140NWF5 RH
9062 09:28:03.493723 Checksum
9063 09:28:03.496448 Checksum: 0xfb (valid)
9064 09:28:03.499501 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9065 09:28:03.502793 DSI data_rate: 832800000 bps
9066 09:28:03.509554 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9067 09:28:03.512646 anx7625_parse_edid: pixelclock(138800).
9068 09:28:03.516063 hactive(1920), hsync(48), hfp(24), hbp(88)
9069 09:28:03.519466 vactive(1080), vsync(12), vfp(3), vbp(17)
9070 09:28:03.522640 anx7625_dsi_config: config dsi.
9071 09:28:03.529266 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9072 09:28:03.542402 anx7625_dsi_config: success to config DSI
9073 09:28:03.546555 anx7625_dp_start: MIPI phy setup OK.
9074 09:28:03.548827 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9075 09:28:03.552385 mtk_ddp_mode_set invalid vrefresh 60
9076 09:28:03.555769 main_disp_path_setup
9077 09:28:03.556383 ovl_layer_smi_id_en
9078 09:28:03.559230 ovl_layer_smi_id_en
9079 09:28:03.559915 ccorr_config
9080 09:28:03.560352 aal_config
9081 09:28:03.562237 gamma_config
9082 09:28:03.562764 postmask_config
9083 09:28:03.566117 dither_config
9084 09:28:03.568698 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9085 09:28:03.575645 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9086 09:28:03.579133 Root Device init finished in 554 msecs
9087 09:28:03.582418 CPU_CLUSTER: 0 init
9088 09:28:03.589163 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9089 09:28:03.591874 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9090 09:28:03.595407 APU_MBOX 0x190000b0 = 0x10001
9091 09:28:03.598437 APU_MBOX 0x190001b0 = 0x10001
9092 09:28:03.602103 APU_MBOX 0x190005b0 = 0x10001
9093 09:28:03.605145 APU_MBOX 0x190006b0 = 0x10001
9094 09:28:03.608969 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9095 09:28:03.621389 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9096 09:28:03.633943 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9097 09:28:03.640428 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9098 09:28:03.651731 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9099 09:28:03.661432 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9100 09:28:03.664158 CPU_CLUSTER: 0 init finished in 81 msecs
9101 09:28:03.667824 Devices initialized
9102 09:28:03.670735 Show all devs... After init.
9103 09:28:03.671196 Root Device: enabled 1
9104 09:28:03.674291 CPU_CLUSTER: 0: enabled 1
9105 09:28:03.677722 CPU: 00: enabled 1
9106 09:28:03.680780 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9107 09:28:03.684286 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9108 09:28:03.687574 ELOG: NV offset 0x57f000 size 0x1000
9109 09:28:03.694147 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9110 09:28:03.700903 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9111 09:28:03.704445 ELOG: Event(17) added with size 13 at 2023-10-20 09:28:04 UTC
9112 09:28:03.710423 out: cmd=0x121: 03 db 21 01 00 00 00 00
9113 09:28:03.713876 in-header: 03 1d 00 00 2c 00 00 00
9114 09:28:03.727430 in-data: 46 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9115 09:28:03.730653 ELOG: Event(A1) added with size 10 at 2023-10-20 09:28:04 UTC
9116 09:28:03.737286 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9117 09:28:03.743899 ELOG: Event(A0) added with size 9 at 2023-10-20 09:28:04 UTC
9118 09:28:03.747314 elog_add_boot_reason: Logged dev mode boot
9119 09:28:03.753609 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9120 09:28:03.754099 Finalize devices...
9121 09:28:03.757112 Devices finalized
9122 09:28:03.760575 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9123 09:28:03.763947 Writing coreboot table at 0xffe64000
9124 09:28:03.767458 0. 000000000010a000-0000000000113fff: RAMSTAGE
9125 09:28:03.773676 1. 0000000040000000-00000000400fffff: RAM
9126 09:28:03.777117 2. 0000000040100000-000000004032afff: RAMSTAGE
9127 09:28:03.780295 3. 000000004032b000-00000000545fffff: RAM
9128 09:28:03.783782 4. 0000000054600000-000000005465ffff: BL31
9129 09:28:03.786823 5. 0000000054660000-00000000ffe63fff: RAM
9130 09:28:03.793513 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9131 09:28:03.797004 7. 0000000100000000-000000013fffffff: RAM
9132 09:28:03.800024 Passing 5 GPIOs to payload:
9133 09:28:03.803771 NAME | PORT | POLARITY | VALUE
9134 09:28:03.810222 EC in RW | 0x000000aa | low | undefined
9135 09:28:03.813895 EC interrupt | 0x00000005 | low | undefined
9136 09:28:03.820085 TPM interrupt | 0x000000ab | high | undefined
9137 09:28:03.823179 SD card detect | 0x00000011 | high | undefined
9138 09:28:03.826819 speaker enable | 0x00000093 | high | undefined
9139 09:28:03.830244 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9140 09:28:03.833259 in-header: 03 f4 00 00 02 00 00 00
9141 09:28:03.836635 in-data: 07 00
9142 09:28:03.840052 ADC[4]: Raw value=668590 ID=5
9143 09:28:03.843149 ADC[3]: Raw value=212549 ID=1
9144 09:28:03.843708 RAM Code: 0x51
9145 09:28:03.846166 ADC[6]: Raw value=74410 ID=0
9146 09:28:03.849792 ADC[5]: Raw value=211812 ID=1
9147 09:28:03.850326 SKU Code: 0x1
9148 09:28:03.856254 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1637
9149 09:28:03.856692 coreboot table: 964 bytes.
9150 09:28:03.859714 IMD ROOT 0. 0xfffff000 0x00001000
9151 09:28:03.863101 IMD SMALL 1. 0xffffe000 0x00001000
9152 09:28:03.866539 RO MCACHE 2. 0xffffc000 0x00001104
9153 09:28:03.869567 CONSOLE 3. 0xfff7c000 0x00080000
9154 09:28:03.872716 FMAP 4. 0xfff7b000 0x00000452
9155 09:28:03.876393 TIME STAMP 5. 0xfff7a000 0x00000910
9156 09:28:03.879470 VBOOT WORK 6. 0xfff66000 0x00014000
9157 09:28:03.882912 RAMOOPS 7. 0xffe66000 0x00100000
9158 09:28:03.886190 COREBOOT 8. 0xffe64000 0x00002000
9159 09:28:03.889656 IMD small region:
9160 09:28:03.892880 IMD ROOT 0. 0xffffec00 0x00000400
9161 09:28:03.896016 VPD 1. 0xffffeb80 0x0000006c
9162 09:28:03.899623 MMC STATUS 2. 0xffffeb60 0x00000004
9163 09:28:03.902945 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9164 09:28:03.906184 Probing TPM: done!
9165 09:28:03.909691 Connected to device vid:did:rid of 1ae0:0028:00
9166 09:28:03.920873 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9167 09:28:03.924614 Initialized TPM device CR50 revision 0
9168 09:28:03.927362 Checking cr50 for pending updates
9169 09:28:03.931298 Reading cr50 TPM mode
9170 09:28:03.940156 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9171 09:28:03.946664 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9172 09:28:03.987137 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9173 09:28:03.990058 Checking segment from ROM address 0x40100000
9174 09:28:03.993399 Checking segment from ROM address 0x4010001c
9175 09:28:04.000374 Loading segment from ROM address 0x40100000
9176 09:28:04.000938 code (compression=0)
9177 09:28:04.010064 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9178 09:28:04.016839 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9179 09:28:04.017411 it's not compressed!
9180 09:28:04.023013 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9181 09:28:04.029891 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9182 09:28:04.047395 Loading segment from ROM address 0x4010001c
9183 09:28:04.047968 Entry Point 0x80000000
9184 09:28:04.050531 Loaded segments
9185 09:28:04.053872 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9186 09:28:04.060468 Jumping to boot code at 0x80000000(0xffe64000)
9187 09:28:04.067329 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9188 09:28:04.074004 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9189 09:28:04.081648 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9190 09:28:04.084794 Checking segment from ROM address 0x40100000
9191 09:28:04.088279 Checking segment from ROM address 0x4010001c
9192 09:28:04.094910 Loading segment from ROM address 0x40100000
9193 09:28:04.095379 code (compression=1)
9194 09:28:04.101588 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9195 09:28:04.111565 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9196 09:28:04.112150 using LZMA
9197 09:28:04.120092 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9198 09:28:04.126997 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9199 09:28:04.129915 Loading segment from ROM address 0x4010001c
9200 09:28:04.130504 Entry Point 0x54601000
9201 09:28:04.133046 Loaded segments
9202 09:28:04.136922 NOTICE: MT8192 bl31_setup
9203 09:28:04.143222 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9204 09:28:04.147061 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9205 09:28:04.150263 WARNING: region 0:
9206 09:28:04.153333 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9207 09:28:04.153992 WARNING: region 1:
9208 09:28:04.159886 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9209 09:28:04.163495 WARNING: region 2:
9210 09:28:04.166685 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9211 09:28:04.170074 WARNING: region 3:
9212 09:28:04.173413 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9213 09:28:04.176596 WARNING: region 4:
9214 09:28:04.183608 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9215 09:28:04.184225 WARNING: region 5:
9216 09:28:04.187218 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9217 09:28:04.190287 WARNING: region 6:
9218 09:28:04.193629 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9219 09:28:04.196802 WARNING: region 7:
9220 09:28:04.199956 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9221 09:28:04.206835 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9222 09:28:04.210424 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9223 09:28:04.213330 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9224 09:28:04.220026 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9225 09:28:04.223427 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9226 09:28:04.226560 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9227 09:28:04.233360 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9228 09:28:04.236880 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9229 09:28:04.243636 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9230 09:28:04.246745 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9231 09:28:04.250169 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9232 09:28:04.257488 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9233 09:28:04.260102 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9234 09:28:04.263623 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9235 09:28:04.270221 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9236 09:28:04.273380 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9237 09:28:04.277006 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9238 09:28:04.283547 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9239 09:28:04.286970 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9240 09:28:04.290240 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9241 09:28:04.297191 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9242 09:28:04.300553 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9243 09:28:04.307181 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9244 09:28:04.310734 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9245 09:28:04.316690 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9246 09:28:04.320555 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9247 09:28:04.323865 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9248 09:28:04.330650 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9249 09:28:04.333335 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9250 09:28:04.336625 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9251 09:28:04.344202 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9252 09:28:04.346956 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9253 09:28:04.350324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9254 09:28:04.356746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9255 09:28:04.360403 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9256 09:28:04.363914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9257 09:28:04.367148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9258 09:28:04.373631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9259 09:28:04.377291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9260 09:28:04.380400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9261 09:28:04.383631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9262 09:28:04.390215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9263 09:28:04.393496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9264 09:28:04.396911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9265 09:28:04.400130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9266 09:28:04.407288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9267 09:28:04.410527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9268 09:28:04.413751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9269 09:28:04.420298 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9270 09:28:04.423499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9271 09:28:04.430152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9272 09:28:04.433494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9273 09:28:04.436832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9274 09:28:04.443453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9275 09:28:04.446828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9276 09:28:04.453722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9277 09:28:04.457004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9278 09:28:04.460210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9279 09:28:04.466902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9280 09:28:04.470245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9281 09:28:04.476886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9282 09:28:04.480153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9283 09:28:04.487077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9284 09:28:04.490197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9285 09:28:04.496788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9286 09:28:04.500025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9287 09:28:04.503704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9288 09:28:04.510159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9289 09:28:04.513455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9290 09:28:04.520016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9291 09:28:04.523585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9292 09:28:04.530378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9293 09:28:04.533202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9294 09:28:04.536837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9295 09:28:04.543217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9296 09:28:04.546809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9297 09:28:04.553166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9298 09:28:04.556389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9299 09:28:04.563308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9300 09:28:04.566583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9301 09:28:04.572838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9302 09:28:04.576717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9303 09:28:04.579746 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9304 09:28:04.586607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9305 09:28:04.590130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9306 09:28:04.596842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9307 09:28:04.599942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9308 09:28:04.606891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9309 09:28:04.609787 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9310 09:28:04.613322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9311 09:28:04.619901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9312 09:28:04.623180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9313 09:28:04.629986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9314 09:28:04.633006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9315 09:28:04.639796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9316 09:28:04.643300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9317 09:28:04.646515 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9318 09:28:04.653099 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9319 09:28:04.656667 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9320 09:28:04.659876 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9321 09:28:04.663536 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9322 09:28:04.669920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9323 09:28:04.673268 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9324 09:28:04.680134 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9325 09:28:04.682987 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9326 09:28:04.686446 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9327 09:28:04.693295 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9328 09:28:04.696609 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9329 09:28:04.700411 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9330 09:28:04.706977 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9331 09:28:04.709907 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9332 09:28:04.716974 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9333 09:28:04.720305 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9334 09:28:04.723291 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9335 09:28:04.730424 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9336 09:28:04.733472 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9337 09:28:04.736627 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9338 09:28:04.743669 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9339 09:28:04.746910 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9340 09:28:04.750227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9341 09:28:04.753607 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9342 09:28:04.760334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9343 09:28:04.763924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9344 09:28:04.766835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9345 09:28:04.773394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9346 09:28:04.776708 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9347 09:28:04.779863 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9348 09:28:04.786535 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9349 09:28:04.789799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9350 09:28:04.796710 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9351 09:28:04.800033 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9352 09:28:04.803048 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9353 09:28:04.809854 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9354 09:28:04.813053 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9355 09:28:04.819731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9356 09:28:04.822975 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9357 09:28:04.826739 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9358 09:28:04.833349 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9359 09:28:04.836915 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9360 09:28:04.839868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9361 09:28:04.846138 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9362 09:28:04.849887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9363 09:28:04.856461 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9364 09:28:04.860243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9365 09:28:04.862970 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9366 09:28:04.869511 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9367 09:28:04.872869 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9368 09:28:04.879664 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9369 09:28:04.883046 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9370 09:28:04.886344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9371 09:28:04.893104 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9372 09:28:04.896412 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9373 09:28:04.900059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9374 09:28:04.906721 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9375 09:28:04.909916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9376 09:28:04.916525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9377 09:28:04.920168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9378 09:28:04.923229 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9379 09:28:04.929988 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9380 09:28:04.933226 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9381 09:28:04.939883 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9382 09:28:04.943182 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9383 09:28:04.946921 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9384 09:28:04.953172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9385 09:28:04.956944 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9386 09:28:04.962845 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9387 09:28:04.966381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9388 09:28:04.969443 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9389 09:28:04.976162 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9390 09:28:04.979692 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9391 09:28:04.986299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9392 09:28:04.989595 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9393 09:28:04.992768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9394 09:28:04.999794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9395 09:28:05.002954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9396 09:28:05.006552 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9397 09:28:05.012807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9398 09:28:05.016099 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9399 09:28:05.022624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9400 09:28:05.026183 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9401 09:28:05.029407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9402 09:28:05.035845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9403 09:28:05.039657 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9404 09:28:05.046130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9405 09:28:05.049379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9406 09:28:05.052655 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9407 09:28:05.059499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9408 09:28:05.062439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9409 09:28:05.069259 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9410 09:28:05.072413 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9411 09:28:05.075932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9412 09:28:05.082364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9413 09:28:05.085528 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9414 09:28:05.092370 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9415 09:28:05.095710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9416 09:28:05.102301 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9417 09:28:05.105772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9418 09:28:05.109079 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9419 09:28:05.115461 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9420 09:28:05.118779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9421 09:28:05.125554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9422 09:28:05.128687 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9423 09:28:05.132273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9424 09:28:05.139018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9425 09:28:05.142377 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9426 09:28:05.148669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9427 09:28:05.152438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9428 09:28:05.158597 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9429 09:28:05.161982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9430 09:28:05.165294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9431 09:28:05.171824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9432 09:28:05.175059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9433 09:28:05.181885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9434 09:28:05.185223 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9435 09:28:05.188365 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9436 09:28:05.195048 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9437 09:28:05.198761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9438 09:28:05.204914 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9439 09:28:05.208491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9440 09:28:05.214897 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9441 09:28:05.218464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9442 09:28:05.221913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9443 09:28:05.228372 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9444 09:28:05.231541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9445 09:28:05.238206 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9446 09:28:05.241928 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9447 09:28:05.245126 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9448 09:28:05.251683 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9449 09:28:05.254800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9450 09:28:05.258281 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9451 09:28:05.264702 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9452 09:28:05.268143 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9453 09:28:05.271564 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9454 09:28:05.274764 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9455 09:28:05.281281 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9456 09:28:05.284682 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9457 09:28:05.291608 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9458 09:28:05.294845 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9459 09:28:05.297991 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9460 09:28:05.304556 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9461 09:28:05.308239 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9462 09:28:05.311554 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9463 09:28:05.318277 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9464 09:28:05.321308 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9465 09:28:05.324726 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9466 09:28:05.331472 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9467 09:28:05.334550 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9468 09:28:05.341767 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9469 09:28:05.344925 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9470 09:28:05.347939 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9471 09:28:05.354921 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9472 09:28:05.357927 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9473 09:28:05.361195 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9474 09:28:05.368525 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9475 09:28:05.371230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9476 09:28:05.374508 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9477 09:28:05.380862 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9478 09:28:05.384562 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9479 09:28:05.387792 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9480 09:28:05.394513 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9481 09:28:05.397583 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9482 09:28:05.404288 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9483 09:28:05.407560 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9484 09:28:05.410739 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9485 09:28:05.417357 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9486 09:28:05.420844 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9487 09:28:05.427691 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9488 09:28:05.430785 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9489 09:28:05.434200 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9490 09:28:05.437562 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9491 09:28:05.444210 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9492 09:28:05.447684 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9493 09:28:05.450693 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9494 09:28:05.454407 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9495 09:28:05.460914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9496 09:28:05.463909 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9497 09:28:05.467334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9498 09:28:05.470532 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9499 09:28:05.477134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9500 09:28:05.480583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9501 09:28:05.483848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9502 09:28:05.487197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9503 09:28:05.494062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9504 09:28:05.497371 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9505 09:28:05.503967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9506 09:28:05.507255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9507 09:28:05.513479 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9508 09:28:05.517080 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9509 09:28:05.520528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9510 09:28:05.526738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9511 09:28:05.530228 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9512 09:28:05.536612 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9513 09:28:05.540248 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9514 09:28:05.543606 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9515 09:28:05.550508 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9516 09:28:05.554126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9517 09:28:05.559937 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9518 09:28:05.563474 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9519 09:28:05.566666 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9520 09:28:05.573343 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9521 09:28:05.576693 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9522 09:28:05.583449 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9523 09:28:05.586393 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9524 09:28:05.593607 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9525 09:28:05.596390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9526 09:28:05.600081 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9527 09:28:05.606875 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9528 09:28:05.610029 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9529 09:28:05.616371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9530 09:28:05.619600 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9531 09:28:05.623141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9532 09:28:05.629867 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9533 09:28:05.633190 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9534 09:28:05.639735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9535 09:28:05.643439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9536 09:28:05.645991 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9537 09:28:05.652987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9538 09:28:05.656082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9539 09:28:05.662747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9540 09:28:05.666277 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9541 09:28:05.672819 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9542 09:28:05.675839 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9543 09:28:05.679632 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9544 09:28:05.685980 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9545 09:28:05.689556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9546 09:28:05.695921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9547 09:28:05.699597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9548 09:28:05.703044 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9549 09:28:05.709152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9550 09:28:05.712931 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9551 09:28:05.719012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9552 09:28:05.722493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9553 09:28:05.725664 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9554 09:28:05.732468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9555 09:28:05.735783 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9556 09:28:05.742334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9557 09:28:05.745578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9558 09:28:05.749162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9559 09:28:05.755459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9560 09:28:05.758829 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9561 09:28:05.765354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9562 09:28:05.768702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9563 09:28:05.775659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9564 09:28:05.778740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9565 09:28:05.782355 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9566 09:28:05.789077 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9567 09:28:05.791997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9568 09:28:05.798563 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9569 09:28:05.802109 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9570 09:28:05.805678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9571 09:28:05.812155 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9572 09:28:05.815474 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9573 09:28:05.822081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9574 09:28:05.825504 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9575 09:28:05.829152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9576 09:28:05.835773 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9577 09:28:05.838690 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9578 09:28:05.845466 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9579 09:28:05.848922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9580 09:28:05.855310 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9581 09:28:05.858860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9582 09:28:05.861762 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9583 09:28:05.868554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9584 09:28:05.872206 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9585 09:28:05.878350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9586 09:28:05.881588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9587 09:28:05.888341 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9588 09:28:05.891847 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9589 09:28:05.898391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9590 09:28:05.901975 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9591 09:28:05.904820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9592 09:28:05.911493 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9593 09:28:05.914995 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9594 09:28:05.921808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9595 09:28:05.924734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9596 09:28:05.931732 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9597 09:28:05.934768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9598 09:28:05.937736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9599 09:28:05.944679 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9600 09:28:05.947997 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9601 09:28:05.954600 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9602 09:28:05.957850 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9603 09:28:05.964580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9604 09:28:05.967801 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9605 09:28:05.974483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9606 09:28:05.977673 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9607 09:28:05.980834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9608 09:28:05.987274 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9609 09:28:05.990976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9610 09:28:05.997430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9611 09:28:06.000896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9612 09:28:06.007320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9613 09:28:06.010788 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9614 09:28:06.013943 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9615 09:28:06.020888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9616 09:28:06.023882 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9617 09:28:06.030827 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9618 09:28:06.034067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9619 09:28:06.040536 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9620 09:28:06.043667 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9621 09:28:06.051131 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9622 09:28:06.053957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9623 09:28:06.056999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9624 09:28:06.063663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9625 09:28:06.066868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9626 09:28:06.073620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9627 09:28:06.077049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9628 09:28:06.083548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9629 09:28:06.086877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9630 09:28:06.093625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9631 09:28:06.096703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9632 09:28:06.103234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9633 09:28:06.106929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9634 09:28:06.113800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9635 09:28:06.116504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9636 09:28:06.123388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9637 09:28:06.126440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9638 09:28:06.130532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9639 09:28:06.136513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9640 09:28:06.140330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9641 09:28:06.146812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9642 09:28:06.149991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9643 09:28:06.156801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9644 09:28:06.159686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9645 09:28:06.166679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9646 09:28:06.169532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9647 09:28:06.176139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9648 09:28:06.179994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9649 09:28:06.186584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9650 09:28:06.189662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9651 09:28:06.196455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9652 09:28:06.199562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9653 09:28:06.206606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9654 09:28:06.209663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9655 09:28:06.216309 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9656 09:28:06.216951 INFO: [APUAPC] vio 0
9657 09:28:06.223399 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9658 09:28:06.226607 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9659 09:28:06.230017 INFO: [APUAPC] D0_APC_0: 0x400510
9660 09:28:06.233649 INFO: [APUAPC] D0_APC_1: 0x0
9661 09:28:06.236503 INFO: [APUAPC] D0_APC_2: 0x1540
9662 09:28:06.239699 INFO: [APUAPC] D0_APC_3: 0x0
9663 09:28:06.243311 INFO: [APUAPC] D1_APC_0: 0xffffffff
9664 09:28:06.246646 INFO: [APUAPC] D1_APC_1: 0xffffffff
9665 09:28:06.250041 INFO: [APUAPC] D1_APC_2: 0x3fffff
9666 09:28:06.253332 INFO: [APUAPC] D1_APC_3: 0x0
9667 09:28:06.256790 INFO: [APUAPC] D2_APC_0: 0xffffffff
9668 09:28:06.259788 INFO: [APUAPC] D2_APC_1: 0xffffffff
9669 09:28:06.263180 INFO: [APUAPC] D2_APC_2: 0x3fffff
9670 09:28:06.265895 INFO: [APUAPC] D2_APC_3: 0x0
9671 09:28:06.269337 INFO: [APUAPC] D3_APC_0: 0xffffffff
9672 09:28:06.272669 INFO: [APUAPC] D3_APC_1: 0xffffffff
9673 09:28:06.276082 INFO: [APUAPC] D3_APC_2: 0x3fffff
9674 09:28:06.279558 INFO: [APUAPC] D3_APC_3: 0x0
9675 09:28:06.282720 INFO: [APUAPC] D4_APC_0: 0xffffffff
9676 09:28:06.286057 INFO: [APUAPC] D4_APC_1: 0xffffffff
9677 09:28:06.289163 INFO: [APUAPC] D4_APC_2: 0x3fffff
9678 09:28:06.292787 INFO: [APUAPC] D4_APC_3: 0x0
9679 09:28:06.296066 INFO: [APUAPC] D5_APC_0: 0xffffffff
9680 09:28:06.299548 INFO: [APUAPC] D5_APC_1: 0xffffffff
9681 09:28:06.302948 INFO: [APUAPC] D5_APC_2: 0x3fffff
9682 09:28:06.305792 INFO: [APUAPC] D5_APC_3: 0x0
9683 09:28:06.309184 INFO: [APUAPC] D6_APC_0: 0xffffffff
9684 09:28:06.312587 INFO: [APUAPC] D6_APC_1: 0xffffffff
9685 09:28:06.315958 INFO: [APUAPC] D6_APC_2: 0x3fffff
9686 09:28:06.316558 INFO: [APUAPC] D6_APC_3: 0x0
9687 09:28:06.319401 INFO: [APUAPC] D7_APC_0: 0xffffffff
9688 09:28:06.322415 INFO: [APUAPC] D7_APC_1: 0xffffffff
9689 09:28:06.325655 INFO: [APUAPC] D7_APC_2: 0x3fffff
9690 09:28:06.329373 INFO: [APUAPC] D7_APC_3: 0x0
9691 09:28:06.332349 INFO: [APUAPC] D8_APC_0: 0xffffffff
9692 09:28:06.335637 INFO: [APUAPC] D8_APC_1: 0xffffffff
9693 09:28:06.339159 INFO: [APUAPC] D8_APC_2: 0x3fffff
9694 09:28:06.342473 INFO: [APUAPC] D8_APC_3: 0x0
9695 09:28:06.345845 INFO: [APUAPC] D9_APC_0: 0xffffffff
9696 09:28:06.348939 INFO: [APUAPC] D9_APC_1: 0xffffffff
9697 09:28:06.352556 INFO: [APUAPC] D9_APC_2: 0x3fffff
9698 09:28:06.355911 INFO: [APUAPC] D9_APC_3: 0x0
9699 09:28:06.358998 INFO: [APUAPC] D10_APC_0: 0xffffffff
9700 09:28:06.362461 INFO: [APUAPC] D10_APC_1: 0xffffffff
9701 09:28:06.365237 INFO: [APUAPC] D10_APC_2: 0x3fffff
9702 09:28:06.368968 INFO: [APUAPC] D10_APC_3: 0x0
9703 09:28:06.372521 INFO: [APUAPC] D11_APC_0: 0xffffffff
9704 09:28:06.375338 INFO: [APUAPC] D11_APC_1: 0xffffffff
9705 09:28:06.378966 INFO: [APUAPC] D11_APC_2: 0x3fffff
9706 09:28:06.381929 INFO: [APUAPC] D11_APC_3: 0x0
9707 09:28:06.385745 INFO: [APUAPC] D12_APC_0: 0xffffffff
9708 09:28:06.388622 INFO: [APUAPC] D12_APC_1: 0xffffffff
9709 09:28:06.392249 INFO: [APUAPC] D12_APC_2: 0x3fffff
9710 09:28:06.395088 INFO: [APUAPC] D12_APC_3: 0x0
9711 09:28:06.398905 INFO: [APUAPC] D13_APC_0: 0xffffffff
9712 09:28:06.402185 INFO: [APUAPC] D13_APC_1: 0xffffffff
9713 09:28:06.405458 INFO: [APUAPC] D13_APC_2: 0x3fffff
9714 09:28:06.408541 INFO: [APUAPC] D13_APC_3: 0x0
9715 09:28:06.411872 INFO: [APUAPC] D14_APC_0: 0xffffffff
9716 09:28:06.415465 INFO: [APUAPC] D14_APC_1: 0xffffffff
9717 09:28:06.418597 INFO: [APUAPC] D14_APC_2: 0x3fffff
9718 09:28:06.422107 INFO: [APUAPC] D14_APC_3: 0x0
9719 09:28:06.424792 INFO: [APUAPC] D15_APC_0: 0xffffffff
9720 09:28:06.431769 INFO: [APUAPC] D15_APC_1: 0xffffffff
9721 09:28:06.435175 INFO: [APUAPC] D15_APC_2: 0x3fffff
9722 09:28:06.435755 INFO: [APUAPC] D15_APC_3: 0x0
9723 09:28:06.438035 INFO: [APUAPC] APC_CON: 0x4
9724 09:28:06.441512 INFO: [NOCDAPC] D0_APC_0: 0x0
9725 09:28:06.444677 INFO: [NOCDAPC] D0_APC_1: 0x0
9726 09:28:06.448085 INFO: [NOCDAPC] D1_APC_0: 0x0
9727 09:28:06.451356 INFO: [NOCDAPC] D1_APC_1: 0xfff
9728 09:28:06.454954 INFO: [NOCDAPC] D2_APC_0: 0x0
9729 09:28:06.458036 INFO: [NOCDAPC] D2_APC_1: 0xfff
9730 09:28:06.461123 INFO: [NOCDAPC] D3_APC_0: 0x0
9731 09:28:06.464565 INFO: [NOCDAPC] D3_APC_1: 0xfff
9732 09:28:06.465134 INFO: [NOCDAPC] D4_APC_0: 0x0
9733 09:28:06.467535 INFO: [NOCDAPC] D4_APC_1: 0xfff
9734 09:28:06.471013 INFO: [NOCDAPC] D5_APC_0: 0x0
9735 09:28:06.474724 INFO: [NOCDAPC] D5_APC_1: 0xfff
9736 09:28:06.477722 INFO: [NOCDAPC] D6_APC_0: 0x0
9737 09:28:06.481345 INFO: [NOCDAPC] D6_APC_1: 0xfff
9738 09:28:06.484291 INFO: [NOCDAPC] D7_APC_0: 0x0
9739 09:28:06.487832 INFO: [NOCDAPC] D7_APC_1: 0xfff
9740 09:28:06.490939 INFO: [NOCDAPC] D8_APC_0: 0x0
9741 09:28:06.494233 INFO: [NOCDAPC] D8_APC_1: 0xfff
9742 09:28:06.497681 INFO: [NOCDAPC] D9_APC_0: 0x0
9743 09:28:06.500879 INFO: [NOCDAPC] D9_APC_1: 0xfff
9744 09:28:06.501439 INFO: [NOCDAPC] D10_APC_0: 0x0
9745 09:28:06.504687 INFO: [NOCDAPC] D10_APC_1: 0xfff
9746 09:28:06.507763 INFO: [NOCDAPC] D11_APC_0: 0x0
9747 09:28:06.511137 INFO: [NOCDAPC] D11_APC_1: 0xfff
9748 09:28:06.514540 INFO: [NOCDAPC] D12_APC_0: 0x0
9749 09:28:06.517204 INFO: [NOCDAPC] D12_APC_1: 0xfff
9750 09:28:06.520871 INFO: [NOCDAPC] D13_APC_0: 0x0
9751 09:28:06.524530 INFO: [NOCDAPC] D13_APC_1: 0xfff
9752 09:28:06.527674 INFO: [NOCDAPC] D14_APC_0: 0x0
9753 09:28:06.530485 INFO: [NOCDAPC] D14_APC_1: 0xfff
9754 09:28:06.534023 INFO: [NOCDAPC] D15_APC_0: 0x0
9755 09:28:06.537673 INFO: [NOCDAPC] D15_APC_1: 0xfff
9756 09:28:06.540673 INFO: [NOCDAPC] APC_CON: 0x4
9757 09:28:06.544048 INFO: [APUAPC] set_apusys_apc done
9758 09:28:06.547612 INFO: [DEVAPC] devapc_init done
9759 09:28:06.550509 INFO: GICv3 without legacy support detected.
9760 09:28:06.553877 INFO: ARM GICv3 driver initialized in EL3
9761 09:28:06.556997 INFO: Maximum SPI INTID supported: 639
9762 09:28:06.560622 INFO: BL31: Initializing runtime services
9763 09:28:06.567051 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9764 09:28:06.570611 INFO: SPM: enable CPC mode
9765 09:28:06.573643 INFO: mcdi ready for mcusys-off-idle and system suspend
9766 09:28:06.580517 INFO: BL31: Preparing for EL3 exit to normal world
9767 09:28:06.583678 INFO: Entry point address = 0x80000000
9768 09:28:06.587158 INFO: SPSR = 0x8
9769 09:28:06.591272
9770 09:28:06.591821
9771 09:28:06.592210
9772 09:28:06.594584 Starting depthcharge on Spherion...
9773 09:28:06.595329
9774 09:28:06.595763 Wipe memory regions:
9775 09:28:06.596110
9776 09:28:06.598770 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9777 09:28:06.599306 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9778 09:28:06.600933 Setting prompt string to ['asurada:']
9779 09:28:06.601403 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9780 09:28:06.602127 [0x00000040000000, 0x00000054600000)
9781 09:28:06.720533
9782 09:28:06.721089 [0x00000054660000, 0x00000080000000)
9783 09:28:06.980303
9784 09:28:06.980823 [0x000000821a7280, 0x000000ffe64000)
9785 09:28:07.724915
9786 09:28:07.725485 [0x00000100000000, 0x00000140000000)
9787 09:28:08.105854
9788 09:28:08.108821 Initializing XHCI USB controller at 0x11200000.
9789 09:28:09.147038
9790 09:28:09.150008 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9791 09:28:09.150473
9792 09:28:09.150838
9793 09:28:09.151177
9794 09:28:09.152054 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9796 09:28:09.253454 asurada: tftpboot 192.168.201.1 11826831/tftp-deploy-_m38mr1m/kernel/image.itb 11826831/tftp-deploy-_m38mr1m/kernel/cmdline
9797 09:28:09.254108 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9798 09:28:09.254581 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9799 09:28:09.259058 tftpboot 192.168.201.1 11826831/tftp-deploy-_m38mr1m/kernel/image.itp-deploy-_m38mr1m/kernel/cmdline
9800 09:28:09.259594
9801 09:28:09.259968 Waiting for link
9802 09:28:09.419977
9803 09:28:09.420586 R8152: Initializing
9804 09:28:09.420972
9805 09:28:09.422706 Version 9 (ocp_data = 6010)
9806 09:28:09.423170
9807 09:28:09.426491 R8152: Done initializing
9808 09:28:09.427046
9809 09:28:09.427418 Adding net device
9810 09:28:11.308981
9811 09:28:11.309550 done.
9812 09:28:11.309944
9813 09:28:11.310292 MAC: 00:e0:4c:68:03:bd
9814 09:28:11.310711
9815 09:28:11.312142 Sending DHCP discover... done.
9816 09:28:11.312699
9817 09:28:11.315228 Waiting for reply... done.
9818 09:28:11.315687
9819 09:28:11.318505 Sending DHCP request... done.
9820 09:28:11.318964
9821 09:28:11.324810 Waiting for reply... done.
9822 09:28:11.325387
9823 09:28:11.325931 My ip is 192.168.201.16
9824 09:28:11.326327
9825 09:28:11.327843 The DHCP server ip is 192.168.201.1
9826 09:28:11.328374
9827 09:28:11.334731 TFTP server IP predefined by user: 192.168.201.1
9828 09:28:11.335196
9829 09:28:11.342023 Bootfile predefined by user: 11826831/tftp-deploy-_m38mr1m/kernel/image.itb
9830 09:28:11.342628
9831 09:28:11.344835 Sending tftp read request... done.
9832 09:28:11.345298
9833 09:28:11.351214 Waiting for the transfer...
9834 09:28:11.351747
9835 09:28:11.661132 00000000 ################################################################
9836 09:28:11.661271
9837 09:28:11.959418 00080000 ################################################################
9838 09:28:11.959556
9839 09:28:12.258016 00100000 ################################################################
9840 09:28:12.258151
9841 09:28:12.560354 00180000 ################################################################
9842 09:28:12.560493
9843 09:28:12.863989 00200000 ################################################################
9844 09:28:12.864127
9845 09:28:13.166989 00280000 ################################################################
9846 09:28:13.167126
9847 09:28:13.469650 00300000 ################################################################
9848 09:28:13.469788
9849 09:28:13.768110 00380000 ################################################################
9850 09:28:13.768258
9851 09:28:14.062990 00400000 ################################################################
9852 09:28:14.063159
9853 09:28:14.367342 00480000 ################################################################
9854 09:28:14.367479
9855 09:28:14.671091 00500000 ################################################################
9856 09:28:14.671231
9857 09:28:14.975409 00580000 ################################################################
9858 09:28:14.975543
9859 09:28:15.280035 00600000 ################################################################
9860 09:28:15.280169
9861 09:28:15.583518 00680000 ################################################################
9862 09:28:15.583655
9863 09:28:15.841816 00700000 ################################################################
9864 09:28:15.841954
9865 09:28:16.113359 00780000 ################################################################
9866 09:28:16.113490
9867 09:28:16.400156 00800000 ################################################################
9868 09:28:16.400324
9869 09:28:16.692820 00880000 ################################################################
9870 09:28:16.692966
9871 09:28:16.950640 00900000 ################################################################
9872 09:28:16.950774
9873 09:28:17.247864 00980000 ################################################################
9874 09:28:17.248002
9875 09:28:17.549509 00a00000 ################################################################
9876 09:28:17.549644
9877 09:28:17.852445 00a80000 ################################################################
9878 09:28:17.852587
9879 09:28:18.145730 00b00000 ################################################################
9880 09:28:18.145873
9881 09:28:18.446210 00b80000 ################################################################
9882 09:28:18.446346
9883 09:28:18.742334 00c00000 ################################################################
9884 09:28:18.742470
9885 09:28:19.121840 00c80000 ################################################################
9886 09:28:19.122365
9887 09:28:19.510726 00d00000 ################################################################
9888 09:28:19.511265
9889 09:28:19.891366 00d80000 ################################################################
9890 09:28:19.891864
9891 09:28:20.273108 00e00000 ################################################################
9892 09:28:20.273691
9893 09:28:20.661411 00e80000 ################################################################
9894 09:28:20.661907
9895 09:28:21.043290 00f00000 ################################################################
9896 09:28:21.043439
9897 09:28:21.331939 00f80000 ################################################################
9898 09:28:21.332092
9899 09:28:21.632098 01000000 ################################################################
9900 09:28:21.632262
9901 09:28:21.935304 01080000 ################################################################
9902 09:28:21.935459
9903 09:28:22.237272 01100000 ################################################################
9904 09:28:22.237407
9905 09:28:22.517160 01180000 ################################################################
9906 09:28:22.517288
9907 09:28:22.783735 01200000 ################################################################
9908 09:28:22.783860
9909 09:28:23.037569 01280000 ################################################################
9910 09:28:23.037702
9911 09:28:23.326029 01300000 ################################################################
9912 09:28:23.326163
9913 09:28:23.608094 01380000 ################################################################
9914 09:28:23.608247
9915 09:28:23.902430 01400000 ################################################################
9916 09:28:23.902561
9917 09:28:24.167969 01480000 ################################################################
9918 09:28:24.168103
9919 09:28:24.439573 01500000 ################################################################
9920 09:28:24.439704
9921 09:28:24.736243 01580000 ################################################################
9922 09:28:24.736367
9923 09:28:25.034328 01600000 ################################################################
9924 09:28:25.034456
9925 09:28:25.329285 01680000 ################################################################
9926 09:28:25.329420
9927 09:28:25.611871 01700000 ################################################################
9928 09:28:25.612000
9929 09:28:25.873286 01780000 ################################################################
9930 09:28:25.873416
9931 09:28:26.170975 01800000 ################################################################
9932 09:28:26.171113
9933 09:28:26.467737 01880000 ################################################################
9934 09:28:26.467878
9935 09:28:26.766640 01900000 ################################################################
9936 09:28:26.766779
9937 09:28:27.064670 01980000 ################################################################
9938 09:28:27.064813
9939 09:28:27.367082 01a00000 ################################################################
9940 09:28:27.367357
9941 09:28:27.751376 01a80000 ################################################################
9942 09:28:27.751888
9943 09:28:28.146478 01b00000 ################################################################
9944 09:28:28.147027
9945 09:28:28.182306 01b80000 ###### done.
9946 09:28:28.182741
9947 09:28:28.186117 The bootfile was 28884274 bytes long.
9948 09:28:28.186693
9949 09:28:28.189242 Sending tftp read request... done.
9950 09:28:28.189669
9951 09:28:28.193281 Waiting for the transfer...
9952 09:28:28.193754
9953 09:28:28.194134 00000000 # done.
9954 09:28:28.194458
9955 09:28:28.199607 Command line loaded dynamically from TFTP file: 11826831/tftp-deploy-_m38mr1m/kernel/cmdline
9956 09:28:28.203033
9957 09:28:28.223020 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9958 09:28:28.223563
9959 09:28:28.223910 Loading FIT.
9960 09:28:28.226149
9961 09:28:28.226571 Image ramdisk-1 has 17790701 bytes.
9962 09:28:28.226915
9963 09:28:28.229377 Image fdt-1 has 47278 bytes.
9964 09:28:28.229802
9965 09:28:28.232724 Image kernel-1 has 11044258 bytes.
9966 09:28:28.233153
9967 09:28:28.242914 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
9968 09:28:28.243448
9969 09:28:28.259476 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9970 09:28:28.260038
9971 09:28:28.265706 Choosing best match conf-1 for compat google,spherion.
9972 09:28:28.266217
9973 09:28:28.273498 Connected to device vid:did:rid of 1ae0:0028:00
9974 09:28:28.280637
9975 09:28:28.283630 tpm_get_response: command 0x17b, return code 0x0
9976 09:28:28.284160
9977 09:28:28.287161 ec_init: CrosEC protocol v3 supported (256, 248)
9978 09:28:28.291250
9979 09:28:28.294469 tpm_cleanup: add release locality here.
9980 09:28:28.294995
9981 09:28:28.295338 Shutting down all USB controllers.
9982 09:28:28.297546
9983 09:28:28.297969 Removing current net device
9984 09:28:28.298309
9985 09:28:28.304344 Exiting depthcharge with code 4 at timestamp: 49900875
9986 09:28:28.304875
9987 09:28:28.307546 LZMA decompressing kernel-1 to 0x821a6718
9988 09:28:28.307970
9989 09:28:28.310817 LZMA decompressing kernel-1 to 0x40000000
9990 09:28:29.699924
9991 09:28:29.700539 jumping to kernel
9992 09:28:29.702240 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
9993 09:28:29.702960 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
9994 09:28:29.703444 Setting prompt string to ['Linux version [0-9]']
9995 09:28:29.703845 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9996 09:28:29.704291 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9997 09:28:29.750048
9998 09:28:29.753334 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9999 09:28:29.756887 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10000 09:28:29.757419 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10001 09:28:29.757821 Setting prompt string to []
10002 09:28:29.758250 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10003 09:28:29.758648 Using line separator: #'\n'#
10004 09:28:29.758988 No login prompt set.
10005 09:28:29.759342 Parsing kernel messages
10006 09:28:29.759656 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10007 09:28:29.760255 [login-action] Waiting for messages, (timeout 00:04:03)
10008 09:28:29.776309 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10009 09:28:29.780370 [ 0.000000] random: crng init done
10010 09:28:29.785912 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10011 09:28:29.789380 [ 0.000000] efi: UEFI not found.
10012 09:28:29.796015 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10013 09:28:29.802905 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10014 09:28:29.812372 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10015 09:28:29.822374 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10016 09:28:29.829042 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10017 09:28:29.835481 [ 0.000000] printk: bootconsole [mtk8250] enabled
10018 09:28:29.842081 [ 0.000000] NUMA: No NUMA configuration found
10019 09:28:29.849126 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10020 09:28:29.851856 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10021 09:28:29.855379 [ 0.000000] Zone ranges:
10022 09:28:29.861616 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10023 09:28:29.865402 [ 0.000000] DMA32 empty
10024 09:28:29.871716 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10025 09:28:29.875382 [ 0.000000] Movable zone start for each node
10026 09:28:29.878754 [ 0.000000] Early memory node ranges
10027 09:28:29.885512 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10028 09:28:29.891795 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10029 09:28:29.898174 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10030 09:28:29.905129 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10031 09:28:29.911352 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10032 09:28:29.918230 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10033 09:28:29.948714 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10034 09:28:29.954840 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10035 09:28:29.961412 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10036 09:28:29.965193 [ 0.000000] psci: probing for conduit method from DT.
10037 09:28:29.971607 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10038 09:28:29.975305 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10039 09:28:29.981178 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10040 09:28:29.985085 [ 0.000000] psci: SMC Calling Convention v1.2
10041 09:28:29.991671 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10042 09:28:29.995196 [ 0.000000] Detected VIPT I-cache on CPU0
10043 09:28:30.001690 [ 0.000000] CPU features: detected: GIC system register CPU interface
10044 09:28:30.008113 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10045 09:28:30.014695 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10046 09:28:30.020923 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10047 09:28:30.031010 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10048 09:28:30.037450 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10049 09:28:30.040777 [ 0.000000] alternatives: applying boot alternatives
10050 09:28:30.047717 [ 0.000000] Fallback order for Node 0: 0
10051 09:28:30.054237 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10052 09:28:30.057493 [ 0.000000] Policy zone: Normal
10053 09:28:30.080932 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10054 09:28:30.090226 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10055 09:28:30.100379 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10056 09:28:30.107016 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10057 09:28:30.113802 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10058 09:28:30.120446 <6>[ 0.000000] software IO TLB: area num 8.
10059 09:28:30.175214 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10060 09:28:30.255514 <6>[ 0.000000] Memory: 3837708K/4191232K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 320756K reserved, 32768K cma-reserved)
10061 09:28:30.261967 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10062 09:28:30.268578 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10063 09:28:30.271919 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10064 09:28:30.278890 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10065 09:28:30.285429 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10066 09:28:30.288892 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10067 09:28:30.298744 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10068 09:28:30.305398 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10069 09:28:30.311482 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10070 09:28:30.318224 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10071 09:28:30.321745 <6>[ 0.000000] GICv3: 608 SPIs implemented
10072 09:28:30.324868 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10073 09:28:30.331388 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10074 09:28:30.334542 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10075 09:28:30.341482 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10076 09:28:30.354523 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10077 09:28:30.367845 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10078 09:28:30.374621 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10079 09:28:30.381971 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10080 09:28:30.395205 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10081 09:28:30.401756 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10082 09:28:30.408738 <6>[ 0.009176] Console: colour dummy device 80x25
10083 09:28:30.418599 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10084 09:28:30.425036 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10085 09:28:30.428819 <6>[ 0.029213] LSM: Security Framework initializing
10086 09:28:30.435143 <6>[ 0.034155] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10087 09:28:30.444914 <6>[ 0.041811] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10088 09:28:30.451783 <6>[ 0.051029] cblist_init_generic: Setting adjustable number of callback queues.
10089 09:28:30.457877 <6>[ 0.058473] cblist_init_generic: Setting shift to 3 and lim to 1.
10090 09:28:30.468147 <6>[ 0.064850] cblist_init_generic: Setting adjustable number of callback queues.
10091 09:28:30.471435 <6>[ 0.072277] cblist_init_generic: Setting shift to 3 and lim to 1.
10092 09:28:30.478283 <6>[ 0.078714] rcu: Hierarchical SRCU implementation.
10093 09:28:30.485137 <6>[ 0.083761] rcu: Max phase no-delay instances is 1000.
10094 09:28:30.491483 <6>[ 0.090784] EFI services will not be available.
10095 09:28:30.494907 <6>[ 0.095768] smp: Bringing up secondary CPUs ...
10096 09:28:30.502178 <6>[ 0.100817] Detected VIPT I-cache on CPU1
10097 09:28:30.508796 <6>[ 0.100885] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10098 09:28:30.515587 <6>[ 0.100915] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10099 09:28:30.518910 <6>[ 0.101237] Detected VIPT I-cache on CPU2
10100 09:28:30.525360 <6>[ 0.101285] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10101 09:28:30.535395 <6>[ 0.101300] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10102 09:28:30.538751 <6>[ 0.101551] Detected VIPT I-cache on CPU3
10103 09:28:30.545333 <6>[ 0.101598] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10104 09:28:30.551845 <6>[ 0.101612] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10105 09:28:30.554821 <6>[ 0.101913] CPU features: detected: Spectre-v4
10106 09:28:30.562036 <6>[ 0.101919] CPU features: detected: Spectre-BHB
10107 09:28:30.565500 <6>[ 0.101924] Detected PIPT I-cache on CPU4
10108 09:28:30.571788 <6>[ 0.101981] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10109 09:28:30.578570 <6>[ 0.101998] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10110 09:28:30.585056 <6>[ 0.102289] Detected PIPT I-cache on CPU5
10111 09:28:30.592136 <6>[ 0.102350] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10112 09:28:30.598415 <6>[ 0.102367] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10113 09:28:30.601359 <6>[ 0.102643] Detected PIPT I-cache on CPU6
10114 09:28:30.608429 <6>[ 0.102704] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10115 09:28:30.614857 <6>[ 0.102720] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10116 09:28:30.621589 <6>[ 0.103016] Detected PIPT I-cache on CPU7
10117 09:28:30.628066 <6>[ 0.103080] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10118 09:28:30.635059 <6>[ 0.103096] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10119 09:28:30.637691 <6>[ 0.103143] smp: Brought up 1 node, 8 CPUs
10120 09:28:30.644501 <6>[ 0.244399] SMP: Total of 8 processors activated.
10121 09:28:30.647977 <6>[ 0.249350] CPU features: detected: 32-bit EL0 Support
10122 09:28:30.658008 <6>[ 0.254712] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10123 09:28:30.664137 <6>[ 0.263512] CPU features: detected: Common not Private translations
10124 09:28:30.671044 <6>[ 0.269988] CPU features: detected: CRC32 instructions
10125 09:28:30.674594 <6>[ 0.275339] CPU features: detected: RCpc load-acquire (LDAPR)
10126 09:28:30.680921 <6>[ 0.281299] CPU features: detected: LSE atomic instructions
10127 09:28:30.687635 <6>[ 0.287117] CPU features: detected: Privileged Access Never
10128 09:28:30.693957 <6>[ 0.292932] CPU features: detected: RAS Extension Support
10129 09:28:30.700771 <6>[ 0.298576] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10130 09:28:30.704594 <6>[ 0.305838] CPU: All CPU(s) started at EL2
10131 09:28:30.710396 <6>[ 0.310156] alternatives: applying system-wide alternatives
10132 09:28:30.719227 <6>[ 0.320066] devtmpfs: initialized
10133 09:28:30.734094 <6>[ 0.328456] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10134 09:28:30.740724 <6>[ 0.338408] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10135 09:28:30.747337 <6>[ 0.346561] pinctrl core: initialized pinctrl subsystem
10136 09:28:30.750857 <6>[ 0.353213] DMI not present or invalid.
10137 09:28:30.757315 <6>[ 0.357612] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10138 09:28:30.767375 <6>[ 0.364475] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10139 09:28:30.774079 <6>[ 0.371913] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10140 09:28:30.783679 <6>[ 0.380003] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10141 09:28:30.786983 <6>[ 0.388159] audit: initializing netlink subsys (disabled)
10142 09:28:30.797143 <5>[ 0.393854] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10143 09:28:30.803634 <6>[ 0.394550] thermal_sys: Registered thermal governor 'step_wise'
10144 09:28:30.810126 <6>[ 0.401817] thermal_sys: Registered thermal governor 'power_allocator'
10145 09:28:30.813967 <6>[ 0.408071] cpuidle: using governor menu
10146 09:28:30.820288 <6>[ 0.419034] NET: Registered PF_QIPCRTR protocol family
10147 09:28:30.826673 <6>[ 0.424523] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10148 09:28:30.829844 <6>[ 0.431621] ASID allocator initialised with 32768 entries
10149 09:28:30.837395 <6>[ 0.438163] Serial: AMBA PL011 UART driver
10150 09:28:30.846111 <4>[ 0.446905] Trying to register duplicate clock ID: 134
10151 09:28:30.900867 <6>[ 0.504863] KASLR enabled
10152 09:28:30.914918 <6>[ 0.512560] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10153 09:28:30.921638 <6>[ 0.519577] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10154 09:28:30.928280 <6>[ 0.526066] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10155 09:28:30.935014 <6>[ 0.533071] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10156 09:28:30.941330 <6>[ 0.539559] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10157 09:28:30.947854 <6>[ 0.546561] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10158 09:28:30.954995 <6>[ 0.553048] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10159 09:28:30.961046 <6>[ 0.560054] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10160 09:28:30.964577 <6>[ 0.567560] ACPI: Interpreter disabled.
10161 09:28:30.973083 <6>[ 0.573921] iommu: Default domain type: Translated
10162 09:28:30.979546 <6>[ 0.579029] iommu: DMA domain TLB invalidation policy: strict mode
10163 09:28:30.982903 <5>[ 0.585688] SCSI subsystem initialized
10164 09:28:30.989883 <6>[ 0.589834] usbcore: registered new interface driver usbfs
10165 09:28:30.996125 <6>[ 0.595569] usbcore: registered new interface driver hub
10166 09:28:30.999415 <6>[ 0.601122] usbcore: registered new device driver usb
10167 09:28:31.006658 <6>[ 0.607208] pps_core: LinuxPPS API ver. 1 registered
10168 09:28:31.016699 <6>[ 0.612400] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10169 09:28:31.019833 <6>[ 0.621742] PTP clock support registered
10170 09:28:31.022659 <6>[ 0.625987] EDAC MC: Ver: 3.0.0
10171 09:28:31.030149 <6>[ 0.631145] FPGA manager framework
10172 09:28:31.036880 <6>[ 0.634825] Advanced Linux Sound Architecture Driver Initialized.
10173 09:28:31.039974 <6>[ 0.641596] vgaarb: loaded
10174 09:28:31.046654 <6>[ 0.644759] clocksource: Switched to clocksource arch_sys_counter
10175 09:28:31.049989 <5>[ 0.651197] VFS: Disk quotas dquot_6.6.0
10176 09:28:31.057022 <6>[ 0.655384] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10177 09:28:31.059793 <6>[ 0.662569] pnp: PnP ACPI: disabled
10178 09:28:31.068673 <6>[ 0.669294] NET: Registered PF_INET protocol family
10179 09:28:31.075205 <6>[ 0.674677] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10180 09:28:31.087392 <6>[ 0.684668] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10181 09:28:31.097161 <6>[ 0.693453] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10182 09:28:31.103916 <6>[ 0.701417] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10183 09:28:31.110309 <6>[ 0.709824] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10184 09:28:31.121148 <6>[ 0.718480] TCP: Hash tables configured (established 32768 bind 32768)
10185 09:28:31.127897 <6>[ 0.725332] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10186 09:28:31.134151 <6>[ 0.732351] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10187 09:28:31.140914 <6>[ 0.739866] NET: Registered PF_UNIX/PF_LOCAL protocol family
10188 09:28:31.147330 <6>[ 0.745988] RPC: Registered named UNIX socket transport module.
10189 09:28:31.150937 <6>[ 0.752139] RPC: Registered udp transport module.
10190 09:28:31.157455 <6>[ 0.757073] RPC: Registered tcp transport module.
10191 09:28:31.163913 <6>[ 0.762002] RPC: Registered tcp NFSv4.1 backchannel transport module.
10192 09:28:31.167524 <6>[ 0.768667] PCI: CLS 0 bytes, default 64
10193 09:28:31.170640 <6>[ 0.773026] Unpacking initramfs...
10194 09:28:31.180300 <6>[ 0.777138] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10195 09:28:31.187053 <6>[ 0.785762] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10196 09:28:31.193867 <6>[ 0.794553] kvm [1]: IPA Size Limit: 40 bits
10197 09:28:31.196812 <6>[ 0.799081] kvm [1]: GICv3: no GICV resource entry
10198 09:28:31.203753 <6>[ 0.804104] kvm [1]: disabling GICv2 emulation
10199 09:28:31.209916 <6>[ 0.808790] kvm [1]: GIC system register CPU interface enabled
10200 09:28:31.213648 <6>[ 0.814947] kvm [1]: vgic interrupt IRQ18
10201 09:28:31.220148 <6>[ 0.819311] kvm [1]: VHE mode initialized successfully
10202 09:28:31.223532 <5>[ 0.825737] Initialise system trusted keyrings
10203 09:28:31.230159 <6>[ 0.830535] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10204 09:28:31.239718 <6>[ 0.840489] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10205 09:28:31.246659 <5>[ 0.846856] NFS: Registering the id_resolver key type
10206 09:28:31.249426 <5>[ 0.852162] Key type id_resolver registered
10207 09:28:31.256355 <5>[ 0.856574] Key type id_legacy registered
10208 09:28:31.263065 <6>[ 0.860865] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10209 09:28:31.269200 <6>[ 0.867784] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10210 09:28:31.275851 <6>[ 0.875510] 9p: Installing v9fs 9p2000 file system support
10211 09:28:31.312844 <5>[ 0.913089] Key type asymmetric registered
10212 09:28:31.315431 <5>[ 0.917419] Asymmetric key parser 'x509' registered
10213 09:28:31.325646 <6>[ 0.922563] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10214 09:28:31.328607 <6>[ 0.930172] io scheduler mq-deadline registered
10215 09:28:31.332267 <6>[ 0.934935] io scheduler kyber registered
10216 09:28:31.351569 <6>[ 0.952037] EINJ: ACPI disabled.
10217 09:28:31.383716 <4>[ 0.977775] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10218 09:28:31.393777 <4>[ 0.988402] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10219 09:28:31.408352 <6>[ 1.009051] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10220 09:28:31.415876 <6>[ 1.017005] printk: console [ttyS0] disabled
10221 09:28:31.444165 <6>[ 1.041652] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10222 09:28:31.450542 <6>[ 1.051131] printk: console [ttyS0] enabled
10223 09:28:31.454347 <6>[ 1.051131] printk: console [ttyS0] enabled
10224 09:28:31.460834 <6>[ 1.060030] printk: bootconsole [mtk8250] disabled
10225 09:28:31.464009 <6>[ 1.060030] printk: bootconsole [mtk8250] disabled
10226 09:28:31.470853 <6>[ 1.071060] SuperH (H)SCI(F) driver initialized
10227 09:28:31.473886 <6>[ 1.076311] msm_serial: driver initialized
10228 09:28:31.488219 <6>[ 1.085238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10229 09:28:31.497733 <6>[ 1.093791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10230 09:28:31.504599 <6>[ 1.102334] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10231 09:28:31.514333 <6>[ 1.110963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10232 09:28:31.524390 <6>[ 1.119675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10233 09:28:31.531065 <6>[ 1.128395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10234 09:28:31.540892 <6>[ 1.136937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10235 09:28:31.547021 <6>[ 1.145727] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10236 09:28:31.557119 <6>[ 1.154271] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10237 09:28:31.569275 <6>[ 1.169814] loop: module loaded
10238 09:28:31.575706 <6>[ 1.175686] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10239 09:28:31.597952 <4>[ 1.198960] mtk-pmic-keys: Failed to locate of_node [id: -1]
10240 09:28:31.604890 <6>[ 1.205848] megasas: 07.719.03.00-rc1
10241 09:28:31.614657 <6>[ 1.215355] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10242 09:28:31.623205 <6>[ 1.224145] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10243 09:28:31.639315 <6>[ 1.240052] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10244 09:28:31.695073 <6>[ 1.289171] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10245 09:28:31.906794 <6>[ 1.507618] Freeing initrd memory: 17368K
10246 09:28:31.916705 <6>[ 1.517817] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10247 09:28:31.927739 <6>[ 1.528632] tun: Universal TUN/TAP device driver, 1.6
10248 09:28:31.931038 <6>[ 1.534697] thunder_xcv, ver 1.0
10249 09:28:31.934186 <6>[ 1.538202] thunder_bgx, ver 1.0
10250 09:28:31.937669 <6>[ 1.541696] nicpf, ver 1.0
10251 09:28:31.947760 <6>[ 1.545705] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10252 09:28:31.951146 <6>[ 1.553182] hns3: Copyright (c) 2017 Huawei Corporation.
10253 09:28:31.954475 <6>[ 1.558768] hclge is initializing
10254 09:28:31.961595 <6>[ 1.562348] e1000: Intel(R) PRO/1000 Network Driver
10255 09:28:31.967934 <6>[ 1.567476] e1000: Copyright (c) 1999-2006 Intel Corporation.
10256 09:28:31.971423 <6>[ 1.573489] e1000e: Intel(R) PRO/1000 Network Driver
10257 09:28:31.978003 <6>[ 1.578705] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10258 09:28:31.984670 <6>[ 1.584891] igb: Intel(R) Gigabit Ethernet Network Driver
10259 09:28:31.991473 <6>[ 1.590542] igb: Copyright (c) 2007-2014 Intel Corporation.
10260 09:28:31.998173 <6>[ 1.596378] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10261 09:28:32.004897 <6>[ 1.602896] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10262 09:28:32.008143 <6>[ 1.609357] sky2: driver version 1.30
10263 09:28:32.014388 <6>[ 1.614343] VFIO - User Level meta-driver version: 0.3
10264 09:28:32.021442 <6>[ 1.622592] usbcore: registered new interface driver usb-storage
10265 09:28:32.028754 <6>[ 1.629031] usbcore: registered new device driver onboard-usb-hub
10266 09:28:32.037267 <6>[ 1.638162] mt6397-rtc mt6359-rtc: registered as rtc0
10267 09:28:32.047192 <6>[ 1.643629] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:28:32 UTC (1697794112)
10268 09:28:32.050623 <6>[ 1.653198] i2c_dev: i2c /dev entries driver
10269 09:28:32.067389 <6>[ 1.664844] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10270 09:28:32.087008 <6>[ 1.687809] cpu cpu0: EM: created perf domain
10271 09:28:32.090002 <6>[ 1.692706] cpu cpu4: EM: created perf domain
10272 09:28:32.097113 <6>[ 1.698185] sdhci: Secure Digital Host Controller Interface driver
10273 09:28:32.104351 <6>[ 1.704617] sdhci: Copyright(c) Pierre Ossman
10274 09:28:32.110800 <6>[ 1.709526] Synopsys Designware Multimedia Card Interface Driver
10275 09:28:32.117149 <6>[ 1.716113] sdhci-pltfm: SDHCI platform and OF driver helper
10276 09:28:32.120729 <6>[ 1.716159] mmc0: CQHCI version 5.10
10277 09:28:32.127431 <6>[ 1.726449] ledtrig-cpu: registered to indicate activity on CPUs
10278 09:28:32.133643 <6>[ 1.733413] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10279 09:28:32.140626 <6>[ 1.740436] usbcore: registered new interface driver usbhid
10280 09:28:32.144088 <6>[ 1.746259] usbhid: USB HID core driver
10281 09:28:32.150342 <6>[ 1.750450] spi_master spi0: will run message pump with realtime priority
10282 09:28:32.193963 <6>[ 1.788322] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10283 09:28:32.213265 <6>[ 1.803930] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10284 09:28:32.216268 <6>[ 1.817580] mmc0: Command Queue Engine enabled
10285 09:28:32.223244 <6>[ 1.822412] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10286 09:28:32.230280 <6>[ 1.829304] cros-ec-spi spi0.0: Chrome EC device registered
10287 09:28:32.233280 <6>[ 1.829693] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10288 09:28:32.244149 <6>[ 1.845098] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10289 09:28:32.251887 <6>[ 1.852952] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10290 09:28:32.258724 <6>[ 1.858857] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10291 09:28:32.265009 <6>[ 1.865136] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10292 09:28:32.280638 <6>[ 1.878023] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10293 09:28:32.288002 <6>[ 1.888879] NET: Registered PF_PACKET protocol family
10294 09:28:32.291069 <6>[ 1.894277] 9pnet: Installing 9P2000 support
10295 09:28:32.297869 <5>[ 1.898837] Key type dns_resolver registered
10296 09:28:32.301702 <6>[ 1.903883] registered taskstats version 1
10297 09:28:32.307908 <5>[ 1.908269] Loading compiled-in X.509 certificates
10298 09:28:32.338337 <4>[ 1.932436] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10299 09:28:32.348015 <4>[ 1.943207] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10300 09:28:32.354694 <3>[ 1.953798] debugfs: File 'uA_load' in directory '/' already present!
10301 09:28:32.361388 <3>[ 1.960505] debugfs: File 'min_uV' in directory '/' already present!
10302 09:28:32.368050 <3>[ 1.967113] debugfs: File 'max_uV' in directory '/' already present!
10303 09:28:32.375055 <3>[ 1.973720] debugfs: File 'constraint_flags' in directory '/' already present!
10304 09:28:32.386342 <3>[ 1.983523] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10305 09:28:32.394406 <6>[ 1.995473] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10306 09:28:32.401318 <6>[ 2.002320] xhci-mtk 11200000.usb: xHCI Host Controller
10307 09:28:32.408268 <6>[ 2.007829] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10308 09:28:32.418062 <6>[ 2.015689] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10309 09:28:32.424978 <6>[ 2.025111] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10310 09:28:32.431440 <6>[ 2.031147] xhci-mtk 11200000.usb: xHCI Host Controller
10311 09:28:32.438296 <6>[ 2.036622] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10312 09:28:32.445139 <6>[ 2.044267] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10313 09:28:32.451325 <6>[ 2.051975] hub 1-0:1.0: USB hub found
10314 09:28:32.454534 <6>[ 2.055986] hub 1-0:1.0: 1 port detected
10315 09:28:32.461682 <6>[ 2.060252] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10316 09:28:32.467985 <6>[ 2.068795] hub 2-0:1.0: USB hub found
10317 09:28:32.471328 <6>[ 2.072800] hub 2-0:1.0: 1 port detected
10318 09:28:32.480655 <6>[ 2.081581] mtk-msdc 11f70000.mmc: Got CD GPIO
10319 09:28:32.490933 <6>[ 2.087157] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10320 09:28:32.497036 <6>[ 2.095192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10321 09:28:32.507409 <4>[ 2.103086] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10322 09:28:32.513933 <6>[ 2.112608] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10323 09:28:32.523561 <6>[ 2.120684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10324 09:28:32.530387 <6>[ 2.128698] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10325 09:28:32.536888 <6>[ 2.136617] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10326 09:28:32.547276 <6>[ 2.144433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10327 09:28:32.556588 <6>[ 2.152250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10328 09:28:32.563893 <6>[ 2.162540] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10329 09:28:32.573265 <6>[ 2.170904] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10330 09:28:32.580376 <6>[ 2.179248] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10331 09:28:32.590487 <6>[ 2.187586] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10332 09:28:32.600058 <6>[ 2.195925] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10333 09:28:32.606939 <6>[ 2.204262] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10334 09:28:32.613756 <6>[ 2.212600] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10335 09:28:32.623376 <6>[ 2.220938] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10336 09:28:32.629743 <6>[ 2.229288] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10337 09:28:32.640432 <6>[ 2.237626] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10338 09:28:32.646769 <6>[ 2.245964] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10339 09:28:32.656593 <6>[ 2.254311] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10340 09:28:32.663331 <6>[ 2.262648] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10341 09:28:32.673655 <6>[ 2.270985] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10342 09:28:32.680011 <6>[ 2.279323] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10343 09:28:32.687389 <6>[ 2.288093] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10344 09:28:32.694580 <6>[ 2.295311] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10345 09:28:32.701430 <6>[ 2.302175] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10346 09:28:32.711369 <6>[ 2.308965] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10347 09:28:32.717549 <6>[ 2.315880] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10348 09:28:32.724244 <6>[ 2.322743] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10349 09:28:32.734889 <6>[ 2.331874] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10350 09:28:32.744552 <6>[ 2.340994] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10351 09:28:32.754318 <6>[ 2.350287] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10352 09:28:32.763986 <6>[ 2.359755] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10353 09:28:32.770930 <6>[ 2.369222] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10354 09:28:32.780711 <6>[ 2.378342] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10355 09:28:32.790750 <6>[ 2.387807] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10356 09:28:32.800872 <6>[ 2.396927] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10357 09:28:32.810848 <6>[ 2.406221] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10358 09:28:32.820387 <6>[ 2.416380] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10359 09:28:32.830549 <6>[ 2.428051] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10360 09:28:32.836883 <6>[ 2.437632] Trying to probe devices needed for running init ...
10361 09:28:32.883309 <6>[ 2.481026] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10362 09:28:33.038195 <6>[ 2.638780] hub 1-1:1.0: USB hub found
10363 09:28:33.041137 <6>[ 2.643294] hub 1-1:1.0: 4 ports detected
10364 09:28:33.163528 <6>[ 2.761375] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10365 09:28:33.190187 <6>[ 2.791291] hub 2-1:1.0: USB hub found
10366 09:28:33.193372 <6>[ 2.795809] hub 2-1:1.0: 3 ports detected
10367 09:28:33.362891 <6>[ 2.961039] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10368 09:28:33.496317 <6>[ 3.097047] hub 1-1.4:1.0: USB hub found
10369 09:28:33.499031 <6>[ 3.101792] hub 1-1.4:1.0: 2 ports detected
10370 09:28:33.575379 <6>[ 3.173304] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10371 09:28:33.795291 <6>[ 3.393088] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10372 09:28:33.987168 <6>[ 3.585081] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10373 09:28:45.128389 <6>[ 14.734153] ALSA device list:
10374 09:28:45.134873 <6>[ 14.737449] No soundcards found.
10375 09:28:45.142989 <6>[ 14.745351] Freeing unused kernel memory: 8384K
10376 09:28:45.146137 <6>[ 14.750351] Run /init as init process
10377 09:28:45.157580 Loading, please wait...
10378 09:28:45.177925 Starting version 247.3-7+deb11u2
10379 09:28:45.374058 <6>[ 14.973659] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10380 09:28:45.386159 <6>[ 14.985447] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10381 09:28:45.392967 <6>[ 14.989853] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10382 09:28:45.403043 <6>[ 14.994385] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10383 09:28:45.413155 <3>[ 15.011561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10384 09:28:45.419550 <3>[ 15.019719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10385 09:28:45.426200 <6>[ 15.020842] remoteproc remoteproc0: scp is available
10386 09:28:45.432643 <3>[ 15.027808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10387 09:28:45.439154 <6>[ 15.033058] remoteproc remoteproc0: powering up scp
10388 09:28:45.445838 <3>[ 15.043740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10389 09:28:45.456116 <6>[ 15.044381] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10390 09:28:45.462873 <6>[ 15.046284] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10391 09:28:45.472590 <3>[ 15.054528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10392 09:28:45.476450 <6>[ 15.057452] mc: Linux media interface: v0.10
10393 09:28:45.482696 <6>[ 15.062034] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10394 09:28:45.489824 <3>[ 15.070438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10395 09:28:45.496668 <4>[ 15.070784] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10396 09:28:45.503354 <4>[ 15.070784] Fallback method does not support PEC.
10397 09:28:45.509673 <6>[ 15.071786] videodev: Linux video capture interface: v2.00
10398 09:28:45.516302 <4>[ 15.074102] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10399 09:28:45.522765 <4>[ 15.074253] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10400 09:28:45.530358 <6>[ 15.075934] usbcore: registered new interface driver r8152
10401 09:28:45.536944 <3>[ 15.097148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10402 09:28:45.547148 <3>[ 15.110536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10403 09:28:45.553414 <3>[ 15.137811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10404 09:28:45.563748 <3>[ 15.145546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10405 09:28:45.569883 <6>[ 15.158785] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10406 09:28:45.576568 <3>[ 15.162370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10407 09:28:45.583287 <6>[ 15.170427] pci_bus 0000:00: root bus resource [bus 00-ff]
10408 09:28:45.593319 <3>[ 15.177316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10409 09:28:45.599931 <6>[ 15.181179] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10410 09:28:45.606484 <6>[ 15.185361] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10411 09:28:45.613186 <3>[ 15.191092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10412 09:28:45.622708 <6>[ 15.193346] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10413 09:28:45.632716 <6>[ 15.197701] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10414 09:28:45.642714 <6>[ 15.198219] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10415 09:28:45.652824 <4>[ 15.204159] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10416 09:28:45.659282 <6>[ 15.204234] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10417 09:28:45.665553 <6>[ 15.206319] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10418 09:28:45.675560 <3>[ 15.207640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10419 09:28:45.682445 <3>[ 15.207701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10420 09:28:45.692628 <3>[ 15.207709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10421 09:28:45.698989 <3>[ 15.207718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10422 09:28:45.708632 <3>[ 15.207727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10423 09:28:45.715620 <3>[ 15.207736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10424 09:28:45.721814 <3>[ 15.207772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10425 09:28:45.731858 <6>[ 15.208120] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10426 09:28:45.738595 <6>[ 15.208154] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10427 09:28:45.748649 <6>[ 15.208167] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10428 09:28:45.751606 <6>[ 15.208227] pci 0000:00:00.0: supports D1 D2
10429 09:28:45.758237 <6>[ 15.208229] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10430 09:28:45.768170 <6>[ 15.209085] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10431 09:28:45.771243 <6>[ 15.209168] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10432 09:28:45.781131 <6>[ 15.209193] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10433 09:28:45.787976 <6>[ 15.209208] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10434 09:28:45.794915 <6>[ 15.209223] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10435 09:28:45.801101 <6>[ 15.209326] pci 0000:01:00.0: supports D1 D2
10436 09:28:45.807964 <6>[ 15.209327] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10437 09:28:45.814289 <4>[ 15.213436] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10438 09:28:45.821033 <6>[ 15.220884] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10439 09:28:45.830948 <6>[ 15.220965] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10440 09:28:45.837403 <6>[ 15.220974] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10441 09:28:45.847579 <6>[ 15.220989] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10442 09:28:45.854089 <6>[ 15.221026] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10443 09:28:45.860689 <6>[ 15.221045] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10444 09:28:45.867258 <6>[ 15.221062] pci 0000:00:00.0: PCI bridge to [bus 01]
10445 09:28:45.873686 <6>[ 15.221072] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10446 09:28:45.880628 <6>[ 15.221273] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10447 09:28:45.886766 <6>[ 15.221551] remoteproc remoteproc0: remote processor scp is now up
10448 09:28:45.893475 <6>[ 15.223651] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10449 09:28:45.900231 <6>[ 15.224404] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10450 09:28:45.906963 <6>[ 15.224447] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10451 09:28:45.916803 <6>[ 15.226823] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10452 09:28:45.920043 <6>[ 15.232203] Bluetooth: Core ver 2.22
10453 09:28:45.926404 <6>[ 15.232476] usbcore: registered new interface driver cdc_ether
10454 09:28:45.933255 <6>[ 15.251113] usbcore: registered new interface driver r8153_ecm
10455 09:28:45.939773 <5>[ 15.252811] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10456 09:28:45.946254 <6>[ 15.259124] NET: Registered PF_BLUETOOTH protocol family
10457 09:28:45.952738 <6>[ 15.260644] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10458 09:28:45.965899 <6>[ 15.261964] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10459 09:28:45.972886 <6>[ 15.262098] usbcore: registered new interface driver uvcvideo
10460 09:28:45.979265 <5>[ 15.264510] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10461 09:28:45.985960 <4>[ 15.264563] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10462 09:28:45.992832 <6>[ 15.264568] cfg80211: failed to load regulatory.db
10463 09:28:45.995947 <6>[ 15.306950] r8152 2-1.3:1.0 eth0: v1.12.13
10464 09:28:46.002529 <6>[ 15.307373] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10465 09:28:46.008783 <6>[ 15.314960] Bluetooth: HCI device and connection manager initialized
10466 09:28:46.015741 <6>[ 15.314974] Bluetooth: HCI socket layer initialized
10467 09:28:46.019539 <6>[ 15.329560] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10468 09:28:46.025620 <6>[ 15.331115] Bluetooth: L2CAP socket layer initialized
10469 09:28:46.031892 <6>[ 15.331122] Bluetooth: SCO socket layer initialized
10470 09:28:46.038820 <6>[ 15.381366] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10471 09:28:46.045294 <6>[ 15.453884] usbcore: registered new interface driver btusb
10472 09:28:46.055431 <4>[ 15.455032] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10473 09:28:46.062048 <3>[ 15.455050] Bluetooth: hci0: Failed to load firmware file (-2)
10474 09:28:46.065233 <3>[ 15.455056] Bluetooth: hci0: Failed to set up firmware (-2)
10475 09:28:46.078281 <4>[ 15.455063] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10476 09:28:46.081750 <6>[ 15.461501] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10477 09:28:46.106225 <6>[ 15.708981] mt7921e 0000:01:00.0: ASIC revision: 79610010
10478 09:28:46.212327 <4>[ 15.808304] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10479 09:28:46.231643 Begin: Loading essential drivers ... done.
10480 09:28:46.234950 Begin: Running /scripts/init-premount ... done.
10481 09:28:46.241355 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10482 09:28:46.251499 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10483 09:28:46.254244 Device /sys/class/net/enx00e04c6803bd found
10484 09:28:46.254705 done.
10485 09:28:46.330982 <4>[ 15.927035] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10486 09:28:46.346400 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10487 09:28:46.449438 <4>[ 16.045837] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10488 09:28:46.565664 <4>[ 16.161755] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10489 09:28:46.681647 <4>[ 16.277587] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10490 09:28:46.797135 <4>[ 16.393565] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10491 09:28:46.914058 <4>[ 16.509738] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10492 09:28:47.029283 <4>[ 16.625628] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10493 09:28:47.145573 <4>[ 16.741552] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10494 09:28:47.261325 <4>[ 16.857548] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10495 09:28:47.286887 <6>[ 16.889393] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10496 09:28:47.368969 <3>[ 16.971517] mt7921e 0000:01:00.0: hardware init failed
10497 09:28:47.540808 IP-Config: no response after 2 secs - giving up
10498 09:28:47.581524 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10499 09:28:47.585017 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10500 09:28:47.591440 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10501 09:28:47.601347 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10502 09:28:47.608054 host : mt8192-asurada-spherion-r0-cbg-4
10503 09:28:47.614331 domain : lava-rack
10504 09:28:47.617515 rootserver: 192.168.201.1 rootpath:
10505 09:28:47.617977 filename :
10506 09:28:47.692255 done.
10507 09:28:47.699174 Begin: Running /scripts/nfs-bottom ... done.
10508 09:28:47.719601 Begin: Running /scripts/init-bottom ... done.
10509 09:28:48.944361 <6>[ 18.547177] NET: Registered PF_INET6 protocol family
10510 09:28:48.951951 <6>[ 18.554702] Segment Routing with IPv6
10511 09:28:48.955065 <6>[ 18.558731] In-situ OAM (IOAM) with IPv6
10512 09:28:49.086085 <30>[ 18.668738] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10513 09:28:49.092037 <30>[ 18.693355] systemd[1]: Detected architecture arm64.
10514 09:28:49.111905
10515 09:28:49.115039 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10516 09:28:49.115605
10517 09:28:49.132917 <30>[ 18.736018] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10518 09:28:50.062457 <30>[ 19.662293] systemd[1]: Queued start job for default target Graphical Interface.
10519 09:28:50.104767 <30>[ 19.707847] systemd[1]: Created slice system-getty.slice.
10520 09:28:50.111308 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10521 09:28:50.127651 <30>[ 19.730687] systemd[1]: Created slice system-modprobe.slice.
10522 09:28:50.134031 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10523 09:28:50.151289 <30>[ 19.754476] systemd[1]: Created slice system-serial\x2dgetty.slice.
10524 09:28:50.161172 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10525 09:28:50.175408 <30>[ 19.778317] systemd[1]: Created slice User and Session Slice.
10526 09:28:50.181891 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10527 09:28:50.201671 <30>[ 19.801377] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10528 09:28:50.211310 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10529 09:28:50.229552 <30>[ 19.829304] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10530 09:28:50.236302 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10531 09:28:50.256509 <30>[ 19.853199] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10532 09:28:50.263617 <30>[ 19.865371] systemd[1]: Reached target Local Encrypted Volumes.
10533 09:28:50.269729 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10534 09:28:50.286517 <30>[ 19.889602] systemd[1]: Reached target Paths.
10535 09:28:50.293105 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10536 09:28:50.306176 <30>[ 19.909078] systemd[1]: Reached target Remote File Systems.
10537 09:28:50.312515 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10538 09:28:50.330257 <30>[ 19.933435] systemd[1]: Reached target Slices.
10539 09:28:50.336883 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10540 09:28:50.349998 <30>[ 19.953110] systemd[1]: Reached target Swap.
10541 09:28:50.353284 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10542 09:28:50.373764 <30>[ 19.973616] systemd[1]: Listening on initctl Compatibility Named Pipe.
10543 09:28:50.380437 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10544 09:28:50.387177 <30>[ 19.989964] systemd[1]: Listening on Journal Audit Socket.
10545 09:28:50.393578 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10546 09:28:50.411725 <30>[ 20.014660] systemd[1]: Listening on Journal Socket (/dev/log).
10547 09:28:50.418267 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10548 09:28:50.434566 <30>[ 20.037697] systemd[1]: Listening on Journal Socket.
10549 09:28:50.441093 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10550 09:28:50.459063 <30>[ 20.058823] systemd[1]: Listening on Network Service Netlink Socket.
10551 09:28:50.465593 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10552 09:28:50.481151 <30>[ 20.084240] systemd[1]: Listening on udev Control Socket.
10553 09:28:50.487751 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10554 09:28:50.502538 <30>[ 20.105582] systemd[1]: Listening on udev Kernel Socket.
10555 09:28:50.509130 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10556 09:28:50.550084 <30>[ 20.153193] systemd[1]: Mounting Huge Pages File System...
10557 09:28:50.556755 Mounting [0;1;39mHuge Pages File System[0m...
10558 09:28:50.574029 <30>[ 20.177371] systemd[1]: Mounting POSIX Message Queue File System...
10559 09:28:50.580917 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10560 09:28:50.602932 <30>[ 20.206129] systemd[1]: Mounting Kernel Debug File System...
10561 09:28:50.609127 Mounting [0;1;39mKernel Debug File System[0m...
10562 09:28:50.625344 <30>[ 20.225577] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10563 09:28:50.641216 <30>[ 20.241052] systemd[1]: Starting Create list of static device nodes for the current kernel...
10564 09:28:50.647590 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10565 09:28:50.670164 <30>[ 20.273638] systemd[1]: Starting Load Kernel Module configfs...
10566 09:28:50.677115 Starting [0;1;39mLoad Kernel Module configfs[0m...
10567 09:28:50.698732 <30>[ 20.301984] systemd[1]: Starting Load Kernel Module drm...
10568 09:28:50.705225 Starting [0;1;39mLoad Kernel Module drm[0m...
10569 09:28:50.727276 <30>[ 20.330370] systemd[1]: Starting Load Kernel Module fuse...
10570 09:28:50.733865 Starting [0;1;39mLoad Kernel Module fuse[0m...
10571 09:28:50.770217 <30>[ 20.369989] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10572 09:28:50.777291 <6>[ 20.380299] fuse: init (API version 7.37)
10573 09:28:50.802570 <30>[ 20.405891] systemd[1]: Starting Journal Service...
10574 09:28:50.809107 Starting [0;1;39mJournal Service[0m...
10575 09:28:50.833951 <30>[ 20.437337] systemd[1]: Starting Load Kernel Modules...
10576 09:28:50.839990 Starting [0;1;39mLoad Kernel Modules[0m...
10577 09:28:50.864622 <30>[ 20.464392] systemd[1]: Starting Remount Root and Kernel File Systems...
10578 09:28:50.871019 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10579 09:28:50.890288 <30>[ 20.494072] systemd[1]: Starting Coldplug All udev Devices...
10580 09:28:50.897248 Starting [0;1;39mColdplug All udev Devices[0m...
10581 09:28:50.921267 <30>[ 20.524344] systemd[1]: Mounted Huge Pages File System.
10582 09:28:50.931052 <3>[ 20.526835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10583 09:28:50.937611 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10584 09:28:50.950329 <30>[ 20.553836] systemd[1]: Mounted POSIX Message Queue File System.
10585 09:28:50.966925 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File Sy<3>[ 20.565389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10586 09:28:50.967040 stem[0m.
10587 09:28:50.982133 <30>[ 20.585726] systemd[1]: Mounted Kernel Debug File System.
10588 09:28:50.988720 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10589 09:28:51.010816 <30>[ 20.610819] systemd[1]: Finished Create list of static device nodes for the current kernel.
10590 09:28:51.020823 <3>[ 20.613749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10591 09:28:51.027576 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10592 09:28:51.043099 <30>[ 20.645787] systemd[1]: modprobe@configfs.service: Succeeded.
10593 09:28:51.052990 <3>[ 20.650140] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10594 09:28:51.059585 <30>[ 20.652503] systemd[1]: Finished Load Kernel Module configfs.
10595 09:28:51.066022 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10596 09:28:51.078610 <30>[ 20.681830] systemd[1]: modprobe@drm.service: Succeeded.
10597 09:28:51.089082 <3>[ 20.683064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10598 09:28:51.095359 <30>[ 20.687991] systemd[1]: Finished Load Kernel Module drm.
10599 09:28:51.098672 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10600 09:28:51.121573 <3>[ 20.721229] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10601 09:28:51.127971 <30>[ 20.722372] systemd[1]: modprobe@fuse.service: Succeeded.
10602 09:28:51.134693 <30>[ 20.736500] systemd[1]: Finished Load Kernel Module fuse.
10603 09:28:51.141800 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10604 09:28:51.152945 <3>[ 20.752930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10605 09:28:51.160319 <30>[ 20.763702] systemd[1]: Finished Load Kernel Modules.
10606 09:28:51.166958 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10607 09:28:51.185207 <3>[ 20.785318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10608 09:28:51.192555 <30>[ 20.787335] systemd[1]: Finished Remount Root and Kernel File Systems.
10609 09:28:51.198850 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10610 09:28:51.215472 <3>[ 20.815270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 09:28:51.245448 <3>[ 20.845309] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10612 09:28:51.260960 <30>[ 20.863980] systemd[1]: Mounting FUSE Control File System...
10613 09:28:51.267897 Mounting [0;1;39mFUSE Control File System[0m...
10614 09:28:51.286640 <30>[ 20.889641] systemd[1]: Mounting Kernel Configuration File System...
10615 09:28:51.293520 Mounting [0;1;39mKernel Configuration File System[0m...
10616 09:28:51.319403 <30>[ 20.919127] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10617 09:28:51.328896 <30>[ 20.928386] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10618 09:28:51.337645 <30>[ 20.940954] systemd[1]: Starting Load/Save Random Seed...
10619 09:28:51.344584 Starting [0;1;39mLoad/Save Random Seed[0m...
10620 09:28:51.363020 <30>[ 20.966302] systemd[1]: Starting Apply Kernel Variables...
10621 09:28:51.369404 Starting [0;1;39mApply Kernel Variables[0m...
10622 09:28:51.387496 <30>[ 20.990779] systemd[1]: Starting Create System Users...
10623 09:28:51.404171 <4>[ 20.992358] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10624 09:28:51.410827 <3>[ 21.012491] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10625 09:28:51.417707 Starting [0;1;39mCreate System Users[0m...
10626 09:28:51.432702 <30>[ 21.035203] systemd[1]: Started Journal Service.
10627 09:28:51.436022 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10628 09:28:51.456505 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10629 09:28:51.470103 See 'systemctl status systemd-udev-trigger.service' for details.
10630 09:28:51.486382 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10631 09:28:51.501798 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10632 09:28:51.517968 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10633 09:28:51.535897 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10634 09:28:51.556160 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10635 09:28:51.598836 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10636 09:28:51.615811 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10637 09:28:51.656493 <46>[ 21.256547] systemd-journald[290]: Received client request to flush runtime journal.
10638 09:28:51.972519 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10639 09:28:51.985324 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10640 09:28:52.001235 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10641 09:28:52.045160 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10642 09:28:53.055849 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10643 09:28:53.102262 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10644 09:28:53.159793 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10645 09:28:53.209912 Starting [0;1;39mNetwork Service[0m...
10646 09:28:53.540731 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10647 09:28:53.563795 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10648 09:28:53.606937 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10649 09:28:53.858586 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10650 09:28:53.876708 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10651 09:28:53.910217 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10652 09:28:53.933858 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10653 09:28:53.950003 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10654 09:28:53.990394 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10655 09:28:54.042487 Starting [0;1;39mNetwork Name Resolution[0m...
10656 09:28:54.071521 Starting [0;1;39mNetwork Time Synchronization[0m...
10657 09:28:54.091206 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10658 09:28:54.107185 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10659 09:28:54.166925 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10660 09:28:54.262335 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10661 09:28:54.278178 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10662 09:28:54.296751 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10663 09:28:54.309317 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10664 09:28:54.325369 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10665 09:28:54.477973 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10666 09:28:54.514269 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10667 09:28:54.544222 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10668 09:28:54.569764 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10669 09:28:54.581085 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10670 09:28:54.602068 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10671 09:28:54.613102 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10672 09:28:54.629526 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10673 09:28:54.674122 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10674 09:28:55.362148 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10675 09:28:55.745878 Starting [0;1;39mUser Login Management[0m...
10676 09:28:55.766904 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10677 09:28:55.784080 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10678 09:28:55.800228 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10679 09:28:55.857863 Starting [0;1;39mPermit User Sessions[0m...
10680 09:28:55.990517 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10681 09:28:56.037634 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10682 09:28:56.046493 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10683 09:28:56.067963 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10684 09:28:56.087904 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10685 09:28:56.105068 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10686 09:28:56.127902 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10687 09:28:56.150587 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10688 09:28:56.209890 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10689 09:28:56.277212 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10690 09:28:56.375029
10691 09:28:56.375175
10692 09:28:56.378706 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10693 09:28:56.378782
10694 09:28:56.382231 debian-bullseye-arm64 login: root (automatic login)
10695 09:28:56.382353
10696 09:28:56.382424
10697 09:28:56.696616 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
10698 09:28:56.697172
10699 09:28:56.703178 The programs included with the Debian GNU/Linux system are free software;
10700 09:28:56.709875 the exact distribution terms for each program are described in the
10701 09:28:56.713280 individual files in /usr/share/doc/*/copyright.
10702 09:28:56.713788
10703 09:28:56.719593 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10704 09:28:56.723026 permitted by applicable law.
10705 09:28:56.824662 Matched prompt #10: / #
10707 09:28:56.826064 Setting prompt string to ['/ #']
10708 09:28:56.826543 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10710 09:28:56.827599 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10711 09:28:56.828107 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10712 09:28:56.828526 Setting prompt string to ['/ #']
10713 09:28:56.828867 Forcing a shell prompt, looking for ['/ #']
10715 09:28:56.879724 / #
10716 09:28:56.880423 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10717 09:28:56.880883 Waiting using forced prompt support (timeout 00:02:30)
10718 09:28:56.886351
10719 09:28:56.887286 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10720 09:28:56.887818 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
10722 09:28:56.989119 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin'
10723 09:28:56.995862 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826831/extract-nfsrootfs-sd8iwjin'
10725 09:28:57.097779 / # export NFS_SERVER_IP='192.168.201.1'
10726 09:28:57.104271 export NFS_SERVER_IP='192.168.201.1'
10727 09:28:57.105239 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10728 09:28:57.105765 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
10729 09:28:57.106241 end: 2 depthcharge-action (duration 00:01:24) [common]
10730 09:28:57.106743 start: 3 lava-test-retry (timeout 00:01:00) [common]
10731 09:28:57.107220 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10732 09:28:57.107638 Using namespace: common
10734 09:28:57.208845 / # #
10735 09:28:57.209501 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10736 09:28:57.215104 #
10737 09:28:57.216020 Using /lava-11826831
10739 09:28:57.317360 / # export SHELL=/bin/sh
10740 09:28:57.324080 export SHELL=/bin/sh
10742 09:28:57.425794 / # . /lava-11826831/environment
10743 09:28:57.432169 . /lava-11826831/environment
10745 09:28:57.539733 / # /lava-11826831/bin/lava-test-runner /lava-11826831/0
10746 09:28:57.540420 Test shell timeout: 10s (minimum of the action and connection timeout)
10747 09:28:57.546264 /lava-11826831/bin/lava-test-runner /lava-11826831/0
10748 09:28:57.800780 + export TESTRUN_ID=0_dmesg
10749 09:28:57.804149 + cd /lava-11826831/0/tests/0_dmesg
10750 09:28:57.807124 + cat uuid
10751 09:28:57.815355 + <8>[ 27.419881] <LAVA_SIGNAL_STARTRUN 0_dmesg 11826831_1.6.2.3.1>
10752 09:28:57.815740 Received signal: <STARTRUN> 0_dmesg 11826831_1.6.2.3.1
10753 09:28:57.815874 Starting test lava.0_dmesg (11826831_1.6.2.3.1)
10754 09:28:57.816012 Skipping test definition patterns.
10755 09:28:57.818847 UUID=11826831_1.6.2.3.1
10756 09:28:57.819018 + set +x
10757 09:28:57.825401 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10758 09:28:57.920673 <8>[ 27.521449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10759 09:28:57.921560 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10761 09:28:58.006443 <8>[ 27.607220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10762 09:28:58.007291 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10764 09:28:58.097219 <8>[ 27.698135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10765 09:28:58.097962 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10767 09:28:58.100823 + set +x
10768 09:28:58.103940 <8>[ 27.707826] <LAVA_SIGNAL_ENDRUN 0_dmesg 11826831_1.6.2.3.1>
10769 09:28:58.104812 Received signal: <ENDRUN> 0_dmesg 11826831_1.6.2.3.1
10770 09:28:58.105278 Ending use of test pattern.
10771 09:28:58.105635 Ending test lava.0_dmesg (11826831_1.6.2.3.1), duration 0.29
10773 09:28:58.116133 <LAVA_TEST_RUNNER EXIT>
10774 09:28:58.116885 ok: lava_test_shell seems to have completed
10775 09:28:58.117535 alert: pass
crit: pass
emerg: pass
10776 09:28:58.117985 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10777 09:28:58.118442 end: 3 lava-test-retry (duration 00:00:01) [common]
10778 09:28:58.118917 start: 4 lava-test-retry (timeout 00:01:00) [common]
10779 09:28:58.119367 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10780 09:28:58.119723 Using namespace: common
10782 09:28:58.220907 / # #
10783 09:28:58.221556 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10784 09:28:58.222250 Using /lava-11826831
10786 09:28:58.323516 export SHELL=/bin/sh
10787 09:28:58.324382 #
10789 09:28:58.426304 / # export SHELL=/bin/sh. /lava-11826831/environment
10790 09:28:58.427086
10792 09:28:58.528800 / # . /lava-11826831/environment/lava-11826831/bin/lava-test-runner /lava-11826831/1
10793 09:28:58.529422 Test shell timeout: 10s (minimum of the action and connection timeout)
10794 09:28:58.529994
10795 09:28:58.535211 / # /lava-11826831/bin/lava-test-runner /lava-11826831/1
10796 09:28:58.659061 + export TESTRUN_ID=1_bootrr
10797 09:28:58.662472 + cd /lava-11826831/1/tests/1_bootrr
10798 09:28:58.665803 + cat uuid
10799 09:28:58.680894 + UUID=11826831_1.<8>[ 28.281693] <LAVA_SIGNAL_STARTRUN 1_bootrr 11826831_1.6.2.3.5>
10800 09:28:58.681467 6.2.3.5
10801 09:28:58.682075 + set +x
10802 09:28:58.682952 Received signal: <STARTRUN> 1_bootrr 11826831_1.6.2.3.5
10803 09:28:58.683354 Starting test lava.1_bootrr (11826831_1.6.2.3.5)
10804 09:28:58.683996 Skipping test definition patterns.
10805 09:28:58.694414 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11826831/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
10806 09:28:58.697123 + cd /opt/bootrr/libexec/bootrr
10807 09:28:58.697588 + sh helpers/bootrr-auto
10808 09:28:58.766425 /lava-11826831/1/../bin/lava-test-case
10809 09:28:58.799671 <8>[ 28.400183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10810 09:28:58.800656 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10812 09:28:58.847429 /lava-11826831/1/../bin/lava-test-case
10813 09:28:58.876522 <8>[ 28.477561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10814 09:28:58.877251 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10816 09:28:58.899847 /lava-11826831/1/../bin/lava-test-case
10817 09:28:58.927035 <8>[ 28.527636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
10818 09:28:58.927889 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
10820 09:28:58.985809 /lava-11826831/1/../bin/lava-test-case
10821 09:28:59.012242 <8>[ 28.613183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10822 09:28:59.013219 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10824 09:28:59.062073 /lava-11826831/1/../bin/lava-test-case
10825 09:28:59.089552 <8>[ 28.690577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10826 09:28:59.090316 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10828 09:28:59.127999 /lava-11826831/1/../bin/lava-test-case
10829 09:28:59.157031 <8>[ 28.758202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10830 09:28:59.157776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10832 09:28:59.194963 /lava-11826831/1/../bin/lava-test-case
10833 09:28:59.225523 <8>[ 28.826515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10834 09:28:59.226367 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10836 09:28:59.263432 /lava-11826831/1/../bin/lava-test-case
10837 09:28:59.295427 <8>[ 28.896304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10838 09:28:59.296370 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10840 09:28:59.327796 /lava-11826831/1/../bin/lava-test-case
10841 09:28:59.356294 <8>[ 28.957175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10842 09:28:59.357161 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10844 09:28:59.394379 /lava-11826831/1/../bin/lava-test-case
10845 09:28:59.423806 <8>[ 29.025027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10846 09:28:59.424171 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10848 09:28:59.444226 /lava-11826831/1/../bin/lava-test-case
10849 09:28:59.471431 <8>[ 29.072719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10850 09:28:59.471790 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10852 09:28:59.507164 /lava-11826831/1/../bin/lava-test-case
10853 09:28:59.535337 <8>[ 29.136184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10854 09:28:59.536411 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10856 09:28:59.572721 /lava-11826831/1/../bin/lava-test-case
10857 09:28:59.600218 <8>[ 29.201295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10858 09:28:59.601065 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10860 09:28:59.638642 /lava-11826831/1/../bin/lava-test-case
10861 09:28:59.667647 <8>[ 29.268631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10862 09:28:59.668563 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10864 09:28:59.711429 /lava-11826831/1/../bin/lava-test-case
10865 09:28:59.741348 <8>[ 29.342917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10866 09:28:59.741716 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10868 09:28:59.765646 /lava-11826831/1/../bin/lava-test-case
10869 09:28:59.793824 <8>[ 29.394606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10870 09:28:59.794531 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10872 09:28:59.827637 /lava-11826831/1/../bin/lava-test-case
10873 09:28:59.858586 <8>[ 29.459274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10874 09:28:59.859495 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10876 09:28:59.883336 /lava-11826831/1/../bin/lava-test-case
10877 09:28:59.913549 <8>[ 29.514675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10878 09:28:59.913836 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10880 09:28:59.950847 /lava-11826831/1/../bin/lava-test-case
10881 09:28:59.979520 <8>[ 29.580477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10882 09:28:59.980278 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10884 09:29:00.004384 /lava-11826831/1/../bin/lava-test-case
10885 09:29:00.033101 <8>[ 29.634096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10886 09:29:00.034006 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10888 09:29:00.075627 /lava-11826831/1/../bin/lava-test-case
10889 09:29:00.105335 <8>[ 29.706499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10890 09:29:00.106166 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10892 09:29:00.129209 /lava-11826831/1/../bin/lava-test-case
10893 09:29:00.160923 <8>[ 29.762086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10894 09:29:00.161661 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10896 09:29:00.201235 /lava-11826831/1/../bin/lava-test-case
10897 09:29:00.233247 <8>[ 29.834425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10898 09:29:00.233995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10900 09:29:00.257327 /lava-11826831/1/../bin/lava-test-case
10901 09:29:00.284968 <8>[ 29.886219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10902 09:29:00.285706 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10904 09:29:00.321152 /lava-11826831/1/../bin/lava-test-case
10905 09:29:00.349700 <8>[ 29.950798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10906 09:29:00.350614 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10908 09:29:00.388869 /lava-11826831/1/../bin/lava-test-case
10909 09:29:00.420310 <8>[ 30.020976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10910 09:29:00.421207 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10912 09:29:00.445347 /lava-11826831/1/../bin/lava-test-case
10913 09:29:00.474185 <8>[ 30.074785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10914 09:29:00.475027 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10916 09:29:00.514784 /lava-11826831/1/../bin/lava-test-case
10917 09:29:00.547239 <8>[ 30.148127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10918 09:29:00.548121 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10920 09:29:00.569609 /lava-11826831/1/../bin/lava-test-case
10921 09:29:00.601617 <8>[ 30.202682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10922 09:29:00.602479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10924 09:29:00.640326 /lava-11826831/1/../bin/lava-test-case
10925 09:29:00.672287 <8>[ 30.273580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10926 09:29:00.673031 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10928 09:29:00.709784 /lava-11826831/1/../bin/lava-test-case
10929 09:29:00.741690 <8>[ 30.342653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10930 09:29:00.742548 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10932 09:29:00.778921 /lava-11826831/1/../bin/lava-test-case
10933 09:29:00.803544 <8>[ 30.404984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10934 09:29:00.804059 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10936 09:29:00.840886 /lava-11826831/1/../bin/lava-test-case
10937 09:29:00.872744 <8>[ 30.473960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10938 09:29:00.873484 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10940 09:29:00.898134 /lava-11826831/1/../bin/lava-test-case
10941 09:29:00.930140 <8>[ 30.530879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10942 09:29:00.931036 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10944 09:29:00.971247 /lava-11826831/1/../bin/lava-test-case
10945 09:29:01.002629 <8>[ 30.603777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10946 09:29:01.003408 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10948 09:29:01.040332 /lava-11826831/1/../bin/lava-test-case
10949 09:29:01.073973 <8>[ 30.675317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10950 09:29:01.074764 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10952 09:29:01.103573 /lava-11826831/1/../bin/lava-test-case
10953 09:29:01.132281 <8>[ 30.733433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10954 09:29:01.132961 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10956 09:29:01.170805 /lava-11826831/1/../bin/lava-test-case
10957 09:29:01.200675 <8>[ 30.801626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10958 09:29:01.201557 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10960 09:29:01.222918 /lava-11826831/1/../bin/lava-test-case
10961 09:29:01.250830 <8>[ 30.852211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10962 09:29:01.251656 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10964 09:29:01.288527 /lava-11826831/1/../bin/lava-test-case
10965 09:29:01.318184 <8>[ 30.919584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10966 09:29:01.319007 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10968 09:29:01.342523 /lava-11826831/1/../bin/lava-test-case
10969 09:29:01.373549 <8>[ 30.975013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10970 09:29:01.374372 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10972 09:29:01.411934 /lava-11826831/1/../bin/lava-test-case
10973 09:29:01.441984 <8>[ 31.043310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10974 09:29:01.442809 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10976 09:29:01.471145 /lava-11826831/1/../bin/lava-test-case
10977 09:29:01.502617 <8>[ 31.104037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10978 09:29:01.503352 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10980 09:29:01.539960 /lava-11826831/1/../bin/lava-test-case
10981 09:29:01.569475 <8>[ 31.170644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10982 09:29:01.570270 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10984 09:29:01.595472 /lava-11826831/1/../bin/lava-test-case
10985 09:29:01.627628 <8>[ 31.228417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10986 09:29:01.628535 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10988 09:29:01.662280 /lava-11826831/1/../bin/lava-test-case
10989 09:29:01.693356 <8>[ 31.294119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10990 09:29:01.694211 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10992 09:29:01.714944 /lava-11826831/1/../bin/lava-test-case
10993 09:29:01.744361 <8>[ 31.345480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10994 09:29:01.745210 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10996 09:29:01.787924 /lava-11826831/1/../bin/lava-test-case
10997 09:29:01.816244 <8>[ 31.417413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10998 09:29:01.817099 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11000 09:29:01.839126 /lava-11826831/1/../bin/lava-test-case
11001 09:29:01.870565 <8>[ 31.471598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11002 09:29:01.871426 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11004 09:29:01.912048 /lava-11826831/1/../bin/lava-test-case
11005 09:29:01.943290 <8>[ 31.544435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11006 09:29:01.944135 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11008 09:29:01.981939 /lava-11826831/1/../bin/lava-test-case
11009 09:29:02.012814 <8>[ 31.614027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11010 09:29:02.013553 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11012 09:29:02.035100 /lava-11826831/1/../bin/lava-test-case
11013 09:29:02.064072 <8>[ 31.665319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11014 09:29:02.064978 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11016 09:29:02.106649 /lava-11826831/1/../bin/lava-test-case
11017 09:29:02.135182 <8>[ 31.736527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11018 09:29:02.136035 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11020 09:29:02.157413 /lava-11826831/1/../bin/lava-test-case
11021 09:29:02.187401 <8>[ 31.788588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11022 09:29:02.188294 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11024 09:29:02.223629 /lava-11826831/1/../bin/lava-test-case
11025 09:29:02.254263 <8>[ 31.855498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11026 09:29:02.255089 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11028 09:29:02.291354 /lava-11826831/1/../bin/lava-test-case
11029 09:29:02.319351 <8>[ 31.920776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11030 09:29:02.320089 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11032 09:29:02.354964 /lava-11826831/1/../bin/lava-test-case
11033 09:29:02.383225 <8>[ 31.984729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11034 09:29:02.383966 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11036 09:29:02.422462 /lava-11826831/1/../bin/lava-test-case
11037 09:29:02.459610 <8>[ 32.060899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11038 09:29:02.460480 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11040 09:29:02.497490 /lava-11826831/1/../bin/lava-test-case
11041 09:29:02.527356 <8>[ 32.128768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11042 09:29:02.528097 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11044 09:29:02.551249 /lava-11826831/1/../bin/lava-test-case
11045 09:29:02.583058 <8>[ 32.184375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11046 09:29:02.583976 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11048 09:29:02.620676 /lava-11826831/1/../bin/lava-test-case
11049 09:29:02.649479 <8>[ 32.250877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11050 09:29:02.650305 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11052 09:29:02.685972 /lava-11826831/1/../bin/lava-test-case
11053 09:29:02.717555 <8>[ 32.319080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11054 09:29:02.718297 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11056 09:29:02.748096 /lava-11826831/1/../bin/lava-test-case
11057 09:29:02.779224 <8>[ 32.380400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11058 09:29:02.780068 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11060 09:29:02.819591 /lava-11826831/1/../bin/lava-test-case
11061 09:29:02.850593 <8>[ 32.451994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11062 09:29:02.851343 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11064 09:29:02.875009 /lava-11826831/1/../bin/lava-test-case
11065 09:29:02.904761 <8>[ 32.505992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11066 09:29:02.905637 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11068 09:29:02.943606 /lava-11826831/1/../bin/lava-test-case
11069 09:29:02.976309 <8>[ 32.577522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11070 09:29:02.977096 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11072 09:29:02.999588 /lava-11826831/1/../bin/lava-test-case
11073 09:29:03.028313 <8>[ 32.629806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11074 09:29:03.029194 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11076 09:29:03.071570 /lava-11826831/1/../bin/lava-test-case
11077 09:29:03.103504 <8>[ 32.704768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11078 09:29:03.104329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11080 09:29:03.141519 /lava-11826831/1/../bin/lava-test-case
11081 09:29:03.175235 <8>[ 32.776739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11082 09:29:03.176011 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11084 09:29:03.214262 /lava-11826831/1/../bin/lava-test-case
11085 09:29:03.245643 <8>[ 32.846891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11086 09:29:03.246486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11088 09:29:03.284910 /lava-11826831/1/../bin/lava-test-case
11089 09:29:03.319029 <8>[ 32.920404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11090 09:29:03.319776 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11092 09:29:03.358617 /lava-11826831/1/../bin/lava-test-case
11093 09:29:03.389400 <8>[ 32.990696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11094 09:29:03.390262 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11096 09:29:03.432215 /lava-11826831/1/../bin/lava-test-case
11097 09:29:03.463260 <8>[ 33.064706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11098 09:29:03.464114 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11100 09:29:03.503862 /lava-11826831/1/../bin/lava-test-case
11101 09:29:03.537830 <8>[ 33.139026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11102 09:29:03.538683 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11104 09:29:03.575028 /lava-11826831/1/../bin/lava-test-case
11105 09:29:03.605077 <8>[ 33.206456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11106 09:29:03.606134 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11108 09:29:03.644767 /lava-11826831/1/../bin/lava-test-case
11109 09:29:03.677056 <8>[ 33.278679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11110 09:29:03.677889 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11112 09:29:03.717634 /lava-11826831/1/../bin/lava-test-case
11113 09:29:03.749738 <8>[ 33.350839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11114 09:29:03.750598 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11116 09:29:03.793892 /lava-11826831/1/../bin/lava-test-case
11117 09:29:03.827500 <8>[ 33.429126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11118 09:29:03.828328 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11120 09:29:03.865114 /lava-11826831/1/../bin/lava-test-case
11121 09:29:03.897115 <8>[ 33.498650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11122 09:29:03.897945 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11124 09:29:03.937615 /lava-11826831/1/../bin/lava-test-case
11125 09:29:03.969382 <8>[ 33.570644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11126 09:29:03.970252 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11128 09:29:04.008675 /lava-11826831/1/../bin/lava-test-case
11129 09:29:04.040143 <8>[ 33.641595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11130 09:29:04.041049 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11132 09:29:04.078526 /lava-11826831/1/../bin/lava-test-case
11133 09:29:04.110542 <8>[ 33.712255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11134 09:29:04.111514 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11136 09:29:04.140479 /lava-11826831/1/../bin/lava-test-case
11137 09:29:04.170660 <8>[ 33.772374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11138 09:29:04.171402 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11140 09:29:04.208652 /lava-11826831/1/../bin/lava-test-case
11141 09:29:04.238894 <8>[ 33.840392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11142 09:29:04.239741 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11144 09:29:04.262917 /lava-11826831/1/../bin/lava-test-case
11145 09:29:04.291797 <8>[ 33.893491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11146 09:29:04.292674 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11148 09:29:04.328660 /lava-11826831/1/../bin/lava-test-case
11149 09:29:04.360829 <8>[ 33.962606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11150 09:29:04.361712 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11152 09:29:04.382592 /lava-11826831/1/../bin/lava-test-case
11153 09:29:04.411764 <8>[ 34.013503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11154 09:29:04.412732 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11156 09:29:04.454840 /lava-11826831/1/../bin/lava-test-case
11157 09:29:04.482107 <8>[ 34.083840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11158 09:29:04.482848 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11160 09:29:04.504490 /lava-11826831/1/../bin/lava-test-case
11161 09:29:04.532342 <8>[ 34.134044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11162 09:29:04.533027 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11164 09:29:04.572956 /lava-11826831/1/../bin/lava-test-case
11165 09:29:04.606456 <8>[ 34.208115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11166 09:29:04.607291 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11168 09:29:04.630068 /lava-11826831/1/../bin/lava-test-case
11169 09:29:04.660670 <8>[ 34.262358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11170 09:29:04.661405 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11172 09:29:04.700990 /lava-11826831/1/../bin/lava-test-case
11173 09:29:04.732741 <8>[ 34.334197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11174 09:29:04.733467 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11176 09:29:04.760862 /lava-11826831/1/../bin/lava-test-case
11177 09:29:04.791367 <8>[ 34.392884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11178 09:29:04.792233 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11180 09:29:04.830779 /lava-11826831/1/../bin/lava-test-case
11181 09:29:04.861925 <8>[ 34.463667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11182 09:29:04.862685 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11184 09:29:04.899565 /lava-11826831/1/../bin/lava-test-case
11185 09:29:04.930535 <8>[ 34.531982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11186 09:29:04.931414 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11188 09:29:04.955489 /lava-11826831/1/../bin/lava-test-case
11189 09:29:04.985430 <8>[ 34.587123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11190 09:29:04.986322 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11192 09:29:05.022002 /lava-11826831/1/../bin/lava-test-case
11193 09:29:05.052529 <8>[ 34.654134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11194 09:29:05.053381 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11196 09:29:05.082783 /lava-11826831/1/../bin/lava-test-case
11197 09:29:05.116258 <8>[ 34.718091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11198 09:29:05.117104 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11200 09:29:05.151795 /lava-11826831/1/../bin/lava-test-case
11201 09:29:05.182242 <8>[ 34.783877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11202 09:29:05.182976 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11204 09:29:05.206346 /lava-11826831/1/../bin/lava-test-case
11205 09:29:05.236375 <8>[ 34.837838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11206 09:29:05.237229 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11208 09:29:06.290142 /lava-11826831/1/../bin/lava-test-case
11209 09:29:06.315389 <8>[ 35.917444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11210 09:29:06.315753 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11212 09:29:06.337818 /lava-11826831/1/../bin/lava-test-case
11213 09:29:06.362525 <8>[ 35.964608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11214 09:29:06.363027 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11216 09:29:07.407673 /lava-11826831/1/../bin/lava-test-case
11217 09:29:07.434612 <8>[ 37.037084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11218 09:29:07.434943 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11220 09:29:07.454344 /lava-11826831/1/../bin/lava-test-case
11221 09:29:07.479542 <8>[ 37.081983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11222 09:29:07.479830 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11224 09:29:08.520227 /lava-11826831/1/../bin/lava-test-case
11225 09:29:08.545707 <8>[ 38.148107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11226 09:29:08.546051 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11228 09:29:08.564112 /lava-11826831/1/../bin/lava-test-case
11229 09:29:08.582166 <8>[ 38.184688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11230 09:29:08.582498 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11232 09:29:09.622041 /lava-11826831/1/../bin/lava-test-case
11233 09:29:09.650394 <8>[ 39.253132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11234 09:29:09.650743 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11236 09:29:09.668970 /lava-11826831/1/../bin/lava-test-case
11237 09:29:09.690876 <8>[ 39.293537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11238 09:29:09.691191 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11240 09:29:10.731654 /lava-11826831/1/../bin/lava-test-case
11241 09:29:10.758351 <8>[ 40.361190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11242 09:29:10.758688 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11244 09:29:10.778188 /lava-11826831/1/../bin/lava-test-case
11245 09:29:10.798506 <8>[ 40.401397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11246 09:29:10.798805 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11248 09:29:11.834281 /lava-11826831/1/../bin/lava-test-case
11249 09:29:11.860982 <8>[ 41.463864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11250 09:29:11.861302 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11252 09:29:11.879935 /lava-11826831/1/../bin/lava-test-case
11253 09:29:11.901186 <8>[ 41.504121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11254 09:29:11.901479 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11256 09:29:12.939535 /lava-11826831/1/../bin/lava-test-case
11257 09:29:12.967182 <8>[ 42.570114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11258 09:29:12.967464 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11260 09:29:12.986520 /lava-11826831/1/../bin/lava-test-case
11261 09:29:13.008036 <8>[ 42.611125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11262 09:29:13.008295 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11264 09:29:13.025720 /lava-11826831/1/../bin/lava-test-case
11265 09:29:13.047993 <8>[ 42.651104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11266 09:29:13.048259 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11268 09:29:14.086295 /lava-11826831/1/../bin/lava-test-case
11269 09:29:14.113206 <8>[ 43.716493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11270 09:29:14.113527 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11272 09:29:14.134925 /lava-11826831/1/../bin/lava-test-case
11273 09:29:14.159957 <8>[ 43.763217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11274 09:29:14.160292 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11276 09:29:14.192497 /lava-11826831/1/../bin/lava-test-case
11277 09:29:14.218646 <8>[ 43.821615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11278 09:29:14.218969 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11280 09:29:14.238531 /lava-11826831/1/../bin/lava-test-case
11281 09:29:14.261779 <8>[ 43.865147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11282 09:29:14.262094 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11284 09:29:14.292569 /lava-11826831/1/../bin/lava-test-case
11285 09:29:14.317222 <8>[ 43.920073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11286 09:29:14.317549 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11288 09:29:14.346104 /lava-11826831/1/../bin/lava-test-case
11289 09:29:14.369789 <8>[ 43.973030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11290 09:29:14.370086 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11292 09:29:14.405961 /lava-11826831/1/../bin/lava-test-case
11293 09:29:14.429253 <8>[ 44.032576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11294 09:29:14.429583 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11296 09:29:14.449010 /lava-11826831/1/../bin/lava-test-case
11297 09:29:14.473631 <8>[ 44.076648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11298 09:29:14.473963 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11300 09:29:14.502276 /lava-11826831/1/../bin/lava-test-case
11301 09:29:14.524343 <8>[ 44.127452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11302 09:29:14.524672 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11304 09:29:14.555181 /lava-11826831/1/../bin/lava-test-case
11305 09:29:14.579557 <8>[ 44.182896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11306 09:29:14.579902 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11308 09:29:14.599181 /lava-11826831/1/../bin/lava-test-case
11309 09:29:14.621145 <8>[ 44.224575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11310 09:29:14.621478 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11312 09:29:14.651028 /lava-11826831/1/../bin/lava-test-case
11313 09:29:14.672729 <8>[ 44.276157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11314 09:29:14.673016 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11316 09:29:14.693197 /lava-11826831/1/../bin/lava-test-case
11317 09:29:14.721079 <8>[ 44.324490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11318 09:29:14.721378 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11320 09:29:14.748492 /lava-11826831/1/../bin/lava-test-case
11321 09:29:14.770054 <8>[ 44.373373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11322 09:29:14.770358 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11324 09:29:14.789062 /lava-11826831/1/../bin/lava-test-case
11325 09:29:14.812019 <8>[ 44.415485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11326 09:29:14.812301 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11328 09:29:14.842157 /lava-11826831/1/../bin/lava-test-case
11329 09:29:14.864692 <8>[ 44.467961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11330 09:29:14.864959 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11332 09:29:14.883542 /lava-11826831/1/../bin/lava-test-case
11333 09:29:14.905070 <8>[ 44.508153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11334 09:29:14.905348 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11336 09:29:14.935247 /lava-11826831/1/../bin/lava-test-case
11337 09:29:14.958048 <8>[ 44.561198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11338 09:29:14.958374 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11340 09:29:14.981168 /lava-11826831/1/../bin/lava-test-case
11341 09:29:15.003984 <8>[ 44.607198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11342 09:29:15.004308 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11344 09:29:15.041322 /lava-11826831/1/../bin/lava-test-case
11345 09:29:15.065004 <8>[ 44.668271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11346 09:29:15.065285 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11348 09:29:15.083696 /lava-11826831/1/../bin/lava-test-case
11349 09:29:15.106471 <8>[ 44.709673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11350 09:29:15.106730 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11352 09:29:16.144747 /lava-11826831/1/../bin/lava-test-case
11353 09:29:16.170204 <8>[ 45.773270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11354 09:29:16.170469 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11356 09:29:16.547346 <6>[ 46.157206] vpu: disabling
11357 09:29:16.550881 <6>[ 46.160346] vproc2: disabling
11358 09:29:16.554805 <6>[ 46.164609] vproc1: disabling
11359 09:29:16.558351 <6>[ 46.168211] vaud18: disabling
11360 09:29:16.565456 <6>[ 46.172015] vsram_others: disabling
11361 09:29:16.568521 <6>[ 46.176253] va09: disabling
11362 09:29:16.571968 <6>[ 46.179693] vsram_md: disabling
11363 09:29:16.575158 <6>[ 46.183504] Vgpu: disabling
11364 09:29:17.205017 /lava-11826831/1/../bin/lava-test-case
11365 09:29:17.231023 <8>[ 46.834473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11366 09:29:17.231300 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11368 09:29:17.249985 /lava-11826831/1/../bin/lava-test-case
11369 09:29:17.273011 <8>[ 46.876515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11370 09:29:17.273293 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11372 09:29:17.303516 /lava-11826831/1/../bin/lava-test-case
11373 09:29:17.326276 <8>[ 46.929831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11374 09:29:17.326532 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11376 09:29:17.345539 /lava-11826831/1/../bin/lava-test-case
11377 09:29:17.369622 <8>[ 46.973172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11378 09:29:17.369879 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11380 09:29:17.397167 /lava-11826831/1/../bin/lava-test-case
11381 09:29:17.421726 <8>[ 47.025127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11382 09:29:17.421981 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11384 09:29:17.444118 /lava-11826831/1/../bin/lava-test-case
11385 09:29:17.466358 <8>[ 47.070090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11386 09:29:17.466615 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11388 09:29:17.496592 /lava-11826831/1/../bin/lava-test-case
11389 09:29:17.516726 <8>[ 47.120222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11390 09:29:17.516984 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11392 09:29:17.541753 /lava-11826831/1/../bin/lava-test-case
11393 09:29:17.566621 <8>[ 47.170130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11394 09:29:17.566957 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11396 09:29:17.594638 /lava-11826831/1/../bin/lava-test-case
11397 09:29:17.619213 <8>[ 47.222769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11398 09:29:17.619525 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11400 09:29:17.639727 /lava-11826831/1/../bin/lava-test-case
11401 09:29:17.664382 <8>[ 47.268025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11402 09:29:17.664704 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11404 09:29:17.694564 /lava-11826831/1/../bin/lava-test-case
11405 09:29:17.716001 <8>[ 47.319655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11406 09:29:17.716316 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11408 09:29:17.734052 /lava-11826831/1/../bin/lava-test-case
11409 09:29:17.755691 <8>[ 47.359258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11410 09:29:17.756014 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11412 09:29:17.784717 /lava-11826831/1/../bin/lava-test-case
11413 09:29:17.809079 <8>[ 47.412882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11414 09:29:17.809410 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11416 09:29:17.825308 /lava-11826831/1/../bin/lava-test-case
11417 09:29:17.847643 <8>[ 47.451305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11418 09:29:17.847971 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11420 09:29:17.882126 /lava-11826831/1/../bin/lava-test-case
11421 09:29:17.901301 <8>[ 47.504937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11422 09:29:17.901628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11424 09:29:17.918302 /lava-11826831/1/../bin/lava-test-case
11425 09:29:17.941255 <8>[ 47.544815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11426 09:29:17.941590 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11428 09:29:17.973118 /lava-11826831/1/../bin/lava-test-case
11429 09:29:17.996542 <8>[ 47.600068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11430 09:29:17.996870 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11432 09:29:18.015199 /lava-11826831/1/../bin/lava-test-case
11433 09:29:18.039985 <8>[ 47.643504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11434 09:29:18.040321 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11436 09:29:18.068578 /lava-11826831/1/../bin/lava-test-case
11437 09:29:18.091615 <8>[ 47.695315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11438 09:29:18.091947 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11440 09:29:18.111016 /lava-11826831/1/../bin/lava-test-case
11441 09:29:18.133520 <8>[ 47.736888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11442 09:29:18.133851 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11444 09:29:18.162027 /lava-11826831/1/../bin/lava-test-case
11445 09:29:18.186128 <8>[ 47.789848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11446 09:29:18.186463 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11448 09:29:19.221036 /lava-11826831/1/../bin/lava-test-case
11449 09:29:19.247532 <8>[ 48.851478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11450 09:29:19.247863 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11452 09:29:20.278024 /lava-11826831/1/../bin/lava-test-case
11453 09:29:20.302651 <8>[ 49.906400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11454 09:29:20.302981 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11455 09:29:20.303080 Bad test result: blocked
11456 09:29:20.320120 /lava-11826831/1/../bin/lava-test-case
11457 09:29:20.341049 <8>[ 49.944599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11458 09:29:20.341379 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11460 09:29:21.376717 /lava-11826831/1/../bin/lava-test-case
11461 09:29:21.400739 <8>[ 51.004733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11462 09:29:21.401126 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11464 09:29:21.417687 /lava-11826831/1/../bin/lava-test-case
11465 09:29:21.444057 <8>[ 51.048000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11466 09:29:21.444428 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11468 09:29:21.472423 /lava-11826831/1/../bin/lava-test-case
11469 09:29:21.494521 <8>[ 51.098456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11470 09:29:21.494854 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11472 09:29:21.519979 /lava-11826831/1/../bin/lava-test-case
11473 09:29:21.544366 <8>[ 51.148384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11474 09:29:21.544700 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11476 09:29:21.563493 /lava-11826831/1/../bin/lava-test-case
11477 09:29:21.585565 <8>[ 51.189739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11478 09:29:21.585898 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11480 09:29:21.615017 /lava-11826831/1/../bin/lava-test-case
11481 09:29:21.639275 <8>[ 51.243371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11482 09:29:21.639608 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11484 09:29:21.658047 /lava-11826831/1/../bin/lava-test-case
11485 09:29:21.679400 <8>[ 51.283186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11486 09:29:21.679732 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11488 09:29:22.723252 /lava-11826831/1/../bin/lava-test-case
11489 09:29:22.750985 <8>[ 52.354944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11490 09:29:22.751315 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11492 09:29:22.768757 /lava-11826831/1/../bin/lava-test-case
11493 09:29:22.788822 <8>[ 52.393019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11494 09:29:22.789146 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11496 09:29:23.826445 /lava-11826831/1/../bin/lava-test-case
11497 09:29:23.852082 <8>[ 53.456536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11498 09:29:23.852520 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11500 09:29:23.867932 /lava-11826831/1/../bin/lava-test-case
11501 09:29:23.886541 <8>[ 53.490855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11502 09:29:23.886876 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11504 09:29:24.920892 /lava-11826831/1/../bin/lava-test-case
11505 09:29:24.947027 <8>[ 54.551357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11506 09:29:24.947405 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11508 09:29:24.965800 /lava-11826831/1/../bin/lava-test-case
11509 09:29:24.986767 <8>[ 54.591357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11510 09:29:24.987101 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11512 09:29:26.024666 /lava-11826831/1/../bin/lava-test-case
11513 09:29:26.052209 <8>[ 55.656737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11514 09:29:26.052560 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11516 09:29:26.070446 /lava-11826831/1/../bin/lava-test-case
11517 09:29:26.089179 <8>[ 55.693814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11518 09:29:26.089537 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11520 09:29:26.115428 /lava-11826831/1/../bin/lava-test-case
11521 09:29:26.137415 <8>[ 55.742132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11522 09:29:26.137725 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11524 09:29:26.163788 /lava-11826831/1/../bin/lava-test-case
11525 09:29:26.184317 <8>[ 55.788978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11526 09:29:26.184616 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11528 09:29:26.201571 /lava-11826831/1/../bin/lava-test-case
11529 09:29:26.221627 <8>[ 55.826203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11530 09:29:26.221940 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11532 09:29:26.247704 /lava-11826831/1/../bin/lava-test-case
11533 09:29:26.268369 <8>[ 55.872951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11534 09:29:26.268676 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11536 09:29:26.287047 /lava-11826831/1/../bin/lava-test-case
11537 09:29:26.309855 <8>[ 55.914503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11538 09:29:26.310175 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11540 09:29:26.347357 /lava-11826831/1/../bin/lava-test-case
11541 09:29:26.367925 <8>[ 55.972559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11542 09:29:26.368277 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11544 09:29:26.388475 /lava-11826831/1/../bin/lava-test-case
11545 09:29:26.409720 <8>[ 56.014279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11546 09:29:26.410037 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11548 09:29:26.437823 /lava-11826831/1/../bin/lava-test-case
11549 09:29:26.459699 <8>[ 56.064326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11550 09:29:26.460029 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11552 09:29:26.464933 + set +x
11553 09:29:26.468307 Received signal: <ENDRUN> 1_bootrr 11826831_1.6.2.3.5
11554 09:29:26.468405 Ending use of test pattern.
11555 09:29:26.468473 Ending test lava.1_bootrr (11826831_1.6.2.3.5), duration 27.79
11557 09:29:26.471398 <8>[ 56.076205] <LAVA_SIGNAL_ENDRUN 1_bootrr 11826831_1.6.2.3.5>
11558 09:29:26.475195 <LAVA_TEST_RUNNER EXIT>
11559 09:29:26.475451 ok: lava_test_shell seems to have completed
11560 09:29:26.476485 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11561 09:29:26.476631 end: 4.1 lava-test-shell (duration 00:00:28) [common]
11562 09:29:26.476720 end: 4 lava-test-retry (duration 00:00:28) [common]
11563 09:29:26.476809 start: 5 finalize (timeout 00:07:41) [common]
11564 09:29:26.476898 start: 5.1 power-off (timeout 00:00:30) [common]
11565 09:29:26.477051 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11566 09:29:26.552669 >> Command sent successfully.
11567 09:29:26.555215 Returned 0 in 0 seconds
11568 09:29:26.655650 end: 5.1 power-off (duration 00:00:00) [common]
11570 09:29:26.656002 start: 5.2 read-feedback (timeout 00:07:41) [common]
11571 09:29:26.656292 Listened to connection for namespace 'common' for up to 1s
11572 09:29:27.656286 Finalising connection for namespace 'common'
11573 09:29:27.656472 Disconnecting from shell: Finalise
11574 09:29:27.656557 / #
11575 09:29:27.756907 end: 5.2 read-feedback (duration 00:00:01) [common]
11576 09:29:27.757092 end: 5 finalize (duration 00:00:01) [common]
11577 09:29:27.757210 Cleaning after the job
11578 09:29:27.757310 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/ramdisk
11579 09:29:27.760026 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/kernel
11580 09:29:27.772692 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/dtb
11581 09:29:27.772910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/nfsrootfs
11582 09:29:27.847430 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826831/tftp-deploy-_m38mr1m/modules
11583 09:29:27.854855 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826831
11584 09:29:28.236794 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826831
11585 09:29:28.236982 Job finished correctly