Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Kernel Errors: 34
- Errors: 1
- Boot result: PASS
1 09:26:37.319956 lava-dispatcher, installed at version: 2023.08
2 09:26:37.320167 start: 0 validate
3 09:26:37.320297 Start time: 2023-10-20 09:26:37.320288+00:00 (UTC)
4 09:26:37.320412 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:26:37.320541 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:26:37.588830 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:26:37.589127 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:26:58.357416 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:26:58.357588 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:26:58.626774 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:26:58.627541 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:26:59.162061 validate duration: 21.84
14 09:26:59.163414 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:26:59.164063 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:26:59.164573 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:26:59.165189 Not decompressing ramdisk as can be used compressed.
18 09:26:59.165683 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 09:26:59.166047 saving as /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/ramdisk/rootfs.cpio.gz
20 09:26:59.166431 total size: 34390042 (32 MB)
21 09:27:02.686475 progress 0 % (0 MB)
22 09:27:02.696175 progress 5 % (1 MB)
23 09:27:02.705689 progress 10 % (3 MB)
24 09:27:02.715083 progress 15 % (4 MB)
25 09:27:02.724452 progress 20 % (6 MB)
26 09:27:02.733813 progress 25 % (8 MB)
27 09:27:02.743042 progress 30 % (9 MB)
28 09:27:02.752268 progress 35 % (11 MB)
29 09:27:02.761329 progress 40 % (13 MB)
30 09:27:02.770732 progress 45 % (14 MB)
31 09:27:02.779705 progress 50 % (16 MB)
32 09:27:02.788813 progress 55 % (18 MB)
33 09:27:02.797795 progress 60 % (19 MB)
34 09:27:02.806897 progress 65 % (21 MB)
35 09:27:02.815891 progress 70 % (22 MB)
36 09:27:02.824955 progress 75 % (24 MB)
37 09:27:02.833930 progress 80 % (26 MB)
38 09:27:02.843087 progress 85 % (27 MB)
39 09:27:02.852051 progress 90 % (29 MB)
40 09:27:02.861039 progress 95 % (31 MB)
41 09:27:02.869713 progress 100 % (32 MB)
42 09:27:02.869901 32 MB downloaded in 3.70 s (8.86 MB/s)
43 09:27:02.870062 end: 1.1.1 http-download (duration 00:00:04) [common]
45 09:27:02.870302 end: 1.1 download-retry (duration 00:00:04) [common]
46 09:27:02.870389 start: 1.2 download-retry (timeout 00:09:56) [common]
47 09:27:02.870474 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 09:27:02.870617 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:27:02.870690 saving as /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/kernel/Image
50 09:27:02.870753 total size: 49236480 (46 MB)
51 09:27:02.870815 No compression specified
52 09:27:02.871946 progress 0 % (0 MB)
53 09:27:02.884993 progress 5 % (2 MB)
54 09:27:02.897842 progress 10 % (4 MB)
55 09:27:02.910721 progress 15 % (7 MB)
56 09:27:02.923703 progress 20 % (9 MB)
57 09:27:02.936563 progress 25 % (11 MB)
58 09:27:02.949483 progress 30 % (14 MB)
59 09:27:02.962421 progress 35 % (16 MB)
60 09:27:02.975527 progress 40 % (18 MB)
61 09:27:02.988365 progress 45 % (21 MB)
62 09:27:03.001382 progress 50 % (23 MB)
63 09:27:03.014415 progress 55 % (25 MB)
64 09:27:03.027475 progress 60 % (28 MB)
65 09:27:03.040437 progress 65 % (30 MB)
66 09:27:03.053327 progress 70 % (32 MB)
67 09:27:03.066189 progress 75 % (35 MB)
68 09:27:03.079292 progress 80 % (37 MB)
69 09:27:03.092099 progress 85 % (39 MB)
70 09:27:03.105057 progress 90 % (42 MB)
71 09:27:03.118058 progress 95 % (44 MB)
72 09:27:03.130844 progress 100 % (46 MB)
73 09:27:03.131081 46 MB downloaded in 0.26 s (180.37 MB/s)
74 09:27:03.131236 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:27:03.131520 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:27:03.131610 start: 1.3 download-retry (timeout 00:09:56) [common]
78 09:27:03.131698 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 09:27:03.131843 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:27:03.131914 saving as /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/dtb/mt8192-asurada-spherion-r0.dtb
81 09:27:03.131976 total size: 47278 (0 MB)
82 09:27:03.132038 No compression specified
83 09:27:03.133171 progress 69 % (0 MB)
84 09:27:03.133453 progress 100 % (0 MB)
85 09:27:03.133610 0 MB downloaded in 0.00 s (27.64 MB/s)
86 09:27:03.133733 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:27:03.133955 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:27:03.134041 start: 1.4 download-retry (timeout 00:09:56) [common]
90 09:27:03.134124 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 09:27:03.134243 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:27:03.134310 saving as /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/modules/modules.tar
93 09:27:03.134371 total size: 8614716 (8 MB)
94 09:27:03.134431 Using unxz to decompress xz
95 09:27:03.138767 progress 0 % (0 MB)
96 09:27:03.159860 progress 5 % (0 MB)
97 09:27:03.193344 progress 10 % (0 MB)
98 09:27:03.223848 progress 15 % (1 MB)
99 09:27:03.249373 progress 20 % (1 MB)
100 09:27:03.275031 progress 25 % (2 MB)
101 09:27:03.302533 progress 30 % (2 MB)
102 09:27:03.330224 progress 35 % (2 MB)
103 09:27:03.354910 progress 40 % (3 MB)
104 09:27:03.380378 progress 45 % (3 MB)
105 09:27:03.407564 progress 50 % (4 MB)
106 09:27:03.433119 progress 55 % (4 MB)
107 09:27:03.458807 progress 60 % (4 MB)
108 09:27:03.485449 progress 65 % (5 MB)
109 09:27:03.513098 progress 70 % (5 MB)
110 09:27:03.537396 progress 75 % (6 MB)
111 09:27:03.564921 progress 80 % (6 MB)
112 09:27:03.591495 progress 85 % (7 MB)
113 09:27:03.617137 progress 90 % (7 MB)
114 09:27:03.647755 progress 95 % (7 MB)
115 09:27:03.676603 progress 100 % (8 MB)
116 09:27:03.683032 8 MB downloaded in 0.55 s (14.97 MB/s)
117 09:27:03.683295 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:27:03.683604 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:27:03.683720 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 09:27:03.683825 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 09:27:03.683906 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:27:03.683993 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 09:27:03.684253 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4
125 09:27:03.684433 makedir: /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin
126 09:27:03.684544 makedir: /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/tests
127 09:27:03.684679 makedir: /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/results
128 09:27:03.684831 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-add-keys
129 09:27:03.685016 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-add-sources
130 09:27:03.685182 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-background-process-start
131 09:27:03.685316 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-background-process-stop
132 09:27:03.685444 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-common-functions
133 09:27:03.685580 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-echo-ipv4
134 09:27:03.685754 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-install-packages
135 09:27:03.685916 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-installed-packages
136 09:27:03.686082 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-os-build
137 09:27:03.686248 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-probe-channel
138 09:27:03.686408 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-probe-ip
139 09:27:03.686555 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-target-ip
140 09:27:03.686682 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-target-mac
141 09:27:03.686810 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-target-storage
142 09:27:03.686944 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-case
143 09:27:03.687078 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-event
144 09:27:03.687207 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-feedback
145 09:27:03.687334 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-raise
146 09:27:03.687473 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-reference
147 09:27:03.687611 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-runner
148 09:27:03.687775 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-set
149 09:27:03.687937 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-test-shell
150 09:27:03.688099 Updating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-install-packages (oe)
151 09:27:03.688297 Updating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/bin/lava-installed-packages (oe)
152 09:27:03.688425 Creating /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/environment
153 09:27:03.688530 LAVA metadata
154 09:27:03.688604 - LAVA_JOB_ID=11826783
155 09:27:03.688667 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:27:03.688768 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 09:27:03.688835 skipped lava-vland-overlay
158 09:27:03.688909 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:27:03.689001 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 09:27:03.689065 skipped lava-multinode-overlay
161 09:27:03.689141 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:27:03.689228 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 09:27:03.689305 Loading test definitions
164 09:27:03.689397 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 09:27:03.689474 Using /lava-11826783 at stage 0
166 09:27:03.689929 uuid=11826783_1.5.2.3.1 testdef=None
167 09:27:03.690066 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:27:03.690186 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 09:27:03.690762 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:27:03.690998 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 09:27:03.691637 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:27:03.691888 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 09:27:03.692578 runner path: /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/0/tests/0_cros-ec test_uuid 11826783_1.5.2.3.1
176 09:27:03.692735 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:27:03.692951 Creating lava-test-runner.conf files
179 09:27:03.693014 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826783/lava-overlay-5ooh9xa4/lava-11826783/0 for stage 0
180 09:27:03.693103 - 0_cros-ec
181 09:27:03.693201 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:27:03.693288 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 09:27:03.700757 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:27:03.700924 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 09:27:03.701016 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:27:03.701102 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:27:03.701198 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 09:27:04.730497 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:27:04.730904 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
190 09:27:04.731023 extracting modules file /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826783/extract-overlay-ramdisk-l9d7fpbk/ramdisk
191 09:27:04.987935 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:27:04.988107 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
193 09:27:04.988206 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826783/compress-overlay-eom6n4lh/overlay-1.5.2.4.tar.gz to ramdisk
194 09:27:04.988274 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826783/compress-overlay-eom6n4lh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826783/extract-overlay-ramdisk-l9d7fpbk/ramdisk
195 09:27:04.995313 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:27:04.995566 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
197 09:27:04.995662 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:27:04.995751 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
199 09:27:04.995833 Building ramdisk /var/lib/lava/dispatcher/tmp/11826783/extract-overlay-ramdisk-l9d7fpbk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826783/extract-overlay-ramdisk-l9d7fpbk/ramdisk
200 09:27:05.786010 >> 271036 blocks
201 09:27:10.653430 rename /var/lib/lava/dispatcher/tmp/11826783/extract-overlay-ramdisk-l9d7fpbk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/ramdisk/ramdisk.cpio.gz
202 09:27:10.653910 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 09:27:10.654038 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 09:27:10.654164 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 09:27:10.654267 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/kernel/Image'
206 09:27:23.837111 Returned 0 in 13 seconds
207 09:27:23.937815 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/kernel/image.itb
208 09:27:24.631100 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:27:24.631590 output: Created: Fri Oct 20 10:27:24 2023
210 09:27:24.631703 output: Image 0 (kernel-1)
211 09:27:24.631801 output: Description:
212 09:27:24.631897 output: Created: Fri Oct 20 10:27:24 2023
213 09:27:24.631994 output: Type: Kernel Image
214 09:27:24.632091 output: Compression: lzma compressed
215 09:27:24.632183 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
216 09:27:24.632279 output: Architecture: AArch64
217 09:27:24.632387 output: OS: Linux
218 09:27:24.632479 output: Load Address: 0x00000000
219 09:27:24.632571 output: Entry Point: 0x00000000
220 09:27:24.632658 output: Hash algo: crc32
221 09:27:24.632744 output: Hash value: 05d3904e
222 09:27:24.632829 output: Image 1 (fdt-1)
223 09:27:24.632917 output: Description: mt8192-asurada-spherion-r0
224 09:27:24.633003 output: Created: Fri Oct 20 10:27:24 2023
225 09:27:24.633088 output: Type: Flat Device Tree
226 09:27:24.633173 output: Compression: uncompressed
227 09:27:24.633257 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:27:24.633342 output: Architecture: AArch64
229 09:27:24.633426 output: Hash algo: crc32
230 09:27:24.633511 output: Hash value: cc4352de
231 09:27:24.633594 output: Image 2 (ramdisk-1)
232 09:27:24.633678 output: Description: unavailable
233 09:27:24.633761 output: Created: Fri Oct 20 10:27:24 2023
234 09:27:24.633843 output: Type: RAMDisk Image
235 09:27:24.633927 output: Compression: Unknown Compression
236 09:27:24.634010 output: Data Size: 47518084 Bytes = 46404.38 KiB = 45.32 MiB
237 09:27:24.634097 output: Architecture: AArch64
238 09:27:24.634183 output: OS: Linux
239 09:27:24.634265 output: Load Address: unavailable
240 09:27:24.634349 output: Entry Point: unavailable
241 09:27:24.634433 output: Hash algo: crc32
242 09:27:24.634517 output: Hash value: 5470a40d
243 09:27:24.634603 output: Default Configuration: 'conf-1'
244 09:27:24.634688 output: Configuration 0 (conf-1)
245 09:27:24.634771 output: Description: mt8192-asurada-spherion-r0
246 09:27:24.634856 output: Kernel: kernel-1
247 09:27:24.634941 output: Init Ramdisk: ramdisk-1
248 09:27:24.635025 output: FDT: fdt-1
249 09:27:24.635108 output: Loadables: kernel-1
250 09:27:24.635193 output:
251 09:27:24.635519 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:27:24.635665 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:27:24.635858 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 09:27:24.636021 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 09:27:24.636134 No LXC device requested
256 09:27:24.636254 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:27:24.636381 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 09:27:24.636495 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:27:24.636598 Checking files for TFTP limit of 4294967296 bytes.
260 09:27:24.637301 end: 1 tftp-deploy (duration 00:00:25) [common]
261 09:27:24.637441 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:27:24.637565 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:27:24.637738 substitutions:
264 09:27:24.637852 - {DTB}: 11826783/tftp-deploy-fnbcpo20/dtb/mt8192-asurada-spherion-r0.dtb
265 09:27:24.637951 - {INITRD}: 11826783/tftp-deploy-fnbcpo20/ramdisk/ramdisk.cpio.gz
266 09:27:24.638041 - {KERNEL}: 11826783/tftp-deploy-fnbcpo20/kernel/Image
267 09:27:24.638132 - {LAVA_MAC}: None
268 09:27:24.638220 - {PRESEED_CONFIG}: None
269 09:27:24.638306 - {PRESEED_LOCAL}: None
270 09:27:24.638391 - {RAMDISK}: 11826783/tftp-deploy-fnbcpo20/ramdisk/ramdisk.cpio.gz
271 09:27:24.638477 - {ROOT_PART}: None
272 09:27:24.638562 - {ROOT}: None
273 09:27:24.638658 - {SERVER_IP}: 192.168.201.1
274 09:27:24.638746 - {TEE}: None
275 09:27:24.638862 Parsed boot commands:
276 09:27:24.638968 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:27:24.639229 Parsed boot commands: tftpboot 192.168.201.1 11826783/tftp-deploy-fnbcpo20/kernel/image.itb 11826783/tftp-deploy-fnbcpo20/kernel/cmdline
278 09:27:24.639360 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:27:24.639520 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:27:24.639654 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:27:24.639791 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:27:24.639949 Not connected, no need to disconnect.
283 09:27:24.640064 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:27:24.640186 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:27:24.640289 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 09:27:24.645239 Setting prompt string to ['lava-test: # ']
287 09:27:24.645736 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:27:24.646002 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:27:24.646182 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:27:24.646347 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:27:24.646688 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 09:27:29.786175 >> Command sent successfully.
293 09:27:29.788789 Returned 0 in 5 seconds
294 09:27:29.889230 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:27:29.889766 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:27:29.889940 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:27:29.890088 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:27:29.890223 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:27:29.890345 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:27:29.890795 [Enter `^Ec?' for help]
302 09:27:30.064294
303 09:27:30.064472
304 09:27:30.064583 F0: 102B 0000
305 09:27:30.064684
306 09:27:30.064781 F3: 1001 0000 [0200]
307 09:27:30.064874
308 09:27:30.067766 F3: 1001 0000
309 09:27:30.067878
310 09:27:30.067977 F7: 102D 0000
311 09:27:30.068070
312 09:27:30.068161 F1: 0000 0000
313 09:27:30.068251
314 09:27:30.071494 V0: 0000 0000 [0001]
315 09:27:30.071606
316 09:27:30.071701 00: 0007 8000
317 09:27:30.071798
318 09:27:30.075154 01: 0000 0000
319 09:27:30.075266
320 09:27:30.075364 BP: 0C00 0209 [0000]
321 09:27:30.075502
322 09:27:30.075597 G0: 1182 0000
323 09:27:30.079192
324 09:27:30.079300 EC: 0000 0021 [4000]
325 09:27:30.079425
326 09:27:30.083059 S7: 0000 0000 [0000]
327 09:27:30.083168
328 09:27:30.083265 CC: 0000 0000 [0001]
329 09:27:30.083360
330 09:27:30.086116 T0: 0000 0040 [010F]
331 09:27:30.086226
332 09:27:30.086322 Jump to BL
333 09:27:30.086414
334 09:27:30.110848
335 09:27:30.110972
336 09:27:30.111070
337 09:27:30.118250 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:27:30.121100 ARM64: Exception handlers installed.
339 09:27:30.124735 ARM64: Testing exception
340 09:27:30.128431 ARM64: Done test exception
341 09:27:30.135942 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:27:30.146555 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:27:30.152854 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:27:30.163315 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:27:30.169994 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:27:30.176315 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:27:30.187598 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:27:30.194691 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:27:30.213942 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:27:30.216983 WDT: Last reset was cold boot
351 09:27:30.220012 SPI1(PAD0) initialized at 2873684 Hz
352 09:27:30.223689 SPI5(PAD0) initialized at 992727 Hz
353 09:27:30.227247 VBOOT: Loading verstage.
354 09:27:30.233977 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:27:30.237420 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:27:30.240399 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:27:30.243866 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:27:30.251193 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:27:30.257933 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:27:30.268750 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 09:27:30.268870
362 09:27:30.268975
363 09:27:30.278522 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:27:30.282040 ARM64: Exception handlers installed.
365 09:27:30.285193 ARM64: Testing exception
366 09:27:30.285304 ARM64: Done test exception
367 09:27:30.292912 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:27:30.296396 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:27:30.309509 Probing TPM: . done!
370 09:27:30.309621 TPM ready after 0 ms
371 09:27:30.316094 Connected to device vid:did:rid of 1ae0:0028:00
372 09:27:30.365316 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 09:27:30.365421 Initialized TPM device CR50 revision 0
374 09:27:30.377450 tlcl_send_startup: Startup return code is 0
375 09:27:30.377538 TPM: setup succeeded
376 09:27:30.388958 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:27:30.397966 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:27:30.409278 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:27:30.418322 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:27:30.421679 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:27:30.425669 in-header: 03 07 00 00 08 00 00 00
382 09:27:30.429441 in-data: aa e4 47 04 13 02 00 00
383 09:27:30.432999 Chrome EC: UHEPI supported
384 09:27:30.440408 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:27:30.443971 in-header: 03 9d 00 00 08 00 00 00
386 09:27:30.447581 in-data: 10 20 20 08 00 00 00 00
387 09:27:30.447669 Phase 1
388 09:27:30.451971 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:27:30.458959 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:27:30.462630 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:27:30.466879 Recovery requested (1009000e)
392 09:27:30.470575 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:27:30.478922 tlcl_extend: response is 0
394 09:27:30.488730 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:27:30.492615 tlcl_extend: response is 0
396 09:27:30.499034 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:27:30.520369 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 09:27:30.527397 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 09:27:30.527572
400 09:27:30.527662
401 09:27:30.535264 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:27:30.538674 ARM64: Exception handlers installed.
403 09:27:30.542271 ARM64: Testing exception
404 09:27:30.545960 ARM64: Done test exception
405 09:27:30.566002 pmic_efuse_setting: Set efuses in 11 msecs
406 09:27:30.569577 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:27:30.573470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:27:30.580383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:27:30.584093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:27:30.587851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:27:30.595750 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:27:30.599006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:27:30.602970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:27:30.606984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:27:30.613129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:27:30.616495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:27:30.623200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:27:30.626960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:27:30.629765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:27:30.636707 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:27:30.643201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:27:30.650146 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:27:30.653240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:27:30.660204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:27:30.664546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:27:30.672049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:27:30.676158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:27:30.682645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:27:30.689073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:27:30.693096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:27:30.699728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:27:30.703351 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:27:30.710109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:27:30.713441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:27:30.720470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:27:30.724165 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:27:30.731330 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:27:30.734973 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:27:30.738834 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:27:30.746049 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:27:30.749475 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:27:30.753655 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:27:30.760278 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:27:30.763308 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:27:30.766907 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:27:30.773458 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:27:30.776840 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:27:30.780114 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:27:30.786862 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:27:30.790399 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:27:30.793401 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:27:30.800277 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:27:30.803513 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:27:30.807127 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:27:30.813469 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:27:30.817144 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:27:30.820613 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:27:30.826804 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:27:30.836787 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:27:30.840336 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:27:30.850204 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:27:30.856937 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:27:30.863666 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:27:30.866608 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:27:30.870464 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:27:30.878158 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2c
467 09:27:30.884758 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:27:30.887803 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 09:27:30.891311 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:27:30.902204 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 09:27:30.905783 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 09:27:30.912257 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 09:27:30.915608 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 09:27:30.919167 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 09:27:30.922187 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 09:27:30.925670 ADC[4]: Raw value=898890 ID=7
477 09:27:30.929103 ADC[3]: Raw value=213070 ID=1
478 09:27:30.932457 RAM Code: 0x71
479 09:27:30.935318 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 09:27:30.938825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 09:27:30.949469 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 09:27:30.956040 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 09:27:30.959718 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 09:27:30.963094 in-header: 03 07 00 00 08 00 00 00
485 09:27:30.966175 in-data: aa e4 47 04 13 02 00 00
486 09:27:30.966260 Chrome EC: UHEPI supported
487 09:27:30.973412 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 09:27:30.977546 in-header: 03 d5 00 00 08 00 00 00
489 09:27:30.981286 in-data: 98 20 60 08 00 00 00 00
490 09:27:30.984917 MRC: failed to locate region type 0.
491 09:27:30.991991 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 09:27:30.995035 DRAM-K: Running full calibration
493 09:27:31.002285 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 09:27:31.002372 header.status = 0x0
495 09:27:31.005957 header.version = 0x6 (expected: 0x6)
496 09:27:31.009427 header.size = 0xd00 (expected: 0xd00)
497 09:27:31.009511 header.flags = 0x0
498 09:27:31.015713 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 09:27:31.034301 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
500 09:27:31.041718 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 09:27:31.044407 dram_init: ddr_geometry: 2
502 09:27:31.047851 [EMI] MDL number = 2
503 09:27:31.047935 [EMI] Get MDL freq = 0
504 09:27:31.051503 dram_init: ddr_type: 0
505 09:27:31.051587 is_discrete_lpddr4: 1
506 09:27:31.054567 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 09:27:31.054651
508 09:27:31.054717
509 09:27:31.057719 [Bian_co] ETT version 0.0.0.1
510 09:27:31.064299 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 09:27:31.064383
512 09:27:31.067734 dramc_set_vcore_voltage set vcore to 650000
513 09:27:31.071322 Read voltage for 800, 4
514 09:27:31.071414 Vio18 = 0
515 09:27:31.071482 Vcore = 650000
516 09:27:31.071545 Vdram = 0
517 09:27:31.074250 Vddq = 0
518 09:27:31.074333 Vmddr = 0
519 09:27:31.077902 dram_init: config_dvfs: 1
520 09:27:31.080936 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 09:27:31.088328 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 09:27:31.091177 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 09:27:31.094640 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 09:27:31.097651 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 09:27:31.101252 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 09:27:31.104589 MEM_TYPE=3, freq_sel=18
527 09:27:31.108217 sv_algorithm_assistance_LP4_1600
528 09:27:31.111047 ============ PULL DRAM RESETB DOWN ============
529 09:27:31.114669 ========== PULL DRAM RESETB DOWN end =========
530 09:27:31.121113 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 09:27:31.124682 ===================================
532 09:27:31.127976 LPDDR4 DRAM CONFIGURATION
533 09:27:31.131257 ===================================
534 09:27:31.131341 EX_ROW_EN[0] = 0x0
535 09:27:31.134348 EX_ROW_EN[1] = 0x0
536 09:27:31.134432 LP4Y_EN = 0x0
537 09:27:31.137834 WORK_FSP = 0x0
538 09:27:31.137916 WL = 0x2
539 09:27:31.140970 RL = 0x2
540 09:27:31.141054 BL = 0x2
541 09:27:31.145021 RPST = 0x0
542 09:27:31.145105 RD_PRE = 0x0
543 09:27:31.148138 WR_PRE = 0x1
544 09:27:31.148221 WR_PST = 0x0
545 09:27:31.151313 DBI_WR = 0x0
546 09:27:31.151460 DBI_RD = 0x0
547 09:27:31.154331 OTF = 0x1
548 09:27:31.157592 ===================================
549 09:27:31.160900 ===================================
550 09:27:31.160984 ANA top config
551 09:27:31.164578 ===================================
552 09:27:31.167759 DLL_ASYNC_EN = 0
553 09:27:31.171087 ALL_SLAVE_EN = 1
554 09:27:31.174431 NEW_RANK_MODE = 1
555 09:27:31.174516 DLL_IDLE_MODE = 1
556 09:27:31.177650 LP45_APHY_COMB_EN = 1
557 09:27:31.181007 TX_ODT_DIS = 1
558 09:27:31.184579 NEW_8X_MODE = 1
559 09:27:31.187581 ===================================
560 09:27:31.190959 ===================================
561 09:27:31.194229 data_rate = 1600
562 09:27:31.194313 CKR = 1
563 09:27:31.197628 DQ_P2S_RATIO = 8
564 09:27:31.201246 ===================================
565 09:27:31.204863 CA_P2S_RATIO = 8
566 09:27:31.207594 DQ_CA_OPEN = 0
567 09:27:31.211048 DQ_SEMI_OPEN = 0
568 09:27:31.214920 CA_SEMI_OPEN = 0
569 09:27:31.215254 CA_FULL_RATE = 0
570 09:27:31.217888 DQ_CKDIV4_EN = 1
571 09:27:31.221025 CA_CKDIV4_EN = 1
572 09:27:31.224892 CA_PREDIV_EN = 0
573 09:27:31.228400 PH8_DLY = 0
574 09:27:31.228595 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 09:27:31.231280 DQ_AAMCK_DIV = 4
576 09:27:31.234635 CA_AAMCK_DIV = 4
577 09:27:31.238372 CA_ADMCK_DIV = 4
578 09:27:31.241286 DQ_TRACK_CA_EN = 0
579 09:27:31.245271 CA_PICK = 800
580 09:27:31.245455 CA_MCKIO = 800
581 09:27:31.248109 MCKIO_SEMI = 0
582 09:27:31.251520 PLL_FREQ = 3068
583 09:27:31.255236 DQ_UI_PI_RATIO = 32
584 09:27:31.259257 CA_UI_PI_RATIO = 0
585 09:27:31.263060 ===================================
586 09:27:31.263148 ===================================
587 09:27:31.267050 memory_type:LPDDR4
588 09:27:31.270588 GP_NUM : 10
589 09:27:31.270672 SRAM_EN : 1
590 09:27:31.274260 MD32_EN : 0
591 09:27:31.274347 ===================================
592 09:27:31.277732 [ANA_INIT] >>>>>>>>>>>>>>
593 09:27:31.281776 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 09:27:31.285638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 09:27:31.288968 ===================================
596 09:27:31.293289 data_rate = 1600,PCW = 0X7600
597 09:27:31.293375 ===================================
598 09:27:31.296877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 09:27:31.304501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 09:27:31.308222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 09:27:31.311738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 09:27:31.315190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 09:27:31.318702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 09:27:31.322982 [ANA_INIT] flow start
605 09:27:31.323068 [ANA_INIT] PLL >>>>>>>>
606 09:27:31.326566 [ANA_INIT] PLL <<<<<<<<
607 09:27:31.330014 [ANA_INIT] MIDPI >>>>>>>>
608 09:27:31.330099 [ANA_INIT] MIDPI <<<<<<<<
609 09:27:31.333473 [ANA_INIT] DLL >>>>>>>>
610 09:27:31.337720 [ANA_INIT] flow end
611 09:27:31.341187 ============ LP4 DIFF to SE enter ============
612 09:27:31.344895 ============ LP4 DIFF to SE exit ============
613 09:27:31.344982 [ANA_INIT] <<<<<<<<<<<<<
614 09:27:31.348942 [Flow] Enable top DCM control >>>>>
615 09:27:31.352752 [Flow] Enable top DCM control <<<<<
616 09:27:31.356280 Enable DLL master slave shuffle
617 09:27:31.360142 ==============================================================
618 09:27:31.363780 Gating Mode config
619 09:27:31.367337 ==============================================================
620 09:27:31.371124 Config description:
621 09:27:31.378311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 09:27:31.385284 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 09:27:31.392171 SELPH_MODE 0: By rank 1: By Phase
624 09:27:31.395613 ==============================================================
625 09:27:31.398956 GAT_TRACK_EN = 1
626 09:27:31.402431 RX_GATING_MODE = 2
627 09:27:31.405786 RX_GATING_TRACK_MODE = 2
628 09:27:31.409024 SELPH_MODE = 1
629 09:27:31.412313 PICG_EARLY_EN = 1
630 09:27:31.415874 VALID_LAT_VALUE = 1
631 09:27:31.419351 ==============================================================
632 09:27:31.422354 Enter into Gating configuration >>>>
633 09:27:31.426027 Exit from Gating configuration <<<<
634 09:27:31.428796 Enter into DVFS_PRE_config >>>>>
635 09:27:31.442334 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 09:27:31.445937 Exit from DVFS_PRE_config <<<<<
637 09:27:31.449295 Enter into PICG configuration >>>>
638 09:27:31.452559 Exit from PICG configuration <<<<
639 09:27:31.452642 [RX_INPUT] configuration >>>>>
640 09:27:31.455862 [RX_INPUT] configuration <<<<<
641 09:27:31.462570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 09:27:31.465677 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 09:27:31.472109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 09:27:31.478741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 09:27:31.485995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 09:27:31.492305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 09:27:31.495915 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 09:27:31.498860 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 09:27:31.502214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 09:27:31.508958 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 09:27:31.512529 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 09:27:31.515999 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 09:27:31.519045 ===================================
654 09:27:31.522531 LPDDR4 DRAM CONFIGURATION
655 09:27:31.525904 ===================================
656 09:27:31.526001 EX_ROW_EN[0] = 0x0
657 09:27:31.528965 EX_ROW_EN[1] = 0x0
658 09:27:31.532560 LP4Y_EN = 0x0
659 09:27:31.532641 WORK_FSP = 0x0
660 09:27:31.535616 WL = 0x2
661 09:27:31.535697 RL = 0x2
662 09:27:31.539346 BL = 0x2
663 09:27:31.539481 RPST = 0x0
664 09:27:31.542654 RD_PRE = 0x0
665 09:27:31.542735 WR_PRE = 0x1
666 09:27:31.545678 WR_PST = 0x0
667 09:27:31.545760 DBI_WR = 0x0
668 09:27:31.549127 DBI_RD = 0x0
669 09:27:31.549208 OTF = 0x1
670 09:27:31.552810 ===================================
671 09:27:31.555682 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 09:27:31.562360 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 09:27:31.566047 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 09:27:31.569047 ===================================
675 09:27:31.572429 LPDDR4 DRAM CONFIGURATION
676 09:27:31.575815 ===================================
677 09:27:31.575897 EX_ROW_EN[0] = 0x10
678 09:27:31.579323 EX_ROW_EN[1] = 0x0
679 09:27:31.579444 LP4Y_EN = 0x0
680 09:27:31.582196 WORK_FSP = 0x0
681 09:27:31.585685 WL = 0x2
682 09:27:31.585775 RL = 0x2
683 09:27:31.589102 BL = 0x2
684 09:27:31.589209 RPST = 0x0
685 09:27:31.592181 RD_PRE = 0x0
686 09:27:31.592264 WR_PRE = 0x1
687 09:27:31.595970 WR_PST = 0x0
688 09:27:31.596137 DBI_WR = 0x0
689 09:27:31.598933 DBI_RD = 0x0
690 09:27:31.599031 OTF = 0x1
691 09:27:31.602401 ===================================
692 09:27:31.609236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 09:27:31.612672 nWR fixed to 40
694 09:27:31.616370 [ModeRegInit_LP4] CH0 RK0
695 09:27:31.616454 [ModeRegInit_LP4] CH0 RK1
696 09:27:31.619381 [ModeRegInit_LP4] CH1 RK0
697 09:27:31.623104 [ModeRegInit_LP4] CH1 RK1
698 09:27:31.623187 match AC timing 13
699 09:27:31.629682 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 09:27:31.633023 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 09:27:31.636485 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 09:27:31.643119 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 09:27:31.646532 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 09:27:31.646616 [EMI DOE] emi_dcm 0
705 09:27:31.653165 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 09:27:31.653262 ==
707 09:27:31.656491 Dram Type= 6, Freq= 0, CH_0, rank 0
708 09:27:31.660001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 09:27:31.660134 ==
710 09:27:31.666305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 09:27:31.669578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 09:27:31.680455 [CA 0] Center 38 (7~69) winsize 63
713 09:27:31.684129 [CA 1] Center 37 (7~68) winsize 62
714 09:27:31.687064 [CA 2] Center 35 (5~66) winsize 62
715 09:27:31.690472 [CA 3] Center 35 (5~66) winsize 62
716 09:27:31.693379 [CA 4] Center 34 (4~65) winsize 62
717 09:27:31.697186 [CA 5] Center 33 (3~64) winsize 62
718 09:27:31.697315
719 09:27:31.700580 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 09:27:31.700685
721 09:27:31.703817 [CATrainingPosCal] consider 1 rank data
722 09:27:31.707298 u2DelayCellTimex100 = 270/100 ps
723 09:27:31.710390 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
724 09:27:31.713421 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
725 09:27:31.720113 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
726 09:27:31.723998 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
727 09:27:31.727157 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
728 09:27:31.730209 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
729 09:27:31.730317
730 09:27:31.733904 CA PerBit enable=1, Macro0, CA PI delay=33
731 09:27:31.734010
732 09:27:31.737098 [CBTSetCACLKResult] CA Dly = 33
733 09:27:31.737213 CS Dly: 6 (0~37)
734 09:27:31.740228 ==
735 09:27:31.743576 Dram Type= 6, Freq= 0, CH_0, rank 1
736 09:27:31.746794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 09:27:31.746880 ==
738 09:27:31.750160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 09:27:31.757110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 09:27:31.766711 [CA 0] Center 38 (7~69) winsize 63
741 09:27:31.770319 [CA 1] Center 37 (7~68) winsize 62
742 09:27:31.773275 [CA 2] Center 35 (5~66) winsize 62
743 09:27:31.776674 [CA 3] Center 35 (5~66) winsize 62
744 09:27:31.780051 [CA 4] Center 34 (4~65) winsize 62
745 09:27:31.783705 [CA 5] Center 34 (4~65) winsize 62
746 09:27:31.783791
747 09:27:31.787044 [CmdBusTrainingLP45] Vref(ca) range 1: 30
748 09:27:31.787128
749 09:27:31.790500 [CATrainingPosCal] consider 2 rank data
750 09:27:31.794061 u2DelayCellTimex100 = 270/100 ps
751 09:27:31.798085 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 09:27:31.801716 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 09:27:31.805157 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 09:27:31.808713 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 09:27:31.812731 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 09:27:31.816228 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 09:27:31.816313
758 09:27:31.819881 CA PerBit enable=1, Macro0, CA PI delay=34
759 09:27:31.819966
760 09:27:31.823691 [CBTSetCACLKResult] CA Dly = 34
761 09:27:31.823815 CS Dly: 6 (0~37)
762 09:27:31.823917
763 09:27:31.827346 ----->DramcWriteLeveling(PI) begin...
764 09:27:31.827471 ==
765 09:27:31.830382 Dram Type= 6, Freq= 0, CH_0, rank 0
766 09:27:31.837732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 09:27:31.837818 ==
768 09:27:31.837885 Write leveling (Byte 0): 31 => 31
769 09:27:31.841214 Write leveling (Byte 1): 30 => 30
770 09:27:31.844912 DramcWriteLeveling(PI) end<-----
771 09:27:31.844996
772 09:27:31.845064 ==
773 09:27:31.849154 Dram Type= 6, Freq= 0, CH_0, rank 0
774 09:27:31.852538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 09:27:31.852623 ==
776 09:27:31.856095 [Gating] SW mode calibration
777 09:27:31.863415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 09:27:31.866968 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 09:27:31.874308 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 09:27:31.878053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 09:27:31.881424 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 09:27:31.885033 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 09:27:31.889389 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 09:27:31.893391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 09:27:31.900949 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 09:27:31.904762 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 09:27:31.908128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 09:27:31.911616 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:27:31.916005 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:27:31.923239 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:27:31.926845 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:27:31.930469 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:27:31.934189 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:27:31.937812 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:27:31.941453 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:27:31.948718 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:27:31.952326 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
798 09:27:31.955874 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 09:27:31.959933 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:27:31.963591 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:27:31.970900 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:27:31.974857 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:27:31.977927 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:27:31.982090 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:27:31.985465 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
806 09:27:31.992938 0 9 12 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 1)
807 09:27:31.996603 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 09:27:31.999922 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 09:27:32.003913 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 09:27:32.007353 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 09:27:32.014665 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 09:27:32.018667 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 09:27:32.022560 0 10 8 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
814 09:27:32.025901 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
815 09:27:32.030090 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:27:32.033665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 09:27:32.040996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 09:27:32.045224 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:27:32.048159 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:27:32.052244 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:27:32.056088 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
822 09:27:32.062950 0 11 12 | B1->B0 | 3838 4343 | 0 0 | (0 0) (0 0)
823 09:27:32.067199 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 09:27:32.070682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 09:27:32.074214 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 09:27:32.078333 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 09:27:32.085675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 09:27:32.089324 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 09:27:32.092940 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:27:32.096999 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 09:27:32.100610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 09:27:32.104267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 09:27:32.111618 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 09:27:32.114910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 09:27:32.118015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 09:27:32.121448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:27:32.128258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:27:32.131377 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:27:32.134898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:27:32.141496 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:27:32.145092 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:27:32.148149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:27:32.154881 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:27:32.158591 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:27:32.161525 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 09:27:32.168691 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 09:27:32.168775 Total UI for P1: 0, mck2ui 16
848 09:27:32.174946 best dqsien dly found for B0: ( 0, 14, 8)
849 09:27:32.178576 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 09:27:32.181658 Total UI for P1: 0, mck2ui 16
851 09:27:32.185182 best dqsien dly found for B1: ( 0, 14, 12)
852 09:27:32.188444 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 09:27:32.191363 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 09:27:32.191497
855 09:27:32.195055 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 09:27:32.198469 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 09:27:32.201669 [Gating] SW calibration Done
858 09:27:32.201752 ==
859 09:27:32.204971 Dram Type= 6, Freq= 0, CH_0, rank 0
860 09:27:32.208507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 09:27:32.208590 ==
862 09:27:32.211682 RX Vref Scan: 0
863 09:27:32.211765
864 09:27:32.214730 RX Vref 0 -> 0, step: 1
865 09:27:32.214812
866 09:27:32.214883 RX Delay -130 -> 252, step: 16
867 09:27:32.221899 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 09:27:32.224965 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 09:27:32.228543 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 09:27:32.231309 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 09:27:32.234982 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 09:27:32.241753 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 09:27:32.244788 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 09:27:32.248460 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 09:27:32.251467 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
876 09:27:32.254518 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 09:27:32.261399 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 09:27:32.265101 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 09:27:32.268228 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 09:27:32.271393 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 09:27:32.278202 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 09:27:32.281308 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 09:27:32.281385 ==
884 09:27:32.284986 Dram Type= 6, Freq= 0, CH_0, rank 0
885 09:27:32.288582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 09:27:32.288658 ==
887 09:27:32.288739 DQS Delay:
888 09:27:32.291629 DQS0 = 0, DQS1 = 0
889 09:27:32.291714 DQM Delay:
890 09:27:32.295094 DQM0 = 82, DQM1 = 70
891 09:27:32.295197 DQ Delay:
892 09:27:32.298141 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 09:27:32.301730 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 09:27:32.304974 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
895 09:27:32.308287 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 09:27:32.308372
897 09:27:32.308457
898 09:27:32.308549 ==
899 09:27:32.311777 Dram Type= 6, Freq= 0, CH_0, rank 0
900 09:27:32.315136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 09:27:32.315219 ==
902 09:27:32.315318
903 09:27:32.315418
904 09:27:32.318888 TX Vref Scan disable
905 09:27:32.322233 == TX Byte 0 ==
906 09:27:32.325143 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
907 09:27:32.328498 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
908 09:27:32.331825 == TX Byte 1 ==
909 09:27:32.335178 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 09:27:32.338564 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 09:27:32.338641 ==
912 09:27:32.341761 Dram Type= 6, Freq= 0, CH_0, rank 0
913 09:27:32.345133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 09:27:32.348428 ==
915 09:27:32.359972 TX Vref=22, minBit 0, minWin=26, winSum=433
916 09:27:32.363503 TX Vref=24, minBit 1, minWin=27, winSum=441
917 09:27:32.366494 TX Vref=26, minBit 10, minWin=27, winSum=442
918 09:27:32.370063 TX Vref=28, minBit 0, minWin=27, winSum=443
919 09:27:32.373562 TX Vref=30, minBit 10, minWin=27, winSum=442
920 09:27:32.380069 TX Vref=32, minBit 4, minWin=27, winSum=440
921 09:27:32.383097 [TxChooseVref] Worse bit 0, Min win 27, Win sum 443, Final Vref 28
922 09:27:32.383181
923 09:27:32.386630 Final TX Range 1 Vref 28
924 09:27:32.386714
925 09:27:32.386815 ==
926 09:27:32.389619 Dram Type= 6, Freq= 0, CH_0, rank 0
927 09:27:32.393258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 09:27:32.396356 ==
929 09:27:32.396440
930 09:27:32.396542
931 09:27:32.396640 TX Vref Scan disable
932 09:27:32.400023 == TX Byte 0 ==
933 09:27:32.403672 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
934 09:27:32.407054 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
935 09:27:32.410161 == TX Byte 1 ==
936 09:27:32.413247 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 09:27:32.416881 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 09:27:32.420309
939 09:27:32.420392 [DATLAT]
940 09:27:32.420478 Freq=800, CH0 RK0
941 09:27:32.420558
942 09:27:32.423194 DATLAT Default: 0xa
943 09:27:32.423281 0, 0xFFFF, sum = 0
944 09:27:32.426462 1, 0xFFFF, sum = 0
945 09:27:32.426547 2, 0xFFFF, sum = 0
946 09:27:32.429987 3, 0xFFFF, sum = 0
947 09:27:32.430072 4, 0xFFFF, sum = 0
948 09:27:32.433296 5, 0xFFFF, sum = 0
949 09:27:32.436895 6, 0xFFFF, sum = 0
950 09:27:32.436999 7, 0xFFFF, sum = 0
951 09:27:32.439902 8, 0xFFFF, sum = 0
952 09:27:32.439987 9, 0x0, sum = 1
953 09:27:32.440073 10, 0x0, sum = 2
954 09:27:32.443195 11, 0x0, sum = 3
955 09:27:32.443279 12, 0x0, sum = 4
956 09:27:32.446656 best_step = 10
957 09:27:32.446743
958 09:27:32.446855 ==
959 09:27:32.450386 Dram Type= 6, Freq= 0, CH_0, rank 0
960 09:27:32.453424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 09:27:32.453508 ==
962 09:27:32.456616 RX Vref Scan: 1
963 09:27:32.456700
964 09:27:32.456795 Set Vref Range= 32 -> 127
965 09:27:32.460324
966 09:27:32.460408 RX Vref 32 -> 127, step: 1
967 09:27:32.460493
968 09:27:32.463581 RX Delay -111 -> 252, step: 8
969 09:27:32.463665
970 09:27:32.466846 Set Vref, RX VrefLevel [Byte0]: 32
971 09:27:32.469877 [Byte1]: 32
972 09:27:32.469961
973 09:27:32.473313 Set Vref, RX VrefLevel [Byte0]: 33
974 09:27:32.476599 [Byte1]: 33
975 09:27:32.480890
976 09:27:32.481023 Set Vref, RX VrefLevel [Byte0]: 34
977 09:27:32.484199 [Byte1]: 34
978 09:27:32.488442
979 09:27:32.488528 Set Vref, RX VrefLevel [Byte0]: 35
980 09:27:32.491430 [Byte1]: 35
981 09:27:32.495796
982 09:27:32.495877 Set Vref, RX VrefLevel [Byte0]: 36
983 09:27:32.499618 [Byte1]: 36
984 09:27:32.503796
985 09:27:32.503876 Set Vref, RX VrefLevel [Byte0]: 37
986 09:27:32.506932 [Byte1]: 37
987 09:27:32.511000
988 09:27:32.511080 Set Vref, RX VrefLevel [Byte0]: 38
989 09:27:32.514793 [Byte1]: 38
990 09:27:32.519214
991 09:27:32.522121 Set Vref, RX VrefLevel [Byte0]: 39
992 09:27:32.522203 [Byte1]: 39
993 09:27:32.526322
994 09:27:32.526403 Set Vref, RX VrefLevel [Byte0]: 40
995 09:27:32.530073 [Byte1]: 40
996 09:27:32.534175
997 09:27:32.534256 Set Vref, RX VrefLevel [Byte0]: 41
998 09:27:32.537768 [Byte1]: 41
999 09:27:32.542062
1000 09:27:32.542143 Set Vref, RX VrefLevel [Byte0]: 42
1001 09:27:32.545346 [Byte1]: 42
1002 09:27:32.549829
1003 09:27:32.549914 Set Vref, RX VrefLevel [Byte0]: 43
1004 09:27:32.552666 [Byte1]: 43
1005 09:27:32.557174
1006 09:27:32.557255 Set Vref, RX VrefLevel [Byte0]: 44
1007 09:27:32.560627 [Byte1]: 44
1008 09:27:32.565052
1009 09:27:32.565134 Set Vref, RX VrefLevel [Byte0]: 45
1010 09:27:32.567877 [Byte1]: 45
1011 09:27:32.572805
1012 09:27:32.572914 Set Vref, RX VrefLevel [Byte0]: 46
1013 09:27:32.575929 [Byte1]: 46
1014 09:27:32.580956
1015 09:27:32.581036 Set Vref, RX VrefLevel [Byte0]: 47
1016 09:27:32.583939 [Byte1]: 47
1017 09:27:32.587910
1018 09:27:32.587991 Set Vref, RX VrefLevel [Byte0]: 48
1019 09:27:32.591662 [Byte1]: 48
1020 09:27:32.595961
1021 09:27:32.596043 Set Vref, RX VrefLevel [Byte0]: 49
1022 09:27:32.598919 [Byte1]: 49
1023 09:27:32.603742
1024 09:27:32.603823 Set Vref, RX VrefLevel [Byte0]: 50
1025 09:27:32.606717 [Byte1]: 50
1026 09:27:32.610856
1027 09:27:32.610936 Set Vref, RX VrefLevel [Byte0]: 51
1028 09:27:32.613748 [Byte1]: 51
1029 09:27:32.618450
1030 09:27:32.618529 Set Vref, RX VrefLevel [Byte0]: 52
1031 09:27:32.621524 [Byte1]: 52
1032 09:27:32.625725
1033 09:27:32.625804 Set Vref, RX VrefLevel [Byte0]: 53
1034 09:27:32.629304 [Byte1]: 53
1035 09:27:32.633500
1036 09:27:32.633579 Set Vref, RX VrefLevel [Byte0]: 54
1037 09:27:32.637066 [Byte1]: 54
1038 09:27:32.641085
1039 09:27:32.641164 Set Vref, RX VrefLevel [Byte0]: 55
1040 09:27:32.644679 [Byte1]: 55
1041 09:27:32.648891
1042 09:27:32.648970 Set Vref, RX VrefLevel [Byte0]: 56
1043 09:27:32.652252 [Byte1]: 56
1044 09:27:32.656262
1045 09:27:32.656341 Set Vref, RX VrefLevel [Byte0]: 57
1046 09:27:32.660066 [Byte1]: 57
1047 09:27:32.664326
1048 09:27:32.664405 Set Vref, RX VrefLevel [Byte0]: 58
1049 09:27:32.667307 [Byte1]: 58
1050 09:27:32.672042
1051 09:27:32.672122 Set Vref, RX VrefLevel [Byte0]: 59
1052 09:27:32.674860 [Byte1]: 59
1053 09:27:32.679581
1054 09:27:32.679660 Set Vref, RX VrefLevel [Byte0]: 60
1055 09:27:32.682912 [Byte1]: 60
1056 09:27:32.686793
1057 09:27:32.686873 Set Vref, RX VrefLevel [Byte0]: 61
1058 09:27:32.690073 [Byte1]: 61
1059 09:27:32.695030
1060 09:27:32.695126 Set Vref, RX VrefLevel [Byte0]: 62
1061 09:27:32.698179 [Byte1]: 62
1062 09:27:32.702244
1063 09:27:32.702323 Set Vref, RX VrefLevel [Byte0]: 63
1064 09:27:32.705894 [Byte1]: 63
1065 09:27:32.709963
1066 09:27:32.710044 Set Vref, RX VrefLevel [Byte0]: 64
1067 09:27:32.713415 [Byte1]: 64
1068 09:27:32.717647
1069 09:27:32.717728 Set Vref, RX VrefLevel [Byte0]: 65
1070 09:27:32.721260 [Byte1]: 65
1071 09:27:32.725548
1072 09:27:32.725643 Set Vref, RX VrefLevel [Byte0]: 66
1073 09:27:32.728444 [Byte1]: 66
1074 09:27:32.732752
1075 09:27:32.732831 Set Vref, RX VrefLevel [Byte0]: 67
1076 09:27:32.736242 [Byte1]: 67
1077 09:27:32.740293
1078 09:27:32.740381 Set Vref, RX VrefLevel [Byte0]: 68
1079 09:27:32.744033 [Byte1]: 68
1080 09:27:32.748394
1081 09:27:32.748505 Set Vref, RX VrefLevel [Byte0]: 69
1082 09:27:32.751558 [Byte1]: 69
1083 09:27:32.755602
1084 09:27:32.755682 Set Vref, RX VrefLevel [Byte0]: 70
1085 09:27:32.759336 [Byte1]: 70
1086 09:27:32.763314
1087 09:27:32.763416 Set Vref, RX VrefLevel [Byte0]: 71
1088 09:27:32.766786 [Byte1]: 71
1089 09:27:32.771223
1090 09:27:32.771303 Set Vref, RX VrefLevel [Byte0]: 72
1091 09:27:32.774518 [Byte1]: 72
1092 09:27:32.778687
1093 09:27:32.778767 Set Vref, RX VrefLevel [Byte0]: 73
1094 09:27:32.781951 [Byte1]: 73
1095 09:27:32.786214
1096 09:27:32.786295 Set Vref, RX VrefLevel [Byte0]: 74
1097 09:27:32.789693 [Byte1]: 74
1098 09:27:32.793932
1099 09:27:32.794012 Set Vref, RX VrefLevel [Byte0]: 75
1100 09:27:32.797385 [Byte1]: 75
1101 09:27:32.801742
1102 09:27:32.801822 Set Vref, RX VrefLevel [Byte0]: 76
1103 09:27:32.804867 [Byte1]: 76
1104 09:27:32.809111
1105 09:27:32.809220 Set Vref, RX VrefLevel [Byte0]: 77
1106 09:27:32.812624 [Byte1]: 77
1107 09:27:32.816884
1108 09:27:32.816964 Set Vref, RX VrefLevel [Byte0]: 78
1109 09:27:32.820294 [Byte1]: 78
1110 09:27:32.824542
1111 09:27:32.824647 Set Vref, RX VrefLevel [Byte0]: 79
1112 09:27:32.827780 [Byte1]: 79
1113 09:27:32.832606
1114 09:27:32.832716 Final RX Vref Byte 0 = 60 to rank0
1115 09:27:32.835480 Final RX Vref Byte 1 = 58 to rank0
1116 09:27:32.839009 Final RX Vref Byte 0 = 60 to rank1
1117 09:27:32.842039 Final RX Vref Byte 1 = 58 to rank1==
1118 09:27:32.845964 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 09:27:32.852026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 09:27:32.852107 ==
1121 09:27:32.852172 DQS Delay:
1122 09:27:32.855576 DQS0 = 0, DQS1 = 0
1123 09:27:32.855657 DQM Delay:
1124 09:27:32.855720 DQM0 = 81, DQM1 = 68
1125 09:27:32.858655 DQ Delay:
1126 09:27:32.862438 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 09:27:32.865412 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1128 09:27:32.865511 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 09:27:32.871879 DQ12 =72, DQ13 =76, DQ14 =76, DQ15 =76
1130 09:27:32.871963
1131 09:27:32.872030
1132 09:27:32.878900 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1133 09:27:32.881904 CH0 RK0: MR19=606, MR18=2929
1134 09:27:32.889087 CH0_RK0: MR19=0x606, MR18=0x2929, DQSOSC=399, MR23=63, INC=92, DEC=61
1135 09:27:32.889196
1136 09:27:32.892101 ----->DramcWriteLeveling(PI) begin...
1137 09:27:32.892209 ==
1138 09:27:32.895349 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 09:27:32.898867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 09:27:32.898949 ==
1141 09:27:32.902338 Write leveling (Byte 0): 32 => 32
1142 09:27:32.905515 Write leveling (Byte 1): 29 => 29
1143 09:27:32.908661 DramcWriteLeveling(PI) end<-----
1144 09:27:32.908742
1145 09:27:32.908804 ==
1146 09:27:32.912078 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 09:27:32.915516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 09:27:32.915598 ==
1149 09:27:32.918661 [Gating] SW mode calibration
1150 09:27:32.925565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 09:27:32.931871 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 09:27:32.935286 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 09:27:32.938872 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 09:27:32.945534 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 09:27:32.948708 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 09:27:32.952314 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 09:27:32.958929 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:27:32.961970 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:27:32.965703 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:27:32.972095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:27:32.975416 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:27:32.978571 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:27:32.985395 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:27:32.989117 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:27:33.032811 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:27:33.033312 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:27:33.033764 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:27:33.033853 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:27:33.034281 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 09:27:33.034834 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 09:27:33.035236 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:27:33.035332 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:27:33.035965 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:27:33.036046 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:27:33.077161 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:27:33.077923 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:27:33.078032 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:27:33.078290 0 9 8 | B1->B0 | 2323 2b2b | 1 0 | (0 0) (0 0)
1179 09:27:33.078353 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1180 09:27:33.079123 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 09:27:33.079369 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 09:27:33.079457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 09:27:33.079516 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 09:27:33.079571 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 09:27:33.082849 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1186 09:27:33.086078 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
1187 09:27:33.089564 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:27:33.092798 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:27:33.099362 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:27:33.103020 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:27:33.106077 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:27:33.113018 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:27:33.116087 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1194 09:27:33.119671 0 11 8 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
1195 09:27:33.123046 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1196 09:27:33.129889 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 09:27:33.133049 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 09:27:33.135976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 09:27:33.142668 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 09:27:33.146498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 09:27:33.150484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 09:27:33.153960 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 09:27:33.161909 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 09:27:33.165171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 09:27:33.168760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 09:27:33.171681 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:27:33.178870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:27:33.182488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:27:33.186089 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:27:33.188831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:27:33.195823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:27:33.198968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:27:33.202630 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:27:33.209084 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:27:33.212695 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:27:33.215648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:27:33.222293 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 09:27:33.225815 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 09:27:33.229337 Total UI for P1: 0, mck2ui 16
1220 09:27:33.232626 best dqsien dly found for B0: ( 0, 14, 4)
1221 09:27:33.235831 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 09:27:33.242224 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 09:27:33.242306 Total UI for P1: 0, mck2ui 16
1224 09:27:33.248995 best dqsien dly found for B1: ( 0, 14, 10)
1225 09:27:33.252507 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1226 09:27:33.255782 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1227 09:27:33.255863
1228 09:27:33.259074 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1229 09:27:33.262633 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1230 09:27:33.265357 [Gating] SW calibration Done
1231 09:27:33.265439 ==
1232 09:27:33.268980 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 09:27:33.272166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 09:27:33.272247 ==
1235 09:27:33.275670 RX Vref Scan: 0
1236 09:27:33.275751
1237 09:27:33.275815 RX Vref 0 -> 0, step: 1
1238 09:27:33.275873
1239 09:27:33.278581 RX Delay -130 -> 252, step: 16
1240 09:27:33.282281 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1241 09:27:33.288711 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1242 09:27:33.292382 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1243 09:27:33.295334 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1244 09:27:33.299123 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1245 09:27:33.302168 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1246 09:27:33.308752 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1247 09:27:33.312340 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1248 09:27:33.315955 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1249 09:27:33.318774 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1250 09:27:33.322355 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 09:27:33.329037 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1252 09:27:33.332501 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1253 09:27:33.335537 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1254 09:27:33.339106 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1255 09:27:33.342378 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1256 09:27:33.342462 ==
1257 09:27:33.345343 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 09:27:33.351966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 09:27:33.352061 ==
1260 09:27:33.352187 DQS Delay:
1261 09:27:33.355459 DQS0 = 0, DQS1 = 0
1262 09:27:33.355541 DQM Delay:
1263 09:27:33.358759 DQM0 = 77, DQM1 = 69
1264 09:27:33.358840 DQ Delay:
1265 09:27:33.362291 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1266 09:27:33.365573 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1267 09:27:33.368760 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1268 09:27:33.372113 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1269 09:27:33.372196
1270 09:27:33.372259
1271 09:27:33.372318 ==
1272 09:27:33.375405 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 09:27:33.378959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 09:27:33.379043 ==
1275 09:27:33.379107
1276 09:27:33.379167
1277 09:27:33.381943 TX Vref Scan disable
1278 09:27:33.385764 == TX Byte 0 ==
1279 09:27:33.388605 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1280 09:27:33.392047 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1281 09:27:33.395669 == TX Byte 1 ==
1282 09:27:33.398769 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1283 09:27:33.402215 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1284 09:27:33.402299 ==
1285 09:27:33.405657 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 09:27:33.408634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 09:27:33.408717 ==
1288 09:27:33.423392 TX Vref=22, minBit 9, minWin=26, winSum=435
1289 09:27:33.426383 TX Vref=24, minBit 1, minWin=27, winSum=437
1290 09:27:33.429999 TX Vref=26, minBit 1, minWin=27, winSum=441
1291 09:27:33.433043 TX Vref=28, minBit 1, minWin=27, winSum=440
1292 09:27:33.436552 TX Vref=30, minBit 1, minWin=27, winSum=444
1293 09:27:33.440068 TX Vref=32, minBit 9, minWin=27, winSum=444
1294 09:27:33.446693 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1295 09:27:33.446797
1296 09:27:33.449560 Final TX Range 1 Vref 30
1297 09:27:33.449644
1298 09:27:33.449708 ==
1299 09:27:33.453119 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 09:27:33.456439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 09:27:33.456527 ==
1302 09:27:33.456591
1303 09:27:33.459923
1304 09:27:33.460004 TX Vref Scan disable
1305 09:27:33.463562 == TX Byte 0 ==
1306 09:27:33.466400 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1307 09:27:33.469878 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1308 09:27:33.473283 == TX Byte 1 ==
1309 09:27:33.476715 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1310 09:27:33.480021 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1311 09:27:33.483215
1312 09:27:33.483300 [DATLAT]
1313 09:27:33.483364 Freq=800, CH0 RK1
1314 09:27:33.483461
1315 09:27:33.486340 DATLAT Default: 0xa
1316 09:27:33.486528 0, 0xFFFF, sum = 0
1317 09:27:33.489992 1, 0xFFFF, sum = 0
1318 09:27:33.490076 2, 0xFFFF, sum = 0
1319 09:27:33.493537 3, 0xFFFF, sum = 0
1320 09:27:33.493622 4, 0xFFFF, sum = 0
1321 09:27:33.496488 5, 0xFFFF, sum = 0
1322 09:27:33.496632 6, 0xFFFF, sum = 0
1323 09:27:33.500210 7, 0xFFFF, sum = 0
1324 09:27:33.503250 8, 0xFFFF, sum = 0
1325 09:27:33.503374 9, 0x0, sum = 1
1326 09:27:33.503471 10, 0x0, sum = 2
1327 09:27:33.507080 11, 0x0, sum = 3
1328 09:27:33.507170 12, 0x0, sum = 4
1329 09:27:33.509805 best_step = 10
1330 09:27:33.509890
1331 09:27:33.509954 ==
1332 09:27:33.512804 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 09:27:33.516176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 09:27:33.516261 ==
1335 09:27:33.519955 RX Vref Scan: 0
1336 09:27:33.520040
1337 09:27:33.520107 RX Vref 0 -> 0, step: 1
1338 09:27:33.520168
1339 09:27:33.523119 RX Delay -111 -> 252, step: 8
1340 09:27:33.529651 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1341 09:27:33.533356 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1342 09:27:33.536565 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1343 09:27:33.540192 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1344 09:27:33.543237 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1345 09:27:33.550015 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1346 09:27:33.552894 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1347 09:27:33.556588 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1348 09:27:33.559654 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1349 09:27:33.563175 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1350 09:27:33.570087 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1351 09:27:33.573169 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1352 09:27:33.576695 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1353 09:27:33.579607 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1354 09:27:33.586256 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1355 09:27:33.589503 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1356 09:27:33.589585 ==
1357 09:27:33.592967 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 09:27:33.596239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 09:27:33.596325 ==
1360 09:27:33.596407 DQS Delay:
1361 09:27:33.599893 DQS0 = 0, DQS1 = 0
1362 09:27:33.599967 DQM Delay:
1363 09:27:33.602996 DQM0 = 79, DQM1 = 70
1364 09:27:33.603071 DQ Delay:
1365 09:27:33.606391 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1366 09:27:33.609770 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1367 09:27:33.613229 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1368 09:27:33.616970 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1369 09:27:33.617054
1370 09:27:33.617118
1371 09:27:33.626147 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1372 09:27:33.626260 CH0 RK1: MR19=606, MR18=4B25
1373 09:27:33.632800 CH0_RK1: MR19=0x606, MR18=0x4B25, DQSOSC=391, MR23=63, INC=96, DEC=64
1374 09:27:33.636471 [RxdqsGatingPostProcess] freq 800
1375 09:27:33.643156 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 09:27:33.646467 Pre-setting of DQS Precalculation
1377 09:27:33.650037 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 09:27:33.650126 ==
1379 09:27:33.653081 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 09:27:33.656677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 09:27:33.656769 ==
1382 09:27:33.662796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 09:27:33.669973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 09:27:33.678549 [CA 0] Center 36 (6~66) winsize 61
1385 09:27:33.681398 [CA 1] Center 36 (6~67) winsize 62
1386 09:27:33.684890 [CA 2] Center 34 (4~64) winsize 61
1387 09:27:33.688033 [CA 3] Center 34 (4~64) winsize 61
1388 09:27:33.691833 [CA 4] Center 34 (4~64) winsize 61
1389 09:27:33.694800 [CA 5] Center 33 (3~64) winsize 62
1390 09:27:33.694888
1391 09:27:33.698283 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1392 09:27:33.698372
1393 09:27:33.701928 [CATrainingPosCal] consider 1 rank data
1394 09:27:33.704640 u2DelayCellTimex100 = 270/100 ps
1395 09:27:33.708416 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 09:27:33.711373 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1397 09:27:33.718126 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1398 09:27:33.721666 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1399 09:27:33.725155 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 09:27:33.727867 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 09:27:33.727962
1402 09:27:33.731220 CA PerBit enable=1, Macro0, CA PI delay=33
1403 09:27:33.731333
1404 09:27:33.734782 [CBTSetCACLKResult] CA Dly = 33
1405 09:27:33.734869 CS Dly: 5 (0~36)
1406 09:27:33.734954 ==
1407 09:27:33.738345 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 09:27:33.744610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 09:27:33.744703 ==
1410 09:27:33.748426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 09:27:33.755603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 09:27:33.764063 [CA 0] Center 36 (6~67) winsize 62
1413 09:27:33.767760 [CA 1] Center 36 (6~67) winsize 62
1414 09:27:33.770888 [CA 2] Center 35 (5~65) winsize 61
1415 09:27:33.773943 [CA 3] Center 33 (3~64) winsize 62
1416 09:27:33.777519 [CA 4] Center 34 (4~65) winsize 62
1417 09:27:33.781012 [CA 5] Center 33 (3~64) winsize 62
1418 09:27:33.781109
1419 09:27:33.784237 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 09:27:33.784325
1421 09:27:33.787278 [CATrainingPosCal] consider 2 rank data
1422 09:27:33.790855 u2DelayCellTimex100 = 270/100 ps
1423 09:27:33.794306 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 09:27:33.797565 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1425 09:27:33.803898 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1426 09:27:33.807645 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1427 09:27:33.811088 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 09:27:33.814767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 09:27:33.814884
1430 09:27:33.818244 CA PerBit enable=1, Macro0, CA PI delay=33
1431 09:27:33.818329
1432 09:27:33.821873 [CBTSetCACLKResult] CA Dly = 33
1433 09:27:33.821961 CS Dly: 6 (0~38)
1434 09:27:33.822026
1435 09:27:33.825996 ----->DramcWriteLeveling(PI) begin...
1436 09:27:33.826083 ==
1437 09:27:33.829343 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 09:27:33.833317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 09:27:33.833406 ==
1440 09:27:33.837188 Write leveling (Byte 0): 26 => 26
1441 09:27:33.840778 Write leveling (Byte 1): 31 => 31
1442 09:27:33.844210 DramcWriteLeveling(PI) end<-----
1443 09:27:33.844299
1444 09:27:33.844364 ==
1445 09:27:33.847813 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 09:27:33.850989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 09:27:33.851080 ==
1448 09:27:33.854704 [Gating] SW mode calibration
1449 09:27:33.861438 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 09:27:33.864390 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 09:27:33.871080 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 09:27:33.874615 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 09:27:33.877770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 09:27:33.884479 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 09:27:33.888061 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:27:33.891311 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:27:33.897864 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:27:33.901167 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:27:33.904264 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:27:33.911262 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:27:33.914640 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:27:33.917600 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:27:33.921197 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:27:33.927951 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:27:33.931286 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:27:33.934344 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:27:33.941151 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:27:33.944244 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 09:27:33.947602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1470 09:27:33.954237 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:27:33.957556 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:27:33.961308 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:27:33.967761 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:27:33.970862 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:27:33.974309 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:27:33.981106 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:27:33.984874 0 9 8 | B1->B0 | 2929 2726 | 0 1 | (0 0) (0 0)
1478 09:27:33.987916 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1479 09:27:33.994507 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 09:27:33.997662 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 09:27:34.001026 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 09:27:34.007815 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 09:27:34.011563 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 09:27:34.014264 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 09:27:34.017673 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 1) (0 0)
1486 09:27:34.024351 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1487 09:27:34.027949 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:27:34.031291 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:27:34.037757 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:27:34.041330 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:27:34.044435 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:27:34.051033 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1493 09:27:34.054578 0 11 8 | B1->B0 | 3939 3535 | 0 0 | (0 0) (1 1)
1494 09:27:34.058086 0 11 12 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
1495 09:27:34.064151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 09:27:34.067440 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 09:27:34.071347 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 09:27:34.078043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 09:27:34.080959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 09:27:34.084545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 09:27:34.091116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 09:27:34.094608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 09:27:34.097675 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:27:34.104410 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:27:34.107856 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:27:34.111338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:27:34.117607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:27:34.120908 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:27:34.124258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:27:34.127791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:27:34.134299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:27:34.138066 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:27:34.141231 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:27:34.147902 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:27:34.150980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:27:34.154539 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:27:34.161090 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 09:27:34.164518 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 09:27:34.168166 Total UI for P1: 0, mck2ui 16
1520 09:27:34.171169 best dqsien dly found for B0: ( 0, 14, 8)
1521 09:27:34.174701 Total UI for P1: 0, mck2ui 16
1522 09:27:34.178471 best dqsien dly found for B1: ( 0, 14, 8)
1523 09:27:34.181186 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1524 09:27:34.184613 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1525 09:27:34.184701
1526 09:27:34.187808 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 09:27:34.191349 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 09:27:34.194381 [Gating] SW calibration Done
1529 09:27:34.194470 ==
1530 09:27:34.198185 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 09:27:34.201093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 09:27:34.201172 ==
1533 09:27:34.204626 RX Vref Scan: 0
1534 09:27:34.204701
1535 09:27:34.208096 RX Vref 0 -> 0, step: 1
1536 09:27:34.208195
1537 09:27:34.208285 RX Delay -130 -> 252, step: 16
1538 09:27:34.214663 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1539 09:27:34.217997 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1540 09:27:34.221140 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1541 09:27:34.224435 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1542 09:27:34.227969 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1543 09:27:34.234177 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1544 09:27:34.238182 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1545 09:27:34.241245 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1546 09:27:34.244775 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1547 09:27:34.247824 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1548 09:27:34.255008 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1549 09:27:34.257972 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1550 09:27:34.261060 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1551 09:27:34.264449 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1552 09:27:34.268097 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1553 09:27:34.274567 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1554 09:27:34.274668 ==
1555 09:27:34.278052 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 09:27:34.281168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 09:27:34.281242 ==
1558 09:27:34.281305 DQS Delay:
1559 09:27:34.284302 DQS0 = 0, DQS1 = 0
1560 09:27:34.284378 DQM Delay:
1561 09:27:34.287797 DQM0 = 85, DQM1 = 77
1562 09:27:34.287869 DQ Delay:
1563 09:27:34.291093 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1564 09:27:34.294492 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1565 09:27:34.297936 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1566 09:27:34.301318 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1567 09:27:34.301397
1568 09:27:34.301466
1569 09:27:34.301528 ==
1570 09:27:34.304450 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 09:27:34.308171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 09:27:34.308247 ==
1573 09:27:34.308308
1574 09:27:34.311246
1575 09:27:34.311316 TX Vref Scan disable
1576 09:27:34.314723 == TX Byte 0 ==
1577 09:27:34.317900 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1578 09:27:34.321494 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1579 09:27:34.324587 == TX Byte 1 ==
1580 09:27:34.327847 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1581 09:27:34.331578 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1582 09:27:34.331662 ==
1583 09:27:34.335046 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 09:27:34.341580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 09:27:34.341673 ==
1586 09:27:34.353123 TX Vref=22, minBit 5, minWin=27, winSum=445
1587 09:27:34.356743 TX Vref=24, minBit 1, minWin=27, winSum=444
1588 09:27:34.359936 TX Vref=26, minBit 1, minWin=27, winSum=447
1589 09:27:34.363344 TX Vref=28, minBit 0, minWin=28, winSum=451
1590 09:27:34.366463 TX Vref=30, minBit 6, minWin=27, winSum=448
1591 09:27:34.370020 TX Vref=32, minBit 6, minWin=27, winSum=449
1592 09:27:34.376565 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
1593 09:27:34.376673
1594 09:27:34.380062 Final TX Range 1 Vref 28
1595 09:27:34.380152
1596 09:27:34.380217 ==
1597 09:27:34.383134 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 09:27:34.387254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 09:27:34.387395 ==
1600 09:27:34.387479
1601 09:27:34.387539
1602 09:27:34.390994 TX Vref Scan disable
1603 09:27:34.393875 == TX Byte 0 ==
1604 09:27:34.397516 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1605 09:27:34.400890 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1606 09:27:34.404352 == TX Byte 1 ==
1607 09:27:34.407508 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1608 09:27:34.410909 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1609 09:27:34.411001
1610 09:27:34.414078 [DATLAT]
1611 09:27:34.414175 Freq=800, CH1 RK0
1612 09:27:34.414246
1613 09:27:34.417745 DATLAT Default: 0xa
1614 09:27:34.417819 0, 0xFFFF, sum = 0
1615 09:27:34.420763 1, 0xFFFF, sum = 0
1616 09:27:34.420842 2, 0xFFFF, sum = 0
1617 09:27:34.424359 3, 0xFFFF, sum = 0
1618 09:27:34.424435 4, 0xFFFF, sum = 0
1619 09:27:34.427313 5, 0xFFFF, sum = 0
1620 09:27:34.427420 6, 0xFFFF, sum = 0
1621 09:27:34.430950 7, 0xFFFF, sum = 0
1622 09:27:34.431030 8, 0xFFFF, sum = 0
1623 09:27:34.433947 9, 0x0, sum = 1
1624 09:27:34.434045 10, 0x0, sum = 2
1625 09:27:34.437484 11, 0x0, sum = 3
1626 09:27:34.437559 12, 0x0, sum = 4
1627 09:27:34.440593 best_step = 10
1628 09:27:34.440667
1629 09:27:34.440727 ==
1630 09:27:34.443899 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 09:27:34.447667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 09:27:34.447773 ==
1633 09:27:34.447870 RX Vref Scan: 1
1634 09:27:34.447961
1635 09:27:34.450632 Set Vref Range= 32 -> 127
1636 09:27:34.450732
1637 09:27:34.454014 RX Vref 32 -> 127, step: 1
1638 09:27:34.454096
1639 09:27:34.457553 RX Delay -111 -> 252, step: 8
1640 09:27:34.457625
1641 09:27:34.460587 Set Vref, RX VrefLevel [Byte0]: 32
1642 09:27:34.463924 [Byte1]: 32
1643 09:27:34.464000
1644 09:27:34.467836 Set Vref, RX VrefLevel [Byte0]: 33
1645 09:27:34.471095 [Byte1]: 33
1646 09:27:34.471177
1647 09:27:34.474126 Set Vref, RX VrefLevel [Byte0]: 34
1648 09:27:34.477312 [Byte1]: 34
1649 09:27:34.481487
1650 09:27:34.481577 Set Vref, RX VrefLevel [Byte0]: 35
1651 09:27:34.484494 [Byte1]: 35
1652 09:27:34.489201
1653 09:27:34.489295 Set Vref, RX VrefLevel [Byte0]: 36
1654 09:27:34.492210 [Byte1]: 36
1655 09:27:34.496620
1656 09:27:34.496706 Set Vref, RX VrefLevel [Byte0]: 37
1657 09:27:34.500160 [Byte1]: 37
1658 09:27:34.504216
1659 09:27:34.504304 Set Vref, RX VrefLevel [Byte0]: 38
1660 09:27:34.507897 [Byte1]: 38
1661 09:27:34.512396
1662 09:27:34.512478 Set Vref, RX VrefLevel [Byte0]: 39
1663 09:27:34.515537 [Byte1]: 39
1664 09:27:34.519412
1665 09:27:34.519507 Set Vref, RX VrefLevel [Byte0]: 40
1666 09:27:34.522829 [Byte1]: 40
1667 09:27:34.527333
1668 09:27:34.527473 Set Vref, RX VrefLevel [Byte0]: 41
1669 09:27:34.530718 [Byte1]: 41
1670 09:27:34.534995
1671 09:27:34.535098 Set Vref, RX VrefLevel [Byte0]: 42
1672 09:27:34.538528 [Byte1]: 42
1673 09:27:34.542648
1674 09:27:34.542740 Set Vref, RX VrefLevel [Byte0]: 43
1675 09:27:34.546202 [Byte1]: 43
1676 09:27:34.550482
1677 09:27:34.550572 Set Vref, RX VrefLevel [Byte0]: 44
1678 09:27:34.553583 [Byte1]: 44
1679 09:27:34.557832
1680 09:27:34.557923 Set Vref, RX VrefLevel [Byte0]: 45
1681 09:27:34.561259 [Byte1]: 45
1682 09:27:34.565346
1683 09:27:34.565439 Set Vref, RX VrefLevel [Byte0]: 46
1684 09:27:34.569157 [Byte1]: 46
1685 09:27:34.573209
1686 09:27:34.573307 Set Vref, RX VrefLevel [Byte0]: 47
1687 09:27:34.576799 [Byte1]: 47
1688 09:27:34.581348
1689 09:27:34.581442 Set Vref, RX VrefLevel [Byte0]: 48
1690 09:27:34.584000 [Byte1]: 48
1691 09:27:34.588371
1692 09:27:34.588458 Set Vref, RX VrefLevel [Byte0]: 49
1693 09:27:34.591718 [Byte1]: 49
1694 09:27:34.596010
1695 09:27:34.596108 Set Vref, RX VrefLevel [Byte0]: 50
1696 09:27:34.599377 [Byte1]: 50
1697 09:27:34.603664
1698 09:27:34.603757 Set Vref, RX VrefLevel [Byte0]: 51
1699 09:27:34.607297 [Byte1]: 51
1700 09:27:34.611653
1701 09:27:34.611739 Set Vref, RX VrefLevel [Byte0]: 52
1702 09:27:34.614986 [Byte1]: 52
1703 09:27:34.619231
1704 09:27:34.619319 Set Vref, RX VrefLevel [Byte0]: 53
1705 09:27:34.622700 [Byte1]: 53
1706 09:27:34.626958
1707 09:27:34.627047 Set Vref, RX VrefLevel [Byte0]: 54
1708 09:27:34.629887 [Byte1]: 54
1709 09:27:34.634540
1710 09:27:34.634632 Set Vref, RX VrefLevel [Byte0]: 55
1711 09:27:34.637692 [Byte1]: 55
1712 09:27:34.642111
1713 09:27:34.642191 Set Vref, RX VrefLevel [Byte0]: 56
1714 09:27:34.645284 [Byte1]: 56
1715 09:27:34.649564
1716 09:27:34.649656 Set Vref, RX VrefLevel [Byte0]: 57
1717 09:27:34.653250 [Byte1]: 57
1718 09:27:34.657298
1719 09:27:34.657401 Set Vref, RX VrefLevel [Byte0]: 58
1720 09:27:34.660643 [Byte1]: 58
1721 09:27:34.664839
1722 09:27:34.664926 Set Vref, RX VrefLevel [Byte0]: 59
1723 09:27:34.668177 [Byte1]: 59
1724 09:27:34.672392
1725 09:27:34.672480 Set Vref, RX VrefLevel [Byte0]: 60
1726 09:27:34.676106 [Byte1]: 60
1727 09:27:34.680318
1728 09:27:34.680402 Set Vref, RX VrefLevel [Byte0]: 61
1729 09:27:34.683375 [Byte1]: 61
1730 09:27:34.688156
1731 09:27:34.688242 Set Vref, RX VrefLevel [Byte0]: 62
1732 09:27:34.691051 [Byte1]: 62
1733 09:27:34.695299
1734 09:27:34.695424 Set Vref, RX VrefLevel [Byte0]: 63
1735 09:27:34.698630 [Byte1]: 63
1736 09:27:34.703287
1737 09:27:34.703378 Set Vref, RX VrefLevel [Byte0]: 64
1738 09:27:34.706417 [Byte1]: 64
1739 09:27:34.710607
1740 09:27:34.710703 Set Vref, RX VrefLevel [Byte0]: 65
1741 09:27:34.713846 [Byte1]: 65
1742 09:27:34.718398
1743 09:27:34.718489 Set Vref, RX VrefLevel [Byte0]: 66
1744 09:27:34.721862 [Byte1]: 66
1745 09:27:34.726006
1746 09:27:34.726085 Set Vref, RX VrefLevel [Byte0]: 67
1747 09:27:34.729446 [Byte1]: 67
1748 09:27:34.733655
1749 09:27:34.733739 Set Vref, RX VrefLevel [Byte0]: 68
1750 09:27:34.737075 [Byte1]: 68
1751 09:27:34.741251
1752 09:27:34.741335 Set Vref, RX VrefLevel [Byte0]: 69
1753 09:27:34.744711 [Byte1]: 69
1754 09:27:34.749446
1755 09:27:34.749539 Set Vref, RX VrefLevel [Byte0]: 70
1756 09:27:34.752434 [Byte1]: 70
1757 09:27:34.756982
1758 09:27:34.757078 Set Vref, RX VrefLevel [Byte0]: 71
1759 09:27:34.760155 [Byte1]: 71
1760 09:27:34.764669
1761 09:27:34.764770 Set Vref, RX VrefLevel [Byte0]: 72
1762 09:27:34.768025 [Byte1]: 72
1763 09:27:34.771754
1764 09:27:34.771845 Final RX Vref Byte 0 = 57 to rank0
1765 09:27:34.775321 Final RX Vref Byte 1 = 54 to rank0
1766 09:27:34.778602 Final RX Vref Byte 0 = 57 to rank1
1767 09:27:34.782088 Final RX Vref Byte 1 = 54 to rank1==
1768 09:27:34.785622 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 09:27:34.792111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 09:27:34.792209 ==
1771 09:27:34.792282 DQS Delay:
1772 09:27:34.792343 DQS0 = 0, DQS1 = 0
1773 09:27:34.795273 DQM Delay:
1774 09:27:34.795361 DQM0 = 81, DQM1 = 71
1775 09:27:34.798859 DQ Delay:
1776 09:27:34.801945 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1777 09:27:34.805514 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1778 09:27:34.805597 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1779 09:27:34.812117 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =80
1780 09:27:34.812211
1781 09:27:34.812282
1782 09:27:34.818586 [DQSOSCAuto] RK0, (LSB)MR18= 0x1621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1783 09:27:34.822230 CH1 RK0: MR19=606, MR18=1621
1784 09:27:34.828735 CH1_RK0: MR19=0x606, MR18=0x1621, DQSOSC=401, MR23=63, INC=91, DEC=61
1785 09:27:34.828842
1786 09:27:34.831708 ----->DramcWriteLeveling(PI) begin...
1787 09:27:34.831805 ==
1788 09:27:34.835302 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 09:27:34.838407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 09:27:34.838522 ==
1791 09:27:34.842058 Write leveling (Byte 0): 28 => 28
1792 09:27:34.844940 Write leveling (Byte 1): 29 => 29
1793 09:27:34.848516 DramcWriteLeveling(PI) end<-----
1794 09:27:34.848600
1795 09:27:34.848670 ==
1796 09:27:34.851884 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 09:27:34.854948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 09:27:34.855027 ==
1799 09:27:34.858628 [Gating] SW mode calibration
1800 09:27:34.865235 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 09:27:34.871566 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 09:27:34.874857 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1803 09:27:34.878616 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1804 09:27:34.885423 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 09:27:34.888543 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 09:27:34.891687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 09:27:34.898860 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 09:27:34.901810 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 09:27:34.905320 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 09:27:34.912084 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 09:27:34.915046 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 09:27:34.918662 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 09:27:34.925254 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 09:27:34.928739 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:27:34.931587 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:27:34.938318 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:27:34.941816 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:27:34.945187 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:27:34.948317 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1820 09:27:34.955285 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:27:34.958892 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:27:34.961964 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:27:34.968519 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:27:34.972165 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:27:34.975156 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:27:34.981608 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:27:34.985377 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1828 09:27:34.988885 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1829 09:27:34.995085 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 09:27:34.998266 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 09:27:35.001815 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 09:27:35.008541 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 09:27:35.011750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 09:27:35.015329 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 09:27:35.021869 0 10 4 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (0 0)
1836 09:27:35.025624 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:27:35.028586 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:27:35.034923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:27:35.038489 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:27:35.042204 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:27:35.045045 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:27:35.051676 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1843 09:27:35.054913 0 11 4 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
1844 09:27:35.058280 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1845 09:27:35.065295 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 09:27:35.068265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 09:27:35.072126 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 09:27:35.078562 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 09:27:35.081715 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 09:27:35.085329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 09:27:35.091922 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 09:27:35.095455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 09:27:35.098519 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 09:27:35.105090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 09:27:35.108636 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 09:27:35.112197 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 09:27:35.118294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 09:27:35.122041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 09:27:35.125194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 09:27:35.131509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 09:27:35.134785 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 09:27:35.138307 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 09:27:35.141992 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 09:27:35.148408 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:27:35.151491 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:27:35.154910 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:27:35.161997 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 09:27:35.164967 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 09:27:35.168185 Total UI for P1: 0, mck2ui 16
1870 09:27:35.171583 best dqsien dly found for B0: ( 0, 14, 4)
1871 09:27:35.174889 Total UI for P1: 0, mck2ui 16
1872 09:27:35.178500 best dqsien dly found for B1: ( 0, 14, 4)
1873 09:27:35.181580 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1874 09:27:35.185150 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 09:27:35.185242
1876 09:27:35.188858 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 09:27:35.191899 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 09:27:35.195550 [Gating] SW calibration Done
1879 09:27:35.195666 ==
1880 09:27:35.199071 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 09:27:35.202053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 09:27:35.202139 ==
1883 09:27:35.205148 RX Vref Scan: 0
1884 09:27:35.205230
1885 09:27:35.208679 RX Vref 0 -> 0, step: 1
1886 09:27:35.208756
1887 09:27:35.211677 RX Delay -130 -> 252, step: 16
1888 09:27:35.215539 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1889 09:27:35.218327 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1890 09:27:35.222008 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1891 09:27:35.225042 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1892 09:27:35.228863 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1893 09:27:35.235266 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1894 09:27:35.238543 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1895 09:27:35.241639 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1896 09:27:35.245327 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1897 09:27:35.248581 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1898 09:27:35.255361 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1899 09:27:35.258707 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1900 09:27:35.261702 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1901 09:27:35.265137 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1902 09:27:35.272191 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1903 09:27:35.275033 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1904 09:27:35.275124 ==
1905 09:27:35.278632 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 09:27:35.281598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 09:27:35.281712 ==
1908 09:27:35.281806 DQS Delay:
1909 09:27:35.285335 DQS0 = 0, DQS1 = 0
1910 09:27:35.285422 DQM Delay:
1911 09:27:35.288772 DQM0 = 80, DQM1 = 74
1912 09:27:35.288858 DQ Delay:
1913 09:27:35.292147 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1914 09:27:35.295329 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1915 09:27:35.298504 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1916 09:27:35.301730 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1917 09:27:35.301850
1918 09:27:35.301942
1919 09:27:35.302031 ==
1920 09:27:35.305129 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 09:27:35.308831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 09:27:35.308947 ==
1923 09:27:35.311798
1924 09:27:35.311881
1925 09:27:35.311947 TX Vref Scan disable
1926 09:27:35.315362 == TX Byte 0 ==
1927 09:27:35.318336 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1928 09:27:35.321842 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1929 09:27:35.325025 == TX Byte 1 ==
1930 09:27:35.328663 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 09:27:35.331968 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 09:27:35.332059 ==
1933 09:27:35.335298 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 09:27:35.342015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 09:27:35.342148 ==
1936 09:27:35.353545 TX Vref=22, minBit 4, minWin=27, winSum=447
1937 09:27:35.356949 TX Vref=24, minBit 6, minWin=27, winSum=451
1938 09:27:35.360641 TX Vref=26, minBit 1, minWin=27, winSum=454
1939 09:27:35.364129 TX Vref=28, minBit 0, minWin=28, winSum=458
1940 09:27:35.367304 TX Vref=30, minBit 1, minWin=27, winSum=459
1941 09:27:35.370583 TX Vref=32, minBit 5, minWin=27, winSum=462
1942 09:27:35.376996 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1943 09:27:35.377108
1944 09:27:35.381026 Final TX Range 1 Vref 28
1945 09:27:35.381118
1946 09:27:35.381184 ==
1947 09:27:35.384100 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 09:27:35.387279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 09:27:35.387367 ==
1950 09:27:35.387480
1951 09:27:35.387540
1952 09:27:35.390870 TX Vref Scan disable
1953 09:27:35.394240 == TX Byte 0 ==
1954 09:27:35.397335 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1955 09:27:35.400871 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1956 09:27:35.404103 == TX Byte 1 ==
1957 09:27:35.407517 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 09:27:35.410735 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 09:27:35.410830
1960 09:27:35.414217 [DATLAT]
1961 09:27:35.414302 Freq=800, CH1 RK1
1962 09:27:35.414445
1963 09:27:35.417673 DATLAT Default: 0xa
1964 09:27:35.417758 0, 0xFFFF, sum = 0
1965 09:27:35.420637 1, 0xFFFF, sum = 0
1966 09:27:35.420725 2, 0xFFFF, sum = 0
1967 09:27:35.424437 3, 0xFFFF, sum = 0
1968 09:27:35.424522 4, 0xFFFF, sum = 0
1969 09:27:35.427406 5, 0xFFFF, sum = 0
1970 09:27:35.427491 6, 0xFFFF, sum = 0
1971 09:27:35.430953 7, 0xFFFF, sum = 0
1972 09:27:35.431038 8, 0xFFFF, sum = 0
1973 09:27:35.433799 9, 0x0, sum = 1
1974 09:27:35.433912 10, 0x0, sum = 2
1975 09:27:35.437421 11, 0x0, sum = 3
1976 09:27:35.437508 12, 0x0, sum = 4
1977 09:27:35.440558 best_step = 10
1978 09:27:35.440641
1979 09:27:35.440706 ==
1980 09:27:35.444271 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 09:27:35.447138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 09:27:35.447224 ==
1983 09:27:35.450810 RX Vref Scan: 0
1984 09:27:35.450896
1985 09:27:35.450960 RX Vref 0 -> 0, step: 1
1986 09:27:35.451024
1987 09:27:35.453872 RX Delay -111 -> 252, step: 8
1988 09:27:35.460893 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1989 09:27:35.464266 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1990 09:27:35.467058 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1991 09:27:35.470395 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1992 09:27:35.474022 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1993 09:27:35.480500 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1994 09:27:35.483898 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1995 09:27:35.487238 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1996 09:27:35.490540 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1997 09:27:35.493672 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1998 09:27:35.500420 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1999 09:27:35.503680 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2000 09:27:35.507141 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2001 09:27:35.510511 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2002 09:27:35.513961 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2003 09:27:35.520721 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2004 09:27:35.520835 ==
2005 09:27:35.523906 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 09:27:35.527345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 09:27:35.527445 ==
2008 09:27:35.527512 DQS Delay:
2009 09:27:35.530354 DQS0 = 0, DQS1 = 0
2010 09:27:35.530438 DQM Delay:
2011 09:27:35.534148 DQM0 = 77, DQM1 = 74
2012 09:27:35.534245 DQ Delay:
2013 09:27:35.537033 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2014 09:27:35.540699 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2015 09:27:35.543668 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2016 09:27:35.547345 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2017 09:27:35.547475
2018 09:27:35.547542
2019 09:27:35.553764 [DQSOSCAuto] RK1, (LSB)MR18= 0x2039, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2020 09:27:35.557255 CH1 RK1: MR19=606, MR18=2039
2021 09:27:35.563932 CH1_RK1: MR19=0x606, MR18=0x2039, DQSOSC=395, MR23=63, INC=94, DEC=63
2022 09:27:35.567311 [RxdqsGatingPostProcess] freq 800
2023 09:27:35.574315 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 09:27:35.577490 Pre-setting of DQS Precalculation
2025 09:27:35.580423 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 09:27:35.587080 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 09:27:35.593472 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 09:27:35.593589
2029 09:27:35.593675
2030 09:27:35.596993 [Calibration Summary] 1600 Mbps
2031 09:27:35.600666 CH 0, Rank 0
2032 09:27:35.600758 SW Impedance : PASS
2033 09:27:35.603523 DUTY Scan : NO K
2034 09:27:35.607177 ZQ Calibration : PASS
2035 09:27:35.607266 Jitter Meter : NO K
2036 09:27:35.610205 CBT Training : PASS
2037 09:27:35.613679 Write leveling : PASS
2038 09:27:35.613766 RX DQS gating : PASS
2039 09:27:35.617144 RX DQ/DQS(RDDQC) : PASS
2040 09:27:35.620751 TX DQ/DQS : PASS
2041 09:27:35.620839 RX DATLAT : PASS
2042 09:27:35.623917 RX DQ/DQS(Engine): PASS
2043 09:27:35.624000 TX OE : NO K
2044 09:27:35.627062 All Pass.
2045 09:27:35.627146
2046 09:27:35.627211 CH 0, Rank 1
2047 09:27:35.630064 SW Impedance : PASS
2048 09:27:35.630150 DUTY Scan : NO K
2049 09:27:35.633356 ZQ Calibration : PASS
2050 09:27:35.636692 Jitter Meter : NO K
2051 09:27:35.636780 CBT Training : PASS
2052 09:27:35.640133 Write leveling : PASS
2053 09:27:35.643654 RX DQS gating : PASS
2054 09:27:35.643742 RX DQ/DQS(RDDQC) : PASS
2055 09:27:35.647308 TX DQ/DQS : PASS
2056 09:27:35.650112 RX DATLAT : PASS
2057 09:27:35.650198 RX DQ/DQS(Engine): PASS
2058 09:27:35.653739 TX OE : NO K
2059 09:27:35.653827 All Pass.
2060 09:27:35.653892
2061 09:27:35.656726 CH 1, Rank 0
2062 09:27:35.656810 SW Impedance : PASS
2063 09:27:35.660493 DUTY Scan : NO K
2064 09:27:35.663307 ZQ Calibration : PASS
2065 09:27:35.663417 Jitter Meter : NO K
2066 09:27:35.666911 CBT Training : PASS
2067 09:27:35.670307 Write leveling : PASS
2068 09:27:35.670393 RX DQS gating : PASS
2069 09:27:35.673440 RX DQ/DQS(RDDQC) : PASS
2070 09:27:35.673531 TX DQ/DQS : PASS
2071 09:27:35.676743 RX DATLAT : PASS
2072 09:27:35.680201 RX DQ/DQS(Engine): PASS
2073 09:27:35.680286 TX OE : NO K
2074 09:27:35.683485 All Pass.
2075 09:27:35.683569
2076 09:27:35.683633 CH 1, Rank 1
2077 09:27:35.686846 SW Impedance : PASS
2078 09:27:35.686929 DUTY Scan : NO K
2079 09:27:35.690372 ZQ Calibration : PASS
2080 09:27:35.693406 Jitter Meter : NO K
2081 09:27:35.693492 CBT Training : PASS
2082 09:27:35.696935 Write leveling : PASS
2083 09:27:35.699849 RX DQS gating : PASS
2084 09:27:35.699934 RX DQ/DQS(RDDQC) : PASS
2085 09:27:35.703479 TX DQ/DQS : PASS
2086 09:27:35.706893 RX DATLAT : PASS
2087 09:27:35.706972 RX DQ/DQS(Engine): PASS
2088 09:27:35.709898 TX OE : NO K
2089 09:27:35.709974 All Pass.
2090 09:27:35.710036
2091 09:27:35.713531 DramC Write-DBI off
2092 09:27:35.717108 PER_BANK_REFRESH: Hybrid Mode
2093 09:27:35.717186 TX_TRACKING: ON
2094 09:27:35.720046 [GetDramInforAfterCalByMRR] Vendor 6.
2095 09:27:35.723073 [GetDramInforAfterCalByMRR] Revision 606.
2096 09:27:35.726528 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 09:27:35.730304 MR0 0x3b3b
2098 09:27:35.730384 MR8 0x5151
2099 09:27:35.733582 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 09:27:35.733671
2101 09:27:35.733735 MR0 0x3b3b
2102 09:27:35.736965 MR8 0x5151
2103 09:27:35.739797 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 09:27:35.739876
2105 09:27:35.746668 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 09:27:35.753314 [FAST_K] Save calibration result to emmc
2107 09:27:35.756647 [FAST_K] Save calibration result to emmc
2108 09:27:35.756766 dram_init: config_dvfs: 1
2109 09:27:35.763906 dramc_set_vcore_voltage set vcore to 662500
2110 09:27:35.764034 Read voltage for 1200, 2
2111 09:27:35.764101 Vio18 = 0
2112 09:27:35.766883 Vcore = 662500
2113 09:27:35.766996 Vdram = 0
2114 09:27:35.767092 Vddq = 0
2115 09:27:35.769829 Vmddr = 0
2116 09:27:35.773575 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 09:27:35.780413 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 09:27:35.780563 MEM_TYPE=3, freq_sel=15
2119 09:27:35.783186 sv_algorithm_assistance_LP4_1600
2120 09:27:35.789825 ============ PULL DRAM RESETB DOWN ============
2121 09:27:35.793302 ========== PULL DRAM RESETB DOWN end =========
2122 09:27:35.796706 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 09:27:35.799819 ===================================
2124 09:27:35.803540 LPDDR4 DRAM CONFIGURATION
2125 09:27:35.806935 ===================================
2126 09:27:35.810291 EX_ROW_EN[0] = 0x0
2127 09:27:35.810402 EX_ROW_EN[1] = 0x0
2128 09:27:35.813305 LP4Y_EN = 0x0
2129 09:27:35.813418 WORK_FSP = 0x0
2130 09:27:35.816496 WL = 0x4
2131 09:27:35.816598 RL = 0x4
2132 09:27:35.820161 BL = 0x2
2133 09:27:35.820264 RPST = 0x0
2134 09:27:35.823069 RD_PRE = 0x0
2135 09:27:35.823175 WR_PRE = 0x1
2136 09:27:35.826560 WR_PST = 0x0
2137 09:27:35.826670 DBI_WR = 0x0
2138 09:27:35.830157 DBI_RD = 0x0
2139 09:27:35.830259 OTF = 0x1
2140 09:27:35.833265 ===================================
2141 09:27:35.836654 ===================================
2142 09:27:35.840197 ANA top config
2143 09:27:35.843341 ===================================
2144 09:27:35.843485 DLL_ASYNC_EN = 0
2145 09:27:35.846476 ALL_SLAVE_EN = 0
2146 09:27:35.850243 NEW_RANK_MODE = 1
2147 09:27:35.853678 DLL_IDLE_MODE = 1
2148 09:27:35.856808 LP45_APHY_COMB_EN = 1
2149 09:27:35.856922 TX_ODT_DIS = 1
2150 09:27:35.860111 NEW_8X_MODE = 1
2151 09:27:35.863398 ===================================
2152 09:27:35.866818 ===================================
2153 09:27:35.870269 data_rate = 2400
2154 09:27:35.873536 CKR = 1
2155 09:27:35.876709 DQ_P2S_RATIO = 8
2156 09:27:35.880174 ===================================
2157 09:27:35.880289 CA_P2S_RATIO = 8
2158 09:27:35.883637 DQ_CA_OPEN = 0
2159 09:27:35.886448 DQ_SEMI_OPEN = 0
2160 09:27:35.890074 CA_SEMI_OPEN = 0
2161 09:27:35.893703 CA_FULL_RATE = 0
2162 09:27:35.896706 DQ_CKDIV4_EN = 0
2163 09:27:35.896820 CA_CKDIV4_EN = 0
2164 09:27:35.899828 CA_PREDIV_EN = 0
2165 09:27:35.903141 PH8_DLY = 17
2166 09:27:35.906756 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 09:27:35.910087 DQ_AAMCK_DIV = 4
2168 09:27:35.913534 CA_AAMCK_DIV = 4
2169 09:27:35.913646 CA_ADMCK_DIV = 4
2170 09:27:35.916714 DQ_TRACK_CA_EN = 0
2171 09:27:35.920074 CA_PICK = 1200
2172 09:27:35.923339 CA_MCKIO = 1200
2173 09:27:35.926700 MCKIO_SEMI = 0
2174 09:27:35.930236 PLL_FREQ = 2366
2175 09:27:35.933175 DQ_UI_PI_RATIO = 32
2176 09:27:35.933289 CA_UI_PI_RATIO = 0
2177 09:27:35.936738 ===================================
2178 09:27:35.940447 ===================================
2179 09:27:35.943454 memory_type:LPDDR4
2180 09:27:35.947141 GP_NUM : 10
2181 09:27:35.947250 SRAM_EN : 1
2182 09:27:35.950501 MD32_EN : 0
2183 09:27:35.953532 ===================================
2184 09:27:35.956630 [ANA_INIT] >>>>>>>>>>>>>>
2185 09:27:35.960175 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 09:27:35.963211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 09:27:35.966678 ===================================
2188 09:27:35.966781 data_rate = 2400,PCW = 0X5b00
2189 09:27:35.970259 ===================================
2190 09:27:35.973514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 09:27:35.980153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 09:27:35.986661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 09:27:35.990349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 09:27:35.993634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 09:27:35.996892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 09:27:36.000115 [ANA_INIT] flow start
2197 09:27:36.000227 [ANA_INIT] PLL >>>>>>>>
2198 09:27:36.003500 [ANA_INIT] PLL <<<<<<<<
2199 09:27:36.006794 [ANA_INIT] MIDPI >>>>>>>>
2200 09:27:36.006955 [ANA_INIT] MIDPI <<<<<<<<
2201 09:27:36.010121 [ANA_INIT] DLL >>>>>>>>
2202 09:27:36.013305 [ANA_INIT] DLL <<<<<<<<
2203 09:27:36.013393 [ANA_INIT] flow end
2204 09:27:36.020675 ============ LP4 DIFF to SE enter ============
2205 09:27:36.023537 ============ LP4 DIFF to SE exit ============
2206 09:27:36.027087 [ANA_INIT] <<<<<<<<<<<<<
2207 09:27:36.030108 [Flow] Enable top DCM control >>>>>
2208 09:27:36.033643 [Flow] Enable top DCM control <<<<<
2209 09:27:36.033759 Enable DLL master slave shuffle
2210 09:27:36.040155 ==============================================================
2211 09:27:36.043302 Gating Mode config
2212 09:27:36.046922 ==============================================================
2213 09:27:36.050363 Config description:
2214 09:27:36.060132 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 09:27:36.066745 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 09:27:36.069964 SELPH_MODE 0: By rank 1: By Phase
2217 09:27:36.076915 ==============================================================
2218 09:27:36.080172 GAT_TRACK_EN = 1
2219 09:27:36.083461 RX_GATING_MODE = 2
2220 09:27:36.087290 RX_GATING_TRACK_MODE = 2
2221 09:27:36.087449 SELPH_MODE = 1
2222 09:27:36.090220 PICG_EARLY_EN = 1
2223 09:27:36.093345 VALID_LAT_VALUE = 1
2224 09:27:36.100318 ==============================================================
2225 09:27:36.103278 Enter into Gating configuration >>>>
2226 09:27:36.107204 Exit from Gating configuration <<<<
2227 09:27:36.110568 Enter into DVFS_PRE_config >>>>>
2228 09:27:36.120119 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 09:27:36.123612 Exit from DVFS_PRE_config <<<<<
2230 09:27:36.126573 Enter into PICG configuration >>>>
2231 09:27:36.130233 Exit from PICG configuration <<<<
2232 09:27:36.133918 [RX_INPUT] configuration >>>>>
2233 09:27:36.136726 [RX_INPUT] configuration <<<<<
2234 09:27:36.140289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 09:27:36.147077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 09:27:36.153874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 09:27:36.160428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 09:27:36.163326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 09:27:36.170137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 09:27:36.173421 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 09:27:36.180609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 09:27:36.183321 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 09:27:36.186676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 09:27:36.190265 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 09:27:36.197134 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 09:27:36.200165 ===================================
2247 09:27:36.200262 LPDDR4 DRAM CONFIGURATION
2248 09:27:36.203619 ===================================
2249 09:27:36.207180 EX_ROW_EN[0] = 0x0
2250 09:27:36.210160 EX_ROW_EN[1] = 0x0
2251 09:27:36.210269 LP4Y_EN = 0x0
2252 09:27:36.213798 WORK_FSP = 0x0
2253 09:27:36.213885 WL = 0x4
2254 09:27:36.216983 RL = 0x4
2255 09:27:36.217067 BL = 0x2
2256 09:27:36.220364 RPST = 0x0
2257 09:27:36.220467 RD_PRE = 0x0
2258 09:27:36.223906 WR_PRE = 0x1
2259 09:27:36.223991 WR_PST = 0x0
2260 09:27:36.226877 DBI_WR = 0x0
2261 09:27:36.226965 DBI_RD = 0x0
2262 09:27:36.230170 OTF = 0x1
2263 09:27:36.233622 ===================================
2264 09:27:36.236861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 09:27:36.240306 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 09:27:36.246865 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 09:27:36.250446 ===================================
2268 09:27:36.250541 LPDDR4 DRAM CONFIGURATION
2269 09:27:36.253504 ===================================
2270 09:27:36.257013 EX_ROW_EN[0] = 0x10
2271 09:27:36.257134 EX_ROW_EN[1] = 0x0
2272 09:27:36.260664 LP4Y_EN = 0x0
2273 09:27:36.260775 WORK_FSP = 0x0
2274 09:27:36.263557 WL = 0x4
2275 09:27:36.267092 RL = 0x4
2276 09:27:36.267195 BL = 0x2
2277 09:27:36.270227 RPST = 0x0
2278 09:27:36.270334 RD_PRE = 0x0
2279 09:27:36.273903 WR_PRE = 0x1
2280 09:27:36.274012 WR_PST = 0x0
2281 09:27:36.276799 DBI_WR = 0x0
2282 09:27:36.276905 DBI_RD = 0x0
2283 09:27:36.280158 OTF = 0x1
2284 09:27:36.283415 ===================================
2285 09:27:36.287099 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 09:27:36.289975 ==
2287 09:27:36.293488 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 09:27:36.296771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 09:27:36.296887 ==
2290 09:27:36.300538 [Duty_Offset_Calibration]
2291 09:27:36.300647 B0:2 B1:0 CA:3
2292 09:27:36.300749
2293 09:27:36.303354 [DutyScan_Calibration_Flow] k_type=0
2294 09:27:36.313338
2295 09:27:36.313493 ==CLK 0==
2296 09:27:36.316332 Final CLK duty delay cell = 0
2297 09:27:36.319404 [0] MAX Duty = 5031%(X100), DQS PI = 12
2298 09:27:36.322958 [0] MIN Duty = 4875%(X100), DQS PI = 58
2299 09:27:36.323066 [0] AVG Duty = 4953%(X100)
2300 09:27:36.326496
2301 09:27:36.330062 CH0 CLK Duty spec in!! Max-Min= 156%
2302 09:27:36.333101 [DutyScan_Calibration_Flow] ====Done====
2303 09:27:36.333216
2304 09:27:36.336218 [DutyScan_Calibration_Flow] k_type=1
2305 09:27:36.351573
2306 09:27:36.351741 ==DQS 0 ==
2307 09:27:36.355059 Final DQS duty delay cell = 0
2308 09:27:36.358461 [0] MAX Duty = 5093%(X100), DQS PI = 12
2309 09:27:36.361830 [0] MIN Duty = 4907%(X100), DQS PI = 48
2310 09:27:36.364642 [0] AVG Duty = 5000%(X100)
2311 09:27:36.364752
2312 09:27:36.364845 ==DQS 1 ==
2313 09:27:36.368071 Final DQS duty delay cell = -4
2314 09:27:36.371295 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2315 09:27:36.374602 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2316 09:27:36.377868 [-4] AVG Duty = 4937%(X100)
2317 09:27:36.377982
2318 09:27:36.381675 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2319 09:27:36.381786
2320 09:27:36.385155 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2321 09:27:36.388358 [DutyScan_Calibration_Flow] ====Done====
2322 09:27:36.388470
2323 09:27:36.391352 [DutyScan_Calibration_Flow] k_type=3
2324 09:27:36.409340
2325 09:27:36.409488 ==DQM 0 ==
2326 09:27:36.412391 Final DQM duty delay cell = 0
2327 09:27:36.415919 [0] MAX Duty = 5124%(X100), DQS PI = 28
2328 09:27:36.419321 [0] MIN Duty = 4907%(X100), DQS PI = 0
2329 09:27:36.419448 [0] AVG Duty = 5015%(X100)
2330 09:27:36.422354
2331 09:27:36.422462 ==DQM 1 ==
2332 09:27:36.426080 Final DQM duty delay cell = 4
2333 09:27:36.429000 [4] MAX Duty = 5124%(X100), DQS PI = 50
2334 09:27:36.432491 [4] MIN Duty = 5031%(X100), DQS PI = 12
2335 09:27:36.432601 [4] AVG Duty = 5077%(X100)
2336 09:27:36.436064
2337 09:27:36.439159 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2338 09:27:36.439267
2339 09:27:36.442518 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2340 09:27:36.445499 [DutyScan_Calibration_Flow] ====Done====
2341 09:27:36.445600
2342 09:27:36.449133 [DutyScan_Calibration_Flow] k_type=2
2343 09:27:36.464112
2344 09:27:36.464273 ==DQ 0 ==
2345 09:27:36.467133 Final DQ duty delay cell = -4
2346 09:27:36.470619 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2347 09:27:36.473767 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2348 09:27:36.477208 [-4] AVG Duty = 4969%(X100)
2349 09:27:36.477298
2350 09:27:36.477361 ==DQ 1 ==
2351 09:27:36.480580 Final DQ duty delay cell = -4
2352 09:27:36.483849 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2353 09:27:36.487202 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2354 09:27:36.490628 [-4] AVG Duty = 4922%(X100)
2355 09:27:36.490719
2356 09:27:36.493984 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2357 09:27:36.494072
2358 09:27:36.497201 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2359 09:27:36.500729 [DutyScan_Calibration_Flow] ====Done====
2360 09:27:36.500817 ==
2361 09:27:36.504231 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 09:27:36.507365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 09:27:36.507487 ==
2364 09:27:36.510523 [Duty_Offset_Calibration]
2365 09:27:36.510603 B0:1 B1:-2 CA:0
2366 09:27:36.510665
2367 09:27:36.514009 [DutyScan_Calibration_Flow] k_type=0
2368 09:27:36.524418
2369 09:27:36.524571 ==CLK 0==
2370 09:27:36.527788 Final CLK duty delay cell = 0
2371 09:27:36.531012 [0] MAX Duty = 5062%(X100), DQS PI = 30
2372 09:27:36.534550 [0] MIN Duty = 4876%(X100), DQS PI = 2
2373 09:27:36.534648 [0] AVG Duty = 4969%(X100)
2374 09:27:36.538205
2375 09:27:36.538294 CH1 CLK Duty spec in!! Max-Min= 186%
2376 09:27:36.544727 [DutyScan_Calibration_Flow] ====Done====
2377 09:27:36.544822
2378 09:27:36.547852 [DutyScan_Calibration_Flow] k_type=1
2379 09:27:36.562845
2380 09:27:36.563008 ==DQS 0 ==
2381 09:27:36.566283 Final DQS duty delay cell = -4
2382 09:27:36.569370 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2383 09:27:36.572938 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2384 09:27:36.576114 [-4] AVG Duty = 4969%(X100)
2385 09:27:36.576209
2386 09:27:36.576274 ==DQS 1 ==
2387 09:27:36.579674 Final DQS duty delay cell = 0
2388 09:27:36.582611 [0] MAX Duty = 5062%(X100), DQS PI = 0
2389 09:27:36.586158 [0] MIN Duty = 4875%(X100), DQS PI = 26
2390 09:27:36.589710 [0] AVG Duty = 4968%(X100)
2391 09:27:36.589800
2392 09:27:36.592924 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2393 09:27:36.593009
2394 09:27:36.596336 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2395 09:27:36.599379 [DutyScan_Calibration_Flow] ====Done====
2396 09:27:36.599512
2397 09:27:36.602883 [DutyScan_Calibration_Flow] k_type=3
2398 09:27:36.619785
2399 09:27:36.619979 ==DQM 0 ==
2400 09:27:36.622955 Final DQM duty delay cell = 0
2401 09:27:36.626337 [0] MAX Duty = 5000%(X100), DQS PI = 24
2402 09:27:36.629560 [0] MIN Duty = 4844%(X100), DQS PI = 52
2403 09:27:36.629653 [0] AVG Duty = 4922%(X100)
2404 09:27:36.632852
2405 09:27:36.632939 ==DQM 1 ==
2406 09:27:36.636344 Final DQM duty delay cell = 0
2407 09:27:36.639644 [0] MAX Duty = 5031%(X100), DQS PI = 36
2408 09:27:36.642886 [0] MIN Duty = 4907%(X100), DQS PI = 2
2409 09:27:36.642978 [0] AVG Duty = 4969%(X100)
2410 09:27:36.643043
2411 09:27:36.649553 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2412 09:27:36.649658
2413 09:27:36.653182 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 09:27:36.656243 [DutyScan_Calibration_Flow] ====Done====
2415 09:27:36.656337
2416 09:27:36.659806 [DutyScan_Calibration_Flow] k_type=2
2417 09:27:36.676410
2418 09:27:36.676558 ==DQ 0 ==
2419 09:27:36.679224 Final DQ duty delay cell = 0
2420 09:27:36.683038 [0] MAX Duty = 5093%(X100), DQS PI = 20
2421 09:27:36.685867 [0] MIN Duty = 4938%(X100), DQS PI = 56
2422 09:27:36.685956 [0] AVG Duty = 5015%(X100)
2423 09:27:36.689063
2424 09:27:36.689146 ==DQ 1 ==
2425 09:27:36.692482 Final DQ duty delay cell = 0
2426 09:27:36.696077 [0] MAX Duty = 5125%(X100), DQS PI = 36
2427 09:27:36.699091 [0] MIN Duty = 4969%(X100), DQS PI = 26
2428 09:27:36.699201 [0] AVG Duty = 5047%(X100)
2429 09:27:36.699301
2430 09:27:36.703143 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2431 09:27:36.703257
2432 09:27:36.706146 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2433 09:27:36.712468 [DutyScan_Calibration_Flow] ====Done====
2434 09:27:36.715936 nWR fixed to 30
2435 09:27:36.716058 [ModeRegInit_LP4] CH0 RK0
2436 09:27:36.719346 [ModeRegInit_LP4] CH0 RK1
2437 09:27:36.722861 [ModeRegInit_LP4] CH1 RK0
2438 09:27:36.722968 [ModeRegInit_LP4] CH1 RK1
2439 09:27:36.726097 match AC timing 7
2440 09:27:36.729754 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 09:27:36.732441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 09:27:36.739672 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 09:27:36.742976 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 09:27:36.749002 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 09:27:36.749135 ==
2446 09:27:36.752554 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 09:27:36.755841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 09:27:36.755986 ==
2449 09:27:36.762571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 09:27:36.765992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 09:27:36.775854 [CA 0] Center 40 (10~71) winsize 62
2452 09:27:36.779144 [CA 1] Center 39 (9~70) winsize 62
2453 09:27:36.782556 [CA 2] Center 36 (6~66) winsize 61
2454 09:27:36.786188 [CA 3] Center 35 (5~66) winsize 62
2455 09:27:36.789732 [CA 4] Center 34 (4~65) winsize 62
2456 09:27:36.792717 [CA 5] Center 33 (3~64) winsize 62
2457 09:27:36.792829
2458 09:27:36.796324 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2459 09:27:36.796436
2460 09:27:36.799272 [CATrainingPosCal] consider 1 rank data
2461 09:27:36.802880 u2DelayCellTimex100 = 270/100 ps
2462 09:27:36.806313 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2463 09:27:36.809426 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2464 09:27:36.815979 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2465 09:27:36.819457 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 09:27:36.822671 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2467 09:27:36.826275 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2468 09:27:36.826386
2469 09:27:36.829425 CA PerBit enable=1, Macro0, CA PI delay=33
2470 09:27:36.829529
2471 09:27:36.832907 [CBTSetCACLKResult] CA Dly = 33
2472 09:27:36.833023 CS Dly: 7 (0~38)
2473 09:27:36.833127 ==
2474 09:27:36.836446 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 09:27:36.843337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 09:27:36.843494 ==
2477 09:27:36.846209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 09:27:36.852943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2479 09:27:36.862285 [CA 0] Center 40 (10~70) winsize 61
2480 09:27:36.865943 [CA 1] Center 40 (10~70) winsize 61
2481 09:27:36.868562 [CA 2] Center 35 (5~66) winsize 62
2482 09:27:36.872115 [CA 3] Center 35 (5~66) winsize 62
2483 09:27:36.875614 [CA 4] Center 34 (4~65) winsize 62
2484 09:27:36.878781 [CA 5] Center 33 (3~64) winsize 62
2485 09:27:36.878867
2486 09:27:36.882280 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 09:27:36.882361
2488 09:27:36.885107 [CATrainingPosCal] consider 2 rank data
2489 09:27:36.888483 u2DelayCellTimex100 = 270/100 ps
2490 09:27:36.892414 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2491 09:27:36.899429 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2492 09:27:36.901852 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2493 09:27:36.905569 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 09:27:36.908951 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2495 09:27:36.912015 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2496 09:27:36.912154
2497 09:27:36.915530 CA PerBit enable=1, Macro0, CA PI delay=33
2498 09:27:36.915616
2499 09:27:36.919004 [CBTSetCACLKResult] CA Dly = 33
2500 09:27:36.921946 CS Dly: 8 (0~40)
2501 09:27:36.922031
2502 09:27:36.925522 ----->DramcWriteLeveling(PI) begin...
2503 09:27:36.925611 ==
2504 09:27:36.928837 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 09:27:36.932279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 09:27:36.932371 ==
2507 09:27:36.935220 Write leveling (Byte 0): 34 => 34
2508 09:27:36.938783 Write leveling (Byte 1): 29 => 29
2509 09:27:36.941968 DramcWriteLeveling(PI) end<-----
2510 09:27:36.942061
2511 09:27:36.942125 ==
2512 09:27:36.945424 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 09:27:36.949086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 09:27:36.949176 ==
2515 09:27:36.952094 [Gating] SW mode calibration
2516 09:27:36.958548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 09:27:36.965185 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 09:27:36.968944 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 09:27:36.971896 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2520 09:27:36.978879 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 09:27:36.981928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 09:27:36.985387 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 09:27:36.988951 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 09:27:36.995597 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 09:27:36.998717 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2526 09:27:37.001764 1 0 0 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
2527 09:27:37.008493 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2528 09:27:37.011759 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 09:27:37.015605 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 09:27:37.022093 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 09:27:37.025472 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 09:27:37.029041 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 09:27:37.035426 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2534 09:27:37.038760 1 1 0 | B1->B0 | 2c2c 3737 | 0 1 | (1 1) (0 0)
2535 09:27:37.042200 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2536 09:27:37.048755 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 09:27:37.051742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 09:27:37.055301 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 09:27:37.062083 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 09:27:37.064981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 09:27:37.069011 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 09:27:37.075508 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2543 09:27:37.078954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 09:27:37.081936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 09:27:37.089065 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 09:27:37.091850 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 09:27:37.095566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 09:27:37.098489 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 09:27:37.105163 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 09:27:37.108834 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 09:27:37.111739 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 09:27:37.118439 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 09:27:37.121694 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 09:27:37.125228 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 09:27:37.131990 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:27:37.135138 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:27:37.138488 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 09:27:37.145330 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2559 09:27:37.148286 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 09:27:37.151994 Total UI for P1: 0, mck2ui 16
2561 09:27:37.155256 best dqsien dly found for B0: ( 1, 3, 30)
2562 09:27:37.158400 Total UI for P1: 0, mck2ui 16
2563 09:27:37.162018 best dqsien dly found for B1: ( 1, 4, 0)
2564 09:27:37.164905 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2565 09:27:37.168388 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 09:27:37.168513
2567 09:27:37.172002 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2568 09:27:37.175520 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 09:27:37.178876 [Gating] SW calibration Done
2570 09:27:37.178991 ==
2571 09:27:37.182087 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 09:27:37.185185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 09:27:37.185312 ==
2574 09:27:37.188401 RX Vref Scan: 0
2575 09:27:37.188543
2576 09:27:37.192032 RX Vref 0 -> 0, step: 1
2577 09:27:37.192137
2578 09:27:37.192228 RX Delay -40 -> 252, step: 8
2579 09:27:37.198540 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2580 09:27:37.201597 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2581 09:27:37.205252 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2582 09:27:37.208697 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2583 09:27:37.211635 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2584 09:27:37.218323 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2585 09:27:37.222096 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2586 09:27:37.225106 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2587 09:27:37.228364 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2588 09:27:37.231945 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2589 09:27:37.235036 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2590 09:27:37.242143 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2591 09:27:37.245062 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2592 09:27:37.248359 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2593 09:27:37.251644 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2594 09:27:37.258267 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2595 09:27:37.258464 ==
2596 09:27:37.261814 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 09:27:37.264862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 09:27:37.264982 ==
2599 09:27:37.265082 DQS Delay:
2600 09:27:37.268285 DQS0 = 0, DQS1 = 0
2601 09:27:37.268410 DQM Delay:
2602 09:27:37.271554 DQM0 = 112, DQM1 = 102
2603 09:27:37.271672 DQ Delay:
2604 09:27:37.275049 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2605 09:27:37.277996 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2606 09:27:37.281511 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2607 09:27:37.284582 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2608 09:27:37.284701
2609 09:27:37.284803
2610 09:27:37.284902 ==
2611 09:27:37.288056 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 09:27:37.294792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 09:27:37.294925 ==
2614 09:27:37.295029
2615 09:27:37.295130
2616 09:27:37.295229 TX Vref Scan disable
2617 09:27:37.298576 == TX Byte 0 ==
2618 09:27:37.301899 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2619 09:27:37.305409 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2620 09:27:37.308501 == TX Byte 1 ==
2621 09:27:37.312142 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2622 09:27:37.318762 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2623 09:27:37.318894 ==
2624 09:27:37.321745 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 09:27:37.325377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 09:27:37.325489 ==
2627 09:27:37.337143 TX Vref=22, minBit 1, minWin=25, winSum=418
2628 09:27:37.340064 TX Vref=24, minBit 1, minWin=25, winSum=421
2629 09:27:37.343367 TX Vref=26, minBit 7, minWin=25, winSum=425
2630 09:27:37.346510 TX Vref=28, minBit 4, minWin=26, winSum=432
2631 09:27:37.350156 TX Vref=30, minBit 10, minWin=26, winSum=430
2632 09:27:37.356616 TX Vref=32, minBit 2, minWin=26, winSum=430
2633 09:27:37.359726 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 28
2634 09:27:37.359863
2635 09:27:37.363149 Final TX Range 1 Vref 28
2636 09:27:37.363261
2637 09:27:37.363362 ==
2638 09:27:37.366536 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 09:27:37.370235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 09:27:37.373113 ==
2641 09:27:37.373217
2642 09:27:37.373308
2643 09:27:37.373407 TX Vref Scan disable
2644 09:27:37.376855 == TX Byte 0 ==
2645 09:27:37.380205 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2646 09:27:37.383268 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2647 09:27:37.386680 == TX Byte 1 ==
2648 09:27:37.390088 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2649 09:27:37.393655 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2650 09:27:37.396603
2651 09:27:37.396711 [DATLAT]
2652 09:27:37.396810 Freq=1200, CH0 RK0
2653 09:27:37.396899
2654 09:27:37.399859 DATLAT Default: 0xd
2655 09:27:37.399935 0, 0xFFFF, sum = 0
2656 09:27:37.403026 1, 0xFFFF, sum = 0
2657 09:27:37.403135 2, 0xFFFF, sum = 0
2658 09:27:37.406561 3, 0xFFFF, sum = 0
2659 09:27:37.406695 4, 0xFFFF, sum = 0
2660 09:27:37.410204 5, 0xFFFF, sum = 0
2661 09:27:37.413418 6, 0xFFFF, sum = 0
2662 09:27:37.413503 7, 0xFFFF, sum = 0
2663 09:27:37.416861 8, 0xFFFF, sum = 0
2664 09:27:37.416942 9, 0xFFFF, sum = 0
2665 09:27:37.420009 10, 0xFFFF, sum = 0
2666 09:27:37.420096 11, 0xFFFF, sum = 0
2667 09:27:37.423641 12, 0x0, sum = 1
2668 09:27:37.423729 13, 0x0, sum = 2
2669 09:27:37.426607 14, 0x0, sum = 3
2670 09:27:37.426691 15, 0x0, sum = 4
2671 09:27:37.426785 best_step = 13
2672 09:27:37.426845
2673 09:27:37.429785 ==
2674 09:27:37.433311 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 09:27:37.436687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 09:27:37.436780 ==
2677 09:27:37.436847 RX Vref Scan: 1
2678 09:27:37.436907
2679 09:27:37.440249 Set Vref Range= 32 -> 127
2680 09:27:37.440335
2681 09:27:37.443178 RX Vref 32 -> 127, step: 1
2682 09:27:37.443294
2683 09:27:37.446767 RX Delay -37 -> 252, step: 4
2684 09:27:37.446879
2685 09:27:37.450365 Set Vref, RX VrefLevel [Byte0]: 32
2686 09:27:37.453432 [Byte1]: 32
2687 09:27:37.453512
2688 09:27:37.456378 Set Vref, RX VrefLevel [Byte0]: 33
2689 09:27:37.459944 [Byte1]: 33
2690 09:27:37.463077
2691 09:27:37.463189 Set Vref, RX VrefLevel [Byte0]: 34
2692 09:27:37.466652 [Byte1]: 34
2693 09:27:37.471177
2694 09:27:37.471286 Set Vref, RX VrefLevel [Byte0]: 35
2695 09:27:37.474968 [Byte1]: 35
2696 09:27:37.479018
2697 09:27:37.479135 Set Vref, RX VrefLevel [Byte0]: 36
2698 09:27:37.482773 [Byte1]: 36
2699 09:27:37.486978
2700 09:27:37.487089 Set Vref, RX VrefLevel [Byte0]: 37
2701 09:27:37.490384 [Byte1]: 37
2702 09:27:37.495140
2703 09:27:37.495251 Set Vref, RX VrefLevel [Byte0]: 38
2704 09:27:37.498798 [Byte1]: 38
2705 09:27:37.503264
2706 09:27:37.503410 Set Vref, RX VrefLevel [Byte0]: 39
2707 09:27:37.506609 [Byte1]: 39
2708 09:27:37.511363
2709 09:27:37.511519 Set Vref, RX VrefLevel [Byte0]: 40
2710 09:27:37.514615 [Byte1]: 40
2711 09:27:37.519267
2712 09:27:37.519377 Set Vref, RX VrefLevel [Byte0]: 41
2713 09:27:37.522932 [Byte1]: 41
2714 09:27:37.527157
2715 09:27:37.527270 Set Vref, RX VrefLevel [Byte0]: 42
2716 09:27:37.530335 [Byte1]: 42
2717 09:27:37.535019
2718 09:27:37.535114 Set Vref, RX VrefLevel [Byte0]: 43
2719 09:27:37.538423 [Byte1]: 43
2720 09:27:37.543219
2721 09:27:37.543352 Set Vref, RX VrefLevel [Byte0]: 44
2722 09:27:37.546886 [Byte1]: 44
2723 09:27:37.551348
2724 09:27:37.551493 Set Vref, RX VrefLevel [Byte0]: 45
2725 09:27:37.554536 [Byte1]: 45
2726 09:27:37.559245
2727 09:27:37.559376 Set Vref, RX VrefLevel [Byte0]: 46
2728 09:27:37.562964 [Byte1]: 46
2729 09:27:37.567804
2730 09:27:37.567916 Set Vref, RX VrefLevel [Byte0]: 47
2731 09:27:37.570457 [Byte1]: 47
2732 09:27:37.575309
2733 09:27:37.575466 Set Vref, RX VrefLevel [Byte0]: 48
2734 09:27:37.578901 [Byte1]: 48
2735 09:27:37.583613
2736 09:27:37.583708 Set Vref, RX VrefLevel [Byte0]: 49
2737 09:27:37.586683 [Byte1]: 49
2738 09:27:37.591424
2739 09:27:37.591553 Set Vref, RX VrefLevel [Byte0]: 50
2740 09:27:37.594340 [Byte1]: 50
2741 09:27:37.599123
2742 09:27:37.599236 Set Vref, RX VrefLevel [Byte0]: 51
2743 09:27:37.602617 [Byte1]: 51
2744 09:27:37.607377
2745 09:27:37.607543 Set Vref, RX VrefLevel [Byte0]: 52
2746 09:27:37.610634 [Byte1]: 52
2747 09:27:37.615317
2748 09:27:37.615470 Set Vref, RX VrefLevel [Byte0]: 53
2749 09:27:37.618585 [Byte1]: 53
2750 09:27:37.623176
2751 09:27:37.623294 Set Vref, RX VrefLevel [Byte0]: 54
2752 09:27:37.626313 [Byte1]: 54
2753 09:27:37.630958
2754 09:27:37.631065 Set Vref, RX VrefLevel [Byte0]: 55
2755 09:27:37.634732 [Byte1]: 55
2756 09:27:37.638968
2757 09:27:37.639091 Set Vref, RX VrefLevel [Byte0]: 56
2758 09:27:37.642575 [Byte1]: 56
2759 09:27:37.647088
2760 09:27:37.647203 Set Vref, RX VrefLevel [Byte0]: 57
2761 09:27:37.650330 [Byte1]: 57
2762 09:27:37.655511
2763 09:27:37.655624 Set Vref, RX VrefLevel [Byte0]: 58
2764 09:27:37.658397 [Byte1]: 58
2765 09:27:37.663261
2766 09:27:37.663381 Set Vref, RX VrefLevel [Byte0]: 59
2767 09:27:37.666330 [Byte1]: 59
2768 09:27:37.671108
2769 09:27:37.671220 Set Vref, RX VrefLevel [Byte0]: 60
2770 09:27:37.674851 [Byte1]: 60
2771 09:27:37.679592
2772 09:27:37.679700 Set Vref, RX VrefLevel [Byte0]: 61
2773 09:27:37.682302 [Byte1]: 61
2774 09:27:37.687597
2775 09:27:37.687722 Set Vref, RX VrefLevel [Byte0]: 62
2776 09:27:37.690656 [Byte1]: 62
2777 09:27:37.695424
2778 09:27:37.695553 Set Vref, RX VrefLevel [Byte0]: 63
2779 09:27:37.698414 [Byte1]: 63
2780 09:27:37.703256
2781 09:27:37.703364 Set Vref, RX VrefLevel [Byte0]: 64
2782 09:27:37.706862 [Byte1]: 64
2783 09:27:37.711079
2784 09:27:37.711183 Set Vref, RX VrefLevel [Byte0]: 65
2785 09:27:37.714621 [Byte1]: 65
2786 09:27:37.719231
2787 09:27:37.719342 Set Vref, RX VrefLevel [Byte0]: 66
2788 09:27:37.722702 [Byte1]: 66
2789 09:27:37.727315
2790 09:27:37.727448 Set Vref, RX VrefLevel [Byte0]: 67
2791 09:27:37.730828 [Byte1]: 67
2792 09:27:37.735027
2793 09:27:37.735129 Set Vref, RX VrefLevel [Byte0]: 68
2794 09:27:37.738267 [Byte1]: 68
2795 09:27:37.742960
2796 09:27:37.743074 Set Vref, RX VrefLevel [Byte0]: 69
2797 09:27:37.746331 [Byte1]: 69
2798 09:27:37.751195
2799 09:27:37.751307 Set Vref, RX VrefLevel [Byte0]: 70
2800 09:27:37.754330 [Byte1]: 70
2801 09:27:37.759006
2802 09:27:37.759120 Set Vref, RX VrefLevel [Byte0]: 71
2803 09:27:37.762627 [Byte1]: 71
2804 09:27:37.767073
2805 09:27:37.767192 Set Vref, RX VrefLevel [Byte0]: 72
2806 09:27:37.770502 [Byte1]: 72
2807 09:27:37.775286
2808 09:27:37.775422 Set Vref, RX VrefLevel [Byte0]: 73
2809 09:27:37.778391 [Byte1]: 73
2810 09:27:37.783116
2811 09:27:37.783220 Set Vref, RX VrefLevel [Byte0]: 74
2812 09:27:37.786626 [Byte1]: 74
2813 09:27:37.791303
2814 09:27:37.791453 Final RX Vref Byte 0 = 64 to rank0
2815 09:27:37.794960 Final RX Vref Byte 1 = 57 to rank0
2816 09:27:37.798020 Final RX Vref Byte 0 = 64 to rank1
2817 09:27:37.801372 Final RX Vref Byte 1 = 57 to rank1==
2818 09:27:37.804933 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 09:27:37.811553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 09:27:37.811668 ==
2821 09:27:37.811749 DQS Delay:
2822 09:27:37.811839 DQS0 = 0, DQS1 = 0
2823 09:27:37.814478 DQM Delay:
2824 09:27:37.814554 DQM0 = 112, DQM1 = 102
2825 09:27:37.817954 DQ Delay:
2826 09:27:37.821674 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2827 09:27:37.824726 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =120
2828 09:27:37.827728 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2829 09:27:37.831025 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =110
2830 09:27:37.831132
2831 09:27:37.831223
2832 09:27:37.838298 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2833 09:27:37.841172 CH0 RK0: MR19=403, MR18=FF
2834 09:27:37.848232 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2835 09:27:37.848396
2836 09:27:37.851314 ----->DramcWriteLeveling(PI) begin...
2837 09:27:37.851438 ==
2838 09:27:37.854849 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 09:27:37.858068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 09:27:37.858181 ==
2841 09:27:37.861502 Write leveling (Byte 0): 30 => 30
2842 09:27:37.864724 Write leveling (Byte 1): 31 => 31
2843 09:27:37.868148 DramcWriteLeveling(PI) end<-----
2844 09:27:37.868270
2845 09:27:37.868336 ==
2846 09:27:37.871283 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 09:27:37.874463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 09:27:37.874553 ==
2849 09:27:37.878243 [Gating] SW mode calibration
2850 09:27:37.884821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 09:27:37.891229 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 09:27:37.894780 0 15 0 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
2853 09:27:37.901242 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 09:27:37.904839 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 09:27:37.907887 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 09:27:37.914321 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 09:27:37.917921 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 09:27:37.921381 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2859 09:27:37.927757 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2860 09:27:37.930982 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2861 09:27:37.934657 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 09:27:37.938061 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 09:27:37.944811 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 09:27:37.948116 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 09:27:37.951350 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 09:27:37.957741 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2867 09:27:37.961556 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2868 09:27:37.964800 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2869 09:27:37.971109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 09:27:37.974712 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 09:27:37.977981 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 09:27:37.984558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 09:27:37.987949 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 09:27:37.991371 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 09:27:37.997960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 09:27:38.000889 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 09:27:38.004347 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:27:38.011031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:27:38.014366 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:27:38.017977 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 09:27:38.024744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 09:27:38.027996 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 09:27:38.030923 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 09:27:38.034238 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 09:27:38.041366 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 09:27:38.044269 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 09:27:38.047925 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 09:27:38.054692 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 09:27:38.057940 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 09:27:38.061549 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2891 09:27:38.067842 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2892 09:27:38.068010 Total UI for P1: 0, mck2ui 16
2893 09:27:38.074728 best dqsien dly found for B0: ( 1, 3, 24)
2894 09:27:38.077709 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 09:27:38.081098 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 09:27:38.084561 Total UI for P1: 0, mck2ui 16
2897 09:27:38.087920 best dqsien dly found for B1: ( 1, 3, 30)
2898 09:27:38.091286 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2899 09:27:38.094344 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2900 09:27:38.094464
2901 09:27:38.097843 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2902 09:27:38.104593 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2903 09:27:38.104764 [Gating] SW calibration Done
2904 09:27:38.104877 ==
2905 09:27:38.108188 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 09:27:38.114869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 09:27:38.115013 ==
2908 09:27:38.115109 RX Vref Scan: 0
2909 09:27:38.115211
2910 09:27:38.118023 RX Vref 0 -> 0, step: 1
2911 09:27:38.118121
2912 09:27:38.121487 RX Delay -40 -> 252, step: 8
2913 09:27:38.124471 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2914 09:27:38.128217 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2915 09:27:38.131833 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2916 09:27:38.137860 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2917 09:27:38.141509 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
2918 09:27:38.144410 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2919 09:27:38.148012 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2920 09:27:38.151039 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2921 09:27:38.154741 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2922 09:27:38.161083 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2923 09:27:38.164556 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2924 09:27:38.167825 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2925 09:27:38.171113 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2926 09:27:38.174594 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2927 09:27:38.181508 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2928 09:27:38.184919 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2929 09:27:38.185045 ==
2930 09:27:38.188083 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 09:27:38.191126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 09:27:38.191266 ==
2933 09:27:38.194541 DQS Delay:
2934 09:27:38.194677 DQS0 = 0, DQS1 = 0
2935 09:27:38.194773 DQM Delay:
2936 09:27:38.198039 DQM0 = 111, DQM1 = 102
2937 09:27:38.198135 DQ Delay:
2938 09:27:38.201178 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2939 09:27:38.204526 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
2940 09:27:38.207919 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2941 09:27:38.211229 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2942 09:27:38.214873
2943 09:27:38.214982
2944 09:27:38.215056 ==
2945 09:27:38.218071 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 09:27:38.221077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 09:27:38.221167 ==
2948 09:27:38.221235
2949 09:27:38.221296
2950 09:27:38.224783 TX Vref Scan disable
2951 09:27:38.224863 == TX Byte 0 ==
2952 09:27:38.231374 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2953 09:27:38.234920 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2954 09:27:38.235018 == TX Byte 1 ==
2955 09:27:38.241431 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2956 09:27:38.245062 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2957 09:27:38.245159 ==
2958 09:27:38.247911 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 09:27:38.251478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 09:27:38.251573 ==
2961 09:27:38.263352 TX Vref=22, minBit 0, minWin=26, winSum=426
2962 09:27:38.267126 TX Vref=24, minBit 0, minWin=26, winSum=430
2963 09:27:38.270102 TX Vref=26, minBit 3, minWin=26, winSum=433
2964 09:27:38.273401 TX Vref=28, minBit 1, minWin=27, winSum=441
2965 09:27:38.277094 TX Vref=30, minBit 8, minWin=26, winSum=442
2966 09:27:38.280022 TX Vref=32, minBit 13, minWin=26, winSum=439
2967 09:27:38.287010 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 28
2968 09:27:38.287158
2969 09:27:38.290512 Final TX Range 1 Vref 28
2970 09:27:38.290625
2971 09:27:38.290724 ==
2972 09:27:38.293616 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 09:27:38.297005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 09:27:38.297117 ==
2975 09:27:38.297218
2976 09:27:38.300119
2977 09:27:38.300227 TX Vref Scan disable
2978 09:27:38.303743 == TX Byte 0 ==
2979 09:27:38.306930 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2980 09:27:38.309956 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2981 09:27:38.313361 == TX Byte 1 ==
2982 09:27:38.316874 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2983 09:27:38.320077 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2984 09:27:38.320202
2985 09:27:38.323650 [DATLAT]
2986 09:27:38.323782 Freq=1200, CH0 RK1
2987 09:27:38.323882
2988 09:27:38.327072 DATLAT Default: 0xd
2989 09:27:38.327196 0, 0xFFFF, sum = 0
2990 09:27:38.330605 1, 0xFFFF, sum = 0
2991 09:27:38.330735 2, 0xFFFF, sum = 0
2992 09:27:38.333494 3, 0xFFFF, sum = 0
2993 09:27:38.333612 4, 0xFFFF, sum = 0
2994 09:27:38.337131 5, 0xFFFF, sum = 0
2995 09:27:38.337254 6, 0xFFFF, sum = 0
2996 09:27:38.340572 7, 0xFFFF, sum = 0
2997 09:27:38.340680 8, 0xFFFF, sum = 0
2998 09:27:38.343621 9, 0xFFFF, sum = 0
2999 09:27:38.347312 10, 0xFFFF, sum = 0
3000 09:27:38.347446 11, 0xFFFF, sum = 0
3001 09:27:38.350316 12, 0x0, sum = 1
3002 09:27:38.350404 13, 0x0, sum = 2
3003 09:27:38.350471 14, 0x0, sum = 3
3004 09:27:38.353818 15, 0x0, sum = 4
3005 09:27:38.353909 best_step = 13
3006 09:27:38.353974
3007 09:27:38.356968 ==
3008 09:27:38.357054 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 09:27:38.363338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 09:27:38.363483 ==
3011 09:27:38.363585 RX Vref Scan: 0
3012 09:27:38.363676
3013 09:27:38.366831 RX Vref 0 -> 0, step: 1
3014 09:27:38.366938
3015 09:27:38.369944 RX Delay -37 -> 252, step: 4
3016 09:27:38.373383 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3017 09:27:38.380326 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3018 09:27:38.383555 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3019 09:27:38.387113 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3020 09:27:38.390212 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3021 09:27:38.393941 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3022 09:27:38.396850 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3023 09:27:38.403499 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3024 09:27:38.406522 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3025 09:27:38.410354 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3026 09:27:38.413336 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3027 09:27:38.417003 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3028 09:27:38.423338 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3029 09:27:38.426687 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3030 09:27:38.430116 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3031 09:27:38.433389 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3032 09:27:38.433508 ==
3033 09:27:38.436645 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 09:27:38.443675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 09:27:38.443836 ==
3036 09:27:38.443938 DQS Delay:
3037 09:27:38.444026 DQS0 = 0, DQS1 = 0
3038 09:27:38.446718 DQM Delay:
3039 09:27:38.446831 DQM0 = 110, DQM1 = 102
3040 09:27:38.450096 DQ Delay:
3041 09:27:38.453176 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3042 09:27:38.456555 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =120
3043 09:27:38.460208 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3044 09:27:38.463296 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3045 09:27:38.463449
3046 09:27:38.463577
3047 09:27:38.473308 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3048 09:27:38.473459 CH0 RK1: MR19=403, MR18=15FC
3049 09:27:38.480195 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3050 09:27:38.483079 [RxdqsGatingPostProcess] freq 1200
3051 09:27:38.489913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 09:27:38.493099 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 09:27:38.496506 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 09:27:38.499657 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 09:27:38.503455 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 09:27:38.503573 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 09:27:38.506386 best DQS1 dly(2T, 0.5T) = (0, 11)
3058 09:27:38.509459 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 09:27:38.512954 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3060 09:27:38.516619 Pre-setting of DQS Precalculation
3061 09:27:38.523207 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 09:27:38.523335 ==
3063 09:27:38.526171 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 09:27:38.529226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 09:27:38.529337 ==
3066 09:27:38.536398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 09:27:38.542685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3068 09:27:38.549591 [CA 0] Center 37 (7~67) winsize 61
3069 09:27:38.552997 [CA 1] Center 37 (7~68) winsize 62
3070 09:27:38.556153 [CA 2] Center 34 (4~64) winsize 61
3071 09:27:38.560213 [CA 3] Center 33 (3~64) winsize 62
3072 09:27:38.563014 [CA 4] Center 34 (4~64) winsize 61
3073 09:27:38.566012 [CA 5] Center 33 (3~63) winsize 61
3074 09:27:38.566138
3075 09:27:38.569543 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3076 09:27:38.569655
3077 09:27:38.573019 [CATrainingPosCal] consider 1 rank data
3078 09:27:38.575911 u2DelayCellTimex100 = 270/100 ps
3079 09:27:38.579408 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3080 09:27:38.582559 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3081 09:27:38.589255 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3082 09:27:38.592948 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3083 09:27:38.596332 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 09:27:38.599331 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3085 09:27:38.599447
3086 09:27:38.602584 CA PerBit enable=1, Macro0, CA PI delay=33
3087 09:27:38.602704
3088 09:27:38.606411 [CBTSetCACLKResult] CA Dly = 33
3089 09:27:38.606529 CS Dly: 5 (0~36)
3090 09:27:38.609883 ==
3091 09:27:38.609996 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 09:27:38.616074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 09:27:38.616194 ==
3094 09:27:38.619493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 09:27:38.626032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3096 09:27:38.635228 [CA 0] Center 37 (7~67) winsize 61
3097 09:27:38.638572 [CA 1] Center 37 (7~68) winsize 62
3098 09:27:38.641998 [CA 2] Center 34 (4~65) winsize 62
3099 09:27:38.645409 [CA 3] Center 33 (3~64) winsize 62
3100 09:27:38.648222 [CA 4] Center 34 (4~65) winsize 62
3101 09:27:38.651857 [CA 5] Center 33 (3~63) winsize 61
3102 09:27:38.651975
3103 09:27:38.655180 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3104 09:27:38.655289
3105 09:27:38.658357 [CATrainingPosCal] consider 2 rank data
3106 09:27:38.661838 u2DelayCellTimex100 = 270/100 ps
3107 09:27:38.665292 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3108 09:27:38.668156 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 09:27:38.675119 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 09:27:38.678768 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 09:27:38.681815 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 09:27:38.684973 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3113 09:27:38.685096
3114 09:27:38.688510 CA PerBit enable=1, Macro0, CA PI delay=33
3115 09:27:38.688621
3116 09:27:38.692053 [CBTSetCACLKResult] CA Dly = 33
3117 09:27:38.692160 CS Dly: 7 (0~40)
3118 09:27:38.692257
3119 09:27:38.695141 ----->DramcWriteLeveling(PI) begin...
3120 09:27:38.698499 ==
3121 09:27:38.698611 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 09:27:38.705155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 09:27:38.705284 ==
3124 09:27:38.708542 Write leveling (Byte 0): 27 => 27
3125 09:27:38.712106 Write leveling (Byte 1): 27 => 27
3126 09:27:38.712219 DramcWriteLeveling(PI) end<-----
3127 09:27:38.715370
3128 09:27:38.715503 ==
3129 09:27:38.718846 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 09:27:38.721911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 09:27:38.722026 ==
3132 09:27:38.725498 [Gating] SW mode calibration
3133 09:27:38.732026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 09:27:38.735056 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 09:27:38.742252 0 15 0 | B1->B0 | 2d2d 2827 | 1 1 | (1 1) (0 0)
3136 09:27:38.745480 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 09:27:38.748369 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 09:27:38.755246 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 09:27:38.758763 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 09:27:38.761875 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 09:27:38.768920 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 09:27:38.772322 0 15 28 | B1->B0 | 2929 2d2d | 0 0 | (1 0) (0 1)
3143 09:27:38.775265 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 09:27:38.781799 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 09:27:38.785198 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 09:27:38.788640 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 09:27:38.794955 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 09:27:38.798938 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 09:27:38.801711 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3150 09:27:38.808863 1 0 28 | B1->B0 | 4141 3636 | 0 0 | (0 0) (0 0)
3151 09:27:38.811615 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3152 09:27:38.815167 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 09:27:38.818786 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 09:27:38.825472 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 09:27:38.828517 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 09:27:38.832005 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 09:27:38.838671 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 09:27:38.842171 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3159 09:27:38.845224 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3160 09:27:38.852230 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:27:38.855530 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 09:27:38.858301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 09:27:38.865614 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 09:27:38.868411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 09:27:38.872048 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 09:27:38.878565 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 09:27:38.881718 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 09:27:38.885150 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 09:27:38.891698 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 09:27:38.895358 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 09:27:38.898705 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 09:27:38.905440 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 09:27:38.908932 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 09:27:38.911863 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3175 09:27:38.915276 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3176 09:27:38.918473 Total UI for P1: 0, mck2ui 16
3177 09:27:38.922044 best dqsien dly found for B1: ( 1, 3, 28)
3178 09:27:38.928496 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 09:27:38.931624 Total UI for P1: 0, mck2ui 16
3180 09:27:38.935110 best dqsien dly found for B0: ( 1, 3, 30)
3181 09:27:38.938958 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3182 09:27:38.941771 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3183 09:27:38.941882
3184 09:27:38.944914 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3185 09:27:38.948495 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3186 09:27:38.952127 [Gating] SW calibration Done
3187 09:27:38.952239 ==
3188 09:27:38.955515 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 09:27:38.958432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 09:27:38.958539 ==
3191 09:27:38.961825 RX Vref Scan: 0
3192 09:27:38.961972
3193 09:27:38.962067 RX Vref 0 -> 0, step: 1
3194 09:27:38.962158
3195 09:27:38.964962 RX Delay -40 -> 252, step: 8
3196 09:27:38.972262 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3197 09:27:38.975185 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3198 09:27:38.978549 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3199 09:27:38.981601 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3200 09:27:38.985116 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3201 09:27:38.988745 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3202 09:27:38.995494 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3203 09:27:38.998652 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3204 09:27:39.002162 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3205 09:27:39.005242 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3206 09:27:39.008874 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3207 09:27:39.014878 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3208 09:27:39.018422 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3209 09:27:39.021857 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3210 09:27:39.025041 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3211 09:27:39.028502 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3212 09:27:39.031699 ==
3213 09:27:39.031802 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 09:27:39.038434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 09:27:39.038590 ==
3216 09:27:39.038686 DQS Delay:
3217 09:27:39.041814 DQS0 = 0, DQS1 = 0
3218 09:27:39.041908 DQM Delay:
3219 09:27:39.045133 DQM0 = 114, DQM1 = 106
3220 09:27:39.045235 DQ Delay:
3221 09:27:39.048596 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =115
3222 09:27:39.052033 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3223 09:27:39.054943 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3224 09:27:39.057954 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3225 09:27:39.058063
3226 09:27:39.058155
3227 09:27:39.058244 ==
3228 09:27:39.061427 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 09:27:39.068070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 09:27:39.068183 ==
3231 09:27:39.068274
3232 09:27:39.068362
3233 09:27:39.068446 TX Vref Scan disable
3234 09:27:39.071822 == TX Byte 0 ==
3235 09:27:39.074776 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3236 09:27:39.081594 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3237 09:27:39.081730 == TX Byte 1 ==
3238 09:27:39.085027 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3239 09:27:39.088093 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3240 09:27:39.091637 ==
3241 09:27:39.095178 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 09:27:39.098316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 09:27:39.098430 ==
3244 09:27:39.109820 TX Vref=22, minBit 9, minWin=24, winSum=406
3245 09:27:39.112602 TX Vref=24, minBit 10, minWin=24, winSum=409
3246 09:27:39.116404 TX Vref=26, minBit 10, minWin=24, winSum=415
3247 09:27:39.119221 TX Vref=28, minBit 9, minWin=25, winSum=421
3248 09:27:39.123085 TX Vref=30, minBit 9, minWin=24, winSum=423
3249 09:27:39.129615 TX Vref=32, minBit 10, minWin=24, winSum=418
3250 09:27:39.132563 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
3251 09:27:39.132675
3252 09:27:39.136167 Final TX Range 1 Vref 28
3253 09:27:39.136274
3254 09:27:39.136368 ==
3255 09:27:39.139641 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 09:27:39.142562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 09:27:39.142673 ==
3258 09:27:39.145903
3259 09:27:39.146009
3260 09:27:39.146098 TX Vref Scan disable
3261 09:27:39.149267 == TX Byte 0 ==
3262 09:27:39.153081 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3263 09:27:39.156093 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3264 09:27:39.159382 == TX Byte 1 ==
3265 09:27:39.162473 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3266 09:27:39.166048 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3267 09:27:39.169564
3268 09:27:39.169681 [DATLAT]
3269 09:27:39.169773 Freq=1200, CH1 RK0
3270 09:27:39.169863
3271 09:27:39.172533 DATLAT Default: 0xd
3272 09:27:39.172634 0, 0xFFFF, sum = 0
3273 09:27:39.175987 1, 0xFFFF, sum = 0
3274 09:27:39.176095 2, 0xFFFF, sum = 0
3275 09:27:39.179349 3, 0xFFFF, sum = 0
3276 09:27:39.179493 4, 0xFFFF, sum = 0
3277 09:27:39.182562 5, 0xFFFF, sum = 0
3278 09:27:39.186048 6, 0xFFFF, sum = 0
3279 09:27:39.186183 7, 0xFFFF, sum = 0
3280 09:27:39.189067 8, 0xFFFF, sum = 0
3281 09:27:39.189179 9, 0xFFFF, sum = 0
3282 09:27:39.192712 10, 0xFFFF, sum = 0
3283 09:27:39.192825 11, 0xFFFF, sum = 0
3284 09:27:39.196297 12, 0x0, sum = 1
3285 09:27:39.196407 13, 0x0, sum = 2
3286 09:27:39.199359 14, 0x0, sum = 3
3287 09:27:39.199536 15, 0x0, sum = 4
3288 09:27:39.199631 best_step = 13
3289 09:27:39.202761
3290 09:27:39.202865 ==
3291 09:27:39.206170 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 09:27:39.209224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 09:27:39.209343 ==
3294 09:27:39.209441 RX Vref Scan: 1
3295 09:27:39.209530
3296 09:27:39.212646 Set Vref Range= 32 -> 127
3297 09:27:39.212748
3298 09:27:39.216350 RX Vref 32 -> 127, step: 1
3299 09:27:39.216460
3300 09:27:39.219184 RX Delay -21 -> 252, step: 4
3301 09:27:39.219284
3302 09:27:39.222903 Set Vref, RX VrefLevel [Byte0]: 32
3303 09:27:39.225781 [Byte1]: 32
3304 09:27:39.225886
3305 09:27:39.229518 Set Vref, RX VrefLevel [Byte0]: 33
3306 09:27:39.232454 [Byte1]: 33
3307 09:27:39.236185
3308 09:27:39.236294 Set Vref, RX VrefLevel [Byte0]: 34
3309 09:27:39.239037 [Byte1]: 34
3310 09:27:39.243876
3311 09:27:39.243996 Set Vref, RX VrefLevel [Byte0]: 35
3312 09:27:39.246850 [Byte1]: 35
3313 09:27:39.251492
3314 09:27:39.251602 Set Vref, RX VrefLevel [Byte0]: 36
3315 09:27:39.255054 [Byte1]: 36
3316 09:27:39.259830
3317 09:27:39.259949 Set Vref, RX VrefLevel [Byte0]: 37
3318 09:27:39.262925 [Byte1]: 37
3319 09:27:39.267454
3320 09:27:39.267542 Set Vref, RX VrefLevel [Byte0]: 38
3321 09:27:39.270945 [Byte1]: 38
3322 09:27:39.275228
3323 09:27:39.275341 Set Vref, RX VrefLevel [Byte0]: 39
3324 09:27:39.278605 [Byte1]: 39
3325 09:27:39.283519
3326 09:27:39.283640 Set Vref, RX VrefLevel [Byte0]: 40
3327 09:27:39.286435 [Byte1]: 40
3328 09:27:39.291337
3329 09:27:39.291499 Set Vref, RX VrefLevel [Byte0]: 41
3330 09:27:39.295457 [Byte1]: 41
3331 09:27:39.299389
3332 09:27:39.299500 Set Vref, RX VrefLevel [Byte0]: 42
3333 09:27:39.302564 [Byte1]: 42
3334 09:27:39.307161
3335 09:27:39.307287 Set Vref, RX VrefLevel [Byte0]: 43
3336 09:27:39.310704 [Byte1]: 43
3337 09:27:39.314841
3338 09:27:39.314955 Set Vref, RX VrefLevel [Byte0]: 44
3339 09:27:39.318320 [Byte1]: 44
3340 09:27:39.322940
3341 09:27:39.323055 Set Vref, RX VrefLevel [Byte0]: 45
3342 09:27:39.326686 [Byte1]: 45
3343 09:27:39.330749
3344 09:27:39.330857 Set Vref, RX VrefLevel [Byte0]: 46
3345 09:27:39.334284 [Byte1]: 46
3346 09:27:39.339211
3347 09:27:39.339317 Set Vref, RX VrefLevel [Byte0]: 47
3348 09:27:39.342071 [Byte1]: 47
3349 09:27:39.347193
3350 09:27:39.347306 Set Vref, RX VrefLevel [Byte0]: 48
3351 09:27:39.350002 [Byte1]: 48
3352 09:27:39.354690
3353 09:27:39.354836 Set Vref, RX VrefLevel [Byte0]: 49
3354 09:27:39.357854 [Byte1]: 49
3355 09:27:39.362620
3356 09:27:39.362740 Set Vref, RX VrefLevel [Byte0]: 50
3357 09:27:39.366092 [Byte1]: 50
3358 09:27:39.370376
3359 09:27:39.370471 Set Vref, RX VrefLevel [Byte0]: 51
3360 09:27:39.373953 [Byte1]: 51
3361 09:27:39.378180
3362 09:27:39.378296 Set Vref, RX VrefLevel [Byte0]: 52
3363 09:27:39.381739 [Byte1]: 52
3364 09:27:39.386222
3365 09:27:39.386337 Set Vref, RX VrefLevel [Byte0]: 53
3366 09:27:39.389749 [Byte1]: 53
3367 09:27:39.394220
3368 09:27:39.394342 Set Vref, RX VrefLevel [Byte0]: 54
3369 09:27:39.397712 [Byte1]: 54
3370 09:27:39.402208
3371 09:27:39.402324 Set Vref, RX VrefLevel [Byte0]: 55
3372 09:27:39.405584 [Byte1]: 55
3373 09:27:39.410164
3374 09:27:39.410286 Set Vref, RX VrefLevel [Byte0]: 56
3375 09:27:39.413535 [Byte1]: 56
3376 09:27:39.417855
3377 09:27:39.418006 Set Vref, RX VrefLevel [Byte0]: 57
3378 09:27:39.421411 [Byte1]: 57
3379 09:27:39.426128
3380 09:27:39.426244 Set Vref, RX VrefLevel [Byte0]: 58
3381 09:27:39.429105 [Byte1]: 58
3382 09:27:39.433906
3383 09:27:39.434026 Set Vref, RX VrefLevel [Byte0]: 59
3384 09:27:39.437134 [Byte1]: 59
3385 09:27:39.441970
3386 09:27:39.442092 Set Vref, RX VrefLevel [Byte0]: 60
3387 09:27:39.445506 [Byte1]: 60
3388 09:27:39.449812
3389 09:27:39.449926 Set Vref, RX VrefLevel [Byte0]: 61
3390 09:27:39.453324 [Byte1]: 61
3391 09:27:39.457569
3392 09:27:39.457682 Set Vref, RX VrefLevel [Byte0]: 62
3393 09:27:39.461065 [Byte1]: 62
3394 09:27:39.465855
3395 09:27:39.465973 Set Vref, RX VrefLevel [Byte0]: 63
3396 09:27:39.468832 [Byte1]: 63
3397 09:27:39.473659
3398 09:27:39.473773 Set Vref, RX VrefLevel [Byte0]: 64
3399 09:27:39.476766 [Byte1]: 64
3400 09:27:39.481430
3401 09:27:39.481551 Set Vref, RX VrefLevel [Byte0]: 65
3402 09:27:39.484937 [Byte1]: 65
3403 09:27:39.489592
3404 09:27:39.489708 Set Vref, RX VrefLevel [Byte0]: 66
3405 09:27:39.492954 [Byte1]: 66
3406 09:27:39.497300
3407 09:27:39.497416 Set Vref, RX VrefLevel [Byte0]: 67
3408 09:27:39.500784 [Byte1]: 67
3409 09:27:39.505467
3410 09:27:39.505584 Final RX Vref Byte 0 = 56 to rank0
3411 09:27:39.508497 Final RX Vref Byte 1 = 56 to rank0
3412 09:27:39.512011 Final RX Vref Byte 0 = 56 to rank1
3413 09:27:39.515134 Final RX Vref Byte 1 = 56 to rank1==
3414 09:27:39.518529 Dram Type= 6, Freq= 0, CH_1, rank 0
3415 09:27:39.524891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 09:27:39.525016 ==
3417 09:27:39.525112 DQS Delay:
3418 09:27:39.525200 DQS0 = 0, DQS1 = 0
3419 09:27:39.528617 DQM Delay:
3420 09:27:39.528725 DQM0 = 114, DQM1 = 106
3421 09:27:39.531854 DQ Delay:
3422 09:27:39.535096 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3423 09:27:39.538419 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =112
3424 09:27:39.541793 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =100
3425 09:27:39.545103 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3426 09:27:39.545216
3427 09:27:39.545310
3428 09:27:39.551802 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3429 09:27:39.554846 CH1 RK0: MR19=303, MR18=ECF4
3430 09:27:39.561618 CH1_RK0: MR19=0x303, MR18=0xECF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3431 09:27:39.561746
3432 09:27:39.565096 ----->DramcWriteLeveling(PI) begin...
3433 09:27:39.565215 ==
3434 09:27:39.568501 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 09:27:39.571550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 09:27:39.575184 ==
3437 09:27:39.575294 Write leveling (Byte 0): 24 => 24
3438 09:27:39.578172 Write leveling (Byte 1): 27 => 27
3439 09:27:39.581688 DramcWriteLeveling(PI) end<-----
3440 09:27:39.581782
3441 09:27:39.581847 ==
3442 09:27:39.585241 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 09:27:39.591956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 09:27:39.592086 ==
3445 09:27:39.592184 [Gating] SW mode calibration
3446 09:27:39.601857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3447 09:27:39.605237 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3448 09:27:39.608407 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3449 09:27:39.615135 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 09:27:39.618824 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 09:27:39.621569 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 09:27:39.628807 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 09:27:39.631669 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3454 09:27:39.634975 0 15 24 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
3455 09:27:39.642056 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3456 09:27:39.644996 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 09:27:39.648159 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 09:27:39.654759 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 09:27:39.658597 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 09:27:39.661664 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 09:27:39.668357 1 0 20 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
3462 09:27:39.671972 1 0 24 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3463 09:27:39.675233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 09:27:39.681941 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 09:27:39.685543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 09:27:39.688432 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 09:27:39.692137 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 09:27:39.698221 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 09:27:39.701864 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 09:27:39.705360 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3471 09:27:39.711807 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3472 09:27:39.714791 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 09:27:39.718264 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 09:27:39.724936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 09:27:39.728019 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 09:27:39.731635 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 09:27:39.738084 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 09:27:39.741441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 09:27:39.744801 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 09:27:39.751465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 09:27:39.755055 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 09:27:39.758009 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 09:27:39.764604 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 09:27:39.767854 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 09:27:39.771201 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3486 09:27:39.777450 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3487 09:27:39.781010 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3488 09:27:39.784476 Total UI for P1: 0, mck2ui 16
3489 09:27:39.787868 best dqsien dly found for B0: ( 1, 3, 22)
3490 09:27:39.790835 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 09:27:39.794205 Total UI for P1: 0, mck2ui 16
3492 09:27:39.797340 best dqsien dly found for B1: ( 1, 3, 26)
3493 09:27:39.800757 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3494 09:27:39.804367 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3495 09:27:39.804487
3496 09:27:39.810813 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3497 09:27:39.814214 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3498 09:27:39.817862 [Gating] SW calibration Done
3499 09:27:39.817975 ==
3500 09:27:39.821149 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 09:27:39.824524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 09:27:39.824633 ==
3503 09:27:39.824727 RX Vref Scan: 0
3504 09:27:39.824818
3505 09:27:39.827544 RX Vref 0 -> 0, step: 1
3506 09:27:39.827634
3507 09:27:39.831112 RX Delay -40 -> 252, step: 8
3508 09:27:39.834388 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3509 09:27:39.837790 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3510 09:27:39.841016 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3511 09:27:39.847409 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3512 09:27:39.850814 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3513 09:27:39.854211 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3514 09:27:39.857703 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3515 09:27:39.860645 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3516 09:27:39.867367 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3517 09:27:39.870910 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3518 09:27:39.873907 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3519 09:27:39.877511 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3520 09:27:39.880433 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3521 09:27:39.887163 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3522 09:27:39.890617 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3523 09:27:39.893592 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3524 09:27:39.893688 ==
3525 09:27:39.897222 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 09:27:39.903759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 09:27:39.903892 ==
3528 09:27:39.903989 DQS Delay:
3529 09:27:39.904082 DQS0 = 0, DQS1 = 0
3530 09:27:39.907272 DQM Delay:
3531 09:27:39.907374 DQM0 = 110, DQM1 = 109
3532 09:27:39.910608 DQ Delay:
3533 09:27:39.913836 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3534 09:27:39.917029 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3535 09:27:39.920033 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3536 09:27:39.923788 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3537 09:27:39.923876
3538 09:27:39.923940
3539 09:27:39.924007 ==
3540 09:27:39.926628 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 09:27:39.930502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 09:27:39.930609 ==
3543 09:27:39.930704
3544 09:27:39.933628
3545 09:27:39.933731 TX Vref Scan disable
3546 09:27:39.936693 == TX Byte 0 ==
3547 09:27:39.940176 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3548 09:27:39.943923 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3549 09:27:39.946839 == TX Byte 1 ==
3550 09:27:39.950361 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 09:27:39.953918 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 09:27:39.954031 ==
3553 09:27:39.956869 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 09:27:39.963260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 09:27:39.963410 ==
3556 09:27:39.974179 TX Vref=22, minBit 9, minWin=25, winSum=415
3557 09:27:39.977687 TX Vref=24, minBit 3, minWin=26, winSum=424
3558 09:27:39.980908 TX Vref=26, minBit 0, minWin=26, winSum=428
3559 09:27:39.983922 TX Vref=28, minBit 1, minWin=26, winSum=431
3560 09:27:39.987574 TX Vref=30, minBit 7, minWin=26, winSum=433
3561 09:27:39.994177 TX Vref=32, minBit 1, minWin=26, winSum=428
3562 09:27:39.997062 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 30
3563 09:27:39.997172
3564 09:27:40.000544 Final TX Range 1 Vref 30
3565 09:27:40.000654
3566 09:27:40.000745 ==
3567 09:27:40.003705 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 09:27:40.007110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 09:27:40.007215 ==
3570 09:27:40.010346
3571 09:27:40.010452
3572 09:27:40.010520 TX Vref Scan disable
3573 09:27:40.013563 == TX Byte 0 ==
3574 09:27:40.016924 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3575 09:27:40.023886 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3576 09:27:40.024014 == TX Byte 1 ==
3577 09:27:40.026773 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 09:27:40.034001 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 09:27:40.034148
3580 09:27:40.034219 [DATLAT]
3581 09:27:40.034279 Freq=1200, CH1 RK1
3582 09:27:40.034339
3583 09:27:40.036775 DATLAT Default: 0xd
3584 09:27:40.036880 0, 0xFFFF, sum = 0
3585 09:27:40.040171 1, 0xFFFF, sum = 0
3586 09:27:40.043583 2, 0xFFFF, sum = 0
3587 09:27:40.043682 3, 0xFFFF, sum = 0
3588 09:27:40.046999 4, 0xFFFF, sum = 0
3589 09:27:40.047109 5, 0xFFFF, sum = 0
3590 09:27:40.050120 6, 0xFFFF, sum = 0
3591 09:27:40.050225 7, 0xFFFF, sum = 0
3592 09:27:40.053260 8, 0xFFFF, sum = 0
3593 09:27:40.053364 9, 0xFFFF, sum = 0
3594 09:27:40.056613 10, 0xFFFF, sum = 0
3595 09:27:40.056698 11, 0xFFFF, sum = 0
3596 09:27:40.060153 12, 0x0, sum = 1
3597 09:27:40.060264 13, 0x0, sum = 2
3598 09:27:40.063783 14, 0x0, sum = 3
3599 09:27:40.063893 15, 0x0, sum = 4
3600 09:27:40.066607 best_step = 13
3601 09:27:40.066711
3602 09:27:40.066803 ==
3603 09:27:40.069704 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 09:27:40.073119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 09:27:40.073227 ==
3606 09:27:40.076747 RX Vref Scan: 0
3607 09:27:40.076845
3608 09:27:40.076938 RX Vref 0 -> 0, step: 1
3609 09:27:40.077025
3610 09:27:40.079805 RX Delay -21 -> 252, step: 4
3611 09:27:40.086438 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3612 09:27:40.089933 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3613 09:27:40.093000 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3614 09:27:40.096558 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3615 09:27:40.099566 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3616 09:27:40.106281 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3617 09:27:40.109750 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3618 09:27:40.113125 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3619 09:27:40.116663 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3620 09:27:40.119800 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3621 09:27:40.123282 iDelay=195, Bit 10, Center 112 (43 ~ 182) 140
3622 09:27:40.129521 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3623 09:27:40.133180 iDelay=195, Bit 12, Center 118 (51 ~ 186) 136
3624 09:27:40.136393 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3625 09:27:40.139418 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3626 09:27:40.146241 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3627 09:27:40.146356 ==
3628 09:27:40.149529 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 09:27:40.152721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 09:27:40.152813 ==
3631 09:27:40.152879 DQS Delay:
3632 09:27:40.156358 DQS0 = 0, DQS1 = 0
3633 09:27:40.156456 DQM Delay:
3634 09:27:40.159537 DQM0 = 110, DQM1 = 109
3635 09:27:40.159624 DQ Delay:
3636 09:27:40.162797 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3637 09:27:40.166335 DQ4 =106, DQ5 =118, DQ6 =120, DQ7 =110
3638 09:27:40.169347 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
3639 09:27:40.172940 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =116
3640 09:27:40.173033
3641 09:27:40.173098
3642 09:27:40.182433 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3643 09:27:40.186038 CH1 RK1: MR19=304, MR18=FA0A
3644 09:27:40.192601 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3645 09:27:40.195806 [RxdqsGatingPostProcess] freq 1200
3646 09:27:40.199332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3647 09:27:40.202388 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 09:27:40.206075 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 09:27:40.209178 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 09:27:40.212248 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 09:27:40.215719 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 09:27:40.218814 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 09:27:40.222489 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 09:27:40.226035 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 09:27:40.228843 Pre-setting of DQS Precalculation
3656 09:27:40.232485 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3657 09:27:40.238985 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3658 09:27:40.248876 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3659 09:27:40.249032
3660 09:27:40.249132
3661 09:27:40.252085 [Calibration Summary] 2400 Mbps
3662 09:27:40.252190 CH 0, Rank 0
3663 09:27:40.255408 SW Impedance : PASS
3664 09:27:40.255571 DUTY Scan : NO K
3665 09:27:40.258905 ZQ Calibration : PASS
3666 09:27:40.262087 Jitter Meter : NO K
3667 09:27:40.262196 CBT Training : PASS
3668 09:27:40.265203 Write leveling : PASS
3669 09:27:40.265303 RX DQS gating : PASS
3670 09:27:40.268703 RX DQ/DQS(RDDQC) : PASS
3671 09:27:40.272043 TX DQ/DQS : PASS
3672 09:27:40.272148 RX DATLAT : PASS
3673 09:27:40.275355 RX DQ/DQS(Engine): PASS
3674 09:27:40.278815 TX OE : NO K
3675 09:27:40.278935 All Pass.
3676 09:27:40.279028
3677 09:27:40.279122 CH 0, Rank 1
3678 09:27:40.282263 SW Impedance : PASS
3679 09:27:40.285473 DUTY Scan : NO K
3680 09:27:40.285591 ZQ Calibration : PASS
3681 09:27:40.288843 Jitter Meter : NO K
3682 09:27:40.291886 CBT Training : PASS
3683 09:27:40.291994 Write leveling : PASS
3684 09:27:40.295305 RX DQS gating : PASS
3685 09:27:40.298467 RX DQ/DQS(RDDQC) : PASS
3686 09:27:40.298548 TX DQ/DQS : PASS
3687 09:27:40.301917 RX DATLAT : PASS
3688 09:27:40.305463 RX DQ/DQS(Engine): PASS
3689 09:27:40.305563 TX OE : NO K
3690 09:27:40.305664 All Pass.
3691 09:27:40.308518
3692 09:27:40.308614 CH 1, Rank 0
3693 09:27:40.312093 SW Impedance : PASS
3694 09:27:40.312166 DUTY Scan : NO K
3695 09:27:40.315642 ZQ Calibration : PASS
3696 09:27:40.315712 Jitter Meter : NO K
3697 09:27:40.318487 CBT Training : PASS
3698 09:27:40.322230 Write leveling : PASS
3699 09:27:40.322331 RX DQS gating : PASS
3700 09:27:40.325329 RX DQ/DQS(RDDQC) : PASS
3701 09:27:40.328851 TX DQ/DQS : PASS
3702 09:27:40.328921 RX DATLAT : PASS
3703 09:27:40.331952 RX DQ/DQS(Engine): PASS
3704 09:27:40.335362 TX OE : NO K
3705 09:27:40.335469 All Pass.
3706 09:27:40.335533
3707 09:27:40.335625 CH 1, Rank 1
3708 09:27:40.338800 SW Impedance : PASS
3709 09:27:40.341810 DUTY Scan : NO K
3710 09:27:40.341928 ZQ Calibration : PASS
3711 09:27:40.345547 Jitter Meter : NO K
3712 09:27:40.348374 CBT Training : PASS
3713 09:27:40.348448 Write leveling : PASS
3714 09:27:40.352391 RX DQS gating : PASS
3715 09:27:40.352485 RX DQ/DQS(RDDQC) : PASS
3716 09:27:40.355209 TX DQ/DQS : PASS
3717 09:27:40.358275 RX DATLAT : PASS
3718 09:27:40.358383 RX DQ/DQS(Engine): PASS
3719 09:27:40.362118 TX OE : NO K
3720 09:27:40.362222 All Pass.
3721 09:27:40.362312
3722 09:27:40.365236 DramC Write-DBI off
3723 09:27:40.368461 PER_BANK_REFRESH: Hybrid Mode
3724 09:27:40.368565 TX_TRACKING: ON
3725 09:27:40.378279 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3726 09:27:40.381705 [FAST_K] Save calibration result to emmc
3727 09:27:40.385014 dramc_set_vcore_voltage set vcore to 650000
3728 09:27:40.388261 Read voltage for 600, 5
3729 09:27:40.388377 Vio18 = 0
3730 09:27:40.391889 Vcore = 650000
3731 09:27:40.391972 Vdram = 0
3732 09:27:40.392036 Vddq = 0
3733 09:27:40.392095 Vmddr = 0
3734 09:27:40.398259 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3735 09:27:40.401598 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3736 09:27:40.405006 MEM_TYPE=3, freq_sel=19
3737 09:27:40.408301 sv_algorithm_assistance_LP4_1600
3738 09:27:40.411671 ============ PULL DRAM RESETB DOWN ============
3739 09:27:40.418294 ========== PULL DRAM RESETB DOWN end =========
3740 09:27:40.421394 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3741 09:27:40.424895 ===================================
3742 09:27:40.428506 LPDDR4 DRAM CONFIGURATION
3743 09:27:40.431496 ===================================
3744 09:27:40.431607 EX_ROW_EN[0] = 0x0
3745 09:27:40.434904 EX_ROW_EN[1] = 0x0
3746 09:27:40.435003 LP4Y_EN = 0x0
3747 09:27:40.438505 WORK_FSP = 0x0
3748 09:27:40.438601 WL = 0x2
3749 09:27:40.441657 RL = 0x2
3750 09:27:40.441747 BL = 0x2
3751 09:27:40.444519 RPST = 0x0
3752 09:27:40.444625 RD_PRE = 0x0
3753 09:27:40.447972 WR_PRE = 0x1
3754 09:27:40.451411 WR_PST = 0x0
3755 09:27:40.451510 DBI_WR = 0x0
3756 09:27:40.454403 DBI_RD = 0x0
3757 09:27:40.454483 OTF = 0x1
3758 09:27:40.457957 ===================================
3759 09:27:40.461191 ===================================
3760 09:27:40.461273 ANA top config
3761 09:27:40.464757 ===================================
3762 09:27:40.467920 DLL_ASYNC_EN = 0
3763 09:27:40.471474 ALL_SLAVE_EN = 1
3764 09:27:40.474677 NEW_RANK_MODE = 1
3765 09:27:40.477568 DLL_IDLE_MODE = 1
3766 09:27:40.477650 LP45_APHY_COMB_EN = 1
3767 09:27:40.481111 TX_ODT_DIS = 1
3768 09:27:40.484332 NEW_8X_MODE = 1
3769 09:27:40.487475 ===================================
3770 09:27:40.490870 ===================================
3771 09:27:40.494372 data_rate = 1200
3772 09:27:40.497840 CKR = 1
3773 09:27:40.497925 DQ_P2S_RATIO = 8
3774 09:27:40.501161 ===================================
3775 09:27:40.504235 CA_P2S_RATIO = 8
3776 09:27:40.507670 DQ_CA_OPEN = 0
3777 09:27:40.511172 DQ_SEMI_OPEN = 0
3778 09:27:40.513981 CA_SEMI_OPEN = 0
3779 09:27:40.517326 CA_FULL_RATE = 0
3780 09:27:40.517411 DQ_CKDIV4_EN = 1
3781 09:27:40.521028 CA_CKDIV4_EN = 1
3782 09:27:40.524318 CA_PREDIV_EN = 0
3783 09:27:40.527455 PH8_DLY = 0
3784 09:27:40.531098 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3785 09:27:40.533996 DQ_AAMCK_DIV = 4
3786 09:27:40.534078 CA_AAMCK_DIV = 4
3787 09:27:40.537450 CA_ADMCK_DIV = 4
3788 09:27:40.540500 DQ_TRACK_CA_EN = 0
3789 09:27:40.544105 CA_PICK = 600
3790 09:27:40.547626 CA_MCKIO = 600
3791 09:27:40.550962 MCKIO_SEMI = 0
3792 09:27:40.554050 PLL_FREQ = 2288
3793 09:27:40.554132 DQ_UI_PI_RATIO = 32
3794 09:27:40.557731 CA_UI_PI_RATIO = 0
3795 09:27:40.560769 ===================================
3796 09:27:40.564067 ===================================
3797 09:27:40.567140 memory_type:LPDDR4
3798 09:27:40.570686 GP_NUM : 10
3799 09:27:40.570801 SRAM_EN : 1
3800 09:27:40.574337 MD32_EN : 0
3801 09:27:40.577319 ===================================
3802 09:27:40.580884 [ANA_INIT] >>>>>>>>>>>>>>
3803 09:27:40.580965 <<<<<< [CONFIGURE PHASE]: ANA_TX
3804 09:27:40.587226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3805 09:27:40.590471 ===================================
3806 09:27:40.590567 data_rate = 1200,PCW = 0X5800
3807 09:27:40.593808 ===================================
3808 09:27:40.596933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3809 09:27:40.603917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 09:27:40.610418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 09:27:40.613745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3812 09:27:40.616960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3813 09:27:40.620288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3814 09:27:40.623714 [ANA_INIT] flow start
3815 09:27:40.623819 [ANA_INIT] PLL >>>>>>>>
3816 09:27:40.627178 [ANA_INIT] PLL <<<<<<<<
3817 09:27:40.630007 [ANA_INIT] MIDPI >>>>>>>>
3818 09:27:40.633594 [ANA_INIT] MIDPI <<<<<<<<
3819 09:27:40.633696 [ANA_INIT] DLL >>>>>>>>
3820 09:27:40.637242 [ANA_INIT] flow end
3821 09:27:40.640144 ============ LP4 DIFF to SE enter ============
3822 09:27:40.643712 ============ LP4 DIFF to SE exit ============
3823 09:27:40.646759 [ANA_INIT] <<<<<<<<<<<<<
3824 09:27:40.650231 [Flow] Enable top DCM control >>>>>
3825 09:27:40.653901 [Flow] Enable top DCM control <<<<<
3826 09:27:40.656801 Enable DLL master slave shuffle
3827 09:27:40.663582 ==============================================================
3828 09:27:40.663678 Gating Mode config
3829 09:27:40.670098 ==============================================================
3830 09:27:40.670212 Config description:
3831 09:27:40.679596 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3832 09:27:40.686267 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3833 09:27:40.692814 SELPH_MODE 0: By rank 1: By Phase
3834 09:27:40.696350 ==============================================================
3835 09:27:40.699852 GAT_TRACK_EN = 1
3836 09:27:40.703234 RX_GATING_MODE = 2
3837 09:27:40.706605 RX_GATING_TRACK_MODE = 2
3838 09:27:40.709481 SELPH_MODE = 1
3839 09:27:40.712685 PICG_EARLY_EN = 1
3840 09:27:40.716303 VALID_LAT_VALUE = 1
3841 09:27:40.722828 ==============================================================
3842 09:27:40.726368 Enter into Gating configuration >>>>
3843 09:27:40.729561 Exit from Gating configuration <<<<
3844 09:27:40.729665 Enter into DVFS_PRE_config >>>>>
3845 09:27:40.742972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3846 09:27:40.746188 Exit from DVFS_PRE_config <<<<<
3847 09:27:40.749572 Enter into PICG configuration >>>>
3848 09:27:40.752689 Exit from PICG configuration <<<<
3849 09:27:40.752802 [RX_INPUT] configuration >>>>>
3850 09:27:40.756252 [RX_INPUT] configuration <<<<<
3851 09:27:40.762703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3852 09:27:40.768040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3853 09:27:40.773041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 09:27:40.779250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 09:27:40.785935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 09:27:40.792573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 09:27:40.795674 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3858 09:27:40.799171 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3859 09:27:40.806313 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3860 09:27:40.809162 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3861 09:27:40.812582 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3862 09:27:40.816147 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3863 09:27:40.819222 ===================================
3864 09:27:40.822559 LPDDR4 DRAM CONFIGURATION
3865 09:27:40.825784 ===================================
3866 09:27:40.829449 EX_ROW_EN[0] = 0x0
3867 09:27:40.829551 EX_ROW_EN[1] = 0x0
3868 09:27:40.832642 LP4Y_EN = 0x0
3869 09:27:40.832746 WORK_FSP = 0x0
3870 09:27:40.835896 WL = 0x2
3871 09:27:40.835997 RL = 0x2
3872 09:27:40.839157 BL = 0x2
3873 09:27:40.839269 RPST = 0x0
3874 09:27:40.842645 RD_PRE = 0x0
3875 09:27:40.842749 WR_PRE = 0x1
3876 09:27:40.845628 WR_PST = 0x0
3877 09:27:40.848730 DBI_WR = 0x0
3878 09:27:40.848830 DBI_RD = 0x0
3879 09:27:40.852253 OTF = 0x1
3880 09:27:40.855519 ===================================
3881 09:27:40.858727 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3882 09:27:40.862353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3883 09:27:40.865330 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 09:27:40.868841 ===================================
3885 09:27:40.872524 LPDDR4 DRAM CONFIGURATION
3886 09:27:40.875352 ===================================
3887 09:27:40.879140 EX_ROW_EN[0] = 0x10
3888 09:27:40.879243 EX_ROW_EN[1] = 0x0
3889 09:27:40.882156 LP4Y_EN = 0x0
3890 09:27:40.882257 WORK_FSP = 0x0
3891 09:27:40.885863 WL = 0x2
3892 09:27:40.885966 RL = 0x2
3893 09:27:40.888843 BL = 0x2
3894 09:27:40.888944 RPST = 0x0
3895 09:27:40.891953 RD_PRE = 0x0
3896 09:27:40.892045 WR_PRE = 0x1
3897 09:27:40.895596 WR_PST = 0x0
3898 09:27:40.895699 DBI_WR = 0x0
3899 09:27:40.898631 DBI_RD = 0x0
3900 09:27:40.898730 OTF = 0x1
3901 09:27:40.902136 ===================================
3902 09:27:40.908578 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3903 09:27:40.913817 nWR fixed to 30
3904 09:27:40.917253 [ModeRegInit_LP4] CH0 RK0
3905 09:27:40.917359 [ModeRegInit_LP4] CH0 RK1
3906 09:27:40.920116 [ModeRegInit_LP4] CH1 RK0
3907 09:27:40.923795 [ModeRegInit_LP4] CH1 RK1
3908 09:27:40.923874 match AC timing 17
3909 09:27:40.930153 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3910 09:27:40.933903 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3911 09:27:40.937253 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3912 09:27:40.943350 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3913 09:27:40.947068 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3914 09:27:40.947156 ==
3915 09:27:40.950172 Dram Type= 6, Freq= 0, CH_0, rank 0
3916 09:27:40.953600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3917 09:27:40.953682 ==
3918 09:27:40.960179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3919 09:27:40.966576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3920 09:27:40.969829 [CA 0] Center 37 (7~67) winsize 61
3921 09:27:40.973278 [CA 1] Center 36 (6~67) winsize 62
3922 09:27:40.976601 [CA 2] Center 35 (5~65) winsize 61
3923 09:27:40.980078 [CA 3] Center 35 (5~65) winsize 61
3924 09:27:40.983143 [CA 4] Center 34 (4~65) winsize 62
3925 09:27:40.986571 [CA 5] Center 34 (3~65) winsize 63
3926 09:27:40.986650
3927 09:27:40.989995 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3928 09:27:40.990101
3929 09:27:40.993447 [CATrainingPosCal] consider 1 rank data
3930 09:27:40.996459 u2DelayCellTimex100 = 270/100 ps
3931 09:27:41.000112 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3932 09:27:41.003132 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3933 09:27:41.006762 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3934 09:27:41.009557 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3935 09:27:41.013389 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3936 09:27:41.019732 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3937 09:27:41.019824
3938 09:27:41.022996 CA PerBit enable=1, Macro0, CA PI delay=34
3939 09:27:41.023120
3940 09:27:41.026304 [CBTSetCACLKResult] CA Dly = 34
3941 09:27:41.026407 CS Dly: 5 (0~36)
3942 09:27:41.026491 ==
3943 09:27:41.029974 Dram Type= 6, Freq= 0, CH_0, rank 1
3944 09:27:41.033058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3945 09:27:41.036519 ==
3946 09:27:41.040220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3947 09:27:41.046354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3948 09:27:41.049981 [CA 0] Center 37 (7~67) winsize 61
3949 09:27:41.052870 [CA 1] Center 36 (6~67) winsize 62
3950 09:27:41.056649 [CA 2] Center 35 (5~65) winsize 61
3951 09:27:41.060002 [CA 3] Center 35 (5~65) winsize 61
3952 09:27:41.063199 [CA 4] Center 34 (4~65) winsize 62
3953 09:27:41.066813 [CA 5] Center 33 (3~64) winsize 62
3954 09:27:41.066895
3955 09:27:41.069960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3956 09:27:41.070035
3957 09:27:41.073350 [CATrainingPosCal] consider 2 rank data
3958 09:27:41.076240 u2DelayCellTimex100 = 270/100 ps
3959 09:27:41.079847 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3960 09:27:41.083335 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3961 09:27:41.086440 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3962 09:27:41.093298 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3963 09:27:41.096617 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 09:27:41.099831 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 09:27:41.099920
3966 09:27:41.102890 CA PerBit enable=1, Macro0, CA PI delay=33
3967 09:27:41.103022
3968 09:27:41.106494 [CBTSetCACLKResult] CA Dly = 33
3969 09:27:41.106596 CS Dly: 6 (0~38)
3970 09:27:41.106685
3971 09:27:41.109383 ----->DramcWriteLeveling(PI) begin...
3972 09:27:41.109468 ==
3973 09:27:41.113017 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 09:27:41.119633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 09:27:41.119718 ==
3976 09:27:41.122632 Write leveling (Byte 0): 30 => 30
3977 09:27:41.126175 Write leveling (Byte 1): 30 => 30
3978 09:27:41.126284 DramcWriteLeveling(PI) end<-----
3979 09:27:41.126374
3980 09:27:41.129422 ==
3981 09:27:41.132705 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 09:27:41.136472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 09:27:41.136583 ==
3984 09:27:41.139402 [Gating] SW mode calibration
3985 09:27:41.146102 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3986 09:27:41.149500 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3987 09:27:41.156369 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 09:27:41.159282 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 09:27:41.162769 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 09:27:41.169342 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3991 09:27:41.172774 0 9 16 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
3992 09:27:41.176309 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3993 09:27:41.182837 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 09:27:41.186401 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 09:27:41.189456 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 09:27:41.196016 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 09:27:41.199443 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 09:27:41.202629 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3999 09:27:41.209015 0 10 16 | B1->B0 | 3232 3838 | 0 0 | (0 0) (0 0)
4000 09:27:41.212646 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 09:27:41.215702 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 09:27:41.222170 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 09:27:41.225708 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 09:27:41.228843 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 09:27:41.235376 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 09:27:41.239160 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 09:27:41.242519 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4008 09:27:41.248966 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 09:27:41.252004 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 09:27:41.255517 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 09:27:41.261913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 09:27:41.265276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 09:27:41.268743 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 09:27:41.272195 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 09:27:41.279204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 09:27:41.282179 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 09:27:41.285505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 09:27:41.292196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 09:27:41.295218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 09:27:41.298688 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 09:27:41.305229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 09:27:41.308909 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4023 09:27:41.312023 Total UI for P1: 0, mck2ui 16
4024 09:27:41.314959 best dqsien dly found for B0: ( 0, 13, 10)
4025 09:27:41.318263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4026 09:27:41.325347 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 09:27:41.328609 Total UI for P1: 0, mck2ui 16
4028 09:27:41.331708 best dqsien dly found for B1: ( 0, 13, 16)
4029 09:27:41.335302 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4030 09:27:41.338271 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4031 09:27:41.338384
4032 09:27:41.341477 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4033 09:27:41.344738 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4034 09:27:41.348173 [Gating] SW calibration Done
4035 09:27:41.348276 ==
4036 09:27:41.351365 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 09:27:41.355062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 09:27:41.355171 ==
4039 09:27:41.358577 RX Vref Scan: 0
4040 09:27:41.358674
4041 09:27:41.361394 RX Vref 0 -> 0, step: 1
4042 09:27:41.361509
4043 09:27:41.361609 RX Delay -230 -> 252, step: 16
4044 09:27:41.368288 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4045 09:27:41.371176 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4046 09:27:41.374459 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4047 09:27:41.377796 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4048 09:27:41.384570 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4049 09:27:41.388142 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4050 09:27:41.391654 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4051 09:27:41.394663 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4052 09:27:41.398358 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4053 09:27:41.404847 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4054 09:27:41.407978 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4055 09:27:41.411363 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4056 09:27:41.414578 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4057 09:27:41.421059 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4058 09:27:41.424610 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4059 09:27:41.427836 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4060 09:27:41.427917 ==
4061 09:27:41.431158 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 09:27:41.434611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 09:27:41.437724 ==
4064 09:27:41.437811 DQS Delay:
4065 09:27:41.437875 DQS0 = 0, DQS1 = 0
4066 09:27:41.441184 DQM Delay:
4067 09:27:41.441289 DQM0 = 38, DQM1 = 30
4068 09:27:41.444588 DQ Delay:
4069 09:27:41.447866 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4070 09:27:41.447962 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4071 09:27:41.451045 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4072 09:27:41.457648 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4073 09:27:41.457730
4074 09:27:41.457793
4075 09:27:41.457852 ==
4076 09:27:41.461040 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 09:27:41.464323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 09:27:41.464431 ==
4079 09:27:41.464553
4080 09:27:41.464647
4081 09:27:41.467867 TX Vref Scan disable
4082 09:27:41.467951 == TX Byte 0 ==
4083 09:27:41.474147 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4084 09:27:41.477278 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4085 09:27:41.477361 == TX Byte 1 ==
4086 09:27:41.484567 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4087 09:27:41.487544 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4088 09:27:41.487632 ==
4089 09:27:41.490788 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 09:27:41.494082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 09:27:41.494191 ==
4092 09:27:41.494286
4093 09:27:41.494374
4094 09:27:41.497147 TX Vref Scan disable
4095 09:27:41.500650 == TX Byte 0 ==
4096 09:27:41.504104 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 09:27:41.507256 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 09:27:41.510766 == TX Byte 1 ==
4099 09:27:41.513646 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4100 09:27:41.520295 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4101 09:27:41.520390
4102 09:27:41.520477 [DATLAT]
4103 09:27:41.520558 Freq=600, CH0 RK0
4104 09:27:41.520637
4105 09:27:41.523902 DATLAT Default: 0x9
4106 09:27:41.523987 0, 0xFFFF, sum = 0
4107 09:27:41.526980 1, 0xFFFF, sum = 0
4108 09:27:41.527066 2, 0xFFFF, sum = 0
4109 09:27:41.530565 3, 0xFFFF, sum = 0
4110 09:27:41.533597 4, 0xFFFF, sum = 0
4111 09:27:41.533695 5, 0xFFFF, sum = 0
4112 09:27:41.536994 6, 0xFFFF, sum = 0
4113 09:27:41.537074 7, 0xFFFF, sum = 0
4114 09:27:41.537137 8, 0x0, sum = 1
4115 09:27:41.540491 9, 0x0, sum = 2
4116 09:27:41.540575 10, 0x0, sum = 3
4117 09:27:41.544069 11, 0x0, sum = 4
4118 09:27:41.544153 best_step = 9
4119 09:27:41.544216
4120 09:27:41.544275 ==
4121 09:27:41.546932 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 09:27:41.554093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 09:27:41.554179 ==
4124 09:27:41.554243 RX Vref Scan: 1
4125 09:27:41.554304
4126 09:27:41.557070 RX Vref 0 -> 0, step: 1
4127 09:27:41.557151
4128 09:27:41.560574 RX Delay -195 -> 252, step: 8
4129 09:27:41.560655
4130 09:27:41.563440 Set Vref, RX VrefLevel [Byte0]: 64
4131 09:27:41.566821 [Byte1]: 57
4132 09:27:41.566917
4133 09:27:41.570307 Final RX Vref Byte 0 = 64 to rank0
4134 09:27:41.573875 Final RX Vref Byte 1 = 57 to rank0
4135 09:27:41.576924 Final RX Vref Byte 0 = 64 to rank1
4136 09:27:41.579897 Final RX Vref Byte 1 = 57 to rank1==
4137 09:27:41.583261 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 09:27:41.586937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 09:27:41.587018 ==
4140 09:27:41.590055 DQS Delay:
4141 09:27:41.590136 DQS0 = 0, DQS1 = 0
4142 09:27:41.593122 DQM Delay:
4143 09:27:41.593205 DQM0 = 36, DQM1 = 29
4144 09:27:41.593284 DQ Delay:
4145 09:27:41.596511 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4146 09:27:41.599921 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4147 09:27:41.603644 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4148 09:27:41.606496 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4149 09:27:41.606594
4150 09:27:41.606671
4151 09:27:41.617021 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4152 09:27:41.620128 CH0 RK0: MR19=808, MR18=4140
4153 09:27:41.623477 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4154 09:27:41.626611
4155 09:27:41.630191 ----->DramcWriteLeveling(PI) begin...
4156 09:27:41.630274 ==
4157 09:27:41.633905 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 09:27:41.636682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 09:27:41.636783 ==
4160 09:27:41.640327 Write leveling (Byte 0): 33 => 33
4161 09:27:41.643303 Write leveling (Byte 1): 31 => 31
4162 09:27:41.646351 DramcWriteLeveling(PI) end<-----
4163 09:27:41.646432
4164 09:27:41.646495 ==
4165 09:27:41.650001 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 09:27:41.653341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 09:27:41.653425 ==
4168 09:27:41.656328 [Gating] SW mode calibration
4169 09:27:41.663059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4170 09:27:41.669524 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4171 09:27:41.673185 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 09:27:41.676077 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 09:27:41.683176 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 09:27:41.686793 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (0 0) (1 0)
4175 09:27:41.689777 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
4176 09:27:41.696328 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 09:27:41.699273 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 09:27:41.703040 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 09:27:41.709844 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 09:27:41.712659 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 09:27:41.715808 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 09:27:41.722742 0 10 12 | B1->B0 | 2828 302f | 0 1 | (0 0) (0 0)
4183 09:27:41.726017 0 10 16 | B1->B0 | 3737 4141 | 0 0 | (1 1) (0 0)
4184 09:27:41.729448 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 09:27:41.735898 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 09:27:41.739077 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 09:27:41.742247 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 09:27:41.749545 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 09:27:41.752425 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 09:27:41.755928 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4191 09:27:41.762555 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4192 09:27:41.765554 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 09:27:41.769066 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 09:27:41.772234 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 09:27:41.779268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 09:27:41.782499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 09:27:41.785531 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 09:27:41.792547 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 09:27:41.795659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 09:27:41.798456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 09:27:41.805046 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 09:27:41.808494 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 09:27:41.812184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 09:27:41.818538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 09:27:41.822178 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 09:27:41.825063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4207 09:27:41.831786 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4208 09:27:41.835443 Total UI for P1: 0, mck2ui 16
4209 09:27:41.838617 best dqsien dly found for B0: ( 0, 13, 12)
4210 09:27:41.841501 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 09:27:41.844774 Total UI for P1: 0, mck2ui 16
4212 09:27:41.848159 best dqsien dly found for B1: ( 0, 13, 16)
4213 09:27:41.851900 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4214 09:27:41.855495 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4215 09:27:41.855578
4216 09:27:41.858149 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4217 09:27:41.864787 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4218 09:27:41.864874 [Gating] SW calibration Done
4219 09:27:41.864940 ==
4220 09:27:41.868231 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 09:27:41.874883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 09:27:41.874992 ==
4223 09:27:41.875060 RX Vref Scan: 0
4224 09:27:41.875123
4225 09:27:41.877797 RX Vref 0 -> 0, step: 1
4226 09:27:41.877873
4227 09:27:41.881398 RX Delay -230 -> 252, step: 16
4228 09:27:41.884364 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4229 09:27:41.888063 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4230 09:27:41.894757 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4231 09:27:41.898114 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4232 09:27:41.901121 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4233 09:27:41.904100 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4234 09:27:41.907783 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4235 09:27:41.914244 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4236 09:27:41.917848 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4237 09:27:41.920964 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4238 09:27:41.923908 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4239 09:27:41.930826 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4240 09:27:41.933982 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4241 09:27:41.937388 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4242 09:27:41.941164 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4243 09:27:41.947120 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4244 09:27:41.947238 ==
4245 09:27:41.950283 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 09:27:41.953627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 09:27:41.953738 ==
4248 09:27:41.953839 DQS Delay:
4249 09:27:41.957114 DQS0 = 0, DQS1 = 0
4250 09:27:41.957219 DQM Delay:
4251 09:27:41.960391 DQM0 = 37, DQM1 = 28
4252 09:27:41.960502 DQ Delay:
4253 09:27:41.963660 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4254 09:27:41.966717 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4255 09:27:41.970415 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4256 09:27:41.973507 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4257 09:27:41.973611
4258 09:27:41.973706
4259 09:27:41.973798 ==
4260 09:27:41.976923 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 09:27:41.980859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 09:27:41.983468 ==
4263 09:27:41.983588
4264 09:27:41.983680
4265 09:27:41.983772 TX Vref Scan disable
4266 09:27:41.987087 == TX Byte 0 ==
4267 09:27:41.990606 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4268 09:27:41.993562 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4269 09:27:41.997167 == TX Byte 1 ==
4270 09:27:41.999900 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4271 09:27:42.003574 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4272 09:27:42.006607 ==
4273 09:27:42.010335 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 09:27:42.013143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 09:27:42.013254 ==
4276 09:27:42.013347
4277 09:27:42.013438
4278 09:27:42.016693 TX Vref Scan disable
4279 09:27:42.019836 == TX Byte 0 ==
4280 09:27:42.023314 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4281 09:27:42.026337 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4282 09:27:42.030003 == TX Byte 1 ==
4283 09:27:42.032872 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 09:27:42.036345 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 09:27:42.036452
4286 09:27:42.036543 [DATLAT]
4287 09:27:42.039973 Freq=600, CH0 RK1
4288 09:27:42.040053
4289 09:27:42.040118 DATLAT Default: 0x9
4290 09:27:42.042927 0, 0xFFFF, sum = 0
4291 09:27:42.046513 1, 0xFFFF, sum = 0
4292 09:27:42.046598 2, 0xFFFF, sum = 0
4293 09:27:42.050011 3, 0xFFFF, sum = 0
4294 09:27:42.050117 4, 0xFFFF, sum = 0
4295 09:27:42.053211 5, 0xFFFF, sum = 0
4296 09:27:42.053319 6, 0xFFFF, sum = 0
4297 09:27:42.056163 7, 0xFFFF, sum = 0
4298 09:27:42.056269 8, 0x0, sum = 1
4299 09:27:42.059902 9, 0x0, sum = 2
4300 09:27:42.059984 10, 0x0, sum = 3
4301 09:27:42.060079 11, 0x0, sum = 4
4302 09:27:42.062591 best_step = 9
4303 09:27:42.062666
4304 09:27:42.062727 ==
4305 09:27:42.066277 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 09:27:42.069304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 09:27:42.069411 ==
4308 09:27:42.073049 RX Vref Scan: 0
4309 09:27:42.073157
4310 09:27:42.075827 RX Vref 0 -> 0, step: 1
4311 09:27:42.075929
4312 09:27:42.075994 RX Delay -195 -> 252, step: 8
4313 09:27:42.083659 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4314 09:27:42.087066 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4315 09:27:42.090606 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4316 09:27:42.093837 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4317 09:27:42.100736 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4318 09:27:42.103556 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4319 09:27:42.107039 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4320 09:27:42.110536 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4321 09:27:42.113809 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4322 09:27:42.120152 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4323 09:27:42.123823 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4324 09:27:42.126942 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4325 09:27:42.130538 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4326 09:27:42.137023 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4327 09:27:42.140337 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4328 09:27:42.143566 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4329 09:27:42.143671 ==
4330 09:27:42.147281 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 09:27:42.150016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 09:27:42.153765 ==
4333 09:27:42.153871 DQS Delay:
4334 09:27:42.153962 DQS0 = 0, DQS1 = 0
4335 09:27:42.156687 DQM Delay:
4336 09:27:42.156790 DQM0 = 33, DQM1 = 27
4337 09:27:42.160308 DQ Delay:
4338 09:27:42.163663 DQ0 =32, DQ1 =32, DQ2 =32, DQ3 =28
4339 09:27:42.163742 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4340 09:27:42.166624 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4341 09:27:42.173178 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4342 09:27:42.173294
4343 09:27:42.173386
4344 09:27:42.180105 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4345 09:27:42.183210 CH0 RK1: MR19=808, MR18=6D3A
4346 09:27:42.189766 CH0_RK1: MR19=0x808, MR18=0x6D3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4347 09:27:42.193265 [RxdqsGatingPostProcess] freq 600
4348 09:27:42.196630 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4349 09:27:42.199970 Pre-setting of DQS Precalculation
4350 09:27:42.206555 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4351 09:27:42.206661 ==
4352 09:27:42.210250 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 09:27:42.213114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 09:27:42.213221 ==
4355 09:27:42.219537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 09:27:42.222814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4357 09:27:42.227734 [CA 0] Center 36 (6~66) winsize 61
4358 09:27:42.230593 [CA 1] Center 36 (6~66) winsize 61
4359 09:27:42.234111 [CA 2] Center 34 (4~65) winsize 62
4360 09:27:42.237178 [CA 3] Center 34 (4~65) winsize 62
4361 09:27:42.240436 [CA 4] Center 34 (4~65) winsize 62
4362 09:27:42.244137 [CA 5] Center 33 (3~64) winsize 62
4363 09:27:42.244225
4364 09:27:42.247029 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4365 09:27:42.247136
4366 09:27:42.250709 [CATrainingPosCal] consider 1 rank data
4367 09:27:42.253732 u2DelayCellTimex100 = 270/100 ps
4368 09:27:42.257325 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4369 09:27:42.260944 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4370 09:27:42.267064 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 09:27:42.270876 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 09:27:42.273954 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 09:27:42.277503 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 09:27:42.277611
4375 09:27:42.280586 CA PerBit enable=1, Macro0, CA PI delay=33
4376 09:27:42.280688
4377 09:27:42.283714 [CBTSetCACLKResult] CA Dly = 33
4378 09:27:42.283820 CS Dly: 6 (0~37)
4379 09:27:42.287228 ==
4380 09:27:42.290216 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 09:27:42.293861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 09:27:42.293971 ==
4383 09:27:42.297218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 09:27:42.303924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4385 09:27:42.307292 [CA 0] Center 36 (6~66) winsize 61
4386 09:27:42.310919 [CA 1] Center 35 (5~66) winsize 62
4387 09:27:42.314302 [CA 2] Center 34 (4~65) winsize 62
4388 09:27:42.317193 [CA 3] Center 34 (3~65) winsize 63
4389 09:27:42.320909 [CA 4] Center 34 (4~65) winsize 62
4390 09:27:42.323990 [CA 5] Center 33 (3~64) winsize 62
4391 09:27:42.324096
4392 09:27:42.327217 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4393 09:27:42.327324
4394 09:27:42.330422 [CATrainingPosCal] consider 2 rank data
4395 09:27:42.334057 u2DelayCellTimex100 = 270/100 ps
4396 09:27:42.337496 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4397 09:27:42.343889 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 09:27:42.347221 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 09:27:42.350809 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 09:27:42.353740 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 09:27:42.357108 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 09:27:42.357216
4403 09:27:42.360669 CA PerBit enable=1, Macro0, CA PI delay=33
4404 09:27:42.360774
4405 09:27:42.363852 [CBTSetCACLKResult] CA Dly = 33
4406 09:27:42.363956 CS Dly: 5 (0~36)
4407 09:27:42.364049
4408 09:27:42.367306 ----->DramcWriteLeveling(PI) begin...
4409 09:27:42.370487 ==
4410 09:27:42.373805 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 09:27:42.377097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 09:27:42.377205 ==
4413 09:27:42.380926 Write leveling (Byte 0): 30 => 30
4414 09:27:42.383934 Write leveling (Byte 1): 30 => 30
4415 09:27:42.387477 DramcWriteLeveling(PI) end<-----
4416 09:27:42.387555
4417 09:27:42.387618 ==
4418 09:27:42.390346 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 09:27:42.393902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 09:27:42.394006 ==
4421 09:27:42.397089 [Gating] SW mode calibration
4422 09:27:42.403575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4423 09:27:42.410220 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4424 09:27:42.413753 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 09:27:42.417081 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 09:27:42.423546 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 09:27:42.427297 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
4428 09:27:42.430200 0 9 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4429 09:27:42.436735 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 09:27:42.440216 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 09:27:42.443268 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 09:27:42.450085 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 09:27:42.453313 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 09:27:42.456619 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 09:27:42.460101 0 10 12 | B1->B0 | 2b2b 3131 | 0 0 | (1 1) (0 0)
4436 09:27:42.466756 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4437 09:27:42.469741 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 09:27:42.473391 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 09:27:42.480275 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 09:27:42.483679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 09:27:42.486407 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 09:27:42.493143 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 09:27:42.496396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4444 09:27:42.499916 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4445 09:27:42.506589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 09:27:42.510063 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 09:27:42.512839 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 09:27:42.519918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 09:27:42.523150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 09:27:42.526450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 09:27:42.533159 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 09:27:42.536146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 09:27:42.539827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 09:27:42.546052 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 09:27:42.549596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 09:27:42.552803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 09:27:42.559481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 09:27:42.562801 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:27:42.566251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4460 09:27:42.572859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 09:27:42.572992 Total UI for P1: 0, mck2ui 16
4462 09:27:42.579444 best dqsien dly found for B0: ( 0, 13, 12)
4463 09:27:42.579563 Total UI for P1: 0, mck2ui 16
4464 09:27:42.586209 best dqsien dly found for B1: ( 0, 13, 14)
4465 09:27:42.589046 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4466 09:27:42.592706 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4467 09:27:42.592854
4468 09:27:42.596237 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4469 09:27:42.599162 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4470 09:27:42.602761 [Gating] SW calibration Done
4471 09:27:42.602879 ==
4472 09:27:42.605944 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 09:27:42.609198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 09:27:42.609304 ==
4475 09:27:42.612574 RX Vref Scan: 0
4476 09:27:42.612691
4477 09:27:42.612794 RX Vref 0 -> 0, step: 1
4478 09:27:42.612885
4479 09:27:42.615873 RX Delay -230 -> 252, step: 16
4480 09:27:42.622436 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4481 09:27:42.625997 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4482 09:27:42.628917 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4483 09:27:42.632229 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4484 09:27:42.635546 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4485 09:27:42.642579 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4486 09:27:42.646106 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4487 09:27:42.648784 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4488 09:27:42.652481 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4489 09:27:42.659082 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4490 09:27:42.662029 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4491 09:27:42.665368 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4492 09:27:42.668545 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4493 09:27:42.675235 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4494 09:27:42.678885 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4495 09:27:42.681880 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4496 09:27:42.681986 ==
4497 09:27:42.685329 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 09:27:42.688898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 09:27:42.689003 ==
4500 09:27:42.692070 DQS Delay:
4501 09:27:42.692169 DQS0 = 0, DQS1 = 0
4502 09:27:42.695545 DQM Delay:
4503 09:27:42.695654 DQM0 = 38, DQM1 = 28
4504 09:27:42.695748 DQ Delay:
4505 09:27:42.698606 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4506 09:27:42.701887 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4507 09:27:42.705341 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4508 09:27:42.708806 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4509 09:27:42.708908
4510 09:27:42.708998
4511 09:27:42.711757 ==
4512 09:27:42.715320 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 09:27:42.718632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 09:27:42.718732 ==
4515 09:27:42.718829
4516 09:27:42.718957
4517 09:27:42.721875 TX Vref Scan disable
4518 09:27:42.721981 == TX Byte 0 ==
4519 09:27:42.728207 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4520 09:27:42.731536 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4521 09:27:42.731612 == TX Byte 1 ==
4522 09:27:42.738741 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 09:27:42.742151 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 09:27:42.742262 ==
4525 09:27:42.745079 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 09:27:42.748825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 09:27:42.748933 ==
4528 09:27:42.749068
4529 09:27:42.749159
4530 09:27:42.752050 TX Vref Scan disable
4531 09:27:42.754816 == TX Byte 0 ==
4532 09:27:42.758422 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4533 09:27:42.761486 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4534 09:27:42.765275 == TX Byte 1 ==
4535 09:27:42.768082 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4536 09:27:42.771754 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4537 09:27:42.771845
4538 09:27:42.774579 [DATLAT]
4539 09:27:42.774682 Freq=600, CH1 RK0
4540 09:27:42.774778
4541 09:27:42.778056 DATLAT Default: 0x9
4542 09:27:42.778162 0, 0xFFFF, sum = 0
4543 09:27:42.781173 1, 0xFFFF, sum = 0
4544 09:27:42.781279 2, 0xFFFF, sum = 0
4545 09:27:42.784582 3, 0xFFFF, sum = 0
4546 09:27:42.784692 4, 0xFFFF, sum = 0
4547 09:27:42.788218 5, 0xFFFF, sum = 0
4548 09:27:42.788326 6, 0xFFFF, sum = 0
4549 09:27:42.791143 7, 0xFFFF, sum = 0
4550 09:27:42.791243 8, 0x0, sum = 1
4551 09:27:42.794932 9, 0x0, sum = 2
4552 09:27:42.795041 10, 0x0, sum = 3
4553 09:27:42.797800 11, 0x0, sum = 4
4554 09:27:42.797903 best_step = 9
4555 09:27:42.797996
4556 09:27:42.798083 ==
4557 09:27:42.801389 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 09:27:42.808119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 09:27:42.808241 ==
4560 09:27:42.808339 RX Vref Scan: 1
4561 09:27:42.808428
4562 09:27:42.811574 RX Vref 0 -> 0, step: 1
4563 09:27:42.811678
4564 09:27:42.814483 RX Delay -195 -> 252, step: 8
4565 09:27:42.814596
4566 09:27:42.818281 Set Vref, RX VrefLevel [Byte0]: 56
4567 09:27:42.821083 [Byte1]: 56
4568 09:27:42.821188
4569 09:27:42.824714 Final RX Vref Byte 0 = 56 to rank0
4570 09:27:42.828263 Final RX Vref Byte 1 = 56 to rank0
4571 09:27:42.831093 Final RX Vref Byte 0 = 56 to rank1
4572 09:27:42.834422 Final RX Vref Byte 1 = 56 to rank1==
4573 09:27:42.837996 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 09:27:42.840946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 09:27:42.841052 ==
4576 09:27:42.844683 DQS Delay:
4577 09:27:42.844786 DQS0 = 0, DQS1 = 0
4578 09:27:42.844880 DQM Delay:
4579 09:27:42.847755 DQM0 = 38, DQM1 = 28
4580 09:27:42.847861 DQ Delay:
4581 09:27:42.851187 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =32
4582 09:27:42.854456 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4583 09:27:42.857549 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4584 09:27:42.861464 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4585 09:27:42.861573
4586 09:27:42.861667
4587 09:27:42.871056 [DQSOSCAuto] RK0, (LSB)MR18= 0x2937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4588 09:27:42.871195 CH1 RK0: MR19=808, MR18=2937
4589 09:27:42.877679 CH1_RK0: MR19=0x808, MR18=0x2937, DQSOSC=399, MR23=63, INC=164, DEC=109
4590 09:27:42.877803
4591 09:27:42.881097 ----->DramcWriteLeveling(PI) begin...
4592 09:27:42.884208 ==
4593 09:27:42.884320 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 09:27:42.890860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 09:27:42.890969 ==
4596 09:27:42.894320 Write leveling (Byte 0): 29 => 29
4597 09:27:42.897983 Write leveling (Byte 1): 33 => 33
4598 09:27:42.900724 DramcWriteLeveling(PI) end<-----
4599 09:27:42.900825
4600 09:27:42.900918 ==
4601 09:27:42.904361 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 09:27:42.907481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 09:27:42.907585 ==
4604 09:27:42.911009 [Gating] SW mode calibration
4605 09:27:42.917756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 09:27:42.921172 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 09:27:42.927794 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 09:27:42.930777 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 09:27:42.934571 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 09:27:42.941019 0 9 12 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (0 0)
4611 09:27:42.944635 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4612 09:27:42.947607 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 09:27:42.954239 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 09:27:42.957492 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 09:27:42.960889 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 09:27:42.967271 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 09:27:42.970787 0 10 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4618 09:27:42.973826 0 10 12 | B1->B0 | 3232 3939 | 0 1 | (0 0) (0 0)
4619 09:27:42.980673 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
4620 09:27:42.983710 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 09:27:42.986881 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 09:27:42.993922 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 09:27:42.996766 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 09:27:43.000578 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 09:27:43.007177 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 09:27:43.010236 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 09:27:43.013969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 09:27:43.020469 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 09:27:43.023994 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 09:27:43.026974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 09:27:43.033517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 09:27:43.036641 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 09:27:43.040212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 09:27:43.046573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 09:27:43.050203 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 09:27:43.053188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 09:27:43.059909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 09:27:43.063298 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 09:27:43.066348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 09:27:43.073407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 09:27:43.076880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 09:27:43.079891 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4643 09:27:43.083243 Total UI for P1: 0, mck2ui 16
4644 09:27:43.086943 best dqsien dly found for B0: ( 0, 13, 10)
4645 09:27:43.090247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 09:27:43.093384 Total UI for P1: 0, mck2ui 16
4647 09:27:43.096637 best dqsien dly found for B1: ( 0, 13, 12)
4648 09:27:43.103581 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4649 09:27:43.106402 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4650 09:27:43.106514
4651 09:27:43.109720 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 09:27:43.112856 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4653 09:27:43.116595 [Gating] SW calibration Done
4654 09:27:43.116710 ==
4655 09:27:43.119507 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 09:27:43.123149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 09:27:43.123252 ==
4658 09:27:43.126537 RX Vref Scan: 0
4659 09:27:43.126648
4660 09:27:43.126743 RX Vref 0 -> 0, step: 1
4661 09:27:43.126831
4662 09:27:43.129651 RX Delay -230 -> 252, step: 16
4663 09:27:43.132840 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4664 09:27:43.139905 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4665 09:27:43.142764 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4666 09:27:43.146390 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4667 09:27:43.149364 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4668 09:27:43.156036 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4669 09:27:43.159452 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4670 09:27:43.162432 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4671 09:27:43.166025 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4672 09:27:43.169159 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4673 09:27:43.175769 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4674 09:27:43.179065 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4675 09:27:43.182381 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4676 09:27:43.185893 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4677 09:27:43.192548 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4678 09:27:43.196126 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4679 09:27:43.196236 ==
4680 09:27:43.199088 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 09:27:43.202184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 09:27:43.202286 ==
4683 09:27:43.205592 DQS Delay:
4684 09:27:43.205698 DQS0 = 0, DQS1 = 0
4685 09:27:43.209017 DQM Delay:
4686 09:27:43.209119 DQM0 = 36, DQM1 = 31
4687 09:27:43.209212 DQ Delay:
4688 09:27:43.212366 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4689 09:27:43.215771 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4690 09:27:43.218578 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4691 09:27:43.222063 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =41
4692 09:27:43.222166
4693 09:27:43.222259
4694 09:27:43.226012 ==
4695 09:27:43.228607 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 09:27:43.232142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 09:27:43.232218 ==
4698 09:27:43.232280
4699 09:27:43.232342
4700 09:27:43.235277 TX Vref Scan disable
4701 09:27:43.235405 == TX Byte 0 ==
4702 09:27:43.242001 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4703 09:27:43.245439 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4704 09:27:43.245546 == TX Byte 1 ==
4705 09:27:43.252105 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4706 09:27:43.255102 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4707 09:27:43.255220 ==
4708 09:27:43.258489 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 09:27:43.262117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 09:27:43.262223 ==
4711 09:27:43.262318
4712 09:27:43.262405
4713 09:27:43.264905 TX Vref Scan disable
4714 09:27:43.268573 == TX Byte 0 ==
4715 09:27:43.272179 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 09:27:43.275087 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 09:27:43.278364 == TX Byte 1 ==
4718 09:27:43.281703 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4719 09:27:43.284744 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4720 09:27:43.284846
4721 09:27:43.288496 [DATLAT]
4722 09:27:43.288599 Freq=600, CH1 RK1
4723 09:27:43.288691
4724 09:27:43.291746 DATLAT Default: 0x9
4725 09:27:43.291851 0, 0xFFFF, sum = 0
4726 09:27:43.294835 1, 0xFFFF, sum = 0
4727 09:27:43.294943 2, 0xFFFF, sum = 0
4728 09:27:43.298465 3, 0xFFFF, sum = 0
4729 09:27:43.298564 4, 0xFFFF, sum = 0
4730 09:27:43.301487 5, 0xFFFF, sum = 0
4731 09:27:43.301573 6, 0xFFFF, sum = 0
4732 09:27:43.305055 7, 0xFFFF, sum = 0
4733 09:27:43.305163 8, 0x0, sum = 1
4734 09:27:43.308618 9, 0x0, sum = 2
4735 09:27:43.308722 10, 0x0, sum = 3
4736 09:27:43.311780 11, 0x0, sum = 4
4737 09:27:43.311891 best_step = 9
4738 09:27:43.311988
4739 09:27:43.312077 ==
4740 09:27:43.314857 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 09:27:43.321626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 09:27:43.321736 ==
4743 09:27:43.321839 RX Vref Scan: 0
4744 09:27:43.321931
4745 09:27:43.324639 RX Vref 0 -> 0, step: 1
4746 09:27:43.324738
4747 09:27:43.328226 RX Delay -195 -> 252, step: 8
4748 09:27:43.331708 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4749 09:27:43.338305 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4750 09:27:43.341213 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4751 09:27:43.344446 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4752 09:27:43.347965 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4753 09:27:43.351197 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4754 09:27:43.358090 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4755 09:27:43.361291 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4756 09:27:43.364464 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4757 09:27:43.367660 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4758 09:27:43.374701 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4759 09:27:43.377928 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4760 09:27:43.381170 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4761 09:27:43.384706 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4762 09:27:43.391455 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4763 09:27:43.394309 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4764 09:27:43.394427 ==
4765 09:27:43.397605 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 09:27:43.401036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 09:27:43.401145 ==
4768 09:27:43.404638 DQS Delay:
4769 09:27:43.404746 DQS0 = 0, DQS1 = 0
4770 09:27:43.404841 DQM Delay:
4771 09:27:43.407470 DQM0 = 36, DQM1 = 29
4772 09:27:43.407574 DQ Delay:
4773 09:27:43.411174 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4774 09:27:43.414141 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4775 09:27:43.417273 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4776 09:27:43.420750 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4777 09:27:43.420857
4778 09:27:43.420952
4779 09:27:43.430772 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4780 09:27:43.430886 CH1 RK1: MR19=808, MR18=3B5B
4781 09:27:43.437803 CH1_RK1: MR19=0x808, MR18=0x3B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4782 09:27:43.440822 [RxdqsGatingPostProcess] freq 600
4783 09:27:43.447350 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4784 09:27:43.450773 Pre-setting of DQS Precalculation
4785 09:27:43.453768 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4786 09:27:43.460729 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4787 09:27:43.470386 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4788 09:27:43.470506
4789 09:27:43.470575
4790 09:27:43.473887 [Calibration Summary] 1200 Mbps
4791 09:27:43.473991 CH 0, Rank 0
4792 09:27:43.477275 SW Impedance : PASS
4793 09:27:43.477375 DUTY Scan : NO K
4794 09:27:43.480508 ZQ Calibration : PASS
4795 09:27:43.483568 Jitter Meter : NO K
4796 09:27:43.483648 CBT Training : PASS
4797 09:27:43.487134 Write leveling : PASS
4798 09:27:43.487244 RX DQS gating : PASS
4799 09:27:43.490424 RX DQ/DQS(RDDQC) : PASS
4800 09:27:43.493835 TX DQ/DQS : PASS
4801 09:27:43.493943 RX DATLAT : PASS
4802 09:27:43.497159 RX DQ/DQS(Engine): PASS
4803 09:27:43.500487 TX OE : NO K
4804 09:27:43.500611 All Pass.
4805 09:27:43.500706
4806 09:27:43.500795 CH 0, Rank 1
4807 09:27:43.503437 SW Impedance : PASS
4808 09:27:43.506775 DUTY Scan : NO K
4809 09:27:43.506887 ZQ Calibration : PASS
4810 09:27:43.510182 Jitter Meter : NO K
4811 09:27:43.513728 CBT Training : PASS
4812 09:27:43.513831 Write leveling : PASS
4813 09:27:43.517188 RX DQS gating : PASS
4814 09:27:43.520063 RX DQ/DQS(RDDQC) : PASS
4815 09:27:43.520168 TX DQ/DQS : PASS
4816 09:27:43.523566 RX DATLAT : PASS
4817 09:27:43.527307 RX DQ/DQS(Engine): PASS
4818 09:27:43.527441 TX OE : NO K
4819 09:27:43.530065 All Pass.
4820 09:27:43.530163
4821 09:27:43.530256 CH 1, Rank 0
4822 09:27:43.533663 SW Impedance : PASS
4823 09:27:43.533772 DUTY Scan : NO K
4824 09:27:43.536473 ZQ Calibration : PASS
4825 09:27:43.540156 Jitter Meter : NO K
4826 09:27:43.540256 CBT Training : PASS
4827 09:27:43.543158 Write leveling : PASS
4828 09:27:43.546756 RX DQS gating : PASS
4829 09:27:43.546831 RX DQ/DQS(RDDQC) : PASS
4830 09:27:43.549983 TX DQ/DQS : PASS
4831 09:27:43.550085 RX DATLAT : PASS
4832 09:27:43.553355 RX DQ/DQS(Engine): PASS
4833 09:27:43.556329 TX OE : NO K
4834 09:27:43.556430 All Pass.
4835 09:27:43.556521
4836 09:27:43.556613 CH 1, Rank 1
4837 09:27:43.560009 SW Impedance : PASS
4838 09:27:43.563563 DUTY Scan : NO K
4839 09:27:43.563664 ZQ Calibration : PASS
4840 09:27:43.566560 Jitter Meter : NO K
4841 09:27:43.570217 CBT Training : PASS
4842 09:27:43.570321 Write leveling : PASS
4843 09:27:43.573336 RX DQS gating : PASS
4844 09:27:43.576700 RX DQ/DQS(RDDQC) : PASS
4845 09:27:43.576807 TX DQ/DQS : PASS
4846 09:27:43.580144 RX DATLAT : PASS
4847 09:27:43.583215 RX DQ/DQS(Engine): PASS
4848 09:27:43.583315 TX OE : NO K
4849 09:27:43.586145 All Pass.
4850 09:27:43.586243
4851 09:27:43.586337 DramC Write-DBI off
4852 09:27:43.589726 PER_BANK_REFRESH: Hybrid Mode
4853 09:27:43.589826 TX_TRACKING: ON
4854 09:27:43.599864 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4855 09:27:43.603406 [FAST_K] Save calibration result to emmc
4856 09:27:43.606306 dramc_set_vcore_voltage set vcore to 662500
4857 09:27:43.610028 Read voltage for 933, 3
4858 09:27:43.610110 Vio18 = 0
4859 09:27:43.612773 Vcore = 662500
4860 09:27:43.612853 Vdram = 0
4861 09:27:43.612918 Vddq = 0
4862 09:27:43.612978 Vmddr = 0
4863 09:27:43.619337 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4864 09:27:43.626535 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4865 09:27:43.626635 MEM_TYPE=3, freq_sel=17
4866 09:27:43.629511 sv_algorithm_assistance_LP4_1600
4867 09:27:43.632806 ============ PULL DRAM RESETB DOWN ============
4868 09:27:43.639143 ========== PULL DRAM RESETB DOWN end =========
4869 09:27:43.642832 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 09:27:43.645941 ===================================
4871 09:27:43.649570 LPDDR4 DRAM CONFIGURATION
4872 09:27:43.652448 ===================================
4873 09:27:43.652558 EX_ROW_EN[0] = 0x0
4874 09:27:43.655941 EX_ROW_EN[1] = 0x0
4875 09:27:43.659143 LP4Y_EN = 0x0
4876 09:27:43.659241 WORK_FSP = 0x0
4877 09:27:43.662626 WL = 0x3
4878 09:27:43.662773 RL = 0x3
4879 09:27:43.665796 BL = 0x2
4880 09:27:43.665894 RPST = 0x0
4881 09:27:43.669401 RD_PRE = 0x0
4882 09:27:43.669482 WR_PRE = 0x1
4883 09:27:43.672368 WR_PST = 0x0
4884 09:27:43.672449 DBI_WR = 0x0
4885 09:27:43.676142 DBI_RD = 0x0
4886 09:27:43.676224 OTF = 0x1
4887 09:27:43.679091 ===================================
4888 09:27:43.682474 ===================================
4889 09:27:43.685991 ANA top config
4890 09:27:43.688994 ===================================
4891 09:27:43.689104 DLL_ASYNC_EN = 0
4892 09:27:43.692619 ALL_SLAVE_EN = 1
4893 09:27:43.695655 NEW_RANK_MODE = 1
4894 09:27:43.699021 DLL_IDLE_MODE = 1
4895 09:27:43.702571 LP45_APHY_COMB_EN = 1
4896 09:27:43.702654 TX_ODT_DIS = 1
4897 09:27:43.705663 NEW_8X_MODE = 1
4898 09:27:43.709159 ===================================
4899 09:27:43.712156 ===================================
4900 09:27:43.715646 data_rate = 1866
4901 09:27:43.719034 CKR = 1
4902 09:27:43.722488 DQ_P2S_RATIO = 8
4903 09:27:43.725862 ===================================
4904 09:27:43.726001 CA_P2S_RATIO = 8
4905 09:27:43.728837 DQ_CA_OPEN = 0
4906 09:27:43.732356 DQ_SEMI_OPEN = 0
4907 09:27:43.735719 CA_SEMI_OPEN = 0
4908 09:27:43.738525 CA_FULL_RATE = 0
4909 09:27:43.741793 DQ_CKDIV4_EN = 1
4910 09:27:43.745240 CA_CKDIV4_EN = 1
4911 09:27:43.745389 CA_PREDIV_EN = 0
4912 09:27:43.748778 PH8_DLY = 0
4913 09:27:43.751892 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4914 09:27:43.755034 DQ_AAMCK_DIV = 4
4915 09:27:43.758675 CA_AAMCK_DIV = 4
4916 09:27:43.758798 CA_ADMCK_DIV = 4
4917 09:27:43.762335 DQ_TRACK_CA_EN = 0
4918 09:27:43.765522 CA_PICK = 933
4919 09:27:43.768796 CA_MCKIO = 933
4920 09:27:43.771840 MCKIO_SEMI = 0
4921 09:27:43.775361 PLL_FREQ = 3732
4922 09:27:43.778471 DQ_UI_PI_RATIO = 32
4923 09:27:43.782245 CA_UI_PI_RATIO = 0
4924 09:27:43.784994 ===================================
4925 09:27:43.788612 ===================================
4926 09:27:43.788764 memory_type:LPDDR4
4927 09:27:43.791908 GP_NUM : 10
4928 09:27:43.794890 SRAM_EN : 1
4929 09:27:43.795026 MD32_EN : 0
4930 09:27:43.798603 ===================================
4931 09:27:43.801441 [ANA_INIT] >>>>>>>>>>>>>>
4932 09:27:43.804910 <<<<<< [CONFIGURE PHASE]: ANA_TX
4933 09:27:43.808560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4934 09:27:43.811615 ===================================
4935 09:27:43.815179 data_rate = 1866,PCW = 0X8f00
4936 09:27:43.815287 ===================================
4937 09:27:43.821777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4938 09:27:43.824768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 09:27:43.831234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 09:27:43.834929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4941 09:27:43.837979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4942 09:27:43.841487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4943 09:27:43.844960 [ANA_INIT] flow start
4944 09:27:43.847902 [ANA_INIT] PLL >>>>>>>>
4945 09:27:43.848010 [ANA_INIT] PLL <<<<<<<<
4946 09:27:43.851644 [ANA_INIT] MIDPI >>>>>>>>
4947 09:27:43.854612 [ANA_INIT] MIDPI <<<<<<<<
4948 09:27:43.854722 [ANA_INIT] DLL >>>>>>>>
4949 09:27:43.858146 [ANA_INIT] flow end
4950 09:27:43.861468 ============ LP4 DIFF to SE enter ============
4951 09:27:43.868093 ============ LP4 DIFF to SE exit ============
4952 09:27:43.868204 [ANA_INIT] <<<<<<<<<<<<<
4953 09:27:43.871316 [Flow] Enable top DCM control >>>>>
4954 09:27:43.874599 [Flow] Enable top DCM control <<<<<
4955 09:27:43.878075 Enable DLL master slave shuffle
4956 09:27:43.885122 ==============================================================
4957 09:27:43.885238 Gating Mode config
4958 09:27:43.891287 ==============================================================
4959 09:27:43.891407 Config description:
4960 09:27:43.901764 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4961 09:27:43.907667 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4962 09:27:43.914792 SELPH_MODE 0: By rank 1: By Phase
4963 09:27:43.921391 ==============================================================
4964 09:27:43.921522 GAT_TRACK_EN = 1
4965 09:27:43.924342 RX_GATING_MODE = 2
4966 09:27:43.927844 RX_GATING_TRACK_MODE = 2
4967 09:27:43.930719 SELPH_MODE = 1
4968 09:27:43.934349 PICG_EARLY_EN = 1
4969 09:27:43.937309 VALID_LAT_VALUE = 1
4970 09:27:43.944344 ==============================================================
4971 09:27:43.947212 Enter into Gating configuration >>>>
4972 09:27:43.950931 Exit from Gating configuration <<<<
4973 09:27:43.953962 Enter into DVFS_PRE_config >>>>>
4974 09:27:43.964047 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4975 09:27:43.967242 Exit from DVFS_PRE_config <<<<<
4976 09:27:43.970658 Enter into PICG configuration >>>>
4977 09:27:43.973754 Exit from PICG configuration <<<<
4978 09:27:43.977405 [RX_INPUT] configuration >>>>>
4979 09:27:43.980753 [RX_INPUT] configuration <<<<<
4980 09:27:43.984008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4981 09:27:43.990576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4982 09:27:43.997358 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 09:27:44.000137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 09:27:44.007031 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 09:27:44.013375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 09:27:44.016977 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4987 09:27:44.023228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4988 09:27:44.026791 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4989 09:27:44.030338 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4990 09:27:44.033327 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4991 09:27:44.040220 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 09:27:44.043267 ===================================
4993 09:27:44.043389 LPDDR4 DRAM CONFIGURATION
4994 09:27:44.046642 ===================================
4995 09:27:44.050246 EX_ROW_EN[0] = 0x0
4996 09:27:44.053171 EX_ROW_EN[1] = 0x0
4997 09:27:44.053260 LP4Y_EN = 0x0
4998 09:27:44.056729 WORK_FSP = 0x0
4999 09:27:44.056844 WL = 0x3
5000 09:27:44.059600 RL = 0x3
5001 09:27:44.059715 BL = 0x2
5002 09:27:44.063232 RPST = 0x0
5003 09:27:44.063335 RD_PRE = 0x0
5004 09:27:44.066329 WR_PRE = 0x1
5005 09:27:44.066430 WR_PST = 0x0
5006 09:27:44.070076 DBI_WR = 0x0
5007 09:27:44.070150 DBI_RD = 0x0
5008 09:27:44.073038 OTF = 0x1
5009 09:27:44.076581 ===================================
5010 09:27:44.080014 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5011 09:27:44.083092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5012 09:27:44.090004 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 09:27:44.092768 ===================================
5014 09:27:44.092876 LPDDR4 DRAM CONFIGURATION
5015 09:27:44.096180 ===================================
5016 09:27:44.099563 EX_ROW_EN[0] = 0x10
5017 09:27:44.103000 EX_ROW_EN[1] = 0x0
5018 09:27:44.103105 LP4Y_EN = 0x0
5019 09:27:44.106132 WORK_FSP = 0x0
5020 09:27:44.106234 WL = 0x3
5021 09:27:44.109936 RL = 0x3
5022 09:27:44.110038 BL = 0x2
5023 09:27:44.112845 RPST = 0x0
5024 09:27:44.112947 RD_PRE = 0x0
5025 09:27:44.115991 WR_PRE = 0x1
5026 09:27:44.116109 WR_PST = 0x0
5027 09:27:44.119256 DBI_WR = 0x0
5028 09:27:44.119360 DBI_RD = 0x0
5029 09:27:44.122454 OTF = 0x1
5030 09:27:44.125795 ===================================
5031 09:27:44.132453 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5032 09:27:44.136178 nWR fixed to 30
5033 09:27:44.139345 [ModeRegInit_LP4] CH0 RK0
5034 09:27:44.139482 [ModeRegInit_LP4] CH0 RK1
5035 09:27:44.142765 [ModeRegInit_LP4] CH1 RK0
5036 09:27:44.145822 [ModeRegInit_LP4] CH1 RK1
5037 09:27:44.145925 match AC timing 9
5038 09:27:44.152362 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5039 09:27:44.155749 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5040 09:27:44.159472 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5041 09:27:44.166053 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5042 09:27:44.168968 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5043 09:27:44.169082 ==
5044 09:27:44.172097 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 09:27:44.175506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 09:27:44.175608 ==
5047 09:27:44.181973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 09:27:44.189101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5049 09:27:44.192120 [CA 0] Center 38 (8~69) winsize 62
5050 09:27:44.195229 [CA 1] Center 38 (7~69) winsize 63
5051 09:27:44.198579 [CA 2] Center 35 (5~65) winsize 61
5052 09:27:44.201933 [CA 3] Center 35 (5~65) winsize 61
5053 09:27:44.205294 [CA 4] Center 34 (4~64) winsize 61
5054 09:27:44.208801 [CA 5] Center 33 (3~64) winsize 62
5055 09:27:44.208907
5056 09:27:44.211651 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5057 09:27:44.211755
5058 09:27:44.215407 [CATrainingPosCal] consider 1 rank data
5059 09:27:44.218711 u2DelayCellTimex100 = 270/100 ps
5060 09:27:44.221746 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5061 09:27:44.225425 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5062 09:27:44.228231 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5063 09:27:44.231816 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5064 09:27:44.235333 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5065 09:27:44.241610 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 09:27:44.241714
5067 09:27:44.244838 CA PerBit enable=1, Macro0, CA PI delay=33
5068 09:27:44.244943
5069 09:27:44.248013 [CBTSetCACLKResult] CA Dly = 33
5070 09:27:44.248089 CS Dly: 6 (0~37)
5071 09:27:44.248220 ==
5072 09:27:44.251270 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 09:27:44.258107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 09:27:44.258219 ==
5075 09:27:44.261082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 09:27:44.267782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5077 09:27:44.271315 [CA 0] Center 38 (8~69) winsize 62
5078 09:27:44.274840 [CA 1] Center 38 (8~69) winsize 62
5079 09:27:44.278018 [CA 2] Center 35 (5~66) winsize 62
5080 09:27:44.280987 [CA 3] Center 35 (5~66) winsize 62
5081 09:27:44.284581 [CA 4] Center 34 (4~65) winsize 62
5082 09:27:44.288164 [CA 5] Center 33 (3~64) winsize 62
5083 09:27:44.288268
5084 09:27:44.291138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5085 09:27:44.291234
5086 09:27:44.294573 [CATrainingPosCal] consider 2 rank data
5087 09:27:44.297624 u2DelayCellTimex100 = 270/100 ps
5088 09:27:44.301231 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5089 09:27:44.304130 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5090 09:27:44.310992 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5091 09:27:44.314345 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5092 09:27:44.317163 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5093 09:27:44.320776 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 09:27:44.320882
5095 09:27:44.323744 CA PerBit enable=1, Macro0, CA PI delay=33
5096 09:27:44.323820
5097 09:27:44.327239 [CBTSetCACLKResult] CA Dly = 33
5098 09:27:44.327337 CS Dly: 7 (0~39)
5099 09:27:44.327454
5100 09:27:44.330914 ----->DramcWriteLeveling(PI) begin...
5101 09:27:44.333910 ==
5102 09:27:44.337354 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 09:27:44.340401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 09:27:44.340492 ==
5105 09:27:44.343827 Write leveling (Byte 0): 30 => 30
5106 09:27:44.346889 Write leveling (Byte 1): 29 => 29
5107 09:27:44.350223 DramcWriteLeveling(PI) end<-----
5108 09:27:44.350325
5109 09:27:44.350419 ==
5110 09:27:44.353937 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 09:27:44.356989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 09:27:44.357089 ==
5113 09:27:44.360522 [Gating] SW mode calibration
5114 09:27:44.367023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 09:27:44.373794 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5116 09:27:44.376800 0 14 0 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
5117 09:27:44.380532 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5118 09:27:44.386692 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 09:27:44.390186 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 09:27:44.393641 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 09:27:44.400154 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 09:27:44.403132 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 09:27:44.406557 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5124 09:27:44.413170 0 15 0 | B1->B0 | 3333 2626 | 0 0 | (0 0) (1 0)
5125 09:27:44.416559 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5126 09:27:44.419960 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 09:27:44.426229 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 09:27:44.429758 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 09:27:44.432965 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 09:27:44.439315 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 09:27:44.442964 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5132 09:27:44.446395 1 0 0 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (1 1)
5133 09:27:44.452989 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5134 09:27:44.456480 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 09:27:44.459603 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 09:27:44.466321 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 09:27:44.469248 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 09:27:44.472797 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 09:27:44.479382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 09:27:44.482938 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 09:27:44.486040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 09:27:44.489379 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 09:27:44.495835 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 09:27:44.499256 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 09:27:44.502766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 09:27:44.509291 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 09:27:44.512613 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 09:27:44.515782 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 09:27:44.522541 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 09:27:44.525887 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 09:27:44.529115 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 09:27:44.535653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 09:27:44.539357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 09:27:44.542315 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 09:27:44.549112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 09:27:44.552089 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5157 09:27:44.555467 Total UI for P1: 0, mck2ui 16
5158 09:27:44.558919 best dqsien dly found for B0: ( 1, 2, 30)
5159 09:27:44.562473 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5160 09:27:44.568896 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 09:27:44.569008 Total UI for P1: 0, mck2ui 16
5162 09:27:44.575494 best dqsien dly found for B1: ( 1, 3, 4)
5163 09:27:44.578509 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5164 09:27:44.582136 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5165 09:27:44.582239
5166 09:27:44.585298 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5167 09:27:44.588859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5168 09:27:44.591839 [Gating] SW calibration Done
5169 09:27:44.591920 ==
5170 09:27:44.595512 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 09:27:44.598796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 09:27:44.598901 ==
5173 09:27:44.602168 RX Vref Scan: 0
5174 09:27:44.602274
5175 09:27:44.602365 RX Vref 0 -> 0, step: 1
5176 09:27:44.602447
5177 09:27:44.605636 RX Delay -80 -> 252, step: 8
5178 09:27:44.608710 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5179 09:27:44.615487 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5180 09:27:44.618726 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5181 09:27:44.621985 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5182 09:27:44.625117 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5183 09:27:44.628565 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5184 09:27:44.631715 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5185 09:27:44.638596 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5186 09:27:44.641828 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5187 09:27:44.645123 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5188 09:27:44.648676 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5189 09:27:44.651838 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5190 09:27:44.658960 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5191 09:27:44.661856 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5192 09:27:44.665313 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5193 09:27:44.668252 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5194 09:27:44.668368 ==
5195 09:27:44.671845 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 09:27:44.675296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 09:27:44.678233 ==
5198 09:27:44.678338 DQS Delay:
5199 09:27:44.678429 DQS0 = 0, DQS1 = 0
5200 09:27:44.682009 DQM Delay:
5201 09:27:44.682079 DQM0 = 94, DQM1 = 84
5202 09:27:44.684857 DQ Delay:
5203 09:27:44.684939 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5204 09:27:44.688431 DQ4 =95, DQ5 =83, DQ6 =99, DQ7 =107
5205 09:27:44.692113 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5206 09:27:44.695141 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5207 09:27:44.698411
5208 09:27:44.698494
5209 09:27:44.698558 ==
5210 09:27:44.701790 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 09:27:44.705335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 09:27:44.705447 ==
5213 09:27:44.705541
5214 09:27:44.705600
5215 09:27:44.708248 TX Vref Scan disable
5216 09:27:44.708356 == TX Byte 0 ==
5217 09:27:44.715125 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5218 09:27:44.718535 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5219 09:27:44.718654 == TX Byte 1 ==
5220 09:27:44.725318 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5221 09:27:44.728220 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5222 09:27:44.728302 ==
5223 09:27:44.731635 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 09:27:44.734581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 09:27:44.734672 ==
5226 09:27:44.734734
5227 09:27:44.734793
5228 09:27:44.737732 TX Vref Scan disable
5229 09:27:44.741540 == TX Byte 0 ==
5230 09:27:44.744288 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5231 09:27:44.748071 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5232 09:27:44.751244 == TX Byte 1 ==
5233 09:27:44.754346 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5234 09:27:44.757673 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5235 09:27:44.757772
5236 09:27:44.761322 [DATLAT]
5237 09:27:44.761427 Freq=933, CH0 RK0
5238 09:27:44.761522
5239 09:27:44.764785 DATLAT Default: 0xd
5240 09:27:44.764889 0, 0xFFFF, sum = 0
5241 09:27:44.767846 1, 0xFFFF, sum = 0
5242 09:27:44.767946 2, 0xFFFF, sum = 0
5243 09:27:44.771552 3, 0xFFFF, sum = 0
5244 09:27:44.771659 4, 0xFFFF, sum = 0
5245 09:27:44.774662 5, 0xFFFF, sum = 0
5246 09:27:44.774745 6, 0xFFFF, sum = 0
5247 09:27:44.778171 7, 0xFFFF, sum = 0
5248 09:27:44.778275 8, 0xFFFF, sum = 0
5249 09:27:44.781344 9, 0xFFFF, sum = 0
5250 09:27:44.781451 10, 0x0, sum = 1
5251 09:27:44.784492 11, 0x0, sum = 2
5252 09:27:44.784593 12, 0x0, sum = 3
5253 09:27:44.788052 13, 0x0, sum = 4
5254 09:27:44.788135 best_step = 11
5255 09:27:44.788200
5256 09:27:44.788279 ==
5257 09:27:44.791620 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 09:27:44.797507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 09:27:44.797592 ==
5260 09:27:44.797657 RX Vref Scan: 1
5261 09:27:44.797747
5262 09:27:44.801087 RX Vref 0 -> 0, step: 1
5263 09:27:44.801185
5264 09:27:44.803979 RX Delay -69 -> 252, step: 4
5265 09:27:44.804077
5266 09:27:44.807802 Set Vref, RX VrefLevel [Byte0]: 64
5267 09:27:44.811239 [Byte1]: 57
5268 09:27:44.811338
5269 09:27:44.814201 Final RX Vref Byte 0 = 64 to rank0
5270 09:27:44.817488 Final RX Vref Byte 1 = 57 to rank0
5271 09:27:44.820928 Final RX Vref Byte 0 = 64 to rank1
5272 09:27:44.824447 Final RX Vref Byte 1 = 57 to rank1==
5273 09:27:44.827334 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 09:27:44.830987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 09:27:44.831094 ==
5276 09:27:44.834096 DQS Delay:
5277 09:27:44.834195 DQS0 = 0, DQS1 = 0
5278 09:27:44.837432 DQM Delay:
5279 09:27:44.837535 DQM0 = 96, DQM1 = 84
5280 09:27:44.837634 DQ Delay:
5281 09:27:44.841098 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5282 09:27:44.844259 DQ4 =96, DQ5 =82, DQ6 =106, DQ7 =108
5283 09:27:44.847822 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5284 09:27:44.851215 DQ12 =90, DQ13 =86, DQ14 =96, DQ15 =90
5285 09:27:44.851323
5286 09:27:44.851418
5287 09:27:44.860572 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5288 09:27:44.864067 CH0 RK0: MR19=505, MR18=1010
5289 09:27:44.870652 CH0_RK0: MR19=0x505, MR18=0x1010, DQSOSC=416, MR23=63, INC=62, DEC=41
5290 09:27:44.870733
5291 09:27:44.874272 ----->DramcWriteLeveling(PI) begin...
5292 09:27:44.874374 ==
5293 09:27:44.877590 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 09:27:44.880517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 09:27:44.880640 ==
5296 09:27:44.883916 Write leveling (Byte 0): 29 => 29
5297 09:27:44.887115 Write leveling (Byte 1): 29 => 29
5298 09:27:44.890726 DramcWriteLeveling(PI) end<-----
5299 09:27:44.890837
5300 09:27:44.890928 ==
5301 09:27:44.893871 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 09:27:44.897624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 09:27:44.897721 ==
5304 09:27:44.900546 [Gating] SW mode calibration
5305 09:27:44.907285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5306 09:27:44.914013 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5307 09:27:44.917523 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5308 09:27:44.920335 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 09:27:44.927025 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 09:27:44.930386 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 09:27:44.933904 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 09:27:44.940597 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 09:27:44.943538 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 09:27:44.947180 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5315 09:27:44.953838 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5316 09:27:44.956720 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 09:27:44.960337 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 09:27:44.966754 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 09:27:44.970167 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 09:27:44.973752 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 09:27:44.980464 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5322 09:27:44.983721 0 15 28 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5323 09:27:44.987047 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5324 09:27:44.990309 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 09:27:44.997125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 09:27:44.999951 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 09:27:45.003309 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 09:27:45.009944 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 09:27:45.013253 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 09:27:45.016821 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5331 09:27:45.023567 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5332 09:27:45.026513 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 09:27:45.030120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 09:27:45.036457 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 09:27:45.039718 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 09:27:45.043598 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 09:27:45.049539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 09:27:45.053206 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 09:27:45.056212 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 09:27:45.063210 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 09:27:45.066340 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 09:27:45.069848 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 09:27:45.076358 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:27:45.079808 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:27:45.082954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 09:27:45.089943 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5347 09:27:45.090028 Total UI for P1: 0, mck2ui 16
5348 09:27:45.096371 best dqsien dly found for B0: ( 1, 2, 26)
5349 09:27:45.099629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5350 09:27:45.103066 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 09:27:45.106657 Total UI for P1: 0, mck2ui 16
5352 09:27:45.109639 best dqsien dly found for B1: ( 1, 2, 30)
5353 09:27:45.112979 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 09:27:45.116382 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5355 09:27:45.116479
5356 09:27:45.119549 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 09:27:45.126112 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5358 09:27:45.126230 [Gating] SW calibration Done
5359 09:27:45.129906 ==
5360 09:27:45.130007 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 09:27:45.136381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 09:27:45.136489 ==
5363 09:27:45.136555 RX Vref Scan: 0
5364 09:27:45.136619
5365 09:27:45.139301 RX Vref 0 -> 0, step: 1
5366 09:27:45.139417
5367 09:27:45.142813 RX Delay -80 -> 252, step: 8
5368 09:27:45.146290 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5369 09:27:45.149611 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5370 09:27:45.152859 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5371 09:27:45.159310 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5372 09:27:45.162425 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5373 09:27:45.165894 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5374 09:27:45.169323 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5375 09:27:45.172341 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5376 09:27:45.176132 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5377 09:27:45.182851 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5378 09:27:45.185659 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5379 09:27:45.189366 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5380 09:27:45.192191 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5381 09:27:45.199218 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5382 09:27:45.202090 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5383 09:27:45.205528 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5384 09:27:45.205608 ==
5385 09:27:45.208654 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 09:27:45.212213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 09:27:45.212316 ==
5388 09:27:45.215893 DQS Delay:
5389 09:27:45.215995 DQS0 = 0, DQS1 = 0
5390 09:27:45.216085 DQM Delay:
5391 09:27:45.218793 DQM0 = 92, DQM1 = 83
5392 09:27:45.218894 DQ Delay:
5393 09:27:45.222344 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5394 09:27:45.225562 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5395 09:27:45.229077 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5396 09:27:45.232126 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5397 09:27:45.232205
5398 09:27:45.232295
5399 09:27:45.235634 ==
5400 09:27:45.235713 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 09:27:45.241805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 09:27:45.241882 ==
5403 09:27:45.241948
5404 09:27:45.242019
5405 09:27:45.245859 TX Vref Scan disable
5406 09:27:45.245964 == TX Byte 0 ==
5407 09:27:45.248862 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5408 09:27:45.255553 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5409 09:27:45.255659 == TX Byte 1 ==
5410 09:27:45.258895 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5411 09:27:45.265230 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5412 09:27:45.265319 ==
5413 09:27:45.268672 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 09:27:45.272212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 09:27:45.272297 ==
5416 09:27:45.272361
5417 09:27:45.272420
5418 09:27:45.275123 TX Vref Scan disable
5419 09:27:45.278224 == TX Byte 0 ==
5420 09:27:45.281886 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5421 09:27:45.285287 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5422 09:27:45.288305 == TX Byte 1 ==
5423 09:27:45.291802 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5424 09:27:45.294776 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5425 09:27:45.294858
5426 09:27:45.298154 [DATLAT]
5427 09:27:45.298239 Freq=933, CH0 RK1
5428 09:27:45.298317
5429 09:27:45.301758 DATLAT Default: 0xb
5430 09:27:45.301840 0, 0xFFFF, sum = 0
5431 09:27:45.304811 1, 0xFFFF, sum = 0
5432 09:27:45.304894 2, 0xFFFF, sum = 0
5433 09:27:45.308315 3, 0xFFFF, sum = 0
5434 09:27:45.308428 4, 0xFFFF, sum = 0
5435 09:27:45.311317 5, 0xFFFF, sum = 0
5436 09:27:45.311439 6, 0xFFFF, sum = 0
5437 09:27:45.314644 7, 0xFFFF, sum = 0
5438 09:27:45.314738 8, 0xFFFF, sum = 0
5439 09:27:45.318022 9, 0xFFFF, sum = 0
5440 09:27:45.318139 10, 0x0, sum = 1
5441 09:27:45.321709 11, 0x0, sum = 2
5442 09:27:45.321787 12, 0x0, sum = 3
5443 09:27:45.324762 13, 0x0, sum = 4
5444 09:27:45.324914 best_step = 11
5445 09:27:45.325055
5446 09:27:45.325142 ==
5447 09:27:45.328260 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 09:27:45.334522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 09:27:45.334636 ==
5450 09:27:45.334727 RX Vref Scan: 0
5451 09:27:45.334813
5452 09:27:45.338187 RX Vref 0 -> 0, step: 1
5453 09:27:45.338288
5454 09:27:45.341240 RX Delay -77 -> 252, step: 4
5455 09:27:45.344920 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5456 09:27:45.347814 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5457 09:27:45.354067 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5458 09:27:45.358220 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5459 09:27:45.361134 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5460 09:27:45.364211 iDelay=199, Bit 5, Center 80 (-9 ~ 170) 180
5461 09:27:45.367588 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5462 09:27:45.374452 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5463 09:27:45.377297 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5464 09:27:45.380917 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5465 09:27:45.383861 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5466 09:27:45.387048 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5467 09:27:45.394035 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5468 09:27:45.396945 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5469 09:27:45.400372 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5470 09:27:45.403891 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5471 09:27:45.404005 ==
5472 09:27:45.407285 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 09:27:45.413257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 09:27:45.413369 ==
5475 09:27:45.413464 DQS Delay:
5476 09:27:45.413553 DQS0 = 0, DQS1 = 0
5477 09:27:45.416842 DQM Delay:
5478 09:27:45.416940 DQM0 = 93, DQM1 = 84
5479 09:27:45.419993 DQ Delay:
5480 09:27:45.423428 DQ0 =90, DQ1 =96, DQ2 =90, DQ3 =88
5481 09:27:45.426727 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5482 09:27:45.429928 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5483 09:27:45.433240 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =90
5484 09:27:45.433342
5485 09:27:45.433435
5486 09:27:45.440237 [DQSOSCAuto] RK1, (LSB)MR18= 0x3012, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5487 09:27:45.443056 CH0 RK1: MR19=505, MR18=3012
5488 09:27:45.449899 CH0_RK1: MR19=0x505, MR18=0x3012, DQSOSC=406, MR23=63, INC=65, DEC=43
5489 09:27:45.452809 [RxdqsGatingPostProcess] freq 933
5490 09:27:45.456437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 09:27:45.459873 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 09:27:45.462989 best DQS1 dly(2T, 0.5T) = (0, 11)
5493 09:27:45.466177 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 09:27:45.469355 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5495 09:27:45.472846 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 09:27:45.476161 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 09:27:45.479515 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 09:27:45.482710 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 09:27:45.486128 Pre-setting of DQS Precalculation
5500 09:27:45.489145 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 09:27:45.492444 ==
5502 09:27:45.495988 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 09:27:45.499533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 09:27:45.499616 ==
5505 09:27:45.502430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 09:27:45.509127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5507 09:27:45.512740 [CA 0] Center 36 (7~66) winsize 60
5508 09:27:45.516363 [CA 1] Center 37 (7~67) winsize 61
5509 09:27:45.519320 [CA 2] Center 34 (4~64) winsize 61
5510 09:27:45.522875 [CA 3] Center 34 (4~64) winsize 61
5511 09:27:45.525998 [CA 4] Center 34 (4~64) winsize 61
5512 09:27:45.529276 [CA 5] Center 33 (4~63) winsize 60
5513 09:27:45.529354
5514 09:27:45.532578 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5515 09:27:45.532652
5516 09:27:45.536061 [CATrainingPosCal] consider 1 rank data
5517 09:27:45.539561 u2DelayCellTimex100 = 270/100 ps
5518 09:27:45.542836 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5519 09:27:45.549656 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5520 09:27:45.552714 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 09:27:45.555754 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 09:27:45.559245 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 09:27:45.562785 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5524 09:27:45.562867
5525 09:27:45.566426 CA PerBit enable=1, Macro0, CA PI delay=33
5526 09:27:45.566589
5527 09:27:45.569358 [CBTSetCACLKResult] CA Dly = 33
5528 09:27:45.569466 CS Dly: 6 (0~37)
5529 09:27:45.573017 ==
5530 09:27:45.573120 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 09:27:45.579142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 09:27:45.579252 ==
5533 09:27:45.582537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 09:27:45.589143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5535 09:27:45.592961 [CA 0] Center 37 (7~67) winsize 61
5536 09:27:45.596059 [CA 1] Center 37 (7~68) winsize 62
5537 09:27:45.599411 [CA 2] Center 34 (5~64) winsize 60
5538 09:27:45.603046 [CA 3] Center 34 (4~64) winsize 61
5539 09:27:45.606788 [CA 4] Center 34 (4~65) winsize 62
5540 09:27:45.609536 [CA 5] Center 33 (3~64) winsize 62
5541 09:27:45.609612
5542 09:27:45.612899 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5543 09:27:45.612984
5544 09:27:45.616028 [CATrainingPosCal] consider 2 rank data
5545 09:27:45.619307 u2DelayCellTimex100 = 270/100 ps
5546 09:27:45.623028 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5547 09:27:45.626175 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5548 09:27:45.632718 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5549 09:27:45.636204 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 09:27:45.639564 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5551 09:27:45.642455 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5552 09:27:45.642530
5553 09:27:45.646000 CA PerBit enable=1, Macro0, CA PI delay=33
5554 09:27:45.646120
5555 09:27:45.649357 [CBTSetCACLKResult] CA Dly = 33
5556 09:27:45.649485 CS Dly: 7 (0~39)
5557 09:27:45.649586
5558 09:27:45.652757 ----->DramcWriteLeveling(PI) begin...
5559 09:27:45.656072 ==
5560 09:27:45.659637 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 09:27:45.662516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 09:27:45.662614 ==
5563 09:27:45.666123 Write leveling (Byte 0): 27 => 27
5564 09:27:45.669134 Write leveling (Byte 1): 27 => 27
5565 09:27:45.672637 DramcWriteLeveling(PI) end<-----
5566 09:27:45.672713
5567 09:27:45.672773 ==
5568 09:27:45.675821 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 09:27:45.679499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 09:27:45.679599 ==
5571 09:27:45.682231 [Gating] SW mode calibration
5572 09:27:45.689000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 09:27:45.695542 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 09:27:45.699094 0 14 0 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (1 1)
5575 09:27:45.702462 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 09:27:45.709005 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 09:27:45.712185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 09:27:45.715894 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 09:27:45.722420 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 09:27:45.725588 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 09:27:45.728562 0 14 28 | B1->B0 | 2f2f 3232 | 0 0 | (1 0) (0 0)
5582 09:27:45.735654 0 15 0 | B1->B0 | 2a2a 2b2b | 0 1 | (1 0) (1 0)
5583 09:27:45.738687 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 09:27:45.742345 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 09:27:45.748610 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 09:27:45.752252 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 09:27:45.755295 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 09:27:45.758703 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 09:27:45.765397 0 15 28 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
5590 09:27:45.768436 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 09:27:45.771945 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 09:27:45.778863 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 09:27:45.781873 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 09:27:45.785422 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 09:27:45.792142 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 09:27:45.795360 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 09:27:45.798346 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5598 09:27:45.805481 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5599 09:27:45.808519 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 09:27:45.811884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 09:27:45.818401 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 09:27:45.821671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 09:27:45.825439 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 09:27:45.831863 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 09:27:45.835030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 09:27:45.838512 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 09:27:45.845221 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:27:45.848222 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:27:45.851764 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:27:45.858142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:27:45.861768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:27:45.864806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:27:45.871846 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5614 09:27:45.874902 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5615 09:27:45.878052 Total UI for P1: 0, mck2ui 16
5616 09:27:45.881571 best dqsien dly found for B0: ( 1, 2, 30)
5617 09:27:45.884738 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 09:27:45.888211 Total UI for P1: 0, mck2ui 16
5619 09:27:45.891345 best dqsien dly found for B1: ( 1, 2, 30)
5620 09:27:45.894871 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5621 09:27:45.898064 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5622 09:27:45.898145
5623 09:27:45.901685 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5624 09:27:45.907943 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5625 09:27:45.908025 [Gating] SW calibration Done
5626 09:27:45.908089 ==
5627 09:27:45.911276 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 09:27:45.917736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 09:27:45.917831 ==
5630 09:27:45.917897 RX Vref Scan: 0
5631 09:27:45.917957
5632 09:27:45.921129 RX Vref 0 -> 0, step: 1
5633 09:27:45.921210
5634 09:27:45.924571 RX Delay -80 -> 252, step: 8
5635 09:27:45.927913 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5636 09:27:45.931211 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5637 09:27:45.934249 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5638 09:27:45.941209 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5639 09:27:45.944379 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5640 09:27:45.947803 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5641 09:27:45.951435 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5642 09:27:45.954285 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5643 09:27:45.957862 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5644 09:27:45.964161 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5645 09:27:45.967520 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5646 09:27:45.971012 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5647 09:27:45.974485 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5648 09:27:45.977810 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5649 09:27:45.984112 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5650 09:27:45.987626 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5651 09:27:45.987726 ==
5652 09:27:45.990777 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 09:27:45.994517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 09:27:45.994598 ==
5655 09:27:45.994662 DQS Delay:
5656 09:27:45.997367 DQS0 = 0, DQS1 = 0
5657 09:27:45.997447 DQM Delay:
5658 09:27:46.001096 DQM0 = 94, DQM1 = 87
5659 09:27:46.001177 DQ Delay:
5660 09:27:46.004291 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5661 09:27:46.007256 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5662 09:27:46.010813 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5663 09:27:46.014394 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5664 09:27:46.014475
5665 09:27:46.014539
5666 09:27:46.014596 ==
5667 09:27:46.017303 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 09:27:46.024105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 09:27:46.024187 ==
5670 09:27:46.024250
5671 09:27:46.024309
5672 09:27:46.024366 TX Vref Scan disable
5673 09:27:46.027609 == TX Byte 0 ==
5674 09:27:46.030909 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5675 09:27:46.037093 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5676 09:27:46.037174 == TX Byte 1 ==
5677 09:27:46.040594 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 09:27:46.047243 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 09:27:46.047458 ==
5680 09:27:46.050313 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 09:27:46.053650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 09:27:46.053766 ==
5683 09:27:46.053836
5684 09:27:46.053897
5685 09:27:46.056804 TX Vref Scan disable
5686 09:27:46.056892 == TX Byte 0 ==
5687 09:27:46.063982 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5688 09:27:46.067003 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5689 09:27:46.067103 == TX Byte 1 ==
5690 09:27:46.073735 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5691 09:27:46.077184 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5692 09:27:46.077275
5693 09:27:46.077339 [DATLAT]
5694 09:27:46.080328 Freq=933, CH1 RK0
5695 09:27:46.080411
5696 09:27:46.080475 DATLAT Default: 0xd
5697 09:27:46.083703 0, 0xFFFF, sum = 0
5698 09:27:46.083789 1, 0xFFFF, sum = 0
5699 09:27:46.086876 2, 0xFFFF, sum = 0
5700 09:27:46.089936 3, 0xFFFF, sum = 0
5701 09:27:46.090057 4, 0xFFFF, sum = 0
5702 09:27:46.093425 5, 0xFFFF, sum = 0
5703 09:27:46.093512 6, 0xFFFF, sum = 0
5704 09:27:46.097063 7, 0xFFFF, sum = 0
5705 09:27:46.097151 8, 0xFFFF, sum = 0
5706 09:27:46.100164 9, 0xFFFF, sum = 0
5707 09:27:46.100246 10, 0x0, sum = 1
5708 09:27:46.103644 11, 0x0, sum = 2
5709 09:27:46.103761 12, 0x0, sum = 3
5710 09:27:46.103858 13, 0x0, sum = 4
5711 09:27:46.106842 best_step = 11
5712 09:27:46.106986
5713 09:27:46.107078 ==
5714 09:27:46.110361 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 09:27:46.113336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 09:27:46.113435 ==
5717 09:27:46.116996 RX Vref Scan: 1
5718 09:27:46.117091
5719 09:27:46.120078 RX Vref 0 -> 0, step: 1
5720 09:27:46.120166
5721 09:27:46.120265 RX Delay -61 -> 252, step: 4
5722 09:27:46.120354
5723 09:27:46.123594 Set Vref, RX VrefLevel [Byte0]: 56
5724 09:27:46.126467 [Byte1]: 56
5725 09:27:46.131320
5726 09:27:46.131419 Final RX Vref Byte 0 = 56 to rank0
5727 09:27:46.134804 Final RX Vref Byte 1 = 56 to rank0
5728 09:27:46.137751 Final RX Vref Byte 0 = 56 to rank1
5729 09:27:46.141249 Final RX Vref Byte 1 = 56 to rank1==
5730 09:27:46.144429 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 09:27:46.151378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 09:27:46.151601 ==
5733 09:27:46.151708 DQS Delay:
5734 09:27:46.154388 DQS0 = 0, DQS1 = 0
5735 09:27:46.154486 DQM Delay:
5736 09:27:46.154575 DQM0 = 95, DQM1 = 87
5737 09:27:46.157947 DQ Delay:
5738 09:27:46.161186 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =90
5739 09:27:46.164392 DQ4 =94, DQ5 =104, DQ6 =106, DQ7 =92
5740 09:27:46.167574 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5741 09:27:46.171214 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5742 09:27:46.171320
5743 09:27:46.171445
5744 09:27:46.177362 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5745 09:27:46.180607 CH1 RK0: MR19=505, MR18=9
5746 09:27:46.187778 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5747 09:27:46.187863
5748 09:27:46.190550 ----->DramcWriteLeveling(PI) begin...
5749 09:27:46.190632 ==
5750 09:27:46.193902 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 09:27:46.197260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 09:27:46.197342 ==
5753 09:27:46.200793 Write leveling (Byte 0): 25 => 25
5754 09:27:46.204273 Write leveling (Byte 1): 25 => 25
5755 09:27:46.207332 DramcWriteLeveling(PI) end<-----
5756 09:27:46.207448
5757 09:27:46.207512 ==
5758 09:27:46.210405 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 09:27:46.214169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 09:27:46.214250 ==
5761 09:27:46.217568 [Gating] SW mode calibration
5762 09:27:46.223814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 09:27:46.230987 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 09:27:46.233804 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 09:27:46.237501 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 09:27:46.244004 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 09:27:46.246961 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 09:27:46.250474 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 09:27:46.257065 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 09:27:46.260640 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5771 09:27:46.263772 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5772 09:27:46.270028 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 09:27:46.273574 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 09:27:46.276810 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 09:27:46.283216 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 09:27:46.287139 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 09:27:46.290332 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 09:27:46.296633 0 15 24 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
5779 09:27:46.300057 0 15 28 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
5780 09:27:46.303264 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 09:27:46.309655 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 09:27:46.313376 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 09:27:46.316365 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 09:27:46.323106 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 09:27:46.326723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 09:27:46.329868 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 09:27:46.336368 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 09:27:46.339676 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 09:27:46.343350 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 09:27:46.350136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 09:27:46.353213 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 09:27:46.356199 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 09:27:46.362801 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 09:27:46.366770 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 09:27:46.370137 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 09:27:46.376272 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 09:27:46.379623 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 09:27:46.383194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:27:46.389597 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:27:46.392948 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:27:46.396320 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5802 09:27:46.399563 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5803 09:27:46.406187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 09:27:46.409233 Total UI for P1: 0, mck2ui 16
5805 09:27:46.412857 best dqsien dly found for B0: ( 1, 2, 22)
5806 09:27:46.416343 Total UI for P1: 0, mck2ui 16
5807 09:27:46.419429 best dqsien dly found for B1: ( 1, 2, 26)
5808 09:27:46.422901 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5809 09:27:46.426074 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5810 09:27:46.426170
5811 09:27:46.429559 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5812 09:27:46.432660 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 09:27:46.435851 [Gating] SW calibration Done
5814 09:27:46.435934 ==
5815 09:27:46.439295 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 09:27:46.442954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 09:27:46.443048 ==
5818 09:27:46.445999 RX Vref Scan: 0
5819 09:27:46.446082
5820 09:27:46.449595 RX Vref 0 -> 0, step: 1
5821 09:27:46.449676
5822 09:27:46.449741 RX Delay -80 -> 252, step: 8
5823 09:27:46.455893 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5824 09:27:46.459475 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5825 09:27:46.462415 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5826 09:27:46.465643 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5827 09:27:46.469195 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5828 09:27:46.472459 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5829 09:27:46.479123 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5830 09:27:46.482734 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5831 09:27:46.486224 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5832 09:27:46.489043 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5833 09:27:46.492707 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5834 09:27:46.499302 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5835 09:27:46.502482 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5836 09:27:46.506051 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5837 09:27:46.509068 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5838 09:27:46.512747 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5839 09:27:46.512828 ==
5840 09:27:46.515636 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 09:27:46.522341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 09:27:46.522447 ==
5843 09:27:46.522539 DQS Delay:
5844 09:27:46.525975 DQS0 = 0, DQS1 = 0
5845 09:27:46.526076 DQM Delay:
5846 09:27:46.526215 DQM0 = 94, DQM1 = 89
5847 09:27:46.529053 DQ Delay:
5848 09:27:46.532122 DQ0 =95, DQ1 =91, DQ2 =79, DQ3 =91
5849 09:27:46.535974 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5850 09:27:46.539093 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5851 09:27:46.542318 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5852 09:27:46.542416
5853 09:27:46.542505
5854 09:27:46.542595 ==
5855 09:27:46.545836 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 09:27:46.548903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 09:27:46.549009 ==
5858 09:27:46.549098
5859 09:27:46.549183
5860 09:27:46.552654 TX Vref Scan disable
5861 09:27:46.552761 == TX Byte 0 ==
5862 09:27:46.559119 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5863 09:27:46.562205 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5864 09:27:46.562311 == TX Byte 1 ==
5865 09:27:46.568741 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5866 09:27:46.571940 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5867 09:27:46.572037 ==
5868 09:27:46.575684 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 09:27:46.578952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 09:27:46.579025 ==
5871 09:27:46.582053
5872 09:27:46.582121
5873 09:27:46.582200 TX Vref Scan disable
5874 09:27:46.585318 == TX Byte 0 ==
5875 09:27:46.588980 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5876 09:27:46.595344 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5877 09:27:46.595441 == TX Byte 1 ==
5878 09:27:46.598342 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5879 09:27:46.605280 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5880 09:27:46.605378
5881 09:27:46.605467 [DATLAT]
5882 09:27:46.605559 Freq=933, CH1 RK1
5883 09:27:46.605619
5884 09:27:46.608744 DATLAT Default: 0xb
5885 09:27:46.608816 0, 0xFFFF, sum = 0
5886 09:27:46.611668 1, 0xFFFF, sum = 0
5887 09:27:46.611739 2, 0xFFFF, sum = 0
5888 09:27:46.614935 3, 0xFFFF, sum = 0
5889 09:27:46.618041 4, 0xFFFF, sum = 0
5890 09:27:46.618123 5, 0xFFFF, sum = 0
5891 09:27:46.621412 6, 0xFFFF, sum = 0
5892 09:27:46.621494 7, 0xFFFF, sum = 0
5893 09:27:46.624746 8, 0xFFFF, sum = 0
5894 09:27:46.624827 9, 0xFFFF, sum = 0
5895 09:27:46.628133 10, 0x0, sum = 1
5896 09:27:46.628215 11, 0x0, sum = 2
5897 09:27:46.631349 12, 0x0, sum = 3
5898 09:27:46.631479 13, 0x0, sum = 4
5899 09:27:46.631545 best_step = 11
5900 09:27:46.634629
5901 09:27:46.634709 ==
5902 09:27:46.638104 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 09:27:46.641172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 09:27:46.641252 ==
5905 09:27:46.641316 RX Vref Scan: 0
5906 09:27:46.641375
5907 09:27:46.644592 RX Vref 0 -> 0, step: 1
5908 09:27:46.644671
5909 09:27:46.648323 RX Delay -61 -> 252, step: 4
5910 09:27:46.654777 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5911 09:27:46.657941 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5912 09:27:46.661667 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5913 09:27:46.664746 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5914 09:27:46.667967 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
5915 09:27:46.671363 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5916 09:27:46.678157 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5917 09:27:46.681113 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5918 09:27:46.684410 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5919 09:27:46.687523 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5920 09:27:46.690937 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5921 09:27:46.697772 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5922 09:27:46.701234 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5923 09:27:46.704203 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5924 09:27:46.707461 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5925 09:27:46.710977 iDelay=203, Bit 15, Center 98 (3 ~ 194) 192
5926 09:27:46.711058 ==
5927 09:27:46.714684 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 09:27:46.720886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 09:27:46.720967 ==
5930 09:27:46.721031 DQS Delay:
5931 09:27:46.723836 DQS0 = 0, DQS1 = 0
5932 09:27:46.723916 DQM Delay:
5933 09:27:46.723979 DQM0 = 93, DQM1 = 89
5934 09:27:46.727376 DQ Delay:
5935 09:27:46.730806 DQ0 =98, DQ1 =88, DQ2 =82, DQ3 =90
5936 09:27:46.733800 DQ4 =92, DQ5 =102, DQ6 =104, DQ7 =90
5937 09:27:46.737484 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
5938 09:27:46.740628 DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =98
5939 09:27:46.740709
5940 09:27:46.740772
5941 09:27:46.747326 [DQSOSCAuto] RK1, (LSB)MR18= 0xc20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5942 09:27:46.750694 CH1 RK1: MR19=505, MR18=C20
5943 09:27:46.757137 CH1_RK1: MR19=0x505, MR18=0xC20, DQSOSC=411, MR23=63, INC=64, DEC=42
5944 09:27:46.760634 [RxdqsGatingPostProcess] freq 933
5945 09:27:46.763693 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 09:27:46.767458 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 09:27:46.770754 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 09:27:46.774010 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 09:27:46.776886 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 09:27:46.780144 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 09:27:46.783962 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 09:27:46.787005 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 09:27:46.789986 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 09:27:46.793608 Pre-setting of DQS Precalculation
5955 09:27:46.797344 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 09:27:46.807222 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 09:27:46.813877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 09:27:46.813961
5959 09:27:46.814024
5960 09:27:46.816734 [Calibration Summary] 1866 Mbps
5961 09:27:46.816815 CH 0, Rank 0
5962 09:27:46.820084 SW Impedance : PASS
5963 09:27:46.820181 DUTY Scan : NO K
5964 09:27:46.823642 ZQ Calibration : PASS
5965 09:27:46.826602 Jitter Meter : NO K
5966 09:27:46.826683 CBT Training : PASS
5967 09:27:46.830216 Write leveling : PASS
5968 09:27:46.833260 RX DQS gating : PASS
5969 09:27:46.833341 RX DQ/DQS(RDDQC) : PASS
5970 09:27:46.836845 TX DQ/DQS : PASS
5971 09:27:46.839831 RX DATLAT : PASS
5972 09:27:46.839911 RX DQ/DQS(Engine): PASS
5973 09:27:46.843451 TX OE : NO K
5974 09:27:46.843558 All Pass.
5975 09:27:46.843650
5976 09:27:46.846494 CH 0, Rank 1
5977 09:27:46.846590 SW Impedance : PASS
5978 09:27:46.850061 DUTY Scan : NO K
5979 09:27:46.853614 ZQ Calibration : PASS
5980 09:27:46.853695 Jitter Meter : NO K
5981 09:27:46.856561 CBT Training : PASS
5982 09:27:46.856683 Write leveling : PASS
5983 09:27:46.860292 RX DQS gating : PASS
5984 09:27:46.863065 RX DQ/DQS(RDDQC) : PASS
5985 09:27:46.863172 TX DQ/DQS : PASS
5986 09:27:46.866516 RX DATLAT : PASS
5987 09:27:46.869674 RX DQ/DQS(Engine): PASS
5988 09:27:46.869763 TX OE : NO K
5989 09:27:46.872992 All Pass.
5990 09:27:46.873072
5991 09:27:46.873136 CH 1, Rank 0
5992 09:27:46.876667 SW Impedance : PASS
5993 09:27:46.876748 DUTY Scan : NO K
5994 09:27:46.879993 ZQ Calibration : PASS
5995 09:27:46.882947 Jitter Meter : NO K
5996 09:27:46.883028 CBT Training : PASS
5997 09:27:46.886286 Write leveling : PASS
5998 09:27:46.890051 RX DQS gating : PASS
5999 09:27:46.890131 RX DQ/DQS(RDDQC) : PASS
6000 09:27:46.892934 TX DQ/DQS : PASS
6001 09:27:46.896276 RX DATLAT : PASS
6002 09:27:46.896357 RX DQ/DQS(Engine): PASS
6003 09:27:46.899791 TX OE : NO K
6004 09:27:46.899871 All Pass.
6005 09:27:46.899935
6006 09:27:46.902945 CH 1, Rank 1
6007 09:27:46.903025 SW Impedance : PASS
6008 09:27:46.905995 DUTY Scan : NO K
6009 09:27:46.909524 ZQ Calibration : PASS
6010 09:27:46.909605 Jitter Meter : NO K
6011 09:27:46.913115 CBT Training : PASS
6012 09:27:46.916020 Write leveling : PASS
6013 09:27:46.916101 RX DQS gating : PASS
6014 09:27:46.919880 RX DQ/DQS(RDDQC) : PASS
6015 09:27:46.919961 TX DQ/DQS : PASS
6016 09:27:46.922961 RX DATLAT : PASS
6017 09:27:46.926648 RX DQ/DQS(Engine): PASS
6018 09:27:46.926727 TX OE : NO K
6019 09:27:46.929612 All Pass.
6020 09:27:46.929692
6021 09:27:46.929771 DramC Write-DBI off
6022 09:27:46.932681 PER_BANK_REFRESH: Hybrid Mode
6023 09:27:46.935852 TX_TRACKING: ON
6024 09:27:46.942836 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 09:27:46.945842 [FAST_K] Save calibration result to emmc
6026 09:27:46.952561 dramc_set_vcore_voltage set vcore to 650000
6027 09:27:46.952643 Read voltage for 400, 6
6028 09:27:46.952706 Vio18 = 0
6029 09:27:46.956013 Vcore = 650000
6030 09:27:46.956094 Vdram = 0
6031 09:27:46.956158 Vddq = 0
6032 09:27:46.959238 Vmddr = 0
6033 09:27:46.962369 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 09:27:46.969114 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 09:27:46.969208 MEM_TYPE=3, freq_sel=20
6036 09:27:46.972730 sv_algorithm_assistance_LP4_800
6037 09:27:46.979218 ============ PULL DRAM RESETB DOWN ============
6038 09:27:46.982646 ========== PULL DRAM RESETB DOWN end =========
6039 09:27:46.985813 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 09:27:46.988930 ===================================
6041 09:27:46.992383 LPDDR4 DRAM CONFIGURATION
6042 09:27:46.995772 ===================================
6043 09:27:46.998867 EX_ROW_EN[0] = 0x0
6044 09:27:46.998948 EX_ROW_EN[1] = 0x0
6045 09:27:47.002403 LP4Y_EN = 0x0
6046 09:27:47.002483 WORK_FSP = 0x0
6047 09:27:47.005631 WL = 0x2
6048 09:27:47.005711 RL = 0x2
6049 09:27:47.009055 BL = 0x2
6050 09:27:47.009135 RPST = 0x0
6051 09:27:47.012151 RD_PRE = 0x0
6052 09:27:47.012231 WR_PRE = 0x1
6053 09:27:47.015323 WR_PST = 0x0
6054 09:27:47.015442 DBI_WR = 0x0
6055 09:27:47.018627 DBI_RD = 0x0
6056 09:27:47.018707 OTF = 0x1
6057 09:27:47.021935 ===================================
6058 09:27:47.025585 ===================================
6059 09:27:47.028735 ANA top config
6060 09:27:47.031898 ===================================
6061 09:27:47.035536 DLL_ASYNC_EN = 0
6062 09:27:47.035616 ALL_SLAVE_EN = 1
6063 09:27:47.038549 NEW_RANK_MODE = 1
6064 09:27:47.042227 DLL_IDLE_MODE = 1
6065 09:27:47.045382 LP45_APHY_COMB_EN = 1
6066 09:27:47.045463 TX_ODT_DIS = 1
6067 09:27:47.048643 NEW_8X_MODE = 1
6068 09:27:47.051783 ===================================
6069 09:27:47.055279 ===================================
6070 09:27:47.058306 data_rate = 800
6071 09:27:47.061646 CKR = 1
6072 09:27:47.065212 DQ_P2S_RATIO = 4
6073 09:27:47.068328 ===================================
6074 09:27:47.071903 CA_P2S_RATIO = 4
6075 09:27:47.071984 DQ_CA_OPEN = 0
6076 09:27:47.074901 DQ_SEMI_OPEN = 1
6077 09:27:47.078208 CA_SEMI_OPEN = 1
6078 09:27:47.081867 CA_FULL_RATE = 0
6079 09:27:47.084814 DQ_CKDIV4_EN = 0
6080 09:27:47.088420 CA_CKDIV4_EN = 1
6081 09:27:47.091395 CA_PREDIV_EN = 0
6082 09:27:47.091476 PH8_DLY = 0
6083 09:27:47.095205 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 09:27:47.098249 DQ_AAMCK_DIV = 0
6085 09:27:47.101904 CA_AAMCK_DIV = 0
6086 09:27:47.105119 CA_ADMCK_DIV = 4
6087 09:27:47.105203 DQ_TRACK_CA_EN = 0
6088 09:27:47.108059 CA_PICK = 800
6089 09:27:47.111782 CA_MCKIO = 400
6090 09:27:47.114604 MCKIO_SEMI = 400
6091 09:27:47.118114 PLL_FREQ = 3016
6092 09:27:47.121208 DQ_UI_PI_RATIO = 32
6093 09:27:47.124575 CA_UI_PI_RATIO = 32
6094 09:27:47.127989 ===================================
6095 09:27:47.131863 ===================================
6096 09:27:47.131945 memory_type:LPDDR4
6097 09:27:47.135062 GP_NUM : 10
6098 09:27:47.138001 SRAM_EN : 1
6099 09:27:47.138106 MD32_EN : 0
6100 09:27:47.141796 ===================================
6101 09:27:47.144513 [ANA_INIT] >>>>>>>>>>>>>>
6102 09:27:47.148134 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 09:27:47.151248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 09:27:47.154794 ===================================
6105 09:27:47.158167 data_rate = 800,PCW = 0X7400
6106 09:27:47.161511 ===================================
6107 09:27:47.164528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 09:27:47.168067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 09:27:47.180991 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 09:27:47.184582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 09:27:47.187553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 09:27:47.191084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 09:27:47.194834 [ANA_INIT] flow start
6114 09:27:47.197914 [ANA_INIT] PLL >>>>>>>>
6115 09:27:47.198014 [ANA_INIT] PLL <<<<<<<<
6116 09:27:47.200959 [ANA_INIT] MIDPI >>>>>>>>
6117 09:27:47.204482 [ANA_INIT] MIDPI <<<<<<<<
6118 09:27:47.204555 [ANA_INIT] DLL >>>>>>>>
6119 09:27:47.207700 [ANA_INIT] flow end
6120 09:27:47.211249 ============ LP4 DIFF to SE enter ============
6121 09:27:47.214417 ============ LP4 DIFF to SE exit ============
6122 09:27:47.217401 [ANA_INIT] <<<<<<<<<<<<<
6123 09:27:47.221036 [Flow] Enable top DCM control >>>>>
6124 09:27:47.224045 [Flow] Enable top DCM control <<<<<
6125 09:27:47.227678 Enable DLL master slave shuffle
6126 09:27:47.233995 ==============================================================
6127 09:27:47.234103 Gating Mode config
6128 09:27:47.240768 ==============================================================
6129 09:27:47.243920 Config description:
6130 09:27:47.250469 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 09:27:47.257160 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 09:27:47.264322 SELPH_MODE 0: By rank 1: By Phase
6133 09:27:47.270232 ==============================================================
6134 09:27:47.270338 GAT_TRACK_EN = 0
6135 09:27:47.273938 RX_GATING_MODE = 2
6136 09:27:47.276917 RX_GATING_TRACK_MODE = 2
6137 09:27:47.280665 SELPH_MODE = 1
6138 09:27:47.283734 PICG_EARLY_EN = 1
6139 09:27:47.287358 VALID_LAT_VALUE = 1
6140 09:27:47.293644 ==============================================================
6141 09:27:47.297189 Enter into Gating configuration >>>>
6142 09:27:47.300462 Exit from Gating configuration <<<<
6143 09:27:47.303342 Enter into DVFS_PRE_config >>>>>
6144 09:27:47.313284 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 09:27:47.316836 Exit from DVFS_PRE_config <<<<<
6146 09:27:47.320023 Enter into PICG configuration >>>>
6147 09:27:47.323584 Exit from PICG configuration <<<<
6148 09:27:47.326844 [RX_INPUT] configuration >>>>>
6149 09:27:47.326941 [RX_INPUT] configuration <<<<<
6150 09:27:47.333534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 09:27:47.340295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 09:27:47.346842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 09:27:47.349923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 09:27:47.356532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 09:27:47.363461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 09:27:47.366690 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 09:27:47.370033 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 09:27:47.376797 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 09:27:47.379567 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 09:27:47.383262 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 09:27:47.389834 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 09:27:47.392941 ===================================
6163 09:27:47.393022 LPDDR4 DRAM CONFIGURATION
6164 09:27:47.396532 ===================================
6165 09:27:47.399563 EX_ROW_EN[0] = 0x0
6166 09:27:47.402865 EX_ROW_EN[1] = 0x0
6167 09:27:47.402949 LP4Y_EN = 0x0
6168 09:27:47.406286 WORK_FSP = 0x0
6169 09:27:47.406368 WL = 0x2
6170 09:27:47.409487 RL = 0x2
6171 09:27:47.409571 BL = 0x2
6172 09:27:47.412881 RPST = 0x0
6173 09:27:47.412966 RD_PRE = 0x0
6174 09:27:47.416520 WR_PRE = 0x1
6175 09:27:47.416603 WR_PST = 0x0
6176 09:27:47.419561 DBI_WR = 0x0
6177 09:27:47.419645 DBI_RD = 0x0
6178 09:27:47.423356 OTF = 0x1
6179 09:27:47.426636 ===================================
6180 09:27:47.429614 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 09:27:47.432724 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 09:27:47.439985 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 09:27:47.443061 ===================================
6184 09:27:47.443145 LPDDR4 DRAM CONFIGURATION
6185 09:27:47.446202 ===================================
6186 09:27:47.449593 EX_ROW_EN[0] = 0x10
6187 09:27:47.449677 EX_ROW_EN[1] = 0x0
6188 09:27:47.452852 LP4Y_EN = 0x0
6189 09:27:47.452936 WORK_FSP = 0x0
6190 09:27:47.456497 WL = 0x2
6191 09:27:47.459552 RL = 0x2
6192 09:27:47.459636 BL = 0x2
6193 09:27:47.463078 RPST = 0x0
6194 09:27:47.463162 RD_PRE = 0x0
6195 09:27:47.466124 WR_PRE = 0x1
6196 09:27:47.466207 WR_PST = 0x0
6197 09:27:47.469596 DBI_WR = 0x0
6198 09:27:47.469679 DBI_RD = 0x0
6199 09:27:47.473108 OTF = 0x1
6200 09:27:47.476029 ===================================
6201 09:27:47.482826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 09:27:47.485921 nWR fixed to 30
6203 09:27:47.486028 [ModeRegInit_LP4] CH0 RK0
6204 09:27:47.489474 [ModeRegInit_LP4] CH0 RK1
6205 09:27:47.492416 [ModeRegInit_LP4] CH1 RK0
6206 09:27:47.492500 [ModeRegInit_LP4] CH1 RK1
6207 09:27:47.495904 match AC timing 19
6208 09:27:47.498962 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 09:27:47.502568 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 09:27:47.509248 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 09:27:47.512575 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 09:27:47.519077 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 09:27:47.519161 ==
6214 09:27:47.522381 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 09:27:47.526114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 09:27:47.526224 ==
6217 09:27:47.532692 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 09:27:47.535818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 09:27:47.539299 [CA 0] Center 36 (8~64) winsize 57
6220 09:27:47.542465 [CA 1] Center 36 (8~64) winsize 57
6221 09:27:47.546082 [CA 2] Center 36 (8~64) winsize 57
6222 09:27:47.549145 [CA 3] Center 36 (8~64) winsize 57
6223 09:27:47.552747 [CA 4] Center 36 (8~64) winsize 57
6224 09:27:47.555668 [CA 5] Center 36 (8~64) winsize 57
6225 09:27:47.555741
6226 09:27:47.559411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 09:27:47.559511
6228 09:27:47.562508 [CATrainingPosCal] consider 1 rank data
6229 09:27:47.565477 u2DelayCellTimex100 = 270/100 ps
6230 09:27:47.569161 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 09:27:47.572166 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 09:27:47.578785 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 09:27:47.582572 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 09:27:47.585415 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 09:27:47.588871 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 09:27:47.588978
6237 09:27:47.592380 CA PerBit enable=1, Macro0, CA PI delay=36
6238 09:27:47.592462
6239 09:27:47.595191 [CBTSetCACLKResult] CA Dly = 36
6240 09:27:47.595272 CS Dly: 1 (0~32)
6241 09:27:47.595337 ==
6242 09:27:47.598724 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 09:27:47.605267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 09:27:47.605349 ==
6245 09:27:47.608404 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 09:27:47.615649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 09:27:47.618595 [CA 0] Center 36 (8~64) winsize 57
6248 09:27:47.621714 [CA 1] Center 36 (8~64) winsize 57
6249 09:27:47.625269 [CA 2] Center 36 (8~64) winsize 57
6250 09:27:47.628284 [CA 3] Center 36 (8~64) winsize 57
6251 09:27:47.631658 [CA 4] Center 36 (8~64) winsize 57
6252 09:27:47.635465 [CA 5] Center 36 (8~64) winsize 57
6253 09:27:47.635546
6254 09:27:47.638314 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 09:27:47.638395
6256 09:27:47.641735 [CATrainingPosCal] consider 2 rank data
6257 09:27:47.644691 u2DelayCellTimex100 = 270/100 ps
6258 09:27:47.648408 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 09:27:47.651285 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 09:27:47.655241 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:27:47.658248 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:27:47.664891 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:27:47.667921 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 09:27:47.668027
6265 09:27:47.671389 CA PerBit enable=1, Macro0, CA PI delay=36
6266 09:27:47.671462
6267 09:27:47.674485 [CBTSetCACLKResult] CA Dly = 36
6268 09:27:47.674580 CS Dly: 1 (0~32)
6269 09:27:47.674669
6270 09:27:47.678265 ----->DramcWriteLeveling(PI) begin...
6271 09:27:47.678345 ==
6272 09:27:47.681148 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 09:27:47.687643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 09:27:47.687746 ==
6275 09:27:47.691150 Write leveling (Byte 0): 40 => 8
6276 09:27:47.694656 Write leveling (Byte 1): 40 => 8
6277 09:27:47.694765 DramcWriteLeveling(PI) end<-----
6278 09:27:47.694847
6279 09:27:47.697976 ==
6280 09:27:47.698086 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 09:27:47.704634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 09:27:47.704724 ==
6283 09:27:47.708121 [Gating] SW mode calibration
6284 09:27:47.714388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 09:27:47.717947 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 09:27:47.724731 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 09:27:47.727861 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 09:27:47.730785 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 09:27:47.737582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 09:27:47.740813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 09:27:47.744741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 09:27:47.751043 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 09:27:47.754007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 09:27:47.757321 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 09:27:47.760401 Total UI for P1: 0, mck2ui 16
6296 09:27:47.763798 best dqsien dly found for B0: ( 0, 14, 24)
6297 09:27:47.767283 Total UI for P1: 0, mck2ui 16
6298 09:27:47.770508 best dqsien dly found for B1: ( 0, 14, 24)
6299 09:27:47.773497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 09:27:47.776947 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 09:27:47.780577
6302 09:27:47.783451 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 09:27:47.786721 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 09:27:47.790364 [Gating] SW calibration Done
6305 09:27:47.790444 ==
6306 09:27:47.793901 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 09:27:47.797285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 09:27:47.797366 ==
6309 09:27:47.797429 RX Vref Scan: 0
6310 09:27:47.800109
6311 09:27:47.800189 RX Vref 0 -> 0, step: 1
6312 09:27:47.800252
6313 09:27:47.803544 RX Delay -410 -> 252, step: 16
6314 09:27:47.806874 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6315 09:27:47.813517 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6316 09:27:47.816947 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6317 09:27:47.820235 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6318 09:27:47.823404 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6319 09:27:47.830124 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6320 09:27:47.833288 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6321 09:27:47.836981 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6322 09:27:47.839934 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6323 09:27:47.846696 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6324 09:27:47.849751 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6325 09:27:47.853368 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6326 09:27:47.856794 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6327 09:27:47.863378 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6328 09:27:47.866637 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6329 09:27:47.869953 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6330 09:27:47.870061 ==
6331 09:27:47.873029 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 09:27:47.879848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 09:27:47.879930 ==
6334 09:27:47.880002 DQS Delay:
6335 09:27:47.883010 DQS0 = 59, DQS1 = 59
6336 09:27:47.883091 DQM Delay:
6337 09:27:47.883155 DQM0 = 17, DQM1 = 10
6338 09:27:47.886373 DQ Delay:
6339 09:27:47.889580 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6340 09:27:47.893201 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6341 09:27:47.893281 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6342 09:27:47.899194 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6343 09:27:47.899275
6344 09:27:47.899337
6345 09:27:47.899430 ==
6346 09:27:47.902734 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 09:27:47.906150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 09:27:47.906231 ==
6349 09:27:47.906294
6350 09:27:47.906353
6351 09:27:47.909174 TX Vref Scan disable
6352 09:27:47.909265 == TX Byte 0 ==
6353 09:27:47.916080 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 09:27:47.919303 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 09:27:47.919392 == TX Byte 1 ==
6356 09:27:47.922891 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 09:27:47.929430 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 09:27:47.929511 ==
6359 09:27:47.932344 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 09:27:47.935868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 09:27:47.935949 ==
6362 09:27:47.936013
6363 09:27:47.936073
6364 09:27:47.939109 TX Vref Scan disable
6365 09:27:47.939190 == TX Byte 0 ==
6366 09:27:47.945908 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 09:27:47.949443 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 09:27:47.949524 == TX Byte 1 ==
6369 09:27:47.955908 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 09:27:47.958969 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 09:27:47.959049
6372 09:27:47.959113 [DATLAT]
6373 09:27:47.962652 Freq=400, CH0 RK0
6374 09:27:47.962733
6375 09:27:47.962795 DATLAT Default: 0xf
6376 09:27:47.966024 0, 0xFFFF, sum = 0
6377 09:27:47.966130 1, 0xFFFF, sum = 0
6378 09:27:47.969118 2, 0xFFFF, sum = 0
6379 09:27:47.969201 3, 0xFFFF, sum = 0
6380 09:27:47.972192 4, 0xFFFF, sum = 0
6381 09:27:47.972274 5, 0xFFFF, sum = 0
6382 09:27:47.975581 6, 0xFFFF, sum = 0
6383 09:27:47.975664 7, 0xFFFF, sum = 0
6384 09:27:47.979156 8, 0xFFFF, sum = 0
6385 09:27:47.979237 9, 0xFFFF, sum = 0
6386 09:27:47.982126 10, 0xFFFF, sum = 0
6387 09:27:47.982208 11, 0xFFFF, sum = 0
6388 09:27:47.985937 12, 0xFFFF, sum = 0
6389 09:27:47.986019 13, 0x0, sum = 1
6390 09:27:47.988898 14, 0x0, sum = 2
6391 09:27:47.988980 15, 0x0, sum = 3
6392 09:27:47.992413 16, 0x0, sum = 4
6393 09:27:47.992495 best_step = 14
6394 09:27:47.992559
6395 09:27:47.992618 ==
6396 09:27:47.995798 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 09:27:48.002118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 09:27:48.002211 ==
6399 09:27:48.002275 RX Vref Scan: 1
6400 09:27:48.002335
6401 09:27:48.005753 RX Vref 0 -> 0, step: 1
6402 09:27:48.005834
6403 09:27:48.008723 RX Delay -359 -> 252, step: 8
6404 09:27:48.008803
6405 09:27:48.012095 Set Vref, RX VrefLevel [Byte0]: 64
6406 09:27:48.015575 [Byte1]: 57
6407 09:27:48.019083
6408 09:27:48.019167 Final RX Vref Byte 0 = 64 to rank0
6409 09:27:48.021970 Final RX Vref Byte 1 = 57 to rank0
6410 09:27:48.025754 Final RX Vref Byte 0 = 64 to rank1
6411 09:27:48.028865 Final RX Vref Byte 1 = 57 to rank1==
6412 09:27:48.031900 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 09:27:48.038874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 09:27:48.038959 ==
6415 09:27:48.039076 DQS Delay:
6416 09:27:48.041869 DQS0 = 60, DQS1 = 68
6417 09:27:48.041952 DQM Delay:
6418 09:27:48.042037 DQM0 = 14, DQM1 = 14
6419 09:27:48.045161 DQ Delay:
6420 09:27:48.048576 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6421 09:27:48.051640 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6422 09:27:48.051723 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6423 09:27:48.058378 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6424 09:27:48.058462
6425 09:27:48.058547
6426 09:27:48.064948 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b8a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6427 09:27:48.068604 CH0 RK0: MR19=C0C, MR18=8B8A
6428 09:27:48.075071 CH0_RK0: MR19=0xC0C, MR18=0x8B8A, DQSOSC=392, MR23=63, INC=384, DEC=256
6429 09:27:48.075180 ==
6430 09:27:48.078781 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 09:27:48.081603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 09:27:48.081687 ==
6433 09:27:48.085107 [Gating] SW mode calibration
6434 09:27:48.091964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 09:27:48.098372 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 09:27:48.101489 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 09:27:48.104957 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 09:27:48.111422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 09:27:48.114701 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 09:27:48.117855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 09:27:48.124513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 09:27:48.128034 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 09:27:48.131097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 09:27:48.138126 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 09:27:48.138212 Total UI for P1: 0, mck2ui 16
6446 09:27:48.145114 best dqsien dly found for B0: ( 0, 14, 24)
6447 09:27:48.145222 Total UI for P1: 0, mck2ui 16
6448 09:27:48.148036 best dqsien dly found for B1: ( 0, 14, 24)
6449 09:27:48.154646 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 09:27:48.157936 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 09:27:48.158021
6452 09:27:48.161391 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 09:27:48.164516 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 09:27:48.168030 [Gating] SW calibration Done
6455 09:27:48.168114 ==
6456 09:27:48.171179 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 09:27:48.174605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 09:27:48.174718 ==
6459 09:27:48.177740 RX Vref Scan: 0
6460 09:27:48.177839
6461 09:27:48.177929 RX Vref 0 -> 0, step: 1
6462 09:27:48.178015
6463 09:27:48.181534 RX Delay -410 -> 252, step: 16
6464 09:27:48.188059 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6465 09:27:48.191107 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 09:27:48.194632 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 09:27:48.197797 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 09:27:48.204424 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 09:27:48.208045 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6470 09:27:48.211142 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6471 09:27:48.214279 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6472 09:27:48.220893 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 09:27:48.224236 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 09:27:48.227749 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 09:27:48.231091 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6476 09:27:48.237627 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6477 09:27:48.241102 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6478 09:27:48.244106 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 09:27:48.247623 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6480 09:27:48.251022 ==
6481 09:27:48.251093 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 09:27:48.257331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 09:27:48.257413 ==
6484 09:27:48.257476 DQS Delay:
6485 09:27:48.260807 DQS0 = 59, DQS1 = 59
6486 09:27:48.260876 DQM Delay:
6487 09:27:48.263979 DQM0 = 16, DQM1 = 10
6488 09:27:48.264059 DQ Delay:
6489 09:27:48.267441 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6490 09:27:48.270973 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6491 09:27:48.274026 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6492 09:27:48.277014 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6493 09:27:48.277095
6494 09:27:48.277158
6495 09:27:48.277215 ==
6496 09:27:48.280680 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 09:27:48.283830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 09:27:48.283910 ==
6499 09:27:48.283972
6500 09:27:48.284031
6501 09:27:48.287108 TX Vref Scan disable
6502 09:27:48.287187 == TX Byte 0 ==
6503 09:27:48.293600 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6504 09:27:48.296878 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6505 09:27:48.296958 == TX Byte 1 ==
6506 09:27:48.303945 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 09:27:48.306884 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 09:27:48.306960 ==
6509 09:27:48.310522 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 09:27:48.313614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 09:27:48.313696 ==
6512 09:27:48.313760
6513 09:27:48.313819
6514 09:27:48.317252 TX Vref Scan disable
6515 09:27:48.317334 == TX Byte 0 ==
6516 09:27:48.324117 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6517 09:27:48.327064 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6518 09:27:48.327145 == TX Byte 1 ==
6519 09:27:48.333997 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6520 09:27:48.337101 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6521 09:27:48.337182
6522 09:27:48.337245 [DATLAT]
6523 09:27:48.340154 Freq=400, CH0 RK1
6524 09:27:48.340235
6525 09:27:48.340300 DATLAT Default: 0xe
6526 09:27:48.343568 0, 0xFFFF, sum = 0
6527 09:27:48.343651 1, 0xFFFF, sum = 0
6528 09:27:48.347243 2, 0xFFFF, sum = 0
6529 09:27:48.347351 3, 0xFFFF, sum = 0
6530 09:27:48.350115 4, 0xFFFF, sum = 0
6531 09:27:48.350197 5, 0xFFFF, sum = 0
6532 09:27:48.353553 6, 0xFFFF, sum = 0
6533 09:27:48.353662 7, 0xFFFF, sum = 0
6534 09:27:48.356747 8, 0xFFFF, sum = 0
6535 09:27:48.356830 9, 0xFFFF, sum = 0
6536 09:27:48.359965 10, 0xFFFF, sum = 0
6537 09:27:48.363596 11, 0xFFFF, sum = 0
6538 09:27:48.363679 12, 0xFFFF, sum = 0
6539 09:27:48.366714 13, 0x0, sum = 1
6540 09:27:48.366796 14, 0x0, sum = 2
6541 09:27:48.370116 15, 0x0, sum = 3
6542 09:27:48.370198 16, 0x0, sum = 4
6543 09:27:48.370264 best_step = 14
6544 09:27:48.370323
6545 09:27:48.373451 ==
6546 09:27:48.376720 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 09:27:48.380052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 09:27:48.380134 ==
6549 09:27:48.380198 RX Vref Scan: 0
6550 09:27:48.380258
6551 09:27:48.383063 RX Vref 0 -> 0, step: 1
6552 09:27:48.383169
6553 09:27:48.386393 RX Delay -359 -> 252, step: 8
6554 09:27:48.393892 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6555 09:27:48.396821 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6556 09:27:48.400418 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6557 09:27:48.403580 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6558 09:27:48.410120 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6559 09:27:48.413873 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6560 09:27:48.416824 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6561 09:27:48.419983 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6562 09:27:48.427195 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6563 09:27:48.430318 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6564 09:27:48.433313 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6565 09:27:48.437012 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6566 09:27:48.443770 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6567 09:27:48.446776 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6568 09:27:48.450165 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6569 09:27:48.456962 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6570 09:27:48.457047 ==
6571 09:27:48.460052 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 09:27:48.463470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 09:27:48.463555 ==
6574 09:27:48.463641 DQS Delay:
6575 09:27:48.467150 DQS0 = 60, DQS1 = 68
6576 09:27:48.467234 DQM Delay:
6577 09:27:48.470088 DQM0 = 12, DQM1 = 14
6578 09:27:48.470173 DQ Delay:
6579 09:27:48.473627 DQ0 =12, DQ1 =16, DQ2 =4, DQ3 =8
6580 09:27:48.476789 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6581 09:27:48.480303 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6582 09:27:48.483550 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6583 09:27:48.483634
6584 09:27:48.483719
6585 09:27:48.489897 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6586 09:27:48.493139 CH0 RK1: MR19=C0C, MR18=C67B
6587 09:27:48.500112 CH0_RK1: MR19=0xC0C, MR18=0xC67B, DQSOSC=385, MR23=63, INC=398, DEC=265
6588 09:27:48.503330 [RxdqsGatingPostProcess] freq 400
6589 09:27:48.509974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 09:27:48.510064 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 09:27:48.513246 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 09:27:48.516647 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 09:27:48.519611 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 09:27:48.523131 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 09:27:48.526240 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 09:27:48.529936 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 09:27:48.532870 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 09:27:48.536593 Pre-setting of DQS Precalculation
6599 09:27:48.543376 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 09:27:48.543499 ==
6601 09:27:48.546361 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 09:27:48.549949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 09:27:48.550034 ==
6604 09:27:48.556626 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 09:27:48.559723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6606 09:27:48.563245 [CA 0] Center 36 (8~64) winsize 57
6607 09:27:48.566106 [CA 1] Center 36 (8~64) winsize 57
6608 09:27:48.569690 [CA 2] Center 36 (8~64) winsize 57
6609 09:27:48.572882 [CA 3] Center 36 (8~64) winsize 57
6610 09:27:48.576085 [CA 4] Center 36 (8~64) winsize 57
6611 09:27:48.579335 [CA 5] Center 36 (8~64) winsize 57
6612 09:27:48.579457
6613 09:27:48.583165 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6614 09:27:48.583252
6615 09:27:48.586098 [CATrainingPosCal] consider 1 rank data
6616 09:27:48.589322 u2DelayCellTimex100 = 270/100 ps
6617 09:27:48.592906 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 09:27:48.595799 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 09:27:48.599223 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 09:27:48.605974 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 09:27:48.609437 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 09:27:48.612725 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 09:27:48.612826
6624 09:27:48.615870 CA PerBit enable=1, Macro0, CA PI delay=36
6625 09:27:48.615949
6626 09:27:48.619062 [CBTSetCACLKResult] CA Dly = 36
6627 09:27:48.619162 CS Dly: 1 (0~32)
6628 09:27:48.619252 ==
6629 09:27:48.622231 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 09:27:48.628852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 09:27:48.628997 ==
6632 09:27:48.632044 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 09:27:48.638553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6634 09:27:48.641898 [CA 0] Center 36 (8~64) winsize 57
6635 09:27:48.645079 [CA 1] Center 36 (8~64) winsize 57
6636 09:27:48.648582 [CA 2] Center 36 (8~64) winsize 57
6637 09:27:48.651869 [CA 3] Center 36 (8~64) winsize 57
6638 09:27:48.655423 [CA 4] Center 36 (8~64) winsize 57
6639 09:27:48.658891 [CA 5] Center 36 (8~64) winsize 57
6640 09:27:48.658975
6641 09:27:48.661958 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6642 09:27:48.662041
6643 09:27:48.665027 [CATrainingPosCal] consider 2 rank data
6644 09:27:48.668545 u2DelayCellTimex100 = 270/100 ps
6645 09:27:48.671574 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 09:27:48.675374 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 09:27:48.678540 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:27:48.681500 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:27:48.688651 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:27:48.691520 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 09:27:48.691605
6652 09:27:48.695302 CA PerBit enable=1, Macro0, CA PI delay=36
6653 09:27:48.695446
6654 09:27:48.698461 [CBTSetCACLKResult] CA Dly = 36
6655 09:27:48.698545 CS Dly: 1 (0~32)
6656 09:27:48.698630
6657 09:27:48.701345 ----->DramcWriteLeveling(PI) begin...
6658 09:27:48.701431 ==
6659 09:27:48.704921 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 09:27:48.711572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 09:27:48.711658 ==
6662 09:27:48.714621 Write leveling (Byte 0): 40 => 8
6663 09:27:48.714706 Write leveling (Byte 1): 40 => 8
6664 09:27:48.718022 DramcWriteLeveling(PI) end<-----
6665 09:27:48.718106
6666 09:27:48.721335 ==
6667 09:27:48.721419 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 09:27:48.727851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 09:27:48.727936 ==
6670 09:27:48.731395 [Gating] SW mode calibration
6671 09:27:48.737972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 09:27:48.740968 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 09:27:48.747713 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 09:27:48.751105 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 09:27:48.754422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 09:27:48.761102 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 09:27:48.764551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 09:27:48.767555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 09:27:48.774113 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 09:27:48.777630 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 09:27:48.780664 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 09:27:48.784347 Total UI for P1: 0, mck2ui 16
6683 09:27:48.787480 best dqsien dly found for B0: ( 0, 14, 24)
6684 09:27:48.790868 Total UI for P1: 0, mck2ui 16
6685 09:27:48.794036 best dqsien dly found for B1: ( 0, 14, 24)
6686 09:27:48.797628 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 09:27:48.800733 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 09:27:48.803901
6689 09:27:48.807430 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 09:27:48.810330 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 09:27:48.813975 [Gating] SW calibration Done
6692 09:27:48.814059 ==
6693 09:27:48.817084 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 09:27:48.820611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 09:27:48.820696 ==
6696 09:27:48.820782 RX Vref Scan: 0
6697 09:27:48.820863
6698 09:27:48.823672 RX Vref 0 -> 0, step: 1
6699 09:27:48.823756
6700 09:27:48.826822 RX Delay -410 -> 252, step: 16
6701 09:27:48.830139 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6702 09:27:48.837118 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6703 09:27:48.840071 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6704 09:27:48.843297 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6705 09:27:48.846883 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6706 09:27:48.853197 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6707 09:27:48.856621 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6708 09:27:48.860230 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6709 09:27:48.863581 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6710 09:27:48.869876 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6711 09:27:48.873515 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6712 09:27:48.876629 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6713 09:27:48.879946 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6714 09:27:48.886561 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6715 09:27:48.889708 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6716 09:27:48.893323 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6717 09:27:48.893408 ==
6718 09:27:48.896284 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 09:27:48.902804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 09:27:48.902917 ==
6721 09:27:48.903003 DQS Delay:
6722 09:27:48.906696 DQS0 = 51, DQS1 = 67
6723 09:27:48.906780 DQM Delay:
6724 09:27:48.906865 DQM0 = 13, DQM1 = 19
6725 09:27:48.909611 DQ Delay:
6726 09:27:48.912762 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6727 09:27:48.916450 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6728 09:27:48.916534 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6729 09:27:48.919358 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6730 09:27:48.923043
6731 09:27:48.923126
6732 09:27:48.923211 ==
6733 09:27:48.926788 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 09:27:48.929821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 09:27:48.929905 ==
6736 09:27:48.929991
6737 09:27:48.930071
6738 09:27:48.932762 TX Vref Scan disable
6739 09:27:48.932846 == TX Byte 0 ==
6740 09:27:48.936116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 09:27:48.942794 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 09:27:48.942903 == TX Byte 1 ==
6743 09:27:48.946255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 09:27:48.953041 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 09:27:48.953119 ==
6746 09:27:48.956144 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 09:27:48.959113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 09:27:48.959213 ==
6749 09:27:48.959306
6750 09:27:48.959415
6751 09:27:48.962766 TX Vref Scan disable
6752 09:27:48.962860 == TX Byte 0 ==
6753 09:27:48.969494 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 09:27:48.972519 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 09:27:48.972618 == TX Byte 1 ==
6756 09:27:48.979269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 09:27:48.982056 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 09:27:48.982163
6759 09:27:48.982255 [DATLAT]
6760 09:27:48.986250 Freq=400, CH1 RK0
6761 09:27:48.986326
6762 09:27:48.986387 DATLAT Default: 0xf
6763 09:27:48.988912 0, 0xFFFF, sum = 0
6764 09:27:48.988981 1, 0xFFFF, sum = 0
6765 09:27:48.992023 2, 0xFFFF, sum = 0
6766 09:27:48.992098 3, 0xFFFF, sum = 0
6767 09:27:48.995513 4, 0xFFFF, sum = 0
6768 09:27:48.995592 5, 0xFFFF, sum = 0
6769 09:27:48.998977 6, 0xFFFF, sum = 0
6770 09:27:48.999045 7, 0xFFFF, sum = 0
6771 09:27:49.002107 8, 0xFFFF, sum = 0
6772 09:27:49.002175 9, 0xFFFF, sum = 0
6773 09:27:49.005629 10, 0xFFFF, sum = 0
6774 09:27:49.008587 11, 0xFFFF, sum = 0
6775 09:27:49.008663 12, 0xFFFF, sum = 0
6776 09:27:49.011829 13, 0x0, sum = 1
6777 09:27:49.011912 14, 0x0, sum = 2
6778 09:27:49.015414 15, 0x0, sum = 3
6779 09:27:49.015502 16, 0x0, sum = 4
6780 09:27:49.015565 best_step = 14
6781 09:27:49.015659
6782 09:27:49.018998 ==
6783 09:27:49.021921 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 09:27:49.025557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 09:27:49.025662 ==
6786 09:27:49.025758 RX Vref Scan: 1
6787 09:27:49.025847
6788 09:27:49.028743 RX Vref 0 -> 0, step: 1
6789 09:27:49.028839
6790 09:27:49.031528 RX Delay -375 -> 252, step: 8
6791 09:27:49.031597
6792 09:27:49.035160 Set Vref, RX VrefLevel [Byte0]: 56
6793 09:27:49.038101 [Byte1]: 56
6794 09:27:49.042446
6795 09:27:49.042522 Final RX Vref Byte 0 = 56 to rank0
6796 09:27:49.045231 Final RX Vref Byte 1 = 56 to rank0
6797 09:27:49.049069 Final RX Vref Byte 0 = 56 to rank1
6798 09:27:49.052261 Final RX Vref Byte 1 = 56 to rank1==
6799 09:27:49.055528 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 09:27:49.062249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 09:27:49.062351 ==
6802 09:27:49.062442 DQS Delay:
6803 09:27:49.065339 DQS0 = 56, DQS1 = 68
6804 09:27:49.065434 DQM Delay:
6805 09:27:49.065524 DQM0 = 12, DQM1 = 13
6806 09:27:49.068839 DQ Delay:
6807 09:27:49.071955 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6808 09:27:49.072052 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6809 09:27:49.075655 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6810 09:27:49.078731 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6811 09:27:49.078828
6812 09:27:49.078915
6813 09:27:49.088555 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6814 09:27:49.092260 CH1 RK0: MR19=C0C, MR18=5A6E
6815 09:27:49.098474 CH1_RK0: MR19=0xC0C, MR18=0x5A6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6816 09:27:49.098550 ==
6817 09:27:49.102407 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 09:27:49.105456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 09:27:49.105538 ==
6820 09:27:49.108756 [Gating] SW mode calibration
6821 09:27:49.115523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 09:27:49.122088 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 09:27:49.125729 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 09:27:49.128539 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 09:27:49.135269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 09:27:49.138971 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 09:27:49.141878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 09:27:49.145037 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 09:27:49.151541 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 09:27:49.155076 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 09:27:49.158524 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 09:27:49.161718 Total UI for P1: 0, mck2ui 16
6833 09:27:49.165070 best dqsien dly found for B0: ( 0, 14, 24)
6834 09:27:49.168329 Total UI for P1: 0, mck2ui 16
6835 09:27:49.171679 best dqsien dly found for B1: ( 0, 14, 24)
6836 09:27:49.175176 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 09:27:49.178253 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 09:27:49.181969
6839 09:27:49.185183 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 09:27:49.188532 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 09:27:49.191549 [Gating] SW calibration Done
6842 09:27:49.191654 ==
6843 09:27:49.195000 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 09:27:49.198105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 09:27:49.198207 ==
6846 09:27:49.198298 RX Vref Scan: 0
6847 09:27:49.201799
6848 09:27:49.201878 RX Vref 0 -> 0, step: 1
6849 09:27:49.201970
6850 09:27:49.204820 RX Delay -410 -> 252, step: 16
6851 09:27:49.208395 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6852 09:27:49.214870 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6853 09:27:49.218223 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6854 09:27:49.221445 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6855 09:27:49.224743 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6856 09:27:49.231822 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6857 09:27:49.234467 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6858 09:27:49.237878 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6859 09:27:49.241495 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6860 09:27:49.248351 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6861 09:27:49.251335 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6862 09:27:49.254350 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6863 09:27:49.258122 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6864 09:27:49.264785 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6865 09:27:49.268166 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6866 09:27:49.271318 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6867 09:27:49.271418 ==
6868 09:27:49.274781 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 09:27:49.281204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 09:27:49.281311 ==
6871 09:27:49.281403 DQS Delay:
6872 09:27:49.284170 DQS0 = 59, DQS1 = 67
6873 09:27:49.284249 DQM Delay:
6874 09:27:49.284316 DQM0 = 19, DQM1 = 22
6875 09:27:49.287629 DQ Delay:
6876 09:27:49.291179 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6877 09:27:49.294796 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6878 09:27:49.297541 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6879 09:27:49.300780 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6880 09:27:49.300881
6881 09:27:49.300970
6882 09:27:49.301058 ==
6883 09:27:49.304450 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 09:27:49.307356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 09:27:49.307460 ==
6886 09:27:49.307529
6887 09:27:49.307605
6888 09:27:49.311184 TX Vref Scan disable
6889 09:27:49.311264 == TX Byte 0 ==
6890 09:27:49.317799 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6891 09:27:49.320651 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6892 09:27:49.320734 == TX Byte 1 ==
6893 09:27:49.324030 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 09:27:49.331182 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 09:27:49.331260 ==
6896 09:27:49.333921 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 09:27:49.337384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 09:27:49.337484 ==
6899 09:27:49.337578
6900 09:27:49.337668
6901 09:27:49.340584 TX Vref Scan disable
6902 09:27:49.340685 == TX Byte 0 ==
6903 09:27:49.347164 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6904 09:27:49.350954 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6905 09:27:49.351059 == TX Byte 1 ==
6906 09:27:49.357645 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6907 09:27:49.360807 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6908 09:27:49.360905
6909 09:27:49.360970 [DATLAT]
6910 09:27:49.363690 Freq=400, CH1 RK1
6911 09:27:49.363787
6912 09:27:49.363862 DATLAT Default: 0xe
6913 09:27:49.367208 0, 0xFFFF, sum = 0
6914 09:27:49.367298 1, 0xFFFF, sum = 0
6915 09:27:49.370487 2, 0xFFFF, sum = 0
6916 09:27:49.370571 3, 0xFFFF, sum = 0
6917 09:27:49.374153 4, 0xFFFF, sum = 0
6918 09:27:49.374269 5, 0xFFFF, sum = 0
6919 09:27:49.376915 6, 0xFFFF, sum = 0
6920 09:27:49.377024 7, 0xFFFF, sum = 0
6921 09:27:49.380088 8, 0xFFFF, sum = 0
6922 09:27:49.380221 9, 0xFFFF, sum = 0
6923 09:27:49.383836 10, 0xFFFF, sum = 0
6924 09:27:49.386820 11, 0xFFFF, sum = 0
6925 09:27:49.386932 12, 0xFFFF, sum = 0
6926 09:27:49.390096 13, 0x0, sum = 1
6927 09:27:49.390210 14, 0x0, sum = 2
6928 09:27:49.390312 15, 0x0, sum = 3
6929 09:27:49.393453 16, 0x0, sum = 4
6930 09:27:49.393535 best_step = 14
6931 09:27:49.393613
6932 09:27:49.393677 ==
6933 09:27:49.396845 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 09:27:49.403662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 09:27:49.403821 ==
6936 09:27:49.403944 RX Vref Scan: 0
6937 09:27:49.404026
6938 09:27:49.406838 RX Vref 0 -> 0, step: 1
6939 09:27:49.406915
6940 09:27:49.410324 RX Delay -375 -> 252, step: 8
6941 09:27:49.417107 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6942 09:27:49.420299 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6943 09:27:49.424119 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6944 09:27:49.427167 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6945 09:27:49.433578 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6946 09:27:49.436785 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6947 09:27:49.440366 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6948 09:27:49.443471 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6949 09:27:49.450158 iDelay=217, Bit 8, Center -68 (-327 ~ 192) 520
6950 09:27:49.453506 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6951 09:27:49.457042 iDelay=217, Bit 10, Center -52 (-311 ~ 208) 520
6952 09:27:49.460330 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
6953 09:27:49.466945 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6954 09:27:49.469991 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6955 09:27:49.473720 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6956 09:27:49.480136 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6957 09:27:49.480280 ==
6958 09:27:49.483190 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 09:27:49.487113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 09:27:49.487240 ==
6961 09:27:49.487342 DQS Delay:
6962 09:27:49.489932 DQS0 = 60, DQS1 = 68
6963 09:27:49.490046 DQM Delay:
6964 09:27:49.493714 DQM0 = 12, DQM1 = 13
6965 09:27:49.493818 DQ Delay:
6966 09:27:49.496568 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6967 09:27:49.499826 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6968 09:27:49.503178 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6969 09:27:49.506822 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6970 09:27:49.506908
6971 09:27:49.506972
6972 09:27:49.513329 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6973 09:27:49.516477 CH1 RK1: MR19=C0C, MR18=7CAC
6974 09:27:49.522768 CH1_RK1: MR19=0xC0C, MR18=0x7CAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6975 09:27:49.526327 [RxdqsGatingPostProcess] freq 400
6976 09:27:49.533046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 09:27:49.536126 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 09:27:49.536207 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 09:27:49.539615 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 09:27:49.543007 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 09:27:49.546478 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 09:27:49.549426 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 09:27:49.552954 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 09:27:49.556459 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 09:27:49.559336 Pre-setting of DQS Precalculation
6986 09:27:49.566516 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 09:27:49.572801 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 09:27:49.579555 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 09:27:49.579637
6990 09:27:49.579701
6991 09:27:49.583120 [Calibration Summary] 800 Mbps
6992 09:27:49.583192 CH 0, Rank 0
6993 09:27:49.586133 SW Impedance : PASS
6994 09:27:49.589307 DUTY Scan : NO K
6995 09:27:49.589392 ZQ Calibration : PASS
6996 09:27:49.592909 Jitter Meter : NO K
6997 09:27:49.592990 CBT Training : PASS
6998 09:27:49.596466 Write leveling : PASS
6999 09:27:49.599576 RX DQS gating : PASS
7000 09:27:49.599656 RX DQ/DQS(RDDQC) : PASS
7001 09:27:49.603054 TX DQ/DQS : PASS
7002 09:27:49.606095 RX DATLAT : PASS
7003 09:27:49.606176 RX DQ/DQS(Engine): PASS
7004 09:27:49.609725 TX OE : NO K
7005 09:27:49.609806 All Pass.
7006 09:27:49.609885
7007 09:27:49.613011 CH 0, Rank 1
7008 09:27:49.613142 SW Impedance : PASS
7009 09:27:49.615935 DUTY Scan : NO K
7010 09:27:49.619149 ZQ Calibration : PASS
7011 09:27:49.619282 Jitter Meter : NO K
7012 09:27:49.622988 CBT Training : PASS
7013 09:27:49.626151 Write leveling : NO K
7014 09:27:49.626259 RX DQS gating : PASS
7015 09:27:49.629702 RX DQ/DQS(RDDQC) : PASS
7016 09:27:49.632824 TX DQ/DQS : PASS
7017 09:27:49.632910 RX DATLAT : PASS
7018 09:27:49.635797 RX DQ/DQS(Engine): PASS
7019 09:27:49.639450 TX OE : NO K
7020 09:27:49.639536 All Pass.
7021 09:27:49.639622
7022 09:27:49.639704 CH 1, Rank 0
7023 09:27:49.642535 SW Impedance : PASS
7024 09:27:49.645949 DUTY Scan : NO K
7025 09:27:49.646071 ZQ Calibration : PASS
7026 09:27:49.648970 Jitter Meter : NO K
7027 09:27:49.649056 CBT Training : PASS
7028 09:27:49.652898 Write leveling : PASS
7029 09:27:49.655788 RX DQS gating : PASS
7030 09:27:49.655873 RX DQ/DQS(RDDQC) : PASS
7031 09:27:49.659353 TX DQ/DQS : PASS
7032 09:27:49.662301 RX DATLAT : PASS
7033 09:27:49.662386 RX DQ/DQS(Engine): PASS
7034 09:27:49.665662 TX OE : NO K
7035 09:27:49.665748 All Pass.
7036 09:27:49.665834
7037 09:27:49.668853 CH 1, Rank 1
7038 09:27:49.668937 SW Impedance : PASS
7039 09:27:49.672613 DUTY Scan : NO K
7040 09:27:49.675659 ZQ Calibration : PASS
7041 09:27:49.675759 Jitter Meter : NO K
7042 09:27:49.679258 CBT Training : PASS
7043 09:27:49.682145 Write leveling : NO K
7044 09:27:49.682230 RX DQS gating : PASS
7045 09:27:49.685871 RX DQ/DQS(RDDQC) : PASS
7046 09:27:49.688981 TX DQ/DQS : PASS
7047 09:27:49.689069 RX DATLAT : PASS
7048 09:27:49.691990 RX DQ/DQS(Engine): PASS
7049 09:27:49.695285 TX OE : NO K
7050 09:27:49.695374 All Pass.
7051 09:27:49.695483
7052 09:27:49.695565 DramC Write-DBI off
7053 09:27:49.698956 PER_BANK_REFRESH: Hybrid Mode
7054 09:27:49.702115 TX_TRACKING: ON
7055 09:27:49.708730 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 09:27:49.711802 [FAST_K] Save calibration result to emmc
7057 09:27:49.718857 dramc_set_vcore_voltage set vcore to 725000
7058 09:27:49.718952 Read voltage for 1600, 0
7059 09:27:49.721775 Vio18 = 0
7060 09:27:49.721875 Vcore = 725000
7061 09:27:49.721961 Vdram = 0
7062 09:27:49.725409 Vddq = 0
7063 09:27:49.725513 Vmddr = 0
7064 09:27:49.728871 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 09:27:49.735119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 09:27:49.738328 MEM_TYPE=3, freq_sel=13
7067 09:27:49.741831 sv_algorithm_assistance_LP4_3733
7068 09:27:49.744926 ============ PULL DRAM RESETB DOWN ============
7069 09:27:49.748593 ========== PULL DRAM RESETB DOWN end =========
7070 09:27:49.754691 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 09:27:49.758117 ===================================
7072 09:27:49.758216 LPDDR4 DRAM CONFIGURATION
7073 09:27:49.761328 ===================================
7074 09:27:49.764766 EX_ROW_EN[0] = 0x0
7075 09:27:49.764852 EX_ROW_EN[1] = 0x0
7076 09:27:49.768300 LP4Y_EN = 0x0
7077 09:27:49.768385 WORK_FSP = 0x1
7078 09:27:49.771596 WL = 0x5
7079 09:27:49.771681 RL = 0x5
7080 09:27:49.774836 BL = 0x2
7081 09:27:49.778435 RPST = 0x0
7082 09:27:49.778519 RD_PRE = 0x0
7083 09:27:49.781440 WR_PRE = 0x1
7084 09:27:49.781524 WR_PST = 0x1
7085 09:27:49.784629 DBI_WR = 0x0
7086 09:27:49.784713 DBI_RD = 0x0
7087 09:27:49.788146 OTF = 0x1
7088 09:27:49.791316 ===================================
7089 09:27:49.794978 ===================================
7090 09:27:49.795062 ANA top config
7091 09:27:49.798299 ===================================
7092 09:27:49.801228 DLL_ASYNC_EN = 0
7093 09:27:49.804821 ALL_SLAVE_EN = 0
7094 09:27:49.804905 NEW_RANK_MODE = 1
7095 09:27:49.808246 DLL_IDLE_MODE = 1
7096 09:27:49.811196 LP45_APHY_COMB_EN = 1
7097 09:27:49.814631 TX_ODT_DIS = 0
7098 09:27:49.814716 NEW_8X_MODE = 1
7099 09:27:49.818217 ===================================
7100 09:27:49.821227 ===================================
7101 09:27:49.824546 data_rate = 3200
7102 09:27:49.827899 CKR = 1
7103 09:27:49.831298 DQ_P2S_RATIO = 8
7104 09:27:49.834701 ===================================
7105 09:27:49.838152 CA_P2S_RATIO = 8
7106 09:27:49.840943 DQ_CA_OPEN = 0
7107 09:27:49.841028 DQ_SEMI_OPEN = 0
7108 09:27:49.844811 CA_SEMI_OPEN = 0
7109 09:27:49.847712 CA_FULL_RATE = 0
7110 09:27:49.851426 DQ_CKDIV4_EN = 0
7111 09:27:49.854280 CA_CKDIV4_EN = 0
7112 09:27:49.857594 CA_PREDIV_EN = 0
7113 09:27:49.857679 PH8_DLY = 12
7114 09:27:49.861006 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 09:27:49.864746 DQ_AAMCK_DIV = 4
7116 09:27:49.867996 CA_AAMCK_DIV = 4
7117 09:27:49.870914 CA_ADMCK_DIV = 4
7118 09:27:49.874402 DQ_TRACK_CA_EN = 0
7119 09:27:49.877787 CA_PICK = 1600
7120 09:27:49.877872 CA_MCKIO = 1600
7121 09:27:49.880815 MCKIO_SEMI = 0
7122 09:27:49.884361 PLL_FREQ = 3068
7123 09:27:49.887575 DQ_UI_PI_RATIO = 32
7124 09:27:49.891261 CA_UI_PI_RATIO = 0
7125 09:27:49.894414 ===================================
7126 09:27:49.897529 ===================================
7127 09:27:49.901060 memory_type:LPDDR4
7128 09:27:49.901145 GP_NUM : 10
7129 09:27:49.903971 SRAM_EN : 1
7130 09:27:49.904058 MD32_EN : 0
7131 09:27:49.907659 ===================================
7132 09:27:49.910796 [ANA_INIT] >>>>>>>>>>>>>>
7133 09:27:49.913746 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 09:27:49.917277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 09:27:49.920602 ===================================
7136 09:27:49.923625 data_rate = 3200,PCW = 0X7600
7137 09:27:49.927123 ===================================
7138 09:27:49.930453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 09:27:49.937269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 09:27:49.940536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 09:27:49.946911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 09:27:49.950259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 09:27:49.953822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 09:27:49.953904 [ANA_INIT] flow start
7145 09:27:49.956981 [ANA_INIT] PLL >>>>>>>>
7146 09:27:49.960099 [ANA_INIT] PLL <<<<<<<<
7147 09:27:49.960180 [ANA_INIT] MIDPI >>>>>>>>
7148 09:27:49.963801 [ANA_INIT] MIDPI <<<<<<<<
7149 09:27:49.966814 [ANA_INIT] DLL >>>>>>>>
7150 09:27:49.970597 [ANA_INIT] DLL <<<<<<<<
7151 09:27:49.970704 [ANA_INIT] flow end
7152 09:27:49.974028 ============ LP4 DIFF to SE enter ============
7153 09:27:49.980157 ============ LP4 DIFF to SE exit ============
7154 09:27:49.980239 [ANA_INIT] <<<<<<<<<<<<<
7155 09:27:49.983672 [Flow] Enable top DCM control >>>>>
7156 09:27:49.987312 [Flow] Enable top DCM control <<<<<
7157 09:27:49.990250 Enable DLL master slave shuffle
7158 09:27:49.997037 ==============================================================
7159 09:27:49.997120 Gating Mode config
7160 09:27:50.003811 ==============================================================
7161 09:27:50.007258 Config description:
7162 09:27:50.013491 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 09:27:50.020223 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 09:27:50.027030 SELPH_MODE 0: By rank 1: By Phase
7165 09:27:50.033659 ==============================================================
7166 09:27:50.033741 GAT_TRACK_EN = 1
7167 09:27:50.037185 RX_GATING_MODE = 2
7168 09:27:50.040110 RX_GATING_TRACK_MODE = 2
7169 09:27:50.043343 SELPH_MODE = 1
7170 09:27:50.047721 PICG_EARLY_EN = 1
7171 09:27:50.049992 VALID_LAT_VALUE = 1
7172 09:27:50.056433 ==============================================================
7173 09:27:50.059995 Enter into Gating configuration >>>>
7174 09:27:50.063101 Exit from Gating configuration <<<<
7175 09:27:50.066484 Enter into DVFS_PRE_config >>>>>
7176 09:27:50.076306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 09:27:50.079600 Exit from DVFS_PRE_config <<<<<
7178 09:27:50.083170 Enter into PICG configuration >>>>
7179 09:27:50.086345 Exit from PICG configuration <<<<
7180 09:27:50.090239 [RX_INPUT] configuration >>>>>
7181 09:27:50.092944 [RX_INPUT] configuration <<<<<
7182 09:27:50.096638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 09:27:50.103347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 09:27:50.109967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 09:27:50.113492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 09:27:50.120067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 09:27:50.126815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 09:27:50.129709 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 09:27:50.133513 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 09:27:50.140031 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 09:27:50.143038 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 09:27:50.146617 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 09:27:50.153436 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 09:27:50.156473 ===================================
7195 09:27:50.156549 LPDDR4 DRAM CONFIGURATION
7196 09:27:50.159571 ===================================
7197 09:27:50.163226 EX_ROW_EN[0] = 0x0
7198 09:27:50.163300 EX_ROW_EN[1] = 0x0
7199 09:27:50.166564 LP4Y_EN = 0x0
7200 09:27:50.169642 WORK_FSP = 0x1
7201 09:27:50.169723 WL = 0x5
7202 09:27:50.172965 RL = 0x5
7203 09:27:50.173045 BL = 0x2
7204 09:27:50.176246 RPST = 0x0
7205 09:27:50.176326 RD_PRE = 0x0
7206 09:27:50.179814 WR_PRE = 0x1
7207 09:27:50.179894 WR_PST = 0x1
7208 09:27:50.182873 DBI_WR = 0x0
7209 09:27:50.182954 DBI_RD = 0x0
7210 09:27:50.186106 OTF = 0x1
7211 09:27:50.189465 ===================================
7212 09:27:50.192616 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 09:27:50.195961 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 09:27:50.202771 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 09:27:50.206128 ===================================
7216 09:27:50.206211 LPDDR4 DRAM CONFIGURATION
7217 09:27:50.209717 ===================================
7218 09:27:50.212586 EX_ROW_EN[0] = 0x10
7219 09:27:50.212668 EX_ROW_EN[1] = 0x0
7220 09:27:50.216429 LP4Y_EN = 0x0
7221 09:27:50.216511 WORK_FSP = 0x1
7222 09:27:50.219118 WL = 0x5
7223 09:27:50.222709 RL = 0x5
7224 09:27:50.222794 BL = 0x2
7225 09:27:50.225838 RPST = 0x0
7226 09:27:50.225922 RD_PRE = 0x0
7227 09:27:50.229409 WR_PRE = 0x1
7228 09:27:50.229490 WR_PST = 0x1
7229 09:27:50.232425 DBI_WR = 0x0
7230 09:27:50.232506 DBI_RD = 0x0
7231 09:27:50.236243 OTF = 0x1
7232 09:27:50.239112 ===================================
7233 09:27:50.242505 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 09:27:50.246330 ==
7235 09:27:50.249333 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 09:27:50.252621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 09:27:50.252718 ==
7238 09:27:50.256112 [Duty_Offset_Calibration]
7239 09:27:50.256213 B0:2 B1:0 CA:3
7240 09:27:50.256308
7241 09:27:50.259000 [DutyScan_Calibration_Flow] k_type=0
7242 09:27:50.269320
7243 09:27:50.269401 ==CLK 0==
7244 09:27:50.272479 Final CLK duty delay cell = 0
7245 09:27:50.275516 [0] MAX Duty = 5031%(X100), DQS PI = 12
7246 09:27:50.279241 [0] MIN Duty = 4907%(X100), DQS PI = 6
7247 09:27:50.279322 [0] AVG Duty = 4969%(X100)
7248 09:27:50.282469
7249 09:27:50.285574 CH0 CLK Duty spec in!! Max-Min= 124%
7250 09:27:50.288752 [DutyScan_Calibration_Flow] ====Done====
7251 09:27:50.288836
7252 09:27:50.292167 [DutyScan_Calibration_Flow] k_type=1
7253 09:27:50.308645
7254 09:27:50.308730 ==DQS 0 ==
7255 09:27:50.312099 Final DQS duty delay cell = 0
7256 09:27:50.315591 [0] MAX Duty = 5125%(X100), DQS PI = 30
7257 09:27:50.318976 [0] MIN Duty = 4875%(X100), DQS PI = 50
7258 09:27:50.321935 [0] AVG Duty = 5000%(X100)
7259 09:27:50.322019
7260 09:27:50.322112 ==DQS 1 ==
7261 09:27:50.325465 Final DQS duty delay cell = 0
7262 09:27:50.328691 [0] MAX Duty = 5156%(X100), DQS PI = 32
7263 09:27:50.331873 [0] MIN Duty = 5062%(X100), DQS PI = 0
7264 09:27:50.335191 [0] AVG Duty = 5109%(X100)
7265 09:27:50.335272
7266 09:27:50.338840 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7267 09:27:50.338941
7268 09:27:50.341828 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7269 09:27:50.345424 [DutyScan_Calibration_Flow] ====Done====
7270 09:27:50.345504
7271 09:27:50.348384 [DutyScan_Calibration_Flow] k_type=3
7272 09:27:50.366581
7273 09:27:50.366662 ==DQM 0 ==
7274 09:27:50.369597 Final DQM duty delay cell = 0
7275 09:27:50.373459 [0] MAX Duty = 5156%(X100), DQS PI = 28
7276 09:27:50.376396 [0] MIN Duty = 4875%(X100), DQS PI = 0
7277 09:27:50.376477 [0] AVG Duty = 5015%(X100)
7278 09:27:50.379971
7279 09:27:50.380051 ==DQM 1 ==
7280 09:27:50.383026 Final DQM duty delay cell = 4
7281 09:27:50.386952 [4] MAX Duty = 5187%(X100), DQS PI = 60
7282 09:27:50.389803 [4] MIN Duty = 5000%(X100), DQS PI = 40
7283 09:27:50.392931 [4] AVG Duty = 5093%(X100)
7284 09:27:50.393012
7285 09:27:50.396760 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7286 09:27:50.396841
7287 09:27:50.399707 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7288 09:27:50.403097 [DutyScan_Calibration_Flow] ====Done====
7289 09:27:50.403177
7290 09:27:50.406507 [DutyScan_Calibration_Flow] k_type=2
7291 09:27:50.422721
7292 09:27:50.422802 ==DQ 0 ==
7293 09:27:50.426174 Final DQ duty delay cell = -4
7294 09:27:50.429362 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7295 09:27:50.432606 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7296 09:27:50.436263 [-4] AVG Duty = 4938%(X100)
7297 09:27:50.436343
7298 09:27:50.436406 ==DQ 1 ==
7299 09:27:50.439261 Final DQ duty delay cell = 0
7300 09:27:50.442437 [0] MAX Duty = 5156%(X100), DQS PI = 60
7301 09:27:50.445718 [0] MIN Duty = 5000%(X100), DQS PI = 14
7302 09:27:50.449152 [0] AVG Duty = 5078%(X100)
7303 09:27:50.449232
7304 09:27:50.452589 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7305 09:27:50.452669
7306 09:27:50.456041 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7307 09:27:50.458993 [DutyScan_Calibration_Flow] ====Done====
7308 09:27:50.459073 ==
7309 09:27:50.462523 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 09:27:50.465750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 09:27:50.465832 ==
7312 09:27:50.468947 [Duty_Offset_Calibration]
7313 09:27:50.469061 B0:1 B1:-2 CA:1
7314 09:27:50.469125
7315 09:27:50.472725 [DutyScan_Calibration_Flow] k_type=0
7316 09:27:50.483068
7317 09:27:50.483148 ==CLK 0==
7318 09:27:50.486665 Final CLK duty delay cell = 0
7319 09:27:50.490252 [0] MAX Duty = 5031%(X100), DQS PI = 52
7320 09:27:50.493057 [0] MIN Duty = 4876%(X100), DQS PI = 12
7321 09:27:50.496442 [0] AVG Duty = 4953%(X100)
7322 09:27:50.496522
7323 09:27:50.499500 CH1 CLK Duty spec in!! Max-Min= 155%
7324 09:27:50.503022 [DutyScan_Calibration_Flow] ====Done====
7325 09:27:50.503102
7326 09:27:50.506112 [DutyScan_Calibration_Flow] k_type=1
7327 09:27:50.522093
7328 09:27:50.522174 ==DQS 0 ==
7329 09:27:50.525278 Final DQS duty delay cell = -4
7330 09:27:50.528624 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7331 09:27:50.531805 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7332 09:27:50.535553 [-4] AVG Duty = 4891%(X100)
7333 09:27:50.535633
7334 09:27:50.535696 ==DQS 1 ==
7335 09:27:50.538551 Final DQS duty delay cell = 0
7336 09:27:50.541961 [0] MAX Duty = 5124%(X100), DQS PI = 30
7337 09:27:50.545449 [0] MIN Duty = 4844%(X100), DQS PI = 56
7338 09:27:50.548454 [0] AVG Duty = 4984%(X100)
7339 09:27:50.548534
7340 09:27:50.551893 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7341 09:27:50.551972
7342 09:27:50.555328 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7343 09:27:50.558381 [DutyScan_Calibration_Flow] ====Done====
7344 09:27:50.558460
7345 09:27:50.561925 [DutyScan_Calibration_Flow] k_type=3
7346 09:27:50.579550
7347 09:27:50.579632 ==DQM 0 ==
7348 09:27:50.582531 Final DQM duty delay cell = 0
7349 09:27:50.585868 [0] MAX Duty = 5000%(X100), DQS PI = 0
7350 09:27:50.589426 [0] MIN Duty = 4844%(X100), DQS PI = 20
7351 09:27:50.589505 [0] AVG Duty = 4922%(X100)
7352 09:27:50.592689
7353 09:27:50.592795 ==DQM 1 ==
7354 09:27:50.595614 Final DQM duty delay cell = 0
7355 09:27:50.599251 [0] MAX Duty = 5062%(X100), DQS PI = 4
7356 09:27:50.602462 [0] MIN Duty = 4875%(X100), DQS PI = 36
7357 09:27:50.602543 [0] AVG Duty = 4968%(X100)
7358 09:27:50.605595
7359 09:27:50.608722 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7360 09:27:50.608802
7361 09:27:50.612394 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7362 09:27:50.615870 [DutyScan_Calibration_Flow] ====Done====
7363 09:27:50.615950
7364 09:27:50.618716 [DutyScan_Calibration_Flow] k_type=2
7365 09:27:50.635875
7366 09:27:50.635956 ==DQ 0 ==
7367 09:27:50.639414 Final DQ duty delay cell = 0
7368 09:27:50.642292 [0] MAX Duty = 5093%(X100), DQS PI = 54
7369 09:27:50.645401 [0] MIN Duty = 4938%(X100), DQS PI = 14
7370 09:27:50.648879 [0] AVG Duty = 5015%(X100)
7371 09:27:50.648959
7372 09:27:50.649022 ==DQ 1 ==
7373 09:27:50.652536 Final DQ duty delay cell = 0
7374 09:27:50.655591 [0] MAX Duty = 5125%(X100), DQS PI = 2
7375 09:27:50.658911 [0] MIN Duty = 4938%(X100), DQS PI = 56
7376 09:27:50.658991 [0] AVG Duty = 5031%(X100)
7377 09:27:50.662317
7378 09:27:50.665779 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7379 09:27:50.665859
7380 09:27:50.668680 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7381 09:27:50.672374 [DutyScan_Calibration_Flow] ====Done====
7382 09:27:50.675342 nWR fixed to 30
7383 09:27:50.675447 [ModeRegInit_LP4] CH0 RK0
7384 09:27:50.678449 [ModeRegInit_LP4] CH0 RK1
7385 09:27:50.681834 [ModeRegInit_LP4] CH1 RK0
7386 09:27:50.685431 [ModeRegInit_LP4] CH1 RK1
7387 09:27:50.685511 match AC timing 5
7388 09:27:50.692062 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 09:27:50.694914 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 09:27:50.698544 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 09:27:50.704999 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 09:27:50.708557 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 09:27:50.708637 [MiockJmeterHQA]
7394 09:27:50.708700
7395 09:27:50.712030 [DramcMiockJmeter] u1RxGatingPI = 0
7396 09:27:50.715060 0 : 4363, 4137
7397 09:27:50.715142 4 : 4365, 4140
7398 09:27:50.718634 8 : 4255, 4027
7399 09:27:50.718715 12 : 4258, 4030
7400 09:27:50.718780 16 : 4366, 4140
7401 09:27:50.721913 20 : 4255, 4027
7402 09:27:50.721994 24 : 4255, 4029
7403 09:27:50.724766 28 : 4255, 4029
7404 09:27:50.724846 32 : 4255, 4030
7405 09:27:50.728135 36 : 4368, 4144
7406 09:27:50.728216 40 : 4363, 4140
7407 09:27:50.731579 44 : 4255, 4029
7408 09:27:50.731660 48 : 4365, 4140
7409 09:27:50.731724 52 : 4252, 4030
7410 09:27:50.735084 56 : 4250, 4027
7411 09:27:50.735165 60 : 4255, 4030
7412 09:27:50.738200 64 : 4363, 4140
7413 09:27:50.738281 68 : 4255, 4029
7414 09:27:50.741359 72 : 4366, 4140
7415 09:27:50.741441 76 : 4250, 4026
7416 09:27:50.744889 80 : 4255, 4029
7417 09:27:50.744970 84 : 4253, 4029
7418 09:27:50.748043 88 : 4257, 4031
7419 09:27:50.748146 92 : 4250, 4027
7420 09:27:50.748241 96 : 4250, 4026
7421 09:27:50.751151 100 : 4254, 4029
7422 09:27:50.751234 104 : 4361, 4114
7423 09:27:50.754752 108 : 4363, 125
7424 09:27:50.754833 112 : 4252, 0
7425 09:27:50.757819 116 : 4258, 0
7426 09:27:50.757900 120 : 4252, 0
7427 09:27:50.757964 124 : 4366, 0
7428 09:27:50.761375 128 : 4253, 0
7429 09:27:50.761457 132 : 4366, 0
7430 09:27:50.767765 136 : 4253, 0
7431 09:27:50.767877 140 : 4255, 0
7432 09:27:50.767976 144 : 4252, 0
7433 09:27:50.768249 148 : 4361, 0
7434 09:27:50.768317 152 : 4255, 0
7435 09:27:50.768377 156 : 4363, 0
7436 09:27:50.770931 160 : 4364, 0
7437 09:27:50.771013 164 : 4250, 0
7438 09:27:50.774407 168 : 4363, 0
7439 09:27:50.774490 172 : 4252, 0
7440 09:27:50.774555 176 : 4255, 0
7441 09:27:50.777622 180 : 4253, 0
7442 09:27:50.777704 184 : 4252, 0
7443 09:27:50.781000 188 : 4252, 0
7444 09:27:50.781082 192 : 4255, 0
7445 09:27:50.781147 196 : 4252, 0
7446 09:27:50.784663 200 : 4253, 0
7447 09:27:50.784745 204 : 4257, 0
7448 09:27:50.787603 208 : 4363, 0
7449 09:27:50.787685 212 : 4363, 0
7450 09:27:50.787749 216 : 4252, 0
7451 09:27:50.791213 220 : 4252, 0
7452 09:27:50.791309 224 : 4363, 0
7453 09:27:50.791434 228 : 4255, 0
7454 09:27:50.794341 232 : 4253, 0
7455 09:27:50.794423 236 : 4254, 477
7456 09:27:50.797378 240 : 4257, 4030
7457 09:27:50.797460 244 : 4255, 4029
7458 09:27:50.801479 248 : 4363, 4140
7459 09:27:50.801562 252 : 4252, 4030
7460 09:27:50.804209 256 : 4252, 4029
7461 09:27:50.804290 260 : 4363, 4140
7462 09:27:50.807663 264 : 4253, 4029
7463 09:27:50.807746 268 : 4252, 4030
7464 09:27:50.810613 272 : 4252, 4029
7465 09:27:50.810695 276 : 4257, 4032
7466 09:27:50.814194 280 : 4255, 4029
7467 09:27:50.814276 284 : 4365, 4140
7468 09:27:50.814341 288 : 4253, 4029
7469 09:27:50.817579 292 : 4255, 4029
7470 09:27:50.817660 296 : 4255, 4029
7471 09:27:50.820404 300 : 4254, 4030
7472 09:27:50.820486 304 : 4252, 4029
7473 09:27:50.824242 308 : 4252, 4029
7474 09:27:50.824324 312 : 4257, 4031
7475 09:27:50.827135 316 : 4253, 4029
7476 09:27:50.827217 320 : 4252, 4030
7477 09:27:50.830352 324 : 4252, 4029
7478 09:27:50.830434 328 : 4258, 4032
7479 09:27:50.833619 332 : 4365, 4140
7480 09:27:50.833700 336 : 4255, 4030
7481 09:27:50.836996 340 : 4253, 4029
7482 09:27:50.837078 344 : 4258, 4032
7483 09:27:50.837143 348 : 4252, 4027
7484 09:27:50.840274 352 : 4363, 4140
7485 09:27:50.840356 356 : 4252, 3214
7486 09:27:50.843922 360 : 4252, 16
7487 09:27:50.844004
7488 09:27:50.846789 MIOCK jitter meter ch=0
7489 09:27:50.846869
7490 09:27:50.846933 1T = (360-108) = 252 dly cells
7491 09:27:50.853435 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7492 09:27:50.853517 ==
7493 09:27:50.856910 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 09:27:50.860032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 09:27:50.863872 ==
7496 09:27:50.866863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 09:27:50.870229 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 09:27:50.876878 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 09:27:50.883308 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 09:27:50.890719 [CA 0] Center 43 (13~74) winsize 62
7501 09:27:50.894208 [CA 1] Center 43 (13~74) winsize 62
7502 09:27:50.897340 [CA 2] Center 39 (10~68) winsize 59
7503 09:27:50.900880 [CA 3] Center 39 (10~68) winsize 59
7504 09:27:50.903900 [CA 4] Center 36 (7~66) winsize 60
7505 09:27:50.907013 [CA 5] Center 36 (7~66) winsize 60
7506 09:27:50.907094
7507 09:27:50.910644 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 09:27:50.910724
7509 09:27:50.917191 [CATrainingPosCal] consider 1 rank data
7510 09:27:50.917272 u2DelayCellTimex100 = 258/100 ps
7511 09:27:50.923560 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7512 09:27:50.926876 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7513 09:27:50.930415 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7514 09:27:50.933566 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7515 09:27:50.937356 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 09:27:50.940299 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 09:27:50.940380
7518 09:27:50.943758 CA PerBit enable=1, Macro0, CA PI delay=36
7519 09:27:50.943838
7520 09:27:50.946863 [CBTSetCACLKResult] CA Dly = 36
7521 09:27:50.950096 CS Dly: 11 (0~42)
7522 09:27:50.953732 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 09:27:50.957212 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 09:27:50.957293 ==
7525 09:27:50.960107 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 09:27:50.966951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 09:27:50.967055 ==
7528 09:27:50.970020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 09:27:50.977212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 09:27:50.980206 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 09:27:50.987109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 09:27:50.994688 [CA 0] Center 43 (13~74) winsize 62
7533 09:27:50.998108 [CA 1] Center 43 (13~74) winsize 62
7534 09:27:51.001288 [CA 2] Center 39 (10~68) winsize 59
7535 09:27:51.005091 [CA 3] Center 39 (10~68) winsize 59
7536 09:27:51.008130 [CA 4] Center 36 (6~66) winsize 61
7537 09:27:51.011785 [CA 5] Center 36 (6~66) winsize 61
7538 09:27:51.011866
7539 09:27:51.014645 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 09:27:51.014725
7541 09:27:51.021503 [CATrainingPosCal] consider 2 rank data
7542 09:27:51.021585 u2DelayCellTimex100 = 258/100 ps
7543 09:27:51.027745 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7544 09:27:51.031562 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7545 09:27:51.034469 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7546 09:27:51.037908 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7547 09:27:51.041041 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 09:27:51.044544 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7549 09:27:51.044625
7550 09:27:51.047720 CA PerBit enable=1, Macro0, CA PI delay=36
7551 09:27:51.047802
7552 09:27:51.051268 [CBTSetCACLKResult] CA Dly = 36
7553 09:27:51.054811 CS Dly: 11 (0~42)
7554 09:27:51.057852 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 09:27:51.061142 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 09:27:51.061233
7557 09:27:51.064788 ----->DramcWriteLeveling(PI) begin...
7558 09:27:51.064871 ==
7559 09:27:51.067557 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 09:27:51.074321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 09:27:51.074421 ==
7562 09:27:51.077757 Write leveling (Byte 0): 37 => 37
7563 09:27:51.080922 Write leveling (Byte 1): 26 => 26
7564 09:27:51.081003 DramcWriteLeveling(PI) end<-----
7565 09:27:51.081067
7566 09:27:51.084403 ==
7567 09:27:51.088197 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 09:27:51.091099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 09:27:51.091180 ==
7570 09:27:51.094726 [Gating] SW mode calibration
7571 09:27:51.101236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 09:27:51.104568 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 09:27:51.110922 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 09:27:51.114590 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 09:27:51.117518 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 09:27:51.124168 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 09:27:51.127882 1 4 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7578 09:27:51.131099 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7579 09:27:51.137798 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 09:27:51.140836 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 09:27:51.143861 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 09:27:51.150573 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 09:27:51.153943 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 09:27:51.157033 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7585 09:27:51.163679 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7586 09:27:51.166999 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7587 09:27:51.170388 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7588 09:27:51.177118 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7589 09:27:51.180520 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 09:27:51.183347 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 09:27:51.190060 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 09:27:51.193787 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 09:27:51.196667 1 6 16 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7594 09:27:51.203816 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7595 09:27:51.206851 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7596 09:27:51.210218 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 09:27:51.216949 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 09:27:51.220002 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 09:27:51.223554 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 09:27:51.229945 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 09:27:51.233528 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 09:27:51.236768 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7603 09:27:51.243349 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 09:27:51.246592 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7605 09:27:51.250319 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 09:27:51.253191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 09:27:51.260399 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 09:27:51.263139 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 09:27:51.266777 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 09:27:51.273218 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 09:27:51.276868 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 09:27:51.279879 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 09:27:51.286366 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 09:27:51.289931 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 09:27:51.292987 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 09:27:51.300115 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 09:27:51.303243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 09:27:51.306681 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 09:27:51.309783 Total UI for P1: 0, mck2ui 16
7620 09:27:51.313275 best dqsien dly found for B0: ( 1, 9, 16)
7621 09:27:51.319750 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 09:27:51.323093 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 09:27:51.326520 Total UI for P1: 0, mck2ui 16
7624 09:27:51.329850 best dqsien dly found for B1: ( 1, 9, 22)
7625 09:27:51.333264 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7626 09:27:51.336422 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7627 09:27:51.336496
7628 09:27:51.339688 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7629 09:27:51.343137 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7630 09:27:51.346299 [Gating] SW calibration Done
7631 09:27:51.346381 ==
7632 09:27:51.350091 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 09:27:51.356021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 09:27:51.356104 ==
7635 09:27:51.356166 RX Vref Scan: 0
7636 09:27:51.356226
7637 09:27:51.359759 RX Vref 0 -> 0, step: 1
7638 09:27:51.359827
7639 09:27:51.362746 RX Delay 0 -> 252, step: 8
7640 09:27:51.366570 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7641 09:27:51.369753 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7642 09:27:51.372838 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7643 09:27:51.376468 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7644 09:27:51.383036 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7645 09:27:51.386188 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7646 09:27:51.389468 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7647 09:27:51.392673 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7648 09:27:51.395959 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7649 09:27:51.403011 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7650 09:27:51.406363 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7651 09:27:51.409289 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7652 09:27:51.412919 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7653 09:27:51.415983 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
7654 09:27:51.422610 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7655 09:27:51.426114 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7656 09:27:51.426218 ==
7657 09:27:51.429092 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 09:27:51.432318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 09:27:51.432392 ==
7660 09:27:51.435953 DQS Delay:
7661 09:27:51.436028 DQS0 = 0, DQS1 = 0
7662 09:27:51.436097 DQM Delay:
7663 09:27:51.438924 DQM0 = 128, DQM1 = 122
7664 09:27:51.438993 DQ Delay:
7665 09:27:51.442202 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7666 09:27:51.445784 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7667 09:27:51.452626 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7668 09:27:51.455788 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =131
7669 09:27:51.455884
7670 09:27:51.455948
7671 09:27:51.456017 ==
7672 09:27:51.458842 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 09:27:51.462560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 09:27:51.462630 ==
7675 09:27:51.462700
7676 09:27:51.462757
7677 09:27:51.465521 TX Vref Scan disable
7678 09:27:51.465593 == TX Byte 0 ==
7679 09:27:51.472137 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7680 09:27:51.475729 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7681 09:27:51.478915 == TX Byte 1 ==
7682 09:27:51.482452 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7683 09:27:51.485329 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7684 09:27:51.485400 ==
7685 09:27:51.488909 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 09:27:51.491949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 09:27:51.495560 ==
7688 09:27:51.507849
7689 09:27:51.511003 TX Vref early break, caculate TX vref
7690 09:27:51.514336 TX Vref=16, minBit 8, minWin=21, winSum=364
7691 09:27:51.517363 TX Vref=18, minBit 9, minWin=21, winSum=373
7692 09:27:51.520783 TX Vref=20, minBit 8, minWin=22, winSum=384
7693 09:27:51.524160 TX Vref=22, minBit 11, minWin=23, winSum=394
7694 09:27:51.527293 TX Vref=24, minBit 8, minWin=23, winSum=399
7695 09:27:51.533934 TX Vref=26, minBit 8, minWin=24, winSum=409
7696 09:27:51.537228 TX Vref=28, minBit 9, minWin=24, winSum=408
7697 09:27:51.540976 TX Vref=30, minBit 8, minWin=24, winSum=404
7698 09:27:51.543885 TX Vref=32, minBit 9, minWin=23, winSum=397
7699 09:27:51.547542 TX Vref=34, minBit 8, minWin=22, winSum=385
7700 09:27:51.553829 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 26
7701 09:27:51.553943
7702 09:27:51.557646 Final TX Range 0 Vref 26
7703 09:27:51.557771
7704 09:27:51.557903 ==
7705 09:27:51.560835 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 09:27:51.563995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 09:27:51.564068 ==
7708 09:27:51.564204
7709 09:27:51.564292
7710 09:27:51.567650 TX Vref Scan disable
7711 09:27:51.573712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7712 09:27:51.573794 == TX Byte 0 ==
7713 09:27:51.577351 u2DelayCellOfst[0]=15 cells (4 PI)
7714 09:27:51.580510 u2DelayCellOfst[1]=18 cells (5 PI)
7715 09:27:51.583716 u2DelayCellOfst[2]=11 cells (3 PI)
7716 09:27:51.587231 u2DelayCellOfst[3]=11 cells (3 PI)
7717 09:27:51.590375 u2DelayCellOfst[4]=7 cells (2 PI)
7718 09:27:51.593846 u2DelayCellOfst[5]=0 cells (0 PI)
7719 09:27:51.596984 u2DelayCellOfst[6]=18 cells (5 PI)
7720 09:27:51.600343 u2DelayCellOfst[7]=18 cells (5 PI)
7721 09:27:51.603585 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7722 09:27:51.607127 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7723 09:27:51.610772 == TX Byte 1 ==
7724 09:27:51.614141 u2DelayCellOfst[8]=0 cells (0 PI)
7725 09:27:51.614259 u2DelayCellOfst[9]=0 cells (0 PI)
7726 09:27:51.617185 u2DelayCellOfst[10]=7 cells (2 PI)
7727 09:27:51.620232 u2DelayCellOfst[11]=3 cells (1 PI)
7728 09:27:51.623684 u2DelayCellOfst[12]=11 cells (3 PI)
7729 09:27:51.627075 u2DelayCellOfst[13]=11 cells (3 PI)
7730 09:27:51.630248 u2DelayCellOfst[14]=15 cells (4 PI)
7731 09:27:51.633537 u2DelayCellOfst[15]=11 cells (3 PI)
7732 09:27:51.637055 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7733 09:27:51.643756 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7734 09:27:51.643863 DramC Write-DBI on
7735 09:27:51.643957 ==
7736 09:27:51.647192 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 09:27:51.650217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 09:27:51.653693 ==
7739 09:27:51.653804
7740 09:27:51.653906
7741 09:27:51.654005 TX Vref Scan disable
7742 09:27:51.657284 == TX Byte 0 ==
7743 09:27:51.660534 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7744 09:27:51.664327 == TX Byte 1 ==
7745 09:27:51.667323 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7746 09:27:51.670413 DramC Write-DBI off
7747 09:27:51.670526
7748 09:27:51.670619 [DATLAT]
7749 09:27:51.670722 Freq=1600, CH0 RK0
7750 09:27:51.670812
7751 09:27:51.674241 DATLAT Default: 0xf
7752 09:27:51.674334 0, 0xFFFF, sum = 0
7753 09:27:51.677209 1, 0xFFFF, sum = 0
7754 09:27:51.677295 2, 0xFFFF, sum = 0
7755 09:27:51.680835 3, 0xFFFF, sum = 0
7756 09:27:51.683828 4, 0xFFFF, sum = 0
7757 09:27:51.683915 5, 0xFFFF, sum = 0
7758 09:27:51.687501 6, 0xFFFF, sum = 0
7759 09:27:51.687585 7, 0xFFFF, sum = 0
7760 09:27:51.690519 8, 0xFFFF, sum = 0
7761 09:27:51.690602 9, 0xFFFF, sum = 0
7762 09:27:51.694060 10, 0xFFFF, sum = 0
7763 09:27:51.694143 11, 0xFFFF, sum = 0
7764 09:27:51.697174 12, 0xFFFF, sum = 0
7765 09:27:51.697258 13, 0xEFFF, sum = 0
7766 09:27:51.700597 14, 0x0, sum = 1
7767 09:27:51.700681 15, 0x0, sum = 2
7768 09:27:51.703791 16, 0x0, sum = 3
7769 09:27:51.703921 17, 0x0, sum = 4
7770 09:27:51.707306 best_step = 15
7771 09:27:51.707415
7772 09:27:51.707481 ==
7773 09:27:51.710481 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 09:27:51.713773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 09:27:51.713939 ==
7776 09:27:51.716778 RX Vref Scan: 1
7777 09:27:51.716877
7778 09:27:51.716976 Set Vref Range= 24 -> 127
7779 09:27:51.717063
7780 09:27:51.720451 RX Vref 24 -> 127, step: 1
7781 09:27:51.720548
7782 09:27:51.723447 RX Delay 11 -> 252, step: 4
7783 09:27:51.723529
7784 09:27:51.726836 Set Vref, RX VrefLevel [Byte0]: 24
7785 09:27:51.730147 [Byte1]: 24
7786 09:27:51.730219
7787 09:27:51.733535 Set Vref, RX VrefLevel [Byte0]: 25
7788 09:27:51.736695 [Byte1]: 25
7789 09:27:51.740066
7790 09:27:51.740157 Set Vref, RX VrefLevel [Byte0]: 26
7791 09:27:51.743213 [Byte1]: 26
7792 09:27:51.747506
7793 09:27:51.747589 Set Vref, RX VrefLevel [Byte0]: 27
7794 09:27:51.750936 [Byte1]: 27
7795 09:27:51.755344
7796 09:27:51.755472 Set Vref, RX VrefLevel [Byte0]: 28
7797 09:27:51.758845 [Byte1]: 28
7798 09:27:51.763106
7799 09:27:51.763183 Set Vref, RX VrefLevel [Byte0]: 29
7800 09:27:51.766087 [Byte1]: 29
7801 09:27:51.770278
7802 09:27:51.770360 Set Vref, RX VrefLevel [Byte0]: 30
7803 09:27:51.773818 [Byte1]: 30
7804 09:27:51.777919
7805 09:27:51.777996 Set Vref, RX VrefLevel [Byte0]: 31
7806 09:27:51.781454 [Byte1]: 31
7807 09:27:51.786059
7808 09:27:51.786158 Set Vref, RX VrefLevel [Byte0]: 32
7809 09:27:51.789067 [Byte1]: 32
7810 09:27:51.793353
7811 09:27:51.793423 Set Vref, RX VrefLevel [Byte0]: 33
7812 09:27:51.796917 [Byte1]: 33
7813 09:27:51.801270
7814 09:27:51.801339 Set Vref, RX VrefLevel [Byte0]: 34
7815 09:27:51.804561 [Byte1]: 34
7816 09:27:51.808392
7817 09:27:51.808462 Set Vref, RX VrefLevel [Byte0]: 35
7818 09:27:51.811978 [Byte1]: 35
7819 09:27:51.816415
7820 09:27:51.816483 Set Vref, RX VrefLevel [Byte0]: 36
7821 09:27:51.819359 [Byte1]: 36
7822 09:27:51.823783
7823 09:27:51.823851 Set Vref, RX VrefLevel [Byte0]: 37
7824 09:27:51.827361 [Byte1]: 37
7825 09:27:51.831667
7826 09:27:51.831746 Set Vref, RX VrefLevel [Byte0]: 38
7827 09:27:51.834651 [Byte1]: 38
7828 09:27:51.838986
7829 09:27:51.839066 Set Vref, RX VrefLevel [Byte0]: 39
7830 09:27:51.842545 [Byte1]: 39
7831 09:27:51.847018
7832 09:27:51.847094 Set Vref, RX VrefLevel [Byte0]: 40
7833 09:27:51.849770 [Byte1]: 40
7834 09:27:51.854288
7835 09:27:51.854362 Set Vref, RX VrefLevel [Byte0]: 41
7836 09:27:51.857409 [Byte1]: 41
7837 09:27:51.861802
7838 09:27:51.861928 Set Vref, RX VrefLevel [Byte0]: 42
7839 09:27:51.865074 [Byte1]: 42
7840 09:27:51.869787
7841 09:27:51.869878 Set Vref, RX VrefLevel [Byte0]: 43
7842 09:27:51.872885 [Byte1]: 43
7843 09:27:51.877255
7844 09:27:51.877352 Set Vref, RX VrefLevel [Byte0]: 44
7845 09:27:51.880588 [Byte1]: 44
7846 09:27:51.884505
7847 09:27:51.884574 Set Vref, RX VrefLevel [Byte0]: 45
7848 09:27:51.888099 [Byte1]: 45
7849 09:27:51.892276
7850 09:27:51.892345 Set Vref, RX VrefLevel [Byte0]: 46
7851 09:27:51.895596 [Byte1]: 46
7852 09:27:51.899951
7853 09:27:51.900036 Set Vref, RX VrefLevel [Byte0]: 47
7854 09:27:51.903279 [Byte1]: 47
7855 09:27:51.907733
7856 09:27:51.907810 Set Vref, RX VrefLevel [Byte0]: 48
7857 09:27:51.911239 [Byte1]: 48
7858 09:27:51.915012
7859 09:27:51.915088 Set Vref, RX VrefLevel [Byte0]: 49
7860 09:27:51.918505 [Byte1]: 49
7861 09:27:51.922783
7862 09:27:51.922864 Set Vref, RX VrefLevel [Byte0]: 50
7863 09:27:51.926600 [Byte1]: 50
7864 09:27:51.930679
7865 09:27:51.930753 Set Vref, RX VrefLevel [Byte0]: 51
7866 09:27:51.933849 [Byte1]: 51
7867 09:27:51.937954
7868 09:27:51.938028 Set Vref, RX VrefLevel [Byte0]: 52
7869 09:27:51.941095 [Byte1]: 52
7870 09:27:51.945417
7871 09:27:51.945488 Set Vref, RX VrefLevel [Byte0]: 53
7872 09:27:51.949117 [Byte1]: 53
7873 09:27:51.953371
7874 09:27:51.953454 Set Vref, RX VrefLevel [Byte0]: 54
7875 09:27:51.956738 [Byte1]: 54
7876 09:27:51.961044
7877 09:27:51.961139 Set Vref, RX VrefLevel [Byte0]: 55
7878 09:27:51.964211 [Byte1]: 55
7879 09:27:51.968458
7880 09:27:51.968536 Set Vref, RX VrefLevel [Byte0]: 56
7881 09:27:51.971967 [Byte1]: 56
7882 09:27:51.976187
7883 09:27:51.976262 Set Vref, RX VrefLevel [Byte0]: 57
7884 09:27:51.979276 [Byte1]: 57
7885 09:27:51.984062
7886 09:27:51.984173 Set Vref, RX VrefLevel [Byte0]: 58
7887 09:27:51.986803 [Byte1]: 58
7888 09:27:51.991058
7889 09:27:51.991133 Set Vref, RX VrefLevel [Byte0]: 59
7890 09:27:51.994639 [Byte1]: 59
7891 09:27:51.998696
7892 09:27:51.998770 Set Vref, RX VrefLevel [Byte0]: 60
7893 09:27:52.002114 [Byte1]: 60
7894 09:27:52.006435
7895 09:27:52.006547 Set Vref, RX VrefLevel [Byte0]: 61
7896 09:27:52.009589 [Byte1]: 61
7897 09:27:52.014212
7898 09:27:52.014295 Set Vref, RX VrefLevel [Byte0]: 62
7899 09:27:52.017696 [Byte1]: 62
7900 09:27:52.021840
7901 09:27:52.021936 Set Vref, RX VrefLevel [Byte0]: 63
7902 09:27:52.025108 [Byte1]: 63
7903 09:27:52.029487
7904 09:27:52.029563 Set Vref, RX VrefLevel [Byte0]: 64
7905 09:27:52.033061 [Byte1]: 64
7906 09:27:52.036863
7907 09:27:52.036964 Set Vref, RX VrefLevel [Byte0]: 65
7908 09:27:52.040066 [Byte1]: 65
7909 09:27:52.044450
7910 09:27:52.044572 Set Vref, RX VrefLevel [Byte0]: 66
7911 09:27:52.048202 [Byte1]: 66
7912 09:27:52.051929
7913 09:27:52.052053 Set Vref, RX VrefLevel [Byte0]: 67
7914 09:27:52.055727 [Byte1]: 67
7915 09:27:52.059991
7916 09:27:52.060092 Set Vref, RX VrefLevel [Byte0]: 68
7917 09:27:52.063157 [Byte1]: 68
7918 09:27:52.067355
7919 09:27:52.067452 Set Vref, RX VrefLevel [Byte0]: 69
7920 09:27:52.070629 [Byte1]: 69
7921 09:27:52.075181
7922 09:27:52.075294 Set Vref, RX VrefLevel [Byte0]: 70
7923 09:27:52.078309 [Byte1]: 70
7924 09:27:52.082894
7925 09:27:52.083032 Set Vref, RX VrefLevel [Byte0]: 71
7926 09:27:52.085856 [Byte1]: 71
7927 09:27:52.090378
7928 09:27:52.090503 Set Vref, RX VrefLevel [Byte0]: 72
7929 09:27:52.093851 [Byte1]: 72
7930 09:27:52.098059
7931 09:27:52.098136 Set Vref, RX VrefLevel [Byte0]: 73
7932 09:27:52.101174 [Byte1]: 73
7933 09:27:52.105662
7934 09:27:52.105768 Set Vref, RX VrefLevel [Byte0]: 74
7935 09:27:52.108752 [Byte1]: 74
7936 09:27:52.113101
7937 09:27:52.113214 Set Vref, RX VrefLevel [Byte0]: 75
7938 09:27:52.116103 [Byte1]: 75
7939 09:27:52.120761
7940 09:27:52.120848 Set Vref, RX VrefLevel [Byte0]: 76
7941 09:27:52.123878 [Byte1]: 76
7942 09:27:52.128073
7943 09:27:52.128161 Set Vref, RX VrefLevel [Byte0]: 77
7944 09:27:52.131762 [Byte1]: 77
7945 09:27:52.135798
7946 09:27:52.135909 Final RX Vref Byte 0 = 63 to rank0
7947 09:27:52.139401 Final RX Vref Byte 1 = 60 to rank0
7948 09:27:52.143066 Final RX Vref Byte 0 = 63 to rank1
7949 09:27:52.146209 Final RX Vref Byte 1 = 60 to rank1==
7950 09:27:52.149285 Dram Type= 6, Freq= 0, CH_0, rank 0
7951 09:27:52.156093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 09:27:52.156180 ==
7953 09:27:52.156246 DQS Delay:
7954 09:27:52.156321 DQS0 = 0, DQS1 = 0
7955 09:27:52.159180 DQM Delay:
7956 09:27:52.159279 DQM0 = 126, DQM1 = 119
7957 09:27:52.162331 DQ Delay:
7958 09:27:52.165849 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7959 09:27:52.168922 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7960 09:27:52.172385 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7961 09:27:52.176019 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7962 09:27:52.176102
7963 09:27:52.176166
7964 09:27:52.176227
7965 09:27:52.178916 [DramC_TX_OE_Calibration] TA2
7966 09:27:52.182659 Original DQ_B0 (3 6) =30, OEN = 27
7967 09:27:52.185744 Original DQ_B1 (3 6) =30, OEN = 27
7968 09:27:52.189390 24, 0x0, End_B0=24 End_B1=24
7969 09:27:52.189474 25, 0x0, End_B0=25 End_B1=25
7970 09:27:52.192351 26, 0x0, End_B0=26 End_B1=26
7971 09:27:52.195893 27, 0x0, End_B0=27 End_B1=27
7972 09:27:52.198861 28, 0x0, End_B0=28 End_B1=28
7973 09:27:52.202577 29, 0x0, End_B0=29 End_B1=29
7974 09:27:52.202662 30, 0x0, End_B0=30 End_B1=30
7975 09:27:52.205573 31, 0x4141, End_B0=30 End_B1=30
7976 09:27:52.209133 Byte0 end_step=30 best_step=27
7977 09:27:52.212233 Byte1 end_step=30 best_step=27
7978 09:27:52.215276 Byte0 TX OE(2T, 0.5T) = (3, 3)
7979 09:27:52.218985 Byte1 TX OE(2T, 0.5T) = (3, 3)
7980 09:27:52.219069
7981 09:27:52.219134
7982 09:27:52.225760 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7983 09:27:52.228670 CH0 RK0: MR19=303, MR18=1212
7984 09:27:52.235154 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
7985 09:27:52.235237
7986 09:27:52.238707 ----->DramcWriteLeveling(PI) begin...
7987 09:27:52.238791 ==
7988 09:27:52.242195 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 09:27:52.245380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 09:27:52.245463 ==
7991 09:27:52.248648 Write leveling (Byte 0): 32 => 32
7992 09:27:52.251872 Write leveling (Byte 1): 28 => 28
7993 09:27:52.255260 DramcWriteLeveling(PI) end<-----
7994 09:27:52.255371
7995 09:27:52.255478 ==
7996 09:27:52.258739 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 09:27:52.261848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 09:27:52.261958 ==
7999 09:27:52.265541 [Gating] SW mode calibration
8000 09:27:52.271802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8001 09:27:52.279151 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8002 09:27:52.282317 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 09:27:52.285512 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 09:27:52.291963 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 09:27:52.295281 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8006 09:27:52.298435 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
8007 09:27:52.304925 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8008 09:27:52.308700 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 09:27:52.312209 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 09:27:52.318738 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 09:27:52.321930 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 09:27:52.325624 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8013 09:27:52.331750 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8014 09:27:52.334955 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8015 09:27:52.338681 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
8016 09:27:52.344827 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 09:27:52.348346 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 09:27:52.351505 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 09:27:52.358129 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 09:27:52.361489 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8021 09:27:52.365040 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8022 09:27:52.371748 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8023 09:27:52.374563 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8024 09:27:52.378052 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 09:27:52.384968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 09:27:52.387954 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 09:27:52.391520 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 09:27:52.398286 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 09:27:52.401302 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 09:27:52.404473 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8031 09:27:52.411368 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8032 09:27:52.414505 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 09:27:52.417961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 09:27:52.424442 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 09:27:52.427752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 09:27:52.431347 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 09:27:52.437968 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 09:27:52.440855 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 09:27:52.444325 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 09:27:52.450941 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 09:27:52.454680 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 09:27:52.457699 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 09:27:52.460717 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 09:27:52.467550 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 09:27:52.471170 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8046 09:27:52.474193 Total UI for P1: 0, mck2ui 16
8047 09:27:52.477403 best dqsien dly found for B0: ( 1, 9, 8)
8048 09:27:52.481182 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 09:27:52.487673 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 09:27:52.490736 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 09:27:52.493816 Total UI for P1: 0, mck2ui 16
8052 09:27:52.497702 best dqsien dly found for B1: ( 1, 9, 16)
8053 09:27:52.500758 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8054 09:27:52.504106 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8055 09:27:52.504181
8056 09:27:52.507493 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8057 09:27:52.513780 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8058 09:27:52.513860 [Gating] SW calibration Done
8059 09:27:52.513925 ==
8060 09:27:52.517105 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 09:27:52.523696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 09:27:52.523774 ==
8063 09:27:52.523838 RX Vref Scan: 0
8064 09:27:52.523898
8065 09:27:52.527351 RX Vref 0 -> 0, step: 1
8066 09:27:52.527426
8067 09:27:52.530202 RX Delay 0 -> 252, step: 8
8068 09:27:52.533512 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8069 09:27:52.536756 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8070 09:27:52.540722 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8071 09:27:52.543783 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8072 09:27:52.550517 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8073 09:27:52.553527 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8074 09:27:52.557188 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8075 09:27:52.560390 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8076 09:27:52.563536 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8077 09:27:52.570258 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8078 09:27:52.573464 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8079 09:27:52.576627 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8080 09:27:52.580562 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8081 09:27:52.586642 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8082 09:27:52.590463 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8083 09:27:52.593478 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8084 09:27:52.593585 ==
8085 09:27:52.596599 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 09:27:52.599776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 09:27:52.599855 ==
8088 09:27:52.603145 DQS Delay:
8089 09:27:52.603261 DQS0 = 0, DQS1 = 0
8090 09:27:52.606700 DQM Delay:
8091 09:27:52.606786 DQM0 = 128, DQM1 = 122
8092 09:27:52.606883 DQ Delay:
8093 09:27:52.612981 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8094 09:27:52.616378 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8095 09:27:52.619757 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8096 09:27:52.623097 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8097 09:27:52.623205
8098 09:27:52.623297
8099 09:27:52.623392 ==
8100 09:27:52.626541 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 09:27:52.629826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 09:27:52.629929 ==
8103 09:27:52.630032
8104 09:27:52.630121
8105 09:27:52.632774 TX Vref Scan disable
8106 09:27:52.636232 == TX Byte 0 ==
8107 09:27:52.639858 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8108 09:27:52.643122 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8109 09:27:52.646169 == TX Byte 1 ==
8110 09:27:52.649857 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8111 09:27:52.652946 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8112 09:27:52.653036 ==
8113 09:27:52.656121 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 09:27:52.659705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 09:27:52.662801 ==
8116 09:27:52.675954
8117 09:27:52.679073 TX Vref early break, caculate TX vref
8118 09:27:52.682330 TX Vref=16, minBit 0, minWin=22, winSum=365
8119 09:27:52.685610 TX Vref=18, minBit 8, minWin=22, winSum=374
8120 09:27:52.688736 TX Vref=20, minBit 8, minWin=22, winSum=380
8121 09:27:52.692349 TX Vref=22, minBit 1, minWin=23, winSum=384
8122 09:27:52.695380 TX Vref=24, minBit 1, minWin=24, winSum=398
8123 09:27:52.701828 TX Vref=26, minBit 1, minWin=25, winSum=409
8124 09:27:52.705593 TX Vref=28, minBit 8, minWin=24, winSum=408
8125 09:27:52.708570 TX Vref=30, minBit 8, minWin=24, winSum=401
8126 09:27:52.712023 TX Vref=32, minBit 8, minWin=22, winSum=394
8127 09:27:52.715488 TX Vref=34, minBit 8, minWin=22, winSum=391
8128 09:27:52.718567 TX Vref=36, minBit 8, minWin=22, winSum=380
8129 09:27:52.725110 [TxChooseVref] Worse bit 1, Min win 25, Win sum 409, Final Vref 26
8130 09:27:52.725215
8131 09:27:52.728610 Final TX Range 0 Vref 26
8132 09:27:52.728733
8133 09:27:52.728890 ==
8134 09:27:52.732259 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 09:27:52.735125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 09:27:52.735253 ==
8137 09:27:52.735345
8138 09:27:52.738615
8139 09:27:52.738697 TX Vref Scan disable
8140 09:27:52.745195 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8141 09:27:52.745315 == TX Byte 0 ==
8142 09:27:52.748141 u2DelayCellOfst[0]=15 cells (4 PI)
8143 09:27:52.751830 u2DelayCellOfst[1]=22 cells (6 PI)
8144 09:27:52.754869 u2DelayCellOfst[2]=15 cells (4 PI)
8145 09:27:52.758585 u2DelayCellOfst[3]=15 cells (4 PI)
8146 09:27:52.761531 u2DelayCellOfst[4]=11 cells (3 PI)
8147 09:27:52.765200 u2DelayCellOfst[5]=0 cells (0 PI)
8148 09:27:52.768039 u2DelayCellOfst[6]=22 cells (6 PI)
8149 09:27:52.771735 u2DelayCellOfst[7]=22 cells (6 PI)
8150 09:27:52.774890 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8151 09:27:52.777868 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8152 09:27:52.781148 == TX Byte 1 ==
8153 09:27:52.784891 u2DelayCellOfst[8]=0 cells (0 PI)
8154 09:27:52.787939 u2DelayCellOfst[9]=0 cells (0 PI)
8155 09:27:52.791105 u2DelayCellOfst[10]=11 cells (3 PI)
8156 09:27:52.794814 u2DelayCellOfst[11]=7 cells (2 PI)
8157 09:27:52.798085 u2DelayCellOfst[12]=15 cells (4 PI)
8158 09:27:52.798190 u2DelayCellOfst[13]=11 cells (3 PI)
8159 09:27:52.801194 u2DelayCellOfst[14]=15 cells (4 PI)
8160 09:27:52.804427 u2DelayCellOfst[15]=15 cells (4 PI)
8161 09:27:52.811045 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8162 09:27:52.814258 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8163 09:27:52.817935 DramC Write-DBI on
8164 09:27:52.818017 ==
8165 09:27:52.821029 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 09:27:52.824090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 09:27:52.824198 ==
8168 09:27:52.824291
8169 09:27:52.824388
8170 09:27:52.827840 TX Vref Scan disable
8171 09:27:52.827939 == TX Byte 0 ==
8172 09:27:52.834591 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8173 09:27:52.834675 == TX Byte 1 ==
8174 09:27:52.837782 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8175 09:27:52.840730 DramC Write-DBI off
8176 09:27:52.840845
8177 09:27:52.840937 [DATLAT]
8178 09:27:52.844242 Freq=1600, CH0 RK1
8179 09:27:52.844349
8180 09:27:52.844454 DATLAT Default: 0xf
8181 09:27:52.847438 0, 0xFFFF, sum = 0
8182 09:27:52.847549 1, 0xFFFF, sum = 0
8183 09:27:52.850994 2, 0xFFFF, sum = 0
8184 09:27:52.851106 3, 0xFFFF, sum = 0
8185 09:27:52.854468 4, 0xFFFF, sum = 0
8186 09:27:52.854566 5, 0xFFFF, sum = 0
8187 09:27:52.857205 6, 0xFFFF, sum = 0
8188 09:27:52.860532 7, 0xFFFF, sum = 0
8189 09:27:52.860611 8, 0xFFFF, sum = 0
8190 09:27:52.864344 9, 0xFFFF, sum = 0
8191 09:27:52.864455 10, 0xFFFF, sum = 0
8192 09:27:52.867299 11, 0xFFFF, sum = 0
8193 09:27:52.867414 12, 0xFFFF, sum = 0
8194 09:27:52.870719 13, 0xCFFF, sum = 0
8195 09:27:52.870796 14, 0x0, sum = 1
8196 09:27:52.874120 15, 0x0, sum = 2
8197 09:27:52.874200 16, 0x0, sum = 3
8198 09:27:52.877090 17, 0x0, sum = 4
8199 09:27:52.877175 best_step = 15
8200 09:27:52.877242
8201 09:27:52.877304 ==
8202 09:27:52.880683 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 09:27:52.883902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 09:27:52.887653 ==
8205 09:27:52.887737 RX Vref Scan: 0
8206 09:27:52.887803
8207 09:27:52.890892 RX Vref 0 -> 0, step: 1
8208 09:27:52.890975
8209 09:27:52.891040 RX Delay 3 -> 252, step: 4
8210 09:27:52.898227 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8211 09:27:52.901693 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8212 09:27:52.904782 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8213 09:27:52.907831 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8214 09:27:52.911139 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8215 09:27:52.917934 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8216 09:27:52.920950 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8217 09:27:52.924627 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8218 09:27:52.927813 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8219 09:27:52.930898 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8220 09:27:52.938020 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8221 09:27:52.940884 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8222 09:27:52.944189 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8223 09:27:52.947438 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8224 09:27:52.954191 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8225 09:27:52.957395 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8226 09:27:52.957510 ==
8227 09:27:52.961065 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 09:27:52.964174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 09:27:52.964278 ==
8230 09:27:52.964381 DQS Delay:
8231 09:27:52.967313 DQS0 = 0, DQS1 = 0
8232 09:27:52.967413 DQM Delay:
8233 09:27:52.970830 DQM0 = 124, DQM1 = 118
8234 09:27:52.970946 DQ Delay:
8235 09:27:52.974556 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8236 09:27:52.977337 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8237 09:27:52.981142 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8238 09:27:52.987857 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8239 09:27:52.987964
8240 09:27:52.988064
8241 09:27:52.988153
8242 09:27:52.988240 [DramC_TX_OE_Calibration] TA2
8243 09:27:52.991142 Original DQ_B0 (3 6) =30, OEN = 27
8244 09:27:52.994312 Original DQ_B1 (3 6) =30, OEN = 27
8245 09:27:52.997441 24, 0x0, End_B0=24 End_B1=24
8246 09:27:53.000539 25, 0x0, End_B0=25 End_B1=25
8247 09:27:53.004306 26, 0x0, End_B0=26 End_B1=26
8248 09:27:53.004418 27, 0x0, End_B0=27 End_B1=27
8249 09:27:53.007645 28, 0x0, End_B0=28 End_B1=28
8250 09:27:53.010489 29, 0x0, End_B0=29 End_B1=29
8251 09:27:53.014466 30, 0x0, End_B0=30 End_B1=30
8252 09:27:53.017610 31, 0x4141, End_B0=30 End_B1=30
8253 09:27:53.020468 Byte0 end_step=30 best_step=27
8254 09:27:53.020574 Byte1 end_step=30 best_step=27
8255 09:27:53.024448 Byte0 TX OE(2T, 0.5T) = (3, 3)
8256 09:27:53.027300 Byte1 TX OE(2T, 0.5T) = (3, 3)
8257 09:27:53.027376
8258 09:27:53.027475
8259 09:27:53.037342 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8260 09:27:53.037429 CH0 RK1: MR19=303, MR18=2210
8261 09:27:53.044140 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8262 09:27:53.047316 [RxdqsGatingPostProcess] freq 1600
8263 09:27:53.054195 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8264 09:27:53.057214 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 09:27:53.060363 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 09:27:53.063872 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 09:27:53.067344 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 09:27:53.067449 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 09:27:53.070320 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 09:27:53.073807 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 09:27:53.076995 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 09:27:53.080317 Pre-setting of DQS Precalculation
8273 09:27:53.087480 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8274 09:27:53.087565 ==
8275 09:27:53.090485 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 09:27:53.094016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 09:27:53.094129 ==
8278 09:27:53.100429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 09:27:53.103751 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 09:27:53.107244 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 09:27:53.113946 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 09:27:53.121892 [CA 0] Center 41 (12~71) winsize 60
8283 09:27:53.125757 [CA 1] Center 42 (12~72) winsize 61
8284 09:27:53.128926 [CA 2] Center 38 (9~67) winsize 59
8285 09:27:53.132129 [CA 3] Center 37 (8~66) winsize 59
8286 09:27:53.135511 [CA 4] Center 37 (8~67) winsize 60
8287 09:27:53.138743 [CA 5] Center 36 (7~66) winsize 60
8288 09:27:53.138828
8289 09:27:53.141662 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8290 09:27:53.141735
8291 09:27:53.145536 [CATrainingPosCal] consider 1 rank data
8292 09:27:53.148822 u2DelayCellTimex100 = 258/100 ps
8293 09:27:53.155047 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8294 09:27:53.158906 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8295 09:27:53.162029 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8296 09:27:53.165084 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8297 09:27:53.168297 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8298 09:27:53.171657 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8299 09:27:53.171736
8300 09:27:53.174975 CA PerBit enable=1, Macro0, CA PI delay=36
8301 09:27:53.175075
8302 09:27:53.178703 [CBTSetCACLKResult] CA Dly = 36
8303 09:27:53.181905 CS Dly: 9 (0~40)
8304 09:27:53.185414 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 09:27:53.188281 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 09:27:53.188363 ==
8307 09:27:53.191962 Dram Type= 6, Freq= 0, CH_1, rank 1
8308 09:27:53.195068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 09:27:53.198193 ==
8310 09:27:53.201625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 09:27:53.205123 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 09:27:53.212092 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 09:27:53.214928 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 09:27:53.225835 [CA 0] Center 42 (13~71) winsize 59
8315 09:27:53.228721 [CA 1] Center 42 (12~72) winsize 61
8316 09:27:53.232259 [CA 2] Center 37 (8~67) winsize 60
8317 09:27:53.235041 [CA 3] Center 36 (7~66) winsize 60
8318 09:27:53.238626 [CA 4] Center 38 (8~68) winsize 61
8319 09:27:53.241823 [CA 5] Center 37 (7~67) winsize 61
8320 09:27:53.241904
8321 09:27:53.244995 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8322 09:27:53.245077
8323 09:27:53.248708 [CATrainingPosCal] consider 2 rank data
8324 09:27:53.251733 u2DelayCellTimex100 = 258/100 ps
8325 09:27:53.254981 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8326 09:27:53.261585 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8327 09:27:53.264843 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8328 09:27:53.268563 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8329 09:27:53.271732 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8330 09:27:53.274748 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8331 09:27:53.274829
8332 09:27:53.278620 CA PerBit enable=1, Macro0, CA PI delay=36
8333 09:27:53.278701
8334 09:27:53.281645 [CBTSetCACLKResult] CA Dly = 36
8335 09:27:53.284733 CS Dly: 10 (0~43)
8336 09:27:53.288330 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 09:27:53.291567 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 09:27:53.291647
8339 09:27:53.294728 ----->DramcWriteLeveling(PI) begin...
8340 09:27:53.294809 ==
8341 09:27:53.298260 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 09:27:53.304545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 09:27:53.304627 ==
8344 09:27:53.308122 Write leveling (Byte 0): 24 => 24
8345 09:27:53.308203 Write leveling (Byte 1): 28 => 28
8346 09:27:53.311519 DramcWriteLeveling(PI) end<-----
8347 09:27:53.311601
8348 09:27:53.314731 ==
8349 09:27:53.314814 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 09:27:53.321203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 09:27:53.321285 ==
8352 09:27:53.324644 [Gating] SW mode calibration
8353 09:27:53.331226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8354 09:27:53.334234 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8355 09:27:53.340736 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 09:27:53.344158 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 09:27:53.347725 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 09:27:53.354306 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 09:27:53.357800 1 4 16 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
8360 09:27:53.360983 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 09:27:53.367819 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 09:27:53.370884 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 09:27:53.374160 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 09:27:53.380904 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 09:27:53.383866 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 09:27:53.387698 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 09:27:53.394249 1 5 16 | B1->B0 | 2626 2626 | 0 1 | (1 0) (1 0)
8368 09:27:53.397251 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 09:27:53.400927 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 09:27:53.407548 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 09:27:53.410780 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 09:27:53.414165 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 09:27:53.420791 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 09:27:53.424033 1 6 12 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
8375 09:27:53.427521 1 6 16 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
8376 09:27:53.434001 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 09:27:53.437551 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 09:27:53.440484 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 09:27:53.443905 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 09:27:53.450610 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 09:27:53.454429 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 09:27:53.457229 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 09:27:53.464218 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8384 09:27:53.467711 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 09:27:53.470513 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 09:27:53.477387 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 09:27:53.480531 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 09:27:53.483810 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 09:27:53.490637 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 09:27:53.493644 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 09:27:53.497224 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 09:27:53.503741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 09:27:53.507177 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 09:27:53.510155 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 09:27:53.517217 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 09:27:53.520136 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 09:27:53.523815 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 09:27:53.530098 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8399 09:27:53.533294 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 09:27:53.536959 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8401 09:27:53.540541 Total UI for P1: 0, mck2ui 16
8402 09:27:53.543462 best dqsien dly found for B0: ( 1, 9, 14)
8403 09:27:53.550269 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 09:27:53.550373 Total UI for P1: 0, mck2ui 16
8405 09:27:53.556869 best dqsien dly found for B1: ( 1, 9, 18)
8406 09:27:53.560012 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8407 09:27:53.563145 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8408 09:27:53.563221
8409 09:27:53.566834 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8410 09:27:53.569895 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8411 09:27:53.573427 [Gating] SW calibration Done
8412 09:27:53.573508 ==
8413 09:27:53.576839 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 09:27:53.580001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 09:27:53.580163 ==
8416 09:27:53.583236 RX Vref Scan: 0
8417 09:27:53.583332
8418 09:27:53.583422 RX Vref 0 -> 0, step: 1
8419 09:27:53.583485
8420 09:27:53.586858 RX Delay 0 -> 252, step: 8
8421 09:27:53.589859 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8422 09:27:53.596574 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8423 09:27:53.599807 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8424 09:27:53.603621 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8425 09:27:53.606730 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8426 09:27:53.609792 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 09:27:53.616751 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8428 09:27:53.619756 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8429 09:27:53.622974 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8430 09:27:53.626566 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8431 09:27:53.629729 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8432 09:27:53.636722 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8433 09:27:53.639808 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8434 09:27:53.642947 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8435 09:27:53.646510 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 09:27:53.649777 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8437 09:27:53.652973 ==
8438 09:27:53.653048 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 09:27:53.659821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 09:27:53.659914 ==
8441 09:27:53.660007 DQS Delay:
8442 09:27:53.662758 DQS0 = 0, DQS1 = 0
8443 09:27:53.662833 DQM Delay:
8444 09:27:53.666414 DQM0 = 131, DQM1 = 126
8445 09:27:53.666487 DQ Delay:
8446 09:27:53.669577 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8447 09:27:53.673007 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8448 09:27:53.676188 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8449 09:27:53.679590 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8450 09:27:53.679685
8451 09:27:53.679786
8452 09:27:53.679846 ==
8453 09:27:53.682887 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 09:27:53.689731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 09:27:53.689843 ==
8456 09:27:53.689935
8457 09:27:53.690030
8458 09:27:53.690115 TX Vref Scan disable
8459 09:27:53.693216 == TX Byte 0 ==
8460 09:27:53.696170 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8461 09:27:53.702724 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8462 09:27:53.702918 == TX Byte 1 ==
8463 09:27:53.706224 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8464 09:27:53.713242 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8465 09:27:53.713325 ==
8466 09:27:53.716131 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 09:27:53.719313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 09:27:53.719437 ==
8469 09:27:53.732981
8470 09:27:53.736089 TX Vref early break, caculate TX vref
8471 09:27:53.739534 TX Vref=16, minBit 5, minWin=21, winSum=361
8472 09:27:53.742758 TX Vref=18, minBit 9, minWin=22, winSum=372
8473 09:27:53.746347 TX Vref=20, minBit 11, minWin=22, winSum=382
8474 09:27:53.749397 TX Vref=22, minBit 12, minWin=23, winSum=392
8475 09:27:53.753305 TX Vref=24, minBit 10, minWin=24, winSum=406
8476 09:27:53.759320 TX Vref=26, minBit 0, minWin=25, winSum=413
8477 09:27:53.763058 TX Vref=28, minBit 0, minWin=25, winSum=417
8478 09:27:53.766101 TX Vref=30, minBit 6, minWin=24, winSum=413
8479 09:27:53.769334 TX Vref=32, minBit 0, minWin=24, winSum=403
8480 09:27:53.772770 TX Vref=34, minBit 0, minWin=23, winSum=396
8481 09:27:53.779219 TX Vref=36, minBit 1, minWin=22, winSum=379
8482 09:27:53.783027 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8483 09:27:53.783112
8484 09:27:53.785932 Final TX Range 0 Vref 28
8485 09:27:53.786015
8486 09:27:53.786079 ==
8487 09:27:53.789308 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 09:27:53.793077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 09:27:53.793160 ==
8490 09:27:53.795780
8491 09:27:53.795893
8492 09:27:53.795988 TX Vref Scan disable
8493 09:27:53.802412 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8494 09:27:53.802495 == TX Byte 0 ==
8495 09:27:53.806163 u2DelayCellOfst[0]=22 cells (6 PI)
8496 09:27:53.808987 u2DelayCellOfst[1]=15 cells (4 PI)
8497 09:27:53.812306 u2DelayCellOfst[2]=0 cells (0 PI)
8498 09:27:53.815890 u2DelayCellOfst[3]=3 cells (1 PI)
8499 09:27:53.819032 u2DelayCellOfst[4]=11 cells (3 PI)
8500 09:27:53.822611 u2DelayCellOfst[5]=26 cells (7 PI)
8501 09:27:53.825443 u2DelayCellOfst[6]=22 cells (6 PI)
8502 09:27:53.828783 u2DelayCellOfst[7]=7 cells (2 PI)
8503 09:27:53.832332 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8504 09:27:53.835880 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8505 09:27:53.838925 == TX Byte 1 ==
8506 09:27:53.842065 u2DelayCellOfst[8]=0 cells (0 PI)
8507 09:27:53.845647 u2DelayCellOfst[9]=11 cells (3 PI)
8508 09:27:53.848760 u2DelayCellOfst[10]=15 cells (4 PI)
8509 09:27:53.852154 u2DelayCellOfst[11]=11 cells (3 PI)
8510 09:27:53.855247 u2DelayCellOfst[12]=18 cells (5 PI)
8511 09:27:53.859085 u2DelayCellOfst[13]=22 cells (6 PI)
8512 09:27:53.862202 u2DelayCellOfst[14]=22 cells (6 PI)
8513 09:27:53.865171 u2DelayCellOfst[15]=22 cells (6 PI)
8514 09:27:53.868244 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8515 09:27:53.871988 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 09:27:53.875404 DramC Write-DBI on
8517 09:27:53.875495 ==
8518 09:27:53.878568 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 09:27:53.882141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 09:27:53.882251 ==
8521 09:27:53.882348
8522 09:27:53.882446
8523 09:27:53.885148 TX Vref Scan disable
8524 09:27:53.885251 == TX Byte 0 ==
8525 09:27:53.891781 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8526 09:27:53.891869 == TX Byte 1 ==
8527 09:27:53.895476 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8528 09:27:53.898501 DramC Write-DBI off
8529 09:27:53.898616
8530 09:27:53.898717 [DATLAT]
8531 09:27:53.902087 Freq=1600, CH1 RK0
8532 09:27:53.902197
8533 09:27:53.902290 DATLAT Default: 0xf
8534 09:27:53.905487 0, 0xFFFF, sum = 0
8535 09:27:53.905562 1, 0xFFFF, sum = 0
8536 09:27:53.908754 2, 0xFFFF, sum = 0
8537 09:27:53.908832 3, 0xFFFF, sum = 0
8538 09:27:53.911535 4, 0xFFFF, sum = 0
8539 09:27:53.915536 5, 0xFFFF, sum = 0
8540 09:27:53.915638 6, 0xFFFF, sum = 0
8541 09:27:53.918219 7, 0xFFFF, sum = 0
8542 09:27:53.918319 8, 0xFFFF, sum = 0
8543 09:27:53.921499 9, 0xFFFF, sum = 0
8544 09:27:53.921602 10, 0xFFFF, sum = 0
8545 09:27:53.925085 11, 0xFFFF, sum = 0
8546 09:27:53.925160 12, 0xFFFF, sum = 0
8547 09:27:53.928032 13, 0x8FFF, sum = 0
8548 09:27:53.928106 14, 0x0, sum = 1
8549 09:27:53.931334 15, 0x0, sum = 2
8550 09:27:53.931431 16, 0x0, sum = 3
8551 09:27:53.934724 17, 0x0, sum = 4
8552 09:27:53.934796 best_step = 15
8553 09:27:53.934866
8554 09:27:53.934926 ==
8555 09:27:53.938097 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 09:27:53.941667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 09:27:53.944774 ==
8558 09:27:53.944848 RX Vref Scan: 1
8559 09:27:53.944910
8560 09:27:53.947923 Set Vref Range= 24 -> 127
8561 09:27:53.948007
8562 09:27:53.951522 RX Vref 24 -> 127, step: 1
8563 09:27:53.951594
8564 09:27:53.951664 RX Delay 11 -> 252, step: 4
8565 09:27:53.951762
8566 09:27:53.954934 Set Vref, RX VrefLevel [Byte0]: 24
8567 09:27:53.958229 [Byte1]: 24
8568 09:27:53.961884
8569 09:27:53.961957 Set Vref, RX VrefLevel [Byte0]: 25
8570 09:27:53.964963 [Byte1]: 25
8571 09:27:53.969902
8572 09:27:53.969976 Set Vref, RX VrefLevel [Byte0]: 26
8573 09:27:53.972903 [Byte1]: 26
8574 09:27:53.977113
8575 09:27:53.977187 Set Vref, RX VrefLevel [Byte0]: 27
8576 09:27:53.980142 [Byte1]: 27
8577 09:27:53.985000
8578 09:27:53.985105 Set Vref, RX VrefLevel [Byte0]: 28
8579 09:27:53.987905 [Byte1]: 28
8580 09:27:53.992576
8581 09:27:53.992653 Set Vref, RX VrefLevel [Byte0]: 29
8582 09:27:53.995530 [Byte1]: 29
8583 09:27:53.999853
8584 09:27:53.999933 Set Vref, RX VrefLevel [Byte0]: 30
8585 09:27:54.003331 [Byte1]: 30
8586 09:27:54.007173
8587 09:27:54.007281 Set Vref, RX VrefLevel [Byte0]: 31
8588 09:27:54.010742 [Byte1]: 31
8589 09:27:54.014973
8590 09:27:54.015080 Set Vref, RX VrefLevel [Byte0]: 32
8591 09:27:54.018597 [Byte1]: 32
8592 09:27:54.022758
8593 09:27:54.022859 Set Vref, RX VrefLevel [Byte0]: 33
8594 09:27:54.025752 [Byte1]: 33
8595 09:27:54.030271
8596 09:27:54.030380 Set Vref, RX VrefLevel [Byte0]: 34
8597 09:27:54.033339 [Byte1]: 34
8598 09:27:54.038279
8599 09:27:54.038393 Set Vref, RX VrefLevel [Byte0]: 35
8600 09:27:54.041221 [Byte1]: 35
8601 09:27:54.045736
8602 09:27:54.045833 Set Vref, RX VrefLevel [Byte0]: 36
8603 09:27:54.049045 [Byte1]: 36
8604 09:27:54.053249
8605 09:27:54.053348 Set Vref, RX VrefLevel [Byte0]: 37
8606 09:27:54.056352 [Byte1]: 37
8607 09:27:54.060906
8608 09:27:54.060984 Set Vref, RX VrefLevel [Byte0]: 38
8609 09:27:54.063929 [Byte1]: 38
8610 09:27:54.068206
8611 09:27:54.068279 Set Vref, RX VrefLevel [Byte0]: 39
8612 09:27:54.071875 [Byte1]: 39
8613 09:27:54.076299
8614 09:27:54.076371 Set Vref, RX VrefLevel [Byte0]: 40
8615 09:27:54.079230 [Byte1]: 40
8616 09:27:54.083457
8617 09:27:54.083539 Set Vref, RX VrefLevel [Byte0]: 41
8618 09:27:54.087153 [Byte1]: 41
8619 09:27:54.091362
8620 09:27:54.091454 Set Vref, RX VrefLevel [Byte0]: 42
8621 09:27:54.094379 [Byte1]: 42
8622 09:27:54.098765
8623 09:27:54.098846 Set Vref, RX VrefLevel [Byte0]: 43
8624 09:27:54.102240 [Byte1]: 43
8625 09:27:54.106365
8626 09:27:54.106445 Set Vref, RX VrefLevel [Byte0]: 44
8627 09:27:54.109563 [Byte1]: 44
8628 09:27:54.114627
8629 09:27:54.114708 Set Vref, RX VrefLevel [Byte0]: 45
8630 09:27:54.117565 [Byte1]: 45
8631 09:27:54.121740
8632 09:27:54.121847 Set Vref, RX VrefLevel [Byte0]: 46
8633 09:27:54.124997 [Byte1]: 46
8634 09:27:54.129168
8635 09:27:54.129249 Set Vref, RX VrefLevel [Byte0]: 47
8636 09:27:54.132678 [Byte1]: 47
8637 09:27:54.136858
8638 09:27:54.136939 Set Vref, RX VrefLevel [Byte0]: 48
8639 09:27:54.140319 [Byte1]: 48
8640 09:27:54.144761
8641 09:27:54.144842 Set Vref, RX VrefLevel [Byte0]: 49
8642 09:27:54.147673 [Byte1]: 49
8643 09:27:54.151915
8644 09:27:54.151995 Set Vref, RX VrefLevel [Byte0]: 50
8645 09:27:54.155738 [Byte1]: 50
8646 09:27:54.159777
8647 09:27:54.159858 Set Vref, RX VrefLevel [Byte0]: 51
8648 09:27:54.163113 [Byte1]: 51
8649 09:27:54.167507
8650 09:27:54.167587 Set Vref, RX VrefLevel [Byte0]: 52
8651 09:27:54.170635 [Byte1]: 52
8652 09:27:54.174843
8653 09:27:54.174924 Set Vref, RX VrefLevel [Byte0]: 53
8654 09:27:54.178400 [Byte1]: 53
8655 09:27:54.182702
8656 09:27:54.182776 Set Vref, RX VrefLevel [Byte0]: 54
8657 09:27:54.185775 [Byte1]: 54
8658 09:27:54.189937
8659 09:27:54.190054 Set Vref, RX VrefLevel [Byte0]: 55
8660 09:27:54.193681 [Byte1]: 55
8661 09:27:54.197711
8662 09:27:54.197812 Set Vref, RX VrefLevel [Byte0]: 56
8663 09:27:54.201226 [Byte1]: 56
8664 09:27:54.205448
8665 09:27:54.205529 Set Vref, RX VrefLevel [Byte0]: 57
8666 09:27:54.208411 [Byte1]: 57
8667 09:27:54.213083
8668 09:27:54.213184 Set Vref, RX VrefLevel [Byte0]: 58
8669 09:27:54.216226 [Byte1]: 58
8670 09:27:54.220557
8671 09:27:54.220637 Set Vref, RX VrefLevel [Byte0]: 59
8672 09:27:54.224113 [Byte1]: 59
8673 09:27:54.228151
8674 09:27:54.228218 Set Vref, RX VrefLevel [Byte0]: 60
8675 09:27:54.231449 [Byte1]: 60
8676 09:27:54.235686
8677 09:27:54.235760 Set Vref, RX VrefLevel [Byte0]: 61
8678 09:27:54.239257 [Byte1]: 61
8679 09:27:54.243288
8680 09:27:54.243453 Set Vref, RX VrefLevel [Byte0]: 62
8681 09:27:54.246854 [Byte1]: 62
8682 09:27:54.251000
8683 09:27:54.251112 Set Vref, RX VrefLevel [Byte0]: 63
8684 09:27:54.254643 [Byte1]: 63
8685 09:27:54.258809
8686 09:27:54.258916 Set Vref, RX VrefLevel [Byte0]: 64
8687 09:27:54.261936 [Byte1]: 64
8688 09:27:54.266249
8689 09:27:54.266329 Set Vref, RX VrefLevel [Byte0]: 65
8690 09:27:54.269938 [Byte1]: 65
8691 09:27:54.274247
8692 09:27:54.274328 Set Vref, RX VrefLevel [Byte0]: 66
8693 09:27:54.277010 [Byte1]: 66
8694 09:27:54.281651
8695 09:27:54.281733 Set Vref, RX VrefLevel [Byte0]: 67
8696 09:27:54.284956 [Byte1]: 67
8697 09:27:54.289376
8698 09:27:54.289472 Set Vref, RX VrefLevel [Byte0]: 68
8699 09:27:54.292744 [Byte1]: 68
8700 09:27:54.297028
8701 09:27:54.297110 Set Vref, RX VrefLevel [Byte0]: 69
8702 09:27:54.299992 [Byte1]: 69
8703 09:27:54.304279
8704 09:27:54.304374 Set Vref, RX VrefLevel [Byte0]: 70
8705 09:27:54.307774 [Byte1]: 70
8706 09:27:54.311926
8707 09:27:54.312007 Set Vref, RX VrefLevel [Byte0]: 71
8708 09:27:54.315308 [Byte1]: 71
8709 09:27:54.319558
8710 09:27:54.319659 Final RX Vref Byte 0 = 57 to rank0
8711 09:27:54.323150 Final RX Vref Byte 1 = 57 to rank0
8712 09:27:54.326373 Final RX Vref Byte 0 = 57 to rank1
8713 09:27:54.329406 Final RX Vref Byte 1 = 57 to rank1==
8714 09:27:54.333030 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 09:27:54.339216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 09:27:54.339297 ==
8717 09:27:54.339362 DQS Delay:
8718 09:27:54.342747 DQS0 = 0, DQS1 = 0
8719 09:27:54.342828 DQM Delay:
8720 09:27:54.342892 DQM0 = 131, DQM1 = 123
8721 09:27:54.345998 DQ Delay:
8722 09:27:54.349463 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =128
8723 09:27:54.353031 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8724 09:27:54.355953 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8725 09:27:54.359794 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8726 09:27:54.359908
8727 09:27:54.360009
8728 09:27:54.360096
8729 09:27:54.362732 [DramC_TX_OE_Calibration] TA2
8730 09:27:54.365723 Original DQ_B0 (3 6) =30, OEN = 27
8731 09:27:54.369511 Original DQ_B1 (3 6) =30, OEN = 27
8732 09:27:54.372949 24, 0x0, End_B0=24 End_B1=24
8733 09:27:54.373030 25, 0x0, End_B0=25 End_B1=25
8734 09:27:54.375933 26, 0x0, End_B0=26 End_B1=26
8735 09:27:54.379039 27, 0x0, End_B0=27 End_B1=27
8736 09:27:54.382538 28, 0x0, End_B0=28 End_B1=28
8737 09:27:54.385878 29, 0x0, End_B0=29 End_B1=29
8738 09:27:54.385957 30, 0x0, End_B0=30 End_B1=30
8739 09:27:54.389156 31, 0x4141, End_B0=30 End_B1=30
8740 09:27:54.392029 Byte0 end_step=30 best_step=27
8741 09:27:54.395530 Byte1 end_step=30 best_step=27
8742 09:27:54.399013 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 09:27:54.401992 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 09:27:54.402075
8745 09:27:54.402139
8746 09:27:54.408855 [DQSOSCAuto] RK0, (LSB)MR18= 0xc10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
8747 09:27:54.412062 CH1 RK0: MR19=303, MR18=C10
8748 09:27:54.419170 CH1_RK0: MR19=0x303, MR18=0xC10, DQSOSC=401, MR23=63, INC=22, DEC=15
8749 09:27:54.419247
8750 09:27:54.421939 ----->DramcWriteLeveling(PI) begin...
8751 09:27:54.422013 ==
8752 09:27:54.425587 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 09:27:54.428580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 09:27:54.428648 ==
8755 09:27:54.432142 Write leveling (Byte 0): 26 => 26
8756 09:27:54.435350 Write leveling (Byte 1): 28 => 28
8757 09:27:54.438484 DramcWriteLeveling(PI) end<-----
8758 09:27:54.438554
8759 09:27:54.438614 ==
8760 09:27:54.442087 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 09:27:54.445169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 09:27:54.445267 ==
8763 09:27:54.448581 [Gating] SW mode calibration
8764 09:27:54.454983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 09:27:54.461952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 09:27:54.464930 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 09:27:54.471504 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 09:27:54.474893 1 4 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8769 09:27:54.478494 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
8770 09:27:54.484688 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 09:27:54.488157 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 09:27:54.491685 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 09:27:54.497897 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 09:27:54.501743 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 09:27:54.504645 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 09:27:54.511169 1 5 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
8777 09:27:54.514564 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8778 09:27:54.517656 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8779 09:27:54.524535 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 09:27:54.527608 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 09:27:54.530909 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 09:27:54.537968 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 09:27:54.541085 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8784 09:27:54.544761 1 6 8 | B1->B0 | 2423 4646 | 1 0 | (0 0) (0 0)
8785 09:27:54.550747 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8786 09:27:54.554174 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 09:27:54.557730 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 09:27:54.560710 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 09:27:54.567322 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 09:27:54.570773 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 09:27:54.574093 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 09:27:54.581188 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 09:27:54.584203 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8794 09:27:54.587275 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8795 09:27:54.593888 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 09:27:54.597613 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 09:27:54.600648 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 09:27:54.607476 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 09:27:54.610400 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 09:27:54.614141 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 09:27:54.620205 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 09:27:54.623983 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 09:27:54.627290 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 09:27:54.634069 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 09:27:54.637391 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 09:27:54.640533 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 09:27:54.647057 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8808 09:27:54.650486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8809 09:27:54.653564 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8810 09:27:54.657055 Total UI for P1: 0, mck2ui 16
8811 09:27:54.660112 best dqsien dly found for B0: ( 1, 9, 6)
8812 09:27:54.667089 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 09:27:54.670389 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 09:27:54.673485 Total UI for P1: 0, mck2ui 16
8815 09:27:54.676912 best dqsien dly found for B1: ( 1, 9, 12)
8816 09:27:54.679962 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8817 09:27:54.683269 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8818 09:27:54.683352
8819 09:27:54.686688 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8820 09:27:54.690293 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8821 09:27:54.693575 [Gating] SW calibration Done
8822 09:27:54.693656 ==
8823 09:27:54.696946 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 09:27:54.700001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 09:27:54.703690 ==
8826 09:27:54.703771 RX Vref Scan: 0
8827 09:27:54.703835
8828 09:27:54.706935 RX Vref 0 -> 0, step: 1
8829 09:27:54.707030
8830 09:27:54.707123 RX Delay 0 -> 252, step: 8
8831 09:27:54.713160 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8832 09:27:54.716872 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8833 09:27:54.719963 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8834 09:27:54.723600 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8835 09:27:54.726883 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8836 09:27:54.733392 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8837 09:27:54.736594 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8838 09:27:54.739634 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8839 09:27:54.743211 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8840 09:27:54.746205 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8841 09:27:54.753211 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8842 09:27:54.756255 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8843 09:27:54.759679 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8844 09:27:54.762960 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8845 09:27:54.769876 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8846 09:27:54.773022 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8847 09:27:54.773105 ==
8848 09:27:54.776836 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 09:27:54.779633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 09:27:54.779715 ==
8851 09:27:54.782991 DQS Delay:
8852 09:27:54.783072 DQS0 = 0, DQS1 = 0
8853 09:27:54.783138 DQM Delay:
8854 09:27:54.786215 DQM0 = 132, DQM1 = 129
8855 09:27:54.786336 DQ Delay:
8856 09:27:54.789850 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8857 09:27:54.792967 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8858 09:27:54.796417 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8859 09:27:54.802932 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8860 09:27:54.803022
8861 09:27:54.803086
8862 09:27:54.803146 ==
8863 09:27:54.806310 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 09:27:54.809539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 09:27:54.809622 ==
8866 09:27:54.809687
8867 09:27:54.809747
8868 09:27:54.812575 TX Vref Scan disable
8869 09:27:54.812657 == TX Byte 0 ==
8870 09:27:54.819748 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8871 09:27:54.822980 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8872 09:27:54.823064 == TX Byte 1 ==
8873 09:27:54.829693 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8874 09:27:54.832787 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8875 09:27:54.832869 ==
8876 09:27:54.836164 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 09:27:54.839321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 09:27:54.839442 ==
8879 09:27:54.854008
8880 09:27:54.857475 TX Vref early break, caculate TX vref
8881 09:27:54.860878 TX Vref=16, minBit 0, minWin=22, winSum=381
8882 09:27:54.864600 TX Vref=18, minBit 0, minWin=23, winSum=391
8883 09:27:54.867648 TX Vref=20, minBit 0, minWin=23, winSum=402
8884 09:27:54.871256 TX Vref=22, minBit 0, minWin=24, winSum=406
8885 09:27:54.874251 TX Vref=24, minBit 0, minWin=24, winSum=412
8886 09:27:54.881064 TX Vref=26, minBit 0, minWin=25, winSum=419
8887 09:27:54.884140 TX Vref=28, minBit 0, minWin=25, winSum=423
8888 09:27:54.887945 TX Vref=30, minBit 1, minWin=24, winSum=416
8889 09:27:54.890828 TX Vref=32, minBit 1, minWin=24, winSum=411
8890 09:27:54.894295 TX Vref=34, minBit 0, minWin=24, winSum=405
8891 09:27:54.897810 TX Vref=36, minBit 5, minWin=23, winSum=397
8892 09:27:54.904062 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8893 09:27:54.904144
8894 09:27:54.907599 Final TX Range 0 Vref 28
8895 09:27:54.907748
8896 09:27:54.907813 ==
8897 09:27:54.911165 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 09:27:54.914145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 09:27:54.914228 ==
8900 09:27:54.914293
8901 09:27:54.914352
8902 09:27:54.917539 TX Vref Scan disable
8903 09:27:54.924014 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8904 09:27:54.924097 == TX Byte 0 ==
8905 09:27:54.927199 u2DelayCellOfst[0]=18 cells (5 PI)
8906 09:27:54.930878 u2DelayCellOfst[1]=15 cells (4 PI)
8907 09:27:54.933950 u2DelayCellOfst[2]=0 cells (0 PI)
8908 09:27:54.936992 u2DelayCellOfst[3]=7 cells (2 PI)
8909 09:27:54.940352 u2DelayCellOfst[4]=11 cells (3 PI)
8910 09:27:54.944211 u2DelayCellOfst[5]=22 cells (6 PI)
8911 09:27:54.947086 u2DelayCellOfst[6]=22 cells (6 PI)
8912 09:27:54.950713 u2DelayCellOfst[7]=7 cells (2 PI)
8913 09:27:54.953850 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8914 09:27:54.956967 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8915 09:27:54.960657 == TX Byte 1 ==
8916 09:27:54.963544 u2DelayCellOfst[8]=0 cells (0 PI)
8917 09:27:54.966898 u2DelayCellOfst[9]=7 cells (2 PI)
8918 09:27:54.966983 u2DelayCellOfst[10]=11 cells (3 PI)
8919 09:27:54.970545 u2DelayCellOfst[11]=7 cells (2 PI)
8920 09:27:54.973763 u2DelayCellOfst[12]=18 cells (5 PI)
8921 09:27:54.976765 u2DelayCellOfst[13]=18 cells (5 PI)
8922 09:27:54.980310 u2DelayCellOfst[14]=22 cells (6 PI)
8923 09:27:54.983857 u2DelayCellOfst[15]=18 cells (5 PI)
8924 09:27:54.989954 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8925 09:27:54.993257 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8926 09:27:54.993338 DramC Write-DBI on
8927 09:27:54.993403 ==
8928 09:27:54.996767 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 09:27:55.003224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 09:27:55.003307 ==
8931 09:27:55.003372
8932 09:27:55.003447
8933 09:27:55.006817 TX Vref Scan disable
8934 09:27:55.006897 == TX Byte 0 ==
8935 09:27:55.013259 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8936 09:27:55.013342 == TX Byte 1 ==
8937 09:27:55.016777 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8938 09:27:55.019514 DramC Write-DBI off
8939 09:27:55.019614
8940 09:27:55.019709 [DATLAT]
8941 09:27:55.022838 Freq=1600, CH1 RK1
8942 09:27:55.022919
8943 09:27:55.022983 DATLAT Default: 0xf
8944 09:27:55.026253 0, 0xFFFF, sum = 0
8945 09:27:55.026336 1, 0xFFFF, sum = 0
8946 09:27:55.029410 2, 0xFFFF, sum = 0
8947 09:27:55.029492 3, 0xFFFF, sum = 0
8948 09:27:55.032977 4, 0xFFFF, sum = 0
8949 09:27:55.033060 5, 0xFFFF, sum = 0
8950 09:27:55.036404 6, 0xFFFF, sum = 0
8951 09:27:55.036486 7, 0xFFFF, sum = 0
8952 09:27:55.039529 8, 0xFFFF, sum = 0
8953 09:27:55.039613 9, 0xFFFF, sum = 0
8954 09:27:55.042710 10, 0xFFFF, sum = 0
8955 09:27:55.046227 11, 0xFFFF, sum = 0
8956 09:27:55.046310 12, 0xFFFF, sum = 0
8957 09:27:55.049798 13, 0x8FFF, sum = 0
8958 09:27:55.049881 14, 0x0, sum = 1
8959 09:27:55.052834 15, 0x0, sum = 2
8960 09:27:55.052917 16, 0x0, sum = 3
8961 09:27:55.056494 17, 0x0, sum = 4
8962 09:27:55.056577 best_step = 15
8963 09:27:55.056642
8964 09:27:55.056702 ==
8965 09:27:55.059519 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 09:27:55.062635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 09:27:55.062718 ==
8968 09:27:55.066359 RX Vref Scan: 0
8969 09:27:55.066441
8970 09:27:55.069194 RX Vref 0 -> 0, step: 1
8971 09:27:55.069276
8972 09:27:55.069341 RX Delay 11 -> 252, step: 4
8973 09:27:55.076394 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8974 09:27:55.079554 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8975 09:27:55.083152 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8976 09:27:55.086120 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8977 09:27:55.089639 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8978 09:27:55.096492 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8979 09:27:55.099515 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8980 09:27:55.103268 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8981 09:27:55.106264 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8982 09:27:55.109891 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8983 09:27:55.115798 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8984 09:27:55.119399 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8985 09:27:55.123020 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8986 09:27:55.125690 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8987 09:27:55.132460 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8988 09:27:55.136092 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8989 09:27:55.136175 ==
8990 09:27:55.139119 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 09:27:55.142393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 09:27:55.142475 ==
8993 09:27:55.145613 DQS Delay:
8994 09:27:55.145708 DQS0 = 0, DQS1 = 0
8995 09:27:55.145773 DQM Delay:
8996 09:27:55.148872 DQM0 = 130, DQM1 = 125
8997 09:27:55.148954 DQ Delay:
8998 09:27:55.152539 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
8999 09:27:55.155725 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =128
9000 09:27:55.159226 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9001 09:27:55.165712 DQ12 =134, DQ13 =134, DQ14 =130, DQ15 =136
9002 09:27:55.165794
9003 09:27:55.165859
9004 09:27:55.165920
9005 09:27:55.168926 [DramC_TX_OE_Calibration] TA2
9006 09:27:55.172178 Original DQ_B0 (3 6) =30, OEN = 27
9007 09:27:55.172260 Original DQ_B1 (3 6) =30, OEN = 27
9008 09:27:55.175799 24, 0x0, End_B0=24 End_B1=24
9009 09:27:55.179254 25, 0x0, End_B0=25 End_B1=25
9010 09:27:55.182273 26, 0x0, End_B0=26 End_B1=26
9011 09:27:55.185301 27, 0x0, End_B0=27 End_B1=27
9012 09:27:55.185384 28, 0x0, End_B0=28 End_B1=28
9013 09:27:55.189021 29, 0x0, End_B0=29 End_B1=29
9014 09:27:55.191933 30, 0x0, End_B0=30 End_B1=30
9015 09:27:55.195624 31, 0x5151, End_B0=30 End_B1=30
9016 09:27:55.198903 Byte0 end_step=30 best_step=27
9017 09:27:55.201907 Byte1 end_step=30 best_step=27
9018 09:27:55.201989 Byte0 TX OE(2T, 0.5T) = (3, 3)
9019 09:27:55.205538 Byte1 TX OE(2T, 0.5T) = (3, 3)
9020 09:27:55.205620
9021 09:27:55.205685
9022 09:27:55.215274 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9023 09:27:55.218733 CH1 RK1: MR19=303, MR18=101C
9024 09:27:55.221729 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9025 09:27:55.225102 [RxdqsGatingPostProcess] freq 1600
9026 09:27:55.231838 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9027 09:27:55.235594 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 09:27:55.238523 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 09:27:55.241586 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 09:27:55.245446 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 09:27:55.248290 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 09:27:55.248373 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 09:27:55.251929 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 09:27:55.254713 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 09:27:55.258136 Pre-setting of DQS Precalculation
9036 09:27:55.264907 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9037 09:27:55.271650 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9038 09:27:55.278000 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9039 09:27:55.278082
9040 09:27:55.278187
9041 09:27:55.281551 [Calibration Summary] 3200 Mbps
9042 09:27:55.285016 CH 0, Rank 0
9043 09:27:55.285097 SW Impedance : PASS
9044 09:27:55.287835 DUTY Scan : NO K
9045 09:27:55.287917 ZQ Calibration : PASS
9046 09:27:55.291425 Jitter Meter : NO K
9047 09:27:55.295033 CBT Training : PASS
9048 09:27:55.295133 Write leveling : PASS
9049 09:27:55.297925 RX DQS gating : PASS
9050 09:27:55.301563 RX DQ/DQS(RDDQC) : PASS
9051 09:27:55.301645 TX DQ/DQS : PASS
9052 09:27:55.304827 RX DATLAT : PASS
9053 09:27:55.307639 RX DQ/DQS(Engine): PASS
9054 09:27:55.307721 TX OE : PASS
9055 09:27:55.311285 All Pass.
9056 09:27:55.311367
9057 09:27:55.311480 CH 0, Rank 1
9058 09:27:55.314331 SW Impedance : PASS
9059 09:27:55.314413 DUTY Scan : NO K
9060 09:27:55.317992 ZQ Calibration : PASS
9061 09:27:55.320926 Jitter Meter : NO K
9062 09:27:55.321008 CBT Training : PASS
9063 09:27:55.324719 Write leveling : PASS
9064 09:27:55.327948 RX DQS gating : PASS
9065 09:27:55.328029 RX DQ/DQS(RDDQC) : PASS
9066 09:27:55.331015 TX DQ/DQS : PASS
9067 09:27:55.334440 RX DATLAT : PASS
9068 09:27:55.334521 RX DQ/DQS(Engine): PASS
9069 09:27:55.337754 TX OE : PASS
9070 09:27:55.337836 All Pass.
9071 09:27:55.337900
9072 09:27:55.340861 CH 1, Rank 0
9073 09:27:55.340942 SW Impedance : PASS
9074 09:27:55.344683 DUTY Scan : NO K
9075 09:27:55.347614 ZQ Calibration : PASS
9076 09:27:55.347696 Jitter Meter : NO K
9077 09:27:55.350760 CBT Training : PASS
9078 09:27:55.350841 Write leveling : PASS
9079 09:27:55.354288 RX DQS gating : PASS
9080 09:27:55.357356 RX DQ/DQS(RDDQC) : PASS
9081 09:27:55.357454 TX DQ/DQS : PASS
9082 09:27:55.360805 RX DATLAT : PASS
9083 09:27:55.363865 RX DQ/DQS(Engine): PASS
9084 09:27:55.363947 TX OE : PASS
9085 09:27:55.367278 All Pass.
9086 09:27:55.367362
9087 09:27:55.367450 CH 1, Rank 1
9088 09:27:55.371062 SW Impedance : PASS
9089 09:27:55.371144 DUTY Scan : NO K
9090 09:27:55.374134 ZQ Calibration : PASS
9091 09:27:55.377563 Jitter Meter : NO K
9092 09:27:55.377645 CBT Training : PASS
9093 09:27:55.380627 Write leveling : PASS
9094 09:27:55.383904 RX DQS gating : PASS
9095 09:27:55.383986 RX DQ/DQS(RDDQC) : PASS
9096 09:27:55.387285 TX DQ/DQS : PASS
9097 09:27:55.390508 RX DATLAT : PASS
9098 09:27:55.390597 RX DQ/DQS(Engine): PASS
9099 09:27:55.393744 TX OE : PASS
9100 09:27:55.393826 All Pass.
9101 09:27:55.393890
9102 09:27:55.397360 DramC Write-DBI on
9103 09:27:55.400604 PER_BANK_REFRESH: Hybrid Mode
9104 09:27:55.400704 TX_TRACKING: ON
9105 09:27:55.410332 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9106 09:27:55.416911 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9107 09:27:55.423299 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9108 09:27:55.427207 [FAST_K] Save calibration result to emmc
9109 09:27:55.430251 sync common calibartion params.
9110 09:27:55.433391 sync cbt_mode0:1, 1:1
9111 09:27:55.436959 dram_init: ddr_geometry: 2
9112 09:27:55.437040 dram_init: ddr_geometry: 2
9113 09:27:55.440070 dram_init: ddr_geometry: 2
9114 09:27:55.443369 0:dram_rank_size:100000000
9115 09:27:55.447102 1:dram_rank_size:100000000
9116 09:27:55.450116 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9117 09:27:55.453923 DFS_SHUFFLE_HW_MODE: ON
9118 09:27:55.456933 dramc_set_vcore_voltage set vcore to 725000
9119 09:27:55.460140 Read voltage for 1600, 0
9120 09:27:55.460222 Vio18 = 0
9121 09:27:55.460286 Vcore = 725000
9122 09:27:55.463815 Vdram = 0
9123 09:27:55.463897 Vddq = 0
9124 09:27:55.463961 Vmddr = 0
9125 09:27:55.466749 switch to 3200 Mbps bootup
9126 09:27:55.470174 [DramcRunTimeConfig]
9127 09:27:55.470256 PHYPLL
9128 09:27:55.470320 DPM_CONTROL_AFTERK: ON
9129 09:27:55.473595 PER_BANK_REFRESH: ON
9130 09:27:55.476943 REFRESH_OVERHEAD_REDUCTION: ON
9131 09:27:55.477024 CMD_PICG_NEW_MODE: OFF
9132 09:27:55.480085 XRTWTW_NEW_MODE: ON
9133 09:27:55.480167 XRTRTR_NEW_MODE: ON
9134 09:27:55.483023 TX_TRACKING: ON
9135 09:27:55.483121 RDSEL_TRACKING: OFF
9136 09:27:55.486849 DQS Precalculation for DVFS: ON
9137 09:27:55.489638 RX_TRACKING: OFF
9138 09:27:55.489720 HW_GATING DBG: ON
9139 09:27:55.493186 ZQCS_ENABLE_LP4: ON
9140 09:27:55.493267 RX_PICG_NEW_MODE: ON
9141 09:27:55.496248 TX_PICG_NEW_MODE: ON
9142 09:27:55.499559 ENABLE_RX_DCM_DPHY: ON
9143 09:27:55.503458 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9144 09:27:55.503557 DUMMY_READ_FOR_TRACKING: OFF
9145 09:27:55.506465 !!! SPM_CONTROL_AFTERK: OFF
9146 09:27:55.509922 !!! SPM could not control APHY
9147 09:27:55.513215 IMPEDANCE_TRACKING: ON
9148 09:27:55.513296 TEMP_SENSOR: ON
9149 09:27:55.516361 HW_SAVE_FOR_SR: OFF
9150 09:27:55.516456 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9151 09:27:55.523363 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9152 09:27:55.523501 Read ODT Tracking: ON
9153 09:27:55.526374 Refresh Rate DeBounce: ON
9154 09:27:55.526490 DFS_NO_QUEUE_FLUSH: ON
9155 09:27:55.529574 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9156 09:27:55.533175 ENABLE_DFS_RUNTIME_MRW: OFF
9157 09:27:55.536303 DDR_RESERVE_NEW_MODE: ON
9158 09:27:55.536385 MR_CBT_SWITCH_FREQ: ON
9159 09:27:55.539370 =========================
9160 09:27:55.559132 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9161 09:27:55.562132 dram_init: ddr_geometry: 2
9162 09:27:55.580398 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9163 09:27:55.583796 dram_init: dram init end (result: 0)
9164 09:27:55.590301 DRAM-K: Full calibration passed in 24584 msecs
9165 09:27:55.593928 MRC: failed to locate region type 0.
9166 09:27:55.594010 DRAM rank0 size:0x100000000,
9167 09:27:55.597014 DRAM rank1 size=0x100000000
9168 09:27:55.607358 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9169 09:27:55.614354 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9170 09:27:55.620264 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9171 09:27:55.627339 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9172 09:27:55.630161 DRAM rank0 size:0x100000000,
9173 09:27:55.633389 DRAM rank1 size=0x100000000
9174 09:27:55.633470 CBMEM:
9175 09:27:55.636718 IMD: root @ 0xfffff000 254 entries.
9176 09:27:55.640434 IMD: root @ 0xffffec00 62 entries.
9177 09:27:55.643334 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9178 09:27:55.646781 WARNING: RO_VPD is uninitialized or empty.
9179 09:27:55.653191 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9180 09:27:55.660752 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9181 09:27:55.673532 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9182 09:27:55.684829 BS: romstage times (exec / console): total (unknown) / 24050 ms
9183 09:27:55.684912
9184 09:27:55.685008
9185 09:27:55.694618 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9186 09:27:55.698203 ARM64: Exception handlers installed.
9187 09:27:55.701422 ARM64: Testing exception
9188 09:27:55.704435 ARM64: Done test exception
9189 09:27:55.704517 Enumerating buses...
9190 09:27:55.707940 Show all devs... Before device enumeration.
9191 09:27:55.711721 Root Device: enabled 1
9192 09:27:55.714604 CPU_CLUSTER: 0: enabled 1
9193 09:27:55.714705 CPU: 00: enabled 1
9194 09:27:55.718004 Compare with tree...
9195 09:27:55.718091 Root Device: enabled 1
9196 09:27:55.721091 CPU_CLUSTER: 0: enabled 1
9197 09:27:55.724748 CPU: 00: enabled 1
9198 09:27:55.724854 Root Device scanning...
9199 09:27:55.727730 scan_static_bus for Root Device
9200 09:27:55.731211 CPU_CLUSTER: 0 enabled
9201 09:27:55.734735 scan_static_bus for Root Device done
9202 09:27:55.737953 scan_bus: bus Root Device finished in 8 msecs
9203 09:27:55.738037 done
9204 09:27:55.744577 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9205 09:27:55.747512 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9206 09:27:55.754248 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9207 09:27:55.757820 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9208 09:27:55.760941 Allocating resources...
9209 09:27:55.764260 Reading resources...
9210 09:27:55.767528 Root Device read_resources bus 0 link: 0
9211 09:27:55.767611 DRAM rank0 size:0x100000000,
9212 09:27:55.771168 DRAM rank1 size=0x100000000
9213 09:27:55.774318 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9214 09:27:55.777969 CPU: 00 missing read_resources
9215 09:27:55.781052 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9216 09:27:55.787751 Root Device read_resources bus 0 link: 0 done
9217 09:27:55.787871 Done reading resources.
9218 09:27:55.794363 Show resources in subtree (Root Device)...After reading.
9219 09:27:55.797339 Root Device child on link 0 CPU_CLUSTER: 0
9220 09:27:55.800641 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 09:27:55.810783 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 09:27:55.810896 CPU: 00
9223 09:27:55.814335 Root Device assign_resources, bus 0 link: 0
9224 09:27:55.817454 CPU_CLUSTER: 0 missing set_resources
9225 09:27:55.824222 Root Device assign_resources, bus 0 link: 0 done
9226 09:27:55.824331 Done setting resources.
9227 09:27:55.830772 Show resources in subtree (Root Device)...After assigning values.
9228 09:27:55.833878 Root Device child on link 0 CPU_CLUSTER: 0
9229 09:27:55.837489 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 09:27:55.847225 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 09:27:55.847331 CPU: 00
9232 09:27:55.850639 Done allocating resources.
9233 09:27:55.854229 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9234 09:27:55.857233 Enabling resources...
9235 09:27:55.857334 done.
9236 09:27:55.864354 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9237 09:27:55.864457 Initializing devices...
9238 09:27:55.867749 Root Device init
9239 09:27:55.867866 init hardware done!
9240 09:27:55.870420 0x00000018: ctrlr->caps
9241 09:27:55.873866 52.000 MHz: ctrlr->f_max
9242 09:27:55.873968 0.400 MHz: ctrlr->f_min
9243 09:27:55.877544 0x40ff8080: ctrlr->voltages
9244 09:27:55.877626 sclk: 390625
9245 09:27:55.880671 Bus Width = 1
9246 09:27:55.880751 sclk: 390625
9247 09:27:55.883621 Bus Width = 1
9248 09:27:55.883701 Early init status = 3
9249 09:27:55.890878 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9250 09:27:55.893805 in-header: 03 fc 00 00 01 00 00 00
9251 09:27:55.893886 in-data: 00
9252 09:27:55.900947 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9253 09:27:55.903982 in-header: 03 fd 00 00 00 00 00 00
9254 09:27:55.907298 in-data:
9255 09:27:55.910134 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9256 09:27:55.913591 in-header: 03 fc 00 00 01 00 00 00
9257 09:27:55.917442 in-data: 00
9258 09:27:55.920394 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9259 09:27:55.925738 in-header: 03 fd 00 00 00 00 00 00
9260 09:27:55.929082 in-data:
9261 09:27:55.932588 [SSUSB] Setting up USB HOST controller...
9262 09:27:55.936060 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9263 09:27:55.939014 [SSUSB] phy power-on done.
9264 09:27:55.942019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9265 09:27:55.948634 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9266 09:27:55.952197 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9267 09:27:55.958587 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9268 09:27:55.965296 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9269 09:27:55.971800 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9270 09:27:55.978478 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9271 09:27:55.985454 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9272 09:27:55.988541 SPM: binary array size = 0x9dc
9273 09:27:55.992150 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9274 09:27:55.998308 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9275 09:27:56.005443 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9276 09:27:56.011719 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9277 09:27:56.015158 configure_display: Starting display init
9278 09:27:56.048991 anx7625_power_on_init: Init interface.
9279 09:27:56.052046 anx7625_disable_pd_protocol: Disabled PD feature.
9280 09:27:56.055407 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9281 09:27:56.083315 anx7625_start_dp_work: Secure OCM version=00
9282 09:27:56.086397 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9283 09:27:56.101492 sp_tx_get_edid_block: EDID Block = 1
9284 09:27:56.204030 Extracted contents:
9285 09:27:56.207093 header: 00 ff ff ff ff ff ff 00
9286 09:27:56.210540 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9287 09:27:56.213759 version: 01 04
9288 09:27:56.217495 basic params: 95 1f 11 78 0a
9289 09:27:56.220548 chroma info: 76 90 94 55 54 90 27 21 50 54
9290 09:27:56.224127 established: 00 00 00
9291 09:27:56.230408 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9292 09:27:56.234102 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9293 09:27:56.240116 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9294 09:27:56.246801 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9295 09:27:56.253813 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9296 09:27:56.257147 extensions: 00
9297 09:27:56.257279 checksum: fb
9298 09:27:56.257408
9299 09:27:56.260478 Manufacturer: IVO Model 57d Serial Number 0
9300 09:27:56.263287 Made week 0 of 2020
9301 09:27:56.263396 EDID version: 1.4
9302 09:27:56.266873 Digital display
9303 09:27:56.270304 6 bits per primary color channel
9304 09:27:56.270413 DisplayPort interface
9305 09:27:56.273350 Maximum image size: 31 cm x 17 cm
9306 09:27:56.277023 Gamma: 220%
9307 09:27:56.277125 Check DPMS levels
9308 09:27:56.280165 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9309 09:27:56.286769 First detailed timing is preferred timing
9310 09:27:56.286873 Established timings supported:
9311 09:27:56.290347 Standard timings supported:
9312 09:27:56.293132 Detailed timings
9313 09:27:56.296616 Hex of detail: 383680a07038204018303c0035ae10000019
9314 09:27:56.300326 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9315 09:27:56.306763 0780 0798 07c8 0820 hborder 0
9316 09:27:56.310197 0438 043b 0447 0458 vborder 0
9317 09:27:56.313411 -hsync -vsync
9318 09:27:56.313509 Did detailed timing
9319 09:27:56.319766 Hex of detail: 000000000000000000000000000000000000
9320 09:27:56.323006 Manufacturer-specified data, tag 0
9321 09:27:56.326720 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9322 09:27:56.329623 ASCII string: InfoVision
9323 09:27:56.333215 Hex of detail: 000000fe00523134304e574635205248200a
9324 09:27:56.336035 ASCII string: R140NWF5 RH
9325 09:27:56.336157 Checksum
9326 09:27:56.339582 Checksum: 0xfb (valid)
9327 09:27:56.343030 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9328 09:27:56.345968 DSI data_rate: 832800000 bps
9329 09:27:56.352919 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9330 09:27:56.356631 anx7625_parse_edid: pixelclock(138800).
9331 09:27:56.359604 hactive(1920), hsync(48), hfp(24), hbp(88)
9332 09:27:56.363148 vactive(1080), vsync(12), vfp(3), vbp(17)
9333 09:27:56.366341 anx7625_dsi_config: config dsi.
9334 09:27:56.372658 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9335 09:27:56.385786 anx7625_dsi_config: success to config DSI
9336 09:27:56.389453 anx7625_dp_start: MIPI phy setup OK.
9337 09:27:56.392613 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9338 09:27:56.396149 mtk_ddp_mode_set invalid vrefresh 60
9339 09:27:56.399650 main_disp_path_setup
9340 09:27:56.399759 ovl_layer_smi_id_en
9341 09:27:56.402366 ovl_layer_smi_id_en
9342 09:27:56.402461 ccorr_config
9343 09:27:56.402533 aal_config
9344 09:27:56.405792 gamma_config
9345 09:27:56.405893 postmask_config
9346 09:27:56.409440 dither_config
9347 09:27:56.412486 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9348 09:27:56.419351 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9349 09:27:56.422529 Root Device init finished in 552 msecs
9350 09:27:56.426002 CPU_CLUSTER: 0 init
9351 09:27:56.432728 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9352 09:27:56.435626 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9353 09:27:56.439224 APU_MBOX 0x190000b0 = 0x10001
9354 09:27:56.442043 APU_MBOX 0x190001b0 = 0x10001
9355 09:27:56.445889 APU_MBOX 0x190005b0 = 0x10001
9356 09:27:56.448670 APU_MBOX 0x190006b0 = 0x10001
9357 09:27:56.452155 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9358 09:27:56.465031 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9359 09:27:56.477202 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9360 09:27:56.483916 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9361 09:27:56.495690 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9362 09:27:56.504741 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9363 09:27:56.508216 CPU_CLUSTER: 0 init finished in 81 msecs
9364 09:27:56.511323 Devices initialized
9365 09:27:56.514933 Show all devs... After init.
9366 09:27:56.515037 Root Device: enabled 1
9367 09:27:56.518420 CPU_CLUSTER: 0: enabled 1
9368 09:27:56.520991 CPU: 00: enabled 1
9369 09:27:56.524383 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9370 09:27:56.527995 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9371 09:27:56.531112 ELOG: NV offset 0x57f000 size 0x1000
9372 09:27:56.538022 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9373 09:27:56.544522 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9374 09:27:56.547524 ELOG: Event(17) added with size 13 at 2023-10-20 09:27:57 UTC
9375 09:27:56.554242 out: cmd=0x121: 03 db 21 01 00 00 00 00
9376 09:27:56.557764 in-header: 03 51 00 00 2c 00 00 00
9377 09:27:56.567539 in-data: 0d 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9378 09:27:56.574160 ELOG: Event(A1) added with size 10 at 2023-10-20 09:27:57 UTC
9379 09:27:56.581292 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9380 09:27:56.587816 ELOG: Event(A0) added with size 9 at 2023-10-20 09:27:57 UTC
9381 09:27:56.590729 elog_add_boot_reason: Logged dev mode boot
9382 09:27:56.594620 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9383 09:27:56.597382 Finalize devices...
9384 09:27:56.600873 Devices finalized
9385 09:27:56.604256 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9386 09:27:56.607725 Writing coreboot table at 0xffe64000
9387 09:27:56.610908 0. 000000000010a000-0000000000113fff: RAMSTAGE
9388 09:27:56.614391 1. 0000000040000000-00000000400fffff: RAM
9389 09:27:56.620633 2. 0000000040100000-000000004032afff: RAMSTAGE
9390 09:27:56.624352 3. 000000004032b000-00000000545fffff: RAM
9391 09:27:56.627312 4. 0000000054600000-000000005465ffff: BL31
9392 09:27:56.630990 5. 0000000054660000-00000000ffe63fff: RAM
9393 09:27:56.637504 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9394 09:27:56.640655 7. 0000000100000000-000000023fffffff: RAM
9395 09:27:56.643827 Passing 5 GPIOs to payload:
9396 09:27:56.647195 NAME | PORT | POLARITY | VALUE
9397 09:27:56.650784 EC in RW | 0x000000aa | low | undefined
9398 09:27:56.657677 EC interrupt | 0x00000005 | low | undefined
9399 09:27:56.660640 TPM interrupt | 0x000000ab | high | undefined
9400 09:27:56.667014 SD card detect | 0x00000011 | high | undefined
9401 09:27:56.670729 speaker enable | 0x00000093 | high | undefined
9402 09:27:56.673847 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9403 09:27:56.676921 in-header: 03 f9 00 00 02 00 00 00
9404 09:27:56.680423 in-data: 02 00
9405 09:27:56.680524 ADC[4]: Raw value=893711 ID=7
9406 09:27:56.683882 ADC[3]: Raw value=212700 ID=1
9407 09:27:56.686861 RAM Code: 0x71
9408 09:27:56.686965 ADC[6]: Raw value=74722 ID=0
9409 09:27:56.690557 ADC[5]: Raw value=211590 ID=1
9410 09:27:56.693411 SKU Code: 0x1
9411 09:27:56.696922 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 357f
9412 09:27:56.700482 coreboot table: 964 bytes.
9413 09:27:56.703382 IMD ROOT 0. 0xfffff000 0x00001000
9414 09:27:56.706737 IMD SMALL 1. 0xffffe000 0x00001000
9415 09:27:56.710305 RO MCACHE 2. 0xffffc000 0x00001104
9416 09:27:56.713277 CONSOLE 3. 0xfff7c000 0x00080000
9417 09:27:56.717175 FMAP 4. 0xfff7b000 0x00000452
9418 09:27:56.720083 TIME STAMP 5. 0xfff7a000 0x00000910
9419 09:27:56.723217 VBOOT WORK 6. 0xfff66000 0x00014000
9420 09:27:56.726744 RAMOOPS 7. 0xffe66000 0x00100000
9421 09:27:56.730219 COREBOOT 8. 0xffe64000 0x00002000
9422 09:27:56.733224 IMD small region:
9423 09:27:56.736426 IMD ROOT 0. 0xffffec00 0x00000400
9424 09:27:56.739995 VPD 1. 0xffffeb80 0x0000006c
9425 09:27:56.743214 MMC STATUS 2. 0xffffeb60 0x00000004
9426 09:27:56.746484 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9427 09:27:56.750098 Probing TPM: done!
9428 09:27:56.753556 Connected to device vid:did:rid of 1ae0:0028:00
9429 09:27:56.763514 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9430 09:27:56.767152 Initialized TPM device CR50 revision 0
9431 09:27:56.770538 Checking cr50 for pending updates
9432 09:27:56.774202 Reading cr50 TPM mode
9433 09:27:56.782786 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9434 09:27:56.789520 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9435 09:27:56.830031 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9436 09:27:56.832911 Checking segment from ROM address 0x40100000
9437 09:27:56.836406 Checking segment from ROM address 0x4010001c
9438 09:27:56.843091 Loading segment from ROM address 0x40100000
9439 09:27:56.843192 code (compression=0)
9440 09:27:56.853088 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9441 09:27:56.859366 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9442 09:27:56.859475 it's not compressed!
9443 09:27:56.866142 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9444 09:27:56.872733 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9445 09:27:56.890132 Loading segment from ROM address 0x4010001c
9446 09:27:56.890255 Entry Point 0x80000000
9447 09:27:56.893633 Loaded segments
9448 09:27:56.897053 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9449 09:27:56.903701 Jumping to boot code at 0x80000000(0xffe64000)
9450 09:27:56.910439 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9451 09:27:56.917173 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9452 09:27:56.924869 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9453 09:27:56.927897 Checking segment from ROM address 0x40100000
9454 09:27:56.931323 Checking segment from ROM address 0x4010001c
9455 09:27:56.937971 Loading segment from ROM address 0x40100000
9456 09:27:56.938053 code (compression=1)
9457 09:27:56.944547 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9458 09:27:56.954883 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9459 09:27:56.954965 using LZMA
9460 09:27:56.962801 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9461 09:27:56.969748 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9462 09:27:56.972902 Loading segment from ROM address 0x4010001c
9463 09:27:56.972983 Entry Point 0x54601000
9464 09:27:56.976396 Loaded segments
9465 09:27:56.979380 NOTICE: MT8192 bl31_setup
9466 09:27:56.987128 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9467 09:27:56.989939 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9468 09:27:56.993341 WARNING: region 0:
9469 09:27:56.996929 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 09:27:56.997052 WARNING: region 1:
9471 09:27:57.003337 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9472 09:27:57.006310 WARNING: region 2:
9473 09:27:57.009899 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9474 09:27:57.013524 WARNING: region 3:
9475 09:27:57.016550 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 09:27:57.019796 WARNING: region 4:
9477 09:27:57.026456 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 09:27:57.026586 WARNING: region 5:
9479 09:27:57.029598 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 09:27:57.033089 WARNING: region 6:
9481 09:27:57.036415 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 09:27:57.040233 WARNING: region 7:
9483 09:27:57.043141 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 09:27:57.049500 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9485 09:27:57.052745 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9486 09:27:57.056648 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9487 09:27:57.062861 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9488 09:27:57.066282 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9489 09:27:57.069740 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9490 09:27:57.076255 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9491 09:27:57.079277 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9492 09:27:57.086045 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9493 09:27:57.089610 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9494 09:27:57.092863 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9495 09:27:57.099593 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9496 09:27:57.103011 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9497 09:27:57.106204 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9498 09:27:57.113177 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9499 09:27:57.116840 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9500 09:27:57.123290 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9501 09:27:57.126525 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9502 09:27:57.130025 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9503 09:27:57.136647 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9504 09:27:57.140077 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9505 09:27:57.142956 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9506 09:27:57.150116 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9507 09:27:57.153262 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9508 09:27:57.160096 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9509 09:27:57.162844 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9510 09:27:57.166362 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9511 09:27:57.173196 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9512 09:27:57.176369 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9513 09:27:57.183715 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9514 09:27:57.186600 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9515 09:27:57.190235 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9516 09:27:57.196410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9517 09:27:57.199964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9518 09:27:57.203368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9519 09:27:57.206393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9520 09:27:57.213131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9521 09:27:57.216741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9522 09:27:57.219962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9523 09:27:57.223312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9524 09:27:57.226404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9525 09:27:57.233020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9526 09:27:57.236910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9527 09:27:57.239805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9528 09:27:57.246866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9529 09:27:57.250125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9530 09:27:57.253479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9531 09:27:57.256382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9532 09:27:57.263546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9533 09:27:57.266692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9534 09:27:57.273354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9535 09:27:57.276605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9536 09:27:57.279859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9537 09:27:57.286701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9538 09:27:57.290173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9539 09:27:57.296919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9540 09:27:57.299990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9541 09:27:57.306477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9542 09:27:57.310130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9543 09:27:57.313394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9544 09:27:57.320009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9545 09:27:57.323507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9546 09:27:57.330637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9547 09:27:57.333682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9548 09:27:57.340323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9549 09:27:57.343327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9550 09:27:57.346623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9551 09:27:57.353412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9552 09:27:57.356830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9553 09:27:57.363227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9554 09:27:57.366878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9555 09:27:57.373345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9556 09:27:57.376861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9557 09:27:57.380136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9558 09:27:57.386791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9559 09:27:57.390273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9560 09:27:57.396948 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9561 09:27:57.400087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9562 09:27:57.406637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9563 09:27:57.410160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9564 09:27:57.413755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9565 09:27:57.419877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9566 09:27:57.423562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9567 09:27:57.430261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9568 09:27:57.433789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9569 09:27:57.440208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9570 09:27:57.443336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9571 09:27:57.446708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9572 09:27:57.453688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9573 09:27:57.457032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9574 09:27:57.463330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9575 09:27:57.466930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9576 09:27:57.473576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9577 09:27:57.476783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9578 09:27:57.483071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9579 09:27:57.486745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9580 09:27:57.490307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9581 09:27:57.493135 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9582 09:27:57.500061 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9583 09:27:57.503042 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9584 09:27:57.506817 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9585 09:27:57.513265 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9586 09:27:57.517053 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9587 09:27:57.519858 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9588 09:27:57.526733 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9589 09:27:57.530123 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9590 09:27:57.536716 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9591 09:27:57.540174 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9592 09:27:57.543108 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9593 09:27:57.550150 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9594 09:27:57.553352 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9595 09:27:57.560174 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9596 09:27:57.563517 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9597 09:27:57.566507 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9598 09:27:57.573436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9599 09:27:57.576437 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9600 09:27:57.579960 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9601 09:27:57.586794 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9602 09:27:57.590172 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9603 09:27:57.593254 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9604 09:27:57.596534 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9605 09:27:57.603307 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9606 09:27:57.606576 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9607 09:27:57.609793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9608 09:27:57.616702 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9609 09:27:57.619897 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9610 09:27:57.623712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9611 09:27:57.630059 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9612 09:27:57.633297 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9613 09:27:57.640346 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9614 09:27:57.643301 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9615 09:27:57.646813 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9616 09:27:57.654114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9617 09:27:57.656909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9618 09:27:57.660071 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9619 09:27:57.667078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9620 09:27:57.669974 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9621 09:27:57.677091 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9622 09:27:57.680483 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9623 09:27:57.683832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9624 09:27:57.690716 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9625 09:27:57.693766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9626 09:27:57.700319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9627 09:27:57.703665 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9628 09:27:57.707034 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9629 09:27:57.713199 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9630 09:27:57.716730 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9631 09:27:57.720069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9632 09:27:57.726699 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9633 09:27:57.729998 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9634 09:27:57.736881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9635 09:27:57.740020 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9636 09:27:57.743308 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9637 09:27:57.749908 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9638 09:27:57.753416 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9639 09:27:57.759879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9640 09:27:57.763638 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9641 09:27:57.766621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9642 09:27:57.773671 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9643 09:27:57.776770 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9644 09:27:57.780451 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9645 09:27:57.786911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9646 09:27:57.789937 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9647 09:27:57.796632 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9648 09:27:57.799881 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9649 09:27:57.803042 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9650 09:27:57.809558 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9651 09:27:57.813479 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9652 09:27:57.819940 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9653 09:27:57.823151 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9654 09:27:57.826165 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9655 09:27:57.832727 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9656 09:27:57.836173 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9657 09:27:57.842719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9658 09:27:57.846195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9659 09:27:57.849527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9660 09:27:57.856056 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9661 09:27:57.859676 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9662 09:27:57.866311 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9663 09:27:57.869450 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9664 09:27:57.872536 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9665 09:27:57.879132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9666 09:27:57.882513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9667 09:27:57.889284 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9668 09:27:57.892910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9669 09:27:57.895761 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9670 09:27:57.902605 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9671 09:27:57.905987 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9672 09:27:57.912497 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9673 09:27:57.915596 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9674 09:27:57.919081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9675 09:27:57.925781 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9676 09:27:57.929355 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9677 09:27:57.935595 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9678 09:27:57.938840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9679 09:27:57.945507 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9680 09:27:57.948608 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9681 09:27:57.952143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9682 09:27:57.958874 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9683 09:27:57.962190 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9684 09:27:57.968829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9685 09:27:57.971869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9686 09:27:57.975245 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9687 09:27:57.982352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9688 09:27:57.985292 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9689 09:27:57.992160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9690 09:27:57.995653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9691 09:27:57.998691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9692 09:27:58.005623 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9693 09:27:58.008566 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9694 09:27:58.015762 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9695 09:27:58.018819 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9696 09:27:58.025104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9697 09:27:58.028907 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9698 09:27:58.032292 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9699 09:27:58.038202 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9700 09:27:58.041812 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9701 09:27:58.048135 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9702 09:27:58.051468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9703 09:27:58.058242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9704 09:27:58.061724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9705 09:27:58.065255 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9706 09:27:58.071433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9707 09:27:58.075014 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9708 09:27:58.081561 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9709 09:27:58.085239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9710 09:27:58.091334 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9711 09:27:58.095039 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9712 09:27:58.098151 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9713 09:27:58.104829 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9714 09:27:58.108186 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9715 09:27:58.111535 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9716 09:27:58.114446 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9717 09:27:58.118044 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9718 09:27:58.124624 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9719 09:27:58.127909 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9720 09:27:58.134434 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9721 09:27:58.137919 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9722 09:27:58.141233 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9723 09:27:58.148036 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9724 09:27:58.151174 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9725 09:27:58.154912 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9726 09:27:58.161397 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9727 09:27:58.164358 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9728 09:27:58.168120 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9729 09:27:58.174440 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9730 09:27:58.177571 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9731 09:27:58.184296 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9732 09:27:58.188101 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9733 09:27:58.191268 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9734 09:27:58.197573 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9735 09:27:58.201340 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9736 09:27:58.204212 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9737 09:27:58.210986 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9738 09:27:58.214478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9739 09:27:58.221204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9740 09:27:58.224220 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9741 09:27:58.227922 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9742 09:27:58.234345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9743 09:27:58.237747 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9744 09:27:58.240727 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9745 09:27:58.247771 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9746 09:27:58.250747 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9747 09:27:58.254184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9748 09:27:58.260874 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9749 09:27:58.264172 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9750 09:27:58.270986 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9751 09:27:58.273946 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9752 09:27:58.277470 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9753 09:27:58.280560 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9754 09:27:58.287112 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9755 09:27:58.290506 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9756 09:27:58.294006 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9757 09:27:58.297125 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9758 09:27:58.304035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9759 09:27:58.307285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9760 09:27:58.310636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9761 09:27:58.313679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9762 09:27:58.320769 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9763 09:27:58.323564 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9764 09:27:58.327034 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9765 09:27:58.330630 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9766 09:27:58.336900 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9767 09:27:58.340209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9768 09:27:58.347104 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9769 09:27:58.350045 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9770 09:27:58.357161 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9771 09:27:58.360238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9772 09:27:58.363658 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9773 09:27:58.370143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9774 09:27:58.373229 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9775 09:27:58.379879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9776 09:27:58.383724 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9777 09:27:58.386546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9778 09:27:58.393088 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9779 09:27:58.396576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9780 09:27:58.403230 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9781 09:27:58.407109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9782 09:27:58.409857 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9783 09:27:58.416727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9784 09:27:58.419870 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9785 09:27:58.426598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9786 09:27:58.429980 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9787 09:27:58.436646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9788 09:27:58.440146 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9789 09:27:58.443069 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9790 09:27:58.450111 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9791 09:27:58.453252 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9792 09:27:58.459786 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9793 09:27:58.462920 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9794 09:27:58.466935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9795 09:27:58.473357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9796 09:27:58.476318 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9797 09:27:58.483049 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9798 09:27:58.486369 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9799 09:27:58.490018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9800 09:27:58.496555 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9801 09:27:58.499245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9802 09:27:58.505875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9803 09:27:58.509489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9804 09:27:58.516242 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9805 09:27:58.518989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9806 09:27:58.522633 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9807 09:27:58.528944 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9808 09:27:58.532618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9809 09:27:58.538971 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9810 09:27:58.542346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9811 09:27:58.545625 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9812 09:27:58.552668 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9813 09:27:58.555611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9814 09:27:58.562414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9815 09:27:58.566122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9816 09:27:58.568913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9817 09:27:58.575631 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9818 09:27:58.578599 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9819 09:27:58.585525 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9820 09:27:58.588976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9821 09:27:58.592044 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9822 09:27:58.598477 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9823 09:27:58.602218 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9824 09:27:58.608807 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9825 09:27:58.611855 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9826 09:27:58.618352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9827 09:27:58.621949 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9828 09:27:58.628554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9829 09:27:58.632201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9830 09:27:58.635128 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9831 09:27:58.641674 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9832 09:27:58.644982 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9833 09:27:58.651703 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9834 09:27:58.654849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9835 09:27:58.658140 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9836 09:27:58.664716 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9837 09:27:58.667849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9838 09:27:58.674473 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9839 09:27:58.677905 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9840 09:27:58.684390 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9841 09:27:58.688108 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9842 09:27:58.690929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9843 09:27:58.697709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9844 09:27:58.701316 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9845 09:27:58.707967 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9846 09:27:58.710782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9847 09:27:58.717898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9848 09:27:58.720940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9849 09:27:58.727701 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9850 09:27:58.730699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9851 09:27:58.734068 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9852 09:27:58.740792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9853 09:27:58.743819 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9854 09:27:58.750514 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9855 09:27:58.754060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9856 09:27:58.760529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9857 09:27:58.763635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9858 09:27:58.770286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9859 09:27:58.773847 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9860 09:27:58.776719 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9861 09:27:58.783412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9862 09:27:58.786971 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9863 09:27:58.793625 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9864 09:27:58.796730 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9865 09:27:58.803029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9866 09:27:58.806431 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9867 09:27:58.812974 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9868 09:27:58.816513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9869 09:27:58.819861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9870 09:27:58.826577 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9871 09:27:58.829695 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9872 09:27:58.836264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9873 09:27:58.839377 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9874 09:27:58.846090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9875 09:27:58.849707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9876 09:27:58.853142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9877 09:27:58.859571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9878 09:27:58.862994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9879 09:27:58.869729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9880 09:27:58.872896 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9881 09:27:58.879572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9882 09:27:58.882549 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9883 09:27:58.885953 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9884 09:27:58.893063 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9885 09:27:58.895865 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9886 09:27:58.902592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9887 09:27:58.906192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9888 09:27:58.912445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9889 09:27:58.915766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9890 09:27:58.922208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9891 09:27:58.926121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9892 09:27:58.929202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9893 09:27:58.935655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9894 09:27:58.938891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9895 09:27:58.946048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9896 09:27:58.948902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9897 09:27:58.955543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9898 09:27:58.959192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9899 09:27:58.965783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9900 09:27:58.968920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9901 09:27:58.975328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9902 09:27:58.978741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9903 09:27:58.985601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9904 09:27:58.988892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9905 09:27:58.995548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9906 09:27:58.998591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9907 09:27:59.005447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9908 09:27:59.008979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9909 09:27:59.015681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9910 09:27:59.018311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9911 09:27:59.025415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9912 09:27:59.028842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9913 09:27:59.035334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9914 09:27:59.038165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9915 09:27:59.045094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9916 09:27:59.048353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9917 09:27:59.054801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9918 09:27:59.058433 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9919 09:27:59.062012 INFO: [APUAPC] vio 0
9920 09:27:59.065062 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9921 09:27:59.071551 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9922 09:27:59.074608 INFO: [APUAPC] D0_APC_0: 0x400510
9923 09:27:59.074690 INFO: [APUAPC] D0_APC_1: 0x0
9924 09:27:59.078095 INFO: [APUAPC] D0_APC_2: 0x1540
9925 09:27:59.081651 INFO: [APUAPC] D0_APC_3: 0x0
9926 09:27:59.084721 INFO: [APUAPC] D1_APC_0: 0xffffffff
9927 09:27:59.088137 INFO: [APUAPC] D1_APC_1: 0xffffffff
9928 09:27:59.091450 INFO: [APUAPC] D1_APC_2: 0x3fffff
9929 09:27:59.094775 INFO: [APUAPC] D1_APC_3: 0x0
9930 09:27:59.097890 INFO: [APUAPC] D2_APC_0: 0xffffffff
9931 09:27:59.101158 INFO: [APUAPC] D2_APC_1: 0xffffffff
9932 09:27:59.104631 INFO: [APUAPC] D2_APC_2: 0x3fffff
9933 09:27:59.107661 INFO: [APUAPC] D2_APC_3: 0x0
9934 09:27:59.111425 INFO: [APUAPC] D3_APC_0: 0xffffffff
9935 09:27:59.114703 INFO: [APUAPC] D3_APC_1: 0xffffffff
9936 09:27:59.117787 INFO: [APUAPC] D3_APC_2: 0x3fffff
9937 09:27:59.121494 INFO: [APUAPC] D3_APC_3: 0x0
9938 09:27:59.124385 INFO: [APUAPC] D4_APC_0: 0xffffffff
9939 09:27:59.127806 INFO: [APUAPC] D4_APC_1: 0xffffffff
9940 09:27:59.131346 INFO: [APUAPC] D4_APC_2: 0x3fffff
9941 09:27:59.134380 INFO: [APUAPC] D4_APC_3: 0x0
9942 09:27:59.137852 INFO: [APUAPC] D5_APC_0: 0xffffffff
9943 09:27:59.140909 INFO: [APUAPC] D5_APC_1: 0xffffffff
9944 09:27:59.144417 INFO: [APUAPC] D5_APC_2: 0x3fffff
9945 09:27:59.148019 INFO: [APUAPC] D5_APC_3: 0x0
9946 09:27:59.151308 INFO: [APUAPC] D6_APC_0: 0xffffffff
9947 09:27:59.154695 INFO: [APUAPC] D6_APC_1: 0xffffffff
9948 09:27:59.157865 INFO: [APUAPC] D6_APC_2: 0x3fffff
9949 09:27:59.161012 INFO: [APUAPC] D6_APC_3: 0x0
9950 09:27:59.164562 INFO: [APUAPC] D7_APC_0: 0xffffffff
9951 09:27:59.167644 INFO: [APUAPC] D7_APC_1: 0xffffffff
9952 09:27:59.171057 INFO: [APUAPC] D7_APC_2: 0x3fffff
9953 09:27:59.174103 INFO: [APUAPC] D7_APC_3: 0x0
9954 09:27:59.177931 INFO: [APUAPC] D8_APC_0: 0xffffffff
9955 09:27:59.180840 INFO: [APUAPC] D8_APC_1: 0xffffffff
9956 09:27:59.184517 INFO: [APUAPC] D8_APC_2: 0x3fffff
9957 09:27:59.187605 INFO: [APUAPC] D8_APC_3: 0x0
9958 09:27:59.191230 INFO: [APUAPC] D9_APC_0: 0xffffffff
9959 09:27:59.194029 INFO: [APUAPC] D9_APC_1: 0xffffffff
9960 09:27:59.197581 INFO: [APUAPC] D9_APC_2: 0x3fffff
9961 09:27:59.200889 INFO: [APUAPC] D9_APC_3: 0x0
9962 09:27:59.204520 INFO: [APUAPC] D10_APC_0: 0xffffffff
9963 09:27:59.207429 INFO: [APUAPC] D10_APC_1: 0xffffffff
9964 09:27:59.210914 INFO: [APUAPC] D10_APC_2: 0x3fffff
9965 09:27:59.214700 INFO: [APUAPC] D10_APC_3: 0x0
9966 09:27:59.217545 INFO: [APUAPC] D11_APC_0: 0xffffffff
9967 09:27:59.220776 INFO: [APUAPC] D11_APC_1: 0xffffffff
9968 09:27:59.224273 INFO: [APUAPC] D11_APC_2: 0x3fffff
9969 09:27:59.227563 INFO: [APUAPC] D11_APC_3: 0x0
9970 09:27:59.231238 INFO: [APUAPC] D12_APC_0: 0xffffffff
9971 09:27:59.234379 INFO: [APUAPC] D12_APC_1: 0xffffffff
9972 09:27:59.237496 INFO: [APUAPC] D12_APC_2: 0x3fffff
9973 09:27:59.241053 INFO: [APUAPC] D12_APC_3: 0x0
9974 09:27:59.244142 INFO: [APUAPC] D13_APC_0: 0xffffffff
9975 09:27:59.247573 INFO: [APUAPC] D13_APC_1: 0xffffffff
9976 09:27:59.251046 INFO: [APUAPC] D13_APC_2: 0x3fffff
9977 09:27:59.254076 INFO: [APUAPC] D13_APC_3: 0x0
9978 09:27:59.257742 INFO: [APUAPC] D14_APC_0: 0xffffffff
9979 09:27:59.260949 INFO: [APUAPC] D14_APC_1: 0xffffffff
9980 09:27:59.264173 INFO: [APUAPC] D14_APC_2: 0x3fffff
9981 09:27:59.267632 INFO: [APUAPC] D14_APC_3: 0x0
9982 09:27:59.270774 INFO: [APUAPC] D15_APC_0: 0xffffffff
9983 09:27:59.274382 INFO: [APUAPC] D15_APC_1: 0xffffffff
9984 09:27:59.278019 INFO: [APUAPC] D15_APC_2: 0x3fffff
9985 09:27:59.280998 INFO: [APUAPC] D15_APC_3: 0x0
9986 09:27:59.281105 INFO: [APUAPC] APC_CON: 0x4
9987 09:27:59.284162 INFO: [NOCDAPC] D0_APC_0: 0x0
9988 09:27:59.287514 INFO: [NOCDAPC] D0_APC_1: 0x0
9989 09:27:59.291373 INFO: [NOCDAPC] D1_APC_0: 0x0
9990 09:27:59.294450 INFO: [NOCDAPC] D1_APC_1: 0xfff
9991 09:27:59.297977 INFO: [NOCDAPC] D2_APC_0: 0x0
9992 09:27:59.300934 INFO: [NOCDAPC] D2_APC_1: 0xfff
9993 09:27:59.304297 INFO: [NOCDAPC] D3_APC_0: 0x0
9994 09:27:59.307716 INFO: [NOCDAPC] D3_APC_1: 0xfff
9995 09:27:59.310608 INFO: [NOCDAPC] D4_APC_0: 0x0
9996 09:27:59.313903 INFO: [NOCDAPC] D4_APC_1: 0xfff
9997 09:27:59.313985 INFO: [NOCDAPC] D5_APC_0: 0x0
9998 09:27:59.317524 INFO: [NOCDAPC] D5_APC_1: 0xfff
9999 09:27:59.320746 INFO: [NOCDAPC] D6_APC_0: 0x0
10000 09:27:59.324365 INFO: [NOCDAPC] D6_APC_1: 0xfff
10001 09:27:59.327201 INFO: [NOCDAPC] D7_APC_0: 0x0
10002 09:27:59.330737 INFO: [NOCDAPC] D7_APC_1: 0xfff
10003 09:27:59.333723 INFO: [NOCDAPC] D8_APC_0: 0x0
10004 09:27:59.337131 INFO: [NOCDAPC] D8_APC_1: 0xfff
10005 09:27:59.340483 INFO: [NOCDAPC] D9_APC_0: 0x0
10006 09:27:59.343926 INFO: [NOCDAPC] D9_APC_1: 0xfff
10007 09:27:59.347174 INFO: [NOCDAPC] D10_APC_0: 0x0
10008 09:27:59.347282 INFO: [NOCDAPC] D10_APC_1: 0xfff
10009 09:27:59.350421 INFO: [NOCDAPC] D11_APC_0: 0x0
10010 09:27:59.353626 INFO: [NOCDAPC] D11_APC_1: 0xfff
10011 09:27:59.357196 INFO: [NOCDAPC] D12_APC_0: 0x0
10012 09:27:59.360748 INFO: [NOCDAPC] D12_APC_1: 0xfff
10013 09:27:59.363799 INFO: [NOCDAPC] D13_APC_0: 0x0
10014 09:27:59.366885 INFO: [NOCDAPC] D13_APC_1: 0xfff
10015 09:27:59.370302 INFO: [NOCDAPC] D14_APC_0: 0x0
10016 09:27:59.373451 INFO: [NOCDAPC] D14_APC_1: 0xfff
10017 09:27:59.376919 INFO: [NOCDAPC] D15_APC_0: 0x0
10018 09:27:59.380500 INFO: [NOCDAPC] D15_APC_1: 0xfff
10019 09:27:59.384118 INFO: [NOCDAPC] APC_CON: 0x4
10020 09:27:59.387193 INFO: [APUAPC] set_apusys_apc done
10021 09:27:59.390128 INFO: [DEVAPC] devapc_init done
10022 09:27:59.393640 INFO: GICv3 without legacy support detected.
10023 09:27:59.397332 INFO: ARM GICv3 driver initialized in EL3
10024 09:27:59.400134 INFO: Maximum SPI INTID supported: 639
10025 09:27:59.403872 INFO: BL31: Initializing runtime services
10026 09:27:59.410523 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10027 09:27:59.413373 INFO: SPM: enable CPC mode
10028 09:27:59.420187 INFO: mcdi ready for mcusys-off-idle and system suspend
10029 09:27:59.423371 INFO: BL31: Preparing for EL3 exit to normal world
10030 09:27:59.426921 INFO: Entry point address = 0x80000000
10031 09:27:59.429881 INFO: SPSR = 0x8
10032 09:27:59.434694
10033 09:27:59.434778
10034 09:27:59.434841
10035 09:27:59.438190 Starting depthcharge on Spherion...
10036 09:27:59.438271
10037 09:27:59.438335 Wipe memory regions:
10038 09:27:59.438395
10039 09:27:59.439081 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10040 09:27:59.439181 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10041 09:27:59.439261 Setting prompt string to ['asurada:']
10042 09:27:59.439347 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10043 09:27:59.441126 [0x00000040000000, 0x00000054600000)
10044 09:27:59.563872
10045 09:27:59.563986 [0x00000054660000, 0x00000080000000)
10046 09:27:59.824011
10047 09:27:59.824148 [0x000000821a7280, 0x000000ffe64000)
10048 09:28:00.568901
10049 09:28:00.569070 [0x00000100000000, 0x00000240000000)
10050 09:28:02.459203
10051 09:28:02.462877 Initializing XHCI USB controller at 0x11200000.
10052 09:28:03.500233
10053 09:28:03.503379 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10054 09:28:03.503539
10055 09:28:03.503632
10056 09:28:03.503714
10057 09:28:03.503993 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 09:28:03.604345 asurada: tftpboot 192.168.201.1 11826783/tftp-deploy-fnbcpo20/kernel/image.itb 11826783/tftp-deploy-fnbcpo20/kernel/cmdline
10060 09:28:03.604476 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 09:28:03.604581 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10062 09:28:03.608651 tftpboot 192.168.201.1 11826783/tftp-deploy-fnbcpo20/kernel/image.itp-deploy-fnbcpo20/kernel/cmdline
10063 09:28:03.608735
10064 09:28:03.608799 Waiting for link
10065 09:28:03.769156
10066 09:28:03.769284 R8152: Initializing
10067 09:28:03.769352
10068 09:28:03.772572 Version 6 (ocp_data = 5c30)
10069 09:28:03.772654
10070 09:28:03.775689 R8152: Done initializing
10071 09:28:03.775774
10072 09:28:03.775839 Adding net device
10073 09:28:05.679266
10074 09:28:05.679442 done.
10075 09:28:05.679511
10076 09:28:05.679572 MAC: 00:24:32:30:78:ff
10077 09:28:05.679632
10078 09:28:05.682910 Sending DHCP discover... done.
10079 09:28:05.683011
10080 09:28:09.816666 Waiting for reply... done.
10081 09:28:09.816809
10082 09:28:09.816881 Sending DHCP request... done.
10083 09:28:09.819504
10084 09:28:09.823488 Waiting for reply... done.
10085 09:28:09.823565
10086 09:28:09.823630 My ip is 192.168.201.21
10087 09:28:09.823689
10088 09:28:09.827185 The DHCP server ip is 192.168.201.1
10089 09:28:09.827273
10090 09:28:09.833683 TFTP server IP predefined by user: 192.168.201.1
10091 09:28:09.833765
10092 09:28:09.840289 Bootfile predefined by user: 11826783/tftp-deploy-fnbcpo20/kernel/image.itb
10093 09:28:09.840369
10094 09:28:09.840432 Sending tftp read request... done.
10095 09:28:09.843811
10096 09:28:09.847539 Waiting for the transfer...
10097 09:28:09.847627
10098 09:28:10.399011 00000000 ################################################################
10099 09:28:10.399192
10100 09:28:10.965309 00080000 ################################################################
10101 09:28:10.965452
10102 09:28:11.537276 00100000 ################################################################
10103 09:28:11.537438
10104 09:28:12.114581 00180000 ################################################################
10105 09:28:12.114718
10106 09:28:12.644001 00200000 ################################################################
10107 09:28:12.644136
10108 09:28:13.172127 00280000 ################################################################
10109 09:28:13.172265
10110 09:28:13.712695 00300000 ################################################################
10111 09:28:13.712832
10112 09:28:14.288762 00380000 ################################################################
10113 09:28:14.288909
10114 09:28:14.948322 00400000 ################################################################
10115 09:28:14.948465
10116 09:28:15.593177 00480000 ################################################################
10117 09:28:15.593317
10118 09:28:16.148609 00500000 ################################################################
10119 09:28:16.148756
10120 09:28:16.717221 00580000 ################################################################
10121 09:28:16.717362
10122 09:28:17.286252 00600000 ################################################################
10123 09:28:17.286387
10124 09:28:17.832508 00680000 ################################################################
10125 09:28:17.832652
10126 09:28:18.384537 00700000 ################################################################
10127 09:28:18.384672
10128 09:28:18.940887 00780000 ################################################################
10129 09:28:18.941019
10130 09:28:19.496277 00800000 ################################################################
10131 09:28:19.496444
10132 09:28:20.029544 00880000 ################################################################
10133 09:28:20.029711
10134 09:28:20.711171 00900000 ################################################################
10135 09:28:20.711799
10136 09:28:21.438728 00980000 ################################################################
10137 09:28:21.439265
10138 09:28:22.147762 00a00000 ################################################################
10139 09:28:22.148271
10140 09:28:22.827136 00a80000 ################################################################
10141 09:28:22.827273
10142 09:28:23.437218 00b00000 ################################################################
10143 09:28:23.437353
10144 09:28:24.007352 00b80000 ################################################################
10145 09:28:24.007555
10146 09:28:24.626102 00c00000 ################################################################
10147 09:28:24.626240
10148 09:28:25.227652 00c80000 ################################################################
10149 09:28:25.227793
10150 09:28:25.870632 00d00000 ################################################################
10151 09:28:25.871177
10152 09:28:26.598764 00d80000 ################################################################
10153 09:28:26.599251
10154 09:28:27.330944 00e00000 ################################################################
10155 09:28:27.331501
10156 09:28:28.068234 00e80000 ################################################################
10157 09:28:28.068761
10158 09:28:28.817326 00f00000 ################################################################
10159 09:28:28.817840
10160 09:28:29.565066 00f80000 ################################################################
10161 09:28:29.565558
10162 09:28:30.292014 01000000 ################################################################
10163 09:28:30.292536
10164 09:28:31.011260 01080000 ################################################################
10165 09:28:31.011828
10166 09:28:31.747218 01100000 ################################################################
10167 09:28:31.747814
10168 09:28:32.473453 01180000 ################################################################
10169 09:28:32.473987
10170 09:28:33.222690 01200000 ################################################################
10171 09:28:33.223209
10172 09:28:33.889409 01280000 ################################################################
10173 09:28:33.889932
10174 09:28:34.602188 01300000 ################################################################
10175 09:28:34.602694
10176 09:28:35.285179 01380000 ################################################################
10177 09:28:35.285745
10178 09:28:35.904639 01400000 ################################################################
10179 09:28:35.905177
10180 09:28:36.616491 01480000 ################################################################
10181 09:28:36.617028
10182 09:28:37.300690 01500000 ################################################################
10183 09:28:37.300835
10184 09:28:37.880011 01580000 ################################################################
10185 09:28:37.880151
10186 09:28:38.450581 01600000 ################################################################
10187 09:28:38.450778
10188 09:28:39.023682 01680000 ################################################################
10189 09:28:39.023845
10190 09:28:39.572904 01700000 ################################################################
10191 09:28:39.573078
10192 09:28:40.119340 01780000 ################################################################
10193 09:28:40.119526
10194 09:28:40.681601 01800000 ################################################################
10195 09:28:40.681757
10196 09:28:41.245894 01880000 ################################################################
10197 09:28:41.246061
10198 09:28:41.795611 01900000 ################################################################
10199 09:28:41.795757
10200 09:28:42.366048 01980000 ################################################################
10201 09:28:42.366185
10202 09:28:42.939162 01a00000 ################################################################
10203 09:28:42.939312
10204 09:28:43.512394 01a80000 ################################################################
10205 09:28:43.512543
10206 09:28:44.085298 01b00000 ################################################################
10207 09:28:44.085444
10208 09:28:44.658961 01b80000 ################################################################
10209 09:28:44.659112
10210 09:28:45.230258 01c00000 ################################################################
10211 09:28:45.230393
10212 09:28:45.776981 01c80000 ################################################################
10213 09:28:45.777123
10214 09:28:46.316363 01d00000 ################################################################
10215 09:28:46.316513
10216 09:28:46.859344 01d80000 ################################################################
10217 09:28:46.859565
10218 09:28:47.398469 01e00000 ################################################################
10219 09:28:47.398647
10220 09:28:47.940218 01e80000 ################################################################
10221 09:28:47.940394
10222 09:28:48.484657 01f00000 ################################################################
10223 09:28:48.484836
10224 09:28:49.033248 01f80000 ################################################################
10225 09:28:49.033385
10226 09:28:49.593561 02000000 ################################################################
10227 09:28:49.593753
10228 09:28:50.163413 02080000 ################################################################
10229 09:28:50.163562
10230 09:28:50.720487 02100000 ################################################################
10231 09:28:50.720644
10232 09:28:51.280154 02180000 ################################################################
10233 09:28:51.280310
10234 09:28:51.808944 02200000 ################################################################
10235 09:28:51.809098
10236 09:28:52.350043 02280000 ################################################################
10237 09:28:52.350216
10238 09:28:52.899111 02300000 ################################################################
10239 09:28:52.899256
10240 09:28:53.454583 02380000 ################################################################
10241 09:28:53.454721
10242 09:28:54.017739 02400000 ################################################################
10243 09:28:54.017923
10244 09:28:54.589024 02480000 ################################################################
10245 09:28:54.589180
10246 09:28:55.161174 02500000 ################################################################
10247 09:28:55.161331
10248 09:28:55.738291 02580000 ################################################################
10249 09:28:55.738455
10250 09:28:56.318661 02600000 ################################################################
10251 09:28:56.318799
10252 09:28:56.896134 02680000 ################################################################
10253 09:28:56.896273
10254 09:28:57.479839 02700000 ################################################################
10255 09:28:57.479979
10256 09:28:58.041538 02780000 ################################################################
10257 09:28:58.041719
10258 09:28:58.625536 02800000 ################################################################
10259 09:28:58.625678
10260 09:28:59.206423 02880000 ################################################################
10261 09:28:59.206562
10262 09:28:59.776644 02900000 ################################################################
10263 09:28:59.776793
10264 09:29:00.357411 02980000 ################################################################
10265 09:29:00.357594
10266 09:29:00.916668 02a00000 ################################################################
10267 09:29:00.916822
10268 09:29:01.465953 02a80000 ################################################################
10269 09:29:01.466101
10270 09:29:02.007638 02b00000 ################################################################
10271 09:29:02.007790
10272 09:29:02.552579 02b80000 ################################################################
10273 09:29:02.552730
10274 09:29:03.106953 02c00000 ################################################################
10275 09:29:03.107105
10276 09:29:03.668567 02c80000 ################################################################
10277 09:29:03.668723
10278 09:29:04.233420 02d00000 ################################################################
10279 09:29:04.233571
10280 09:29:04.781754 02d80000 ################################################################
10281 09:29:04.781930
10282 09:29:05.390274 02e00000 ################################################################
10283 09:29:05.390799
10284 09:29:05.941022 02e80000 ################################################################
10285 09:29:05.941177
10286 09:29:06.492720 02f00000 ################################################################
10287 09:29:06.492857
10288 09:29:07.078258 02f80000 ################################################################
10289 09:29:07.078403
10290 09:29:07.655110 03000000 ################################################################
10291 09:29:07.655252
10292 09:29:08.204567 03080000 ################################################################
10293 09:29:08.204717
10294 09:29:08.785897 03100000 ################################################################
10295 09:29:08.786040
10296 09:29:09.380865 03180000 ################################################################
10297 09:29:09.381003
10298 09:29:09.987524 03200000 ################################################################
10299 09:29:09.987670
10300 09:29:10.567918 03280000 ################################################################
10301 09:29:10.568053
10302 09:29:11.128491 03300000 ################################################################
10303 09:29:11.128626
10304 09:29:11.713672 03380000 ################################################################
10305 09:29:11.713811
10306 09:29:12.290133 03400000 ################################################################
10307 09:29:12.290280
10308 09:29:12.887520 03480000 ################################################################
10309 09:29:12.887655
10310 09:29:13.461797 03500000 ################################################################
10311 09:29:13.461930
10312 09:29:14.035869 03580000 ################################################################
10313 09:29:14.036001
10314 09:29:14.607456 03600000 ################################################################
10315 09:29:14.607590
10316 09:29:15.182039 03680000 ################################################################
10317 09:29:15.182178
10318 09:29:15.755793 03700000 ################################################################
10319 09:29:15.755961
10320 09:29:16.180112 03780000 ################################################### done.
10321 09:29:16.180250
10322 09:29:16.183619 The bootfile was 58611654 bytes long.
10323 09:29:16.183706
10324 09:29:16.187296 Sending tftp read request... done.
10325 09:29:16.187389
10326 09:29:16.187459 Waiting for the transfer...
10327 09:29:16.187522
10328 09:29:16.190243 00000000 # done.
10329 09:29:16.190328
10330 09:29:16.196690 Command line loaded dynamically from TFTP file: 11826783/tftp-deploy-fnbcpo20/kernel/cmdline
10331 09:29:16.196778
10332 09:29:16.209945 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10333 09:29:16.210036
10334 09:29:16.213627 Loading FIT.
10335 09:29:16.213709
10336 09:29:16.216766 Image ramdisk-1 has 47518084 bytes.
10337 09:29:16.216850
10338 09:29:16.216938 Image fdt-1 has 47278 bytes.
10339 09:29:16.219872
10340 09:29:16.219952 Image kernel-1 has 11044258 bytes.
10341 09:29:16.220016
10342 09:29:16.230219 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10343 09:29:16.230322
10344 09:29:16.246608 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10345 09:29:16.246697
10346 09:29:16.252944 Choosing best match conf-1 for compat google,spherion-rev2.
10347 09:29:16.257484
10348 09:29:16.262347 Connected to device vid:did:rid of 1ae0:0028:00
10349 09:29:16.268656
10350 09:29:16.272136 tpm_get_response: command 0x17b, return code 0x0
10351 09:29:16.272218
10352 09:29:16.275591 ec_init: CrosEC protocol v3 supported (256, 248)
10353 09:29:16.279603
10354 09:29:16.282710 tpm_cleanup: add release locality here.
10355 09:29:16.282792
10356 09:29:16.282856 Shutting down all USB controllers.
10357 09:29:16.286319
10358 09:29:16.286437 Removing current net device
10359 09:29:16.286535
10360 09:29:16.293012 Exiting depthcharge with code 4 at timestamp: 106178118
10361 09:29:16.293207
10362 09:29:16.296635 LZMA decompressing kernel-1 to 0x821a6718
10363 09:29:16.296754
10364 09:29:16.299745 LZMA decompressing kernel-1 to 0x40000000
10365 09:29:17.689813
10366 09:29:17.689962 jumping to kernel
10367 09:29:17.690482 end: 2.2.4 bootloader-commands (duration 00:01:18) [common]
10368 09:29:17.690636 start: 2.2.5 auto-login-action (timeout 00:03:07) [common]
10369 09:29:17.690764 Setting prompt string to ['Linux version [0-9]']
10370 09:29:17.690873 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 09:29:17.690962 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 09:29:17.771235
10373 09:29:17.774796 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10374 09:29:17.778093 start: 2.2.5.1 login-action (timeout 00:03:07) [common]
10375 09:29:17.778184 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 09:29:17.778255 Setting prompt string to []
10377 09:29:17.778335 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10378 09:29:17.778411 Using line separator: #'\n'#
10379 09:29:17.778470 No login prompt set.
10380 09:29:17.778530 Parsing kernel messages
10381 09:29:17.778584 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10382 09:29:17.778687 [login-action] Waiting for messages, (timeout 00:03:07)
10383 09:29:17.797863 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10384 09:29:17.801446 [ 0.000000] random: crng init done
10385 09:29:17.807620 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10386 09:29:17.807702 [ 0.000000] efi: UEFI not found.
10387 09:29:17.817602 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10388 09:29:17.824595 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10389 09:29:17.834244 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10390 09:29:17.844458 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10391 09:29:17.851053 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10392 09:29:17.854140 [ 0.000000] printk: bootconsole [mtk8250] enabled
10393 09:29:17.862989 [ 0.000000] NUMA: No NUMA configuration found
10394 09:29:17.869866 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10395 09:29:17.876024 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10396 09:29:17.876110 [ 0.000000] Zone ranges:
10397 09:29:17.882836 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10398 09:29:17.886520 [ 0.000000] DMA32 empty
10399 09:29:17.892971 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10400 09:29:17.896016 [ 0.000000] Movable zone start for each node
10401 09:29:17.899221 [ 0.000000] Early memory node ranges
10402 09:29:17.906152 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10403 09:29:17.912382 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10404 09:29:17.919100 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10405 09:29:17.925807 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10406 09:29:17.931970 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10407 09:29:17.938758 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10408 09:29:17.995620 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10409 09:29:18.002439 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10410 09:29:18.008706 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10411 09:29:18.012444 [ 0.000000] psci: probing for conduit method from DT.
10412 09:29:18.018814 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10413 09:29:18.021798 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10414 09:29:18.028570 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10415 09:29:18.032049 [ 0.000000] psci: SMC Calling Convention v1.2
10416 09:29:18.038727 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10417 09:29:18.041838 [ 0.000000] Detected VIPT I-cache on CPU0
10418 09:29:18.048419 [ 0.000000] CPU features: detected: GIC system register CPU interface
10419 09:29:18.055461 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10420 09:29:18.062046 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10421 09:29:18.068490 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10422 09:29:18.074879 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10423 09:29:18.085251 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10424 09:29:18.087968 [ 0.000000] alternatives: applying boot alternatives
10425 09:29:18.094985 [ 0.000000] Fallback order for Node 0: 0
10426 09:29:18.101246 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10427 09:29:18.105004 [ 0.000000] Policy zone: Normal
10428 09:29:18.118037 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10429 09:29:18.127808 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10430 09:29:18.139931 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10431 09:29:18.149804 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10432 09:29:18.156571 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10433 09:29:18.159720 <6>[ 0.000000] software IO TLB: area num 8.
10434 09:29:18.216924 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10435 09:29:18.365501 <6>[ 0.000000] Memory: 7923088K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 429680K reserved, 32768K cma-reserved)
10436 09:29:18.372024 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10437 09:29:18.379195 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10438 09:29:18.382214 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10439 09:29:18.388951 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10440 09:29:18.395702 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10441 09:29:18.399046 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10442 09:29:18.408953 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10443 09:29:18.415247 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10444 09:29:18.421788 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10445 09:29:18.428621 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10446 09:29:18.431706 <6>[ 0.000000] GICv3: 608 SPIs implemented
10447 09:29:18.435265 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10448 09:29:18.441518 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10449 09:29:18.445002 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10450 09:29:18.451518 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10451 09:29:18.465024 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10452 09:29:18.474988 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10453 09:29:18.484573 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10454 09:29:18.492087 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10455 09:29:18.505252 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10456 09:29:18.512001 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10457 09:29:18.518472 <6>[ 0.009235] Console: colour dummy device 80x25
10458 09:29:18.528429 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10459 09:29:18.535243 <6>[ 0.024466] pid_max: default: 32768 minimum: 301
10460 09:29:18.538835 <6>[ 0.029338] LSM: Security Framework initializing
10461 09:29:18.544788 <6>[ 0.034247] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 09:29:18.554737 <6>[ 0.042061] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 09:29:18.564897 <6>[ 0.051482] cblist_init_generic: Setting adjustable number of callback queues.
10464 09:29:18.567799 <6>[ 0.058973] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 09:29:18.577996 <6>[ 0.065352] cblist_init_generic: Setting adjustable number of callback queues.
10466 09:29:18.584998 <6>[ 0.072779] cblist_init_generic: Setting shift to 3 and lim to 1.
10467 09:29:18.587849 <6>[ 0.079218] rcu: Hierarchical SRCU implementation.
10468 09:29:18.594351 <6>[ 0.084234] rcu: Max phase no-delay instances is 1000.
10469 09:29:18.601245 <6>[ 0.091259] EFI services will not be available.
10470 09:29:18.604379 <6>[ 0.096215] smp: Bringing up secondary CPUs ...
10471 09:29:18.612990 <6>[ 0.101265] Detected VIPT I-cache on CPU1
10472 09:29:18.619923 <6>[ 0.101319] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10473 09:29:18.625935 <6>[ 0.101344] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10474 09:29:18.629117 <6>[ 0.101649] Detected VIPT I-cache on CPU2
10475 09:29:18.639109 <6>[ 0.101693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10476 09:29:18.645802 <6>[ 0.101710] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10477 09:29:18.648908 <6>[ 0.101964] Detected VIPT I-cache on CPU3
10478 09:29:18.656024 <6>[ 0.102009] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10479 09:29:18.662675 <6>[ 0.102023] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10480 09:29:18.666000 <6>[ 0.102327] CPU features: detected: Spectre-v4
10481 09:29:18.672456 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10482 09:29:18.675621 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10483 09:29:18.682088 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10484 09:29:18.688918 <6>[ 0.102413] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10485 09:29:18.695998 <6>[ 0.102700] Detected PIPT I-cache on CPU5
10486 09:29:18.702342 <6>[ 0.102762] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10487 09:29:18.708985 <6>[ 0.102779] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10488 09:29:18.712120 <6>[ 0.103057] Detected PIPT I-cache on CPU6
10489 09:29:18.719022 <6>[ 0.103121] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10490 09:29:18.725209 <6>[ 0.103138] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10491 09:29:18.731950 <6>[ 0.103435] Detected PIPT I-cache on CPU7
10492 09:29:18.738618 <6>[ 0.103499] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10493 09:29:18.745482 <6>[ 0.103515] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10494 09:29:18.748638 <6>[ 0.103562] smp: Brought up 1 node, 8 CPUs
10495 09:29:18.754832 <6>[ 0.244871] SMP: Total of 8 processors activated.
10496 09:29:18.758499 <6>[ 0.249793] CPU features: detected: 32-bit EL0 Support
10497 09:29:18.768590 <6>[ 0.255188] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10498 09:29:18.775203 <6>[ 0.263989] CPU features: detected: Common not Private translations
10499 09:29:18.781892 <6>[ 0.270505] CPU features: detected: CRC32 instructions
10500 09:29:18.785464 <6>[ 0.275859] CPU features: detected: RCpc load-acquire (LDAPR)
10501 09:29:18.791706 <6>[ 0.281819] CPU features: detected: LSE atomic instructions
10502 09:29:18.798401 <6>[ 0.287601] CPU features: detected: Privileged Access Never
10503 09:29:18.805140 <6>[ 0.293381] CPU features: detected: RAS Extension Support
10504 09:29:18.811230 <6>[ 0.298989] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10505 09:29:18.814587 <6>[ 0.306212] CPU: All CPU(s) started at EL2
10506 09:29:18.821211 <6>[ 0.310529] alternatives: applying system-wide alternatives
10507 09:29:18.830541 <6>[ 0.321220] devtmpfs: initialized
10508 09:29:18.846063 <6>[ 0.330271] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10509 09:29:18.852982 <6>[ 0.340231] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10510 09:29:18.859144 <6>[ 0.348468] pinctrl core: initialized pinctrl subsystem
10511 09:29:18.862921 <6>[ 0.355101] DMI not present or invalid.
10512 09:29:18.869101 <6>[ 0.359506] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10513 09:29:18.879068 <6>[ 0.366378] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10514 09:29:18.886078 <6>[ 0.373961] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10515 09:29:18.896259 <6>[ 0.382187] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10516 09:29:18.899174 <6>[ 0.390426] audit: initializing netlink subsys (disabled)
10517 09:29:18.908931 <5>[ 0.396118] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10518 09:29:18.915829 <6>[ 0.396810] thermal_sys: Registered thermal governor 'step_wise'
10519 09:29:18.921955 <6>[ 0.404083] thermal_sys: Registered thermal governor 'power_allocator'
10520 09:29:18.925515 <6>[ 0.410337] cpuidle: using governor menu
10521 09:29:18.932366 <6>[ 0.421300] NET: Registered PF_QIPCRTR protocol family
10522 09:29:18.938743 <6>[ 0.426781] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10523 09:29:18.945456 <6>[ 0.433884] ASID allocator initialised with 32768 entries
10524 09:29:18.948681 <6>[ 0.440446] Serial: AMBA PL011 UART driver
10525 09:29:18.958559 <4>[ 0.449198] Trying to register duplicate clock ID: 134
10526 09:29:19.013006 <6>[ 0.507027] KASLR enabled
10527 09:29:19.027790 <6>[ 0.514742] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10528 09:29:19.033937 <6>[ 0.521759] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10529 09:29:19.040709 <6>[ 0.528244] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10530 09:29:19.047454 <6>[ 0.535249] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10531 09:29:19.053589 <6>[ 0.541735] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10532 09:29:19.060533 <6>[ 0.548740] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10533 09:29:19.066914 <6>[ 0.555229] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10534 09:29:19.073833 <6>[ 0.562231] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10535 09:29:19.077361 <6>[ 0.569741] ACPI: Interpreter disabled.
10536 09:29:19.085488 <6>[ 0.576163] iommu: Default domain type: Translated
10537 09:29:19.092407 <6>[ 0.581274] iommu: DMA domain TLB invalidation policy: strict mode
10538 09:29:19.095564 <5>[ 0.587931] SCSI subsystem initialized
10539 09:29:19.102286 <6>[ 0.592097] usbcore: registered new interface driver usbfs
10540 09:29:19.108255 <6>[ 0.597828] usbcore: registered new interface driver hub
10541 09:29:19.111952 <6>[ 0.603377] usbcore: registered new device driver usb
10542 09:29:19.118693 <6>[ 0.609474] pps_core: LinuxPPS API ver. 1 registered
10543 09:29:19.128633 <6>[ 0.614668] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10544 09:29:19.132225 <6>[ 0.624014] PTP clock support registered
10545 09:29:19.135120 <6>[ 0.628255] EDAC MC: Ver: 3.0.0
10546 09:29:19.142711 <6>[ 0.633423] FPGA manager framework
10547 09:29:19.145793 <6>[ 0.637101] Advanced Linux Sound Architecture Driver Initialized.
10548 09:29:19.150049 <6>[ 0.643870] vgaarb: loaded
10549 09:29:19.156316 <6>[ 0.647027] clocksource: Switched to clocksource arch_sys_counter
10550 09:29:19.163326 <5>[ 0.653461] VFS: Disk quotas dquot_6.6.0
10551 09:29:19.169557 <6>[ 0.657647] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10552 09:29:19.173210 <6>[ 0.664838] pnp: PnP ACPI: disabled
10553 09:29:19.180533 <6>[ 0.671467] NET: Registered PF_INET protocol family
10554 09:29:19.190439 <6>[ 0.677055] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10555 09:29:19.202085 <6>[ 0.689354] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10556 09:29:19.211723 <6>[ 0.698167] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10557 09:29:19.218452 <6>[ 0.706137] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10558 09:29:19.228154 <6>[ 0.714835] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10559 09:29:19.235070 <6>[ 0.724586] TCP: Hash tables configured (established 65536 bind 65536)
10560 09:29:19.241588 <6>[ 0.731447] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 09:29:19.251614 <6>[ 0.738643] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 09:29:19.258140 <6>[ 0.746344] NET: Registered PF_UNIX/PF_LOCAL protocol family
10563 09:29:19.264740 <6>[ 0.752509] RPC: Registered named UNIX socket transport module.
10564 09:29:19.267690 <6>[ 0.758661] RPC: Registered udp transport module.
10565 09:29:19.271147 <6>[ 0.763593] RPC: Registered tcp transport module.
10566 09:29:19.281521 <6>[ 0.768525] RPC: Registered tcp NFSv4.1 backchannel transport module.
10567 09:29:19.284354 <6>[ 0.775194] PCI: CLS 0 bytes, default 64
10568 09:29:19.287990 <6>[ 0.779586] Unpacking initramfs...
10569 09:29:19.311896 <6>[ 0.799279] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10570 09:29:19.321891 <6>[ 0.807941] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10571 09:29:19.325006 <6>[ 0.816792] kvm [1]: IPA Size Limit: 40 bits
10572 09:29:19.331424 <6>[ 0.821320] kvm [1]: GICv3: no GICV resource entry
10573 09:29:19.334805 <6>[ 0.826338] kvm [1]: disabling GICv2 emulation
10574 09:29:19.341800 <6>[ 0.831031] kvm [1]: GIC system register CPU interface enabled
10575 09:29:19.344714 <6>[ 0.837199] kvm [1]: vgic interrupt IRQ18
10576 09:29:19.351588 <6>[ 0.841552] kvm [1]: VHE mode initialized successfully
10577 09:29:19.358573 <5>[ 0.847973] Initialise system trusted keyrings
10578 09:29:19.364798 <6>[ 0.852749] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10579 09:29:19.372266 <6>[ 0.862684] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10580 09:29:19.378678 <5>[ 0.869070] NFS: Registering the id_resolver key type
10581 09:29:19.382473 <5>[ 0.874370] Key type id_resolver registered
10582 09:29:19.388381 <5>[ 0.878786] Key type id_legacy registered
10583 09:29:19.394944 <6>[ 0.883065] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10584 09:29:19.401672 <6>[ 0.889986] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10585 09:29:19.408353 <6>[ 0.897698] 9p: Installing v9fs 9p2000 file system support
10586 09:29:19.444629 <5>[ 0.934939] Key type asymmetric registered
10587 09:29:19.447812 <5>[ 0.939270] Asymmetric key parser 'x509' registered
10588 09:29:19.457561 <6>[ 0.944417] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10589 09:29:19.460516 <6>[ 0.952029] io scheduler mq-deadline registered
10590 09:29:19.463722 <6>[ 0.956809] io scheduler kyber registered
10591 09:29:19.483237 <6>[ 0.973945] EINJ: ACPI disabled.
10592 09:29:19.516020 <4>[ 1.000094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 09:29:19.525750 <4>[ 1.010733] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 09:29:19.541257 <6>[ 1.031827] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10595 09:29:19.549614 <6>[ 1.039864] printk: console [ttyS0] disabled
10596 09:29:19.577818 <6>[ 1.064511] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10597 09:29:19.584454 <6>[ 1.073983] printk: console [ttyS0] enabled
10598 09:29:19.587589 <6>[ 1.073983] printk: console [ttyS0] enabled
10599 09:29:19.593761 <6>[ 1.082877] printk: bootconsole [mtk8250] disabled
10600 09:29:19.597354 <6>[ 1.082877] printk: bootconsole [mtk8250] disabled
10601 09:29:19.604270 <6>[ 1.094053] SuperH (H)SCI(F) driver initialized
10602 09:29:19.606731 <6>[ 1.099331] msm_serial: driver initialized
10603 09:29:19.621070 <6>[ 1.108335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10604 09:29:19.631253 <6>[ 1.116888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10605 09:29:19.638036 <6>[ 1.125430] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10606 09:29:19.647921 <6>[ 1.134059] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10607 09:29:19.657616 <6>[ 1.142776] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10608 09:29:19.664524 <6>[ 1.151491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10609 09:29:19.674646 <6>[ 1.160029] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10610 09:29:19.681046 <6>[ 1.168832] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10611 09:29:19.691079 <6>[ 1.177379] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10612 09:29:19.702536 <6>[ 1.192895] loop: module loaded
10613 09:29:19.709286 <6>[ 1.198956] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10614 09:29:19.731743 <4>[ 1.222281] mtk-pmic-keys: Failed to locate of_node [id: -1]
10615 09:29:19.739318 <6>[ 1.229142] megasas: 07.719.03.00-rc1
10616 09:29:19.748377 <6>[ 1.238659] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10617 09:29:19.755968 <6>[ 1.246435] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10618 09:29:19.773034 <6>[ 1.263160] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10619 09:29:19.829535 <6>[ 1.313093] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10620 09:29:21.316339 <6>[ 2.807312] Freeing initrd memory: 46400K
10621 09:29:21.326869 <6>[ 2.817774] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10622 09:29:21.338175 <6>[ 2.828717] tun: Universal TUN/TAP device driver, 1.6
10623 09:29:21.341106 <6>[ 2.834775] thunder_xcv, ver 1.0
10624 09:29:21.344524 <6>[ 2.838279] thunder_bgx, ver 1.0
10625 09:29:21.347972 <6>[ 2.841775] nicpf, ver 1.0
10626 09:29:21.357848 <6>[ 2.845789] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10627 09:29:21.361589 <6>[ 2.853265] hns3: Copyright (c) 2017 Huawei Corporation.
10628 09:29:21.367736 <6>[ 2.858868] hclge is initializing
10629 09:29:21.371373 <6>[ 2.862448] e1000: Intel(R) PRO/1000 Network Driver
10630 09:29:21.377894 <6>[ 2.867577] e1000: Copyright (c) 1999-2006 Intel Corporation.
10631 09:29:21.381244 <6>[ 2.873590] e1000e: Intel(R) PRO/1000 Network Driver
10632 09:29:21.387709 <6>[ 2.878806] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10633 09:29:21.394167 <6>[ 2.884994] igb: Intel(R) Gigabit Ethernet Network Driver
10634 09:29:21.401193 <6>[ 2.890644] igb: Copyright (c) 2007-2014 Intel Corporation.
10635 09:29:21.407882 <6>[ 2.896480] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10636 09:29:21.414053 <6>[ 2.902997] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10637 09:29:21.417823 <6>[ 2.909461] sky2: driver version 1.30
10638 09:29:21.424526 <6>[ 2.914445] VFIO - User Level meta-driver version: 0.3
10639 09:29:21.431858 <6>[ 2.922679] usbcore: registered new interface driver usb-storage
10640 09:29:21.438624 <6>[ 2.929130] usbcore: registered new device driver onboard-usb-hub
10641 09:29:21.447106 <6>[ 2.938239] mt6397-rtc mt6359-rtc: registered as rtc0
10642 09:29:21.457380 <6>[ 2.943707] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:29:22 UTC (1697794162)
10643 09:29:21.460460 <6>[ 2.953267] i2c_dev: i2c /dev entries driver
10644 09:29:21.477228 <6>[ 2.965045] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10645 09:29:21.496808 <6>[ 2.988048] cpu cpu0: EM: created perf domain
10646 09:29:21.500561 <6>[ 2.992993] cpu cpu4: EM: created perf domain
10647 09:29:21.507707 <6>[ 2.998598] sdhci: Secure Digital Host Controller Interface driver
10648 09:29:21.514075 <6>[ 3.005031] sdhci: Copyright(c) Pierre Ossman
10649 09:29:21.520768 <6>[ 3.009987] Synopsys Designware Multimedia Card Interface Driver
10650 09:29:21.527594 <6>[ 3.016618] sdhci-pltfm: SDHCI platform and OF driver helper
10651 09:29:21.530897 <6>[ 3.016669] mmc0: CQHCI version 5.10
10652 09:29:21.537756 <6>[ 3.026869] ledtrig-cpu: registered to indicate activity on CPUs
10653 09:29:21.544118 <6>[ 3.033970] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10654 09:29:21.550696 <6>[ 3.041027] usbcore: registered new interface driver usbhid
10655 09:29:21.554039 <6>[ 3.046850] usbhid: USB HID core driver
10656 09:29:21.560546 <6>[ 3.051011] spi_master spi0: will run message pump with realtime priority
10657 09:29:21.606821 <6>[ 3.091323] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10658 09:29:21.626542 <6>[ 3.106958] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10659 09:29:21.629695 <6>[ 3.120511] mmc0: Command Queue Engine enabled
10660 09:29:21.636795 <6>[ 3.121972] cros-ec-spi spi0.0: Chrome EC device registered
10661 09:29:21.643144 <6>[ 3.125238] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10662 09:29:21.646900 <6>[ 3.138367] mmcblk0: mmc0:0001 DA4128 116 GiB
10663 09:29:21.657749 <6>[ 3.145537] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10664 09:29:21.664285 <6>[ 3.148219] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10665 09:29:21.671227 <6>[ 3.156018] NET: Registered PF_PACKET protocol family
10666 09:29:21.674511 <6>[ 3.162199] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10667 09:29:21.680774 <6>[ 3.166174] 9pnet: Installing 9P2000 support
10668 09:29:21.684136 <6>[ 3.172014] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10669 09:29:21.690813 <5>[ 3.175860] Key type dns_resolver registered
10670 09:29:21.697241 <6>[ 3.181718] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10671 09:29:21.701003 <6>[ 3.186129] registered taskstats version 1
10672 09:29:21.704104 <5>[ 3.196468] Loading compiled-in X.509 certificates
10673 09:29:21.733909 <4>[ 3.218399] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 09:29:21.744065 <4>[ 3.229119] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10675 09:29:21.750841 <3>[ 3.239649] debugfs: File 'uA_load' in directory '/' already present!
10676 09:29:21.756854 <3>[ 3.246348] debugfs: File 'min_uV' in directory '/' already present!
10677 09:29:21.763829 <3>[ 3.253014] debugfs: File 'max_uV' in directory '/' already present!
10678 09:29:21.770186 <3>[ 3.259627] debugfs: File 'constraint_flags' in directory '/' already present!
10679 09:29:21.781043 <3>[ 3.268954] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10680 09:29:21.791114 <6>[ 3.281964] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10681 09:29:21.797469 <6>[ 3.288658] xhci-mtk 11200000.usb: xHCI Host Controller
10682 09:29:21.804217 <6>[ 3.294143] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10683 09:29:21.814915 <6>[ 3.302086] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10684 09:29:21.821095 <6>[ 3.311546] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10685 09:29:21.827694 <6>[ 3.317615] xhci-mtk 11200000.usb: xHCI Host Controller
10686 09:29:21.833942 <6>[ 3.323108] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10687 09:29:21.840780 <6>[ 3.330763] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10688 09:29:21.847834 <6>[ 3.338637] hub 1-0:1.0: USB hub found
10689 09:29:21.850919 <6>[ 3.342662] hub 1-0:1.0: 1 port detected
10690 09:29:21.860999 <6>[ 3.346941] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10691 09:29:21.864091 <6>[ 3.355722] hub 2-0:1.0: USB hub found
10692 09:29:21.867757 <6>[ 3.359746] hub 2-0:1.0: 1 port detected
10693 09:29:21.877139 <6>[ 3.368056] mtk-msdc 11f70000.mmc: Got CD GPIO
10694 09:29:21.886903 <6>[ 3.374307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10695 09:29:21.893665 <6>[ 3.382328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10696 09:29:21.904296 <4>[ 3.390218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10697 09:29:21.913812 <6>[ 3.399744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10698 09:29:21.920584 <6>[ 3.407825] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10699 09:29:21.926915 <6>[ 3.415851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10700 09:29:21.936993 <6>[ 3.423767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10701 09:29:21.943277 <6>[ 3.431590] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10702 09:29:21.953354 <6>[ 3.439408] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10703 09:29:21.963265 <6>[ 3.449790] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10704 09:29:21.970252 <6>[ 3.458148] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10705 09:29:21.979842 <6>[ 3.466493] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10706 09:29:21.986536 <6>[ 3.474832] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10707 09:29:21.996335 <6>[ 3.483170] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10708 09:29:22.003024 <6>[ 3.491518] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10709 09:29:22.013006 <6>[ 3.499857] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10710 09:29:22.019622 <6>[ 3.508196] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10711 09:29:22.029859 <6>[ 3.516534] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10712 09:29:22.036235 <6>[ 3.524872] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10713 09:29:22.046266 <6>[ 3.533210] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10714 09:29:22.052815 <6>[ 3.541549] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10715 09:29:22.062454 <6>[ 3.549888] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10716 09:29:22.072352 <6>[ 3.558226] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10717 09:29:22.079164 <6>[ 3.566565] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10718 09:29:22.085930 <6>[ 3.575311] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10719 09:29:22.092160 <6>[ 3.582471] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10720 09:29:22.098639 <6>[ 3.589224] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10721 09:29:22.105288 <6>[ 3.595980] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10722 09:29:22.111752 <6>[ 3.602924] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10723 09:29:22.121831 <6>[ 3.609786] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10724 09:29:22.131927 <6>[ 3.618918] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10725 09:29:22.142158 <6>[ 3.628042] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10726 09:29:22.151619 <6>[ 3.637337] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10727 09:29:22.161458 <6>[ 3.646805] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10728 09:29:22.168032 <6>[ 3.656273] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10729 09:29:22.178499 <6>[ 3.665392] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10730 09:29:22.187884 <6>[ 3.674861] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10731 09:29:22.197981 <6>[ 3.683987] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10732 09:29:22.208179 <6>[ 3.693282] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10733 09:29:22.217640 <6>[ 3.703442] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10734 09:29:22.227672 <6>[ 3.715596] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10735 09:29:22.275673 <6>[ 3.763299] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10736 09:29:22.430430 <6>[ 3.921275] hub 1-1:1.0: USB hub found
10737 09:29:22.433376 <6>[ 3.925796] hub 1-1:1.0: 4 ports detected
10738 09:29:22.555754 <6>[ 4.043426] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10739 09:29:22.582007 <6>[ 4.072958] hub 2-1:1.0: USB hub found
10740 09:29:22.584985 <6>[ 4.077424] hub 2-1:1.0: 3 ports detected
10741 09:29:22.755434 <6>[ 4.243308] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10742 09:29:22.888631 <6>[ 4.379596] hub 1-1.4:1.0: USB hub found
10743 09:29:22.891807 <6>[ 4.384331] hub 1-1.4:1.0: 2 ports detected
10744 09:29:22.967561 <6>[ 4.455565] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10745 09:29:23.187798 <6>[ 4.675348] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10746 09:29:23.379406 <6>[ 4.867317] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10747 09:29:34.520527 <6>[ 16.016323] ALSA device list:
10748 09:29:34.527272 <6>[ 16.019616] No soundcards found.
10749 09:29:34.534895 <6>[ 16.027587] Freeing unused kernel memory: 8384K
10750 09:29:34.538540 <6>[ 16.032637] Run /init as init process
10751 09:29:34.587382 <6>[ 16.079599] NET: Registered PF_INET6 protocol family
10752 09:29:34.593551 <6>[ 16.086028] Segment Routing with IPv6
10753 09:29:34.597152 <6>[ 16.089980] In-situ OAM (IOAM) with IPv6
10754 09:29:34.632392 <30>[ 16.104842] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10755 09:29:34.635624 <30>[ 16.128627] systemd[1]: Detected architecture arm64.
10756 09:29:34.635710
10757 09:29:34.642275 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10758 09:29:34.642357
10759 09:29:34.654677 <30>[ 16.147275] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10760 09:29:34.783833 <30>[ 16.273123] systemd[1]: Queued start job for default target Graphical Interface.
10761 09:29:34.811603 <30>[ 16.303984] systemd[1]: Created slice system-getty.slice.
10762 09:29:34.817931 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10763 09:29:34.835173 <30>[ 16.327656] systemd[1]: Created slice system-modprobe.slice.
10764 09:29:34.841875 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10765 09:29:34.859180 <30>[ 16.351827] systemd[1]: Created slice system-serial\x2dgetty.slice.
10766 09:29:34.869517 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10767 09:29:34.883688 <30>[ 16.376382] systemd[1]: Created slice User and Session Slice.
10768 09:29:34.891090 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10769 09:29:34.911171 <30>[ 16.399907] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10770 09:29:34.920373 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10771 09:29:34.938694 <30>[ 16.427918] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10772 09:29:34.945754 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10773 09:29:34.965329 <30>[ 16.451316] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10774 09:29:34.972617 <30>[ 16.463432] systemd[1]: Reached target Local Encrypted Volumes.
10775 09:29:34.979054 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10776 09:29:34.995562 <30>[ 16.487828] systemd[1]: Reached target Paths.
10777 09:29:34.998716 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10778 09:29:35.015012 <30>[ 16.507311] systemd[1]: Reached target Remote File Systems.
10779 09:29:35.021545 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10780 09:29:35.035035 <30>[ 16.527285] systemd[1]: Reached target Slices.
10781 09:29:35.038610 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10782 09:29:35.055502 <30>[ 16.547314] systemd[1]: Reached target Swap.
10783 09:29:35.058434 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10784 09:29:35.079114 <30>[ 16.567763] systemd[1]: Listening on initctl Compatibility Named Pipe.
10785 09:29:35.085997 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10786 09:29:35.100743 <30>[ 16.592754] systemd[1]: Listening on Journal Audit Socket.
10787 09:29:35.107705 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10788 09:29:35.124111 <30>[ 16.616471] systemd[1]: Listening on Journal Socket (/dev/log).
10789 09:29:35.130583 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10790 09:29:35.148316 <30>[ 16.640517] systemd[1]: Listening on Journal Socket.
10791 09:29:35.154925 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10792 09:29:35.171319 <30>[ 16.660022] systemd[1]: Listening on Network Service Netlink Socket.
10793 09:29:35.178001 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10794 09:29:35.193073 <30>[ 16.684592] systemd[1]: Listening on udev Control Socket.
10795 09:29:35.199332 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10796 09:29:35.216331 <30>[ 16.708363] systemd[1]: Listening on udev Kernel Socket.
10797 09:29:35.223196 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10798 09:29:35.275334 <30>[ 16.767565] systemd[1]: Mounting Huge Pages File System...
10799 09:29:35.281867 Mounting [0;1;39mHuge Pages File System[0m...
10800 09:29:35.298701 <30>[ 16.790791] systemd[1]: Mounting POSIX Message Queue File System...
10801 09:29:35.305431 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10802 09:29:35.327422 <30>[ 16.819264] systemd[1]: Mounting Kernel Debug File System...
10803 09:29:35.334128 Mounting [0;1;39mKernel Debug File System[0m...
10804 09:29:35.350352 <30>[ 16.839452] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10805 09:29:35.399343 <30>[ 16.887811] systemd[1]: Starting Create list of static device nodes for the current kernel...
10806 09:29:35.406212 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10807 09:29:35.428157 <30>[ 16.919744] systemd[1]: Starting Load Kernel Module configfs...
10808 09:29:35.434561 Starting [0;1;39mLoad Kernel Module configfs[0m...
10809 09:29:35.451014 <30>[ 16.942852] systemd[1]: Starting Load Kernel Module drm...
10810 09:29:35.457506 Starting [0;1;39mLoad Kernel Module drm[0m...
10811 09:29:35.474466 <30>[ 16.963446] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10812 09:29:35.519938 <30>[ 17.011696] systemd[1]: Starting Journal Service...
10813 09:29:35.522627 Starting [0;1;39mJournal Service[0m...
10814 09:29:35.542437 <30>[ 17.034330] systemd[1]: Starting Load Kernel Modules...
10815 09:29:35.548620 Starting [0;1;39mLoad Kernel Modules[0m...
10816 09:29:35.568611 <30>[ 17.057761] systemd[1]: Starting Remount Root and Kernel File Systems...
10817 09:29:35.575672 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10818 09:29:35.591709 <30>[ 17.083713] systemd[1]: Starting Coldplug All udev Devices...
10819 09:29:35.598451 Starting [0;1;39mColdplug All udev Devices[0m...
10820 09:29:35.615470 <30>[ 17.107526] systemd[1]: Started Journal Service.
10821 09:29:35.622024 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10822 09:29:35.639158 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10823 09:29:35.656282 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10824 09:29:35.673072 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10825 09:29:35.692890 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10826 09:29:35.710948 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10827 09:29:35.730197 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10828 09:29:35.748383 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10829 09:29:35.769416 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10830 09:29:35.783976 See 'systemctl status systemd-remount-fs.service' for details.
10831 09:29:35.828685 Mounting [0;1;39mKernel Configuration File System[0m...
10832 09:29:35.846153 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10833 09:29:35.859827 <46>[ 17.348581] systemd-journald[177]: Received client request to flush runtime journal.
10834 09:29:35.868346 Starting [0;1;39mLoad/Save Random Seed[0m...
10835 09:29:35.887041 Starting [0;1;39mApply Kernel Variables[0m...
10836 09:29:35.912129 Starting [0;1;39mCreate System Users[0m...
10837 09:29:35.934351 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10838 09:29:35.952182 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10839 09:29:35.972186 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10840 09:29:35.989139 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10841 09:29:36.005285 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10842 09:29:36.012825 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10843 09:29:36.051849 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10844 09:29:36.074863 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10845 09:29:36.087300 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10846 09:29:36.103227 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10847 09:29:36.124036 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10848 09:29:36.147965 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10849 09:29:36.175071 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10850 09:29:36.195625 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10851 09:29:36.253063 Starting [0;1;39mNetwork Service[0m...
10852 09:29:36.281060 Starting [0;1;39mNetwork Time Synchronization[0m...
10853 09:29:36.302611 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10854 09:29:36.348622 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10855 09:29:36.363720 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10856 09:29:36.396489 <6>[ 17.885864] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10857 09:29:36.403224 <3>[ 17.889688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 09:29:36.412924 <6>[ 17.896952] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10859 09:29:36.419691 <3>[ 17.901583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 09:29:36.429702 <3>[ 17.901591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 09:29:36.435986 <4>[ 17.912660] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10862 09:29:36.446045 <6>[ 17.918858] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10863 09:29:36.452323 <3>[ 17.934694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 09:29:36.458906 <4>[ 17.934717] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10865 09:29:36.465977 <6>[ 17.944729] usbcore: registered new interface driver r8152
10866 09:29:36.475942 <3>[ 17.950777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 09:29:36.482583 <3>[ 17.950783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 09:29:36.488996 <3>[ 17.950789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 09:29:36.498803 <3>[ 17.950792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 09:29:36.505579 <3>[ 17.959091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 09:29:36.515711 <6>[ 17.979706] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10872 09:29:36.522411 <3>[ 17.980203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 09:29:36.532159 <6>[ 17.999595] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10874 09:29:36.541817 <3>[ 18.004354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 09:29:36.545171 <6>[ 18.008594] mc: Linux media interface: v0.10
10876 09:29:36.551999 <6>[ 18.032960] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10877 09:29:36.561474 <3>[ 18.038276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 09:29:36.568632 <6>[ 18.043702] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10879 09:29:36.578353 <3>[ 18.049976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 09:29:36.588337 <6>[ 18.062285] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10881 09:29:36.594906 <3>[ 18.067152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 09:29:36.604768 <4>[ 18.067951] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10883 09:29:36.611063 <4>[ 18.067962] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10884 09:29:36.617766 <6>[ 18.068251] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10885 09:29:36.624547 <6>[ 18.068261] pci_bus 0000:00: root bus resource [bus 00-ff]
10886 09:29:36.631172 <6>[ 18.068268] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10887 09:29:36.641211 <6>[ 18.068274] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10888 09:29:36.647820 <6>[ 18.068345] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10889 09:29:36.654548 <6>[ 18.068370] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10890 09:29:36.660968 <6>[ 18.068480] pci 0000:00:00.0: supports D1 D2
10891 09:29:36.667637 <6>[ 18.068487] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10892 09:29:36.674489 <6>[ 18.078898] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10893 09:29:36.684271 <3>[ 18.084553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 09:29:36.691030 <3>[ 18.084562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 09:29:36.697456 <6>[ 18.112678] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10896 09:29:36.707242 <3>[ 18.116638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 09:29:36.713750 <6>[ 18.123588] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10898 09:29:36.720353 <3>[ 18.140361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 09:29:36.727074 <6>[ 18.141164] videodev: Linux video capture interface: v2.00
10900 09:29:36.733887 <6>[ 18.145972] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10901 09:29:36.740324 <6>[ 18.156098] usbcore: registered new interface driver cdc_ether
10902 09:29:36.746998 <6>[ 18.157764] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10903 09:29:36.753444 <6>[ 18.164663] r8152 2-1.3:1.0 eth0: v1.12.13
10904 09:29:36.757049 <6>[ 18.173002] pci 0000:01:00.0: supports D1 D2
10905 09:29:36.763408 <6>[ 18.185759] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10906 09:29:36.770126 <6>[ 18.189238] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10907 09:29:36.776549 <6>[ 18.225134] remoteproc remoteproc0: scp is available
10908 09:29:36.783480 <6>[ 18.225205] usbcore: registered new interface driver r8153_ecm
10909 09:29:36.789810 <4>[ 18.236692] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10910 09:29:36.796817 <4>[ 18.236692] Fallback method does not support PEC.
10911 09:29:36.800142 <6>[ 18.238621] remoteproc remoteproc0: powering up scp
10912 09:29:36.806589 <6>[ 18.247756] Bluetooth: Core ver 2.22
10913 09:29:36.812890 <6>[ 18.250114] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10914 09:29:36.820160 <6>[ 18.256278] NET: Registered PF_BLUETOOTH protocol family
10915 09:29:36.823052 <6>[ 18.261986] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10916 09:29:36.829792 <6>[ 18.268823] Bluetooth: HCI device and connection manager initialized
10917 09:29:36.839532 <6>[ 18.271791] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10918 09:29:36.846724 <6>[ 18.271841] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10919 09:29:36.853094 <6>[ 18.271846] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10920 09:29:36.862988 <6>[ 18.271858] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10921 09:29:36.869758 <6>[ 18.271871] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10922 09:29:36.879520 <6>[ 18.271884] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10923 09:29:36.882562 <6>[ 18.271896] pci 0000:00:00.0: PCI bridge to [bus 01]
10924 09:29:36.893456 <6>[ 18.271901] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10925 09:29:36.896797 <6>[ 18.296590] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10926 09:29:36.903277 <6>[ 18.299078] Bluetooth: HCI socket layer initialized
10927 09:29:36.909848 <6>[ 18.325229] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10928 09:29:36.916646 <6>[ 18.329011] Bluetooth: L2CAP socket layer initialized
10929 09:29:36.926552 <6>[ 18.338780] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10930 09:29:36.933427 <6>[ 18.340218] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10931 09:29:36.940070 <6>[ 18.340460] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10932 09:29:36.947254 <6>[ 18.344001] Bluetooth: SCO socket layer initialized
10933 09:29:36.950363 <6>[ 18.352710] usbcore: registered new interface driver uvcvideo
10934 09:29:36.957559 <6>[ 18.362082] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10935 09:29:36.964127 <6>[ 18.362505] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10936 09:29:36.974400 <3>[ 18.396439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 09:29:36.981136 <6>[ 18.399457] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10938 09:29:36.987577 <6>[ 18.399496] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10939 09:29:36.994360 <6>[ 18.399505] remoteproc remoteproc0: remote processor scp is now up
10940 09:29:37.001630 <6>[ 18.408663] usbcore: registered new interface driver btusb
10941 09:29:37.011640 <4>[ 18.409184] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10942 09:29:37.018237 <3>[ 18.409199] Bluetooth: hci0: Failed to load firmware file (-2)
10943 09:29:37.021571 <3>[ 18.409204] Bluetooth: hci0: Failed to set up firmware (-2)
10944 09:29:37.032459 <4>[ 18.409209] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10945 09:29:37.042395 <6>[ 18.414467] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10946 09:29:37.049125 <5>[ 18.429204] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10947 09:29:37.058852 <6>[ 18.451542] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10948 09:29:37.065369 <5>[ 18.476906] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10949 09:29:37.072323 <3>[ 18.480624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 09:29:37.082927 <4>[ 18.487630] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10951 09:29:37.089655 <3>[ 18.500967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 09:29:37.096023 <6>[ 18.508648] cfg80211: failed to load regulatory.db
10953 09:29:37.106316 <3>[ 18.526070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 09:29:37.112729 <3>[ 18.547587] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10955 09:29:37.122656 <3>[ 18.582198] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 09:29:37.129043 <6>[ 18.606793] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10957 09:29:37.136304 <6>[ 18.628385] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10958 09:29:37.146770 [[0;32m OK [<3>[ 18.635329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 09:29:37.153036 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10960 09:29:37.162631 <6>[ 18.655058] mt7921e 0000:01:00.0: ASIC revision: 79610010
10961 09:29:37.169346 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10962 09:29:37.180566 <3>[ 18.670154] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 09:29:37.187201 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10964 09:29:37.212496 <3>[ 18.702000] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 09:29:37.226062 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10966 09:29:37.244731 <3>[ 18.734272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 09:29:37.259248 Starting [0;1;39mNetwork Name Resolution[0m...
10968 09:29:37.274919 <4>[ 18.760328] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 09:29:37.288438 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10970 09:29:37.307930 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10971 09:29:37.335272 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10972 09:29:37.401429 <4>[ 18.887619] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 09:29:37.409195 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10974 09:29:37.519070 <4>[ 19.005401] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 09:29:37.535016 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10976 09:29:37.550709 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10977 09:29:37.573751 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10978 09:29:37.586307 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10979 09:29:37.610088 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10980 09:29:37.626997 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10981 09:29:37.640483 <4>[ 19.125653] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 09:29:37.643806 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10983 09:29:37.663735 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10984 09:29:37.674818 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10985 09:29:37.690531 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10986 09:29:37.710416 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10987 09:29:37.746307 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10988 09:29:37.760261 <4>[ 19.246657] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 09:29:37.786693 Starting [0;1;39mUser Login Management[0m...
10990 09:29:37.806606 Starting [0;1;39mPermit User Sessions[0m...
10991 09:29:37.826839 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10992 09:29:37.847643 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10993 09:29:37.879990 <4>[ 19.366435] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 09:29:37.889858 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10995 09:29:37.898282 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10996 09:29:37.919631 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10997 09:29:37.935619 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10998 09:29:37.955156 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10999 09:29:37.973108 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11000 09:29:38.000078 <4>[ 19.486051] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 09:29:38.006575 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11002 09:29:38.048856 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11003 09:29:38.084424 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11004 09:29:38.120869 <4>[ 19.606996] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11005 09:29:38.140533
11006 09:29:38.140639
11007 09:29:38.143894 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11008 09:29:38.143969
11009 09:29:38.147306 debian-bullseye-arm64 login: root (automatic login)
11010 09:29:38.147449
11011 09:29:38.147515
11012 09:29:38.163755 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
11013 09:29:38.163840
11014 09:29:38.170768 The programs included with the Debian GNU/Linux system are free software;
11015 09:29:38.176903 the exact distribution terms for each program are described in the
11016 09:29:38.180471 individual files in /usr/share/doc/*/copyright.
11017 09:29:38.180554
11018 09:29:38.187265 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 09:29:38.190134 permitted by applicable law.
11020 09:29:38.190760 Matched prompt #10: / #
11022 09:29:38.191071 Setting prompt string to ['/ #']
11023 09:29:38.191197 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11025 09:29:38.191510 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11026 09:29:38.191629 start: 2.2.6 expect-shell-connection (timeout 00:02:46) [common]
11027 09:29:38.191725 Setting prompt string to ['/ #']
11028 09:29:38.191813 Forcing a shell prompt, looking for ['/ #']
11030 09:29:38.242051 / #
11031 09:29:38.242165 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 09:29:38.242275 Waiting using forced prompt support (timeout 00:02:30)
11033 09:29:38.242408 <4>[ 19.726149] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11034 09:29:38.247928
11035 09:29:38.291762 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11036 09:29:38.291890 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
11037 09:29:38.291989 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11038 09:29:38.292076 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
11039 09:29:38.292160 end: 2 depthcharge-action (duration 00:02:14) [common]
11040 09:29:38.292249 start: 3 lava-test-retry (timeout 00:05:00) [common]
11041 09:29:38.292334 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11042 09:29:38.292409 Using namespace: common
11044 09:29:38.392709 / # #
11045 09:29:38.392842 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11046 09:29:38.392953 <6>[ 19.839717] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11047 09:29:38.393021 #<4>[ 19.847864] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11048 09:29:38.393084 <6>[ 19.848162] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11049 09:29:38.398203
11050 09:29:38.398474 Using /lava-11826783
11052 09:29:38.498802 / # export SHELL=/bin/sh
11053 09:29:38.498985 export SHELL=/bin/sh<3>[ 19.967549] mt7921e 0000:01:00.0: hardware init failed
11054 09:29:38.504173
11056 09:29:38.604655 / # . /lava-11826783/environment
11057 09:29:38.609841 . /lava-11826783/environment
11059 09:29:38.710373 / # /lava-11826783/bin/lava-test-runner /lava-11826783/0
11060 09:29:38.710509 Test shell timeout: 10s (minimum of the action and connection timeout)
11061 09:29:38.715854 /lava-11826783/bin/lava-test-runner /lava-11826783/0
11062 09:29:38.736871 + export TESTRUN_ID=0_cros-ec
11063 09:29:38.743572 +<8>[ 20.235611] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11826783_1.5.2.3.1>
11064 09:29:38.743832 Received signal: <STARTRUN> 0_cros-ec 11826783_1.5.2.3.1
11065 09:29:38.743907 Starting test lava.0_cros-ec (11826783_1.5.2.3.1)
11066 09:29:38.743994 Skipping test definition patterns.
11067 09:29:38.746715 cd /lava-11826783/0/tests/0_cros-ec
11068 09:29:38.750426 + cat uuid
11069 09:29:38.750509 + UUID=11826783_1.5.2.3.1
11070 09:29:38.750575 + set +x
11071 09:29:38.756874 + python3 -m cros.runners.lava_runner -v
11072 09:29:39.125101 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11073 09:29:39.131935 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11074 09:29:39.135620
11075 09:29:39.138604 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11077 09:29:39.142115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11078 09:29:39.148827 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11079 09:29:39.158486 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11080 09:29:39.158609
11081 09:29:39.162216 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11082 09:29:39.162315 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11083 09:29:39.168698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.660454] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11826783_1.5.2.3.1>
11084 09:29:39.168957 Received signal: <ENDRUN> 0_cros-ec 11826783_1.5.2.3.1
11085 09:29:39.169046 Ending use of test pattern.
11086 09:29:39.169120 Ending test lava.0_cros-ec (11826783_1.5.2.3.1), duration 0.43
11088 09:29:39.171741 valid RESULT=skip>
11089 09:29:39.175122 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11090 09:29:39.181514 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11091 09:29:39.181599
11092 09:29:39.188523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11093 09:29:39.188779 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11095 09:29:39.195115 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11096 09:29:39.201540 Checks the standard ABI for the main Embedded Controller. ... ok
11097 09:29:39.201646
11098 09:29:39.204818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11099 09:29:39.205083 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11101 09:29:39.211277 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11102 09:29:39.218136 Checks the main Embedded controller character device. ... ok
11103 09:29:39.218220
11104 09:29:39.224505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11105 09:29:39.224760 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11107 09:29:39.227562 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11108 09:29:39.234267 Checks basic comunication with the main Embedded controller. ... ok
11109 09:29:39.234377
11110 09:29:39.241042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11111 09:29:39.241298 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11113 09:29:39.244295 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11114 09:29:39.254404 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11115 09:29:39.254489
11116 09:29:39.257414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11117 09:29:39.257672 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11119 09:29:39.264215 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11120 09:29:39.273942 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11121 09:29:39.274027
11122 09:29:39.277468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11123 09:29:39.277730 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11125 09:29:39.283677 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11126 09:29:39.290390 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11127 09:29:39.290475
11128 09:29:39.297385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11129 09:29:39.297642 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11131 09:29:39.300572 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11132 09:29:39.310048 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11133 09:29:39.310131
11134 09:29:39.316821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11135 09:29:39.317076 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11137 09:29:39.320049 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11138 09:29:39.329966 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11139 09:29:39.330050
11140 09:29:39.336689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11141 09:29:39.336944 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11143 09:29:39.340164 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11144 09:29:39.346680 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11145 09:29:39.346765
11146 09:29:39.353288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11147 09:29:39.353543 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11149 09:29:39.359488 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11150 09:29:39.366398 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11151 09:29:39.366484
11152 09:29:39.372768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11153 09:29:39.373027 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11155 09:29:39.379371 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11156 09:29:39.386328 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11157 09:29:39.389382
11158 09:29:39.393163 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11160 09:29:39.396163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11161 09:29:39.399571 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11162 09:29:39.405717 Check the cros battery ABI. ... skipped 'No BAT found'
11163 09:29:39.405800
11164 09:29:39.412723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11165 09:29:39.412979 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11167 09:29:39.418885 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11168 09:29:39.425534 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11169 09:29:39.425618
11170 09:29:39.432877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11171 09:29:39.433132 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11173 09:29:39.438587 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11174 09:29:39.445294 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11175 09:29:39.445377
11176 09:29:39.448937 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11178 09:29:39.451857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11179 09:29:39.455555 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11180 09:29:39.462017 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11181 09:29:39.462099
11182 09:29:39.468570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11183 09:29:39.468651
11184 09:29:39.468886 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11186 09:29:39.475291 ----------------------------------------------------------------------
11187 09:29:39.478338 Ran 18 tests in 0.008s
11188 09:29:39.478420
11189 09:29:39.478485 OK (skipped=15)
11190 09:29:39.481547 + set +x
11191 09:29:39.481631 <LAVA_TEST_RUNNER EXIT>
11192 09:29:39.481867 ok: lava_test_shell seems to have completed
11193 09:29:39.482030 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11194 09:29:39.482128 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11195 09:29:39.482218 end: 3 lava-test-retry (duration 00:00:01) [common]
11196 09:29:39.482305 start: 4 finalize (timeout 00:07:20) [common]
11197 09:29:39.482392 start: 4.1 power-off (timeout 00:00:30) [common]
11198 09:29:39.482539 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11199 09:29:39.552735 >> Command sent successfully.
11200 09:29:39.555320 Returned 0 in 0 seconds
11201 09:29:39.655773 end: 4.1 power-off (duration 00:00:00) [common]
11203 09:29:39.656108 start: 4.2 read-feedback (timeout 00:07:20) [common]
11204 09:29:39.656372 Listened to connection for namespace 'common' for up to 1s
11205 09:29:40.657316 Finalising connection for namespace 'common'
11206 09:29:40.657489 Disconnecting from shell: Finalise
11207 09:29:40.657567 / #
11208 09:29:40.757889 end: 4.2 read-feedback (duration 00:00:01) [common]
11209 09:29:40.758053 end: 4 finalize (duration 00:00:01) [common]
11210 09:29:40.758165 Cleaning after the job
11211 09:29:40.758261 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/ramdisk
11212 09:29:40.765007 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/kernel
11213 09:29:40.773372 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/dtb
11214 09:29:40.773540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826783/tftp-deploy-fnbcpo20/modules
11215 09:29:40.780924 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826783
11216 09:29:40.899630 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826783
11217 09:29:40.899807 Job finished correctly