Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 22
- Kernel Errors: 32
- Errors: 0
- Boot result: PASS
1 09:30:37.389792 lava-dispatcher, installed at version: 2023.08
2 09:30:37.390001 start: 0 validate
3 09:30:37.390136 Start time: 2023-10-20 09:30:37.390128+00:00 (UTC)
4 09:30:37.390255 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:30:37.390393 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:30:37.650132 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:30:37.650302 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:30:37.916075 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:30:37.916302 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:30:38.182513 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:30:38.182692 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:30:38.449454 validate duration: 1.06
14 09:30:38.449750 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:30:38.449855 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:30:38.450009 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:30:38.450133 Not decompressing ramdisk as can be used compressed.
18 09:30:38.450217 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 09:30:38.450278 saving as /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/ramdisk/rootfs.cpio.gz
20 09:30:38.450340 total size: 43284872 (41 MB)
21 09:30:38.451695 progress 0 % (0 MB)
22 09:30:38.463885 progress 5 % (2 MB)
23 09:30:38.475703 progress 10 % (4 MB)
24 09:30:38.487139 progress 15 % (6 MB)
25 09:30:38.498629 progress 20 % (8 MB)
26 09:30:38.510022 progress 25 % (10 MB)
27 09:30:38.521606 progress 30 % (12 MB)
28 09:30:38.533289 progress 35 % (14 MB)
29 09:30:38.544828 progress 40 % (16 MB)
30 09:30:38.557040 progress 45 % (18 MB)
31 09:30:38.568449 progress 50 % (20 MB)
32 09:30:38.580063 progress 55 % (22 MB)
33 09:30:38.591549 progress 60 % (24 MB)
34 09:30:38.603289 progress 65 % (26 MB)
35 09:30:38.615138 progress 70 % (28 MB)
36 09:30:38.626589 progress 75 % (30 MB)
37 09:30:38.638182 progress 80 % (33 MB)
38 09:30:38.649879 progress 85 % (35 MB)
39 09:30:38.661505 progress 90 % (37 MB)
40 09:30:38.672886 progress 95 % (39 MB)
41 09:30:38.684095 progress 100 % (41 MB)
42 09:30:38.684359 41 MB downloaded in 0.23 s (176.39 MB/s)
43 09:30:38.684526 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:30:38.684771 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:30:38.684858 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:30:38.684942 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:30:38.685080 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:30:38.685150 saving as /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/kernel/Image
50 09:30:38.685212 total size: 49236480 (46 MB)
51 09:30:38.685273 No compression specified
52 09:30:38.686398 progress 0 % (0 MB)
53 09:30:38.699256 progress 5 % (2 MB)
54 09:30:38.712105 progress 10 % (4 MB)
55 09:30:38.725000 progress 15 % (7 MB)
56 09:30:38.738061 progress 20 % (9 MB)
57 09:30:38.751244 progress 25 % (11 MB)
58 09:30:38.764397 progress 30 % (14 MB)
59 09:30:38.777663 progress 35 % (16 MB)
60 09:30:38.790860 progress 40 % (18 MB)
61 09:30:38.803685 progress 45 % (21 MB)
62 09:30:38.816524 progress 50 % (23 MB)
63 09:30:38.829740 progress 55 % (25 MB)
64 09:30:38.842913 progress 60 % (28 MB)
65 09:30:38.856010 progress 65 % (30 MB)
66 09:30:38.869120 progress 70 % (32 MB)
67 09:30:38.882212 progress 75 % (35 MB)
68 09:30:38.895498 progress 80 % (37 MB)
69 09:30:38.908871 progress 85 % (39 MB)
70 09:30:38.922015 progress 90 % (42 MB)
71 09:30:38.934925 progress 95 % (44 MB)
72 09:30:38.947950 progress 100 % (46 MB)
73 09:30:38.948158 46 MB downloaded in 0.26 s (178.58 MB/s)
74 09:30:38.948348 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:30:38.948605 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:30:38.948689 start: 1.3 download-retry (timeout 00:10:00) [common]
78 09:30:38.948772 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 09:30:38.948908 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:30:38.948980 saving as /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/dtb/mt8192-asurada-spherion-r0.dtb
81 09:30:38.949040 total size: 47278 (0 MB)
82 09:30:38.949131 No compression specified
83 09:30:38.950450 progress 69 % (0 MB)
84 09:30:38.950792 progress 100 % (0 MB)
85 09:30:38.950997 0 MB downloaded in 0.00 s (23.08 MB/s)
86 09:30:38.951174 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:30:38.951599 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:30:38.951738 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:30:38.951821 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:30:38.951934 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:30:38.952029 saving as /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/modules/modules.tar
93 09:30:38.952087 total size: 8614716 (8 MB)
94 09:30:38.952147 Using unxz to decompress xz
95 09:30:38.956436 progress 0 % (0 MB)
96 09:30:38.977701 progress 5 % (0 MB)
97 09:30:39.002541 progress 10 % (0 MB)
98 09:30:39.027515 progress 15 % (1 MB)
99 09:30:39.052307 progress 20 % (1 MB)
100 09:30:39.077837 progress 25 % (2 MB)
101 09:30:39.105796 progress 30 % (2 MB)
102 09:30:39.132814 progress 35 % (2 MB)
103 09:30:39.156817 progress 40 % (3 MB)
104 09:30:39.181238 progress 45 % (3 MB)
105 09:30:39.206891 progress 50 % (4 MB)
106 09:30:39.232021 progress 55 % (4 MB)
107 09:30:39.257504 progress 60 % (4 MB)
108 09:30:39.283371 progress 65 % (5 MB)
109 09:30:39.310749 progress 70 % (5 MB)
110 09:30:39.334577 progress 75 % (6 MB)
111 09:30:39.361880 progress 80 % (6 MB)
112 09:30:39.388220 progress 85 % (7 MB)
113 09:30:39.413547 progress 90 % (7 MB)
114 09:30:39.443601 progress 95 % (7 MB)
115 09:30:39.471963 progress 100 % (8 MB)
116 09:30:39.478348 8 MB downloaded in 0.53 s (15.61 MB/s)
117 09:30:39.478688 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:30:39.479119 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:30:39.479272 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:30:39.479448 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:30:39.479597 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:30:39.479713 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:30:39.479950 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko
125 09:30:39.480118 makedir: /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin
126 09:30:39.480269 makedir: /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/tests
127 09:30:39.480435 makedir: /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/results
128 09:30:39.480614 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-add-keys
129 09:30:39.480803 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-add-sources
130 09:30:39.480941 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-background-process-start
131 09:30:39.481084 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-background-process-stop
132 09:30:39.481223 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-common-functions
133 09:30:39.481352 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-echo-ipv4
134 09:30:39.481531 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-install-packages
135 09:30:39.481682 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-installed-packages
136 09:30:39.481835 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-os-build
137 09:30:39.482007 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-probe-channel
138 09:30:39.482164 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-probe-ip
139 09:30:39.482348 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-target-ip
140 09:30:39.482507 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-target-mac
141 09:30:39.482675 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-target-storage
142 09:30:39.482822 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-case
143 09:30:39.482951 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-event
144 09:30:39.483088 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-feedback
145 09:30:39.483223 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-raise
146 09:30:39.483351 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-reference
147 09:30:39.483500 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-runner
148 09:30:39.483628 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-set
149 09:30:39.483767 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-test-shell
150 09:30:39.483942 Updating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-install-packages (oe)
151 09:30:39.484128 Updating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/bin/lava-installed-packages (oe)
152 09:30:39.484295 Creating /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/environment
153 09:30:39.484438 LAVA metadata
154 09:30:39.484562 - LAVA_JOB_ID=11826824
155 09:30:39.484645 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:30:39.484803 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:30:39.484884 skipped lava-vland-overlay
158 09:30:39.484972 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:30:39.485058 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:30:39.485133 skipped lava-multinode-overlay
161 09:30:39.485212 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:30:39.485304 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:30:39.485381 Loading test definitions
164 09:30:39.485496 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:30:39.485621 Using /lava-11826824 at stage 0
166 09:30:39.485957 uuid=11826824_1.5.2.3.1 testdef=None
167 09:30:39.486047 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:30:39.486143 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:30:39.486922 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:30:39.487299 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:30:39.488129 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:30:39.488532 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:30:39.489218 runner path: /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/0/tests/0_igt-gpu-panfrost test_uuid 11826824_1.5.2.3.1
176 09:30:39.489407 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:30:39.489768 Creating lava-test-runner.conf files
179 09:30:39.489879 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826824/lava-overlay-b6b04_ko/lava-11826824/0 for stage 0
180 09:30:39.490006 - 0_igt-gpu-panfrost
181 09:30:39.490148 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:30:39.490267 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:30:39.498460 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:30:39.498581 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:30:39.498670 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:30:39.498764 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:30:39.498868 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:30:40.968436 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:30:40.968858 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 09:30:40.969067 extracting modules file /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826824/extract-overlay-ramdisk-hz5afm23/ramdisk
191 09:30:41.233769 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:30:41.233957 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 09:30:41.234085 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826824/compress-overlay-_i62_twt/overlay-1.5.2.4.tar.gz to ramdisk
194 09:30:41.234197 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826824/compress-overlay-_i62_twt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826824/extract-overlay-ramdisk-hz5afm23/ramdisk
195 09:30:41.244603 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:30:41.244752 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 09:30:41.244923 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:30:41.245062 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 09:30:41.245179 Building ramdisk /var/lib/lava/dispatcher/tmp/11826824/extract-overlay-ramdisk-hz5afm23/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826824/extract-overlay-ramdisk-hz5afm23/ramdisk
200 09:30:42.184629 >> 369946 blocks
201 09:30:48.047865 rename /var/lib/lava/dispatcher/tmp/11826824/extract-overlay-ramdisk-hz5afm23/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/ramdisk/ramdisk.cpio.gz
202 09:30:48.048339 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 09:30:48.048463 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 09:30:48.048568 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 09:30:48.048674 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/kernel/Image'
206 09:31:00.875804 Returned 0 in 12 seconds
207 09:31:00.976438 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/kernel/image.itb
208 09:31:01.930974 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:31:01.931349 output: Created: Fri Oct 20 10:31:01 2023
210 09:31:01.931463 output: Image 0 (kernel-1)
211 09:31:01.931534 output: Description:
212 09:31:01.931597 output: Created: Fri Oct 20 10:31:01 2023
213 09:31:01.931658 output: Type: Kernel Image
214 09:31:01.931719 output: Compression: lzma compressed
215 09:31:01.931781 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
216 09:31:01.931841 output: Architecture: AArch64
217 09:31:01.931900 output: OS: Linux
218 09:31:01.931957 output: Load Address: 0x00000000
219 09:31:01.932017 output: Entry Point: 0x00000000
220 09:31:01.932070 output: Hash algo: crc32
221 09:31:01.932123 output: Hash value: 05d3904e
222 09:31:01.932176 output: Image 1 (fdt-1)
223 09:31:01.932232 output: Description: mt8192-asurada-spherion-r0
224 09:31:01.932284 output: Created: Fri Oct 20 10:31:01 2023
225 09:31:01.932337 output: Type: Flat Device Tree
226 09:31:01.932390 output: Compression: uncompressed
227 09:31:01.932443 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:31:01.932496 output: Architecture: AArch64
229 09:31:01.932548 output: Hash algo: crc32
230 09:31:01.932600 output: Hash value: cc4352de
231 09:31:01.932653 output: Image 2 (ramdisk-1)
232 09:31:01.932705 output: Description: unavailable
233 09:31:01.932757 output: Created: Fri Oct 20 10:31:01 2023
234 09:31:01.932810 output: Type: RAMDisk Image
235 09:31:01.932863 output: Compression: Unknown Compression
236 09:31:01.932915 output: Data Size: 56404874 Bytes = 55082.88 KiB = 53.79 MiB
237 09:31:01.932967 output: Architecture: AArch64
238 09:31:01.933019 output: OS: Linux
239 09:31:01.933072 output: Load Address: unavailable
240 09:31:01.933124 output: Entry Point: unavailable
241 09:31:01.933177 output: Hash algo: crc32
242 09:31:01.933229 output: Hash value: 1a99c7b2
243 09:31:01.933280 output: Default Configuration: 'conf-1'
244 09:31:01.933332 output: Configuration 0 (conf-1)
245 09:31:01.933384 output: Description: mt8192-asurada-spherion-r0
246 09:31:01.933436 output: Kernel: kernel-1
247 09:31:01.933487 output: Init Ramdisk: ramdisk-1
248 09:31:01.933539 output: FDT: fdt-1
249 09:31:01.933591 output: Loadables: kernel-1
250 09:31:01.933644 output:
251 09:31:01.933843 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:31:01.933939 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:31:01.934041 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 09:31:01.934136 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 09:31:01.934215 No LXC device requested
256 09:31:01.934295 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:31:01.934382 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 09:31:01.934462 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:31:01.934531 Checking files for TFTP limit of 4294967296 bytes.
260 09:31:01.935046 end: 1 tftp-deploy (duration 00:00:23) [common]
261 09:31:01.935147 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:31:01.935236 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:31:01.935359 substitutions:
264 09:31:01.935468 - {DTB}: 11826824/tftp-deploy-qyjri2xd/dtb/mt8192-asurada-spherion-r0.dtb
265 09:31:01.935531 - {INITRD}: 11826824/tftp-deploy-qyjri2xd/ramdisk/ramdisk.cpio.gz
266 09:31:01.935592 - {KERNEL}: 11826824/tftp-deploy-qyjri2xd/kernel/Image
267 09:31:01.935650 - {LAVA_MAC}: None
268 09:31:01.935706 - {PRESEED_CONFIG}: None
269 09:31:01.935762 - {PRESEED_LOCAL}: None
270 09:31:01.935816 - {RAMDISK}: 11826824/tftp-deploy-qyjri2xd/ramdisk/ramdisk.cpio.gz
271 09:31:01.935871 - {ROOT_PART}: None
272 09:31:01.935924 - {ROOT}: None
273 09:31:01.935978 - {SERVER_IP}: 192.168.201.1
274 09:31:01.936031 - {TEE}: None
275 09:31:01.936084 Parsed boot commands:
276 09:31:01.936138 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:31:01.936318 Parsed boot commands: tftpboot 192.168.201.1 11826824/tftp-deploy-qyjri2xd/kernel/image.itb 11826824/tftp-deploy-qyjri2xd/kernel/cmdline
278 09:31:01.936407 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:31:01.936491 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:31:01.936584 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:31:01.936670 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:31:01.936740 Not connected, no need to disconnect.
283 09:31:01.936814 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:31:01.936895 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:31:01.936966 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 09:31:01.941041 Setting prompt string to ['lava-test: # ']
287 09:31:01.941415 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:31:01.941525 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:31:01.941623 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:31:01.941712 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:31:01.941945 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 09:31:07.078738 >> Command sent successfully.
293 09:31:07.081166 Returned 0 in 5 seconds
294 09:31:07.181543 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:31:07.181879 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:31:07.181975 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:31:07.182063 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:31:07.182129 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:31:07.182193 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:31:07.182457 [Enter `^Ec?' for help]
302 09:31:07.354259
303 09:31:07.354421
304 09:31:07.354493 F0: 102B 0000
305 09:31:07.354561
306 09:31:07.354622 F3: 1001 0000 [0200]
307 09:31:07.357529
308 09:31:07.357614 F3: 1001 0000
309 09:31:07.357681
310 09:31:07.357742 F7: 102D 0000
311 09:31:07.357801
312 09:31:07.360952 F1: 0000 0000
313 09:31:07.361036
314 09:31:07.361101 V0: 0000 0000 [0001]
315 09:31:07.361165
316 09:31:07.363706 00: 0007 8000
317 09:31:07.363793
318 09:31:07.363858 01: 0000 0000
319 09:31:07.363921
320 09:31:07.367520 BP: 0C00 0209 [0000]
321 09:31:07.367602
322 09:31:07.367667 G0: 1182 0000
323 09:31:07.367729
324 09:31:07.370791 EC: 0000 0021 [4000]
325 09:31:07.370873
326 09:31:07.370939 S7: 0000 0000 [0000]
327 09:31:07.371000
328 09:31:07.374639 CC: 0000 0000 [0001]
329 09:31:07.374721
330 09:31:07.374786 T0: 0000 0040 [010F]
331 09:31:07.374846
332 09:31:07.374904 Jump to BL
333 09:31:07.374960
334 09:31:07.401313
335 09:31:07.401436
336 09:31:07.401503
337 09:31:07.408501 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:31:07.411879 ARM64: Exception handlers installed.
339 09:31:07.415636 ARM64: Testing exception
340 09:31:07.418953 ARM64: Done test exception
341 09:31:07.425564 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:31:07.436058 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:31:07.442928 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:31:07.453028 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:31:07.459335 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:31:07.466069 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:31:07.478074 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:31:07.484898 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:31:07.504047 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:31:07.507358 WDT: Last reset was cold boot
351 09:31:07.510725 SPI1(PAD0) initialized at 2873684 Hz
352 09:31:07.513539 SPI5(PAD0) initialized at 992727 Hz
353 09:31:07.517164 VBOOT: Loading verstage.
354 09:31:07.523955 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:31:07.526945 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:31:07.530648 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:31:07.534162 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:31:07.541338 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:31:07.548004 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:31:07.558915 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 09:31:07.559001
362 09:31:07.559066
363 09:31:07.568869 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:31:07.572278 ARM64: Exception handlers installed.
365 09:31:07.575668 ARM64: Testing exception
366 09:31:07.575752 ARM64: Done test exception
367 09:31:07.583252 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:31:07.586465 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:31:07.600082 Probing TPM: . done!
370 09:31:07.600173 TPM ready after 0 ms
371 09:31:07.606624 Connected to device vid:did:rid of 1ae0:0028:00
372 09:31:07.613301 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 09:31:07.655735 Initialized TPM device CR50 revision 0
374 09:31:07.667722 tlcl_send_startup: Startup return code is 0
375 09:31:07.667831 TPM: setup succeeded
376 09:31:07.678928 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:31:07.688217 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:31:07.699316 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:31:07.708634 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:31:07.712051 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:31:07.715803 in-header: 03 07 00 00 08 00 00 00
382 09:31:07.719569 in-data: aa e4 47 04 13 02 00 00
383 09:31:07.723323 Chrome EC: UHEPI supported
384 09:31:07.730436 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:31:07.734081 in-header: 03 9d 00 00 08 00 00 00
386 09:31:07.737864 in-data: 10 20 20 08 00 00 00 00
387 09:31:07.737975 Phase 1
388 09:31:07.741485 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:31:07.748802 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:31:07.752858 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:31:07.755949 Recovery requested (1009000e)
392 09:31:07.762747 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:31:07.768880 tlcl_extend: response is 0
394 09:31:07.776822 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:31:07.781790 tlcl_extend: response is 0
396 09:31:07.789045 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:31:07.809628 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 09:31:07.816705 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 09:31:07.816796
400 09:31:07.816861
401 09:31:07.828007 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:31:07.828098 ARM64: Exception handlers installed.
403 09:31:07.831379 ARM64: Testing exception
404 09:31:07.834782 ARM64: Done test exception
405 09:31:07.855139 pmic_efuse_setting: Set efuses in 11 msecs
406 09:31:07.858662 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:31:07.862312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:31:07.869898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:31:07.874070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:31:07.877789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:31:07.884745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:31:07.888477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:31:07.892195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:31:07.896420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:31:07.903058 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:31:07.906050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:31:07.912927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:31:07.916271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:31:07.919357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:31:07.926464 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:31:07.933126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:31:07.939687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:31:07.943032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:31:07.949772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:31:07.956915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:31:07.961067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:31:07.967889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:31:07.971003 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:31:07.977654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:31:07.981405 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:31:07.988823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:31:07.995112 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:31:07.998725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:31:08.002438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:31:08.009120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:31:08.012374 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:31:08.019640 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:31:08.023427 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:31:08.026853 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:31:08.034826 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:31:08.038424 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:31:08.045178 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:31:08.048125 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:31:08.054990 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:31:08.058139 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:31:08.061559 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:31:08.068194 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:31:08.071880 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:31:08.075237 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:31:08.078434 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:31:08.085216 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:31:08.088264 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:31:08.091681 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:31:08.098289 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:31:08.101654 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:31:08.105003 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:31:08.108114 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:31:08.118308 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:31:08.125028 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:31:08.131503 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:31:08.138251 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:31:08.148116 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:31:08.151348 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:31:08.154863 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:31:08.161429 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:31:08.168217 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2c
467 09:31:08.171439 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:31:08.179066 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 09:31:08.182309 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:31:08.191909 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 09:31:08.195128 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 09:31:08.201829 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 09:31:08.205323 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 09:31:08.208636 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 09:31:08.212001 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 09:31:08.215274 ADC[4]: Raw value=897780 ID=7
477 09:31:08.219222 ADC[3]: Raw value=213440 ID=1
478 09:31:08.219305 RAM Code: 0x71
479 09:31:08.225392 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 09:31:08.228798 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 09:31:08.239070 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 09:31:08.246332 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 09:31:08.249728 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 09:31:08.252926 in-header: 03 07 00 00 08 00 00 00
485 09:31:08.256047 in-data: aa e4 47 04 13 02 00 00
486 09:31:08.256129 Chrome EC: UHEPI supported
487 09:31:08.262512 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 09:31:08.266769 in-header: 03 d5 00 00 08 00 00 00
489 09:31:08.270735 in-data: 98 20 60 08 00 00 00 00
490 09:31:08.274252 MRC: failed to locate region type 0.
491 09:31:08.281444 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 09:31:08.284893 DRAM-K: Running full calibration
493 09:31:08.291529 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 09:31:08.291613 header.status = 0x0
495 09:31:08.294838 header.version = 0x6 (expected: 0x6)
496 09:31:08.298256 header.size = 0xd00 (expected: 0xd00)
497 09:31:08.301970 header.flags = 0x0
498 09:31:08.305375 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 09:31:08.324448 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
500 09:31:08.331018 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 09:31:08.334301 dram_init: ddr_geometry: 2
502 09:31:08.337667 [EMI] MDL number = 2
503 09:31:08.337749 [EMI] Get MDL freq = 0
504 09:31:08.341038 dram_init: ddr_type: 0
505 09:31:08.341120 is_discrete_lpddr4: 1
506 09:31:08.344386 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 09:31:08.344468
508 09:31:08.344533
509 09:31:08.347754 [Bian_co] ETT version 0.0.0.1
510 09:31:08.354443 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 09:31:08.354525
512 09:31:08.358184 dramc_set_vcore_voltage set vcore to 650000
513 09:31:08.358267 Read voltage for 800, 4
514 09:31:08.360909 Vio18 = 0
515 09:31:08.360991 Vcore = 650000
516 09:31:08.361057 Vdram = 0
517 09:31:08.364282 Vddq = 0
518 09:31:08.364363 Vmddr = 0
519 09:31:08.367488 dram_init: config_dvfs: 1
520 09:31:08.370854 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 09:31:08.377609 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 09:31:08.380805 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 09:31:08.384416 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 09:31:08.387497 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 09:31:08.391010 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 09:31:08.394066 MEM_TYPE=3, freq_sel=18
527 09:31:08.397432 sv_algorithm_assistance_LP4_1600
528 09:31:08.400956 ============ PULL DRAM RESETB DOWN ============
529 09:31:08.404066 ========== PULL DRAM RESETB DOWN end =========
530 09:31:08.410777 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 09:31:08.414544 ===================================
532 09:31:08.417303 LPDDR4 DRAM CONFIGURATION
533 09:31:08.420493 ===================================
534 09:31:08.420576 EX_ROW_EN[0] = 0x0
535 09:31:08.423983 EX_ROW_EN[1] = 0x0
536 09:31:08.424066 LP4Y_EN = 0x0
537 09:31:08.427352 WORK_FSP = 0x0
538 09:31:08.427443 WL = 0x2
539 09:31:08.430526 RL = 0x2
540 09:31:08.430609 BL = 0x2
541 09:31:08.434129 RPST = 0x0
542 09:31:08.434211 RD_PRE = 0x0
543 09:31:08.437228 WR_PRE = 0x1
544 09:31:08.437317 WR_PST = 0x0
545 09:31:08.440608 DBI_WR = 0x0
546 09:31:08.440692 DBI_RD = 0x0
547 09:31:08.444218 OTF = 0x1
548 09:31:08.447549 ===================================
549 09:31:08.451082 ===================================
550 09:31:08.451165 ANA top config
551 09:31:08.454913 ===================================
552 09:31:08.458853 DLL_ASYNC_EN = 0
553 09:31:08.462152 ALL_SLAVE_EN = 1
554 09:31:08.462235 NEW_RANK_MODE = 1
555 09:31:08.465548 DLL_IDLE_MODE = 1
556 09:31:08.469786 LP45_APHY_COMB_EN = 1
557 09:31:08.469868 TX_ODT_DIS = 1
558 09:31:08.473101 NEW_8X_MODE = 1
559 09:31:08.477065 ===================================
560 09:31:08.480988 ===================================
561 09:31:08.484709 data_rate = 1600
562 09:31:08.484791 CKR = 1
563 09:31:08.488112 DQ_P2S_RATIO = 8
564 09:31:08.491998 ===================================
565 09:31:08.496049 CA_P2S_RATIO = 8
566 09:31:08.496132 DQ_CA_OPEN = 0
567 09:31:08.499540 DQ_SEMI_OPEN = 0
568 09:31:08.503096 CA_SEMI_OPEN = 0
569 09:31:08.507124 CA_FULL_RATE = 0
570 09:31:08.507206 DQ_CKDIV4_EN = 1
571 09:31:08.510698 CA_CKDIV4_EN = 1
572 09:31:08.514230 CA_PREDIV_EN = 0
573 09:31:08.518034 PH8_DLY = 0
574 09:31:08.518118 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 09:31:08.521853 DQ_AAMCK_DIV = 4
576 09:31:08.525323 CA_AAMCK_DIV = 4
577 09:31:08.528761 CA_ADMCK_DIV = 4
578 09:31:08.528844 DQ_TRACK_CA_EN = 0
579 09:31:08.533090 CA_PICK = 800
580 09:31:08.536255 CA_MCKIO = 800
581 09:31:08.539270 MCKIO_SEMI = 0
582 09:31:08.542917 PLL_FREQ = 3068
583 09:31:08.543002 DQ_UI_PI_RATIO = 32
584 09:31:08.546191 CA_UI_PI_RATIO = 0
585 09:31:08.549388 ===================================
586 09:31:08.553019 ===================================
587 09:31:08.556398 memory_type:LPDDR4
588 09:31:08.559556 GP_NUM : 10
589 09:31:08.559639 SRAM_EN : 1
590 09:31:08.563068 MD32_EN : 0
591 09:31:08.566390 ===================================
592 09:31:08.569785 [ANA_INIT] >>>>>>>>>>>>>>
593 09:31:08.569867 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 09:31:08.573025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 09:31:08.576544 ===================================
596 09:31:08.579884 data_rate = 1600,PCW = 0X7600
597 09:31:08.582901 ===================================
598 09:31:08.586455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 09:31:08.592743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 09:31:08.599727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 09:31:08.602655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 09:31:08.606451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 09:31:08.609892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 09:31:08.613321 [ANA_INIT] flow start
605 09:31:08.613403 [ANA_INIT] PLL >>>>>>>>
606 09:31:08.616919 [ANA_INIT] PLL <<<<<<<<
607 09:31:08.620340 [ANA_INIT] MIDPI >>>>>>>>
608 09:31:08.620422 [ANA_INIT] MIDPI <<<<<<<<
609 09:31:08.624045 [ANA_INIT] DLL >>>>>>>>
610 09:31:08.624128 [ANA_INIT] flow end
611 09:31:08.627893 ============ LP4 DIFF to SE enter ============
612 09:31:08.635523 ============ LP4 DIFF to SE exit ============
613 09:31:08.635634 [ANA_INIT] <<<<<<<<<<<<<
614 09:31:08.638925 [Flow] Enable top DCM control >>>>>
615 09:31:08.642304 [Flow] Enable top DCM control <<<<<
616 09:31:08.645947 Enable DLL master slave shuffle
617 09:31:08.650464 ==============================================================
618 09:31:08.653916 Gating Mode config
619 09:31:08.656558 ==============================================================
620 09:31:08.659672 Config description:
621 09:31:08.669934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 09:31:08.676246 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 09:31:08.679597 SELPH_MODE 0: By rank 1: By Phase
624 09:31:08.686650 ==============================================================
625 09:31:08.689593 GAT_TRACK_EN = 1
626 09:31:08.693378 RX_GATING_MODE = 2
627 09:31:08.696452 RX_GATING_TRACK_MODE = 2
628 09:31:08.699643 SELPH_MODE = 1
629 09:31:08.702898 PICG_EARLY_EN = 1
630 09:31:08.702980 VALID_LAT_VALUE = 1
631 09:31:08.709581 ==============================================================
632 09:31:08.713047 Enter into Gating configuration >>>>
633 09:31:08.716388 Exit from Gating configuration <<<<
634 09:31:08.719659 Enter into DVFS_PRE_config >>>>>
635 09:31:08.729611 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 09:31:08.733193 Exit from DVFS_PRE_config <<<<<
637 09:31:08.736366 Enter into PICG configuration >>>>
638 09:31:08.739826 Exit from PICG configuration <<<<
639 09:31:08.743172 [RX_INPUT] configuration >>>>>
640 09:31:08.746324 [RX_INPUT] configuration <<<<<
641 09:31:08.749873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 09:31:08.756292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 09:31:08.763335 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 09:31:08.770114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 09:31:08.776746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 09:31:08.779871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 09:31:08.786463 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 09:31:08.789707 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 09:31:08.792920 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 09:31:08.796360 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 09:31:08.803007 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 09:31:08.806068 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 09:31:08.809844 ===================================
654 09:31:08.813135 LPDDR4 DRAM CONFIGURATION
655 09:31:08.816484 ===================================
656 09:31:08.816567 EX_ROW_EN[0] = 0x0
657 09:31:08.819808 EX_ROW_EN[1] = 0x0
658 09:31:08.819891 LP4Y_EN = 0x0
659 09:31:08.823016 WORK_FSP = 0x0
660 09:31:08.823098 WL = 0x2
661 09:31:08.826575 RL = 0x2
662 09:31:08.826657 BL = 0x2
663 09:31:08.829998 RPST = 0x0
664 09:31:08.830080 RD_PRE = 0x0
665 09:31:08.833064 WR_PRE = 0x1
666 09:31:08.833146 WR_PST = 0x0
667 09:31:08.836512 DBI_WR = 0x0
668 09:31:08.836594 DBI_RD = 0x0
669 09:31:08.839774 OTF = 0x1
670 09:31:08.843141 ===================================
671 09:31:08.846190 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 09:31:08.849472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 09:31:08.855994 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 09:31:08.859568 ===================================
675 09:31:08.859651 LPDDR4 DRAM CONFIGURATION
676 09:31:08.863204 ===================================
677 09:31:08.866391 EX_ROW_EN[0] = 0x10
678 09:31:08.869884 EX_ROW_EN[1] = 0x0
679 09:31:08.869966 LP4Y_EN = 0x0
680 09:31:08.873557 WORK_FSP = 0x0
681 09:31:08.873639 WL = 0x2
682 09:31:08.877007 RL = 0x2
683 09:31:08.877089 BL = 0x2
684 09:31:08.881005 RPST = 0x0
685 09:31:08.881087 RD_PRE = 0x0
686 09:31:08.881153 WR_PRE = 0x1
687 09:31:08.884105 WR_PST = 0x0
688 09:31:08.884187 DBI_WR = 0x0
689 09:31:08.888060 DBI_RD = 0x0
690 09:31:08.888142 OTF = 0x1
691 09:31:08.891507 ===================================
692 09:31:08.897913 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 09:31:08.902085 nWR fixed to 40
694 09:31:08.905760 [ModeRegInit_LP4] CH0 RK0
695 09:31:08.905842 [ModeRegInit_LP4] CH0 RK1
696 09:31:08.909385 [ModeRegInit_LP4] CH1 RK0
697 09:31:08.913114 [ModeRegInit_LP4] CH1 RK1
698 09:31:08.913197 match AC timing 13
699 09:31:08.916840 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 09:31:08.920202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 09:31:08.928112 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 09:31:08.931689 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 09:31:08.935522 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 09:31:08.939365 [EMI DOE] emi_dcm 0
705 09:31:08.942776 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 09:31:08.942858 ==
707 09:31:08.946702 Dram Type= 6, Freq= 0, CH_0, rank 0
708 09:31:08.950539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 09:31:08.950622 ==
710 09:31:08.953870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 09:31:08.961154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 09:31:08.970477 [CA 0] Center 38 (7~69) winsize 63
713 09:31:08.973881 [CA 1] Center 37 (7~68) winsize 62
714 09:31:08.978085 [CA 2] Center 35 (5~66) winsize 62
715 09:31:08.980947 [CA 3] Center 35 (5~66) winsize 62
716 09:31:08.984865 [CA 4] Center 34 (4~65) winsize 62
717 09:31:08.988691 [CA 5] Center 34 (4~64) winsize 61
718 09:31:08.988774
719 09:31:08.992040 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 09:31:08.992123
721 09:31:08.995710 [CATrainingPosCal] consider 1 rank data
722 09:31:08.999767 u2DelayCellTimex100 = 270/100 ps
723 09:31:08.999879 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 09:31:09.003506 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 09:31:09.007334 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 09:31:09.011560 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 09:31:09.014452 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 09:31:09.018328 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 09:31:09.018411
730 09:31:09.022760 CA PerBit enable=1, Macro0, CA PI delay=34
731 09:31:09.022844
732 09:31:09.026394 [CBTSetCACLKResult] CA Dly = 34
733 09:31:09.026515 CS Dly: 6 (0~37)
734 09:31:09.030351 ==
735 09:31:09.030435 Dram Type= 6, Freq= 0, CH_0, rank 1
736 09:31:09.037496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 09:31:09.037579 ==
738 09:31:09.041340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 09:31:09.048397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 09:31:09.056593 [CA 0] Center 38 (7~69) winsize 63
741 09:31:09.060288 [CA 1] Center 38 (7~69) winsize 63
742 09:31:09.064321 [CA 2] Center 35 (5~66) winsize 62
743 09:31:09.068416 [CA 3] Center 35 (5~66) winsize 62
744 09:31:09.071590 [CA 4] Center 34 (4~65) winsize 62
745 09:31:09.071672 [CA 5] Center 34 (4~64) winsize 61
746 09:31:09.075682
747 09:31:09.079310 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 09:31:09.079430
749 09:31:09.082225 [CATrainingPosCal] consider 2 rank data
750 09:31:09.082307 u2DelayCellTimex100 = 270/100 ps
751 09:31:09.086837 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 09:31:09.093413 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 09:31:09.096798 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 09:31:09.100162 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 09:31:09.104036 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 09:31:09.104124 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 09:31:09.107873
758 09:31:09.111661 CA PerBit enable=1, Macro0, CA PI delay=34
759 09:31:09.111744
760 09:31:09.111810 [CBTSetCACLKResult] CA Dly = 34
761 09:31:09.115210 CS Dly: 6 (0~37)
762 09:31:09.115293
763 09:31:09.118810 ----->DramcWriteLeveling(PI) begin...
764 09:31:09.118893 ==
765 09:31:09.122541 Dram Type= 6, Freq= 0, CH_0, rank 0
766 09:31:09.125999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 09:31:09.126082 ==
768 09:31:09.129844 Write leveling (Byte 0): 31 => 31
769 09:31:09.133385 Write leveling (Byte 1): 29 => 29
770 09:31:09.133467 DramcWriteLeveling(PI) end<-----
771 09:31:09.133533
772 09:31:09.137144 ==
773 09:31:09.137226 Dram Type= 6, Freq= 0, CH_0, rank 0
774 09:31:09.144397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 09:31:09.144494 ==
776 09:31:09.144604 [Gating] SW mode calibration
777 09:31:09.151851 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 09:31:09.159171 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 09:31:09.162901 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 09:31:09.166999 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 09:31:09.170646 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 09:31:09.173910 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 09:31:09.180692 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 09:31:09.183867 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 09:31:09.186907 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 09:31:09.194118 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 09:31:09.198317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 09:31:09.201828 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:31:09.205158 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:31:09.209049 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:31:09.215289 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:31:09.218786 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:31:09.222499 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:31:09.229689 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:31:09.233135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:31:09.236483 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
797 09:31:09.242899 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
798 09:31:09.246118 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 09:31:09.249300 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:31:09.253184 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:31:09.259276 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:31:09.262818 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:31:09.266331 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:31:09.273089 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:31:09.276104 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:31:09.279441 0 9 12 | B1->B0 | 2929 3333 | 1 1 | (1 1) (1 1)
807 09:31:09.286483 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 09:31:09.289656 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 09:31:09.292865 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 09:31:09.299886 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 09:31:09.303052 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 09:31:09.306632 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 09:31:09.313434 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
814 09:31:09.316484 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
815 09:31:09.319978 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:31:09.323145 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 09:31:09.330031 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 09:31:09.333191 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 09:31:09.336450 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:31:09.343216 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:31:09.346276 0 11 8 | B1->B0 | 2727 2b2b | 1 1 | (0 0) (0 0)
822 09:31:09.349425 0 11 12 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (0 0)
823 09:31:09.356509 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 09:31:09.359797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 09:31:09.363298 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 09:31:09.369822 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 09:31:09.373214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 09:31:09.376043 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 09:31:09.382871 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 09:31:09.386325 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 09:31:09.389479 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
832 09:31:09.396611 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 09:31:09.399356 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 09:31:09.403175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 09:31:09.409888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 09:31:09.413027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:31:09.416103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:31:09.423027 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:31:09.426080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:31:09.429599 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:31:09.432654 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:31:09.439923 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:31:09.443099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:31:09.446092 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:31:09.453147 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 09:31:09.456152 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 09:31:09.459652 Total UI for P1: 0, mck2ui 16
848 09:31:09.462542 best dqsien dly found for B0: ( 0, 14, 8)
849 09:31:09.466472 Total UI for P1: 0, mck2ui 16
850 09:31:09.469287 best dqsien dly found for B1: ( 0, 14, 10)
851 09:31:09.473159 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 09:31:09.476201 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 09:31:09.476287
854 09:31:09.479431 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 09:31:09.482642 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 09:31:09.486030 [Gating] SW calibration Done
857 09:31:09.486114 ==
858 09:31:09.489645 Dram Type= 6, Freq= 0, CH_0, rank 0
859 09:31:09.496286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 09:31:09.496377 ==
861 09:31:09.496445 RX Vref Scan: 0
862 09:31:09.496507
863 09:31:09.499592 RX Vref 0 -> 0, step: 1
864 09:31:09.499677
865 09:31:09.502784 RX Delay -130 -> 252, step: 16
866 09:31:09.506106 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 09:31:09.509236 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 09:31:09.512579 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 09:31:09.516264 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 09:31:09.522596 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 09:31:09.526178 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 09:31:09.529910 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 09:31:09.532901 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 09:31:09.536335 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 09:31:09.542871 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 09:31:09.546283 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 09:31:09.549284 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
878 09:31:09.552687 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 09:31:09.556381 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 09:31:09.562992 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 09:31:09.566185 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 09:31:09.566267 ==
883 09:31:09.569488 Dram Type= 6, Freq= 0, CH_0, rank 0
884 09:31:09.572806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 09:31:09.572889 ==
886 09:31:09.576187 DQS Delay:
887 09:31:09.576269 DQS0 = 0, DQS1 = 0
888 09:31:09.576355 DQM Delay:
889 09:31:09.579660 DQM0 = 81, DQM1 = 70
890 09:31:09.579742 DQ Delay:
891 09:31:09.582730 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 09:31:09.586037 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 09:31:09.589617 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
894 09:31:09.592994 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 09:31:09.593077
896 09:31:09.593142
897 09:31:09.593204 ==
898 09:31:09.596077 Dram Type= 6, Freq= 0, CH_0, rank 0
899 09:31:09.599548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 09:31:09.602870 ==
901 09:31:09.602952
902 09:31:09.603016
903 09:31:09.603076 TX Vref Scan disable
904 09:31:09.606607 == TX Byte 0 ==
905 09:31:09.610932 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 09:31:09.613243 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 09:31:09.617056 == TX Byte 1 ==
908 09:31:09.620349 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 09:31:09.623552 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 09:31:09.623637 ==
911 09:31:09.626581 Dram Type= 6, Freq= 0, CH_0, rank 0
912 09:31:09.633564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 09:31:09.633650 ==
914 09:31:09.645208 TX Vref=22, minBit 14, minWin=26, winSum=435
915 09:31:09.648514 TX Vref=24, minBit 1, minWin=26, winSum=437
916 09:31:09.651863 TX Vref=26, minBit 0, minWin=27, winSum=442
917 09:31:09.655116 TX Vref=28, minBit 0, minWin=28, winSum=449
918 09:31:09.658375 TX Vref=30, minBit 11, minWin=27, winSum=444
919 09:31:09.665359 TX Vref=32, minBit 10, minWin=26, winSum=441
920 09:31:09.668493 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 28
921 09:31:09.668578
922 09:31:09.671724 Final TX Range 1 Vref 28
923 09:31:09.671808
924 09:31:09.671875 ==
925 09:31:09.675051 Dram Type= 6, Freq= 0, CH_0, rank 0
926 09:31:09.678521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 09:31:09.682012 ==
928 09:31:09.682095
929 09:31:09.682161
930 09:31:09.682224 TX Vref Scan disable
931 09:31:09.685119 == TX Byte 0 ==
932 09:31:09.688507 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
933 09:31:09.695421 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
934 09:31:09.695521 == TX Byte 1 ==
935 09:31:09.698566 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
936 09:31:09.705813 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
937 09:31:09.705900
938 09:31:09.705968 [DATLAT]
939 09:31:09.706030 Freq=800, CH0 RK0
940 09:31:09.706090
941 09:31:09.708946 DATLAT Default: 0xa
942 09:31:09.709032 0, 0xFFFF, sum = 0
943 09:31:09.711781 1, 0xFFFF, sum = 0
944 09:31:09.711870 2, 0xFFFF, sum = 0
945 09:31:09.715149 3, 0xFFFF, sum = 0
946 09:31:09.715235 4, 0xFFFF, sum = 0
947 09:31:09.718416 5, 0xFFFF, sum = 0
948 09:31:09.722335 6, 0xFFFF, sum = 0
949 09:31:09.722422 7, 0xFFFF, sum = 0
950 09:31:09.725166 8, 0xFFFF, sum = 0
951 09:31:09.725252 9, 0x0, sum = 1
952 09:31:09.725320 10, 0x0, sum = 2
953 09:31:09.729029 11, 0x0, sum = 3
954 09:31:09.729113 12, 0x0, sum = 4
955 09:31:09.732056 best_step = 10
956 09:31:09.732140
957 09:31:09.732206 ==
958 09:31:09.735683 Dram Type= 6, Freq= 0, CH_0, rank 0
959 09:31:09.739026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 09:31:09.739111 ==
961 09:31:09.742339 RX Vref Scan: 1
962 09:31:09.742422
963 09:31:09.742489 Set Vref Range= 32 -> 127
964 09:31:09.742553
965 09:31:09.745485 RX Vref 32 -> 127, step: 1
966 09:31:09.745569
967 09:31:09.748847 RX Delay -111 -> 252, step: 8
968 09:31:09.748932
969 09:31:09.752654 Set Vref, RX VrefLevel [Byte0]: 32
970 09:31:09.755543 [Byte1]: 32
971 09:31:09.755628
972 09:31:09.758849 Set Vref, RX VrefLevel [Byte0]: 33
973 09:31:09.762241 [Byte1]: 33
974 09:31:09.766058
975 09:31:09.766147 Set Vref, RX VrefLevel [Byte0]: 34
976 09:31:09.769357 [Byte1]: 34
977 09:31:09.773570
978 09:31:09.773655 Set Vref, RX VrefLevel [Byte0]: 35
979 09:31:09.776818 [Byte1]: 35
980 09:31:09.780973
981 09:31:09.781058 Set Vref, RX VrefLevel [Byte0]: 36
982 09:31:09.784203 [Byte1]: 36
983 09:31:09.789033
984 09:31:09.789118 Set Vref, RX VrefLevel [Byte0]: 37
985 09:31:09.792239 [Byte1]: 37
986 09:31:09.796650
987 09:31:09.796737 Set Vref, RX VrefLevel [Byte0]: 38
988 09:31:09.799439 [Byte1]: 38
989 09:31:09.804160
990 09:31:09.804246 Set Vref, RX VrefLevel [Byte0]: 39
991 09:31:09.807663 [Byte1]: 39
992 09:31:09.812057
993 09:31:09.812140 Set Vref, RX VrefLevel [Byte0]: 40
994 09:31:09.815108 [Byte1]: 40
995 09:31:09.819239
996 09:31:09.819324 Set Vref, RX VrefLevel [Byte0]: 41
997 09:31:09.822822 [Byte1]: 41
998 09:31:09.826942
999 09:31:09.827025 Set Vref, RX VrefLevel [Byte0]: 42
1000 09:31:09.830258 [Byte1]: 42
1001 09:31:09.834741
1002 09:31:09.834826 Set Vref, RX VrefLevel [Byte0]: 43
1003 09:31:09.837824 [Byte1]: 43
1004 09:31:09.842241
1005 09:31:09.842324 Set Vref, RX VrefLevel [Byte0]: 44
1006 09:31:09.845462 [Byte1]: 44
1007 09:31:09.850288
1008 09:31:09.850371 Set Vref, RX VrefLevel [Byte0]: 45
1009 09:31:09.853234 [Byte1]: 45
1010 09:31:09.858354
1011 09:31:09.858439 Set Vref, RX VrefLevel [Byte0]: 46
1012 09:31:09.861460 [Byte1]: 46
1013 09:31:09.865669
1014 09:31:09.865754 Set Vref, RX VrefLevel [Byte0]: 47
1015 09:31:09.869106 [Byte1]: 47
1016 09:31:09.873045
1017 09:31:09.873131 Set Vref, RX VrefLevel [Byte0]: 48
1018 09:31:09.876416 [Byte1]: 48
1019 09:31:09.881032
1020 09:31:09.881120 Set Vref, RX VrefLevel [Byte0]: 49
1021 09:31:09.884521 [Byte1]: 49
1022 09:31:09.888426
1023 09:31:09.888510 Set Vref, RX VrefLevel [Byte0]: 50
1024 09:31:09.891822 [Byte1]: 50
1025 09:31:09.896139
1026 09:31:09.896242 Set Vref, RX VrefLevel [Byte0]: 51
1027 09:31:09.899286 [Byte1]: 51
1028 09:31:09.903635
1029 09:31:09.903733 Set Vref, RX VrefLevel [Byte0]: 52
1030 09:31:09.906849 [Byte1]: 52
1031 09:31:09.911311
1032 09:31:09.911449 Set Vref, RX VrefLevel [Byte0]: 53
1033 09:31:09.914642 [Byte1]: 53
1034 09:31:09.918987
1035 09:31:09.919087 Set Vref, RX VrefLevel [Byte0]: 54
1036 09:31:09.922351 [Byte1]: 54
1037 09:31:09.926851
1038 09:31:09.926945 Set Vref, RX VrefLevel [Byte0]: 55
1039 09:31:09.929969 [Byte1]: 55
1040 09:31:09.934152
1041 09:31:09.934235 Set Vref, RX VrefLevel [Byte0]: 56
1042 09:31:09.937341 [Byte1]: 56
1043 09:31:09.941804
1044 09:31:09.941889 Set Vref, RX VrefLevel [Byte0]: 57
1045 09:31:09.945054 [Byte1]: 57
1046 09:31:09.949178
1047 09:31:09.949269 Set Vref, RX VrefLevel [Byte0]: 58
1048 09:31:09.952657 [Byte1]: 58
1049 09:31:09.957279
1050 09:31:09.957375 Set Vref, RX VrefLevel [Byte0]: 59
1051 09:31:09.960583 [Byte1]: 59
1052 09:31:09.964624
1053 09:31:09.964719 Set Vref, RX VrefLevel [Byte0]: 60
1054 09:31:09.967810 [Byte1]: 60
1055 09:31:09.972392
1056 09:31:09.972475 Set Vref, RX VrefLevel [Byte0]: 61
1057 09:31:09.975733 [Byte1]: 61
1058 09:31:09.980149
1059 09:31:09.980236 Set Vref, RX VrefLevel [Byte0]: 62
1060 09:31:09.983246 [Byte1]: 62
1061 09:31:09.987621
1062 09:31:09.987711 Set Vref, RX VrefLevel [Byte0]: 63
1063 09:31:09.991056 [Byte1]: 63
1064 09:31:09.995276
1065 09:31:09.995372 Set Vref, RX VrefLevel [Byte0]: 64
1066 09:31:09.998849 [Byte1]: 64
1067 09:31:10.002771
1068 09:31:10.002857 Set Vref, RX VrefLevel [Byte0]: 65
1069 09:31:10.006257 [Byte1]: 65
1070 09:31:10.010652
1071 09:31:10.010735 Set Vref, RX VrefLevel [Byte0]: 66
1072 09:31:10.013810 [Byte1]: 66
1073 09:31:10.018265
1074 09:31:10.018347 Set Vref, RX VrefLevel [Byte0]: 67
1075 09:31:10.021606 [Byte1]: 67
1076 09:31:10.025891
1077 09:31:10.025974 Set Vref, RX VrefLevel [Byte0]: 68
1078 09:31:10.029260 [Byte1]: 68
1079 09:31:10.033495
1080 09:31:10.033585 Set Vref, RX VrefLevel [Byte0]: 69
1081 09:31:10.036767 [Byte1]: 69
1082 09:31:10.041032
1083 09:31:10.041128 Set Vref, RX VrefLevel [Byte0]: 70
1084 09:31:10.044224 [Byte1]: 70
1085 09:31:10.048749
1086 09:31:10.048844 Set Vref, RX VrefLevel [Byte0]: 71
1087 09:31:10.052121 [Byte1]: 71
1088 09:31:10.056303
1089 09:31:10.056396 Set Vref, RX VrefLevel [Byte0]: 72
1090 09:31:10.059675 [Byte1]: 72
1091 09:31:10.064189
1092 09:31:10.064282 Set Vref, RX VrefLevel [Byte0]: 73
1093 09:31:10.067311 [Byte1]: 73
1094 09:31:10.071714
1095 09:31:10.071796 Set Vref, RX VrefLevel [Byte0]: 74
1096 09:31:10.075082 [Byte1]: 74
1097 09:31:10.079641
1098 09:31:10.079738 Set Vref, RX VrefLevel [Byte0]: 75
1099 09:31:10.083006 [Byte1]: 75
1100 09:31:10.087190
1101 09:31:10.087278 Set Vref, RX VrefLevel [Byte0]: 76
1102 09:31:10.090121 [Byte1]: 76
1103 09:31:10.094403
1104 09:31:10.094504 Set Vref, RX VrefLevel [Byte0]: 77
1105 09:31:10.097993 [Byte1]: 77
1106 09:31:10.102579
1107 09:31:10.102672 Set Vref, RX VrefLevel [Byte0]: 78
1108 09:31:10.105386 [Byte1]: 78
1109 09:31:10.109744
1110 09:31:10.109839 Set Vref, RX VrefLevel [Byte0]: 79
1111 09:31:10.112985 [Byte1]: 79
1112 09:31:10.117262
1113 09:31:10.117351 Set Vref, RX VrefLevel [Byte0]: 80
1114 09:31:10.120757 [Byte1]: 80
1115 09:31:10.125041
1116 09:31:10.125128 Final RX Vref Byte 0 = 59 to rank0
1117 09:31:10.128504 Final RX Vref Byte 1 = 58 to rank0
1118 09:31:10.131610 Final RX Vref Byte 0 = 59 to rank1
1119 09:31:10.135307 Final RX Vref Byte 1 = 58 to rank1==
1120 09:31:10.138635 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 09:31:10.145032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 09:31:10.145115 ==
1123 09:31:10.145181 DQS Delay:
1124 09:31:10.145241 DQS0 = 0, DQS1 = 0
1125 09:31:10.148404 DQM Delay:
1126 09:31:10.148486 DQM0 = 82, DQM1 = 68
1127 09:31:10.152285 DQ Delay:
1128 09:31:10.154891 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1129 09:31:10.154972 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1130 09:31:10.158590 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =64
1131 09:31:10.161595 DQ12 =76, DQ13 =68, DQ14 =76, DQ15 =76
1132 09:31:10.165131
1133 09:31:10.165214
1134 09:31:10.171941 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1135 09:31:10.174961 CH0 RK0: MR19=606, MR18=2726
1136 09:31:10.181923 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1137 09:31:10.182019
1138 09:31:10.185120 ----->DramcWriteLeveling(PI) begin...
1139 09:31:10.185207 ==
1140 09:31:10.188433 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 09:31:10.191861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 09:31:10.191949 ==
1143 09:31:10.195119 Write leveling (Byte 0): 32 => 32
1144 09:31:10.198489 Write leveling (Byte 1): 32 => 32
1145 09:31:10.201751 DramcWriteLeveling(PI) end<-----
1146 09:31:10.201835
1147 09:31:10.201900 ==
1148 09:31:10.204948 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 09:31:10.208536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 09:31:10.208621 ==
1151 09:31:10.212002 [Gating] SW mode calibration
1152 09:31:10.218411 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 09:31:10.225301 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 09:31:10.228932 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 09:31:10.231731 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 09:31:10.238561 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 09:31:10.241832 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:31:10.245110 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:31:10.251604 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:31:10.254897 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:31:10.258293 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:31:10.264882 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:31:10.268603 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:31:10.271827 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:31:10.278397 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:31:10.322723 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:31:10.323077 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:31:10.323158 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:31:10.323230 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:31:10.323302 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:31:10.323746 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1172 09:31:10.323827 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1173 09:31:10.324077 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:31:10.324158 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:31:10.324404 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:31:10.366787 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:31:10.366940 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:31:10.367206 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:31:10.367857 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1180 09:31:10.368125 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
1181 09:31:10.368197 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1182 09:31:10.368259 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 09:31:10.368329 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 09:31:10.369100 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 09:31:10.369365 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 09:31:10.371888 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1187 09:31:10.371973 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1188 09:31:10.378390 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
1189 09:31:10.381977 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1190 09:31:10.385310 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:31:10.391832 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:31:10.395247 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:31:10.398702 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:31:10.405226 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:31:10.408560 0 11 4 | B1->B0 | 2424 2424 | 0 1 | (0 0) (0 0)
1196 09:31:10.412379 0 11 8 | B1->B0 | 2f2f 3a3a | 1 0 | (0 0) (0 0)
1197 09:31:10.418449 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 09:31:10.422430 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 09:31:10.425075 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 09:31:10.432308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 09:31:10.435658 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 09:31:10.439016 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 09:31:10.442959 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 09:31:10.446784 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 09:31:10.453720 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 09:31:10.456904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:31:10.460136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:31:10.467256 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:31:10.470901 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:31:10.474643 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:31:10.477772 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:31:10.483933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:31:10.487226 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:31:10.490907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:31:10.497426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:31:10.500512 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:31:10.504526 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 09:31:10.510505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 09:31:10.514195 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:31:10.517680 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1221 09:31:10.520846 Total UI for P1: 0, mck2ui 16
1222 09:31:10.524139 best dqsien dly found for B0: ( 0, 14, 6)
1223 09:31:10.530845 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 09:31:10.530957 Total UI for P1: 0, mck2ui 16
1225 09:31:10.537321 best dqsien dly found for B1: ( 0, 14, 8)
1226 09:31:10.540875 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1227 09:31:10.544026 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 09:31:10.544118
1229 09:31:10.547221 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1230 09:31:10.550494 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 09:31:10.554121 [Gating] SW calibration Done
1232 09:31:10.554215 ==
1233 09:31:10.557397 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 09:31:10.560549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 09:31:10.560636 ==
1236 09:31:10.563793 RX Vref Scan: 0
1237 09:31:10.563874
1238 09:31:10.563939 RX Vref 0 -> 0, step: 1
1239 09:31:10.563998
1240 09:31:10.567127 RX Delay -130 -> 252, step: 16
1241 09:31:10.570833 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1242 09:31:10.577545 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1243 09:31:10.580471 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1244 09:31:10.583833 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1245 09:31:10.587212 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1246 09:31:10.590717 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1247 09:31:10.597044 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1248 09:31:10.600680 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1249 09:31:10.603807 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1250 09:31:10.607115 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1251 09:31:10.610783 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1252 09:31:10.617305 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1253 09:31:10.620803 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1254 09:31:10.624015 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1255 09:31:10.627656 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1256 09:31:10.630589 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1257 09:31:10.630669 ==
1258 09:31:10.633876 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 09:31:10.640551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 09:31:10.640632 ==
1261 09:31:10.640697 DQS Delay:
1262 09:31:10.644076 DQS0 = 0, DQS1 = 0
1263 09:31:10.644156 DQM Delay:
1264 09:31:10.644219 DQM0 = 81, DQM1 = 69
1265 09:31:10.647355 DQ Delay:
1266 09:31:10.650447 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1267 09:31:10.654073 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1268 09:31:10.657256 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1269 09:31:10.660395 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1270 09:31:10.660475
1271 09:31:10.660567
1272 09:31:10.660628 ==
1273 09:31:10.663870 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 09:31:10.667291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 09:31:10.667394 ==
1276 09:31:10.667505
1277 09:31:10.667566
1278 09:31:10.670683 TX Vref Scan disable
1279 09:31:10.670762 == TX Byte 0 ==
1280 09:31:10.677021 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 09:31:10.680487 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 09:31:10.680567 == TX Byte 1 ==
1283 09:31:10.687358 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 09:31:10.690619 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 09:31:10.690737 ==
1286 09:31:10.694163 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 09:31:10.697235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 09:31:10.697316 ==
1289 09:31:10.711227 TX Vref=22, minBit 0, minWin=27, winSum=437
1290 09:31:10.714467 TX Vref=24, minBit 1, minWin=27, winSum=442
1291 09:31:10.718097 TX Vref=26, minBit 1, minWin=27, winSum=442
1292 09:31:10.721084 TX Vref=28, minBit 2, minWin=27, winSum=440
1293 09:31:10.724443 TX Vref=30, minBit 1, minWin=27, winSum=444
1294 09:31:10.727921 TX Vref=32, minBit 2, minWin=27, winSum=445
1295 09:31:10.734426 [TxChooseVref] Worse bit 2, Min win 27, Win sum 445, Final Vref 32
1296 09:31:10.734585
1297 09:31:10.737805 Final TX Range 1 Vref 32
1298 09:31:10.737955
1299 09:31:10.738093 ==
1300 09:31:10.741245 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 09:31:10.744499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 09:31:10.744650 ==
1303 09:31:10.747369
1304 09:31:10.747526
1305 09:31:10.747664 TX Vref Scan disable
1306 09:31:10.750733 == TX Byte 0 ==
1307 09:31:10.754212 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1308 09:31:10.757940 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1309 09:31:10.761186 == TX Byte 1 ==
1310 09:31:10.764398 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1311 09:31:10.767894 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1312 09:31:10.770911
1313 09:31:10.770990 [DATLAT]
1314 09:31:10.771054 Freq=800, CH0 RK1
1315 09:31:10.771114
1316 09:31:10.774193 DATLAT Default: 0xa
1317 09:31:10.774274 0, 0xFFFF, sum = 0
1318 09:31:10.777685 1, 0xFFFF, sum = 0
1319 09:31:10.777767 2, 0xFFFF, sum = 0
1320 09:31:10.781326 3, 0xFFFF, sum = 0
1321 09:31:10.781408 4, 0xFFFF, sum = 0
1322 09:31:10.784648 5, 0xFFFF, sum = 0
1323 09:31:10.784729 6, 0xFFFF, sum = 0
1324 09:31:10.787578 7, 0xFFFF, sum = 0
1325 09:31:10.791320 8, 0xFFFF, sum = 0
1326 09:31:10.791410 9, 0x0, sum = 1
1327 09:31:10.791477 10, 0x0, sum = 2
1328 09:31:10.794406 11, 0x0, sum = 3
1329 09:31:10.794486 12, 0x0, sum = 4
1330 09:31:10.797471 best_step = 10
1331 09:31:10.797551
1332 09:31:10.797614 ==
1333 09:31:10.801113 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 09:31:10.804621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 09:31:10.804702 ==
1336 09:31:10.807711 RX Vref Scan: 0
1337 09:31:10.807792
1338 09:31:10.807855 RX Vref 0 -> 0, step: 1
1339 09:31:10.807914
1340 09:31:10.810706 RX Delay -111 -> 252, step: 8
1341 09:31:10.817879 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1342 09:31:10.821787 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 09:31:10.824453 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 09:31:10.827883 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1345 09:31:10.831089 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1346 09:31:10.837759 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 09:31:10.841034 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1348 09:31:10.844355 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1349 09:31:10.847681 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1350 09:31:10.850997 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1351 09:31:10.857810 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 09:31:10.861227 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1353 09:31:10.864441 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1354 09:31:10.867809 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1355 09:31:10.871128 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 09:31:10.878043 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1357 09:31:10.878127 ==
1358 09:31:10.881079 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 09:31:10.884807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 09:31:10.884888 ==
1361 09:31:10.884952 DQS Delay:
1362 09:31:10.887976 DQS0 = 0, DQS1 = 0
1363 09:31:10.888056 DQM Delay:
1364 09:31:10.891104 DQM0 = 78, DQM1 = 70
1365 09:31:10.891183 DQ Delay:
1366 09:31:10.894239 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1367 09:31:10.898258 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1368 09:31:10.901083 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1369 09:31:10.904730 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1370 09:31:10.904811
1371 09:31:10.904874
1372 09:31:10.910862 [DQSOSCAuto] RK1, (LSB)MR18= 0x4822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1373 09:31:10.914460 CH0 RK1: MR19=606, MR18=4822
1374 09:31:10.921353 CH0_RK1: MR19=0x606, MR18=0x4822, DQSOSC=391, MR23=63, INC=96, DEC=64
1375 09:31:10.924589 [RxdqsGatingPostProcess] freq 800
1376 09:31:10.931350 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 09:31:10.934811 Pre-setting of DQS Precalculation
1378 09:31:10.937550 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 09:31:10.937632 ==
1380 09:31:10.941276 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 09:31:10.944578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 09:31:10.944661 ==
1383 09:31:10.951336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 09:31:10.957884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 09:31:10.966230 [CA 0] Center 36 (6~66) winsize 61
1386 09:31:10.969554 [CA 1] Center 36 (6~67) winsize 62
1387 09:31:10.972999 [CA 2] Center 34 (4~64) winsize 61
1388 09:31:10.976175 [CA 3] Center 34 (4~64) winsize 61
1389 09:31:10.979347 [CA 4] Center 34 (4~64) winsize 61
1390 09:31:10.982542 [CA 5] Center 33 (3~64) winsize 62
1391 09:31:10.982626
1392 09:31:10.986238 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 09:31:10.986319
1394 09:31:10.989352 [CATrainingPosCal] consider 1 rank data
1395 09:31:10.992591 u2DelayCellTimex100 = 270/100 ps
1396 09:31:10.995720 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1397 09:31:10.999215 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1398 09:31:11.006143 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1399 09:31:11.009343 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 09:31:11.012762 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1401 09:31:11.016196 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 09:31:11.016277
1403 09:31:11.019282 CA PerBit enable=1, Macro0, CA PI delay=33
1404 09:31:11.019361
1405 09:31:11.022831 [CBTSetCACLKResult] CA Dly = 33
1406 09:31:11.022911 CS Dly: 5 (0~36)
1407 09:31:11.022975 ==
1408 09:31:11.026111 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 09:31:11.032540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 09:31:11.032622 ==
1411 09:31:11.035981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 09:31:11.042772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 09:31:11.052563 [CA 0] Center 36 (6~67) winsize 62
1414 09:31:11.055354 [CA 1] Center 36 (6~67) winsize 62
1415 09:31:11.058571 [CA 2] Center 34 (4~65) winsize 62
1416 09:31:11.062317 [CA 3] Center 33 (3~64) winsize 62
1417 09:31:11.065678 [CA 4] Center 34 (4~65) winsize 62
1418 09:31:11.068819 [CA 5] Center 33 (3~64) winsize 62
1419 09:31:11.068898
1420 09:31:11.072300 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 09:31:11.072379
1422 09:31:11.075807 [CATrainingPosCal] consider 2 rank data
1423 09:31:11.079089 u2DelayCellTimex100 = 270/100 ps
1424 09:31:11.082291 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1425 09:31:11.085577 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 09:31:11.091986 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1427 09:31:11.095859 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 09:31:11.099292 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1429 09:31:11.103111 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 09:31:11.103191
1431 09:31:11.106668 CA PerBit enable=1, Macro0, CA PI delay=33
1432 09:31:11.106748
1433 09:31:11.110356 [CBTSetCACLKResult] CA Dly = 33
1434 09:31:11.110437 CS Dly: 6 (0~38)
1435 09:31:11.110501
1436 09:31:11.113838 ----->DramcWriteLeveling(PI) begin...
1437 09:31:11.113920 ==
1438 09:31:11.117658 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 09:31:11.121476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 09:31:11.121558 ==
1441 09:31:11.125400 Write leveling (Byte 0): 30 => 30
1442 09:31:11.128677 Write leveling (Byte 1): 30 => 30
1443 09:31:11.132474 DramcWriteLeveling(PI) end<-----
1444 09:31:11.132556
1445 09:31:11.132621 ==
1446 09:31:11.135768 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 09:31:11.139340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 09:31:11.139452 ==
1449 09:31:11.142680 [Gating] SW mode calibration
1450 09:31:11.148836 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 09:31:11.152522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 09:31:11.159055 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 09:31:11.162313 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 09:31:11.165908 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1455 09:31:11.172457 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:31:11.175642 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:31:11.179184 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:31:11.185876 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:31:11.189155 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:31:11.192253 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:31:11.199252 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:31:11.202558 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:31:11.205698 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:31:11.209400 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:31:11.215598 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:31:11.219540 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:31:11.222703 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:31:11.229477 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:31:11.232829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:31:11.236275 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1471 09:31:11.242591 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:31:11.246045 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:31:11.249358 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:31:11.255840 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:31:11.259116 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:31:11.262418 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:31:11.268934 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:31:11.272551 0 9 8 | B1->B0 | 2a2a 2525 | 1 0 | (1 1) (0 0)
1479 09:31:11.275698 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1480 09:31:11.283132 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 09:31:11.285659 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 09:31:11.289379 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 09:31:11.295819 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 09:31:11.299109 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 09:31:11.302466 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1486 09:31:11.305789 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
1487 09:31:11.312490 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:31:11.316148 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:31:11.319261 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:31:11.325753 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:31:11.329010 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:31:11.332365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:31:11.339703 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1494 09:31:11.342711 0 11 8 | B1->B0 | 3535 3737 | 1 1 | (0 0) (0 0)
1495 09:31:11.346093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 09:31:11.352408 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 09:31:11.355880 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 09:31:11.359325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 09:31:11.365923 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 09:31:11.369203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 09:31:11.372523 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 09:31:11.379610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 09:31:11.382593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:31:11.386040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:31:11.392782 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:31:11.395836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:31:11.399137 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:31:11.402804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:31:11.408928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:31:11.412564 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:31:11.416065 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:31:11.422476 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:31:11.425543 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:31:11.428854 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:31:11.436030 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:31:11.439339 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:31:11.442893 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:31:11.449305 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 09:31:11.452706 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 09:31:11.455993 Total UI for P1: 0, mck2ui 16
1521 09:31:11.459329 best dqsien dly found for B0: ( 0, 14, 8)
1522 09:31:11.462478 Total UI for P1: 0, mck2ui 16
1523 09:31:11.465657 best dqsien dly found for B1: ( 0, 14, 8)
1524 09:31:11.469286 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1525 09:31:11.472558 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1526 09:31:11.472638
1527 09:31:11.475733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 09:31:11.479138 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 09:31:11.482452 [Gating] SW calibration Done
1530 09:31:11.482532 ==
1531 09:31:11.485849 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 09:31:11.488864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 09:31:11.488945 ==
1534 09:31:11.492316 RX Vref Scan: 0
1535 09:31:11.492396
1536 09:31:11.495734 RX Vref 0 -> 0, step: 1
1537 09:31:11.495815
1538 09:31:11.495879 RX Delay -130 -> 252, step: 16
1539 09:31:11.502614 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 09:31:11.505828 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 09:31:11.509040 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1542 09:31:11.512607 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 09:31:11.515894 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 09:31:11.522695 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 09:31:11.525729 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 09:31:11.529026 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 09:31:11.532481 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 09:31:11.535674 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1549 09:31:11.542696 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 09:31:11.545916 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 09:31:11.549079 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 09:31:11.552496 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 09:31:11.556025 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 09:31:11.562465 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 09:31:11.562545 ==
1556 09:31:11.565658 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 09:31:11.569091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 09:31:11.569170 ==
1559 09:31:11.569233 DQS Delay:
1560 09:31:11.572256 DQS0 = 0, DQS1 = 0
1561 09:31:11.572335 DQM Delay:
1562 09:31:11.575893 DQM0 = 80, DQM1 = 71
1563 09:31:11.575974 DQ Delay:
1564 09:31:11.579111 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1565 09:31:11.582548 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 09:31:11.585896 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1567 09:31:11.589206 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 09:31:11.589285
1569 09:31:11.589348
1570 09:31:11.589406 ==
1571 09:31:11.592827 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 09:31:11.595631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 09:31:11.595711 ==
1574 09:31:11.595802
1575 09:31:11.599160
1576 09:31:11.599238 TX Vref Scan disable
1577 09:31:11.602382 == TX Byte 0 ==
1578 09:31:11.605793 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1579 09:31:11.609011 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1580 09:31:11.612347 == TX Byte 1 ==
1581 09:31:11.615734 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 09:31:11.619565 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 09:31:11.619645 ==
1584 09:31:11.622701 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 09:31:11.629091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 09:31:11.629171 ==
1587 09:31:11.640566 TX Vref=22, minBit 1, minWin=27, winSum=441
1588 09:31:11.644172 TX Vref=24, minBit 1, minWin=26, winSum=442
1589 09:31:11.647308 TX Vref=26, minBit 1, minWin=27, winSum=442
1590 09:31:11.650891 TX Vref=28, minBit 4, minWin=27, winSum=446
1591 09:31:11.653899 TX Vref=30, minBit 4, minWin=27, winSum=447
1592 09:31:11.661066 TX Vref=32, minBit 0, minWin=27, winSum=445
1593 09:31:11.664369 [TxChooseVref] Worse bit 4, Min win 27, Win sum 447, Final Vref 30
1594 09:31:11.664451
1595 09:31:11.667449 Final TX Range 1 Vref 30
1596 09:31:11.667530
1597 09:31:11.667594 ==
1598 09:31:11.670676 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 09:31:11.674175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 09:31:11.674256 ==
1601 09:31:11.674320
1602 09:31:11.674379
1603 09:31:11.678027 TX Vref Scan disable
1604 09:31:11.681143 == TX Byte 0 ==
1605 09:31:11.684584 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1606 09:31:11.687987 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1607 09:31:11.691189 == TX Byte 1 ==
1608 09:31:11.694489 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 09:31:11.697875 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 09:31:11.697955
1611 09:31:11.701158 [DATLAT]
1612 09:31:11.701239 Freq=800, CH1 RK0
1613 09:31:11.701304
1614 09:31:11.704484 DATLAT Default: 0xa
1615 09:31:11.704571 0, 0xFFFF, sum = 0
1616 09:31:11.708256 1, 0xFFFF, sum = 0
1617 09:31:11.708337 2, 0xFFFF, sum = 0
1618 09:31:11.711671 3, 0xFFFF, sum = 0
1619 09:31:11.711753 4, 0xFFFF, sum = 0
1620 09:31:11.714744 5, 0xFFFF, sum = 0
1621 09:31:11.714827 6, 0xFFFF, sum = 0
1622 09:31:11.717802 7, 0xFFFF, sum = 0
1623 09:31:11.717883 8, 0xFFFF, sum = 0
1624 09:31:11.721647 9, 0x0, sum = 1
1625 09:31:11.721729 10, 0x0, sum = 2
1626 09:31:11.724718 11, 0x0, sum = 3
1627 09:31:11.724800 12, 0x0, sum = 4
1628 09:31:11.728075 best_step = 10
1629 09:31:11.728154
1630 09:31:11.728218 ==
1631 09:31:11.731336 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 09:31:11.734870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 09:31:11.734950 ==
1634 09:31:11.735013 RX Vref Scan: 1
1635 09:31:11.737951
1636 09:31:11.738031 Set Vref Range= 32 -> 127
1637 09:31:11.738095
1638 09:31:11.741461 RX Vref 32 -> 127, step: 1
1639 09:31:11.741541
1640 09:31:11.744531 RX Delay -111 -> 252, step: 8
1641 09:31:11.744612
1642 09:31:11.748446 Set Vref, RX VrefLevel [Byte0]: 32
1643 09:31:11.751355 [Byte1]: 32
1644 09:31:11.751470
1645 09:31:11.754627 Set Vref, RX VrefLevel [Byte0]: 33
1646 09:31:11.758387 [Byte1]: 33
1647 09:31:11.758468
1648 09:31:11.761573 Set Vref, RX VrefLevel [Byte0]: 34
1649 09:31:11.764778 [Byte1]: 34
1650 09:31:11.768588
1651 09:31:11.768669 Set Vref, RX VrefLevel [Byte0]: 35
1652 09:31:11.772037 [Byte1]: 35
1653 09:31:11.776236
1654 09:31:11.776316 Set Vref, RX VrefLevel [Byte0]: 36
1655 09:31:11.779806 [Byte1]: 36
1656 09:31:11.784006
1657 09:31:11.784085 Set Vref, RX VrefLevel [Byte0]: 37
1658 09:31:11.787487 [Byte1]: 37
1659 09:31:11.791708
1660 09:31:11.791787 Set Vref, RX VrefLevel [Byte0]: 38
1661 09:31:11.794959 [Byte1]: 38
1662 09:31:11.799572
1663 09:31:11.799651 Set Vref, RX VrefLevel [Byte0]: 39
1664 09:31:11.802696 [Byte1]: 39
1665 09:31:11.807267
1666 09:31:11.807347 Set Vref, RX VrefLevel [Byte0]: 40
1667 09:31:11.810444 [Byte1]: 40
1668 09:31:11.814800
1669 09:31:11.814906 Set Vref, RX VrefLevel [Byte0]: 41
1670 09:31:11.817918 [Byte1]: 41
1671 09:31:11.822419
1672 09:31:11.822499 Set Vref, RX VrefLevel [Byte0]: 42
1673 09:31:11.825790 [Byte1]: 42
1674 09:31:11.829908
1675 09:31:11.829988 Set Vref, RX VrefLevel [Byte0]: 43
1676 09:31:11.833184 [Byte1]: 43
1677 09:31:11.837499
1678 09:31:11.837578 Set Vref, RX VrefLevel [Byte0]: 44
1679 09:31:11.841097 [Byte1]: 44
1680 09:31:11.845112
1681 09:31:11.845192 Set Vref, RX VrefLevel [Byte0]: 45
1682 09:31:11.848766 [Byte1]: 45
1683 09:31:11.852694
1684 09:31:11.852774 Set Vref, RX VrefLevel [Byte0]: 46
1685 09:31:11.856024 [Byte1]: 46
1686 09:31:11.860526
1687 09:31:11.860606 Set Vref, RX VrefLevel [Byte0]: 47
1688 09:31:11.863889 [Byte1]: 47
1689 09:31:11.868056
1690 09:31:11.868136 Set Vref, RX VrefLevel [Byte0]: 48
1691 09:31:11.871872 [Byte1]: 48
1692 09:31:11.875863
1693 09:31:11.875943 Set Vref, RX VrefLevel [Byte0]: 49
1694 09:31:11.879065 [Byte1]: 49
1695 09:31:11.883567
1696 09:31:11.883646 Set Vref, RX VrefLevel [Byte0]: 50
1697 09:31:11.887138 [Byte1]: 50
1698 09:31:11.890995
1699 09:31:11.891075 Set Vref, RX VrefLevel [Byte0]: 51
1700 09:31:11.894322 [Byte1]: 51
1701 09:31:11.898864
1702 09:31:11.898944 Set Vref, RX VrefLevel [Byte0]: 52
1703 09:31:11.901837 [Byte1]: 52
1704 09:31:11.906290
1705 09:31:11.906370 Set Vref, RX VrefLevel [Byte0]: 53
1706 09:31:11.909609 [Byte1]: 53
1707 09:31:11.913893
1708 09:31:11.913974 Set Vref, RX VrefLevel [Byte0]: 54
1709 09:31:11.917467 [Byte1]: 54
1710 09:31:11.921865
1711 09:31:11.921945 Set Vref, RX VrefLevel [Byte0]: 55
1712 09:31:11.925272 [Byte1]: 55
1713 09:31:11.929626
1714 09:31:11.929707 Set Vref, RX VrefLevel [Byte0]: 56
1715 09:31:11.932908 [Byte1]: 56
1716 09:31:11.937233
1717 09:31:11.937312 Set Vref, RX VrefLevel [Byte0]: 57
1718 09:31:11.940418 [Byte1]: 57
1719 09:31:11.944469
1720 09:31:11.944549 Set Vref, RX VrefLevel [Byte0]: 58
1721 09:31:11.948131 [Byte1]: 58
1722 09:31:11.952177
1723 09:31:11.952257 Set Vref, RX VrefLevel [Byte0]: 59
1724 09:31:11.955407 [Byte1]: 59
1725 09:31:11.959710
1726 09:31:11.959789 Set Vref, RX VrefLevel [Byte0]: 60
1727 09:31:11.963198 [Byte1]: 60
1728 09:31:11.967520
1729 09:31:11.967600 Set Vref, RX VrefLevel [Byte0]: 61
1730 09:31:11.971019 [Byte1]: 61
1731 09:31:11.975200
1732 09:31:11.975281 Set Vref, RX VrefLevel [Byte0]: 62
1733 09:31:11.978418 [Byte1]: 62
1734 09:31:11.983007
1735 09:31:11.983087 Set Vref, RX VrefLevel [Byte0]: 63
1736 09:31:11.986165 [Byte1]: 63
1737 09:31:11.990400
1738 09:31:11.990480 Set Vref, RX VrefLevel [Byte0]: 64
1739 09:31:11.993704 [Byte1]: 64
1740 09:31:11.998033
1741 09:31:11.998114 Set Vref, RX VrefLevel [Byte0]: 65
1742 09:31:12.001618 [Byte1]: 65
1743 09:31:12.005947
1744 09:31:12.006027 Set Vref, RX VrefLevel [Byte0]: 66
1745 09:31:12.009006 [Byte1]: 66
1746 09:31:12.013306
1747 09:31:12.013385 Set Vref, RX VrefLevel [Byte0]: 67
1748 09:31:12.019791 [Byte1]: 67
1749 09:31:12.019870
1750 09:31:12.023561 Set Vref, RX VrefLevel [Byte0]: 68
1751 09:31:12.026576 [Byte1]: 68
1752 09:31:12.026655
1753 09:31:12.029941 Set Vref, RX VrefLevel [Byte0]: 69
1754 09:31:12.033289 [Byte1]: 69
1755 09:31:12.036577
1756 09:31:12.036656 Set Vref, RX VrefLevel [Byte0]: 70
1757 09:31:12.040001 [Byte1]: 70
1758 09:31:12.044461
1759 09:31:12.044539 Set Vref, RX VrefLevel [Byte0]: 71
1760 09:31:12.047228 [Byte1]: 71
1761 09:31:12.052006
1762 09:31:12.052085 Set Vref, RX VrefLevel [Byte0]: 72
1763 09:31:12.055083 [Byte1]: 72
1764 09:31:12.059327
1765 09:31:12.059444 Set Vref, RX VrefLevel [Byte0]: 73
1766 09:31:12.062561 [Byte1]: 73
1767 09:31:12.067130
1768 09:31:12.067209 Set Vref, RX VrefLevel [Byte0]: 74
1769 09:31:12.070144 [Byte1]: 74
1770 09:31:12.074571
1771 09:31:12.074650 Final RX Vref Byte 0 = 60 to rank0
1772 09:31:12.077977 Final RX Vref Byte 1 = 55 to rank0
1773 09:31:12.081680 Final RX Vref Byte 0 = 60 to rank1
1774 09:31:12.085197 Final RX Vref Byte 1 = 55 to rank1==
1775 09:31:12.088239 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 09:31:12.094899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 09:31:12.094984 ==
1778 09:31:12.095048 DQS Delay:
1779 09:31:12.095105 DQS0 = 0, DQS1 = 0
1780 09:31:12.097752 DQM Delay:
1781 09:31:12.097831 DQM0 = 80, DQM1 = 71
1782 09:31:12.101147 DQ Delay:
1783 09:31:12.104759 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1784 09:31:12.104853 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1785 09:31:12.108242 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1786 09:31:12.114469 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1787 09:31:12.114548
1788 09:31:12.114627
1789 09:31:12.121472 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1790 09:31:12.124733 CH1 RK0: MR19=606, MR18=151F
1791 09:31:12.131145 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1792 09:31:12.131225
1793 09:31:12.134855 ----->DramcWriteLeveling(PI) begin...
1794 09:31:12.134936 ==
1795 09:31:12.137863 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 09:31:12.141087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 09:31:12.141166 ==
1798 09:31:12.144526 Write leveling (Byte 0): 27 => 27
1799 09:31:12.147764 Write leveling (Byte 1): 29 => 29
1800 09:31:12.151071 DramcWriteLeveling(PI) end<-----
1801 09:31:12.151149
1802 09:31:12.151211 ==
1803 09:31:12.154421 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 09:31:12.158091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 09:31:12.158170 ==
1806 09:31:12.161239 [Gating] SW mode calibration
1807 09:31:12.167846 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 09:31:12.174377 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 09:31:12.177702 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1810 09:31:12.181509 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1811 09:31:12.188129 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 09:31:12.191294 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 09:31:12.194662 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 09:31:12.201184 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:31:12.204668 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:31:12.207816 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:31:12.214771 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:31:12.218118 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:31:12.221563 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:31:12.228327 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:31:12.231711 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:31:12.234993 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:31:12.238086 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:31:12.244627 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:31:12.248281 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:31:12.251573 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1827 09:31:12.258330 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:31:12.261494 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:31:12.264538 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:31:12.271647 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:31:12.274993 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:31:12.277944 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:31:12.284827 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:31:12.288339 0 9 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1835 09:31:12.291535 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1836 09:31:12.298231 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 09:31:12.301366 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 09:31:12.304549 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 09:31:12.311362 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 09:31:12.314703 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 09:31:12.318025 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 09:31:12.321268 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (1 1)
1843 09:31:12.328093 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1844 09:31:12.331657 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:31:12.335029 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:31:12.341655 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:31:12.344599 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:31:12.348093 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:31:12.354852 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1850 09:31:12.358139 0 11 4 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1851 09:31:12.361524 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1852 09:31:12.368043 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 09:31:12.371712 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 09:31:12.374902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 09:31:12.381409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 09:31:12.384559 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 09:31:12.387720 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 09:31:12.394477 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1859 09:31:12.398010 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1860 09:31:12.401759 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 09:31:12.407863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 09:31:12.411802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 09:31:12.414517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 09:31:12.417976 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:31:12.424740 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:31:12.428080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:31:12.431300 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:31:12.438261 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 09:31:12.441666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 09:31:12.445138 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:31:12.451180 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 09:31:12.454924 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:31:12.457851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1874 09:31:12.464720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1875 09:31:12.468355 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 09:31:12.471637 Total UI for P1: 0, mck2ui 16
1877 09:31:12.474542 best dqsien dly found for B0: ( 0, 14, 2)
1878 09:31:12.477819 Total UI for P1: 0, mck2ui 16
1879 09:31:12.481475 best dqsien dly found for B1: ( 0, 14, 6)
1880 09:31:12.484914 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1881 09:31:12.488253 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1882 09:31:12.488333
1883 09:31:12.491406 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1884 09:31:12.494599 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1885 09:31:12.497902 [Gating] SW calibration Done
1886 09:31:12.497982 ==
1887 09:31:12.501440 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 09:31:12.505024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 09:31:12.505105 ==
1890 09:31:12.508087 RX Vref Scan: 0
1891 09:31:12.508167
1892 09:31:12.511512 RX Vref 0 -> 0, step: 1
1893 09:31:12.511592
1894 09:31:12.511655 RX Delay -130 -> 252, step: 16
1895 09:31:12.518251 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1896 09:31:12.521509 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1897 09:31:12.524625 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1898 09:31:12.527769 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1899 09:31:12.531704 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1900 09:31:12.538058 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1901 09:31:12.541367 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1902 09:31:12.544723 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1903 09:31:12.548162 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1904 09:31:12.551254 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1905 09:31:12.558061 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1906 09:31:12.561478 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1907 09:31:12.564713 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1908 09:31:12.568481 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1909 09:31:12.571318 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1910 09:31:12.577808 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1911 09:31:12.577889 ==
1912 09:31:12.581244 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 09:31:12.584682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 09:31:12.584763 ==
1915 09:31:12.584827 DQS Delay:
1916 09:31:12.587846 DQS0 = 0, DQS1 = 0
1917 09:31:12.587927 DQM Delay:
1918 09:31:12.591590 DQM0 = 78, DQM1 = 77
1919 09:31:12.591669 DQ Delay:
1920 09:31:12.594889 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1921 09:31:12.598289 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1922 09:31:12.601587 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1923 09:31:12.604827 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1924 09:31:12.604907
1925 09:31:12.604971
1926 09:31:12.605029 ==
1927 09:31:12.608145 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 09:31:12.612015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 09:31:12.612096 ==
1930 09:31:12.612159
1931 09:31:12.614632
1932 09:31:12.614712 TX Vref Scan disable
1933 09:31:12.618456 == TX Byte 0 ==
1934 09:31:12.621160 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 09:31:12.624994 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 09:31:12.627835 == TX Byte 1 ==
1937 09:31:12.631076 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 09:31:12.634489 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 09:31:12.634569 ==
1940 09:31:12.638040 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 09:31:12.644810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 09:31:12.644917 ==
1943 09:31:12.656659 TX Vref=22, minBit 0, minWin=28, winSum=449
1944 09:31:12.659619 TX Vref=24, minBit 6, minWin=27, winSum=450
1945 09:31:12.663614 TX Vref=26, minBit 1, minWin=28, winSum=455
1946 09:31:12.666491 TX Vref=28, minBit 1, minWin=27, winSum=459
1947 09:31:12.670078 TX Vref=30, minBit 1, minWin=28, winSum=465
1948 09:31:12.673234 TX Vref=32, minBit 0, minWin=28, winSum=460
1949 09:31:12.679882 [TxChooseVref] Worse bit 1, Min win 28, Win sum 465, Final Vref 30
1950 09:31:12.679963
1951 09:31:12.683079 Final TX Range 1 Vref 30
1952 09:31:12.683160
1953 09:31:12.683224 ==
1954 09:31:12.686797 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 09:31:12.689817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 09:31:12.689898 ==
1957 09:31:12.689961
1958 09:31:12.693230
1959 09:31:12.693309 TX Vref Scan disable
1960 09:31:12.696353 == TX Byte 0 ==
1961 09:31:12.699672 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 09:31:12.706463 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 09:31:12.706544 == TX Byte 1 ==
1964 09:31:12.710234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1965 09:31:12.713144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1966 09:31:12.716842
1967 09:31:12.716922 [DATLAT]
1968 09:31:12.716986 Freq=800, CH1 RK1
1969 09:31:12.717045
1970 09:31:12.720076 DATLAT Default: 0xa
1971 09:31:12.720157 0, 0xFFFF, sum = 0
1972 09:31:12.723426 1, 0xFFFF, sum = 0
1973 09:31:12.723558 2, 0xFFFF, sum = 0
1974 09:31:12.726441 3, 0xFFFF, sum = 0
1975 09:31:12.726522 4, 0xFFFF, sum = 0
1976 09:31:12.730158 5, 0xFFFF, sum = 0
1977 09:31:12.730239 6, 0xFFFF, sum = 0
1978 09:31:12.732957 7, 0xFFFF, sum = 0
1979 09:31:12.736302 8, 0xFFFF, sum = 0
1980 09:31:12.736383 9, 0x0, sum = 1
1981 09:31:12.736448 10, 0x0, sum = 2
1982 09:31:12.739907 11, 0x0, sum = 3
1983 09:31:12.739989 12, 0x0, sum = 4
1984 09:31:12.742838 best_step = 10
1985 09:31:12.742918
1986 09:31:12.742982 ==
1987 09:31:12.746614 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 09:31:12.749512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 09:31:12.749593 ==
1990 09:31:12.753196 RX Vref Scan: 0
1991 09:31:12.753276
1992 09:31:12.753340 RX Vref 0 -> 0, step: 1
1993 09:31:12.753399
1994 09:31:12.756514 RX Delay -111 -> 252, step: 8
1995 09:31:12.763040 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1996 09:31:12.766662 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1997 09:31:12.770000 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1998 09:31:12.773480 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1999 09:31:12.776569 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2000 09:31:12.783324 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2001 09:31:12.786723 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2002 09:31:12.790077 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2003 09:31:12.793746 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2004 09:31:12.796663 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2005 09:31:12.803768 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2006 09:31:12.807316 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2007 09:31:12.810100 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2008 09:31:12.813470 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2009 09:31:12.816654 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2010 09:31:12.823703 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2011 09:31:12.823808 ==
2012 09:31:12.826478 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 09:31:12.830220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 09:31:12.830423 ==
2015 09:31:12.830545 DQS Delay:
2016 09:31:12.833540 DQS0 = 0, DQS1 = 0
2017 09:31:12.833689 DQM Delay:
2018 09:31:12.837063 DQM0 = 78, DQM1 = 74
2019 09:31:12.837200 DQ Delay:
2020 09:31:12.840356 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2021 09:31:12.843665 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2022 09:31:12.847189 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2023 09:31:12.850254 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2024 09:31:12.850468
2025 09:31:12.850611
2026 09:31:12.857250 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2027 09:31:12.860248 CH1 RK1: MR19=606, MR18=1F38
2028 09:31:12.867346 CH1_RK1: MR19=0x606, MR18=0x1F38, DQSOSC=395, MR23=63, INC=94, DEC=63
2029 09:31:12.870560 [RxdqsGatingPostProcess] freq 800
2030 09:31:12.877406 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 09:31:12.880271 Pre-setting of DQS Precalculation
2032 09:31:12.883938 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 09:31:12.890538 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 09:31:12.897516 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 09:31:12.898045
2036 09:31:12.898353
2037 09:31:12.900060 [Calibration Summary] 1600 Mbps
2038 09:31:12.903429 CH 0, Rank 0
2039 09:31:12.903808 SW Impedance : PASS
2040 09:31:12.907196 DUTY Scan : NO K
2041 09:31:12.910558 ZQ Calibration : PASS
2042 09:31:12.911245 Jitter Meter : NO K
2043 09:31:12.913976 CBT Training : PASS
2044 09:31:12.916985 Write leveling : PASS
2045 09:31:12.917367 RX DQS gating : PASS
2046 09:31:12.920070 RX DQ/DQS(RDDQC) : PASS
2047 09:31:12.923440 TX DQ/DQS : PASS
2048 09:31:12.923823 RX DATLAT : PASS
2049 09:31:12.927362 RX DQ/DQS(Engine): PASS
2050 09:31:12.927889 TX OE : NO K
2051 09:31:12.930331 All Pass.
2052 09:31:12.930818
2053 09:31:12.931119 CH 0, Rank 1
2054 09:31:12.933399 SW Impedance : PASS
2055 09:31:12.933778 DUTY Scan : NO K
2056 09:31:12.937064 ZQ Calibration : PASS
2057 09:31:12.940315 Jitter Meter : NO K
2058 09:31:12.940802 CBT Training : PASS
2059 09:31:12.944000 Write leveling : PASS
2060 09:31:12.947124 RX DQS gating : PASS
2061 09:31:12.947642 RX DQ/DQS(RDDQC) : PASS
2062 09:31:12.950215 TX DQ/DQS : PASS
2063 09:31:12.953995 RX DATLAT : PASS
2064 09:31:12.954484 RX DQ/DQS(Engine): PASS
2065 09:31:12.957066 TX OE : NO K
2066 09:31:12.957445 All Pass.
2067 09:31:12.957748
2068 09:31:12.960433 CH 1, Rank 0
2069 09:31:12.960957 SW Impedance : PASS
2070 09:31:12.963974 DUTY Scan : NO K
2071 09:31:12.967103 ZQ Calibration : PASS
2072 09:31:12.967541 Jitter Meter : NO K
2073 09:31:12.970575 CBT Training : PASS
2074 09:31:12.971061 Write leveling : PASS
2075 09:31:12.973662 RX DQS gating : PASS
2076 09:31:12.976941 RX DQ/DQS(RDDQC) : PASS
2077 09:31:12.977317 TX DQ/DQS : PASS
2078 09:31:12.980302 RX DATLAT : PASS
2079 09:31:12.983658 RX DQ/DQS(Engine): PASS
2080 09:31:12.984044 TX OE : NO K
2081 09:31:12.987136 All Pass.
2082 09:31:12.987561
2083 09:31:12.987866 CH 1, Rank 1
2084 09:31:12.990361 SW Impedance : PASS
2085 09:31:12.990849 DUTY Scan : NO K
2086 09:31:12.993873 ZQ Calibration : PASS
2087 09:31:12.996947 Jitter Meter : NO K
2088 09:31:12.997453 CBT Training : PASS
2089 09:31:13.000018 Write leveling : PASS
2090 09:31:13.003537 RX DQS gating : PASS
2091 09:31:13.003913 RX DQ/DQS(RDDQC) : PASS
2092 09:31:13.006860 TX DQ/DQS : PASS
2093 09:31:13.010344 RX DATLAT : PASS
2094 09:31:13.010830 RX DQ/DQS(Engine): PASS
2095 09:31:13.013865 TX OE : NO K
2096 09:31:13.014352 All Pass.
2097 09:31:13.014659
2098 09:31:13.016904 DramC Write-DBI off
2099 09:31:13.020204 PER_BANK_REFRESH: Hybrid Mode
2100 09:31:13.020583 TX_TRACKING: ON
2101 09:31:13.023486 [GetDramInforAfterCalByMRR] Vendor 6.
2102 09:31:13.027215 [GetDramInforAfterCalByMRR] Revision 606.
2103 09:31:13.030205 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 09:31:13.033183 MR0 0x3b3b
2105 09:31:13.033563 MR8 0x5151
2106 09:31:13.036635 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 09:31:13.037020
2108 09:31:13.037325 MR0 0x3b3b
2109 09:31:13.040336 MR8 0x5151
2110 09:31:13.043161 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 09:31:13.043680
2112 09:31:13.050037 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 09:31:13.056674 [FAST_K] Save calibration result to emmc
2114 09:31:13.060106 [FAST_K] Save calibration result to emmc
2115 09:31:13.060484 dram_init: config_dvfs: 1
2116 09:31:13.066350 dramc_set_vcore_voltage set vcore to 662500
2117 09:31:13.066730 Read voltage for 1200, 2
2118 09:31:13.067045 Vio18 = 0
2119 09:31:13.070017 Vcore = 662500
2120 09:31:13.070395 Vdram = 0
2121 09:31:13.070698 Vddq = 0
2122 09:31:13.073953 Vmddr = 0
2123 09:31:13.076330 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 09:31:13.083267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 09:31:13.086443 MEM_TYPE=3, freq_sel=15
2126 09:31:13.086828 sv_algorithm_assistance_LP4_1600
2127 09:31:13.093708 ============ PULL DRAM RESETB DOWN ============
2128 09:31:13.096431 ========== PULL DRAM RESETB DOWN end =========
2129 09:31:13.099933 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 09:31:13.103160 ===================================
2131 09:31:13.107174 LPDDR4 DRAM CONFIGURATION
2132 09:31:13.110342 ===================================
2133 09:31:13.113892 EX_ROW_EN[0] = 0x0
2134 09:31:13.114413 EX_ROW_EN[1] = 0x0
2135 09:31:13.117150 LP4Y_EN = 0x0
2136 09:31:13.117669 WORK_FSP = 0x0
2137 09:31:13.120696 WL = 0x4
2138 09:31:13.121219 RL = 0x4
2139 09:31:13.123438 BL = 0x2
2140 09:31:13.123859 RPST = 0x0
2141 09:31:13.126693 RD_PRE = 0x0
2142 09:31:13.127114 WR_PRE = 0x1
2143 09:31:13.129714 WR_PST = 0x0
2144 09:31:13.130132 DBI_WR = 0x0
2145 09:31:13.133530 DBI_RD = 0x0
2146 09:31:13.133948 OTF = 0x1
2147 09:31:13.136767 ===================================
2148 09:31:13.140074 ===================================
2149 09:31:13.143243 ANA top config
2150 09:31:13.146608 ===================================
2151 09:31:13.147170 DLL_ASYNC_EN = 0
2152 09:31:13.149932 ALL_SLAVE_EN = 0
2153 09:31:13.153493 NEW_RANK_MODE = 1
2154 09:31:13.156646 DLL_IDLE_MODE = 1
2155 09:31:13.159470 LP45_APHY_COMB_EN = 1
2156 09:31:13.159695 TX_ODT_DIS = 1
2157 09:31:13.163262 NEW_8X_MODE = 1
2158 09:31:13.166421 ===================================
2159 09:31:13.169743 ===================================
2160 09:31:13.173311 data_rate = 2400
2161 09:31:13.176543 CKR = 1
2162 09:31:13.180009 DQ_P2S_RATIO = 8
2163 09:31:13.183186 ===================================
2164 09:31:13.183446 CA_P2S_RATIO = 8
2165 09:31:13.186575 DQ_CA_OPEN = 0
2166 09:31:13.190037 DQ_SEMI_OPEN = 0
2167 09:31:13.193110 CA_SEMI_OPEN = 0
2168 09:31:13.196604 CA_FULL_RATE = 0
2169 09:31:13.199993 DQ_CKDIV4_EN = 0
2170 09:31:13.200376 CA_CKDIV4_EN = 0
2171 09:31:13.203323 CA_PREDIV_EN = 0
2172 09:31:13.207035 PH8_DLY = 17
2173 09:31:13.210387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 09:31:13.213194 DQ_AAMCK_DIV = 4
2175 09:31:13.217147 CA_AAMCK_DIV = 4
2176 09:31:13.217675 CA_ADMCK_DIV = 4
2177 09:31:13.219875 DQ_TRACK_CA_EN = 0
2178 09:31:13.223728 CA_PICK = 1200
2179 09:31:13.226768 CA_MCKIO = 1200
2180 09:31:13.230390 MCKIO_SEMI = 0
2181 09:31:13.234041 PLL_FREQ = 2366
2182 09:31:13.236522 DQ_UI_PI_RATIO = 32
2183 09:31:13.236946 CA_UI_PI_RATIO = 0
2184 09:31:13.239970 ===================================
2185 09:31:13.243553 ===================================
2186 09:31:13.246362 memory_type:LPDDR4
2187 09:31:13.249715 GP_NUM : 10
2188 09:31:13.250139 SRAM_EN : 1
2189 09:31:13.253225 MD32_EN : 0
2190 09:31:13.256563 ===================================
2191 09:31:13.259879 [ANA_INIT] >>>>>>>>>>>>>>
2192 09:31:13.263296 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 09:31:13.266477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 09:31:13.270114 ===================================
2195 09:31:13.270542 data_rate = 2400,PCW = 0X5b00
2196 09:31:13.273420 ===================================
2197 09:31:13.276517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 09:31:13.283451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 09:31:13.290300 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 09:31:13.293624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 09:31:13.296938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 09:31:13.300056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 09:31:13.303006 [ANA_INIT] flow start
2204 09:31:13.303462 [ANA_INIT] PLL >>>>>>>>
2205 09:31:13.306858 [ANA_INIT] PLL <<<<<<<<
2206 09:31:13.310155 [ANA_INIT] MIDPI >>>>>>>>
2207 09:31:13.313403 [ANA_INIT] MIDPI <<<<<<<<
2208 09:31:13.313823 [ANA_INIT] DLL >>>>>>>>
2209 09:31:13.316928 [ANA_INIT] DLL <<<<<<<<
2210 09:31:13.317345 [ANA_INIT] flow end
2211 09:31:13.323613 ============ LP4 DIFF to SE enter ============
2212 09:31:13.326330 ============ LP4 DIFF to SE exit ============
2213 09:31:13.330440 [ANA_INIT] <<<<<<<<<<<<<
2214 09:31:13.333295 [Flow] Enable top DCM control >>>>>
2215 09:31:13.336544 [Flow] Enable top DCM control <<<<<
2216 09:31:13.340166 Enable DLL master slave shuffle
2217 09:31:13.343706 ==============================================================
2218 09:31:13.346769 Gating Mode config
2219 09:31:13.349451 ==============================================================
2220 09:31:13.353371 Config description:
2221 09:31:13.363734 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 09:31:13.369924 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 09:31:13.373395 SELPH_MODE 0: By rank 1: By Phase
2224 09:31:13.379854 ==============================================================
2225 09:31:13.383203 GAT_TRACK_EN = 1
2226 09:31:13.386911 RX_GATING_MODE = 2
2227 09:31:13.389850 RX_GATING_TRACK_MODE = 2
2228 09:31:13.393369 SELPH_MODE = 1
2229 09:31:13.393892 PICG_EARLY_EN = 1
2230 09:31:13.396900 VALID_LAT_VALUE = 1
2231 09:31:13.403195 ==============================================================
2232 09:31:13.406494 Enter into Gating configuration >>>>
2233 09:31:13.409654 Exit from Gating configuration <<<<
2234 09:31:13.412898 Enter into DVFS_PRE_config >>>>>
2235 09:31:13.422969 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 09:31:13.426512 Exit from DVFS_PRE_config <<<<<
2237 09:31:13.429519 Enter into PICG configuration >>>>
2238 09:31:13.433298 Exit from PICG configuration <<<<
2239 09:31:13.436439 [RX_INPUT] configuration >>>>>
2240 09:31:13.439959 [RX_INPUT] configuration <<<<<
2241 09:31:13.443511 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 09:31:13.449842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 09:31:13.456420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 09:31:13.462953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 09:31:13.469797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 09:31:13.473099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 09:31:13.479804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 09:31:13.482977 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 09:31:13.486504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 09:31:13.489998 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 09:31:13.492843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 09:31:13.499652 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 09:31:13.502534 ===================================
2254 09:31:13.505960 LPDDR4 DRAM CONFIGURATION
2255 09:31:13.509414 ===================================
2256 09:31:13.509832 EX_ROW_EN[0] = 0x0
2257 09:31:13.512933 EX_ROW_EN[1] = 0x0
2258 09:31:13.513332 LP4Y_EN = 0x0
2259 09:31:13.516215 WORK_FSP = 0x0
2260 09:31:13.516629 WL = 0x4
2261 09:31:13.519241 RL = 0x4
2262 09:31:13.519696 BL = 0x2
2263 09:31:13.522939 RPST = 0x0
2264 09:31:13.523520 RD_PRE = 0x0
2265 09:31:13.526357 WR_PRE = 0x1
2266 09:31:13.526875 WR_PST = 0x0
2267 09:31:13.529459 DBI_WR = 0x0
2268 09:31:13.529874 DBI_RD = 0x0
2269 09:31:13.533215 OTF = 0x1
2270 09:31:13.535919 ===================================
2271 09:31:13.539292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 09:31:13.542496 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 09:31:13.550130 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 09:31:13.553773 ===================================
2275 09:31:13.554294 LPDDR4 DRAM CONFIGURATION
2276 09:31:13.556126 ===================================
2277 09:31:13.559285 EX_ROW_EN[0] = 0x10
2278 09:31:13.562652 EX_ROW_EN[1] = 0x0
2279 09:31:13.563062 LP4Y_EN = 0x0
2280 09:31:13.566274 WORK_FSP = 0x0
2281 09:31:13.566811 WL = 0x4
2282 09:31:13.569807 RL = 0x4
2283 09:31:13.570223 BL = 0x2
2284 09:31:13.573433 RPST = 0x0
2285 09:31:13.573956 RD_PRE = 0x0
2286 09:31:13.575739 WR_PRE = 0x1
2287 09:31:13.576152 WR_PST = 0x0
2288 09:31:13.579382 DBI_WR = 0x0
2289 09:31:13.579838 DBI_RD = 0x0
2290 09:31:13.582731 OTF = 0x1
2291 09:31:13.586127 ===================================
2292 09:31:13.592974 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 09:31:13.593354 ==
2294 09:31:13.595815 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 09:31:13.599449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 09:31:13.599829 ==
2297 09:31:13.602230 [Duty_Offset_Calibration]
2298 09:31:13.602605 B0:2 B1:0 CA:3
2299 09:31:13.602901
2300 09:31:13.605369 [DutyScan_Calibration_Flow] k_type=0
2301 09:31:13.616439
2302 09:31:13.616911 ==CLK 0==
2303 09:31:13.619671 Final CLK duty delay cell = 0
2304 09:31:13.623281 [0] MAX Duty = 5031%(X100), DQS PI = 12
2305 09:31:13.625952 [0] MIN Duty = 4875%(X100), DQS PI = 58
2306 09:31:13.626462 [0] AVG Duty = 4953%(X100)
2307 09:31:13.629435
2308 09:31:13.632935 CH0 CLK Duty spec in!! Max-Min= 156%
2309 09:31:13.636430 [DutyScan_Calibration_Flow] ====Done====
2310 09:31:13.636945
2311 09:31:13.639367 [DutyScan_Calibration_Flow] k_type=1
2312 09:31:13.654673
2313 09:31:13.655093 ==DQS 0 ==
2314 09:31:13.658166 Final DQS duty delay cell = 0
2315 09:31:13.661103 [0] MAX Duty = 5093%(X100), DQS PI = 28
2316 09:31:13.664668 [0] MIN Duty = 4907%(X100), DQS PI = 44
2317 09:31:13.668282 [0] AVG Duty = 5000%(X100)
2318 09:31:13.668676
2319 09:31:13.668976 ==DQS 1 ==
2320 09:31:13.671241 Final DQS duty delay cell = -4
2321 09:31:13.674598 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2322 09:31:13.678069 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2323 09:31:13.681504 [-4] AVG Duty = 4922%(X100)
2324 09:31:13.681880
2325 09:31:13.684619 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2326 09:31:13.684995
2327 09:31:13.688145 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2328 09:31:13.691462 [DutyScan_Calibration_Flow] ====Done====
2329 09:31:13.691840
2330 09:31:13.694771 [DutyScan_Calibration_Flow] k_type=3
2331 09:31:13.712260
2332 09:31:13.712850 ==DQM 0 ==
2333 09:31:13.715512 Final DQM duty delay cell = 0
2334 09:31:13.718772 [0] MAX Duty = 5124%(X100), DQS PI = 12
2335 09:31:13.722230 [0] MIN Duty = 4876%(X100), DQS PI = 0
2336 09:31:13.722606 [0] AVG Duty = 5000%(X100)
2337 09:31:13.725731
2338 09:31:13.726109 ==DQM 1 ==
2339 09:31:13.728653 Final DQM duty delay cell = 4
2340 09:31:13.732439 [4] MAX Duty = 5124%(X100), DQS PI = 50
2341 09:31:13.735175 [4] MIN Duty = 5031%(X100), DQS PI = 12
2342 09:31:13.738606 [4] AVG Duty = 5077%(X100)
2343 09:31:13.738980
2344 09:31:13.741998 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2345 09:31:13.742376
2346 09:31:13.745431 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2347 09:31:13.748905 [DutyScan_Calibration_Flow] ====Done====
2348 09:31:13.749282
2349 09:31:13.752291 [DutyScan_Calibration_Flow] k_type=2
2350 09:31:13.766958
2351 09:31:13.767483 ==DQ 0 ==
2352 09:31:13.770445 Final DQ duty delay cell = -4
2353 09:31:13.774001 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2354 09:31:13.777189 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2355 09:31:13.780512 [-4] AVG Duty = 4953%(X100)
2356 09:31:13.780999
2357 09:31:13.781307 ==DQ 1 ==
2358 09:31:13.783630 Final DQ duty delay cell = -4
2359 09:31:13.786922 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2360 09:31:13.790330 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2361 09:31:13.793854 [-4] AVG Duty = 4938%(X100)
2362 09:31:13.794276
2363 09:31:13.797112 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2364 09:31:13.797490
2365 09:31:13.800437 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2366 09:31:13.803863 [DutyScan_Calibration_Flow] ====Done====
2367 09:31:13.804240 ==
2368 09:31:13.807053 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 09:31:13.810545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 09:31:13.810934 ==
2371 09:31:13.813783 [Duty_Offset_Calibration]
2372 09:31:13.814161 B0:1 B1:-2 CA:0
2373 09:31:13.814460
2374 09:31:13.817242 [DutyScan_Calibration_Flow] k_type=0
2375 09:31:13.827695
2376 09:31:13.828072 ==CLK 0==
2377 09:31:13.831284 Final CLK duty delay cell = 0
2378 09:31:13.834387 [0] MAX Duty = 5062%(X100), DQS PI = 30
2379 09:31:13.837861 [0] MIN Duty = 4876%(X100), DQS PI = 0
2380 09:31:13.838238 [0] AVG Duty = 4969%(X100)
2381 09:31:13.841398
2382 09:31:13.841781 CH1 CLK Duty spec in!! Max-Min= 186%
2383 09:31:13.847506 [DutyScan_Calibration_Flow] ====Done====
2384 09:31:13.848006
2385 09:31:13.850880 [DutyScan_Calibration_Flow] k_type=1
2386 09:31:13.865841
2387 09:31:13.866338 ==DQS 0 ==
2388 09:31:13.869381 Final DQS duty delay cell = -4
2389 09:31:13.872890 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2390 09:31:13.876019 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2391 09:31:13.879630 [-4] AVG Duty = 4953%(X100)
2392 09:31:13.880001
2393 09:31:13.880298 ==DQS 1 ==
2394 09:31:13.882969 Final DQS duty delay cell = 0
2395 09:31:13.885848 [0] MAX Duty = 5093%(X100), DQS PI = 0
2396 09:31:13.889088 [0] MIN Duty = 4844%(X100), DQS PI = 28
2397 09:31:13.893166 [0] AVG Duty = 4968%(X100)
2398 09:31:13.893546
2399 09:31:13.895821 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2400 09:31:13.896347
2401 09:31:13.899177 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2402 09:31:13.902631 [DutyScan_Calibration_Flow] ====Done====
2403 09:31:13.903010
2404 09:31:13.906065 [DutyScan_Calibration_Flow] k_type=3
2405 09:31:13.922451
2406 09:31:13.922831 ==DQM 0 ==
2407 09:31:13.926094 Final DQM duty delay cell = 0
2408 09:31:13.929330 [0] MAX Duty = 5000%(X100), DQS PI = 22
2409 09:31:13.932610 [0] MIN Duty = 4844%(X100), DQS PI = 52
2410 09:31:13.936214 [0] AVG Duty = 4922%(X100)
2411 09:31:13.936595
2412 09:31:13.936899 ==DQM 1 ==
2413 09:31:13.939304 Final DQM duty delay cell = 0
2414 09:31:13.942760 [0] MAX Duty = 5031%(X100), DQS PI = 36
2415 09:31:13.945709 [0] MIN Duty = 4907%(X100), DQS PI = 0
2416 09:31:13.949126 [0] AVG Duty = 4969%(X100)
2417 09:31:13.949504
2418 09:31:13.952408 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2419 09:31:13.952785
2420 09:31:13.955794 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2421 09:31:13.959287 [DutyScan_Calibration_Flow] ====Done====
2422 09:31:13.959727
2423 09:31:13.962240 [DutyScan_Calibration_Flow] k_type=2
2424 09:31:13.978975
2425 09:31:13.979356 ==DQ 0 ==
2426 09:31:13.982317 Final DQ duty delay cell = 0
2427 09:31:13.985563 [0] MAX Duty = 5062%(X100), DQS PI = 14
2428 09:31:13.988950 [0] MIN Duty = 4938%(X100), DQS PI = 54
2429 09:31:13.989332 [0] AVG Duty = 5000%(X100)
2430 09:31:13.992206
2431 09:31:13.992673 ==DQ 1 ==
2432 09:31:13.995856 Final DQ duty delay cell = 0
2433 09:31:13.998963 [0] MAX Duty = 5125%(X100), DQS PI = 46
2434 09:31:14.002261 [0] MIN Duty = 4969%(X100), DQS PI = 26
2435 09:31:14.002641 [0] AVG Duty = 5047%(X100)
2436 09:31:14.002944
2437 09:31:14.005595 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2438 09:31:14.008993
2439 09:31:14.012336 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2440 09:31:14.015536 [DutyScan_Calibration_Flow] ====Done====
2441 09:31:14.018668 nWR fixed to 30
2442 09:31:14.019050 [ModeRegInit_LP4] CH0 RK0
2443 09:31:14.022183 [ModeRegInit_LP4] CH0 RK1
2444 09:31:14.025914 [ModeRegInit_LP4] CH1 RK0
2445 09:31:14.026299 [ModeRegInit_LP4] CH1 RK1
2446 09:31:14.028979 match AC timing 7
2447 09:31:14.032003 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 09:31:14.035435 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 09:31:14.042583 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 09:31:14.045979 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 09:31:14.052119 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 09:31:14.052506 ==
2453 09:31:14.055440 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 09:31:14.058741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 09:31:14.059128 ==
2456 09:31:14.065830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 09:31:14.068820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2458 09:31:14.079004 [CA 0] Center 40 (10~71) winsize 62
2459 09:31:14.082828 [CA 1] Center 40 (10~70) winsize 61
2460 09:31:14.085758 [CA 2] Center 36 (6~66) winsize 61
2461 09:31:14.088966 [CA 3] Center 35 (5~66) winsize 62
2462 09:31:14.092063 [CA 4] Center 34 (4~65) winsize 62
2463 09:31:14.095507 [CA 5] Center 33 (3~64) winsize 62
2464 09:31:14.095893
2465 09:31:14.099430 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2466 09:31:14.099817
2467 09:31:14.102382 [CATrainingPosCal] consider 1 rank data
2468 09:31:14.106212 u2DelayCellTimex100 = 270/100 ps
2469 09:31:14.109606 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2470 09:31:14.115938 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2471 09:31:14.118899 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2472 09:31:14.122564 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2473 09:31:14.125956 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2474 09:31:14.129068 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2475 09:31:14.129482
2476 09:31:14.132729 CA PerBit enable=1, Macro0, CA PI delay=33
2477 09:31:14.133149
2478 09:31:14.136108 [CBTSetCACLKResult] CA Dly = 33
2479 09:31:14.136522 CS Dly: 7 (0~38)
2480 09:31:14.139195 ==
2481 09:31:14.142572 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 09:31:14.146317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 09:31:14.146846 ==
2484 09:31:14.148965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 09:31:14.155830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2486 09:31:14.165913 [CA 0] Center 40 (10~70) winsize 61
2487 09:31:14.169087 [CA 1] Center 39 (9~70) winsize 62
2488 09:31:14.172239 [CA 2] Center 35 (5~66) winsize 62
2489 09:31:14.175969 [CA 3] Center 35 (5~66) winsize 62
2490 09:31:14.179217 [CA 4] Center 34 (4~65) winsize 62
2491 09:31:14.182104 [CA 5] Center 33 (3~63) winsize 61
2492 09:31:14.182629
2493 09:31:14.185348 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2494 09:31:14.185771
2495 09:31:14.188958 [CATrainingPosCal] consider 2 rank data
2496 09:31:14.191943 u2DelayCellTimex100 = 270/100 ps
2497 09:31:14.195332 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2498 09:31:14.201720 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2499 09:31:14.205166 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2500 09:31:14.209017 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 09:31:14.212030 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2502 09:31:14.215258 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2503 09:31:14.215707
2504 09:31:14.218482 CA PerBit enable=1, Macro0, CA PI delay=33
2505 09:31:14.218894
2506 09:31:14.221657 [CBTSetCACLKResult] CA Dly = 33
2507 09:31:14.225110 CS Dly: 8 (0~40)
2508 09:31:14.225521
2509 09:31:14.228687 ----->DramcWriteLeveling(PI) begin...
2510 09:31:14.229106 ==
2511 09:31:14.231910 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 09:31:14.235123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 09:31:14.235584 ==
2514 09:31:14.238794 Write leveling (Byte 0): 33 => 33
2515 09:31:14.241481 Write leveling (Byte 1): 29 => 29
2516 09:31:14.244817 DramcWriteLeveling(PI) end<-----
2517 09:31:14.245234
2518 09:31:14.245565 ==
2519 09:31:14.249277 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 09:31:14.251315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 09:31:14.251449 ==
2522 09:31:14.255030 [Gating] SW mode calibration
2523 09:31:14.261330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 09:31:14.268028 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 09:31:14.271247 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 09:31:14.274618 0 15 4 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
2527 09:31:14.281538 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 09:31:14.284958 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 09:31:14.287858 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 09:31:14.294599 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 09:31:14.298060 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 09:31:14.301251 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2533 09:31:14.304686 1 0 0 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
2534 09:31:14.311551 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 09:31:14.315038 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 09:31:14.318139 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 09:31:14.325270 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 09:31:14.328191 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 09:31:14.331167 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 09:31:14.338305 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2541 09:31:14.341474 1 1 0 | B1->B0 | 2727 3333 | 1 0 | (0 0) (0 0)
2542 09:31:14.344564 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2543 09:31:14.351368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 09:31:14.354592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 09:31:14.358040 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 09:31:14.364257 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 09:31:14.367764 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 09:31:14.371305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 09:31:14.377979 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2550 09:31:14.381285 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 09:31:14.384724 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 09:31:14.391848 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 09:31:14.394930 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 09:31:14.397976 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 09:31:14.405166 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:31:14.408301 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:31:14.411734 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 09:31:14.418114 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 09:31:14.421581 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 09:31:14.425250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 09:31:14.431565 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 09:31:14.435074 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:31:14.438191 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:31:14.442015 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 09:31:14.447876 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 09:31:14.451958 Total UI for P1: 0, mck2ui 16
2567 09:31:14.454875 best dqsien dly found for B0: ( 1, 3, 28)
2568 09:31:14.458059 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 09:31:14.461539 Total UI for P1: 0, mck2ui 16
2570 09:31:14.464732 best dqsien dly found for B1: ( 1, 4, 0)
2571 09:31:14.467957 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2572 09:31:14.471281 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2573 09:31:14.471859
2574 09:31:14.474794 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2575 09:31:14.478727 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2576 09:31:14.482211 [Gating] SW calibration Done
2577 09:31:14.482736 ==
2578 09:31:14.484722 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 09:31:14.488295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 09:31:14.491730 ==
2581 09:31:14.492259 RX Vref Scan: 0
2582 09:31:14.492597
2583 09:31:14.494530 RX Vref 0 -> 0, step: 1
2584 09:31:14.494944
2585 09:31:14.498177 RX Delay -40 -> 252, step: 8
2586 09:31:14.501284 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2587 09:31:14.504777 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2588 09:31:14.508208 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2589 09:31:14.511316 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2590 09:31:14.517971 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2591 09:31:14.521469 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2592 09:31:14.524652 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2593 09:31:14.528328 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2594 09:31:14.531598 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2595 09:31:14.535339 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2596 09:31:14.541557 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2597 09:31:14.545455 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2598 09:31:14.547939 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2599 09:31:14.551617 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2600 09:31:14.555155 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2601 09:31:14.561799 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2602 09:31:14.562322 ==
2603 09:31:14.564866 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 09:31:14.568124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 09:31:14.568835 ==
2606 09:31:14.569462 DQS Delay:
2607 09:31:14.571203 DQS0 = 0, DQS1 = 0
2608 09:31:14.571674 DQM Delay:
2609 09:31:14.574426 DQM0 = 112, DQM1 = 103
2610 09:31:14.575015 DQ Delay:
2611 09:31:14.577987 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2612 09:31:14.581727 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2613 09:31:14.584368 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2614 09:31:14.587742 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2615 09:31:14.588158
2616 09:31:14.588512
2617 09:31:14.591092 ==
2618 09:31:14.591556 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 09:31:14.597887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 09:31:14.598304 ==
2621 09:31:14.598635
2622 09:31:14.598942
2623 09:31:14.601522 TX Vref Scan disable
2624 09:31:14.601935 == TX Byte 0 ==
2625 09:31:14.604417 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2626 09:31:14.611746 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2627 09:31:14.612265 == TX Byte 1 ==
2628 09:31:14.614638 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2629 09:31:14.621510 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2630 09:31:14.622014 ==
2631 09:31:14.624296 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 09:31:14.627807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 09:31:14.628249 ==
2634 09:31:14.640245 TX Vref=22, minBit 11, minWin=25, winSum=419
2635 09:31:14.643642 TX Vref=24, minBit 0, minWin=26, winSum=421
2636 09:31:14.646823 TX Vref=26, minBit 7, minWin=25, winSum=427
2637 09:31:14.650105 TX Vref=28, minBit 10, minWin=26, winSum=435
2638 09:31:14.653933 TX Vref=30, minBit 10, minWin=26, winSum=432
2639 09:31:14.660008 TX Vref=32, minBit 3, minWin=26, winSum=429
2640 09:31:14.663599 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2641 09:31:14.664011
2642 09:31:14.666983 Final TX Range 1 Vref 28
2643 09:31:14.667576
2644 09:31:14.668050 ==
2645 09:31:14.670173 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 09:31:14.673339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 09:31:14.673865 ==
2648 09:31:14.676447
2649 09:31:14.676854
2650 09:31:14.677179 TX Vref Scan disable
2651 09:31:14.680043 == TX Byte 0 ==
2652 09:31:14.683529 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2653 09:31:14.686923 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2654 09:31:14.690386 == TX Byte 1 ==
2655 09:31:14.693939 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2656 09:31:14.697358 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2657 09:31:14.699907
2658 09:31:14.700318 [DATLAT]
2659 09:31:14.700642 Freq=1200, CH0 RK0
2660 09:31:14.700944
2661 09:31:14.703690 DATLAT Default: 0xd
2662 09:31:14.704205 0, 0xFFFF, sum = 0
2663 09:31:14.706838 1, 0xFFFF, sum = 0
2664 09:31:14.707361 2, 0xFFFF, sum = 0
2665 09:31:14.710635 3, 0xFFFF, sum = 0
2666 09:31:14.713424 4, 0xFFFF, sum = 0
2667 09:31:14.713940 5, 0xFFFF, sum = 0
2668 09:31:14.716706 6, 0xFFFF, sum = 0
2669 09:31:14.717169 7, 0xFFFF, sum = 0
2670 09:31:14.720053 8, 0xFFFF, sum = 0
2671 09:31:14.720470 9, 0xFFFF, sum = 0
2672 09:31:14.723721 10, 0xFFFF, sum = 0
2673 09:31:14.724237 11, 0xFFFF, sum = 0
2674 09:31:14.727446 12, 0x0, sum = 1
2675 09:31:14.728003 13, 0x0, sum = 2
2676 09:31:14.730123 14, 0x0, sum = 3
2677 09:31:14.730644 15, 0x0, sum = 4
2678 09:31:14.730978 best_step = 13
2679 09:31:14.733645
2680 09:31:14.734124 ==
2681 09:31:14.736671 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 09:31:14.740197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 09:31:14.740711 ==
2684 09:31:14.741039 RX Vref Scan: 1
2685 09:31:14.741347
2686 09:31:14.743499 Set Vref Range= 32 -> 127
2687 09:31:14.743910
2688 09:31:14.746593 RX Vref 32 -> 127, step: 1
2689 09:31:14.747001
2690 09:31:14.750301 RX Delay -37 -> 252, step: 4
2691 09:31:14.750814
2692 09:31:14.753547 Set Vref, RX VrefLevel [Byte0]: 32
2693 09:31:14.756753 [Byte1]: 32
2694 09:31:14.757167
2695 09:31:14.759791 Set Vref, RX VrefLevel [Byte0]: 33
2696 09:31:14.763496 [Byte1]: 33
2697 09:31:14.766397
2698 09:31:14.766808 Set Vref, RX VrefLevel [Byte0]: 34
2699 09:31:14.769997 [Byte1]: 34
2700 09:31:14.774315
2701 09:31:14.774733 Set Vref, RX VrefLevel [Byte0]: 35
2702 09:31:14.777839 [Byte1]: 35
2703 09:31:14.782509
2704 09:31:14.782967 Set Vref, RX VrefLevel [Byte0]: 36
2705 09:31:14.785975 [Byte1]: 36
2706 09:31:14.790577
2707 09:31:14.790991 Set Vref, RX VrefLevel [Byte0]: 37
2708 09:31:14.793896 [Byte1]: 37
2709 09:31:14.798807
2710 09:31:14.799442 Set Vref, RX VrefLevel [Byte0]: 38
2711 09:31:14.802550 [Byte1]: 38
2712 09:31:14.806864
2713 09:31:14.807280 Set Vref, RX VrefLevel [Byte0]: 39
2714 09:31:14.809881 [Byte1]: 39
2715 09:31:14.814895
2716 09:31:14.815308 Set Vref, RX VrefLevel [Byte0]: 40
2717 09:31:14.817818 [Byte1]: 40
2718 09:31:14.822525
2719 09:31:14.822940 Set Vref, RX VrefLevel [Byte0]: 41
2720 09:31:14.825997 [Byte1]: 41
2721 09:31:14.830486
2722 09:31:14.830902 Set Vref, RX VrefLevel [Byte0]: 42
2723 09:31:14.834025 [Byte1]: 42
2724 09:31:14.838804
2725 09:31:14.839468 Set Vref, RX VrefLevel [Byte0]: 43
2726 09:31:14.841745 [Byte1]: 43
2727 09:31:14.846510
2728 09:31:14.847302 Set Vref, RX VrefLevel [Byte0]: 44
2729 09:31:14.849877 [Byte1]: 44
2730 09:31:14.854208
2731 09:31:14.854720 Set Vref, RX VrefLevel [Byte0]: 45
2732 09:31:14.858173 [Byte1]: 45
2733 09:31:14.862332
2734 09:31:14.862824 Set Vref, RX VrefLevel [Byte0]: 46
2735 09:31:14.865824 [Byte1]: 46
2736 09:31:14.870268
2737 09:31:14.870785 Set Vref, RX VrefLevel [Byte0]: 47
2738 09:31:14.873799 [Byte1]: 47
2739 09:31:14.878787
2740 09:31:14.879205 Set Vref, RX VrefLevel [Byte0]: 48
2741 09:31:14.881864 [Byte1]: 48
2742 09:31:14.886803
2743 09:31:14.887216 Set Vref, RX VrefLevel [Byte0]: 49
2744 09:31:14.889976 [Byte1]: 49
2745 09:31:14.894546
2746 09:31:14.894961 Set Vref, RX VrefLevel [Byte0]: 50
2747 09:31:14.898129 [Byte1]: 50
2748 09:31:14.902675
2749 09:31:14.903130 Set Vref, RX VrefLevel [Byte0]: 51
2750 09:31:14.905724 [Byte1]: 51
2751 09:31:14.910494
2752 09:31:14.910908 Set Vref, RX VrefLevel [Byte0]: 52
2753 09:31:14.914003 [Byte1]: 52
2754 09:31:14.918478
2755 09:31:14.918909 Set Vref, RX VrefLevel [Byte0]: 53
2756 09:31:14.922086 [Byte1]: 53
2757 09:31:14.926700
2758 09:31:14.927302 Set Vref, RX VrefLevel [Byte0]: 54
2759 09:31:14.930093 [Byte1]: 54
2760 09:31:14.934534
2761 09:31:14.934950 Set Vref, RX VrefLevel [Byte0]: 55
2762 09:31:14.937776 [Byte1]: 55
2763 09:31:14.942733
2764 09:31:14.943253 Set Vref, RX VrefLevel [Byte0]: 56
2765 09:31:14.946231 [Byte1]: 56
2766 09:31:14.950930
2767 09:31:14.951494 Set Vref, RX VrefLevel [Byte0]: 57
2768 09:31:14.954527 [Byte1]: 57
2769 09:31:14.958618
2770 09:31:14.959133 Set Vref, RX VrefLevel [Byte0]: 58
2771 09:31:14.962355 [Byte1]: 58
2772 09:31:14.967067
2773 09:31:14.967631 Set Vref, RX VrefLevel [Byte0]: 59
2774 09:31:14.970569 [Byte1]: 59
2775 09:31:14.975116
2776 09:31:14.975678 Set Vref, RX VrefLevel [Byte0]: 60
2777 09:31:14.977732 [Byte1]: 60
2778 09:31:14.982761
2779 09:31:14.983287 Set Vref, RX VrefLevel [Byte0]: 61
2780 09:31:14.986065 [Byte1]: 61
2781 09:31:14.990566
2782 09:31:14.990985 Set Vref, RX VrefLevel [Byte0]: 62
2783 09:31:14.994048 [Byte1]: 62
2784 09:31:14.999163
2785 09:31:14.999774 Set Vref, RX VrefLevel [Byte0]: 63
2786 09:31:15.002346 [Byte1]: 63
2787 09:31:15.006865
2788 09:31:15.007434 Set Vref, RX VrefLevel [Byte0]: 64
2789 09:31:15.010267 [Byte1]: 64
2790 09:31:15.014761
2791 09:31:15.015286 Set Vref, RX VrefLevel [Byte0]: 65
2792 09:31:15.017948 [Byte1]: 65
2793 09:31:15.022773
2794 09:31:15.023297 Set Vref, RX VrefLevel [Byte0]: 66
2795 09:31:15.025829 [Byte1]: 66
2796 09:31:15.031078
2797 09:31:15.031539 Set Vref, RX VrefLevel [Byte0]: 67
2798 09:31:15.034221 [Byte1]: 67
2799 09:31:15.039089
2800 09:31:15.039575 Set Vref, RX VrefLevel [Byte0]: 68
2801 09:31:15.042007 [Byte1]: 68
2802 09:31:15.047061
2803 09:31:15.047526 Set Vref, RX VrefLevel [Byte0]: 69
2804 09:31:15.049837 [Byte1]: 69
2805 09:31:15.054742
2806 09:31:15.055158 Set Vref, RX VrefLevel [Byte0]: 70
2807 09:31:15.057913 [Byte1]: 70
2808 09:31:15.062754
2809 09:31:15.063169 Set Vref, RX VrefLevel [Byte0]: 71
2810 09:31:15.066556 [Byte1]: 71
2811 09:31:15.070720
2812 09:31:15.071140 Set Vref, RX VrefLevel [Byte0]: 72
2813 09:31:15.074565 [Byte1]: 72
2814 09:31:15.078836
2815 09:31:15.079256 Set Vref, RX VrefLevel [Byte0]: 73
2816 09:31:15.082093 [Byte1]: 73
2817 09:31:15.086413
2818 09:31:15.086837 Set Vref, RX VrefLevel [Byte0]: 74
2819 09:31:15.090146 [Byte1]: 74
2820 09:31:15.095316
2821 09:31:15.095873 Final RX Vref Byte 0 = 61 to rank0
2822 09:31:15.098217 Final RX Vref Byte 1 = 53 to rank0
2823 09:31:15.101621 Final RX Vref Byte 0 = 61 to rank1
2824 09:31:15.104568 Final RX Vref Byte 1 = 53 to rank1==
2825 09:31:15.108362 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 09:31:15.114953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 09:31:15.115510 ==
2828 09:31:15.115859 DQS Delay:
2829 09:31:15.116210 DQS0 = 0, DQS1 = 0
2830 09:31:15.117984 DQM Delay:
2831 09:31:15.118403 DQM0 = 111, DQM1 = 101
2832 09:31:15.121375 DQ Delay:
2833 09:31:15.124915 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2834 09:31:15.127756 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2835 09:31:15.131563 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2836 09:31:15.134864 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2837 09:31:15.135436
2838 09:31:15.135787
2839 09:31:15.141033 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2840 09:31:15.144853 CH0 RK0: MR19=303, MR18=FDFD
2841 09:31:15.151264 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2842 09:31:15.151815
2843 09:31:15.154765 ----->DramcWriteLeveling(PI) begin...
2844 09:31:15.155280 ==
2845 09:31:15.158390 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 09:31:15.161072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 09:31:15.164842 ==
2848 09:31:15.165358 Write leveling (Byte 0): 31 => 31
2849 09:31:15.167973 Write leveling (Byte 1): 31 => 31
2850 09:31:15.171361 DramcWriteLeveling(PI) end<-----
2851 09:31:15.171929
2852 09:31:15.172271 ==
2853 09:31:15.174958 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 09:31:15.181136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 09:31:15.181648 ==
2856 09:31:15.181982 [Gating] SW mode calibration
2857 09:31:15.191349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 09:31:15.194958 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 09:31:15.198373 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2860 09:31:15.204801 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 09:31:15.207869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 09:31:15.211040 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 09:31:15.218182 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 09:31:15.221390 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 09:31:15.224333 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2866 09:31:15.231507 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2867 09:31:15.234826 1 0 0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
2868 09:31:15.238092 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 09:31:15.244354 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 09:31:15.247882 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 09:31:15.251639 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 09:31:15.257747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 09:31:15.260967 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2874 09:31:15.264750 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2875 09:31:15.271110 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2876 09:31:15.274589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 09:31:15.278028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 09:31:15.281150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 09:31:15.287751 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 09:31:15.291257 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 09:31:15.294390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 09:31:15.301504 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2883 09:31:15.305226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 09:31:15.308024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 09:31:15.314823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 09:31:15.318275 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 09:31:15.321635 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 09:31:15.328017 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 09:31:15.331620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 09:31:15.334514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 09:31:15.341199 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 09:31:15.345063 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 09:31:15.348256 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 09:31:15.354696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 09:31:15.358214 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 09:31:15.361387 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 09:31:15.367946 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 09:31:15.371426 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 09:31:15.375207 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 09:31:15.377830 Total UI for P1: 0, mck2ui 16
2901 09:31:15.381192 best dqsien dly found for B0: ( 1, 3, 26)
2902 09:31:15.384666 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 09:31:15.388239 Total UI for P1: 0, mck2ui 16
2904 09:31:15.391616 best dqsien dly found for B1: ( 1, 4, 0)
2905 09:31:15.394857 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 09:31:15.398394 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2907 09:31:15.398932
2908 09:31:15.404797 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 09:31:15.408541 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2910 09:31:15.409097 [Gating] SW calibration Done
2911 09:31:15.411821 ==
2912 09:31:15.414594 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 09:31:15.418125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 09:31:15.418566 ==
2915 09:31:15.419015 RX Vref Scan: 0
2916 09:31:15.419472
2917 09:31:15.421672 RX Vref 0 -> 0, step: 1
2918 09:31:15.422228
2919 09:31:15.424771 RX Delay -40 -> 252, step: 8
2920 09:31:15.427901 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2921 09:31:15.431257 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2922 09:31:15.437912 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 09:31:15.441662 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2924 09:31:15.444788 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 09:31:15.448208 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2926 09:31:15.451446 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2927 09:31:15.454797 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 09:31:15.461151 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2929 09:31:15.465267 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2930 09:31:15.468320 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 09:31:15.471764 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2932 09:31:15.474554 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 09:31:15.481255 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2934 09:31:15.484638 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2935 09:31:15.488154 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 09:31:15.488586 ==
2937 09:31:15.491238 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 09:31:15.494746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 09:31:15.495179 ==
2940 09:31:15.498177 DQS Delay:
2941 09:31:15.498614 DQS0 = 0, DQS1 = 0
2942 09:31:15.501440 DQM Delay:
2943 09:31:15.501876 DQM0 = 111, DQM1 = 102
2944 09:31:15.502325 DQ Delay:
2945 09:31:15.504286 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2946 09:31:15.511336 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2947 09:31:15.514500 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2948 09:31:15.518002 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2949 09:31:15.518419
2950 09:31:15.518752
2951 09:31:15.519058 ==
2952 09:31:15.520990 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 09:31:15.524425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 09:31:15.524846 ==
2955 09:31:15.525178
2956 09:31:15.525488
2957 09:31:15.527680 TX Vref Scan disable
2958 09:31:15.528098 == TX Byte 0 ==
2959 09:31:15.534523 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2960 09:31:15.537584 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2961 09:31:15.538006 == TX Byte 1 ==
2962 09:31:15.544488 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2963 09:31:15.547918 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2964 09:31:15.548470 ==
2965 09:31:15.551475 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 09:31:15.554646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 09:31:15.555192 ==
2968 09:31:15.567498 TX Vref=22, minBit 2, minWin=26, winSum=424
2969 09:31:15.571220 TX Vref=24, minBit 8, minWin=26, winSum=429
2970 09:31:15.574131 TX Vref=26, minBit 5, minWin=26, winSum=435
2971 09:31:15.577537 TX Vref=28, minBit 1, minWin=27, winSum=441
2972 09:31:15.580863 TX Vref=30, minBit 0, minWin=27, winSum=438
2973 09:31:15.587224 TX Vref=32, minBit 5, minWin=26, winSum=437
2974 09:31:15.590974 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 28
2975 09:31:15.591432
2976 09:31:15.593807 Final TX Range 1 Vref 28
2977 09:31:15.594222
2978 09:31:15.594555 ==
2979 09:31:15.597360 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 09:31:15.600984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 09:31:15.601499 ==
2982 09:31:15.604006
2983 09:31:15.604417
2984 09:31:15.604746 TX Vref Scan disable
2985 09:31:15.607726 == TX Byte 0 ==
2986 09:31:15.610477 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2987 09:31:15.614153 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2988 09:31:15.617428 == TX Byte 1 ==
2989 09:31:15.620612 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2990 09:31:15.623896 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2991 09:31:15.624316
2992 09:31:15.627532 [DATLAT]
2993 09:31:15.628036 Freq=1200, CH0 RK1
2994 09:31:15.628375
2995 09:31:15.630833 DATLAT Default: 0xd
2996 09:31:15.631338 0, 0xFFFF, sum = 0
2997 09:31:15.634010 1, 0xFFFF, sum = 0
2998 09:31:15.634434 2, 0xFFFF, sum = 0
2999 09:31:15.637316 3, 0xFFFF, sum = 0
3000 09:31:15.637862 4, 0xFFFF, sum = 0
3001 09:31:15.640598 5, 0xFFFF, sum = 0
3002 09:31:15.641018 6, 0xFFFF, sum = 0
3003 09:31:15.644088 7, 0xFFFF, sum = 0
3004 09:31:15.646794 8, 0xFFFF, sum = 0
3005 09:31:15.647423 9, 0xFFFF, sum = 0
3006 09:31:15.650244 10, 0xFFFF, sum = 0
3007 09:31:15.650720 11, 0xFFFF, sum = 0
3008 09:31:15.653943 12, 0x0, sum = 1
3009 09:31:15.654381 13, 0x0, sum = 2
3010 09:31:15.657198 14, 0x0, sum = 3
3011 09:31:15.657638 15, 0x0, sum = 4
3012 09:31:15.658086 best_step = 13
3013 09:31:15.658498
3014 09:31:15.660218 ==
3015 09:31:15.663485 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 09:31:15.666787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 09:31:15.667320 ==
3018 09:31:15.667798 RX Vref Scan: 0
3019 09:31:15.668216
3020 09:31:15.670374 RX Vref 0 -> 0, step: 1
3021 09:31:15.670807
3022 09:31:15.673679 RX Delay -37 -> 252, step: 4
3023 09:31:15.677021 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3024 09:31:15.683860 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3025 09:31:15.687286 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3026 09:31:15.690798 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3027 09:31:15.693527 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3028 09:31:15.697094 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3029 09:31:15.703504 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3030 09:31:15.706713 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3031 09:31:15.710045 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3032 09:31:15.713545 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3033 09:31:15.717527 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3034 09:31:15.720774 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 09:31:15.727343 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3036 09:31:15.730882 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3037 09:31:15.733994 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3038 09:31:15.737040 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3039 09:31:15.737453 ==
3040 09:31:15.740343 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 09:31:15.747161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 09:31:15.747908 ==
3043 09:31:15.748394 DQS Delay:
3044 09:31:15.750086 DQS0 = 0, DQS1 = 0
3045 09:31:15.750577 DQM Delay:
3046 09:31:15.751024 DQM0 = 111, DQM1 = 101
3047 09:31:15.753807 DQ Delay:
3048 09:31:15.757529 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3049 09:31:15.760274 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =120
3050 09:31:15.763987 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3051 09:31:15.767553 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3052 09:31:15.768066
3053 09:31:15.768399
3054 09:31:15.777502 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3055 09:31:15.778020 CH0 RK1: MR19=403, MR18=10F8
3056 09:31:15.783491 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3057 09:31:15.786978 [RxdqsGatingPostProcess] freq 1200
3058 09:31:15.793208 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 09:31:15.796771 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 09:31:15.800120 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 09:31:15.803279 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 09:31:15.806812 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 09:31:15.807511 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 09:31:15.810084 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 09:31:15.813199 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 09:31:15.816638 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 09:31:15.819809 Pre-setting of DQS Precalculation
3068 09:31:15.826847 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 09:31:15.827279 ==
3070 09:31:15.830314 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 09:31:15.833103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 09:31:15.833528 ==
3073 09:31:15.839816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 09:31:15.843484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 09:31:15.853224 [CA 0] Center 37 (7~67) winsize 61
3076 09:31:15.856249 [CA 1] Center 37 (7~68) winsize 62
3077 09:31:15.859865 [CA 2] Center 34 (4~64) winsize 61
3078 09:31:15.863096 [CA 3] Center 33 (3~64) winsize 62
3079 09:31:15.866564 [CA 4] Center 34 (4~64) winsize 61
3080 09:31:15.869892 [CA 5] Center 33 (3~63) winsize 61
3081 09:31:15.870310
3082 09:31:15.872843 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3083 09:31:15.873261
3084 09:31:15.876288 [CATrainingPosCal] consider 1 rank data
3085 09:31:15.879753 u2DelayCellTimex100 = 270/100 ps
3086 09:31:15.883177 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3087 09:31:15.887108 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 09:31:15.893082 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 09:31:15.896981 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 09:31:15.900393 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 09:31:15.903350 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3092 09:31:15.903929
3093 09:31:15.906679 CA PerBit enable=1, Macro0, CA PI delay=33
3094 09:31:15.907204
3095 09:31:15.910076 [CBTSetCACLKResult] CA Dly = 33
3096 09:31:15.910603 CS Dly: 6 (0~37)
3097 09:31:15.910937 ==
3098 09:31:15.913814 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 09:31:15.920127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 09:31:15.920663 ==
3101 09:31:15.922892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 09:31:15.929685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3103 09:31:15.938662 [CA 0] Center 37 (7~67) winsize 61
3104 09:31:15.942420 [CA 1] Center 37 (7~68) winsize 62
3105 09:31:15.945635 [CA 2] Center 34 (4~65) winsize 62
3106 09:31:15.948707 [CA 3] Center 33 (3~64) winsize 62
3107 09:31:15.952173 [CA 4] Center 34 (4~65) winsize 62
3108 09:31:15.955535 [CA 5] Center 32 (2~63) winsize 62
3109 09:31:15.955983
3110 09:31:15.959253 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3111 09:31:15.959842
3112 09:31:15.962234 [CATrainingPosCal] consider 2 rank data
3113 09:31:15.965389 u2DelayCellTimex100 = 270/100 ps
3114 09:31:15.968725 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3115 09:31:15.972051 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3116 09:31:15.979022 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 09:31:15.982473 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3118 09:31:15.985440 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 09:31:15.988766 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3120 09:31:15.989183
3121 09:31:15.992000 CA PerBit enable=1, Macro0, CA PI delay=33
3122 09:31:15.992422
3123 09:31:15.995503 [CBTSetCACLKResult] CA Dly = 33
3124 09:31:15.995963 CS Dly: 7 (0~39)
3125 09:31:15.996298
3126 09:31:15.998828 ----->DramcWriteLeveling(PI) begin...
3127 09:31:15.999252 ==
3128 09:31:16.002248 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 09:31:16.008794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 09:31:16.009214 ==
3131 09:31:16.012209 Write leveling (Byte 0): 25 => 25
3132 09:31:16.015647 Write leveling (Byte 1): 30 => 30
3133 09:31:16.016161 DramcWriteLeveling(PI) end<-----
3134 09:31:16.018893
3135 09:31:16.019309 ==
3136 09:31:16.022398 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 09:31:16.025471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 09:31:16.025961 ==
3139 09:31:16.028699 [Gating] SW mode calibration
3140 09:31:16.035573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 09:31:16.039121 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 09:31:16.045367 0 15 0 | B1->B0 | 2c2c 2727 | 1 1 | (0 0) (1 1)
3143 09:31:16.048852 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 09:31:16.052525 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 09:31:16.059853 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 09:31:16.062679 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 09:31:16.065621 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 09:31:16.072469 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 09:31:16.075777 0 15 28 | B1->B0 | 2e2e 2f2f | 0 1 | (0 1) (1 0)
3150 09:31:16.078997 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 09:31:16.085935 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 09:31:16.089059 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 09:31:16.092400 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 09:31:16.095686 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 09:31:16.102163 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 09:31:16.105991 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3157 09:31:16.109314 1 0 28 | B1->B0 | 4040 3d3d | 0 0 | (0 0) (1 1)
3158 09:31:16.116024 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3159 09:31:16.119468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 09:31:16.122398 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 09:31:16.128801 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 09:31:16.131898 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 09:31:16.135978 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 09:31:16.142117 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 09:31:16.145864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3166 09:31:16.148814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 09:31:16.155529 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 09:31:16.159193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 09:31:16.161899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 09:31:16.169065 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 09:31:16.172405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 09:31:16.175723 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 09:31:16.182006 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 09:31:16.185412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 09:31:16.188722 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 09:31:16.195351 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 09:31:16.199746 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 09:31:16.203025 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 09:31:16.209097 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 09:31:16.212503 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 09:31:16.216106 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3182 09:31:16.219062 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3183 09:31:16.222646 Total UI for P1: 0, mck2ui 16
3184 09:31:16.225943 best dqsien dly found for B1: ( 1, 3, 28)
3185 09:31:16.232349 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 09:31:16.235896 Total UI for P1: 0, mck2ui 16
3187 09:31:16.238903 best dqsien dly found for B0: ( 1, 3, 30)
3188 09:31:16.242271 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3189 09:31:16.245792 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3190 09:31:16.246302
3191 09:31:16.248952 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 09:31:16.252517 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 09:31:16.255447 [Gating] SW calibration Done
3194 09:31:16.255960 ==
3195 09:31:16.259083 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 09:31:16.262396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 09:31:16.263042 ==
3198 09:31:16.265406 RX Vref Scan: 0
3199 09:31:16.265813
3200 09:31:16.266136 RX Vref 0 -> 0, step: 1
3201 09:31:16.266440
3202 09:31:16.268681 RX Delay -40 -> 252, step: 8
3203 09:31:16.275880 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 09:31:16.279433 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3205 09:31:16.282534 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3206 09:31:16.285346 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3207 09:31:16.288844 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 09:31:16.292273 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3209 09:31:16.298745 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3210 09:31:16.302381 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3211 09:31:16.305862 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3212 09:31:16.309431 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3213 09:31:16.312004 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3214 09:31:16.319512 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3215 09:31:16.322265 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3216 09:31:16.325377 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3217 09:31:16.328905 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 09:31:16.331926 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 09:31:16.335621 ==
3220 09:31:16.336127 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 09:31:16.342026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 09:31:16.342534 ==
3223 09:31:16.342921 DQS Delay:
3224 09:31:16.345520 DQS0 = 0, DQS1 = 0
3225 09:31:16.346033 DQM Delay:
3226 09:31:16.349043 DQM0 = 114, DQM1 = 105
3227 09:31:16.349557 DQ Delay:
3228 09:31:16.353136 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =115
3229 09:31:16.355951 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3230 09:31:16.359794 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =99
3231 09:31:16.362039 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3232 09:31:16.362453
3233 09:31:16.362874
3234 09:31:16.363254 ==
3235 09:31:16.365920 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 09:31:16.368895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 09:31:16.372050 ==
3238 09:31:16.372467
3239 09:31:16.372910
3240 09:31:16.373366 TX Vref Scan disable
3241 09:31:16.375462 == TX Byte 0 ==
3242 09:31:16.378934 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3243 09:31:16.381945 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3244 09:31:16.385303 == TX Byte 1 ==
3245 09:31:16.388787 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3246 09:31:16.392278 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3247 09:31:16.392796 ==
3248 09:31:16.395877 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 09:31:16.402373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 09:31:16.402884 ==
3251 09:31:16.413375 TX Vref=22, minBit 3, minWin=25, winSum=415
3252 09:31:16.416991 TX Vref=24, minBit 1, minWin=25, winSum=418
3253 09:31:16.420382 TX Vref=26, minBit 1, minWin=26, winSum=427
3254 09:31:16.423485 TX Vref=28, minBit 1, minWin=26, winSum=430
3255 09:31:16.426751 TX Vref=30, minBit 1, minWin=26, winSum=433
3256 09:31:16.430130 TX Vref=32, minBit 1, minWin=26, winSum=429
3257 09:31:16.437113 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3258 09:31:16.437669
3259 09:31:16.440261 Final TX Range 1 Vref 30
3260 09:31:16.440789
3261 09:31:16.441125 ==
3262 09:31:16.443836 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 09:31:16.446771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 09:31:16.447284 ==
3265 09:31:16.447700
3266 09:31:16.450164
3267 09:31:16.450673 TX Vref Scan disable
3268 09:31:16.453048 == TX Byte 0 ==
3269 09:31:16.456692 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 09:31:16.460404 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 09:31:16.463765 == TX Byte 1 ==
3272 09:31:16.466440 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3273 09:31:16.469981 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3274 09:31:16.470505
3275 09:31:16.473038 [DATLAT]
3276 09:31:16.473485 Freq=1200, CH1 RK0
3277 09:31:16.473826
3278 09:31:16.476564 DATLAT Default: 0xd
3279 09:31:16.477075 0, 0xFFFF, sum = 0
3280 09:31:16.480397 1, 0xFFFF, sum = 0
3281 09:31:16.480917 2, 0xFFFF, sum = 0
3282 09:31:16.483180 3, 0xFFFF, sum = 0
3283 09:31:16.483711 4, 0xFFFF, sum = 0
3284 09:31:16.486676 5, 0xFFFF, sum = 0
3285 09:31:16.487144 6, 0xFFFF, sum = 0
3286 09:31:16.490249 7, 0xFFFF, sum = 0
3287 09:31:16.494954 8, 0xFFFF, sum = 0
3288 09:31:16.495523 9, 0xFFFF, sum = 0
3289 09:31:16.497322 10, 0xFFFF, sum = 0
3290 09:31:16.497862 11, 0xFFFF, sum = 0
3291 09:31:16.499995 12, 0x0, sum = 1
3292 09:31:16.500420 13, 0x0, sum = 2
3293 09:31:16.502784 14, 0x0, sum = 3
3294 09:31:16.503198 15, 0x0, sum = 4
3295 09:31:16.503595 best_step = 13
3296 09:31:16.503923
3297 09:31:16.506361 ==
3298 09:31:16.506774 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 09:31:16.512974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 09:31:16.513386 ==
3301 09:31:16.513718 RX Vref Scan: 1
3302 09:31:16.514023
3303 09:31:16.516416 Set Vref Range= 32 -> 127
3304 09:31:16.516822
3305 09:31:16.519881 RX Vref 32 -> 127, step: 1
3306 09:31:16.520463
3307 09:31:16.522997 RX Delay -21 -> 252, step: 4
3308 09:31:16.523518
3309 09:31:16.526483 Set Vref, RX VrefLevel [Byte0]: 32
3310 09:31:16.529920 [Byte1]: 32
3311 09:31:16.530326
3312 09:31:16.532968 Set Vref, RX VrefLevel [Byte0]: 33
3313 09:31:16.536313 [Byte1]: 33
3314 09:31:16.536719
3315 09:31:16.539925 Set Vref, RX VrefLevel [Byte0]: 34
3316 09:31:16.542657 [Byte1]: 34
3317 09:31:16.547667
3318 09:31:16.548072 Set Vref, RX VrefLevel [Byte0]: 35
3319 09:31:16.550682 [Byte1]: 35
3320 09:31:16.555501
3321 09:31:16.556010 Set Vref, RX VrefLevel [Byte0]: 36
3322 09:31:16.558911 [Byte1]: 36
3323 09:31:16.563537
3324 09:31:16.564057 Set Vref, RX VrefLevel [Byte0]: 37
3325 09:31:16.566246 [Byte1]: 37
3326 09:31:16.570907
3327 09:31:16.571313 Set Vref, RX VrefLevel [Byte0]: 38
3328 09:31:16.574241 [Byte1]: 38
3329 09:31:16.578829
3330 09:31:16.579233 Set Vref, RX VrefLevel [Byte0]: 39
3331 09:31:16.582684 [Byte1]: 39
3332 09:31:16.587272
3333 09:31:16.587840 Set Vref, RX VrefLevel [Byte0]: 40
3334 09:31:16.590403 [Byte1]: 40
3335 09:31:16.595139
3336 09:31:16.595691 Set Vref, RX VrefLevel [Byte0]: 41
3337 09:31:16.598668 [Byte1]: 41
3338 09:31:16.603059
3339 09:31:16.603605 Set Vref, RX VrefLevel [Byte0]: 42
3340 09:31:16.606119 [Byte1]: 42
3341 09:31:16.610754
3342 09:31:16.611275 Set Vref, RX VrefLevel [Byte0]: 43
3343 09:31:16.614522 [Byte1]: 43
3344 09:31:16.618506
3345 09:31:16.618916 Set Vref, RX VrefLevel [Byte0]: 44
3346 09:31:16.621807 [Byte1]: 44
3347 09:31:16.626325
3348 09:31:16.626814 Set Vref, RX VrefLevel [Byte0]: 45
3349 09:31:16.629850 [Byte1]: 45
3350 09:31:16.634388
3351 09:31:16.634799 Set Vref, RX VrefLevel [Byte0]: 46
3352 09:31:16.637970 [Byte1]: 46
3353 09:31:16.642801
3354 09:31:16.643347 Set Vref, RX VrefLevel [Byte0]: 47
3355 09:31:16.646388 [Byte1]: 47
3356 09:31:16.650232
3357 09:31:16.650972 Set Vref, RX VrefLevel [Byte0]: 48
3358 09:31:16.653762 [Byte1]: 48
3359 09:31:16.658704
3360 09:31:16.659208 Set Vref, RX VrefLevel [Byte0]: 49
3361 09:31:16.661766 [Byte1]: 49
3362 09:31:16.666469
3363 09:31:16.666991 Set Vref, RX VrefLevel [Byte0]: 50
3364 09:31:16.669953 [Byte1]: 50
3365 09:31:16.674274
3366 09:31:16.674685 Set Vref, RX VrefLevel [Byte0]: 51
3367 09:31:16.678052 [Byte1]: 51
3368 09:31:16.682285
3369 09:31:16.682740 Set Vref, RX VrefLevel [Byte0]: 52
3370 09:31:16.685124 [Byte1]: 52
3371 09:31:16.689924
3372 09:31:16.690438 Set Vref, RX VrefLevel [Byte0]: 53
3373 09:31:16.693245 [Byte1]: 53
3374 09:31:16.698076
3375 09:31:16.698580 Set Vref, RX VrefLevel [Byte0]: 54
3376 09:31:16.701320 [Byte1]: 54
3377 09:31:16.705745
3378 09:31:16.706196 Set Vref, RX VrefLevel [Byte0]: 55
3379 09:31:16.709015 [Byte1]: 55
3380 09:31:16.713659
3381 09:31:16.714099 Set Vref, RX VrefLevel [Byte0]: 56
3382 09:31:16.717031 [Byte1]: 56
3383 09:31:16.721510
3384 09:31:16.721915 Set Vref, RX VrefLevel [Byte0]: 57
3385 09:31:16.724582 [Byte1]: 57
3386 09:31:16.729932
3387 09:31:16.730350 Set Vref, RX VrefLevel [Byte0]: 58
3388 09:31:16.733147 [Byte1]: 58
3389 09:31:16.737213
3390 09:31:16.737723 Set Vref, RX VrefLevel [Byte0]: 59
3391 09:31:16.740600 [Byte1]: 59
3392 09:31:16.745380
3393 09:31:16.745787 Set Vref, RX VrefLevel [Byte0]: 60
3394 09:31:16.748671 [Byte1]: 60
3395 09:31:16.753515
3396 09:31:16.754027 Set Vref, RX VrefLevel [Byte0]: 61
3397 09:31:16.756585 [Byte1]: 61
3398 09:31:16.761021
3399 09:31:16.761430 Set Vref, RX VrefLevel [Byte0]: 62
3400 09:31:16.764389 [Byte1]: 62
3401 09:31:16.769029
3402 09:31:16.769436 Set Vref, RX VrefLevel [Byte0]: 63
3403 09:31:16.772317 [Byte1]: 63
3404 09:31:16.777021
3405 09:31:16.777447 Set Vref, RX VrefLevel [Byte0]: 64
3406 09:31:16.780800 [Byte1]: 64
3407 09:31:16.784682
3408 09:31:16.785105 Set Vref, RX VrefLevel [Byte0]: 65
3409 09:31:16.788105 [Byte1]: 65
3410 09:31:16.792726
3411 09:31:16.793137 Final RX Vref Byte 0 = 57 to rank0
3412 09:31:16.796150 Final RX Vref Byte 1 = 50 to rank0
3413 09:31:16.799702 Final RX Vref Byte 0 = 57 to rank1
3414 09:31:16.803117 Final RX Vref Byte 1 = 50 to rank1==
3415 09:31:16.806290 Dram Type= 6, Freq= 0, CH_1, rank 0
3416 09:31:16.812529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 09:31:16.812940 ==
3418 09:31:16.813265 DQS Delay:
3419 09:31:16.813568 DQS0 = 0, DQS1 = 0
3420 09:31:16.816099 DQM Delay:
3421 09:31:16.816513 DQM0 = 114, DQM1 = 106
3422 09:31:16.819243 DQ Delay:
3423 09:31:16.822835 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3424 09:31:16.826081 DQ4 =110, DQ5 =124, DQ6 =126, DQ7 =112
3425 09:31:16.829633 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =102
3426 09:31:16.832970 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =110
3427 09:31:16.833386
3428 09:31:16.833716
3429 09:31:16.839290 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3430 09:31:16.843076 CH1 RK0: MR19=303, MR18=EFF6
3431 09:31:16.849904 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3432 09:31:16.850425
3433 09:31:16.853315 ----->DramcWriteLeveling(PI) begin...
3434 09:31:16.853843 ==
3435 09:31:16.856638 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 09:31:16.859616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 09:31:16.863067 ==
3438 09:31:16.863658 Write leveling (Byte 0): 23 => 23
3439 09:31:16.866472 Write leveling (Byte 1): 27 => 27
3440 09:31:16.869628 DramcWriteLeveling(PI) end<-----
3441 09:31:16.870148
3442 09:31:16.870482 ==
3443 09:31:16.873647 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 09:31:16.879871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 09:31:16.880411 ==
3446 09:31:16.880751 [Gating] SW mode calibration
3447 09:31:16.889227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3448 09:31:16.892662 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3449 09:31:16.896151 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 09:31:16.902845 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 09:31:16.906246 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 09:31:16.909917 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 09:31:16.916488 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 09:31:16.919893 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 09:31:16.923303 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 1)
3456 09:31:16.929601 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3457 09:31:16.932978 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 09:31:16.936347 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 09:31:16.942982 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 09:31:16.946492 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 09:31:16.949812 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 09:31:16.956596 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3463 09:31:16.959632 1 0 24 | B1->B0 | 2e2d 4646 | 1 0 | (0 0) (0 0)
3464 09:31:16.963084 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3465 09:31:16.969467 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 09:31:16.972794 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 09:31:16.976498 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 09:31:16.979440 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 09:31:16.985945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 09:31:16.989913 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3471 09:31:16.992607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3472 09:31:16.999502 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3473 09:31:17.003104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 09:31:17.006050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 09:31:17.012538 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 09:31:17.015879 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 09:31:17.018931 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 09:31:17.025780 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 09:31:17.028929 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 09:31:17.032546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 09:31:17.038862 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 09:31:17.042472 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 09:31:17.045676 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 09:31:17.052917 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 09:31:17.055938 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 09:31:17.058917 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 09:31:17.065435 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3488 09:31:17.068447 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 09:31:17.071867 Total UI for P1: 0, mck2ui 16
3490 09:31:17.075099 best dqsien dly found for B0: ( 1, 3, 24)
3491 09:31:17.079064 Total UI for P1: 0, mck2ui 16
3492 09:31:17.081936 best dqsien dly found for B1: ( 1, 3, 24)
3493 09:31:17.085297 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3494 09:31:17.088531 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3495 09:31:17.088943
3496 09:31:17.091883 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3497 09:31:17.098765 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3498 09:31:17.099266 [Gating] SW calibration Done
3499 09:31:17.099650 ==
3500 09:31:17.101468 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 09:31:17.108257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 09:31:17.108779 ==
3503 09:31:17.109113 RX Vref Scan: 0
3504 09:31:17.109450
3505 09:31:17.111745 RX Vref 0 -> 0, step: 1
3506 09:31:17.112283
3507 09:31:17.114847 RX Delay -40 -> 252, step: 8
3508 09:31:17.118531 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3509 09:31:17.121511 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3510 09:31:17.124722 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3511 09:31:17.131432 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3512 09:31:17.134607 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3513 09:31:17.137592 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3514 09:31:17.141034 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3515 09:31:17.144474 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3516 09:31:17.150944 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3517 09:31:17.154238 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3518 09:31:17.157726 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3519 09:31:17.161116 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3520 09:31:17.163993 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3521 09:31:17.170343 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3522 09:31:17.173798 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3523 09:31:17.177365 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3524 09:31:17.177775 ==
3525 09:31:17.180887 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 09:31:17.183889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 09:31:17.184304 ==
3528 09:31:17.187276 DQS Delay:
3529 09:31:17.187737 DQS0 = 0, DQS1 = 0
3530 09:31:17.190526 DQM Delay:
3531 09:31:17.190936 DQM0 = 111, DQM1 = 106
3532 09:31:17.193916 DQ Delay:
3533 09:31:17.197314 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =107
3534 09:31:17.200439 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3535 09:31:17.203996 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3536 09:31:17.207357 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3537 09:31:17.207923
3538 09:31:17.208260
3539 09:31:17.208559 ==
3540 09:31:17.210284 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 09:31:17.213811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 09:31:17.214227 ==
3543 09:31:17.214554
3544 09:31:17.214855
3545 09:31:17.216801 TX Vref Scan disable
3546 09:31:17.220564 == TX Byte 0 ==
3547 09:31:17.223348 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3548 09:31:17.226719 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3549 09:31:17.230261 == TX Byte 1 ==
3550 09:31:17.233704 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3551 09:31:17.237091 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3552 09:31:17.237507 ==
3553 09:31:17.240600 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 09:31:17.246857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 09:31:17.247273 ==
3556 09:31:17.257513 TX Vref=22, minBit 9, minWin=25, winSum=421
3557 09:31:17.260544 TX Vref=24, minBit 9, minWin=25, winSum=425
3558 09:31:17.263652 TX Vref=26, minBit 0, minWin=26, winSum=428
3559 09:31:17.267076 TX Vref=28, minBit 8, minWin=26, winSum=434
3560 09:31:17.270396 TX Vref=30, minBit 0, minWin=26, winSum=433
3561 09:31:17.277516 TX Vref=32, minBit 4, minWin=26, winSum=431
3562 09:31:17.280386 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3563 09:31:17.280820
3564 09:31:17.283909 Final TX Range 1 Vref 28
3565 09:31:17.284327
3566 09:31:17.284656 ==
3567 09:31:17.286773 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 09:31:17.290745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 09:31:17.291163 ==
3570 09:31:17.293472
3571 09:31:17.293884
3572 09:31:17.294214 TX Vref Scan disable
3573 09:31:17.296731 == TX Byte 0 ==
3574 09:31:17.300340 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3575 09:31:17.307095 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3576 09:31:17.307650 == TX Byte 1 ==
3577 09:31:17.310248 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 09:31:17.316961 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 09:31:17.317127
3580 09:31:17.317206 [DATLAT]
3581 09:31:17.317279 Freq=1200, CH1 RK1
3582 09:31:17.317348
3583 09:31:17.320404 DATLAT Default: 0xd
3584 09:31:17.320573 0, 0xFFFF, sum = 0
3585 09:31:17.323253 1, 0xFFFF, sum = 0
3586 09:31:17.326868 2, 0xFFFF, sum = 0
3587 09:31:17.327049 3, 0xFFFF, sum = 0
3588 09:31:17.330291 4, 0xFFFF, sum = 0
3589 09:31:17.330443 5, 0xFFFF, sum = 0
3590 09:31:17.333115 6, 0xFFFF, sum = 0
3591 09:31:17.333284 7, 0xFFFF, sum = 0
3592 09:31:17.336359 8, 0xFFFF, sum = 0
3593 09:31:17.336562 9, 0xFFFF, sum = 0
3594 09:31:17.340494 10, 0xFFFF, sum = 0
3595 09:31:17.340697 11, 0xFFFF, sum = 0
3596 09:31:17.343349 12, 0x0, sum = 1
3597 09:31:17.343584 13, 0x0, sum = 2
3598 09:31:17.346452 14, 0x0, sum = 3
3599 09:31:17.346661 15, 0x0, sum = 4
3600 09:31:17.350007 best_step = 13
3601 09:31:17.350242
3602 09:31:17.350374 ==
3603 09:31:17.353494 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 09:31:17.356194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 09:31:17.356414 ==
3606 09:31:17.356563 RX Vref Scan: 0
3607 09:31:17.359569
3608 09:31:17.359786 RX Vref 0 -> 0, step: 1
3609 09:31:17.359946
3610 09:31:17.363290 RX Delay -21 -> 252, step: 4
3611 09:31:17.370174 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3612 09:31:17.372982 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3613 09:31:17.376838 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3614 09:31:17.379713 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3615 09:31:17.383463 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3616 09:31:17.386747 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3617 09:31:17.393093 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3618 09:31:17.396563 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3619 09:31:17.399897 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3620 09:31:17.403157 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3621 09:31:17.406484 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3622 09:31:17.412858 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3623 09:31:17.416124 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3624 09:31:17.419352 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3625 09:31:17.422868 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3626 09:31:17.429681 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3627 09:31:17.430101 ==
3628 09:31:17.432725 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 09:31:17.436102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 09:31:17.436518 ==
3631 09:31:17.436848 DQS Delay:
3632 09:31:17.439468 DQS0 = 0, DQS1 = 0
3633 09:31:17.439886 DQM Delay:
3634 09:31:17.442915 DQM0 = 111, DQM1 = 109
3635 09:31:17.443350 DQ Delay:
3636 09:31:17.445960 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3637 09:31:17.449735 DQ4 =106, DQ5 =122, DQ6 =122, DQ7 =108
3638 09:31:17.452460 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3639 09:31:17.455792 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3640 09:31:17.456214
3641 09:31:17.456599
3642 09:31:17.465934 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3643 09:31:17.468854 CH1 RK1: MR19=304, MR18=F808
3644 09:31:17.475743 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3645 09:31:17.475942 [RxdqsGatingPostProcess] freq 1200
3646 09:31:17.482556 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3647 09:31:17.485330 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 09:31:17.488590 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 09:31:17.492086 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 09:31:17.495448 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 09:31:17.498511 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 09:31:17.501779 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 09:31:17.505458 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 09:31:17.508450 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 09:31:17.512241 Pre-setting of DQS Precalculation
3656 09:31:17.515727 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3657 09:31:17.521880 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3658 09:31:17.528822 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3659 09:31:17.531895
3660 09:31:17.531983
3661 09:31:17.532048 [Calibration Summary] 2400 Mbps
3662 09:31:17.535330 CH 0, Rank 0
3663 09:31:17.535436 SW Impedance : PASS
3664 09:31:17.538765 DUTY Scan : NO K
3665 09:31:17.541633 ZQ Calibration : PASS
3666 09:31:17.541719 Jitter Meter : NO K
3667 09:31:17.545300 CBT Training : PASS
3668 09:31:17.548600 Write leveling : PASS
3669 09:31:17.548691 RX DQS gating : PASS
3670 09:31:17.551771 RX DQ/DQS(RDDQC) : PASS
3671 09:31:17.555120 TX DQ/DQS : PASS
3672 09:31:17.555204 RX DATLAT : PASS
3673 09:31:17.558399 RX DQ/DQS(Engine): PASS
3674 09:31:17.561771 TX OE : NO K
3675 09:31:17.561856 All Pass.
3676 09:31:17.561922
3677 09:31:17.561982 CH 0, Rank 1
3678 09:31:17.565292 SW Impedance : PASS
3679 09:31:17.568612 DUTY Scan : NO K
3680 09:31:17.568697 ZQ Calibration : PASS
3681 09:31:17.571668 Jitter Meter : NO K
3682 09:31:17.574990 CBT Training : PASS
3683 09:31:17.575077 Write leveling : PASS
3684 09:31:17.578510 RX DQS gating : PASS
3685 09:31:17.581442 RX DQ/DQS(RDDQC) : PASS
3686 09:31:17.581528 TX DQ/DQS : PASS
3687 09:31:17.584890 RX DATLAT : PASS
3688 09:31:17.584972 RX DQ/DQS(Engine): PASS
3689 09:31:17.588353 TX OE : NO K
3690 09:31:17.588436 All Pass.
3691 09:31:17.588502
3692 09:31:17.591887 CH 1, Rank 0
3693 09:31:17.591971 SW Impedance : PASS
3694 09:31:17.594712 DUTY Scan : NO K
3695 09:31:17.598455 ZQ Calibration : PASS
3696 09:31:17.598542 Jitter Meter : NO K
3697 09:31:17.601721 CBT Training : PASS
3698 09:31:17.604626 Write leveling : PASS
3699 09:31:17.604709 RX DQS gating : PASS
3700 09:31:17.608194 RX DQ/DQS(RDDQC) : PASS
3701 09:31:17.611700 TX DQ/DQS : PASS
3702 09:31:17.611803 RX DATLAT : PASS
3703 09:31:17.614853 RX DQ/DQS(Engine): PASS
3704 09:31:17.618227 TX OE : NO K
3705 09:31:17.618325 All Pass.
3706 09:31:17.618392
3707 09:31:17.618453 CH 1, Rank 1
3708 09:31:17.621587 SW Impedance : PASS
3709 09:31:17.625136 DUTY Scan : NO K
3710 09:31:17.625223 ZQ Calibration : PASS
3711 09:31:17.628185 Jitter Meter : NO K
3712 09:31:17.631245 CBT Training : PASS
3713 09:31:17.631358 Write leveling : PASS
3714 09:31:17.634762 RX DQS gating : PASS
3715 09:31:17.634845 RX DQ/DQS(RDDQC) : PASS
3716 09:31:17.638493 TX DQ/DQS : PASS
3717 09:31:17.641642 RX DATLAT : PASS
3718 09:31:17.641726 RX DQ/DQS(Engine): PASS
3719 09:31:17.644942 TX OE : NO K
3720 09:31:17.645024 All Pass.
3721 09:31:17.645089
3722 09:31:17.648300 DramC Write-DBI off
3723 09:31:17.651426 PER_BANK_REFRESH: Hybrid Mode
3724 09:31:17.651517 TX_TRACKING: ON
3725 09:31:17.661436 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3726 09:31:17.664776 [FAST_K] Save calibration result to emmc
3727 09:31:17.668152 dramc_set_vcore_voltage set vcore to 650000
3728 09:31:17.671380 Read voltage for 600, 5
3729 09:31:17.671473 Vio18 = 0
3730 09:31:17.671558 Vcore = 650000
3731 09:31:17.674812 Vdram = 0
3732 09:31:17.674899 Vddq = 0
3733 09:31:17.674985 Vmddr = 0
3734 09:31:17.681426 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3735 09:31:17.684743 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3736 09:31:17.687999 MEM_TYPE=3, freq_sel=19
3737 09:31:17.691600 sv_algorithm_assistance_LP4_1600
3738 09:31:17.694967 ============ PULL DRAM RESETB DOWN ============
3739 09:31:17.697967 ========== PULL DRAM RESETB DOWN end =========
3740 09:31:17.704803 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3741 09:31:17.708374 ===================================
3742 09:31:17.711881 LPDDR4 DRAM CONFIGURATION
3743 09:31:17.714776 ===================================
3744 09:31:17.715186 EX_ROW_EN[0] = 0x0
3745 09:31:17.718712 EX_ROW_EN[1] = 0x0
3746 09:31:17.719121 LP4Y_EN = 0x0
3747 09:31:17.721438 WORK_FSP = 0x0
3748 09:31:17.721849 WL = 0x2
3749 09:31:17.724727 RL = 0x2
3750 09:31:17.725136 BL = 0x2
3751 09:31:17.728504 RPST = 0x0
3752 09:31:17.728914 RD_PRE = 0x0
3753 09:31:17.731875 WR_PRE = 0x1
3754 09:31:17.732286 WR_PST = 0x0
3755 09:31:17.735352 DBI_WR = 0x0
3756 09:31:17.735806 DBI_RD = 0x0
3757 09:31:17.738141 OTF = 0x1
3758 09:31:17.741484 ===================================
3759 09:31:17.744332 ===================================
3760 09:31:17.744417 ANA top config
3761 09:31:17.747851 ===================================
3762 09:31:17.751245 DLL_ASYNC_EN = 0
3763 09:31:17.754555 ALL_SLAVE_EN = 1
3764 09:31:17.757889 NEW_RANK_MODE = 1
3765 09:31:17.757972 DLL_IDLE_MODE = 1
3766 09:31:17.761338 LP45_APHY_COMB_EN = 1
3767 09:31:17.764698 TX_ODT_DIS = 1
3768 09:31:17.767804 NEW_8X_MODE = 1
3769 09:31:17.771143 ===================================
3770 09:31:17.774555 ===================================
3771 09:31:17.778049 data_rate = 1200
3772 09:31:17.778135 CKR = 1
3773 09:31:17.780983 DQ_P2S_RATIO = 8
3774 09:31:17.784215 ===================================
3775 09:31:17.787496 CA_P2S_RATIO = 8
3776 09:31:17.791228 DQ_CA_OPEN = 0
3777 09:31:17.794465 DQ_SEMI_OPEN = 0
3778 09:31:17.797772 CA_SEMI_OPEN = 0
3779 09:31:17.800766 CA_FULL_RATE = 0
3780 09:31:17.800849 DQ_CKDIV4_EN = 1
3781 09:31:17.804229 CA_CKDIV4_EN = 1
3782 09:31:17.807306 CA_PREDIV_EN = 0
3783 09:31:17.810552 PH8_DLY = 0
3784 09:31:17.814676 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3785 09:31:17.817227 DQ_AAMCK_DIV = 4
3786 09:31:17.817313 CA_AAMCK_DIV = 4
3787 09:31:17.821010 CA_ADMCK_DIV = 4
3788 09:31:17.824276 DQ_TRACK_CA_EN = 0
3789 09:31:17.827058 CA_PICK = 600
3790 09:31:17.830463 CA_MCKIO = 600
3791 09:31:17.834065 MCKIO_SEMI = 0
3792 09:31:17.837344 PLL_FREQ = 2288
3793 09:31:17.837435 DQ_UI_PI_RATIO = 32
3794 09:31:17.840369 CA_UI_PI_RATIO = 0
3795 09:31:17.843803 ===================================
3796 09:31:17.846711 ===================================
3797 09:31:17.850018 memory_type:LPDDR4
3798 09:31:17.853866 GP_NUM : 10
3799 09:31:17.853956 SRAM_EN : 1
3800 09:31:17.856639 MD32_EN : 0
3801 09:31:17.860308 ===================================
3802 09:31:17.863755 [ANA_INIT] >>>>>>>>>>>>>>
3803 09:31:17.863848 <<<<<< [CONFIGURE PHASE]: ANA_TX
3804 09:31:17.867142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3805 09:31:17.870128 ===================================
3806 09:31:17.873336 data_rate = 1200,PCW = 0X5800
3807 09:31:17.876537 ===================================
3808 09:31:17.879937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3809 09:31:17.886835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 09:31:17.893133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 09:31:17.896565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3812 09:31:17.899960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3813 09:31:17.902910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3814 09:31:17.906210 [ANA_INIT] flow start
3815 09:31:17.906293 [ANA_INIT] PLL >>>>>>>>
3816 09:31:17.909766 [ANA_INIT] PLL <<<<<<<<
3817 09:31:17.913288 [ANA_INIT] MIDPI >>>>>>>>
3818 09:31:17.916308 [ANA_INIT] MIDPI <<<<<<<<
3819 09:31:17.916408 [ANA_INIT] DLL >>>>>>>>
3820 09:31:17.919812 [ANA_INIT] flow end
3821 09:31:17.922993 ============ LP4 DIFF to SE enter ============
3822 09:31:17.926045 ============ LP4 DIFF to SE exit ============
3823 09:31:17.929572 [ANA_INIT] <<<<<<<<<<<<<
3824 09:31:17.933056 [Flow] Enable top DCM control >>>>>
3825 09:31:17.936418 [Flow] Enable top DCM control <<<<<
3826 09:31:17.939608 Enable DLL master slave shuffle
3827 09:31:17.946193 ==============================================================
3828 09:31:17.946276 Gating Mode config
3829 09:31:17.952833 ==============================================================
3830 09:31:17.952922 Config description:
3831 09:31:17.962760 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3832 09:31:17.969374 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3833 09:31:17.976223 SELPH_MODE 0: By rank 1: By Phase
3834 09:31:17.979491 ==============================================================
3835 09:31:17.982814 GAT_TRACK_EN = 1
3836 09:31:17.986188 RX_GATING_MODE = 2
3837 09:31:17.989663 RX_GATING_TRACK_MODE = 2
3838 09:31:17.992768 SELPH_MODE = 1
3839 09:31:17.996374 PICG_EARLY_EN = 1
3840 09:31:17.999190 VALID_LAT_VALUE = 1
3841 09:31:18.005989 ==============================================================
3842 09:31:18.008853 Enter into Gating configuration >>>>
3843 09:31:18.012197 Exit from Gating configuration <<<<
3844 09:31:18.012290 Enter into DVFS_PRE_config >>>>>
3845 09:31:18.026113 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3846 09:31:18.028895 Exit from DVFS_PRE_config <<<<<
3847 09:31:18.032350 Enter into PICG configuration >>>>
3848 09:31:18.035653 Exit from PICG configuration <<<<
3849 09:31:18.039089 [RX_INPUT] configuration >>>>>
3850 09:31:18.039298 [RX_INPUT] configuration <<<<<
3851 09:31:18.045299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3852 09:31:18.052476 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3853 09:31:18.056052 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 09:31:18.062007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 09:31:18.069302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 09:31:18.075101 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 09:31:18.078363 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3858 09:31:18.081936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3859 09:31:18.088530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3860 09:31:18.091874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3861 09:31:18.095235 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3862 09:31:18.102097 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3863 09:31:18.104977 ===================================
3864 09:31:18.105392 LPDDR4 DRAM CONFIGURATION
3865 09:31:18.108534 ===================================
3866 09:31:18.111790 EX_ROW_EN[0] = 0x0
3867 09:31:18.115293 EX_ROW_EN[1] = 0x0
3868 09:31:18.115768 LP4Y_EN = 0x0
3869 09:31:18.118185 WORK_FSP = 0x0
3870 09:31:18.118591 WL = 0x2
3871 09:31:18.121415 RL = 0x2
3872 09:31:18.121830 BL = 0x2
3873 09:31:18.125180 RPST = 0x0
3874 09:31:18.125597 RD_PRE = 0x0
3875 09:31:18.128177 WR_PRE = 0x1
3876 09:31:18.128588 WR_PST = 0x0
3877 09:31:18.131425 DBI_WR = 0x0
3878 09:31:18.131844 DBI_RD = 0x0
3879 09:31:18.134943 OTF = 0x1
3880 09:31:18.137930 ===================================
3881 09:31:18.141411 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3882 09:31:18.144651 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3883 09:31:18.151278 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 09:31:18.154590 ===================================
3885 09:31:18.154769 LPDDR4 DRAM CONFIGURATION
3886 09:31:18.157704 ===================================
3887 09:31:18.161052 EX_ROW_EN[0] = 0x10
3888 09:31:18.161203 EX_ROW_EN[1] = 0x0
3889 09:31:18.164353 LP4Y_EN = 0x0
3890 09:31:18.167531 WORK_FSP = 0x0
3891 09:31:18.167661 WL = 0x2
3892 09:31:18.171147 RL = 0x2
3893 09:31:18.171259 BL = 0x2
3894 09:31:18.174571 RPST = 0x0
3895 09:31:18.174671 RD_PRE = 0x0
3896 09:31:18.177408 WR_PRE = 0x1
3897 09:31:18.177509 WR_PST = 0x0
3898 09:31:18.180949 DBI_WR = 0x0
3899 09:31:18.181039 DBI_RD = 0x0
3900 09:31:18.184441 OTF = 0x1
3901 09:31:18.187796 ===================================
3902 09:31:18.194251 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3903 09:31:18.197299 nWR fixed to 30
3904 09:31:18.197390 [ModeRegInit_LP4] CH0 RK0
3905 09:31:18.200688 [ModeRegInit_LP4] CH0 RK1
3906 09:31:18.203869 [ModeRegInit_LP4] CH1 RK0
3907 09:31:18.203964 [ModeRegInit_LP4] CH1 RK1
3908 09:31:18.207228 match AC timing 17
3909 09:31:18.210856 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3910 09:31:18.214221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3911 09:31:18.220649 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3912 09:31:18.224032 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3913 09:31:18.230720 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3914 09:31:18.230826 ==
3915 09:31:18.234118 Dram Type= 6, Freq= 0, CH_0, rank 0
3916 09:31:18.237135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3917 09:31:18.237219 ==
3918 09:31:18.243829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3919 09:31:18.250211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3920 09:31:18.253690 [CA 0] Center 37 (7~67) winsize 61
3921 09:31:18.256983 [CA 1] Center 36 (6~67) winsize 62
3922 09:31:18.260523 [CA 2] Center 35 (5~65) winsize 61
3923 09:31:18.263942 [CA 3] Center 35 (5~65) winsize 61
3924 09:31:18.267077 [CA 4] Center 34 (4~64) winsize 61
3925 09:31:18.269972 [CA 5] Center 33 (3~64) winsize 62
3926 09:31:18.270056
3927 09:31:18.273971 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3928 09:31:18.274058
3929 09:31:18.276844 [CATrainingPosCal] consider 1 rank data
3930 09:31:18.280221 u2DelayCellTimex100 = 270/100 ps
3931 09:31:18.283538 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3932 09:31:18.286760 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 09:31:18.290245 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3934 09:31:18.293207 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3935 09:31:18.296697 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3936 09:31:18.300063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3937 09:31:18.300160
3938 09:31:18.306530 CA PerBit enable=1, Macro0, CA PI delay=33
3939 09:31:18.306645
3940 09:31:18.309614 [CBTSetCACLKResult] CA Dly = 33
3941 09:31:18.309701 CS Dly: 6 (0~37)
3942 09:31:18.309768 ==
3943 09:31:18.313665 Dram Type= 6, Freq= 0, CH_0, rank 1
3944 09:31:18.316890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3945 09:31:18.316976 ==
3946 09:31:18.323028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3947 09:31:18.329613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3948 09:31:18.332823 [CA 0] Center 37 (7~67) winsize 61
3949 09:31:18.336147 [CA 1] Center 36 (6~67) winsize 62
3950 09:31:18.339708 [CA 2] Center 35 (5~65) winsize 61
3951 09:31:18.342665 [CA 3] Center 35 (5~65) winsize 61
3952 09:31:18.346556 [CA 4] Center 34 (4~65) winsize 62
3953 09:31:18.349536 [CA 5] Center 34 (3~65) winsize 63
3954 09:31:18.349616
3955 09:31:18.353064 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3956 09:31:18.353144
3957 09:31:18.356701 [CATrainingPosCal] consider 2 rank data
3958 09:31:18.359769 u2DelayCellTimex100 = 270/100 ps
3959 09:31:18.362732 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3960 09:31:18.366259 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3961 09:31:18.369490 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3962 09:31:18.372871 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3963 09:31:18.379146 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3964 09:31:18.382730 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 09:31:18.382812
3966 09:31:18.385941 CA PerBit enable=1, Macro0, CA PI delay=33
3967 09:31:18.386022
3968 09:31:18.389330 [CBTSetCACLKResult] CA Dly = 33
3969 09:31:18.389410 CS Dly: 6 (0~38)
3970 09:31:18.389474
3971 09:31:18.392662 ----->DramcWriteLeveling(PI) begin...
3972 09:31:18.392770 ==
3973 09:31:18.396372 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 09:31:18.402812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 09:31:18.402973 ==
3976 09:31:18.406709 Write leveling (Byte 0): 33 => 33
3977 09:31:18.409317 Write leveling (Byte 1): 29 => 29
3978 09:31:18.409462 DramcWriteLeveling(PI) end<-----
3979 09:31:18.409539
3980 09:31:18.413058 ==
3981 09:31:18.415739 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 09:31:18.419401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 09:31:18.419574 ==
3984 09:31:18.422907 [Gating] SW mode calibration
3985 09:31:18.429612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3986 09:31:18.432947 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3987 09:31:18.439304 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 09:31:18.442811 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 09:31:18.445830 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 09:31:18.452521 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 09:31:18.455905 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
3992 09:31:18.459229 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3993 09:31:18.465916 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 09:31:18.469503 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 09:31:18.472410 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 09:31:18.479332 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 09:31:18.482804 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 09:31:18.486013 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3999 09:31:18.492278 0 10 16 | B1->B0 | 3535 3737 | 0 0 | (1 1) (0 0)
4000 09:31:18.496200 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 09:31:18.499416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 09:31:18.506206 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 09:31:18.509552 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 09:31:18.512796 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 09:31:18.519030 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 09:31:18.522696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 09:31:18.526244 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4008 09:31:18.532231 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 09:31:18.535905 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 09:31:18.539111 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 09:31:18.545488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 09:31:18.548866 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 09:31:18.551980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 09:31:18.555976 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 09:31:18.561912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 09:31:18.565155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 09:31:18.568544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 09:31:18.575123 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 09:31:18.578711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 09:31:18.582112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 09:31:18.588181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 09:31:18.591570 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 09:31:18.594945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4024 09:31:18.601779 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 09:31:18.604828 Total UI for P1: 0, mck2ui 16
4026 09:31:18.608529 best dqsien dly found for B0: ( 0, 13, 16)
4027 09:31:18.611378 Total UI for P1: 0, mck2ui 16
4028 09:31:18.614649 best dqsien dly found for B1: ( 0, 13, 18)
4029 09:31:18.618099 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4030 09:31:18.621592 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4031 09:31:18.622011
4032 09:31:18.625188 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4033 09:31:18.628022 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4034 09:31:18.631459 [Gating] SW calibration Done
4035 09:31:18.631892 ==
4036 09:31:18.634935 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 09:31:18.638339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 09:31:18.638872 ==
4039 09:31:18.641897 RX Vref Scan: 0
4040 09:31:18.642430
4041 09:31:18.645302 RX Vref 0 -> 0, step: 1
4042 09:31:18.645843
4043 09:31:18.646184 RX Delay -230 -> 252, step: 16
4044 09:31:18.651282 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4045 09:31:18.654712 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4046 09:31:18.658864 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4047 09:31:18.661853 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4048 09:31:18.668127 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4049 09:31:18.671493 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4050 09:31:18.674808 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4051 09:31:18.678225 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4052 09:31:18.681964 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4053 09:31:18.687758 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4054 09:31:18.691185 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4055 09:31:18.694747 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4056 09:31:18.698413 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4057 09:31:18.704274 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4058 09:31:18.707754 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4059 09:31:18.710860 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4060 09:31:18.711294 ==
4061 09:31:18.714595 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 09:31:18.720923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 09:31:18.721425 ==
4064 09:31:18.721762 DQS Delay:
4065 09:31:18.722075 DQS0 = 0, DQS1 = 0
4066 09:31:18.724267 DQM Delay:
4067 09:31:18.724687 DQM0 = 38, DQM1 = 30
4068 09:31:18.727982 DQ Delay:
4069 09:31:18.731219 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4070 09:31:18.734201 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4071 09:31:18.737608 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4072 09:31:18.741044 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4073 09:31:18.741573
4074 09:31:18.741910
4075 09:31:18.742216 ==
4076 09:31:18.744068 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 09:31:18.747593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 09:31:18.748204 ==
4079 09:31:18.748772
4080 09:31:18.749312
4081 09:31:18.750834 TX Vref Scan disable
4082 09:31:18.751456 == TX Byte 0 ==
4083 09:31:18.757116 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4084 09:31:18.760486 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4085 09:31:18.760946 == TX Byte 1 ==
4086 09:31:18.767195 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4087 09:31:18.770261 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4088 09:31:18.770546 ==
4089 09:31:18.773765 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 09:31:18.776634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 09:31:18.776819 ==
4092 09:31:18.776977
4093 09:31:18.779898
4094 09:31:18.780096 TX Vref Scan disable
4095 09:31:18.783875 == TX Byte 0 ==
4096 09:31:18.787151 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4097 09:31:18.793579 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4098 09:31:18.793737 == TX Byte 1 ==
4099 09:31:18.797070 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4100 09:31:18.803333 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4101 09:31:18.803458
4102 09:31:18.803538 [DATLAT]
4103 09:31:18.803630 Freq=600, CH0 RK0
4104 09:31:18.803701
4105 09:31:18.806784 DATLAT Default: 0x9
4106 09:31:18.806876 0, 0xFFFF, sum = 0
4107 09:31:18.810159 1, 0xFFFF, sum = 0
4108 09:31:18.813519 2, 0xFFFF, sum = 0
4109 09:31:18.813608 3, 0xFFFF, sum = 0
4110 09:31:18.816868 4, 0xFFFF, sum = 0
4111 09:31:18.816952 5, 0xFFFF, sum = 0
4112 09:31:18.820623 6, 0xFFFF, sum = 0
4113 09:31:18.820706 7, 0xFFFF, sum = 0
4114 09:31:18.823288 8, 0x0, sum = 1
4115 09:31:18.823423 9, 0x0, sum = 2
4116 09:31:18.823492 10, 0x0, sum = 3
4117 09:31:18.826556 11, 0x0, sum = 4
4118 09:31:18.826626 best_step = 9
4119 09:31:18.826685
4120 09:31:18.826741 ==
4121 09:31:18.829945 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 09:31:18.836680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 09:31:18.836773 ==
4124 09:31:18.836845 RX Vref Scan: 1
4125 09:31:18.836975
4126 09:31:18.840181 RX Vref 0 -> 0, step: 1
4127 09:31:18.840264
4128 09:31:18.843319 RX Delay -195 -> 252, step: 8
4129 09:31:18.843447
4130 09:31:18.846669 Set Vref, RX VrefLevel [Byte0]: 61
4131 09:31:18.850163 [Byte1]: 53
4132 09:31:18.850252
4133 09:31:18.853517 Final RX Vref Byte 0 = 61 to rank0
4134 09:31:18.856948 Final RX Vref Byte 1 = 53 to rank0
4135 09:31:18.859730 Final RX Vref Byte 0 = 61 to rank1
4136 09:31:18.863137 Final RX Vref Byte 1 = 53 to rank1==
4137 09:31:18.866547 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 09:31:18.869729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 09:31:18.869815 ==
4140 09:31:18.873574 DQS Delay:
4141 09:31:18.873657 DQS0 = 0, DQS1 = 0
4142 09:31:18.876802 DQM Delay:
4143 09:31:18.876885 DQM0 = 34, DQM1 = 29
4144 09:31:18.876950 DQ Delay:
4145 09:31:18.879765 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4146 09:31:18.883242 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4147 09:31:18.886507 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4148 09:31:18.889929 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4149 09:31:18.890014
4150 09:31:18.890079
4151 09:31:18.899622 [DQSOSCAuto] RK0, (LSB)MR18= 0x4242, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4152 09:31:18.902882 CH0 RK0: MR19=808, MR18=4242
4153 09:31:18.909864 CH0_RK0: MR19=0x808, MR18=0x4242, DQSOSC=397, MR23=63, INC=166, DEC=110
4154 09:31:18.909960
4155 09:31:18.913352 ----->DramcWriteLeveling(PI) begin...
4156 09:31:18.913435 ==
4157 09:31:18.916667 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 09:31:18.920051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 09:31:18.920133 ==
4160 09:31:18.922930 Write leveling (Byte 0): 35 => 35
4161 09:31:18.926282 Write leveling (Byte 1): 31 => 31
4162 09:31:18.929603 DramcWriteLeveling(PI) end<-----
4163 09:31:18.929689
4164 09:31:18.929753 ==
4165 09:31:18.933380 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 09:31:18.936620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 09:31:18.936716 ==
4168 09:31:18.939629 [Gating] SW mode calibration
4169 09:31:18.946720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4170 09:31:18.952976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4171 09:31:18.956329 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 09:31:18.959461 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 09:31:18.966214 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 09:31:18.969669 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4175 09:31:18.972898 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4176 09:31:18.979724 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 09:31:18.983047 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 09:31:18.986181 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 09:31:18.989846 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 09:31:18.996521 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 09:31:19.000044 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 09:31:19.002700 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4183 09:31:19.009706 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4184 09:31:19.012648 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 09:31:19.016033 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 09:31:19.022468 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 09:31:19.026040 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 09:31:19.029390 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 09:31:19.035714 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 09:31:19.039063 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4191 09:31:19.042463 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4192 09:31:19.048926 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 09:31:19.052502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 09:31:19.055631 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 09:31:19.062275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 09:31:19.065454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 09:31:19.068925 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 09:31:19.075683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 09:31:19.078860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 09:31:19.082267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 09:31:19.088865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 09:31:19.092227 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 09:31:19.095568 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 09:31:19.102051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 09:31:19.105542 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 09:31:19.108489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4207 09:31:19.111779 Total UI for P1: 0, mck2ui 16
4208 09:31:19.115102 best dqsien dly found for B0: ( 0, 13, 10)
4209 09:31:19.121985 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4210 09:31:19.125071 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 09:31:19.128617 Total UI for P1: 0, mck2ui 16
4212 09:31:19.131525 best dqsien dly found for B1: ( 0, 13, 16)
4213 09:31:19.135064 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4214 09:31:19.138492 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4215 09:31:19.138578
4216 09:31:19.141525 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4217 09:31:19.144812 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4218 09:31:19.148324 [Gating] SW calibration Done
4219 09:31:19.148405 ==
4220 09:31:19.151824 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 09:31:19.158552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 09:31:19.158639 ==
4223 09:31:19.158705 RX Vref Scan: 0
4224 09:31:19.158764
4225 09:31:19.161699 RX Vref 0 -> 0, step: 1
4226 09:31:19.161780
4227 09:31:19.164816 RX Delay -230 -> 252, step: 16
4228 09:31:19.168148 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4229 09:31:19.171505 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4230 09:31:19.175067 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4231 09:31:19.181376 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4232 09:31:19.184513 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4233 09:31:19.187844 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4234 09:31:19.191292 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4235 09:31:19.197808 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4236 09:31:19.201564 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4237 09:31:19.204580 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4238 09:31:19.208084 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4239 09:31:19.211100 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4240 09:31:19.217840 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4241 09:31:19.221313 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4242 09:31:19.224688 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4243 09:31:19.228225 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4244 09:31:19.231071 ==
4245 09:31:19.231156 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 09:31:19.237486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 09:31:19.237574 ==
4248 09:31:19.237659 DQS Delay:
4249 09:31:19.240843 DQS0 = 0, DQS1 = 0
4250 09:31:19.240990 DQM Delay:
4251 09:31:19.244447 DQM0 = 36, DQM1 = 30
4252 09:31:19.244548 DQ Delay:
4253 09:31:19.247725 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4254 09:31:19.251070 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4255 09:31:19.254428 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4256 09:31:19.257390 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4257 09:31:19.257473
4258 09:31:19.257539
4259 09:31:19.257598 ==
4260 09:31:19.261278 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 09:31:19.264164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 09:31:19.264251 ==
4263 09:31:19.264317
4264 09:31:19.264377
4265 09:31:19.267620 TX Vref Scan disable
4266 09:31:19.271134 == TX Byte 0 ==
4267 09:31:19.274263 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4268 09:31:19.277514 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4269 09:31:19.280920 == TX Byte 1 ==
4270 09:31:19.284259 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4271 09:31:19.287828 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4272 09:31:19.287914 ==
4273 09:31:19.291049 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 09:31:19.297406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 09:31:19.297499 ==
4276 09:31:19.297566
4277 09:31:19.297627
4278 09:31:19.297698 TX Vref Scan disable
4279 09:31:19.301704 == TX Byte 0 ==
4280 09:31:19.305141 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4281 09:31:19.311685 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4282 09:31:19.311773 == TX Byte 1 ==
4283 09:31:19.314768 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 09:31:19.321519 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 09:31:19.321606
4286 09:31:19.321671 [DATLAT]
4287 09:31:19.321732 Freq=600, CH0 RK1
4288 09:31:19.321792
4289 09:31:19.325032 DATLAT Default: 0x9
4290 09:31:19.325114 0, 0xFFFF, sum = 0
4291 09:31:19.328018 1, 0xFFFF, sum = 0
4292 09:31:19.328102 2, 0xFFFF, sum = 0
4293 09:31:19.331493 3, 0xFFFF, sum = 0
4294 09:31:19.334786 4, 0xFFFF, sum = 0
4295 09:31:19.334875 5, 0xFFFF, sum = 0
4296 09:31:19.338034 6, 0xFFFF, sum = 0
4297 09:31:19.338118 7, 0xFFFF, sum = 0
4298 09:31:19.341592 8, 0x0, sum = 1
4299 09:31:19.341675 9, 0x0, sum = 2
4300 09:31:19.341741 10, 0x0, sum = 3
4301 09:31:19.344978 11, 0x0, sum = 4
4302 09:31:19.345061 best_step = 9
4303 09:31:19.345126
4304 09:31:19.345187 ==
4305 09:31:19.348271 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 09:31:19.354386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 09:31:19.354469 ==
4308 09:31:19.354534 RX Vref Scan: 0
4309 09:31:19.354594
4310 09:31:19.357948 RX Vref 0 -> 0, step: 1
4311 09:31:19.358029
4312 09:31:19.361355 RX Delay -195 -> 252, step: 8
4313 09:31:19.367958 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4314 09:31:19.370962 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4315 09:31:19.374442 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4316 09:31:19.377619 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4317 09:31:19.381065 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4318 09:31:19.387556 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4319 09:31:19.391004 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4320 09:31:19.394642 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4321 09:31:19.397463 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4322 09:31:19.404330 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4323 09:31:19.407277 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4324 09:31:19.410714 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4325 09:31:19.414496 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4326 09:31:19.420740 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4327 09:31:19.423959 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4328 09:31:19.427278 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4329 09:31:19.427361 ==
4330 09:31:19.430621 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 09:31:19.434075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 09:31:19.434158 ==
4333 09:31:19.437346 DQS Delay:
4334 09:31:19.437427 DQS0 = 0, DQS1 = 0
4335 09:31:19.440753 DQM Delay:
4336 09:31:19.440834 DQM0 = 33, DQM1 = 27
4337 09:31:19.440899 DQ Delay:
4338 09:31:19.444130 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4339 09:31:19.447651 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4340 09:31:19.450487 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4341 09:31:19.454200 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4342 09:31:19.454283
4343 09:31:19.454348
4344 09:31:19.464146 [DQSOSCAuto] RK1, (LSB)MR18= 0x703e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
4345 09:31:19.467371 CH0 RK1: MR19=808, MR18=703E
4346 09:31:19.473683 CH0_RK1: MR19=0x808, MR18=0x703E, DQSOSC=388, MR23=63, INC=174, DEC=116
4347 09:31:19.473772 [RxdqsGatingPostProcess] freq 600
4348 09:31:19.480469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4349 09:31:19.483755 Pre-setting of DQS Precalculation
4350 09:31:19.487191 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4351 09:31:19.490471 ==
4352 09:31:19.490554 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 09:31:19.497232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 09:31:19.497321 ==
4355 09:31:19.500257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 09:31:19.506812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4357 09:31:19.510819 [CA 0] Center 35 (5~66) winsize 62
4358 09:31:19.514205 [CA 1] Center 35 (5~66) winsize 62
4359 09:31:19.517502 [CA 2] Center 34 (4~65) winsize 62
4360 09:31:19.520380 [CA 3] Center 34 (3~65) winsize 63
4361 09:31:19.523803 [CA 4] Center 34 (4~65) winsize 62
4362 09:31:19.526907 [CA 5] Center 33 (3~64) winsize 62
4363 09:31:19.526988
4364 09:31:19.530417 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4365 09:31:19.530521
4366 09:31:19.533719 [CATrainingPosCal] consider 1 rank data
4367 09:31:19.537345 u2DelayCellTimex100 = 270/100 ps
4368 09:31:19.540601 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4369 09:31:19.547274 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 09:31:19.550525 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 09:31:19.554092 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4372 09:31:19.557420 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 09:31:19.560314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 09:31:19.560470
4375 09:31:19.563984 CA PerBit enable=1, Macro0, CA PI delay=33
4376 09:31:19.564065
4377 09:31:19.567182 [CBTSetCACLKResult] CA Dly = 33
4378 09:31:19.567264 CS Dly: 4 (0~35)
4379 09:31:19.570451 ==
4380 09:31:19.573567 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 09:31:19.576791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 09:31:19.576875 ==
4383 09:31:19.583792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 09:31:19.586558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4385 09:31:19.590953 [CA 0] Center 36 (6~66) winsize 61
4386 09:31:19.593918 [CA 1] Center 36 (6~66) winsize 61
4387 09:31:19.597138 [CA 2] Center 34 (4~65) winsize 62
4388 09:31:19.601020 [CA 3] Center 34 (3~65) winsize 63
4389 09:31:19.604121 [CA 4] Center 34 (3~65) winsize 63
4390 09:31:19.607320 [CA 5] Center 34 (3~65) winsize 63
4391 09:31:19.607464
4392 09:31:19.610923 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4393 09:31:19.611006
4394 09:31:19.613888 [CATrainingPosCal] consider 2 rank data
4395 09:31:19.617335 u2DelayCellTimex100 = 270/100 ps
4396 09:31:19.620531 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4397 09:31:19.627406 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 09:31:19.630326 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 09:31:19.634134 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4400 09:31:19.637359 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 09:31:19.640606 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 09:31:19.640692
4403 09:31:19.643492 CA PerBit enable=1, Macro0, CA PI delay=33
4404 09:31:19.643574
4405 09:31:19.647214 [CBTSetCACLKResult] CA Dly = 33
4406 09:31:19.647322 CS Dly: 4 (0~36)
4407 09:31:19.650112
4408 09:31:19.653535 ----->DramcWriteLeveling(PI) begin...
4409 09:31:19.653619 ==
4410 09:31:19.656784 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 09:31:19.660342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 09:31:19.660426 ==
4413 09:31:19.663952 Write leveling (Byte 0): 28 => 28
4414 09:31:19.667135 Write leveling (Byte 1): 27 => 27
4415 09:31:19.670167 DramcWriteLeveling(PI) end<-----
4416 09:31:19.670249
4417 09:31:19.670315 ==
4418 09:31:19.673445 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 09:31:19.677187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 09:31:19.677282 ==
4421 09:31:19.680086 [Gating] SW mode calibration
4422 09:31:19.686851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4423 09:31:19.693432 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4424 09:31:19.696734 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 09:31:19.700161 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 09:31:19.706632 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 09:31:19.710208 0 9 12 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
4428 09:31:19.713552 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4429 09:31:19.719757 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 09:31:19.723274 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 09:31:19.726504 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 09:31:19.732945 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 09:31:19.736407 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 09:31:19.739938 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 09:31:19.746189 0 10 12 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
4436 09:31:19.749913 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4437 09:31:19.753004 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 09:31:19.760067 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 09:31:19.762826 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 09:31:19.766224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 09:31:19.772540 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 09:31:19.775872 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 09:31:19.779350 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4444 09:31:19.785877 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4445 09:31:19.789185 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 09:31:19.792504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 09:31:19.799213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 09:31:19.802363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 09:31:19.805783 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 09:31:19.812799 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 09:31:19.815839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 09:31:19.819307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 09:31:19.822166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 09:31:19.829029 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 09:31:19.832488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 09:31:19.835382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 09:31:19.842212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 09:31:19.845846 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:31:19.849112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 09:31:19.855424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 09:31:19.858698 Total UI for P1: 0, mck2ui 16
4462 09:31:19.862289 best dqsien dly found for B0: ( 0, 13, 14)
4463 09:31:19.865468 Total UI for P1: 0, mck2ui 16
4464 09:31:19.868882 best dqsien dly found for B1: ( 0, 13, 14)
4465 09:31:19.871843 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4466 09:31:19.875281 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4467 09:31:19.875412
4468 09:31:19.878727 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4469 09:31:19.881702 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4470 09:31:19.885038 [Gating] SW calibration Done
4471 09:31:19.885132 ==
4472 09:31:19.888430 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 09:31:19.891591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 09:31:19.891696 ==
4475 09:31:19.895484 RX Vref Scan: 0
4476 09:31:19.895598
4477 09:31:19.898339 RX Vref 0 -> 0, step: 1
4478 09:31:19.898421
4479 09:31:19.898494 RX Delay -230 -> 252, step: 16
4480 09:31:19.905105 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4481 09:31:19.908543 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4482 09:31:19.911837 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4483 09:31:19.915189 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4484 09:31:19.921708 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4485 09:31:19.925242 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4486 09:31:19.928135 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4487 09:31:19.931957 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4488 09:31:19.938580 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4489 09:31:19.941360 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4490 09:31:19.944740 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4491 09:31:19.948174 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4492 09:31:19.951745 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4493 09:31:19.958344 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4494 09:31:19.961686 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4495 09:31:19.965168 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4496 09:31:19.965251 ==
4497 09:31:19.967951 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 09:31:19.974562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 09:31:19.974651 ==
4500 09:31:19.974756 DQS Delay:
4501 09:31:19.974818 DQS0 = 0, DQS1 = 0
4502 09:31:19.977912 DQM Delay:
4503 09:31:19.977994 DQM0 = 42, DQM1 = 34
4504 09:31:19.981502 DQ Delay:
4505 09:31:19.984710 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4506 09:31:19.984820 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4507 09:31:19.988241 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4508 09:31:19.994735 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4509 09:31:19.994835
4510 09:31:19.994928
4511 09:31:19.995016 ==
4512 09:31:19.997909 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 09:31:20.001199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 09:31:20.001283 ==
4515 09:31:20.001348
4516 09:31:20.001408
4517 09:31:20.004449 TX Vref Scan disable
4518 09:31:20.004547 == TX Byte 0 ==
4519 09:31:20.011430 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4520 09:31:20.014795 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4521 09:31:20.014878 == TX Byte 1 ==
4522 09:31:20.021328 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4523 09:31:20.024615 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4524 09:31:20.024698 ==
4525 09:31:20.027526 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 09:31:20.030848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 09:31:20.030931 ==
4528 09:31:20.031010
4529 09:31:20.031114
4530 09:31:20.034311 TX Vref Scan disable
4531 09:31:20.038004 == TX Byte 0 ==
4532 09:31:20.040902 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 09:31:20.047482 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 09:31:20.047616 == TX Byte 1 ==
4535 09:31:20.050873 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4536 09:31:20.057316 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4537 09:31:20.057404
4538 09:31:20.057470 [DATLAT]
4539 09:31:20.057530 Freq=600, CH1 RK0
4540 09:31:20.057637
4541 09:31:20.061210 DATLAT Default: 0x9
4542 09:31:20.061295 0, 0xFFFF, sum = 0
4543 09:31:20.064360 1, 0xFFFF, sum = 0
4544 09:31:20.064444 2, 0xFFFF, sum = 0
4545 09:31:20.067285 3, 0xFFFF, sum = 0
4546 09:31:20.070587 4, 0xFFFF, sum = 0
4547 09:31:20.070730 5, 0xFFFF, sum = 0
4548 09:31:20.074190 6, 0xFFFF, sum = 0
4549 09:31:20.074298 7, 0xFFFF, sum = 0
4550 09:31:20.077390 8, 0x0, sum = 1
4551 09:31:20.077473 9, 0x0, sum = 2
4552 09:31:20.077540 10, 0x0, sum = 3
4553 09:31:20.080529 11, 0x0, sum = 4
4554 09:31:20.080612 best_step = 9
4555 09:31:20.080676
4556 09:31:20.080759 ==
4557 09:31:20.084259 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 09:31:20.090472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 09:31:20.090624 ==
4560 09:31:20.090708 RX Vref Scan: 1
4561 09:31:20.090770
4562 09:31:20.094113 RX Vref 0 -> 0, step: 1
4563 09:31:20.094239
4564 09:31:20.097530 RX Delay -195 -> 252, step: 8
4565 09:31:20.097654
4566 09:31:20.100760 Set Vref, RX VrefLevel [Byte0]: 57
4567 09:31:20.104001 [Byte1]: 50
4568 09:31:20.104111
4569 09:31:20.107258 Final RX Vref Byte 0 = 57 to rank0
4570 09:31:20.110466 Final RX Vref Byte 1 = 50 to rank0
4571 09:31:20.113864 Final RX Vref Byte 0 = 57 to rank1
4572 09:31:20.117343 Final RX Vref Byte 1 = 50 to rank1==
4573 09:31:20.120897 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 09:31:20.123949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 09:31:20.124035 ==
4576 09:31:20.127179 DQS Delay:
4577 09:31:20.127309 DQS0 = 0, DQS1 = 0
4578 09:31:20.130395 DQM Delay:
4579 09:31:20.130504 DQM0 = 38, DQM1 = 28
4580 09:31:20.130597 DQ Delay:
4581 09:31:20.134015 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =32
4582 09:31:20.137336 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4583 09:31:20.140788 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4584 09:31:20.144248 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4585 09:31:20.144332
4586 09:31:20.144397
4587 09:31:20.154485 [DQSOSCAuto] RK0, (LSB)MR18= 0x2836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4588 09:31:20.157095 CH1 RK0: MR19=808, MR18=2836
4589 09:31:20.160658 CH1_RK0: MR19=0x808, MR18=0x2836, DQSOSC=399, MR23=63, INC=164, DEC=109
4590 09:31:20.163938
4591 09:31:20.167271 ----->DramcWriteLeveling(PI) begin...
4592 09:31:20.167394 ==
4593 09:31:20.170276 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 09:31:20.174166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 09:31:20.174251 ==
4596 09:31:20.177349 Write leveling (Byte 0): 29 => 29
4597 09:31:20.180240 Write leveling (Byte 1): 30 => 30
4598 09:31:20.183791 DramcWriteLeveling(PI) end<-----
4599 09:31:20.183886
4600 09:31:20.183952 ==
4601 09:31:20.186928 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 09:31:20.190426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 09:31:20.190518 ==
4604 09:31:20.193854 [Gating] SW mode calibration
4605 09:31:20.200211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 09:31:20.206958 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 09:31:20.210252 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 09:31:20.213834 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 09:31:20.220153 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 09:31:20.223366 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 1)
4611 09:31:20.226922 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4612 09:31:20.233403 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 09:31:20.236679 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 09:31:20.240064 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 09:31:20.246915 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 09:31:20.250295 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 09:31:20.253285 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4618 09:31:20.256713 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
4619 09:31:20.263310 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 09:31:20.266569 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 09:31:20.269956 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 09:31:20.276553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 09:31:20.280030 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 09:31:20.283314 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 09:31:20.289985 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 09:31:20.293113 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4627 09:31:20.296272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 09:31:20.302983 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 09:31:20.306545 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 09:31:20.309978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 09:31:20.315967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 09:31:20.319338 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 09:31:20.322959 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 09:31:20.329259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 09:31:20.332692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 09:31:20.336232 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 09:31:20.342656 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 09:31:20.345793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 09:31:20.349190 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 09:31:20.355551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 09:31:20.358975 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4642 09:31:20.362317 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 09:31:20.365831 Total UI for P1: 0, mck2ui 16
4644 09:31:20.368740 best dqsien dly found for B0: ( 0, 13, 8)
4645 09:31:20.372111 Total UI for P1: 0, mck2ui 16
4646 09:31:20.375651 best dqsien dly found for B1: ( 0, 13, 10)
4647 09:31:20.379148 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4648 09:31:20.382034 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4649 09:31:20.385973
4650 09:31:20.389256 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4651 09:31:20.392035 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 09:31:20.395713 [Gating] SW calibration Done
4653 09:31:20.395811 ==
4654 09:31:20.398662 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 09:31:20.402731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 09:31:20.402814 ==
4657 09:31:20.402879 RX Vref Scan: 0
4658 09:31:20.405209
4659 09:31:20.405290 RX Vref 0 -> 0, step: 1
4660 09:31:20.405354
4661 09:31:20.409078 RX Delay -230 -> 252, step: 16
4662 09:31:20.412087 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4663 09:31:20.418496 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4664 09:31:20.421848 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4665 09:31:20.425338 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4666 09:31:20.428411 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4667 09:31:20.431699 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4668 09:31:20.438416 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4669 09:31:20.441450 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4670 09:31:20.444868 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4671 09:31:20.448302 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4672 09:31:20.455305 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4673 09:31:20.458156 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4674 09:31:20.461642 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4675 09:31:20.465176 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4676 09:31:20.471236 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4677 09:31:20.474735 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4678 09:31:20.474825 ==
4679 09:31:20.478295 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 09:31:20.481703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 09:31:20.481787 ==
4682 09:31:20.484539 DQS Delay:
4683 09:31:20.484622 DQS0 = 0, DQS1 = 0
4684 09:31:20.484687 DQM Delay:
4685 09:31:20.487903 DQM0 = 35, DQM1 = 29
4686 09:31:20.487984 DQ Delay:
4687 09:31:20.491417 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4688 09:31:20.494970 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4689 09:31:20.498284 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4690 09:31:20.500959 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4691 09:31:20.501042
4692 09:31:20.501107
4693 09:31:20.501166 ==
4694 09:31:20.504518 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 09:31:20.511281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 09:31:20.511437 ==
4697 09:31:20.511509
4698 09:31:20.511570
4699 09:31:20.511630 TX Vref Scan disable
4700 09:31:20.514969 == TX Byte 0 ==
4701 09:31:20.517970 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4702 09:31:20.521459 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4703 09:31:20.524960 == TX Byte 1 ==
4704 09:31:20.528112 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 09:31:20.534676 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 09:31:20.534762 ==
4707 09:31:20.538110 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 09:31:20.541401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 09:31:20.541485 ==
4710 09:31:20.541550
4711 09:31:20.541609
4712 09:31:20.544690 TX Vref Scan disable
4713 09:31:20.548064 == TX Byte 0 ==
4714 09:31:20.551619 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4715 09:31:20.554879 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4716 09:31:20.558286 == TX Byte 1 ==
4717 09:31:20.561356 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 09:31:20.564799 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 09:31:20.564880
4720 09:31:20.564944 [DATLAT]
4721 09:31:20.568316 Freq=600, CH1 RK1
4722 09:31:20.568398
4723 09:31:20.568462 DATLAT Default: 0x9
4724 09:31:20.571081 0, 0xFFFF, sum = 0
4725 09:31:20.571164 1, 0xFFFF, sum = 0
4726 09:31:20.574362 2, 0xFFFF, sum = 0
4727 09:31:20.577830 3, 0xFFFF, sum = 0
4728 09:31:20.577939 4, 0xFFFF, sum = 0
4729 09:31:20.581347 5, 0xFFFF, sum = 0
4730 09:31:20.581456 6, 0xFFFF, sum = 0
4731 09:31:20.584630 7, 0xFFFF, sum = 0
4732 09:31:20.584752 8, 0x0, sum = 1
4733 09:31:20.588154 9, 0x0, sum = 2
4734 09:31:20.588277 10, 0x0, sum = 3
4735 09:31:20.588378 11, 0x0, sum = 4
4736 09:31:20.590952 best_step = 9
4737 09:31:20.591055
4738 09:31:20.591157 ==
4739 09:31:20.594369 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 09:31:20.597755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 09:31:20.597867 ==
4742 09:31:20.601298 RX Vref Scan: 0
4743 09:31:20.601400
4744 09:31:20.601503 RX Vref 0 -> 0, step: 1
4745 09:31:20.601595
4746 09:31:20.604132 RX Delay -195 -> 252, step: 8
4747 09:31:20.611845 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4748 09:31:20.615548 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4749 09:31:20.618949 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4750 09:31:20.622077 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4751 09:31:20.628954 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4752 09:31:20.631866 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4753 09:31:20.635380 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4754 09:31:20.638322 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4755 09:31:20.641816 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4756 09:31:20.649022 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4757 09:31:20.651981 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4758 09:31:20.655203 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4759 09:31:20.658363 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4760 09:31:20.665208 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4761 09:31:20.668311 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4762 09:31:20.671345 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4763 09:31:20.671504 ==
4764 09:31:20.674647 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 09:31:20.681475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 09:31:20.681627 ==
4767 09:31:20.681723 DQS Delay:
4768 09:31:20.681813 DQS0 = 0, DQS1 = 0
4769 09:31:20.684997 DQM Delay:
4770 09:31:20.685106 DQM0 = 35, DQM1 = 29
4771 09:31:20.688182 DQ Delay:
4772 09:31:20.691652 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4773 09:31:20.691777 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =32
4774 09:31:20.695023 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4775 09:31:20.701469 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4776 09:31:20.701664
4777 09:31:20.701792
4778 09:31:20.708489 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4779 09:31:20.711620 CH1 RK1: MR19=808, MR18=3D5D
4780 09:31:20.718302 CH1_RK1: MR19=0x808, MR18=0x3D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4781 09:31:20.721133 [RxdqsGatingPostProcess] freq 600
4782 09:31:20.724670 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4783 09:31:20.728202 Pre-setting of DQS Precalculation
4784 09:31:20.734735 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4785 09:31:20.741175 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4786 09:31:20.747913 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4787 09:31:20.748033
4788 09:31:20.748102
4789 09:31:20.751226 [Calibration Summary] 1200 Mbps
4790 09:31:20.751303 CH 0, Rank 0
4791 09:31:20.754761 SW Impedance : PASS
4792 09:31:20.758187 DUTY Scan : NO K
4793 09:31:20.758268 ZQ Calibration : PASS
4794 09:31:20.761058 Jitter Meter : NO K
4795 09:31:20.764246 CBT Training : PASS
4796 09:31:20.764345 Write leveling : PASS
4797 09:31:20.767657 RX DQS gating : PASS
4798 09:31:20.771358 RX DQ/DQS(RDDQC) : PASS
4799 09:31:20.771465 TX DQ/DQS : PASS
4800 09:31:20.774517 RX DATLAT : PASS
4801 09:31:20.774601 RX DQ/DQS(Engine): PASS
4802 09:31:20.777461 TX OE : NO K
4803 09:31:20.777595 All Pass.
4804 09:31:20.777699
4805 09:31:20.781082 CH 0, Rank 1
4806 09:31:20.781163 SW Impedance : PASS
4807 09:31:20.784184 DUTY Scan : NO K
4808 09:31:20.787623 ZQ Calibration : PASS
4809 09:31:20.787698 Jitter Meter : NO K
4810 09:31:20.791268 CBT Training : PASS
4811 09:31:20.794465 Write leveling : PASS
4812 09:31:20.794564 RX DQS gating : PASS
4813 09:31:20.797946 RX DQ/DQS(RDDQC) : PASS
4814 09:31:20.800841 TX DQ/DQS : PASS
4815 09:31:20.800947 RX DATLAT : PASS
4816 09:31:20.804493 RX DQ/DQS(Engine): PASS
4817 09:31:20.807590 TX OE : NO K
4818 09:31:20.807669 All Pass.
4819 09:31:20.807732
4820 09:31:20.807792 CH 1, Rank 0
4821 09:31:20.810897 SW Impedance : PASS
4822 09:31:20.814320 DUTY Scan : NO K
4823 09:31:20.814411 ZQ Calibration : PASS
4824 09:31:20.817743 Jitter Meter : NO K
4825 09:31:20.821118 CBT Training : PASS
4826 09:31:20.821194 Write leveling : PASS
4827 09:31:20.824373 RX DQS gating : PASS
4828 09:31:20.824452 RX DQ/DQS(RDDQC) : PASS
4829 09:31:20.827244 TX DQ/DQS : PASS
4830 09:31:20.831070 RX DATLAT : PASS
4831 09:31:20.831165 RX DQ/DQS(Engine): PASS
4832 09:31:20.834692 TX OE : NO K
4833 09:31:20.834785 All Pass.
4834 09:31:20.834863
4835 09:31:20.838009 CH 1, Rank 1
4836 09:31:20.838084 SW Impedance : PASS
4837 09:31:20.841037 DUTY Scan : NO K
4838 09:31:20.845098 ZQ Calibration : PASS
4839 09:31:20.845185 Jitter Meter : NO K
4840 09:31:20.847564 CBT Training : PASS
4841 09:31:20.850967 Write leveling : PASS
4842 09:31:20.851066 RX DQS gating : PASS
4843 09:31:20.854343 RX DQ/DQS(RDDQC) : PASS
4844 09:31:20.857883 TX DQ/DQS : PASS
4845 09:31:20.857967 RX DATLAT : PASS
4846 09:31:20.861233 RX DQ/DQS(Engine): PASS
4847 09:31:20.861331 TX OE : NO K
4848 09:31:20.864225 All Pass.
4849 09:31:20.864306
4850 09:31:20.864371 DramC Write-DBI off
4851 09:31:20.867724 PER_BANK_REFRESH: Hybrid Mode
4852 09:31:20.870571 TX_TRACKING: ON
4853 09:31:20.877086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4854 09:31:20.880605 [FAST_K] Save calibration result to emmc
4855 09:31:20.887532 dramc_set_vcore_voltage set vcore to 662500
4856 09:31:20.887623 Read voltage for 933, 3
4857 09:31:20.890835 Vio18 = 0
4858 09:31:20.890917 Vcore = 662500
4859 09:31:20.890982 Vdram = 0
4860 09:31:20.891043 Vddq = 0
4861 09:31:20.894103 Vmddr = 0
4862 09:31:20.897616 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4863 09:31:20.903848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4864 09:31:20.906884 MEM_TYPE=3, freq_sel=17
4865 09:31:20.906968 sv_algorithm_assistance_LP4_1600
4866 09:31:20.913777 ============ PULL DRAM RESETB DOWN ============
4867 09:31:20.916908 ========== PULL DRAM RESETB DOWN end =========
4868 09:31:20.920601 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 09:31:20.923541 ===================================
4870 09:31:20.927271 LPDDR4 DRAM CONFIGURATION
4871 09:31:20.930680 ===================================
4872 09:31:20.933502 EX_ROW_EN[0] = 0x0
4873 09:31:20.933586 EX_ROW_EN[1] = 0x0
4874 09:31:20.936899 LP4Y_EN = 0x0
4875 09:31:20.936981 WORK_FSP = 0x0
4876 09:31:20.940348 WL = 0x3
4877 09:31:20.940454 RL = 0x3
4878 09:31:20.943907 BL = 0x2
4879 09:31:20.943991 RPST = 0x0
4880 09:31:20.947003 RD_PRE = 0x0
4881 09:31:20.947085 WR_PRE = 0x1
4882 09:31:20.950063 WR_PST = 0x0
4883 09:31:20.950145 DBI_WR = 0x0
4884 09:31:20.953478 DBI_RD = 0x0
4885 09:31:20.956794 OTF = 0x1
4886 09:31:20.960253 ===================================
4887 09:31:20.963207 ===================================
4888 09:31:20.963305 ANA top config
4889 09:31:20.967211 ===================================
4890 09:31:20.970132 DLL_ASYNC_EN = 0
4891 09:31:20.970220 ALL_SLAVE_EN = 1
4892 09:31:20.973561 NEW_RANK_MODE = 1
4893 09:31:20.976900 DLL_IDLE_MODE = 1
4894 09:31:20.980011 LP45_APHY_COMB_EN = 1
4895 09:31:20.983275 TX_ODT_DIS = 1
4896 09:31:20.983382 NEW_8X_MODE = 1
4897 09:31:20.986579 ===================================
4898 09:31:20.990013 ===================================
4899 09:31:20.993052 data_rate = 1866
4900 09:31:20.996348 CKR = 1
4901 09:31:20.999632 DQ_P2S_RATIO = 8
4902 09:31:21.003071 ===================================
4903 09:31:21.006205 CA_P2S_RATIO = 8
4904 09:31:21.009598 DQ_CA_OPEN = 0
4905 09:31:21.009677 DQ_SEMI_OPEN = 0
4906 09:31:21.012968 CA_SEMI_OPEN = 0
4907 09:31:21.016427 CA_FULL_RATE = 0
4908 09:31:21.020097 DQ_CKDIV4_EN = 1
4909 09:31:21.022836 CA_CKDIV4_EN = 1
4910 09:31:21.026148 CA_PREDIV_EN = 0
4911 09:31:21.026273 PH8_DLY = 0
4912 09:31:21.029384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4913 09:31:21.032956 DQ_AAMCK_DIV = 4
4914 09:31:21.036322 CA_AAMCK_DIV = 4
4915 09:31:21.039626 CA_ADMCK_DIV = 4
4916 09:31:21.042897 DQ_TRACK_CA_EN = 0
4917 09:31:21.046260 CA_PICK = 933
4918 09:31:21.046338 CA_MCKIO = 933
4919 09:31:21.049623 MCKIO_SEMI = 0
4920 09:31:21.052487 PLL_FREQ = 3732
4921 09:31:21.055936 DQ_UI_PI_RATIO = 32
4922 09:31:21.059341 CA_UI_PI_RATIO = 0
4923 09:31:21.062612 ===================================
4924 09:31:21.065642 ===================================
4925 09:31:21.069106 memory_type:LPDDR4
4926 09:31:21.069188 GP_NUM : 10
4927 09:31:21.072519 SRAM_EN : 1
4928 09:31:21.072597 MD32_EN : 0
4929 09:31:21.076034 ===================================
4930 09:31:21.078908 [ANA_INIT] >>>>>>>>>>>>>>
4931 09:31:21.082154 <<<<<< [CONFIGURE PHASE]: ANA_TX
4932 09:31:21.085514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4933 09:31:21.089042 ===================================
4934 09:31:21.092343 data_rate = 1866,PCW = 0X8f00
4935 09:31:21.095794 ===================================
4936 09:31:21.099242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4937 09:31:21.105318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 09:31:21.109170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 09:31:21.115244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4940 09:31:21.118707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4941 09:31:21.122103 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4942 09:31:21.122189 [ANA_INIT] flow start
4943 09:31:21.125232 [ANA_INIT] PLL >>>>>>>>
4944 09:31:21.129150 [ANA_INIT] PLL <<<<<<<<
4945 09:31:21.129262 [ANA_INIT] MIDPI >>>>>>>>
4946 09:31:21.131886 [ANA_INIT] MIDPI <<<<<<<<
4947 09:31:21.135430 [ANA_INIT] DLL >>>>>>>>
4948 09:31:21.135538 [ANA_INIT] flow end
4949 09:31:21.141850 ============ LP4 DIFF to SE enter ============
4950 09:31:21.145767 ============ LP4 DIFF to SE exit ============
4951 09:31:21.148576 [ANA_INIT] <<<<<<<<<<<<<
4952 09:31:21.151671 [Flow] Enable top DCM control >>>>>
4953 09:31:21.155269 [Flow] Enable top DCM control <<<<<
4954 09:31:21.155399 Enable DLL master slave shuffle
4955 09:31:21.161872 ==============================================================
4956 09:31:21.165248 Gating Mode config
4957 09:31:21.168528 ==============================================================
4958 09:31:21.171893 Config description:
4959 09:31:21.181578 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4960 09:31:21.188574 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4961 09:31:21.191849 SELPH_MODE 0: By rank 1: By Phase
4962 09:31:21.198261 ==============================================================
4963 09:31:21.201644 GAT_TRACK_EN = 1
4964 09:31:21.205054 RX_GATING_MODE = 2
4965 09:31:21.208340 RX_GATING_TRACK_MODE = 2
4966 09:31:21.211341 SELPH_MODE = 1
4967 09:31:21.211457 PICG_EARLY_EN = 1
4968 09:31:21.215074 VALID_LAT_VALUE = 1
4969 09:31:21.221881 ==============================================================
4970 09:31:21.224711 Enter into Gating configuration >>>>
4971 09:31:21.228290 Exit from Gating configuration <<<<
4972 09:31:21.231225 Enter into DVFS_PRE_config >>>>>
4973 09:31:21.241505 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4974 09:31:21.244947 Exit from DVFS_PRE_config <<<<<
4975 09:31:21.247855 Enter into PICG configuration >>>>
4976 09:31:21.251631 Exit from PICG configuration <<<<
4977 09:31:21.254546 [RX_INPUT] configuration >>>>>
4978 09:31:21.258031 [RX_INPUT] configuration <<<<<
4979 09:31:21.261348 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4980 09:31:21.267840 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4981 09:31:21.275307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 09:31:21.281342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 09:31:21.287716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 09:31:21.294456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 09:31:21.297367 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4986 09:31:21.300794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4987 09:31:21.304626 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4988 09:31:21.307726 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4989 09:31:21.314229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4990 09:31:21.317681 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 09:31:21.320945 ===================================
4992 09:31:21.324422 LPDDR4 DRAM CONFIGURATION
4993 09:31:21.327335 ===================================
4994 09:31:21.327467 EX_ROW_EN[0] = 0x0
4995 09:31:21.330646 EX_ROW_EN[1] = 0x0
4996 09:31:21.330745 LP4Y_EN = 0x0
4997 09:31:21.334157 WORK_FSP = 0x0
4998 09:31:21.334233 WL = 0x3
4999 09:31:21.337252 RL = 0x3
5000 09:31:21.337332 BL = 0x2
5001 09:31:21.340652 RPST = 0x0
5002 09:31:21.344169 RD_PRE = 0x0
5003 09:31:21.344258 WR_PRE = 0x1
5004 09:31:21.347533 WR_PST = 0x0
5005 09:31:21.347615 DBI_WR = 0x0
5006 09:31:21.350943 DBI_RD = 0x0
5007 09:31:21.351025 OTF = 0x1
5008 09:31:21.354132 ===================================
5009 09:31:21.357349 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5010 09:31:21.363785 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5011 09:31:21.367183 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 09:31:21.370586 ===================================
5013 09:31:21.373969 LPDDR4 DRAM CONFIGURATION
5014 09:31:21.377440 ===================================
5015 09:31:21.377516 EX_ROW_EN[0] = 0x10
5016 09:31:21.380813 EX_ROW_EN[1] = 0x0
5017 09:31:21.380885 LP4Y_EN = 0x0
5018 09:31:21.384497 WORK_FSP = 0x0
5019 09:31:21.384572 WL = 0x3
5020 09:31:21.387740 RL = 0x3
5021 09:31:21.387814 BL = 0x2
5022 09:31:21.391175 RPST = 0x0
5023 09:31:21.391248 RD_PRE = 0x0
5024 09:31:21.393873 WR_PRE = 0x1
5025 09:31:21.393981 WR_PST = 0x0
5026 09:31:21.397239 DBI_WR = 0x0
5027 09:31:21.400615 DBI_RD = 0x0
5028 09:31:21.400709 OTF = 0x1
5029 09:31:21.403976 ===================================
5030 09:31:21.410694 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5031 09:31:21.414359 nWR fixed to 30
5032 09:31:21.417330 [ModeRegInit_LP4] CH0 RK0
5033 09:31:21.417415 [ModeRegInit_LP4] CH0 RK1
5034 09:31:21.420956 [ModeRegInit_LP4] CH1 RK0
5035 09:31:21.424031 [ModeRegInit_LP4] CH1 RK1
5036 09:31:21.424114 match AC timing 9
5037 09:31:21.430773 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5038 09:31:21.433684 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5039 09:31:21.437146 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5040 09:31:21.443656 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5041 09:31:21.447149 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5042 09:31:21.447258 ==
5043 09:31:21.450268 Dram Type= 6, Freq= 0, CH_0, rank 0
5044 09:31:21.453696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5045 09:31:21.453782 ==
5046 09:31:21.460054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5047 09:31:21.466802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5048 09:31:21.470229 [CA 0] Center 38 (8~69) winsize 62
5049 09:31:21.473242 [CA 1] Center 38 (8~69) winsize 62
5050 09:31:21.476948 [CA 2] Center 35 (5~66) winsize 62
5051 09:31:21.480373 [CA 3] Center 35 (5~65) winsize 61
5052 09:31:21.483292 [CA 4] Center 34 (4~64) winsize 61
5053 09:31:21.486786 [CA 5] Center 33 (3~64) winsize 62
5054 09:31:21.486871
5055 09:31:21.490122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5056 09:31:21.490205
5057 09:31:21.493562 [CATrainingPosCal] consider 1 rank data
5058 09:31:21.497196 u2DelayCellTimex100 = 270/100 ps
5059 09:31:21.499826 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5060 09:31:21.503727 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5061 09:31:21.506649 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5062 09:31:21.510129 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5063 09:31:21.513659 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5064 09:31:21.520413 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5065 09:31:21.520500
5066 09:31:21.523096 CA PerBit enable=1, Macro0, CA PI delay=33
5067 09:31:21.523223
5068 09:31:21.526718 [CBTSetCACLKResult] CA Dly = 33
5069 09:31:21.526802 CS Dly: 7 (0~38)
5070 09:31:21.526888 ==
5071 09:31:21.529824 Dram Type= 6, Freq= 0, CH_0, rank 1
5072 09:31:21.533176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 09:31:21.536575 ==
5074 09:31:21.540245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 09:31:21.546464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5076 09:31:21.549677 [CA 0] Center 38 (8~69) winsize 62
5077 09:31:21.552948 [CA 1] Center 38 (8~69) winsize 62
5078 09:31:21.556841 [CA 2] Center 35 (5~66) winsize 62
5079 09:31:21.559686 [CA 3] Center 35 (5~66) winsize 62
5080 09:31:21.563062 [CA 4] Center 34 (4~65) winsize 62
5081 09:31:21.566583 [CA 5] Center 34 (4~64) winsize 61
5082 09:31:21.566671
5083 09:31:21.569774 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5084 09:31:21.569858
5085 09:31:21.573201 [CATrainingPosCal] consider 2 rank data
5086 09:31:21.576662 u2DelayCellTimex100 = 270/100 ps
5087 09:31:21.579804 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5088 09:31:21.583228 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5089 09:31:21.586774 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5090 09:31:21.589476 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5091 09:31:21.596510 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5092 09:31:21.599338 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5093 09:31:21.599459
5094 09:31:21.602800 CA PerBit enable=1, Macro0, CA PI delay=34
5095 09:31:21.602885
5096 09:31:21.606230 [CBTSetCACLKResult] CA Dly = 34
5097 09:31:21.606315 CS Dly: 7 (0~38)
5098 09:31:21.606399
5099 09:31:21.609581 ----->DramcWriteLeveling(PI) begin...
5100 09:31:21.609666 ==
5101 09:31:21.612687 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 09:31:21.619444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 09:31:21.619533 ==
5104 09:31:21.622736 Write leveling (Byte 0): 31 => 31
5105 09:31:21.626077 Write leveling (Byte 1): 30 => 30
5106 09:31:21.626163 DramcWriteLeveling(PI) end<-----
5107 09:31:21.626247
5108 09:31:21.629662 ==
5109 09:31:21.632799 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 09:31:21.636256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 09:31:21.636367 ==
5112 09:31:21.639406 [Gating] SW mode calibration
5113 09:31:21.645808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5114 09:31:21.649325 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5115 09:31:21.656313 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5116 09:31:21.659504 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5117 09:31:21.662623 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 09:31:21.669402 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 09:31:21.672419 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 09:31:21.676065 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 09:31:21.682257 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 09:31:21.685654 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5123 09:31:21.689094 0 15 0 | B1->B0 | 3333 2c2c | 0 1 | (0 0) (1 0)
5124 09:31:21.696051 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5125 09:31:21.699010 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 09:31:21.702854 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 09:31:21.709069 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 09:31:21.712532 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 09:31:21.716327 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 09:31:21.722368 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 09:31:21.725759 1 0 0 | B1->B0 | 2f2f 3d3d | 0 0 | (0 0) (0 0)
5132 09:31:21.728678 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 09:31:21.735706 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 09:31:21.738888 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 09:31:21.742041 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 09:31:21.748900 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 09:31:21.752128 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 09:31:21.755255 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 09:31:21.762109 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 09:31:21.765026 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5141 09:31:21.768632 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 09:31:21.775209 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 09:31:21.778542 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 09:31:21.781960 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 09:31:21.788444 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 09:31:21.791376 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 09:31:21.794983 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 09:31:21.801636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 09:31:21.805072 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 09:31:21.808460 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 09:31:21.814922 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 09:31:21.818413 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 09:31:21.821655 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 09:31:21.825008 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 09:31:21.831812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5156 09:31:21.834987 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5157 09:31:21.838035 Total UI for P1: 0, mck2ui 16
5158 09:31:21.841327 best dqsien dly found for B0: ( 1, 2, 30)
5159 09:31:21.844784 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 09:31:21.847817 Total UI for P1: 0, mck2ui 16
5161 09:31:21.851264 best dqsien dly found for B1: ( 1, 3, 4)
5162 09:31:21.854421 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5163 09:31:21.861497 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5164 09:31:21.861580
5165 09:31:21.864286 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5166 09:31:21.867651 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5167 09:31:21.871199 [Gating] SW calibration Done
5168 09:31:21.871280 ==
5169 09:31:21.874573 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 09:31:21.878027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 09:31:21.878108 ==
5172 09:31:21.878172 RX Vref Scan: 0
5173 09:31:21.881077
5174 09:31:21.881158 RX Vref 0 -> 0, step: 1
5175 09:31:21.881222
5176 09:31:21.884531 RX Delay -80 -> 252, step: 8
5177 09:31:21.887635 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5178 09:31:21.891086 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5179 09:31:21.897680 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5180 09:31:21.900768 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5181 09:31:21.904201 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5182 09:31:21.907401 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5183 09:31:21.910859 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5184 09:31:21.914074 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5185 09:31:21.920655 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5186 09:31:21.923991 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5187 09:31:21.927297 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5188 09:31:21.930663 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5189 09:31:21.934180 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5190 09:31:21.940944 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5191 09:31:21.944206 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5192 09:31:21.947183 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5193 09:31:21.947289 ==
5194 09:31:21.950503 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 09:31:21.953965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 09:31:21.957160 ==
5197 09:31:21.957241 DQS Delay:
5198 09:31:21.957306 DQS0 = 0, DQS1 = 0
5199 09:31:21.960551 DQM Delay:
5200 09:31:21.960635 DQM0 = 94, DQM1 = 83
5201 09:31:21.963508 DQ Delay:
5202 09:31:21.963589 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5203 09:31:21.966702 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5204 09:31:21.970490 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5205 09:31:21.976835 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5206 09:31:21.976916
5207 09:31:21.976980
5208 09:31:21.977039 ==
5209 09:31:21.980204 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 09:31:21.983555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 09:31:21.983652 ==
5212 09:31:21.983716
5213 09:31:21.983774
5214 09:31:21.986588 TX Vref Scan disable
5215 09:31:21.986669 == TX Byte 0 ==
5216 09:31:21.993325 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5217 09:31:21.996505 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5218 09:31:21.996587 == TX Byte 1 ==
5219 09:31:22.002966 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5220 09:31:22.006252 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5221 09:31:22.006360 ==
5222 09:31:22.009571 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 09:31:22.013141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 09:31:22.013250 ==
5225 09:31:22.013344
5226 09:31:22.016254
5227 09:31:22.016357 TX Vref Scan disable
5228 09:31:22.019530 == TX Byte 0 ==
5229 09:31:22.022968 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5230 09:31:22.025915 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5231 09:31:22.029466 == TX Byte 1 ==
5232 09:31:22.033162 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5233 09:31:22.036060 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5234 09:31:22.039506
5235 09:31:22.039586 [DATLAT]
5236 09:31:22.039650 Freq=933, CH0 RK0
5237 09:31:22.039710
5238 09:31:22.043148 DATLAT Default: 0xd
5239 09:31:22.043266 0, 0xFFFF, sum = 0
5240 09:31:22.046030 1, 0xFFFF, sum = 0
5241 09:31:22.046112 2, 0xFFFF, sum = 0
5242 09:31:22.049581 3, 0xFFFF, sum = 0
5243 09:31:22.049663 4, 0xFFFF, sum = 0
5244 09:31:22.052917 5, 0xFFFF, sum = 0
5245 09:31:22.056484 6, 0xFFFF, sum = 0
5246 09:31:22.056564 7, 0xFFFF, sum = 0
5247 09:31:22.059987 8, 0xFFFF, sum = 0
5248 09:31:22.060068 9, 0xFFFF, sum = 0
5249 09:31:22.062870 10, 0x0, sum = 1
5250 09:31:22.062951 11, 0x0, sum = 2
5251 09:31:22.065714 12, 0x0, sum = 3
5252 09:31:22.065825 13, 0x0, sum = 4
5253 09:31:22.065889 best_step = 11
5254 09:31:22.065948
5255 09:31:22.069095 ==
5256 09:31:22.072528 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 09:31:22.076034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 09:31:22.076130 ==
5259 09:31:22.076193 RX Vref Scan: 1
5260 09:31:22.076254
5261 09:31:22.079286 RX Vref 0 -> 0, step: 1
5262 09:31:22.079401
5263 09:31:22.082679 RX Delay -77 -> 252, step: 4
5264 09:31:22.082759
5265 09:31:22.086081 Set Vref, RX VrefLevel [Byte0]: 61
5266 09:31:22.088971 [Byte1]: 53
5267 09:31:22.089052
5268 09:31:22.092296 Final RX Vref Byte 0 = 61 to rank0
5269 09:31:22.095784 Final RX Vref Byte 1 = 53 to rank0
5270 09:31:22.098973 Final RX Vref Byte 0 = 61 to rank1
5271 09:31:22.102501 Final RX Vref Byte 1 = 53 to rank1==
5272 09:31:22.105962 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 09:31:22.108822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 09:31:22.112320 ==
5275 09:31:22.112401 DQS Delay:
5276 09:31:22.112466 DQS0 = 0, DQS1 = 0
5277 09:31:22.115495 DQM Delay:
5278 09:31:22.115576 DQM0 = 95, DQM1 = 83
5279 09:31:22.118760 DQ Delay:
5280 09:31:22.118840 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5281 09:31:22.122393 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5282 09:31:22.125333 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =78
5283 09:31:22.131981 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =90
5284 09:31:22.132100
5285 09:31:22.132164
5286 09:31:22.138904 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5287 09:31:22.142284 CH0 RK0: MR19=505, MR18=1111
5288 09:31:22.148892 CH0_RK0: MR19=0x505, MR18=0x1111, DQSOSC=416, MR23=63, INC=62, DEC=41
5289 09:31:22.148978
5290 09:31:22.151964 ----->DramcWriteLeveling(PI) begin...
5291 09:31:22.152046 ==
5292 09:31:22.155285 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 09:31:22.158573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 09:31:22.158653 ==
5295 09:31:22.162066 Write leveling (Byte 0): 31 => 31
5296 09:31:22.165638 Write leveling (Byte 1): 31 => 31
5297 09:31:22.168943 DramcWriteLeveling(PI) end<-----
5298 09:31:22.169023
5299 09:31:22.169086 ==
5300 09:31:22.172413 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 09:31:22.175153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 09:31:22.175233 ==
5303 09:31:22.178723 [Gating] SW mode calibration
5304 09:31:22.185373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 09:31:22.192217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 09:31:22.195139 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5307 09:31:22.198892 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 09:31:22.204939 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 09:31:22.208375 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 09:31:22.211754 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 09:31:22.218779 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 09:31:22.222042 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5313 09:31:22.224957 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (1 0)
5314 09:31:22.231662 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5315 09:31:22.234912 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 09:31:22.238616 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 09:31:22.245312 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 09:31:22.248218 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 09:31:22.251636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 09:31:22.258242 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 09:31:22.261422 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
5322 09:31:22.264755 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5323 09:31:22.271180 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 09:31:22.274803 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 09:31:22.278321 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 09:31:22.285152 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 09:31:22.288005 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 09:31:22.291349 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 09:31:22.298399 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5330 09:31:22.301508 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5331 09:31:22.304464 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 09:31:22.311301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 09:31:22.314689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 09:31:22.317814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 09:31:22.324708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 09:31:22.327963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 09:31:22.331542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 09:31:22.337689 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 09:31:22.341157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 09:31:22.344638 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 09:31:22.351121 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 09:31:22.354280 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 09:31:22.357556 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:31:22.364141 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:31:22.367395 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5346 09:31:22.370764 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 09:31:22.377550 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 09:31:22.377633 Total UI for P1: 0, mck2ui 16
5349 09:31:22.380577 best dqsien dly found for B0: ( 1, 2, 30)
5350 09:31:22.384201 Total UI for P1: 0, mck2ui 16
5351 09:31:22.387656 best dqsien dly found for B1: ( 1, 3, 2)
5352 09:31:22.390489 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5353 09:31:22.397765 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5354 09:31:22.397848
5355 09:31:22.401082 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5356 09:31:22.404557 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5357 09:31:22.407349 [Gating] SW calibration Done
5358 09:31:22.407457 ==
5359 09:31:22.410689 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 09:31:22.414394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 09:31:22.414515 ==
5362 09:31:22.414603 RX Vref Scan: 0
5363 09:31:22.414681
5364 09:31:22.417101 RX Vref 0 -> 0, step: 1
5365 09:31:22.417173
5366 09:31:22.420863 RX Delay -80 -> 252, step: 8
5367 09:31:22.423864 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5368 09:31:22.427057 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5369 09:31:22.433921 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5370 09:31:22.437296 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5371 09:31:22.440644 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5372 09:31:22.444058 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5373 09:31:22.446902 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5374 09:31:22.450434 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5375 09:31:22.457410 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5376 09:31:22.460287 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5377 09:31:22.463770 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5378 09:31:22.467102 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5379 09:31:22.470351 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5380 09:31:22.477203 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5381 09:31:22.480381 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5382 09:31:22.483725 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5383 09:31:22.483804 ==
5384 09:31:22.487065 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 09:31:22.490382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 09:31:22.493303 ==
5387 09:31:22.493381 DQS Delay:
5388 09:31:22.493446 DQS0 = 0, DQS1 = 0
5389 09:31:22.496816 DQM Delay:
5390 09:31:22.496893 DQM0 = 91, DQM1 = 83
5391 09:31:22.500353 DQ Delay:
5392 09:31:22.500428 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5393 09:31:22.503515 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5394 09:31:22.506584 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5395 09:31:22.509943 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5396 09:31:22.513401
5397 09:31:22.513499
5398 09:31:22.513581 ==
5399 09:31:22.516438 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 09:31:22.520145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 09:31:22.520219 ==
5402 09:31:22.520282
5403 09:31:22.520345
5404 09:31:22.523304 TX Vref Scan disable
5405 09:31:22.523394 == TX Byte 0 ==
5406 09:31:22.529596 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5407 09:31:22.533157 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5408 09:31:22.533239 == TX Byte 1 ==
5409 09:31:22.539626 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5410 09:31:22.543324 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5411 09:31:22.543456 ==
5412 09:31:22.546332 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 09:31:22.549609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 09:31:22.549691 ==
5415 09:31:22.549756
5416 09:31:22.549815
5417 09:31:22.553074 TX Vref Scan disable
5418 09:31:22.556697 == TX Byte 0 ==
5419 09:31:22.560162 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5420 09:31:22.563087 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5421 09:31:22.566507 == TX Byte 1 ==
5422 09:31:22.569455 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5423 09:31:22.572852 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5424 09:31:22.572933
5425 09:31:22.576383 [DATLAT]
5426 09:31:22.576463 Freq=933, CH0 RK1
5427 09:31:22.576528
5428 09:31:22.579653 DATLAT Default: 0xb
5429 09:31:22.579758 0, 0xFFFF, sum = 0
5430 09:31:22.583307 1, 0xFFFF, sum = 0
5431 09:31:22.583406 2, 0xFFFF, sum = 0
5432 09:31:22.586044 3, 0xFFFF, sum = 0
5433 09:31:22.586126 4, 0xFFFF, sum = 0
5434 09:31:22.589982 5, 0xFFFF, sum = 0
5435 09:31:22.590065 6, 0xFFFF, sum = 0
5436 09:31:22.593224 7, 0xFFFF, sum = 0
5437 09:31:22.593307 8, 0xFFFF, sum = 0
5438 09:31:22.596454 9, 0xFFFF, sum = 0
5439 09:31:22.596537 10, 0x0, sum = 1
5440 09:31:22.599583 11, 0x0, sum = 2
5441 09:31:22.599665 12, 0x0, sum = 3
5442 09:31:22.602872 13, 0x0, sum = 4
5443 09:31:22.602955 best_step = 11
5444 09:31:22.603019
5445 09:31:22.603079 ==
5446 09:31:22.606359 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 09:31:22.612615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 09:31:22.612698 ==
5449 09:31:22.612763 RX Vref Scan: 0
5450 09:31:22.612822
5451 09:31:22.615768 RX Vref 0 -> 0, step: 1
5452 09:31:22.615850
5453 09:31:22.619131 RX Delay -77 -> 252, step: 4
5454 09:31:22.622606 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5455 09:31:22.626045 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5456 09:31:22.632877 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5457 09:31:22.636115 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5458 09:31:22.639271 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5459 09:31:22.642640 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5460 09:31:22.645933 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5461 09:31:22.652657 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5462 09:31:22.655769 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5463 09:31:22.659218 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5464 09:31:22.662669 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5465 09:31:22.665971 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5466 09:31:22.672324 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5467 09:31:22.676017 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5468 09:31:22.679351 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5469 09:31:22.682228 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5470 09:31:22.682309 ==
5471 09:31:22.685515 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 09:31:22.688943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 09:31:22.692068 ==
5474 09:31:22.692149 DQS Delay:
5475 09:31:22.692214 DQS0 = 0, DQS1 = 0
5476 09:31:22.695836 DQM Delay:
5477 09:31:22.695917 DQM0 = 93, DQM1 = 84
5478 09:31:22.698711 DQ Delay:
5479 09:31:22.698791 DQ0 =92, DQ1 =94, DQ2 =88, DQ3 =88
5480 09:31:22.702142 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5481 09:31:22.705736 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =76
5482 09:31:22.708944 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =92
5483 09:31:22.712272
5484 09:31:22.712352
5485 09:31:22.718536 [DQSOSCAuto] RK1, (LSB)MR18= 0x3113, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5486 09:31:22.722056 CH0 RK1: MR19=505, MR18=3113
5487 09:31:22.728779 CH0_RK1: MR19=0x505, MR18=0x3113, DQSOSC=406, MR23=63, INC=65, DEC=43
5488 09:31:22.732189 [RxdqsGatingPostProcess] freq 933
5489 09:31:22.735113 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5490 09:31:22.738680 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 09:31:22.741979 best DQS1 dly(2T, 0.5T) = (0, 11)
5492 09:31:22.744975 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 09:31:22.748684 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5494 09:31:22.751935 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 09:31:22.755524 best DQS1 dly(2T, 0.5T) = (0, 11)
5496 09:31:22.758794 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 09:31:22.761938 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5498 09:31:22.765147 Pre-setting of DQS Precalculation
5499 09:31:22.768214 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5500 09:31:22.768296 ==
5501 09:31:22.771629 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 09:31:22.778442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 09:31:22.778525 ==
5504 09:31:22.781416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 09:31:22.788364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5506 09:31:22.791331 [CA 0] Center 37 (7~67) winsize 61
5507 09:31:22.795293 [CA 1] Center 37 (7~67) winsize 61
5508 09:31:22.798378 [CA 2] Center 34 (5~64) winsize 60
5509 09:31:22.801647 [CA 3] Center 34 (4~64) winsize 61
5510 09:31:22.805001 [CA 4] Center 34 (5~64) winsize 60
5511 09:31:22.807943 [CA 5] Center 33 (4~63) winsize 60
5512 09:31:22.808024
5513 09:31:22.811943 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5514 09:31:22.812024
5515 09:31:22.815204 [CATrainingPosCal] consider 1 rank data
5516 09:31:22.818426 u2DelayCellTimex100 = 270/100 ps
5517 09:31:22.821835 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5518 09:31:22.824924 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5519 09:31:22.831367 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5520 09:31:22.834824 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 09:31:22.838015 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5522 09:31:22.841460 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5523 09:31:22.841542
5524 09:31:22.844761 CA PerBit enable=1, Macro0, CA PI delay=33
5525 09:31:22.844867
5526 09:31:22.847992 [CBTSetCACLKResult] CA Dly = 33
5527 09:31:22.848074 CS Dly: 5 (0~36)
5528 09:31:22.848139 ==
5529 09:31:22.851230 Dram Type= 6, Freq= 0, CH_1, rank 1
5530 09:31:22.858130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 09:31:22.858240 ==
5532 09:31:22.861479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5533 09:31:22.868007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5534 09:31:22.871596 [CA 0] Center 37 (7~67) winsize 61
5535 09:31:22.874714 [CA 1] Center 37 (7~68) winsize 62
5536 09:31:22.877666 [CA 2] Center 35 (5~65) winsize 61
5537 09:31:22.880965 [CA 3] Center 34 (4~64) winsize 61
5538 09:31:22.884495 [CA 4] Center 34 (4~65) winsize 62
5539 09:31:22.887907 [CA 5] Center 33 (3~64) winsize 62
5540 09:31:22.887987
5541 09:31:22.891496 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5542 09:31:22.891577
5543 09:31:22.894301 [CATrainingPosCal] consider 2 rank data
5544 09:31:22.897803 u2DelayCellTimex100 = 270/100 ps
5545 09:31:22.901173 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5546 09:31:22.907327 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5547 09:31:22.910838 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5548 09:31:22.914183 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5549 09:31:22.917690 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5550 09:31:22.921132 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5551 09:31:22.921253
5552 09:31:22.923968 CA PerBit enable=1, Macro0, CA PI delay=33
5553 09:31:22.924049
5554 09:31:22.927282 [CBTSetCACLKResult] CA Dly = 33
5555 09:31:22.927363 CS Dly: 6 (0~39)
5556 09:31:22.930934
5557 09:31:22.934312 ----->DramcWriteLeveling(PI) begin...
5558 09:31:22.934395 ==
5559 09:31:22.937250 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 09:31:22.940807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 09:31:22.940888 ==
5562 09:31:22.943907 Write leveling (Byte 0): 26 => 26
5563 09:31:22.947074 Write leveling (Byte 1): 28 => 28
5564 09:31:22.950415 DramcWriteLeveling(PI) end<-----
5565 09:31:22.950497
5566 09:31:22.950561 ==
5567 09:31:22.953779 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 09:31:22.956931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 09:31:22.957021 ==
5570 09:31:22.960658 [Gating] SW mode calibration
5571 09:31:22.967283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5572 09:31:22.973640 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5573 09:31:22.976909 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5574 09:31:22.980416 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 09:31:22.986670 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 09:31:22.990151 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 09:31:22.993163 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 09:31:22.999983 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 09:31:23.003374 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 09:31:23.006898 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
5581 09:31:23.013107 0 15 0 | B1->B0 | 2525 2626 | 0 0 | (1 0) (0 0)
5582 09:31:23.016539 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 09:31:23.019937 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 09:31:23.026624 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 09:31:23.029615 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 09:31:23.032941 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 09:31:23.039940 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 09:31:23.042756 0 15 28 | B1->B0 | 3131 3131 | 0 1 | (0 0) (0 0)
5589 09:31:23.046240 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5590 09:31:23.053036 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 09:31:23.056392 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 09:31:23.060000 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 09:31:23.066268 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 09:31:23.069527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 09:31:23.072602 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 09:31:23.079221 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5597 09:31:23.082691 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 09:31:23.086382 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 09:31:23.092651 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 09:31:23.095777 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 09:31:23.099083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 09:31:23.105878 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 09:31:23.108876 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 09:31:23.112401 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 09:31:23.118933 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 09:31:23.122157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 09:31:23.125497 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 09:31:23.132002 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 09:31:23.135280 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:31:23.138774 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:31:23.145415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:31:23.148595 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5613 09:31:23.152150 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 09:31:23.158398 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 09:31:23.158480 Total UI for P1: 0, mck2ui 16
5616 09:31:23.165403 best dqsien dly found for B0: ( 1, 2, 30)
5617 09:31:23.165486 Total UI for P1: 0, mck2ui 16
5618 09:31:23.168742 best dqsien dly found for B1: ( 1, 2, 30)
5619 09:31:23.175032 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5620 09:31:23.178613 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5621 09:31:23.178694
5622 09:31:23.181813 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5623 09:31:23.185092 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5624 09:31:23.188463 [Gating] SW calibration Done
5625 09:31:23.188544 ==
5626 09:31:23.192064 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 09:31:23.195314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 09:31:23.195411 ==
5629 09:31:23.198092 RX Vref Scan: 0
5630 09:31:23.198189
5631 09:31:23.198254 RX Vref 0 -> 0, step: 1
5632 09:31:23.198316
5633 09:31:23.201768 RX Delay -80 -> 252, step: 8
5634 09:31:23.205335 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5635 09:31:23.211309 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5636 09:31:23.214850 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5637 09:31:23.217944 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5638 09:31:23.221620 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5639 09:31:23.225166 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5640 09:31:23.227967 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5641 09:31:23.235273 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5642 09:31:23.238274 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5643 09:31:23.241511 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5644 09:31:23.245072 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5645 09:31:23.248279 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5646 09:31:23.254745 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5647 09:31:23.257924 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5648 09:31:23.261442 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5649 09:31:23.264332 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5650 09:31:23.264428 ==
5651 09:31:23.267879 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 09:31:23.274685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 09:31:23.274768 ==
5654 09:31:23.274833 DQS Delay:
5655 09:31:23.274892 DQS0 = 0, DQS1 = 0
5656 09:31:23.277513 DQM Delay:
5657 09:31:23.277595 DQM0 = 94, DQM1 = 86
5658 09:31:23.281097 DQ Delay:
5659 09:31:23.284181 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5660 09:31:23.287513 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5661 09:31:23.290883 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5662 09:31:23.294031 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5663 09:31:23.294113
5664 09:31:23.294177
5665 09:31:23.294260 ==
5666 09:31:23.297497 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 09:31:23.300910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 09:31:23.300993 ==
5669 09:31:23.301073
5670 09:31:23.301145
5671 09:31:23.304338 TX Vref Scan disable
5672 09:31:23.304419 == TX Byte 0 ==
5673 09:31:23.310871 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5674 09:31:23.314352 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5675 09:31:23.317547 == TX Byte 1 ==
5676 09:31:23.321038 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5677 09:31:23.323940 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5678 09:31:23.324039 ==
5679 09:31:23.327482 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 09:31:23.330482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 09:31:23.330580 ==
5682 09:31:23.330660
5683 09:31:23.334007
5684 09:31:23.334089 TX Vref Scan disable
5685 09:31:23.337313 == TX Byte 0 ==
5686 09:31:23.340734 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5687 09:31:23.346949 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5688 09:31:23.347082 == TX Byte 1 ==
5689 09:31:23.351203 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5690 09:31:23.357207 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5691 09:31:23.357294
5692 09:31:23.357359 [DATLAT]
5693 09:31:23.357418 Freq=933, CH1 RK0
5694 09:31:23.357477
5695 09:31:23.360545 DATLAT Default: 0xd
5696 09:31:23.360625 0, 0xFFFF, sum = 0
5697 09:31:23.363769 1, 0xFFFF, sum = 0
5698 09:31:23.363858 2, 0xFFFF, sum = 0
5699 09:31:23.366937 3, 0xFFFF, sum = 0
5700 09:31:23.370427 4, 0xFFFF, sum = 0
5701 09:31:23.370511 5, 0xFFFF, sum = 0
5702 09:31:23.373704 6, 0xFFFF, sum = 0
5703 09:31:23.373803 7, 0xFFFF, sum = 0
5704 09:31:23.377267 8, 0xFFFF, sum = 0
5705 09:31:23.377349 9, 0xFFFF, sum = 0
5706 09:31:23.380832 10, 0x0, sum = 1
5707 09:31:23.380915 11, 0x0, sum = 2
5708 09:31:23.383373 12, 0x0, sum = 3
5709 09:31:23.383490 13, 0x0, sum = 4
5710 09:31:23.383556 best_step = 11
5711 09:31:23.383616
5712 09:31:23.386881 ==
5713 09:31:23.390369 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 09:31:23.393622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 09:31:23.393703 ==
5716 09:31:23.393767 RX Vref Scan: 1
5717 09:31:23.393827
5718 09:31:23.397050 RX Vref 0 -> 0, step: 1
5719 09:31:23.397131
5720 09:31:23.400025 RX Delay -69 -> 252, step: 4
5721 09:31:23.400131
5722 09:31:23.403635 Set Vref, RX VrefLevel [Byte0]: 57
5723 09:31:23.406941 [Byte1]: 50
5724 09:31:23.407023
5725 09:31:23.410078 Final RX Vref Byte 0 = 57 to rank0
5726 09:31:23.413440 Final RX Vref Byte 1 = 50 to rank0
5727 09:31:23.417170 Final RX Vref Byte 0 = 57 to rank1
5728 09:31:23.419954 Final RX Vref Byte 1 = 50 to rank1==
5729 09:31:23.423053 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 09:31:23.426612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 09:31:23.429924 ==
5732 09:31:23.430013 DQS Delay:
5733 09:31:23.430115 DQS0 = 0, DQS1 = 0
5734 09:31:23.433110 DQM Delay:
5735 09:31:23.433190 DQM0 = 95, DQM1 = 88
5736 09:31:23.436678 DQ Delay:
5737 09:31:23.439952 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5738 09:31:23.443343 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5739 09:31:23.446860 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5740 09:31:23.450136 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5741 09:31:23.450218
5742 09:31:23.450282
5743 09:31:23.456415 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5744 09:31:23.459917 CH1 RK0: MR19=405, MR18=FF08
5745 09:31:23.466238 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5746 09:31:23.466346
5747 09:31:23.469807 ----->DramcWriteLeveling(PI) begin...
5748 09:31:23.469889 ==
5749 09:31:23.472811 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 09:31:23.476643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 09:31:23.476726 ==
5752 09:31:23.479560 Write leveling (Byte 0): 26 => 26
5753 09:31:23.482966 Write leveling (Byte 1): 25 => 25
5754 09:31:23.486438 DramcWriteLeveling(PI) end<-----
5755 09:31:23.486543
5756 09:31:23.486635 ==
5757 09:31:23.489915 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 09:31:23.492780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 09:31:23.492860 ==
5760 09:31:23.496269 [Gating] SW mode calibration
5761 09:31:23.502580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 09:31:23.509830 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 09:31:23.512857 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5764 09:31:23.519639 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 09:31:23.523064 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 09:31:23.526184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 09:31:23.532566 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 09:31:23.535912 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 09:31:23.539340 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5770 09:31:23.542671 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5771 09:31:23.549553 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 09:31:23.552823 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 09:31:23.555729 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 09:31:23.562362 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 09:31:23.565642 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 09:31:23.568975 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 09:31:23.575555 0 15 24 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
5778 09:31:23.578797 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5779 09:31:23.582213 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5780 09:31:23.588977 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 09:31:23.592609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 09:31:23.595291 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 09:31:23.602320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 09:31:23.605369 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 09:31:23.608813 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5786 09:31:23.615269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5787 09:31:23.618929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 09:31:23.622125 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 09:31:23.628726 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 09:31:23.632117 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 09:31:23.635178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 09:31:23.642478 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 09:31:23.645084 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 09:31:23.648516 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 09:31:23.655267 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 09:31:23.658621 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 09:31:23.662157 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 09:31:23.668263 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:31:23.671912 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:31:23.674928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:31:23.681644 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 09:31:23.685093 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 09:31:23.688547 Total UI for P1: 0, mck2ui 16
5804 09:31:23.691938 best dqsien dly found for B0: ( 1, 2, 26)
5805 09:31:23.694993 Total UI for P1: 0, mck2ui 16
5806 09:31:23.698239 best dqsien dly found for B1: ( 1, 2, 26)
5807 09:31:23.701512 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5808 09:31:23.704933 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5809 09:31:23.705015
5810 09:31:23.708493 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 09:31:23.711316 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5812 09:31:23.715300 [Gating] SW calibration Done
5813 09:31:23.715417 ==
5814 09:31:23.718051 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 09:31:23.721493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 09:31:23.725003 ==
5817 09:31:23.725084 RX Vref Scan: 0
5818 09:31:23.725150
5819 09:31:23.728161 RX Vref 0 -> 0, step: 1
5820 09:31:23.728254
5821 09:31:23.728332 RX Delay -80 -> 252, step: 8
5822 09:31:23.735057 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5823 09:31:23.738309 iDelay=208, Bit 1, Center 83 (-16 ~ 183) 200
5824 09:31:23.741724 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5825 09:31:23.745150 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5826 09:31:23.748281 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5827 09:31:23.755138 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5828 09:31:23.758486 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5829 09:31:23.761476 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5830 09:31:23.764845 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5831 09:31:23.768267 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5832 09:31:23.775022 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5833 09:31:23.778302 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5834 09:31:23.781602 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5835 09:31:23.785035 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5836 09:31:23.788359 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5837 09:31:23.791726 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5838 09:31:23.795227 ==
5839 09:31:23.795339 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 09:31:23.801234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 09:31:23.801318 ==
5842 09:31:23.801422 DQS Delay:
5843 09:31:23.804728 DQS0 = 0, DQS1 = 0
5844 09:31:23.804810 DQM Delay:
5845 09:31:23.807872 DQM0 = 91, DQM1 = 87
5846 09:31:23.807953 DQ Delay:
5847 09:31:23.811274 DQ0 =95, DQ1 =83, DQ2 =83, DQ3 =87
5848 09:31:23.814610 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5849 09:31:23.817917 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5850 09:31:23.821221 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5851 09:31:23.821303
5852 09:31:23.821368
5853 09:31:23.821427 ==
5854 09:31:23.824659 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 09:31:23.828145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 09:31:23.828226 ==
5857 09:31:23.828290
5858 09:31:23.828364
5859 09:31:23.831232 TX Vref Scan disable
5860 09:31:23.834561 == TX Byte 0 ==
5861 09:31:23.837843 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5862 09:31:23.841391 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5863 09:31:23.844353 == TX Byte 1 ==
5864 09:31:23.848013 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5865 09:31:23.850911 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5866 09:31:23.851010 ==
5867 09:31:23.854765 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 09:31:23.860934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 09:31:23.861018 ==
5870 09:31:23.861083
5871 09:31:23.861156
5872 09:31:23.861228 TX Vref Scan disable
5873 09:31:23.864988 == TX Byte 0 ==
5874 09:31:23.868253 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5875 09:31:23.874718 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5876 09:31:23.874800 == TX Byte 1 ==
5877 09:31:23.878085 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5878 09:31:23.884490 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5879 09:31:23.884589
5880 09:31:23.884668 [DATLAT]
5881 09:31:23.884728 Freq=933, CH1 RK1
5882 09:31:23.884787
5883 09:31:23.888060 DATLAT Default: 0xb
5884 09:31:23.891138 0, 0xFFFF, sum = 0
5885 09:31:23.891221 1, 0xFFFF, sum = 0
5886 09:31:23.894769 2, 0xFFFF, sum = 0
5887 09:31:23.894852 3, 0xFFFF, sum = 0
5888 09:31:23.898085 4, 0xFFFF, sum = 0
5889 09:31:23.898198 5, 0xFFFF, sum = 0
5890 09:31:23.901556 6, 0xFFFF, sum = 0
5891 09:31:23.901663 7, 0xFFFF, sum = 0
5892 09:31:23.904269 8, 0xFFFF, sum = 0
5893 09:31:23.904352 9, 0xFFFF, sum = 0
5894 09:31:23.907836 10, 0x0, sum = 1
5895 09:31:23.907919 11, 0x0, sum = 2
5896 09:31:23.911270 12, 0x0, sum = 3
5897 09:31:23.911353 13, 0x0, sum = 4
5898 09:31:23.914542 best_step = 11
5899 09:31:23.914692
5900 09:31:23.914758 ==
5901 09:31:23.917508 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 09:31:23.921018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 09:31:23.921100 ==
5904 09:31:23.921165 RX Vref Scan: 0
5905 09:31:23.921225
5906 09:31:23.924689 RX Vref 0 -> 0, step: 1
5907 09:31:23.924770
5908 09:31:23.927684 RX Delay -69 -> 252, step: 4
5909 09:31:23.934203 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5910 09:31:23.937622 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5911 09:31:23.941192 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5912 09:31:23.944369 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5913 09:31:23.947316 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5914 09:31:23.951106 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5915 09:31:23.957256 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5916 09:31:23.960827 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5917 09:31:23.963865 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5918 09:31:23.967478 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5919 09:31:23.970960 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5920 09:31:23.977528 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5921 09:31:23.980431 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5922 09:31:23.983751 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5923 09:31:23.987302 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5924 09:31:23.990970 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5925 09:31:23.991055 ==
5926 09:31:23.993768 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 09:31:24.000415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 09:31:24.000500 ==
5929 09:31:24.000584 DQS Delay:
5930 09:31:24.004315 DQS0 = 0, DQS1 = 0
5931 09:31:24.004425 DQM Delay:
5932 09:31:24.004509 DQM0 = 91, DQM1 = 90
5933 09:31:24.007254 DQ Delay:
5934 09:31:24.010629 DQ0 =94, DQ1 =86, DQ2 =80, DQ3 =88
5935 09:31:24.013418 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88
5936 09:31:24.016979 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
5937 09:31:24.020535 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5938 09:31:24.020639
5939 09:31:24.020739
5940 09:31:24.027119 [DQSOSCAuto] RK1, (LSB)MR18= 0x1326, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5941 09:31:24.030374 CH1 RK1: MR19=505, MR18=1326
5942 09:31:24.036816 CH1_RK1: MR19=0x505, MR18=0x1326, DQSOSC=409, MR23=63, INC=64, DEC=43
5943 09:31:24.040205 [RxdqsGatingPostProcess] freq 933
5944 09:31:24.046512 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5945 09:31:24.046596 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 09:31:24.050101 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 09:31:24.053351 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 09:31:24.056388 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 09:31:24.060215 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 09:31:24.063505 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 09:31:24.066532 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 09:31:24.069644 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 09:31:24.073269 Pre-setting of DQS Precalculation
5954 09:31:24.079780 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5955 09:31:24.086556 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5956 09:31:24.092796 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5957 09:31:24.092880
5958 09:31:24.092944
5959 09:31:24.096301 [Calibration Summary] 1866 Mbps
5960 09:31:24.096383 CH 0, Rank 0
5961 09:31:24.099584 SW Impedance : PASS
5962 09:31:24.102952 DUTY Scan : NO K
5963 09:31:24.103061 ZQ Calibration : PASS
5964 09:31:24.106468 Jitter Meter : NO K
5965 09:31:24.106549 CBT Training : PASS
5966 09:31:24.110007 Write leveling : PASS
5967 09:31:24.112796 RX DQS gating : PASS
5968 09:31:24.112880 RX DQ/DQS(RDDQC) : PASS
5969 09:31:24.116227 TX DQ/DQS : PASS
5970 09:31:24.119684 RX DATLAT : PASS
5971 09:31:24.119765 RX DQ/DQS(Engine): PASS
5972 09:31:24.122770 TX OE : NO K
5973 09:31:24.122858 All Pass.
5974 09:31:24.122945
5975 09:31:24.126098 CH 0, Rank 1
5976 09:31:24.126178 SW Impedance : PASS
5977 09:31:24.129405 DUTY Scan : NO K
5978 09:31:24.132770 ZQ Calibration : PASS
5979 09:31:24.132863 Jitter Meter : NO K
5980 09:31:24.135949 CBT Training : PASS
5981 09:31:24.139290 Write leveling : PASS
5982 09:31:24.139421 RX DQS gating : PASS
5983 09:31:24.142696 RX DQ/DQS(RDDQC) : PASS
5984 09:31:24.145994 TX DQ/DQS : PASS
5985 09:31:24.146075 RX DATLAT : PASS
5986 09:31:24.149417 RX DQ/DQS(Engine): PASS
5987 09:31:24.152262 TX OE : NO K
5988 09:31:24.152344 All Pass.
5989 09:31:24.152408
5990 09:31:24.152466 CH 1, Rank 0
5991 09:31:24.156116 SW Impedance : PASS
5992 09:31:24.159120 DUTY Scan : NO K
5993 09:31:24.159227 ZQ Calibration : PASS
5994 09:31:24.162373 Jitter Meter : NO K
5995 09:31:24.165380 CBT Training : PASS
5996 09:31:24.165459 Write leveling : PASS
5997 09:31:24.169160 RX DQS gating : PASS
5998 09:31:24.169241 RX DQ/DQS(RDDQC) : PASS
5999 09:31:24.172495 TX DQ/DQS : PASS
6000 09:31:24.175930 RX DATLAT : PASS
6001 09:31:24.176010 RX DQ/DQS(Engine): PASS
6002 09:31:24.178710 TX OE : NO K
6003 09:31:24.178790 All Pass.
6004 09:31:24.178855
6005 09:31:24.182167 CH 1, Rank 1
6006 09:31:24.182247 SW Impedance : PASS
6007 09:31:24.185337 DUTY Scan : NO K
6008 09:31:24.188788 ZQ Calibration : PASS
6009 09:31:24.188870 Jitter Meter : NO K
6010 09:31:24.192507 CBT Training : PASS
6011 09:31:24.195283 Write leveling : PASS
6012 09:31:24.195412 RX DQS gating : PASS
6013 09:31:24.198764 RX DQ/DQS(RDDQC) : PASS
6014 09:31:24.201759 TX DQ/DQS : PASS
6015 09:31:24.201839 RX DATLAT : PASS
6016 09:31:24.205213 RX DQ/DQS(Engine): PASS
6017 09:31:24.208593 TX OE : NO K
6018 09:31:24.208675 All Pass.
6019 09:31:24.208740
6020 09:31:24.212207 DramC Write-DBI off
6021 09:31:24.212293 PER_BANK_REFRESH: Hybrid Mode
6022 09:31:24.215023 TX_TRACKING: ON
6023 09:31:24.221906 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6024 09:31:24.228290 [FAST_K] Save calibration result to emmc
6025 09:31:24.231431 dramc_set_vcore_voltage set vcore to 650000
6026 09:31:24.231556 Read voltage for 400, 6
6027 09:31:24.234915 Vio18 = 0
6028 09:31:24.235017 Vcore = 650000
6029 09:31:24.235145 Vdram = 0
6030 09:31:24.238651 Vddq = 0
6031 09:31:24.238755 Vmddr = 0
6032 09:31:24.241461 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6033 09:31:24.248389 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6034 09:31:24.251844 MEM_TYPE=3, freq_sel=20
6035 09:31:24.255039 sv_algorithm_assistance_LP4_800
6036 09:31:24.258180 ============ PULL DRAM RESETB DOWN ============
6037 09:31:24.261406 ========== PULL DRAM RESETB DOWN end =========
6038 09:31:24.267971 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6039 09:31:24.271492 ===================================
6040 09:31:24.271575 LPDDR4 DRAM CONFIGURATION
6041 09:31:24.274887 ===================================
6042 09:31:24.278054 EX_ROW_EN[0] = 0x0
6043 09:31:24.278137 EX_ROW_EN[1] = 0x0
6044 09:31:24.281376 LP4Y_EN = 0x0
6045 09:31:24.281459 WORK_FSP = 0x0
6046 09:31:24.284997 WL = 0x2
6047 09:31:24.285096 RL = 0x2
6048 09:31:24.288336 BL = 0x2
6049 09:31:24.291111 RPST = 0x0
6050 09:31:24.291235 RD_PRE = 0x0
6051 09:31:24.294778 WR_PRE = 0x1
6052 09:31:24.294860 WR_PST = 0x0
6053 09:31:24.297582 DBI_WR = 0x0
6054 09:31:24.297664 DBI_RD = 0x0
6055 09:31:24.301174 OTF = 0x1
6056 09:31:24.304422 ===================================
6057 09:31:24.307691 ===================================
6058 09:31:24.307780 ANA top config
6059 09:31:24.311263 ===================================
6060 09:31:24.314211 DLL_ASYNC_EN = 0
6061 09:31:24.317617 ALL_SLAVE_EN = 1
6062 09:31:24.317708 NEW_RANK_MODE = 1
6063 09:31:24.321187 DLL_IDLE_MODE = 1
6064 09:31:24.324492 LP45_APHY_COMB_EN = 1
6065 09:31:24.327320 TX_ODT_DIS = 1
6066 09:31:24.330923 NEW_8X_MODE = 1
6067 09:31:24.334223 ===================================
6068 09:31:24.337051 ===================================
6069 09:31:24.337142 data_rate = 800
6070 09:31:24.340594 CKR = 1
6071 09:31:24.343861 DQ_P2S_RATIO = 4
6072 09:31:24.347233 ===================================
6073 09:31:24.350702 CA_P2S_RATIO = 4
6074 09:31:24.353707 DQ_CA_OPEN = 0
6075 09:31:24.357225 DQ_SEMI_OPEN = 1
6076 09:31:24.357324 CA_SEMI_OPEN = 1
6077 09:31:24.360945 CA_FULL_RATE = 0
6078 09:31:24.363735 DQ_CKDIV4_EN = 0
6079 09:31:24.367304 CA_CKDIV4_EN = 1
6080 09:31:24.370146 CA_PREDIV_EN = 0
6081 09:31:24.373545 PH8_DLY = 0
6082 09:31:24.373632 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6083 09:31:24.377164 DQ_AAMCK_DIV = 0
6084 09:31:24.380562 CA_AAMCK_DIV = 0
6085 09:31:24.383923 CA_ADMCK_DIV = 4
6086 09:31:24.386894 DQ_TRACK_CA_EN = 0
6087 09:31:24.390480 CA_PICK = 800
6088 09:31:24.393425 CA_MCKIO = 400
6089 09:31:24.393515 MCKIO_SEMI = 400
6090 09:31:24.396838 PLL_FREQ = 3016
6091 09:31:24.400330 DQ_UI_PI_RATIO = 32
6092 09:31:24.403682 CA_UI_PI_RATIO = 32
6093 09:31:24.406965 ===================================
6094 09:31:24.410113 ===================================
6095 09:31:24.413658 memory_type:LPDDR4
6096 09:31:24.413761 GP_NUM : 10
6097 09:31:24.416812 SRAM_EN : 1
6098 09:31:24.420248 MD32_EN : 0
6099 09:31:24.423306 ===================================
6100 09:31:24.423436 [ANA_INIT] >>>>>>>>>>>>>>
6101 09:31:24.426829 <<<<<< [CONFIGURE PHASE]: ANA_TX
6102 09:31:24.429776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6103 09:31:24.432930 ===================================
6104 09:31:24.436448 data_rate = 800,PCW = 0X7400
6105 09:31:24.440029 ===================================
6106 09:31:24.442953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6107 09:31:24.449509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 09:31:24.459359 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 09:31:24.465948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6110 09:31:24.469535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6111 09:31:24.473209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6112 09:31:24.473294 [ANA_INIT] flow start
6113 09:31:24.475995 [ANA_INIT] PLL >>>>>>>>
6114 09:31:24.479742 [ANA_INIT] PLL <<<<<<<<
6115 09:31:24.479830 [ANA_INIT] MIDPI >>>>>>>>
6116 09:31:24.482695 [ANA_INIT] MIDPI <<<<<<<<
6117 09:31:24.486190 [ANA_INIT] DLL >>>>>>>>
6118 09:31:24.486299 [ANA_INIT] flow end
6119 09:31:24.492747 ============ LP4 DIFF to SE enter ============
6120 09:31:24.496327 ============ LP4 DIFF to SE exit ============
6121 09:31:24.499304 [ANA_INIT] <<<<<<<<<<<<<
6122 09:31:24.502882 [Flow] Enable top DCM control >>>>>
6123 09:31:24.505853 [Flow] Enable top DCM control <<<<<
6124 09:31:24.505960 Enable DLL master slave shuffle
6125 09:31:24.512967 ==============================================================
6126 09:31:24.515721 Gating Mode config
6127 09:31:24.519482 ==============================================================
6128 09:31:24.522528 Config description:
6129 09:31:24.532458 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6130 09:31:24.539072 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6131 09:31:24.542549 SELPH_MODE 0: By rank 1: By Phase
6132 09:31:24.549253 ==============================================================
6133 09:31:24.552798 GAT_TRACK_EN = 0
6134 09:31:24.555923 RX_GATING_MODE = 2
6135 09:31:24.559306 RX_GATING_TRACK_MODE = 2
6136 09:31:24.562438 SELPH_MODE = 1
6137 09:31:24.565939 PICG_EARLY_EN = 1
6138 09:31:24.566022 VALID_LAT_VALUE = 1
6139 09:31:24.572237 ==============================================================
6140 09:31:24.575506 Enter into Gating configuration >>>>
6141 09:31:24.579193 Exit from Gating configuration <<<<
6142 09:31:24.582273 Enter into DVFS_PRE_config >>>>>
6143 09:31:24.592284 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6144 09:31:24.595624 Exit from DVFS_PRE_config <<<<<
6145 09:31:24.598499 Enter into PICG configuration >>>>
6146 09:31:24.602168 Exit from PICG configuration <<<<
6147 09:31:24.605571 [RX_INPUT] configuration >>>>>
6148 09:31:24.608436 [RX_INPUT] configuration <<<<<
6149 09:31:24.612143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6150 09:31:24.618566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6151 09:31:24.625160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 09:31:24.631811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 09:31:24.638336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 09:31:24.645257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 09:31:24.648357 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6156 09:31:24.651822 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6157 09:31:24.654962 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6158 09:31:24.661683 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6159 09:31:24.664975 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6160 09:31:24.668320 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 09:31:24.671881 ===================================
6162 09:31:24.674820 LPDDR4 DRAM CONFIGURATION
6163 09:31:24.678093 ===================================
6164 09:31:24.678202 EX_ROW_EN[0] = 0x0
6165 09:31:24.681350 EX_ROW_EN[1] = 0x0
6166 09:31:24.681494 LP4Y_EN = 0x0
6167 09:31:24.684940 WORK_FSP = 0x0
6168 09:31:24.687931 WL = 0x2
6169 09:31:24.688046 RL = 0x2
6170 09:31:24.691255 BL = 0x2
6171 09:31:24.691337 RPST = 0x0
6172 09:31:24.694841 RD_PRE = 0x0
6173 09:31:24.694923 WR_PRE = 0x1
6174 09:31:24.698004 WR_PST = 0x0
6175 09:31:24.698224 DBI_WR = 0x0
6176 09:31:24.701313 DBI_RD = 0x0
6177 09:31:24.701395 OTF = 0x1
6178 09:31:24.705015 ===================================
6179 09:31:24.708114 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6180 09:31:24.715047 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6181 09:31:24.718110 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 09:31:24.721590 ===================================
6183 09:31:24.724643 LPDDR4 DRAM CONFIGURATION
6184 09:31:24.728103 ===================================
6185 09:31:24.728211 EX_ROW_EN[0] = 0x10
6186 09:31:24.731158 EX_ROW_EN[1] = 0x0
6187 09:31:24.731241 LP4Y_EN = 0x0
6188 09:31:24.734605 WORK_FSP = 0x0
6189 09:31:24.734686 WL = 0x2
6190 09:31:24.737719 RL = 0x2
6191 09:31:24.741072 BL = 0x2
6192 09:31:24.741151 RPST = 0x0
6193 09:31:24.744333 RD_PRE = 0x0
6194 09:31:24.744434 WR_PRE = 0x1
6195 09:31:24.747829 WR_PST = 0x0
6196 09:31:24.747903 DBI_WR = 0x0
6197 09:31:24.751286 DBI_RD = 0x0
6198 09:31:24.751366 OTF = 0x1
6199 09:31:24.754561 ===================================
6200 09:31:24.760884 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6201 09:31:24.765125 nWR fixed to 30
6202 09:31:24.768474 [ModeRegInit_LP4] CH0 RK0
6203 09:31:24.768556 [ModeRegInit_LP4] CH0 RK1
6204 09:31:24.771778 [ModeRegInit_LP4] CH1 RK0
6205 09:31:24.774983 [ModeRegInit_LP4] CH1 RK1
6206 09:31:24.775061 match AC timing 19
6207 09:31:24.781629 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6208 09:31:24.785138 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6209 09:31:24.787934 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6210 09:31:24.795078 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6211 09:31:24.798032 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6212 09:31:24.798110 ==
6213 09:31:24.801271 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 09:31:24.804496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 09:31:24.804575 ==
6216 09:31:24.811357 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 09:31:24.817943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6218 09:31:24.821559 [CA 0] Center 36 (8~64) winsize 57
6219 09:31:24.824588 [CA 1] Center 36 (8~64) winsize 57
6220 09:31:24.828008 [CA 2] Center 36 (8~64) winsize 57
6221 09:31:24.831025 [CA 3] Center 36 (8~64) winsize 57
6222 09:31:24.831108 [CA 4] Center 36 (8~64) winsize 57
6223 09:31:24.834632 [CA 5] Center 36 (8~64) winsize 57
6224 09:31:24.834714
6225 09:31:24.841306 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6226 09:31:24.841390
6227 09:31:24.844842 [CATrainingPosCal] consider 1 rank data
6228 09:31:24.847953 u2DelayCellTimex100 = 270/100 ps
6229 09:31:24.851300 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 09:31:24.854584 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 09:31:24.857938 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 09:31:24.861421 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 09:31:24.864303 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 09:31:24.868010 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 09:31:24.868095
6236 09:31:24.870837 CA PerBit enable=1, Macro0, CA PI delay=36
6237 09:31:24.870919
6238 09:31:24.874519 [CBTSetCACLKResult] CA Dly = 36
6239 09:31:24.877921 CS Dly: 1 (0~32)
6240 09:31:24.878003 ==
6241 09:31:24.881218 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 09:31:24.884537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 09:31:24.884621 ==
6244 09:31:24.890856 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 09:31:24.897702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6246 09:31:24.897787 [CA 0] Center 36 (8~64) winsize 57
6247 09:31:24.900667 [CA 1] Center 36 (8~64) winsize 57
6248 09:31:24.904168 [CA 2] Center 36 (8~64) winsize 57
6249 09:31:24.907626 [CA 3] Center 36 (8~64) winsize 57
6250 09:31:24.910552 [CA 4] Center 36 (8~64) winsize 57
6251 09:31:24.913966 [CA 5] Center 36 (8~64) winsize 57
6252 09:31:24.914050
6253 09:31:24.917263 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6254 09:31:24.917350
6255 09:31:24.920538 [CATrainingPosCal] consider 2 rank data
6256 09:31:24.924067 u2DelayCellTimex100 = 270/100 ps
6257 09:31:24.927661 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 09:31:24.934068 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 09:31:24.937117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 09:31:24.940376 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:31:24.943909 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 09:31:24.946913 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 09:31:24.946996
6264 09:31:24.950423 CA PerBit enable=1, Macro0, CA PI delay=36
6265 09:31:24.950505
6266 09:31:24.953573 [CBTSetCACLKResult] CA Dly = 36
6267 09:31:24.957150 CS Dly: 1 (0~32)
6268 09:31:24.957232
6269 09:31:24.960037 ----->DramcWriteLeveling(PI) begin...
6270 09:31:24.960120 ==
6271 09:31:24.963610 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 09:31:24.967083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 09:31:24.967166 ==
6274 09:31:24.970443 Write leveling (Byte 0): 40 => 8
6275 09:31:24.973695 Write leveling (Byte 1): 40 => 8
6276 09:31:24.976791 DramcWriteLeveling(PI) end<-----
6277 09:31:24.976873
6278 09:31:24.976938 ==
6279 09:31:24.980152 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 09:31:24.983436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 09:31:24.983520 ==
6282 09:31:24.986776 [Gating] SW mode calibration
6283 09:31:24.993312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6284 09:31:25.000239 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6285 09:31:25.003195 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 09:31:25.006787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 09:31:25.013522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 09:31:25.016546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 09:31:25.020046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 09:31:25.026617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 09:31:25.029556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 09:31:25.032971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 09:31:25.039466 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 09:31:25.039551 Total UI for P1: 0, mck2ui 16
6295 09:31:25.046656 best dqsien dly found for B0: ( 0, 14, 24)
6296 09:31:25.046740 Total UI for P1: 0, mck2ui 16
6297 09:31:25.052918 best dqsien dly found for B1: ( 0, 14, 24)
6298 09:31:25.056490 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6299 09:31:25.059365 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6300 09:31:25.059473
6301 09:31:25.063084 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 09:31:25.065974 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 09:31:25.069482 [Gating] SW calibration Done
6304 09:31:25.069563 ==
6305 09:31:25.072763 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 09:31:25.075824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 09:31:25.075907 ==
6308 09:31:25.079316 RX Vref Scan: 0
6309 09:31:25.079452
6310 09:31:25.079519 RX Vref 0 -> 0, step: 1
6311 09:31:25.079582
6312 09:31:25.082951 RX Delay -410 -> 252, step: 16
6313 09:31:25.089395 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6314 09:31:25.092357 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6315 09:31:25.095745 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6316 09:31:25.099206 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6317 09:31:25.106145 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6318 09:31:25.109348 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6319 09:31:25.112820 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6320 09:31:25.116203 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6321 09:31:25.122654 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6322 09:31:25.126065 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6323 09:31:25.128948 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6324 09:31:25.132378 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6325 09:31:25.139357 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6326 09:31:25.143005 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6327 09:31:25.145828 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6328 09:31:25.149401 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6329 09:31:25.152403 ==
6330 09:31:25.152486 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 09:31:25.158936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 09:31:25.159019 ==
6333 09:31:25.159085 DQS Delay:
6334 09:31:25.162018 DQS0 = 59, DQS1 = 59
6335 09:31:25.162125 DQM Delay:
6336 09:31:25.165435 DQM0 = 18, DQM1 = 10
6337 09:31:25.165537 DQ Delay:
6338 09:31:25.168864 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6339 09:31:25.171966 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6340 09:31:25.175285 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6341 09:31:25.178994 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6342 09:31:25.179092
6343 09:31:25.179182
6344 09:31:25.179269 ==
6345 09:31:25.182224 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 09:31:25.185721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 09:31:25.185803 ==
6348 09:31:25.185869
6349 09:31:25.185928
6350 09:31:25.188542 TX Vref Scan disable
6351 09:31:25.188624 == TX Byte 0 ==
6352 09:31:25.195250 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 09:31:25.198542 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 09:31:25.198625 == TX Byte 1 ==
6355 09:31:25.205336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 09:31:25.208402 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 09:31:25.208485 ==
6358 09:31:25.211659 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 09:31:25.215053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 09:31:25.215163 ==
6361 09:31:25.215256
6362 09:31:25.215344
6363 09:31:25.218571 TX Vref Scan disable
6364 09:31:25.221639 == TX Byte 0 ==
6365 09:31:25.224780 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 09:31:25.228482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 09:31:25.231877 == TX Byte 1 ==
6368 09:31:25.234840 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 09:31:25.238318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 09:31:25.238400
6371 09:31:25.238464 [DATLAT]
6372 09:31:25.241433 Freq=400, CH0 RK0
6373 09:31:25.241510
6374 09:31:25.241573 DATLAT Default: 0xf
6375 09:31:25.244812 0, 0xFFFF, sum = 0
6376 09:31:25.244891 1, 0xFFFF, sum = 0
6377 09:31:25.248277 2, 0xFFFF, sum = 0
6378 09:31:25.248353 3, 0xFFFF, sum = 0
6379 09:31:25.251288 4, 0xFFFF, sum = 0
6380 09:31:25.254889 5, 0xFFFF, sum = 0
6381 09:31:25.254966 6, 0xFFFF, sum = 0
6382 09:31:25.257962 7, 0xFFFF, sum = 0
6383 09:31:25.258035 8, 0xFFFF, sum = 0
6384 09:31:25.261476 9, 0xFFFF, sum = 0
6385 09:31:25.261549 10, 0xFFFF, sum = 0
6386 09:31:25.264411 11, 0xFFFF, sum = 0
6387 09:31:25.264485 12, 0xFFFF, sum = 0
6388 09:31:25.267840 13, 0x0, sum = 1
6389 09:31:25.267939 14, 0x0, sum = 2
6390 09:31:25.271644 15, 0x0, sum = 3
6391 09:31:25.271742 16, 0x0, sum = 4
6392 09:31:25.274483 best_step = 14
6393 09:31:25.274575
6394 09:31:25.274640 ==
6395 09:31:25.277770 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 09:31:25.281298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 09:31:25.281403 ==
6398 09:31:25.284199 RX Vref Scan: 1
6399 09:31:25.284301
6400 09:31:25.284391 RX Vref 0 -> 0, step: 1
6401 09:31:25.284476
6402 09:31:25.287821 RX Delay -359 -> 252, step: 8
6403 09:31:25.287897
6404 09:31:25.290699 Set Vref, RX VrefLevel [Byte0]: 61
6405 09:31:25.294274 [Byte1]: 53
6406 09:31:25.299018
6407 09:31:25.299099 Final RX Vref Byte 0 = 61 to rank0
6408 09:31:25.301849 Final RX Vref Byte 1 = 53 to rank0
6409 09:31:25.305282 Final RX Vref Byte 0 = 61 to rank1
6410 09:31:25.308660 Final RX Vref Byte 1 = 53 to rank1==
6411 09:31:25.311901 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 09:31:25.318865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 09:31:25.318976 ==
6414 09:31:25.319094 DQS Delay:
6415 09:31:25.322281 DQS0 = 60, DQS1 = 68
6416 09:31:25.322356 DQM Delay:
6417 09:31:25.322435 DQM0 = 14, DQM1 = 13
6418 09:31:25.325137 DQ Delay:
6419 09:31:25.328357 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6420 09:31:25.332231 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6421 09:31:25.332318 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6422 09:31:25.335391 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6423 09:31:25.338793
6424 09:31:25.338915
6425 09:31:25.345223 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6426 09:31:25.348519 CH0 RK0: MR19=C0C, MR18=7E7D
6427 09:31:25.355139 CH0_RK0: MR19=0xC0C, MR18=0x7E7D, DQSOSC=393, MR23=63, INC=382, DEC=254
6428 09:31:25.355282 ==
6429 09:31:25.358200 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 09:31:25.361678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 09:31:25.361783 ==
6432 09:31:25.365270 [Gating] SW mode calibration
6433 09:31:25.371752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6434 09:31:25.378259 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6435 09:31:25.381605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 09:31:25.384754 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 09:31:25.391610 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 09:31:25.395045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 09:31:25.398061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 09:31:25.404992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 09:31:25.408393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 09:31:25.411281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 09:31:25.418076 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 09:31:25.418174 Total UI for P1: 0, mck2ui 16
6445 09:31:25.421474 best dqsien dly found for B0: ( 0, 14, 24)
6446 09:31:25.425032 Total UI for P1: 0, mck2ui 16
6447 09:31:25.427834 best dqsien dly found for B1: ( 0, 14, 24)
6448 09:31:25.434824 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6449 09:31:25.438238 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6450 09:31:25.438329
6451 09:31:25.441645 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 09:31:25.444453 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 09:31:25.447840 [Gating] SW calibration Done
6454 09:31:25.447931 ==
6455 09:31:25.451287 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 09:31:25.454824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 09:31:25.454914 ==
6458 09:31:25.458129 RX Vref Scan: 0
6459 09:31:25.458216
6460 09:31:25.458282 RX Vref 0 -> 0, step: 1
6461 09:31:25.458343
6462 09:31:25.460973 RX Delay -410 -> 252, step: 16
6463 09:31:25.468061 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6464 09:31:25.470950 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6465 09:31:25.474473 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6466 09:31:25.477523 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6467 09:31:25.484181 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6468 09:31:25.487773 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6469 09:31:25.491191 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6470 09:31:25.494533 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6471 09:31:25.500947 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6472 09:31:25.504195 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6473 09:31:25.507731 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6474 09:31:25.510850 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6475 09:31:25.517358 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6476 09:31:25.520922 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6477 09:31:25.524176 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6478 09:31:25.527555 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6479 09:31:25.530948 ==
6480 09:31:25.531038 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 09:31:25.537237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 09:31:25.537334 ==
6483 09:31:25.537403 DQS Delay:
6484 09:31:25.540728 DQS0 = 59, DQS1 = 59
6485 09:31:25.540813 DQM Delay:
6486 09:31:25.543803 DQM0 = 16, DQM1 = 10
6487 09:31:25.543887 DQ Delay:
6488 09:31:25.547106 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6489 09:31:25.550505 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6490 09:31:25.553906 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6491 09:31:25.557585 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6492 09:31:25.557678
6493 09:31:25.557746
6494 09:31:25.557806 ==
6495 09:31:25.560526 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 09:31:25.564060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 09:31:25.564147 ==
6498 09:31:25.564214
6499 09:31:25.564275
6500 09:31:25.567509 TX Vref Scan disable
6501 09:31:25.567679 == TX Byte 0 ==
6502 09:31:25.573975 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6503 09:31:25.577038 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6504 09:31:25.577128 == TX Byte 1 ==
6505 09:31:25.583573 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6506 09:31:25.587130 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6507 09:31:25.587246 ==
6508 09:31:25.590116 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 09:31:25.593656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 09:31:25.593742 ==
6511 09:31:25.593809
6512 09:31:25.593869
6513 09:31:25.597385 TX Vref Scan disable
6514 09:31:25.597470 == TX Byte 0 ==
6515 09:31:25.603571 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6516 09:31:25.607010 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6517 09:31:25.607107 == TX Byte 1 ==
6518 09:31:25.613769 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6519 09:31:25.616838 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6520 09:31:25.616930
6521 09:31:25.616996 [DATLAT]
6522 09:31:25.620413 Freq=400, CH0 RK1
6523 09:31:25.620509
6524 09:31:25.620575 DATLAT Default: 0xe
6525 09:31:25.623317 0, 0xFFFF, sum = 0
6526 09:31:25.623459 1, 0xFFFF, sum = 0
6527 09:31:25.627081 2, 0xFFFF, sum = 0
6528 09:31:25.627172 3, 0xFFFF, sum = 0
6529 09:31:25.630217 4, 0xFFFF, sum = 0
6530 09:31:25.630314 5, 0xFFFF, sum = 0
6531 09:31:25.633538 6, 0xFFFF, sum = 0
6532 09:31:25.633632 7, 0xFFFF, sum = 0
6533 09:31:25.636680 8, 0xFFFF, sum = 0
6534 09:31:25.636773 9, 0xFFFF, sum = 0
6535 09:31:25.640144 10, 0xFFFF, sum = 0
6536 09:31:25.643427 11, 0xFFFF, sum = 0
6537 09:31:25.643525 12, 0xFFFF, sum = 0
6538 09:31:25.647045 13, 0x0, sum = 1
6539 09:31:25.647139 14, 0x0, sum = 2
6540 09:31:25.649898 15, 0x0, sum = 3
6541 09:31:25.649989 16, 0x0, sum = 4
6542 09:31:25.650077 best_step = 14
6543 09:31:25.650157
6544 09:31:25.653371 ==
6545 09:31:25.656802 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 09:31:25.659632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 09:31:25.659758 ==
6548 09:31:25.659832 RX Vref Scan: 0
6549 09:31:25.659893
6550 09:31:25.663620 RX Vref 0 -> 0, step: 1
6551 09:31:25.663719
6552 09:31:25.666485 RX Delay -359 -> 252, step: 8
6553 09:31:25.673273 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6554 09:31:25.677033 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6555 09:31:25.680099 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6556 09:31:25.686472 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6557 09:31:25.690087 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6558 09:31:25.693586 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6559 09:31:25.696583 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6560 09:31:25.700135 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6561 09:31:25.706653 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6562 09:31:25.709892 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6563 09:31:25.713449 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6564 09:31:25.716866 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6565 09:31:25.723369 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6566 09:31:25.726939 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6567 09:31:25.730150 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6568 09:31:25.736698 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6569 09:31:25.736806 ==
6570 09:31:25.740088 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 09:31:25.743201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 09:31:25.743293 ==
6573 09:31:25.743359 DQS Delay:
6574 09:31:25.746751 DQS0 = 60, DQS1 = 72
6575 09:31:25.746839 DQM Delay:
6576 09:31:25.749966 DQM0 = 11, DQM1 = 17
6577 09:31:25.750056 DQ Delay:
6578 09:31:25.753364 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6579 09:31:25.756518 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6580 09:31:25.760079 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6581 09:31:25.763105 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6582 09:31:25.763200
6583 09:31:25.763268
6584 09:31:25.769838 [DQSOSCAuto] RK1, (LSB)MR18= 0xc478, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6585 09:31:25.772718 CH0 RK1: MR19=C0C, MR18=C478
6586 09:31:25.779723 CH0_RK1: MR19=0xC0C, MR18=0xC478, DQSOSC=385, MR23=63, INC=398, DEC=265
6587 09:31:25.782964 [RxdqsGatingPostProcess] freq 400
6588 09:31:25.790003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6589 09:31:25.792838 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 09:31:25.792934 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 09:31:25.796007 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 09:31:25.799574 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 09:31:25.803190 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 09:31:25.806189 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 09:31:25.809169 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 09:31:25.812980 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 09:31:25.815814 Pre-setting of DQS Precalculation
6598 09:31:25.822798 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6599 09:31:25.822914 ==
6600 09:31:25.825823 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 09:31:25.829311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 09:31:25.829409 ==
6603 09:31:25.835901 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 09:31:25.842401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6605 09:31:25.842515 [CA 0] Center 36 (8~64) winsize 57
6606 09:31:25.845937 [CA 1] Center 36 (8~64) winsize 57
6607 09:31:25.848654 [CA 2] Center 36 (8~64) winsize 57
6608 09:31:25.851923 [CA 3] Center 36 (8~64) winsize 57
6609 09:31:25.855342 [CA 4] Center 36 (8~64) winsize 57
6610 09:31:25.859222 [CA 5] Center 36 (8~64) winsize 57
6611 09:31:25.859353
6612 09:31:25.862334 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6613 09:31:25.862422
6614 09:31:25.865305 [CATrainingPosCal] consider 1 rank data
6615 09:31:25.868897 u2DelayCellTimex100 = 270/100 ps
6616 09:31:25.872107 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 09:31:25.878877 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 09:31:25.882169 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 09:31:25.885222 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 09:31:25.888584 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 09:31:25.892133 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 09:31:25.892231
6623 09:31:25.895346 CA PerBit enable=1, Macro0, CA PI delay=36
6624 09:31:25.895477
6625 09:31:25.898538 [CBTSetCACLKResult] CA Dly = 36
6626 09:31:25.898630 CS Dly: 1 (0~32)
6627 09:31:25.902068 ==
6628 09:31:25.905699 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 09:31:25.908623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 09:31:25.908724 ==
6631 09:31:25.912141 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 09:31:25.918371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6633 09:31:25.922026 [CA 0] Center 36 (8~64) winsize 57
6634 09:31:25.925051 [CA 1] Center 36 (8~64) winsize 57
6635 09:31:25.928466 [CA 2] Center 36 (8~64) winsize 57
6636 09:31:25.931978 [CA 3] Center 36 (8~64) winsize 57
6637 09:31:25.935670 [CA 4] Center 36 (8~64) winsize 57
6638 09:31:25.938627 [CA 5] Center 36 (8~64) winsize 57
6639 09:31:25.938723
6640 09:31:25.942134 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6641 09:31:25.942225
6642 09:31:25.945026 [CATrainingPosCal] consider 2 rank data
6643 09:31:25.948563 u2DelayCellTimex100 = 270/100 ps
6644 09:31:25.952031 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 09:31:25.955487 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 09:31:25.958283 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 09:31:25.961594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:31:25.968310 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 09:31:25.971584 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 09:31:25.971681
6651 09:31:25.975077 CA PerBit enable=1, Macro0, CA PI delay=36
6652 09:31:25.975169
6653 09:31:25.978169 [CBTSetCACLKResult] CA Dly = 36
6654 09:31:25.978256 CS Dly: 1 (0~32)
6655 09:31:25.978322
6656 09:31:25.981446 ----->DramcWriteLeveling(PI) begin...
6657 09:31:25.981534 ==
6658 09:31:25.984894 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 09:31:25.991425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 09:31:25.991551 ==
6661 09:31:25.994873 Write leveling (Byte 0): 40 => 8
6662 09:31:25.994963 Write leveling (Byte 1): 40 => 8
6663 09:31:25.998513 DramcWriteLeveling(PI) end<-----
6664 09:31:25.998602
6665 09:31:25.998669 ==
6666 09:31:26.001536 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 09:31:26.008176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 09:31:26.008296 ==
6669 09:31:26.011691 [Gating] SW mode calibration
6670 09:31:26.018203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6671 09:31:26.021807 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6672 09:31:26.028317 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 09:31:26.031689 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 09:31:26.034708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 09:31:26.041545 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 09:31:26.045067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 09:31:26.047799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 09:31:26.054719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 09:31:26.058158 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 09:31:26.061256 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 09:31:26.064666 Total UI for P1: 0, mck2ui 16
6682 09:31:26.067935 best dqsien dly found for B0: ( 0, 14, 24)
6683 09:31:26.070946 Total UI for P1: 0, mck2ui 16
6684 09:31:26.074400 best dqsien dly found for B1: ( 0, 14, 24)
6685 09:31:26.077918 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6686 09:31:26.080878 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6687 09:31:26.080970
6688 09:31:26.087786 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 09:31:26.091142 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 09:31:26.091241 [Gating] SW calibration Done
6691 09:31:26.094108 ==
6692 09:31:26.097654 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 09:31:26.101287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 09:31:26.101385 ==
6695 09:31:26.101452 RX Vref Scan: 0
6696 09:31:26.101514
6697 09:31:26.104110 RX Vref 0 -> 0, step: 1
6698 09:31:26.104198
6699 09:31:26.107228 RX Delay -410 -> 252, step: 16
6700 09:31:26.110819 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6701 09:31:26.114086 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6702 09:31:26.120905 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6703 09:31:26.123915 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6704 09:31:26.127630 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6705 09:31:26.130607 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6706 09:31:26.137213 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6707 09:31:26.140468 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6708 09:31:26.144078 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6709 09:31:26.150671 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6710 09:31:26.153604 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6711 09:31:26.157073 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6712 09:31:26.160362 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6713 09:31:26.166979 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6714 09:31:26.170560 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6715 09:31:26.173936 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6716 09:31:26.174035 ==
6717 09:31:26.176923 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 09:31:26.180367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 09:31:26.183275 ==
6720 09:31:26.183361 DQS Delay:
6721 09:31:26.183468 DQS0 = 51, DQS1 = 67
6722 09:31:26.186766 DQM Delay:
6723 09:31:26.186853 DQM0 = 13, DQM1 = 19
6724 09:31:26.190325 DQ Delay:
6725 09:31:26.190416 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6726 09:31:26.193760 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6727 09:31:26.196572 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6728 09:31:26.200287 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6729 09:31:26.200385
6730 09:31:26.200450
6731 09:31:26.203683 ==
6732 09:31:26.203771 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 09:31:26.210442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 09:31:26.210577 ==
6735 09:31:26.210688
6736 09:31:26.210750
6737 09:31:26.213533 TX Vref Scan disable
6738 09:31:26.213618 == TX Byte 0 ==
6739 09:31:26.216668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 09:31:26.223363 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 09:31:26.223507 == TX Byte 1 ==
6742 09:31:26.226569 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 09:31:26.233405 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 09:31:26.233529 ==
6745 09:31:26.236421 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 09:31:26.239717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 09:31:26.239812 ==
6748 09:31:26.239879
6749 09:31:26.239939
6750 09:31:26.243400 TX Vref Scan disable
6751 09:31:26.243506 == TX Byte 0 ==
6752 09:31:26.246670 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 09:31:26.253109 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 09:31:26.253220 == TX Byte 1 ==
6755 09:31:26.256615 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 09:31:26.263353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 09:31:26.263490
6758 09:31:26.263559 [DATLAT]
6759 09:31:26.263619 Freq=400, CH1 RK0
6760 09:31:26.263678
6761 09:31:26.266354 DATLAT Default: 0xf
6762 09:31:26.269801 0, 0xFFFF, sum = 0
6763 09:31:26.269894 1, 0xFFFF, sum = 0
6764 09:31:26.272796 2, 0xFFFF, sum = 0
6765 09:31:26.272897 3, 0xFFFF, sum = 0
6766 09:31:26.276360 4, 0xFFFF, sum = 0
6767 09:31:26.276443 5, 0xFFFF, sum = 0
6768 09:31:26.279705 6, 0xFFFF, sum = 0
6769 09:31:26.279807 7, 0xFFFF, sum = 0
6770 09:31:26.283270 8, 0xFFFF, sum = 0
6771 09:31:26.283359 9, 0xFFFF, sum = 0
6772 09:31:26.286131 10, 0xFFFF, sum = 0
6773 09:31:26.286219 11, 0xFFFF, sum = 0
6774 09:31:26.289551 12, 0xFFFF, sum = 0
6775 09:31:26.289658 13, 0x0, sum = 1
6776 09:31:26.293234 14, 0x0, sum = 2
6777 09:31:26.293324 15, 0x0, sum = 3
6778 09:31:26.296110 16, 0x0, sum = 4
6779 09:31:26.296198 best_step = 14
6780 09:31:26.296264
6781 09:31:26.296325 ==
6782 09:31:26.299375 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 09:31:26.305977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 09:31:26.306088 ==
6785 09:31:26.306158 RX Vref Scan: 1
6786 09:31:26.306219
6787 09:31:26.309396 RX Vref 0 -> 0, step: 1
6788 09:31:26.309487
6789 09:31:26.313118 RX Delay -375 -> 252, step: 8
6790 09:31:26.313208
6791 09:31:26.316098 Set Vref, RX VrefLevel [Byte0]: 57
6792 09:31:26.319090 [Byte1]: 50
6793 09:31:26.319178
6794 09:31:26.322599 Final RX Vref Byte 0 = 57 to rank0
6795 09:31:26.325872 Final RX Vref Byte 1 = 50 to rank0
6796 09:31:26.329232 Final RX Vref Byte 0 = 57 to rank1
6797 09:31:26.332387 Final RX Vref Byte 1 = 50 to rank1==
6798 09:31:26.335972 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 09:31:26.339157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 09:31:26.342485 ==
6801 09:31:26.342587 DQS Delay:
6802 09:31:26.342674 DQS0 = 52, DQS1 = 64
6803 09:31:26.346040 DQM Delay:
6804 09:31:26.346128 DQM0 = 9, DQM1 = 10
6805 09:31:26.349300 DQ Delay:
6806 09:31:26.349392 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6807 09:31:26.352612 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6808 09:31:26.355696 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6809 09:31:26.359135 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6810 09:31:26.359228
6811 09:31:26.359328
6812 09:31:26.369265 [DQSOSCAuto] RK0, (LSB)MR18= 0x586d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6813 09:31:26.372472 CH1 RK0: MR19=C0C, MR18=586D
6814 09:31:26.375928 CH1_RK0: MR19=0xC0C, MR18=0x586D, DQSOSC=396, MR23=63, INC=376, DEC=251
6815 09:31:26.379364 ==
6816 09:31:26.379490 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 09:31:26.385534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 09:31:26.385650 ==
6819 09:31:26.389454 [Gating] SW mode calibration
6820 09:31:26.395628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6821 09:31:26.399218 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6822 09:31:26.405654 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 09:31:26.409104 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 09:31:26.412202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 09:31:26.418615 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 09:31:26.422225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 09:31:26.425355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 09:31:26.431916 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 09:31:26.435289 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 09:31:26.438696 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 09:31:26.442004 Total UI for P1: 0, mck2ui 16
6832 09:31:26.445158 best dqsien dly found for B0: ( 0, 14, 24)
6833 09:31:26.448928 Total UI for P1: 0, mck2ui 16
6834 09:31:26.452375 best dqsien dly found for B1: ( 0, 14, 24)
6835 09:31:26.455592 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6836 09:31:26.459072 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6837 09:31:26.459169
6838 09:31:26.465345 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 09:31:26.469080 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 09:31:26.469184 [Gating] SW calibration Done
6841 09:31:26.472069 ==
6842 09:31:26.475593 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 09:31:26.478531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 09:31:26.478629 ==
6845 09:31:26.478718 RX Vref Scan: 0
6846 09:31:26.478800
6847 09:31:26.481933 RX Vref 0 -> 0, step: 1
6848 09:31:26.482016
6849 09:31:26.485213 RX Delay -410 -> 252, step: 16
6850 09:31:26.488788 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6851 09:31:26.491917 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6852 09:31:26.498817 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6853 09:31:26.501715 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6854 09:31:26.505104 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6855 09:31:26.508222 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6856 09:31:26.515261 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6857 09:31:26.518231 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6858 09:31:26.521778 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6859 09:31:26.524730 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6860 09:31:26.531899 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6861 09:31:26.534780 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6862 09:31:26.538296 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6863 09:31:26.544931 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6864 09:31:26.548432 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6865 09:31:26.551772 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6866 09:31:26.551870 ==
6867 09:31:26.554910 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 09:31:26.558444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 09:31:26.561663 ==
6870 09:31:26.561762 DQS Delay:
6871 09:31:26.561829 DQS0 = 59, DQS1 = 59
6872 09:31:26.564820 DQM Delay:
6873 09:31:26.564907 DQM0 = 19, DQM1 = 13
6874 09:31:26.567903 DQ Delay:
6875 09:31:26.567997 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6876 09:31:26.571210 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6877 09:31:26.574875 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6878 09:31:26.578368 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6879 09:31:26.578494
6880 09:31:26.578587
6881 09:31:26.581132 ==
6882 09:31:26.584872 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 09:31:26.587759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 09:31:26.587853 ==
6885 09:31:26.587919
6886 09:31:26.587979
6887 09:31:26.591318 TX Vref Scan disable
6888 09:31:26.591439 == TX Byte 0 ==
6889 09:31:26.594366 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6890 09:31:26.601544 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6891 09:31:26.601665 == TX Byte 1 ==
6892 09:31:26.604784 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6893 09:31:26.608110 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6894 09:31:26.611525 ==
6895 09:31:26.615001 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 09:31:26.617916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 09:31:26.618008 ==
6898 09:31:26.618076
6899 09:31:26.618136
6900 09:31:26.620985 TX Vref Scan disable
6901 09:31:26.621070 == TX Byte 0 ==
6902 09:31:26.624667 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6903 09:31:26.631371 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6904 09:31:26.631519 == TX Byte 1 ==
6905 09:31:26.634349 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6906 09:31:26.641428 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6907 09:31:26.641538
6908 09:31:26.641604 [DATLAT]
6909 09:31:26.641665 Freq=400, CH1 RK1
6910 09:31:26.641724
6911 09:31:26.644493 DATLAT Default: 0xe
6912 09:31:26.644578 0, 0xFFFF, sum = 0
6913 09:31:26.647874 1, 0xFFFF, sum = 0
6914 09:31:26.647961 2, 0xFFFF, sum = 0
6915 09:31:26.651342 3, 0xFFFF, sum = 0
6916 09:31:26.654253 4, 0xFFFF, sum = 0
6917 09:31:26.654344 5, 0xFFFF, sum = 0
6918 09:31:26.657876 6, 0xFFFF, sum = 0
6919 09:31:26.657966 7, 0xFFFF, sum = 0
6920 09:31:26.661377 8, 0xFFFF, sum = 0
6921 09:31:26.661466 9, 0xFFFF, sum = 0
6922 09:31:26.664012 10, 0xFFFF, sum = 0
6923 09:31:26.664098 11, 0xFFFF, sum = 0
6924 09:31:26.667835 12, 0xFFFF, sum = 0
6925 09:31:26.667945 13, 0x0, sum = 1
6926 09:31:26.670694 14, 0x0, sum = 2
6927 09:31:26.670780 15, 0x0, sum = 3
6928 09:31:26.674503 16, 0x0, sum = 4
6929 09:31:26.674590 best_step = 14
6930 09:31:26.674656
6931 09:31:26.674717 ==
6932 09:31:26.677596 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 09:31:26.681080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 09:31:26.684602 ==
6935 09:31:26.684699 RX Vref Scan: 0
6936 09:31:26.684765
6937 09:31:26.687509 RX Vref 0 -> 0, step: 1
6938 09:31:26.687594
6939 09:31:26.687660 RX Delay -359 -> 252, step: 8
6940 09:31:26.696775 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6941 09:31:26.699977 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6942 09:31:26.702911 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6943 09:31:26.709951 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6944 09:31:26.712881 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6945 09:31:26.716440 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6946 09:31:26.720013 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6947 09:31:26.726293 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6948 09:31:26.729652 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6949 09:31:26.733361 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
6950 09:31:26.736237 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6951 09:31:26.742891 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6952 09:31:26.746216 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6953 09:31:26.749532 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6954 09:31:26.753046 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6955 09:31:26.759526 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6956 09:31:26.759699 ==
6957 09:31:26.763096 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 09:31:26.766113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 09:31:26.766212 ==
6960 09:31:26.766281 DQS Delay:
6961 09:31:26.769446 DQS0 = 60, DQS1 = 64
6962 09:31:26.769535 DQM Delay:
6963 09:31:26.772668 DQM0 = 13, DQM1 = 11
6964 09:31:26.772760 DQ Delay:
6965 09:31:26.776021 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6966 09:31:26.779544 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6967 09:31:26.783050 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6968 09:31:26.786397 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6969 09:31:26.786493
6970 09:31:26.786560
6971 09:31:26.792972 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6972 09:31:26.796051 CH1 RK1: MR19=C0C, MR18=7DAD
6973 09:31:26.802930 CH1_RK1: MR19=0xC0C, MR18=0x7DAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6974 09:31:26.806402 [RxdqsGatingPostProcess] freq 400
6975 09:31:26.812944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6976 09:31:26.815829 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 09:31:26.815932 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 09:31:26.819467 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 09:31:26.823084 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 09:31:26.825858 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 09:31:26.829295 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 09:31:26.832513 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 09:31:26.836247 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 09:31:26.839203 Pre-setting of DQS Precalculation
6985 09:31:26.845552 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6986 09:31:26.852766 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6987 09:31:26.858880 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6988 09:31:26.858999
6989 09:31:26.859067
6990 09:31:26.862191 [Calibration Summary] 800 Mbps
6991 09:31:26.862280 CH 0, Rank 0
6992 09:31:26.865511 SW Impedance : PASS
6993 09:31:26.868941 DUTY Scan : NO K
6994 09:31:26.869040 ZQ Calibration : PASS
6995 09:31:26.872104 Jitter Meter : NO K
6996 09:31:26.875725 CBT Training : PASS
6997 09:31:26.875850 Write leveling : PASS
6998 09:31:26.879015 RX DQS gating : PASS
6999 09:31:26.882208 RX DQ/DQS(RDDQC) : PASS
7000 09:31:26.882308 TX DQ/DQS : PASS
7001 09:31:26.885198 RX DATLAT : PASS
7002 09:31:26.885289 RX DQ/DQS(Engine): PASS
7003 09:31:26.888722 TX OE : NO K
7004 09:31:26.888816 All Pass.
7005 09:31:26.888903
7006 09:31:26.892086 CH 0, Rank 1
7007 09:31:26.892178 SW Impedance : PASS
7008 09:31:26.895640 DUTY Scan : NO K
7009 09:31:26.898417 ZQ Calibration : PASS
7010 09:31:26.898512 Jitter Meter : NO K
7011 09:31:26.901721 CBT Training : PASS
7012 09:31:26.904899 Write leveling : NO K
7013 09:31:26.904995 RX DQS gating : PASS
7014 09:31:26.908414 RX DQ/DQS(RDDQC) : PASS
7015 09:31:26.911880 TX DQ/DQS : PASS
7016 09:31:26.911987 RX DATLAT : PASS
7017 09:31:26.914953 RX DQ/DQS(Engine): PASS
7018 09:31:26.918375 TX OE : NO K
7019 09:31:26.918476 All Pass.
7020 09:31:26.918543
7021 09:31:26.918603 CH 1, Rank 0
7022 09:31:26.921885 SW Impedance : PASS
7023 09:31:26.925496 DUTY Scan : NO K
7024 09:31:26.925590 ZQ Calibration : PASS
7025 09:31:26.928466 Jitter Meter : NO K
7026 09:31:26.932137 CBT Training : PASS
7027 09:31:26.932230 Write leveling : PASS
7028 09:31:26.934902 RX DQS gating : PASS
7029 09:31:26.938516 RX DQ/DQS(RDDQC) : PASS
7030 09:31:26.938619 TX DQ/DQS : PASS
7031 09:31:26.941437 RX DATLAT : PASS
7032 09:31:26.945101 RX DQ/DQS(Engine): PASS
7033 09:31:26.945194 TX OE : NO K
7034 09:31:26.945261 All Pass.
7035 09:31:26.948540
7036 09:31:26.948664 CH 1, Rank 1
7037 09:31:26.951456 SW Impedance : PASS
7038 09:31:26.951542 DUTY Scan : NO K
7039 09:31:26.954861 ZQ Calibration : PASS
7040 09:31:26.954950 Jitter Meter : NO K
7041 09:31:26.958500 CBT Training : PASS
7042 09:31:26.961810 Write leveling : NO K
7043 09:31:26.961911 RX DQS gating : PASS
7044 09:31:26.964839 RX DQ/DQS(RDDQC) : PASS
7045 09:31:26.967865 TX DQ/DQS : PASS
7046 09:31:26.967959 RX DATLAT : PASS
7047 09:31:26.971279 RX DQ/DQS(Engine): PASS
7048 09:31:26.974779 TX OE : NO K
7049 09:31:26.974874 All Pass.
7050 09:31:26.974961
7051 09:31:26.978684 DramC Write-DBI off
7052 09:31:26.978773 PER_BANK_REFRESH: Hybrid Mode
7053 09:31:26.981385 TX_TRACKING: ON
7054 09:31:26.991231 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7055 09:31:26.994547 [FAST_K] Save calibration result to emmc
7056 09:31:26.998135 dramc_set_vcore_voltage set vcore to 725000
7057 09:31:26.998238 Read voltage for 1600, 0
7058 09:31:27.001105 Vio18 = 0
7059 09:31:27.001191 Vcore = 725000
7060 09:31:27.001256 Vdram = 0
7061 09:31:27.005020 Vddq = 0
7062 09:31:27.005117 Vmddr = 0
7063 09:31:27.008248 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7064 09:31:27.014399 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7065 09:31:27.017932 MEM_TYPE=3, freq_sel=13
7066 09:31:27.021329 sv_algorithm_assistance_LP4_3733
7067 09:31:27.024655 ============ PULL DRAM RESETB DOWN ============
7068 09:31:27.027613 ========== PULL DRAM RESETB DOWN end =========
7069 09:31:27.034742 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7070 09:31:27.037741 ===================================
7071 09:31:27.037843 LPDDR4 DRAM CONFIGURATION
7072 09:31:27.041189 ===================================
7073 09:31:27.044221 EX_ROW_EN[0] = 0x0
7074 09:31:27.044313 EX_ROW_EN[1] = 0x0
7075 09:31:27.047614 LP4Y_EN = 0x0
7076 09:31:27.047693 WORK_FSP = 0x1
7077 09:31:27.051268 WL = 0x5
7078 09:31:27.054209 RL = 0x5
7079 09:31:27.054303 BL = 0x2
7080 09:31:27.057636 RPST = 0x0
7081 09:31:27.057740 RD_PRE = 0x0
7082 09:31:27.061217 WR_PRE = 0x1
7083 09:31:27.061309 WR_PST = 0x1
7084 09:31:27.064576 DBI_WR = 0x0
7085 09:31:27.064668 DBI_RD = 0x0
7086 09:31:27.067574 OTF = 0x1
7087 09:31:27.071258 ===================================
7088 09:31:27.074230 ===================================
7089 09:31:27.074320 ANA top config
7090 09:31:27.077895 ===================================
7091 09:31:27.080783 DLL_ASYNC_EN = 0
7092 09:31:27.084224 ALL_SLAVE_EN = 0
7093 09:31:27.084314 NEW_RANK_MODE = 1
7094 09:31:27.087286 DLL_IDLE_MODE = 1
7095 09:31:27.090789 LP45_APHY_COMB_EN = 1
7096 09:31:27.094320 TX_ODT_DIS = 0
7097 09:31:27.097709 NEW_8X_MODE = 1
7098 09:31:27.100686 ===================================
7099 09:31:27.103904 ===================================
7100 09:31:27.104003 data_rate = 3200
7101 09:31:27.107236 CKR = 1
7102 09:31:27.110583 DQ_P2S_RATIO = 8
7103 09:31:27.114282 ===================================
7104 09:31:27.117397 CA_P2S_RATIO = 8
7105 09:31:27.120811 DQ_CA_OPEN = 0
7106 09:31:27.123692 DQ_SEMI_OPEN = 0
7107 09:31:27.123833 CA_SEMI_OPEN = 0
7108 09:31:27.127061 CA_FULL_RATE = 0
7109 09:31:27.130407 DQ_CKDIV4_EN = 0
7110 09:31:27.133608 CA_CKDIV4_EN = 0
7111 09:31:27.137022 CA_PREDIV_EN = 0
7112 09:31:27.140170 PH8_DLY = 12
7113 09:31:27.140287 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7114 09:31:27.143350 DQ_AAMCK_DIV = 4
7115 09:31:27.147211 CA_AAMCK_DIV = 4
7116 09:31:27.150123 CA_ADMCK_DIV = 4
7117 09:31:27.153619 DQ_TRACK_CA_EN = 0
7118 09:31:27.156707 CA_PICK = 1600
7119 09:31:27.159984 CA_MCKIO = 1600
7120 09:31:27.160082 MCKIO_SEMI = 0
7121 09:31:27.163539 PLL_FREQ = 3068
7122 09:31:27.166953 DQ_UI_PI_RATIO = 32
7123 09:31:27.169975 CA_UI_PI_RATIO = 0
7124 09:31:27.173536 ===================================
7125 09:31:27.177054 ===================================
7126 09:31:27.179958 memory_type:LPDDR4
7127 09:31:27.180044 GP_NUM : 10
7128 09:31:27.183378 SRAM_EN : 1
7129 09:31:27.186462 MD32_EN : 0
7130 09:31:27.189932 ===================================
7131 09:31:27.190020 [ANA_INIT] >>>>>>>>>>>>>>
7132 09:31:27.193590 <<<<<< [CONFIGURE PHASE]: ANA_TX
7133 09:31:27.196610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7134 09:31:27.199975 ===================================
7135 09:31:27.203527 data_rate = 3200,PCW = 0X7600
7136 09:31:27.206467 ===================================
7137 09:31:27.209921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7138 09:31:27.216417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 09:31:27.219955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 09:31:27.226417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7141 09:31:27.229835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7142 09:31:27.233368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7143 09:31:27.233469 [ANA_INIT] flow start
7144 09:31:27.236226 [ANA_INIT] PLL >>>>>>>>
7145 09:31:27.239544 [ANA_INIT] PLL <<<<<<<<
7146 09:31:27.243013 [ANA_INIT] MIDPI >>>>>>>>
7147 09:31:27.243107 [ANA_INIT] MIDPI <<<<<<<<
7148 09:31:27.246551 [ANA_INIT] DLL >>>>>>>>
7149 09:31:27.249571 [ANA_INIT] DLL <<<<<<<<
7150 09:31:27.249670 [ANA_INIT] flow end
7151 09:31:27.252701 ============ LP4 DIFF to SE enter ============
7152 09:31:27.259593 ============ LP4 DIFF to SE exit ============
7153 09:31:27.259705 [ANA_INIT] <<<<<<<<<<<<<
7154 09:31:27.263133 [Flow] Enable top DCM control >>>>>
7155 09:31:27.266007 [Flow] Enable top DCM control <<<<<
7156 09:31:27.269582 Enable DLL master slave shuffle
7157 09:31:27.275948 ==============================================================
7158 09:31:27.276064 Gating Mode config
7159 09:31:27.282908 ==============================================================
7160 09:31:27.285805 Config description:
7161 09:31:27.296021 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7162 09:31:27.302334 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7163 09:31:27.305733 SELPH_MODE 0: By rank 1: By Phase
7164 09:31:27.312811 ==============================================================
7165 09:31:27.316269 GAT_TRACK_EN = 1
7166 09:31:27.319223 RX_GATING_MODE = 2
7167 09:31:27.319353 RX_GATING_TRACK_MODE = 2
7168 09:31:27.322716 SELPH_MODE = 1
7169 09:31:27.325742 PICG_EARLY_EN = 1
7170 09:31:27.329269 VALID_LAT_VALUE = 1
7171 09:31:27.335791 ==============================================================
7172 09:31:27.339215 Enter into Gating configuration >>>>
7173 09:31:27.342642 Exit from Gating configuration <<<<
7174 09:31:27.345640 Enter into DVFS_PRE_config >>>>>
7175 09:31:27.355980 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7176 09:31:27.359367 Exit from DVFS_PRE_config <<<<<
7177 09:31:27.362368 Enter into PICG configuration >>>>
7178 09:31:27.365927 Exit from PICG configuration <<<<
7179 09:31:27.368860 [RX_INPUT] configuration >>>>>
7180 09:31:27.372366 [RX_INPUT] configuration <<<<<
7181 09:31:27.376038 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7182 09:31:27.382331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7183 09:31:27.389480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 09:31:27.395440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 09:31:27.398743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 09:31:27.405608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 09:31:27.408936 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7188 09:31:27.415352 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7189 09:31:27.418627 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7190 09:31:27.422079 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7191 09:31:27.425335 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7192 09:31:27.432553 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 09:31:27.435591 ===================================
7194 09:31:27.435692 LPDDR4 DRAM CONFIGURATION
7195 09:31:27.439013 ===================================
7196 09:31:27.442369 EX_ROW_EN[0] = 0x0
7197 09:31:27.445339 EX_ROW_EN[1] = 0x0
7198 09:31:27.445436 LP4Y_EN = 0x0
7199 09:31:27.448931 WORK_FSP = 0x1
7200 09:31:27.449023 WL = 0x5
7201 09:31:27.451787 RL = 0x5
7202 09:31:27.451876 BL = 0x2
7203 09:31:27.455178 RPST = 0x0
7204 09:31:27.455287 RD_PRE = 0x0
7205 09:31:27.458660 WR_PRE = 0x1
7206 09:31:27.458758 WR_PST = 0x1
7207 09:31:27.461597 DBI_WR = 0x0
7208 09:31:27.461686 DBI_RD = 0x0
7209 09:31:27.465168 OTF = 0x1
7210 09:31:27.468727 ===================================
7211 09:31:27.471604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7212 09:31:27.475264 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7213 09:31:27.481705 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 09:31:27.484726 ===================================
7215 09:31:27.484823 LPDDR4 DRAM CONFIGURATION
7216 09:31:27.488256 ===================================
7217 09:31:27.491826 EX_ROW_EN[0] = 0x10
7218 09:31:27.494665 EX_ROW_EN[1] = 0x0
7219 09:31:27.494761 LP4Y_EN = 0x0
7220 09:31:27.498177 WORK_FSP = 0x1
7221 09:31:27.498289 WL = 0x5
7222 09:31:27.501679 RL = 0x5
7223 09:31:27.501803 BL = 0x2
7224 09:31:27.505226 RPST = 0x0
7225 09:31:27.505317 RD_PRE = 0x0
7226 09:31:27.508080 WR_PRE = 0x1
7227 09:31:27.508166 WR_PST = 0x1
7228 09:31:27.511351 DBI_WR = 0x0
7229 09:31:27.511513 DBI_RD = 0x0
7230 09:31:27.514565 OTF = 0x1
7231 09:31:27.518205 ===================================
7232 09:31:27.524565 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7233 09:31:27.524674 ==
7234 09:31:27.528033 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 09:31:27.531188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7236 09:31:27.531279 ==
7237 09:31:27.534506 [Duty_Offset_Calibration]
7238 09:31:27.534593 B0:2 B1:0 CA:3
7239 09:31:27.534658
7240 09:31:27.538417 [DutyScan_Calibration_Flow] k_type=0
7241 09:31:27.549374
7242 09:31:27.549504 ==CLK 0==
7243 09:31:27.552099 Final CLK duty delay cell = 0
7244 09:31:27.555297 [0] MAX Duty = 5031%(X100), DQS PI = 12
7245 09:31:27.558479 [0] MIN Duty = 4907%(X100), DQS PI = 2
7246 09:31:27.558587 [0] AVG Duty = 4969%(X100)
7247 09:31:27.561963
7248 09:31:27.565165 CH0 CLK Duty spec in!! Max-Min= 124%
7249 09:31:27.568777 [DutyScan_Calibration_Flow] ====Done====
7250 09:31:27.568874
7251 09:31:27.571755 [DutyScan_Calibration_Flow] k_type=1
7252 09:31:27.588987
7253 09:31:27.589127 ==DQS 0 ==
7254 09:31:27.591970 Final DQS duty delay cell = 0
7255 09:31:27.595337 [0] MAX Duty = 5094%(X100), DQS PI = 28
7256 09:31:27.598458 [0] MIN Duty = 4906%(X100), DQS PI = 52
7257 09:31:27.602140 [0] AVG Duty = 5000%(X100)
7258 09:31:27.602237
7259 09:31:27.602304 ==DQS 1 ==
7260 09:31:27.605033 Final DQS duty delay cell = 0
7261 09:31:27.608527 [0] MAX Duty = 5156%(X100), DQS PI = 30
7262 09:31:27.612103 [0] MIN Duty = 5062%(X100), DQS PI = 6
7263 09:31:27.614962 [0] AVG Duty = 5109%(X100)
7264 09:31:27.615078
7265 09:31:27.618437 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7266 09:31:27.618552
7267 09:31:27.621701 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7268 09:31:27.625208 [DutyScan_Calibration_Flow] ====Done====
7269 09:31:27.625336
7270 09:31:27.628287 [DutyScan_Calibration_Flow] k_type=3
7271 09:31:27.645703
7272 09:31:27.645868 ==DQM 0 ==
7273 09:31:27.648753 Final DQM duty delay cell = 0
7274 09:31:27.651936 [0] MAX Duty = 5156%(X100), DQS PI = 30
7275 09:31:27.655193 [0] MIN Duty = 4875%(X100), DQS PI = 0
7276 09:31:27.655320 [0] AVG Duty = 5015%(X100)
7277 09:31:27.658645
7278 09:31:27.658761 ==DQM 1 ==
7279 09:31:27.662274 Final DQM duty delay cell = 0
7280 09:31:27.665262 [0] MAX Duty = 4938%(X100), DQS PI = 52
7281 09:31:27.668669 [0] MIN Duty = 4813%(X100), DQS PI = 10
7282 09:31:27.671936 [0] AVG Duty = 4875%(X100)
7283 09:31:27.672049
7284 09:31:27.675314 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7285 09:31:27.675529
7286 09:31:27.678270 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7287 09:31:27.682445 [DutyScan_Calibration_Flow] ====Done====
7288 09:31:27.682547
7289 09:31:27.684923 [DutyScan_Calibration_Flow] k_type=2
7290 09:31:27.701783
7291 09:31:27.701923 ==DQ 0 ==
7292 09:31:27.704581 Final DQ duty delay cell = -4
7293 09:31:27.708265 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7294 09:31:27.711932 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7295 09:31:27.714806 [-4] AVG Duty = 4938%(X100)
7296 09:31:27.714897
7297 09:31:27.714961 ==DQ 1 ==
7298 09:31:27.718307 Final DQ duty delay cell = 0
7299 09:31:27.721312 [0] MAX Duty = 5156%(X100), DQS PI = 58
7300 09:31:27.724735 [0] MIN Duty = 5000%(X100), DQS PI = 14
7301 09:31:27.728088 [0] AVG Duty = 5078%(X100)
7302 09:31:27.728222
7303 09:31:27.731612 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7304 09:31:27.731729
7305 09:31:27.734563 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7306 09:31:27.738165 [DutyScan_Calibration_Flow] ====Done====
7307 09:31:27.738281 ==
7308 09:31:27.741180 Dram Type= 6, Freq= 0, CH_1, rank 0
7309 09:31:27.744745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 09:31:27.744864 ==
7311 09:31:27.748201 [Duty_Offset_Calibration]
7312 09:31:27.748319 B0:1 B1:-2 CA:1
7313 09:31:27.748412
7314 09:31:27.751147 [DutyScan_Calibration_Flow] k_type=0
7315 09:31:27.762043
7316 09:31:27.762207 ==CLK 0==
7317 09:31:27.765691 Final CLK duty delay cell = 0
7318 09:31:27.768498 [0] MAX Duty = 5062%(X100), DQS PI = 22
7319 09:31:27.772147 [0] MIN Duty = 4813%(X100), DQS PI = 60
7320 09:31:27.775505 [0] AVG Duty = 4937%(X100)
7321 09:31:27.775629
7322 09:31:27.778330 CH1 CLK Duty spec in!! Max-Min= 249%
7323 09:31:27.781652 [DutyScan_Calibration_Flow] ====Done====
7324 09:31:27.781825
7325 09:31:27.785046 [DutyScan_Calibration_Flow] k_type=1
7326 09:31:27.801640
7327 09:31:27.801816 ==DQS 0 ==
7328 09:31:27.805264 Final DQS duty delay cell = 0
7329 09:31:27.808488 [0] MAX Duty = 5187%(X100), DQS PI = 24
7330 09:31:27.811644 [0] MIN Duty = 5062%(X100), DQS PI = 0
7331 09:31:27.811808 [0] AVG Duty = 5124%(X100)
7332 09:31:27.815042
7333 09:31:27.815156 ==DQS 1 ==
7334 09:31:27.818210 Final DQS duty delay cell = 0
7335 09:31:27.821822 [0] MAX Duty = 5093%(X100), DQS PI = 60
7336 09:31:27.824516 [0] MIN Duty = 4844%(X100), DQS PI = 24
7337 09:31:27.828147 [0] AVG Duty = 4968%(X100)
7338 09:31:27.828273
7339 09:31:27.831615 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7340 09:31:27.831728
7341 09:31:27.834738 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7342 09:31:27.838433 [DutyScan_Calibration_Flow] ====Done====
7343 09:31:27.838552
7344 09:31:27.841397 [DutyScan_Calibration_Flow] k_type=3
7345 09:31:27.858392
7346 09:31:27.858561 ==DQM 0 ==
7347 09:31:27.861735 Final DQM duty delay cell = 0
7348 09:31:27.865197 [0] MAX Duty = 5031%(X100), DQS PI = 24
7349 09:31:27.868263 [0] MIN Duty = 4813%(X100), DQS PI = 54
7350 09:31:27.871928 [0] AVG Duty = 4922%(X100)
7351 09:31:27.872052
7352 09:31:27.872148 ==DQM 1 ==
7353 09:31:27.874794 Final DQM duty delay cell = 0
7354 09:31:27.878237 [0] MAX Duty = 5062%(X100), DQS PI = 34
7355 09:31:27.881365 [0] MIN Duty = 4875%(X100), DQS PI = 24
7356 09:31:27.884740 [0] AVG Duty = 4968%(X100)
7357 09:31:27.884909
7358 09:31:27.888193 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7359 09:31:27.888310
7360 09:31:27.891625 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7361 09:31:27.894669 [DutyScan_Calibration_Flow] ====Done====
7362 09:31:27.894790
7363 09:31:27.898351 [DutyScan_Calibration_Flow] k_type=2
7364 09:31:27.915243
7365 09:31:27.915466 ==DQ 0 ==
7366 09:31:27.918737 Final DQ duty delay cell = 0
7367 09:31:27.921931 [0] MAX Duty = 5093%(X100), DQS PI = 20
7368 09:31:27.925399 [0] MIN Duty = 4938%(X100), DQS PI = 0
7369 09:31:27.925522 [0] AVG Duty = 5015%(X100)
7370 09:31:27.928504
7371 09:31:27.928615 ==DQ 1 ==
7372 09:31:27.932063 Final DQ duty delay cell = 0
7373 09:31:27.934875 [0] MAX Duty = 5125%(X100), DQS PI = 34
7374 09:31:27.938449 [0] MIN Duty = 4969%(X100), DQS PI = 24
7375 09:31:27.938573 [0] AVG Duty = 5047%(X100)
7376 09:31:27.938670
7377 09:31:27.945150 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7378 09:31:27.945290
7379 09:31:27.948356 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7380 09:31:27.951541 [DutyScan_Calibration_Flow] ====Done====
7381 09:31:27.955084 nWR fixed to 30
7382 09:31:27.955214 [ModeRegInit_LP4] CH0 RK0
7383 09:31:27.958509 [ModeRegInit_LP4] CH0 RK1
7384 09:31:27.961413 [ModeRegInit_LP4] CH1 RK0
7385 09:31:27.964902 [ModeRegInit_LP4] CH1 RK1
7386 09:31:27.965025 match AC timing 5
7387 09:31:27.968285 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7388 09:31:27.974916 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7389 09:31:27.977984 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7390 09:31:27.984671 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7391 09:31:27.988244 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7392 09:31:27.988400 [MiockJmeterHQA]
7393 09:31:27.988502
7394 09:31:27.991581 [DramcMiockJmeter] u1RxGatingPI = 0
7395 09:31:27.994498 0 : 4368, 4140
7396 09:31:27.994619 4 : 4260, 4032
7397 09:31:27.998070 8 : 4257, 4029
7398 09:31:27.998183 12 : 4257, 4029
7399 09:31:27.998278 16 : 4255, 4029
7400 09:31:28.001117 20 : 4255, 4029
7401 09:31:28.001228 24 : 4254, 4029
7402 09:31:28.004555 28 : 4363, 4140
7403 09:31:28.004669 32 : 4255, 4030
7404 09:31:28.007973 36 : 4255, 4029
7405 09:31:28.008091 40 : 4363, 4137
7406 09:31:28.011503 44 : 4255, 4029
7407 09:31:28.011623 48 : 4253, 4029
7408 09:31:28.011720 52 : 4253, 4029
7409 09:31:28.014990 56 : 4252, 4029
7410 09:31:28.015103 60 : 4252, 4030
7411 09:31:28.017672 64 : 4255, 4030
7412 09:31:28.017784 68 : 4255, 4029
7413 09:31:28.021477 72 : 4255, 4029
7414 09:31:28.021597 76 : 4257, 4032
7415 09:31:28.024584 80 : 4253, 4029
7416 09:31:28.024699 84 : 4252, 4030
7417 09:31:28.024795 88 : 4255, 4029
7418 09:31:28.027528 92 : 4252, 4029
7419 09:31:28.027639 96 : 4258, 4032
7420 09:31:28.031062 100 : 4366, 4139
7421 09:31:28.031174 104 : 4252, 4014
7422 09:31:28.034730 108 : 4252, 217
7423 09:31:28.034845 112 : 4253, 0
7424 09:31:28.034943 116 : 4255, 0
7425 09:31:28.037633 120 : 4363, 0
7426 09:31:28.037741 124 : 4255, 0
7427 09:31:28.040781 128 : 4255, 0
7428 09:31:28.040890 132 : 4255, 0
7429 09:31:28.040983 136 : 4365, 0
7430 09:31:28.044180 140 : 4252, 0
7431 09:31:28.044295 144 : 4253, 0
7432 09:31:28.047396 148 : 4252, 0
7433 09:31:28.047521 152 : 4253, 0
7434 09:31:28.047616 156 : 4252, 0
7435 09:31:28.051093 160 : 4252, 0
7436 09:31:28.051207 164 : 4253, 0
7437 09:31:28.054294 168 : 4258, 0
7438 09:31:28.054411 172 : 4252, 0
7439 09:31:28.054512 176 : 4253, 0
7440 09:31:28.057411 180 : 4368, 0
7441 09:31:28.057520 184 : 4360, 0
7442 09:31:28.057616 188 : 4252, 0
7443 09:31:28.060890 192 : 4360, 0
7444 09:31:28.060999 196 : 4363, 0
7445 09:31:28.064134 200 : 4252, 0
7446 09:31:28.064242 204 : 4366, 0
7447 09:31:28.064336 208 : 4252, 0
7448 09:31:28.067690 212 : 4363, 0
7449 09:31:28.067799 216 : 4361, 0
7450 09:31:28.070766 220 : 4252, 0
7451 09:31:28.070885 224 : 4363, 0
7452 09:31:28.070980 228 : 4253, 0
7453 09:31:28.074327 232 : 4363, 0
7454 09:31:28.074444 236 : 4252, 470
7455 09:31:28.077254 240 : 4366, 4135
7456 09:31:28.077365 244 : 4361, 4137
7457 09:31:28.080723 248 : 4250, 4027
7458 09:31:28.080836 252 : 4252, 4029
7459 09:31:28.083762 256 : 4368, 4143
7460 09:31:28.083876 260 : 4255, 4029
7461 09:31:28.087124 264 : 4252, 4030
7462 09:31:28.087237 268 : 4363, 4140
7463 09:31:28.087333 272 : 4255, 4030
7464 09:31:28.090669 276 : 4365, 4140
7465 09:31:28.090782 280 : 4365, 4139
7466 09:31:28.094091 284 : 4363, 4140
7467 09:31:28.094214 288 : 4250, 4027
7468 09:31:28.097068 292 : 4250, 4027
7469 09:31:28.097178 296 : 4363, 4140
7470 09:31:28.100546 300 : 4252, 4030
7471 09:31:28.100672 304 : 4363, 4140
7472 09:31:28.104174 308 : 4255, 4030
7473 09:31:28.104290 312 : 4255, 4029
7474 09:31:28.107255 316 : 4252, 4029
7475 09:31:28.107382 320 : 4255, 4029
7476 09:31:28.110203 324 : 4257, 4032
7477 09:31:28.110316 328 : 4365, 4140
7478 09:31:28.110416 332 : 4253, 4029
7479 09:31:28.113549 336 : 4252, 4029
7480 09:31:28.113661 340 : 4258, 4032
7481 09:31:28.117101 344 : 4252, 4029
7482 09:31:28.117216 348 : 4253, 4029
7483 09:31:28.120228 352 : 4252, 4028
7484 09:31:28.120338 356 : 4363, 3139
7485 09:31:28.123503 360 : 4255, 8
7486 09:31:28.123615
7487 09:31:28.123708 MIOCK jitter meter ch=0
7488 09:31:28.123797
7489 09:31:28.127022 1T = (360-108) = 252 dly cells
7490 09:31:28.133537 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7491 09:31:28.133682 ==
7492 09:31:28.137018 Dram Type= 6, Freq= 0, CH_0, rank 0
7493 09:31:28.140523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 09:31:28.140642 ==
7495 09:31:28.146786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 09:31:28.150272 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 09:31:28.156935 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 09:31:28.159997 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 09:31:28.170031 [CA 0] Center 44 (14~74) winsize 61
7500 09:31:28.173494 [CA 1] Center 43 (13~74) winsize 62
7501 09:31:28.177203 [CA 2] Center 39 (10~68) winsize 59
7502 09:31:28.180413 [CA 3] Center 39 (10~68) winsize 59
7503 09:31:28.183803 [CA 4] Center 37 (8~66) winsize 59
7504 09:31:28.186648 [CA 5] Center 36 (7~66) winsize 60
7505 09:31:28.186771
7506 09:31:28.190037 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 09:31:28.190150
7508 09:31:28.197084 [CATrainingPosCal] consider 1 rank data
7509 09:31:28.197237 u2DelayCellTimex100 = 258/100 ps
7510 09:31:28.203582 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7511 09:31:28.206421 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7512 09:31:28.209997 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7513 09:31:28.213452 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7514 09:31:28.216410 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7515 09:31:28.219995 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 09:31:28.220128
7517 09:31:28.222979 CA PerBit enable=1, Macro0, CA PI delay=36
7518 09:31:28.223090
7519 09:31:28.226464 [CBTSetCACLKResult] CA Dly = 36
7520 09:31:28.229897 CS Dly: 11 (0~42)
7521 09:31:28.233341 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 09:31:28.236896 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 09:31:28.237021 ==
7524 09:31:28.240112 Dram Type= 6, Freq= 0, CH_0, rank 1
7525 09:31:28.246464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 09:31:28.246606 ==
7527 09:31:28.249890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 09:31:28.256737 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 09:31:28.259554 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 09:31:28.266349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 09:31:28.274118 [CA 0] Center 44 (13~75) winsize 63
7532 09:31:28.277621 [CA 1] Center 43 (13~74) winsize 62
7533 09:31:28.280509 [CA 2] Center 39 (10~69) winsize 60
7534 09:31:28.284016 [CA 3] Center 39 (10~68) winsize 59
7535 09:31:28.287552 [CA 4] Center 37 (8~67) winsize 60
7536 09:31:28.290585 [CA 5] Center 36 (7~66) winsize 60
7537 09:31:28.290703
7538 09:31:28.294080 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 09:31:28.294197
7540 09:31:28.297422 [CATrainingPosCal] consider 2 rank data
7541 09:31:28.300962 u2DelayCellTimex100 = 258/100 ps
7542 09:31:28.303912 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7543 09:31:28.310606 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7544 09:31:28.314195 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7545 09:31:28.317210 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7546 09:31:28.320550 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7547 09:31:28.324016 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 09:31:28.324146
7549 09:31:28.327298 CA PerBit enable=1, Macro0, CA PI delay=36
7550 09:31:28.327451
7551 09:31:28.330281 [CBTSetCACLKResult] CA Dly = 36
7552 09:31:28.333823 CS Dly: 11 (0~43)
7553 09:31:28.336899 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 09:31:28.340652 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 09:31:28.340776
7556 09:31:28.343962 ----->DramcWriteLeveling(PI) begin...
7557 09:31:28.344082 ==
7558 09:31:28.346925 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 09:31:28.353898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 09:31:28.354041 ==
7561 09:31:28.356752 Write leveling (Byte 0): 35 => 35
7562 09:31:28.360223 Write leveling (Byte 1): 30 => 30
7563 09:31:28.360342 DramcWriteLeveling(PI) end<-----
7564 09:31:28.363634
7565 09:31:28.363747 ==
7566 09:31:28.366994 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 09:31:28.370375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 09:31:28.370476 ==
7569 09:31:28.373754 [Gating] SW mode calibration
7570 09:31:28.380270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7571 09:31:28.383340 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7572 09:31:28.390428 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 09:31:28.393307 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 09:31:28.396941 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 09:31:28.403875 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 09:31:28.406801 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7577 09:31:28.410435 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7578 09:31:28.417062 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7579 09:31:28.419769 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 09:31:28.423598 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 09:31:28.429937 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 09:31:28.432940 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 09:31:28.436638 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7584 09:31:28.442964 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7585 09:31:28.446524 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7586 09:31:28.449852 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7587 09:31:28.456179 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7588 09:31:28.460214 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 09:31:28.462770 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 09:31:28.469411 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 09:31:28.472619 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7592 09:31:28.476421 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7593 09:31:28.482766 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7594 09:31:28.486304 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7595 09:31:28.489306 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 09:31:28.495996 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 09:31:28.499518 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 09:31:28.502384 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 09:31:28.509512 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 09:31:28.512420 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7601 09:31:28.515647 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 09:31:28.522561 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7603 09:31:28.525474 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 09:31:28.529099 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 09:31:28.535567 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 09:31:28.539003 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 09:31:28.542351 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 09:31:28.549039 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 09:31:28.552406 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 09:31:28.555798 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 09:31:28.562146 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 09:31:28.565660 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 09:31:28.568640 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 09:31:28.575280 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 09:31:28.578775 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7616 09:31:28.581766 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 09:31:28.588502 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7618 09:31:28.588643 Total UI for P1: 0, mck2ui 16
7619 09:31:28.595348 best dqsien dly found for B0: ( 1, 9, 14)
7620 09:31:28.598404 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7621 09:31:28.602050 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 09:31:28.604999 Total UI for P1: 0, mck2ui 16
7623 09:31:28.608435 best dqsien dly found for B1: ( 1, 9, 24)
7624 09:31:28.612097 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7625 09:31:28.615167 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7626 09:31:28.615293
7627 09:31:28.618546 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7628 09:31:28.625055 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7629 09:31:28.625195 [Gating] SW calibration Done
7630 09:31:28.625293 ==
7631 09:31:28.628653 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 09:31:28.635296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 09:31:28.635474 ==
7634 09:31:28.635577 RX Vref Scan: 0
7635 09:31:28.635667
7636 09:31:28.638628 RX Vref 0 -> 0, step: 1
7637 09:31:28.638738
7638 09:31:28.642025 RX Delay 0 -> 252, step: 8
7639 09:31:28.644907 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7640 09:31:28.648344 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7641 09:31:28.651777 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7642 09:31:28.658223 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7643 09:31:28.661893 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7644 09:31:28.664704 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7645 09:31:28.668361 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7646 09:31:28.671928 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7647 09:31:28.678494 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7648 09:31:28.681427 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7649 09:31:28.684939 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7650 09:31:28.688195 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7651 09:31:28.691576 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7652 09:31:28.698527 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7653 09:31:28.702260 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7654 09:31:28.704713 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7655 09:31:28.704838 ==
7656 09:31:28.708622 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 09:31:28.711780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 09:31:28.711918 ==
7659 09:31:28.714572 DQS Delay:
7660 09:31:28.714684 DQS0 = 0, DQS1 = 0
7661 09:31:28.718227 DQM Delay:
7662 09:31:28.718342 DQM0 = 128, DQM1 = 123
7663 09:31:28.718435 DQ Delay:
7664 09:31:28.724748 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7665 09:31:28.727821 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7666 09:31:28.731264 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7667 09:31:28.734787 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7668 09:31:28.734884
7669 09:31:28.734949
7670 09:31:28.735010 ==
7671 09:31:28.738191 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 09:31:28.741392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 09:31:28.741485 ==
7674 09:31:28.741551
7675 09:31:28.741611
7676 09:31:28.744701 TX Vref Scan disable
7677 09:31:28.748072 == TX Byte 0 ==
7678 09:31:28.751102 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7679 09:31:28.754589 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7680 09:31:28.758029 == TX Byte 1 ==
7681 09:31:28.760895 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7682 09:31:28.764436 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7683 09:31:28.764559 ==
7684 09:31:28.768234 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 09:31:28.774578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 09:31:28.774730 ==
7687 09:31:28.786377
7688 09:31:28.789470 TX Vref early break, caculate TX vref
7689 09:31:28.793026 TX Vref=16, minBit 0, minWin=22, winSum=361
7690 09:31:28.795997 TX Vref=18, minBit 0, minWin=23, winSum=373
7691 09:31:28.799540 TX Vref=20, minBit 7, minWin=23, winSum=389
7692 09:31:28.802518 TX Vref=22, minBit 0, minWin=24, winSum=396
7693 09:31:28.806139 TX Vref=24, minBit 0, minWin=25, winSum=411
7694 09:31:28.812833 TX Vref=26, minBit 4, minWin=24, winSum=415
7695 09:31:28.815976 TX Vref=28, minBit 2, minWin=25, winSum=416
7696 09:31:28.819622 TX Vref=30, minBit 0, minWin=24, winSum=407
7697 09:31:28.823098 TX Vref=32, minBit 4, minWin=24, winSum=399
7698 09:31:28.826067 TX Vref=34, minBit 14, minWin=23, winSum=387
7699 09:31:28.832427 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 28
7700 09:31:28.832572
7701 09:31:28.835878 Final TX Range 0 Vref 28
7702 09:31:28.836051
7703 09:31:28.836147 ==
7704 09:31:28.839138 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 09:31:28.842733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 09:31:28.842851 ==
7707 09:31:28.842945
7708 09:31:28.843035
7709 09:31:28.846148 TX Vref Scan disable
7710 09:31:28.852340 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7711 09:31:28.852482 == TX Byte 0 ==
7712 09:31:28.855601 u2DelayCellOfst[0]=11 cells (3 PI)
7713 09:31:28.858912 u2DelayCellOfst[1]=18 cells (5 PI)
7714 09:31:28.862442 u2DelayCellOfst[2]=11 cells (3 PI)
7715 09:31:28.865423 u2DelayCellOfst[3]=11 cells (3 PI)
7716 09:31:28.868887 u2DelayCellOfst[4]=7 cells (2 PI)
7717 09:31:28.872118 u2DelayCellOfst[5]=0 cells (0 PI)
7718 09:31:28.875412 u2DelayCellOfst[6]=18 cells (5 PI)
7719 09:31:28.878941 u2DelayCellOfst[7]=18 cells (5 PI)
7720 09:31:28.882534 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7721 09:31:28.885592 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7722 09:31:28.888438 == TX Byte 1 ==
7723 09:31:28.892062 u2DelayCellOfst[8]=0 cells (0 PI)
7724 09:31:28.892183 u2DelayCellOfst[9]=0 cells (0 PI)
7725 09:31:28.895072 u2DelayCellOfst[10]=3 cells (1 PI)
7726 09:31:28.898623 u2DelayCellOfst[11]=0 cells (0 PI)
7727 09:31:28.902066 u2DelayCellOfst[12]=11 cells (3 PI)
7728 09:31:28.905048 u2DelayCellOfst[13]=7 cells (2 PI)
7729 09:31:28.908536 u2DelayCellOfst[14]=15 cells (4 PI)
7730 09:31:28.912196 u2DelayCellOfst[15]=7 cells (2 PI)
7731 09:31:28.915371 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7732 09:31:28.921587 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7733 09:31:28.921734 DramC Write-DBI on
7734 09:31:28.921832 ==
7735 09:31:28.925166 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 09:31:28.931541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 09:31:28.931683 ==
7738 09:31:28.931783
7739 09:31:28.931871
7740 09:31:28.931958 TX Vref Scan disable
7741 09:31:28.935289 == TX Byte 0 ==
7742 09:31:28.938718 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7743 09:31:28.941976 == TX Byte 1 ==
7744 09:31:28.945472 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7745 09:31:28.948794 DramC Write-DBI off
7746 09:31:28.948918
7747 09:31:28.949014 [DATLAT]
7748 09:31:28.949110 Freq=1600, CH0 RK0
7749 09:31:28.949199
7750 09:31:28.951697 DATLAT Default: 0xf
7751 09:31:28.955305 0, 0xFFFF, sum = 0
7752 09:31:28.955465 1, 0xFFFF, sum = 0
7753 09:31:28.958315 2, 0xFFFF, sum = 0
7754 09:31:28.958429 3, 0xFFFF, sum = 0
7755 09:31:28.961731 4, 0xFFFF, sum = 0
7756 09:31:28.961846 5, 0xFFFF, sum = 0
7757 09:31:28.964973 6, 0xFFFF, sum = 0
7758 09:31:28.965087 7, 0xFFFF, sum = 0
7759 09:31:28.968655 8, 0xFFFF, sum = 0
7760 09:31:28.968768 9, 0xFFFF, sum = 0
7761 09:31:28.971900 10, 0xFFFF, sum = 0
7762 09:31:28.972013 11, 0xFFFF, sum = 0
7763 09:31:28.974983 12, 0xFFFF, sum = 0
7764 09:31:28.975094 13, 0xEFFF, sum = 0
7765 09:31:28.978359 14, 0x0, sum = 1
7766 09:31:28.978470 15, 0x0, sum = 2
7767 09:31:28.981732 16, 0x0, sum = 3
7768 09:31:28.981847 17, 0x0, sum = 4
7769 09:31:28.985237 best_step = 15
7770 09:31:28.985350
7771 09:31:28.985443 ==
7772 09:31:28.988354 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 09:31:28.992111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 09:31:28.992236 ==
7775 09:31:28.994959 RX Vref Scan: 1
7776 09:31:28.995069
7777 09:31:28.995161 Set Vref Range= 24 -> 127
7778 09:31:28.995252
7779 09:31:28.998462 RX Vref 24 -> 127, step: 1
7780 09:31:28.998588
7781 09:31:29.002104 RX Delay 11 -> 252, step: 4
7782 09:31:29.002219
7783 09:31:29.004965 Set Vref, RX VrefLevel [Byte0]: 24
7784 09:31:29.008528 [Byte1]: 24
7785 09:31:29.008645
7786 09:31:29.011552 Set Vref, RX VrefLevel [Byte0]: 25
7787 09:31:29.015056 [Byte1]: 25
7788 09:31:29.018066
7789 09:31:29.018180 Set Vref, RX VrefLevel [Byte0]: 26
7790 09:31:29.021536 [Byte1]: 26
7791 09:31:29.026239
7792 09:31:29.026365 Set Vref, RX VrefLevel [Byte0]: 27
7793 09:31:29.029261 [Byte1]: 27
7794 09:31:29.033775
7795 09:31:29.033895 Set Vref, RX VrefLevel [Byte0]: 28
7796 09:31:29.036763 [Byte1]: 28
7797 09:31:29.040940
7798 09:31:29.041058 Set Vref, RX VrefLevel [Byte0]: 29
7799 09:31:29.044433 [Byte1]: 29
7800 09:31:29.049003
7801 09:31:29.049131 Set Vref, RX VrefLevel [Byte0]: 30
7802 09:31:29.052071 [Byte1]: 30
7803 09:31:29.056175
7804 09:31:29.056300 Set Vref, RX VrefLevel [Byte0]: 31
7805 09:31:29.059676 [Byte1]: 31
7806 09:31:29.063734
7807 09:31:29.063853 Set Vref, RX VrefLevel [Byte0]: 32
7808 09:31:29.067398 [Byte1]: 32
7809 09:31:29.071296
7810 09:31:29.071456 Set Vref, RX VrefLevel [Byte0]: 33
7811 09:31:29.074796 [Byte1]: 33
7812 09:31:29.079091
7813 09:31:29.079219 Set Vref, RX VrefLevel [Byte0]: 34
7814 09:31:29.082720 [Byte1]: 34
7815 09:31:29.086825
7816 09:31:29.086987 Set Vref, RX VrefLevel [Byte0]: 35
7817 09:31:29.090276 [Byte1]: 35
7818 09:31:29.094164
7819 09:31:29.094329 Set Vref, RX VrefLevel [Byte0]: 36
7820 09:31:29.097911 [Byte1]: 36
7821 09:31:29.101887
7822 09:31:29.102017 Set Vref, RX VrefLevel [Byte0]: 37
7823 09:31:29.105115 [Byte1]: 37
7824 09:31:29.109514
7825 09:31:29.109640 Set Vref, RX VrefLevel [Byte0]: 38
7826 09:31:29.113039 [Byte1]: 38
7827 09:31:29.117301
7828 09:31:29.117429 Set Vref, RX VrefLevel [Byte0]: 39
7829 09:31:29.120591 [Byte1]: 39
7830 09:31:29.124959
7831 09:31:29.125089 Set Vref, RX VrefLevel [Byte0]: 40
7832 09:31:29.128196 [Byte1]: 40
7833 09:31:29.132448
7834 09:31:29.132574 Set Vref, RX VrefLevel [Byte0]: 41
7835 09:31:29.135899 [Byte1]: 41
7836 09:31:29.140219
7837 09:31:29.140343 Set Vref, RX VrefLevel [Byte0]: 42
7838 09:31:29.143521 [Byte1]: 42
7839 09:31:29.147694
7840 09:31:29.147812 Set Vref, RX VrefLevel [Byte0]: 43
7841 09:31:29.151363 [Byte1]: 43
7842 09:31:29.155164
7843 09:31:29.155280 Set Vref, RX VrefLevel [Byte0]: 44
7844 09:31:29.158504 [Byte1]: 44
7845 09:31:29.162771
7846 09:31:29.162893 Set Vref, RX VrefLevel [Byte0]: 45
7847 09:31:29.166203 [Byte1]: 45
7848 09:31:29.170451
7849 09:31:29.170576 Set Vref, RX VrefLevel [Byte0]: 46
7850 09:31:29.173519 [Byte1]: 46
7851 09:31:29.177968
7852 09:31:29.178102 Set Vref, RX VrefLevel [Byte0]: 47
7853 09:31:29.181253 [Byte1]: 47
7854 09:31:29.186064
7855 09:31:29.186190 Set Vref, RX VrefLevel [Byte0]: 48
7856 09:31:29.188841 [Byte1]: 48
7857 09:31:29.193554
7858 09:31:29.193682 Set Vref, RX VrefLevel [Byte0]: 49
7859 09:31:29.196595 [Byte1]: 49
7860 09:31:29.201276
7861 09:31:29.201405 Set Vref, RX VrefLevel [Byte0]: 50
7862 09:31:29.204242 [Byte1]: 50
7863 09:31:29.208707
7864 09:31:29.208830 Set Vref, RX VrefLevel [Byte0]: 51
7865 09:31:29.211954 [Byte1]: 51
7866 09:31:29.216333
7867 09:31:29.216456 Set Vref, RX VrefLevel [Byte0]: 52
7868 09:31:29.219572 [Byte1]: 52
7869 09:31:29.223595
7870 09:31:29.223722 Set Vref, RX VrefLevel [Byte0]: 53
7871 09:31:29.227046 [Byte1]: 53
7872 09:31:29.231493
7873 09:31:29.231621 Set Vref, RX VrefLevel [Byte0]: 54
7874 09:31:29.234632 [Byte1]: 54
7875 09:31:29.239223
7876 09:31:29.239363 Set Vref, RX VrefLevel [Byte0]: 55
7877 09:31:29.242044 [Byte1]: 55
7878 09:31:29.246504
7879 09:31:29.246626 Set Vref, RX VrefLevel [Byte0]: 56
7880 09:31:29.249797 [Byte1]: 56
7881 09:31:29.254581
7882 09:31:29.254688 Set Vref, RX VrefLevel [Byte0]: 57
7883 09:31:29.257423 [Byte1]: 57
7884 09:31:29.261904
7885 09:31:29.262033 Set Vref, RX VrefLevel [Byte0]: 58
7886 09:31:29.265441 [Byte1]: 58
7887 09:31:29.269415
7888 09:31:29.269534 Set Vref, RX VrefLevel [Byte0]: 59
7889 09:31:29.273020 [Byte1]: 59
7890 09:31:29.276904
7891 09:31:29.277022 Set Vref, RX VrefLevel [Byte0]: 60
7892 09:31:29.280565 [Byte1]: 60
7893 09:31:29.284879
7894 09:31:29.284976 Set Vref, RX VrefLevel [Byte0]: 61
7895 09:31:29.288021 [Byte1]: 61
7896 09:31:29.292349
7897 09:31:29.292448 Set Vref, RX VrefLevel [Byte0]: 62
7898 09:31:29.295729 [Byte1]: 62
7899 09:31:29.299949
7900 09:31:29.300045 Set Vref, RX VrefLevel [Byte0]: 63
7901 09:31:29.303294 [Byte1]: 63
7902 09:31:29.307314
7903 09:31:29.307447 Set Vref, RX VrefLevel [Byte0]: 64
7904 09:31:29.310984 [Byte1]: 64
7905 09:31:29.315153
7906 09:31:29.315251 Set Vref, RX VrefLevel [Byte0]: 65
7907 09:31:29.318443 [Byte1]: 65
7908 09:31:29.322772
7909 09:31:29.322867 Set Vref, RX VrefLevel [Byte0]: 66
7910 09:31:29.326360 [Byte1]: 66
7911 09:31:29.330549
7912 09:31:29.330644 Set Vref, RX VrefLevel [Byte0]: 67
7913 09:31:29.333447 [Byte1]: 67
7914 09:31:29.338117
7915 09:31:29.338208 Set Vref, RX VrefLevel [Byte0]: 68
7916 09:31:29.341127 [Byte1]: 68
7917 09:31:29.345760
7918 09:31:29.345885 Set Vref, RX VrefLevel [Byte0]: 69
7919 09:31:29.349033 [Byte1]: 69
7920 09:31:29.353282
7921 09:31:29.353399 Set Vref, RX VrefLevel [Byte0]: 70
7922 09:31:29.356353 [Byte1]: 70
7923 09:31:29.360520
7924 09:31:29.360646 Set Vref, RX VrefLevel [Byte0]: 71
7925 09:31:29.364199 [Byte1]: 71
7926 09:31:29.368189
7927 09:31:29.368313 Set Vref, RX VrefLevel [Byte0]: 72
7928 09:31:29.371585 [Byte1]: 72
7929 09:31:29.376474
7930 09:31:29.376604 Set Vref, RX VrefLevel [Byte0]: 73
7931 09:31:29.379335 [Byte1]: 73
7932 09:31:29.383580
7933 09:31:29.383684 Set Vref, RX VrefLevel [Byte0]: 74
7934 09:31:29.387043 [Byte1]: 74
7935 09:31:29.391358
7936 09:31:29.391500 Set Vref, RX VrefLevel [Byte0]: 75
7937 09:31:29.394514 [Byte1]: 75
7938 09:31:29.398693
7939 09:31:29.398804 Set Vref, RX VrefLevel [Byte0]: 76
7940 09:31:29.402435 [Byte1]: 76
7941 09:31:29.406485
7942 09:31:29.406614 Set Vref, RX VrefLevel [Byte0]: 77
7943 09:31:29.410056 [Byte1]: 77
7944 09:31:29.414065
7945 09:31:29.414219 Set Vref, RX VrefLevel [Byte0]: 78
7946 09:31:29.417918 [Byte1]: 78
7947 09:31:29.421843
7948 09:31:29.421985 Final RX Vref Byte 0 = 64 to rank0
7949 09:31:29.425391 Final RX Vref Byte 1 = 62 to rank0
7950 09:31:29.428152 Final RX Vref Byte 0 = 64 to rank1
7951 09:31:29.431311 Final RX Vref Byte 1 = 62 to rank1==
7952 09:31:29.434935 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 09:31:29.441422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 09:31:29.441534 ==
7955 09:31:29.441601 DQS Delay:
7956 09:31:29.441662 DQS0 = 0, DQS1 = 0
7957 09:31:29.444843 DQM Delay:
7958 09:31:29.444949 DQM0 = 126, DQM1 = 119
7959 09:31:29.448280 DQ Delay:
7960 09:31:29.451331 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7961 09:31:29.455000 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7962 09:31:29.458041 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7963 09:31:29.461449 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =126
7964 09:31:29.461549
7965 09:31:29.461615
7966 09:31:29.461675
7967 09:31:29.464913 [DramC_TX_OE_Calibration] TA2
7968 09:31:29.467906 Original DQ_B0 (3 6) =30, OEN = 27
7969 09:31:29.471258 Original DQ_B1 (3 6) =30, OEN = 27
7970 09:31:29.474926 24, 0x0, End_B0=24 End_B1=24
7971 09:31:29.475025 25, 0x0, End_B0=25 End_B1=25
7972 09:31:29.478289 26, 0x0, End_B0=26 End_B1=26
7973 09:31:29.481452 27, 0x0, End_B0=27 End_B1=27
7974 09:31:29.484528 28, 0x0, End_B0=28 End_B1=28
7975 09:31:29.488176 29, 0x0, End_B0=29 End_B1=29
7976 09:31:29.488274 30, 0x0, End_B0=30 End_B1=30
7977 09:31:29.491254 31, 0x4545, End_B0=30 End_B1=30
7978 09:31:29.494802 Byte0 end_step=30 best_step=27
7979 09:31:29.497653 Byte1 end_step=30 best_step=27
7980 09:31:29.501091 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 09:31:29.504427 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 09:31:29.504526
7983 09:31:29.504592
7984 09:31:29.511131 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7985 09:31:29.514633 CH0 RK0: MR19=303, MR18=1413
7986 09:31:29.521167 CH0_RK0: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
7987 09:31:29.521288
7988 09:31:29.524534 ----->DramcWriteLeveling(PI) begin...
7989 09:31:29.524632 ==
7990 09:31:29.527627 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 09:31:29.531151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 09:31:29.531279 ==
7993 09:31:29.534509 Write leveling (Byte 0): 36 => 36
7994 09:31:29.537894 Write leveling (Byte 1): 29 => 29
7995 09:31:29.540943 DramcWriteLeveling(PI) end<-----
7996 09:31:29.541044
7997 09:31:29.541110 ==
7998 09:31:29.544442 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 09:31:29.547443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 09:31:29.547568 ==
8001 09:31:29.551041 [Gating] SW mode calibration
8002 09:31:29.557511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 09:31:29.564170 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 09:31:29.567712 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 09:31:29.574177 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 09:31:29.577231 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 09:31:29.580748 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8008 09:31:29.587381 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8009 09:31:29.590719 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 09:31:29.594024 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 09:31:29.597545 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 09:31:29.604233 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 09:31:29.607372 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 09:31:29.611099 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8015 09:31:29.617595 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8016 09:31:29.620341 1 5 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8017 09:31:29.624163 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8018 09:31:29.630464 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 09:31:29.634141 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 09:31:29.637077 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 09:31:29.643669 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 09:31:29.647351 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8023 09:31:29.650319 1 6 12 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8024 09:31:29.656774 1 6 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8025 09:31:29.660156 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 09:31:29.663769 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 09:31:29.670313 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 09:31:29.673354 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 09:31:29.676896 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 09:31:29.683408 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 09:31:29.686984 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 09:31:29.689865 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8033 09:31:29.696999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 09:31:29.699987 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 09:31:29.703373 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 09:31:29.710175 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 09:31:29.713333 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 09:31:29.716417 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 09:31:29.723165 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 09:31:29.726682 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 09:31:29.729626 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 09:31:29.736431 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 09:31:29.739816 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 09:31:29.743256 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 09:31:29.749690 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 09:31:29.752895 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 09:31:29.756599 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8048 09:31:29.759966 Total UI for P1: 0, mck2ui 16
8049 09:31:29.763264 best dqsien dly found for B0: ( 1, 9, 6)
8050 09:31:29.769683 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 09:31:29.773170 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 09:31:29.776188 Total UI for P1: 0, mck2ui 16
8053 09:31:29.779788 best dqsien dly found for B1: ( 1, 9, 14)
8054 09:31:29.782847 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8055 09:31:29.786737 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8056 09:31:29.786841
8057 09:31:29.789876 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8058 09:31:29.792739 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8059 09:31:29.796301 [Gating] SW calibration Done
8060 09:31:29.796396 ==
8061 09:31:29.799319 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 09:31:29.802921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 09:31:29.803019 ==
8064 09:31:29.806060 RX Vref Scan: 0
8065 09:31:29.806181
8066 09:31:29.809348 RX Vref 0 -> 0, step: 1
8067 09:31:29.809434
8068 09:31:29.809500 RX Delay 0 -> 252, step: 8
8069 09:31:29.816045 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8070 09:31:29.819599 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8071 09:31:29.822914 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8072 09:31:29.825928 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8073 09:31:29.829459 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8074 09:31:29.835774 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8075 09:31:29.839290 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8076 09:31:29.842242 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8077 09:31:29.845701 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8078 09:31:29.849410 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8079 09:31:29.855665 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8080 09:31:29.858920 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8081 09:31:29.862250 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8082 09:31:29.865878 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8083 09:31:29.868933 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8084 09:31:29.875793 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8085 09:31:29.875949 ==
8086 09:31:29.879134 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 09:31:29.882136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 09:31:29.882234 ==
8089 09:31:29.882300 DQS Delay:
8090 09:31:29.885624 DQS0 = 0, DQS1 = 0
8091 09:31:29.885710 DQM Delay:
8092 09:31:29.889097 DQM0 = 127, DQM1 = 122
8093 09:31:29.889184 DQ Delay:
8094 09:31:29.892173 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8095 09:31:29.895723 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8096 09:31:29.898645 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8097 09:31:29.905212 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8098 09:31:29.905317
8099 09:31:29.905385
8100 09:31:29.905446 ==
8101 09:31:29.908860 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 09:31:29.912193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 09:31:29.912284 ==
8104 09:31:29.912351
8105 09:31:29.912412
8106 09:31:29.915176 TX Vref Scan disable
8107 09:31:29.915262 == TX Byte 0 ==
8108 09:31:29.921629 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8109 09:31:29.925333 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8110 09:31:29.925433 == TX Byte 1 ==
8111 09:31:29.931838 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8112 09:31:29.935232 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8113 09:31:29.935331 ==
8114 09:31:29.938420 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 09:31:29.941517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 09:31:29.941614 ==
8117 09:31:29.957568
8118 09:31:29.960996 TX Vref early break, caculate TX vref
8119 09:31:29.963899 TX Vref=16, minBit 8, minWin=22, winSum=374
8120 09:31:29.967563 TX Vref=18, minBit 8, minWin=22, winSum=383
8121 09:31:29.970521 TX Vref=20, minBit 8, minWin=23, winSum=391
8122 09:31:29.974310 TX Vref=22, minBit 8, minWin=23, winSum=397
8123 09:31:29.977105 TX Vref=24, minBit 2, minWin=25, winSum=410
8124 09:31:29.984200 TX Vref=26, minBit 2, minWin=25, winSum=414
8125 09:31:29.987287 TX Vref=28, minBit 8, minWin=25, winSum=417
8126 09:31:29.990769 TX Vref=30, minBit 3, minWin=25, winSum=412
8127 09:31:29.993824 TX Vref=32, minBit 8, minWin=24, winSum=413
8128 09:31:29.997154 TX Vref=34, minBit 8, minWin=22, winSum=399
8129 09:31:30.000736 TX Vref=36, minBit 8, minWin=23, winSum=390
8130 09:31:30.007214 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8131 09:31:30.007341
8132 09:31:30.010743 Final TX Range 0 Vref 28
8133 09:31:30.010838
8134 09:31:30.010905 ==
8135 09:31:30.013855 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 09:31:30.017807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 09:31:30.017913 ==
8138 09:31:30.017980
8139 09:31:30.018039
8140 09:31:30.020656 TX Vref Scan disable
8141 09:31:30.027107 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8142 09:31:30.027246 == TX Byte 0 ==
8143 09:31:30.030556 u2DelayCellOfst[0]=15 cells (4 PI)
8144 09:31:30.033754 u2DelayCellOfst[1]=18 cells (5 PI)
8145 09:31:30.037301 u2DelayCellOfst[2]=11 cells (3 PI)
8146 09:31:30.040107 u2DelayCellOfst[3]=11 cells (3 PI)
8147 09:31:30.043732 u2DelayCellOfst[4]=7 cells (2 PI)
8148 09:31:30.047111 u2DelayCellOfst[5]=0 cells (0 PI)
8149 09:31:30.050636 u2DelayCellOfst[6]=18 cells (5 PI)
8150 09:31:30.053351 u2DelayCellOfst[7]=18 cells (5 PI)
8151 09:31:30.056911 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8152 09:31:30.060368 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8153 09:31:30.063645 == TX Byte 1 ==
8154 09:31:30.066967 u2DelayCellOfst[8]=0 cells (0 PI)
8155 09:31:30.070164 u2DelayCellOfst[9]=0 cells (0 PI)
8156 09:31:30.073776 u2DelayCellOfst[10]=3 cells (1 PI)
8157 09:31:30.073886 u2DelayCellOfst[11]=3 cells (1 PI)
8158 09:31:30.076657 u2DelayCellOfst[12]=7 cells (2 PI)
8159 09:31:30.079829 u2DelayCellOfst[13]=11 cells (3 PI)
8160 09:31:30.083317 u2DelayCellOfst[14]=15 cells (4 PI)
8161 09:31:30.086583 u2DelayCellOfst[15]=7 cells (2 PI)
8162 09:31:30.093552 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8163 09:31:30.097106 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8164 09:31:30.097215 DramC Write-DBI on
8165 09:31:30.097281 ==
8166 09:31:30.099880 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 09:31:30.106526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 09:31:30.106640 ==
8169 09:31:30.106707
8170 09:31:30.106766
8171 09:31:30.106823 TX Vref Scan disable
8172 09:31:30.111002 == TX Byte 0 ==
8173 09:31:30.114221 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8174 09:31:30.117602 == TX Byte 1 ==
8175 09:31:30.120568 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8176 09:31:30.124142 DramC Write-DBI off
8177 09:31:30.124266
8178 09:31:30.124359 [DATLAT]
8179 09:31:30.124447 Freq=1600, CH0 RK1
8180 09:31:30.124532
8181 09:31:30.127765 DATLAT Default: 0xf
8182 09:31:30.127847 0, 0xFFFF, sum = 0
8183 09:31:30.130623 1, 0xFFFF, sum = 0
8184 09:31:30.134004 2, 0xFFFF, sum = 0
8185 09:31:30.134137 3, 0xFFFF, sum = 0
8186 09:31:30.137153 4, 0xFFFF, sum = 0
8187 09:31:30.137262 5, 0xFFFF, sum = 0
8188 09:31:30.140700 6, 0xFFFF, sum = 0
8189 09:31:30.140801 7, 0xFFFF, sum = 0
8190 09:31:30.143666 8, 0xFFFF, sum = 0
8191 09:31:30.143754 9, 0xFFFF, sum = 0
8192 09:31:30.147160 10, 0xFFFF, sum = 0
8193 09:31:30.147317 11, 0xFFFF, sum = 0
8194 09:31:30.150582 12, 0xFFFF, sum = 0
8195 09:31:30.150731 13, 0xCFFF, sum = 0
8196 09:31:30.154171 14, 0x0, sum = 1
8197 09:31:30.154284 15, 0x0, sum = 2
8198 09:31:30.156991 16, 0x0, sum = 3
8199 09:31:30.157096 17, 0x0, sum = 4
8200 09:31:30.160508 best_step = 15
8201 09:31:30.160601
8202 09:31:30.160667 ==
8203 09:31:30.163512 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 09:31:30.167052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 09:31:30.167179 ==
8206 09:31:30.170173 RX Vref Scan: 0
8207 09:31:30.170262
8208 09:31:30.170357 RX Vref 0 -> 0, step: 1
8209 09:31:30.170458
8210 09:31:30.173691 RX Delay 3 -> 252, step: 4
8211 09:31:30.177103 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8212 09:31:30.183849 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8213 09:31:30.187121 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8214 09:31:30.190415 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8215 09:31:30.193378 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8216 09:31:30.196912 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8217 09:31:30.203665 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8218 09:31:30.207229 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8219 09:31:30.210136 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8220 09:31:30.213604 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8221 09:31:30.217123 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8222 09:31:30.223286 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8223 09:31:30.226663 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8224 09:31:30.230102 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8225 09:31:30.233679 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8226 09:31:30.240216 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8227 09:31:30.240365 ==
8228 09:31:30.243157 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 09:31:30.246688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 09:31:30.246790 ==
8231 09:31:30.246857 DQS Delay:
8232 09:31:30.250444 DQS0 = 0, DQS1 = 0
8233 09:31:30.250540 DQM Delay:
8234 09:31:30.253175 DQM0 = 124, DQM1 = 117
8235 09:31:30.253266 DQ Delay:
8236 09:31:30.256426 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8237 09:31:30.260099 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8238 09:31:30.263111 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8239 09:31:30.266697 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8240 09:31:30.266803
8241 09:31:30.266873
8242 09:31:30.269614
8243 09:31:30.269702 [DramC_TX_OE_Calibration] TA2
8244 09:31:30.273272 Original DQ_B0 (3 6) =30, OEN = 27
8245 09:31:30.276188 Original DQ_B1 (3 6) =30, OEN = 27
8246 09:31:30.279884 24, 0x0, End_B0=24 End_B1=24
8247 09:31:30.282766 25, 0x0, End_B0=25 End_B1=25
8248 09:31:30.286562 26, 0x0, End_B0=26 End_B1=26
8249 09:31:30.286701 27, 0x0, End_B0=27 End_B1=27
8250 09:31:30.289675 28, 0x0, End_B0=28 End_B1=28
8251 09:31:30.292921 29, 0x0, End_B0=29 End_B1=29
8252 09:31:30.296057 30, 0x0, End_B0=30 End_B1=30
8253 09:31:30.299906 31, 0x4141, End_B0=30 End_B1=30
8254 09:31:30.300014 Byte0 end_step=30 best_step=27
8255 09:31:30.303119 Byte1 end_step=30 best_step=27
8256 09:31:30.305926 Byte0 TX OE(2T, 0.5T) = (3, 3)
8257 09:31:30.309361 Byte1 TX OE(2T, 0.5T) = (3, 3)
8258 09:31:30.309462
8259 09:31:30.309529
8260 09:31:30.316268 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8261 09:31:30.319804 CH0 RK1: MR19=303, MR18=2411
8262 09:31:30.326276 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8263 09:31:30.329285 [RxdqsGatingPostProcess] freq 1600
8264 09:31:30.336044 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8265 09:31:30.339706 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 09:31:30.339822 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 09:31:30.342935 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 09:31:30.345903 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 09:31:30.349294 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 09:31:30.352897 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 09:31:30.355813 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 09:31:30.359240 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 09:31:30.362502 Pre-setting of DQS Precalculation
8274 09:31:30.366030 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8275 09:31:30.369066 ==
8276 09:31:30.372611 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 09:31:30.375667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 09:31:30.375771 ==
8279 09:31:30.379292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 09:31:30.385781 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 09:31:30.389320 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 09:31:30.395833 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 09:31:30.403894 [CA 0] Center 42 (13~71) winsize 59
8284 09:31:30.407050 [CA 1] Center 42 (13~72) winsize 60
8285 09:31:30.410629 [CA 2] Center 37 (9~66) winsize 58
8286 09:31:30.413969 [CA 3] Center 36 (7~66) winsize 60
8287 09:31:30.417378 [CA 4] Center 37 (8~67) winsize 60
8288 09:31:30.420695 [CA 5] Center 36 (7~66) winsize 60
8289 09:31:30.420799
8290 09:31:30.423635 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 09:31:30.423727
8292 09:31:30.426867 [CATrainingPosCal] consider 1 rank data
8293 09:31:30.430309 u2DelayCellTimex100 = 258/100 ps
8294 09:31:30.434011 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8295 09:31:30.440430 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8296 09:31:30.443817 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8297 09:31:30.447257 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 09:31:30.450756 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8299 09:31:30.453836 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 09:31:30.453946
8301 09:31:30.457028 CA PerBit enable=1, Macro0, CA PI delay=36
8302 09:31:30.457130
8303 09:31:30.460201 [CBTSetCACLKResult] CA Dly = 36
8304 09:31:30.463804 CS Dly: 9 (0~40)
8305 09:31:30.467283 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 09:31:30.470229 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 09:31:30.470336 ==
8308 09:31:30.473770 Dram Type= 6, Freq= 0, CH_1, rank 1
8309 09:31:30.476650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 09:31:30.476832 ==
8311 09:31:30.483847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 09:31:30.486823 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 09:31:30.493270 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 09:31:30.496817 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 09:31:30.506973 [CA 0] Center 42 (12~72) winsize 61
8316 09:31:30.510323 [CA 1] Center 42 (12~72) winsize 61
8317 09:31:30.513938 [CA 2] Center 38 (9~67) winsize 59
8318 09:31:30.516989 [CA 3] Center 36 (7~66) winsize 60
8319 09:31:30.520591 [CA 4] Center 38 (8~68) winsize 61
8320 09:31:30.523454 [CA 5] Center 36 (6~66) winsize 61
8321 09:31:30.523561
8322 09:31:30.527143 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8323 09:31:30.527242
8324 09:31:30.530361 [CATrainingPosCal] consider 2 rank data
8325 09:31:30.533518 u2DelayCellTimex100 = 258/100 ps
8326 09:31:30.536674 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8327 09:31:30.543592 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8328 09:31:30.546661 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8329 09:31:30.550454 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 09:31:30.553547 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8331 09:31:30.556721 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8332 09:31:30.556833
8333 09:31:30.560109 CA PerBit enable=1, Macro0, CA PI delay=36
8334 09:31:30.560203
8335 09:31:30.563373 [CBTSetCACLKResult] CA Dly = 36
8336 09:31:30.566958 CS Dly: 10 (0~43)
8337 09:31:30.570067 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 09:31:30.573483 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 09:31:30.573587
8340 09:31:30.576561 ----->DramcWriteLeveling(PI) begin...
8341 09:31:30.576663 ==
8342 09:31:30.580209 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 09:31:30.583159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 09:31:30.586689 ==
8345 09:31:30.586791 Write leveling (Byte 0): 23 => 23
8346 09:31:30.589689 Write leveling (Byte 1): 28 => 28
8347 09:31:30.593205 DramcWriteLeveling(PI) end<-----
8348 09:31:30.593302
8349 09:31:30.593367 ==
8350 09:31:30.596716 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 09:31:30.603347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 09:31:30.603510 ==
8353 09:31:30.606878 [Gating] SW mode calibration
8354 09:31:30.613293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8355 09:31:30.616250 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8356 09:31:30.623171 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 09:31:30.626523 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 09:31:30.629920 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 09:31:30.636574 1 4 12 | B1->B0 | 2525 2322 | 0 1 | (1 1) (0 0)
8360 09:31:30.639276 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8361 09:31:30.642765 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 09:31:30.649820 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 09:31:30.652710 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 09:31:30.656297 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 09:31:30.662393 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 09:31:30.665988 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 09:31:30.669229 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8368 09:31:30.675977 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (1 0) (1 0)
8369 09:31:30.679369 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 09:31:30.682471 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 09:31:30.689120 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 09:31:30.692612 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 09:31:30.695737 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 09:31:30.702260 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 09:31:30.705838 1 6 12 | B1->B0 | 2b2b 2424 | 0 1 | (0 0) (0 0)
8376 09:31:30.709344 1 6 16 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
8377 09:31:30.712442 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 09:31:30.719114 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 09:31:30.722717 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 09:31:30.725743 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 09:31:30.732278 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 09:31:30.735695 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 09:31:30.738782 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 09:31:30.745552 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 09:31:30.748970 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 09:31:30.751991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 09:31:30.759098 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 09:31:30.762042 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 09:31:30.765121 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 09:31:30.771851 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 09:31:30.775651 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 09:31:30.778750 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 09:31:30.785303 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 09:31:30.788538 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 09:31:30.791911 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 09:31:30.798152 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 09:31:30.801717 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 09:31:30.804796 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 09:31:30.811338 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8400 09:31:30.814933 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 09:31:30.818039 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 09:31:30.821592 Total UI for P1: 0, mck2ui 16
8403 09:31:30.825092 best dqsien dly found for B0: ( 1, 9, 14)
8404 09:31:30.827864 Total UI for P1: 0, mck2ui 16
8405 09:31:30.831542 best dqsien dly found for B1: ( 1, 9, 16)
8406 09:31:30.834902 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8407 09:31:30.838227 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8408 09:31:30.838356
8409 09:31:30.844605 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8410 09:31:30.848177 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 09:31:30.851031 [Gating] SW calibration Done
8412 09:31:30.851146 ==
8413 09:31:30.854981 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 09:31:30.857921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 09:31:30.858037 ==
8416 09:31:30.858105 RX Vref Scan: 0
8417 09:31:30.861263
8418 09:31:30.861366 RX Vref 0 -> 0, step: 1
8419 09:31:30.861434
8420 09:31:30.864270 RX Delay 0 -> 252, step: 8
8421 09:31:30.867786 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8422 09:31:30.871347 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8423 09:31:30.877902 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8424 09:31:30.881409 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8425 09:31:30.884273 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8426 09:31:30.888180 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 09:31:30.891342 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8428 09:31:30.897696 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8429 09:31:30.901137 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8430 09:31:30.904572 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8431 09:31:30.907706 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8432 09:31:30.911012 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8433 09:31:30.917845 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8434 09:31:30.920831 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8435 09:31:30.924018 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 09:31:30.927548 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8437 09:31:30.927662 ==
8438 09:31:30.931110 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 09:31:30.937562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 09:31:30.937717 ==
8441 09:31:30.937797 DQS Delay:
8442 09:31:30.937911 DQS0 = 0, DQS1 = 0
8443 09:31:30.941069 DQM Delay:
8444 09:31:30.941157 DQM0 = 131, DQM1 = 126
8445 09:31:30.944150 DQ Delay:
8446 09:31:30.947564 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8447 09:31:30.950471 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8448 09:31:30.954119 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8449 09:31:30.957348 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8450 09:31:30.957456
8451 09:31:30.957522
8452 09:31:30.957581 ==
8453 09:31:30.960713 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 09:31:30.964320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 09:31:30.967358 ==
8456 09:31:30.967502
8457 09:31:30.967568
8458 09:31:30.967628 TX Vref Scan disable
8459 09:31:30.970778 == TX Byte 0 ==
8460 09:31:30.973941 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8461 09:31:30.976841 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8462 09:31:30.980207 == TX Byte 1 ==
8463 09:31:30.983940 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8464 09:31:30.987330 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8465 09:31:30.990309 ==
8466 09:31:30.994005 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 09:31:30.996976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 09:31:30.997085 ==
8469 09:31:31.010234
8470 09:31:31.013684 TX Vref early break, caculate TX vref
8471 09:31:31.016988 TX Vref=16, minBit 5, minWin=21, winSum=357
8472 09:31:31.020256 TX Vref=18, minBit 1, minWin=22, winSum=372
8473 09:31:31.023590 TX Vref=20, minBit 1, minWin=23, winSum=382
8474 09:31:31.026812 TX Vref=22, minBit 13, minWin=23, winSum=391
8475 09:31:31.030116 TX Vref=24, minBit 8, minWin=24, winSum=405
8476 09:31:31.037032 TX Vref=26, minBit 0, minWin=25, winSum=412
8477 09:31:31.040026 TX Vref=28, minBit 6, minWin=24, winSum=415
8478 09:31:31.043608 TX Vref=30, minBit 0, minWin=24, winSum=412
8479 09:31:31.047185 TX Vref=32, minBit 0, minWin=23, winSum=403
8480 09:31:31.050306 TX Vref=34, minBit 0, minWin=23, winSum=395
8481 09:31:31.053222 TX Vref=36, minBit 5, minWin=22, winSum=380
8482 09:31:31.059959 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
8483 09:31:31.060156
8484 09:31:31.063304 Final TX Range 0 Vref 26
8485 09:31:31.063426
8486 09:31:31.063509 ==
8487 09:31:31.066845 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 09:31:31.069780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 09:31:31.069889 ==
8490 09:31:31.069954
8491 09:31:31.073308
8492 09:31:31.073399 TX Vref Scan disable
8493 09:31:31.079850 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8494 09:31:31.079974 == TX Byte 0 ==
8495 09:31:31.083370 u2DelayCellOfst[0]=18 cells (5 PI)
8496 09:31:31.086417 u2DelayCellOfst[1]=11 cells (3 PI)
8497 09:31:31.089897 u2DelayCellOfst[2]=0 cells (0 PI)
8498 09:31:31.093534 u2DelayCellOfst[3]=3 cells (1 PI)
8499 09:31:31.096383 u2DelayCellOfst[4]=7 cells (2 PI)
8500 09:31:31.100002 u2DelayCellOfst[5]=22 cells (6 PI)
8501 09:31:31.103549 u2DelayCellOfst[6]=18 cells (5 PI)
8502 09:31:31.107064 u2DelayCellOfst[7]=3 cells (1 PI)
8503 09:31:31.109993 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 09:31:31.113440 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8505 09:31:31.116357 == TX Byte 1 ==
8506 09:31:31.120124 u2DelayCellOfst[8]=0 cells (0 PI)
8507 09:31:31.120280 u2DelayCellOfst[9]=7 cells (2 PI)
8508 09:31:31.123118 u2DelayCellOfst[10]=18 cells (5 PI)
8509 09:31:31.126331 u2DelayCellOfst[11]=11 cells (3 PI)
8510 09:31:31.129611 u2DelayCellOfst[12]=18 cells (5 PI)
8511 09:31:31.133085 u2DelayCellOfst[13]=22 cells (6 PI)
8512 09:31:31.136388 u2DelayCellOfst[14]=22 cells (6 PI)
8513 09:31:31.139633 u2DelayCellOfst[15]=22 cells (6 PI)
8514 09:31:31.146045 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8515 09:31:31.149725 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 09:31:31.149924 DramC Write-DBI on
8517 09:31:31.150063 ==
8518 09:31:31.153270 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 09:31:31.159862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 09:31:31.160082 ==
8521 09:31:31.160215
8522 09:31:31.160341
8523 09:31:31.160459 TX Vref Scan disable
8524 09:31:31.163604 == TX Byte 0 ==
8525 09:31:31.167010 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8526 09:31:31.170238 == TX Byte 1 ==
8527 09:31:31.173760 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 09:31:31.176726 DramC Write-DBI off
8529 09:31:31.176866
8530 09:31:31.176992 [DATLAT]
8531 09:31:31.177112 Freq=1600, CH1 RK0
8532 09:31:31.177231
8533 09:31:31.180324 DATLAT Default: 0xf
8534 09:31:31.180461 0, 0xFFFF, sum = 0
8535 09:31:31.183315 1, 0xFFFF, sum = 0
8536 09:31:31.186906 2, 0xFFFF, sum = 0
8537 09:31:31.187053 3, 0xFFFF, sum = 0
8538 09:31:31.190294 4, 0xFFFF, sum = 0
8539 09:31:31.190434 5, 0xFFFF, sum = 0
8540 09:31:31.193441 6, 0xFFFF, sum = 0
8541 09:31:31.193587 7, 0xFFFF, sum = 0
8542 09:31:31.196952 8, 0xFFFF, sum = 0
8543 09:31:31.197094 9, 0xFFFF, sum = 0
8544 09:31:31.199939 10, 0xFFFF, sum = 0
8545 09:31:31.200079 11, 0xFFFF, sum = 0
8546 09:31:31.203502 12, 0xFFFF, sum = 0
8547 09:31:31.203651 13, 0x8FFF, sum = 0
8548 09:31:31.207076 14, 0x0, sum = 1
8549 09:31:31.207222 15, 0x0, sum = 2
8550 09:31:31.210147 16, 0x0, sum = 3
8551 09:31:31.210297 17, 0x0, sum = 4
8552 09:31:31.213153 best_step = 15
8553 09:31:31.213293
8554 09:31:31.213415 ==
8555 09:31:31.216517 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 09:31:31.219995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 09:31:31.220153 ==
8558 09:31:31.223592 RX Vref Scan: 1
8559 09:31:31.223733
8560 09:31:31.223853 Set Vref Range= 24 -> 127
8561 09:31:31.223972
8562 09:31:31.226551 RX Vref 24 -> 127, step: 1
8563 09:31:31.226682
8564 09:31:31.229978 RX Delay 11 -> 252, step: 4
8565 09:31:31.230114
8566 09:31:31.233471 Set Vref, RX VrefLevel [Byte0]: 24
8567 09:31:31.236587 [Byte1]: 24
8568 09:31:31.236758
8569 09:31:31.239948 Set Vref, RX VrefLevel [Byte0]: 25
8570 09:31:31.243598 [Byte1]: 25
8571 09:31:31.243780
8572 09:31:31.246558 Set Vref, RX VrefLevel [Byte0]: 26
8573 09:31:31.249847 [Byte1]: 26
8574 09:31:31.254275
8575 09:31:31.254410 Set Vref, RX VrefLevel [Byte0]: 27
8576 09:31:31.257449 [Byte1]: 27
8577 09:31:31.262005
8578 09:31:31.262141 Set Vref, RX VrefLevel [Byte0]: 28
8579 09:31:31.264760 [Byte1]: 28
8580 09:31:31.269255
8581 09:31:31.269387 Set Vref, RX VrefLevel [Byte0]: 29
8582 09:31:31.272363 [Byte1]: 29
8583 09:31:31.276735
8584 09:31:31.276868 Set Vref, RX VrefLevel [Byte0]: 30
8585 09:31:31.280337 [Byte1]: 30
8586 09:31:31.284456
8587 09:31:31.284588 Set Vref, RX VrefLevel [Byte0]: 31
8588 09:31:31.287985 [Byte1]: 31
8589 09:31:31.292099
8590 09:31:31.292226 Set Vref, RX VrefLevel [Byte0]: 32
8591 09:31:31.295616 [Byte1]: 32
8592 09:31:31.299722
8593 09:31:31.299839 Set Vref, RX VrefLevel [Byte0]: 33
8594 09:31:31.303308 [Byte1]: 33
8595 09:31:31.307556
8596 09:31:31.307651 Set Vref, RX VrefLevel [Byte0]: 34
8597 09:31:31.310440 [Byte1]: 34
8598 09:31:31.315074
8599 09:31:31.315170 Set Vref, RX VrefLevel [Byte0]: 35
8600 09:31:31.318040 [Byte1]: 35
8601 09:31:31.322473
8602 09:31:31.322573 Set Vref, RX VrefLevel [Byte0]: 36
8603 09:31:31.326091 [Byte1]: 36
8604 09:31:31.330218
8605 09:31:31.330318 Set Vref, RX VrefLevel [Byte0]: 37
8606 09:31:31.333225 [Byte1]: 37
8607 09:31:31.337898
8608 09:31:31.338002 Set Vref, RX VrefLevel [Byte0]: 38
8609 09:31:31.341462 [Byte1]: 38
8610 09:31:31.345558
8611 09:31:31.345662 Set Vref, RX VrefLevel [Byte0]: 39
8612 09:31:31.348955 [Byte1]: 39
8613 09:31:31.353209
8614 09:31:31.353328 Set Vref, RX VrefLevel [Byte0]: 40
8615 09:31:31.356041 [Byte1]: 40
8616 09:31:31.360674
8617 09:31:31.360780 Set Vref, RX VrefLevel [Byte0]: 41
8618 09:31:31.364022 [Byte1]: 41
8619 09:31:31.367949
8620 09:31:31.368049 Set Vref, RX VrefLevel [Byte0]: 42
8621 09:31:31.371406 [Byte1]: 42
8622 09:31:31.375876
8623 09:31:31.375985 Set Vref, RX VrefLevel [Byte0]: 43
8624 09:31:31.379006 [Byte1]: 43
8625 09:31:31.383811
8626 09:31:31.383918 Set Vref, RX VrefLevel [Byte0]: 44
8627 09:31:31.387048 [Byte1]: 44
8628 09:31:31.390912
8629 09:31:31.391010 Set Vref, RX VrefLevel [Byte0]: 45
8630 09:31:31.397384 [Byte1]: 45
8631 09:31:31.397494
8632 09:31:31.400535 Set Vref, RX VrefLevel [Byte0]: 46
8633 09:31:31.404321 [Byte1]: 46
8634 09:31:31.404428
8635 09:31:31.407210 Set Vref, RX VrefLevel [Byte0]: 47
8636 09:31:31.410951 [Byte1]: 47
8637 09:31:31.414345
8638 09:31:31.414438 Set Vref, RX VrefLevel [Byte0]: 48
8639 09:31:31.417346 [Byte1]: 48
8640 09:31:31.421538
8641 09:31:31.421637 Set Vref, RX VrefLevel [Byte0]: 49
8642 09:31:31.424989 [Byte1]: 49
8643 09:31:31.428916
8644 09:31:31.429019 Set Vref, RX VrefLevel [Byte0]: 50
8645 09:31:31.432459 [Byte1]: 50
8646 09:31:31.436666
8647 09:31:31.436764 Set Vref, RX VrefLevel [Byte0]: 51
8648 09:31:31.440214 [Byte1]: 51
8649 09:31:31.444528
8650 09:31:31.444642 Set Vref, RX VrefLevel [Byte0]: 52
8651 09:31:31.447611 [Byte1]: 52
8652 09:31:31.452302
8653 09:31:31.452404 Set Vref, RX VrefLevel [Byte0]: 53
8654 09:31:31.455305 [Byte1]: 53
8655 09:31:31.459839
8656 09:31:31.459939 Set Vref, RX VrefLevel [Byte0]: 54
8657 09:31:31.462759 [Byte1]: 54
8658 09:31:31.467196
8659 09:31:31.467390 Set Vref, RX VrefLevel [Byte0]: 55
8660 09:31:31.470371 [Byte1]: 55
8661 09:31:31.474895
8662 09:31:31.475065 Set Vref, RX VrefLevel [Byte0]: 56
8663 09:31:31.478332 [Byte1]: 56
8664 09:31:31.482559
8665 09:31:31.482738 Set Vref, RX VrefLevel [Byte0]: 57
8666 09:31:31.485906 [Byte1]: 57
8667 09:31:31.489767
8668 09:31:31.489939 Set Vref, RX VrefLevel [Byte0]: 58
8669 09:31:31.493346 [Byte1]: 58
8670 09:31:31.497406
8671 09:31:31.497584 Set Vref, RX VrefLevel [Byte0]: 59
8672 09:31:31.500971 [Byte1]: 59
8673 09:31:31.505010
8674 09:31:31.505182 Set Vref, RX VrefLevel [Byte0]: 60
8675 09:31:31.508697 [Byte1]: 60
8676 09:31:31.513165
8677 09:31:31.513285 Set Vref, RX VrefLevel [Byte0]: 61
8678 09:31:31.516225 [Byte1]: 61
8679 09:31:31.520502
8680 09:31:31.520598 Set Vref, RX VrefLevel [Byte0]: 62
8681 09:31:31.524299 [Byte1]: 62
8682 09:31:31.528045
8683 09:31:31.528144 Set Vref, RX VrefLevel [Byte0]: 63
8684 09:31:31.531639 [Byte1]: 63
8685 09:31:31.535782
8686 09:31:31.535878 Set Vref, RX VrefLevel [Byte0]: 64
8687 09:31:31.538679 [Byte1]: 64
8688 09:31:31.543418
8689 09:31:31.543525 Set Vref, RX VrefLevel [Byte0]: 65
8690 09:31:31.546450 [Byte1]: 65
8691 09:31:31.551158
8692 09:31:31.551251 Set Vref, RX VrefLevel [Byte0]: 66
8693 09:31:31.554164 [Byte1]: 66
8694 09:31:31.558444
8695 09:31:31.558534 Set Vref, RX VrefLevel [Byte0]: 67
8696 09:31:31.561879 [Byte1]: 67
8697 09:31:31.566081
8698 09:31:31.566174 Set Vref, RX VrefLevel [Byte0]: 68
8699 09:31:31.569441 [Byte1]: 68
8700 09:31:31.573539
8701 09:31:31.573646 Set Vref, RX VrefLevel [Byte0]: 69
8702 09:31:31.577034 [Byte1]: 69
8703 09:31:31.581178
8704 09:31:31.581284 Final RX Vref Byte 0 = 58 to rank0
8705 09:31:31.584773 Final RX Vref Byte 1 = 56 to rank0
8706 09:31:31.587749 Final RX Vref Byte 0 = 58 to rank1
8707 09:31:31.591305 Final RX Vref Byte 1 = 56 to rank1==
8708 09:31:31.594406 Dram Type= 6, Freq= 0, CH_1, rank 0
8709 09:31:31.601547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 09:31:31.601694 ==
8711 09:31:31.601763 DQS Delay:
8712 09:31:31.601825 DQS0 = 0, DQS1 = 0
8713 09:31:31.604388 DQM Delay:
8714 09:31:31.604475 DQM0 = 131, DQM1 = 123
8715 09:31:31.608196 DQ Delay:
8716 09:31:31.611018 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8717 09:31:31.614678 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8718 09:31:31.617758 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8719 09:31:31.621093 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8720 09:31:31.621210
8721 09:31:31.621299
8722 09:31:31.621361
8723 09:31:31.624464 [DramC_TX_OE_Calibration] TA2
8724 09:31:31.627732 Original DQ_B0 (3 6) =30, OEN = 27
8725 09:31:31.630748 Original DQ_B1 (3 6) =30, OEN = 27
8726 09:31:31.634095 24, 0x0, End_B0=24 End_B1=24
8727 09:31:31.634196 25, 0x0, End_B0=25 End_B1=25
8728 09:31:31.637729 26, 0x0, End_B0=26 End_B1=26
8729 09:31:31.641146 27, 0x0, End_B0=27 End_B1=27
8730 09:31:31.644290 28, 0x0, End_B0=28 End_B1=28
8731 09:31:31.647272 29, 0x0, End_B0=29 End_B1=29
8732 09:31:31.647427 30, 0x0, End_B0=30 End_B1=30
8733 09:31:31.650617 31, 0x4141, End_B0=30 End_B1=30
8734 09:31:31.654153 Byte0 end_step=30 best_step=27
8735 09:31:31.657693 Byte1 end_step=30 best_step=27
8736 09:31:31.660680 Byte0 TX OE(2T, 0.5T) = (3, 3)
8737 09:31:31.664222 Byte1 TX OE(2T, 0.5T) = (3, 3)
8738 09:31:31.664316
8739 09:31:31.664384
8740 09:31:31.670652 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8741 09:31:31.674007 CH1 RK0: MR19=303, MR18=90E
8742 09:31:31.681206 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8743 09:31:31.681338
8744 09:31:31.684190 ----->DramcWriteLeveling(PI) begin...
8745 09:31:31.684285 ==
8746 09:31:31.687684 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 09:31:31.690717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 09:31:31.690816 ==
8749 09:31:31.694034 Write leveling (Byte 0): 25 => 25
8750 09:31:31.697226 Write leveling (Byte 1): 28 => 28
8751 09:31:31.700760 DramcWriteLeveling(PI) end<-----
8752 09:31:31.700881
8753 09:31:31.700948 ==
8754 09:31:31.703875 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 09:31:31.707006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 09:31:31.707114 ==
8757 09:31:31.710553 [Gating] SW mode calibration
8758 09:31:31.716886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8759 09:31:31.723778 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8760 09:31:31.727244 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 09:31:31.733892 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 09:31:31.737239 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8763 09:31:31.740312 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8764 09:31:31.743563 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 09:31:31.749958 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 09:31:31.753618 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 09:31:31.760064 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 09:31:31.763635 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 09:31:31.766674 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8770 09:31:31.773082 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8771 09:31:31.776501 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8772 09:31:31.779953 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8773 09:31:31.783005 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 09:31:31.789959 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 09:31:31.792975 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 09:31:31.796533 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 09:31:31.802994 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8778 09:31:31.806353 1 6 8 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8779 09:31:31.809532 1 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8780 09:31:31.816123 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 09:31:31.819767 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 09:31:31.822956 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 09:31:31.829525 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 09:31:31.832561 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 09:31:31.836161 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 09:31:31.842661 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8787 09:31:31.846184 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8788 09:31:31.848994 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 09:31:31.855657 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 09:31:31.859056 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 09:31:31.862534 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 09:31:31.869295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 09:31:31.872206 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 09:31:31.875916 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 09:31:31.882423 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 09:31:31.885637 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 09:31:31.888609 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 09:31:31.895664 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 09:31:31.898706 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 09:31:31.902137 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 09:31:31.908676 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8802 09:31:31.912301 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8803 09:31:31.915578 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8804 09:31:31.918652 Total UI for P1: 0, mck2ui 16
8805 09:31:31.922227 best dqsien dly found for B0: ( 1, 9, 6)
8806 09:31:31.928567 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 09:31:31.928717 Total UI for P1: 0, mck2ui 16
8808 09:31:31.935251 best dqsien dly found for B1: ( 1, 9, 10)
8809 09:31:31.938949 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8810 09:31:31.942349 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8811 09:31:31.942471
8812 09:31:31.945346 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8813 09:31:31.948904 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8814 09:31:31.952006 [Gating] SW calibration Done
8815 09:31:31.952134 ==
8816 09:31:31.955339 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 09:31:31.958597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 09:31:31.958691 ==
8819 09:31:31.962018 RX Vref Scan: 0
8820 09:31:31.962112
8821 09:31:31.962185 RX Vref 0 -> 0, step: 1
8822 09:31:31.962249
8823 09:31:31.965389 RX Delay 0 -> 252, step: 8
8824 09:31:31.968381 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8825 09:31:31.975347 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8826 09:31:31.978351 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8827 09:31:31.981785 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8828 09:31:31.984874 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8829 09:31:31.988514 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8830 09:31:31.995014 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8831 09:31:31.998528 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8832 09:31:32.001385 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8833 09:31:32.005058 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8834 09:31:32.008093 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8835 09:31:32.015103 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8836 09:31:32.018210 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8837 09:31:32.021636 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8838 09:31:32.024897 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8839 09:31:32.028127 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8840 09:31:32.031263 ==
8841 09:31:32.034996 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 09:31:32.038473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 09:31:32.038586 ==
8844 09:31:32.038678 DQS Delay:
8845 09:31:32.041411 DQS0 = 0, DQS1 = 0
8846 09:31:32.041500 DQM Delay:
8847 09:31:32.044655 DQM0 = 132, DQM1 = 127
8848 09:31:32.044744 DQ Delay:
8849 09:31:32.047931 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8850 09:31:32.051275 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8851 09:31:32.054902 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8852 09:31:32.058412 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8853 09:31:32.058535
8854 09:31:32.058621
8855 09:31:32.058702 ==
8856 09:31:32.061299 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 09:31:32.068002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 09:31:32.068111 ==
8859 09:31:32.068201
8860 09:31:32.068282
8861 09:31:32.068361 TX Vref Scan disable
8862 09:31:32.071876 == TX Byte 0 ==
8863 09:31:32.074964 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8864 09:31:32.081775 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8865 09:31:32.081891 == TX Byte 1 ==
8866 09:31:32.085219 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8867 09:31:32.088198 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8868 09:31:32.091565 ==
8869 09:31:32.094906 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 09:31:32.098012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 09:31:32.098101 ==
8872 09:31:32.110370
8873 09:31:32.113980 TX Vref early break, caculate TX vref
8874 09:31:32.117464 TX Vref=16, minBit 0, minWin=23, winSum=382
8875 09:31:32.120319 TX Vref=18, minBit 0, minWin=23, winSum=391
8876 09:31:32.123968 TX Vref=20, minBit 0, minWin=23, winSum=404
8877 09:31:32.126965 TX Vref=22, minBit 0, minWin=24, winSum=410
8878 09:31:32.130305 TX Vref=24, minBit 0, minWin=25, winSum=418
8879 09:31:32.136884 TX Vref=26, minBit 5, minWin=25, winSum=423
8880 09:31:32.140125 TX Vref=28, minBit 0, minWin=26, winSum=428
8881 09:31:32.143686 TX Vref=30, minBit 5, minWin=25, winSum=421
8882 09:31:32.147136 TX Vref=32, minBit 0, minWin=24, winSum=414
8883 09:31:32.150150 TX Vref=34, minBit 5, minWin=23, winSum=403
8884 09:31:32.156726 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8885 09:31:32.156840
8886 09:31:32.160286 Final TX Range 0 Vref 28
8887 09:31:32.160374
8888 09:31:32.160439 ==
8889 09:31:32.163274 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 09:31:32.166873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 09:31:32.166962 ==
8892 09:31:32.167028
8893 09:31:32.167088
8894 09:31:32.169766 TX Vref Scan disable
8895 09:31:32.176698 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8896 09:31:32.176806 == TX Byte 0 ==
8897 09:31:32.180129 u2DelayCellOfst[0]=18 cells (5 PI)
8898 09:31:32.183173 u2DelayCellOfst[1]=11 cells (3 PI)
8899 09:31:32.186730 u2DelayCellOfst[2]=0 cells (0 PI)
8900 09:31:32.190293 u2DelayCellOfst[3]=7 cells (2 PI)
8901 09:31:32.193336 u2DelayCellOfst[4]=7 cells (2 PI)
8902 09:31:32.196909 u2DelayCellOfst[5]=22 cells (6 PI)
8903 09:31:32.199882 u2DelayCellOfst[6]=18 cells (5 PI)
8904 09:31:32.203255 u2DelayCellOfst[7]=7 cells (2 PI)
8905 09:31:32.206695 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8906 09:31:32.210148 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8907 09:31:32.213367 == TX Byte 1 ==
8908 09:31:32.213458 u2DelayCellOfst[8]=0 cells (0 PI)
8909 09:31:32.216602 u2DelayCellOfst[9]=7 cells (2 PI)
8910 09:31:32.219777 u2DelayCellOfst[10]=15 cells (4 PI)
8911 09:31:32.222883 u2DelayCellOfst[11]=7 cells (2 PI)
8912 09:31:32.226459 u2DelayCellOfst[12]=18 cells (5 PI)
8913 09:31:32.229938 u2DelayCellOfst[13]=18 cells (5 PI)
8914 09:31:32.232996 u2DelayCellOfst[14]=22 cells (6 PI)
8915 09:31:32.236218 u2DelayCellOfst[15]=18 cells (5 PI)
8916 09:31:32.239995 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8917 09:31:32.246138 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8918 09:31:32.246250 DramC Write-DBI on
8919 09:31:32.246318 ==
8920 09:31:32.249537 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 09:31:32.253258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 09:31:32.256463 ==
8923 09:31:32.256556
8924 09:31:32.256622
8925 09:31:32.256682 TX Vref Scan disable
8926 09:31:32.259968 == TX Byte 0 ==
8927 09:31:32.263365 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8928 09:31:32.266810 == TX Byte 1 ==
8929 09:31:32.269715 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 09:31:32.273292 DramC Write-DBI off
8931 09:31:32.273385
8932 09:31:32.273452 [DATLAT]
8933 09:31:32.273514 Freq=1600, CH1 RK1
8934 09:31:32.273573
8935 09:31:32.276164 DATLAT Default: 0xf
8936 09:31:32.276247 0, 0xFFFF, sum = 0
8937 09:31:32.279694 1, 0xFFFF, sum = 0
8938 09:31:32.283238 2, 0xFFFF, sum = 0
8939 09:31:32.283355 3, 0xFFFF, sum = 0
8940 09:31:32.286122 4, 0xFFFF, sum = 0
8941 09:31:32.286242 5, 0xFFFF, sum = 0
8942 09:31:32.289876 6, 0xFFFF, sum = 0
8943 09:31:32.289962 7, 0xFFFF, sum = 0
8944 09:31:32.293032 8, 0xFFFF, sum = 0
8945 09:31:32.293120 9, 0xFFFF, sum = 0
8946 09:31:32.296429 10, 0xFFFF, sum = 0
8947 09:31:32.296517 11, 0xFFFF, sum = 0
8948 09:31:32.299700 12, 0xFFFF, sum = 0
8949 09:31:32.299788 13, 0x8FFF, sum = 0
8950 09:31:32.302631 14, 0x0, sum = 1
8951 09:31:32.302718 15, 0x0, sum = 2
8952 09:31:32.306046 16, 0x0, sum = 3
8953 09:31:32.306134 17, 0x0, sum = 4
8954 09:31:32.309608 best_step = 15
8955 09:31:32.309693
8956 09:31:32.309759 ==
8957 09:31:32.312564 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 09:31:32.315970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 09:31:32.316083 ==
8960 09:31:32.319566 RX Vref Scan: 0
8961 09:31:32.319656
8962 09:31:32.319724 RX Vref 0 -> 0, step: 1
8963 09:31:32.319785
8964 09:31:32.322994 RX Delay 11 -> 252, step: 4
8965 09:31:32.329220 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8966 09:31:32.332891 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8967 09:31:32.336044 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8968 09:31:32.339142 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8969 09:31:32.342397 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8970 09:31:32.349067 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8971 09:31:32.352584 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8972 09:31:32.355980 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8973 09:31:32.359218 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8974 09:31:32.362236 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8975 09:31:32.369148 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8976 09:31:32.372581 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8977 09:31:32.376036 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8978 09:31:32.378984 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8979 09:31:32.382464 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8980 09:31:32.388885 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8981 09:31:32.389000 ==
8982 09:31:32.392479 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 09:31:32.395277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 09:31:32.395412 ==
8985 09:31:32.395495 DQS Delay:
8986 09:31:32.398507 DQS0 = 0, DQS1 = 0
8987 09:31:32.398593 DQM Delay:
8988 09:31:32.401900 DQM0 = 129, DQM1 = 125
8989 09:31:32.401989 DQ Delay:
8990 09:31:32.405611 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =128
8991 09:31:32.408413 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =124
8992 09:31:32.412101 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
8993 09:31:32.415043 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
8994 09:31:32.418634
8995 09:31:32.418729
8996 09:31:32.418796
8997 09:31:32.418856 [DramC_TX_OE_Calibration] TA2
8998 09:31:32.422026 Original DQ_B0 (3 6) =30, OEN = 27
8999 09:31:32.425463 Original DQ_B1 (3 6) =30, OEN = 27
9000 09:31:32.428459 24, 0x0, End_B0=24 End_B1=24
9001 09:31:32.432095 25, 0x0, End_B0=25 End_B1=25
9002 09:31:32.434971 26, 0x0, End_B0=26 End_B1=26
9003 09:31:32.435063 27, 0x0, End_B0=27 End_B1=27
9004 09:31:32.438446 28, 0x0, End_B0=28 End_B1=28
9005 09:31:32.441786 29, 0x0, End_B0=29 End_B1=29
9006 09:31:32.445333 30, 0x0, End_B0=30 End_B1=30
9007 09:31:32.448383 31, 0x4141, End_B0=30 End_B1=30
9008 09:31:32.448497 Byte0 end_step=30 best_step=27
9009 09:31:32.451511 Byte1 end_step=30 best_step=27
9010 09:31:32.455130 Byte0 TX OE(2T, 0.5T) = (3, 3)
9011 09:31:32.458587 Byte1 TX OE(2T, 0.5T) = (3, 3)
9012 09:31:32.458682
9013 09:31:32.458747
9014 09:31:32.468161 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9015 09:31:32.468285 CH1 RK1: MR19=303, MR18=111E
9016 09:31:32.475245 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9017 09:31:32.478458 [RxdqsGatingPostProcess] freq 1600
9018 09:31:32.484810 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9019 09:31:32.488256 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 09:31:32.491780 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 09:31:32.494699 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 09:31:32.494790 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 09:31:32.498382 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 09:31:32.501367 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 09:31:32.504883 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 09:31:32.508186 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 09:31:32.511362 Pre-setting of DQS Precalculation
9028 09:31:32.518224 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9029 09:31:32.524467 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9030 09:31:32.531454 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9031 09:31:32.531539
9032 09:31:32.531604
9033 09:31:32.534505 [Calibration Summary] 3200 Mbps
9034 09:31:32.534588 CH 0, Rank 0
9035 09:31:32.538045 SW Impedance : PASS
9036 09:31:32.541503 DUTY Scan : NO K
9037 09:31:32.541585 ZQ Calibration : PASS
9038 09:31:32.544544 Jitter Meter : NO K
9039 09:31:32.548178 CBT Training : PASS
9040 09:31:32.548261 Write leveling : PASS
9041 09:31:32.551010 RX DQS gating : PASS
9042 09:31:32.551092 RX DQ/DQS(RDDQC) : PASS
9043 09:31:32.554281 TX DQ/DQS : PASS
9044 09:31:32.557682 RX DATLAT : PASS
9045 09:31:32.557765 RX DQ/DQS(Engine): PASS
9046 09:31:32.561315 TX OE : PASS
9047 09:31:32.561397 All Pass.
9048 09:31:32.561462
9049 09:31:32.564744 CH 0, Rank 1
9050 09:31:32.564825 SW Impedance : PASS
9051 09:31:32.567880 DUTY Scan : NO K
9052 09:31:32.571281 ZQ Calibration : PASS
9053 09:31:32.571363 Jitter Meter : NO K
9054 09:31:32.574579 CBT Training : PASS
9055 09:31:32.577673 Write leveling : PASS
9056 09:31:32.577755 RX DQS gating : PASS
9057 09:31:32.581355 RX DQ/DQS(RDDQC) : PASS
9058 09:31:32.584579 TX DQ/DQS : PASS
9059 09:31:32.584664 RX DATLAT : PASS
9060 09:31:32.587907 RX DQ/DQS(Engine): PASS
9061 09:31:32.591121 TX OE : PASS
9062 09:31:32.591203 All Pass.
9063 09:31:32.591268
9064 09:31:32.591329 CH 1, Rank 0
9065 09:31:32.594231 SW Impedance : PASS
9066 09:31:32.597730 DUTY Scan : NO K
9067 09:31:32.597811 ZQ Calibration : PASS
9068 09:31:32.600714 Jitter Meter : NO K
9069 09:31:32.604317 CBT Training : PASS
9070 09:31:32.604399 Write leveling : PASS
9071 09:31:32.607817 RX DQS gating : PASS
9072 09:31:32.607899 RX DQ/DQS(RDDQC) : PASS
9073 09:31:32.610660 TX DQ/DQS : PASS
9074 09:31:32.614250 RX DATLAT : PASS
9075 09:31:32.614332 RX DQ/DQS(Engine): PASS
9076 09:31:32.617635 TX OE : PASS
9077 09:31:32.617717 All Pass.
9078 09:31:32.617781
9079 09:31:32.621135 CH 1, Rank 1
9080 09:31:32.621216 SW Impedance : PASS
9081 09:31:32.624405 DUTY Scan : NO K
9082 09:31:32.627344 ZQ Calibration : PASS
9083 09:31:32.627458 Jitter Meter : NO K
9084 09:31:32.630687 CBT Training : PASS
9085 09:31:32.634068 Write leveling : PASS
9086 09:31:32.634149 RX DQS gating : PASS
9087 09:31:32.637137 RX DQ/DQS(RDDQC) : PASS
9088 09:31:32.640644 TX DQ/DQS : PASS
9089 09:31:32.640728 RX DATLAT : PASS
9090 09:31:32.644255 RX DQ/DQS(Engine): PASS
9091 09:31:32.647074 TX OE : PASS
9092 09:31:32.647156 All Pass.
9093 09:31:32.647221
9094 09:31:32.647281 DramC Write-DBI on
9095 09:31:32.650582 PER_BANK_REFRESH: Hybrid Mode
9096 09:31:32.653589 TX_TRACKING: ON
9097 09:31:32.660250 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9098 09:31:32.670382 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9099 09:31:32.677333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 09:31:32.680062 [FAST_K] Save calibration result to emmc
9101 09:31:32.683407 sync common calibartion params.
9102 09:31:32.686695 sync cbt_mode0:1, 1:1
9103 09:31:32.686776 dram_init: ddr_geometry: 2
9104 09:31:32.690138 dram_init: ddr_geometry: 2
9105 09:31:32.693444 dram_init: ddr_geometry: 2
9106 09:31:32.697123 0:dram_rank_size:100000000
9107 09:31:32.697207 1:dram_rank_size:100000000
9108 09:31:32.703242 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9109 09:31:32.706496 DFS_SHUFFLE_HW_MODE: ON
9110 09:31:32.710281 dramc_set_vcore_voltage set vcore to 725000
9111 09:31:32.710363 Read voltage for 1600, 0
9112 09:31:32.713498 Vio18 = 0
9113 09:31:32.713580 Vcore = 725000
9114 09:31:32.713645 Vdram = 0
9115 09:31:32.716761 Vddq = 0
9116 09:31:32.716871 Vmddr = 0
9117 09:31:32.719863 switch to 3200 Mbps bootup
9118 09:31:32.719948 [DramcRunTimeConfig]
9119 09:31:32.720033 PHYPLL
9120 09:31:32.723443 DPM_CONTROL_AFTERK: ON
9121 09:31:32.726697 PER_BANK_REFRESH: ON
9122 09:31:32.726781 REFRESH_OVERHEAD_REDUCTION: ON
9123 09:31:32.730037 CMD_PICG_NEW_MODE: OFF
9124 09:31:32.733156 XRTWTW_NEW_MODE: ON
9125 09:31:32.733264 XRTRTR_NEW_MODE: ON
9126 09:31:32.736868 TX_TRACKING: ON
9127 09:31:32.736952 RDSEL_TRACKING: OFF
9128 09:31:32.739726 DQS Precalculation for DVFS: ON
9129 09:31:32.743191 RX_TRACKING: OFF
9130 09:31:32.743275 HW_GATING DBG: ON
9131 09:31:32.746874 ZQCS_ENABLE_LP4: ON
9132 09:31:32.746961 RX_PICG_NEW_MODE: ON
9133 09:31:32.749730 TX_PICG_NEW_MODE: ON
9134 09:31:32.749815 ENABLE_RX_DCM_DPHY: ON
9135 09:31:32.753516 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9136 09:31:32.756938 DUMMY_READ_FOR_TRACKING: OFF
9137 09:31:32.759760 !!! SPM_CONTROL_AFTERK: OFF
9138 09:31:32.763296 !!! SPM could not control APHY
9139 09:31:32.763428 IMPEDANCE_TRACKING: ON
9140 09:31:32.766231 TEMP_SENSOR: ON
9141 09:31:32.766316 HW_SAVE_FOR_SR: OFF
9142 09:31:32.769746 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9143 09:31:32.773284 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9144 09:31:32.776362 Read ODT Tracking: ON
9145 09:31:32.779772 Refresh Rate DeBounce: ON
9146 09:31:32.779857 DFS_NO_QUEUE_FLUSH: ON
9147 09:31:32.783305 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9148 09:31:32.786185 ENABLE_DFS_RUNTIME_MRW: OFF
9149 09:31:32.789678 DDR_RESERVE_NEW_MODE: ON
9150 09:31:32.789763 MR_CBT_SWITCH_FREQ: ON
9151 09:31:32.792691 =========================
9152 09:31:32.811723 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9153 09:31:32.814790 dram_init: ddr_geometry: 2
9154 09:31:32.832986 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9155 09:31:32.836052 dram_init: dram init end (result: 0)
9156 09:31:32.842573 DRAM-K: Full calibration passed in 24547 msecs
9157 09:31:32.845984 MRC: failed to locate region type 0.
9158 09:31:32.846071 DRAM rank0 size:0x100000000,
9159 09:31:32.849311 DRAM rank1 size=0x100000000
9160 09:31:32.859171 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9161 09:31:32.865768 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9162 09:31:32.872393 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9163 09:31:32.879460 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9164 09:31:32.882408 DRAM rank0 size:0x100000000,
9165 09:31:32.885872 DRAM rank1 size=0x100000000
9166 09:31:32.886005 CBMEM:
9167 09:31:32.889450 IMD: root @ 0xfffff000 254 entries.
9168 09:31:32.892985 IMD: root @ 0xffffec00 62 entries.
9169 09:31:32.895929 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9170 09:31:32.899641 WARNING: RO_VPD is uninitialized or empty.
9171 09:31:32.905944 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9172 09:31:32.912720 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9173 09:31:32.925690 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9174 09:31:32.937128 BS: romstage times (exec / console): total (unknown) / 24014 ms
9175 09:31:32.937234
9176 09:31:32.937299
9177 09:31:32.947285 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9178 09:31:32.950621 ARM64: Exception handlers installed.
9179 09:31:32.953581 ARM64: Testing exception
9180 09:31:32.957140 ARM64: Done test exception
9181 09:31:32.957230 Enumerating buses...
9182 09:31:32.960356 Show all devs... Before device enumeration.
9183 09:31:32.963884 Root Device: enabled 1
9184 09:31:32.967131 CPU_CLUSTER: 0: enabled 1
9185 09:31:32.967214 CPU: 00: enabled 1
9186 09:31:32.970401 Compare with tree...
9187 09:31:32.970483 Root Device: enabled 1
9188 09:31:32.973528 CPU_CLUSTER: 0: enabled 1
9189 09:31:32.977073 CPU: 00: enabled 1
9190 09:31:32.977156 Root Device scanning...
9191 09:31:32.980280 scan_static_bus for Root Device
9192 09:31:32.983822 CPU_CLUSTER: 0 enabled
9193 09:31:32.986851 scan_static_bus for Root Device done
9194 09:31:32.990410 scan_bus: bus Root Device finished in 8 msecs
9195 09:31:32.990495 done
9196 09:31:32.997026 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9197 09:31:32.999873 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9198 09:31:33.006930 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9199 09:31:33.009736 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9200 09:31:33.013204 Allocating resources...
9201 09:31:33.016586 Reading resources...
9202 09:31:33.020097 Root Device read_resources bus 0 link: 0
9203 09:31:33.020182 DRAM rank0 size:0x100000000,
9204 09:31:33.023104 DRAM rank1 size=0x100000000
9205 09:31:33.026600 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9206 09:31:33.029563 CPU: 00 missing read_resources
9207 09:31:33.036493 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9208 09:31:33.039538 Root Device read_resources bus 0 link: 0 done
9209 09:31:33.039621 Done reading resources.
9210 09:31:33.046523 Show resources in subtree (Root Device)...After reading.
9211 09:31:33.049383 Root Device child on link 0 CPU_CLUSTER: 0
9212 09:31:33.052797 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 09:31:33.063139 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 09:31:33.063293 CPU: 00
9215 09:31:33.066157 Root Device assign_resources, bus 0 link: 0
9216 09:31:33.069606 CPU_CLUSTER: 0 missing set_resources
9217 09:31:33.076224 Root Device assign_resources, bus 0 link: 0 done
9218 09:31:33.076313 Done setting resources.
9219 09:31:33.082698 Show resources in subtree (Root Device)...After assigning values.
9220 09:31:33.086191 Root Device child on link 0 CPU_CLUSTER: 0
9221 09:31:33.089694 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 09:31:33.099264 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 09:31:33.099409 CPU: 00
9224 09:31:33.102275 Done allocating resources.
9225 09:31:33.109286 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9226 09:31:33.109406 Enabling resources...
9227 09:31:33.109477 done.
9228 09:31:33.115634 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9229 09:31:33.115721 Initializing devices...
9230 09:31:33.119367 Root Device init
9231 09:31:33.119487 init hardware done!
9232 09:31:33.122614 0x00000018: ctrlr->caps
9233 09:31:33.125568 52.000 MHz: ctrlr->f_max
9234 09:31:33.125653 0.400 MHz: ctrlr->f_min
9235 09:31:33.129193 0x40ff8080: ctrlr->voltages
9236 09:31:33.132178 sclk: 390625
9237 09:31:33.132260 Bus Width = 1
9238 09:31:33.132326 sclk: 390625
9239 09:31:33.135811 Bus Width = 1
9240 09:31:33.135892 Early init status = 3
9241 09:31:33.142148 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9242 09:31:33.145654 in-header: 03 fc 00 00 01 00 00 00
9243 09:31:33.149041 in-data: 00
9244 09:31:33.152099 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9245 09:31:33.158036 in-header: 03 fd 00 00 00 00 00 00
9246 09:31:33.161214 in-data:
9247 09:31:33.164427 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9248 09:31:33.168364 in-header: 03 fc 00 00 01 00 00 00
9249 09:31:33.171635 in-data: 00
9250 09:31:33.175421 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9251 09:31:33.180506 in-header: 03 fd 00 00 00 00 00 00
9252 09:31:33.184374 in-data:
9253 09:31:33.187061 [SSUSB] Setting up USB HOST controller...
9254 09:31:33.190628 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9255 09:31:33.194234 [SSUSB] phy power-on done.
9256 09:31:33.197099 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9257 09:31:33.203815 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9258 09:31:33.206922 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9259 09:31:33.213983 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9260 09:31:33.220285 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9261 09:31:33.227333 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9262 09:31:33.233967 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9263 09:31:33.240396 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9264 09:31:33.243832 SPM: binary array size = 0x9dc
9265 09:31:33.247201 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9266 09:31:33.253827 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9267 09:31:33.260353 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9268 09:31:33.266809 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9269 09:31:33.270170 configure_display: Starting display init
9270 09:31:33.303813 anx7625_power_on_init: Init interface.
9271 09:31:33.307372 anx7625_disable_pd_protocol: Disabled PD feature.
9272 09:31:33.310692 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9273 09:31:33.338531 anx7625_start_dp_work: Secure OCM version=00
9274 09:31:33.341442 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9275 09:31:33.356472 sp_tx_get_edid_block: EDID Block = 1
9276 09:31:33.459150 Extracted contents:
9277 09:31:33.462149 header: 00 ff ff ff ff ff ff 00
9278 09:31:33.465748 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9279 09:31:33.469343 version: 01 04
9280 09:31:33.472267 basic params: 95 1f 11 78 0a
9281 09:31:33.475729 chroma info: 76 90 94 55 54 90 27 21 50 54
9282 09:31:33.478587 established: 00 00 00
9283 09:31:33.485637 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9284 09:31:33.489197 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9285 09:31:33.495187 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9286 09:31:33.502038 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9287 09:31:33.508344 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9288 09:31:33.511613 extensions: 00
9289 09:31:33.511699 checksum: fb
9290 09:31:33.511765
9291 09:31:33.515299 Manufacturer: IVO Model 57d Serial Number 0
9292 09:31:33.518634 Made week 0 of 2020
9293 09:31:33.521605 EDID version: 1.4
9294 09:31:33.521693 Digital display
9295 09:31:33.525127 6 bits per primary color channel
9296 09:31:33.525211 DisplayPort interface
9297 09:31:33.528577 Maximum image size: 31 cm x 17 cm
9298 09:31:33.531557 Gamma: 220%
9299 09:31:33.531640 Check DPMS levels
9300 09:31:33.534977 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9301 09:31:33.541884 First detailed timing is preferred timing
9302 09:31:33.541975 Established timings supported:
9303 09:31:33.544734 Standard timings supported:
9304 09:31:33.548309 Detailed timings
9305 09:31:33.551549 Hex of detail: 383680a07038204018303c0035ae10000019
9306 09:31:33.558418 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9307 09:31:33.561263 0780 0798 07c8 0820 hborder 0
9308 09:31:33.564527 0438 043b 0447 0458 vborder 0
9309 09:31:33.567993 -hsync -vsync
9310 09:31:33.568114 Did detailed timing
9311 09:31:33.574875 Hex of detail: 000000000000000000000000000000000000
9312 09:31:33.577829 Manufacturer-specified data, tag 0
9313 09:31:33.581327 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9314 09:31:33.584863 ASCII string: InfoVision
9315 09:31:33.587997 Hex of detail: 000000fe00523134304e574635205248200a
9316 09:31:33.591079 ASCII string: R140NWF5 RH
9317 09:31:33.591154 Checksum
9318 09:31:33.594646 Checksum: 0xfb (valid)
9319 09:31:33.597615 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9320 09:31:33.600929 DSI data_rate: 832800000 bps
9321 09:31:33.607880 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9322 09:31:33.610896 anx7625_parse_edid: pixelclock(138800).
9323 09:31:33.614328 hactive(1920), hsync(48), hfp(24), hbp(88)
9324 09:31:33.617593 vactive(1080), vsync(12), vfp(3), vbp(17)
9325 09:31:33.620853 anx7625_dsi_config: config dsi.
9326 09:31:33.627293 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9327 09:31:33.641398 anx7625_dsi_config: success to config DSI
9328 09:31:33.644300 anx7625_dp_start: MIPI phy setup OK.
9329 09:31:33.647744 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9330 09:31:33.651288 mtk_ddp_mode_set invalid vrefresh 60
9331 09:31:33.654329 main_disp_path_setup
9332 09:31:33.654431 ovl_layer_smi_id_en
9333 09:31:33.658041 ovl_layer_smi_id_en
9334 09:31:33.658115 ccorr_config
9335 09:31:33.658178 aal_config
9336 09:31:33.661058 gamma_config
9337 09:31:33.661128 postmask_config
9338 09:31:33.664545 dither_config
9339 09:31:33.667784 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9340 09:31:33.674355 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9341 09:31:33.677736 Root Device init finished in 555 msecs
9342 09:31:33.677820 CPU_CLUSTER: 0 init
9343 09:31:33.687592 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9344 09:31:33.691298 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9345 09:31:33.694785 APU_MBOX 0x190000b0 = 0x10001
9346 09:31:33.697724 APU_MBOX 0x190001b0 = 0x10001
9347 09:31:33.701443 APU_MBOX 0x190005b0 = 0x10001
9348 09:31:33.704383 APU_MBOX 0x190006b0 = 0x10001
9349 09:31:33.707228 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9350 09:31:33.720034 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9351 09:31:33.732789 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9352 09:31:33.739204 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9353 09:31:33.750996 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9354 09:31:33.760095 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9355 09:31:33.763016 CPU_CLUSTER: 0 init finished in 81 msecs
9356 09:31:33.766544 Devices initialized
9357 09:31:33.770293 Show all devs... After init.
9358 09:31:33.770400 Root Device: enabled 1
9359 09:31:33.773153 CPU_CLUSTER: 0: enabled 1
9360 09:31:33.776479 CPU: 00: enabled 1
9361 09:31:33.779885 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9362 09:31:33.783229 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9363 09:31:33.786339 ELOG: NV offset 0x57f000 size 0x1000
9364 09:31:33.793327 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9365 09:31:33.800093 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9366 09:31:33.803146 ELOG: Event(17) added with size 13 at 2023-10-20 09:31:34 UTC
9367 09:31:33.806120 out: cmd=0x121: 03 db 21 01 00 00 00 00
9368 09:31:33.810268 in-header: 03 76 00 00 2c 00 00 00
9369 09:31:33.823686 in-data: e9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 09:31:33.830203 ELOG: Event(A1) added with size 10 at 2023-10-20 09:31:34 UTC
9371 09:31:33.836575 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9372 09:31:33.842906 ELOG: Event(A0) added with size 9 at 2023-10-20 09:31:34 UTC
9373 09:31:33.846303 elog_add_boot_reason: Logged dev mode boot
9374 09:31:33.849667 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9375 09:31:33.852951 Finalize devices...
9376 09:31:33.853031 Devices finalized
9377 09:31:33.859708 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9378 09:31:33.863271 Writing coreboot table at 0xffe64000
9379 09:31:33.866233 0. 000000000010a000-0000000000113fff: RAMSTAGE
9380 09:31:33.869972 1. 0000000040000000-00000000400fffff: RAM
9381 09:31:33.876497 2. 0000000040100000-000000004032afff: RAMSTAGE
9382 09:31:33.879984 3. 000000004032b000-00000000545fffff: RAM
9383 09:31:33.882943 4. 0000000054600000-000000005465ffff: BL31
9384 09:31:33.886589 5. 0000000054660000-00000000ffe63fff: RAM
9385 09:31:33.892776 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9386 09:31:33.896213 7. 0000000100000000-000000023fffffff: RAM
9387 09:31:33.899648 Passing 5 GPIOs to payload:
9388 09:31:33.902973 NAME | PORT | POLARITY | VALUE
9389 09:31:33.905858 EC in RW | 0x000000aa | low | undefined
9390 09:31:33.912566 EC interrupt | 0x00000005 | low | undefined
9391 09:31:33.916088 TPM interrupt | 0x000000ab | high | undefined
9392 09:31:33.922736 SD card detect | 0x00000011 | high | undefined
9393 09:31:33.926088 speaker enable | 0x00000093 | high | undefined
9394 09:31:33.929295 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9395 09:31:33.932952 in-header: 03 f9 00 00 02 00 00 00
9396 09:31:33.936006 in-data: 02 00
9397 09:31:33.936081 ADC[4]: Raw value=897410 ID=7
9398 09:31:33.939494 ADC[3]: Raw value=213440 ID=1
9399 09:31:33.942494 RAM Code: 0x71
9400 09:31:33.942565 ADC[6]: Raw value=74722 ID=0
9401 09:31:33.946104 ADC[5]: Raw value=211960 ID=1
9402 09:31:33.949017 SKU Code: 0x1
9403 09:31:33.952311 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 357f
9404 09:31:33.955706 coreboot table: 964 bytes.
9405 09:31:33.959056 IMD ROOT 0. 0xfffff000 0x00001000
9406 09:31:33.962133 IMD SMALL 1. 0xffffe000 0x00001000
9407 09:31:33.965910 RO MCACHE 2. 0xffffc000 0x00001104
9408 09:31:33.968983 CONSOLE 3. 0xfff7c000 0x00080000
9409 09:31:33.972404 FMAP 4. 0xfff7b000 0x00000452
9410 09:31:33.975530 TIME STAMP 5. 0xfff7a000 0x00000910
9411 09:31:33.979071 VBOOT WORK 6. 0xfff66000 0x00014000
9412 09:31:33.982658 RAMOOPS 7. 0xffe66000 0x00100000
9413 09:31:33.985473 COREBOOT 8. 0xffe64000 0x00002000
9414 09:31:33.985551 IMD small region:
9415 09:31:33.988986 IMD ROOT 0. 0xffffec00 0x00000400
9416 09:31:33.991953 VPD 1. 0xffffeb80 0x0000006c
9417 09:31:33.998954 MMC STATUS 2. 0xffffeb60 0x00000004
9418 09:31:34.002021 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9419 09:31:34.005458 Probing TPM: done!
9420 09:31:34.008792 Connected to device vid:did:rid of 1ae0:0028:00
9421 09:31:34.019207 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9422 09:31:34.022326 Initialized TPM device CR50 revision 0
9423 09:31:34.026022 Checking cr50 for pending updates
9424 09:31:34.029628 Reading cr50 TPM mode
9425 09:31:34.038174 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9426 09:31:34.044599 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9427 09:31:34.084701 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9428 09:31:34.088321 Checking segment from ROM address 0x40100000
9429 09:31:34.091920 Checking segment from ROM address 0x4010001c
9430 09:31:34.098046 Loading segment from ROM address 0x40100000
9431 09:31:34.098142 code (compression=0)
9432 09:31:34.108030 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9433 09:31:34.115075 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9434 09:31:34.115234 it's not compressed!
9435 09:31:34.121524 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9436 09:31:34.125006 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9437 09:31:34.145211 Loading segment from ROM address 0x4010001c
9438 09:31:34.145337 Entry Point 0x80000000
9439 09:31:34.148879 Loaded segments
9440 09:31:34.151788 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9441 09:31:34.158880 Jumping to boot code at 0x80000000(0xffe64000)
9442 09:31:34.165067 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9443 09:31:34.171680 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9444 09:31:34.180195 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9445 09:31:34.183257 Checking segment from ROM address 0x40100000
9446 09:31:34.187015 Checking segment from ROM address 0x4010001c
9447 09:31:34.193346 Loading segment from ROM address 0x40100000
9448 09:31:34.193446 code (compression=1)
9449 09:31:34.199705 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9450 09:31:34.209925 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9451 09:31:34.210029 using LZMA
9452 09:31:34.218003 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9453 09:31:34.224964 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9454 09:31:34.228291 Loading segment from ROM address 0x4010001c
9455 09:31:34.228377 Entry Point 0x54601000
9456 09:31:34.231600 Loaded segments
9457 09:31:34.234747 NOTICE: MT8192 bl31_setup
9458 09:31:34.242253 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9459 09:31:34.245236 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9460 09:31:34.248187 WARNING: region 0:
9461 09:31:34.251721 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 09:31:34.251836 WARNING: region 1:
9463 09:31:34.258712 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9464 09:31:34.261709 WARNING: region 2:
9465 09:31:34.265201 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9466 09:31:34.268944 WARNING: region 3:
9467 09:31:34.271855 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 09:31:34.275396 WARNING: region 4:
9469 09:31:34.282016 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 09:31:34.282127 WARNING: region 5:
9471 09:31:34.284998 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 09:31:34.288613 WARNING: region 6:
9473 09:31:34.292191 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 09:31:34.292298 WARNING: region 7:
9475 09:31:34.298577 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 09:31:34.305370 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9477 09:31:34.308849 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9478 09:31:34.311937 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9479 09:31:34.318286 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9480 09:31:34.322229 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9481 09:31:34.325250 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9482 09:31:34.331835 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9483 09:31:34.335407 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9484 09:31:34.338853 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9485 09:31:34.345385 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9486 09:31:34.348345 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9487 09:31:34.354965 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9488 09:31:34.358351 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9489 09:31:34.361765 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9490 09:31:34.369166 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9491 09:31:34.372106 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9492 09:31:34.375390 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9493 09:31:34.382401 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9494 09:31:34.385420 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9495 09:31:34.388488 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9496 09:31:34.395435 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9497 09:31:34.398488 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9498 09:31:34.405422 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9499 09:31:34.409037 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9500 09:31:34.415140 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9501 09:31:34.418690 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9502 09:31:34.422299 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9503 09:31:34.428451 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9504 09:31:34.432165 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9505 09:31:34.435035 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9506 09:31:34.442140 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9507 09:31:34.445180 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9508 09:31:34.451989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9509 09:31:34.455059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9510 09:31:34.458501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9511 09:31:34.461914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9512 09:31:34.464939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9513 09:31:34.472236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9514 09:31:34.475478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9515 09:31:34.478770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9516 09:31:34.481742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9517 09:31:34.488632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9518 09:31:34.491826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9519 09:31:34.495174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9520 09:31:34.498703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9521 09:31:34.505208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9522 09:31:34.508502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9523 09:31:34.512021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9524 09:31:34.518459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9525 09:31:34.521978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9526 09:31:34.528560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9527 09:31:34.531991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9528 09:31:34.534938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9529 09:31:34.541995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9530 09:31:34.544965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9531 09:31:34.551658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9532 09:31:34.555251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9533 09:31:34.561794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9534 09:31:34.565246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9535 09:31:34.568173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9536 09:31:34.575351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9537 09:31:34.578219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9538 09:31:34.584941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9539 09:31:34.588390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9540 09:31:34.595296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9541 09:31:34.598327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9542 09:31:34.601836 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9543 09:31:34.608675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9544 09:31:34.611853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9545 09:31:34.618326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9546 09:31:34.622005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9547 09:31:34.628419 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9548 09:31:34.631975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9549 09:31:34.635032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9550 09:31:34.642168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9551 09:31:34.645245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9552 09:31:34.651779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9553 09:31:34.655363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9554 09:31:34.661887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9555 09:31:34.665534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9556 09:31:34.668443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9557 09:31:34.675614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9558 09:31:34.678682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9559 09:31:34.685070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9560 09:31:34.688355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9561 09:31:34.695320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9562 09:31:34.698326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9563 09:31:34.701725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9564 09:31:34.708362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9565 09:31:34.711932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9566 09:31:34.718529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9567 09:31:34.721575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9568 09:31:34.728553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9569 09:31:34.731911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9570 09:31:34.738038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9571 09:31:34.741552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9572 09:31:34.745060 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9573 09:31:34.751714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9574 09:31:34.754777 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9575 09:31:34.758488 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9576 09:31:34.761531 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9577 09:31:34.768185 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9578 09:31:34.771735 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9579 09:31:34.778171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9580 09:31:34.781834 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9581 09:31:34.784751 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9582 09:31:34.791457 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9583 09:31:34.794780 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9584 09:31:34.801819 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9585 09:31:34.804829 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9586 09:31:34.808247 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9587 09:31:34.814901 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9588 09:31:34.818477 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9589 09:31:34.821872 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9590 09:31:34.828711 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9591 09:31:34.831763 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9592 09:31:34.835219 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9593 09:31:34.841485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9594 09:31:34.845291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9595 09:31:34.848453 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9596 09:31:34.855354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9597 09:31:34.858696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9598 09:31:34.861971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9599 09:31:34.865085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9600 09:31:34.872137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9601 09:31:34.875026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9602 09:31:34.878497 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9603 09:31:34.885159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9604 09:31:34.888578 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9605 09:31:34.895270 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9606 09:31:34.898189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9607 09:31:34.901888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9608 09:31:34.908357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9609 09:31:34.911598 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9610 09:31:34.918613 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9611 09:31:34.921623 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9612 09:31:34.925245 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9613 09:31:34.932052 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9614 09:31:34.935348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9615 09:31:34.938258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9616 09:31:34.945436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9617 09:31:34.948459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9618 09:31:34.954982 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9619 09:31:34.958793 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9620 09:31:34.962085 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9621 09:31:34.968402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9622 09:31:34.971682 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9623 09:31:34.978597 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9624 09:31:34.981617 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9625 09:31:34.984971 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9626 09:31:34.992203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9627 09:31:34.995216 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9628 09:31:34.998763 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9629 09:31:35.005366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9630 09:31:35.008807 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9631 09:31:35.015067 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9632 09:31:35.018393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9633 09:31:35.021839 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9634 09:31:35.028847 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9635 09:31:35.032468 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9636 09:31:35.035374 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9637 09:31:35.041900 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9638 09:31:35.045249 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9639 09:31:35.051777 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9640 09:31:35.055250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9641 09:31:35.058280 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9642 09:31:35.065399 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9643 09:31:35.068429 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9644 09:31:35.075064 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9645 09:31:35.078360 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9646 09:31:35.081607 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9647 09:31:35.088364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9648 09:31:35.091600 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9649 09:31:35.098377 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9650 09:31:35.101357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9651 09:31:35.104965 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9652 09:31:35.111635 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9653 09:31:35.114682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9654 09:31:35.121415 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9655 09:31:35.124944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9656 09:31:35.127768 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9657 09:31:35.134817 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9658 09:31:35.137872 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9659 09:31:35.144654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9660 09:31:35.147601 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9661 09:31:35.150979 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9662 09:31:35.157850 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9663 09:31:35.160912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9664 09:31:35.167342 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9665 09:31:35.171085 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9666 09:31:35.174166 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9667 09:31:35.180804 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9668 09:31:35.184168 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9669 09:31:35.190948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9670 09:31:35.194423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9671 09:31:35.200790 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9672 09:31:35.204102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9673 09:31:35.207215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9674 09:31:35.213722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9675 09:31:35.217286 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9676 09:31:35.223815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9677 09:31:35.227304 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9678 09:31:35.233551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9679 09:31:35.236877 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9680 09:31:35.240397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9681 09:31:35.246916 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9682 09:31:35.250065 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9683 09:31:35.256587 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9684 09:31:35.259959 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9685 09:31:35.266731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9686 09:31:35.270341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9687 09:31:35.273358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9688 09:31:35.280004 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9689 09:31:35.283572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9690 09:31:35.290049 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9691 09:31:35.293350 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9692 09:31:35.296841 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9693 09:31:35.302979 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9694 09:31:35.306585 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9695 09:31:35.312932 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9696 09:31:35.316684 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9697 09:31:35.319826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9698 09:31:35.326000 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9699 09:31:35.329709 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9700 09:31:35.335948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9701 09:31:35.339503 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9702 09:31:35.346386 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9703 09:31:35.349739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9704 09:31:35.352767 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9705 09:31:35.359489 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9706 09:31:35.362987 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9707 09:31:35.365857 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9708 09:31:35.369046 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9709 09:31:35.376117 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9710 09:31:35.379187 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9711 09:31:35.382270 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9712 09:31:35.389418 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9713 09:31:35.392441 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9714 09:31:35.395512 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9715 09:31:35.402107 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9716 09:31:35.405503 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9717 09:31:35.412239 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9718 09:31:35.415164 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9719 09:31:35.418749 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9720 09:31:35.425727 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9721 09:31:35.428986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9722 09:31:35.435589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9723 09:31:35.438885 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9724 09:31:35.442169 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9725 09:31:35.448633 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9726 09:31:35.452214 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9727 09:31:35.455166 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9728 09:31:35.461883 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9729 09:31:35.465445 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9730 09:31:35.468406 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9731 09:31:35.474996 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9732 09:31:35.478866 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9733 09:31:35.485249 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9734 09:31:35.488320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9735 09:31:35.491893 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9736 09:31:35.497965 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9737 09:31:35.501537 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9738 09:31:35.504754 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9739 09:31:35.511395 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9740 09:31:35.514758 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9741 09:31:35.521560 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9742 09:31:35.524535 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9743 09:31:35.528215 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9744 09:31:35.534656 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9745 09:31:35.538039 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9746 09:31:35.541340 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9747 09:31:35.544553 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9748 09:31:35.547740 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9749 09:31:35.554597 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9750 09:31:35.557670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9751 09:31:35.561055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9752 09:31:35.564572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9753 09:31:35.571077 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9754 09:31:35.574046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9755 09:31:35.577677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9756 09:31:35.584046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9757 09:31:35.587308 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9758 09:31:35.590882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9759 09:31:35.597559 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9760 09:31:35.600606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9761 09:31:35.607266 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9762 09:31:35.610294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9763 09:31:35.617184 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9764 09:31:35.620579 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9765 09:31:35.623863 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9766 09:31:35.630675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9767 09:31:35.633599 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9768 09:31:35.637191 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9769 09:31:35.643530 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9770 09:31:35.647299 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9771 09:31:35.653894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9772 09:31:35.656615 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9773 09:31:35.663595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9774 09:31:35.666488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9775 09:31:35.669975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9776 09:31:35.677109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9777 09:31:35.680145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9778 09:31:35.686249 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9779 09:31:35.689632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9780 09:31:35.696448 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9781 09:31:35.699981 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9782 09:31:35.702954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9783 09:31:35.709610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9784 09:31:35.713339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9785 09:31:35.720047 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9786 09:31:35.722877 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9787 09:31:35.726156 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9788 09:31:35.732599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9789 09:31:35.736583 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9790 09:31:35.742616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9791 09:31:35.746221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9792 09:31:35.749895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9793 09:31:35.756192 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9794 09:31:35.759546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9795 09:31:35.766036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9796 09:31:35.769321 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9797 09:31:35.772647 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9798 09:31:35.779119 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9799 09:31:35.782802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9800 09:31:35.789412 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9801 09:31:35.792385 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9802 09:31:35.799337 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9803 09:31:35.802752 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9804 09:31:35.806108 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9805 09:31:35.812818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9806 09:31:35.815777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9807 09:31:35.822448 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9808 09:31:35.826069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9809 09:31:35.829087 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9810 09:31:35.835600 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9811 09:31:35.838760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9812 09:31:35.845884 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9813 09:31:35.848742 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9814 09:31:35.852533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9815 09:31:35.858808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9816 09:31:35.862099 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9817 09:31:35.868987 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9818 09:31:35.871971 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9819 09:31:35.878621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9820 09:31:35.882045 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9821 09:31:35.885485 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9822 09:31:35.892215 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9823 09:31:35.895233 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9824 09:31:35.901877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9825 09:31:35.905458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9826 09:31:35.908772 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9827 09:31:35.914887 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9828 09:31:35.918458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9829 09:31:35.925075 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9830 09:31:35.928647 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9831 09:31:35.931613 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9832 09:31:35.938735 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9833 09:31:35.941670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9834 09:31:35.948522 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9835 09:31:35.951758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9836 09:31:35.958411 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9837 09:31:35.961703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9838 09:31:35.965125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9839 09:31:35.971681 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9840 09:31:35.974576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9841 09:31:35.981543 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9842 09:31:35.984856 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9843 09:31:35.991604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9844 09:31:35.994984 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9845 09:31:36.001625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9846 09:31:36.004746 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9847 09:31:36.008264 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9848 09:31:36.014833 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9849 09:31:36.018006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9850 09:31:36.024719 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9851 09:31:36.027786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9852 09:31:36.034400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9853 09:31:36.038036 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9854 09:31:36.044679 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9855 09:31:36.047711 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9856 09:31:36.050755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9857 09:31:36.057950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9858 09:31:36.060675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9859 09:31:36.067632 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9860 09:31:36.071025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9861 09:31:36.077482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9862 09:31:36.080875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9863 09:31:36.084108 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9864 09:31:36.090951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9865 09:31:36.094395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9866 09:31:36.100599 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9867 09:31:36.104262 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9868 09:31:36.110782 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9869 09:31:36.113934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9870 09:31:36.117548 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9871 09:31:36.124059 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9872 09:31:36.127411 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9873 09:31:36.133907 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9874 09:31:36.137415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9875 09:31:36.143510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9876 09:31:36.147071 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9877 09:31:36.153609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9878 09:31:36.157207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9879 09:31:36.160163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9880 09:31:36.166841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9881 09:31:36.170262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9882 09:31:36.177230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9883 09:31:36.180371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9884 09:31:36.187178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9885 09:31:36.190424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9886 09:31:36.196820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9887 09:31:36.199955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9888 09:31:36.206871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9889 09:31:36.210288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9890 09:31:36.216969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9891 09:31:36.219914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9892 09:31:36.226577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9893 09:31:36.230301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9894 09:31:36.236496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9895 09:31:36.239774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9896 09:31:36.243320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9897 09:31:36.249854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9898 09:31:36.253355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9899 09:31:36.260033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9900 09:31:36.262953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9901 09:31:36.269688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9902 09:31:36.273265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9903 09:31:36.279820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9904 09:31:36.286354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9905 09:31:36.289736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9906 09:31:36.296043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9907 09:31:36.299682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9908 09:31:36.306283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9909 09:31:36.309381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9910 09:31:36.312820 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9911 09:31:36.316335 INFO: [APUAPC] vio 0
9912 09:31:36.319307 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9913 09:31:36.325966 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9914 09:31:36.329602 INFO: [APUAPC] D0_APC_0: 0x400510
9915 09:31:36.332728 INFO: [APUAPC] D0_APC_1: 0x0
9916 09:31:36.336233 INFO: [APUAPC] D0_APC_2: 0x1540
9917 09:31:36.336319 INFO: [APUAPC] D0_APC_3: 0x0
9918 09:31:36.339228 INFO: [APUAPC] D1_APC_0: 0xffffffff
9919 09:31:36.346474 INFO: [APUAPC] D1_APC_1: 0xffffffff
9920 09:31:36.346564 INFO: [APUAPC] D1_APC_2: 0x3fffff
9921 09:31:36.349382 INFO: [APUAPC] D1_APC_3: 0x0
9922 09:31:36.352722 INFO: [APUAPC] D2_APC_0: 0xffffffff
9923 09:31:36.356018 INFO: [APUAPC] D2_APC_1: 0xffffffff
9924 09:31:36.359714 INFO: [APUAPC] D2_APC_2: 0x3fffff
9925 09:31:36.362721 INFO: [APUAPC] D2_APC_3: 0x0
9926 09:31:36.366323 INFO: [APUAPC] D3_APC_0: 0xffffffff
9927 09:31:36.369359 INFO: [APUAPC] D3_APC_1: 0xffffffff
9928 09:31:36.373047 INFO: [APUAPC] D3_APC_2: 0x3fffff
9929 09:31:36.376046 INFO: [APUAPC] D3_APC_3: 0x0
9930 09:31:36.379650 INFO: [APUAPC] D4_APC_0: 0xffffffff
9931 09:31:36.382648 INFO: [APUAPC] D4_APC_1: 0xffffffff
9932 09:31:36.386149 INFO: [APUAPC] D4_APC_2: 0x3fffff
9933 09:31:36.389193 INFO: [APUAPC] D4_APC_3: 0x0
9934 09:31:36.392645 INFO: [APUAPC] D5_APC_0: 0xffffffff
9935 09:31:36.396057 INFO: [APUAPC] D5_APC_1: 0xffffffff
9936 09:31:36.399327 INFO: [APUAPC] D5_APC_2: 0x3fffff
9937 09:31:36.402771 INFO: [APUAPC] D5_APC_3: 0x0
9938 09:31:36.405727 INFO: [APUAPC] D6_APC_0: 0xffffffff
9939 09:31:36.408882 INFO: [APUAPC] D6_APC_1: 0xffffffff
9940 09:31:36.412477 INFO: [APUAPC] D6_APC_2: 0x3fffff
9941 09:31:36.415319 INFO: [APUAPC] D6_APC_3: 0x0
9942 09:31:36.418708 INFO: [APUAPC] D7_APC_0: 0xffffffff
9943 09:31:36.422241 INFO: [APUAPC] D7_APC_1: 0xffffffff
9944 09:31:36.425292 INFO: [APUAPC] D7_APC_2: 0x3fffff
9945 09:31:36.428710 INFO: [APUAPC] D7_APC_3: 0x0
9946 09:31:36.431886 INFO: [APUAPC] D8_APC_0: 0xffffffff
9947 09:31:36.435588 INFO: [APUAPC] D8_APC_1: 0xffffffff
9948 09:31:36.438620 INFO: [APUAPC] D8_APC_2: 0x3fffff
9949 09:31:36.442035 INFO: [APUAPC] D8_APC_3: 0x0
9950 09:31:36.445422 INFO: [APUAPC] D9_APC_0: 0xffffffff
9951 09:31:36.448609 INFO: [APUAPC] D9_APC_1: 0xffffffff
9952 09:31:36.451683 INFO: [APUAPC] D9_APC_2: 0x3fffff
9953 09:31:36.455236 INFO: [APUAPC] D9_APC_3: 0x0
9954 09:31:36.458802 INFO: [APUAPC] D10_APC_0: 0xffffffff
9955 09:31:36.461657 INFO: [APUAPC] D10_APC_1: 0xffffffff
9956 09:31:36.465099 INFO: [APUAPC] D10_APC_2: 0x3fffff
9957 09:31:36.468374 INFO: [APUAPC] D10_APC_3: 0x0
9958 09:31:36.472065 INFO: [APUAPC] D11_APC_0: 0xffffffff
9959 09:31:36.475048 INFO: [APUAPC] D11_APC_1: 0xffffffff
9960 09:31:36.478008 INFO: [APUAPC] D11_APC_2: 0x3fffff
9961 09:31:36.481562 INFO: [APUAPC] D11_APC_3: 0x0
9962 09:31:36.485278 INFO: [APUAPC] D12_APC_0: 0xffffffff
9963 09:31:36.488065 INFO: [APUAPC] D12_APC_1: 0xffffffff
9964 09:31:36.491637 INFO: [APUAPC] D12_APC_2: 0x3fffff
9965 09:31:36.494633 INFO: [APUAPC] D12_APC_3: 0x0
9966 09:31:36.498312 INFO: [APUAPC] D13_APC_0: 0xffffffff
9967 09:31:36.501653 INFO: [APUAPC] D13_APC_1: 0xffffffff
9968 09:31:36.504545 INFO: [APUAPC] D13_APC_2: 0x3fffff
9969 09:31:36.507987 INFO: [APUAPC] D13_APC_3: 0x0
9970 09:31:36.511023 INFO: [APUAPC] D14_APC_0: 0xffffffff
9971 09:31:36.514526 INFO: [APUAPC] D14_APC_1: 0xffffffff
9972 09:31:36.518030 INFO: [APUAPC] D14_APC_2: 0x3fffff
9973 09:31:36.521454 INFO: [APUAPC] D14_APC_3: 0x0
9974 09:31:36.524383 INFO: [APUAPC] D15_APC_0: 0xffffffff
9975 09:31:36.527930 INFO: [APUAPC] D15_APC_1: 0xffffffff
9976 09:31:36.531027 INFO: [APUAPC] D15_APC_2: 0x3fffff
9977 09:31:36.534666 INFO: [APUAPC] D15_APC_3: 0x0
9978 09:31:36.537593 INFO: [APUAPC] APC_CON: 0x4
9979 09:31:36.541176 INFO: [NOCDAPC] D0_APC_0: 0x0
9980 09:31:36.544211 INFO: [NOCDAPC] D0_APC_1: 0x0
9981 09:31:36.547855 INFO: [NOCDAPC] D1_APC_0: 0x0
9982 09:31:36.551235 INFO: [NOCDAPC] D1_APC_1: 0xfff
9983 09:31:36.551317 INFO: [NOCDAPC] D2_APC_0: 0x0
9984 09:31:36.554422 INFO: [NOCDAPC] D2_APC_1: 0xfff
9985 09:31:36.557475 INFO: [NOCDAPC] D3_APC_0: 0x0
9986 09:31:36.560913 INFO: [NOCDAPC] D3_APC_1: 0xfff
9987 09:31:36.564163 INFO: [NOCDAPC] D4_APC_0: 0x0
9988 09:31:36.567697 INFO: [NOCDAPC] D4_APC_1: 0xfff
9989 09:31:36.571058 INFO: [NOCDAPC] D5_APC_0: 0x0
9990 09:31:36.574482 INFO: [NOCDAPC] D5_APC_1: 0xfff
9991 09:31:36.577300 INFO: [NOCDAPC] D6_APC_0: 0x0
9992 09:31:36.580548 INFO: [NOCDAPC] D6_APC_1: 0xfff
9993 09:31:36.584318 INFO: [NOCDAPC] D7_APC_0: 0x0
9994 09:31:36.584401 INFO: [NOCDAPC] D7_APC_1: 0xfff
9995 09:31:36.587371 INFO: [NOCDAPC] D8_APC_0: 0x0
9996 09:31:36.590939 INFO: [NOCDAPC] D8_APC_1: 0xfff
9997 09:31:36.593811 INFO: [NOCDAPC] D9_APC_0: 0x0
9998 09:31:36.597401 INFO: [NOCDAPC] D9_APC_1: 0xfff
9999 09:31:36.600517 INFO: [NOCDAPC] D10_APC_0: 0x0
10000 09:31:36.603966 INFO: [NOCDAPC] D10_APC_1: 0xfff
10001 09:31:36.607367 INFO: [NOCDAPC] D11_APC_0: 0x0
10002 09:31:36.610460 INFO: [NOCDAPC] D11_APC_1: 0xfff
10003 09:31:36.613873 INFO: [NOCDAPC] D12_APC_0: 0x0
10004 09:31:36.617436 INFO: [NOCDAPC] D12_APC_1: 0xfff
10005 09:31:36.620387 INFO: [NOCDAPC] D13_APC_0: 0x0
10006 09:31:36.623856 INFO: [NOCDAPC] D13_APC_1: 0xfff
10007 09:31:36.627314 INFO: [NOCDAPC] D14_APC_0: 0x0
10008 09:31:36.630151 INFO: [NOCDAPC] D14_APC_1: 0xfff
10009 09:31:36.630235 INFO: [NOCDAPC] D15_APC_0: 0x0
10010 09:31:36.633807 INFO: [NOCDAPC] D15_APC_1: 0xfff
10011 09:31:36.636867 INFO: [NOCDAPC] APC_CON: 0x4
10012 09:31:36.640424 INFO: [APUAPC] set_apusys_apc done
10013 09:31:36.643347 INFO: [DEVAPC] devapc_init done
10014 09:31:36.650182 INFO: GICv3 without legacy support detected.
10015 09:31:36.653095 INFO: ARM GICv3 driver initialized in EL3
10016 09:31:36.656805 INFO: Maximum SPI INTID supported: 639
10017 09:31:36.659848 INFO: BL31: Initializing runtime services
10018 09:31:36.666353 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10019 09:31:36.669954 INFO: SPM: enable CPC mode
10020 09:31:36.673163 INFO: mcdi ready for mcusys-off-idle and system suspend
10021 09:31:36.679917 INFO: BL31: Preparing for EL3 exit to normal world
10022 09:31:36.682947 INFO: Entry point address = 0x80000000
10023 09:31:36.683031 INFO: SPSR = 0x8
10024 09:31:36.689836
10025 09:31:36.689921
10026 09:31:36.689988
10027 09:31:36.693239 Starting depthcharge on Spherion...
10028 09:31:36.693321
10029 09:31:36.693386 Wipe memory regions:
10030 09:31:36.693445
10031 09:31:36.694200 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10032 09:31:36.694302 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10033 09:31:36.694389 Setting prompt string to ['asurada:']
10034 09:31:36.694468 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10035 09:31:36.696391 [0x00000040000000, 0x00000054600000)
10036 09:31:36.819407
10037 09:31:36.819542 [0x00000054660000, 0x00000080000000)
10038 09:31:37.079359
10039 09:31:37.079516 [0x000000821a7280, 0x000000ffe64000)
10040 09:31:37.824328
10041 09:31:37.824464 [0x00000100000000, 0x00000240000000)
10042 09:31:39.714002
10043 09:31:39.717546 Initializing XHCI USB controller at 0x11200000.
10044 09:31:40.754999
10045 09:31:40.758474 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10046 09:31:40.758927
10047 09:31:40.759262
10048 09:31:40.759667
10049 09:31:40.760424 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 09:31:40.861505 asurada: tftpboot 192.168.201.1 11826824/tftp-deploy-qyjri2xd/kernel/image.itb 11826824/tftp-deploy-qyjri2xd/kernel/cmdline
10052 09:31:40.862099 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 09:31:40.862615 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10054 09:31:40.867094 tftpboot 192.168.201.1 11826824/tftp-deploy-qyjri2xd/kernel/image.ittp-deploy-qyjri2xd/kernel/cmdline
10055 09:31:40.867592
10056 09:31:40.867967 Waiting for link
10057 09:31:41.027474
10058 09:31:41.027965 R8152: Initializing
10059 09:31:41.028329
10060 09:31:41.031207 Version 6 (ocp_data = 5c30)
10061 09:31:41.031717
10062 09:31:41.034099 R8152: Done initializing
10063 09:31:41.034680
10064 09:31:41.035096 Adding net device
10065 09:31:42.934428
10066 09:31:42.935053 done.
10067 09:31:42.935567
10068 09:31:42.935900 MAC: 00:24:32:30:78:ff
10069 09:31:42.936276
10070 09:31:42.938001 Sending DHCP discover... done.
10071 09:31:42.938420
10072 09:31:46.091319 Waiting for reply... done.
10073 09:31:46.091505
10074 09:31:46.091622 Sending DHCP request... done.
10075 09:31:46.094347
10076 09:31:46.094460 Waiting for reply... done.
10077 09:31:46.094565
10078 09:31:46.097604 My ip is 192.168.201.21
10079 09:31:46.097709
10080 09:31:46.101235 The DHCP server ip is 192.168.201.1
10081 09:31:46.101357
10082 09:31:46.104842 TFTP server IP predefined by user: 192.168.201.1
10083 09:31:46.104970
10084 09:31:46.111206 Bootfile predefined by user: 11826824/tftp-deploy-qyjri2xd/kernel/image.itb
10085 09:31:46.111332
10086 09:31:46.114336 Sending tftp read request... done.
10087 09:31:46.114446
10088 09:31:46.117465 Waiting for the transfer...
10089 09:31:46.117576
10090 09:31:46.670317 00000000 ################################################################
10091 09:31:46.670474
10092 09:31:47.226668 00080000 ################################################################
10093 09:31:47.226856
10094 09:31:47.796124 00100000 ################################################################
10095 09:31:47.796293
10096 09:31:48.341811 00180000 ################################################################
10097 09:31:48.341974
10098 09:31:48.882286 00200000 ################################################################
10099 09:31:48.882450
10100 09:31:49.423980 00280000 ################################################################
10101 09:31:49.424126
10102 09:31:49.963359 00300000 ################################################################
10103 09:31:49.963533
10104 09:31:50.489317 00380000 ################################################################
10105 09:31:50.489453
10106 09:31:51.028864 00400000 ################################################################
10107 09:31:51.029026
10108 09:31:51.569526 00480000 ################################################################
10109 09:31:51.569693
10110 09:31:52.108304 00500000 ################################################################
10111 09:31:52.108448
10112 09:31:52.644953 00580000 ################################################################
10113 09:31:52.645115
10114 09:31:53.176862 00600000 ################################################################
10115 09:31:53.177060
10116 09:31:53.704935 00680000 ################################################################
10117 09:31:53.705100
10118 09:31:54.239899 00700000 ################################################################
10119 09:31:54.240057
10120 09:31:54.764823 00780000 ################################################################
10121 09:31:54.765005
10122 09:31:55.286428 00800000 ################################################################
10123 09:31:55.286608
10124 09:31:55.813259 00880000 ################################################################
10125 09:31:55.813414
10126 09:31:56.324429 00900000 ################################################################
10127 09:31:56.324563
10128 09:31:56.846914 00980000 ################################################################
10129 09:31:56.847082
10130 09:31:57.376487 00a00000 ################################################################
10131 09:31:57.376634
10132 09:31:57.901284 00a80000 ################################################################
10133 09:31:57.901442
10134 09:31:58.429164 00b00000 ################################################################
10135 09:31:58.429305
10136 09:31:58.957439 00b80000 ################################################################
10137 09:31:58.957608
10138 09:31:59.474945 00c00000 ################################################################
10139 09:31:59.475127
10140 09:31:59.992969 00c80000 ################################################################
10141 09:31:59.993112
10142 09:32:00.513427 00d00000 ################################################################
10143 09:32:00.513615
10144 09:32:01.034619 00d80000 ################################################################
10145 09:32:01.034767
10146 09:32:01.551949 00e00000 ################################################################
10147 09:32:01.552124
10148 09:32:02.066342 00e80000 ################################################################
10149 09:32:02.066499
10150 09:32:02.582715 00f00000 ################################################################
10151 09:32:02.582895
10152 09:32:03.102525 00f80000 ################################################################
10153 09:32:03.102701
10154 09:32:03.615991 01000000 ################################################################
10155 09:32:03.616172
10156 09:32:04.135581 01080000 ################################################################
10157 09:32:04.135761
10158 09:32:04.654352 01100000 ################################################################
10159 09:32:04.654524
10160 09:32:05.169296 01180000 ################################################################
10161 09:32:05.169462
10162 09:32:05.685012 01200000 ################################################################
10163 09:32:05.685149
10164 09:32:06.206200 01280000 ################################################################
10165 09:32:06.206369
10166 09:32:06.727278 01300000 ################################################################
10167 09:32:06.727461
10168 09:32:07.248223 01380000 ################################################################
10169 09:32:07.248365
10170 09:32:07.777498 01400000 ################################################################
10171 09:32:07.777634
10172 09:32:08.296403 01480000 ################################################################
10173 09:32:08.296543
10174 09:32:08.824637 01500000 ################################################################
10175 09:32:08.824790
10176 09:32:09.383722 01580000 ################################################################
10177 09:32:09.383876
10178 09:32:09.956534 01600000 ################################################################
10179 09:32:09.956672
10180 09:32:10.518404 01680000 ################################################################
10181 09:32:10.518538
10182 09:32:11.084207 01700000 ################################################################
10183 09:32:11.084347
10184 09:32:11.633666 01780000 ################################################################
10185 09:32:11.633809
10186 09:32:12.195830 01800000 ################################################################
10187 09:32:12.195967
10188 09:32:12.759849 01880000 ################################################################
10189 09:32:12.760042
10190 09:32:13.293565 01900000 ################################################################
10191 09:32:13.293721
10192 09:32:13.812273 01980000 ################################################################
10193 09:32:13.812409
10194 09:32:14.352863 01a00000 ################################################################
10195 09:32:14.353102
10196 09:32:14.886436 01a80000 ################################################################
10197 09:32:14.886633
10198 09:32:15.414419 01b00000 ################################################################
10199 09:32:15.414617
10200 09:32:15.963934 01b80000 ################################################################
10201 09:32:15.964093
10202 09:32:16.532714 01c00000 ################################################################
10203 09:32:16.532848
10204 09:32:17.101819 01c80000 ################################################################
10205 09:32:17.101957
10206 09:32:17.654873 01d00000 ################################################################
10207 09:32:17.655011
10208 09:32:18.194143 01d80000 ################################################################
10209 09:32:18.194325
10210 09:32:18.749321 01e00000 ################################################################
10211 09:32:18.749460
10212 09:32:19.292917 01e80000 ################################################################
10213 09:32:19.293060
10214 09:32:19.843124 01f00000 ################################################################
10215 09:32:19.843261
10216 09:32:20.384771 01f80000 ################################################################
10217 09:32:20.384956
10218 09:32:20.923610 02000000 ################################################################
10219 09:32:20.923750
10220 09:32:21.475059 02080000 ################################################################
10221 09:32:21.475192
10222 09:32:22.031258 02100000 ################################################################
10223 09:32:22.031423
10224 09:32:22.605363 02180000 ################################################################
10225 09:32:22.605503
10226 09:32:23.162807 02200000 ################################################################
10227 09:32:23.162944
10228 09:32:23.739806 02280000 ################################################################
10229 09:32:23.739939
10230 09:32:24.306595 02300000 ################################################################
10231 09:32:24.306737
10232 09:32:24.888315 02380000 ################################################################
10233 09:32:24.888457
10234 09:32:25.488821 02400000 ################################################################
10235 09:32:25.488995
10236 09:32:26.030629 02480000 ################################################################
10237 09:32:26.030804
10238 09:32:26.603429 02500000 ################################################################
10239 09:32:26.603575
10240 09:32:27.180303 02580000 ################################################################
10241 09:32:27.180442
10242 09:32:27.769779 02600000 ################################################################
10243 09:32:27.769930
10244 09:32:28.344423 02680000 ################################################################
10245 09:32:28.344574
10246 09:32:28.923886 02700000 ################################################################
10247 09:32:28.924051
10248 09:32:29.514036 02780000 ################################################################
10249 09:32:29.514195
10250 09:32:30.111659 02800000 ################################################################
10251 09:32:30.111819
10252 09:32:30.717478 02880000 ################################################################
10253 09:32:30.717635
10254 09:32:31.307701 02900000 ################################################################
10255 09:32:31.307866
10256 09:32:31.885629 02980000 ################################################################
10257 09:32:31.885784
10258 09:32:32.476143 02a00000 ################################################################
10259 09:32:32.476299
10260 09:32:33.051122 02a80000 ################################################################
10261 09:32:33.051277
10262 09:32:33.637777 02b00000 ################################################################
10263 09:32:33.637919
10264 09:32:34.224337 02b80000 ################################################################
10265 09:32:34.224495
10266 09:32:34.820774 02c00000 ################################################################
10267 09:32:34.820911
10268 09:32:35.401225 02c80000 ################################################################
10269 09:32:35.401367
10270 09:32:35.995728 02d00000 ################################################################
10271 09:32:35.995881
10272 09:32:36.575719 02d80000 ################################################################
10273 09:32:36.575865
10274 09:32:37.152520 02e00000 ################################################################
10275 09:32:37.152661
10276 09:32:37.743173 02e80000 ################################################################
10277 09:32:37.743310
10278 09:32:38.332688 02f00000 ################################################################
10279 09:32:38.332823
10280 09:32:38.916795 02f80000 ################################################################
10281 09:32:38.916936
10282 09:32:39.506288 03000000 ################################################################
10283 09:32:39.506428
10284 09:32:40.087808 03080000 ################################################################
10285 09:32:40.087945
10286 09:32:40.691278 03100000 ################################################################
10287 09:32:40.691452
10288 09:32:41.389565 03180000 ################################################################
10289 09:32:41.390099
10290 09:32:42.108079 03200000 ################################################################
10291 09:32:42.108576
10292 09:32:42.833668 03280000 ################################################################
10293 09:32:42.834195
10294 09:32:43.506023 03300000 ################################################################
10295 09:32:43.506284
10296 09:32:44.114375 03380000 ################################################################
10297 09:32:44.115108
10298 09:32:44.712212 03400000 ################################################################
10299 09:32:44.712363
10300 09:32:45.261967 03480000 ################################################################
10301 09:32:45.262106
10302 09:32:45.828966 03500000 ################################################################
10303 09:32:45.829144
10304 09:32:46.378108 03580000 ################################################################
10305 09:32:46.378255
10306 09:32:46.925188 03600000 ################################################################
10307 09:32:46.925327
10308 09:32:47.460680 03680000 ################################################################
10309 09:32:47.460814
10310 09:32:47.997090 03700000 ################################################################
10311 09:32:47.997222
10312 09:32:48.560650 03780000 ################################################################
10313 09:32:48.560814
10314 09:32:49.113888 03800000 ################################################################
10315 09:32:49.114059
10316 09:32:49.663002 03880000 ################################################################
10317 09:32:49.663169
10318 09:32:50.203122 03900000 ################################################################
10319 09:32:50.203300
10320 09:32:50.731763 03980000 ################################################################
10321 09:32:50.731907
10322 09:32:51.265155 03a00000 ################################################################
10323 09:32:51.265341
10324 09:32:51.789943 03a80000 ################################################################
10325 09:32:51.790085
10326 09:32:52.319354 03b00000 ################################################################
10327 09:32:52.319523
10328 09:32:52.847905 03b80000 ################################################################
10329 09:32:52.848073
10330 09:32:53.374257 03c00000 ################################################################
10331 09:32:53.374424
10332 09:32:53.893915 03c80000 ################################################################
10333 09:32:53.894059
10334 09:32:54.420008 03d00000 ################################################################
10335 09:32:54.420158
10336 09:32:54.947130 03d80000 ################################################################
10337 09:32:54.947322
10338 09:32:55.475747 03e00000 ################################################################
10339 09:32:55.475919
10340 09:32:56.000053 03e80000 ################################################################
10341 09:32:56.000192
10342 09:32:56.518923 03f00000 ################################################################
10343 09:32:56.519082
10344 09:32:57.052592 03f80000 ################################################################
10345 09:32:57.052753
10346 09:32:57.453152 04000000 ################################################ done.
10347 09:32:57.453315
10348 09:32:57.456187 The bootfile was 67498446 bytes long.
10349 09:32:57.456295
10350 09:32:57.459777 Sending tftp read request... done.
10351 09:32:57.459858
10352 09:32:57.459921 Waiting for the transfer...
10353 09:32:57.459983
10354 09:32:57.463256 00000000 # done.
10355 09:32:57.463349
10356 09:32:57.469681 Command line loaded dynamically from TFTP file: 11826824/tftp-deploy-qyjri2xd/kernel/cmdline
10357 09:32:57.469792
10358 09:32:57.483053 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10359 09:32:57.483171
10360 09:32:57.486289 Loading FIT.
10361 09:32:57.486395
10362 09:32:57.489546 Image ramdisk-1 has 56404874 bytes.
10363 09:32:57.489657
10364 09:32:57.489753 Image fdt-1 has 47278 bytes.
10365 09:32:57.492939
10366 09:32:57.493040 Image kernel-1 has 11044258 bytes.
10367 09:32:57.493133
10368 09:32:57.503127 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10369 09:32:57.503235
10370 09:32:57.519710 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10371 09:32:57.519801
10372 09:32:57.525831 Choosing best match conf-1 for compat google,spherion-rev2.
10373 09:32:57.530196
10374 09:32:57.535104 Connected to device vid:did:rid of 1ae0:0028:00
10375 09:32:57.543149
10376 09:32:57.546039 tpm_get_response: command 0x17b, return code 0x0
10377 09:32:57.546144
10378 09:32:57.549409 ec_init: CrosEC protocol v3 supported (256, 248)
10379 09:32:57.554250
10380 09:32:57.557913 tpm_cleanup: add release locality here.
10381 09:32:57.558013
10382 09:32:57.558107 Shutting down all USB controllers.
10383 09:32:57.560979
10384 09:32:57.561057 Removing current net device
10385 09:32:57.561128
10386 09:32:57.567988 Exiting depthcharge with code 4 at timestamp: 110162898
10387 09:32:57.568092
10388 09:32:57.571264 LZMA decompressing kernel-1 to 0x821a6718
10389 09:32:57.571371
10390 09:32:57.574252 LZMA decompressing kernel-1 to 0x40000000
10391 09:32:58.963231
10392 09:32:58.963401 jumping to kernel
10393 09:32:58.964450 end: 2.2.4 bootloader-commands (duration 00:01:22) [common]
10394 09:32:58.964581 start: 2.2.5 auto-login-action (timeout 00:03:03) [common]
10395 09:32:58.964688 Setting prompt string to ['Linux version [0-9]']
10396 09:32:58.964786 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10397 09:32:58.964885 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10398 09:32:59.045513
10399 09:32:59.048703 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10400 09:32:59.051854 start: 2.2.5.1 login-action (timeout 00:03:03) [common]
10401 09:32:59.051947 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10402 09:32:59.052039 Setting prompt string to []
10403 09:32:59.052126 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10404 09:32:59.052203 Using line separator: #'\n'#
10405 09:32:59.052284 No login prompt set.
10406 09:32:59.052366 Parsing kernel messages
10407 09:32:59.052451 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10408 09:32:59.052636 [login-action] Waiting for messages, (timeout 00:03:03)
10409 09:32:59.071644 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10410 09:32:59.075084 [ 0.000000] random: crng init done
10411 09:32:59.081681 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10412 09:32:59.081803 [ 0.000000] efi: UEFI not found.
10413 09:32:59.091517 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10414 09:32:59.098110 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10415 09:32:59.108560 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10416 09:32:59.118020 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10417 09:32:59.124572 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10418 09:32:59.131501 [ 0.000000] printk: bootconsole [mtk8250] enabled
10419 09:32:59.137862 [ 0.000000] NUMA: No NUMA configuration found
10420 09:32:59.144690 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10421 09:32:59.147787 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10422 09:32:59.151464 [ 0.000000] Zone ranges:
10423 09:32:59.157662 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10424 09:32:59.161188 [ 0.000000] DMA32 empty
10425 09:32:59.167571 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10426 09:32:59.171004 [ 0.000000] Movable zone start for each node
10427 09:32:59.174632 [ 0.000000] Early memory node ranges
10428 09:32:59.180735 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10429 09:32:59.187719 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10430 09:32:59.194451 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10431 09:32:59.200990 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10432 09:32:59.204026 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10433 09:32:59.213918 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10434 09:32:59.269769 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10435 09:32:59.276275 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10436 09:32:59.283046 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10437 09:32:59.286648 [ 0.000000] psci: probing for conduit method from DT.
10438 09:32:59.293090 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10439 09:32:59.296133 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10440 09:32:59.302934 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10441 09:32:59.305927 [ 0.000000] psci: SMC Calling Convention v1.2
10442 09:32:59.312572 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10443 09:32:59.316197 [ 0.000000] Detected VIPT I-cache on CPU0
10444 09:32:59.322881 [ 0.000000] CPU features: detected: GIC system register CPU interface
10445 09:32:59.329440 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10446 09:32:59.336159 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10447 09:32:59.342866 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10448 09:32:59.348998 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10449 09:32:59.359106 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10450 09:32:59.362156 [ 0.000000] alternatives: applying boot alternatives
10451 09:32:59.369077 [ 0.000000] Fallback order for Node 0: 0
10452 09:32:59.375667 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10453 09:32:59.378452 [ 0.000000] Policy zone: Normal
10454 09:32:59.392368 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10455 09:32:59.402252 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10456 09:32:59.413804 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10457 09:32:59.423897 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10458 09:32:59.430655 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10459 09:32:59.434089 <6>[ 0.000000] software IO TLB: area num 8.
10460 09:32:59.490429 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10461 09:32:59.639717 <6>[ 0.000000] Memory: 7914408K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 438360K reserved, 32768K cma-reserved)
10462 09:32:59.646209 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10463 09:32:59.652717 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10464 09:32:59.656320 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10465 09:32:59.662441 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10466 09:32:59.669262 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10467 09:32:59.672479 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10468 09:32:59.682270 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10469 09:32:59.689101 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10470 09:32:59.695798 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10471 09:32:59.702486 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10472 09:32:59.705735 <6>[ 0.000000] GICv3: 608 SPIs implemented
10473 09:32:59.708606 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10474 09:32:59.715487 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10475 09:32:59.718954 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10476 09:32:59.725196 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10477 09:32:59.738400 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10478 09:32:59.751784 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10479 09:32:59.758527 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10480 09:32:59.766007 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10481 09:32:59.779562 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10482 09:32:59.785717 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10483 09:32:59.792603 <6>[ 0.009185] Console: colour dummy device 80x25
10484 09:32:59.803033 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10485 09:32:59.809081 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10486 09:32:59.812752 <6>[ 0.029252] LSM: Security Framework initializing
10487 09:32:59.819009 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10488 09:32:59.829278 <6>[ 0.042003] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10489 09:32:59.835711 <6>[ 0.051467] cblist_init_generic: Setting adjustable number of callback queues.
10490 09:32:59.842176 <6>[ 0.058911] cblist_init_generic: Setting shift to 3 and lim to 1.
10491 09:32:59.852144 <6>[ 0.065250] cblist_init_generic: Setting adjustable number of callback queues.
10492 09:32:59.858677 <6>[ 0.072677] cblist_init_generic: Setting shift to 3 and lim to 1.
10493 09:32:59.862319 <6>[ 0.079117] rcu: Hierarchical SRCU implementation.
10494 09:32:59.868816 <6>[ 0.084134] rcu: Max phase no-delay instances is 1000.
10495 09:32:59.875638 <6>[ 0.091166] EFI services will not be available.
10496 09:32:59.878750 <6>[ 0.096124] smp: Bringing up secondary CPUs ...
10497 09:32:59.886858 <6>[ 0.101173] Detected VIPT I-cache on CPU1
10498 09:32:59.893677 <6>[ 0.101242] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10499 09:32:59.900572 <6>[ 0.101272] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10500 09:32:59.903637 <6>[ 0.101605] Detected VIPT I-cache on CPU2
10501 09:32:59.910305 <6>[ 0.101654] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10502 09:32:59.916612 <6>[ 0.101669] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10503 09:32:59.923540 <6>[ 0.101924] Detected VIPT I-cache on CPU3
10504 09:32:59.930097 <6>[ 0.101970] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10505 09:32:59.936910 <6>[ 0.101984] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10506 09:32:59.939849 <6>[ 0.102286] CPU features: detected: Spectre-v4
10507 09:32:59.946826 <6>[ 0.102292] CPU features: detected: Spectre-BHB
10508 09:32:59.949911 <6>[ 0.102297] Detected PIPT I-cache on CPU4
10509 09:32:59.956713 <6>[ 0.102354] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10510 09:32:59.963465 <6>[ 0.102371] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10511 09:32:59.969608 <6>[ 0.102661] Detected PIPT I-cache on CPU5
10512 09:32:59.976558 <6>[ 0.102723] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10513 09:32:59.983074 <6>[ 0.102739] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10514 09:32:59.986051 <6>[ 0.103022] Detected PIPT I-cache on CPU6
10515 09:32:59.992625 <6>[ 0.103087] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10516 09:32:59.999508 <6>[ 0.103103] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10517 09:33:00.006220 <6>[ 0.103399] Detected PIPT I-cache on CPU7
10518 09:33:00.012935 <6>[ 0.103464] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10519 09:33:00.019128 <6>[ 0.103480] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10520 09:33:00.022825 <6>[ 0.103528] smp: Brought up 1 node, 8 CPUs
10521 09:33:00.029501 <6>[ 0.244833] SMP: Total of 8 processors activated.
10522 09:33:00.032852 <6>[ 0.249785] CPU features: detected: 32-bit EL0 Support
10523 09:33:00.042280 <6>[ 0.255145] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10524 09:33:00.048905 <6>[ 0.263996] CPU features: detected: Common not Private translations
10525 09:33:00.055849 <6>[ 0.270474] CPU features: detected: CRC32 instructions
10526 09:33:00.058832 <6>[ 0.275861] CPU features: detected: RCpc load-acquire (LDAPR)
10527 09:33:00.065698 <6>[ 0.281820] CPU features: detected: LSE atomic instructions
10528 09:33:00.072321 <6>[ 0.287601] CPU features: detected: Privileged Access Never
10529 09:33:00.078749 <6>[ 0.293388] CPU features: detected: RAS Extension Support
10530 09:33:00.085925 <6>[ 0.298999] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10531 09:33:00.088827 <6>[ 0.306262] CPU: All CPU(s) started at EL2
10532 09:33:00.095508 <6>[ 0.310579] alternatives: applying system-wide alternatives
10533 09:33:00.104446 <6>[ 0.321284] devtmpfs: initialized
10534 09:33:00.120095 <6>[ 0.330205] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10535 09:33:00.126878 <6>[ 0.340166] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10536 09:33:00.133444 <6>[ 0.348181] pinctrl core: initialized pinctrl subsystem
10537 09:33:00.136618 <6>[ 0.354826] DMI not present or invalid.
10538 09:33:00.143379 <6>[ 0.359229] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10539 09:33:00.153001 <6>[ 0.366073] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10540 09:33:00.159956 <6>[ 0.373654] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10541 09:33:00.169550 <6>[ 0.381865] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10542 09:33:00.173230 <6>[ 0.390106] audit: initializing netlink subsys (disabled)
10543 09:33:00.183062 <5>[ 0.395795] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10544 09:33:00.189766 <6>[ 0.396503] thermal_sys: Registered thermal governor 'step_wise'
10545 09:33:00.196016 <6>[ 0.403761] thermal_sys: Registered thermal governor 'power_allocator'
10546 09:33:00.199123 <6>[ 0.410016] cpuidle: using governor menu
10547 09:33:00.205910 <6>[ 0.420974] NET: Registered PF_QIPCRTR protocol family
10548 09:33:00.212559 <6>[ 0.426454] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10549 09:33:00.218975 <6>[ 0.433559] ASID allocator initialised with 32768 entries
10550 09:33:00.222231 <6>[ 0.440100] Serial: AMBA PL011 UART driver
10551 09:33:00.232223 <4>[ 0.448881] Trying to register duplicate clock ID: 134
10552 09:33:00.286968 <6>[ 0.506541] KASLR enabled
10553 09:33:00.300925 <6>[ 0.514239] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10554 09:33:00.307938 <6>[ 0.521254] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10555 09:33:00.313995 <6>[ 0.527744] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10556 09:33:00.320600 <6>[ 0.534748] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10557 09:33:00.327799 <6>[ 0.541236] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10558 09:33:00.333856 <6>[ 0.548241] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10559 09:33:00.340526 <6>[ 0.554730] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10560 09:33:00.346996 <6>[ 0.561735] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10561 09:33:00.350469 <6>[ 0.569249] ACPI: Interpreter disabled.
10562 09:33:00.358844 <6>[ 0.575655] iommu: Default domain type: Translated
10563 09:33:00.365691 <6>[ 0.580765] iommu: DMA domain TLB invalidation policy: strict mode
10564 09:33:00.368854 <5>[ 0.587425] SCSI subsystem initialized
10565 09:33:00.375648 <6>[ 0.591590] usbcore: registered new interface driver usbfs
10566 09:33:00.382107 <6>[ 0.597322] usbcore: registered new interface driver hub
10567 09:33:00.385260 <6>[ 0.602873] usbcore: registered new device driver usb
10568 09:33:00.392045 <6>[ 0.608977] pps_core: LinuxPPS API ver. 1 registered
10569 09:33:00.402464 <6>[ 0.614168] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10570 09:33:00.405625 <6>[ 0.623511] PTP clock support registered
10571 09:33:00.408685 <6>[ 0.627753] EDAC MC: Ver: 3.0.0
10572 09:33:00.416543 <6>[ 0.632918] FPGA manager framework
10573 09:33:00.423302 <6>[ 0.636599] Advanced Linux Sound Architecture Driver Initialized.
10574 09:33:00.426393 <6>[ 0.643376] vgaarb: loaded
10575 09:33:00.432986 <6>[ 0.646541] clocksource: Switched to clocksource arch_sys_counter
10576 09:33:00.436028 <5>[ 0.652985] VFS: Disk quotas dquot_6.6.0
10577 09:33:00.442543 <6>[ 0.657165] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10578 09:33:00.446254 <6>[ 0.664352] pnp: PnP ACPI: disabled
10579 09:33:00.454362 <6>[ 0.671048] NET: Registered PF_INET protocol family
10580 09:33:00.463984 <6>[ 0.676637] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10581 09:33:00.475852 <6>[ 0.688944] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10582 09:33:00.485670 <6>[ 0.697756] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10583 09:33:00.492099 <6>[ 0.705727] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10584 09:33:00.501604 <6>[ 0.714429] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10585 09:33:00.508431 <6>[ 0.724161] TCP: Hash tables configured (established 65536 bind 65536)
10586 09:33:00.515239 <6>[ 0.731016] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10587 09:33:00.524953 <6>[ 0.738216] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10588 09:33:00.531816 <6>[ 0.745915] NET: Registered PF_UNIX/PF_LOCAL protocol family
10589 09:33:00.534824 <6>[ 0.752085] RPC: Registered named UNIX socket transport module.
10590 09:33:00.541783 <6>[ 0.758239] RPC: Registered udp transport module.
10591 09:33:00.544885 <6>[ 0.763171] RPC: Registered tcp transport module.
10592 09:33:00.551591 <6>[ 0.768101] RPC: Registered tcp NFSv4.1 backchannel transport module.
10593 09:33:00.558216 <6>[ 0.774772] PCI: CLS 0 bytes, default 64
10594 09:33:00.561122 <6>[ 0.779169] Unpacking initramfs...
10595 09:33:00.585509 <6>[ 0.798687] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10596 09:33:00.595216 <6>[ 0.807346] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10597 09:33:00.598639 <6>[ 0.816189] kvm [1]: IPA Size Limit: 40 bits
10598 09:33:00.605331 <6>[ 0.820718] kvm [1]: GICv3: no GICV resource entry
10599 09:33:00.608689 <6>[ 0.825736] kvm [1]: disabling GICv2 emulation
10600 09:33:00.614897 <6>[ 0.830424] kvm [1]: GIC system register CPU interface enabled
10601 09:33:00.618642 <6>[ 0.836586] kvm [1]: vgic interrupt IRQ18
10602 09:33:00.625195 <6>[ 0.840941] kvm [1]: VHE mode initialized successfully
10603 09:33:00.632236 <5>[ 0.847452] Initialise system trusted keyrings
10604 09:33:00.638029 <6>[ 0.852276] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10605 09:33:00.645436 <6>[ 0.862207] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10606 09:33:00.652266 <5>[ 0.868587] NFS: Registering the id_resolver key type
10607 09:33:00.655319 <5>[ 0.873891] Key type id_resolver registered
10608 09:33:00.662230 <5>[ 0.878311] Key type id_legacy registered
10609 09:33:00.668801 <6>[ 0.882595] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10610 09:33:00.675038 <6>[ 0.889515] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10611 09:33:00.681740 <6>[ 0.897250] 9p: Installing v9fs 9p2000 file system support
10612 09:33:00.718482 <5>[ 0.935164] Key type asymmetric registered
10613 09:33:00.721880 <5>[ 0.939501] Asymmetric key parser 'x509' registered
10614 09:33:00.731627 <6>[ 0.944665] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10615 09:33:00.735341 <6>[ 0.952280] io scheduler mq-deadline registered
10616 09:33:00.738451 <6>[ 0.957075] io scheduler kyber registered
10617 09:33:00.757422 <6>[ 0.974310] EINJ: ACPI disabled.
10618 09:33:00.789845 <4>[ 1.000123] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 09:33:00.799696 <4>[ 1.010751] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 09:33:00.814509 <6>[ 1.031323] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10621 09:33:00.822404 <6>[ 1.039300] printk: console [ttyS0] disabled
10622 09:33:00.850539 <6>[ 1.063942] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10623 09:33:00.857256 <6>[ 1.073417] printk: console [ttyS0] enabled
10624 09:33:00.860870 <6>[ 1.073417] printk: console [ttyS0] enabled
10625 09:33:00.867202 <6>[ 1.082311] printk: bootconsole [mtk8250] disabled
10626 09:33:00.870466 <6>[ 1.082311] printk: bootconsole [mtk8250] disabled
10627 09:33:00.877271 <6>[ 1.093300] SuperH (H)SCI(F) driver initialized
10628 09:33:00.880313 <6>[ 1.098577] msm_serial: driver initialized
10629 09:33:00.894401 <6>[ 1.107481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10630 09:33:00.904476 <6>[ 1.116025] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10631 09:33:00.910702 <6>[ 1.124566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10632 09:33:00.920525 <6>[ 1.133194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10633 09:33:00.930879 <6>[ 1.141900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10634 09:33:00.937190 <6>[ 1.150622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10635 09:33:00.947356 <6>[ 1.159165] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10636 09:33:00.953582 <6>[ 1.167957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10637 09:33:00.963519 <6>[ 1.176499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10638 09:33:00.975125 <6>[ 1.192053] loop: module loaded
10639 09:33:00.981939 <6>[ 1.197926] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10640 09:33:01.004701 <4>[ 1.221235] mtk-pmic-keys: Failed to locate of_node [id: -1]
10641 09:33:01.011416 <6>[ 1.228110] megasas: 07.719.03.00-rc1
10642 09:33:01.020872 <6>[ 1.237717] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10643 09:33:01.029455 <6>[ 1.245924] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10644 09:33:01.045955 <6>[ 1.262561] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10645 09:33:01.102592 <6>[ 1.312497] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10646 09:33:02.963476 <6>[ 3.180273] Freeing initrd memory: 55076K
10647 09:33:02.973594 <6>[ 3.190763] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10648 09:33:02.985034 <6>[ 3.201818] tun: Universal TUN/TAP device driver, 1.6
10649 09:33:02.988189 <6>[ 3.207903] thunder_xcv, ver 1.0
10650 09:33:02.991538 <6>[ 3.211407] thunder_bgx, ver 1.0
10651 09:33:02.994716 <6>[ 3.214902] nicpf, ver 1.0
10652 09:33:03.005521 <6>[ 3.218937] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10653 09:33:03.008964 <6>[ 3.226412] hns3: Copyright (c) 2017 Huawei Corporation.
10654 09:33:03.015676 <6>[ 3.232005] hclge is initializing
10655 09:33:03.018581 <6>[ 3.235586] e1000: Intel(R) PRO/1000 Network Driver
10656 09:33:03.025490 <6>[ 3.240716] e1000: Copyright (c) 1999-2006 Intel Corporation.
10657 09:33:03.028401 <6>[ 3.246728] e1000e: Intel(R) PRO/1000 Network Driver
10658 09:33:03.035077 <6>[ 3.251943] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10659 09:33:03.041684 <6>[ 3.258129] igb: Intel(R) Gigabit Ethernet Network Driver
10660 09:33:03.048624 <6>[ 3.263778] igb: Copyright (c) 2007-2014 Intel Corporation.
10661 09:33:03.055266 <6>[ 3.269614] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10662 09:33:03.061725 <6>[ 3.276132] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10663 09:33:03.065303 <6>[ 3.282610] sky2: driver version 1.30
10664 09:33:03.071682 <6>[ 3.287611] VFIO - User Level meta-driver version: 0.3
10665 09:33:03.079398 <6>[ 3.295903] usbcore: registered new interface driver usb-storage
10666 09:33:03.085380 <6>[ 3.302346] usbcore: registered new device driver onboard-usb-hub
10667 09:33:03.094824 <6>[ 3.311496] mt6397-rtc mt6359-rtc: registered as rtc0
10668 09:33:03.104570 <6>[ 3.316965] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:33:03 UTC (1697794383)
10669 09:33:03.107933 <6>[ 3.326540] i2c_dev: i2c /dev entries driver
10670 09:33:03.124939 <6>[ 3.338285] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10671 09:33:03.144201 <6>[ 3.361283] cpu cpu0: EM: created perf domain
10672 09:33:03.147614 <6>[ 3.366227] cpu cpu4: EM: created perf domain
10673 09:33:03.154967 <6>[ 3.371856] sdhci: Secure Digital Host Controller Interface driver
10674 09:33:03.161358 <6>[ 3.378290] sdhci: Copyright(c) Pierre Ossman
10675 09:33:03.168044 <6>[ 3.383244] Synopsys Designware Multimedia Card Interface Driver
10676 09:33:03.174595 <6>[ 3.389877] sdhci-pltfm: SDHCI platform and OF driver helper
10677 09:33:03.178102 <6>[ 3.389907] mmc0: CQHCI version 5.10
10678 09:33:03.184678 <6>[ 3.400218] ledtrig-cpu: registered to indicate activity on CPUs
10679 09:33:03.191395 <6>[ 3.407338] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10680 09:33:03.197967 <6>[ 3.414396] usbcore: registered new interface driver usbhid
10681 09:33:03.201426 <6>[ 3.420220] usbhid: USB HID core driver
10682 09:33:03.207779 <6>[ 3.424406] spi_master spi0: will run message pump with realtime priority
10683 09:33:03.253185 <6>[ 3.463407] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10684 09:33:03.272269 <6>[ 3.479378] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10685 09:33:03.275967 <6>[ 3.493084] mmc0: Command Queue Engine enabled
10686 09:33:03.282628 <6>[ 3.497899] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10687 09:33:03.289242 <6>[ 3.505233] mmcblk0: mmc0:0001 DA4128 116 GiB
10688 09:33:03.292339 <6>[ 3.510065] cros-ec-spi spi0.0: Chrome EC device registered
10689 09:33:03.298842 <6>[ 3.514068] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10690 09:33:03.305926 <6>[ 3.522991] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10691 09:33:03.312560 <6>[ 3.529036] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10692 09:33:03.319481 <6>[ 3.535100] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10693 09:33:03.336165 <6>[ 3.549998] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10694 09:33:03.343919 <6>[ 3.560611] NET: Registered PF_PACKET protocol family
10695 09:33:03.346995 <6>[ 3.566035] 9pnet: Installing 9P2000 support
10696 09:33:03.353584 <5>[ 3.570599] Key type dns_resolver registered
10697 09:33:03.357114 <6>[ 3.575579] registered taskstats version 1
10698 09:33:03.363858 <5>[ 3.579968] Loading compiled-in X.509 certificates
10699 09:33:03.394258 <4>[ 3.604183] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10700 09:33:03.403970 <4>[ 3.614931] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10701 09:33:03.410577 <3>[ 3.625477] debugfs: File 'uA_load' in directory '/' already present!
10702 09:33:03.417127 <3>[ 3.632180] debugfs: File 'min_uV' in directory '/' already present!
10703 09:33:03.423804 <3>[ 3.638788] debugfs: File 'max_uV' in directory '/' already present!
10704 09:33:03.430065 <3>[ 3.645395] debugfs: File 'constraint_flags' in directory '/' already present!
10705 09:33:03.441537 <3>[ 3.655373] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10706 09:33:03.455208 <6>[ 3.671871] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10707 09:33:03.461771 <6>[ 3.678603] xhci-mtk 11200000.usb: xHCI Host Controller
10708 09:33:03.468478 <6>[ 3.684120] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10709 09:33:03.478743 <6>[ 3.691987] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10710 09:33:03.484961 <6>[ 3.701446] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10711 09:33:03.492089 <6>[ 3.707542] xhci-mtk 11200000.usb: xHCI Host Controller
10712 09:33:03.498506 <6>[ 3.713177] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10713 09:33:03.505018 <6>[ 3.720865] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10714 09:33:03.512040 <6>[ 3.728755] hub 1-0:1.0: USB hub found
10715 09:33:03.515399 <6>[ 3.732792] hub 1-0:1.0: 1 port detected
10716 09:33:03.525166 <6>[ 3.737101] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10717 09:33:03.528582 <6>[ 3.745916] hub 2-0:1.0: USB hub found
10718 09:33:03.531509 <6>[ 3.749939] hub 2-0:1.0: 1 port detected
10719 09:33:03.541221 <6>[ 3.757856] mtk-msdc 11f70000.mmc: Got CD GPIO
10720 09:33:03.552358 <6>[ 3.765996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10721 09:33:03.558970 <6>[ 3.774022] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10722 09:33:03.569080 <4>[ 3.781981] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10723 09:33:03.578879 <6>[ 3.791549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10724 09:33:03.585629 <6>[ 3.799626] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10725 09:33:03.592409 <6>[ 3.807603] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10726 09:33:03.602360 <6>[ 3.815524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10727 09:33:03.608743 <6>[ 3.823341] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10728 09:33:03.618773 <6>[ 3.831160] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10729 09:33:03.628100 <6>[ 3.841327] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10730 09:33:03.634909 <6>[ 3.849679] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10731 09:33:03.645126 <6>[ 3.858026] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10732 09:33:03.651537 <6>[ 3.866364] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10733 09:33:03.661517 <6>[ 3.874703] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10734 09:33:03.668068 <6>[ 3.883042] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10735 09:33:03.678305 <6>[ 3.891396] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10736 09:33:03.684505 <6>[ 3.899735] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10737 09:33:03.694847 <6>[ 3.908074] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10738 09:33:03.704411 <6>[ 3.916412] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10739 09:33:03.711091 <6>[ 3.924751] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10740 09:33:03.720857 <6>[ 3.933089] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10741 09:33:03.727310 <6>[ 3.941428] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10742 09:33:03.737698 <6>[ 3.949766] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10743 09:33:03.743802 <6>[ 3.958105] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10744 09:33:03.750477 <6>[ 3.966851] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10745 09:33:03.756869 <6>[ 3.974009] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10746 09:33:03.763910 <6>[ 3.980775] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10747 09:33:03.773674 <6>[ 3.987541] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10748 09:33:03.780536 <6>[ 3.994482] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10749 09:33:03.787124 <6>[ 4.001321] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10750 09:33:03.796980 <6>[ 4.010453] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10751 09:33:03.807230 <6>[ 4.019574] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10752 09:33:03.816914 <6>[ 4.028869] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10753 09:33:03.826567 <6>[ 4.038337] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10754 09:33:03.836629 <6>[ 4.047804] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10755 09:33:03.843351 <6>[ 4.056924] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10756 09:33:03.852922 <6>[ 4.066397] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10757 09:33:03.862972 <6>[ 4.075517] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10758 09:33:03.872950 <6>[ 4.084821] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10759 09:33:03.882447 <6>[ 4.094981] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10760 09:33:03.893045 <6>[ 4.106789] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10761 09:33:03.941293 <6>[ 4.154818] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10762 09:33:04.095763 <6>[ 4.312593] hub 1-1:1.0: USB hub found
10763 09:33:04.098758 <6>[ 4.317119] hub 1-1:1.0: 4 ports detected
10764 09:33:04.221064 <6>[ 4.434993] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10765 09:33:04.248200 <6>[ 4.464972] hub 2-1:1.0: USB hub found
10766 09:33:04.251379 <6>[ 4.469465] hub 2-1:1.0: 3 ports detected
10767 09:33:04.421240 <6>[ 4.634862] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10768 09:33:04.552960 <6>[ 4.769943] hub 1-1.4:1.0: USB hub found
10769 09:33:04.556009 <6>[ 4.774478] hub 1-1.4:1.0: 2 ports detected
10770 09:33:04.633310 <6>[ 4.847022] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10771 09:33:04.853099 <6>[ 5.066862] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10772 09:33:05.045204 <6>[ 5.258861] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10773 09:33:16.178527 <6>[ 16.399872] ALSA device list:
10774 09:33:16.184945 <6>[ 16.403159] No soundcards found.
10775 09:33:16.192889 <6>[ 16.411106] Freeing unused kernel memory: 8384K
10776 09:33:16.196291 <6>[ 16.416099] Run /init as init process
10777 09:33:16.245433 <6>[ 16.463837] NET: Registered PF_INET6 protocol family
10778 09:33:16.251853 <6>[ 16.470433] Segment Routing with IPv6
10779 09:33:16.255317 <6>[ 16.474386] In-situ OAM (IOAM) with IPv6
10780 09:33:16.293154 <30>[ 16.491479] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10781 09:33:16.296014 <30>[ 16.515442] systemd[1]: Detected architecture arm64.
10782 09:33:16.299679
10783 09:33:16.302844 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10784 09:33:16.302961
10785 09:33:16.316756 <30>[ 16.534755] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10786 09:33:16.477332 <30>[ 16.691952] systemd[1]: Queued start job for default target Graphical Interface.
10787 09:33:16.517809 <30>[ 16.735887] systemd[1]: Created slice system-getty.slice.
10788 09:33:16.523868 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10789 09:33:16.541387 <30>[ 16.759535] systemd[1]: Created slice system-modprobe.slice.
10790 09:33:16.547600 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10791 09:33:16.564687 <30>[ 16.783165] systemd[1]: Created slice system-serial\x2dgetty.slice.
10792 09:33:16.574873 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10793 09:33:16.589230 <30>[ 16.807857] systemd[1]: Created slice User and Session Slice.
10794 09:33:16.595966 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10795 09:33:16.616118 <30>[ 16.831350] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10796 09:33:16.626222 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10797 09:33:16.644379 <30>[ 16.859461] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10798 09:33:16.651119 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10799 09:33:16.674987 <30>[ 16.886863] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10800 09:33:16.681754 <30>[ 16.898972] systemd[1]: Reached target Local Encrypted Volumes.
10801 09:33:16.688260 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10802 09:33:16.705101 <30>[ 16.923308] systemd[1]: Reached target Paths.
10803 09:33:16.708017 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10804 09:33:16.724373 <30>[ 16.942788] systemd[1]: Reached target Remote File Systems.
10805 09:33:16.731164 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10806 09:33:16.744669 <30>[ 16.962766] systemd[1]: Reached target Slices.
10807 09:33:16.747659 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10808 09:33:16.764445 <30>[ 16.982792] systemd[1]: Reached target Swap.
10809 09:33:16.767710 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10810 09:33:16.788178 <30>[ 17.003255] systemd[1]: Listening on initctl Compatibility Named Pipe.
10811 09:33:16.795040 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10812 09:33:16.809662 <30>[ 17.028166] systemd[1]: Listening on Journal Audit Socket.
10813 09:33:16.816537 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10814 09:33:16.833410 <30>[ 17.051903] systemd[1]: Listening on Journal Socket (/dev/log).
10815 09:33:16.840081 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10816 09:33:16.857149 <30>[ 17.075265] systemd[1]: Listening on Journal Socket.
10817 09:33:16.863672 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10818 09:33:16.877014 <30>[ 17.095278] systemd[1]: Listening on udev Control Socket.
10819 09:33:16.883617 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10820 09:33:16.901510 <30>[ 17.119804] systemd[1]: Listening on udev Kernel Socket.
10821 09:33:16.908180 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10822 09:33:16.948943 <30>[ 17.166921] systemd[1]: Mounting Huge Pages File System...
10823 09:33:16.955565 Mounting [0;1;39mHuge Pages File System[0m...
10824 09:33:16.970440 <30>[ 17.188435] systemd[1]: Mounting POSIX Message Queue File System...
10825 09:33:16.977101 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10826 09:33:16.994018 <30>[ 17.212648] systemd[1]: Mounting Kernel Debug File System...
10827 09:33:17.001020 Mounting [0;1;39mKernel Debug File System[0m...
10828 09:33:17.019817 <30>[ 17.235031] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10829 09:33:17.031948 <30>[ 17.246911] systemd[1]: Starting Create list of static device nodes for the current kernel...
10830 09:33:17.038203 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10831 09:33:17.059819 <30>[ 17.278408] systemd[1]: Starting Load Kernel Module configfs...
10832 09:33:17.066468 Starting [0;1;39mLoad Kernel Module configfs[0m...
10833 09:33:17.084562 <30>[ 17.303055] systemd[1]: Starting Load Kernel Module drm...
10834 09:33:17.091125 Starting [0;1;39mLoad Kernel Module drm[0m...
10835 09:33:17.107930 <30>[ 17.323227] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10836 09:33:17.122879 <30>[ 17.340853] systemd[1]: Starting Journal Service...
10837 09:33:17.125711 Starting [0;1;39mJournal Service[0m...
10838 09:33:17.145456 <30>[ 17.363517] systemd[1]: Starting Load Kernel Modules...
10839 09:33:17.151662 Starting [0;1;39mLoad Kernel Modules[0m...
10840 09:33:17.172494 <30>[ 17.387348] systemd[1]: Starting Remount Root and Kernel File Systems...
10841 09:33:17.178987 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10842 09:33:17.194673 <30>[ 17.413070] systemd[1]: Starting Coldplug All udev Devices...
10843 09:33:17.201294 Starting [0;1;39mColdplug All udev Devices[0m...
10844 09:33:17.219748 <30>[ 17.437861] systemd[1]: Started Journal Service.
10845 09:33:17.226044 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10846 09:33:17.243021 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10847 09:33:17.261402 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10848 09:33:17.277180 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10849 09:33:17.297645 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10850 09:33:17.314656 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10851 09:33:17.334460 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10852 09:33:17.350817 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10853 09:33:17.370122 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10854 09:33:17.384305 See 'systemctl status systemd-remount-fs.service' for details.
10855 09:33:17.445221 Mounting [0;1;39mKernel Configuration File System[0m...
10856 09:33:17.465473 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10857 09:33:17.478693 <46>[ 17.693687] systemd-journald[176]: Received client request to flush runtime journal.
10858 09:33:17.489957 Starting [0;1;39mLoad/Save Random Seed[0m...
10859 09:33:17.509402 Starting [0;1;39mApply Kernel Variables[0m...
10860 09:33:17.529527 Starting [0;1;39mCreate System Users[0m...
10861 09:33:17.549716 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10862 09:33:17.565814 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10863 09:33:17.585514 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10864 09:33:17.598261 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10865 09:33:17.614179 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10866 09:33:17.629820 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10867 09:33:17.669061 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10868 09:33:17.692757 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10869 09:33:17.704980 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10870 09:33:17.720519 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10871 09:33:17.765157 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10872 09:33:17.792309 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10873 09:33:17.813512 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10874 09:33:17.835167 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10875 09:33:17.891352 Starting [0;1;39mNetwork Time Synchronization[0m...
10876 09:33:17.910412 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10877 09:33:17.966837 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<6>[ 18.181984] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10878 09:33:17.976775 e Synchronizatio<6>[ 18.190341] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10879 09:33:17.976907 n[0m.
10880 09:33:17.986748 <6>[ 18.200460] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10881 09:33:18.003599 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10882 09:33:18.032731 [[0;32m OK [<3>[ 18.248222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 09:33:18.046129 0m] Created slice [0;1;39msyste<3>[ 18.258800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 09:33:18.055726 m-systemd\x2dbac<3>[ 18.268816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 09:33:18.062392 klight.slice[0m<6>[ 18.271013] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10886 09:33:18.062484 .
10887 09:33:18.072202 <3>[ 18.287448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 09:33:18.079279 <3>[ 18.295735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 09:33:18.088952 <6>[ 18.300031] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10890 09:33:18.095499 <4>[ 18.300757] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10891 09:33:18.102073 <6>[ 18.302669] usbcore: registered new interface driver r8152
10892 09:33:18.109174 <3>[ 18.303986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 09:33:18.112201 <6>[ 18.308486] mc: Linux media interface: v0.10
10894 09:33:18.119243 <4>[ 18.316222] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10895 09:33:18.129312 <3>[ 18.318497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 09:33:18.135968 <4>[ 18.321296] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10897 09:33:18.142561 <4>[ 18.321296] Fallback method does not support PEC.
10898 09:33:18.149712 <6>[ 18.331220] remoteproc remoteproc0: scp is available
10899 09:33:18.155784 <3>[ 18.332282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 09:33:18.162554 <6>[ 18.336961] remoteproc remoteproc0: powering up scp
10901 09:33:18.169163 <6>[ 18.338503] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10902 09:33:18.172405 <6>[ 18.338515] pci_bus 0000:00: root bus resource [bus 00-ff]
10903 09:33:18.179122 <6>[ 18.338524] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10904 09:33:18.189595 <6>[ 18.338529] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10905 09:33:18.196435 <6>[ 18.338755] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10906 09:33:18.202967 <6>[ 18.338776] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10907 09:33:18.210001 <6>[ 18.338857] pci 0000:00:00.0: supports D1 D2
10908 09:33:18.216607 <6>[ 18.338861] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10909 09:33:18.226587 <3>[ 18.345110] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 09:33:18.232757 <6>[ 18.347559] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10911 09:33:18.242858 <6>[ 18.352352] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10912 09:33:18.249428 <6>[ 18.353780] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10913 09:33:18.256520 <6>[ 18.353820] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10914 09:33:18.263168 <6>[ 18.353846] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10915 09:33:18.272718 <6>[ 18.353865] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10916 09:33:18.276207 <6>[ 18.354036] pci 0000:01:00.0: supports D1 D2
10917 09:33:18.282889 <6>[ 18.354042] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10918 09:33:18.289296 <3>[ 18.358346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 09:33:18.299847 <3>[ 18.366363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 09:33:18.306015 <6>[ 18.371308] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10921 09:33:18.312373 <6>[ 18.378818] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10922 09:33:18.319234 <6>[ 18.378873] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10923 09:33:18.329340 <6>[ 18.378880] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10924 09:33:18.336089 <6>[ 18.378910] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10925 09:33:18.342722 <6>[ 18.378928] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10926 09:33:18.352460 <6>[ 18.378946] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10927 09:33:18.355965 <6>[ 18.378963] pci 0000:00:00.0: PCI bridge to [bus 01]
10928 09:33:18.365406 <6>[ 18.378976] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10929 09:33:18.372010 <3>[ 18.379381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 09:33:18.378554 <6>[ 18.385434] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10931 09:33:18.388880 <3>[ 18.391371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 09:33:18.395233 <3>[ 18.394187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 09:33:18.405497 <6>[ 18.396365] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10934 09:33:18.415178 <6>[ 18.396699] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10935 09:33:18.421994 <6>[ 18.404136] videodev: Linux video capture interface: v2.00
10936 09:33:18.428335 <3>[ 18.405273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10937 09:33:18.434638 <6>[ 18.416761] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10938 09:33:18.444663 <3>[ 18.419386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 09:33:18.451776 <3>[ 18.420212] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10940 09:33:18.458163 <3>[ 18.420695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 09:33:18.468236 <6>[ 18.421337] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10942 09:33:18.471236 <6>[ 18.429226] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10943 09:33:18.481440 <6>[ 18.433224] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10944 09:33:18.491103 <3>[ 18.433324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 09:33:18.497628 <3>[ 18.433347] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 09:33:18.507824 <3>[ 18.433414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 09:33:18.514489 <6>[ 18.729907] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10948 09:33:18.521036 <6>[ 18.737035] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10949 09:33:18.530643 [[0;32m OK [<6>[ 18.737050] remoteproc remoteproc0: remote processor scp is now up
10950 09:33:18.537604 <5>[ 18.749768] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10951 09:33:18.543885 0m] Reached targ<6>[ 18.750152] usbcore: registered new interface driver cdc_ether
10952 09:33:18.557476 et [0;1;39mSyst<4>[ 18.754557] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10953 09:33:18.563764 em Time Set[0m.<6>[ 18.762325] usbcore: registered new interface driver r8153_ecm
10954 09:33:18.563846
10955 09:33:18.570748 <4>[ 18.769817] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10956 09:33:18.577082 <5>[ 18.780833] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10957 09:33:18.587298 <6>[ 18.782456] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10958 09:33:18.590215 <6>[ 18.787706] Bluetooth: Core ver 2.22
10959 09:33:18.601382 <4>[ 18.795333] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10960 09:33:18.607875 <6>[ 18.796317] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10961 09:33:18.614346 <6>[ 18.796910] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10962 09:33:18.628680 <6>[ 18.800429] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10963 09:33:18.631722 <6>[ 18.800547] usbcore: registered new interface driver uvcvideo
10964 09:33:18.638997 <6>[ 18.802703] NET: Registered PF_BLUETOOTH protocol family
10965 09:33:18.642451 <6>[ 18.810244] cfg80211: failed to load regulatory.db
10966 09:33:18.648874 <6>[ 18.814749] Bluetooth: HCI device and connection manager initialized
10967 09:33:18.655693 <6>[ 18.824159] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10968 09:33:18.665467 <3>[ 18.829382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 09:33:18.675631 <3>[ 18.830066] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10970 09:33:18.678781 <6>[ 18.831227] Bluetooth: HCI socket layer initialized
10971 09:33:18.685552 <6>[ 18.831234] Bluetooth: L2CAP socket layer initialized
10972 09:33:18.689208 <6>[ 18.831262] Bluetooth: SCO socket layer initialized
10973 09:33:18.695729 <6>[ 18.842704] r8152 2-1.3:1.0 eth0: v1.12.13
10974 09:33:18.702162 <3>[ 18.847798] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 09:33:18.713177 <3>[ 18.864915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 09:33:18.716315 <6>[ 18.868882] usbcore: registered new interface driver btusb
10977 09:33:18.729174 <4>[ 18.869671] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10978 09:33:18.732821 <3>[ 18.869693] Bluetooth: hci0: Failed to load firmware file (-2)
10979 09:33:18.739408 <3>[ 18.869699] Bluetooth: hci0: Failed to set up firmware (-2)
10980 09:33:18.748947 <4>[ 18.869703] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10981 09:33:18.756227 <6>[ 18.885465] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10982 09:33:18.762760 <6>[ 18.892439] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10983 09:33:18.772709 <3>[ 18.912325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 09:33:18.779300 <6>[ 18.913617] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10985 09:33:18.789174 <3>[ 18.937227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 09:33:18.792702 <6>[ 18.958727] mt7921e 0000:01:00.0: ASIC revision: 79610010
10987 09:33:18.802646 <3>[ 18.986086] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 09:33:18.808963 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10989 09:33:18.872661 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd<4>[ 19.083321] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 09:33:18.872808 _backlight[0m...
10991 09:33:18.894159 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10992 09:33:18.921208 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10993 09:33:18.993467 <4>[ 19.205336] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 09:33:19.083306 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10995 09:33:19.099956 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10996 09:33:19.117952 <4>[ 19.329662] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 09:33:19.124243 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10998 09:33:19.147425 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10999 09:33:19.160226 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11000 09:33:19.184068 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11001 09:33:19.196169 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11002 09:33:19.212574 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11003 09:33:19.235777 [[0;32m OK [<4>[ 19.449182] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11004 09:33:19.242115 0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11005 09:33:19.297254 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11006 09:33:19.336235 Starting [0;1;39mUser Login Management[0m...
11007 09:33:19.357479 <4>[ 19.569803] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 09:33:19.374448 Starting [0;1;39mPermit User Sessions[0m...
11009 09:33:19.394942 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11010 09:33:19.413428 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11011 09:33:19.430668 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11012 09:33:19.449860 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11013 09:33:19.481849 <4>[ 19.694016] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11014 09:33:19.526194 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11015 09:33:19.546436 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11016 09:33:19.565071 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11017 09:33:19.580770 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11018 09:33:19.600904 <4>[ 19.813219] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 09:33:19.607903 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11020 09:33:19.661491 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11021 09:33:19.700394 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11022 09:33:19.720818 <4>[ 19.933063] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11023 09:33:19.751090
11024 09:33:19.751181
11025 09:33:19.754341 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11026 09:33:19.754427
11027 09:33:19.758019 debian-bullseye-arm64 login: root (automatic login)
11028 09:33:19.758100
11029 09:33:19.758165
11030 09:33:19.786791 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
11031 09:33:19.786881
11032 09:33:19.793495 The programs included with the Debian GNU/Linux system are free software;
11033 09:33:19.799970 the exact distribution terms for each program are described in the
11034 09:33:19.803526 individual files in /usr/share/doc/*/copyright.
11035 09:33:19.803607
11036 09:33:19.810008 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11037 09:33:19.812932 permitted by applicable law.
11038 09:33:19.813316 Matched prompt #10: / #
11040 09:33:19.813517 Setting prompt string to ['/ #']
11041 09:33:19.813610 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11043 09:33:19.813798 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11044 09:33:19.813887 start: 2.2.6 expect-shell-connection (timeout 00:02:42) [common]
11045 09:33:19.813960 Setting prompt string to ['/ #']
11046 09:33:19.814020 Forcing a shell prompt, looking for ['/ #']
11048 09:33:19.864279 / #
11049 09:33:19.864395 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11050 09:33:19.864472 Waiting using forced prompt support (timeout 00:02:30)
11051 09:33:19.864567 <4>[ 20.053317] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11052 09:33:19.869149
11053 09:33:19.869416 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11054 09:33:19.869511 start: 2.2.7 export-device-env (timeout 00:02:42) [common]
11055 09:33:19.869601 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11056 09:33:19.869683 end: 2.2 depthcharge-retry (duration 00:02:18) [common]
11057 09:33:19.869767 end: 2 depthcharge-action (duration 00:02:18) [common]
11058 09:33:19.869851 start: 3 lava-test-retry (timeout 00:07:19) [common]
11059 09:33:19.869934 start: 3.1 lava-test-shell (timeout 00:07:19) [common]
11060 09:33:19.870007 Using namespace: common
11062 09:33:19.970305 / # #
11063 09:33:19.970434 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11064 09:33:19.970551 #<4>[ 20.177281] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11065 09:33:19.975728
11066 09:33:19.975992 Using /lava-11826824
11068 09:33:20.076334 / #export SHELL=/bin/sh
11069 09:33:20.076504 export SHELL=/bin/sh<3>[ 20.295285] mt7921e 0000:01:00.0: hardware init failed
11070 09:33:20.081080
11072 09:33:20.181584 / # . /lava-11826824/environment
11073 09:33:20.187172 . /lava-11826824/environment
11075 09:33:20.287714 / # /lava-11826824/bin/lava-test-runner /lava-11826824/0
11076 09:33:20.287832 Test shell timeout: 10s (minimum of the action and connection timeout)
11077 09:33:20.293036 /lava-11826824/bin/lava-test-runner /lava-11826824/0
11078 09:33:20.319812 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.536528] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 11826824_1.5.2.3.1>
11079 09:33:20.320073 Received signal: <STARTRUN> 0_igt-gpu-panfrost 11826824_1.5.2.3.1
11080 09:33:20.320148 Starting test lava.0_igt-gpu-panfrost (11826824_1.5.2.3.1)
11081 09:33:20.320232 Skipping test definition patterns.
11082 09:33:20.323136 nfrost
11083 09:33:20.326579 + cd /lava-11826824/0/tests/0_igt-gpu-panfrost
11084 09:33:20.326661 + cat uuid
11085 09:33:20.329423 + UUID=11826824_1.5.2.3.1
11086 09:33:20.329505 + set +x
11087 09:33:20.343177 Received signal: <TESTSET> START panfrost_gem_new
11088 09:33:20.343261 Starting test_set panfrost_gem_new
11089 09:33:20.346646 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime p<8>[ 20.561914] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11090 09:33:20.346729 anfrost_submit
11091 09:33:20.363074 <14>[ 20.581569] [IGT] panfrost_gem_new: executing
11092 09:33:20.369273 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.588545] [IGT] panfrost_gem_new: exiting, ret=77
11093 09:33:20.372497 rch64) (Linux: 6.1.58-cip7 aarch64)
11094 09:33:20.385934 Test requirement not met in function drm_op<8>[ 20.601152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11095 09:33:20.386187 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11097 09:33:20.389370 en_driver, file ../lib/drmtest.c:621:
11098 09:33:20.389451 Test requirement: !(fd<0)
11099 09:33:20.396073 No known gpu found for chipset flags 0x32 (panfrost)
11100 09:33:20.399645 Last errno: 2, No such file or directory
11101 09:33:20.402448 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11102 09:33:20.409336 <14>[ 20.628198] [IGT] panfrost_gem_new: executing
11103 09:33:20.419516 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.635981] [IGT] panfrost_gem_new: exiting, ret=77
11104 09:33:20.419600 .1.58-cip7 aarch64)
11105 09:33:20.432710 Test requirement not met in function drm_open_driver, file <8>[ 20.648178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11106 09:33:20.432975 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11108 09:33:20.435733 ../lib/drmtest.c:621:
11109 09:33:20.435813 Test requirement: !(fd<0)
11110 09:33:20.442559 No known gpu found for chipset flags 0x32 (panfrost)
11111 09:33:20.445601 Last errno: 2, No such file or directory
11112 09:33:20.449223 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11113 09:33:20.459232 <14>[ 20.677781] [IGT] panfrost_gem_new: executing
11114 09:33:20.469224 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.685643] [IGT] panfrost_gem_new: exiting, ret=77
11115 09:33:20.469307 .1.58-cip7 aarch64)
11116 09:33:20.482094 Test requirement not met in function drm_open_driver, file <8>[ 20.698015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11117 09:33:20.482349 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11119 09:33:20.485297 ../lib/drmtest.c:621:
11120 09:33:20.488958 Test requ<8>[ 20.708495] <LAVA_SIGNAL_TESTSET STOP>
11121 09:33:20.489221 Received signal: <TESTSET> STOP
11122 09:33:20.489295 Closing test_set panfrost_gem_new
11123 09:33:20.492026 irement: !(fd<0)
11124 09:33:20.495174 No known gpu found for chipset flags 0x32 (panfrost)
11125 09:33:20.498750 Last errno: 2, No such file or directory
11126 09:33:20.502318 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11127 09:33:20.520090 <8>[ 20.738683] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11128 09:33:20.520342 Received signal: <TESTSET> START panfrost_get_param
11129 09:33:20.520410 Starting test_set panfrost_get_param
11130 09:33:20.553913 <14>[ 20.772283] [IGT] panfrost_get_param: executing
11131 09:33:20.563364 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.780309] [IGT] panfrost_get_param: exiting, ret=77
11132 09:33:20.567024 .1.58-cip7 aarch64)
11133 09:33:20.573413 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11134 09:33:20.579848 Test requ<8>[ 20.796128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11135 09:33:20.579930 irement: !(fd<0)
11136 09:33:20.580196 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11138 09:33:20.587070 No known gpu found for chipset flags 0x32 (panfrost)
11139 09:33:20.589925 Last errno: 2, No such file or directory
11140 09:33:20.593264 [1mSubtest base-params: SKIP (0.000s)[0m
11141 09:33:20.607595 <14>[ 20.826201] [IGT] panfrost_get_param: executing
11142 09:33:20.617259 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.834091] [IGT] panfrost_get_param: exiting, ret=77
11143 09:33:20.620655 rch64) (Linux: 6.1.58-cip7 aarch64)
11144 09:33:20.630801 Test requirement not met in function drm_open_driver, file <8>[ 20.847640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11145 09:33:20.631056 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11147 09:33:20.633715 ../lib/drmtest.c:621:
11148 09:33:20.637323 Test requirement: !(fd<0)
11149 09:33:20.640547 No known gpu found for chipset flags 0x32 (panfrost)
11150 09:33:20.643908 Last errno: 2, No such file or directory
11151 09:33:20.646889 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11152 09:33:20.657708 <14>[ 20.876413] [IGT] panfrost_get_param: executing
11153 09:33:20.667370 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.884618] [IGT] panfrost_get_param: exiting, ret=77
11154 09:33:20.670807 .1.58-cip7 aarch64)
11155 09:33:20.677396 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11156 09:33:20.684483 Test requ<8>[ 20.900813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11157 09:33:20.684737 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11159 09:33:20.687640 irement: !(fd<0)
11160 09:33:20.690598 No known gpu f<8>[ 20.910171] <LAVA_SIGNAL_TESTSET STOP>
11161 09:33:20.690850 Received signal: <TESTSET> STOP
11162 09:33:20.690918 Closing test_set panfrost_get_param
11163 09:33:20.694288 ound for chipset flags 0x32 (panfrost)
11164 09:33:20.697264 Last errno: 2, No such file or directory
11165 09:33:20.703681 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11166 09:33:20.721226 <8>[ 20.940215] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11167 09:33:20.721483 Received signal: <TESTSET> START panfrost_prime
11168 09:33:20.721555 Starting test_set panfrost_prime
11169 09:33:20.747944 <14>[ 20.966634] [IGT] panfrost_prime: executing
11170 09:33:20.757613 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.974214] [IGT] panfrost_prime: exiting, ret=77
11171 09:33:20.757697 .1.58-cip7 aarch64)
11172 09:33:20.770861 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 20.988738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11173 09:33:20.771125 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11175 09:33:20.774154 :621:
11176 09:33:20.777794 Received signal: <TESTSET> STOP
11177 09:33:20.777873 Closing test_set panfrost_prime
11178 09:33:20.780656 Test requirement: !(fd<0)<8>[ 20.998111] <LAVA_SIGNAL_TESTSET STOP>
11179 09:33:20.780738
11180 09:33:20.784105 No known gpu found for chipset flags 0x32 (panfrost)
11181 09:33:20.787708 Last errno: 2, No such file or directory
11182 09:33:20.790650 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11183 09:33:20.809993 <8>[ 21.028463] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11184 09:33:20.810247 Received signal: <TESTSET> START panfrost_submit
11185 09:33:20.810317 Starting test_set panfrost_submit
11186 09:33:20.836014 <14>[ 21.054828] [IGT] panfrost_submit: executing
11187 09:33:20.845992 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.063221] [IGT] panfrost_submit: exiting, ret=77
11188 09:33:20.846075 .1.58-cip7 aarch64)
11189 09:33:20.859114 Test requirement not met in function drm_open_driver, file <8>[ 21.074636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11190 09:33:20.859197 ../lib/drmtest.c:621:
11191 09:33:20.859431 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11193 09:33:20.862643 Test requirement: !(fd<0)
11194 09:33:20.869341 No known gpu found for chipset flags 0x32 (panfrost)
11195 09:33:20.872245 Last errno: 2, No such file or directory
11196 09:33:20.875828 [1mSubtest pan-submit: SKIP (0.000s)[0m
11197 09:33:20.886158 <14>[ 21.104722] [IGT] panfrost_submit: executing
11198 09:33:20.895806 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.112474] [IGT] panfrost_submit: exiting, ret=77
11199 09:33:20.895905 .1.58-cip7 aarch64)
11200 09:33:20.902587 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11201 09:33:20.912522 Test requ<8>[ 21.128209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11202 09:33:20.912801 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11204 09:33:20.915516 irement: !(fd<0)
11205 09:33:20.918864 No known gpu found for chipset flags 0x32 (panfrost)
11206 09:33:20.922375 Last errno: 2, No such file or directory
11207 09:33:20.929117 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11208 09:33:20.940711 <14>[ 21.159532] [IGT] panfrost_submit: executing
11209 09:33:20.950863 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.167508] [IGT] panfrost_submit: exiting, ret=77
11210 09:33:20.950947 .1.58-cip7 aarch64)
11211 09:33:20.960509 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11212 09:33:20.967310 Test requ<8>[ 21.183205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11213 09:33:20.967592 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11215 09:33:20.970919 irement: !(fd<0)
11216 09:33:20.973897 No known gpu found for chipset flags 0x32 (panfrost)
11217 09:33:20.977485 Last errno: 2, No such file or directory
11218 09:33:20.983610 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11219 09:33:20.996207 <14>[ 21.214743] [IGT] panfrost_submit: executing
11220 09:33:21.006290 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.222504] [IGT] panfrost_submit: exiting, ret=77
11221 09:33:21.006372 .1.58-cip7 aarch64)
11222 09:33:21.022474 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 21.236984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11223 09:33:21.022558 :621:
11224 09:33:21.022795 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11226 09:33:21.026051 Test requirement: !(fd<0)
11227 09:33:21.028798 No known gpu found for chipset flags 0x32 (panfrost)
11228 09:33:21.032378 Last errno: 2, No such file or directory
11229 09:33:21.039170 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11230 09:33:21.048978 <14>[ 21.267741] [IGT] panfrost_submit: executing
11231 09:33:21.058582 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.275495] [IGT] panfrost_submit: exiting, ret=77
11232 09:33:21.058663 .1.58-cip7 aarch64)
11233 09:33:21.068639 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11234 09:33:21.075147 Test requ<8>[ 21.291303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11235 09:33:21.075426 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11237 09:33:21.078413 irement: !(fd<0)
11238 09:33:21.081834 No known gpu found for chipset flags 0x32 (panfrost)
11239 09:33:21.085294 Last errno: 2, No such file or directory
11240 09:33:21.091673 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11241 09:33:21.104825 <14>[ 21.323780] [IGT] panfrost_submit: executing
11242 09:33:21.114789 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.331542] [IGT] panfrost_submit: exiting, ret=77
11243 09:33:21.114873 .1.58-cip7 aarch64)
11244 09:33:21.121471 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11245 09:33:21.131935 Test requ<8>[ 21.347165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11246 09:33:21.132191 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11248 09:33:21.135132 irement: !(fd<0)
11249 09:33:21.138249 No known gpu found for chipset flags 0x32 (panfrost)
11250 09:33:21.141285 Last errno: 2, No such file or directory
11251 09:33:21.148091 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11252 09:33:21.159565 <14>[ 21.378125] [IGT] panfrost_submit: executing
11253 09:33:21.165655 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.385852] [IGT] panfrost_submit: exiting, ret=77
11254 09:33:21.169321 rch64) (Linux: 6.1.58-cip7 aarch64)
11255 09:33:21.182254 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 21.400388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11256 09:33:21.182510 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11258 09:33:21.185753 :621:
11259 09:33:21.185833 Test requirement: !(fd<0)
11260 09:33:21.192389 No known gpu found for chipset flags 0x32 (panfrost)
11261 09:33:21.195413 Last errno: 2, No such file or directory
11262 09:33:21.198806 [1mSubtest pan-reset: SKIP (0.000s)[0m
11263 09:33:21.210753 <14>[ 21.429891] [IGT] panfrost_submit: executing
11264 09:33:21.221139 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.438239] [IGT] panfrost_submit: exiting, ret=77
11265 09:33:21.221222 .1.58-cip7 aarch64)
11266 09:33:21.234323 Test requirement not met in function drm_op<8>[ 21.449331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11267 09:33:21.234580 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11269 09:33:21.237306 en_driver, file ../lib/drmtest.c:621:
11270 09:33:21.237386 Test requirement: !(fd<0)
11271 09:33:21.243975 No known gpu found for chipset flags 0x32 (panfrost)
11272 09:33:21.247584 Last errno: 2, No such file or directory
11273 09:33:21.250587 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11274 09:33:21.261079 <14>[ 21.479889] [IGT] panfrost_submit: executing
11275 09:33:21.271225 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.487657] [IGT] panfrost_submit: exiting, ret=77
11276 09:33:21.271307 .1.58-cip7 aarch64)
11277 09:33:21.280943 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11278 09:33:21.287351 Test requ<8>[ 21.503268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11279 09:33:21.287630 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11281 09:33:21.290463 irement: !(fd<0)
11282 09:33:21.293998 No known gpu f<8>[ 21.513984] <LAVA_SIGNAL_TESTSET STOP>
11283 09:33:21.294250 Received signal: <TESTSET> STOP
11284 09:33:21.294320 Closing test_set panfrost_submit
11285 09:33:21.304160 ound for chipset<8>[ 21.519666] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 11826824_1.5.2.3.1>
11286 09:33:21.304241 flags 0x32 (panfrost)
11287 09:33:21.304477 Received signal: <ENDRUN> 0_igt-gpu-panfrost 11826824_1.5.2.3.1
11288 09:33:21.304557 Ending use of test pattern.
11289 09:33:21.304616 Ending test lava.0_igt-gpu-panfrost (11826824_1.5.2.3.1), duration 0.98
11291 09:33:21.307513 Last errno: 2, No such file or directory
11292 09:33:21.313887 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11293 09:33:21.313968 + set +x
11294 09:33:21.316899 <LAVA_TEST_RUNNER EXIT>
11295 09:33:21.317149 ok: lava_test_shell seems to have completed
11296 09:33:21.317457 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11297 09:33:21.317558 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11298 09:33:21.317644 end: 3 lava-test-retry (duration 00:00:01) [common]
11299 09:33:21.317727 start: 4 finalize (timeout 00:07:17) [common]
11300 09:33:21.317814 start: 4.1 power-off (timeout 00:00:30) [common]
11301 09:33:21.317985 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11302 09:33:21.395990 >> Command sent successfully.
11303 09:33:21.398525 Returned 0 in 0 seconds
11304 09:33:21.498934 end: 4.1 power-off (duration 00:00:00) [common]
11306 09:33:21.499285 start: 4.2 read-feedback (timeout 00:07:17) [common]
11307 09:33:21.499607 Listened to connection for namespace 'common' for up to 1s
11308 09:33:22.499529 Finalising connection for namespace 'common'
11309 09:33:22.499739 Disconnecting from shell: Finalise
11310 09:33:22.499822 / #
11311 09:33:22.600149 end: 4.2 read-feedback (duration 00:00:01) [common]
11312 09:33:22.600319 end: 4 finalize (duration 00:00:01) [common]
11313 09:33:22.600437 Cleaning after the job
11314 09:33:22.600533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/ramdisk
11315 09:33:22.608399 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/kernel
11316 09:33:22.616855 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/dtb
11317 09:33:22.617022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826824/tftp-deploy-qyjri2xd/modules
11318 09:33:22.624335 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826824
11319 09:33:22.743034 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826824
11320 09:33:22.743206 Job finished correctly