Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 41
- Errors: 0
- Boot result: PASS
1 09:32:35.691709 lava-dispatcher, installed at version: 2023.08
2 09:32:35.691937 start: 0 validate
3 09:32:35.692072 Start time: 2023-10-20 09:32:35.692065+00:00 (UTC)
4 09:32:35.692184 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:32:35.692314 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:32:35.982044 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:32:35.982783 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:32:36.254879 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:32:36.255720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:32:36.521903 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:32:36.522654 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:32:36.800777 validate duration: 1.11
14 09:32:36.802139 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:32:36.802686 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:32:36.803185 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:32:36.803838 Not decompressing ramdisk as can be used compressed.
18 09:32:36.804319 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 09:32:36.804684 saving as /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/ramdisk/rootfs.cpio.gz
20 09:32:36.805048 total size: 43284872 (41 MB)
21 09:32:36.810337 progress 0 % (0 MB)
22 09:32:36.843580 progress 5 % (2 MB)
23 09:32:36.858658 progress 10 % (4 MB)
24 09:32:36.870305 progress 15 % (6 MB)
25 09:32:36.881620 progress 20 % (8 MB)
26 09:32:36.892915 progress 25 % (10 MB)
27 09:32:36.904292 progress 30 % (12 MB)
28 09:32:36.915623 progress 35 % (14 MB)
29 09:32:36.927016 progress 40 % (16 MB)
30 09:32:36.938249 progress 45 % (18 MB)
31 09:32:36.949417 progress 50 % (20 MB)
32 09:32:36.960948 progress 55 % (22 MB)
33 09:32:36.972198 progress 60 % (24 MB)
34 09:32:36.983394 progress 65 % (26 MB)
35 09:32:36.994612 progress 70 % (28 MB)
36 09:32:37.005834 progress 75 % (30 MB)
37 09:32:37.017206 progress 80 % (33 MB)
38 09:32:37.028589 progress 85 % (35 MB)
39 09:32:37.039953 progress 90 % (37 MB)
40 09:32:37.051100 progress 95 % (39 MB)
41 09:32:37.062234 progress 100 % (41 MB)
42 09:32:37.062512 41 MB downloaded in 0.26 s (160.32 MB/s)
43 09:32:37.062720 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:32:37.063096 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:32:37.063213 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:32:37.063329 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:32:37.063497 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:32:37.063593 saving as /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/kernel/Image
50 09:32:37.063683 total size: 49236480 (46 MB)
51 09:32:37.063769 No compression specified
52 09:32:37.064871 progress 0 % (0 MB)
53 09:32:37.077653 progress 5 % (2 MB)
54 09:32:37.090319 progress 10 % (4 MB)
55 09:32:37.103078 progress 15 % (7 MB)
56 09:32:37.116028 progress 20 % (9 MB)
57 09:32:37.129082 progress 25 % (11 MB)
58 09:32:37.141870 progress 30 % (14 MB)
59 09:32:37.154853 progress 35 % (16 MB)
60 09:32:37.168210 progress 40 % (18 MB)
61 09:32:37.181393 progress 45 % (21 MB)
62 09:32:37.194055 progress 50 % (23 MB)
63 09:32:37.206771 progress 55 % (25 MB)
64 09:32:37.219630 progress 60 % (28 MB)
65 09:32:37.232654 progress 65 % (30 MB)
66 09:32:37.245359 progress 70 % (32 MB)
67 09:32:37.258136 progress 75 % (35 MB)
68 09:32:37.271127 progress 80 % (37 MB)
69 09:32:37.284136 progress 85 % (39 MB)
70 09:32:37.297089 progress 90 % (42 MB)
71 09:32:37.309598 progress 95 % (44 MB)
72 09:32:37.322083 progress 100 % (46 MB)
73 09:32:37.322279 46 MB downloaded in 0.26 s (181.58 MB/s)
74 09:32:37.322428 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:32:37.322659 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:32:37.322746 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:32:37.322831 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:32:37.322970 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:32:37.323040 saving as /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/dtb/mt8192-asurada-spherion-r0.dtb
81 09:32:37.323116 total size: 47278 (0 MB)
82 09:32:37.323211 No compression specified
83 09:32:37.324572 progress 69 % (0 MB)
84 09:32:37.324845 progress 100 % (0 MB)
85 09:32:37.325000 0 MB downloaded in 0.00 s (23.95 MB/s)
86 09:32:37.325120 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:32:37.325339 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:32:37.325422 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:32:37.325504 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:32:37.325615 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:32:37.325682 saving as /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/modules/modules.tar
93 09:32:37.325742 total size: 8614716 (8 MB)
94 09:32:37.325802 Using unxz to decompress xz
95 09:32:37.329961 progress 0 % (0 MB)
96 09:32:37.350991 progress 5 % (0 MB)
97 09:32:37.375043 progress 10 % (0 MB)
98 09:32:37.398467 progress 15 % (1 MB)
99 09:32:37.421864 progress 20 % (1 MB)
100 09:32:37.445792 progress 25 % (2 MB)
101 09:32:37.471476 progress 30 % (2 MB)
102 09:32:37.497428 progress 35 % (2 MB)
103 09:32:37.520876 progress 40 % (3 MB)
104 09:32:37.544677 progress 45 % (3 MB)
105 09:32:37.569749 progress 50 % (4 MB)
106 09:32:37.593597 progress 55 % (4 MB)
107 09:32:37.618203 progress 60 % (4 MB)
108 09:32:37.643419 progress 65 % (5 MB)
109 09:32:37.670132 progress 70 % (5 MB)
110 09:32:37.693333 progress 75 % (6 MB)
111 09:32:37.720136 progress 80 % (6 MB)
112 09:32:37.745719 progress 85 % (7 MB)
113 09:32:37.770622 progress 90 % (7 MB)
114 09:32:37.799768 progress 95 % (7 MB)
115 09:32:37.827477 progress 100 % (8 MB)
116 09:32:37.833718 8 MB downloaded in 0.51 s (16.17 MB/s)
117 09:32:37.833971 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:32:37.834231 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:32:37.834323 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:32:37.834419 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:32:37.834502 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:32:37.834586 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:32:37.834809 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3
125 09:32:37.834944 makedir: /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin
126 09:32:37.835050 makedir: /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/tests
127 09:32:37.835150 makedir: /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/results
128 09:32:37.835266 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-add-keys
129 09:32:37.835412 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-add-sources
130 09:32:37.835581 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-background-process-start
131 09:32:37.835713 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-background-process-stop
132 09:32:37.835848 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-common-functions
133 09:32:37.835974 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-echo-ipv4
134 09:32:37.836099 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-install-packages
135 09:32:37.836223 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-installed-packages
136 09:32:37.836347 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-os-build
137 09:32:37.836472 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-probe-channel
138 09:32:37.836597 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-probe-ip
139 09:32:37.836721 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-target-ip
140 09:32:37.836845 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-target-mac
141 09:32:37.836968 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-target-storage
142 09:32:37.837097 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-case
143 09:32:37.837222 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-event
144 09:32:37.837347 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-feedback
145 09:32:37.837470 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-raise
146 09:32:37.837595 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-reference
147 09:32:37.837718 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-runner
148 09:32:37.837841 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-set
149 09:32:37.837966 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-test-shell
150 09:32:37.838093 Updating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-install-packages (oe)
151 09:32:37.838246 Updating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/bin/lava-installed-packages (oe)
152 09:32:37.838369 Creating /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/environment
153 09:32:37.838469 LAVA metadata
154 09:32:37.838543 - LAVA_JOB_ID=11826833
155 09:32:37.838607 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:32:37.838709 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:32:37.838776 skipped lava-vland-overlay
158 09:32:37.838851 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:32:37.838932 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:32:37.838993 skipped lava-multinode-overlay
161 09:32:37.839067 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:32:37.839151 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:32:37.839226 Loading test definitions
164 09:32:37.839321 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:32:37.839397 Using /lava-11826833 at stage 0
166 09:32:37.839714 uuid=11826833_1.5.2.3.1 testdef=None
167 09:32:37.839810 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:32:37.839898 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:32:37.840428 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:32:37.840644 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:32:37.841257 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:32:37.841483 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:32:37.842079 runner path: /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/0/tests/0_igt-kms-mediatek test_uuid 11826833_1.5.2.3.1
176 09:32:37.842240 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:32:37.842441 Creating lava-test-runner.conf files
179 09:32:37.842504 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826833/lava-overlay-_0f_rfc3/lava-11826833/0 for stage 0
180 09:32:37.842593 - 0_igt-kms-mediatek
181 09:32:37.842688 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:32:37.842775 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:32:37.849486 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:32:37.849589 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:32:37.849676 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:32:37.849760 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:32:37.849848 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:32:39.248718 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:32:39.249116 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:32:39.249236 extracting modules file /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826833/extract-overlay-ramdisk-adb0m_zo/ramdisk
191 09:32:39.476619 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:32:39.476783 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 09:32:39.476877 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826833/compress-overlay-r8o_rxis/overlay-1.5.2.4.tar.gz to ramdisk
194 09:32:39.476948 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826833/compress-overlay-r8o_rxis/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826833/extract-overlay-ramdisk-adb0m_zo/ramdisk
195 09:32:39.483412 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:32:39.483520 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 09:32:39.483611 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:32:39.483697 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 09:32:39.483887 Building ramdisk /var/lib/lava/dispatcher/tmp/11826833/extract-overlay-ramdisk-adb0m_zo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826833/extract-overlay-ramdisk-adb0m_zo/ramdisk
200 09:32:40.515553 >> 369946 blocks
201 09:32:46.207039 rename /var/lib/lava/dispatcher/tmp/11826833/extract-overlay-ramdisk-adb0m_zo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/ramdisk/ramdisk.cpio.gz
202 09:32:46.207501 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 09:32:46.207627 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 09:32:46.207740 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 09:32:46.207852 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/kernel/Image'
206 09:32:58.287022 Returned 0 in 12 seconds
207 09:32:58.388037 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/kernel/image.itb
208 09:32:59.222680 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:32:59.223067 output: Created: Fri Oct 20 10:32:59 2023
210 09:32:59.223142 output: Image 0 (kernel-1)
211 09:32:59.223209 output: Description:
212 09:32:59.223271 output: Created: Fri Oct 20 10:32:59 2023
213 09:32:59.223332 output: Type: Kernel Image
214 09:32:59.223394 output: Compression: lzma compressed
215 09:32:59.223454 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
216 09:32:59.223511 output: Architecture: AArch64
217 09:32:59.223572 output: OS: Linux
218 09:32:59.223630 output: Load Address: 0x00000000
219 09:32:59.223688 output: Entry Point: 0x00000000
220 09:32:59.223753 output: Hash algo: crc32
221 09:32:59.223810 output: Hash value: 05d3904e
222 09:32:59.223864 output: Image 1 (fdt-1)
223 09:32:59.223921 output: Description: mt8192-asurada-spherion-r0
224 09:32:59.223974 output: Created: Fri Oct 20 10:32:59 2023
225 09:32:59.224026 output: Type: Flat Device Tree
226 09:32:59.224078 output: Compression: uncompressed
227 09:32:59.224130 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:32:59.224182 output: Architecture: AArch64
229 09:32:59.224234 output: Hash algo: crc32
230 09:32:59.224286 output: Hash value: cc4352de
231 09:32:59.224338 output: Image 2 (ramdisk-1)
232 09:32:59.224389 output: Description: unavailable
233 09:32:59.224441 output: Created: Fri Oct 20 10:32:59 2023
234 09:32:59.224493 output: Type: RAMDisk Image
235 09:32:59.224544 output: Compression: Unknown Compression
236 09:32:59.224596 output: Data Size: 56425397 Bytes = 55102.93 KiB = 53.81 MiB
237 09:32:59.224648 output: Architecture: AArch64
238 09:32:59.224699 output: OS: Linux
239 09:32:59.224750 output: Load Address: unavailable
240 09:32:59.224801 output: Entry Point: unavailable
241 09:32:59.224852 output: Hash algo: crc32
242 09:32:59.224903 output: Hash value: 198b7a8b
243 09:32:59.224954 output: Default Configuration: 'conf-1'
244 09:32:59.225006 output: Configuration 0 (conf-1)
245 09:32:59.225057 output: Description: mt8192-asurada-spherion-r0
246 09:32:59.225109 output: Kernel: kernel-1
247 09:32:59.225160 output: Init Ramdisk: ramdisk-1
248 09:32:59.225211 output: FDT: fdt-1
249 09:32:59.225262 output: Loadables: kernel-1
250 09:32:59.225313 output:
251 09:32:59.225515 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 09:32:59.225613 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 09:32:59.225724 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 09:32:59.225816 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 09:32:59.225894 No LXC device requested
256 09:32:59.225971 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:32:59.226052 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 09:32:59.226126 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:32:59.226195 Checking files for TFTP limit of 4294967296 bytes.
260 09:32:59.226692 end: 1 tftp-deploy (duration 00:00:22) [common]
261 09:32:59.226789 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:32:59.226879 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:32:59.226999 substitutions:
264 09:32:59.227064 - {DTB}: 11826833/tftp-deploy-49sr7nl6/dtb/mt8192-asurada-spherion-r0.dtb
265 09:32:59.227128 - {INITRD}: 11826833/tftp-deploy-49sr7nl6/ramdisk/ramdisk.cpio.gz
266 09:32:59.227186 - {KERNEL}: 11826833/tftp-deploy-49sr7nl6/kernel/Image
267 09:32:59.227243 - {LAVA_MAC}: None
268 09:32:59.227298 - {PRESEED_CONFIG}: None
269 09:32:59.227352 - {PRESEED_LOCAL}: None
270 09:32:59.227405 - {RAMDISK}: 11826833/tftp-deploy-49sr7nl6/ramdisk/ramdisk.cpio.gz
271 09:32:59.227459 - {ROOT_PART}: None
272 09:32:59.227512 - {ROOT}: None
273 09:32:59.227565 - {SERVER_IP}: 192.168.201.1
274 09:32:59.227617 - {TEE}: None
275 09:32:59.227670 Parsed boot commands:
276 09:32:59.227727 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:32:59.227908 Parsed boot commands: tftpboot 192.168.201.1 11826833/tftp-deploy-49sr7nl6/kernel/image.itb 11826833/tftp-deploy-49sr7nl6/kernel/cmdline
278 09:32:59.227997 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:32:59.228082 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:32:59.228175 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:32:59.228266 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:32:59.228337 Not connected, no need to disconnect.
283 09:32:59.228412 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:32:59.228492 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:32:59.228560 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 09:32:59.232509 Setting prompt string to ['lava-test: # ']
287 09:32:59.232875 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:32:59.232984 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:32:59.233082 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:32:59.233172 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:32:59.233364 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 09:33:04.382845 >> Command sent successfully.
293 09:33:04.394481 Returned 0 in 5 seconds
294 09:33:04.495880 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:33:04.497721 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:33:04.498370 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:33:04.498947 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:33:04.499471 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:33:04.500073 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:33:04.501401 [Enter `^Ec?' for help]
302 09:33:04.660160
303 09:33:04.660755
304 09:33:04.661141 F0: 102B 0000
305 09:33:04.661486
306 09:33:04.661815 F3: 1001 0000 [0200]
307 09:33:04.662142
308 09:33:04.663801 F3: 1001 0000
309 09:33:04.664270
310 09:33:04.664649 F7: 102D 0000
311 09:33:04.664992
312 09:33:04.665318 F1: 0000 0000
313 09:33:04.665639
314 09:33:04.667691 V0: 0000 0000 [0001]
315 09:33:04.668207
316 09:33:04.668576 00: 0007 8000
317 09:33:04.668931
318 09:33:04.671181 01: 0000 0000
319 09:33:04.671609
320 09:33:04.671979 BP: 0C00 0209 [0000]
321 09:33:04.672292
322 09:33:04.675141 G0: 1182 0000
323 09:33:04.675802
324 09:33:04.676255 EC: 0000 0021 [4000]
325 09:33:04.676580
326 09:33:04.678740 S7: 0000 0000 [0000]
327 09:33:04.679161
328 09:33:04.679780 CC: 0000 0000 [0001]
329 09:33:04.680138
330 09:33:04.681853 T0: 0000 0040 [010F]
331 09:33:04.682272
332 09:33:04.682602 Jump to BL
333 09:33:04.682910
334 09:33:04.706711
335 09:33:04.707266
336 09:33:04.707634
337 09:33:04.713559 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:33:04.717271 ARM64: Exception handlers installed.
339 09:33:04.720388 ARM64: Testing exception
340 09:33:04.724365 ARM64: Done test exception
341 09:33:04.731495 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:33:04.742088 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:33:04.749759 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:33:04.759830 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:33:04.766574 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:33:04.773005 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:33:04.783483 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:33:04.789935 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:33:04.810191 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:33:04.812833 WDT: Last reset was cold boot
351 09:33:04.816618 SPI1(PAD0) initialized at 2873684 Hz
352 09:33:04.819649 SPI5(PAD0) initialized at 992727 Hz
353 09:33:04.823141 VBOOT: Loading verstage.
354 09:33:04.829610 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:33:04.833035 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:33:04.836166 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:33:04.839580 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:33:04.846703 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:33:04.853117 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:33:04.864411 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 09:33:04.864892
362 09:33:04.865263
363 09:33:04.874342 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:33:04.877834 ARM64: Exception handlers installed.
365 09:33:04.881150 ARM64: Testing exception
366 09:33:04.881706 ARM64: Done test exception
367 09:33:04.887576 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:33:04.891079 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:33:04.905575 Probing TPM: . done!
370 09:33:04.905997 TPM ready after 0 ms
371 09:33:04.912047 Connected to device vid:did:rid of 1ae0:0028:00
372 09:33:04.921771 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 09:33:04.960486 Initialized TPM device CR50 revision 0
374 09:33:04.972439 tlcl_send_startup: Startup return code is 0
375 09:33:04.972879 TPM: setup succeeded
376 09:33:04.983649 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:33:04.992253 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:33:04.999385 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:33:05.011660 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:33:05.014820 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:33:05.018117 in-header: 03 07 00 00 08 00 00 00
382 09:33:05.021404 in-data: aa e4 47 04 13 02 00 00
383 09:33:05.025203 Chrome EC: UHEPI supported
384 09:33:05.031219 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:33:05.034923 in-header: 03 ad 00 00 08 00 00 00
386 09:33:05.038146 in-data: 00 20 20 08 00 00 00 00
387 09:33:05.038706 Phase 1
388 09:33:05.041370 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:33:05.048088 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:33:05.054708 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:33:05.057884 Recovery requested (1009000e)
392 09:33:05.062017 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:33:05.071191 tlcl_extend: response is 0
394 09:33:05.079028 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:33:05.084020 tlcl_extend: response is 0
396 09:33:05.090790 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:33:05.110930 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 09:33:05.117899 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 09:33:05.118369
400 09:33:05.118734
401 09:33:05.128630 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:33:05.131839 ARM64: Exception handlers installed.
403 09:33:05.132307 ARM64: Testing exception
404 09:33:05.135055 ARM64: Done test exception
405 09:33:05.157569 pmic_efuse_setting: Set efuses in 11 msecs
406 09:33:05.160956 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:33:05.164601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:33:05.171373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:33:05.174652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:33:05.181419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:33:05.184869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:33:05.191221 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:33:05.194893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:33:05.198050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:33:05.204704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:33:05.208044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:33:05.214544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:33:05.217967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:33:05.221007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:33:05.227899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:33:05.234643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:33:05.241069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:33:05.245124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:33:05.251676 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:33:05.257806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:33:05.264639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:33:05.267839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:33:05.275047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:33:05.278853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:33:05.285579 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:33:05.289095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:33:05.296289 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:33:05.299914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:33:05.306231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:33:05.309562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:33:05.316002 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:33:05.319241 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:33:05.326400 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:33:05.329442 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:33:05.336271 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:33:05.339141 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:33:05.346098 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:33:05.349123 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:33:05.355901 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:33:05.359480 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:33:05.363681 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:33:05.369730 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:33:05.373999 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:33:05.377084 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:33:05.383342 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:33:05.386816 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:33:05.390241 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:33:05.393437 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:33:05.400120 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:33:05.403502 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:33:05.407105 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:33:05.410163 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:33:05.420569 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:33:05.426854 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:33:05.433218 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:33:05.439934 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:33:05.450282 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:33:05.453595 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:33:05.459935 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:33:05.463419 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:33:05.469644 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x24
467 09:33:05.476088 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:33:05.479650 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 09:33:05.483205 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:33:05.493885 [RTC]rtc_get_frequency_meter,154: input=15, output=834
471 09:33:05.503352 [RTC]rtc_get_frequency_meter,154: input=7, output=708
472 09:33:05.513011 [RTC]rtc_get_frequency_meter,154: input=11, output=771
473 09:33:05.522295 [RTC]rtc_get_frequency_meter,154: input=13, output=802
474 09:33:05.532329 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 09:33:05.541293 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 09:33:05.550939 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 09:33:05.554363 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 09:33:05.561658 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 09:33:05.564709 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 09:33:05.568713 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 09:33:05.575425 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 09:33:05.578241 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 09:33:05.581320 ADC[4]: Raw value=903031 ID=7
484 09:33:05.581883 ADC[3]: Raw value=212912 ID=1
485 09:33:05.584620 RAM Code: 0x71
486 09:33:05.587931 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 09:33:05.594689 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 09:33:05.600895 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 09:33:05.608041 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 09:33:05.611127 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 09:33:05.614385 in-header: 03 07 00 00 08 00 00 00
492 09:33:05.617425 in-data: aa e4 47 04 13 02 00 00
493 09:33:05.621389 Chrome EC: UHEPI supported
494 09:33:05.627361 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 09:33:05.630999 in-header: 03 dd 00 00 08 00 00 00
496 09:33:05.634117 in-data: 90 20 60 08 00 00 00 00
497 09:33:05.638080 MRC: failed to locate region type 0.
498 09:33:05.644345 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 09:33:05.647606 DRAM-K: Running full calibration
500 09:33:05.654142 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 09:33:05.657351 header.status = 0x0
502 09:33:05.657818 header.version = 0x6 (expected: 0x6)
503 09:33:05.663842 header.size = 0xd00 (expected: 0xd00)
504 09:33:05.664283 header.flags = 0x0
505 09:33:05.670170 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 09:33:05.688093 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 09:33:05.694372 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 09:33:05.698076 dram_init: ddr_geometry: 2
509 09:33:05.701204 [EMI] MDL number = 2
510 09:33:05.701669 [EMI] Get MDL freq = 0
511 09:33:05.704239 dram_init: ddr_type: 0
512 09:33:05.704740 is_discrete_lpddr4: 1
513 09:33:05.707818 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 09:33:05.708238
515 09:33:05.711072
516 09:33:05.711489 [Bian_co] ETT version 0.0.0.1
517 09:33:05.717351 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 09:33:05.717772
519 09:33:05.721704 dramc_set_vcore_voltage set vcore to 650000
520 09:33:05.723945 Read voltage for 800, 4
521 09:33:05.724484 Vio18 = 0
522 09:33:05.724822 Vcore = 650000
523 09:33:05.727601 Vdram = 0
524 09:33:05.728074 Vddq = 0
525 09:33:05.728406 Vmddr = 0
526 09:33:05.730646 dram_init: config_dvfs: 1
527 09:33:05.734136 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 09:33:05.740997 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 09:33:05.744273 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 09:33:05.747744 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 09:33:05.751245 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 09:33:05.757471 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 09:33:05.758044 MEM_TYPE=3, freq_sel=18
534 09:33:05.760504 sv_algorithm_assistance_LP4_1600
535 09:33:05.763637 ============ PULL DRAM RESETB DOWN ============
536 09:33:05.770739 ========== PULL DRAM RESETB DOWN end =========
537 09:33:05.774387 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 09:33:05.777280 ===================================
539 09:33:05.780508 LPDDR4 DRAM CONFIGURATION
540 09:33:05.783643 ===================================
541 09:33:05.784147 EX_ROW_EN[0] = 0x0
542 09:33:05.786996 EX_ROW_EN[1] = 0x0
543 09:33:05.790001 LP4Y_EN = 0x0
544 09:33:05.790517 WORK_FSP = 0x0
545 09:33:05.793697 WL = 0x2
546 09:33:05.794166 RL = 0x2
547 09:33:05.797246 BL = 0x2
548 09:33:05.797713 RPST = 0x0
549 09:33:05.800250 RD_PRE = 0x0
550 09:33:05.800719 WR_PRE = 0x1
551 09:33:05.803229 WR_PST = 0x0
552 09:33:05.803696 DBI_WR = 0x0
553 09:33:05.806416 DBI_RD = 0x0
554 09:33:05.806894 OTF = 0x1
555 09:33:05.810381 ===================================
556 09:33:05.813536 ===================================
557 09:33:05.817097 ANA top config
558 09:33:05.820047 ===================================
559 09:33:05.820471 DLL_ASYNC_EN = 0
560 09:33:05.823436 ALL_SLAVE_EN = 1
561 09:33:05.826556 NEW_RANK_MODE = 1
562 09:33:05.830356 DLL_IDLE_MODE = 1
563 09:33:05.832932 LP45_APHY_COMB_EN = 1
564 09:33:05.833357 TX_ODT_DIS = 1
565 09:33:05.836419 NEW_8X_MODE = 1
566 09:33:05.840197 ===================================
567 09:33:05.843457 ===================================
568 09:33:05.846845 data_rate = 1600
569 09:33:05.850280 CKR = 1
570 09:33:05.853286 DQ_P2S_RATIO = 8
571 09:33:05.856151 ===================================
572 09:33:05.859966 CA_P2S_RATIO = 8
573 09:33:05.860497 DQ_CA_OPEN = 0
574 09:33:05.863263 DQ_SEMI_OPEN = 0
575 09:33:05.866711 CA_SEMI_OPEN = 0
576 09:33:05.870012 CA_FULL_RATE = 0
577 09:33:05.873064 DQ_CKDIV4_EN = 1
578 09:33:05.873587 CA_CKDIV4_EN = 1
579 09:33:05.876624 CA_PREDIV_EN = 0
580 09:33:05.879946 PH8_DLY = 0
581 09:33:05.883383 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 09:33:05.885922 DQ_AAMCK_DIV = 4
583 09:33:05.889422 CA_AAMCK_DIV = 4
584 09:33:05.892666 CA_ADMCK_DIV = 4
585 09:33:05.893138 DQ_TRACK_CA_EN = 0
586 09:33:05.896296 CA_PICK = 800
587 09:33:05.899509 CA_MCKIO = 800
588 09:33:05.902450 MCKIO_SEMI = 0
589 09:33:05.905819 PLL_FREQ = 3068
590 09:33:05.909757 DQ_UI_PI_RATIO = 32
591 09:33:05.912765 CA_UI_PI_RATIO = 0
592 09:33:05.915482 ===================================
593 09:33:05.919242 ===================================
594 09:33:05.919855 memory_type:LPDDR4
595 09:33:05.922740 GP_NUM : 10
596 09:33:05.925788 SRAM_EN : 1
597 09:33:05.926358 MD32_EN : 0
598 09:33:05.928935 ===================================
599 09:33:05.932234 [ANA_INIT] >>>>>>>>>>>>>>
600 09:33:05.935319 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 09:33:05.939083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 09:33:05.942234 ===================================
603 09:33:05.945997 data_rate = 1600,PCW = 0X7600
604 09:33:05.948550 ===================================
605 09:33:05.952180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 09:33:05.955673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:33:05.962550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 09:33:05.965381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 09:33:05.969331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:33:05.971846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 09:33:05.975613 [ANA_INIT] flow start
612 09:33:05.978546 [ANA_INIT] PLL >>>>>>>>
613 09:33:05.979012 [ANA_INIT] PLL <<<<<<<<
614 09:33:05.982769 [ANA_INIT] MIDPI >>>>>>>>
615 09:33:05.985229 [ANA_INIT] MIDPI <<<<<<<<
616 09:33:05.988449 [ANA_INIT] DLL >>>>>>>>
617 09:33:05.988914 [ANA_INIT] flow end
618 09:33:05.992104 ============ LP4 DIFF to SE enter ============
619 09:33:05.998731 ============ LP4 DIFF to SE exit ============
620 09:33:05.999303 [ANA_INIT] <<<<<<<<<<<<<
621 09:33:06.001675 [Flow] Enable top DCM control >>>>>
622 09:33:06.004969 [Flow] Enable top DCM control <<<<<
623 09:33:06.008124 Enable DLL master slave shuffle
624 09:33:06.014790 ==============================================================
625 09:33:06.015359 Gating Mode config
626 09:33:06.021482 ==============================================================
627 09:33:06.024341 Config description:
628 09:33:06.034787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 09:33:06.041176 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 09:33:06.044453 SELPH_MODE 0: By rank 1: By Phase
631 09:33:06.051485 ==============================================================
632 09:33:06.054680 GAT_TRACK_EN = 1
633 09:33:06.058289 RX_GATING_MODE = 2
634 09:33:06.058858 RX_GATING_TRACK_MODE = 2
635 09:33:06.061236 SELPH_MODE = 1
636 09:33:06.064318 PICG_EARLY_EN = 1
637 09:33:06.067788 VALID_LAT_VALUE = 1
638 09:33:06.074703 ==============================================================
639 09:33:06.077522 Enter into Gating configuration >>>>
640 09:33:06.080999 Exit from Gating configuration <<<<
641 09:33:06.084112 Enter into DVFS_PRE_config >>>>>
642 09:33:06.094260 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 09:33:06.097940 Exit from DVFS_PRE_config <<<<<
644 09:33:06.100718 Enter into PICG configuration >>>>
645 09:33:06.104175 Exit from PICG configuration <<<<
646 09:33:06.107850 [RX_INPUT] configuration >>>>>
647 09:33:06.110968 [RX_INPUT] configuration <<<<<
648 09:33:06.114222 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 09:33:06.120982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 09:33:06.128517 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 09:33:06.132105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 09:33:06.139100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 09:33:06.146272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 09:33:06.149892 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 09:33:06.153970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 09:33:06.157196 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 09:33:06.161301 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 09:33:06.164413 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 09:33:06.171908 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 09:33:06.172459 ===================================
661 09:33:06.175650 LPDDR4 DRAM CONFIGURATION
662 09:33:06.178702 ===================================
663 09:33:06.182736 EX_ROW_EN[0] = 0x0
664 09:33:06.183358 EX_ROW_EN[1] = 0x0
665 09:33:06.186351 LP4Y_EN = 0x0
666 09:33:06.186896 WORK_FSP = 0x0
667 09:33:06.189885 WL = 0x2
668 09:33:06.190352 RL = 0x2
669 09:33:06.190719 BL = 0x2
670 09:33:06.194042 RPST = 0x0
671 09:33:06.194503 RD_PRE = 0x0
672 09:33:06.197545 WR_PRE = 0x1
673 09:33:06.198134 WR_PST = 0x0
674 09:33:06.201016 DBI_WR = 0x0
675 09:33:06.201505 DBI_RD = 0x0
676 09:33:06.204672 OTF = 0x1
677 09:33:06.208468 ===================================
678 09:33:06.212118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 09:33:06.216060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 09:33:06.219217 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 09:33:06.222778 ===================================
682 09:33:06.226195 LPDDR4 DRAM CONFIGURATION
683 09:33:06.229760 ===================================
684 09:33:06.230182 EX_ROW_EN[0] = 0x10
685 09:33:06.233431 EX_ROW_EN[1] = 0x0
686 09:33:06.233857 LP4Y_EN = 0x0
687 09:33:06.237592 WORK_FSP = 0x0
688 09:33:06.238013 WL = 0x2
689 09:33:06.241043 RL = 0x2
690 09:33:06.241463 BL = 0x2
691 09:33:06.241796 RPST = 0x0
692 09:33:06.244894 RD_PRE = 0x0
693 09:33:06.245458 WR_PRE = 0x1
694 09:33:06.248274 WR_PST = 0x0
695 09:33:06.248697 DBI_WR = 0x0
696 09:33:06.251508 DBI_RD = 0x0
697 09:33:06.251975 OTF = 0x1
698 09:33:06.255550 ===================================
699 09:33:06.262409 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 09:33:06.266452 nWR fixed to 40
701 09:33:06.269704 [ModeRegInit_LP4] CH0 RK0
702 09:33:06.270124 [ModeRegInit_LP4] CH0 RK1
703 09:33:06.273494 [ModeRegInit_LP4] CH1 RK0
704 09:33:06.276756 [ModeRegInit_LP4] CH1 RK1
705 09:33:06.277177 match AC timing 13
706 09:33:06.283363 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 09:33:06.286775 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 09:33:06.290222 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 09:33:06.297168 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 09:33:06.300573 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 09:33:06.301032 [EMI DOE] emi_dcm 0
712 09:33:06.306912 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 09:33:06.307335 ==
714 09:33:06.310597 Dram Type= 6, Freq= 0, CH_0, rank 0
715 09:33:06.313479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 09:33:06.314047 ==
717 09:33:06.316891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 09:33:06.323882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 09:33:06.334043 [CA 0] Center 37 (6~68) winsize 63
720 09:33:06.337186 [CA 1] Center 37 (6~68) winsize 63
721 09:33:06.340557 [CA 2] Center 34 (4~65) winsize 62
722 09:33:06.343818 [CA 3] Center 34 (4~65) winsize 62
723 09:33:06.347233 [CA 4] Center 33 (3~64) winsize 62
724 09:33:06.350926 [CA 5] Center 33 (3~64) winsize 62
725 09:33:06.351396
726 09:33:06.354694 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 09:33:06.355264
728 09:33:06.357761 [CATrainingPosCal] consider 1 rank data
729 09:33:06.361363 u2DelayCellTimex100 = 270/100 ps
730 09:33:06.364718 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 09:33:06.368102 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 09:33:06.371123 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 09:33:06.374580 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 09:33:06.381110 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:33:06.384783 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 09:33:06.385354
737 09:33:06.387410 CA PerBit enable=1, Macro0, CA PI delay=33
738 09:33:06.387907
739 09:33:06.391249 [CBTSetCACLKResult] CA Dly = 33
740 09:33:06.391774 CS Dly: 7 (0~38)
741 09:33:06.392168 ==
742 09:33:06.394425 Dram Type= 6, Freq= 0, CH_0, rank 1
743 09:33:06.401311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 09:33:06.401884 ==
745 09:33:06.404042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 09:33:06.411440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 09:33:06.419914 [CA 0] Center 37 (6~68) winsize 63
748 09:33:06.423423 [CA 1] Center 37 (7~68) winsize 62
749 09:33:06.426679 [CA 2] Center 34 (4~65) winsize 62
750 09:33:06.430472 [CA 3] Center 34 (4~65) winsize 62
751 09:33:06.433484 [CA 4] Center 33 (3~64) winsize 62
752 09:33:06.436675 [CA 5] Center 33 (2~64) winsize 63
753 09:33:06.437142
754 09:33:06.440243 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 09:33:06.440708
756 09:33:06.443923 [CATrainingPosCal] consider 2 rank data
757 09:33:06.446835 u2DelayCellTimex100 = 270/100 ps
758 09:33:06.450358 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 09:33:06.453563 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 09:33:06.460261 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 09:33:06.463500 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 09:33:06.467483 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:33:06.470726 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 09:33:06.471216
765 09:33:06.474670 CA PerBit enable=1, Macro0, CA PI delay=33
766 09:33:06.475277
767 09:33:06.475813 [CBTSetCACLKResult] CA Dly = 33
768 09:33:06.478551 CS Dly: 7 (0~38)
769 09:33:06.479033
770 09:33:06.482005 ----->DramcWriteLeveling(PI) begin...
771 09:33:06.482706 ==
772 09:33:06.485453 Dram Type= 6, Freq= 0, CH_0, rank 0
773 09:33:06.489068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 09:33:06.489564 ==
775 09:33:06.492656 Write leveling (Byte 0): 31 => 31
776 09:33:06.496299 Write leveling (Byte 1): 30 => 30
777 09:33:06.499502 DramcWriteLeveling(PI) end<-----
778 09:33:06.500047
779 09:33:06.500537 ==
780 09:33:06.502835 Dram Type= 6, Freq= 0, CH_0, rank 0
781 09:33:06.506502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 09:33:06.507090 ==
783 09:33:06.509956 [Gating] SW mode calibration
784 09:33:06.516369 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 09:33:06.522978 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 09:33:06.526192 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 09:33:06.529472 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 09:33:06.536319 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 09:33:06.539823 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:33:06.542901 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:33:06.546294 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:33:06.552998 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:33:06.556171 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:33:06.559546 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:33:06.566261 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:33:06.569757 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:33:06.572690 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:33:06.579599 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:33:06.582831 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:33:06.585728 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:33:06.592565 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:33:06.595876 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:33:06.599094 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:33:06.605792 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 09:33:06.609573 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:33:06.612550 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:33:06.619332 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:33:06.622979 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:33:06.625563 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:33:06.632401 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:33:06.636157 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:33:06.639191 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
813 09:33:06.645950 0 9 12 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
814 09:33:06.649455 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:33:06.652553 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:33:06.658848 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:33:06.662335 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:33:06.665590 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 09:33:06.672645 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 09:33:06.675757 0 10 8 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 0)
821 09:33:06.678911 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
822 09:33:06.685566 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:33:06.688580 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:33:06.692063 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:33:06.699277 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:33:06.701648 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:33:06.705088 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 09:33:06.708804 0 11 8 | B1->B0 | 2525 3d3d | 0 1 | (0 0) (1 1)
829 09:33:06.715283 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
830 09:33:06.719437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:33:06.722552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:33:06.726163 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:33:06.733669 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:33:06.737228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:33:06.740679 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 09:33:06.745139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 09:33:06.751632 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:33:06.755705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:33:06.758473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:33:06.762113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:33:06.766075 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:33:06.772737 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:33:06.775897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:33:06.779367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:33:06.786074 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:33:06.789077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:33:06.792679 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:33:06.799121 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:33:06.802640 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:33:06.805882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:33:06.812025 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 09:33:06.815579 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 09:33:06.819040 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 09:33:06.822068 Total UI for P1: 0, mck2ui 16
855 09:33:06.825718 best dqsien dly found for B0: ( 0, 14, 8)
856 09:33:06.829160 Total UI for P1: 0, mck2ui 16
857 09:33:06.832817 best dqsien dly found for B1: ( 0, 14, 8)
858 09:33:06.836961 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 09:33:06.840494 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 09:33:06.840929
861 09:33:06.844032 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 09:33:06.847927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 09:33:06.851563 [Gating] SW calibration Done
864 09:33:06.852145 ==
865 09:33:06.855573 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:33:06.858676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:33:06.859106 ==
868 09:33:06.859464 RX Vref Scan: 0
869 09:33:06.859880
870 09:33:06.862214 RX Vref 0 -> 0, step: 1
871 09:33:06.862639
872 09:33:06.866074 RX Delay -130 -> 252, step: 16
873 09:33:06.869061 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 09:33:06.872138 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 09:33:06.876109 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 09:33:06.882700 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 09:33:06.885447 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 09:33:06.889165 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 09:33:06.892094 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 09:33:06.895987 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 09:33:06.902443 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 09:33:06.905844 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 09:33:06.908920 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 09:33:06.912319 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 09:33:06.915408 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 09:33:06.922110 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 09:33:06.925466 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 09:33:06.928531 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 09:33:06.928959 ==
890 09:33:06.931929 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:33:06.935006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:33:06.938639 ==
893 09:33:06.939189 DQS Delay:
894 09:33:06.939528 DQS0 = 0, DQS1 = 0
895 09:33:06.941871 DQM Delay:
896 09:33:06.942394 DQM0 = 87, DQM1 = 76
897 09:33:06.945555 DQ Delay:
898 09:33:06.946129 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 09:33:06.948583 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 09:33:06.952118 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 09:33:06.955501 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 09:33:06.958653
903 09:33:06.959260
904 09:33:06.959630 ==
905 09:33:06.962229 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:33:06.965092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:33:06.965558 ==
908 09:33:06.965925
909 09:33:06.966267
910 09:33:06.968900 TX Vref Scan disable
911 09:33:06.969422 == TX Byte 0 ==
912 09:33:06.975266 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 09:33:06.978771 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 09:33:06.979353 == TX Byte 1 ==
915 09:33:06.984969 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 09:33:06.988259 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 09:33:06.988727 ==
918 09:33:06.991762 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:33:06.994988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:33:06.995466 ==
921 09:33:07.008787 TX Vref=22, minBit 4, minWin=27, winSum=440
922 09:33:07.012134 TX Vref=24, minBit 5, minWin=27, winSum=443
923 09:33:07.015313 TX Vref=26, minBit 8, minWin=27, winSum=444
924 09:33:07.018469 TX Vref=28, minBit 8, minWin=27, winSum=447
925 09:33:07.022142 TX Vref=30, minBit 4, minWin=27, winSum=444
926 09:33:07.028282 TX Vref=32, minBit 11, minWin=26, winSum=443
927 09:33:07.031629 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
928 09:33:07.032248
929 09:33:07.035035 Final TX Range 1 Vref 28
930 09:33:07.035505
931 09:33:07.035937 ==
932 09:33:07.038636 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:33:07.042546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:33:07.043022 ==
935 09:33:07.045187
936 09:33:07.045847
937 09:33:07.046369 TX Vref Scan disable
938 09:33:07.048543 == TX Byte 0 ==
939 09:33:07.052106 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 09:33:07.058893 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 09:33:07.059475 == TX Byte 1 ==
942 09:33:07.061769 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 09:33:07.068405 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 09:33:07.069041
945 09:33:07.069466 [DATLAT]
946 09:33:07.070037 Freq=800, CH0 RK0
947 09:33:07.070431
948 09:33:07.071456 DATLAT Default: 0xa
949 09:33:07.071980 0, 0xFFFF, sum = 0
950 09:33:07.074714 1, 0xFFFF, sum = 0
951 09:33:07.078805 2, 0xFFFF, sum = 0
952 09:33:07.079385 3, 0xFFFF, sum = 0
953 09:33:07.082042 4, 0xFFFF, sum = 0
954 09:33:07.082609 5, 0xFFFF, sum = 0
955 09:33:07.085407 6, 0xFFFF, sum = 0
956 09:33:07.085985 7, 0xFFFF, sum = 0
957 09:33:07.087836 8, 0xFFFF, sum = 0
958 09:33:07.088362 9, 0x0, sum = 1
959 09:33:07.091439 10, 0x0, sum = 2
960 09:33:07.092090 11, 0x0, sum = 3
961 09:33:07.094572 12, 0x0, sum = 4
962 09:33:07.095045 best_step = 10
963 09:33:07.095413
964 09:33:07.095808 ==
965 09:33:07.097867 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:33:07.101337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:33:07.101808 ==
968 09:33:07.104456 RX Vref Scan: 1
969 09:33:07.104960
970 09:33:07.107534 Set Vref Range= 32 -> 127
971 09:33:07.108174
972 09:33:07.108781 RX Vref 32 -> 127, step: 1
973 09:33:07.109241
974 09:33:07.111235 RX Delay -95 -> 252, step: 8
975 09:33:07.111700
976 09:33:07.114356 Set Vref, RX VrefLevel [Byte0]: 32
977 09:33:07.117515 [Byte1]: 32
978 09:33:07.121360
979 09:33:07.121883 Set Vref, RX VrefLevel [Byte0]: 33
980 09:33:07.124507 [Byte1]: 33
981 09:33:07.129397
982 09:33:07.129916 Set Vref, RX VrefLevel [Byte0]: 34
983 09:33:07.132673 [Byte1]: 34
984 09:33:07.136359
985 09:33:07.136934 Set Vref, RX VrefLevel [Byte0]: 35
986 09:33:07.139545 [Byte1]: 35
987 09:33:07.143871
988 09:33:07.144338 Set Vref, RX VrefLevel [Byte0]: 36
989 09:33:07.151158 [Byte1]: 36
990 09:33:07.151677
991 09:33:07.154354 Set Vref, RX VrefLevel [Byte0]: 37
992 09:33:07.157644 [Byte1]: 37
993 09:33:07.158078
994 09:33:07.160985 Set Vref, RX VrefLevel [Byte0]: 38
995 09:33:07.164435 [Byte1]: 38
996 09:33:07.164864
997 09:33:07.167548 Set Vref, RX VrefLevel [Byte0]: 39
998 09:33:07.170875 [Byte1]: 39
999 09:33:07.174631
1000 09:33:07.175153 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:33:07.177438 [Byte1]: 40
1002 09:33:07.182354
1003 09:33:07.183055 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:33:07.185286 [Byte1]: 41
1005 09:33:07.189478
1006 09:33:07.189904 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:33:07.193112 [Byte1]: 42
1008 09:33:07.196902
1009 09:33:07.197348 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:33:07.200663 [Byte1]: 43
1011 09:33:07.205037
1012 09:33:07.205459 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:33:07.208350 [Byte1]: 44
1014 09:33:07.212323
1015 09:33:07.212893 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:33:07.215601 [Byte1]: 45
1017 09:33:07.220210
1018 09:33:07.220789 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:33:07.223453 [Byte1]: 46
1020 09:33:07.227801
1021 09:33:07.228328 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:33:07.231146 [Byte1]: 47
1023 09:33:07.235268
1024 09:33:07.235697 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:33:07.238466 [Byte1]: 48
1026 09:33:07.243286
1027 09:33:07.243841 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:33:07.245990 [Byte1]: 49
1029 09:33:07.250481
1030 09:33:07.251036 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:33:07.253459 [Byte1]: 50
1032 09:33:07.258031
1033 09:33:07.258492 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:33:07.261636 [Byte1]: 51
1035 09:33:07.265672
1036 09:33:07.266241 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:33:07.269035 [Byte1]: 52
1038 09:33:07.273477
1039 09:33:07.274034 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:33:07.276715 [Byte1]: 53
1041 09:33:07.280743
1042 09:33:07.281297 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:33:07.284583 [Byte1]: 54
1044 09:33:07.289669
1045 09:33:07.290222 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:33:07.292125 [Byte1]: 55
1047 09:33:07.296018
1048 09:33:07.298928 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:33:07.299395 [Byte1]: 56
1050 09:33:07.304313
1051 09:33:07.304910 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:33:07.307042 [Byte1]: 57
1053 09:33:07.311226
1054 09:33:07.311681 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:33:07.314536 [Byte1]: 58
1056 09:33:07.318807
1057 09:33:07.319268 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:33:07.322581 [Byte1]: 59
1059 09:33:07.326908
1060 09:33:07.327455 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:33:07.329807 [Byte1]: 60
1062 09:33:07.334143
1063 09:33:07.334656 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:33:07.337323 [Byte1]: 61
1065 09:33:07.341590
1066 09:33:07.342135 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:33:07.344805 [Byte1]: 62
1068 09:33:07.349644
1069 09:33:07.350189 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:33:07.352811 [Byte1]: 63
1071 09:33:07.357526
1072 09:33:07.358078 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:33:07.360616 [Byte1]: 64
1074 09:33:07.364208
1075 09:33:07.368128 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:33:07.368735 [Byte1]: 65
1077 09:33:07.372292
1078 09:33:07.372766 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:33:07.375458 [Byte1]: 66
1080 09:33:07.379342
1081 09:33:07.382824 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:33:07.383285 [Byte1]: 67
1083 09:33:07.387639
1084 09:33:07.388302 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:33:07.391167 [Byte1]: 68
1086 09:33:07.395231
1087 09:33:07.395967 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:33:07.398284 [Byte1]: 69
1089 09:33:07.402123
1090 09:33:07.402823 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:33:07.405646 [Byte1]: 70
1092 09:33:07.409635
1093 09:33:07.410137 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:33:07.413029 [Byte1]: 71
1095 09:33:07.417917
1096 09:33:07.418404 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:33:07.421241 [Byte1]: 72
1098 09:33:07.425602
1099 09:33:07.426010 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:33:07.428908 [Byte1]: 73
1101 09:33:07.433042
1102 09:33:07.433548 Set Vref, RX VrefLevel [Byte0]: 74
1103 09:33:07.435836 [Byte1]: 74
1104 09:33:07.440418
1105 09:33:07.440928 Set Vref, RX VrefLevel [Byte0]: 75
1106 09:33:07.443520 [Byte1]: 75
1107 09:33:07.447881
1108 09:33:07.448392 Set Vref, RX VrefLevel [Byte0]: 76
1109 09:33:07.451164 [Byte1]: 76
1110 09:33:07.455834
1111 09:33:07.456396 Set Vref, RX VrefLevel [Byte0]: 77
1112 09:33:07.458753 [Byte1]: 77
1113 09:33:07.463004
1114 09:33:07.463456 Set Vref, RX VrefLevel [Byte0]: 78
1115 09:33:07.466450 [Byte1]: 78
1116 09:33:07.470906
1117 09:33:07.471462 Set Vref, RX VrefLevel [Byte0]: 79
1118 09:33:07.474091 [Byte1]: 79
1119 09:33:07.478431
1120 09:33:07.478980 Set Vref, RX VrefLevel [Byte0]: 80
1121 09:33:07.481795 [Byte1]: 80
1122 09:33:07.485946
1123 09:33:07.486518 Set Vref, RX VrefLevel [Byte0]: 81
1124 09:33:07.489187 [Byte1]: 81
1125 09:33:07.492979
1126 09:33:07.493463 Set Vref, RX VrefLevel [Byte0]: 82
1127 09:33:07.496745 [Byte1]: 82
1128 09:33:07.501363
1129 09:33:07.501934 Final RX Vref Byte 0 = 61 to rank0
1130 09:33:07.504108 Final RX Vref Byte 1 = 49 to rank0
1131 09:33:07.508427 Final RX Vref Byte 0 = 61 to rank1
1132 09:33:07.510973 Final RX Vref Byte 1 = 49 to rank1==
1133 09:33:07.514372 Dram Type= 6, Freq= 0, CH_0, rank 0
1134 09:33:07.520776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 09:33:07.521267 ==
1136 09:33:07.521635 DQS Delay:
1137 09:33:07.521977 DQS0 = 0, DQS1 = 0
1138 09:33:07.524270 DQM Delay:
1139 09:33:07.524724 DQM0 = 87, DQM1 = 76
1140 09:33:07.527612 DQ Delay:
1141 09:33:07.531142 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1142 09:33:07.531701 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1143 09:33:07.534909 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1144 09:33:07.537713 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1145 09:33:07.540820
1146 09:33:07.541274
1147 09:33:07.547665 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1148 09:33:07.551268 CH0 RK0: MR19=606, MR18=4829
1149 09:33:07.557813 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1150 09:33:07.558375
1151 09:33:07.560778 ----->DramcWriteLeveling(PI) begin...
1152 09:33:07.561302 ==
1153 09:33:07.563938 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 09:33:07.567422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 09:33:07.568049 ==
1156 09:33:07.570850 Write leveling (Byte 0): 33 => 33
1157 09:33:07.574266 Write leveling (Byte 1): 28 => 28
1158 09:33:07.577403 DramcWriteLeveling(PI) end<-----
1159 09:33:07.577959
1160 09:33:07.578323 ==
1161 09:33:07.580492 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 09:33:07.624711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 09:33:07.625293 ==
1164 09:33:07.625663 [Gating] SW mode calibration
1165 09:33:07.626351 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1166 09:33:07.626721 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1167 09:33:07.627058 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1168 09:33:07.627456 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 09:33:07.627868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1170 09:33:07.628287 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1171 09:33:07.628614 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:33:07.628924 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:33:07.652545 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:33:07.653200 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:33:07.653964 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:33:07.654344 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:33:07.654686 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:33:07.655048 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:33:07.656354 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:33:07.663417 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:33:07.666792 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:33:07.669945 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:33:07.673543 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:33:07.680055 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1185 09:33:07.683522 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1186 09:33:07.686569 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:33:07.693197 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:33:07.696233 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:33:07.699559 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:33:07.706297 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:33:07.709776 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:33:07.713023 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:33:07.719629 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
1194 09:33:07.722428 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1195 09:33:07.725903 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 09:33:07.733025 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 09:33:07.735897 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 09:33:07.739167 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 09:33:07.746014 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 09:33:07.750195 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1201 09:33:07.752705 0 10 8 | B1->B0 | 2f2f 2828 | 0 0 | (1 1) (1 1)
1202 09:33:07.758974 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 09:33:07.762479 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 09:33:07.765777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 09:33:07.772243 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 09:33:07.775832 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 09:33:07.779134 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 09:33:07.785893 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 09:33:07.788649 0 11 8 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
1210 09:33:07.792450 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1211 09:33:07.798726 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 09:33:07.802244 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 09:33:07.805475 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 09:33:07.812649 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 09:33:07.815606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 09:33:07.818638 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 09:33:07.825683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1218 09:33:07.828759 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1219 09:33:07.831609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:33:07.835193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 09:33:07.842078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 09:33:07.845240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 09:33:07.849277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 09:33:07.856020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 09:33:07.859151 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 09:33:07.862816 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 09:33:07.866471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 09:33:07.873707 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 09:33:07.876891 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 09:33:07.880496 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 09:33:07.884037 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 09:33:07.891360 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 09:33:07.894718 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 09:33:07.898456 Total UI for P1: 0, mck2ui 16
1235 09:33:07.902272 best dqsien dly found for B0: ( 0, 14, 6)
1236 09:33:07.902444 Total UI for P1: 0, mck2ui 16
1237 09:33:07.906120 best dqsien dly found for B1: ( 0, 14, 6)
1238 09:33:07.909500 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1239 09:33:07.912680 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1240 09:33:07.912825
1241 09:33:07.916684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1242 09:33:07.920102 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1243 09:33:07.923604 [Gating] SW calibration Done
1244 09:33:07.923813 ==
1245 09:33:07.927632 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 09:33:07.931351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1247 09:33:07.931684 ==
1248 09:33:07.934995 RX Vref Scan: 0
1249 09:33:07.935276
1250 09:33:07.935493 RX Vref 0 -> 0, step: 1
1251 09:33:07.935700
1252 09:33:07.938956 RX Delay -130 -> 252, step: 16
1253 09:33:07.942788 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1254 09:33:07.946902 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1255 09:33:07.950527 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1256 09:33:07.956914 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1257 09:33:07.960614 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1258 09:33:07.964404 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1259 09:33:07.968336 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1260 09:33:07.971882 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1261 09:33:07.975350 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1262 09:33:07.978848 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1263 09:33:07.982496 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1264 09:33:07.986590 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1265 09:33:07.990204 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1266 09:33:07.993672 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1267 09:33:08.000426 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1268 09:33:08.004500 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1269 09:33:08.005020 ==
1270 09:33:08.008042 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 09:33:08.011920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 09:33:08.012486 ==
1273 09:33:08.012928 DQS Delay:
1274 09:33:08.015763 DQS0 = 0, DQS1 = 0
1275 09:33:08.016223 DQM Delay:
1276 09:33:08.016645 DQM0 = 83, DQM1 = 75
1277 09:33:08.019255 DQ Delay:
1278 09:33:08.022725 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1279 09:33:08.023205 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1280 09:33:08.026249 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1281 09:33:08.029859 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1282 09:33:08.030324
1283 09:33:08.030689
1284 09:33:08.033434 ==
1285 09:33:08.033969 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 09:33:08.040309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 09:33:08.040758 ==
1288 09:33:08.041093
1289 09:33:08.041399
1290 09:33:08.041696 TX Vref Scan disable
1291 09:33:08.044091 == TX Byte 0 ==
1292 09:33:08.048364 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1293 09:33:08.051540 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1294 09:33:08.055577 == TX Byte 1 ==
1295 09:33:08.059035 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1296 09:33:08.062834 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1297 09:33:08.063251 ==
1298 09:33:08.066133 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 09:33:08.069621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 09:33:08.069918 ==
1301 09:33:08.083684 TX Vref=22, minBit 8, minWin=26, winSum=440
1302 09:33:08.087434 TX Vref=24, minBit 8, minWin=27, winSum=446
1303 09:33:08.091027 TX Vref=26, minBit 9, minWin=27, winSum=446
1304 09:33:08.094339 TX Vref=28, minBit 9, minWin=27, winSum=448
1305 09:33:08.098307 TX Vref=30, minBit 9, minWin=27, winSum=448
1306 09:33:08.101975 TX Vref=32, minBit 9, minWin=27, winSum=447
1307 09:33:08.109187 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 28
1308 09:33:08.109618
1309 09:33:08.109950 Final TX Range 1 Vref 28
1310 09:33:08.110266
1311 09:33:08.110565 ==
1312 09:33:08.113029 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 09:33:08.116460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 09:33:08.119427 ==
1315 09:33:08.119882
1316 09:33:08.120218
1317 09:33:08.120529 TX Vref Scan disable
1318 09:33:08.123506 == TX Byte 0 ==
1319 09:33:08.127585 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1320 09:33:08.130992 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1321 09:33:08.135164 == TX Byte 1 ==
1322 09:33:08.138499 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1323 09:33:08.142611 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1324 09:33:08.143030
1325 09:33:08.143420 [DATLAT]
1326 09:33:08.145936 Freq=800, CH0 RK1
1327 09:33:08.146414
1328 09:33:08.146874 DATLAT Default: 0xa
1329 09:33:08.149577 0, 0xFFFF, sum = 0
1330 09:33:08.150092 1, 0xFFFF, sum = 0
1331 09:33:08.152445 2, 0xFFFF, sum = 0
1332 09:33:08.152884 3, 0xFFFF, sum = 0
1333 09:33:08.156412 4, 0xFFFF, sum = 0
1334 09:33:08.156999 5, 0xFFFF, sum = 0
1335 09:33:08.159663 6, 0xFFFF, sum = 0
1336 09:33:08.160297 7, 0xFFFF, sum = 0
1337 09:33:08.163317 8, 0xFFFF, sum = 0
1338 09:33:08.163925 9, 0x0, sum = 1
1339 09:33:08.164288 10, 0x0, sum = 2
1340 09:33:08.167240 11, 0x0, sum = 3
1341 09:33:08.167696 12, 0x0, sum = 4
1342 09:33:08.170811 best_step = 10
1343 09:33:08.171338
1344 09:33:08.171672 ==
1345 09:33:08.174612 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 09:33:08.178101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 09:33:08.178650 ==
1348 09:33:08.179005 RX Vref Scan: 0
1349 09:33:08.179353
1350 09:33:08.181235 RX Vref 0 -> 0, step: 1
1351 09:33:08.181649
1352 09:33:08.184962 RX Delay -95 -> 252, step: 8
1353 09:33:08.188006 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1354 09:33:08.191454 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1355 09:33:08.197941 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1356 09:33:08.201489 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1357 09:33:08.204745 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1358 09:33:08.207792 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1359 09:33:08.211121 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1360 09:33:08.218083 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1361 09:33:08.221514 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1362 09:33:08.224927 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1363 09:33:08.228351 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1364 09:33:08.231526 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1365 09:33:08.237727 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1366 09:33:08.241518 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1367 09:33:08.244201 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1368 09:33:08.248058 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1369 09:33:08.248521 ==
1370 09:33:08.250952 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 09:33:08.257677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 09:33:08.258242 ==
1373 09:33:08.258610 DQS Delay:
1374 09:33:08.260924 DQS0 = 0, DQS1 = 0
1375 09:33:08.261390 DQM Delay:
1376 09:33:08.261758 DQM0 = 85, DQM1 = 76
1377 09:33:08.264277 DQ Delay:
1378 09:33:08.267375 DQ0 =80, DQ1 =88, DQ2 =76, DQ3 =84
1379 09:33:08.271490 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1380 09:33:08.274262 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1381 09:33:08.278044 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1382 09:33:08.278643
1383 09:33:08.279028
1384 09:33:08.284079 [DQSOSCAuto] RK1, (LSB)MR18= 0x4106, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1385 09:33:08.287272 CH0 RK1: MR19=606, MR18=4106
1386 09:33:08.294309 CH0_RK1: MR19=0x606, MR18=0x4106, DQSOSC=393, MR23=63, INC=95, DEC=63
1387 09:33:08.297359 [RxdqsGatingPostProcess] freq 800
1388 09:33:08.300914 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1389 09:33:08.304254 Pre-setting of DQS Precalculation
1390 09:33:08.310571 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1391 09:33:08.310990 ==
1392 09:33:08.314442 Dram Type= 6, Freq= 0, CH_1, rank 0
1393 09:33:08.317564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 09:33:08.317998 ==
1395 09:33:08.324334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 09:33:08.330612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 09:33:08.338514 [CA 0] Center 36 (6~67) winsize 62
1398 09:33:08.342077 [CA 1] Center 37 (6~68) winsize 63
1399 09:33:08.345018 [CA 2] Center 34 (4~65) winsize 62
1400 09:33:08.348738 [CA 3] Center 34 (3~65) winsize 63
1401 09:33:08.351573 [CA 4] Center 34 (4~65) winsize 62
1402 09:33:08.355254 [CA 5] Center 34 (3~65) winsize 63
1403 09:33:08.355830
1404 09:33:08.358253 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 09:33:08.358773
1406 09:33:08.361715 [CATrainingPosCal] consider 1 rank data
1407 09:33:08.364918 u2DelayCellTimex100 = 270/100 ps
1408 09:33:08.368191 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 09:33:08.374684 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1410 09:33:08.377705 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 09:33:08.381024 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1412 09:33:08.384292 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 09:33:08.387969 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1414 09:33:08.388504
1415 09:33:08.391198 CA PerBit enable=1, Macro0, CA PI delay=34
1416 09:33:08.391621
1417 09:33:08.394478 [CBTSetCACLKResult] CA Dly = 34
1418 09:33:08.397681 CS Dly: 5 (0~36)
1419 09:33:08.398104 ==
1420 09:33:08.400870 Dram Type= 6, Freq= 0, CH_1, rank 1
1421 09:33:08.404180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 09:33:08.404602 ==
1423 09:33:08.411355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1424 09:33:08.414081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1425 09:33:08.424886 [CA 0] Center 36 (6~67) winsize 62
1426 09:33:08.428228 [CA 1] Center 37 (6~68) winsize 63
1427 09:33:08.431135 [CA 2] Center 34 (4~65) winsize 62
1428 09:33:08.434804 [CA 3] Center 34 (3~65) winsize 63
1429 09:33:08.437760 [CA 4] Center 34 (4~65) winsize 62
1430 09:33:08.441512 [CA 5] Center 33 (3~64) winsize 62
1431 09:33:08.442083
1432 09:33:08.444274 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1433 09:33:08.444743
1434 09:33:08.447815 [CATrainingPosCal] consider 2 rank data
1435 09:33:08.451052 u2DelayCellTimex100 = 270/100 ps
1436 09:33:08.454130 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1437 09:33:08.460572 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1438 09:33:08.464126 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1439 09:33:08.467578 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1440 09:33:08.471087 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1441 09:33:08.474299 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1442 09:33:08.474823
1443 09:33:08.477613 CA PerBit enable=1, Macro0, CA PI delay=33
1444 09:33:08.478145
1445 09:33:08.481286 [CBTSetCACLKResult] CA Dly = 33
1446 09:33:08.481817 CS Dly: 6 (0~38)
1447 09:33:08.484181
1448 09:33:08.487282 ----->DramcWriteLeveling(PI) begin...
1449 09:33:08.487853 ==
1450 09:33:08.490703 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 09:33:08.495198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 09:33:08.495803 ==
1453 09:33:08.497136 Write leveling (Byte 0): 26 => 26
1454 09:33:08.500461 Write leveling (Byte 1): 30 => 30
1455 09:33:08.503576 DramcWriteLeveling(PI) end<-----
1456 09:33:08.504041
1457 09:33:08.504382 ==
1458 09:33:08.507502 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 09:33:08.510520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1460 09:33:08.510942 ==
1461 09:33:08.513980 [Gating] SW mode calibration
1462 09:33:08.520766 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1463 09:33:08.527356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1464 09:33:08.530865 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1465 09:33:08.533954 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1466 09:33:08.540360 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1467 09:33:08.543849 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:33:08.547186 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:33:08.553544 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:33:08.556936 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:33:08.560485 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:33:08.567063 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:33:08.570197 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:33:08.573576 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:33:08.576706 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:33:08.584101 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:33:08.587429 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:33:08.590931 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:33:08.596906 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:33:08.600297 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1481 09:33:08.603800 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1482 09:33:08.610533 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:33:08.613588 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:33:08.617069 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:33:08.623669 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:33:08.626762 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:33:08.630190 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:33:08.637402 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:33:08.640310 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:33:08.643647 0 9 8 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
1491 09:33:08.650174 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 09:33:08.653602 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 09:33:08.656789 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 09:33:08.663090 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 09:33:08.667054 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 09:33:08.670513 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 09:33:08.676662 0 10 4 | B1->B0 | 3232 3333 | 0 0 | (0 1) (0 1)
1498 09:33:08.680278 0 10 8 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (0 0)
1499 09:33:08.683195 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:33:08.690030 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 09:33:08.692888 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 09:33:08.696397 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 09:33:08.703061 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 09:33:08.706626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 09:33:08.709444 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1506 09:33:08.716371 0 11 8 | B1->B0 | 3a3a 3d3d | 1 1 | (0 0) (0 0)
1507 09:33:08.719642 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 09:33:08.722998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 09:33:08.729941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 09:33:08.732920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 09:33:08.736220 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 09:33:08.742703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 09:33:08.746399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1514 09:33:08.749462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1515 09:33:08.755996 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:33:08.759959 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:33:08.762935 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:33:08.766271 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 09:33:08.773099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 09:33:08.776466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 09:33:08.779231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 09:33:08.786370 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 09:33:08.789162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 09:33:08.792321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 09:33:08.799330 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 09:33:08.802539 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 09:33:08.805984 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 09:33:08.812257 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 09:33:08.815349 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1530 09:33:08.819036 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1531 09:33:08.822381 Total UI for P1: 0, mck2ui 16
1532 09:33:08.825698 best dqsien dly found for B0: ( 0, 14, 4)
1533 09:33:08.832340 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 09:33:08.832881 Total UI for P1: 0, mck2ui 16
1535 09:33:08.839062 best dqsien dly found for B1: ( 0, 14, 8)
1536 09:33:08.842212 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1537 09:33:08.845621 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1538 09:33:08.846174
1539 09:33:08.848739 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1540 09:33:08.852594 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1541 09:33:08.855206 [Gating] SW calibration Done
1542 09:33:08.855661 ==
1543 09:33:08.858811 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 09:33:08.862667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 09:33:08.863224 ==
1546 09:33:08.865468 RX Vref Scan: 0
1547 09:33:08.865978
1548 09:33:08.866361 RX Vref 0 -> 0, step: 1
1549 09:33:08.866703
1550 09:33:08.869122 RX Delay -130 -> 252, step: 16
1551 09:33:08.872277 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1552 09:33:08.878839 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1553 09:33:08.882289 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1554 09:33:08.885273 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1555 09:33:08.888467 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1556 09:33:08.891642 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1557 09:33:08.898429 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1558 09:33:08.902134 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1559 09:33:08.905300 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1560 09:33:08.908364 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1561 09:33:08.912020 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1562 09:33:08.918649 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1563 09:33:08.921814 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1564 09:33:08.924996 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1565 09:33:08.928384 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1566 09:33:08.934793 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1567 09:33:08.935284 ==
1568 09:33:08.938465 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 09:33:08.941582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 09:33:08.941998 ==
1571 09:33:08.942326 DQS Delay:
1572 09:33:08.944957 DQS0 = 0, DQS1 = 0
1573 09:33:08.945370 DQM Delay:
1574 09:33:08.948445 DQM0 = 89, DQM1 = 77
1575 09:33:08.948856 DQ Delay:
1576 09:33:08.951544 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1577 09:33:08.955331 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1578 09:33:08.958343 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1579 09:33:08.961736 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1580 09:33:08.962149
1581 09:33:08.962479
1582 09:33:08.962874 ==
1583 09:33:08.964960 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 09:33:08.968338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 09:33:08.968758 ==
1586 09:33:08.969102
1587 09:33:08.971858
1588 09:33:08.972277 TX Vref Scan disable
1589 09:33:08.975566 == TX Byte 0 ==
1590 09:33:08.978371 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1591 09:33:08.981641 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1592 09:33:08.985178 == TX Byte 1 ==
1593 09:33:08.988365 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1594 09:33:08.992113 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1595 09:33:08.992650 ==
1596 09:33:08.995463 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 09:33:09.001464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 09:33:09.001882 ==
1599 09:33:09.013487 TX Vref=22, minBit 10, minWin=26, winSum=439
1600 09:33:09.016772 TX Vref=24, minBit 8, minWin=27, winSum=448
1601 09:33:09.020026 TX Vref=26, minBit 9, minWin=27, winSum=446
1602 09:33:09.023838 TX Vref=28, minBit 9, minWin=27, winSum=449
1603 09:33:09.027086 TX Vref=30, minBit 10, minWin=27, winSum=447
1604 09:33:09.033199 TX Vref=32, minBit 8, minWin=27, winSum=445
1605 09:33:09.036846 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 28
1606 09:33:09.037322
1607 09:33:09.039913 Final TX Range 1 Vref 28
1608 09:33:09.040339
1609 09:33:09.040844 ==
1610 09:33:09.043639 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 09:33:09.046633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 09:33:09.047060 ==
1613 09:33:09.050318
1614 09:33:09.050896
1615 09:33:09.051345 TX Vref Scan disable
1616 09:33:09.053622 == TX Byte 0 ==
1617 09:33:09.056951 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1618 09:33:09.063807 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1619 09:33:09.064341 == TX Byte 1 ==
1620 09:33:09.066702 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1621 09:33:09.073642 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1622 09:33:09.074159
1623 09:33:09.074548 [DATLAT]
1624 09:33:09.074859 Freq=800, CH1 RK0
1625 09:33:09.075158
1626 09:33:09.076602 DATLAT Default: 0xa
1627 09:33:09.077014 0, 0xFFFF, sum = 0
1628 09:33:09.080046 1, 0xFFFF, sum = 0
1629 09:33:09.083322 2, 0xFFFF, sum = 0
1630 09:33:09.083910 3, 0xFFFF, sum = 0
1631 09:33:09.086871 4, 0xFFFF, sum = 0
1632 09:33:09.087388 5, 0xFFFF, sum = 0
1633 09:33:09.089908 6, 0xFFFF, sum = 0
1634 09:33:09.090327 7, 0xFFFF, sum = 0
1635 09:33:09.093953 8, 0xFFFF, sum = 0
1636 09:33:09.094513 9, 0x0, sum = 1
1637 09:33:09.096331 10, 0x0, sum = 2
1638 09:33:09.096987 11, 0x0, sum = 3
1639 09:33:09.097427 12, 0x0, sum = 4
1640 09:33:09.099835 best_step = 10
1641 09:33:09.100294
1642 09:33:09.100656 ==
1643 09:33:09.102945 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 09:33:09.106186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 09:33:09.106645 ==
1646 09:33:09.109930 RX Vref Scan: 1
1647 09:33:09.110375
1648 09:33:09.113044 Set Vref Range= 32 -> 127
1649 09:33:09.113590
1650 09:33:09.114064 RX Vref 32 -> 127, step: 1
1651 09:33:09.114517
1652 09:33:09.116654 RX Delay -111 -> 252, step: 8
1653 09:33:09.117067
1654 09:33:09.119402 Set Vref, RX VrefLevel [Byte0]: 32
1655 09:33:09.122987 [Byte1]: 32
1656 09:33:09.126096
1657 09:33:09.126531 Set Vref, RX VrefLevel [Byte0]: 33
1658 09:33:09.129929 [Byte1]: 33
1659 09:33:09.134155
1660 09:33:09.134563 Set Vref, RX VrefLevel [Byte0]: 34
1661 09:33:09.140321 [Byte1]: 34
1662 09:33:09.140735
1663 09:33:09.143663 Set Vref, RX VrefLevel [Byte0]: 35
1664 09:33:09.147212 [Byte1]: 35
1665 09:33:09.147763
1666 09:33:09.150440 Set Vref, RX VrefLevel [Byte0]: 36
1667 09:33:09.153833 [Byte1]: 36
1668 09:33:09.157112
1669 09:33:09.157627 Set Vref, RX VrefLevel [Byte0]: 37
1670 09:33:09.160441 [Byte1]: 37
1671 09:33:09.164774
1672 09:33:09.165287 Set Vref, RX VrefLevel [Byte0]: 38
1673 09:33:09.167842 [Byte1]: 38
1674 09:33:09.172595
1675 09:33:09.173109 Set Vref, RX VrefLevel [Byte0]: 39
1676 09:33:09.175822 [Byte1]: 39
1677 09:33:09.180616
1678 09:33:09.181125 Set Vref, RX VrefLevel [Byte0]: 40
1679 09:33:09.183128 [Byte1]: 40
1680 09:33:09.188114
1681 09:33:09.188628 Set Vref, RX VrefLevel [Byte0]: 41
1682 09:33:09.190983 [Byte1]: 41
1683 09:33:09.195757
1684 09:33:09.196272 Set Vref, RX VrefLevel [Byte0]: 42
1685 09:33:09.198411 [Byte1]: 42
1686 09:33:09.203379
1687 09:33:09.203917 Set Vref, RX VrefLevel [Byte0]: 43
1688 09:33:09.206194 [Byte1]: 43
1689 09:33:09.210924
1690 09:33:09.214004 Set Vref, RX VrefLevel [Byte0]: 44
1691 09:33:09.214522 [Byte1]: 44
1692 09:33:09.218875
1693 09:33:09.219385 Set Vref, RX VrefLevel [Byte0]: 45
1694 09:33:09.221553 [Byte1]: 45
1695 09:33:09.225917
1696 09:33:09.226333 Set Vref, RX VrefLevel [Byte0]: 46
1697 09:33:09.229674 [Byte1]: 46
1698 09:33:09.233351
1699 09:33:09.233788 Set Vref, RX VrefLevel [Byte0]: 47
1700 09:33:09.236757 [Byte1]: 47
1701 09:33:09.241361
1702 09:33:09.241873 Set Vref, RX VrefLevel [Byte0]: 48
1703 09:33:09.244826 [Byte1]: 48
1704 09:33:09.249356
1705 09:33:09.249867 Set Vref, RX VrefLevel [Byte0]: 49
1706 09:33:09.252730 [Byte1]: 49
1707 09:33:09.256936
1708 09:33:09.257440 Set Vref, RX VrefLevel [Byte0]: 50
1709 09:33:09.259871 [Byte1]: 50
1710 09:33:09.264691
1711 09:33:09.265209 Set Vref, RX VrefLevel [Byte0]: 51
1712 09:33:09.267454 [Byte1]: 51
1713 09:33:09.271558
1714 09:33:09.272033 Set Vref, RX VrefLevel [Byte0]: 52
1715 09:33:09.275291 [Byte1]: 52
1716 09:33:09.279449
1717 09:33:09.280027 Set Vref, RX VrefLevel [Byte0]: 53
1718 09:33:09.282703 [Byte1]: 53
1719 09:33:09.287828
1720 09:33:09.288335 Set Vref, RX VrefLevel [Byte0]: 54
1721 09:33:09.290655 [Byte1]: 54
1722 09:33:09.294701
1723 09:33:09.295214 Set Vref, RX VrefLevel [Byte0]: 55
1724 09:33:09.297835 [Byte1]: 55
1725 09:33:09.302542
1726 09:33:09.303051 Set Vref, RX VrefLevel [Byte0]: 56
1727 09:33:09.305517 [Byte1]: 56
1728 09:33:09.309631
1729 09:33:09.310041 Set Vref, RX VrefLevel [Byte0]: 57
1730 09:33:09.312973 [Byte1]: 57
1731 09:33:09.317433
1732 09:33:09.317843 Set Vref, RX VrefLevel [Byte0]: 58
1733 09:33:09.320960 [Byte1]: 58
1734 09:33:09.325084
1735 09:33:09.325578 Set Vref, RX VrefLevel [Byte0]: 59
1736 09:33:09.329199 [Byte1]: 59
1737 09:33:09.332611
1738 09:33:09.333021 Set Vref, RX VrefLevel [Byte0]: 60
1739 09:33:09.337077 [Byte1]: 60
1740 09:33:09.340388
1741 09:33:09.340834 Set Vref, RX VrefLevel [Byte0]: 61
1742 09:33:09.343907 [Byte1]: 61
1743 09:33:09.348526
1744 09:33:09.349037 Set Vref, RX VrefLevel [Byte0]: 62
1745 09:33:09.351803 [Byte1]: 62
1746 09:33:09.356165
1747 09:33:09.356684 Set Vref, RX VrefLevel [Byte0]: 63
1748 09:33:09.359797 [Byte1]: 63
1749 09:33:09.364081
1750 09:33:09.364594 Set Vref, RX VrefLevel [Byte0]: 64
1751 09:33:09.367374 [Byte1]: 64
1752 09:33:09.371872
1753 09:33:09.372383 Set Vref, RX VrefLevel [Byte0]: 65
1754 09:33:09.374544 [Byte1]: 65
1755 09:33:09.379075
1756 09:33:09.379608 Set Vref, RX VrefLevel [Byte0]: 66
1757 09:33:09.382382 [Byte1]: 66
1758 09:33:09.386702
1759 09:33:09.387215 Set Vref, RX VrefLevel [Byte0]: 67
1760 09:33:09.390013 [Byte1]: 67
1761 09:33:09.394498
1762 09:33:09.395031 Set Vref, RX VrefLevel [Byte0]: 68
1763 09:33:09.397500 [Byte1]: 68
1764 09:33:09.401993
1765 09:33:09.402506 Set Vref, RX VrefLevel [Byte0]: 69
1766 09:33:09.404868 [Byte1]: 69
1767 09:33:09.409566
1768 09:33:09.409979 Set Vref, RX VrefLevel [Byte0]: 70
1769 09:33:09.412697 [Byte1]: 70
1770 09:33:09.417416
1771 09:33:09.417937 Set Vref, RX VrefLevel [Byte0]: 71
1772 09:33:09.420261 [Byte1]: 71
1773 09:33:09.425150
1774 09:33:09.425856 Set Vref, RX VrefLevel [Byte0]: 72
1775 09:33:09.428073 [Byte1]: 72
1776 09:33:09.432409
1777 09:33:09.432921 Set Vref, RX VrefLevel [Byte0]: 73
1778 09:33:09.435893 [Byte1]: 73
1779 09:33:09.440244
1780 09:33:09.440754 Set Vref, RX VrefLevel [Byte0]: 74
1781 09:33:09.443432 [Byte1]: 74
1782 09:33:09.447855
1783 09:33:09.448380 Set Vref, RX VrefLevel [Byte0]: 75
1784 09:33:09.450812 [Byte1]: 75
1785 09:33:09.455373
1786 09:33:09.455876 Set Vref, RX VrefLevel [Byte0]: 76
1787 09:33:09.458701 [Byte1]: 76
1788 09:33:09.463079
1789 09:33:09.463693 Set Vref, RX VrefLevel [Byte0]: 77
1790 09:33:09.466143 [Byte1]: 77
1791 09:33:09.470691
1792 09:33:09.471210 Final RX Vref Byte 0 = 51 to rank0
1793 09:33:09.474249 Final RX Vref Byte 1 = 62 to rank0
1794 09:33:09.477373 Final RX Vref Byte 0 = 51 to rank1
1795 09:33:09.480404 Final RX Vref Byte 1 = 62 to rank1==
1796 09:33:09.483817 Dram Type= 6, Freq= 0, CH_1, rank 0
1797 09:33:09.490517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 09:33:09.491090 ==
1799 09:33:09.491640 DQS Delay:
1800 09:33:09.493575 DQS0 = 0, DQS1 = 0
1801 09:33:09.494065 DQM Delay:
1802 09:33:09.494543 DQM0 = 86, DQM1 = 79
1803 09:33:09.497187 DQ Delay:
1804 09:33:09.500237 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1805 09:33:09.503558 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1806 09:33:09.507012 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1807 09:33:09.510195 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1808 09:33:09.510607
1809 09:33:09.510935
1810 09:33:09.516919 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1811 09:33:09.520121 CH1 RK0: MR19=606, MR18=301C
1812 09:33:09.526813 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1813 09:33:09.527405
1814 09:33:09.530499 ----->DramcWriteLeveling(PI) begin...
1815 09:33:09.531020 ==
1816 09:33:09.533813 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 09:33:09.536543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 09:33:09.536955 ==
1819 09:33:09.540657 Write leveling (Byte 0): 27 => 27
1820 09:33:09.543556 Write leveling (Byte 1): 27 => 27
1821 09:33:09.546302 DramcWriteLeveling(PI) end<-----
1822 09:33:09.546888
1823 09:33:09.547229 ==
1824 09:33:09.550239 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 09:33:09.553751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 09:33:09.554321 ==
1827 09:33:09.556422 [Gating] SW mode calibration
1828 09:33:09.563435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1829 09:33:09.570005 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1830 09:33:09.573591 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1831 09:33:09.580398 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1832 09:33:09.583091 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1833 09:33:09.587144 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:33:09.590151 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:33:09.596277 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:33:09.599662 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:33:09.602953 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:33:09.610160 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:33:09.612750 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:33:09.616593 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:33:09.623123 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:33:09.626497 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:33:09.629709 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:33:09.636073 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:33:09.639391 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:33:09.642844 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:33:09.649473 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1848 09:33:09.652629 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:33:09.656273 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:33:09.663599 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:33:09.666339 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:33:09.669780 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:33:09.676162 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:33:09.679666 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:33:09.682608 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:33:09.689205 0 9 8 | B1->B0 | 3232 2525 | 1 0 | (1 1) (0 0)
1857 09:33:09.692655 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 09:33:09.696434 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 09:33:09.702623 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 09:33:09.706120 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 09:33:09.708714 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 09:33:09.715865 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 09:33:09.719658 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 1)
1864 09:33:09.722555 0 10 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 0)
1865 09:33:09.729589 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:33:09.732513 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:33:09.735669 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:33:09.742486 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:33:09.745924 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 09:33:09.748766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:33:09.755376 0 11 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1872 09:33:09.758646 0 11 8 | B1->B0 | 3e3e 3838 | 0 0 | (1 1) (0 0)
1873 09:33:09.761884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 09:33:09.769047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 09:33:09.771944 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 09:33:09.775709 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 09:33:09.781984 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 09:33:09.785184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 09:33:09.788518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1880 09:33:09.795104 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 09:33:09.798337 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 09:33:09.802341 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 09:33:09.808508 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 09:33:09.811844 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 09:33:09.814764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 09:33:09.821272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 09:33:09.825041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 09:33:09.828334 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 09:33:09.832168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 09:33:09.838756 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 09:33:09.841259 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 09:33:09.845436 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 09:33:09.851669 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 09:33:09.854411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:33:09.858026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1896 09:33:09.865149 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1897 09:33:09.868173 Total UI for P1: 0, mck2ui 16
1898 09:33:09.870955 best dqsien dly found for B1: ( 0, 14, 4)
1899 09:33:09.874876 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 09:33:09.877902 Total UI for P1: 0, mck2ui 16
1901 09:33:09.881340 best dqsien dly found for B0: ( 0, 14, 8)
1902 09:33:09.884622 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1903 09:33:09.888439 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1904 09:33:09.888955
1905 09:33:09.890971 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1906 09:33:09.894943 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1907 09:33:09.898004 [Gating] SW calibration Done
1908 09:33:09.898419 ==
1909 09:33:09.901497 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 09:33:09.907761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 09:33:09.908289 ==
1912 09:33:09.908731 RX Vref Scan: 0
1913 09:33:09.909224
1914 09:33:09.910671 RX Vref 0 -> 0, step: 1
1915 09:33:09.911155
1916 09:33:09.914103 RX Delay -130 -> 252, step: 16
1917 09:33:09.917942 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1918 09:33:09.921314 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1919 09:33:09.923913 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1920 09:33:09.930896 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1921 09:33:09.934793 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1922 09:33:09.937780 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1923 09:33:09.940593 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1924 09:33:09.944078 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1925 09:33:09.950428 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1926 09:33:09.954256 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1927 09:33:09.956981 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1928 09:33:09.960381 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1929 09:33:09.964142 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1930 09:33:09.970281 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1931 09:33:09.974231 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1932 09:33:09.976915 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1933 09:33:09.977337 ==
1934 09:33:09.980721 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 09:33:09.983462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 09:33:09.986709 ==
1937 09:33:09.987270 DQS Delay:
1938 09:33:09.987780 DQS0 = 0, DQS1 = 0
1939 09:33:09.990529 DQM Delay:
1940 09:33:09.990945 DQM0 = 86, DQM1 = 78
1941 09:33:09.994002 DQ Delay:
1942 09:33:09.994614 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =77
1943 09:33:09.996970 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1944 09:33:10.000037 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1945 09:33:10.003580 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1946 09:33:10.006676
1947 09:33:10.007096
1948 09:33:10.007427 ==
1949 09:33:10.010097 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 09:33:10.013428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 09:33:10.013854 ==
1952 09:33:10.014188
1953 09:33:10.014499
1954 09:33:10.016872 TX Vref Scan disable
1955 09:33:10.017294 == TX Byte 0 ==
1956 09:33:10.023082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1957 09:33:10.026615 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1958 09:33:10.027038 == TX Byte 1 ==
1959 09:33:10.033408 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1960 09:33:10.036790 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1961 09:33:10.037356 ==
1962 09:33:10.039690 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 09:33:10.043145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 09:33:10.043771 ==
1965 09:33:10.056978 TX Vref=22, minBit 1, minWin=27, winSum=443
1966 09:33:10.060531 TX Vref=24, minBit 8, minWin=27, winSum=446
1967 09:33:10.063649 TX Vref=26, minBit 8, minWin=27, winSum=449
1968 09:33:10.067153 TX Vref=28, minBit 13, minWin=27, winSum=452
1969 09:33:10.070638 TX Vref=30, minBit 8, minWin=27, winSum=451
1970 09:33:10.077024 TX Vref=32, minBit 8, minWin=27, winSum=448
1971 09:33:10.080142 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1972 09:33:10.080629
1973 09:33:10.083822 Final TX Range 1 Vref 28
1974 09:33:10.084241
1975 09:33:10.084572 ==
1976 09:33:10.086904 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 09:33:10.090476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 09:33:10.094093 ==
1979 09:33:10.094608
1980 09:33:10.094940
1981 09:33:10.095249 TX Vref Scan disable
1982 09:33:10.097111 == TX Byte 0 ==
1983 09:33:10.100813 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1984 09:33:10.106950 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1985 09:33:10.107396 == TX Byte 1 ==
1986 09:33:10.110463 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1987 09:33:10.117199 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1988 09:33:10.117620
1989 09:33:10.117952 [DATLAT]
1990 09:33:10.118262 Freq=800, CH1 RK1
1991 09:33:10.118590
1992 09:33:10.121425 DATLAT Default: 0xa
1993 09:33:10.121947 0, 0xFFFF, sum = 0
1994 09:33:10.124032 1, 0xFFFF, sum = 0
1995 09:33:10.126630 2, 0xFFFF, sum = 0
1996 09:33:10.127057 3, 0xFFFF, sum = 0
1997 09:33:10.130188 4, 0xFFFF, sum = 0
1998 09:33:10.130614 5, 0xFFFF, sum = 0
1999 09:33:10.133751 6, 0xFFFF, sum = 0
2000 09:33:10.134271 7, 0xFFFF, sum = 0
2001 09:33:10.137636 8, 0xFFFF, sum = 0
2002 09:33:10.138154 9, 0x0, sum = 1
2003 09:33:10.140466 10, 0x0, sum = 2
2004 09:33:10.140896 11, 0x0, sum = 3
2005 09:33:10.143598 12, 0x0, sum = 4
2006 09:33:10.144163 best_step = 10
2007 09:33:10.144504
2008 09:33:10.144815 ==
2009 09:33:10.146610 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 09:33:10.150196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 09:33:10.150621 ==
2012 09:33:10.153418 RX Vref Scan: 0
2013 09:33:10.153838
2014 09:33:10.157025 RX Vref 0 -> 0, step: 1
2015 09:33:10.157536
2016 09:33:10.157871 RX Delay -95 -> 252, step: 8
2017 09:33:10.164177 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2018 09:33:10.167528 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2019 09:33:10.170680 iDelay=217, Bit 2, Center 72 (-39 ~ 184) 224
2020 09:33:10.174031 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2021 09:33:10.178054 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2022 09:33:10.183866 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2023 09:33:10.187492 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2024 09:33:10.190694 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2025 09:33:10.194051 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2026 09:33:10.197083 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2027 09:33:10.203818 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2028 09:33:10.207186 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2029 09:33:10.210369 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2030 09:33:10.213873 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2031 09:33:10.220372 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2032 09:33:10.224178 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2033 09:33:10.224736 ==
2034 09:33:10.227140 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 09:33:10.230208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 09:33:10.230763 ==
2037 09:33:10.234289 DQS Delay:
2038 09:33:10.234838 DQS0 = 0, DQS1 = 0
2039 09:33:10.235254 DQM Delay:
2040 09:33:10.236734 DQM0 = 86, DQM1 = 78
2041 09:33:10.237189 DQ Delay:
2042 09:33:10.240978 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =84
2043 09:33:10.243518 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2044 09:33:10.247051 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2045 09:33:10.250122 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2046 09:33:10.250584
2047 09:33:10.250947
2048 09:33:10.260166 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2049 09:33:10.260717 CH1 RK1: MR19=606, MR18=1C14
2050 09:33:10.266894 CH1_RK1: MR19=0x606, MR18=0x1C14, DQSOSC=402, MR23=63, INC=91, DEC=60
2051 09:33:10.270347 [RxdqsGatingPostProcess] freq 800
2052 09:33:10.276991 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2053 09:33:10.280485 Pre-setting of DQS Precalculation
2054 09:33:10.283914 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2055 09:33:10.293549 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2056 09:33:10.300008 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2057 09:33:10.300575
2058 09:33:10.300991
2059 09:33:10.303192 [Calibration Summary] 1600 Mbps
2060 09:33:10.303783 CH 0, Rank 0
2061 09:33:10.306624 SW Impedance : PASS
2062 09:33:10.307185 DUTY Scan : NO K
2063 09:33:10.310082 ZQ Calibration : PASS
2064 09:33:10.312679 Jitter Meter : NO K
2065 09:33:10.313149 CBT Training : PASS
2066 09:33:10.316364 Write leveling : PASS
2067 09:33:10.319873 RX DQS gating : PASS
2068 09:33:10.320431 RX DQ/DQS(RDDQC) : PASS
2069 09:33:10.323217 TX DQ/DQS : PASS
2070 09:33:10.326170 RX DATLAT : PASS
2071 09:33:10.326703 RX DQ/DQS(Engine): PASS
2072 09:33:10.329158 TX OE : NO K
2073 09:33:10.329625 All Pass.
2074 09:33:10.329989
2075 09:33:10.333454 CH 0, Rank 1
2076 09:33:10.334011 SW Impedance : PASS
2077 09:33:10.336224 DUTY Scan : NO K
2078 09:33:10.339455 ZQ Calibration : PASS
2079 09:33:10.340088 Jitter Meter : NO K
2080 09:33:10.342854 CBT Training : PASS
2081 09:33:10.343336 Write leveling : PASS
2082 09:33:10.346280 RX DQS gating : PASS
2083 09:33:10.349462 RX DQ/DQS(RDDQC) : PASS
2084 09:33:10.350020 TX DQ/DQS : PASS
2085 09:33:10.353156 RX DATLAT : PASS
2086 09:33:10.355650 RX DQ/DQS(Engine): PASS
2087 09:33:10.356172 TX OE : NO K
2088 09:33:10.358992 All Pass.
2089 09:33:10.359547
2090 09:33:10.359959 CH 1, Rank 0
2091 09:33:10.362580 SW Impedance : PASS
2092 09:33:10.363143 DUTY Scan : NO K
2093 09:33:10.366059 ZQ Calibration : PASS
2094 09:33:10.369319 Jitter Meter : NO K
2095 09:33:10.369876 CBT Training : PASS
2096 09:33:10.372334 Write leveling : PASS
2097 09:33:10.376315 RX DQS gating : PASS
2098 09:33:10.376873 RX DQ/DQS(RDDQC) : PASS
2099 09:33:10.379395 TX DQ/DQS : PASS
2100 09:33:10.382825 RX DATLAT : PASS
2101 09:33:10.383376 RX DQ/DQS(Engine): PASS
2102 09:33:10.385970 TX OE : NO K
2103 09:33:10.386728 All Pass.
2104 09:33:10.387182
2105 09:33:10.389032 CH 1, Rank 1
2106 09:33:10.389492 SW Impedance : PASS
2107 09:33:10.392475 DUTY Scan : NO K
2108 09:33:10.395499 ZQ Calibration : PASS
2109 09:33:10.396006 Jitter Meter : NO K
2110 09:33:10.399268 CBT Training : PASS
2111 09:33:10.399829 Write leveling : PASS
2112 09:33:10.402624 RX DQS gating : PASS
2113 09:33:10.405754 RX DQ/DQS(RDDQC) : PASS
2114 09:33:10.406314 TX DQ/DQS : PASS
2115 09:33:10.409625 RX DATLAT : PASS
2116 09:33:10.412646 RX DQ/DQS(Engine): PASS
2117 09:33:10.413110 TX OE : NO K
2118 09:33:10.415572 All Pass.
2119 09:33:10.416096
2120 09:33:10.416468 DramC Write-DBI off
2121 09:33:10.419789 PER_BANK_REFRESH: Hybrid Mode
2122 09:33:10.420256 TX_TRACKING: ON
2123 09:33:10.422958 [GetDramInforAfterCalByMRR] Vendor 6.
2124 09:33:10.429013 [GetDramInforAfterCalByMRR] Revision 606.
2125 09:33:10.432980 [GetDramInforAfterCalByMRR] Revision 2 0.
2126 09:33:10.433546 MR0 0x3b3b
2127 09:33:10.433909 MR8 0x5151
2128 09:33:10.436021 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 09:33:10.436479
2130 09:33:10.439705 MR0 0x3b3b
2131 09:33:10.440295 MR8 0x5151
2132 09:33:10.442283 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 09:33:10.442740
2134 09:33:10.452515 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2135 09:33:10.455836 [FAST_K] Save calibration result to emmc
2136 09:33:10.459623 [FAST_K] Save calibration result to emmc
2137 09:33:10.462270 dram_init: config_dvfs: 1
2138 09:33:10.466015 dramc_set_vcore_voltage set vcore to 662500
2139 09:33:10.468825 Read voltage for 1200, 2
2140 09:33:10.469343 Vio18 = 0
2141 09:33:10.469711 Vcore = 662500
2142 09:33:10.472048 Vdram = 0
2143 09:33:10.472506 Vddq = 0
2144 09:33:10.472868 Vmddr = 0
2145 09:33:10.479066 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2146 09:33:10.482526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2147 09:33:10.485148 MEM_TYPE=3, freq_sel=15
2148 09:33:10.488916 sv_algorithm_assistance_LP4_1600
2149 09:33:10.492107 ============ PULL DRAM RESETB DOWN ============
2150 09:33:10.495520 ========== PULL DRAM RESETB DOWN end =========
2151 09:33:10.502046 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2152 09:33:10.505531 ===================================
2153 09:33:10.508574 LPDDR4 DRAM CONFIGURATION
2154 09:33:10.511772 ===================================
2155 09:33:10.512350 EX_ROW_EN[0] = 0x0
2156 09:33:10.515205 EX_ROW_EN[1] = 0x0
2157 09:33:10.515624 LP4Y_EN = 0x0
2158 09:33:10.518692 WORK_FSP = 0x0
2159 09:33:10.519376 WL = 0x4
2160 09:33:10.522123 RL = 0x4
2161 09:33:10.522544 BL = 0x2
2162 09:33:10.525045 RPST = 0x0
2163 09:33:10.525507 RD_PRE = 0x0
2164 09:33:10.528262 WR_PRE = 0x1
2165 09:33:10.528892 WR_PST = 0x0
2166 09:33:10.532127 DBI_WR = 0x0
2167 09:33:10.532685 DBI_RD = 0x0
2168 09:33:10.535456 OTF = 0x1
2169 09:33:10.538396 ===================================
2170 09:33:10.541661 ===================================
2171 09:33:10.542217 ANA top config
2172 09:33:10.545187 ===================================
2173 09:33:10.548095 DLL_ASYNC_EN = 0
2174 09:33:10.551834 ALL_SLAVE_EN = 0
2175 09:33:10.555109 NEW_RANK_MODE = 1
2176 09:33:10.555668 DLL_IDLE_MODE = 1
2177 09:33:10.558635 LP45_APHY_COMB_EN = 1
2178 09:33:10.561917 TX_ODT_DIS = 1
2179 09:33:10.565468 NEW_8X_MODE = 1
2180 09:33:10.568127 ===================================
2181 09:33:10.571831 ===================================
2182 09:33:10.574770 data_rate = 2400
2183 09:33:10.578019 CKR = 1
2184 09:33:10.578578 DQ_P2S_RATIO = 8
2185 09:33:10.581381 ===================================
2186 09:33:10.584732 CA_P2S_RATIO = 8
2187 09:33:10.587834 DQ_CA_OPEN = 0
2188 09:33:10.591817 DQ_SEMI_OPEN = 0
2189 09:33:10.594475 CA_SEMI_OPEN = 0
2190 09:33:10.597854 CA_FULL_RATE = 0
2191 09:33:10.598411 DQ_CKDIV4_EN = 0
2192 09:33:10.601162 CA_CKDIV4_EN = 0
2193 09:33:10.604420 CA_PREDIV_EN = 0
2194 09:33:10.607875 PH8_DLY = 17
2195 09:33:10.611016 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2196 09:33:10.614429 DQ_AAMCK_DIV = 4
2197 09:33:10.614953 CA_AAMCK_DIV = 4
2198 09:33:10.618288 CA_ADMCK_DIV = 4
2199 09:33:10.621192 DQ_TRACK_CA_EN = 0
2200 09:33:10.624663 CA_PICK = 1200
2201 09:33:10.627919 CA_MCKIO = 1200
2202 09:33:10.631235 MCKIO_SEMI = 0
2203 09:33:10.634342 PLL_FREQ = 2366
2204 09:33:10.634898 DQ_UI_PI_RATIO = 32
2205 09:33:10.637759 CA_UI_PI_RATIO = 0
2206 09:33:10.640937 ===================================
2207 09:33:10.644392 ===================================
2208 09:33:10.647588 memory_type:LPDDR4
2209 09:33:10.651547 GP_NUM : 10
2210 09:33:10.652159 SRAM_EN : 1
2211 09:33:10.654657 MD32_EN : 0
2212 09:33:10.657642 ===================================
2213 09:33:10.661247 [ANA_INIT] >>>>>>>>>>>>>>
2214 09:33:10.661809 <<<<<< [CONFIGURE PHASE]: ANA_TX
2215 09:33:10.664269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2216 09:33:10.667521 ===================================
2217 09:33:10.671088 data_rate = 2400,PCW = 0X5b00
2218 09:33:10.674829 ===================================
2219 09:33:10.677378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2220 09:33:10.684396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2221 09:33:10.690994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2222 09:33:10.694259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2223 09:33:10.697279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2224 09:33:10.701112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2225 09:33:10.704039 [ANA_INIT] flow start
2226 09:33:10.704503 [ANA_INIT] PLL >>>>>>>>
2227 09:33:10.707345 [ANA_INIT] PLL <<<<<<<<
2228 09:33:10.710801 [ANA_INIT] MIDPI >>>>>>>>
2229 09:33:10.713687 [ANA_INIT] MIDPI <<<<<<<<
2230 09:33:10.714153 [ANA_INIT] DLL >>>>>>>>
2231 09:33:10.717138 [ANA_INIT] DLL <<<<<<<<
2232 09:33:10.717692 [ANA_INIT] flow end
2233 09:33:10.723823 ============ LP4 DIFF to SE enter ============
2234 09:33:10.727291 ============ LP4 DIFF to SE exit ============
2235 09:33:10.730865 [ANA_INIT] <<<<<<<<<<<<<
2236 09:33:10.734074 [Flow] Enable top DCM control >>>>>
2237 09:33:10.737208 [Flow] Enable top DCM control <<<<<
2238 09:33:10.737677 Enable DLL master slave shuffle
2239 09:33:10.743658 ==============================================================
2240 09:33:10.747030 Gating Mode config
2241 09:33:10.750488 ==============================================================
2242 09:33:10.754184 Config description:
2243 09:33:10.763589 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2244 09:33:10.770195 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2245 09:33:10.773758 SELPH_MODE 0: By rank 1: By Phase
2246 09:33:10.779990 ==============================================================
2247 09:33:10.784002 GAT_TRACK_EN = 1
2248 09:33:10.787245 RX_GATING_MODE = 2
2249 09:33:10.790809 RX_GATING_TRACK_MODE = 2
2250 09:33:10.794036 SELPH_MODE = 1
2251 09:33:10.797110 PICG_EARLY_EN = 1
2252 09:33:10.797663 VALID_LAT_VALUE = 1
2253 09:33:10.803895 ==============================================================
2254 09:33:10.806856 Enter into Gating configuration >>>>
2255 09:33:10.810515 Exit from Gating configuration <<<<
2256 09:33:10.813200 Enter into DVFS_PRE_config >>>>>
2257 09:33:10.823137 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2258 09:33:10.826617 Exit from DVFS_PRE_config <<<<<
2259 09:33:10.829770 Enter into PICG configuration >>>>
2260 09:33:10.833569 Exit from PICG configuration <<<<
2261 09:33:10.836684 [RX_INPUT] configuration >>>>>
2262 09:33:10.839795 [RX_INPUT] configuration <<<<<
2263 09:33:10.843711 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2264 09:33:10.849826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2265 09:33:10.856458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 09:33:10.863093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 09:33:10.869520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2268 09:33:10.876317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2269 09:33:10.879629 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2270 09:33:10.882710 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2271 09:33:10.885904 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2272 09:33:10.892534 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2273 09:33:10.895915 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2274 09:33:10.899276 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 09:33:10.902590 ===================================
2276 09:33:10.906111 LPDDR4 DRAM CONFIGURATION
2277 09:33:10.909498 ===================================
2278 09:33:10.910017 EX_ROW_EN[0] = 0x0
2279 09:33:10.912927 EX_ROW_EN[1] = 0x0
2280 09:33:10.916130 LP4Y_EN = 0x0
2281 09:33:10.916557 WORK_FSP = 0x0
2282 09:33:10.919544 WL = 0x4
2283 09:33:10.920113 RL = 0x4
2284 09:33:10.922813 BL = 0x2
2285 09:33:10.923326 RPST = 0x0
2286 09:33:10.926231 RD_PRE = 0x0
2287 09:33:10.926651 WR_PRE = 0x1
2288 09:33:10.929185 WR_PST = 0x0
2289 09:33:10.929647 DBI_WR = 0x0
2290 09:33:10.932978 DBI_RD = 0x0
2291 09:33:10.933494 OTF = 0x1
2292 09:33:10.936091 ===================================
2293 09:33:10.939917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2294 09:33:10.945772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2295 09:33:10.948804 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 09:33:10.952180 ===================================
2297 09:33:10.955707 LPDDR4 DRAM CONFIGURATION
2298 09:33:10.959506 ===================================
2299 09:33:10.960063 EX_ROW_EN[0] = 0x10
2300 09:33:10.962586 EX_ROW_EN[1] = 0x0
2301 09:33:10.963097 LP4Y_EN = 0x0
2302 09:33:10.965811 WORK_FSP = 0x0
2303 09:33:10.966229 WL = 0x4
2304 09:33:10.969187 RL = 0x4
2305 09:33:10.972724 BL = 0x2
2306 09:33:10.973232 RPST = 0x0
2307 09:33:10.975647 RD_PRE = 0x0
2308 09:33:10.976210 WR_PRE = 0x1
2309 09:33:10.979093 WR_PST = 0x0
2310 09:33:10.979507 DBI_WR = 0x0
2311 09:33:10.982643 DBI_RD = 0x0
2312 09:33:10.983153 OTF = 0x1
2313 09:33:10.985797 ===================================
2314 09:33:10.992329 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2315 09:33:10.992831 ==
2316 09:33:10.995551 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 09:33:10.999210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2318 09:33:10.999631 ==
2319 09:33:11.002103 [Duty_Offset_Calibration]
2320 09:33:11.005573 B0:1 B1:-1 CA:0
2321 09:33:11.006098
2322 09:33:11.008603 [DutyScan_Calibration_Flow] k_type=0
2323 09:33:11.017135
2324 09:33:11.017634 ==CLK 0==
2325 09:33:11.020077 Final CLK duty delay cell = 0
2326 09:33:11.023515 [0] MAX Duty = 5125%(X100), DQS PI = 24
2327 09:33:11.027430 [0] MIN Duty = 4907%(X100), DQS PI = 10
2328 09:33:11.027996 [0] AVG Duty = 5016%(X100)
2329 09:33:11.030132
2330 09:33:11.033710 CH0 CLK Duty spec in!! Max-Min= 218%
2331 09:33:11.037081 [DutyScan_Calibration_Flow] ====Done====
2332 09:33:11.037590
2333 09:33:11.040297 [DutyScan_Calibration_Flow] k_type=1
2334 09:33:11.055360
2335 09:33:11.055986 ==DQS 0 ==
2336 09:33:11.058917 Final DQS duty delay cell = -4
2337 09:33:11.061955 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2338 09:33:11.065271 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2339 09:33:11.069352 [-4] AVG Duty = 4968%(X100)
2340 09:33:11.069907
2341 09:33:11.070274 ==DQS 1 ==
2342 09:33:11.071781 Final DQS duty delay cell = 0
2343 09:33:11.075058 [0] MAX Duty = 5124%(X100), DQS PI = 4
2344 09:33:11.078118 [0] MIN Duty = 5000%(X100), DQS PI = 24
2345 09:33:11.082039 [0] AVG Duty = 5062%(X100)
2346 09:33:11.082587
2347 09:33:11.085401 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2348 09:33:11.085957
2349 09:33:11.089128 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2350 09:33:11.092344 [DutyScan_Calibration_Flow] ====Done====
2351 09:33:11.092895
2352 09:33:11.095023 [DutyScan_Calibration_Flow] k_type=3
2353 09:33:11.113397
2354 09:33:11.114179 ==DQM 0 ==
2355 09:33:11.116380 Final DQM duty delay cell = 0
2356 09:33:11.119410 [0] MAX Duty = 5062%(X100), DQS PI = 24
2357 09:33:11.122922 [0] MIN Duty = 4875%(X100), DQS PI = 6
2358 09:33:11.123357 [0] AVG Duty = 4968%(X100)
2359 09:33:11.126666
2360 09:33:11.127242 ==DQM 1 ==
2361 09:33:11.129545 Final DQM duty delay cell = 4
2362 09:33:11.132745 [4] MAX Duty = 5187%(X100), DQS PI = 14
2363 09:33:11.136396 [4] MIN Duty = 5000%(X100), DQS PI = 24
2364 09:33:11.140006 [4] AVG Duty = 5093%(X100)
2365 09:33:11.140461
2366 09:33:11.143131 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2367 09:33:11.143588
2368 09:33:11.145922 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2369 09:33:11.149274 [DutyScan_Calibration_Flow] ====Done====
2370 09:33:11.149692
2371 09:33:11.152426 [DutyScan_Calibration_Flow] k_type=2
2372 09:33:11.167828
2373 09:33:11.168243 ==DQ 0 ==
2374 09:33:11.171384 Final DQ duty delay cell = -4
2375 09:33:11.174671 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2376 09:33:11.178054 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2377 09:33:11.181299 [-4] AVG Duty = 4969%(X100)
2378 09:33:11.181818
2379 09:33:11.182151 ==DQ 1 ==
2380 09:33:11.184514 Final DQ duty delay cell = -4
2381 09:33:11.187443 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2382 09:33:11.191423 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2383 09:33:11.194364 [-4] AVG Duty = 4938%(X100)
2384 09:33:11.194915
2385 09:33:11.197952 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2386 09:33:11.198508
2387 09:33:11.200837 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2388 09:33:11.204095 [DutyScan_Calibration_Flow] ====Done====
2389 09:33:11.204550 ==
2390 09:33:11.208208 Dram Type= 6, Freq= 0, CH_1, rank 0
2391 09:33:11.211208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2392 09:33:11.211965 ==
2393 09:33:11.214238 [Duty_Offset_Calibration]
2394 09:33:11.217774 B0:-1 B1:1 CA:1
2395 09:33:11.218233
2396 09:33:11.221064 [DutyScan_Calibration_Flow] k_type=0
2397 09:33:11.228750
2398 09:33:11.229309 ==CLK 0==
2399 09:33:11.231787 Final CLK duty delay cell = 0
2400 09:33:11.235591 [0] MAX Duty = 5156%(X100), DQS PI = 22
2401 09:33:11.238653 [0] MIN Duty = 4969%(X100), DQS PI = 60
2402 09:33:11.241877 [0] AVG Duty = 5062%(X100)
2403 09:33:11.242461
2404 09:33:11.245328 CH1 CLK Duty spec in!! Max-Min= 187%
2405 09:33:11.248303 [DutyScan_Calibration_Flow] ====Done====
2406 09:33:11.248721
2407 09:33:11.251846 [DutyScan_Calibration_Flow] k_type=1
2408 09:33:11.267909
2409 09:33:11.268411 ==DQS 0 ==
2410 09:33:11.271354 Final DQS duty delay cell = 0
2411 09:33:11.274558 [0] MAX Duty = 5156%(X100), DQS PI = 48
2412 09:33:11.278635 [0] MIN Duty = 4875%(X100), DQS PI = 8
2413 09:33:11.281491 [0] AVG Duty = 5015%(X100)
2414 09:33:11.282041
2415 09:33:11.282406 ==DQS 1 ==
2416 09:33:11.284506 Final DQS duty delay cell = 0
2417 09:33:11.287806 [0] MAX Duty = 5094%(X100), DQS PI = 14
2418 09:33:11.291670 [0] MIN Duty = 4969%(X100), DQS PI = 56
2419 09:33:11.294817 [0] AVG Duty = 5031%(X100)
2420 09:33:11.295368
2421 09:33:11.298251 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2422 09:33:11.298805
2423 09:33:11.300856 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2424 09:33:11.304360 [DutyScan_Calibration_Flow] ====Done====
2425 09:33:11.304953
2426 09:33:11.307527 [DutyScan_Calibration_Flow] k_type=3
2427 09:33:11.323641
2428 09:33:11.324196 ==DQM 0 ==
2429 09:33:11.327023 Final DQM duty delay cell = -4
2430 09:33:11.329923 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2431 09:33:11.334223 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2432 09:33:11.337116 [-4] AVG Duty = 4969%(X100)
2433 09:33:11.337669
2434 09:33:11.338030 ==DQM 1 ==
2435 09:33:11.340413 Final DQM duty delay cell = 0
2436 09:33:11.343886 [0] MAX Duty = 5156%(X100), DQS PI = 4
2437 09:33:11.346672 [0] MIN Duty = 5000%(X100), DQS PI = 28
2438 09:33:11.350149 [0] AVG Duty = 5078%(X100)
2439 09:33:11.350572
2440 09:33:11.353334 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2441 09:33:11.353753
2442 09:33:11.356477 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2443 09:33:11.360028 [DutyScan_Calibration_Flow] ====Done====
2444 09:33:11.360448
2445 09:33:11.363118 [DutyScan_Calibration_Flow] k_type=2
2446 09:33:11.380425
2447 09:33:11.380997 ==DQ 0 ==
2448 09:33:11.383337 Final DQ duty delay cell = 0
2449 09:33:11.387287 [0] MAX Duty = 5156%(X100), DQS PI = 28
2450 09:33:11.390525 [0] MIN Duty = 4876%(X100), DQS PI = 8
2451 09:33:11.391004 [0] AVG Duty = 5016%(X100)
2452 09:33:11.393535
2453 09:33:11.393995 ==DQ 1 ==
2454 09:33:11.396670 Final DQ duty delay cell = 0
2455 09:33:11.400148 [0] MAX Duty = 5124%(X100), DQS PI = 10
2456 09:33:11.403384 [0] MIN Duty = 4969%(X100), DQS PI = 34
2457 09:33:11.403850 [0] AVG Duty = 5046%(X100)
2458 09:33:11.404194
2459 09:33:11.407091 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2460 09:33:11.410496
2461 09:33:11.413657 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2462 09:33:11.416861 [DutyScan_Calibration_Flow] ====Done====
2463 09:33:11.420279 nWR fixed to 30
2464 09:33:11.420700 [ModeRegInit_LP4] CH0 RK0
2465 09:33:11.423131 [ModeRegInit_LP4] CH0 RK1
2466 09:33:11.427109 [ModeRegInit_LP4] CH1 RK0
2467 09:33:11.430482 [ModeRegInit_LP4] CH1 RK1
2468 09:33:11.430997 match AC timing 7
2469 09:33:11.433777 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2470 09:33:11.440092 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2471 09:33:11.443349 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2472 09:33:11.447194 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2473 09:33:11.453870 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2474 09:33:11.454600 ==
2475 09:33:11.456665 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 09:33:11.459927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 09:33:11.460394 ==
2478 09:33:11.466941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 09:33:11.473331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 09:33:11.480249 [CA 0] Center 39 (9~70) winsize 62
2481 09:33:11.484039 [CA 1] Center 39 (9~70) winsize 62
2482 09:33:11.486645 [CA 2] Center 35 (5~66) winsize 62
2483 09:33:11.490560 [CA 3] Center 35 (5~65) winsize 61
2484 09:33:11.493579 [CA 4] Center 33 (3~64) winsize 62
2485 09:33:11.497299 [CA 5] Center 33 (4~63) winsize 60
2486 09:33:11.497855
2487 09:33:11.500132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 09:33:11.500593
2489 09:33:11.503647 [CATrainingPosCal] consider 1 rank data
2490 09:33:11.507374 u2DelayCellTimex100 = 270/100 ps
2491 09:33:11.509939 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2492 09:33:11.517081 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2493 09:33:11.520446 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 09:33:11.523557 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2495 09:33:11.526443 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2496 09:33:11.529906 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2497 09:33:11.530366
2498 09:33:11.533074 CA PerBit enable=1, Macro0, CA PI delay=33
2499 09:33:11.533537
2500 09:33:11.536124 [CBTSetCACLKResult] CA Dly = 33
2501 09:33:11.539669 CS Dly: 8 (0~39)
2502 09:33:11.540131 ==
2503 09:33:11.543157 Dram Type= 6, Freq= 0, CH_0, rank 1
2504 09:33:11.546558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 09:33:11.546988 ==
2506 09:33:11.549633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 09:33:11.556304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 09:33:11.566122 [CA 0] Center 39 (9~70) winsize 62
2509 09:33:11.569628 [CA 1] Center 39 (9~70) winsize 62
2510 09:33:11.573032 [CA 2] Center 35 (5~66) winsize 62
2511 09:33:11.576310 [CA 3] Center 34 (4~65) winsize 62
2512 09:33:11.579269 [CA 4] Center 33 (3~64) winsize 62
2513 09:33:11.582262 [CA 5] Center 33 (3~63) winsize 61
2514 09:33:11.582680
2515 09:33:11.585558 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 09:33:11.585973
2517 09:33:11.589375 [CATrainingPosCal] consider 2 rank data
2518 09:33:11.592385 u2DelayCellTimex100 = 270/100 ps
2519 09:33:11.595593 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2520 09:33:11.602364 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2521 09:33:11.605427 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 09:33:11.609110 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2523 09:33:11.612080 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2524 09:33:11.615702 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2525 09:33:11.616261
2526 09:33:11.619389 CA PerBit enable=1, Macro0, CA PI delay=33
2527 09:33:11.619927
2528 09:33:11.622205 [CBTSetCACLKResult] CA Dly = 33
2529 09:33:11.622668 CS Dly: 9 (0~41)
2530 09:33:11.625606
2531 09:33:11.628772 ----->DramcWriteLeveling(PI) begin...
2532 09:33:11.629199 ==
2533 09:33:11.632104 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 09:33:11.636105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 09:33:11.636623 ==
2536 09:33:11.639385 Write leveling (Byte 0): 34 => 34
2537 09:33:11.642240 Write leveling (Byte 1): 29 => 29
2538 09:33:11.646028 DramcWriteLeveling(PI) end<-----
2539 09:33:11.646463
2540 09:33:11.646794 ==
2541 09:33:11.649097 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 09:33:11.652480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 09:33:11.652946 ==
2544 09:33:11.656400 [Gating] SW mode calibration
2545 09:33:11.662494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2546 09:33:11.668813 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2547 09:33:11.672293 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2548 09:33:11.676197 0 15 4 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2549 09:33:11.682099 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 09:33:11.685257 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 09:33:11.688876 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 09:33:11.695430 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 09:33:11.698511 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 09:33:11.701933 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 1)
2555 09:33:11.708600 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2556 09:33:11.712032 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 09:33:11.715154 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 09:33:11.718278 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 09:33:11.724783 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 09:33:11.728429 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 09:33:11.731634 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 09:33:11.738759 1 0 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
2563 09:33:11.742104 1 1 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2564 09:33:11.745105 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2565 09:33:11.751877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 09:33:11.755072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 09:33:11.758311 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 09:33:11.764754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 09:33:11.768367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 09:33:11.771630 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2571 09:33:11.778665 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2572 09:33:11.782025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 09:33:11.784650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 09:33:11.791442 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 09:33:11.795038 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 09:33:11.797914 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 09:33:11.804603 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 09:33:11.808031 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 09:33:11.811110 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 09:33:11.817927 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 09:33:11.821263 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 09:33:11.824539 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 09:33:11.830982 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 09:33:11.833924 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 09:33:11.837286 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 09:33:11.844419 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2587 09:33:11.847471 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2588 09:33:11.851165 Total UI for P1: 0, mck2ui 16
2589 09:33:11.854665 best dqsien dly found for B0: ( 1, 3, 28)
2590 09:33:11.857502 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2591 09:33:11.864162 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 09:33:11.864720 Total UI for P1: 0, mck2ui 16
2593 09:33:11.870922 best dqsien dly found for B1: ( 1, 4, 2)
2594 09:33:11.874092 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2595 09:33:11.877683 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2596 09:33:11.878261
2597 09:33:11.880493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2598 09:33:11.884311 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2599 09:33:11.887438 [Gating] SW calibration Done
2600 09:33:11.888079 ==
2601 09:33:11.891016 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 09:33:11.894477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 09:33:11.895063 ==
2604 09:33:11.897778 RX Vref Scan: 0
2605 09:33:11.898354
2606 09:33:11.898841 RX Vref 0 -> 0, step: 1
2607 09:33:11.899297
2608 09:33:11.901297 RX Delay -40 -> 252, step: 8
2609 09:33:11.903873 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2610 09:33:11.910556 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2611 09:33:11.913650 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2612 09:33:11.917540 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2613 09:33:11.920483 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2614 09:33:11.923700 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2615 09:33:11.930460 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2616 09:33:11.933600 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2617 09:33:11.937162 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2618 09:33:11.940135 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2619 09:33:11.943406 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2620 09:33:11.950558 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2621 09:33:11.953642 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2622 09:33:11.956525 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2623 09:33:11.959820 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2624 09:33:11.966821 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2625 09:33:11.967375 ==
2626 09:33:11.970193 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 09:33:11.973214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 09:33:11.973672 ==
2629 09:33:11.974030 DQS Delay:
2630 09:33:11.976567 DQS0 = 0, DQS1 = 0
2631 09:33:11.977023 DQM Delay:
2632 09:33:11.980268 DQM0 = 119, DQM1 = 107
2633 09:33:11.980828 DQ Delay:
2634 09:33:11.983474 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2635 09:33:11.986641 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2636 09:33:11.989714 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2637 09:33:11.993442 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2638 09:33:11.993995
2639 09:33:11.994357
2640 09:33:11.996263 ==
2641 09:33:11.996719 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 09:33:12.003381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 09:33:12.004155 ==
2644 09:33:12.004535
2645 09:33:12.004878
2646 09:33:12.005957 TX Vref Scan disable
2647 09:33:12.006417 == TX Byte 0 ==
2648 09:33:12.009535 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2649 09:33:12.016685 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2650 09:33:12.017245 == TX Byte 1 ==
2651 09:33:12.019715 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2652 09:33:12.026316 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2653 09:33:12.026871 ==
2654 09:33:12.029461 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 09:33:12.032627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 09:33:12.033086 ==
2657 09:33:12.045415 TX Vref=22, minBit 5, minWin=25, winSum=414
2658 09:33:12.048358 TX Vref=24, minBit 13, minWin=25, winSum=422
2659 09:33:12.052313 TX Vref=26, minBit 1, minWin=26, winSum=429
2660 09:33:12.054927 TX Vref=28, minBit 10, minWin=26, winSum=436
2661 09:33:12.058320 TX Vref=30, minBit 10, minWin=26, winSum=438
2662 09:33:12.065098 TX Vref=32, minBit 4, minWin=26, winSum=431
2663 09:33:12.068217 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
2664 09:33:12.068676
2665 09:33:12.071608 Final TX Range 1 Vref 30
2666 09:33:12.072106
2667 09:33:12.072469 ==
2668 09:33:12.075041 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 09:33:12.081301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 09:33:12.081944 ==
2671 09:33:12.082464
2672 09:33:12.082814
2673 09:33:12.083142 TX Vref Scan disable
2674 09:33:12.084877 == TX Byte 0 ==
2675 09:33:12.088487 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2676 09:33:12.095180 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2677 09:33:12.095778 == TX Byte 1 ==
2678 09:33:12.098604 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2679 09:33:12.104902 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2680 09:33:12.105361
2681 09:33:12.105722 [DATLAT]
2682 09:33:12.106058 Freq=1200, CH0 RK0
2683 09:33:12.106385
2684 09:33:12.108453 DATLAT Default: 0xd
2685 09:33:12.108907 0, 0xFFFF, sum = 0
2686 09:33:12.111547 1, 0xFFFF, sum = 0
2687 09:33:12.115151 2, 0xFFFF, sum = 0
2688 09:33:12.115617 3, 0xFFFF, sum = 0
2689 09:33:12.118420 4, 0xFFFF, sum = 0
2690 09:33:12.118893 5, 0xFFFF, sum = 0
2691 09:33:12.121449 6, 0xFFFF, sum = 0
2692 09:33:12.122156 7, 0xFFFF, sum = 0
2693 09:33:12.125455 8, 0xFFFF, sum = 0
2694 09:33:12.126015 9, 0xFFFF, sum = 0
2695 09:33:12.128305 10, 0xFFFF, sum = 0
2696 09:33:12.128768 11, 0xFFFF, sum = 0
2697 09:33:12.131674 12, 0x0, sum = 1
2698 09:33:12.132187 13, 0x0, sum = 2
2699 09:33:12.135119 14, 0x0, sum = 3
2700 09:33:12.135673 15, 0x0, sum = 4
2701 09:33:12.138246 best_step = 13
2702 09:33:12.138791
2703 09:33:12.139158 ==
2704 09:33:12.142262 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 09:33:12.145065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 09:33:12.145618 ==
2707 09:33:12.145987 RX Vref Scan: 1
2708 09:33:12.146326
2709 09:33:12.148270 Set Vref Range= 32 -> 127
2710 09:33:12.148725
2711 09:33:12.151959 RX Vref 32 -> 127, step: 1
2712 09:33:12.152516
2713 09:33:12.155044 RX Delay -21 -> 252, step: 4
2714 09:33:12.155591
2715 09:33:12.158601 Set Vref, RX VrefLevel [Byte0]: 32
2716 09:33:12.161683 [Byte1]: 32
2717 09:33:12.162144
2718 09:33:12.165535 Set Vref, RX VrefLevel [Byte0]: 33
2719 09:33:12.168690 [Byte1]: 33
2720 09:33:12.171338
2721 09:33:12.171828 Set Vref, RX VrefLevel [Byte0]: 34
2722 09:33:12.175007 [Byte1]: 34
2723 09:33:12.179946
2724 09:33:12.180510 Set Vref, RX VrefLevel [Byte0]: 35
2725 09:33:12.183182 [Byte1]: 35
2726 09:33:12.188012
2727 09:33:12.188621 Set Vref, RX VrefLevel [Byte0]: 36
2728 09:33:12.190586 [Byte1]: 36
2729 09:33:12.195966
2730 09:33:12.196534 Set Vref, RX VrefLevel [Byte0]: 37
2731 09:33:12.199251 [Byte1]: 37
2732 09:33:12.203255
2733 09:33:12.203916 Set Vref, RX VrefLevel [Byte0]: 38
2734 09:33:12.206362 [Byte1]: 38
2735 09:33:12.211244
2736 09:33:12.211718 Set Vref, RX VrefLevel [Byte0]: 39
2737 09:33:12.214390 [Byte1]: 39
2738 09:33:12.218983
2739 09:33:12.219446 Set Vref, RX VrefLevel [Byte0]: 40
2740 09:33:12.222446 [Byte1]: 40
2741 09:33:12.227116
2742 09:33:12.227538 Set Vref, RX VrefLevel [Byte0]: 41
2743 09:33:12.230515 [Byte1]: 41
2744 09:33:12.234837
2745 09:33:12.235309 Set Vref, RX VrefLevel [Byte0]: 42
2746 09:33:12.238009 [Byte1]: 42
2747 09:33:12.242952
2748 09:33:12.243370 Set Vref, RX VrefLevel [Byte0]: 43
2749 09:33:12.246163 [Byte1]: 43
2750 09:33:12.250860
2751 09:33:12.254301 Set Vref, RX VrefLevel [Byte0]: 44
2752 09:33:12.254726 [Byte1]: 44
2753 09:33:12.258817
2754 09:33:12.259265 Set Vref, RX VrefLevel [Byte0]: 45
2755 09:33:12.262303 [Byte1]: 45
2756 09:33:12.266676
2757 09:33:12.267165 Set Vref, RX VrefLevel [Byte0]: 46
2758 09:33:12.269989 [Byte1]: 46
2759 09:33:12.274919
2760 09:33:12.275340 Set Vref, RX VrefLevel [Byte0]: 47
2761 09:33:12.278035 [Byte1]: 47
2762 09:33:12.282768
2763 09:33:12.283284 Set Vref, RX VrefLevel [Byte0]: 48
2764 09:33:12.286230 [Byte1]: 48
2765 09:33:12.290661
2766 09:33:12.291124 Set Vref, RX VrefLevel [Byte0]: 49
2767 09:33:12.294391 [Byte1]: 49
2768 09:33:12.298518
2769 09:33:12.299074 Set Vref, RX VrefLevel [Byte0]: 50
2770 09:33:12.301813 [Byte1]: 50
2771 09:33:12.306210
2772 09:33:12.306816 Set Vref, RX VrefLevel [Byte0]: 51
2773 09:33:12.309776 [Byte1]: 51
2774 09:33:12.314905
2775 09:33:12.315462 Set Vref, RX VrefLevel [Byte0]: 52
2776 09:33:12.317783 [Byte1]: 52
2777 09:33:12.322603
2778 09:33:12.323262 Set Vref, RX VrefLevel [Byte0]: 53
2779 09:33:12.325441 [Byte1]: 53
2780 09:33:12.330394
2781 09:33:12.330951 Set Vref, RX VrefLevel [Byte0]: 54
2782 09:33:12.333362 [Byte1]: 54
2783 09:33:12.338033
2784 09:33:12.338601 Set Vref, RX VrefLevel [Byte0]: 55
2785 09:33:12.341137 [Byte1]: 55
2786 09:33:12.346035
2787 09:33:12.346601 Set Vref, RX VrefLevel [Byte0]: 56
2788 09:33:12.349351 [Byte1]: 56
2789 09:33:12.353796
2790 09:33:12.354257 Set Vref, RX VrefLevel [Byte0]: 57
2791 09:33:12.357623 [Byte1]: 57
2792 09:33:12.361626
2793 09:33:12.362090 Set Vref, RX VrefLevel [Byte0]: 58
2794 09:33:12.365449 [Byte1]: 58
2795 09:33:12.370449
2796 09:33:12.371011 Set Vref, RX VrefLevel [Byte0]: 59
2797 09:33:12.372941 [Byte1]: 59
2798 09:33:12.377664
2799 09:33:12.378251 Set Vref, RX VrefLevel [Byte0]: 60
2800 09:33:12.381131 [Byte1]: 60
2801 09:33:12.385827
2802 09:33:12.386392 Set Vref, RX VrefLevel [Byte0]: 61
2803 09:33:12.389352 [Byte1]: 61
2804 09:33:12.393850
2805 09:33:12.394416 Set Vref, RX VrefLevel [Byte0]: 62
2806 09:33:12.396700 [Byte1]: 62
2807 09:33:12.401493
2808 09:33:12.402111 Set Vref, RX VrefLevel [Byte0]: 63
2809 09:33:12.404511 [Byte1]: 63
2810 09:33:12.409781
2811 09:33:12.410399 Set Vref, RX VrefLevel [Byte0]: 64
2812 09:33:12.413046 [Byte1]: 64
2813 09:33:12.417587
2814 09:33:12.418220 Set Vref, RX VrefLevel [Byte0]: 65
2815 09:33:12.420926 [Byte1]: 65
2816 09:33:12.425624
2817 09:33:12.426182 Set Vref, RX VrefLevel [Byte0]: 66
2818 09:33:12.428584 [Byte1]: 66
2819 09:33:12.433582
2820 09:33:12.434142 Set Vref, RX VrefLevel [Byte0]: 67
2821 09:33:12.436836 [Byte1]: 67
2822 09:33:12.441292
2823 09:33:12.441754 Set Vref, RX VrefLevel [Byte0]: 68
2824 09:33:12.444110 [Byte1]: 68
2825 09:33:12.449006
2826 09:33:12.452130 Set Vref, RX VrefLevel [Byte0]: 69
2827 09:33:12.455892 [Byte1]: 69
2828 09:33:12.456358
2829 09:33:12.458805 Set Vref, RX VrefLevel [Byte0]: 70
2830 09:33:12.462091 [Byte1]: 70
2831 09:33:12.462663
2832 09:33:12.465191 Set Vref, RX VrefLevel [Byte0]: 71
2833 09:33:12.468495 [Byte1]: 71
2834 09:33:12.472781
2835 09:33:12.473345 Set Vref, RX VrefLevel [Byte0]: 72
2836 09:33:12.476304 [Byte1]: 72
2837 09:33:12.481020
2838 09:33:12.481577 Set Vref, RX VrefLevel [Byte0]: 73
2839 09:33:12.483836 [Byte1]: 73
2840 09:33:12.488919
2841 09:33:12.489480 Set Vref, RX VrefLevel [Byte0]: 74
2842 09:33:12.491988 [Byte1]: 74
2843 09:33:12.496596
2844 09:33:12.497160 Set Vref, RX VrefLevel [Byte0]: 75
2845 09:33:12.499973 [Byte1]: 75
2846 09:33:12.504542
2847 09:33:12.505168 Set Vref, RX VrefLevel [Byte0]: 76
2848 09:33:12.507928 [Byte1]: 76
2849 09:33:12.512657
2850 09:33:12.513221 Set Vref, RX VrefLevel [Byte0]: 77
2851 09:33:12.515684 [Byte1]: 77
2852 09:33:12.520633
2853 09:33:12.521199 Final RX Vref Byte 0 = 59 to rank0
2854 09:33:12.523386 Final RX Vref Byte 1 = 58 to rank0
2855 09:33:12.527156 Final RX Vref Byte 0 = 59 to rank1
2856 09:33:12.530295 Final RX Vref Byte 1 = 58 to rank1==
2857 09:33:12.533701 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 09:33:12.540740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 09:33:12.541332 ==
2860 09:33:12.541704 DQS Delay:
2861 09:33:12.542047 DQS0 = 0, DQS1 = 0
2862 09:33:12.543477 DQM Delay:
2863 09:33:12.543971 DQM0 = 119, DQM1 = 107
2864 09:33:12.547112 DQ Delay:
2865 09:33:12.550291 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =116
2866 09:33:12.553268 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =128
2867 09:33:12.557275 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2868 09:33:12.559921 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2869 09:33:12.560388
2870 09:33:12.560753
2871 09:33:12.570047 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2872 09:33:12.570613 CH0 RK0: MR19=403, MR18=12FE
2873 09:33:12.576657 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2874 09:33:12.577220
2875 09:33:12.580535 ----->DramcWriteLeveling(PI) begin...
2876 09:33:12.581102 ==
2877 09:33:12.583471 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 09:33:12.589975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 09:33:12.590540 ==
2880 09:33:12.593516 Write leveling (Byte 0): 32 => 32
2881 09:33:12.594079 Write leveling (Byte 1): 29 => 29
2882 09:33:12.596685 DramcWriteLeveling(PI) end<-----
2883 09:33:12.597249
2884 09:33:12.600062 ==
2885 09:33:12.603386 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 09:33:12.606517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 09:33:12.607076 ==
2888 09:33:12.609892 [Gating] SW mode calibration
2889 09:33:12.616595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 09:33:12.619719 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 09:33:12.626449 0 15 0 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2892 09:33:12.629249 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2893 09:33:12.632876 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 09:33:12.639478 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 09:33:12.642942 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 09:33:12.646600 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 09:33:12.653406 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2898 09:33:12.656279 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2899 09:33:12.659589 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2900 09:33:12.666161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 09:33:12.669833 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 09:33:12.672680 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 09:33:12.679701 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 09:33:12.682917 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:33:12.686351 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:33:12.692325 1 0 28 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
2907 09:33:12.695947 1 1 0 | B1->B0 | 3736 4646 | 1 0 | (0 0) (0 0)
2908 09:33:12.699197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 09:33:12.703005 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 09:33:12.709284 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 09:33:12.712986 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 09:33:12.715919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:33:12.722368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:33:12.725825 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 09:33:12.728998 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2916 09:33:12.736077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 09:33:12.739051 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:33:12.742105 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:33:12.748871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:33:12.752192 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:33:12.755671 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:33:12.762099 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:33:12.765118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:33:12.768671 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:33:12.775102 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:33:12.778712 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:33:12.781694 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:33:12.788872 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:33:12.791811 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:33:12.795603 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 09:33:12.801520 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2932 09:33:12.805272 Total UI for P1: 0, mck2ui 16
2933 09:33:12.808268 best dqsien dly found for B0: ( 1, 3, 28)
2934 09:33:12.811452 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 09:33:12.814832 Total UI for P1: 0, mck2ui 16
2936 09:33:12.818025 best dqsien dly found for B1: ( 1, 4, 0)
2937 09:33:12.821342 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2938 09:33:12.824532 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2939 09:33:12.824987
2940 09:33:12.827945 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2941 09:33:12.831220 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2942 09:33:12.834816 [Gating] SW calibration Done
2943 09:33:12.835276 ==
2944 09:33:12.837759 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 09:33:12.844609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 09:33:12.845136 ==
2947 09:33:12.845509 RX Vref Scan: 0
2948 09:33:12.845847
2949 09:33:12.847785 RX Vref 0 -> 0, step: 1
2950 09:33:12.848243
2951 09:33:12.851087 RX Delay -40 -> 252, step: 8
2952 09:33:12.854871 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2953 09:33:12.858518 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2954 09:33:12.861576 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 09:33:12.864861 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2956 09:33:12.871915 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2957 09:33:12.874411 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2958 09:33:12.878141 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 09:33:12.881301 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 09:33:12.884432 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2961 09:33:12.891557 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2962 09:33:12.894761 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2963 09:33:12.897878 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2964 09:33:12.901137 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2965 09:33:12.907398 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2966 09:33:12.910913 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2967 09:33:12.914051 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2968 09:33:12.914516 ==
2969 09:33:12.917395 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 09:33:12.920695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 09:33:12.921162 ==
2972 09:33:12.924079 DQS Delay:
2973 09:33:12.924541 DQS0 = 0, DQS1 = 0
2974 09:33:12.927216 DQM Delay:
2975 09:33:12.927672 DQM0 = 117, DQM1 = 108
2976 09:33:12.928092 DQ Delay:
2977 09:33:12.933667 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2978 09:33:12.936864 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2979 09:33:12.940345 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2980 09:33:12.943528 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2981 09:33:12.944196
2982 09:33:12.944688
2983 09:33:12.945151 ==
2984 09:33:12.946803 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 09:33:12.949810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 09:33:12.950113 ==
2987 09:33:12.950385
2988 09:33:12.950646
2989 09:33:12.953484 TX Vref Scan disable
2990 09:33:12.956793 == TX Byte 0 ==
2991 09:33:12.960127 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2992 09:33:12.963045 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2993 09:33:12.966554 == TX Byte 1 ==
2994 09:33:12.969882 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2995 09:33:12.973048 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2996 09:33:12.973232 ==
2997 09:33:12.976505 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 09:33:12.979803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 09:33:12.983378 ==
3000 09:33:12.993469 TX Vref=22, minBit 1, minWin=25, winSum=421
3001 09:33:12.996929 TX Vref=24, minBit 13, minWin=25, winSum=422
3002 09:33:12.999958 TX Vref=26, minBit 1, minWin=26, winSum=429
3003 09:33:13.003339 TX Vref=28, minBit 4, minWin=26, winSum=433
3004 09:33:13.006811 TX Vref=30, minBit 13, minWin=26, winSum=434
3005 09:33:13.013533 TX Vref=32, minBit 8, minWin=26, winSum=434
3006 09:33:13.016594 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 30
3007 09:33:13.016750
3008 09:33:13.019996 Final TX Range 1 Vref 30
3009 09:33:13.020147
3010 09:33:13.020289 ==
3011 09:33:13.023057 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 09:33:13.026280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 09:33:13.029713 ==
3014 09:33:13.029838
3015 09:33:13.029949
3016 09:33:13.030056 TX Vref Scan disable
3017 09:33:13.033552 == TX Byte 0 ==
3018 09:33:13.036724 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3019 09:33:13.039948 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3020 09:33:13.043157 == TX Byte 1 ==
3021 09:33:13.046615 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3022 09:33:13.053427 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3023 09:33:13.053586
3024 09:33:13.053731 [DATLAT]
3025 09:33:13.053881 Freq=1200, CH0 RK1
3026 09:33:13.054018
3027 09:33:13.056682 DATLAT Default: 0xd
3028 09:33:13.056835 0, 0xFFFF, sum = 0
3029 09:33:13.060221 1, 0xFFFF, sum = 0
3030 09:33:13.060373 2, 0xFFFF, sum = 0
3031 09:33:13.063023 3, 0xFFFF, sum = 0
3032 09:33:13.063154 4, 0xFFFF, sum = 0
3033 09:33:13.066425 5, 0xFFFF, sum = 0
3034 09:33:13.069890 6, 0xFFFF, sum = 0
3035 09:33:13.070042 7, 0xFFFF, sum = 0
3036 09:33:13.073353 8, 0xFFFF, sum = 0
3037 09:33:13.073500 9, 0xFFFF, sum = 0
3038 09:33:13.076609 10, 0xFFFF, sum = 0
3039 09:33:13.076733 11, 0xFFFF, sum = 0
3040 09:33:13.080137 12, 0x0, sum = 1
3041 09:33:13.080260 13, 0x0, sum = 2
3042 09:33:13.083241 14, 0x0, sum = 3
3043 09:33:13.083389 15, 0x0, sum = 4
3044 09:33:13.083523 best_step = 13
3045 09:33:13.086365
3046 09:33:13.086479 ==
3047 09:33:13.089766 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 09:33:13.093322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 09:33:13.093439 ==
3050 09:33:13.093544 RX Vref Scan: 0
3051 09:33:13.093646
3052 09:33:13.096557 RX Vref 0 -> 0, step: 1
3053 09:33:13.096695
3054 09:33:13.099871 RX Delay -21 -> 252, step: 4
3055 09:33:13.103235 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3056 09:33:13.109540 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3057 09:33:13.113194 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3058 09:33:13.116295 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3059 09:33:13.119805 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3060 09:33:13.123307 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3061 09:33:13.130107 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3062 09:33:13.133474 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3063 09:33:13.136508 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3064 09:33:13.140116 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3065 09:33:13.143118 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3066 09:33:13.149869 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3067 09:33:13.153022 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3068 09:33:13.156394 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3069 09:33:13.159792 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3070 09:33:13.166670 iDelay=199, Bit 15, Center 118 (55 ~ 182) 128
3071 09:33:13.167190 ==
3072 09:33:13.169742 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 09:33:13.173195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 09:33:13.173709 ==
3075 09:33:13.174043 DQS Delay:
3076 09:33:13.176103 DQS0 = 0, DQS1 = 0
3077 09:33:13.176574 DQM Delay:
3078 09:33:13.179409 DQM0 = 116, DQM1 = 109
3079 09:33:13.179904 DQ Delay:
3080 09:33:13.182789 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3081 09:33:13.186105 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3082 09:33:13.189265 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =102
3083 09:33:13.193185 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =118
3084 09:33:13.193703
3085 09:33:13.194163
3086 09:33:13.203100 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 405 ps
3087 09:33:13.206649 CH0 RK1: MR19=403, MR18=BE5
3088 09:33:13.209273 CH0_RK1: MR19=0x403, MR18=0xBE5, DQSOSC=405, MR23=63, INC=39, DEC=26
3089 09:33:13.212936 [RxdqsGatingPostProcess] freq 1200
3090 09:33:13.219514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 09:33:13.223094 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 09:33:13.226052 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 09:33:13.229392 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 09:33:13.232524 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 09:33:13.236135 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 09:33:13.239688 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 09:33:13.242931 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 09:33:13.246385 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 09:33:13.246959 Pre-setting of DQS Precalculation
3100 09:33:13.252694 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 09:33:13.253254 ==
3102 09:33:13.255908 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 09:33:13.259324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 09:33:13.259821 ==
3105 09:33:13.266404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 09:33:13.272748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 09:33:13.280169 [CA 0] Center 38 (8~68) winsize 61
3108 09:33:13.282967 [CA 1] Center 37 (7~68) winsize 62
3109 09:33:13.286330 [CA 2] Center 34 (4~64) winsize 61
3110 09:33:13.290175 [CA 3] Center 33 (3~64) winsize 62
3111 09:33:13.292812 [CA 4] Center 34 (4~64) winsize 61
3112 09:33:13.296442 [CA 5] Center 33 (3~64) winsize 62
3113 09:33:13.296896
3114 09:33:13.299923 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3115 09:33:13.300380
3116 09:33:13.302929 [CATrainingPosCal] consider 1 rank data
3117 09:33:13.306096 u2DelayCellTimex100 = 270/100 ps
3118 09:33:13.309748 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3119 09:33:13.316067 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 09:33:13.320024 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 09:33:13.323052 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 09:33:13.326183 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 09:33:13.329798 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 09:33:13.330210
3125 09:33:13.332870 CA PerBit enable=1, Macro0, CA PI delay=33
3126 09:33:13.333375
3127 09:33:13.335858 [CBTSetCACLKResult] CA Dly = 33
3128 09:33:13.336326 CS Dly: 6 (0~37)
3129 09:33:13.339695 ==
3130 09:33:13.342924 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 09:33:13.346343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 09:33:13.346758 ==
3133 09:33:13.349367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 09:33:13.355818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3135 09:33:13.365557 [CA 0] Center 37 (7~68) winsize 62
3136 09:33:13.368831 [CA 1] Center 38 (8~68) winsize 61
3137 09:33:13.372152 [CA 2] Center 34 (4~65) winsize 62
3138 09:33:13.375419 [CA 3] Center 33 (3~64) winsize 62
3139 09:33:13.378681 [CA 4] Center 34 (4~65) winsize 62
3140 09:33:13.382148 [CA 5] Center 33 (3~64) winsize 62
3141 09:33:13.382664
3142 09:33:13.385454 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 09:33:13.385930
3144 09:33:13.389233 [CATrainingPosCal] consider 2 rank data
3145 09:33:13.392351 u2DelayCellTimex100 = 270/100 ps
3146 09:33:13.395711 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3147 09:33:13.398689 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 09:33:13.405772 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 09:33:13.408858 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 09:33:13.412720 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 09:33:13.415607 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 09:33:13.416248
3153 09:33:13.419028 CA PerBit enable=1, Macro0, CA PI delay=33
3154 09:33:13.419847
3155 09:33:13.422107 [CBTSetCACLKResult] CA Dly = 33
3156 09:33:13.422672 CS Dly: 7 (0~40)
3157 09:33:13.423042
3158 09:33:13.425239 ----->DramcWriteLeveling(PI) begin...
3159 09:33:13.429099 ==
3160 09:33:13.429586 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 09:33:13.435497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 09:33:13.436092 ==
3163 09:33:13.439013 Write leveling (Byte 0): 24 => 24
3164 09:33:13.442588 Write leveling (Byte 1): 26 => 26
3165 09:33:13.445443 DramcWriteLeveling(PI) end<-----
3166 09:33:13.446012
3167 09:33:13.446381 ==
3168 09:33:13.448872 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 09:33:13.452399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 09:33:13.452863 ==
3171 09:33:13.455558 [Gating] SW mode calibration
3172 09:33:13.461986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 09:33:13.468862 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 09:33:13.472459 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3175 09:33:13.475346 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 09:33:13.482003 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 09:33:13.485391 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 09:33:13.488472 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 09:33:13.491755 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 09:33:13.498730 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
3181 09:33:13.502337 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3182 09:33:13.505112 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 09:33:13.512309 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 09:33:13.515259 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 09:33:13.518662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 09:33:13.525419 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 09:33:13.528239 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:33:13.531472 1 0 24 | B1->B0 | 2a29 3e3e | 1 0 | (0 0) (0 0)
3189 09:33:13.538008 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3190 09:33:13.541546 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 09:33:13.545074 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 09:33:13.551547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 09:33:13.555109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 09:33:13.558256 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:33:13.565513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:33:13.567960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:33:13.571571 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 09:33:13.578212 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 09:33:13.581768 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:33:13.585158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:33:13.591845 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:33:13.594496 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:33:13.598029 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:33:13.604572 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:33:13.607548 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:33:13.611571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:33:13.617924 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:33:13.620773 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:33:13.624443 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:33:13.631044 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:33:13.634152 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:33:13.637754 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 09:33:13.644591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 09:33:13.647704 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 09:33:13.650739 Total UI for P1: 0, mck2ui 16
3216 09:33:13.654324 best dqsien dly found for B0: ( 1, 3, 26)
3217 09:33:13.657566 Total UI for P1: 0, mck2ui 16
3218 09:33:13.661426 best dqsien dly found for B1: ( 1, 3, 26)
3219 09:33:13.664258 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3220 09:33:13.668079 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3221 09:33:13.668639
3222 09:33:13.670948 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3223 09:33:13.674427 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3224 09:33:13.677466 [Gating] SW calibration Done
3225 09:33:13.678037 ==
3226 09:33:13.680676 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 09:33:13.684117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 09:33:13.684692 ==
3229 09:33:13.687899 RX Vref Scan: 0
3230 09:33:13.688458
3231 09:33:13.690877 RX Vref 0 -> 0, step: 1
3232 09:33:13.691436
3233 09:33:13.691857 RX Delay -40 -> 252, step: 8
3234 09:33:13.697343 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3235 09:33:13.700566 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3236 09:33:13.704108 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3237 09:33:13.706900 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3238 09:33:13.710538 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3239 09:33:13.717350 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3240 09:33:13.720805 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3241 09:33:13.723552 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3242 09:33:13.726953 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3243 09:33:13.730178 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3244 09:33:13.737162 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3245 09:33:13.740974 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3246 09:33:13.743529 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3247 09:33:13.747242 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3248 09:33:13.753337 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3249 09:33:13.756494 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3250 09:33:13.756960 ==
3251 09:33:13.759939 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 09:33:13.763699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 09:33:13.764313 ==
3254 09:33:13.764684 DQS Delay:
3255 09:33:13.766659 DQS0 = 0, DQS1 = 0
3256 09:33:13.767119 DQM Delay:
3257 09:33:13.770183 DQM0 = 118, DQM1 = 110
3258 09:33:13.770833 DQ Delay:
3259 09:33:13.773577 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3260 09:33:13.777030 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3261 09:33:13.779811 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3262 09:33:13.783547 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3263 09:33:13.786941
3264 09:33:13.787501
3265 09:33:13.787909 ==
3266 09:33:13.790491 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 09:33:13.793033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 09:33:13.793499 ==
3269 09:33:13.793865
3270 09:33:13.794205
3271 09:33:13.796644 TX Vref Scan disable
3272 09:33:13.797212 == TX Byte 0 ==
3273 09:33:13.804063 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3274 09:33:13.806457 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3275 09:33:13.806992 == TX Byte 1 ==
3276 09:33:13.813305 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3277 09:33:13.816455 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3278 09:33:13.816919 ==
3279 09:33:13.819791 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 09:33:13.823020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 09:33:13.823607 ==
3282 09:33:13.835267 TX Vref=22, minBit 9, minWin=25, winSum=418
3283 09:33:13.838833 TX Vref=24, minBit 10, minWin=25, winSum=427
3284 09:33:13.842325 TX Vref=26, minBit 10, minWin=26, winSum=433
3285 09:33:13.845127 TX Vref=28, minBit 8, minWin=26, winSum=436
3286 09:33:13.849249 TX Vref=30, minBit 11, minWin=26, winSum=434
3287 09:33:13.855447 TX Vref=32, minBit 9, minWin=26, winSum=429
3288 09:33:13.858349 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3289 09:33:13.858817
3290 09:33:13.861867 Final TX Range 1 Vref 28
3291 09:33:13.862334
3292 09:33:13.862696 ==
3293 09:33:13.865664 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 09:33:13.868197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 09:33:13.871607 ==
3296 09:33:13.872121
3297 09:33:13.872487
3298 09:33:13.872826 TX Vref Scan disable
3299 09:33:13.874985 == TX Byte 0 ==
3300 09:33:13.878279 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3301 09:33:13.885329 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3302 09:33:13.885748 == TX Byte 1 ==
3303 09:33:13.888629 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3304 09:33:13.895234 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3305 09:33:13.895652
3306 09:33:13.896038 [DATLAT]
3307 09:33:13.896355 Freq=1200, CH1 RK0
3308 09:33:13.896655
3309 09:33:13.898835 DATLAT Default: 0xd
3310 09:33:13.899354 0, 0xFFFF, sum = 0
3311 09:33:13.901778 1, 0xFFFF, sum = 0
3312 09:33:13.905471 2, 0xFFFF, sum = 0
3313 09:33:13.906001 3, 0xFFFF, sum = 0
3314 09:33:13.908375 4, 0xFFFF, sum = 0
3315 09:33:13.908798 5, 0xFFFF, sum = 0
3316 09:33:13.911790 6, 0xFFFF, sum = 0
3317 09:33:13.912323 7, 0xFFFF, sum = 0
3318 09:33:13.915268 8, 0xFFFF, sum = 0
3319 09:33:13.915693 9, 0xFFFF, sum = 0
3320 09:33:13.918344 10, 0xFFFF, sum = 0
3321 09:33:13.918769 11, 0xFFFF, sum = 0
3322 09:33:13.921487 12, 0x0, sum = 1
3323 09:33:13.921909 13, 0x0, sum = 2
3324 09:33:13.924726 14, 0x0, sum = 3
3325 09:33:13.925153 15, 0x0, sum = 4
3326 09:33:13.928112 best_step = 13
3327 09:33:13.928532
3328 09:33:13.928863 ==
3329 09:33:13.931633 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 09:33:13.934818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 09:33:13.935234 ==
3332 09:33:13.935564 RX Vref Scan: 1
3333 09:33:13.935950
3334 09:33:13.938248 Set Vref Range= 32 -> 127
3335 09:33:13.938665
3336 09:33:13.941895 RX Vref 32 -> 127, step: 1
3337 09:33:13.942420
3338 09:33:13.944857 RX Delay -21 -> 252, step: 4
3339 09:33:13.945277
3340 09:33:13.948120 Set Vref, RX VrefLevel [Byte0]: 32
3341 09:33:13.952490 [Byte1]: 32
3342 09:33:13.952906
3343 09:33:13.954679 Set Vref, RX VrefLevel [Byte0]: 33
3344 09:33:13.958580 [Byte1]: 33
3345 09:33:13.961835
3346 09:33:13.962353 Set Vref, RX VrefLevel [Byte0]: 34
3347 09:33:13.965374 [Byte1]: 34
3348 09:33:13.969747
3349 09:33:13.970267 Set Vref, RX VrefLevel [Byte0]: 35
3350 09:33:13.972737 [Byte1]: 35
3351 09:33:13.977707
3352 09:33:13.978119 Set Vref, RX VrefLevel [Byte0]: 36
3353 09:33:13.980741 [Byte1]: 36
3354 09:33:13.985611
3355 09:33:13.986041 Set Vref, RX VrefLevel [Byte0]: 37
3356 09:33:13.988927 [Byte1]: 37
3357 09:33:13.993313
3358 09:33:13.993732 Set Vref, RX VrefLevel [Byte0]: 38
3359 09:33:13.996909 [Byte1]: 38
3360 09:33:14.001309
3361 09:33:14.001731 Set Vref, RX VrefLevel [Byte0]: 39
3362 09:33:14.004330 [Byte1]: 39
3363 09:33:14.009576
3364 09:33:14.010117 Set Vref, RX VrefLevel [Byte0]: 40
3365 09:33:14.012514 [Byte1]: 40
3366 09:33:14.017656
3367 09:33:14.018173 Set Vref, RX VrefLevel [Byte0]: 41
3368 09:33:14.020669 [Byte1]: 41
3369 09:33:14.025494
3370 09:33:14.026012 Set Vref, RX VrefLevel [Byte0]: 42
3371 09:33:14.029034 [Byte1]: 42
3372 09:33:14.033295
3373 09:33:14.033716 Set Vref, RX VrefLevel [Byte0]: 43
3374 09:33:14.036214 [Byte1]: 43
3375 09:33:14.041199
3376 09:33:14.041719 Set Vref, RX VrefLevel [Byte0]: 44
3377 09:33:14.044149 [Byte1]: 44
3378 09:33:14.048827
3379 09:33:14.049348 Set Vref, RX VrefLevel [Byte0]: 45
3380 09:33:14.052220 [Byte1]: 45
3381 09:33:14.056764
3382 09:33:14.057280 Set Vref, RX VrefLevel [Byte0]: 46
3383 09:33:14.060336 [Byte1]: 46
3384 09:33:14.064907
3385 09:33:14.065325 Set Vref, RX VrefLevel [Byte0]: 47
3386 09:33:14.071388 [Byte1]: 47
3387 09:33:14.071963
3388 09:33:14.074405 Set Vref, RX VrefLevel [Byte0]: 48
3389 09:33:14.077948 [Byte1]: 48
3390 09:33:14.078369
3391 09:33:14.081121 Set Vref, RX VrefLevel [Byte0]: 49
3392 09:33:14.084546 [Byte1]: 49
3393 09:33:14.088777
3394 09:33:14.089195 Set Vref, RX VrefLevel [Byte0]: 50
3395 09:33:14.094807 [Byte1]: 50
3396 09:33:14.095283
3397 09:33:14.098135 Set Vref, RX VrefLevel [Byte0]: 51
3398 09:33:14.101301 [Byte1]: 51
3399 09:33:14.101883
3400 09:33:14.104673 Set Vref, RX VrefLevel [Byte0]: 52
3401 09:33:14.107899 [Byte1]: 52
3402 09:33:14.112035
3403 09:33:14.112450 Set Vref, RX VrefLevel [Byte0]: 53
3404 09:33:14.115686 [Byte1]: 53
3405 09:33:14.119853
3406 09:33:14.120271 Set Vref, RX VrefLevel [Byte0]: 54
3407 09:33:14.123649 [Byte1]: 54
3408 09:33:14.128469
3409 09:33:14.128986 Set Vref, RX VrefLevel [Byte0]: 55
3410 09:33:14.131940 [Byte1]: 55
3411 09:33:14.136204
3412 09:33:14.136764 Set Vref, RX VrefLevel [Byte0]: 56
3413 09:33:14.139646 [Byte1]: 56
3414 09:33:14.144039
3415 09:33:14.144601 Set Vref, RX VrefLevel [Byte0]: 57
3416 09:33:14.147040 [Byte1]: 57
3417 09:33:14.152079
3418 09:33:14.152639 Set Vref, RX VrefLevel [Byte0]: 58
3419 09:33:14.155470 [Byte1]: 58
3420 09:33:14.159699
3421 09:33:14.160316 Set Vref, RX VrefLevel [Byte0]: 59
3422 09:33:14.163381 [Byte1]: 59
3423 09:33:14.167981
3424 09:33:14.168537 Set Vref, RX VrefLevel [Byte0]: 60
3425 09:33:14.171143 [Byte1]: 60
3426 09:33:14.176013
3427 09:33:14.176596 Set Vref, RX VrefLevel [Byte0]: 61
3428 09:33:14.178762 [Byte1]: 61
3429 09:33:14.183658
3430 09:33:14.184259 Set Vref, RX VrefLevel [Byte0]: 62
3431 09:33:14.186933 [Byte1]: 62
3432 09:33:14.191377
3433 09:33:14.191929 Set Vref, RX VrefLevel [Byte0]: 63
3434 09:33:14.194961 [Byte1]: 63
3435 09:33:14.199397
3436 09:33:14.199992 Set Vref, RX VrefLevel [Byte0]: 64
3437 09:33:14.202800 [Byte1]: 64
3438 09:33:14.207495
3439 09:33:14.208222 Set Vref, RX VrefLevel [Byte0]: 65
3440 09:33:14.210945 [Byte1]: 65
3441 09:33:14.215526
3442 09:33:14.216128 Set Vref, RX VrefLevel [Byte0]: 66
3443 09:33:14.218537 [Byte1]: 66
3444 09:33:14.223083
3445 09:33:14.223645 Set Vref, RX VrefLevel [Byte0]: 67
3446 09:33:14.226798 [Byte1]: 67
3447 09:33:14.231135
3448 09:33:14.231698 Final RX Vref Byte 0 = 46 to rank0
3449 09:33:14.234331 Final RX Vref Byte 1 = 54 to rank0
3450 09:33:14.237601 Final RX Vref Byte 0 = 46 to rank1
3451 09:33:14.240675 Final RX Vref Byte 1 = 54 to rank1==
3452 09:33:14.244063 Dram Type= 6, Freq= 0, CH_1, rank 0
3453 09:33:14.251106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 09:33:14.251694 ==
3455 09:33:14.252183 DQS Delay:
3456 09:33:14.254574 DQS0 = 0, DQS1 = 0
3457 09:33:14.255149 DQM Delay:
3458 09:33:14.255512 DQM0 = 115, DQM1 = 110
3459 09:33:14.257601 DQ Delay:
3460 09:33:14.261152 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3461 09:33:14.264242 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3462 09:33:14.267226 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3463 09:33:14.270963 DQ12 =116, DQ13 =118, DQ14 =120, DQ15 =118
3464 09:33:14.271485
3465 09:33:14.271920
3466 09:33:14.280712 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3467 09:33:14.281216 CH1 RK0: MR19=403, MR18=4F8
3468 09:33:14.287163 CH1_RK0: MR19=0x403, MR18=0x4F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3469 09:33:14.287587
3470 09:33:14.290822 ----->DramcWriteLeveling(PI) begin...
3471 09:33:14.291355 ==
3472 09:33:14.294393 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 09:33:14.300702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 09:33:14.301262 ==
3475 09:33:14.303935 Write leveling (Byte 0): 25 => 25
3476 09:33:14.304454 Write leveling (Byte 1): 26 => 26
3477 09:33:14.307011 DramcWriteLeveling(PI) end<-----
3478 09:33:14.307434
3479 09:33:14.307994 ==
3480 09:33:14.310398 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 09:33:14.317013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 09:33:14.317546 ==
3483 09:33:14.320345 [Gating] SW mode calibration
3484 09:33:14.327609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3485 09:33:14.330321 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3486 09:33:14.336580 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3487 09:33:14.339889 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 09:33:14.343146 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 09:33:14.350060 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 09:33:14.353674 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 09:33:14.356995 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 09:33:14.363214 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
3493 09:33:14.366595 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3494 09:33:14.369830 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 09:33:14.376729 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 09:33:14.379919 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 09:33:14.383177 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 09:33:14.389197 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 09:33:14.392980 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 09:33:14.396073 1 0 24 | B1->B0 | 3a3a 2929 | 0 0 | (0 0) (0 0)
3501 09:33:14.402344 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3502 09:33:14.405716 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 09:33:14.408924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 09:33:14.415597 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 09:33:14.418952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 09:33:14.422368 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 09:33:14.429176 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 09:33:14.431817 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3509 09:33:14.435244 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3510 09:33:14.441676 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:33:14.445105 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:33:14.448889 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:33:14.455400 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:33:14.458118 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:33:14.461378 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:33:14.468269 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:33:14.471524 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:33:14.474727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 09:33:14.481320 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 09:33:14.484611 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 09:33:14.487834 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:33:14.494789 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 09:33:14.497950 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 09:33:14.501168 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3525 09:33:14.507610 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3526 09:33:14.511325 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 09:33:14.514547 Total UI for P1: 0, mck2ui 16
3528 09:33:14.517758 best dqsien dly found for B0: ( 1, 3, 28)
3529 09:33:14.520822 Total UI for P1: 0, mck2ui 16
3530 09:33:14.524438 best dqsien dly found for B1: ( 1, 3, 26)
3531 09:33:14.527961 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3532 09:33:14.530933 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3533 09:33:14.531356
3534 09:33:14.534402 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3535 09:33:14.537446 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3536 09:33:14.541161 [Gating] SW calibration Done
3537 09:33:14.541576 ==
3538 09:33:14.544583 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 09:33:14.547658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 09:33:14.550899 ==
3541 09:33:14.551480 RX Vref Scan: 0
3542 09:33:14.551881
3543 09:33:14.554141 RX Vref 0 -> 0, step: 1
3544 09:33:14.554562
3545 09:33:14.557195 RX Delay -40 -> 252, step: 8
3546 09:33:14.560825 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3547 09:33:14.564002 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3548 09:33:14.567808 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3549 09:33:14.571218 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3550 09:33:14.577583 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3551 09:33:14.580760 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3552 09:33:14.583778 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3553 09:33:14.587607 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3554 09:33:14.590687 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3555 09:33:14.597267 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3556 09:33:14.600719 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3557 09:33:14.603591 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3558 09:33:14.606802 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3559 09:33:14.613727 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3560 09:33:14.616889 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3561 09:33:14.620061 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3562 09:33:14.620624 ==
3563 09:33:14.623006 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 09:33:14.627111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 09:33:14.627637 ==
3566 09:33:14.629715 DQS Delay:
3567 09:33:14.630134 DQS0 = 0, DQS1 = 0
3568 09:33:14.633656 DQM Delay:
3569 09:33:14.634183 DQM0 = 117, DQM1 = 110
3570 09:33:14.636171 DQ Delay:
3571 09:33:14.639418 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3572 09:33:14.643544 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3573 09:33:14.646282 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3574 09:33:14.649340 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3575 09:33:14.649762
3576 09:33:14.650096
3577 09:33:14.650406 ==
3578 09:33:14.652484 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 09:33:14.656259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 09:33:14.656714 ==
3581 09:33:14.657246
3582 09:33:14.657587
3583 09:33:14.659467 TX Vref Scan disable
3584 09:33:14.663102 == TX Byte 0 ==
3585 09:33:14.665997 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3586 09:33:14.669793 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3587 09:33:14.672901 == TX Byte 1 ==
3588 09:33:14.676310 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3589 09:33:14.679292 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3590 09:33:14.679717 ==
3591 09:33:14.682902 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 09:33:14.689319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 09:33:14.689847 ==
3594 09:33:14.699888 TX Vref=22, minBit 3, minWin=26, winSum=423
3595 09:33:14.703233 TX Vref=24, minBit 9, minWin=26, winSum=429
3596 09:33:14.706622 TX Vref=26, minBit 8, minWin=26, winSum=430
3597 09:33:14.709664 TX Vref=28, minBit 9, minWin=26, winSum=432
3598 09:33:14.713024 TX Vref=30, minBit 9, minWin=26, winSum=434
3599 09:33:14.719674 TX Vref=32, minBit 9, minWin=26, winSum=433
3600 09:33:14.722699 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3601 09:33:14.723128
3602 09:33:14.726881 Final TX Range 1 Vref 30
3603 09:33:14.727438
3604 09:33:14.727830 ==
3605 09:33:14.729398 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 09:33:14.732442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 09:33:14.735782 ==
3608 09:33:14.736216
3609 09:33:14.736552
3610 09:33:14.736866 TX Vref Scan disable
3611 09:33:14.739100 == TX Byte 0 ==
3612 09:33:14.742822 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3613 09:33:14.749612 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3614 09:33:14.750143 == TX Byte 1 ==
3615 09:33:14.752552 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3616 09:33:14.759385 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3617 09:33:14.760080
3618 09:33:14.760432 [DATLAT]
3619 09:33:14.760751 Freq=1200, CH1 RK1
3620 09:33:14.761058
3621 09:33:14.762775 DATLAT Default: 0xd
3622 09:33:14.765903 0, 0xFFFF, sum = 0
3623 09:33:14.766330 1, 0xFFFF, sum = 0
3624 09:33:14.769292 2, 0xFFFF, sum = 0
3625 09:33:14.769827 3, 0xFFFF, sum = 0
3626 09:33:14.772600 4, 0xFFFF, sum = 0
3627 09:33:14.773192 5, 0xFFFF, sum = 0
3628 09:33:14.775624 6, 0xFFFF, sum = 0
3629 09:33:14.776124 7, 0xFFFF, sum = 0
3630 09:33:14.779060 8, 0xFFFF, sum = 0
3631 09:33:14.779594 9, 0xFFFF, sum = 0
3632 09:33:14.782629 10, 0xFFFF, sum = 0
3633 09:33:14.783203 11, 0xFFFF, sum = 0
3634 09:33:14.785299 12, 0x0, sum = 1
3635 09:33:14.785728 13, 0x0, sum = 2
3636 09:33:14.789758 14, 0x0, sum = 3
3637 09:33:14.790292 15, 0x0, sum = 4
3638 09:33:14.792444 best_step = 13
3639 09:33:14.792866
3640 09:33:14.793199 ==
3641 09:33:14.796006 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 09:33:14.798844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 09:33:14.799370 ==
3644 09:33:14.802037 RX Vref Scan: 0
3645 09:33:14.802560
3646 09:33:14.802902 RX Vref 0 -> 0, step: 1
3647 09:33:14.803218
3648 09:33:14.805437 RX Delay -21 -> 252, step: 4
3649 09:33:14.811943 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3650 09:33:14.815678 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3651 09:33:14.818815 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3652 09:33:14.822031 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3653 09:33:14.825216 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3654 09:33:14.831935 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3655 09:33:14.835065 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3656 09:33:14.838258 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3657 09:33:14.841842 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3658 09:33:14.845269 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3659 09:33:14.851517 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3660 09:33:14.854721 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3661 09:33:14.858304 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3662 09:33:14.861793 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3663 09:33:14.867965 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3664 09:33:14.871439 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3665 09:33:14.871899 ==
3666 09:33:14.874851 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 09:33:14.878277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 09:33:14.878865 ==
3669 09:33:14.879211 DQS Delay:
3670 09:33:14.881255 DQS0 = 0, DQS1 = 0
3671 09:33:14.881693 DQM Delay:
3672 09:33:14.884841 DQM0 = 116, DQM1 = 110
3673 09:33:14.885385 DQ Delay:
3674 09:33:14.887796 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3675 09:33:14.891336 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3676 09:33:14.894440 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3677 09:33:14.901154 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3678 09:33:14.901669
3679 09:33:14.902006
3680 09:33:14.907700 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
3681 09:33:14.910703 CH1 RK1: MR19=303, MR18=F4F0
3682 09:33:14.918082 CH1_RK1: MR19=0x303, MR18=0xF4F0, DQSOSC=415, MR23=63, INC=38, DEC=25
3683 09:33:14.920574 [RxdqsGatingPostProcess] freq 1200
3684 09:33:14.924125 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3685 09:33:14.927902 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 09:33:14.931069 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 09:33:14.934030 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 09:33:14.937346 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 09:33:14.940440 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 09:33:14.944072 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 09:33:14.947390 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 09:33:14.950483 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 09:33:14.953845 Pre-setting of DQS Precalculation
3694 09:33:14.957193 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3695 09:33:14.966991 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3696 09:33:14.973303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3697 09:33:14.973808
3698 09:33:14.974153
3699 09:33:14.976546 [Calibration Summary] 2400 Mbps
3700 09:33:14.977010 CH 0, Rank 0
3701 09:33:14.980382 SW Impedance : PASS
3702 09:33:14.983085 DUTY Scan : NO K
3703 09:33:14.983527 ZQ Calibration : PASS
3704 09:33:14.986797 Jitter Meter : NO K
3705 09:33:14.987378 CBT Training : PASS
3706 09:33:14.989706 Write leveling : PASS
3707 09:33:14.993644 RX DQS gating : PASS
3708 09:33:14.994219 RX DQ/DQS(RDDQC) : PASS
3709 09:33:14.996648 TX DQ/DQS : PASS
3710 09:33:14.999537 RX DATLAT : PASS
3711 09:33:15.000042 RX DQ/DQS(Engine): PASS
3712 09:33:15.003363 TX OE : NO K
3713 09:33:15.003982 All Pass.
3714 09:33:15.004355
3715 09:33:15.006363 CH 0, Rank 1
3716 09:33:15.006818 SW Impedance : PASS
3717 09:33:15.009790 DUTY Scan : NO K
3718 09:33:15.012864 ZQ Calibration : PASS
3719 09:33:15.013280 Jitter Meter : NO K
3720 09:33:15.016328 CBT Training : PASS
3721 09:33:15.019709 Write leveling : PASS
3722 09:33:15.020272 RX DQS gating : PASS
3723 09:33:15.022647 RX DQ/DQS(RDDQC) : PASS
3724 09:33:15.026266 TX DQ/DQS : PASS
3725 09:33:15.026781 RX DATLAT : PASS
3726 09:33:15.029376 RX DQ/DQS(Engine): PASS
3727 09:33:15.033072 TX OE : NO K
3728 09:33:15.033590 All Pass.
3729 09:33:15.033925
3730 09:33:15.034232 CH 1, Rank 0
3731 09:33:15.035660 SW Impedance : PASS
3732 09:33:15.038959 DUTY Scan : NO K
3733 09:33:15.039486 ZQ Calibration : PASS
3734 09:33:15.042444 Jitter Meter : NO K
3735 09:33:15.046166 CBT Training : PASS
3736 09:33:15.046576 Write leveling : PASS
3737 09:33:15.048887 RX DQS gating : PASS
3738 09:33:15.052548 RX DQ/DQS(RDDQC) : PASS
3739 09:33:15.052961 TX DQ/DQS : PASS
3740 09:33:15.055625 RX DATLAT : PASS
3741 09:33:15.059590 RX DQ/DQS(Engine): PASS
3742 09:33:15.060202 TX OE : NO K
3743 09:33:15.060590 All Pass.
3744 09:33:15.062427
3745 09:33:15.062976 CH 1, Rank 1
3746 09:33:15.065735 SW Impedance : PASS
3747 09:33:15.066147 DUTY Scan : NO K
3748 09:33:15.069095 ZQ Calibration : PASS
3749 09:33:15.069509 Jitter Meter : NO K
3750 09:33:15.072199 CBT Training : PASS
3751 09:33:15.075939 Write leveling : PASS
3752 09:33:15.076355 RX DQS gating : PASS
3753 09:33:15.079268 RX DQ/DQS(RDDQC) : PASS
3754 09:33:15.082513 TX DQ/DQS : PASS
3755 09:33:15.082926 RX DATLAT : PASS
3756 09:33:15.085698 RX DQ/DQS(Engine): PASS
3757 09:33:15.088687 TX OE : NO K
3758 09:33:15.089099 All Pass.
3759 09:33:15.089484
3760 09:33:15.092275 DramC Write-DBI off
3761 09:33:15.092687 PER_BANK_REFRESH: Hybrid Mode
3762 09:33:15.095708 TX_TRACKING: ON
3763 09:33:15.102234 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3764 09:33:15.108624 [FAST_K] Save calibration result to emmc
3765 09:33:15.112254 dramc_set_vcore_voltage set vcore to 650000
3766 09:33:15.112672 Read voltage for 600, 5
3767 09:33:15.115436 Vio18 = 0
3768 09:33:15.116003 Vcore = 650000
3769 09:33:15.116346 Vdram = 0
3770 09:33:15.118894 Vddq = 0
3771 09:33:15.119409 Vmddr = 0
3772 09:33:15.122189 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3773 09:33:15.128731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3774 09:33:15.131885 MEM_TYPE=3, freq_sel=19
3775 09:33:15.135808 sv_algorithm_assistance_LP4_1600
3776 09:33:15.138798 ============ PULL DRAM RESETB DOWN ============
3777 09:33:15.141753 ========== PULL DRAM RESETB DOWN end =========
3778 09:33:15.148248 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3779 09:33:15.151774 ===================================
3780 09:33:15.152294 LPDDR4 DRAM CONFIGURATION
3781 09:33:15.154960 ===================================
3782 09:33:15.158071 EX_ROW_EN[0] = 0x0
3783 09:33:15.161502 EX_ROW_EN[1] = 0x0
3784 09:33:15.162015 LP4Y_EN = 0x0
3785 09:33:15.165061 WORK_FSP = 0x0
3786 09:33:15.165597 WL = 0x2
3787 09:33:15.168478 RL = 0x2
3788 09:33:15.168993 BL = 0x2
3789 09:33:15.171525 RPST = 0x0
3790 09:33:15.172083 RD_PRE = 0x0
3791 09:33:15.174615 WR_PRE = 0x1
3792 09:33:15.175025 WR_PST = 0x0
3793 09:33:15.177943 DBI_WR = 0x0
3794 09:33:15.178462 DBI_RD = 0x0
3795 09:33:15.181305 OTF = 0x1
3796 09:33:15.184655 ===================================
3797 09:33:15.188126 ===================================
3798 09:33:15.188644 ANA top config
3799 09:33:15.190883 ===================================
3800 09:33:15.194447 DLL_ASYNC_EN = 0
3801 09:33:15.197424 ALL_SLAVE_EN = 1
3802 09:33:15.201115 NEW_RANK_MODE = 1
3803 09:33:15.201637 DLL_IDLE_MODE = 1
3804 09:33:15.204146 LP45_APHY_COMB_EN = 1
3805 09:33:15.207418 TX_ODT_DIS = 1
3806 09:33:15.210562 NEW_8X_MODE = 1
3807 09:33:15.214588 ===================================
3808 09:33:15.217761 ===================================
3809 09:33:15.220698 data_rate = 1200
3810 09:33:15.221111 CKR = 1
3811 09:33:15.224112 DQ_P2S_RATIO = 8
3812 09:33:15.227151 ===================================
3813 09:33:15.230841 CA_P2S_RATIO = 8
3814 09:33:15.233411 DQ_CA_OPEN = 0
3815 09:33:15.237716 DQ_SEMI_OPEN = 0
3816 09:33:15.240577 CA_SEMI_OPEN = 0
3817 09:33:15.240992 CA_FULL_RATE = 0
3818 09:33:15.243647 DQ_CKDIV4_EN = 1
3819 09:33:15.247209 CA_CKDIV4_EN = 1
3820 09:33:15.250396 CA_PREDIV_EN = 0
3821 09:33:15.253843 PH8_DLY = 0
3822 09:33:15.256597 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3823 09:33:15.260391 DQ_AAMCK_DIV = 4
3824 09:33:15.260939 CA_AAMCK_DIV = 4
3825 09:33:15.263540 CA_ADMCK_DIV = 4
3826 09:33:15.267267 DQ_TRACK_CA_EN = 0
3827 09:33:15.270644 CA_PICK = 600
3828 09:33:15.273866 CA_MCKIO = 600
3829 09:33:15.276429 MCKIO_SEMI = 0
3830 09:33:15.279622 PLL_FREQ = 2288
3831 09:33:15.280097 DQ_UI_PI_RATIO = 32
3832 09:33:15.283777 CA_UI_PI_RATIO = 0
3833 09:33:15.287081 ===================================
3834 09:33:15.290033 ===================================
3835 09:33:15.292633 memory_type:LPDDR4
3836 09:33:15.295956 GP_NUM : 10
3837 09:33:15.296396 SRAM_EN : 1
3838 09:33:15.299846 MD32_EN : 0
3839 09:33:15.303004 ===================================
3840 09:33:15.306170 [ANA_INIT] >>>>>>>>>>>>>>
3841 09:33:15.309248 <<<<<< [CONFIGURE PHASE]: ANA_TX
3842 09:33:15.312431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3843 09:33:15.315797 ===================================
3844 09:33:15.316310 data_rate = 1200,PCW = 0X5800
3845 09:33:15.319336 ===================================
3846 09:33:15.322004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3847 09:33:15.328827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 09:33:15.335208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 09:33:15.338763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3850 09:33:15.341822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3851 09:33:15.345121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3852 09:33:15.348529 [ANA_INIT] flow start
3853 09:33:15.351767 [ANA_INIT] PLL >>>>>>>>
3854 09:33:15.352188 [ANA_INIT] PLL <<<<<<<<
3855 09:33:15.355374 [ANA_INIT] MIDPI >>>>>>>>
3856 09:33:15.358874 [ANA_INIT] MIDPI <<<<<<<<
3857 09:33:15.359391 [ANA_INIT] DLL >>>>>>>>
3858 09:33:15.362107 [ANA_INIT] flow end
3859 09:33:15.365225 ============ LP4 DIFF to SE enter ============
3860 09:33:15.371798 ============ LP4 DIFF to SE exit ============
3861 09:33:15.372319 [ANA_INIT] <<<<<<<<<<<<<
3862 09:33:15.375417 [Flow] Enable top DCM control >>>>>
3863 09:33:15.379157 [Flow] Enable top DCM control <<<<<
3864 09:33:15.382128 Enable DLL master slave shuffle
3865 09:33:15.388696 ==============================================================
3866 09:33:15.389217 Gating Mode config
3867 09:33:15.395193 ==============================================================
3868 09:33:15.398202 Config description:
3869 09:33:15.408104 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3870 09:33:15.414877 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3871 09:33:15.417941 SELPH_MODE 0: By rank 1: By Phase
3872 09:33:15.424288 ==============================================================
3873 09:33:15.427893 GAT_TRACK_EN = 1
3874 09:33:15.431027 RX_GATING_MODE = 2
3875 09:33:15.431574 RX_GATING_TRACK_MODE = 2
3876 09:33:15.434124 SELPH_MODE = 1
3877 09:33:15.437581 PICG_EARLY_EN = 1
3878 09:33:15.441268 VALID_LAT_VALUE = 1
3879 09:33:15.447530 ==============================================================
3880 09:33:15.451141 Enter into Gating configuration >>>>
3881 09:33:15.453983 Exit from Gating configuration <<<<
3882 09:33:15.457427 Enter into DVFS_PRE_config >>>>>
3883 09:33:15.466906 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3884 09:33:15.470735 Exit from DVFS_PRE_config <<<<<
3885 09:33:15.473665 Enter into PICG configuration >>>>
3886 09:33:15.477191 Exit from PICG configuration <<<<
3887 09:33:15.480203 [RX_INPUT] configuration >>>>>
3888 09:33:15.483529 [RX_INPUT] configuration <<<<<
3889 09:33:15.486874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3890 09:33:15.493490 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3891 09:33:15.500063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 09:33:15.506505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 09:33:15.513087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 09:33:15.516798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 09:33:15.522894 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3896 09:33:15.526244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3897 09:33:15.530560 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3898 09:33:15.533522 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3899 09:33:15.539647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3900 09:33:15.542734 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 09:33:15.546439 ===================================
3902 09:33:15.549838 LPDDR4 DRAM CONFIGURATION
3903 09:33:15.552654 ===================================
3904 09:33:15.553077 EX_ROW_EN[0] = 0x0
3905 09:33:15.556016 EX_ROW_EN[1] = 0x0
3906 09:33:15.556438 LP4Y_EN = 0x0
3907 09:33:15.559555 WORK_FSP = 0x0
3908 09:33:15.560059 WL = 0x2
3909 09:33:15.562877 RL = 0x2
3910 09:33:15.563401 BL = 0x2
3911 09:33:15.566325 RPST = 0x0
3912 09:33:15.566843 RD_PRE = 0x0
3913 09:33:15.569640 WR_PRE = 0x1
3914 09:33:15.572955 WR_PST = 0x0
3915 09:33:15.573477 DBI_WR = 0x0
3916 09:33:15.575857 DBI_RD = 0x0
3917 09:33:15.576298 OTF = 0x1
3918 09:33:15.579238 ===================================
3919 09:33:15.582426 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3920 09:33:15.589300 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3921 09:33:15.592761 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 09:33:15.596534 ===================================
3923 09:33:15.599363 LPDDR4 DRAM CONFIGURATION
3924 09:33:15.602676 ===================================
3925 09:33:15.603199 EX_ROW_EN[0] = 0x10
3926 09:33:15.606132 EX_ROW_EN[1] = 0x0
3927 09:33:15.606657 LP4Y_EN = 0x0
3928 09:33:15.609193 WORK_FSP = 0x0
3929 09:33:15.609619 WL = 0x2
3930 09:33:15.612339 RL = 0x2
3931 09:33:15.612764 BL = 0x2
3932 09:33:15.616296 RPST = 0x0
3933 09:33:15.619566 RD_PRE = 0x0
3934 09:33:15.620149 WR_PRE = 0x1
3935 09:33:15.622586 WR_PST = 0x0
3936 09:33:15.623102 DBI_WR = 0x0
3937 09:33:15.625541 DBI_RD = 0x0
3938 09:33:15.626062 OTF = 0x1
3939 09:33:15.629091 ===================================
3940 09:33:15.635421 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3941 09:33:15.639074 nWR fixed to 30
3942 09:33:15.642834 [ModeRegInit_LP4] CH0 RK0
3943 09:33:15.643257 [ModeRegInit_LP4] CH0 RK1
3944 09:33:15.646076 [ModeRegInit_LP4] CH1 RK0
3945 09:33:15.649094 [ModeRegInit_LP4] CH1 RK1
3946 09:33:15.649518 match AC timing 17
3947 09:33:15.655781 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3948 09:33:15.659398 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3949 09:33:15.662105 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3950 09:33:15.669235 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3951 09:33:15.672338 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3952 09:33:15.672906 ==
3953 09:33:15.675521 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 09:33:15.679110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 09:33:15.679621 ==
3956 09:33:15.685518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 09:33:15.691966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 09:33:15.695397 [CA 0] Center 36 (6~66) winsize 61
3959 09:33:15.698529 [CA 1] Center 36 (6~66) winsize 61
3960 09:33:15.702125 [CA 2] Center 34 (4~65) winsize 62
3961 09:33:15.705250 [CA 3] Center 34 (4~64) winsize 61
3962 09:33:15.708608 [CA 4] Center 33 (3~64) winsize 62
3963 09:33:15.711974 [CA 5] Center 34 (4~64) winsize 61
3964 09:33:15.712438
3965 09:33:15.715634 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 09:33:15.716249
3967 09:33:15.718418 [CATrainingPosCal] consider 1 rank data
3968 09:33:15.721887 u2DelayCellTimex100 = 270/100 ps
3969 09:33:15.724915 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 09:33:15.728147 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3971 09:33:15.731809 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 09:33:15.738304 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3973 09:33:15.741299 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 09:33:15.745342 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
3975 09:33:15.745909
3976 09:33:15.748210 CA PerBit enable=1, Macro0, CA PI delay=33
3977 09:33:15.748667
3978 09:33:15.751441 [CBTSetCACLKResult] CA Dly = 33
3979 09:33:15.751957 CS Dly: 5 (0~36)
3980 09:33:15.752322 ==
3981 09:33:15.755104 Dram Type= 6, Freq= 0, CH_0, rank 1
3982 09:33:15.761603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 09:33:15.762170 ==
3984 09:33:15.764247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 09:33:15.771056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3986 09:33:15.774680 [CA 0] Center 36 (6~66) winsize 61
3987 09:33:15.778732 [CA 1] Center 36 (6~66) winsize 61
3988 09:33:15.781269 [CA 2] Center 33 (3~64) winsize 62
3989 09:33:15.785076 [CA 3] Center 33 (3~64) winsize 62
3990 09:33:15.788085 [CA 4] Center 33 (2~64) winsize 63
3991 09:33:15.791812 [CA 5] Center 33 (2~64) winsize 63
3992 09:33:15.792379
3993 09:33:15.794739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3994 09:33:15.795297
3995 09:33:15.798596 [CATrainingPosCal] consider 2 rank data
3996 09:33:15.801808 u2DelayCellTimex100 = 270/100 ps
3997 09:33:15.804463 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3998 09:33:15.811265 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3999 09:33:15.814717 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4000 09:33:15.817482 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4001 09:33:15.820900 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 09:33:15.824525 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4003 09:33:15.824993
4004 09:33:15.828309 CA PerBit enable=1, Macro0, CA PI delay=33
4005 09:33:15.828877
4006 09:33:15.830644 [CBTSetCACLKResult] CA Dly = 33
4007 09:33:15.834205 CS Dly: 5 (0~37)
4008 09:33:15.834791
4009 09:33:15.837768 ----->DramcWriteLeveling(PI) begin...
4010 09:33:15.838337 ==
4011 09:33:15.840883 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 09:33:15.843798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 09:33:15.844269 ==
4014 09:33:15.847266 Write leveling (Byte 0): 36 => 36
4015 09:33:15.850504 Write leveling (Byte 1): 28 => 28
4016 09:33:15.853872 DramcWriteLeveling(PI) end<-----
4017 09:33:15.854294
4018 09:33:15.854625 ==
4019 09:33:15.857078 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 09:33:15.860191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 09:33:15.860637 ==
4022 09:33:15.863810 [Gating] SW mode calibration
4023 09:33:15.870457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4024 09:33:15.877186 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4025 09:33:15.880262 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 09:33:15.883799 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 09:33:15.890092 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 09:33:15.893321 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4029 09:33:15.896632 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 1) (1 0)
4030 09:33:15.903295 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 09:33:15.906565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 09:33:15.909881 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 09:33:15.916268 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 09:33:15.919638 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 09:33:15.922671 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 09:33:15.929356 0 10 12 | B1->B0 | 2423 2828 | 1 0 | (0 0) (0 0)
4037 09:33:15.932556 0 10 16 | B1->B0 | 3636 3b3b | 0 0 | (1 1) (0 0)
4038 09:33:15.935928 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 09:33:15.942575 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 09:33:15.946011 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 09:33:15.948878 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 09:33:15.955567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 09:33:15.958816 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 09:33:15.962142 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 09:33:15.968986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4046 09:33:15.972401 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:33:15.975301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:33:15.981970 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:33:15.985270 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:33:15.988625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:33:15.995227 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:33:15.998917 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:33:16.002005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:33:16.008521 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:33:16.011690 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:33:16.014788 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:33:16.021807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:33:16.024879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:33:16.028452 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:33:16.034921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:33:16.039644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 09:33:16.041588 Total UI for P1: 0, mck2ui 16
4063 09:33:16.046444 best dqsien dly found for B0: ( 0, 13, 14)
4064 09:33:16.048337 Total UI for P1: 0, mck2ui 16
4065 09:33:16.051889 best dqsien dly found for B1: ( 0, 13, 14)
4066 09:33:16.055224 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4067 09:33:16.058711 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4068 09:33:16.059228
4069 09:33:16.062283 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4070 09:33:16.065466 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4071 09:33:16.068437 [Gating] SW calibration Done
4072 09:33:16.068902 ==
4073 09:33:16.071466 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 09:33:16.078308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 09:33:16.078885 ==
4076 09:33:16.079219 RX Vref Scan: 0
4077 09:33:16.079529
4078 09:33:16.082039 RX Vref 0 -> 0, step: 1
4079 09:33:16.082710
4080 09:33:16.084841 RX Delay -230 -> 252, step: 16
4081 09:33:16.088311 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4082 09:33:16.091184 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4083 09:33:16.094581 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4084 09:33:16.101815 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4085 09:33:16.104478 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4086 09:33:16.108014 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4087 09:33:16.111035 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4088 09:33:16.118335 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4089 09:33:16.121167 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4090 09:33:16.124552 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4091 09:33:16.127880 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4092 09:33:16.134492 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4093 09:33:16.137985 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4094 09:33:16.140898 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4095 09:33:16.144205 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4096 09:33:16.151308 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4097 09:33:16.151770 ==
4098 09:33:16.154145 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 09:33:16.157494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 09:33:16.157918 ==
4101 09:33:16.158254 DQS Delay:
4102 09:33:16.160417 DQS0 = 0, DQS1 = 0
4103 09:33:16.160840 DQM Delay:
4104 09:33:16.163805 DQM0 = 43, DQM1 = 30
4105 09:33:16.164227 DQ Delay:
4106 09:33:16.167318 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4107 09:33:16.170681 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4108 09:33:16.173871 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4109 09:33:16.177211 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4110 09:33:16.177633
4111 09:33:16.177969
4112 09:33:16.178278 ==
4113 09:33:16.180439 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 09:33:16.184041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 09:33:16.184465 ==
4116 09:33:16.184800
4117 09:33:16.187297
4118 09:33:16.187715 TX Vref Scan disable
4119 09:33:16.191209 == TX Byte 0 ==
4120 09:33:16.193650 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4121 09:33:16.197029 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4122 09:33:16.200643 == TX Byte 1 ==
4123 09:33:16.203794 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4124 09:33:16.207191 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4125 09:33:16.210257 ==
4126 09:33:16.210773 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 09:33:16.216701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 09:33:16.217219 ==
4129 09:33:16.217555
4130 09:33:16.217863
4131 09:33:16.220047 TX Vref Scan disable
4132 09:33:16.223566 == TX Byte 0 ==
4133 09:33:16.226442 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4134 09:33:16.229616 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4135 09:33:16.232894 == TX Byte 1 ==
4136 09:33:16.236181 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4137 09:33:16.239824 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4138 09:33:16.240262
4139 09:33:16.240701 [DATLAT]
4140 09:33:16.243412 Freq=600, CH0 RK0
4141 09:33:16.243892
4142 09:33:16.246370 DATLAT Default: 0x9
4143 09:33:16.246789 0, 0xFFFF, sum = 0
4144 09:33:16.249699 1, 0xFFFF, sum = 0
4145 09:33:16.250130 2, 0xFFFF, sum = 0
4146 09:33:16.252734 3, 0xFFFF, sum = 0
4147 09:33:16.253175 4, 0xFFFF, sum = 0
4148 09:33:16.256447 5, 0xFFFF, sum = 0
4149 09:33:16.256876 6, 0xFFFF, sum = 0
4150 09:33:16.259832 7, 0xFFFF, sum = 0
4151 09:33:16.260264 8, 0x0, sum = 1
4152 09:33:16.262777 9, 0x0, sum = 2
4153 09:33:16.263219 10, 0x0, sum = 3
4154 09:33:16.266060 11, 0x0, sum = 4
4155 09:33:16.266608 best_step = 9
4156 09:33:16.267058
4157 09:33:16.267480 ==
4158 09:33:16.269667 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 09:33:16.272383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 09:33:16.272819 ==
4161 09:33:16.275939 RX Vref Scan: 1
4162 09:33:16.276372
4163 09:33:16.279634 RX Vref 0 -> 0, step: 1
4164 09:33:16.280239
4165 09:33:16.280700 RX Delay -195 -> 252, step: 8
4166 09:33:16.281121
4167 09:33:16.282466 Set Vref, RX VrefLevel [Byte0]: 59
4168 09:33:16.286265 [Byte1]: 58
4169 09:33:16.290632
4170 09:33:16.291172 Final RX Vref Byte 0 = 59 to rank0
4171 09:33:16.293924 Final RX Vref Byte 1 = 58 to rank0
4172 09:33:16.297038 Final RX Vref Byte 0 = 59 to rank1
4173 09:33:16.300533 Final RX Vref Byte 1 = 58 to rank1==
4174 09:33:16.304065 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 09:33:16.310315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 09:33:16.310756 ==
4177 09:33:16.311199 DQS Delay:
4178 09:33:16.313633 DQS0 = 0, DQS1 = 0
4179 09:33:16.314068 DQM Delay:
4180 09:33:16.314516 DQM0 = 43, DQM1 = 32
4181 09:33:16.316948 DQ Delay:
4182 09:33:16.320395 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4183 09:33:16.323287 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4184 09:33:16.326755 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4185 09:33:16.330284 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4186 09:33:16.330753
4187 09:33:16.331202
4188 09:33:16.337067 [DQSOSCAuto] RK0, (LSB)MR18= 0x663d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4189 09:33:16.339996 CH0 RK0: MR19=808, MR18=663D
4190 09:33:16.346655 CH0_RK0: MR19=0x808, MR18=0x663D, DQSOSC=390, MR23=63, INC=172, DEC=114
4191 09:33:16.347096
4192 09:33:16.350117 ----->DramcWriteLeveling(PI) begin...
4193 09:33:16.350563 ==
4194 09:33:16.353501 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 09:33:16.356759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 09:33:16.357201 ==
4197 09:33:16.359809 Write leveling (Byte 0): 32 => 32
4198 09:33:16.363083 Write leveling (Byte 1): 31 => 31
4199 09:33:16.366314 DramcWriteLeveling(PI) end<-----
4200 09:33:16.366746
4201 09:33:16.367189 ==
4202 09:33:16.369783 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 09:33:16.373340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 09:33:16.376446 ==
4205 09:33:16.376879 [Gating] SW mode calibration
4206 09:33:16.386010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4207 09:33:16.389250 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4208 09:33:16.392351 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 09:33:16.399818 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 09:33:16.402708 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 09:33:16.406020 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4212 09:33:16.412322 0 9 16 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (1 0)
4213 09:33:16.415814 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 09:33:16.418942 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 09:33:16.425595 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 09:33:16.429221 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 09:33:16.432343 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 09:33:16.439341 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 09:33:16.441956 0 10 12 | B1->B0 | 2424 2a2a | 0 0 | (1 1) (0 0)
4220 09:33:16.445508 0 10 16 | B1->B0 | 3c3c 4343 | 1 0 | (0 0) (0 0)
4221 09:33:16.452108 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 09:33:16.455207 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 09:33:16.458588 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 09:33:16.465313 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 09:33:16.468739 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 09:33:16.474865 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 09:33:16.478241 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4228 09:33:16.481878 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4229 09:33:16.488717 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:33:16.491714 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:33:16.494660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:33:16.501402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:33:16.504518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:33:16.507890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:33:16.514130 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:33:16.517354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:33:16.521019 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:33:16.527447 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:33:16.530989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:33:16.534146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:33:16.540779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:33:16.543835 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4243 09:33:16.547271 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4244 09:33:16.554339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4245 09:33:16.557449 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 09:33:16.560507 Total UI for P1: 0, mck2ui 16
4247 09:33:16.563785 best dqsien dly found for B0: ( 0, 13, 12)
4248 09:33:16.567082 Total UI for P1: 0, mck2ui 16
4249 09:33:16.570364 best dqsien dly found for B1: ( 0, 13, 14)
4250 09:33:16.574102 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4251 09:33:16.577064 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4252 09:33:16.577484
4253 09:33:16.580279 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4254 09:33:16.583962 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4255 09:33:16.586934 [Gating] SW calibration Done
4256 09:33:16.587354 ==
4257 09:33:16.590068 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 09:33:16.593984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 09:33:16.597282 ==
4260 09:33:16.597808 RX Vref Scan: 0
4261 09:33:16.598147
4262 09:33:16.600036 RX Vref 0 -> 0, step: 1
4263 09:33:16.600662
4264 09:33:16.603318 RX Delay -230 -> 252, step: 16
4265 09:33:16.606725 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4266 09:33:16.610185 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4267 09:33:16.613182 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4268 09:33:16.619662 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4269 09:33:16.623097 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4270 09:33:16.626211 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4271 09:33:16.629841 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4272 09:33:16.632780 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4273 09:33:16.639879 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4274 09:33:16.643010 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4275 09:33:16.645757 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4276 09:33:16.649284 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4277 09:33:16.655789 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4278 09:33:16.659418 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4279 09:33:16.662363 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4280 09:33:16.666175 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4281 09:33:16.669360 ==
4282 09:33:16.672711 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 09:33:16.676539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 09:33:16.677066 ==
4285 09:33:16.677403 DQS Delay:
4286 09:33:16.679197 DQS0 = 0, DQS1 = 0
4287 09:33:16.679616 DQM Delay:
4288 09:33:16.682881 DQM0 = 41, DQM1 = 35
4289 09:33:16.683406 DQ Delay:
4290 09:33:16.685680 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4291 09:33:16.689439 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4292 09:33:16.692519 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4293 09:33:16.695397 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4294 09:33:16.695959
4295 09:33:16.696426
4296 09:33:16.696872 ==
4297 09:33:16.699027 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 09:33:16.701953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 09:33:16.702373 ==
4300 09:33:16.702702
4301 09:33:16.703008
4302 09:33:16.705586 TX Vref Scan disable
4303 09:33:16.708946 == TX Byte 0 ==
4304 09:33:16.711796 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4305 09:33:16.715372 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4306 09:33:16.718917 == TX Byte 1 ==
4307 09:33:16.722616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4308 09:33:16.725731 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4309 09:33:16.726253 ==
4310 09:33:16.728884 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 09:33:16.735868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 09:33:16.736398 ==
4313 09:33:16.736734
4314 09:33:16.737040
4315 09:33:16.737332 TX Vref Scan disable
4316 09:33:16.739826 == TX Byte 0 ==
4317 09:33:16.743230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4318 09:33:16.749952 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4319 09:33:16.750380 == TX Byte 1 ==
4320 09:33:16.753308 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4321 09:33:16.759658 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4322 09:33:16.760105
4323 09:33:16.760435 [DATLAT]
4324 09:33:16.760744 Freq=600, CH0 RK1
4325 09:33:16.761046
4326 09:33:16.763410 DATLAT Default: 0x9
4327 09:33:16.763922 0, 0xFFFF, sum = 0
4328 09:33:16.766719 1, 0xFFFF, sum = 0
4329 09:33:16.769551 2, 0xFFFF, sum = 0
4330 09:33:16.770078 3, 0xFFFF, sum = 0
4331 09:33:16.773121 4, 0xFFFF, sum = 0
4332 09:33:16.773648 5, 0xFFFF, sum = 0
4333 09:33:16.776213 6, 0xFFFF, sum = 0
4334 09:33:16.776633 7, 0xFFFF, sum = 0
4335 09:33:16.779433 8, 0x0, sum = 1
4336 09:33:16.779928 9, 0x0, sum = 2
4337 09:33:16.780461 10, 0x0, sum = 3
4338 09:33:16.782730 11, 0x0, sum = 4
4339 09:33:16.783152 best_step = 9
4340 09:33:16.783480
4341 09:33:16.783834 ==
4342 09:33:16.786307 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 09:33:16.792691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 09:33:16.793214 ==
4345 09:33:16.793546 RX Vref Scan: 0
4346 09:33:16.793851
4347 09:33:16.795972 RX Vref 0 -> 0, step: 1
4348 09:33:16.796478
4349 09:33:16.799889 RX Delay -179 -> 252, step: 8
4350 09:33:16.802886 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4351 09:33:16.809234 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4352 09:33:16.812637 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4353 09:33:16.816094 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4354 09:33:16.819690 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4355 09:33:16.825803 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4356 09:33:16.829312 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4357 09:33:16.832083 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4358 09:33:16.835650 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4359 09:33:16.841727 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4360 09:33:16.845324 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4361 09:33:16.848899 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4362 09:33:16.852168 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4363 09:33:16.858677 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4364 09:33:16.861919 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4365 09:33:16.865092 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4366 09:33:16.865551 ==
4367 09:33:16.868543 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 09:33:16.872726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 09:33:16.875005 ==
4370 09:33:16.875465 DQS Delay:
4371 09:33:16.875882 DQS0 = 0, DQS1 = 0
4372 09:33:16.878650 DQM Delay:
4373 09:33:16.879269 DQM0 = 41, DQM1 = 36
4374 09:33:16.881325 DQ Delay:
4375 09:33:16.881860 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4376 09:33:16.884984 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4377 09:33:16.888112 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4378 09:33:16.891311 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4379 09:33:16.891783
4380 09:33:16.894756
4381 09:33:16.901629 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c0f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4382 09:33:16.904792 CH0 RK1: MR19=808, MR18=5C0F
4383 09:33:16.911822 CH0_RK1: MR19=0x808, MR18=0x5C0F, DQSOSC=392, MR23=63, INC=170, DEC=113
4384 09:33:16.914668 [RxdqsGatingPostProcess] freq 600
4385 09:33:16.919158 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4386 09:33:16.921265 Pre-setting of DQS Precalculation
4387 09:33:16.927760 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4388 09:33:16.928259 ==
4389 09:33:16.931224 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 09:33:16.934314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 09:33:16.934779 ==
4392 09:33:16.941309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 09:33:16.944377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4394 09:33:16.948715 [CA 0] Center 35 (5~66) winsize 62
4395 09:33:16.952311 [CA 1] Center 36 (6~66) winsize 61
4396 09:33:16.955674 [CA 2] Center 34 (4~65) winsize 62
4397 09:33:16.958936 [CA 3] Center 33 (3~64) winsize 62
4398 09:33:16.962133 [CA 4] Center 34 (4~64) winsize 61
4399 09:33:16.965268 [CA 5] Center 33 (3~64) winsize 62
4400 09:33:16.965733
4401 09:33:16.968332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4402 09:33:16.968847
4403 09:33:16.971534 [CATrainingPosCal] consider 1 rank data
4404 09:33:16.975593 u2DelayCellTimex100 = 270/100 ps
4405 09:33:16.978689 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 09:33:16.984757 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 09:33:16.988094 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 09:33:16.991612 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 09:33:16.995567 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4410 09:33:16.998184 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 09:33:16.998757
4412 09:33:17.001498 CA PerBit enable=1, Macro0, CA PI delay=33
4413 09:33:17.002095
4414 09:33:17.005093 [CBTSetCACLKResult] CA Dly = 33
4415 09:33:17.008364 CS Dly: 5 (0~36)
4416 09:33:17.008921 ==
4417 09:33:17.011301 Dram Type= 6, Freq= 0, CH_1, rank 1
4418 09:33:17.014824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 09:33:17.015381 ==
4420 09:33:17.021585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 09:33:17.024629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4422 09:33:17.029471 [CA 0] Center 35 (5~66) winsize 62
4423 09:33:17.032429 [CA 1] Center 36 (6~66) winsize 61
4424 09:33:17.035684 [CA 2] Center 34 (4~65) winsize 62
4425 09:33:17.038733 [CA 3] Center 34 (3~65) winsize 63
4426 09:33:17.041920 [CA 4] Center 34 (3~65) winsize 63
4427 09:33:17.045450 [CA 5] Center 34 (3~65) winsize 63
4428 09:33:17.045969
4429 09:33:17.048640 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4430 09:33:17.049078
4431 09:33:17.052116 [CATrainingPosCal] consider 2 rank data
4432 09:33:17.055121 u2DelayCellTimex100 = 270/100 ps
4433 09:33:17.058345 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 09:33:17.065233 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4435 09:33:17.068496 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 09:33:17.071905 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 09:33:17.075160 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4438 09:33:17.078283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 09:33:17.078812
4440 09:33:17.081775 CA PerBit enable=1, Macro0, CA PI delay=33
4441 09:33:17.082306
4442 09:33:17.084680 [CBTSetCACLKResult] CA Dly = 33
4443 09:33:17.088320 CS Dly: 5 (0~36)
4444 09:33:17.088828
4445 09:33:17.091617 ----->DramcWriteLeveling(PI) begin...
4446 09:33:17.092125 ==
4447 09:33:17.094715 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 09:33:17.098239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 09:33:17.098786 ==
4450 09:33:17.101203 Write leveling (Byte 0): 27 => 27
4451 09:33:17.104499 Write leveling (Byte 1): 29 => 29
4452 09:33:17.107940 DramcWriteLeveling(PI) end<-----
4453 09:33:17.108357
4454 09:33:17.108687 ==
4455 09:33:17.111256 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 09:33:17.114312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 09:33:17.114733 ==
4458 09:33:17.118209 [Gating] SW mode calibration
4459 09:33:17.124453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4460 09:33:17.131343 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4461 09:33:17.134284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 09:33:17.138166 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 09:33:17.144582 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 09:33:17.147646 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4465 09:33:17.150659 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 09:33:17.157013 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 09:33:17.160730 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 09:33:17.164300 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 09:33:17.170949 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 09:33:17.174335 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 09:33:17.177957 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 09:33:17.184118 0 10 12 | B1->B0 | 3434 3939 | 1 0 | (0 0) (0 0)
4473 09:33:17.187467 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 09:33:17.190838 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:33:17.196987 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 09:33:17.200191 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 09:33:17.203643 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 09:33:17.210245 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 09:33:17.213473 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 09:33:17.216724 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4481 09:33:17.223761 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:33:17.227111 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:33:17.230152 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:33:17.236655 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:33:17.239842 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:33:17.243202 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:33:17.249694 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:33:17.252910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:33:17.256325 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:33:17.262947 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:33:17.266037 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:33:17.270183 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:33:17.276639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:33:17.280147 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:33:17.282939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:33:17.289928 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4497 09:33:17.290482 Total UI for P1: 0, mck2ui 16
4498 09:33:17.296359 best dqsien dly found for B0: ( 0, 13, 10)
4499 09:33:17.299539 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 09:33:17.302692 Total UI for P1: 0, mck2ui 16
4501 09:33:17.306122 best dqsien dly found for B1: ( 0, 13, 12)
4502 09:33:17.309245 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4503 09:33:17.312575 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4504 09:33:17.312997
4505 09:33:17.315826 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4506 09:33:17.319507 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4507 09:33:17.323089 [Gating] SW calibration Done
4508 09:33:17.323597 ==
4509 09:33:17.325654 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 09:33:17.332235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 09:33:17.332650 ==
4512 09:33:17.333036 RX Vref Scan: 0
4513 09:33:17.333346
4514 09:33:17.336029 RX Vref 0 -> 0, step: 1
4515 09:33:17.336442
4516 09:33:17.339354 RX Delay -230 -> 252, step: 16
4517 09:33:17.342346 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4518 09:33:17.345792 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4519 09:33:17.348807 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4520 09:33:17.355684 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4521 09:33:17.358545 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4522 09:33:17.361878 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4523 09:33:17.365467 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4524 09:33:17.372065 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4525 09:33:17.375171 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4526 09:33:17.378800 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4527 09:33:17.382147 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 09:33:17.388608 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4529 09:33:17.391864 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4530 09:33:17.395390 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4531 09:33:17.398612 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4532 09:33:17.405410 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4533 09:33:17.405929 ==
4534 09:33:17.407980 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 09:33:17.411769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 09:33:17.412188 ==
4537 09:33:17.412514 DQS Delay:
4538 09:33:17.414814 DQS0 = 0, DQS1 = 0
4539 09:33:17.415223 DQM Delay:
4540 09:33:17.418335 DQM0 = 46, DQM1 = 38
4541 09:33:17.418854 DQ Delay:
4542 09:33:17.421298 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4543 09:33:17.424860 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4544 09:33:17.428000 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4545 09:33:17.431015 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4546 09:33:17.431439
4547 09:33:17.431794
4548 09:33:17.432105 ==
4549 09:33:17.434349 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 09:33:17.437632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 09:33:17.440918 ==
4552 09:33:17.441470
4553 09:33:17.441815
4554 09:33:17.442121 TX Vref Scan disable
4555 09:33:17.444069 == TX Byte 0 ==
4556 09:33:17.447599 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4557 09:33:17.451068 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4558 09:33:17.454465 == TX Byte 1 ==
4559 09:33:17.457721 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4560 09:33:17.461063 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4561 09:33:17.463999 ==
4562 09:33:17.467145 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 09:33:17.470983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 09:33:17.471497 ==
4565 09:33:17.471879
4566 09:33:17.472195
4567 09:33:17.474278 TX Vref Scan disable
4568 09:33:17.477177 == TX Byte 0 ==
4569 09:33:17.480596 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4570 09:33:17.483517 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4571 09:33:17.487143 == TX Byte 1 ==
4572 09:33:17.490426 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4573 09:33:17.493838 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4574 09:33:17.494364
4575 09:33:17.494694 [DATLAT]
4576 09:33:17.497326 Freq=600, CH1 RK0
4577 09:33:17.497742
4578 09:33:17.500103 DATLAT Default: 0x9
4579 09:33:17.500514 0, 0xFFFF, sum = 0
4580 09:33:17.503859 1, 0xFFFF, sum = 0
4581 09:33:17.504375 2, 0xFFFF, sum = 0
4582 09:33:17.506901 3, 0xFFFF, sum = 0
4583 09:33:17.507318 4, 0xFFFF, sum = 0
4584 09:33:17.510430 5, 0xFFFF, sum = 0
4585 09:33:17.510957 6, 0xFFFF, sum = 0
4586 09:33:17.513455 7, 0xFFFF, sum = 0
4587 09:33:17.513914 8, 0x0, sum = 1
4588 09:33:17.517171 9, 0x0, sum = 2
4589 09:33:17.517687 10, 0x0, sum = 3
4590 09:33:17.519707 11, 0x0, sum = 4
4591 09:33:17.520173 best_step = 9
4592 09:33:17.520501
4593 09:33:17.520803 ==
4594 09:33:17.523139 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 09:33:17.526587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 09:33:17.527003 ==
4597 09:33:17.529693 RX Vref Scan: 1
4598 09:33:17.530103
4599 09:33:17.533696 RX Vref 0 -> 0, step: 1
4600 09:33:17.534209
4601 09:33:17.534538 RX Delay -195 -> 252, step: 8
4602 09:33:17.534843
4603 09:33:17.537054 Set Vref, RX VrefLevel [Byte0]: 46
4604 09:33:17.540442 [Byte1]: 54
4605 09:33:17.544480
4606 09:33:17.544996 Final RX Vref Byte 0 = 46 to rank0
4607 09:33:17.547972 Final RX Vref Byte 1 = 54 to rank0
4608 09:33:17.550883 Final RX Vref Byte 0 = 46 to rank1
4609 09:33:17.554647 Final RX Vref Byte 1 = 54 to rank1==
4610 09:33:17.557600 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 09:33:17.564141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 09:33:17.564559 ==
4613 09:33:17.564888 DQS Delay:
4614 09:33:17.567678 DQS0 = 0, DQS1 = 0
4615 09:33:17.568235 DQM Delay:
4616 09:33:17.568566 DQM0 = 46, DQM1 = 36
4617 09:33:17.570964 DQ Delay:
4618 09:33:17.574344 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4619 09:33:17.578172 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4620 09:33:17.580764 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4621 09:33:17.584014 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =48
4622 09:33:17.584530
4623 09:33:17.584859
4624 09:33:17.591032 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4625 09:33:17.594259 CH1 RK0: MR19=808, MR18=4A2F
4626 09:33:17.600163 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4627 09:33:17.600663
4628 09:33:17.603520 ----->DramcWriteLeveling(PI) begin...
4629 09:33:17.603975 ==
4630 09:33:17.606930 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 09:33:17.610344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 09:33:17.610860 ==
4633 09:33:17.614068 Write leveling (Byte 0): 29 => 29
4634 09:33:17.617485 Write leveling (Byte 1): 29 => 29
4635 09:33:17.620097 DramcWriteLeveling(PI) end<-----
4636 09:33:17.620508
4637 09:33:17.620836 ==
4638 09:33:17.623800 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 09:33:17.627567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 09:33:17.630655 ==
4641 09:33:17.631171 [Gating] SW mode calibration
4642 09:33:17.639985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4643 09:33:17.643216 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4644 09:33:17.647120 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 09:33:17.653911 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 09:33:17.657111 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 09:33:17.660132 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4648 09:33:17.666718 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4649 09:33:17.670316 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 09:33:17.672892 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 09:33:17.679482 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 09:33:17.683031 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 09:33:17.686070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 09:33:17.693761 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 09:33:17.696249 0 10 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4656 09:33:17.700192 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4657 09:33:17.705845 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 09:33:17.709909 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 09:33:17.713075 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 09:33:17.719356 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 09:33:17.722946 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 09:33:17.725742 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 09:33:17.732589 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4664 09:33:17.735851 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4665 09:33:17.739816 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:33:17.745823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:33:17.749115 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:33:17.752421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:33:17.759229 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:33:17.762332 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:33:17.765620 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:33:17.772217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:33:17.775287 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:33:17.778419 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 09:33:17.785054 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:33:17.788250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:33:17.791806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:33:17.798426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 09:33:17.801439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 09:33:17.804536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 09:33:17.808055 Total UI for P1: 0, mck2ui 16
4682 09:33:17.811003 best dqsien dly found for B0: ( 0, 13, 14)
4683 09:33:17.814177 Total UI for P1: 0, mck2ui 16
4684 09:33:17.817909 best dqsien dly found for B1: ( 0, 13, 14)
4685 09:33:17.821782 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4686 09:33:17.827962 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4687 09:33:17.828542
4688 09:33:17.831225 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4689 09:33:17.834868 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4690 09:33:17.837452 [Gating] SW calibration Done
4691 09:33:17.837865 ==
4692 09:33:17.840940 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 09:33:17.844409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 09:33:17.844939 ==
4695 09:33:17.847881 RX Vref Scan: 0
4696 09:33:17.848436
4697 09:33:17.848877 RX Vref 0 -> 0, step: 1
4698 09:33:17.849284
4699 09:33:17.850731 RX Delay -230 -> 252, step: 16
4700 09:33:17.857033 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4701 09:33:17.860366 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4702 09:33:17.863494 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4703 09:33:17.867175 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4704 09:33:17.871009 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4705 09:33:17.877011 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4706 09:33:17.880217 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4707 09:33:17.883883 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4708 09:33:17.886827 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4709 09:33:17.893485 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4710 09:33:17.896580 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4711 09:33:17.900130 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4712 09:33:17.903387 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4713 09:33:17.910084 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4714 09:33:17.913201 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4715 09:33:17.917035 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4716 09:33:17.917635 ==
4717 09:33:17.920171 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 09:33:17.922983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 09:33:17.923429 ==
4720 09:33:17.926719 DQS Delay:
4721 09:33:17.927202 DQS0 = 0, DQS1 = 0
4722 09:33:17.929574 DQM Delay:
4723 09:33:17.930190 DQM0 = 42, DQM1 = 37
4724 09:33:17.933328 DQ Delay:
4725 09:33:17.934009 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4726 09:33:17.936223 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4727 09:33:17.939550 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4728 09:33:17.943062 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4729 09:33:17.943489
4730 09:33:17.946261
4731 09:33:17.946798 ==
4732 09:33:17.949468 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 09:33:17.953157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 09:33:17.953574 ==
4735 09:33:17.953903
4736 09:33:17.954208
4737 09:33:17.956380 TX Vref Scan disable
4738 09:33:17.956791 == TX Byte 0 ==
4739 09:33:17.962719 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4740 09:33:17.966367 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4741 09:33:17.966783 == TX Byte 1 ==
4742 09:33:17.972594 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4743 09:33:17.976280 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4744 09:33:17.976690 ==
4745 09:33:17.979130 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 09:33:17.982990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 09:33:17.983510 ==
4748 09:33:17.983892
4749 09:33:17.984207
4750 09:33:17.986219 TX Vref Scan disable
4751 09:33:17.989494 == TX Byte 0 ==
4752 09:33:17.992684 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 09:33:17.996583 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 09:33:17.999686 == TX Byte 1 ==
4755 09:33:18.002665 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4756 09:33:18.006423 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4757 09:33:18.009236
4758 09:33:18.009894 [DATLAT]
4759 09:33:18.010237 Freq=600, CH1 RK1
4760 09:33:18.010549
4761 09:33:18.012553 DATLAT Default: 0x9
4762 09:33:18.012960 0, 0xFFFF, sum = 0
4763 09:33:18.015794 1, 0xFFFF, sum = 0
4764 09:33:18.016216 2, 0xFFFF, sum = 0
4765 09:33:18.018981 3, 0xFFFF, sum = 0
4766 09:33:18.019402 4, 0xFFFF, sum = 0
4767 09:33:18.022493 5, 0xFFFF, sum = 0
4768 09:33:18.026254 6, 0xFFFF, sum = 0
4769 09:33:18.026771 7, 0xFFFF, sum = 0
4770 09:33:18.027107 8, 0x0, sum = 1
4771 09:33:18.029161 9, 0x0, sum = 2
4772 09:33:18.029580 10, 0x0, sum = 3
4773 09:33:18.032451 11, 0x0, sum = 4
4774 09:33:18.032867 best_step = 9
4775 09:33:18.033191
4776 09:33:18.033493 ==
4777 09:33:18.035712 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 09:33:18.042192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 09:33:18.042708 ==
4780 09:33:18.043037 RX Vref Scan: 0
4781 09:33:18.043344
4782 09:33:18.045214 RX Vref 0 -> 0, step: 1
4783 09:33:18.045624
4784 09:33:18.048834 RX Delay -195 -> 252, step: 8
4785 09:33:18.052171 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4786 09:33:18.058602 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4787 09:33:18.061606 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4788 09:33:18.065194 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4789 09:33:18.068440 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4790 09:33:18.075374 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4791 09:33:18.078896 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4792 09:33:18.081594 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4793 09:33:18.084986 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4794 09:33:18.088025 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4795 09:33:18.094540 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4796 09:33:18.098029 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4797 09:33:18.101374 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4798 09:33:18.104727 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4799 09:33:18.111299 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4800 09:33:18.114691 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4801 09:33:18.115129 ==
4802 09:33:18.118003 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 09:33:18.121433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 09:33:18.122035 ==
4805 09:33:18.124524 DQS Delay:
4806 09:33:18.124937 DQS0 = 0, DQS1 = 0
4807 09:33:18.127965 DQM Delay:
4808 09:33:18.128374 DQM0 = 45, DQM1 = 36
4809 09:33:18.128702 DQ Delay:
4810 09:33:18.131371 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4811 09:33:18.134744 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4812 09:33:18.137804 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4813 09:33:18.141577 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4814 09:33:18.142090
4815 09:33:18.142431
4816 09:33:18.151520 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4817 09:33:18.154468 CH1 RK1: MR19=808, MR18=2D21
4818 09:33:18.161171 CH1_RK1: MR19=0x808, MR18=0x2D21, DQSOSC=401, MR23=63, INC=163, DEC=108
4819 09:33:18.161587 [RxdqsGatingPostProcess] freq 600
4820 09:33:18.167527 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 09:33:18.171079 Pre-setting of DQS Precalculation
4822 09:33:18.174541 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 09:33:18.184126 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 09:33:18.190950 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 09:33:18.191494
4826 09:33:18.192055
4827 09:33:18.194119 [Calibration Summary] 1200 Mbps
4828 09:33:18.194571 CH 0, Rank 0
4829 09:33:18.197735 SW Impedance : PASS
4830 09:33:18.198148 DUTY Scan : NO K
4831 09:33:18.200559 ZQ Calibration : PASS
4832 09:33:18.203777 Jitter Meter : NO K
4833 09:33:18.204192 CBT Training : PASS
4834 09:33:18.207514 Write leveling : PASS
4835 09:33:18.210584 RX DQS gating : PASS
4836 09:33:18.210998 RX DQ/DQS(RDDQC) : PASS
4837 09:33:18.213689 TX DQ/DQS : PASS
4838 09:33:18.216789 RX DATLAT : PASS
4839 09:33:18.217202 RX DQ/DQS(Engine): PASS
4840 09:33:18.220403 TX OE : NO K
4841 09:33:18.220933 All Pass.
4842 09:33:18.221268
4843 09:33:18.224117 CH 0, Rank 1
4844 09:33:18.224630 SW Impedance : PASS
4845 09:33:18.227296 DUTY Scan : NO K
4846 09:33:18.230052 ZQ Calibration : PASS
4847 09:33:18.230481 Jitter Meter : NO K
4848 09:33:18.233562 CBT Training : PASS
4849 09:33:18.236992 Write leveling : PASS
4850 09:33:18.237403 RX DQS gating : PASS
4851 09:33:18.240543 RX DQ/DQS(RDDQC) : PASS
4852 09:33:18.243970 TX DQ/DQS : PASS
4853 09:33:18.244385 RX DATLAT : PASS
4854 09:33:18.246578 RX DQ/DQS(Engine): PASS
4855 09:33:18.250370 TX OE : NO K
4856 09:33:18.250881 All Pass.
4857 09:33:18.251267
4858 09:33:18.251579 CH 1, Rank 0
4859 09:33:18.253666 SW Impedance : PASS
4860 09:33:18.256607 DUTY Scan : NO K
4861 09:33:18.257023 ZQ Calibration : PASS
4862 09:33:18.259802 Jitter Meter : NO K
4863 09:33:18.260215 CBT Training : PASS
4864 09:33:18.263783 Write leveling : PASS
4865 09:33:18.266929 RX DQS gating : PASS
4866 09:33:18.267441 RX DQ/DQS(RDDQC) : PASS
4867 09:33:18.270057 TX DQ/DQS : PASS
4868 09:33:18.273193 RX DATLAT : PASS
4869 09:33:18.273706 RX DQ/DQS(Engine): PASS
4870 09:33:18.276283 TX OE : NO K
4871 09:33:18.276698 All Pass.
4872 09:33:18.277024
4873 09:33:18.279412 CH 1, Rank 1
4874 09:33:18.279851 SW Impedance : PASS
4875 09:33:18.283450 DUTY Scan : NO K
4876 09:33:18.286298 ZQ Calibration : PASS
4877 09:33:18.286809 Jitter Meter : NO K
4878 09:33:18.290250 CBT Training : PASS
4879 09:33:18.292790 Write leveling : PASS
4880 09:33:18.293206 RX DQS gating : PASS
4881 09:33:18.296084 RX DQ/DQS(RDDQC) : PASS
4882 09:33:18.299787 TX DQ/DQS : PASS
4883 09:33:18.300228 RX DATLAT : PASS
4884 09:33:18.303107 RX DQ/DQS(Engine): PASS
4885 09:33:18.306532 TX OE : NO K
4886 09:33:18.307057 All Pass.
4887 09:33:18.307392
4888 09:33:18.307699 DramC Write-DBI off
4889 09:33:18.309811 PER_BANK_REFRESH: Hybrid Mode
4890 09:33:18.313115 TX_TRACKING: ON
4891 09:33:18.319558 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 09:33:18.322992 [FAST_K] Save calibration result to emmc
4893 09:33:18.329571 dramc_set_vcore_voltage set vcore to 662500
4894 09:33:18.330030 Read voltage for 933, 3
4895 09:33:18.332937 Vio18 = 0
4896 09:33:18.333347 Vcore = 662500
4897 09:33:18.333673 Vdram = 0
4898 09:33:18.336219 Vddq = 0
4899 09:33:18.336629 Vmddr = 0
4900 09:33:18.339204 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 09:33:18.345937 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 09:33:18.349444 MEM_TYPE=3, freq_sel=17
4903 09:33:18.352398 sv_algorithm_assistance_LP4_1600
4904 09:33:18.356084 ============ PULL DRAM RESETB DOWN ============
4905 09:33:18.359658 ========== PULL DRAM RESETB DOWN end =========
4906 09:33:18.365697 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 09:33:18.368907 ===================================
4908 09:33:18.369370 LPDDR4 DRAM CONFIGURATION
4909 09:33:18.372475 ===================================
4910 09:33:18.375824 EX_ROW_EN[0] = 0x0
4911 09:33:18.376390 EX_ROW_EN[1] = 0x0
4912 09:33:18.379556 LP4Y_EN = 0x0
4913 09:33:18.380181 WORK_FSP = 0x0
4914 09:33:18.382209 WL = 0x3
4915 09:33:18.382774 RL = 0x3
4916 09:33:18.385285 BL = 0x2
4917 09:33:18.389346 RPST = 0x0
4918 09:33:18.389910 RD_PRE = 0x0
4919 09:33:18.392282 WR_PRE = 0x1
4920 09:33:18.392738 WR_PST = 0x0
4921 09:33:18.395540 DBI_WR = 0x0
4922 09:33:18.396129 DBI_RD = 0x0
4923 09:33:18.398557 OTF = 0x1
4924 09:33:18.402016 ===================================
4925 09:33:18.405170 ===================================
4926 09:33:18.405589 ANA top config
4927 09:33:18.408545 ===================================
4928 09:33:18.412225 DLL_ASYNC_EN = 0
4929 09:33:18.415316 ALL_SLAVE_EN = 1
4930 09:33:18.415930 NEW_RANK_MODE = 1
4931 09:33:18.418412 DLL_IDLE_MODE = 1
4932 09:33:18.421764 LP45_APHY_COMB_EN = 1
4933 09:33:18.425476 TX_ODT_DIS = 1
4934 09:33:18.428734 NEW_8X_MODE = 1
4935 09:33:18.431883 ===================================
4936 09:33:18.435423 ===================================
4937 09:33:18.435994 data_rate = 1866
4938 09:33:18.438393 CKR = 1
4939 09:33:18.441848 DQ_P2S_RATIO = 8
4940 09:33:18.445002 ===================================
4941 09:33:18.448212 CA_P2S_RATIO = 8
4942 09:33:18.451632 DQ_CA_OPEN = 0
4943 09:33:18.454840 DQ_SEMI_OPEN = 0
4944 09:33:18.455410 CA_SEMI_OPEN = 0
4945 09:33:18.457887 CA_FULL_RATE = 0
4946 09:33:18.461292 DQ_CKDIV4_EN = 1
4947 09:33:18.464438 CA_CKDIV4_EN = 1
4948 09:33:18.468055 CA_PREDIV_EN = 0
4949 09:33:18.471611 PH8_DLY = 0
4950 09:33:18.472258 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 09:33:18.474964 DQ_AAMCK_DIV = 4
4952 09:33:18.477822 CA_AAMCK_DIV = 4
4953 09:33:18.481347 CA_ADMCK_DIV = 4
4954 09:33:18.484147 DQ_TRACK_CA_EN = 0
4955 09:33:18.487689 CA_PICK = 933
4956 09:33:18.491310 CA_MCKIO = 933
4957 09:33:18.491930 MCKIO_SEMI = 0
4958 09:33:18.494057 PLL_FREQ = 3732
4959 09:33:18.497696 DQ_UI_PI_RATIO = 32
4960 09:33:18.501268 CA_UI_PI_RATIO = 0
4961 09:33:18.504137 ===================================
4962 09:33:18.507709 ===================================
4963 09:33:18.511037 memory_type:LPDDR4
4964 09:33:18.511592 GP_NUM : 10
4965 09:33:18.513772 SRAM_EN : 1
4966 09:33:18.517273 MD32_EN : 0
4967 09:33:18.520819 ===================================
4968 09:33:18.521334 [ANA_INIT] >>>>>>>>>>>>>>
4969 09:33:18.523754 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 09:33:18.527260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 09:33:18.530601 ===================================
4972 09:33:18.534081 data_rate = 1866,PCW = 0X8f00
4973 09:33:18.536981 ===================================
4974 09:33:18.540594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 09:33:18.546867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 09:33:18.554298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 09:33:18.557080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 09:33:18.560138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 09:33:18.563519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 09:33:18.566745 [ANA_INIT] flow start
4981 09:33:18.567260 [ANA_INIT] PLL >>>>>>>>
4982 09:33:18.569815 [ANA_INIT] PLL <<<<<<<<
4983 09:33:18.573297 [ANA_INIT] MIDPI >>>>>>>>
4984 09:33:18.573724 [ANA_INIT] MIDPI <<<<<<<<
4985 09:33:18.576706 [ANA_INIT] DLL >>>>>>>>
4986 09:33:18.579893 [ANA_INIT] flow end
4987 09:33:18.583482 ============ LP4 DIFF to SE enter ============
4988 09:33:18.586771 ============ LP4 DIFF to SE exit ============
4989 09:33:18.589709 [ANA_INIT] <<<<<<<<<<<<<
4990 09:33:18.592998 [Flow] Enable top DCM control >>>>>
4991 09:33:18.596246 [Flow] Enable top DCM control <<<<<
4992 09:33:18.599619 Enable DLL master slave shuffle
4993 09:33:18.603095 ==============================================================
4994 09:33:18.606436 Gating Mode config
4995 09:33:18.613214 ==============================================================
4996 09:33:18.613744 Config description:
4997 09:33:18.623359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 09:33:18.628990 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 09:33:18.636000 SELPH_MODE 0: By rank 1: By Phase
5000 09:33:18.639568 ==============================================================
5001 09:33:18.642854 GAT_TRACK_EN = 1
5002 09:33:18.645882 RX_GATING_MODE = 2
5003 09:33:18.648742 RX_GATING_TRACK_MODE = 2
5004 09:33:18.652204 SELPH_MODE = 1
5005 09:33:18.655604 PICG_EARLY_EN = 1
5006 09:33:18.659405 VALID_LAT_VALUE = 1
5007 09:33:18.665621 ==============================================================
5008 09:33:18.668902 Enter into Gating configuration >>>>
5009 09:33:18.671786 Exit from Gating configuration <<<<
5010 09:33:18.675441 Enter into DVFS_PRE_config >>>>>
5011 09:33:18.685192 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 09:33:18.688671 Exit from DVFS_PRE_config <<<<<
5013 09:33:18.691780 Enter into PICG configuration >>>>
5014 09:33:18.695398 Exit from PICG configuration <<<<
5015 09:33:18.698309 [RX_INPUT] configuration >>>>>
5016 09:33:18.698818 [RX_INPUT] configuration <<<<<
5017 09:33:18.704726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 09:33:18.711484 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 09:33:18.718315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 09:33:18.721686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 09:33:18.728320 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 09:33:18.734538 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 09:33:18.738088 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 09:33:18.744259 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 09:33:18.747795 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 09:33:18.750637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 09:33:18.754169 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 09:33:18.761289 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 09:33:18.764019 ===================================
5030 09:33:18.764641 LPDDR4 DRAM CONFIGURATION
5031 09:33:18.767204 ===================================
5032 09:33:18.771049 EX_ROW_EN[0] = 0x0
5033 09:33:18.774101 EX_ROW_EN[1] = 0x0
5034 09:33:18.774670 LP4Y_EN = 0x0
5035 09:33:18.777867 WORK_FSP = 0x0
5036 09:33:18.778287 WL = 0x3
5037 09:33:18.780859 RL = 0x3
5038 09:33:18.781277 BL = 0x2
5039 09:33:18.784134 RPST = 0x0
5040 09:33:18.784553 RD_PRE = 0x0
5041 09:33:18.787710 WR_PRE = 0x1
5042 09:33:18.788270 WR_PST = 0x0
5043 09:33:18.791319 DBI_WR = 0x0
5044 09:33:18.791886 DBI_RD = 0x0
5045 09:33:18.793964 OTF = 0x1
5046 09:33:18.797349 ===================================
5047 09:33:18.801045 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 09:33:18.804255 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 09:33:18.810864 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 09:33:18.813928 ===================================
5051 09:33:18.814353 LPDDR4 DRAM CONFIGURATION
5052 09:33:18.817248 ===================================
5053 09:33:18.820808 EX_ROW_EN[0] = 0x10
5054 09:33:18.823953 EX_ROW_EN[1] = 0x0
5055 09:33:18.824470 LP4Y_EN = 0x0
5056 09:33:18.826763 WORK_FSP = 0x0
5057 09:33:18.827183 WL = 0x3
5058 09:33:18.830356 RL = 0x3
5059 09:33:18.830778 BL = 0x2
5060 09:33:18.834113 RPST = 0x0
5061 09:33:18.834535 RD_PRE = 0x0
5062 09:33:18.836746 WR_PRE = 0x1
5063 09:33:18.837307 WR_PST = 0x0
5064 09:33:18.840754 DBI_WR = 0x0
5065 09:33:18.841173 DBI_RD = 0x0
5066 09:33:18.843594 OTF = 0x1
5067 09:33:18.846697 ===================================
5068 09:33:18.853441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 09:33:18.856782 nWR fixed to 30
5070 09:33:18.860173 [ModeRegInit_LP4] CH0 RK0
5071 09:33:18.860596 [ModeRegInit_LP4] CH0 RK1
5072 09:33:18.863051 [ModeRegInit_LP4] CH1 RK0
5073 09:33:18.866838 [ModeRegInit_LP4] CH1 RK1
5074 09:33:18.867260 match AC timing 9
5075 09:33:18.873047 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 09:33:18.876456 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 09:33:18.879465 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 09:33:18.886424 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 09:33:18.889961 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 09:33:18.890383 ==
5081 09:33:18.893009 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 09:33:18.895953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 09:33:18.896378 ==
5084 09:33:18.902505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 09:33:18.909269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 09:33:18.912590 [CA 0] Center 37 (7~68) winsize 62
5087 09:33:18.916006 [CA 1] Center 37 (7~68) winsize 62
5088 09:33:18.919816 [CA 2] Center 34 (4~65) winsize 62
5089 09:33:18.922619 [CA 3] Center 35 (5~65) winsize 61
5090 09:33:18.925616 [CA 4] Center 33 (3~64) winsize 62
5091 09:33:18.929239 [CA 5] Center 33 (4~63) winsize 60
5092 09:33:18.929660
5093 09:33:18.932112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 09:33:18.932550
5095 09:33:18.935704 [CATrainingPosCal] consider 1 rank data
5096 09:33:18.938694 u2DelayCellTimex100 = 270/100 ps
5097 09:33:18.942040 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5098 09:33:18.945545 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5099 09:33:18.948691 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5100 09:33:18.951957 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5101 09:33:18.958585 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5102 09:33:18.961925 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5103 09:33:18.962505
5104 09:33:18.965099 CA PerBit enable=1, Macro0, CA PI delay=33
5105 09:33:18.965651
5106 09:33:18.968412 [CBTSetCACLKResult] CA Dly = 33
5107 09:33:18.968946 CS Dly: 7 (0~38)
5108 09:33:18.969435 ==
5109 09:33:18.971920 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 09:33:18.979039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 09:33:18.979460 ==
5112 09:33:18.981917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 09:33:18.988580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5114 09:33:18.991486 [CA 0] Center 37 (7~68) winsize 62
5115 09:33:18.995050 [CA 1] Center 37 (7~68) winsize 62
5116 09:33:18.998381 [CA 2] Center 34 (4~65) winsize 62
5117 09:33:19.001855 [CA 3] Center 34 (4~65) winsize 62
5118 09:33:19.004905 [CA 4] Center 33 (3~64) winsize 62
5119 09:33:19.008573 [CA 5] Center 33 (3~63) winsize 61
5120 09:33:19.009097
5121 09:33:19.011338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5122 09:33:19.011777
5123 09:33:19.014558 [CATrainingPosCal] consider 2 rank data
5124 09:33:19.018152 u2DelayCellTimex100 = 270/100 ps
5125 09:33:19.021514 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5126 09:33:19.024839 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5127 09:33:19.031360 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5128 09:33:19.034982 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5129 09:33:19.037801 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5130 09:33:19.041419 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5131 09:33:19.041840
5132 09:33:19.044587 CA PerBit enable=1, Macro0, CA PI delay=33
5133 09:33:19.045007
5134 09:33:19.048201 [CBTSetCACLKResult] CA Dly = 33
5135 09:33:19.048623 CS Dly: 7 (0~39)
5136 09:33:19.048954
5137 09:33:19.054714 ----->DramcWriteLeveling(PI) begin...
5138 09:33:19.055135 ==
5139 09:33:19.058221 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 09:33:19.061192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 09:33:19.061645 ==
5142 09:33:19.064216 Write leveling (Byte 0): 35 => 35
5143 09:33:19.067828 Write leveling (Byte 1): 29 => 29
5144 09:33:19.070835 DramcWriteLeveling(PI) end<-----
5145 09:33:19.071338
5146 09:33:19.071862 ==
5147 09:33:19.074869 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 09:33:19.077954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 09:33:19.078472 ==
5150 09:33:19.080877 [Gating] SW mode calibration
5151 09:33:19.087352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 09:33:19.094051 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 09:33:19.097974 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5154 09:33:19.100522 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 09:33:19.107454 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 09:33:19.111000 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 09:33:19.114475 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 09:33:19.121257 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 09:33:19.124305 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 09:33:19.127347 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5161 09:33:19.133978 0 15 0 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
5162 09:33:19.137447 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 09:33:19.140245 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 09:33:19.147245 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 09:33:19.150260 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 09:33:19.154102 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 09:33:19.160201 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 09:33:19.163692 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (1 1)
5169 09:33:19.166902 1 0 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5170 09:33:19.173455 1 0 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
5171 09:33:19.176926 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 09:33:19.180205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 09:33:19.186299 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 09:33:19.189937 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 09:33:19.193318 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 09:33:19.199800 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5177 09:33:19.202779 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5178 09:33:19.206079 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:33:19.212728 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:33:19.215783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:33:19.219141 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:33:19.226007 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:33:19.229560 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:33:19.232480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:33:19.239347 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:33:19.242853 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:33:19.245764 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 09:33:19.252255 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:33:19.255519 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 09:33:19.259418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:33:19.265449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:33:19.269561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 09:33:19.272487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5194 09:33:19.275395 Total UI for P1: 0, mck2ui 16
5195 09:33:19.278964 best dqsien dly found for B0: ( 1, 2, 28)
5196 09:33:19.285434 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 09:33:19.285853 Total UI for P1: 0, mck2ui 16
5198 09:33:19.292042 best dqsien dly found for B1: ( 1, 3, 0)
5199 09:33:19.295407 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5200 09:33:19.298508 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5201 09:33:19.299147
5202 09:33:19.301941 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5203 09:33:19.304767 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5204 09:33:19.308274 [Gating] SW calibration Done
5205 09:33:19.308695 ==
5206 09:33:19.311551 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 09:33:19.314891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 09:33:19.315307 ==
5209 09:33:19.317895 RX Vref Scan: 0
5210 09:33:19.318270
5211 09:33:19.318591 RX Vref 0 -> 0, step: 1
5212 09:33:19.318896
5213 09:33:19.321388 RX Delay -80 -> 252, step: 8
5214 09:33:19.325300 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5215 09:33:19.331346 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5216 09:33:19.334996 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5217 09:33:19.338101 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5218 09:33:19.341177 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5219 09:33:19.344286 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5220 09:33:19.347985 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5221 09:33:19.354929 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5222 09:33:19.358005 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5223 09:33:19.360887 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5224 09:33:19.365035 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5225 09:33:19.367917 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5226 09:33:19.374780 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5227 09:33:19.378063 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5228 09:33:19.381167 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5229 09:33:19.384479 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5230 09:33:19.384941 ==
5231 09:33:19.387702 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 09:33:19.394084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 09:33:19.394646 ==
5234 09:33:19.395013 DQS Delay:
5235 09:33:19.397449 DQS0 = 0, DQS1 = 0
5236 09:33:19.398003 DQM Delay:
5237 09:33:19.398371 DQM0 = 96, DQM1 = 86
5238 09:33:19.401002 DQ Delay:
5239 09:33:19.404161 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5240 09:33:19.407303 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5241 09:33:19.410145 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5242 09:33:19.413994 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5243 09:33:19.414546
5244 09:33:19.414909
5245 09:33:19.415242 ==
5246 09:33:19.417150 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 09:33:19.420275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 09:33:19.420733 ==
5249 09:33:19.421094
5250 09:33:19.421468
5251 09:33:19.424088 TX Vref Scan disable
5252 09:33:19.427066 == TX Byte 0 ==
5253 09:33:19.430275 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5254 09:33:19.433576 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5255 09:33:19.437093 == TX Byte 1 ==
5256 09:33:19.440182 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5257 09:33:19.443452 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5258 09:33:19.444057 ==
5259 09:33:19.447386 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 09:33:19.453489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 09:33:19.453963 ==
5262 09:33:19.454362
5263 09:33:19.454704
5264 09:33:19.455028 TX Vref Scan disable
5265 09:33:19.457034 == TX Byte 0 ==
5266 09:33:19.460403 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5267 09:33:19.466975 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5268 09:33:19.467450 == TX Byte 1 ==
5269 09:33:19.470226 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5270 09:33:19.477352 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5271 09:33:19.477921
5272 09:33:19.478402 [DATLAT]
5273 09:33:19.478857 Freq=933, CH0 RK0
5274 09:33:19.479311
5275 09:33:19.480277 DATLAT Default: 0xd
5276 09:33:19.483422 0, 0xFFFF, sum = 0
5277 09:33:19.483901 1, 0xFFFF, sum = 0
5278 09:33:19.487160 2, 0xFFFF, sum = 0
5279 09:33:19.487597 3, 0xFFFF, sum = 0
5280 09:33:19.489973 4, 0xFFFF, sum = 0
5281 09:33:19.490509 5, 0xFFFF, sum = 0
5282 09:33:19.493687 6, 0xFFFF, sum = 0
5283 09:33:19.494223 7, 0xFFFF, sum = 0
5284 09:33:19.496923 8, 0xFFFF, sum = 0
5285 09:33:19.497455 9, 0xFFFF, sum = 0
5286 09:33:19.499968 10, 0x0, sum = 1
5287 09:33:19.500406 11, 0x0, sum = 2
5288 09:33:19.503617 12, 0x0, sum = 3
5289 09:33:19.504205 13, 0x0, sum = 4
5290 09:33:19.506317 best_step = 11
5291 09:33:19.506747
5292 09:33:19.507183 ==
5293 09:33:19.509873 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 09:33:19.513017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 09:33:19.513536 ==
5296 09:33:19.513988 RX Vref Scan: 1
5297 09:33:19.516388
5298 09:33:19.516883 RX Vref 0 -> 0, step: 1
5299 09:33:19.517327
5300 09:33:19.519487 RX Delay -61 -> 252, step: 4
5301 09:33:19.519970
5302 09:33:19.522999 Set Vref, RX VrefLevel [Byte0]: 59
5303 09:33:19.525907 [Byte1]: 58
5304 09:33:19.529695
5305 09:33:19.529915 Final RX Vref Byte 0 = 59 to rank0
5306 09:33:19.532908 Final RX Vref Byte 1 = 58 to rank0
5307 09:33:19.535978 Final RX Vref Byte 0 = 59 to rank1
5308 09:33:19.539553 Final RX Vref Byte 1 = 58 to rank1==
5309 09:33:19.542502 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 09:33:19.549059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 09:33:19.549250 ==
5312 09:33:19.549392 DQS Delay:
5313 09:33:19.552251 DQS0 = 0, DQS1 = 0
5314 09:33:19.552440 DQM Delay:
5315 09:33:19.552581 DQM0 = 96, DQM1 = 87
5316 09:33:19.555933 DQ Delay:
5317 09:33:19.559397 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5318 09:33:19.562639 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =106
5319 09:33:19.565766 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =82
5320 09:33:19.568863 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5321 09:33:19.569041
5322 09:33:19.569180
5323 09:33:19.575790 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5324 09:33:19.578899 CH0 RK0: MR19=505, MR18=280F
5325 09:33:19.585571 CH0_RK0: MR19=0x505, MR18=0x280F, DQSOSC=409, MR23=63, INC=64, DEC=43
5326 09:33:19.585892
5327 09:33:19.589076 ----->DramcWriteLeveling(PI) begin...
5328 09:33:19.589494 ==
5329 09:33:19.592352 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 09:33:19.595691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 09:33:19.596144 ==
5332 09:33:19.599637 Write leveling (Byte 0): 30 => 30
5333 09:33:19.602326 Write leveling (Byte 1): 29 => 29
5334 09:33:19.605804 DramcWriteLeveling(PI) end<-----
5335 09:33:19.606327
5336 09:33:19.606658 ==
5337 09:33:19.608904 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 09:33:19.612616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 09:33:19.615877 ==
5340 09:33:19.616437 [Gating] SW mode calibration
5341 09:33:19.625945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 09:33:19.628632 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5343 09:33:19.632382 0 14 0 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (1 1)
5344 09:33:19.638485 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 09:33:19.642001 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 09:33:19.645461 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 09:33:19.651504 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 09:33:19.655360 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 09:33:19.658671 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 09:33:19.665359 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (1 0)
5351 09:33:19.668267 0 15 0 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (1 1)
5352 09:33:19.671603 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 09:33:19.678563 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 09:33:19.682038 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 09:33:19.685476 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 09:33:19.691683 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 09:33:19.694648 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 09:33:19.698044 0 15 28 | B1->B0 | 2525 3737 | 0 1 | (0 0) (0 0)
5359 09:33:19.704662 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5360 09:33:19.707793 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 09:33:19.711187 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 09:33:19.717601 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 09:33:19.721229 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 09:33:19.724544 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 09:33:19.731040 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 09:33:19.733924 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5367 09:33:19.737530 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5368 09:33:19.744119 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:33:19.747883 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:33:19.750295 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:33:19.757239 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:33:19.760556 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:33:19.763658 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:33:19.770667 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:33:19.773663 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:33:19.776768 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:33:19.783917 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 09:33:19.787140 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 09:33:19.789894 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 09:33:19.796886 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 09:33:19.799970 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 09:33:19.803086 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5383 09:33:19.809683 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5384 09:33:19.813367 Total UI for P1: 0, mck2ui 16
5385 09:33:19.816468 best dqsien dly found for B0: ( 1, 2, 28)
5386 09:33:19.820099 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 09:33:19.823267 Total UI for P1: 0, mck2ui 16
5388 09:33:19.827115 best dqsien dly found for B1: ( 1, 2, 30)
5389 09:33:19.830074 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5390 09:33:19.833048 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5391 09:33:19.833462
5392 09:33:19.836820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5393 09:33:19.839955 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5394 09:33:19.843139 [Gating] SW calibration Done
5395 09:33:19.843555 ==
5396 09:33:19.846057 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 09:33:19.852899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 09:33:19.853371 ==
5399 09:33:19.853734 RX Vref Scan: 0
5400 09:33:19.854069
5401 09:33:19.856034 RX Vref 0 -> 0, step: 1
5402 09:33:19.856491
5403 09:33:19.859540 RX Delay -80 -> 252, step: 8
5404 09:33:19.862726 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5405 09:33:19.866389 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5406 09:33:19.869322 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5407 09:33:19.872552 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5408 09:33:19.879309 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5409 09:33:19.882936 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5410 09:33:19.885893 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5411 09:33:19.889294 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5412 09:33:19.892604 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5413 09:33:19.896083 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5414 09:33:19.902574 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5415 09:33:19.905744 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5416 09:33:19.909047 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5417 09:33:19.912238 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5418 09:33:19.915951 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5419 09:33:19.922743 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5420 09:33:19.923307 ==
5421 09:33:19.925753 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 09:33:19.928976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 09:33:19.929550 ==
5424 09:33:19.929921 DQS Delay:
5425 09:33:19.932067 DQS0 = 0, DQS1 = 0
5426 09:33:19.932526 DQM Delay:
5427 09:33:19.935783 DQM0 = 97, DQM1 = 89
5428 09:33:19.936247 DQ Delay:
5429 09:33:19.938571 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5430 09:33:19.941988 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5431 09:33:19.945653 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5432 09:33:19.949131 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5433 09:33:19.949551
5434 09:33:19.949881
5435 09:33:19.950189 ==
5436 09:33:19.951997 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 09:33:19.955181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 09:33:19.958991 ==
5439 09:33:19.959525
5440 09:33:19.960004
5441 09:33:19.960423 TX Vref Scan disable
5442 09:33:19.962201 == TX Byte 0 ==
5443 09:33:19.965793 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5444 09:33:19.968673 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5445 09:33:19.972428 == TX Byte 1 ==
5446 09:33:19.975125 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5447 09:33:19.978934 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5448 09:33:19.979447 ==
5449 09:33:19.982110 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 09:33:19.988238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 09:33:19.988721 ==
5452 09:33:19.989086
5453 09:33:19.989423
5454 09:33:19.991913 TX Vref Scan disable
5455 09:33:19.992464 == TX Byte 0 ==
5456 09:33:19.998449 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5457 09:33:20.001794 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5458 09:33:20.002347 == TX Byte 1 ==
5459 09:33:20.008706 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5460 09:33:20.012475 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5461 09:33:20.013055
5462 09:33:20.013444 [DATLAT]
5463 09:33:20.014770 Freq=933, CH0 RK1
5464 09:33:20.015261
5465 09:33:20.015647 DATLAT Default: 0xb
5466 09:33:20.018136 0, 0xFFFF, sum = 0
5467 09:33:20.018658 1, 0xFFFF, sum = 0
5468 09:33:20.021468 2, 0xFFFF, sum = 0
5469 09:33:20.021942 3, 0xFFFF, sum = 0
5470 09:33:20.024719 4, 0xFFFF, sum = 0
5471 09:33:20.025124 5, 0xFFFF, sum = 0
5472 09:33:20.027848 6, 0xFFFF, sum = 0
5473 09:33:20.028315 7, 0xFFFF, sum = 0
5474 09:33:20.031552 8, 0xFFFF, sum = 0
5475 09:33:20.034772 9, 0xFFFF, sum = 0
5476 09:33:20.035235 10, 0x0, sum = 1
5477 09:33:20.035604 11, 0x0, sum = 2
5478 09:33:20.038161 12, 0x0, sum = 3
5479 09:33:20.038584 13, 0x0, sum = 4
5480 09:33:20.041291 best_step = 11
5481 09:33:20.041705
5482 09:33:20.042030 ==
5483 09:33:20.044668 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 09:33:20.047833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 09:33:20.048251 ==
5486 09:33:20.051175 RX Vref Scan: 0
5487 09:33:20.051588
5488 09:33:20.052090 RX Vref 0 -> 0, step: 1
5489 09:33:20.052469
5490 09:33:20.054579 RX Delay -61 -> 252, step: 4
5491 09:33:20.061916 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5492 09:33:20.065572 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5493 09:33:20.068411 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5494 09:33:20.071567 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5495 09:33:20.075209 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5496 09:33:20.081611 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5497 09:33:20.084656 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5498 09:33:20.088215 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5499 09:33:20.091824 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5500 09:33:20.094777 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5501 09:33:20.101407 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5502 09:33:20.104790 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5503 09:33:20.107840 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5504 09:33:20.111142 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5505 09:33:20.114245 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5506 09:33:20.121250 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5507 09:33:20.121673 ==
5508 09:33:20.124489 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 09:33:20.127849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 09:33:20.128288 ==
5511 09:33:20.128629 DQS Delay:
5512 09:33:20.131359 DQS0 = 0, DQS1 = 0
5513 09:33:20.131816 DQM Delay:
5514 09:33:20.134497 DQM0 = 95, DQM1 = 88
5515 09:33:20.134955 DQ Delay:
5516 09:33:20.137541 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5517 09:33:20.141197 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5518 09:33:20.144363 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5519 09:33:20.147804 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5520 09:33:20.148320
5521 09:33:20.148651
5522 09:33:20.154707 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5523 09:33:20.157480 CH0 RK1: MR19=504, MR18=27F8
5524 09:33:20.164163 CH0_RK1: MR19=0x504, MR18=0x27F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5525 09:33:20.167404 [RxdqsGatingPostProcess] freq 933
5526 09:33:20.174501 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5527 09:33:20.176988 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 09:33:20.180643 best DQS1 dly(2T, 0.5T) = (0, 11)
5529 09:33:20.184583 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 09:33:20.187089 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5531 09:33:20.187523 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 09:33:20.190964 best DQS1 dly(2T, 0.5T) = (0, 10)
5533 09:33:20.194079 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 09:33:20.197110 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5535 09:33:20.200269 Pre-setting of DQS Precalculation
5536 09:33:20.206515 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5537 09:33:20.207012 ==
5538 09:33:20.209871 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 09:33:20.213373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 09:33:20.213960 ==
5541 09:33:20.219754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 09:33:20.226694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5543 09:33:20.229820 [CA 0] Center 37 (7~67) winsize 61
5544 09:33:20.233387 [CA 1] Center 37 (7~68) winsize 62
5545 09:33:20.236831 [CA 2] Center 34 (4~65) winsize 62
5546 09:33:20.240027 [CA 3] Center 33 (3~64) winsize 62
5547 09:33:20.243401 [CA 4] Center 34 (5~64) winsize 60
5548 09:33:20.246424 [CA 5] Center 33 (3~64) winsize 62
5549 09:33:20.246981
5550 09:33:20.249649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5551 09:33:20.250188
5552 09:33:20.252969 [CATrainingPosCal] consider 1 rank data
5553 09:33:20.256470 u2DelayCellTimex100 = 270/100 ps
5554 09:33:20.259376 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5555 09:33:20.263053 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5556 09:33:20.266122 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5557 09:33:20.269795 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 09:33:20.272972 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5559 09:33:20.276174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 09:33:20.279600
5561 09:33:20.282726 CA PerBit enable=1, Macro0, CA PI delay=33
5562 09:33:20.283280
5563 09:33:20.286487 [CBTSetCACLKResult] CA Dly = 33
5564 09:33:20.287039 CS Dly: 6 (0~37)
5565 09:33:20.287407 ==
5566 09:33:20.289349 Dram Type= 6, Freq= 0, CH_1, rank 1
5567 09:33:20.292558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 09:33:20.293023 ==
5569 09:33:20.299196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 09:33:20.305224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5571 09:33:20.308626 [CA 0] Center 36 (6~67) winsize 62
5572 09:33:20.312408 [CA 1] Center 37 (7~67) winsize 61
5573 09:33:20.315070 [CA 2] Center 34 (4~65) winsize 62
5574 09:33:20.318541 [CA 3] Center 34 (3~65) winsize 63
5575 09:33:20.322219 [CA 4] Center 34 (4~65) winsize 62
5576 09:33:20.325125 [CA 5] Center 33 (3~64) winsize 62
5577 09:33:20.325588
5578 09:33:20.328380 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5579 09:33:20.328847
5580 09:33:20.331873 [CATrainingPosCal] consider 2 rank data
5581 09:33:20.335004 u2DelayCellTimex100 = 270/100 ps
5582 09:33:20.338330 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5583 09:33:20.342194 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5584 09:33:20.345293 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5585 09:33:20.351847 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5586 09:33:20.354802 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5587 09:33:20.358469 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5588 09:33:20.359046
5589 09:33:20.361672 CA PerBit enable=1, Macro0, CA PI delay=33
5590 09:33:20.362147
5591 09:33:20.364879 [CBTSetCACLKResult] CA Dly = 33
5592 09:33:20.365551 CS Dly: 7 (0~39)
5593 09:33:20.366033
5594 09:33:20.368150 ----->DramcWriteLeveling(PI) begin...
5595 09:33:20.371759 ==
5596 09:33:20.374592 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 09:33:20.378137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 09:33:20.378751 ==
5599 09:33:20.381116 Write leveling (Byte 0): 26 => 26
5600 09:33:20.384544 Write leveling (Byte 1): 27 => 27
5601 09:33:20.387605 DramcWriteLeveling(PI) end<-----
5602 09:33:20.388078
5603 09:33:20.388517 ==
5604 09:33:20.390812 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 09:33:20.394939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 09:33:20.395372 ==
5607 09:33:20.397601 [Gating] SW mode calibration
5608 09:33:20.404240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5609 09:33:20.410805 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5610 09:33:20.414385 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5611 09:33:20.417352 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 09:33:20.424227 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 09:33:20.427890 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 09:33:20.430714 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 09:33:20.437269 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 09:33:20.440472 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5617 09:33:20.443816 0 14 28 | B1->B0 | 2e2e 2b2b | 1 0 | (1 0) (0 0)
5618 09:33:20.450701 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5619 09:33:20.453774 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 09:33:20.456749 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 09:33:20.463573 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 09:33:20.466825 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 09:33:20.470604 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 09:33:20.476941 0 15 24 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
5625 09:33:20.480015 0 15 28 | B1->B0 | 3030 3636 | 0 1 | (0 0) (0 0)
5626 09:33:20.483621 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 09:33:20.490333 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 09:33:20.493478 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 09:33:20.497531 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 09:33:20.503046 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 09:33:20.506731 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5632 09:33:20.510251 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5633 09:33:20.513679 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5634 09:33:20.520070 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:33:20.523275 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:33:20.530226 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:33:20.533162 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:33:20.536272 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:33:20.540382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:33:20.546727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:33:20.549784 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:33:20.556122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:33:20.559389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 09:33:20.562839 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 09:33:20.569572 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 09:33:20.572887 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:33:20.575807 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 09:33:20.579885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 09:33:20.585923 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 09:33:20.589165 Total UI for P1: 0, mck2ui 16
5651 09:33:20.593304 best dqsien dly found for B0: ( 1, 2, 26)
5652 09:33:20.595970 Total UI for P1: 0, mck2ui 16
5653 09:33:20.599166 best dqsien dly found for B1: ( 1, 2, 26)
5654 09:33:20.603041 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5655 09:33:20.605874 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5656 09:33:20.606429
5657 09:33:20.609160 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5658 09:33:20.612517 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5659 09:33:20.616280 [Gating] SW calibration Done
5660 09:33:20.616839 ==
5661 09:33:20.618686 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 09:33:20.622231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 09:33:20.622693 ==
5664 09:33:20.625801 RX Vref Scan: 0
5665 09:33:20.626364
5666 09:33:20.629331 RX Vref 0 -> 0, step: 1
5667 09:33:20.629892
5668 09:33:20.630258 RX Delay -80 -> 252, step: 8
5669 09:33:20.635716 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5670 09:33:20.638775 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5671 09:33:20.642174 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5672 09:33:20.645163 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5673 09:33:20.649036 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5674 09:33:20.655306 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5675 09:33:20.658570 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5676 09:33:20.661786 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5677 09:33:20.664991 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5678 09:33:20.668269 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5679 09:33:20.671684 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5680 09:33:20.678654 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5681 09:33:20.681943 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5682 09:33:20.684894 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5683 09:33:20.688173 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5684 09:33:20.691670 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5685 09:33:20.695186 ==
5686 09:33:20.695702 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 09:33:20.701544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 09:33:20.702057 ==
5689 09:33:20.702388 DQS Delay:
5690 09:33:20.704795 DQS0 = 0, DQS1 = 0
5691 09:33:20.705313 DQM Delay:
5692 09:33:20.708138 DQM0 = 102, DQM1 = 90
5693 09:33:20.708552 DQ Delay:
5694 09:33:20.711378 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5695 09:33:20.714691 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5696 09:33:20.718065 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5697 09:33:20.721408 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =103
5698 09:33:20.721819
5699 09:33:20.722146
5700 09:33:20.722449 ==
5701 09:33:20.725148 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 09:33:20.727908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 09:33:20.728324 ==
5704 09:33:20.728650
5705 09:33:20.731096
5706 09:33:20.731598 TX Vref Scan disable
5707 09:33:20.735122 == TX Byte 0 ==
5708 09:33:20.737965 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5709 09:33:20.741095 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5710 09:33:20.744216 == TX Byte 1 ==
5711 09:33:20.747607 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5712 09:33:20.750863 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5713 09:33:20.751275 ==
5714 09:33:20.754195 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 09:33:20.760983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 09:33:20.761498 ==
5717 09:33:20.761831
5718 09:33:20.762135
5719 09:33:20.764322 TX Vref Scan disable
5720 09:33:20.764733 == TX Byte 0 ==
5721 09:33:20.770630 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5722 09:33:20.773990 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5723 09:33:20.774503 == TX Byte 1 ==
5724 09:33:20.780345 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5725 09:33:20.783934 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5726 09:33:20.784370
5727 09:33:20.784699 [DATLAT]
5728 09:33:20.786979 Freq=933, CH1 RK0
5729 09:33:20.787346
5730 09:33:20.787652 DATLAT Default: 0xd
5731 09:33:20.790449 0, 0xFFFF, sum = 0
5732 09:33:20.790833 1, 0xFFFF, sum = 0
5733 09:33:20.793558 2, 0xFFFF, sum = 0
5734 09:33:20.793967 3, 0xFFFF, sum = 0
5735 09:33:20.797289 4, 0xFFFF, sum = 0
5736 09:33:20.797673 5, 0xFFFF, sum = 0
5737 09:33:20.800659 6, 0xFFFF, sum = 0
5738 09:33:20.801025 7, 0xFFFF, sum = 0
5739 09:33:20.803569 8, 0xFFFF, sum = 0
5740 09:33:20.807129 9, 0xFFFF, sum = 0
5741 09:33:20.807551 10, 0x0, sum = 1
5742 09:33:20.807944 11, 0x0, sum = 2
5743 09:33:20.810590 12, 0x0, sum = 3
5744 09:33:20.811107 13, 0x0, sum = 4
5745 09:33:20.814000 best_step = 11
5746 09:33:20.814508
5747 09:33:20.814839 ==
5748 09:33:20.817062 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 09:33:20.820322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 09:33:20.820840 ==
5751 09:33:20.823844 RX Vref Scan: 1
5752 09:33:20.824355
5753 09:33:20.824686 RX Vref 0 -> 0, step: 1
5754 09:33:20.824992
5755 09:33:20.827127 RX Delay -69 -> 252, step: 4
5756 09:33:20.827639
5757 09:33:20.831208 Set Vref, RX VrefLevel [Byte0]: 46
5758 09:33:20.833876 [Byte1]: 54
5759 09:33:20.837580
5760 09:33:20.837995 Final RX Vref Byte 0 = 46 to rank0
5761 09:33:20.840930 Final RX Vref Byte 1 = 54 to rank0
5762 09:33:20.844258 Final RX Vref Byte 0 = 46 to rank1
5763 09:33:20.847630 Final RX Vref Byte 1 = 54 to rank1==
5764 09:33:20.851266 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 09:33:20.857770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 09:33:20.858214 ==
5767 09:33:20.858561 DQS Delay:
5768 09:33:20.860784 DQS0 = 0, DQS1 = 0
5769 09:33:20.861201 DQM Delay:
5770 09:33:20.861531 DQM0 = 101, DQM1 = 94
5771 09:33:20.864364 DQ Delay:
5772 09:33:20.867866 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5773 09:33:20.870762 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5774 09:33:20.874322 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =86
5775 09:33:20.877462 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =102
5776 09:33:20.877912
5777 09:33:20.878249
5778 09:33:20.884089 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5779 09:33:20.887350 CH1 RK0: MR19=505, MR18=1D0D
5780 09:33:20.893783 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5781 09:33:20.894283
5782 09:33:20.897108 ----->DramcWriteLeveling(PI) begin...
5783 09:33:20.897653 ==
5784 09:33:20.900073 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 09:33:20.903665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 09:33:20.906884 ==
5787 09:33:20.907347 Write leveling (Byte 0): 27 => 27
5788 09:33:20.910042 Write leveling (Byte 1): 29 => 29
5789 09:33:20.913529 DramcWriteLeveling(PI) end<-----
5790 09:33:20.913973
5791 09:33:20.914307 ==
5792 09:33:20.917147 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 09:33:20.923235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 09:33:20.923789 ==
5795 09:33:20.926853 [Gating] SW mode calibration
5796 09:33:20.932847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5797 09:33:20.936929 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5798 09:33:20.943023 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5799 09:33:20.946082 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 09:33:20.949834 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 09:33:20.956245 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 09:33:20.959864 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 09:33:20.962835 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 09:33:20.969660 0 14 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
5805 09:33:20.973232 0 14 28 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (1 1)
5806 09:33:20.976308 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5807 09:33:20.983108 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 09:33:20.986188 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 09:33:20.989513 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 09:33:20.996139 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 09:33:20.999515 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 09:33:21.002905 0 15 24 | B1->B0 | 2d2c 2323 | 1 0 | (1 1) (0 0)
5813 09:33:21.009282 0 15 28 | B1->B0 | 4040 3333 | 0 0 | (0 0) (0 0)
5814 09:33:21.012432 1 0 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5815 09:33:21.015711 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 09:33:21.022370 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 09:33:21.026235 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 09:33:21.029224 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 09:33:21.035872 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 09:33:21.038811 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5821 09:33:21.042502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5822 09:33:21.048837 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:33:21.051975 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:33:21.055112 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:33:21.062020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:33:21.065172 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:33:21.068281 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:33:21.075079 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:33:21.078470 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:33:21.081838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:33:21.087954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 09:33:21.091621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 09:33:21.094778 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 09:33:21.101635 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:33:21.104640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:33:21.108338 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5837 09:33:21.114745 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5838 09:33:21.115308 Total UI for P1: 0, mck2ui 16
5839 09:33:21.121250 best dqsien dly found for B1: ( 1, 2, 24)
5840 09:33:21.124426 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 09:33:21.127784 Total UI for P1: 0, mck2ui 16
5842 09:33:21.131401 best dqsien dly found for B0: ( 1, 2, 26)
5843 09:33:21.134493 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5844 09:33:21.137490 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5845 09:33:21.137963
5846 09:33:21.140930 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5847 09:33:21.144529 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5848 09:33:21.147821 [Gating] SW calibration Done
5849 09:33:21.148400 ==
5850 09:33:21.151283 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 09:33:21.153964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 09:33:21.157272 ==
5853 09:33:21.157733 RX Vref Scan: 0
5854 09:33:21.158093
5855 09:33:21.160502 RX Vref 0 -> 0, step: 1
5856 09:33:21.161002
5857 09:33:21.163951 RX Delay -80 -> 252, step: 8
5858 09:33:21.166880 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5859 09:33:21.170366 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5860 09:33:21.173869 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5861 09:33:21.177290 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5862 09:33:21.183576 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5863 09:33:21.186896 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5864 09:33:21.190491 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5865 09:33:21.193792 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5866 09:33:21.196941 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5867 09:33:21.203528 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5868 09:33:21.206476 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5869 09:33:21.209936 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5870 09:33:21.213083 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5871 09:33:21.216419 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5872 09:33:21.219770 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5873 09:33:21.226726 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5874 09:33:21.227243 ==
5875 09:33:21.229406 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 09:33:21.232623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 09:33:21.233088 ==
5878 09:33:21.233451 DQS Delay:
5879 09:33:21.236198 DQS0 = 0, DQS1 = 0
5880 09:33:21.236657 DQM Delay:
5881 09:33:21.239064 DQM0 = 101, DQM1 = 91
5882 09:33:21.239524 DQ Delay:
5883 09:33:21.242755 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5884 09:33:21.246133 DQ4 =95, DQ5 =111, DQ6 =115, DQ7 =95
5885 09:33:21.248972 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5886 09:33:21.252162 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5887 09:33:21.252580
5888 09:33:21.252909
5889 09:33:21.253214 ==
5890 09:33:21.255572 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 09:33:21.262584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 09:33:21.263115 ==
5893 09:33:21.263463
5894 09:33:21.263822
5895 09:33:21.264129 TX Vref Scan disable
5896 09:33:21.265712 == TX Byte 0 ==
5897 09:33:21.269449 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5898 09:33:21.275886 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5899 09:33:21.276311 == TX Byte 1 ==
5900 09:33:21.278975 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5901 09:33:21.285772 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5902 09:33:21.286195 ==
5903 09:33:21.289515 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 09:33:21.292095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 09:33:21.292523 ==
5906 09:33:21.292860
5907 09:33:21.293176
5908 09:33:21.295574 TX Vref Scan disable
5909 09:33:21.299316 == TX Byte 0 ==
5910 09:33:21.302322 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5911 09:33:21.305501 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5912 09:33:21.309175 == TX Byte 1 ==
5913 09:33:21.311947 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5914 09:33:21.315212 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5915 09:33:21.315821
5916 09:33:21.316211 [DATLAT]
5917 09:33:21.318380 Freq=933, CH1 RK1
5918 09:33:21.318947
5919 09:33:21.321706 DATLAT Default: 0xb
5920 09:33:21.322183 0, 0xFFFF, sum = 0
5921 09:33:21.325102 1, 0xFFFF, sum = 0
5922 09:33:21.325569 2, 0xFFFF, sum = 0
5923 09:33:21.328594 3, 0xFFFF, sum = 0
5924 09:33:21.329061 4, 0xFFFF, sum = 0
5925 09:33:21.331889 5, 0xFFFF, sum = 0
5926 09:33:21.332313 6, 0xFFFF, sum = 0
5927 09:33:21.334935 7, 0xFFFF, sum = 0
5928 09:33:21.335355 8, 0xFFFF, sum = 0
5929 09:33:21.337895 9, 0xFFFF, sum = 0
5930 09:33:21.338338 10, 0x0, sum = 1
5931 09:33:21.341568 11, 0x0, sum = 2
5932 09:33:21.341989 12, 0x0, sum = 3
5933 09:33:21.345023 13, 0x0, sum = 4
5934 09:33:21.345444 best_step = 11
5935 09:33:21.345776
5936 09:33:21.346083 ==
5937 09:33:21.347832 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 09:33:21.351306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 09:33:21.354511 ==
5940 09:33:21.354922 RX Vref Scan: 0
5941 09:33:21.355370
5942 09:33:21.358431 RX Vref 0 -> 0, step: 1
5943 09:33:21.358951
5944 09:33:21.361170 RX Delay -61 -> 252, step: 4
5945 09:33:21.364781 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5946 09:33:21.368046 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
5947 09:33:21.374745 iDelay=203, Bit 2, Center 92 (7 ~ 178) 172
5948 09:33:21.377922 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5949 09:33:21.380885 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5950 09:33:21.384976 iDelay=203, Bit 5, Center 110 (23 ~ 198) 176
5951 09:33:21.388068 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
5952 09:33:21.394166 iDelay=203, Bit 7, Center 98 (7 ~ 190) 184
5953 09:33:21.397466 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5954 09:33:21.400692 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5955 09:33:21.404165 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5956 09:33:21.407774 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5957 09:33:21.410770 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5958 09:33:21.417750 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5959 09:33:21.420673 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5960 09:33:21.423655 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5961 09:33:21.424131 ==
5962 09:33:21.427084 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 09:33:21.430519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 09:33:21.433936 ==
5965 09:33:21.434495 DQS Delay:
5966 09:33:21.434885 DQS0 = 0, DQS1 = 0
5967 09:33:21.436839 DQM Delay:
5968 09:33:21.437254 DQM0 = 102, DQM1 = 93
5969 09:33:21.440251 DQ Delay:
5970 09:33:21.443426 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5971 09:33:21.447119 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
5972 09:33:21.450754 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5973 09:33:21.453354 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5974 09:33:21.453774
5975 09:33:21.454104
5976 09:33:21.460282 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5977 09:33:21.463240 CH1 RK1: MR19=504, MR18=5FF
5978 09:33:21.470416 CH1_RK1: MR19=0x504, MR18=0x5FF, DQSOSC=420, MR23=63, INC=61, DEC=40
5979 09:33:21.473420 [RxdqsGatingPostProcess] freq 933
5980 09:33:21.476365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 09:33:21.480103 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 09:33:21.483201 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 09:33:21.486657 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 09:33:21.489942 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 09:33:21.493197 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 09:33:21.496361 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 09:33:21.499909 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 09:33:21.503247 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 09:33:21.506721 Pre-setting of DQS Precalculation
5990 09:33:21.509670 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 09:33:21.519682 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 09:33:21.526398 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 09:33:21.526963
5994 09:33:21.527331
5995 09:33:21.529811 [Calibration Summary] 1866 Mbps
5996 09:33:21.530372 CH 0, Rank 0
5997 09:33:21.532353 SW Impedance : PASS
5998 09:33:21.532810 DUTY Scan : NO K
5999 09:33:21.535800 ZQ Calibration : PASS
6000 09:33:21.538883 Jitter Meter : NO K
6001 09:33:21.539343 CBT Training : PASS
6002 09:33:21.542433 Write leveling : PASS
6003 09:33:21.545626 RX DQS gating : PASS
6004 09:33:21.546042 RX DQ/DQS(RDDQC) : PASS
6005 09:33:21.548996 TX DQ/DQS : PASS
6006 09:33:21.552256 RX DATLAT : PASS
6007 09:33:21.552831 RX DQ/DQS(Engine): PASS
6008 09:33:21.555720 TX OE : NO K
6009 09:33:21.556264 All Pass.
6010 09:33:21.556603
6011 09:33:21.559154 CH 0, Rank 1
6012 09:33:21.559567 SW Impedance : PASS
6013 09:33:21.562290 DUTY Scan : NO K
6014 09:33:21.565361 ZQ Calibration : PASS
6015 09:33:21.565795 Jitter Meter : NO K
6016 09:33:21.568455 CBT Training : PASS
6017 09:33:21.572376 Write leveling : PASS
6018 09:33:21.572790 RX DQS gating : PASS
6019 09:33:21.575185 RX DQ/DQS(RDDQC) : PASS
6020 09:33:21.578888 TX DQ/DQS : PASS
6021 09:33:21.579404 RX DATLAT : PASS
6022 09:33:21.582144 RX DQ/DQS(Engine): PASS
6023 09:33:21.585604 TX OE : NO K
6024 09:33:21.586115 All Pass.
6025 09:33:21.586446
6026 09:33:21.586750 CH 1, Rank 0
6027 09:33:21.588842 SW Impedance : PASS
6028 09:33:21.591811 DUTY Scan : NO K
6029 09:33:21.592231 ZQ Calibration : PASS
6030 09:33:21.595143 Jitter Meter : NO K
6031 09:33:21.598780 CBT Training : PASS
6032 09:33:21.599296 Write leveling : PASS
6033 09:33:21.602388 RX DQS gating : PASS
6034 09:33:21.602901 RX DQ/DQS(RDDQC) : PASS
6035 09:33:21.605223 TX DQ/DQS : PASS
6036 09:33:21.608429 RX DATLAT : PASS
6037 09:33:21.608845 RX DQ/DQS(Engine): PASS
6038 09:33:21.612078 TX OE : NO K
6039 09:33:21.612499 All Pass.
6040 09:33:21.612825
6041 09:33:21.615565 CH 1, Rank 1
6042 09:33:21.616163 SW Impedance : PASS
6043 09:33:21.618310 DUTY Scan : NO K
6044 09:33:21.621786 ZQ Calibration : PASS
6045 09:33:21.622395 Jitter Meter : NO K
6046 09:33:21.625333 CBT Training : PASS
6047 09:33:21.628646 Write leveling : PASS
6048 09:33:21.629156 RX DQS gating : PASS
6049 09:33:21.631851 RX DQ/DQS(RDDQC) : PASS
6050 09:33:21.635271 TX DQ/DQS : PASS
6051 09:33:21.635836 RX DATLAT : PASS
6052 09:33:21.638371 RX DQ/DQS(Engine): PASS
6053 09:33:21.641814 TX OE : NO K
6054 09:33:21.642329 All Pass.
6055 09:33:21.642660
6056 09:33:21.644893 DramC Write-DBI off
6057 09:33:21.645326 PER_BANK_REFRESH: Hybrid Mode
6058 09:33:21.648273 TX_TRACKING: ON
6059 09:33:21.654807 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 09:33:21.661268 [FAST_K] Save calibration result to emmc
6061 09:33:21.664468 dramc_set_vcore_voltage set vcore to 650000
6062 09:33:21.664898 Read voltage for 400, 6
6063 09:33:21.667512 Vio18 = 0
6064 09:33:21.667978 Vcore = 650000
6065 09:33:21.668334 Vdram = 0
6066 09:33:21.671347 Vddq = 0
6067 09:33:21.671836 Vmddr = 0
6068 09:33:21.674448 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 09:33:21.681729 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 09:33:21.684651 MEM_TYPE=3, freq_sel=20
6071 09:33:21.687909 sv_algorithm_assistance_LP4_800
6072 09:33:21.691446 ============ PULL DRAM RESETB DOWN ============
6073 09:33:21.694568 ========== PULL DRAM RESETB DOWN end =========
6074 09:33:21.700925 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 09:33:21.704612 ===================================
6076 09:33:21.705167 LPDDR4 DRAM CONFIGURATION
6077 09:33:21.707764 ===================================
6078 09:33:21.710623 EX_ROW_EN[0] = 0x0
6079 09:33:21.711183 EX_ROW_EN[1] = 0x0
6080 09:33:21.714135 LP4Y_EN = 0x0
6081 09:33:21.714597 WORK_FSP = 0x0
6082 09:33:21.718004 WL = 0x2
6083 09:33:21.720947 RL = 0x2
6084 09:33:21.721514 BL = 0x2
6085 09:33:21.723674 RPST = 0x0
6086 09:33:21.724168 RD_PRE = 0x0
6087 09:33:21.727388 WR_PRE = 0x1
6088 09:33:21.728188 WR_PST = 0x0
6089 09:33:21.730601 DBI_WR = 0x0
6090 09:33:21.731161 DBI_RD = 0x0
6091 09:33:21.734040 OTF = 0x1
6092 09:33:21.737137 ===================================
6093 09:33:21.741014 ===================================
6094 09:33:21.741578 ANA top config
6095 09:33:21.743932 ===================================
6096 09:33:21.747671 DLL_ASYNC_EN = 0
6097 09:33:21.750390 ALL_SLAVE_EN = 1
6098 09:33:21.750947 NEW_RANK_MODE = 1
6099 09:33:21.753674 DLL_IDLE_MODE = 1
6100 09:33:21.757118 LP45_APHY_COMB_EN = 1
6101 09:33:21.760770 TX_ODT_DIS = 1
6102 09:33:21.764196 NEW_8X_MODE = 1
6103 09:33:21.767185 ===================================
6104 09:33:21.769978 ===================================
6105 09:33:21.770441 data_rate = 800
6106 09:33:21.773665 CKR = 1
6107 09:33:21.776719 DQ_P2S_RATIO = 4
6108 09:33:21.779896 ===================================
6109 09:33:21.783195 CA_P2S_RATIO = 4
6110 09:33:21.786577 DQ_CA_OPEN = 0
6111 09:33:21.789902 DQ_SEMI_OPEN = 1
6112 09:33:21.793240 CA_SEMI_OPEN = 1
6113 09:33:21.793805 CA_FULL_RATE = 0
6114 09:33:21.796227 DQ_CKDIV4_EN = 0
6115 09:33:21.800056 CA_CKDIV4_EN = 1
6116 09:33:21.802954 CA_PREDIV_EN = 0
6117 09:33:21.806247 PH8_DLY = 0
6118 09:33:21.809763 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 09:33:21.810208 DQ_AAMCK_DIV = 0
6120 09:33:21.812675 CA_AAMCK_DIV = 0
6121 09:33:21.816195 CA_ADMCK_DIV = 4
6122 09:33:21.819586 DQ_TRACK_CA_EN = 0
6123 09:33:21.823162 CA_PICK = 800
6124 09:33:21.826626 CA_MCKIO = 400
6125 09:33:21.829063 MCKIO_SEMI = 400
6126 09:33:21.829624 PLL_FREQ = 3016
6127 09:33:21.832696 DQ_UI_PI_RATIO = 32
6128 09:33:21.835703 CA_UI_PI_RATIO = 32
6129 09:33:21.839185 ===================================
6130 09:33:21.842821 ===================================
6131 09:33:21.845841 memory_type:LPDDR4
6132 09:33:21.849324 GP_NUM : 10
6133 09:33:21.849865 SRAM_EN : 1
6134 09:33:21.853115 MD32_EN : 0
6135 09:33:21.856001 ===================================
6136 09:33:21.859115 [ANA_INIT] >>>>>>>>>>>>>>
6137 09:33:21.859506 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 09:33:21.862428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 09:33:21.865667 ===================================
6140 09:33:21.869173 data_rate = 800,PCW = 0X7400
6141 09:33:21.872234 ===================================
6142 09:33:21.875596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 09:33:21.882262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 09:33:21.892107 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 09:33:21.898359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 09:33:21.902168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 09:33:21.904927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 09:33:21.908625 [ANA_INIT] flow start
6149 09:33:21.909045 [ANA_INIT] PLL >>>>>>>>
6150 09:33:21.912071 [ANA_INIT] PLL <<<<<<<<
6151 09:33:21.914884 [ANA_INIT] MIDPI >>>>>>>>
6152 09:33:21.915297 [ANA_INIT] MIDPI <<<<<<<<
6153 09:33:21.918479 [ANA_INIT] DLL >>>>>>>>
6154 09:33:21.921706 [ANA_INIT] flow end
6155 09:33:21.925146 ============ LP4 DIFF to SE enter ============
6156 09:33:21.928334 ============ LP4 DIFF to SE exit ============
6157 09:33:21.931819 [ANA_INIT] <<<<<<<<<<<<<
6158 09:33:21.935362 [Flow] Enable top DCM control >>>>>
6159 09:33:21.938254 [Flow] Enable top DCM control <<<<<
6160 09:33:21.941396 Enable DLL master slave shuffle
6161 09:33:21.944983 ==============================================================
6162 09:33:21.948336 Gating Mode config
6163 09:33:21.954666 ==============================================================
6164 09:33:21.955264 Config description:
6165 09:33:21.964619 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 09:33:21.971281 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 09:33:21.977482 SELPH_MODE 0: By rank 1: By Phase
6168 09:33:21.980896 ==============================================================
6169 09:33:21.984520 GAT_TRACK_EN = 0
6170 09:33:21.987524 RX_GATING_MODE = 2
6171 09:33:21.990581 RX_GATING_TRACK_MODE = 2
6172 09:33:21.993813 SELPH_MODE = 1
6173 09:33:21.997595 PICG_EARLY_EN = 1
6174 09:33:22.000767 VALID_LAT_VALUE = 1
6175 09:33:22.003812 ==============================================================
6176 09:33:22.007085 Enter into Gating configuration >>>>
6177 09:33:22.010332 Exit from Gating configuration <<<<
6178 09:33:22.014500 Enter into DVFS_PRE_config >>>>>
6179 09:33:22.027230 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 09:33:22.030475 Exit from DVFS_PRE_config <<<<<
6181 09:33:22.033881 Enter into PICG configuration >>>>
6182 09:33:22.037243 Exit from PICG configuration <<<<
6183 09:33:22.037665 [RX_INPUT] configuration >>>>>
6184 09:33:22.040414 [RX_INPUT] configuration <<<<<
6185 09:33:22.046629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 09:33:22.053468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 09:33:22.056656 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 09:33:22.063288 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 09:33:22.069656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 09:33:22.076337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 09:33:22.079834 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 09:33:22.083092 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 09:33:22.090177 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 09:33:22.093127 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 09:33:22.096331 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 09:33:22.103415 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 09:33:22.106111 ===================================
6198 09:33:22.106529 LPDDR4 DRAM CONFIGURATION
6199 09:33:22.109262 ===================================
6200 09:33:22.112672 EX_ROW_EN[0] = 0x0
6201 09:33:22.113108 EX_ROW_EN[1] = 0x0
6202 09:33:22.115903 LP4Y_EN = 0x0
6203 09:33:22.116351 WORK_FSP = 0x0
6204 09:33:22.119139 WL = 0x2
6205 09:33:22.122346 RL = 0x2
6206 09:33:22.122760 BL = 0x2
6207 09:33:22.126096 RPST = 0x0
6208 09:33:22.126508 RD_PRE = 0x0
6209 09:33:22.129366 WR_PRE = 0x1
6210 09:33:22.129780 WR_PST = 0x0
6211 09:33:22.132590 DBI_WR = 0x0
6212 09:33:22.133005 DBI_RD = 0x0
6213 09:33:22.135690 OTF = 0x1
6214 09:33:22.138995 ===================================
6215 09:33:22.142693 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 09:33:22.146247 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 09:33:22.152069 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 09:33:22.155362 ===================================
6219 09:33:22.155840 LPDDR4 DRAM CONFIGURATION
6220 09:33:22.158657 ===================================
6221 09:33:22.161891 EX_ROW_EN[0] = 0x10
6222 09:33:22.165687 EX_ROW_EN[1] = 0x0
6223 09:33:22.166231 LP4Y_EN = 0x0
6224 09:33:22.168770 WORK_FSP = 0x0
6225 09:33:22.169189 WL = 0x2
6226 09:33:22.171891 RL = 0x2
6227 09:33:22.172312 BL = 0x2
6228 09:33:22.175092 RPST = 0x0
6229 09:33:22.175505 RD_PRE = 0x0
6230 09:33:22.178779 WR_PRE = 0x1
6231 09:33:22.179238 WR_PST = 0x0
6232 09:33:22.182287 DBI_WR = 0x0
6233 09:33:22.183010 DBI_RD = 0x0
6234 09:33:22.186009 OTF = 0x1
6235 09:33:22.188463 ===================================
6236 09:33:22.195310 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 09:33:22.198568 nWR fixed to 30
6238 09:33:22.199029 [ModeRegInit_LP4] CH0 RK0
6239 09:33:22.202080 [ModeRegInit_LP4] CH0 RK1
6240 09:33:22.205275 [ModeRegInit_LP4] CH1 RK0
6241 09:33:22.208483 [ModeRegInit_LP4] CH1 RK1
6242 09:33:22.208944 match AC timing 19
6243 09:33:22.215082 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 09:33:22.218533 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 09:33:22.221688 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 09:33:22.228434 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 09:33:22.231224 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 09:33:22.231830 ==
6249 09:33:22.234800 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 09:33:22.238409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 09:33:22.238977 ==
6252 09:33:22.244897 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 09:33:22.251421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6254 09:33:22.254677 [CA 0] Center 36 (8~64) winsize 57
6255 09:33:22.257578 [CA 1] Center 36 (8~64) winsize 57
6256 09:33:22.260738 [CA 2] Center 36 (8~64) winsize 57
6257 09:33:22.264319 [CA 3] Center 36 (8~64) winsize 57
6258 09:33:22.264879 [CA 4] Center 36 (8~64) winsize 57
6259 09:33:22.267412 [CA 5] Center 36 (8~64) winsize 57
6260 09:33:22.267924
6261 09:33:22.274269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6262 09:33:22.274825
6263 09:33:22.277581 [CATrainingPosCal] consider 1 rank data
6264 09:33:22.280633 u2DelayCellTimex100 = 270/100 ps
6265 09:33:22.283836 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 09:33:22.287499 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 09:33:22.290888 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 09:33:22.294019 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 09:33:22.297048 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:33:22.300530 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 09:33:22.300988
6272 09:33:22.303876 CA PerBit enable=1, Macro0, CA PI delay=36
6273 09:33:22.304334
6274 09:33:22.306920 [CBTSetCACLKResult] CA Dly = 36
6275 09:33:22.310512 CS Dly: 1 (0~32)
6276 09:33:22.311056 ==
6277 09:33:22.313788 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 09:33:22.316780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 09:33:22.317241 ==
6280 09:33:22.324224 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 09:33:22.330826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6282 09:33:22.333680 [CA 0] Center 36 (8~64) winsize 57
6283 09:33:22.334231 [CA 1] Center 36 (8~64) winsize 57
6284 09:33:22.336767 [CA 2] Center 36 (8~64) winsize 57
6285 09:33:22.340053 [CA 3] Center 36 (8~64) winsize 57
6286 09:33:22.343549 [CA 4] Center 36 (8~64) winsize 57
6287 09:33:22.347093 [CA 5] Center 36 (8~64) winsize 57
6288 09:33:22.347656
6289 09:33:22.350646 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6290 09:33:22.351198
6291 09:33:22.356890 [CATrainingPosCal] consider 2 rank data
6292 09:33:22.357444 u2DelayCellTimex100 = 270/100 ps
6293 09:33:22.363206 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 09:33:22.366447 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 09:33:22.369691 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 09:33:22.373175 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 09:33:22.376551 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:33:22.379571 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:33:22.380088
6300 09:33:22.382801 CA PerBit enable=1, Macro0, CA PI delay=36
6301 09:33:22.383259
6302 09:33:22.386393 [CBTSetCACLKResult] CA Dly = 36
6303 09:33:22.389673 CS Dly: 1 (0~32)
6304 09:33:22.390169
6305 09:33:22.392762 ----->DramcWriteLeveling(PI) begin...
6306 09:33:22.393229 ==
6307 09:33:22.396351 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 09:33:22.399441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 09:33:22.399954 ==
6310 09:33:22.402896 Write leveling (Byte 0): 40 => 8
6311 09:33:22.406494 Write leveling (Byte 1): 32 => 0
6312 09:33:22.409554 DramcWriteLeveling(PI) end<-----
6313 09:33:22.410013
6314 09:33:22.410377 ==
6315 09:33:22.413234 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 09:33:22.416269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 09:33:22.416689 ==
6318 09:33:22.419129 [Gating] SW mode calibration
6319 09:33:22.425926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 09:33:22.432690 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 09:33:22.435922 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 09:33:22.439154 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 09:33:22.445562 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 09:33:22.449089 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 09:33:22.452588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 09:33:22.458713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 09:33:22.462292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 09:33:22.465894 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 09:33:22.472185 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 09:33:22.475872 Total UI for P1: 0, mck2ui 16
6331 09:33:22.478855 best dqsien dly found for B0: ( 0, 14, 24)
6332 09:33:22.479484 Total UI for P1: 0, mck2ui 16
6333 09:33:22.485239 best dqsien dly found for B1: ( 0, 14, 24)
6334 09:33:22.488867 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 09:33:22.491884 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 09:33:22.492438
6337 09:33:22.495026 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 09:33:22.498286 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 09:33:22.502355 [Gating] SW calibration Done
6340 09:33:22.502979 ==
6341 09:33:22.505077 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 09:33:22.508402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 09:33:22.508868 ==
6344 09:33:22.512106 RX Vref Scan: 0
6345 09:33:22.512565
6346 09:33:22.515037 RX Vref 0 -> 0, step: 1
6347 09:33:22.515499
6348 09:33:22.516009 RX Delay -410 -> 252, step: 16
6349 09:33:22.522001 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6350 09:33:22.524877 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6351 09:33:22.529395 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6352 09:33:22.532361 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6353 09:33:22.538128 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6354 09:33:22.541199 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6355 09:33:22.544865 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6356 09:33:22.551215 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6357 09:33:22.554490 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6358 09:33:22.558220 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6359 09:33:22.561517 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6360 09:33:22.568089 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6361 09:33:22.571390 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6362 09:33:22.574467 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6363 09:33:22.577524 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6364 09:33:22.584690 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6365 09:33:22.585260 ==
6366 09:33:22.587714 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 09:33:22.590932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 09:33:22.591481 ==
6369 09:33:22.591910 DQS Delay:
6370 09:33:22.594448 DQS0 = 43, DQS1 = 59
6371 09:33:22.595001 DQM Delay:
6372 09:33:22.597692 DQM0 = 11, DQM1 = 14
6373 09:33:22.598262 DQ Delay:
6374 09:33:22.600902 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6375 09:33:22.604323 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =16
6376 09:33:22.608166 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6377 09:33:22.610642 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6378 09:33:22.611188
6379 09:33:22.611555
6380 09:33:22.611958 ==
6381 09:33:22.613696 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 09:33:22.617284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 09:33:22.617775 ==
6384 09:33:22.620472
6385 09:33:22.620927
6386 09:33:22.621285 TX Vref Scan disable
6387 09:33:22.623819 == TX Byte 0 ==
6388 09:33:22.627523 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 09:33:22.630750 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 09:33:22.633998 == TX Byte 1 ==
6391 09:33:22.637235 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 09:33:22.640591 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 09:33:22.641163 ==
6394 09:33:22.644411 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 09:33:22.650106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 09:33:22.650645 ==
6397 09:33:22.651002
6398 09:33:22.651333
6399 09:33:22.651651 TX Vref Scan disable
6400 09:33:22.653614 == TX Byte 0 ==
6401 09:33:22.657215 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 09:33:22.659897 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 09:33:22.663489 == TX Byte 1 ==
6404 09:33:22.666687 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6405 09:33:22.670076 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6406 09:33:22.670629
6407 09:33:22.673115 [DATLAT]
6408 09:33:22.673561 Freq=400, CH0 RK0
6409 09:33:22.673919
6410 09:33:22.676702 DATLAT Default: 0xf
6411 09:33:22.677253 0, 0xFFFF, sum = 0
6412 09:33:22.680312 1, 0xFFFF, sum = 0
6413 09:33:22.680780 2, 0xFFFF, sum = 0
6414 09:33:22.683342 3, 0xFFFF, sum = 0
6415 09:33:22.683845 4, 0xFFFF, sum = 0
6416 09:33:22.686495 5, 0xFFFF, sum = 0
6417 09:33:22.687054 6, 0xFFFF, sum = 0
6418 09:33:22.689972 7, 0xFFFF, sum = 0
6419 09:33:22.690773 8, 0xFFFF, sum = 0
6420 09:33:22.693157 9, 0xFFFF, sum = 0
6421 09:33:22.696586 10, 0xFFFF, sum = 0
6422 09:33:22.697143 11, 0xFFFF, sum = 0
6423 09:33:22.700261 12, 0xFFFF, sum = 0
6424 09:33:22.700816 13, 0x0, sum = 1
6425 09:33:22.703235 14, 0x0, sum = 2
6426 09:33:22.703824 15, 0x0, sum = 3
6427 09:33:22.706542 16, 0x0, sum = 4
6428 09:33:22.707118 best_step = 14
6429 09:33:22.707480
6430 09:33:22.707870 ==
6431 09:33:22.709910 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 09:33:22.713218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 09:33:22.713677 ==
6434 09:33:22.716419 RX Vref Scan: 1
6435 09:33:22.716962
6436 09:33:22.720161 RX Vref 0 -> 0, step: 1
6437 09:33:22.720716
6438 09:33:22.721077 RX Delay -359 -> 252, step: 8
6439 09:33:22.721415
6440 09:33:22.722759 Set Vref, RX VrefLevel [Byte0]: 59
6441 09:33:22.726627 [Byte1]: 58
6442 09:33:22.731645
6443 09:33:22.732221 Final RX Vref Byte 0 = 59 to rank0
6444 09:33:22.734789 Final RX Vref Byte 1 = 58 to rank0
6445 09:33:22.738551 Final RX Vref Byte 0 = 59 to rank1
6446 09:33:22.741684 Final RX Vref Byte 1 = 58 to rank1==
6447 09:33:22.744970 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 09:33:22.752157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 09:33:22.752717 ==
6450 09:33:22.753079 DQS Delay:
6451 09:33:22.754897 DQS0 = 48, DQS1 = 60
6452 09:33:22.755453 DQM Delay:
6453 09:33:22.755851 DQM0 = 12, DQM1 = 11
6454 09:33:22.758466 DQ Delay:
6455 09:33:22.762447 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6456 09:33:22.765172 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6457 09:33:22.765729 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6458 09:33:22.771570 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6459 09:33:22.772164
6460 09:33:22.772527
6461 09:33:22.778084 [DQSOSCAuto] RK0, (LSB)MR18= 0xb97c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6462 09:33:22.781234 CH0 RK0: MR19=C0C, MR18=B97C
6463 09:33:22.787803 CH0_RK0: MR19=0xC0C, MR18=0xB97C, DQSOSC=386, MR23=63, INC=396, DEC=264
6464 09:33:22.788278 ==
6465 09:33:22.791290 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 09:33:22.794545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 09:33:22.795120 ==
6468 09:33:22.797986 [Gating] SW mode calibration
6469 09:33:22.804523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 09:33:22.811656 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 09:33:22.814672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 09:33:22.818000 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 09:33:22.824433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 09:33:22.827666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 09:33:22.830771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 09:33:22.837471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 09:33:22.840596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 09:33:22.844286 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 09:33:22.850784 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 09:33:22.851355 Total UI for P1: 0, mck2ui 16
6481 09:33:22.857732 best dqsien dly found for B0: ( 0, 14, 24)
6482 09:33:22.858288 Total UI for P1: 0, mck2ui 16
6483 09:33:22.864300 best dqsien dly found for B1: ( 0, 14, 24)
6484 09:33:22.867283 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 09:33:22.870628 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 09:33:22.871181
6487 09:33:22.873860 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 09:33:22.877411 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 09:33:22.880882 [Gating] SW calibration Done
6490 09:33:22.881342 ==
6491 09:33:22.883576 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 09:33:22.887433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 09:33:22.888051 ==
6494 09:33:22.890351 RX Vref Scan: 0
6495 09:33:22.890802
6496 09:33:22.891164 RX Vref 0 -> 0, step: 1
6497 09:33:22.894043
6498 09:33:22.894603 RX Delay -410 -> 252, step: 16
6499 09:33:22.900365 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6500 09:33:22.903857 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6501 09:33:22.906664 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6502 09:33:22.910233 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6503 09:33:22.916469 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6504 09:33:22.920149 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6505 09:33:22.923475 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6506 09:33:22.926600 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6507 09:33:22.933611 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6508 09:33:22.936617 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6509 09:33:22.940090 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6510 09:33:22.946842 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6511 09:33:22.949888 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6512 09:33:22.953478 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6513 09:33:22.956270 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6514 09:33:22.962847 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6515 09:33:22.963413 ==
6516 09:33:22.966036 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 09:33:22.969849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 09:33:22.970404 ==
6519 09:33:22.970766 DQS Delay:
6520 09:33:22.972803 DQS0 = 43, DQS1 = 59
6521 09:33:22.973259 DQM Delay:
6522 09:33:22.976266 DQM0 = 11, DQM1 = 16
6523 09:33:22.976826 DQ Delay:
6524 09:33:22.979044 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6525 09:33:22.982195 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6526 09:33:22.985803 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6527 09:33:22.989811 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6528 09:33:22.990371
6529 09:33:22.990739
6530 09:33:22.991074 ==
6531 09:33:22.992417 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 09:33:22.995916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 09:33:22.996377 ==
6534 09:33:22.998907
6535 09:33:22.999458
6536 09:33:22.999875 TX Vref Scan disable
6537 09:33:23.002303 == TX Byte 0 ==
6538 09:33:23.005637 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6539 09:33:23.008576 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6540 09:33:23.012226 == TX Byte 1 ==
6541 09:33:23.015101 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6542 09:33:23.018329 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6543 09:33:23.018791 ==
6544 09:33:23.022037 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 09:33:23.025578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 09:33:23.028443 ==
6547 09:33:23.028946
6548 09:33:23.029530
6549 09:33:23.029887 TX Vref Scan disable
6550 09:33:23.031748 == TX Byte 0 ==
6551 09:33:23.035149 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 09:33:23.038270 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 09:33:23.041527 == TX Byte 1 ==
6554 09:33:23.045143 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6555 09:33:23.048403 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6556 09:33:23.048862
6557 09:33:23.052015 [DATLAT]
6558 09:33:23.052567 Freq=400, CH0 RK1
6559 09:33:23.052934
6560 09:33:23.054819 DATLAT Default: 0xe
6561 09:33:23.055372 0, 0xFFFF, sum = 0
6562 09:33:23.058118 1, 0xFFFF, sum = 0
6563 09:33:23.058584 2, 0xFFFF, sum = 0
6564 09:33:23.061401 3, 0xFFFF, sum = 0
6565 09:33:23.061884 4, 0xFFFF, sum = 0
6566 09:33:23.064459 5, 0xFFFF, sum = 0
6567 09:33:23.064940 6, 0xFFFF, sum = 0
6568 09:33:23.068346 7, 0xFFFF, sum = 0
6569 09:33:23.068826 8, 0xFFFF, sum = 0
6570 09:33:23.071827 9, 0xFFFF, sum = 0
6571 09:33:23.072404 10, 0xFFFF, sum = 0
6572 09:33:23.075096 11, 0xFFFF, sum = 0
6573 09:33:23.077780 12, 0xFFFF, sum = 0
6574 09:33:23.078357 13, 0x0, sum = 1
6575 09:33:23.081039 14, 0x0, sum = 2
6576 09:33:23.081519 15, 0x0, sum = 3
6577 09:33:23.084089 16, 0x0, sum = 4
6578 09:33:23.084607 best_step = 14
6579 09:33:23.085080
6580 09:33:23.085527 ==
6581 09:33:23.087462 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 09:33:23.090831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 09:33:23.091306 ==
6584 09:33:23.093971 RX Vref Scan: 0
6585 09:33:23.094439
6586 09:33:23.097338 RX Vref 0 -> 0, step: 1
6587 09:33:23.097767
6588 09:33:23.098194 RX Delay -359 -> 252, step: 8
6589 09:33:23.106449 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6590 09:33:23.109990 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6591 09:33:23.113243 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6592 09:33:23.119583 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6593 09:33:23.122840 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6594 09:33:23.125733 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6595 09:33:23.129113 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6596 09:33:23.136024 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6597 09:33:23.138805 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6598 09:33:23.142452 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6599 09:33:23.146206 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6600 09:33:23.152470 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6601 09:33:23.155748 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6602 09:33:23.158700 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6603 09:33:23.161781 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6604 09:33:23.168633 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6605 09:33:23.169338 ==
6606 09:33:23.171808 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 09:33:23.175308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 09:33:23.175998 ==
6609 09:33:23.178107 DQS Delay:
6610 09:33:23.178518 DQS0 = 44, DQS1 = 60
6611 09:33:23.178904 DQM Delay:
6612 09:33:23.181694 DQM0 = 8, DQM1 = 14
6613 09:33:23.182110 DQ Delay:
6614 09:33:23.184887 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6615 09:33:23.188158 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6616 09:33:23.191478 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6617 09:33:23.195310 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6618 09:33:23.196057
6619 09:33:23.196588
6620 09:33:23.204606 [DQSOSCAuto] RK1, (LSB)MR18= 0xba45, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6621 09:33:23.205026 CH0 RK1: MR19=C0C, MR18=BA45
6622 09:33:23.211689 CH0_RK1: MR19=0xC0C, MR18=0xBA45, DQSOSC=386, MR23=63, INC=396, DEC=264
6623 09:33:23.214788 [RxdqsGatingPostProcess] freq 400
6624 09:33:23.221446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 09:33:23.224838 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 09:33:23.227907 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 09:33:23.231327 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 09:33:23.234509 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 09:33:23.235109 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 09:33:23.238284 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 09:33:23.240921 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 09:33:23.244648 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 09:33:23.247835 Pre-setting of DQS Precalculation
6634 09:33:23.254635 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 09:33:23.255150 ==
6636 09:33:23.257759 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 09:33:23.261154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 09:33:23.261570 ==
6639 09:33:23.267599 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 09:33:23.274627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6641 09:33:23.278058 [CA 0] Center 36 (8~64) winsize 57
6642 09:33:23.280770 [CA 1] Center 36 (8~64) winsize 57
6643 09:33:23.281206 [CA 2] Center 36 (8~64) winsize 57
6644 09:33:23.284185 [CA 3] Center 36 (8~64) winsize 57
6645 09:33:23.287628 [CA 4] Center 36 (8~64) winsize 57
6646 09:33:23.290666 [CA 5] Center 36 (8~64) winsize 57
6647 09:33:23.291096
6648 09:33:23.294173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6649 09:33:23.297436
6650 09:33:23.301033 [CATrainingPosCal] consider 1 rank data
6651 09:33:23.301567 u2DelayCellTimex100 = 270/100 ps
6652 09:33:23.307243 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 09:33:23.310747 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 09:33:23.314192 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 09:33:23.317519 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 09:33:23.320305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:33:23.324099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 09:33:23.324630
6659 09:33:23.327078 CA PerBit enable=1, Macro0, CA PI delay=36
6660 09:33:23.327600
6661 09:33:23.330657 [CBTSetCACLKResult] CA Dly = 36
6662 09:33:23.333587 CS Dly: 1 (0~32)
6663 09:33:23.334015 ==
6664 09:33:23.337085 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 09:33:23.340013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 09:33:23.340443 ==
6667 09:33:23.347235 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 09:33:23.350679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6669 09:33:23.353843 [CA 0] Center 36 (8~64) winsize 57
6670 09:33:23.356788 [CA 1] Center 36 (8~64) winsize 57
6671 09:33:23.360115 [CA 2] Center 36 (8~64) winsize 57
6672 09:33:23.363484 [CA 3] Center 36 (8~64) winsize 57
6673 09:33:23.366475 [CA 4] Center 36 (8~64) winsize 57
6674 09:33:23.369951 [CA 5] Center 36 (8~64) winsize 57
6675 09:33:23.370398
6676 09:33:23.373119 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6677 09:33:23.373548
6678 09:33:23.376477 [CATrainingPosCal] consider 2 rank data
6679 09:33:23.380032 u2DelayCellTimex100 = 270/100 ps
6680 09:33:23.383119 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 09:33:23.389564 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 09:33:23.393199 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 09:33:23.396992 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 09:33:23.399832 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:33:23.403205 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:33:23.403774
6687 09:33:23.406349 CA PerBit enable=1, Macro0, CA PI delay=36
6688 09:33:23.406896
6689 09:33:23.409508 [CBTSetCACLKResult] CA Dly = 36
6690 09:33:23.412710 CS Dly: 1 (0~32)
6691 09:33:23.413152
6692 09:33:23.416382 ----->DramcWriteLeveling(PI) begin...
6693 09:33:23.416967 ==
6694 09:33:23.419179 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 09:33:23.422855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 09:33:23.423389 ==
6697 09:33:23.426255 Write leveling (Byte 0): 40 => 8
6698 09:33:23.429305 Write leveling (Byte 1): 40 => 8
6699 09:33:23.432339 DramcWriteLeveling(PI) end<-----
6700 09:33:23.432752
6701 09:33:23.433077 ==
6702 09:33:23.435836 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 09:33:23.439227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 09:33:23.439802 ==
6705 09:33:23.442717 [Gating] SW mode calibration
6706 09:33:23.448850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 09:33:23.455675 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 09:33:23.459081 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 09:33:23.462909 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 09:33:23.469217 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 09:33:23.472338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 09:33:23.475481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 09:33:23.481851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 09:33:23.485498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 09:33:23.488805 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 09:33:23.495347 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 09:33:23.495945 Total UI for P1: 0, mck2ui 16
6718 09:33:23.501965 best dqsien dly found for B0: ( 0, 14, 24)
6719 09:33:23.502423 Total UI for P1: 0, mck2ui 16
6720 09:33:23.508706 best dqsien dly found for B1: ( 0, 14, 24)
6721 09:33:23.511960 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 09:33:23.515371 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 09:33:23.515961
6724 09:33:23.518529 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 09:33:23.522420 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 09:33:23.525564 [Gating] SW calibration Done
6727 09:33:23.526154 ==
6728 09:33:23.528349 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 09:33:23.532319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 09:33:23.532871 ==
6731 09:33:23.535105 RX Vref Scan: 0
6732 09:33:23.535558
6733 09:33:23.535986 RX Vref 0 -> 0, step: 1
6734 09:33:23.536329
6735 09:33:23.538405 RX Delay -410 -> 252, step: 16
6736 09:33:23.545013 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6737 09:33:23.548120 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6738 09:33:23.551796 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6739 09:33:23.554948 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6740 09:33:23.561193 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6741 09:33:23.565145 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6742 09:33:23.568679 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6743 09:33:23.572112 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6744 09:33:23.578261 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6745 09:33:23.581666 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6746 09:33:23.584484 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6747 09:33:23.587766 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6748 09:33:23.594836 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6749 09:33:23.597573 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6750 09:33:23.601457 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6751 09:33:23.608122 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6752 09:33:23.608687 ==
6753 09:33:23.611036 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 09:33:23.614801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 09:33:23.615360 ==
6756 09:33:23.615756 DQS Delay:
6757 09:33:23.618020 DQS0 = 43, DQS1 = 51
6758 09:33:23.618574 DQM Delay:
6759 09:33:23.621107 DQM0 = 12, DQM1 = 15
6760 09:33:23.621662 DQ Delay:
6761 09:33:23.624271 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6762 09:33:23.627474 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6763 09:33:23.631113 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6764 09:33:23.634236 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6765 09:33:23.634690
6766 09:33:23.635046
6767 09:33:23.635379 ==
6768 09:33:23.637370 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 09:33:23.641605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 09:33:23.642164 ==
6771 09:33:23.642530
6772 09:33:23.642864
6773 09:33:23.644678 TX Vref Scan disable
6774 09:33:23.647468 == TX Byte 0 ==
6775 09:33:23.650518 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 09:33:23.653881 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 09:33:23.657285 == TX Byte 1 ==
6778 09:33:23.660171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 09:33:23.664011 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 09:33:23.664567 ==
6781 09:33:23.666886 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 09:33:23.670374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 09:33:23.673250 ==
6784 09:33:23.673705
6785 09:33:23.674063
6786 09:33:23.674418 TX Vref Scan disable
6787 09:33:23.676436 == TX Byte 0 ==
6788 09:33:23.680800 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 09:33:23.683706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 09:33:23.686775 == TX Byte 1 ==
6791 09:33:23.690387 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 09:33:23.693693 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 09:33:23.694254
6794 09:33:23.696503 [DATLAT]
6795 09:33:23.696959 Freq=400, CH1 RK0
6796 09:33:23.697327
6797 09:33:23.700055 DATLAT Default: 0xf
6798 09:33:23.700507 0, 0xFFFF, sum = 0
6799 09:33:23.702823 1, 0xFFFF, sum = 0
6800 09:33:23.703284 2, 0xFFFF, sum = 0
6801 09:33:23.706782 3, 0xFFFF, sum = 0
6802 09:33:23.707351 4, 0xFFFF, sum = 0
6803 09:33:23.709686 5, 0xFFFF, sum = 0
6804 09:33:23.710250 6, 0xFFFF, sum = 0
6805 09:33:23.713277 7, 0xFFFF, sum = 0
6806 09:33:23.713841 8, 0xFFFF, sum = 0
6807 09:33:23.716909 9, 0xFFFF, sum = 0
6808 09:33:23.717470 10, 0xFFFF, sum = 0
6809 09:33:23.719452 11, 0xFFFF, sum = 0
6810 09:33:23.723000 12, 0xFFFF, sum = 0
6811 09:33:23.723464 13, 0x0, sum = 1
6812 09:33:23.723881 14, 0x0, sum = 2
6813 09:33:23.726248 15, 0x0, sum = 3
6814 09:33:23.726765 16, 0x0, sum = 4
6815 09:33:23.729477 best_step = 14
6816 09:33:23.729929
6817 09:33:23.730288 ==
6818 09:33:23.732432 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 09:33:23.736032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 09:33:23.736492 ==
6821 09:33:23.739885 RX Vref Scan: 1
6822 09:33:23.740439
6823 09:33:23.740807 RX Vref 0 -> 0, step: 1
6824 09:33:23.742633
6825 09:33:23.743183 RX Delay -343 -> 252, step: 8
6826 09:33:23.743552
6827 09:33:23.745594 Set Vref, RX VrefLevel [Byte0]: 46
6828 09:33:23.749004 [Byte1]: 54
6829 09:33:23.755066
6830 09:33:23.755618 Final RX Vref Byte 0 = 46 to rank0
6831 09:33:23.757714 Final RX Vref Byte 1 = 54 to rank0
6832 09:33:23.761054 Final RX Vref Byte 0 = 46 to rank1
6833 09:33:23.764429 Final RX Vref Byte 1 = 54 to rank1==
6834 09:33:23.767705 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 09:33:23.774028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 09:33:23.774486 ==
6837 09:33:23.774851 DQS Delay:
6838 09:33:23.777471 DQS0 = 44, DQS1 = 56
6839 09:33:23.778047 DQM Delay:
6840 09:33:23.778408 DQM0 = 8, DQM1 = 13
6841 09:33:23.780923 DQ Delay:
6842 09:33:23.784061 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6843 09:33:23.784522 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6844 09:33:23.787423 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6845 09:33:23.790474 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6846 09:33:23.791030
6847 09:33:23.794374
6848 09:33:23.800452 [DQSOSCAuto] RK0, (LSB)MR18= 0x956c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6849 09:33:23.803784 CH1 RK0: MR19=C0C, MR18=956C
6850 09:33:23.810360 CH1_RK0: MR19=0xC0C, MR18=0x956C, DQSOSC=391, MR23=63, INC=386, DEC=257
6851 09:33:23.810822 ==
6852 09:33:23.813581 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 09:33:23.816651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 09:33:23.817067 ==
6855 09:33:23.820036 [Gating] SW mode calibration
6856 09:33:23.826425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 09:33:23.833565 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 09:33:23.836803 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 09:33:23.840241 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 09:33:23.846767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 09:33:23.850010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 09:33:23.853151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 09:33:23.859639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 09:33:23.863128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 09:33:23.866008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 09:33:23.872780 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 09:33:23.873301 Total UI for P1: 0, mck2ui 16
6868 09:33:23.880086 best dqsien dly found for B0: ( 0, 14, 24)
6869 09:33:23.880586 Total UI for P1: 0, mck2ui 16
6870 09:33:23.885555 best dqsien dly found for B1: ( 0, 14, 24)
6871 09:33:23.888646 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 09:33:23.892141 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 09:33:23.892221
6874 09:33:23.895746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 09:33:23.898557 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 09:33:23.901770 [Gating] SW calibration Done
6877 09:33:23.901851 ==
6878 09:33:23.905208 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 09:33:23.908272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 09:33:23.908353 ==
6881 09:33:23.911807 RX Vref Scan: 0
6882 09:33:23.911887
6883 09:33:23.911951 RX Vref 0 -> 0, step: 1
6884 09:33:23.914932
6885 09:33:23.915012 RX Delay -410 -> 252, step: 16
6886 09:33:23.921533 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6887 09:33:23.925046 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6888 09:33:23.928395 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6889 09:33:23.935170 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6890 09:33:23.938255 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6891 09:33:23.941505 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6892 09:33:23.944899 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6893 09:33:23.951230 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6894 09:33:23.954510 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6895 09:33:23.958294 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6896 09:33:23.961425 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6897 09:33:23.967955 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6898 09:33:23.971141 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6899 09:33:23.974378 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6900 09:33:23.977603 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6901 09:33:23.984171 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6902 09:33:23.984252 ==
6903 09:33:23.987781 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 09:33:23.990841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 09:33:23.990922 ==
6906 09:33:23.990985 DQS Delay:
6907 09:33:23.994612 DQS0 = 51, DQS1 = 51
6908 09:33:23.994692 DQM Delay:
6909 09:33:23.997543 DQM0 = 19, DQM1 = 14
6910 09:33:23.997624 DQ Delay:
6911 09:33:24.000925 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6912 09:33:24.003984 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6913 09:33:24.007327 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6914 09:33:24.010708 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6915 09:33:24.010788
6916 09:33:24.010852
6917 09:33:24.010911 ==
6918 09:33:24.014216 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 09:33:24.017848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 09:33:24.020845 ==
6921 09:33:24.021262
6922 09:33:24.021585
6923 09:33:24.021890 TX Vref Scan disable
6924 09:33:24.025044 == TX Byte 0 ==
6925 09:33:24.027575 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6926 09:33:24.030852 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6927 09:33:24.034117 == TX Byte 1 ==
6928 09:33:24.037737 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6929 09:33:24.040598 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6930 09:33:24.041012 ==
6931 09:33:24.044434 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 09:33:24.050327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 09:33:24.050741 ==
6934 09:33:24.051066
6935 09:33:24.051369
6936 09:33:24.051660 TX Vref Scan disable
6937 09:33:24.055029 == TX Byte 0 ==
6938 09:33:24.057046 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 09:33:24.060904 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 09:33:24.063608 == TX Byte 1 ==
6941 09:33:24.067977 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 09:33:24.070526 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 09:33:24.070942
6944 09:33:24.073731 [DATLAT]
6945 09:33:24.074239 Freq=400, CH1 RK1
6946 09:33:24.074570
6947 09:33:24.077477 DATLAT Default: 0xe
6948 09:33:24.077993 0, 0xFFFF, sum = 0
6949 09:33:24.080454 1, 0xFFFF, sum = 0
6950 09:33:24.080873 2, 0xFFFF, sum = 0
6951 09:33:24.083976 3, 0xFFFF, sum = 0
6952 09:33:24.084495 4, 0xFFFF, sum = 0
6953 09:33:24.087602 5, 0xFFFF, sum = 0
6954 09:33:24.088092 6, 0xFFFF, sum = 0
6955 09:33:24.090537 7, 0xFFFF, sum = 0
6956 09:33:24.091054 8, 0xFFFF, sum = 0
6957 09:33:24.093825 9, 0xFFFF, sum = 0
6958 09:33:24.097120 10, 0xFFFF, sum = 0
6959 09:33:24.097591 11, 0xFFFF, sum = 0
6960 09:33:24.100238 12, 0xFFFF, sum = 0
6961 09:33:24.100656 13, 0x0, sum = 1
6962 09:33:24.103813 14, 0x0, sum = 2
6963 09:33:24.104343 15, 0x0, sum = 3
6964 09:33:24.104680 16, 0x0, sum = 4
6965 09:33:24.106776 best_step = 14
6966 09:33:24.107185
6967 09:33:24.107509 ==
6968 09:33:24.110057 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 09:33:24.113419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 09:33:24.113835 ==
6971 09:33:24.117514 RX Vref Scan: 0
6972 09:33:24.117924
6973 09:33:24.119822 RX Vref 0 -> 0, step: 1
6974 09:33:24.120235
6975 09:33:24.120562 RX Delay -343 -> 252, step: 8
6976 09:33:24.128439 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6977 09:33:24.132029 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6978 09:33:24.135076 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6979 09:33:24.141484 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6980 09:33:24.145012 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6981 09:33:24.148326 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6982 09:33:24.151697 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6983 09:33:24.158320 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6984 09:33:24.161267 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6985 09:33:24.164578 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6986 09:33:24.168139 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6987 09:33:24.174753 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6988 09:33:24.178053 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6989 09:33:24.181612 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6990 09:33:24.184481 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6991 09:33:24.191342 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6992 09:33:24.191791 ==
6993 09:33:24.194529 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 09:33:24.197753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 09:33:24.198239 ==
6996 09:33:24.198733 DQS Delay:
6997 09:33:24.201217 DQS0 = 48, DQS1 = 56
6998 09:33:24.201728 DQM Delay:
6999 09:33:24.204851 DQM0 = 13, DQM1 = 11
7000 09:33:24.205262 DQ Delay:
7001 09:33:24.207454 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7002 09:33:24.211863 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7003 09:33:24.214436 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7004 09:33:24.217614 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7005 09:33:24.218151
7006 09:33:24.218487
7007 09:33:24.227308 [DQSOSCAuto] RK1, (LSB)MR18= 0x6555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7008 09:33:24.227848 CH1 RK1: MR19=C0C, MR18=6555
7009 09:33:24.233921 CH1_RK1: MR19=0xC0C, MR18=0x6555, DQSOSC=397, MR23=63, INC=374, DEC=249
7010 09:33:24.238127 [RxdqsGatingPostProcess] freq 400
7011 09:33:24.244334 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 09:33:24.247529 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 09:33:24.250741 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 09:33:24.253852 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 09:33:24.257791 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 09:33:24.260322 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 09:33:24.260755 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 09:33:24.264086 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 09:33:24.267205 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 09:33:24.270388 Pre-setting of DQS Precalculation
7021 09:33:24.276825 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 09:33:24.283388 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 09:33:24.290616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 09:33:24.291089
7025 09:33:24.291415
7026 09:33:24.293358 [Calibration Summary] 800 Mbps
7027 09:33:24.296968 CH 0, Rank 0
7028 09:33:24.297377 SW Impedance : PASS
7029 09:33:24.300061 DUTY Scan : NO K
7030 09:33:24.300471 ZQ Calibration : PASS
7031 09:33:24.303429 Jitter Meter : NO K
7032 09:33:24.306700 CBT Training : PASS
7033 09:33:24.307114 Write leveling : PASS
7034 09:33:24.310255 RX DQS gating : PASS
7035 09:33:24.313740 RX DQ/DQS(RDDQC) : PASS
7036 09:33:24.314153 TX DQ/DQS : PASS
7037 09:33:24.316775 RX DATLAT : PASS
7038 09:33:24.319604 RX DQ/DQS(Engine): PASS
7039 09:33:24.319684 TX OE : NO K
7040 09:33:24.322908 All Pass.
7041 09:33:24.323013
7042 09:33:24.323103 CH 0, Rank 1
7043 09:33:24.326325 SW Impedance : PASS
7044 09:33:24.326405 DUTY Scan : NO K
7045 09:33:24.329664 ZQ Calibration : PASS
7046 09:33:24.333134 Jitter Meter : NO K
7047 09:33:24.333214 CBT Training : PASS
7048 09:33:24.336356 Write leveling : NO K
7049 09:33:24.339654 RX DQS gating : PASS
7050 09:33:24.339778 RX DQ/DQS(RDDQC) : PASS
7051 09:33:24.343027 TX DQ/DQS : PASS
7052 09:33:24.345733 RX DATLAT : PASS
7053 09:33:24.345808 RX DQ/DQS(Engine): PASS
7054 09:33:24.349794 TX OE : NO K
7055 09:33:24.349864 All Pass.
7056 09:33:24.349924
7057 09:33:24.352667 CH 1, Rank 0
7058 09:33:24.352735 SW Impedance : PASS
7059 09:33:24.356005 DUTY Scan : NO K
7060 09:33:24.358952 ZQ Calibration : PASS
7061 09:33:24.359047 Jitter Meter : NO K
7062 09:33:24.362322 CBT Training : PASS
7063 09:33:24.365967 Write leveling : PASS
7064 09:33:24.366041 RX DQS gating : PASS
7065 09:33:24.368859 RX DQ/DQS(RDDQC) : PASS
7066 09:33:24.372229 TX DQ/DQS : PASS
7067 09:33:24.372297 RX DATLAT : PASS
7068 09:33:24.375319 RX DQ/DQS(Engine): PASS
7069 09:33:24.375415 TX OE : NO K
7070 09:33:24.378908 All Pass.
7071 09:33:24.378980
7072 09:33:24.379039 CH 1, Rank 1
7073 09:33:24.382114 SW Impedance : PASS
7074 09:33:24.385265 DUTY Scan : NO K
7075 09:33:24.385339 ZQ Calibration : PASS
7076 09:33:24.388295 Jitter Meter : NO K
7077 09:33:24.388389 CBT Training : PASS
7078 09:33:24.391755 Write leveling : NO K
7079 09:33:24.394914 RX DQS gating : PASS
7080 09:33:24.394988 RX DQ/DQS(RDDQC) : PASS
7081 09:33:24.398739 TX DQ/DQS : PASS
7082 09:33:24.401771 RX DATLAT : PASS
7083 09:33:24.401843 RX DQ/DQS(Engine): PASS
7084 09:33:24.405729 TX OE : NO K
7085 09:33:24.405809 All Pass.
7086 09:33:24.405873
7087 09:33:24.408310 DramC Write-DBI off
7088 09:33:24.411532 PER_BANK_REFRESH: Hybrid Mode
7089 09:33:24.411612 TX_TRACKING: ON
7090 09:33:24.421789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 09:33:24.424623 [FAST_K] Save calibration result to emmc
7092 09:33:24.427899 dramc_set_vcore_voltage set vcore to 725000
7093 09:33:24.431371 Read voltage for 1600, 0
7094 09:33:24.431452 Vio18 = 0
7095 09:33:24.434881 Vcore = 725000
7096 09:33:24.434961 Vdram = 0
7097 09:33:24.435024 Vddq = 0
7098 09:33:24.435082 Vmddr = 0
7099 09:33:24.441371 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 09:33:24.448224 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 09:33:24.448304 MEM_TYPE=3, freq_sel=13
7102 09:33:24.451405 sv_algorithm_assistance_LP4_3733
7103 09:33:24.454680 ============ PULL DRAM RESETB DOWN ============
7104 09:33:24.461413 ========== PULL DRAM RESETB DOWN end =========
7105 09:33:24.464622 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 09:33:24.468051 ===================================
7107 09:33:24.471380 LPDDR4 DRAM CONFIGURATION
7108 09:33:24.474959 ===================================
7109 09:33:24.475161 EX_ROW_EN[0] = 0x0
7110 09:33:24.477896 EX_ROW_EN[1] = 0x0
7111 09:33:24.478109 LP4Y_EN = 0x0
7112 09:33:24.481261 WORK_FSP = 0x1
7113 09:33:24.481475 WL = 0x5
7114 09:33:24.484814 RL = 0x5
7115 09:33:24.487986 BL = 0x2
7116 09:33:24.488244 RPST = 0x0
7117 09:33:24.491567 RD_PRE = 0x0
7118 09:33:24.491820 WR_PRE = 0x1
7119 09:33:24.495058 WR_PST = 0x1
7120 09:33:24.495341 DBI_WR = 0x0
7121 09:33:24.497963 DBI_RD = 0x0
7122 09:33:24.498290 OTF = 0x1
7123 09:33:24.501384 ===================================
7124 09:33:24.504920 ===================================
7125 09:33:24.508201 ANA top config
7126 09:33:24.511681 ===================================
7127 09:33:24.512208 DLL_ASYNC_EN = 0
7128 09:33:24.515026 ALL_SLAVE_EN = 0
7129 09:33:24.518438 NEW_RANK_MODE = 1
7130 09:33:24.521615 DLL_IDLE_MODE = 1
7131 09:33:24.522173 LP45_APHY_COMB_EN = 1
7132 09:33:24.524855 TX_ODT_DIS = 0
7133 09:33:24.527664 NEW_8X_MODE = 1
7134 09:33:24.531091 ===================================
7135 09:33:24.534330 ===================================
7136 09:33:24.537851 data_rate = 3200
7137 09:33:24.540844 CKR = 1
7138 09:33:24.544457 DQ_P2S_RATIO = 8
7139 09:33:24.547601 ===================================
7140 09:33:24.548250 CA_P2S_RATIO = 8
7141 09:33:24.550927 DQ_CA_OPEN = 0
7142 09:33:24.554410 DQ_SEMI_OPEN = 0
7143 09:33:24.557261 CA_SEMI_OPEN = 0
7144 09:33:24.561179 CA_FULL_RATE = 0
7145 09:33:24.564055 DQ_CKDIV4_EN = 0
7146 09:33:24.564512 CA_CKDIV4_EN = 0
7147 09:33:24.567316 CA_PREDIV_EN = 0
7148 09:33:24.570516 PH8_DLY = 12
7149 09:33:24.574042 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 09:33:24.577206 DQ_AAMCK_DIV = 4
7151 09:33:24.580377 CA_AAMCK_DIV = 4
7152 09:33:24.583848 CA_ADMCK_DIV = 4
7153 09:33:24.584308 DQ_TRACK_CA_EN = 0
7154 09:33:24.586675 CA_PICK = 1600
7155 09:33:24.589967 CA_MCKIO = 1600
7156 09:33:24.593719 MCKIO_SEMI = 0
7157 09:33:24.597066 PLL_FREQ = 3068
7158 09:33:24.600302 DQ_UI_PI_RATIO = 32
7159 09:33:24.603568 CA_UI_PI_RATIO = 0
7160 09:33:24.606858 ===================================
7161 09:33:24.609937 ===================================
7162 09:33:24.610352 memory_type:LPDDR4
7163 09:33:24.613147 GP_NUM : 10
7164 09:33:24.616881 SRAM_EN : 1
7165 09:33:24.617292 MD32_EN : 0
7166 09:33:24.619554 ===================================
7167 09:33:24.623288 [ANA_INIT] >>>>>>>>>>>>>>
7168 09:33:24.626852 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 09:33:24.629609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 09:33:24.633428 ===================================
7171 09:33:24.636156 data_rate = 3200,PCW = 0X7600
7172 09:33:24.640427 ===================================
7173 09:33:24.643060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 09:33:24.646564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 09:33:24.652969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 09:33:24.656281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 09:33:24.659859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 09:33:24.666565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 09:33:24.667092 [ANA_INIT] flow start
7180 09:33:24.669681 [ANA_INIT] PLL >>>>>>>>
7181 09:33:24.672998 [ANA_INIT] PLL <<<<<<<<
7182 09:33:24.673475 [ANA_INIT] MIDPI >>>>>>>>
7183 09:33:24.676589 [ANA_INIT] MIDPI <<<<<<<<
7184 09:33:24.679271 [ANA_INIT] DLL >>>>>>>>
7185 09:33:24.679694 [ANA_INIT] DLL <<<<<<<<
7186 09:33:24.682736 [ANA_INIT] flow end
7187 09:33:24.685996 ============ LP4 DIFF to SE enter ============
7188 09:33:24.689484 ============ LP4 DIFF to SE exit ============
7189 09:33:24.692533 [ANA_INIT] <<<<<<<<<<<<<
7190 09:33:24.695967 [Flow] Enable top DCM control >>>>>
7191 09:33:24.698923 [Flow] Enable top DCM control <<<<<
7192 09:33:24.702796 Enable DLL master slave shuffle
7193 09:33:24.709007 ==============================================================
7194 09:33:24.709595 Gating Mode config
7195 09:33:24.715394 ==============================================================
7196 09:33:24.718958 Config description:
7197 09:33:24.725562 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 09:33:24.731838 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 09:33:24.738567 SELPH_MODE 0: By rank 1: By Phase
7200 09:33:24.745166 ==============================================================
7201 09:33:24.748865 GAT_TRACK_EN = 1
7202 09:33:24.749382 RX_GATING_MODE = 2
7203 09:33:24.751962 RX_GATING_TRACK_MODE = 2
7204 09:33:24.755622 SELPH_MODE = 1
7205 09:33:24.758318 PICG_EARLY_EN = 1
7206 09:33:24.761586 VALID_LAT_VALUE = 1
7207 09:33:24.768445 ==============================================================
7208 09:33:24.771280 Enter into Gating configuration >>>>
7209 09:33:24.775029 Exit from Gating configuration <<<<
7210 09:33:24.778213 Enter into DVFS_PRE_config >>>>>
7211 09:33:24.787889 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 09:33:24.791427 Exit from DVFS_PRE_config <<<<<
7213 09:33:24.794532 Enter into PICG configuration >>>>
7214 09:33:24.799256 Exit from PICG configuration <<<<
7215 09:33:24.801818 [RX_INPUT] configuration >>>>>
7216 09:33:24.804565 [RX_INPUT] configuration <<<<<
7217 09:33:24.808001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 09:33:24.814619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 09:33:24.820826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 09:33:24.827848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 09:33:24.834039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 09:33:24.837095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 09:33:24.843889 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 09:33:24.847222 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 09:33:24.850530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 09:33:24.853941 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 09:33:24.860932 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 09:33:24.863880 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 09:33:24.867227 ===================================
7230 09:33:24.870398 LPDDR4 DRAM CONFIGURATION
7231 09:33:24.873733 ===================================
7232 09:33:24.874304 EX_ROW_EN[0] = 0x0
7233 09:33:24.877136 EX_ROW_EN[1] = 0x0
7234 09:33:24.877590 LP4Y_EN = 0x0
7235 09:33:24.880243 WORK_FSP = 0x1
7236 09:33:24.880698 WL = 0x5
7237 09:33:24.883563 RL = 0x5
7238 09:33:24.884146 BL = 0x2
7239 09:33:24.886844 RPST = 0x0
7240 09:33:24.889784 RD_PRE = 0x0
7241 09:33:24.890238 WR_PRE = 0x1
7242 09:33:24.892998 WR_PST = 0x1
7243 09:33:24.893455 DBI_WR = 0x0
7244 09:33:24.896318 DBI_RD = 0x0
7245 09:33:24.896773 OTF = 0x1
7246 09:33:24.900103 ===================================
7247 09:33:24.903358 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 09:33:24.909942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 09:33:24.913315 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 09:33:24.916752 ===================================
7251 09:33:24.919938 LPDDR4 DRAM CONFIGURATION
7252 09:33:24.922917 ===================================
7253 09:33:24.923465 EX_ROW_EN[0] = 0x10
7254 09:33:24.926460 EX_ROW_EN[1] = 0x0
7255 09:33:24.927018 LP4Y_EN = 0x0
7256 09:33:24.929829 WORK_FSP = 0x1
7257 09:33:24.930284 WL = 0x5
7258 09:33:24.932942 RL = 0x5
7259 09:33:24.933496 BL = 0x2
7260 09:33:24.936716 RPST = 0x0
7261 09:33:24.937272 RD_PRE = 0x0
7262 09:33:24.939491 WR_PRE = 0x1
7263 09:33:24.942795 WR_PST = 0x1
7264 09:33:24.943249 DBI_WR = 0x0
7265 09:33:24.946468 DBI_RD = 0x0
7266 09:33:24.947078 OTF = 0x1
7267 09:33:24.949586 ===================================
7268 09:33:24.955820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 09:33:24.956282 ==
7270 09:33:24.959657 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 09:33:24.962886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 09:33:24.963440 ==
7273 09:33:24.966162 [Duty_Offset_Calibration]
7274 09:33:24.969173 B0:1 B1:-1 CA:0
7275 09:33:24.969642
7276 09:33:24.972713 [DutyScan_Calibration_Flow] k_type=0
7277 09:33:24.981113
7278 09:33:24.981665 ==CLK 0==
7279 09:33:24.984613 Final CLK duty delay cell = 0
7280 09:33:24.987869 [0] MAX Duty = 5124%(X100), DQS PI = 22
7281 09:33:24.991114 [0] MIN Duty = 4907%(X100), DQS PI = 6
7282 09:33:24.991631 [0] AVG Duty = 5015%(X100)
7283 09:33:24.994279
7284 09:33:24.997659 CH0 CLK Duty spec in!! Max-Min= 217%
7285 09:33:25.001210 [DutyScan_Calibration_Flow] ====Done====
7286 09:33:25.001768
7287 09:33:25.004396 [DutyScan_Calibration_Flow] k_type=1
7288 09:33:25.020392
7289 09:33:25.020939 ==DQS 0 ==
7290 09:33:25.023822 Final DQS duty delay cell = -4
7291 09:33:25.026776 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7292 09:33:25.029656 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7293 09:33:25.033353 [-4] AVG Duty = 4906%(X100)
7294 09:33:25.033804
7295 09:33:25.034155 ==DQS 1 ==
7296 09:33:25.037462 Final DQS duty delay cell = 0
7297 09:33:25.039571 [0] MAX Duty = 5156%(X100), DQS PI = 2
7298 09:33:25.043229 [0] MIN Duty = 5031%(X100), DQS PI = 16
7299 09:33:25.046311 [0] AVG Duty = 5093%(X100)
7300 09:33:25.046726
7301 09:33:25.049456 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7302 09:33:25.049868
7303 09:33:25.053228 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7304 09:33:25.056375 [DutyScan_Calibration_Flow] ====Done====
7305 09:33:25.057070
7306 09:33:25.059597 [DutyScan_Calibration_Flow] k_type=3
7307 09:33:25.077708
7308 09:33:25.078226 ==DQM 0 ==
7309 09:33:25.080713 Final DQM duty delay cell = 0
7310 09:33:25.084322 [0] MAX Duty = 5124%(X100), DQS PI = 20
7311 09:33:25.087364 [0] MIN Duty = 4907%(X100), DQS PI = 8
7312 09:33:25.087940 [0] AVG Duty = 5015%(X100)
7313 09:33:25.091259
7314 09:33:25.091854 ==DQM 1 ==
7315 09:33:25.094263 Final DQM duty delay cell = 0
7316 09:33:25.097923 [0] MAX Duty = 5000%(X100), DQS PI = 6
7317 09:33:25.101159 [0] MIN Duty = 4782%(X100), DQS PI = 22
7318 09:33:25.104431 [0] AVG Duty = 4891%(X100)
7319 09:33:25.104880
7320 09:33:25.107574 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7321 09:33:25.108105
7322 09:33:25.110743 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7323 09:33:25.114049 [DutyScan_Calibration_Flow] ====Done====
7324 09:33:25.114644
7325 09:33:25.116984 [DutyScan_Calibration_Flow] k_type=2
7326 09:33:25.134529
7327 09:33:25.135076 ==DQ 0 ==
7328 09:33:25.137820 Final DQ duty delay cell = -4
7329 09:33:25.140477 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7330 09:33:25.143836 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7331 09:33:25.147682 [-4] AVG Duty = 4953%(X100)
7332 09:33:25.148284
7333 09:33:25.148646 ==DQ 1 ==
7334 09:33:25.150303 Final DQ duty delay cell = 0
7335 09:33:25.154012 [0] MAX Duty = 5125%(X100), DQS PI = 2
7336 09:33:25.156751 [0] MIN Duty = 5000%(X100), DQS PI = 36
7337 09:33:25.160068 [0] AVG Duty = 5062%(X100)
7338 09:33:25.160518
7339 09:33:25.163822 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7340 09:33:25.164387
7341 09:33:25.166988 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7342 09:33:25.170003 [DutyScan_Calibration_Flow] ====Done====
7343 09:33:25.170456 ==
7344 09:33:25.173965 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 09:33:25.176725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 09:33:25.177283 ==
7347 09:33:25.179862 [Duty_Offset_Calibration]
7348 09:33:25.180316 B0:-1 B1:1 CA:2
7349 09:33:25.180672
7350 09:33:25.183697 [DutyScan_Calibration_Flow] k_type=0
7351 09:33:25.194278
7352 09:33:25.194810 ==CLK 0==
7353 09:33:25.197803 Final CLK duty delay cell = 0
7354 09:33:25.201200 [0] MAX Duty = 5187%(X100), DQS PI = 22
7355 09:33:25.204616 [0] MIN Duty = 5031%(X100), DQS PI = 14
7356 09:33:25.205165 [0] AVG Duty = 5109%(X100)
7357 09:33:25.207598
7358 09:33:25.210664 CH1 CLK Duty spec in!! Max-Min= 156%
7359 09:33:25.214542 [DutyScan_Calibration_Flow] ====Done====
7360 09:33:25.215096
7361 09:33:25.217608 [DutyScan_Calibration_Flow] k_type=1
7362 09:33:25.234151
7363 09:33:25.234698 ==DQS 0 ==
7364 09:33:25.237511 Final DQS duty delay cell = 0
7365 09:33:25.241109 [0] MAX Duty = 5156%(X100), DQS PI = 20
7366 09:33:25.244454 [0] MIN Duty = 4907%(X100), DQS PI = 42
7367 09:33:25.247555 [0] AVG Duty = 5031%(X100)
7368 09:33:25.248155
7369 09:33:25.248517 ==DQS 1 ==
7370 09:33:25.250872 Final DQS duty delay cell = 0
7371 09:33:25.254388 [0] MAX Duty = 5093%(X100), DQS PI = 6
7372 09:33:25.258040 [0] MIN Duty = 4969%(X100), DQS PI = 26
7373 09:33:25.260870 [0] AVG Duty = 5031%(X100)
7374 09:33:25.261416
7375 09:33:25.263777 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7376 09:33:25.264237
7377 09:33:25.267774 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7378 09:33:25.270516 [DutyScan_Calibration_Flow] ====Done====
7379 09:33:25.271073
7380 09:33:25.273566 [DutyScan_Calibration_Flow] k_type=3
7381 09:33:25.291055
7382 09:33:25.291591 ==DQM 0 ==
7383 09:33:25.294043 Final DQM duty delay cell = 0
7384 09:33:25.297968 [0] MAX Duty = 5218%(X100), DQS PI = 6
7385 09:33:25.300756 [0] MIN Duty = 5031%(X100), DQS PI = 40
7386 09:33:25.304726 [0] AVG Duty = 5124%(X100)
7387 09:33:25.305400
7388 09:33:25.305769 ==DQM 1 ==
7389 09:33:25.307999 Final DQM duty delay cell = 0
7390 09:33:25.310787 [0] MAX Duty = 5187%(X100), DQS PI = 34
7391 09:33:25.314011 [0] MIN Duty = 4969%(X100), DQS PI = 2
7392 09:33:25.317278 [0] AVG Duty = 5078%(X100)
7393 09:33:25.317738
7394 09:33:25.320327 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7395 09:33:25.320913
7396 09:33:25.324202 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7397 09:33:25.327543 [DutyScan_Calibration_Flow] ====Done====
7398 09:33:25.328148
7399 09:33:25.330445 [DutyScan_Calibration_Flow] k_type=2
7400 09:33:25.347864
7401 09:33:25.348409 ==DQ 0 ==
7402 09:33:25.351413 Final DQ duty delay cell = 0
7403 09:33:25.354769 [0] MAX Duty = 5156%(X100), DQS PI = 0
7404 09:33:25.357823 [0] MIN Duty = 4906%(X100), DQS PI = 42
7405 09:33:25.358336 [0] AVG Duty = 5031%(X100)
7406 09:33:25.361035
7407 09:33:25.361447 ==DQ 1 ==
7408 09:33:25.364198 Final DQ duty delay cell = 0
7409 09:33:25.367414 [0] MAX Duty = 5156%(X100), DQS PI = 42
7410 09:33:25.370976 [0] MIN Duty = 4969%(X100), DQS PI = 28
7411 09:33:25.371389 [0] AVG Duty = 5062%(X100)
7412 09:33:25.374048
7413 09:33:25.377446 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7414 09:33:25.377857
7415 09:33:25.380610 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7416 09:33:25.384240 [DutyScan_Calibration_Flow] ====Done====
7417 09:33:25.387105 nWR fixed to 30
7418 09:33:25.387684 [ModeRegInit_LP4] CH0 RK0
7419 09:33:25.390334 [ModeRegInit_LP4] CH0 RK1
7420 09:33:25.393683 [ModeRegInit_LP4] CH1 RK0
7421 09:33:25.397231 [ModeRegInit_LP4] CH1 RK1
7422 09:33:25.397739 match AC timing 5
7423 09:33:25.403874 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 09:33:25.406848 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 09:33:25.410662 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 09:33:25.416970 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 09:33:25.420293 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 09:33:25.420741 [MiockJmeterHQA]
7429 09:33:25.421107
7430 09:33:25.423899 [DramcMiockJmeter] u1RxGatingPI = 0
7431 09:33:25.426622 0 : 4253, 4026
7432 09:33:25.427160 4 : 4253, 4027
7433 09:33:25.430014 8 : 4370, 4142
7434 09:33:25.430432 12 : 4368, 4140
7435 09:33:25.433219 16 : 4257, 4029
7436 09:33:25.433640 20 : 4252, 4027
7437 09:33:25.433974 24 : 4253, 4026
7438 09:33:25.436852 28 : 4253, 4026
7439 09:33:25.437373 32 : 4252, 4027
7440 09:33:25.439960 36 : 4260, 4032
7441 09:33:25.440482 40 : 4363, 4137
7442 09:33:25.443244 44 : 4252, 4027
7443 09:33:25.443875 48 : 4253, 4026
7444 09:33:25.447057 52 : 4252, 4027
7445 09:33:25.447574 56 : 4255, 4030
7446 09:33:25.448029 60 : 4254, 4029
7447 09:33:25.450068 64 : 4360, 4138
7448 09:33:25.450592 68 : 4361, 4137
7449 09:33:25.453060 72 : 4250, 4027
7450 09:33:25.453479 76 : 4250, 4027
7451 09:33:25.456390 80 : 4250, 4026
7452 09:33:25.456808 84 : 4253, 4029
7453 09:33:25.459936 88 : 4253, 4029
7454 09:33:25.460352 92 : 4361, 732
7455 09:33:25.460684 96 : 4252, 0
7456 09:33:25.463154 100 : 4253, 0
7457 09:33:25.463570 104 : 4360, 0
7458 09:33:25.466416 108 : 4250, 0
7459 09:33:25.466838 112 : 4250, 0
7460 09:33:25.467169 116 : 4250, 0
7461 09:33:25.469708 120 : 4250, 0
7462 09:33:25.470230 124 : 4363, 0
7463 09:33:25.472530 128 : 4252, 0
7464 09:33:25.472947 132 : 4250, 0
7465 09:33:25.473279 136 : 4252, 0
7466 09:33:25.476032 140 : 4250, 0
7467 09:33:25.476453 144 : 4361, 0
7468 09:33:25.476785 148 : 4361, 0
7469 09:33:25.479289 152 : 4250, 0
7470 09:33:25.479706 156 : 4250, 0
7471 09:33:25.482668 160 : 4250, 0
7472 09:33:25.483187 164 : 4250, 0
7473 09:33:25.483525 168 : 4250, 0
7474 09:33:25.486025 172 : 4250, 0
7475 09:33:25.486443 176 : 4252, 0
7476 09:33:25.489437 180 : 4250, 0
7477 09:33:25.489957 184 : 4250, 0
7478 09:33:25.490291 188 : 4253, 0
7479 09:33:25.492949 192 : 4360, 0
7480 09:33:25.493368 196 : 4361, 0
7481 09:33:25.495468 200 : 4364, 0
7482 09:33:25.496053 204 : 4250, 0
7483 09:33:25.496398 208 : 4250, 0
7484 09:33:25.499122 212 : 4250, 0
7485 09:33:25.499542 216 : 4253, 0
7486 09:33:25.502079 220 : 4250, 0
7487 09:33:25.502497 224 : 4250, 125
7488 09:33:25.505815 228 : 4250, 3125
7489 09:33:25.506361 232 : 4250, 4026
7490 09:33:25.506701 236 : 4361, 4137
7491 09:33:25.509017 240 : 4250, 4026
7492 09:33:25.509534 244 : 4252, 4027
7493 09:33:25.512094 248 : 4250, 4027
7494 09:33:25.512514 252 : 4253, 4029
7495 09:33:25.515602 256 : 4250, 4027
7496 09:33:25.516080 260 : 4250, 4027
7497 09:33:25.518674 264 : 4360, 4138
7498 09:33:25.519088 268 : 4250, 4027
7499 09:33:25.521970 272 : 4250, 4026
7500 09:33:25.522387 276 : 4360, 4137
7501 09:33:25.525680 280 : 4250, 4027
7502 09:33:25.526223 284 : 4250, 4027
7503 09:33:25.528627 288 : 4364, 4140
7504 09:33:25.529044 292 : 4250, 4027
7505 09:33:25.532128 296 : 4250, 4027
7506 09:33:25.532646 300 : 4250, 4027
7507 09:33:25.532980 304 : 4252, 4029
7508 09:33:25.535374 308 : 4250, 4026
7509 09:33:25.535937 312 : 4250, 4027
7510 09:33:25.538645 316 : 4360, 4137
7511 09:33:25.539067 320 : 4249, 4027
7512 09:33:25.541814 324 : 4250, 4026
7513 09:33:25.542236 328 : 4361, 4137
7514 09:33:25.545008 332 : 4250, 4027
7515 09:33:25.545534 336 : 4249, 3929
7516 09:33:25.548186 340 : 4363, 2151
7517 09:33:25.548609
7518 09:33:25.548934 MIOCK jitter meter ch=0
7519 09:33:25.551577
7520 09:33:25.552106 1T = (340-92) = 248 dly cells
7521 09:33:25.558234 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7522 09:33:25.558760 ==
7523 09:33:25.561269 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 09:33:25.565009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 09:33:25.565424 ==
7526 09:33:25.571906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 09:33:25.574492 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 09:33:25.581246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 09:33:25.584668 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 09:33:25.595454 [CA 0] Center 43 (13~74) winsize 62
7531 09:33:25.598357 [CA 1] Center 43 (13~74) winsize 62
7532 09:33:25.601559 [CA 2] Center 39 (10~69) winsize 60
7533 09:33:25.604773 [CA 3] Center 38 (9~68) winsize 60
7534 09:33:25.608377 [CA 4] Center 37 (8~66) winsize 59
7535 09:33:25.611976 [CA 5] Center 36 (7~66) winsize 60
7536 09:33:25.612530
7537 09:33:25.615141 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 09:33:25.615700
7539 09:33:25.618363 [CATrainingPosCal] consider 1 rank data
7540 09:33:25.621733 u2DelayCellTimex100 = 262/100 ps
7541 09:33:25.627914 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7542 09:33:25.631257 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7543 09:33:25.634534 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7544 09:33:25.637987 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7545 09:33:25.640872 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7546 09:33:25.644312 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7547 09:33:25.644772
7548 09:33:25.647537 CA PerBit enable=1, Macro0, CA PI delay=36
7549 09:33:25.648062
7550 09:33:25.651033 [CBTSetCACLKResult] CA Dly = 36
7551 09:33:25.654543 CS Dly: 11 (0~42)
7552 09:33:25.657823 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 09:33:25.660825 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 09:33:25.661284 ==
7555 09:33:25.663901 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 09:33:25.671186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 09:33:25.671800 ==
7558 09:33:25.673958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 09:33:25.681150 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 09:33:25.683871 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 09:33:25.690701 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 09:33:25.698889 [CA 0] Center 43 (13~74) winsize 62
7563 09:33:25.701616 [CA 1] Center 44 (14~74) winsize 61
7564 09:33:25.705542 [CA 2] Center 38 (9~68) winsize 60
7565 09:33:25.708252 [CA 3] Center 38 (9~68) winsize 60
7566 09:33:25.711510 [CA 4] Center 36 (7~66) winsize 60
7567 09:33:25.715248 [CA 5] Center 36 (6~66) winsize 61
7568 09:33:25.715847
7569 09:33:25.718393 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 09:33:25.718847
7571 09:33:25.724884 [CATrainingPosCal] consider 2 rank data
7572 09:33:25.725444 u2DelayCellTimex100 = 262/100 ps
7573 09:33:25.731148 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7574 09:33:25.734881 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7575 09:33:25.737978 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7576 09:33:25.741447 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7577 09:33:25.744538 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7578 09:33:25.748120 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7579 09:33:25.748733
7580 09:33:25.751217 CA PerBit enable=1, Macro0, CA PI delay=36
7581 09:33:25.751674
7582 09:33:25.755042 [CBTSetCACLKResult] CA Dly = 36
7583 09:33:25.758370 CS Dly: 11 (0~43)
7584 09:33:25.762086 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 09:33:25.764197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 09:33:25.764654
7587 09:33:25.767278 ----->DramcWriteLeveling(PI) begin...
7588 09:33:25.771403 ==
7589 09:33:25.771996 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 09:33:25.777569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 09:33:25.778128 ==
7592 09:33:25.780918 Write leveling (Byte 0): 36 => 36
7593 09:33:25.784101 Write leveling (Byte 1): 28 => 28
7594 09:33:25.787106 DramcWriteLeveling(PI) end<-----
7595 09:33:25.787563
7596 09:33:25.787968 ==
7597 09:33:25.790525 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 09:33:25.793822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 09:33:25.794283 ==
7600 09:33:25.797073 [Gating] SW mode calibration
7601 09:33:25.804468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 09:33:25.810899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 09:33:25.814273 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 09:33:25.816972 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 09:33:25.823876 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 09:33:25.827160 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7607 09:33:25.830275 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 09:33:25.837360 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7609 09:33:25.840649 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 09:33:25.843872 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 09:33:25.850167 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 09:33:25.853261 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 09:33:25.856267 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 09:33:25.863115 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7615 09:33:25.866658 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7616 09:33:25.870027 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7617 09:33:25.876744 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7618 09:33:25.879918 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 09:33:25.883832 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 09:33:25.886888 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 09:33:25.893197 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 09:33:25.896732 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
7623 09:33:25.900102 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7624 09:33:25.906523 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7625 09:33:25.909509 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7626 09:33:25.912968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 09:33:25.919587 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 09:33:25.922991 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 09:33:25.925963 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 09:33:25.932856 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 09:33:25.935829 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7632 09:33:25.939050 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 09:33:25.945714 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 09:33:25.949197 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 09:33:25.952980 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 09:33:25.959292 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 09:33:25.962759 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 09:33:25.966267 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 09:33:25.972681 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 09:33:25.975617 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 09:33:25.978964 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 09:33:25.985140 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 09:33:25.988098 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 09:33:25.991663 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 09:33:25.998314 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 09:33:26.001598 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 09:33:26.005064 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 09:33:26.008385 Total UI for P1: 0, mck2ui 16
7649 09:33:26.011182 best dqsien dly found for B0: ( 1, 9, 10)
7650 09:33:26.017909 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 09:33:26.021704 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 09:33:26.025229 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 09:33:26.027828 Total UI for P1: 0, mck2ui 16
7654 09:33:26.031466 best dqsien dly found for B1: ( 1, 9, 22)
7655 09:33:26.034521 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 09:33:26.037726 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7657 09:33:26.040979
7658 09:33:26.044481 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 09:33:26.047987 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7660 09:33:26.050833 [Gating] SW calibration Done
7661 09:33:26.050913 ==
7662 09:33:26.054107 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 09:33:26.057699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 09:33:26.057781 ==
7665 09:33:26.060848 RX Vref Scan: 0
7666 09:33:26.060928
7667 09:33:26.060991 RX Vref 0 -> 0, step: 1
7668 09:33:26.061050
7669 09:33:26.064199 RX Delay 0 -> 252, step: 8
7670 09:33:26.067350 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7671 09:33:26.070662 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7672 09:33:26.077167 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7673 09:33:26.080469 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7674 09:33:26.084045 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7675 09:33:26.087514 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7676 09:33:26.090639 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7677 09:33:26.097045 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7678 09:33:26.100315 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7679 09:33:26.104121 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7680 09:33:26.107415 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7681 09:33:26.113668 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7682 09:33:26.117526 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 09:33:26.121122 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7684 09:33:26.123618 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7685 09:33:26.127187 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7686 09:33:26.130222 ==
7687 09:33:26.130398 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 09:33:26.136676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 09:33:26.136894 ==
7690 09:33:26.137033 DQS Delay:
7691 09:33:26.140020 DQS0 = 0, DQS1 = 0
7692 09:33:26.140209 DQM Delay:
7693 09:33:26.143461 DQM0 = 134, DQM1 = 126
7694 09:33:26.143715 DQ Delay:
7695 09:33:26.147564 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7696 09:33:26.150699 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7697 09:33:26.153672 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7698 09:33:26.157085 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7699 09:33:26.157415
7700 09:33:26.157617
7701 09:33:26.157821 ==
7702 09:33:26.160539 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 09:33:26.166819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 09:33:26.167398 ==
7705 09:33:26.167789
7706 09:33:26.168137
7707 09:33:26.168462 TX Vref Scan disable
7708 09:33:26.171124 == TX Byte 0 ==
7709 09:33:26.174250 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7710 09:33:26.180697 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7711 09:33:26.181255 == TX Byte 1 ==
7712 09:33:26.184179 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7713 09:33:26.190413 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7714 09:33:26.190974 ==
7715 09:33:26.193945 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 09:33:26.197229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 09:33:26.197697 ==
7718 09:33:26.210622
7719 09:33:26.213998 TX Vref early break, caculate TX vref
7720 09:33:26.216588 TX Vref=16, minBit 14, minWin=22, winSum=372
7721 09:33:26.219812 TX Vref=18, minBit 1, minWin=23, winSum=385
7722 09:33:26.222960 TX Vref=20, minBit 1, minWin=23, winSum=392
7723 09:33:26.226421 TX Vref=22, minBit 1, minWin=24, winSum=401
7724 09:33:26.232966 TX Vref=24, minBit 3, minWin=24, winSum=413
7725 09:33:26.236338 TX Vref=26, minBit 1, minWin=25, winSum=421
7726 09:33:26.239610 TX Vref=28, minBit 0, minWin=25, winSum=418
7727 09:33:26.242982 TX Vref=30, minBit 0, minWin=24, winSum=411
7728 09:33:26.246482 TX Vref=32, minBit 0, minWin=24, winSum=400
7729 09:33:26.249706 TX Vref=34, minBit 4, minWin=22, winSum=388
7730 09:33:26.256580 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 26
7731 09:33:26.257000
7732 09:33:26.259635 Final TX Range 0 Vref 26
7733 09:33:26.260092
7734 09:33:26.260425 ==
7735 09:33:26.262604 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 09:33:26.266511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 09:33:26.267040 ==
7738 09:33:26.267378
7739 09:33:26.267929
7740 09:33:26.269873 TX Vref Scan disable
7741 09:33:26.276234 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7742 09:33:26.276676 == TX Byte 0 ==
7743 09:33:26.279326 u2DelayCellOfst[0]=14 cells (4 PI)
7744 09:33:26.282800 u2DelayCellOfst[1]=18 cells (5 PI)
7745 09:33:26.285801 u2DelayCellOfst[2]=14 cells (4 PI)
7746 09:33:26.289320 u2DelayCellOfst[3]=14 cells (4 PI)
7747 09:33:26.293019 u2DelayCellOfst[4]=14 cells (4 PI)
7748 09:33:26.296030 u2DelayCellOfst[5]=0 cells (0 PI)
7749 09:33:26.299609 u2DelayCellOfst[6]=22 cells (6 PI)
7750 09:33:26.302323 u2DelayCellOfst[7]=18 cells (5 PI)
7751 09:33:26.305884 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7752 09:33:26.309272 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7753 09:33:26.311877 == TX Byte 1 ==
7754 09:33:26.315600 u2DelayCellOfst[8]=0 cells (0 PI)
7755 09:33:26.318663 u2DelayCellOfst[9]=0 cells (0 PI)
7756 09:33:26.322058 u2DelayCellOfst[10]=7 cells (2 PI)
7757 09:33:26.325439 u2DelayCellOfst[11]=3 cells (1 PI)
7758 09:33:26.328896 u2DelayCellOfst[12]=11 cells (3 PI)
7759 09:33:26.332230 u2DelayCellOfst[13]=11 cells (3 PI)
7760 09:33:26.332644 u2DelayCellOfst[14]=14 cells (4 PI)
7761 09:33:26.335315 u2DelayCellOfst[15]=11 cells (3 PI)
7762 09:33:26.341859 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7763 09:33:26.345034 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7764 09:33:26.348267 DramC Write-DBI on
7765 09:33:26.348678 ==
7766 09:33:26.351440 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 09:33:26.354903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 09:33:26.355316 ==
7769 09:33:26.355643
7770 09:33:26.356007
7771 09:33:26.357895 TX Vref Scan disable
7772 09:33:26.358304 == TX Byte 0 ==
7773 09:33:26.364733 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7774 09:33:26.365217 == TX Byte 1 ==
7775 09:33:26.371346 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7776 09:33:26.371801 DramC Write-DBI off
7777 09:33:26.372138
7778 09:33:26.372441 [DATLAT]
7779 09:33:26.374526 Freq=1600, CH0 RK0
7780 09:33:26.374936
7781 09:33:26.378055 DATLAT Default: 0xf
7782 09:33:26.378573 0, 0xFFFF, sum = 0
7783 09:33:26.381377 1, 0xFFFF, sum = 0
7784 09:33:26.381796 2, 0xFFFF, sum = 0
7785 09:33:26.384297 3, 0xFFFF, sum = 0
7786 09:33:26.384713 4, 0xFFFF, sum = 0
7787 09:33:26.387761 5, 0xFFFF, sum = 0
7788 09:33:26.388179 6, 0xFFFF, sum = 0
7789 09:33:26.390939 7, 0xFFFF, sum = 0
7790 09:33:26.391354 8, 0xFFFF, sum = 0
7791 09:33:26.394840 9, 0xFFFF, sum = 0
7792 09:33:26.395359 10, 0xFFFF, sum = 0
7793 09:33:26.397515 11, 0xFFFF, sum = 0
7794 09:33:26.397932 12, 0xFFFF, sum = 0
7795 09:33:26.401475 13, 0xFFFF, sum = 0
7796 09:33:26.401994 14, 0x0, sum = 1
7797 09:33:26.404116 15, 0x0, sum = 2
7798 09:33:26.404535 16, 0x0, sum = 3
7799 09:33:26.407514 17, 0x0, sum = 4
7800 09:33:26.407980 best_step = 15
7801 09:33:26.408313
7802 09:33:26.408620 ==
7803 09:33:26.410663 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 09:33:26.417625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 09:33:26.418157 ==
7806 09:33:26.418490 RX Vref Scan: 1
7807 09:33:26.418801
7808 09:33:26.421139 Set Vref Range= 24 -> 127
7809 09:33:26.421552
7810 09:33:26.424030 RX Vref 24 -> 127, step: 1
7811 09:33:26.424443
7812 09:33:26.427642 RX Delay 11 -> 252, step: 4
7813 09:33:26.428194
7814 09:33:26.430585 Set Vref, RX VrefLevel [Byte0]: 24
7815 09:33:26.433474 [Byte1]: 24
7816 09:33:26.433885
7817 09:33:26.437290 Set Vref, RX VrefLevel [Byte0]: 25
7818 09:33:26.440405 [Byte1]: 25
7819 09:33:26.440818
7820 09:33:26.443813 Set Vref, RX VrefLevel [Byte0]: 26
7821 09:33:26.446842 [Byte1]: 26
7822 09:33:26.450011
7823 09:33:26.450643 Set Vref, RX VrefLevel [Byte0]: 27
7824 09:33:26.453296 [Byte1]: 27
7825 09:33:26.458376
7826 09:33:26.458787 Set Vref, RX VrefLevel [Byte0]: 28
7827 09:33:26.461343 [Byte1]: 28
7828 09:33:26.465109
7829 09:33:26.465541 Set Vref, RX VrefLevel [Byte0]: 29
7830 09:33:26.468469 [Byte1]: 29
7831 09:33:26.473364
7832 09:33:26.473775 Set Vref, RX VrefLevel [Byte0]: 30
7833 09:33:26.476622 [Byte1]: 30
7834 09:33:26.480985
7835 09:33:26.481397 Set Vref, RX VrefLevel [Byte0]: 31
7836 09:33:26.484060 [Byte1]: 31
7837 09:33:26.488045
7838 09:33:26.488454 Set Vref, RX VrefLevel [Byte0]: 32
7839 09:33:26.491238 [Byte1]: 32
7840 09:33:26.496182
7841 09:33:26.496594 Set Vref, RX VrefLevel [Byte0]: 33
7842 09:33:26.499193 [Byte1]: 33
7843 09:33:26.503368
7844 09:33:26.504009 Set Vref, RX VrefLevel [Byte0]: 34
7845 09:33:26.506756 [Byte1]: 34
7846 09:33:26.510964
7847 09:33:26.511413 Set Vref, RX VrefLevel [Byte0]: 35
7848 09:33:26.514467 [Byte1]: 35
7849 09:33:26.519100
7850 09:33:26.519612 Set Vref, RX VrefLevel [Byte0]: 36
7851 09:33:26.522612 [Byte1]: 36
7852 09:33:26.526610
7853 09:33:26.527124 Set Vref, RX VrefLevel [Byte0]: 37
7854 09:33:26.529884 [Byte1]: 37
7855 09:33:26.534090
7856 09:33:26.534498 Set Vref, RX VrefLevel [Byte0]: 38
7857 09:33:26.537481 [Byte1]: 38
7858 09:33:26.542063
7859 09:33:26.542632 Set Vref, RX VrefLevel [Byte0]: 39
7860 09:33:26.544860 [Byte1]: 39
7861 09:33:26.548939
7862 09:33:26.549346 Set Vref, RX VrefLevel [Byte0]: 40
7863 09:33:26.552221 [Byte1]: 40
7864 09:33:26.557021
7865 09:33:26.557532 Set Vref, RX VrefLevel [Byte0]: 41
7866 09:33:26.560094 [Byte1]: 41
7867 09:33:26.564384
7868 09:33:26.564899 Set Vref, RX VrefLevel [Byte0]: 42
7869 09:33:26.567873 [Byte1]: 42
7870 09:33:26.572105
7871 09:33:26.572621 Set Vref, RX VrefLevel [Byte0]: 43
7872 09:33:26.575428 [Byte1]: 43
7873 09:33:26.579844
7874 09:33:26.580369 Set Vref, RX VrefLevel [Byte0]: 44
7875 09:33:26.583154 [Byte1]: 44
7876 09:33:26.587621
7877 09:33:26.588176 Set Vref, RX VrefLevel [Byte0]: 45
7878 09:33:26.591070 [Byte1]: 45
7879 09:33:26.595346
7880 09:33:26.595894 Set Vref, RX VrefLevel [Byte0]: 46
7881 09:33:26.598173 [Byte1]: 46
7882 09:33:26.602492
7883 09:33:26.603006 Set Vref, RX VrefLevel [Byte0]: 47
7884 09:33:26.605948 [Byte1]: 47
7885 09:33:26.610053
7886 09:33:26.610567 Set Vref, RX VrefLevel [Byte0]: 48
7887 09:33:26.613521 [Byte1]: 48
7888 09:33:26.618266
7889 09:33:26.618777 Set Vref, RX VrefLevel [Byte0]: 49
7890 09:33:26.621038 [Byte1]: 49
7891 09:33:26.625677
7892 09:33:26.626185 Set Vref, RX VrefLevel [Byte0]: 50
7893 09:33:26.628671 [Byte1]: 50
7894 09:33:26.633031
7895 09:33:26.633442 Set Vref, RX VrefLevel [Byte0]: 51
7896 09:33:26.636767 [Byte1]: 51
7897 09:33:26.640638
7898 09:33:26.641048 Set Vref, RX VrefLevel [Byte0]: 52
7899 09:33:26.644280 [Byte1]: 52
7900 09:33:26.648167
7901 09:33:26.648599 Set Vref, RX VrefLevel [Byte0]: 53
7902 09:33:26.651614 [Byte1]: 53
7903 09:33:26.656179
7904 09:33:26.656688 Set Vref, RX VrefLevel [Byte0]: 54
7905 09:33:26.658902 [Byte1]: 54
7906 09:33:26.663850
7907 09:33:26.664385 Set Vref, RX VrefLevel [Byte0]: 55
7908 09:33:26.666365 [Byte1]: 55
7909 09:33:26.671268
7910 09:33:26.671816 Set Vref, RX VrefLevel [Byte0]: 56
7911 09:33:26.674628 [Byte1]: 56
7912 09:33:26.678999
7913 09:33:26.679516 Set Vref, RX VrefLevel [Byte0]: 57
7914 09:33:26.682340 [Byte1]: 57
7915 09:33:26.686313
7916 09:33:26.686822 Set Vref, RX VrefLevel [Byte0]: 58
7917 09:33:26.689554 [Byte1]: 58
7918 09:33:26.694058
7919 09:33:26.694573 Set Vref, RX VrefLevel [Byte0]: 59
7920 09:33:26.697031 [Byte1]: 59
7921 09:33:26.701287
7922 09:33:26.701760 Set Vref, RX VrefLevel [Byte0]: 60
7923 09:33:26.705273 [Byte1]: 60
7924 09:33:26.708975
7925 09:33:26.709494 Set Vref, RX VrefLevel [Byte0]: 61
7926 09:33:26.712534 [Byte1]: 61
7927 09:33:26.717186
7928 09:33:26.717751 Set Vref, RX VrefLevel [Byte0]: 62
7929 09:33:26.720133 [Byte1]: 62
7930 09:33:26.724468
7931 09:33:26.724981 Set Vref, RX VrefLevel [Byte0]: 63
7932 09:33:26.727986 [Byte1]: 63
7933 09:33:26.732439
7934 09:33:26.732956 Set Vref, RX VrefLevel [Byte0]: 64
7935 09:33:26.735492 [Byte1]: 64
7936 09:33:26.739695
7937 09:33:26.740264 Set Vref, RX VrefLevel [Byte0]: 65
7938 09:33:26.743142 [Byte1]: 65
7939 09:33:26.747569
7940 09:33:26.748127 Set Vref, RX VrefLevel [Byte0]: 66
7941 09:33:26.750963 [Byte1]: 66
7942 09:33:26.755164
7943 09:33:26.755676 Set Vref, RX VrefLevel [Byte0]: 67
7944 09:33:26.758275 [Byte1]: 67
7945 09:33:26.763376
7946 09:33:26.763912 Set Vref, RX VrefLevel [Byte0]: 68
7947 09:33:26.766231 [Byte1]: 68
7948 09:33:26.770223
7949 09:33:26.770636 Set Vref, RX VrefLevel [Byte0]: 69
7950 09:33:26.773256 [Byte1]: 69
7951 09:33:26.777593
7952 09:33:26.778105 Set Vref, RX VrefLevel [Byte0]: 70
7953 09:33:26.780715 [Byte1]: 70
7954 09:33:26.785512
7955 09:33:26.786023 Set Vref, RX VrefLevel [Byte0]: 71
7956 09:33:26.788577 [Byte1]: 71
7957 09:33:26.792780
7958 09:33:26.793354 Set Vref, RX VrefLevel [Byte0]: 72
7959 09:33:26.796202 [Byte1]: 72
7960 09:33:26.800601
7961 09:33:26.801203 Set Vref, RX VrefLevel [Byte0]: 73
7962 09:33:26.803765 [Byte1]: 73
7963 09:33:26.808077
7964 09:33:26.808602 Set Vref, RX VrefLevel [Byte0]: 74
7965 09:33:26.811386 [Byte1]: 74
7966 09:33:26.815647
7967 09:33:26.816207 Set Vref, RX VrefLevel [Byte0]: 75
7968 09:33:26.819617 [Byte1]: 75
7969 09:33:26.823175
7970 09:33:26.823683 Set Vref, RX VrefLevel [Byte0]: 76
7971 09:33:26.826348 [Byte1]: 76
7972 09:33:26.831305
7973 09:33:26.831875 Set Vref, RX VrefLevel [Byte0]: 77
7974 09:33:26.834421 [Byte1]: 77
7975 09:33:26.839191
7976 09:33:26.839702 Set Vref, RX VrefLevel [Byte0]: 78
7977 09:33:26.841843 [Byte1]: 78
7978 09:33:26.846272
7979 09:33:26.846790 Set Vref, RX VrefLevel [Byte0]: 79
7980 09:33:26.849468 [Byte1]: 79
7981 09:33:26.854112
7982 09:33:26.854624 Final RX Vref Byte 0 = 65 to rank0
7983 09:33:26.857044 Final RX Vref Byte 1 = 58 to rank0
7984 09:33:26.860467 Final RX Vref Byte 0 = 65 to rank1
7985 09:33:26.863961 Final RX Vref Byte 1 = 58 to rank1==
7986 09:33:26.867025 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 09:33:26.873636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 09:33:26.874165 ==
7989 09:33:26.874496 DQS Delay:
7990 09:33:26.874800 DQS0 = 0, DQS1 = 0
7991 09:33:26.877127 DQM Delay:
7992 09:33:26.877538 DQM0 = 132, DQM1 = 123
7993 09:33:26.880203 DQ Delay:
7994 09:33:26.883699 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =132
7995 09:33:26.886959 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
7996 09:33:26.890032 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =118
7997 09:33:26.893935 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
7998 09:33:26.894442
7999 09:33:26.894771
8000 09:33:26.895074
8001 09:33:26.896764 [DramC_TX_OE_Calibration] TA2
8002 09:33:26.900111 Original DQ_B0 (3 6) =30, OEN = 27
8003 09:33:26.903467 Original DQ_B1 (3 6) =30, OEN = 27
8004 09:33:26.907111 24, 0x0, End_B0=24 End_B1=24
8005 09:33:26.907642 25, 0x0, End_B0=25 End_B1=25
8006 09:33:26.910372 26, 0x0, End_B0=26 End_B1=26
8007 09:33:26.912949 27, 0x0, End_B0=27 End_B1=27
8008 09:33:26.916527 28, 0x0, End_B0=28 End_B1=28
8009 09:33:26.919712 29, 0x0, End_B0=29 End_B1=29
8010 09:33:26.920233 30, 0x0, End_B0=30 End_B1=30
8011 09:33:26.923417 31, 0x4141, End_B0=30 End_B1=30
8012 09:33:26.926285 Byte0 end_step=30 best_step=27
8013 09:33:26.929343 Byte1 end_step=30 best_step=27
8014 09:33:26.933346 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 09:33:26.936359 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 09:33:26.936822
8017 09:33:26.937185
8018 09:33:26.943313 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8019 09:33:26.946449 CH0 RK0: MR19=303, MR18=2011
8020 09:33:26.953237 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8021 09:33:26.953811
8022 09:33:26.955771 ----->DramcWriteLeveling(PI) begin...
8023 09:33:26.956245 ==
8024 09:33:26.959431 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 09:33:26.963002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 09:33:26.963579 ==
8027 09:33:26.966041 Write leveling (Byte 0): 36 => 36
8028 09:33:26.969189 Write leveling (Byte 1): 28 => 28
8029 09:33:26.973412 DramcWriteLeveling(PI) end<-----
8030 09:33:26.973977
8031 09:33:26.974347 ==
8032 09:33:26.975978 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 09:33:26.979566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 09:33:26.983039 ==
8035 09:33:26.983503 [Gating] SW mode calibration
8036 09:33:26.988953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 09:33:26.995665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 09:33:26.999061 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 09:33:27.005147 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 09:33:27.008972 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 09:33:27.012611 1 4 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8042 09:33:27.019095 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8043 09:33:27.021856 1 4 20 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8044 09:33:27.025782 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 09:33:27.031798 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 09:33:27.035605 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 09:33:27.038990 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 09:33:27.045172 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 09:33:27.048387 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8050 09:33:27.051563 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8051 09:33:27.058519 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8052 09:33:27.061851 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8053 09:33:27.064774 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 09:33:27.071923 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 09:33:27.074753 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 09:33:27.078207 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 09:33:27.084935 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8058 09:33:27.088265 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8059 09:33:27.091444 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8060 09:33:27.097918 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 09:33:27.101803 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 09:33:27.104311 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 09:33:27.110982 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 09:33:27.114869 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 09:33:27.117919 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 09:33:27.124302 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 09:33:27.127687 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8068 09:33:27.130797 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 09:33:27.137973 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 09:33:27.141054 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 09:33:27.144066 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 09:33:27.150937 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 09:33:27.154195 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 09:33:27.157633 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 09:33:27.163808 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 09:33:27.167606 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 09:33:27.170352 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 09:33:27.176869 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 09:33:27.180129 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 09:33:27.183569 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 09:33:27.190135 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8082 09:33:27.193528 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 09:33:27.197270 Total UI for P1: 0, mck2ui 16
8084 09:33:27.200351 best dqsien dly found for B0: ( 1, 9, 10)
8085 09:33:27.203265 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 09:33:27.206927 Total UI for P1: 0, mck2ui 16
8087 09:33:27.210110 best dqsien dly found for B1: ( 1, 9, 16)
8088 09:33:27.213750 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8089 09:33:27.217623 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8090 09:33:27.218182
8091 09:33:27.223564 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8092 09:33:27.226830 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8093 09:33:27.230196 [Gating] SW calibration Done
8094 09:33:27.230769 ==
8095 09:33:27.233467 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 09:33:27.236433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 09:33:27.237046 ==
8098 09:33:27.237430 RX Vref Scan: 0
8099 09:33:27.237774
8100 09:33:27.240125 RX Vref 0 -> 0, step: 1
8101 09:33:27.240680
8102 09:33:27.243333 RX Delay 0 -> 252, step: 8
8103 09:33:27.246356 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8104 09:33:27.249748 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8105 09:33:27.256528 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8106 09:33:27.259821 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8107 09:33:27.263447 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8108 09:33:27.266572 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8109 09:33:27.269295 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8110 09:33:27.276046 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8111 09:33:27.279395 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8112 09:33:27.282866 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8113 09:33:27.286546 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8114 09:33:27.289381 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8115 09:33:27.296060 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8116 09:33:27.299029 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8117 09:33:27.302804 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8118 09:33:27.305951 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8119 09:33:27.306414 ==
8120 09:33:27.309220 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 09:33:27.315828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 09:33:27.316645 ==
8123 09:33:27.317066 DQS Delay:
8124 09:33:27.319219 DQS0 = 0, DQS1 = 0
8125 09:33:27.319824 DQM Delay:
8126 09:33:27.322792 DQM0 = 133, DQM1 = 127
8127 09:33:27.323349 DQ Delay:
8128 09:33:27.325382 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8129 09:33:27.329320 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8130 09:33:27.332042 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8131 09:33:27.335504 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8132 09:33:27.336016
8133 09:33:27.336379
8134 09:33:27.336713 ==
8135 09:33:27.338903 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 09:33:27.345644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 09:33:27.346204 ==
8138 09:33:27.346569
8139 09:33:27.346907
8140 09:33:27.347225 TX Vref Scan disable
8141 09:33:27.348818 == TX Byte 0 ==
8142 09:33:27.352222 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8143 09:33:27.359149 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8144 09:33:27.359694 == TX Byte 1 ==
8145 09:33:27.362031 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8146 09:33:27.368440 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8147 09:33:27.368904 ==
8148 09:33:27.372207 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 09:33:27.375196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 09:33:27.375787 ==
8151 09:33:27.388685
8152 09:33:27.391822 TX Vref early break, caculate TX vref
8153 09:33:27.395050 TX Vref=16, minBit 1, minWin=22, winSum=379
8154 09:33:27.398441 TX Vref=18, minBit 0, minWin=23, winSum=385
8155 09:33:27.402104 TX Vref=20, minBit 0, minWin=23, winSum=395
8156 09:33:27.405212 TX Vref=22, minBit 1, minWin=23, winSum=399
8157 09:33:27.408372 TX Vref=24, minBit 1, minWin=24, winSum=410
8158 09:33:27.414908 TX Vref=26, minBit 4, minWin=24, winSum=413
8159 09:33:27.418083 TX Vref=28, minBit 0, minWin=25, winSum=410
8160 09:33:27.421772 TX Vref=30, minBit 1, minWin=24, winSum=403
8161 09:33:27.425219 TX Vref=32, minBit 5, minWin=23, winSum=395
8162 09:33:27.428216 TX Vref=34, minBit 5, minWin=23, winSum=388
8163 09:33:27.435017 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8164 09:33:27.435561
8165 09:33:27.438155 Final TX Range 0 Vref 28
8166 09:33:27.438709
8167 09:33:27.439069 ==
8168 09:33:27.441457 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 09:33:27.445052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 09:33:27.445510 ==
8171 09:33:27.445871
8172 09:33:27.446200
8173 09:33:27.448113 TX Vref Scan disable
8174 09:33:27.454613 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8175 09:33:27.455166 == TX Byte 0 ==
8176 09:33:27.457707 u2DelayCellOfst[0]=14 cells (4 PI)
8177 09:33:27.461364 u2DelayCellOfst[1]=18 cells (5 PI)
8178 09:33:27.464303 u2DelayCellOfst[2]=14 cells (4 PI)
8179 09:33:27.467517 u2DelayCellOfst[3]=14 cells (4 PI)
8180 09:33:27.470815 u2DelayCellOfst[4]=11 cells (3 PI)
8181 09:33:27.474545 u2DelayCellOfst[5]=0 cells (0 PI)
8182 09:33:27.477403 u2DelayCellOfst[6]=18 cells (5 PI)
8183 09:33:27.481117 u2DelayCellOfst[7]=22 cells (6 PI)
8184 09:33:27.484491 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8185 09:33:27.487889 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8186 09:33:27.491433 == TX Byte 1 ==
8187 09:33:27.493671 u2DelayCellOfst[8]=0 cells (0 PI)
8188 09:33:27.497554 u2DelayCellOfst[9]=3 cells (1 PI)
8189 09:33:27.501018 u2DelayCellOfst[10]=7 cells (2 PI)
8190 09:33:27.503837 u2DelayCellOfst[11]=3 cells (1 PI)
8191 09:33:27.504298 u2DelayCellOfst[12]=11 cells (3 PI)
8192 09:33:27.507146 u2DelayCellOfst[13]=14 cells (4 PI)
8193 09:33:27.510368 u2DelayCellOfst[14]=18 cells (5 PI)
8194 09:33:27.514061 u2DelayCellOfst[15]=11 cells (3 PI)
8195 09:33:27.520493 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8196 09:33:27.523583 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8197 09:33:27.524112 DramC Write-DBI on
8198 09:33:27.527314 ==
8199 09:33:27.530272 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 09:33:27.533437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 09:33:27.534132 ==
8202 09:33:27.534509
8203 09:33:27.534951
8204 09:33:27.536769 TX Vref Scan disable
8205 09:33:27.537227 == TX Byte 0 ==
8206 09:33:27.543195 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8207 09:33:27.543652 == TX Byte 1 ==
8208 09:33:27.546629 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8209 09:33:27.549940 DramC Write-DBI off
8210 09:33:27.550390
8211 09:33:27.550749 [DATLAT]
8212 09:33:27.552973 Freq=1600, CH0 RK1
8213 09:33:27.553443
8214 09:33:27.553784 DATLAT Default: 0xf
8215 09:33:27.556466 0, 0xFFFF, sum = 0
8216 09:33:27.556990 1, 0xFFFF, sum = 0
8217 09:33:27.559792 2, 0xFFFF, sum = 0
8218 09:33:27.560209 3, 0xFFFF, sum = 0
8219 09:33:27.562973 4, 0xFFFF, sum = 0
8220 09:33:27.566209 5, 0xFFFF, sum = 0
8221 09:33:27.566633 6, 0xFFFF, sum = 0
8222 09:33:27.569522 7, 0xFFFF, sum = 0
8223 09:33:27.569940 8, 0xFFFF, sum = 0
8224 09:33:27.572873 9, 0xFFFF, sum = 0
8225 09:33:27.573291 10, 0xFFFF, sum = 0
8226 09:33:27.576122 11, 0xFFFF, sum = 0
8227 09:33:27.576689 12, 0xFFFF, sum = 0
8228 09:33:27.579518 13, 0xFFFF, sum = 0
8229 09:33:27.580171 14, 0x0, sum = 1
8230 09:33:27.583164 15, 0x0, sum = 2
8231 09:33:27.583771 16, 0x0, sum = 3
8232 09:33:27.586416 17, 0x0, sum = 4
8233 09:33:27.586873 best_step = 15
8234 09:33:27.587406
8235 09:33:27.588021 ==
8236 09:33:27.589259 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 09:33:27.596182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 09:33:27.596599 ==
8239 09:33:27.596930 RX Vref Scan: 0
8240 09:33:27.597236
8241 09:33:27.599228 RX Vref 0 -> 0, step: 1
8242 09:33:27.599887
8243 09:33:27.602662 RX Delay 11 -> 252, step: 4
8244 09:33:27.605688 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8245 09:33:27.609667 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8246 09:33:27.612433 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8247 09:33:27.619119 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8248 09:33:27.622118 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8249 09:33:27.626135 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8250 09:33:27.629155 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8251 09:33:27.635197 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8252 09:33:27.638901 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8253 09:33:27.641891 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8254 09:33:27.645248 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8255 09:33:27.648454 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8256 09:33:27.655171 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8257 09:33:27.658714 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8258 09:33:27.662216 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8259 09:33:27.664474 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8260 09:33:27.664929 ==
8261 09:33:27.668700 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 09:33:27.674809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 09:33:27.675365 ==
8264 09:33:27.675770 DQS Delay:
8265 09:33:27.677895 DQS0 = 0, DQS1 = 0
8266 09:33:27.678447 DQM Delay:
8267 09:33:27.681133 DQM0 = 130, DQM1 = 125
8268 09:33:27.681588 DQ Delay:
8269 09:33:27.684244 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8270 09:33:27.688033 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8271 09:33:27.691127 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8272 09:33:27.694665 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8273 09:33:27.695222
8274 09:33:27.695583
8275 09:33:27.695988
8276 09:33:27.697842 [DramC_TX_OE_Calibration] TA2
8277 09:33:27.701282 Original DQ_B0 (3 6) =30, OEN = 27
8278 09:33:27.704062 Original DQ_B1 (3 6) =30, OEN = 27
8279 09:33:27.707420 24, 0x0, End_B0=24 End_B1=24
8280 09:33:27.710872 25, 0x0, End_B0=25 End_B1=25
8281 09:33:27.711439 26, 0x0, End_B0=26 End_B1=26
8282 09:33:27.714114 27, 0x0, End_B0=27 End_B1=27
8283 09:33:27.717592 28, 0x0, End_B0=28 End_B1=28
8284 09:33:27.721319 29, 0x0, End_B0=29 End_B1=29
8285 09:33:27.724051 30, 0x0, End_B0=30 End_B1=30
8286 09:33:27.724516 31, 0x4141, End_B0=30 End_B1=30
8287 09:33:27.727408 Byte0 end_step=30 best_step=27
8288 09:33:27.730878 Byte1 end_step=30 best_step=27
8289 09:33:27.733917 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 09:33:27.737286 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 09:33:27.737847
8292 09:33:27.738209
8293 09:33:27.743766 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8294 09:33:27.746914 CH0 RK1: MR19=303, MR18=1D00
8295 09:33:27.753735 CH0_RK1: MR19=0x303, MR18=0x1D00, DQSOSC=395, MR23=63, INC=23, DEC=15
8296 09:33:27.756757 [RxdqsGatingPostProcess] freq 1600
8297 09:33:27.763256 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 09:33:27.766874 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 09:33:27.767387 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 09:33:27.770102 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 09:33:27.773526 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 09:33:27.776537 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 09:33:27.779838 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 09:33:27.783493 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 09:33:27.787059 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 09:33:27.790039 Pre-setting of DQS Precalculation
8307 09:33:27.793148 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 09:33:27.796704 ==
8309 09:33:27.800131 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 09:33:27.803382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 09:33:27.804040 ==
8312 09:33:27.809977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 09:33:27.813004 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 09:33:27.816030 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 09:33:27.822590 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 09:33:27.831159 [CA 0] Center 41 (12~71) winsize 60
8317 09:33:27.834340 [CA 1] Center 42 (12~72) winsize 61
8318 09:33:27.838143 [CA 2] Center 36 (7~66) winsize 60
8319 09:33:27.841473 [CA 3] Center 35 (6~65) winsize 60
8320 09:33:27.844329 [CA 4] Center 36 (7~66) winsize 60
8321 09:33:27.847884 [CA 5] Center 36 (7~66) winsize 60
8322 09:33:27.848463
8323 09:33:27.851361 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 09:33:27.851966
8325 09:33:27.854678 [CATrainingPosCal] consider 1 rank data
8326 09:33:27.857602 u2DelayCellTimex100 = 262/100 ps
8327 09:33:27.864487 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8328 09:33:27.867767 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8329 09:33:27.870586 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8330 09:33:27.874637 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8331 09:33:27.877261 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8332 09:33:27.880785 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8333 09:33:27.881335
8334 09:33:27.884038 CA PerBit enable=1, Macro0, CA PI delay=35
8335 09:33:27.884588
8336 09:33:27.887445 [CBTSetCACLKResult] CA Dly = 35
8337 09:33:27.891378 CS Dly: 9 (0~40)
8338 09:33:27.893995 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 09:33:27.897614 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 09:33:27.898168 ==
8341 09:33:27.900325 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 09:33:27.906879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 09:33:27.907541 ==
8344 09:33:27.910427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 09:33:27.917311 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 09:33:27.920434 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 09:33:27.926934 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 09:33:27.934402 [CA 0] Center 43 (14~72) winsize 59
8349 09:33:27.937748 [CA 1] Center 42 (12~72) winsize 61
8350 09:33:27.941226 [CA 2] Center 37 (8~67) winsize 60
8351 09:33:27.944442 [CA 3] Center 37 (8~67) winsize 60
8352 09:33:27.947330 [CA 4] Center 37 (8~67) winsize 60
8353 09:33:27.950821 [CA 5] Center 37 (8~67) winsize 60
8354 09:33:27.951373
8355 09:33:27.954368 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8356 09:33:27.954980
8357 09:33:27.957226 [CATrainingPosCal] consider 2 rank data
8358 09:33:27.960663 u2DelayCellTimex100 = 262/100 ps
8359 09:33:27.967867 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8360 09:33:27.970668 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8361 09:33:27.973769 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 09:33:27.977129 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8363 09:33:27.980766 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8364 09:33:27.983783 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8365 09:33:27.984192
8366 09:33:27.987258 CA PerBit enable=1, Macro0, CA PI delay=36
8367 09:33:27.987861
8368 09:33:27.991100 [CBTSetCACLKResult] CA Dly = 36
8369 09:33:27.994035 CS Dly: 11 (0~44)
8370 09:33:27.997911 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 09:33:28.000580 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 09:33:28.001082
8373 09:33:28.004241 ----->DramcWriteLeveling(PI) begin...
8374 09:33:28.004785 ==
8375 09:33:28.006613 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 09:33:28.013722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 09:33:28.014236 ==
8378 09:33:28.016735 Write leveling (Byte 0): 22 => 22
8379 09:33:28.019939 Write leveling (Byte 1): 27 => 27
8380 09:33:28.020379 DramcWriteLeveling(PI) end<-----
8381 09:33:28.020704
8382 09:33:28.023568 ==
8383 09:33:28.027131 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 09:33:28.030473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 09:33:28.031027 ==
8386 09:33:28.033779 [Gating] SW mode calibration
8387 09:33:28.040096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 09:33:28.043226 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 09:33:28.049660 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 09:33:28.053105 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 09:33:28.056390 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8392 09:33:28.062737 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
8393 09:33:28.066307 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 09:33:28.069739 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 09:33:28.075950 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 09:33:28.079644 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 09:33:28.083166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 09:33:28.089670 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 09:33:28.092458 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8400 09:33:28.096039 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8401 09:33:28.103028 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8402 09:33:28.106071 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 09:33:28.109051 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 09:33:28.115975 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 09:33:28.119558 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 09:33:28.122454 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 09:33:28.129177 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8408 09:33:28.132609 1 6 12 | B1->B0 | 2625 4545 | 1 0 | (1 1) (0 0)
8409 09:33:28.135420 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 09:33:28.142435 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 09:33:28.145068 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 09:33:28.148603 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 09:33:28.155278 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 09:33:28.158612 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 09:33:28.162030 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 09:33:28.168643 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8417 09:33:28.171563 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8418 09:33:28.175475 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 09:33:28.181964 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 09:33:28.184761 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 09:33:28.188451 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 09:33:28.194596 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 09:33:28.198096 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 09:33:28.201806 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 09:33:28.208255 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 09:33:28.211436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 09:33:28.214647 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 09:33:28.220967 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 09:33:28.224292 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 09:33:28.227752 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 09:33:28.234717 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8432 09:33:28.238157 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8433 09:33:28.241524 Total UI for P1: 0, mck2ui 16
8434 09:33:28.244663 best dqsien dly found for B0: ( 1, 9, 8)
8435 09:33:28.247831 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8436 09:33:28.254502 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 09:33:28.257773 Total UI for P1: 0, mck2ui 16
8438 09:33:28.261062 best dqsien dly found for B1: ( 1, 9, 14)
8439 09:33:28.264341 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8440 09:33:28.267541 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8441 09:33:28.268185
8442 09:33:28.271271 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8443 09:33:28.273889 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8444 09:33:28.276979 [Gating] SW calibration Done
8445 09:33:28.277453 ==
8446 09:33:28.280254 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 09:33:28.283944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 09:33:28.284524 ==
8449 09:33:28.287668 RX Vref Scan: 0
8450 09:33:28.288296
8451 09:33:28.290379 RX Vref 0 -> 0, step: 1
8452 09:33:28.290964
8453 09:33:28.291453 RX Delay 0 -> 252, step: 8
8454 09:33:28.296998 iDelay=208, Bit 0, Center 147 (96 ~ 199) 104
8455 09:33:28.300562 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8456 09:33:28.304104 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8457 09:33:28.307193 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8458 09:33:28.310446 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8459 09:33:28.317200 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8460 09:33:28.319771 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8461 09:33:28.323878 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8462 09:33:28.326754 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8463 09:33:28.330122 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8464 09:33:28.336337 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8465 09:33:28.339920 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8466 09:33:28.342758 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8467 09:33:28.346464 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8468 09:33:28.352924 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8469 09:33:28.356426 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8470 09:33:28.356886 ==
8471 09:33:28.359457 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 09:33:28.362806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 09:33:28.363269 ==
8474 09:33:28.366196 DQS Delay:
8475 09:33:28.366761 DQS0 = 0, DQS1 = 0
8476 09:33:28.367133 DQM Delay:
8477 09:33:28.369819 DQM0 = 139, DQM1 = 128
8478 09:33:28.370380 DQ Delay:
8479 09:33:28.372643 DQ0 =147, DQ1 =131, DQ2 =127, DQ3 =139
8480 09:33:28.376329 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8481 09:33:28.379888 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8482 09:33:28.386195 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8483 09:33:28.386654
8484 09:33:28.387017
8485 09:33:28.387357 ==
8486 09:33:28.389676 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 09:33:28.393101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 09:33:28.393549 ==
8489 09:33:28.393989
8490 09:33:28.394399
8491 09:33:28.395811 TX Vref Scan disable
8492 09:33:28.396243 == TX Byte 0 ==
8493 09:33:28.402652 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8494 09:33:28.406387 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8495 09:33:28.406916 == TX Byte 1 ==
8496 09:33:28.412448 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8497 09:33:28.415859 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 09:33:28.416381 ==
8499 09:33:28.419015 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 09:33:28.422257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 09:33:28.425749 ==
8502 09:33:28.436650
8503 09:33:28.440056 TX Vref early break, caculate TX vref
8504 09:33:28.443839 TX Vref=16, minBit 0, minWin=21, winSum=372
8505 09:33:28.447493 TX Vref=18, minBit 0, minWin=23, winSum=386
8506 09:33:28.450055 TX Vref=20, minBit 0, minWin=23, winSum=391
8507 09:33:28.453313 TX Vref=22, minBit 0, minWin=23, winSum=403
8508 09:33:28.456448 TX Vref=24, minBit 0, minWin=24, winSum=413
8509 09:33:28.463179 TX Vref=26, minBit 0, minWin=24, winSum=418
8510 09:33:28.466705 TX Vref=28, minBit 0, minWin=24, winSum=419
8511 09:33:28.469932 TX Vref=30, minBit 0, minWin=24, winSum=415
8512 09:33:28.472759 TX Vref=32, minBit 0, minWin=23, winSum=404
8513 09:33:28.476322 TX Vref=34, minBit 0, minWin=22, winSum=393
8514 09:33:28.483116 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 28
8515 09:33:28.483578
8516 09:33:28.486377 Final TX Range 0 Vref 28
8517 09:33:28.486840
8518 09:33:28.487200 ==
8519 09:33:28.489959 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 09:33:28.492568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 09:33:28.493033 ==
8522 09:33:28.493401
8523 09:33:28.493739
8524 09:33:28.496304 TX Vref Scan disable
8525 09:33:28.502823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8526 09:33:28.503387 == TX Byte 0 ==
8527 09:33:28.506185 u2DelayCellOfst[0]=18 cells (5 PI)
8528 09:33:28.509176 u2DelayCellOfst[1]=14 cells (4 PI)
8529 09:33:28.513038 u2DelayCellOfst[2]=0 cells (0 PI)
8530 09:33:28.516193 u2DelayCellOfst[3]=7 cells (2 PI)
8531 09:33:28.519093 u2DelayCellOfst[4]=7 cells (2 PI)
8532 09:33:28.522873 u2DelayCellOfst[5]=22 cells (6 PI)
8533 09:33:28.526329 u2DelayCellOfst[6]=22 cells (6 PI)
8534 09:33:28.529725 u2DelayCellOfst[7]=7 cells (2 PI)
8535 09:33:28.532501 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8536 09:33:28.536442 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8537 09:33:28.539056 == TX Byte 1 ==
8538 09:33:28.542550 u2DelayCellOfst[8]=0 cells (0 PI)
8539 09:33:28.543124 u2DelayCellOfst[9]=3 cells (1 PI)
8540 09:33:28.545473 u2DelayCellOfst[10]=11 cells (3 PI)
8541 09:33:28.548850 u2DelayCellOfst[11]=3 cells (1 PI)
8542 09:33:28.552317 u2DelayCellOfst[12]=14 cells (4 PI)
8543 09:33:28.556011 u2DelayCellOfst[13]=18 cells (5 PI)
8544 09:33:28.559080 u2DelayCellOfst[14]=18 cells (5 PI)
8545 09:33:28.561885 u2DelayCellOfst[15]=18 cells (5 PI)
8546 09:33:28.569169 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8547 09:33:28.572335 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8548 09:33:28.572900 DramC Write-DBI on
8549 09:33:28.573396 ==
8550 09:33:28.575473 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 09:33:28.581668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 09:33:28.582143 ==
8553 09:33:28.582624
8554 09:33:28.583078
8555 09:33:28.583570 TX Vref Scan disable
8556 09:33:28.585733 == TX Byte 0 ==
8557 09:33:28.589231 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8558 09:33:28.592225 == TX Byte 1 ==
8559 09:33:28.595505 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8560 09:33:28.598772 DramC Write-DBI off
8561 09:33:28.599185
8562 09:33:28.599509 [DATLAT]
8563 09:33:28.599864 Freq=1600, CH1 RK0
8564 09:33:28.600167
8565 09:33:28.602275 DATLAT Default: 0xf
8566 09:33:28.605368 0, 0xFFFF, sum = 0
8567 09:33:28.605789 1, 0xFFFF, sum = 0
8568 09:33:28.608856 2, 0xFFFF, sum = 0
8569 09:33:28.609275 3, 0xFFFF, sum = 0
8570 09:33:28.612258 4, 0xFFFF, sum = 0
8571 09:33:28.612682 5, 0xFFFF, sum = 0
8572 09:33:28.615487 6, 0xFFFF, sum = 0
8573 09:33:28.615976 7, 0xFFFF, sum = 0
8574 09:33:28.618736 8, 0xFFFF, sum = 0
8575 09:33:28.619168 9, 0xFFFF, sum = 0
8576 09:33:28.622078 10, 0xFFFF, sum = 0
8577 09:33:28.622619 11, 0xFFFF, sum = 0
8578 09:33:28.625745 12, 0xFFFF, sum = 0
8579 09:33:28.626303 13, 0xFFFF, sum = 0
8580 09:33:28.628308 14, 0x0, sum = 1
8581 09:33:28.628745 15, 0x0, sum = 2
8582 09:33:28.631643 16, 0x0, sum = 3
8583 09:33:28.632169 17, 0x0, sum = 4
8584 09:33:28.635373 best_step = 15
8585 09:33:28.635841
8586 09:33:28.636306 ==
8587 09:33:28.638878 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 09:33:28.642014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 09:33:28.642558 ==
8590 09:33:28.645455 RX Vref Scan: 1
8591 09:33:28.645887
8592 09:33:28.646332 Set Vref Range= 24 -> 127
8593 09:33:28.646758
8594 09:33:28.648415 RX Vref 24 -> 127, step: 1
8595 09:33:28.648844
8596 09:33:28.651679 RX Delay 11 -> 252, step: 4
8597 09:33:28.652155
8598 09:33:28.654692 Set Vref, RX VrefLevel [Byte0]: 24
8599 09:33:28.658620 [Byte1]: 24
8600 09:33:28.659050
8601 09:33:28.661464 Set Vref, RX VrefLevel [Byte0]: 25
8602 09:33:28.664612 [Byte1]: 25
8603 09:33:28.668481
8604 09:33:28.668907 Set Vref, RX VrefLevel [Byte0]: 26
8605 09:33:28.672075 [Byte1]: 26
8606 09:33:28.676264
8607 09:33:28.676693 Set Vref, RX VrefLevel [Byte0]: 27
8608 09:33:28.679477 [Byte1]: 27
8609 09:33:28.683826
8610 09:33:28.684255 Set Vref, RX VrefLevel [Byte0]: 28
8611 09:33:28.687273 [Byte1]: 28
8612 09:33:28.691713
8613 09:33:28.692210 Set Vref, RX VrefLevel [Byte0]: 29
8614 09:33:28.694949 [Byte1]: 29
8615 09:33:28.699630
8616 09:33:28.700105 Set Vref, RX VrefLevel [Byte0]: 30
8617 09:33:28.702376 [Byte1]: 30
8618 09:33:28.707261
8619 09:33:28.707838 Set Vref, RX VrefLevel [Byte0]: 31
8620 09:33:28.709897 [Byte1]: 31
8621 09:33:28.714719
8622 09:33:28.715145 Set Vref, RX VrefLevel [Byte0]: 32
8623 09:33:28.717629 [Byte1]: 32
8624 09:33:28.722363
8625 09:33:28.723002 Set Vref, RX VrefLevel [Byte0]: 33
8626 09:33:28.725170 [Byte1]: 33
8627 09:33:28.729927
8628 09:33:28.730461 Set Vref, RX VrefLevel [Byte0]: 34
8629 09:33:28.733063 [Byte1]: 34
8630 09:33:28.737557
8631 09:33:28.738144 Set Vref, RX VrefLevel [Byte0]: 35
8632 09:33:28.740316 [Byte1]: 35
8633 09:33:28.744702
8634 09:33:28.745238 Set Vref, RX VrefLevel [Byte0]: 36
8635 09:33:28.748249 [Byte1]: 36
8636 09:33:28.752436
8637 09:33:28.752866 Set Vref, RX VrefLevel [Byte0]: 37
8638 09:33:28.755665 [Byte1]: 37
8639 09:33:28.760059
8640 09:33:28.760591 Set Vref, RX VrefLevel [Byte0]: 38
8641 09:33:28.763294 [Byte1]: 38
8642 09:33:28.767863
8643 09:33:28.768394 Set Vref, RX VrefLevel [Byte0]: 39
8644 09:33:28.770738 [Byte1]: 39
8645 09:33:28.775313
8646 09:33:28.775764 Set Vref, RX VrefLevel [Byte0]: 40
8647 09:33:28.778782 [Byte1]: 40
8648 09:33:28.783103
8649 09:33:28.783641 Set Vref, RX VrefLevel [Byte0]: 41
8650 09:33:28.786823 [Byte1]: 41
8651 09:33:28.790506
8652 09:33:28.791039 Set Vref, RX VrefLevel [Byte0]: 42
8653 09:33:28.794390 [Byte1]: 42
8654 09:33:28.798471
8655 09:33:28.799013 Set Vref, RX VrefLevel [Byte0]: 43
8656 09:33:28.801478 [Byte1]: 43
8657 09:33:28.805926
8658 09:33:28.806463 Set Vref, RX VrefLevel [Byte0]: 44
8659 09:33:28.809451 [Byte1]: 44
8660 09:33:28.813223
8661 09:33:28.813698 Set Vref, RX VrefLevel [Byte0]: 45
8662 09:33:28.816414 [Byte1]: 45
8663 09:33:28.821298
8664 09:33:28.821873 Set Vref, RX VrefLevel [Byte0]: 46
8665 09:33:28.824446 [Byte1]: 46
8666 09:33:28.828660
8667 09:33:28.829245 Set Vref, RX VrefLevel [Byte0]: 47
8668 09:33:28.832043 [Byte1]: 47
8669 09:33:28.836463
8670 09:33:28.837031 Set Vref, RX VrefLevel [Byte0]: 48
8671 09:33:28.839544 [Byte1]: 48
8672 09:33:28.844320
8673 09:33:28.844904 Set Vref, RX VrefLevel [Byte0]: 49
8674 09:33:28.846862 [Byte1]: 49
8675 09:33:28.851370
8676 09:33:28.851894 Set Vref, RX VrefLevel [Byte0]: 50
8677 09:33:28.854844 [Byte1]: 50
8678 09:33:28.859206
8679 09:33:28.859695 Set Vref, RX VrefLevel [Byte0]: 51
8680 09:33:28.862513 [Byte1]: 51
8681 09:33:28.866656
8682 09:33:28.867207 Set Vref, RX VrefLevel [Byte0]: 52
8683 09:33:28.870101 [Byte1]: 52
8684 09:33:28.874167
8685 09:33:28.874733 Set Vref, RX VrefLevel [Byte0]: 53
8686 09:33:28.877961 [Byte1]: 53
8687 09:33:28.881919
8688 09:33:28.882468 Set Vref, RX VrefLevel [Byte0]: 54
8689 09:33:28.885210 [Byte1]: 54
8690 09:33:28.889683
8691 09:33:28.890237 Set Vref, RX VrefLevel [Byte0]: 55
8692 09:33:28.893048 [Byte1]: 55
8693 09:33:28.897379
8694 09:33:28.897930 Set Vref, RX VrefLevel [Byte0]: 56
8695 09:33:28.900623 [Byte1]: 56
8696 09:33:28.904918
8697 09:33:28.905469 Set Vref, RX VrefLevel [Byte0]: 57
8698 09:33:28.908330 [Byte1]: 57
8699 09:33:28.912426
8700 09:33:28.912887 Set Vref, RX VrefLevel [Byte0]: 58
8701 09:33:28.915715 [Byte1]: 58
8702 09:33:28.920204
8703 09:33:28.920761 Set Vref, RX VrefLevel [Byte0]: 59
8704 09:33:28.923686 [Byte1]: 59
8705 09:33:28.928348
8706 09:33:28.928902 Set Vref, RX VrefLevel [Byte0]: 60
8707 09:33:28.930777 [Byte1]: 60
8708 09:33:28.935119
8709 09:33:28.935679 Set Vref, RX VrefLevel [Byte0]: 61
8710 09:33:28.939143 [Byte1]: 61
8711 09:33:28.943103
8712 09:33:28.943673 Set Vref, RX VrefLevel [Byte0]: 62
8713 09:33:28.946546 [Byte1]: 62
8714 09:33:28.950574
8715 09:33:28.951123 Set Vref, RX VrefLevel [Byte0]: 63
8716 09:33:28.953710 [Byte1]: 63
8717 09:33:28.958564
8718 09:33:28.959119 Set Vref, RX VrefLevel [Byte0]: 64
8719 09:33:28.961398 [Byte1]: 64
8720 09:33:28.965586
8721 09:33:28.966054 Set Vref, RX VrefLevel [Byte0]: 65
8722 09:33:28.968749 [Byte1]: 65
8723 09:33:28.973084
8724 09:33:28.973565 Set Vref, RX VrefLevel [Byte0]: 66
8725 09:33:28.976408 [Byte1]: 66
8726 09:33:28.981018
8727 09:33:28.981503 Set Vref, RX VrefLevel [Byte0]: 67
8728 09:33:28.983906 [Byte1]: 67
8729 09:33:28.988426
8730 09:33:28.988932 Set Vref, RX VrefLevel [Byte0]: 68
8731 09:33:28.991690 [Byte1]: 68
8732 09:33:28.996326
8733 09:33:28.996843 Set Vref, RX VrefLevel [Byte0]: 69
8734 09:33:28.999564 [Byte1]: 69
8735 09:33:29.004301
8736 09:33:29.004862 Set Vref, RX VrefLevel [Byte0]: 70
8737 09:33:29.007542 [Byte1]: 70
8738 09:33:29.011293
8739 09:33:29.011924 Set Vref, RX VrefLevel [Byte0]: 71
8740 09:33:29.014301 [Byte1]: 71
8741 09:33:29.019349
8742 09:33:29.019964 Set Vref, RX VrefLevel [Byte0]: 72
8743 09:33:29.022687 [Byte1]: 72
8744 09:33:29.026636
8745 09:33:29.027188 Set Vref, RX VrefLevel [Byte0]: 73
8746 09:33:29.029813 [Byte1]: 73
8747 09:33:29.033880
8748 09:33:29.034358 Set Vref, RX VrefLevel [Byte0]: 74
8749 09:33:29.037231 [Byte1]: 74
8750 09:33:29.041602
8751 09:33:29.042066 Set Vref, RX VrefLevel [Byte0]: 75
8752 09:33:29.044961 [Byte1]: 75
8753 09:33:29.050243
8754 09:33:29.050751 Final RX Vref Byte 0 = 52 to rank0
8755 09:33:29.053076 Final RX Vref Byte 1 = 57 to rank0
8756 09:33:29.056145 Final RX Vref Byte 0 = 52 to rank1
8757 09:33:29.059622 Final RX Vref Byte 1 = 57 to rank1==
8758 09:33:29.062711 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 09:33:29.069408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 09:33:29.069964 ==
8761 09:33:29.070333 DQS Delay:
8762 09:33:29.070671 DQS0 = 0, DQS1 = 0
8763 09:33:29.072461 DQM Delay:
8764 09:33:29.072925 DQM0 = 134, DQM1 = 127
8765 09:33:29.075762 DQ Delay:
8766 09:33:29.079085 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8767 09:33:29.082846 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8768 09:33:29.086427 DQ8 =114, DQ9 =114, DQ10 =130, DQ11 =116
8769 09:33:29.088807 DQ12 =134, DQ13 =136, DQ14 =138, DQ15 =138
8770 09:33:29.089355
8771 09:33:29.089728
8772 09:33:29.090067
8773 09:33:29.092403 [DramC_TX_OE_Calibration] TA2
8774 09:33:29.095655 Original DQ_B0 (3 6) =30, OEN = 27
8775 09:33:29.098858 Original DQ_B1 (3 6) =30, OEN = 27
8776 09:33:29.102089 24, 0x0, End_B0=24 End_B1=24
8777 09:33:29.106142 25, 0x0, End_B0=25 End_B1=25
8778 09:33:29.106706 26, 0x0, End_B0=26 End_B1=26
8779 09:33:29.108556 27, 0x0, End_B0=27 End_B1=27
8780 09:33:29.111639 28, 0x0, End_B0=28 End_B1=28
8781 09:33:29.115310 29, 0x0, End_B0=29 End_B1=29
8782 09:33:29.115818 30, 0x0, End_B0=30 End_B1=30
8783 09:33:29.118353 31, 0x4141, End_B0=30 End_B1=30
8784 09:33:29.121978 Byte0 end_step=30 best_step=27
8785 09:33:29.125144 Byte1 end_step=30 best_step=27
8786 09:33:29.128886 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 09:33:29.131846 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 09:33:29.132397
8789 09:33:29.132763
8790 09:33:29.138101 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8791 09:33:29.141796 CH1 RK0: MR19=303, MR18=1A10
8792 09:33:29.148149 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8793 09:33:29.148706
8794 09:33:29.151866 ----->DramcWriteLeveling(PI) begin...
8795 09:33:29.152425 ==
8796 09:33:29.155040 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 09:33:29.158450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 09:33:29.159008 ==
8799 09:33:29.161684 Write leveling (Byte 0): 22 => 22
8800 09:33:29.164556 Write leveling (Byte 1): 28 => 28
8801 09:33:29.168430 DramcWriteLeveling(PI) end<-----
8802 09:33:29.168887
8803 09:33:29.169249 ==
8804 09:33:29.171247 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 09:33:29.174908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 09:33:29.178415 ==
8807 09:33:29.178976 [Gating] SW mode calibration
8808 09:33:29.188215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 09:33:29.191323 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 09:33:29.194591 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 09:33:29.201514 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 09:33:29.204680 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8813 09:33:29.207941 1 4 12 | B1->B0 | 2e2e 2525 | 1 0 | (1 1) (0 0)
8814 09:33:29.214654 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 09:33:29.217867 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 09:33:29.221222 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 09:33:29.227378 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 09:33:29.230589 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 09:33:29.233799 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 09:33:29.240846 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8821 09:33:29.244031 1 5 12 | B1->B0 | 2828 3232 | 0 1 | (0 0) (1 0)
8822 09:33:29.247591 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 09:33:29.254412 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 09:33:29.257183 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 09:33:29.261476 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 09:33:29.267643 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 09:33:29.270868 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 09:33:29.273919 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8829 09:33:29.280684 1 6 12 | B1->B0 | 4444 2d2d | 0 0 | (0 0) (0 0)
8830 09:33:29.284141 1 6 16 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
8831 09:33:29.286976 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 09:33:29.294339 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 09:33:29.296820 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 09:33:29.300826 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 09:33:29.307204 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 09:33:29.310832 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 09:33:29.313653 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8838 09:33:29.320453 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 09:33:29.323778 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 09:33:29.326745 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 09:33:29.333740 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 09:33:29.336705 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 09:33:29.340115 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 09:33:29.346272 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 09:33:29.349778 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 09:33:29.353058 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 09:33:29.359601 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 09:33:29.363060 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 09:33:29.366498 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 09:33:29.373286 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 09:33:29.376231 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 09:33:29.379595 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8853 09:33:29.386340 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8854 09:33:29.389149 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 09:33:29.393072 Total UI for P1: 0, mck2ui 16
8856 09:33:29.396698 best dqsien dly found for B0: ( 1, 9, 12)
8857 09:33:29.399402 Total UI for P1: 0, mck2ui 16
8858 09:33:29.402793 best dqsien dly found for B1: ( 1, 9, 10)
8859 09:33:29.405901 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8860 09:33:29.408983 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8861 09:33:29.409452
8862 09:33:29.412802 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8863 09:33:29.415598 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8864 09:33:29.419298 [Gating] SW calibration Done
8865 09:33:29.419923 ==
8866 09:33:29.422604 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 09:33:29.425950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 09:33:29.429291 ==
8869 09:33:29.429845 RX Vref Scan: 0
8870 09:33:29.430214
8871 09:33:29.432226 RX Vref 0 -> 0, step: 1
8872 09:33:29.432836
8873 09:33:29.435926 RX Delay 0 -> 252, step: 8
8874 09:33:29.438591 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8875 09:33:29.442279 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8876 09:33:29.445891 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8877 09:33:29.449367 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8878 09:33:29.455758 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8879 09:33:29.458927 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8880 09:33:29.462092 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8881 09:33:29.465678 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8882 09:33:29.469324 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8883 09:33:29.475259 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8884 09:33:29.478809 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8885 09:33:29.481933 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8886 09:33:29.485260 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8887 09:33:29.488949 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8888 09:33:29.495679 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8889 09:33:29.498797 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8890 09:33:29.499350 ==
8891 09:33:29.502146 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 09:33:29.505498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 09:33:29.505957 ==
8894 09:33:29.508662 DQS Delay:
8895 09:33:29.509117 DQS0 = 0, DQS1 = 0
8896 09:33:29.509475 DQM Delay:
8897 09:33:29.511911 DQM0 = 138, DQM1 = 129
8898 09:33:29.512368 DQ Delay:
8899 09:33:29.515341 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8900 09:33:29.518161 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8901 09:33:29.525070 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8902 09:33:29.528341 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8903 09:33:29.528802
8904 09:33:29.529162
8905 09:33:29.529497 ==
8906 09:33:29.531415 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 09:33:29.534951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 09:33:29.535361 ==
8909 09:33:29.535690
8910 09:33:29.536051
8911 09:33:29.537867 TX Vref Scan disable
8912 09:33:29.541732 == TX Byte 0 ==
8913 09:33:29.544642 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8914 09:33:29.548040 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8915 09:33:29.551767 == TX Byte 1 ==
8916 09:33:29.555137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8917 09:33:29.557713 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 09:33:29.558170 ==
8919 09:33:29.561972 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 09:33:29.564418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 09:33:29.567570 ==
8922 09:33:29.580499
8923 09:33:29.583865 TX Vref early break, caculate TX vref
8924 09:33:29.587837 TX Vref=16, minBit 0, minWin=22, winSum=379
8925 09:33:29.590588 TX Vref=18, minBit 0, minWin=22, winSum=392
8926 09:33:29.593756 TX Vref=20, minBit 1, minWin=23, winSum=398
8927 09:33:29.597121 TX Vref=22, minBit 1, minWin=23, winSum=406
8928 09:33:29.600489 TX Vref=24, minBit 0, minWin=24, winSum=415
8929 09:33:29.607417 TX Vref=26, minBit 0, minWin=24, winSum=417
8930 09:33:29.610453 TX Vref=28, minBit 0, minWin=23, winSum=418
8931 09:33:29.613711 TX Vref=30, minBit 0, minWin=24, winSum=417
8932 09:33:29.616577 TX Vref=32, minBit 0, minWin=23, winSum=405
8933 09:33:29.620143 TX Vref=34, minBit 0, minWin=23, winSum=399
8934 09:33:29.623696 TX Vref=36, minBit 0, minWin=22, winSum=390
8935 09:33:29.629991 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8936 09:33:29.630551
8937 09:33:29.633017 Final TX Range 0 Vref 26
8938 09:33:29.633474
8939 09:33:29.633838 ==
8940 09:33:29.636428 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 09:33:29.640065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 09:33:29.640525 ==
8943 09:33:29.642980
8944 09:33:29.643431
8945 09:33:29.643849 TX Vref Scan disable
8946 09:33:29.649909 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8947 09:33:29.650485 == TX Byte 0 ==
8948 09:33:29.653532 u2DelayCellOfst[0]=18 cells (5 PI)
8949 09:33:29.656608 u2DelayCellOfst[1]=11 cells (3 PI)
8950 09:33:29.659987 u2DelayCellOfst[2]=0 cells (0 PI)
8951 09:33:29.663479 u2DelayCellOfst[3]=3 cells (1 PI)
8952 09:33:29.666185 u2DelayCellOfst[4]=7 cells (2 PI)
8953 09:33:29.669652 u2DelayCellOfst[5]=18 cells (5 PI)
8954 09:33:29.672825 u2DelayCellOfst[6]=18 cells (5 PI)
8955 09:33:29.676000 u2DelayCellOfst[7]=3 cells (1 PI)
8956 09:33:29.679210 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8957 09:33:29.682746 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8958 09:33:29.685719 == TX Byte 1 ==
8959 09:33:29.689214 u2DelayCellOfst[8]=0 cells (0 PI)
8960 09:33:29.692901 u2DelayCellOfst[9]=3 cells (1 PI)
8961 09:33:29.696551 u2DelayCellOfst[10]=11 cells (3 PI)
8962 09:33:29.699505 u2DelayCellOfst[11]=7 cells (2 PI)
8963 09:33:29.702651 u2DelayCellOfst[12]=14 cells (4 PI)
8964 09:33:29.706090 u2DelayCellOfst[13]=14 cells (4 PI)
8965 09:33:29.709133 u2DelayCellOfst[14]=18 cells (5 PI)
8966 09:33:29.709590 u2DelayCellOfst[15]=18 cells (5 PI)
8967 09:33:29.715798 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8968 09:33:29.719080 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 09:33:29.722354 DramC Write-DBI on
8970 09:33:29.722929 ==
8971 09:33:29.725461 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 09:33:29.728817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 09:33:29.729458 ==
8974 09:33:29.729987
8975 09:33:29.730530
8976 09:33:29.731624 TX Vref Scan disable
8977 09:33:29.732124 == TX Byte 0 ==
8978 09:33:29.739185 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8979 09:33:29.740116 == TX Byte 1 ==
8980 09:33:29.741737 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8981 09:33:29.745282 DramC Write-DBI off
8982 09:33:29.745793
8983 09:33:29.746153 [DATLAT]
8984 09:33:29.748395 Freq=1600, CH1 RK1
8985 09:33:29.748808
8986 09:33:29.749134 DATLAT Default: 0xf
8987 09:33:29.752204 0, 0xFFFF, sum = 0
8988 09:33:29.755090 1, 0xFFFF, sum = 0
8989 09:33:29.755508 2, 0xFFFF, sum = 0
8990 09:33:29.758735 3, 0xFFFF, sum = 0
8991 09:33:29.759224 4, 0xFFFF, sum = 0
8992 09:33:29.761886 5, 0xFFFF, sum = 0
8993 09:33:29.762305 6, 0xFFFF, sum = 0
8994 09:33:29.764928 7, 0xFFFF, sum = 0
8995 09:33:29.765348 8, 0xFFFF, sum = 0
8996 09:33:29.768370 9, 0xFFFF, sum = 0
8997 09:33:29.768928 10, 0xFFFF, sum = 0
8998 09:33:29.771519 11, 0xFFFF, sum = 0
8999 09:33:29.771987 12, 0xFFFF, sum = 0
9000 09:33:29.774884 13, 0xFFFF, sum = 0
9001 09:33:29.775301 14, 0x0, sum = 1
9002 09:33:29.778014 15, 0x0, sum = 2
9003 09:33:29.778483 16, 0x0, sum = 3
9004 09:33:29.781620 17, 0x0, sum = 4
9005 09:33:29.782055 best_step = 15
9006 09:33:29.782382
9007 09:33:29.782691 ==
9008 09:33:29.784727 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 09:33:29.791643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 09:33:29.792195 ==
9011 09:33:29.792530 RX Vref Scan: 0
9012 09:33:29.792839
9013 09:33:29.794840 RX Vref 0 -> 0, step: 1
9014 09:33:29.795354
9015 09:33:29.798220 RX Delay 11 -> 252, step: 4
9016 09:33:29.801651 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9017 09:33:29.804815 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9018 09:33:29.811702 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9019 09:33:29.814317 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9020 09:33:29.817792 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9021 09:33:29.821168 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9022 09:33:29.824536 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9023 09:33:29.827765 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9024 09:33:29.834428 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9025 09:33:29.837596 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9026 09:33:29.840794 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9027 09:33:29.844520 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9028 09:33:29.850798 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9029 09:33:29.853838 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9030 09:33:29.857584 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9031 09:33:29.860492 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9032 09:33:29.860905 ==
9033 09:33:29.864144 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 09:33:29.870450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 09:33:29.870966 ==
9036 09:33:29.871300 DQS Delay:
9037 09:33:29.873931 DQS0 = 0, DQS1 = 0
9038 09:33:29.874446 DQM Delay:
9039 09:33:29.874780 DQM0 = 134, DQM1 = 126
9040 09:33:29.877094 DQ Delay:
9041 09:33:29.880687 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
9042 09:33:29.883932 DQ4 =134, DQ5 =144, DQ6 =148, DQ7 =130
9043 09:33:29.887259 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9044 09:33:29.890244 DQ12 =138, DQ13 =134, DQ14 =132, DQ15 =138
9045 09:33:29.890656
9046 09:33:29.890983
9047 09:33:29.891285
9048 09:33:29.893726 [DramC_TX_OE_Calibration] TA2
9049 09:33:29.897042 Original DQ_B0 (3 6) =30, OEN = 27
9050 09:33:29.900084 Original DQ_B1 (3 6) =30, OEN = 27
9051 09:33:29.903403 24, 0x0, End_B0=24 End_B1=24
9052 09:33:29.903860 25, 0x0, End_B0=25 End_B1=25
9053 09:33:29.907430 26, 0x0, End_B0=26 End_B1=26
9054 09:33:29.910462 27, 0x0, End_B0=27 End_B1=27
9055 09:33:29.913967 28, 0x0, End_B0=28 End_B1=28
9056 09:33:29.917149 29, 0x0, End_B0=29 End_B1=29
9057 09:33:29.917677 30, 0x0, End_B0=30 End_B1=30
9058 09:33:29.920032 31, 0x4141, End_B0=30 End_B1=30
9059 09:33:29.923682 Byte0 end_step=30 best_step=27
9060 09:33:29.926547 Byte1 end_step=30 best_step=27
9061 09:33:29.930674 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 09:33:29.933907 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 09:33:29.934430
9064 09:33:29.934761
9065 09:33:29.939955 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9066 09:33:29.943501 CH1 RK1: MR19=303, MR18=E0A
9067 09:33:29.949804 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9068 09:33:29.953194 [RxdqsGatingPostProcess] freq 1600
9069 09:33:29.956737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 09:33:29.959708 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 09:33:29.963035 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 09:33:29.966467 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 09:33:29.969859 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 09:33:29.972583 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 09:33:29.975999 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 09:33:29.979406 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 09:33:29.982867 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 09:33:29.986091 Pre-setting of DQS Precalculation
9079 09:33:29.989233 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 09:33:29.996261 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 09:33:30.006061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 09:33:30.006580
9083 09:33:30.006907
9084 09:33:30.009365 [Calibration Summary] 3200 Mbps
9085 09:33:30.009882 CH 0, Rank 0
9086 09:33:30.013209 SW Impedance : PASS
9087 09:33:30.013729 DUTY Scan : NO K
9088 09:33:30.016671 ZQ Calibration : PASS
9089 09:33:30.018999 Jitter Meter : NO K
9090 09:33:30.019633 CBT Training : PASS
9091 09:33:30.022551 Write leveling : PASS
9092 09:33:30.025934 RX DQS gating : PASS
9093 09:33:30.026461 RX DQ/DQS(RDDQC) : PASS
9094 09:33:30.028727 TX DQ/DQS : PASS
9095 09:33:30.032173 RX DATLAT : PASS
9096 09:33:30.032718 RX DQ/DQS(Engine): PASS
9097 09:33:30.036032 TX OE : PASS
9098 09:33:30.036445 All Pass.
9099 09:33:30.036846
9100 09:33:30.038796 CH 0, Rank 1
9101 09:33:30.039238 SW Impedance : PASS
9102 09:33:30.042416 DUTY Scan : NO K
9103 09:33:30.045500 ZQ Calibration : PASS
9104 09:33:30.046022 Jitter Meter : NO K
9105 09:33:30.048997 CBT Training : PASS
9106 09:33:30.049407 Write leveling : PASS
9107 09:33:30.052198 RX DQS gating : PASS
9108 09:33:30.055053 RX DQ/DQS(RDDQC) : PASS
9109 09:33:30.055466 TX DQ/DQS : PASS
9110 09:33:30.058277 RX DATLAT : PASS
9111 09:33:30.062301 RX DQ/DQS(Engine): PASS
9112 09:33:30.062818 TX OE : PASS
9113 09:33:30.065288 All Pass.
9114 09:33:30.065853
9115 09:33:30.066187 CH 1, Rank 0
9116 09:33:30.069083 SW Impedance : PASS
9117 09:33:30.069640 DUTY Scan : NO K
9118 09:33:30.071648 ZQ Calibration : PASS
9119 09:33:30.074982 Jitter Meter : NO K
9120 09:33:30.075492 CBT Training : PASS
9121 09:33:30.078143 Write leveling : PASS
9122 09:33:30.081729 RX DQS gating : PASS
9123 09:33:30.082249 RX DQ/DQS(RDDQC) : PASS
9124 09:33:30.084513 TX DQ/DQS : PASS
9125 09:33:30.088347 RX DATLAT : PASS
9126 09:33:30.088862 RX DQ/DQS(Engine): PASS
9127 09:33:30.091115 TX OE : PASS
9128 09:33:30.091530 All Pass.
9129 09:33:30.091954
9130 09:33:30.094592 CH 1, Rank 1
9131 09:33:30.095003 SW Impedance : PASS
9132 09:33:30.097828 DUTY Scan : NO K
9133 09:33:30.101483 ZQ Calibration : PASS
9134 09:33:30.102014 Jitter Meter : NO K
9135 09:33:30.104717 CBT Training : PASS
9136 09:33:30.108402 Write leveling : PASS
9137 09:33:30.109077 RX DQS gating : PASS
9138 09:33:30.111933 RX DQ/DQS(RDDQC) : PASS
9139 09:33:30.115080 TX DQ/DQS : PASS
9140 09:33:30.115597 RX DATLAT : PASS
9141 09:33:30.118033 RX DQ/DQS(Engine): PASS
9142 09:33:30.118524 TX OE : PASS
9143 09:33:30.121453 All Pass.
9144 09:33:30.121961
9145 09:33:30.122289 DramC Write-DBI on
9146 09:33:30.125145 PER_BANK_REFRESH: Hybrid Mode
9147 09:33:30.128014 TX_TRACKING: ON
9148 09:33:30.134676 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 09:33:30.144697 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 09:33:30.151066 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 09:33:30.154144 [FAST_K] Save calibration result to emmc
9152 09:33:30.158194 sync common calibartion params.
9153 09:33:30.158770 sync cbt_mode0:1, 1:1
9154 09:33:30.161089 dram_init: ddr_geometry: 2
9155 09:33:30.164263 dram_init: ddr_geometry: 2
9156 09:33:30.167860 dram_init: ddr_geometry: 2
9157 09:33:30.168438 0:dram_rank_size:100000000
9158 09:33:30.171294 1:dram_rank_size:100000000
9159 09:33:30.177278 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 09:33:30.177869 DFS_SHUFFLE_HW_MODE: ON
9161 09:33:30.183916 dramc_set_vcore_voltage set vcore to 725000
9162 09:33:30.184522 Read voltage for 1600, 0
9163 09:33:30.187319 Vio18 = 0
9164 09:33:30.187939 Vcore = 725000
9165 09:33:30.188469 Vdram = 0
9166 09:33:30.190271 Vddq = 0
9167 09:33:30.190744 Vmddr = 0
9168 09:33:30.194037 switch to 3200 Mbps bootup
9169 09:33:30.194609 [DramcRunTimeConfig]
9170 09:33:30.195092 PHYPLL
9171 09:33:30.197181 DPM_CONTROL_AFTERK: ON
9172 09:33:30.200654 PER_BANK_REFRESH: ON
9173 09:33:30.201227 REFRESH_OVERHEAD_REDUCTION: ON
9174 09:33:30.203791 CMD_PICG_NEW_MODE: OFF
9175 09:33:30.207032 XRTWTW_NEW_MODE: ON
9176 09:33:30.207604 XRTRTR_NEW_MODE: ON
9177 09:33:30.210335 TX_TRACKING: ON
9178 09:33:30.210933 RDSEL_TRACKING: OFF
9179 09:33:30.213918 DQS Precalculation for DVFS: ON
9180 09:33:30.214486 RX_TRACKING: OFF
9181 09:33:30.217372 HW_GATING DBG: ON
9182 09:33:30.219998 ZQCS_ENABLE_LP4: ON
9183 09:33:30.220555 RX_PICG_NEW_MODE: ON
9184 09:33:30.223847 TX_PICG_NEW_MODE: ON
9185 09:33:30.224410 ENABLE_RX_DCM_DPHY: ON
9186 09:33:30.226847 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 09:33:30.230108 DUMMY_READ_FOR_TRACKING: OFF
9188 09:33:30.233765 !!! SPM_CONTROL_AFTERK: OFF
9189 09:33:30.237003 !!! SPM could not control APHY
9190 09:33:30.237604 IMPEDANCE_TRACKING: ON
9191 09:33:30.240281 TEMP_SENSOR: ON
9192 09:33:30.240737 HW_SAVE_FOR_SR: OFF
9193 09:33:30.243675 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 09:33:30.247418 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 09:33:30.250336 Read ODT Tracking: ON
9196 09:33:30.253533 Refresh Rate DeBounce: ON
9197 09:33:30.254090 DFS_NO_QUEUE_FLUSH: ON
9198 09:33:30.256583 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 09:33:30.259611 ENABLE_DFS_RUNTIME_MRW: OFF
9200 09:33:30.263318 DDR_RESERVE_NEW_MODE: ON
9201 09:33:30.263922 MR_CBT_SWITCH_FREQ: ON
9202 09:33:30.266510 =========================
9203 09:33:30.285182 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 09:33:30.288664 dram_init: ddr_geometry: 2
9205 09:33:30.306681 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 09:33:30.310153 dram_init: dram init end (result: 0)
9207 09:33:30.316620 DRAM-K: Full calibration passed in 24656 msecs
9208 09:33:30.320114 MRC: failed to locate region type 0.
9209 09:33:30.320917 DRAM rank0 size:0x100000000,
9210 09:33:30.322853 DRAM rank1 size=0x100000000
9211 09:33:30.333025 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 09:33:30.339676 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 09:33:30.346234 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 09:33:30.352768 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 09:33:30.356375 DRAM rank0 size:0x100000000,
9216 09:33:30.359473 DRAM rank1 size=0x100000000
9217 09:33:30.360107 CBMEM:
9218 09:33:30.362513 IMD: root @ 0xfffff000 254 entries.
9219 09:33:30.366205 IMD: root @ 0xffffec00 62 entries.
9220 09:33:30.369086 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 09:33:30.376276 WARNING: RO_VPD is uninitialized or empty.
9222 09:33:30.379387 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 09:33:30.386635 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 09:33:30.399450 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9225 09:33:30.411131 BS: romstage times (exec / console): total (unknown) / 24141 ms
9226 09:33:30.411671
9227 09:33:30.412095
9228 09:33:30.420319 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 09:33:30.423965 ARM64: Exception handlers installed.
9230 09:33:30.426843 ARM64: Testing exception
9231 09:33:30.430819 ARM64: Done test exception
9232 09:33:30.431371 Enumerating buses...
9233 09:33:30.434045 Show all devs... Before device enumeration.
9234 09:33:30.436903 Root Device: enabled 1
9235 09:33:30.440041 CPU_CLUSTER: 0: enabled 1
9236 09:33:30.440498 CPU: 00: enabled 1
9237 09:33:30.443687 Compare with tree...
9238 09:33:30.447197 Root Device: enabled 1
9239 09:33:30.447803 CPU_CLUSTER: 0: enabled 1
9240 09:33:30.450048 CPU: 00: enabled 1
9241 09:33:30.450603 Root Device scanning...
9242 09:33:30.453032 scan_static_bus for Root Device
9243 09:33:30.456525 CPU_CLUSTER: 0 enabled
9244 09:33:30.459971 scan_static_bus for Root Device done
9245 09:33:30.463373 scan_bus: bus Root Device finished in 8 msecs
9246 09:33:30.463883 done
9247 09:33:30.469631 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 09:33:30.472616 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 09:33:30.479466 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 09:33:30.486396 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 09:33:30.486915 Allocating resources...
9252 09:33:30.489508 Reading resources...
9253 09:33:30.492742 Root Device read_resources bus 0 link: 0
9254 09:33:30.496560 DRAM rank0 size:0x100000000,
9255 09:33:30.497112 DRAM rank1 size=0x100000000
9256 09:33:30.503402 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 09:33:30.504009 CPU: 00 missing read_resources
9258 09:33:30.509517 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 09:33:30.512564 Root Device read_resources bus 0 link: 0 done
9260 09:33:30.516334 Done reading resources.
9261 09:33:30.519294 Show resources in subtree (Root Device)...After reading.
9262 09:33:30.522266 Root Device child on link 0 CPU_CLUSTER: 0
9263 09:33:30.525837 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 09:33:30.535445 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 09:33:30.536139 CPU: 00
9266 09:33:30.542280 Root Device assign_resources, bus 0 link: 0
9267 09:33:30.545662 CPU_CLUSTER: 0 missing set_resources
9268 09:33:30.548746 Root Device assign_resources, bus 0 link: 0 done
9269 09:33:30.552315 Done setting resources.
9270 09:33:30.555396 Show resources in subtree (Root Device)...After assigning values.
9271 09:33:30.562359 Root Device child on link 0 CPU_CLUSTER: 0
9272 09:33:30.565341 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 09:33:30.571919 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 09:33:30.575317 CPU: 00
9275 09:33:30.575926 Done allocating resources.
9276 09:33:30.582358 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 09:33:30.582975 Enabling resources...
9278 09:33:30.585468 done.
9279 09:33:30.588342 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 09:33:30.591889 Initializing devices...
9281 09:33:30.592440 Root Device init
9282 09:33:30.595141 init hardware done!
9283 09:33:30.595699 0x00000018: ctrlr->caps
9284 09:33:30.598924 52.000 MHz: ctrlr->f_max
9285 09:33:30.601591 0.400 MHz: ctrlr->f_min
9286 09:33:30.604664 0x40ff8080: ctrlr->voltages
9287 09:33:30.605235 sclk: 390625
9288 09:33:30.605679 Bus Width = 1
9289 09:33:30.608139 sclk: 390625
9290 09:33:30.608697 Bus Width = 1
9291 09:33:30.611606 Early init status = 3
9292 09:33:30.614670 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 09:33:30.618713 in-header: 03 fc 00 00 01 00 00 00
9294 09:33:30.622212 in-data: 00
9295 09:33:30.625749 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9296 09:33:30.630664 in-header: 03 fd 00 00 00 00 00 00
9297 09:33:30.634066 in-data:
9298 09:33:30.637556 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9299 09:33:30.640668 in-header: 03 fc 00 00 01 00 00 00
9300 09:33:30.644057 in-data: 00
9301 09:33:30.647283 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9302 09:33:30.652496 in-header: 03 fd 00 00 00 00 00 00
9303 09:33:30.655382 in-data:
9304 09:33:30.658929 [SSUSB] Setting up USB HOST controller...
9305 09:33:30.662080 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9306 09:33:30.665185 [SSUSB] phy power-on done.
9307 09:33:30.668314 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9308 09:33:30.674855 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9309 09:33:30.678566 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9310 09:33:30.685191 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9311 09:33:30.692277 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9312 09:33:30.698387 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9313 09:33:30.704675 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9314 09:33:30.711457 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9315 09:33:30.714540 SPM: binary array size = 0x9dc
9316 09:33:30.718128 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9317 09:33:30.724866 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9318 09:33:30.731288 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9319 09:33:30.737507 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9320 09:33:30.740327 configure_display: Starting display init
9321 09:33:30.775435 anx7625_power_on_init: Init interface.
9322 09:33:30.778480 anx7625_disable_pd_protocol: Disabled PD feature.
9323 09:33:30.781974 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9324 09:33:30.809576 anx7625_start_dp_work: Secure OCM version=00
9325 09:33:30.812580 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9326 09:33:30.828218 sp_tx_get_edid_block: EDID Block = 1
9327 09:33:30.930535 Extracted contents:
9328 09:33:30.933704 header: 00 ff ff ff ff ff ff 00
9329 09:33:30.936862 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9330 09:33:30.940635 version: 01 04
9331 09:33:30.943855 basic params: 95 1f 11 78 0a
9332 09:33:30.946870 chroma info: 76 90 94 55 54 90 27 21 50 54
9333 09:33:30.950579 established: 00 00 00
9334 09:33:30.956612 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9335 09:33:30.963226 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9336 09:33:30.966492 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 09:33:30.973513 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9338 09:33:30.980149 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9339 09:33:30.983609 extensions: 00
9340 09:33:30.984206 checksum: fb
9341 09:33:30.984573
9342 09:33:30.986477 Manufacturer: IVO Model 57d Serial Number 0
9343 09:33:30.989997 Made week 0 of 2020
9344 09:33:30.992874 EDID version: 1.4
9345 09:33:30.993333 Digital display
9346 09:33:30.996627 6 bits per primary color channel
9347 09:33:30.997190 DisplayPort interface
9348 09:33:30.999460 Maximum image size: 31 cm x 17 cm
9349 09:33:31.002508 Gamma: 220%
9350 09:33:31.002987 Check DPMS levels
9351 09:33:31.009748 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9352 09:33:31.012612 First detailed timing is preferred timing
9353 09:33:31.013126 Established timings supported:
9354 09:33:31.016275 Standard timings supported:
9355 09:33:31.019576 Detailed timings
9356 09:33:31.022508 Hex of detail: 383680a07038204018303c0035ae10000019
9357 09:33:31.029039 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9358 09:33:31.032195 0780 0798 07c8 0820 hborder 0
9359 09:33:31.036111 0438 043b 0447 0458 vborder 0
9360 09:33:31.039564 -hsync -vsync
9361 09:33:31.040172 Did detailed timing
9362 09:33:31.046200 Hex of detail: 000000000000000000000000000000000000
9363 09:33:31.048732 Manufacturer-specified data, tag 0
9364 09:33:31.052310 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9365 09:33:31.055835 ASCII string: InfoVision
9366 09:33:31.059174 Hex of detail: 000000fe00523134304e574635205248200a
9367 09:33:31.062052 ASCII string: R140NWF5 RH
9368 09:33:31.062509 Checksum
9369 09:33:31.065983 Checksum: 0xfb (valid)
9370 09:33:31.068667 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9371 09:33:31.072407 DSI data_rate: 832800000 bps
9372 09:33:31.078667 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9373 09:33:31.082451 anx7625_parse_edid: pixelclock(138800).
9374 09:33:31.085047 hactive(1920), hsync(48), hfp(24), hbp(88)
9375 09:33:31.088743 vactive(1080), vsync(12), vfp(3), vbp(17)
9376 09:33:31.092332 anx7625_dsi_config: config dsi.
9377 09:33:31.098788 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9378 09:33:31.112430 anx7625_dsi_config: success to config DSI
9379 09:33:31.115477 anx7625_dp_start: MIPI phy setup OK.
9380 09:33:31.119177 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9381 09:33:31.122081 mtk_ddp_mode_set invalid vrefresh 60
9382 09:33:31.125080 main_disp_path_setup
9383 09:33:31.125600 ovl_layer_smi_id_en
9384 09:33:31.128448 ovl_layer_smi_id_en
9385 09:33:31.128940 ccorr_config
9386 09:33:31.129315 aal_config
9387 09:33:31.132192 gamma_config
9388 09:33:31.132647 postmask_config
9389 09:33:31.135063 dither_config
9390 09:33:31.138789 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9391 09:33:31.145846 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9392 09:33:31.148461 Root Device init finished in 552 msecs
9393 09:33:31.152114 CPU_CLUSTER: 0 init
9394 09:33:31.158914 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9395 09:33:31.165050 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9396 09:33:31.165513 APU_MBOX 0x190000b0 = 0x10001
9397 09:33:31.168192 APU_MBOX 0x190001b0 = 0x10001
9398 09:33:31.171711 APU_MBOX 0x190005b0 = 0x10001
9399 09:33:31.175256 APU_MBOX 0x190006b0 = 0x10001
9400 09:33:31.181323 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9401 09:33:31.191690 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9402 09:33:31.203952 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9403 09:33:31.210551 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9404 09:33:31.222145 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9405 09:33:31.231050 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9406 09:33:31.234481 CPU_CLUSTER: 0 init finished in 81 msecs
9407 09:33:31.237773 Devices initialized
9408 09:33:31.241230 Show all devs... After init.
9409 09:33:31.241698 Root Device: enabled 1
9410 09:33:31.244292 CPU_CLUSTER: 0: enabled 1
9411 09:33:31.247611 CPU: 00: enabled 1
9412 09:33:31.251228 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9413 09:33:31.254426 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9414 09:33:31.257155 ELOG: NV offset 0x57f000 size 0x1000
9415 09:33:31.264219 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9416 09:33:31.270934 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9417 09:33:31.274285 ELOG: Event(17) added with size 13 at 2023-10-20 09:33:32 UTC
9418 09:33:31.280872 out: cmd=0x121: 03 db 21 01 00 00 00 00
9419 09:33:31.284479 in-header: 03 a2 00 00 2c 00 00 00
9420 09:33:31.293689 in-data: bd 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9421 09:33:31.300436 ELOG: Event(A1) added with size 10 at 2023-10-20 09:33:32 UTC
9422 09:33:31.307582 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9423 09:33:31.313935 ELOG: Event(A0) added with size 9 at 2023-10-20 09:33:32 UTC
9424 09:33:31.317118 elog_add_boot_reason: Logged dev mode boot
9425 09:33:31.324136 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9426 09:33:31.324721 Finalize devices...
9427 09:33:31.327034 Devices finalized
9428 09:33:31.330071 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9429 09:33:31.333691 Writing coreboot table at 0xffe64000
9430 09:33:31.336444 0. 000000000010a000-0000000000113fff: RAMSTAGE
9431 09:33:31.343193 1. 0000000040000000-00000000400fffff: RAM
9432 09:33:31.346198 2. 0000000040100000-000000004032afff: RAMSTAGE
9433 09:33:31.349673 3. 000000004032b000-00000000545fffff: RAM
9434 09:33:31.352881 4. 0000000054600000-000000005465ffff: BL31
9435 09:33:31.356363 5. 0000000054660000-00000000ffe63fff: RAM
9436 09:33:31.362884 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9437 09:33:31.366553 7. 0000000100000000-000000023fffffff: RAM
9438 09:33:31.369339 Passing 5 GPIOs to payload:
9439 09:33:31.372651 NAME | PORT | POLARITY | VALUE
9440 09:33:31.379691 EC in RW | 0x000000aa | low | undefined
9441 09:33:31.382823 EC interrupt | 0x00000005 | low | undefined
9442 09:33:31.389250 TPM interrupt | 0x000000ab | high | undefined
9443 09:33:31.393449 SD card detect | 0x00000011 | high | undefined
9444 09:33:31.395934 speaker enable | 0x00000093 | high | undefined
9445 09:33:31.399012 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9446 09:33:31.402536 in-header: 03 f9 00 00 02 00 00 00
9447 09:33:31.406023 in-data: 02 00
9448 09:33:31.409383 ADC[4]: Raw value=903031 ID=7
9449 09:33:31.412236 ADC[3]: Raw value=212912 ID=1
9450 09:33:31.412702 RAM Code: 0x71
9451 09:33:31.415698 ADC[6]: Raw value=75036 ID=0
9452 09:33:31.419187 ADC[5]: Raw value=213652 ID=1
9453 09:33:31.419806 SKU Code: 0x1
9454 09:33:31.425699 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9455 09:33:31.426311 coreboot table: 964 bytes.
9456 09:33:31.429128 IMD ROOT 0. 0xfffff000 0x00001000
9457 09:33:31.432347 IMD SMALL 1. 0xffffe000 0x00001000
9458 09:33:31.435533 RO MCACHE 2. 0xffffc000 0x00001104
9459 09:33:31.438633 CONSOLE 3. 0xfff7c000 0x00080000
9460 09:33:31.442023 FMAP 4. 0xfff7b000 0x00000452
9461 09:33:31.445938 TIME STAMP 5. 0xfff7a000 0x00000910
9462 09:33:31.448944 VBOOT WORK 6. 0xfff66000 0x00014000
9463 09:33:31.452193 RAMOOPS 7. 0xffe66000 0x00100000
9464 09:33:31.455247 COREBOOT 8. 0xffe64000 0x00002000
9465 09:33:31.458930 IMD small region:
9466 09:33:31.462204 IMD ROOT 0. 0xffffec00 0x00000400
9467 09:33:31.465520 VPD 1. 0xffffeb80 0x0000006c
9468 09:33:31.468723 MMC STATUS 2. 0xffffeb60 0x00000004
9469 09:33:31.475542 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9470 09:33:31.476175 Probing TPM: done!
9471 09:33:31.478945 Connected to device vid:did:rid of 1ae0:0028:00
9472 09:33:31.490515 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9473 09:33:31.493292 Initialized TPM device CR50 revision 0
9474 09:33:31.496506 Checking cr50 for pending updates
9475 09:33:31.501014 Reading cr50 TPM mode
9476 09:33:31.509209 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9477 09:33:31.516274 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9478 09:33:31.556127 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9479 09:33:31.559653 Checking segment from ROM address 0x40100000
9480 09:33:31.565572 Checking segment from ROM address 0x4010001c
9481 09:33:31.569725 Loading segment from ROM address 0x40100000
9482 09:33:31.570282 code (compression=0)
9483 09:33:31.578945 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9484 09:33:31.586096 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9485 09:33:31.589149 it's not compressed!
9486 09:33:31.592514 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9487 09:33:31.599090 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9488 09:33:31.616464 Loading segment from ROM address 0x4010001c
9489 09:33:31.617026 Entry Point 0x80000000
9490 09:33:31.619772 Loaded segments
9491 09:33:31.623203 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9492 09:33:31.630151 Jumping to boot code at 0x80000000(0xffe64000)
9493 09:33:31.637150 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9494 09:33:31.643191 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9495 09:33:31.651141 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9496 09:33:31.654320 Checking segment from ROM address 0x40100000
9497 09:33:31.657393 Checking segment from ROM address 0x4010001c
9498 09:33:31.663907 Loading segment from ROM address 0x40100000
9499 09:33:31.664377 code (compression=1)
9500 09:33:31.670781 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9501 09:33:31.680697 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9502 09:33:31.681336 using LZMA
9503 09:33:31.689835 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9504 09:33:31.695850 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9505 09:33:31.699486 Loading segment from ROM address 0x4010001c
9506 09:33:31.700127 Entry Point 0x54601000
9507 09:33:31.702520 Loaded segments
9508 09:33:31.705941 NOTICE: MT8192 bl31_setup
9509 09:33:31.713000 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9510 09:33:31.716495 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9511 09:33:31.719898 WARNING: region 0:
9512 09:33:31.723223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 09:33:31.723840 WARNING: region 1:
9514 09:33:31.729280 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9515 09:33:31.732547 WARNING: region 2:
9516 09:33:31.736076 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9517 09:33:31.739362 WARNING: region 3:
9518 09:33:31.742662 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 09:33:31.746057 WARNING: region 4:
9520 09:33:31.752802 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 09:33:31.753363 WARNING: region 5:
9522 09:33:31.756329 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 09:33:31.759370 WARNING: region 6:
9524 09:33:31.762962 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 09:33:31.765943 WARNING: region 7:
9526 09:33:31.769252 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 09:33:31.776148 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9528 09:33:31.779453 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9529 09:33:31.782563 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9530 09:33:31.789849 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9531 09:33:31.792461 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9532 09:33:31.795697 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9533 09:33:31.802636 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9534 09:33:31.805977 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9535 09:33:31.812388 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9536 09:33:31.815697 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9537 09:33:31.819048 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9538 09:33:31.826225 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9539 09:33:31.829071 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9540 09:33:31.832434 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9541 09:33:31.839264 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9542 09:33:31.842426 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9543 09:33:31.849228 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9544 09:33:31.852444 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9545 09:33:31.855521 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9546 09:33:31.863142 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9547 09:33:31.865415 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9548 09:33:31.872187 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9549 09:33:31.875587 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9550 09:33:31.879028 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9551 09:33:31.885498 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9552 09:33:31.888974 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9553 09:33:31.896166 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9554 09:33:31.899143 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9555 09:33:31.902625 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9556 09:33:31.908464 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9557 09:33:31.912139 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9558 09:33:31.918921 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9559 09:33:31.922305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9560 09:33:31.925440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9561 09:33:31.928795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9562 09:33:31.935110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9563 09:33:31.938309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9564 09:33:31.941694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9565 09:33:31.944905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9566 09:33:31.951810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9567 09:33:31.955254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9568 09:33:31.958756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9569 09:33:31.961646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9570 09:33:31.968213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9571 09:33:31.971765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9572 09:33:31.974944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9573 09:33:31.978709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9574 09:33:31.984993 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9575 09:33:31.988114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9576 09:33:31.995021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9577 09:33:31.998572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9578 09:33:32.001776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9579 09:33:32.007804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9580 09:33:32.011418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9581 09:33:32.017827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9582 09:33:32.021109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9583 09:33:32.027788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9584 09:33:32.031212 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9585 09:33:32.038017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9586 09:33:32.041302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9587 09:33:32.044250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9588 09:33:32.050854 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9589 09:33:32.054370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9590 09:33:32.061478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9591 09:33:32.064109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9592 09:33:32.070566 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9593 09:33:32.074211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9594 09:33:32.080666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9595 09:33:32.083928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9596 09:33:32.087056 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9597 09:33:32.094070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9598 09:33:32.097244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9599 09:33:32.104189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9600 09:33:32.107291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9601 09:33:32.114122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9602 09:33:32.117215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9603 09:33:32.120234 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9604 09:33:32.127240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9605 09:33:32.130590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9606 09:33:32.137219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9607 09:33:32.140518 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9608 09:33:32.146866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9609 09:33:32.150591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9610 09:33:32.156994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9611 09:33:32.160597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9612 09:33:32.163438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9613 09:33:32.170386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9614 09:33:32.173350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9615 09:33:32.179964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9616 09:33:32.183228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9617 09:33:32.189937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9618 09:33:32.193208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9619 09:33:32.200178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9620 09:33:32.203565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9621 09:33:32.210459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9622 09:33:32.212806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9623 09:33:32.216248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9624 09:33:32.223458 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9625 09:33:32.226260 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9626 09:33:32.229743 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9627 09:33:32.232801 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9628 09:33:32.240027 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9629 09:33:32.242873 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9630 09:33:32.249355 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9631 09:33:32.253047 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9632 09:33:32.255826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9633 09:33:32.262884 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9634 09:33:32.266253 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9635 09:33:32.272613 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9636 09:33:32.275886 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9637 09:33:32.279140 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9638 09:33:32.285559 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9639 09:33:32.289457 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9640 09:33:32.296460 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9641 09:33:32.299539 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9642 09:33:32.302508 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9643 09:33:32.305669 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9644 09:33:32.312660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9645 09:33:32.316251 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9646 09:33:32.322496 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9647 09:33:32.325770 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9648 09:33:32.328989 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9649 09:33:32.331981 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9650 09:33:32.339430 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9651 09:33:32.342616 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9652 09:33:32.345926 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9653 09:33:32.352466 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9654 09:33:32.355401 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9655 09:33:32.361836 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9656 09:33:32.365420 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9657 09:33:32.368633 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9658 09:33:32.374857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9659 09:33:32.378408 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9660 09:33:32.381664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9661 09:33:32.388424 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9662 09:33:32.391844 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9663 09:33:32.398644 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9664 09:33:32.401889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9665 09:33:32.404924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9666 09:33:32.411585 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9667 09:33:32.414775 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9668 09:33:32.421408 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9669 09:33:32.424568 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9670 09:33:32.428405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9671 09:33:32.435085 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9672 09:33:32.438513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9673 09:33:32.444639 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9674 09:33:32.448317 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9675 09:33:32.451428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9676 09:33:32.458167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9677 09:33:32.461376 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9678 09:33:32.467885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9679 09:33:32.471385 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9680 09:33:32.474370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9681 09:33:32.481497 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9682 09:33:32.485217 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9683 09:33:32.491241 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9684 09:33:32.494659 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9685 09:33:32.497781 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9686 09:33:32.504640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9687 09:33:32.507475 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9688 09:33:32.514420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9689 09:33:32.517394 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9690 09:33:32.520942 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9691 09:33:32.527794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9692 09:33:32.531086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9693 09:33:32.537302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9694 09:33:32.541222 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9695 09:33:32.543977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9696 09:33:32.551078 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9697 09:33:32.554181 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9698 09:33:32.560052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9699 09:33:32.563474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9700 09:33:32.566766 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9701 09:33:32.573138 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9702 09:33:32.576914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9703 09:33:32.582929 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9704 09:33:32.586293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9705 09:33:32.589634 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9706 09:33:32.596440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9707 09:33:32.600193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9708 09:33:32.606687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9709 09:33:32.609812 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9710 09:33:32.612570 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9711 09:33:32.619829 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9712 09:33:32.622702 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9713 09:33:32.629682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9714 09:33:32.633172 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9715 09:33:32.636200 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9716 09:33:32.642402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9717 09:33:32.645475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9718 09:33:32.652330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9719 09:33:32.655874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9720 09:33:32.662148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9721 09:33:32.665475 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9722 09:33:32.669059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9723 09:33:32.675320 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9724 09:33:32.679536 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9725 09:33:32.685287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9726 09:33:32.688398 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9727 09:33:32.695489 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9728 09:33:32.698389 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9729 09:33:32.701835 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9730 09:33:32.708555 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9731 09:33:32.711830 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9732 09:33:32.718346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9733 09:33:32.721356 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9734 09:33:32.728654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9735 09:33:32.731911 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9736 09:33:32.734691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9737 09:33:32.742202 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9738 09:33:32.744785 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9739 09:33:32.751342 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9740 09:33:32.755092 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9741 09:33:32.758263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9742 09:33:32.764715 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9743 09:33:32.768477 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9744 09:33:32.774521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9745 09:33:32.777910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9746 09:33:32.784108 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9747 09:33:32.787814 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9748 09:33:32.791164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9749 09:33:32.797833 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9750 09:33:32.800675 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9751 09:33:32.807320 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9752 09:33:32.810762 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9753 09:33:32.817145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9754 09:33:32.820364 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9755 09:33:32.823902 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9756 09:33:32.830665 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9757 09:33:32.833675 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9758 09:33:32.837112 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9759 09:33:32.840602 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9760 09:33:32.846973 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9761 09:33:32.849989 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9762 09:33:32.853594 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9763 09:33:32.860124 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9764 09:33:32.863384 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9765 09:33:32.870227 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9766 09:33:32.873259 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9767 09:33:32.876405 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9768 09:33:32.883139 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9769 09:33:32.886531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9770 09:33:32.889401 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9771 09:33:32.896591 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9772 09:33:32.900177 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9773 09:33:32.906438 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9774 09:33:32.909688 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9775 09:33:32.913141 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9776 09:33:32.919395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9777 09:33:32.922746 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9778 09:33:32.926082 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9779 09:33:32.932657 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9780 09:33:32.935911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9781 09:33:32.942308 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9782 09:33:32.945741 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9783 09:33:32.949230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9784 09:33:32.955582 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9785 09:33:32.958779 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9786 09:33:32.962406 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9787 09:33:32.968741 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9788 09:33:32.972249 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9789 09:33:32.978703 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9790 09:33:32.982214 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9791 09:33:32.985322 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9792 09:33:32.992532 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9793 09:33:32.995341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9794 09:33:33.001811 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9795 09:33:33.006077 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9796 09:33:33.008325 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9797 09:33:33.011467 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9798 09:33:33.015208 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9799 09:33:33.021821 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9800 09:33:33.024975 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9801 09:33:33.028370 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9802 09:33:33.031604 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9803 09:33:33.038447 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9804 09:33:33.041525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9805 09:33:33.044667 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9806 09:33:33.047795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9807 09:33:33.054593 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9808 09:33:33.058286 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9809 09:33:33.061428 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9810 09:33:33.067804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9811 09:33:33.071517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9812 09:33:33.077696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9813 09:33:33.080771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9814 09:33:33.087620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9815 09:33:33.091136 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9816 09:33:33.094446 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9817 09:33:33.101331 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9818 09:33:33.104075 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9819 09:33:33.111028 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9820 09:33:33.114589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9821 09:33:33.120623 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9822 09:33:33.123977 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9823 09:33:33.127324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9824 09:33:33.133902 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9825 09:33:33.137227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9826 09:33:33.144353 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9827 09:33:33.147061 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9828 09:33:33.150559 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9829 09:33:33.157357 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9830 09:33:33.160290 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9831 09:33:33.166706 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9832 09:33:33.170037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9833 09:33:33.173567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9834 09:33:33.180261 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9835 09:33:33.183225 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9836 09:33:33.189811 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9837 09:33:33.193095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9838 09:33:33.199544 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9839 09:33:33.203240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9840 09:33:33.206542 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9841 09:33:33.213024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9842 09:33:33.216722 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9843 09:33:33.222783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9844 09:33:33.226558 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9845 09:33:33.232550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9846 09:33:33.236601 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9847 09:33:33.239755 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9848 09:33:33.245942 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9849 09:33:33.249331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9850 09:33:33.256112 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9851 09:33:33.259497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9852 09:33:33.262758 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9853 09:33:33.269173 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9854 09:33:33.272269 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9855 09:33:33.278822 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9856 09:33:33.282261 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9857 09:33:33.285573 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9858 09:33:33.292686 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9859 09:33:33.295817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9860 09:33:33.301955 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9861 09:33:33.305598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9862 09:33:33.311711 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9863 09:33:33.315914 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9864 09:33:33.318279 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9865 09:33:33.324948 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9866 09:33:33.328839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9867 09:33:33.335515 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9868 09:33:33.338561 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9869 09:33:33.344877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9870 09:33:33.348735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9871 09:33:33.351597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9872 09:33:33.358435 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9873 09:33:33.361912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9874 09:33:33.368123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9875 09:33:33.371692 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9876 09:33:33.378096 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9877 09:33:33.381403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9878 09:33:33.384815 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9879 09:33:33.391063 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9880 09:33:33.394478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9881 09:33:33.400845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9882 09:33:33.404468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9883 09:33:33.407810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9884 09:33:33.414280 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9885 09:33:33.417652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9886 09:33:33.424314 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9887 09:33:33.427322 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9888 09:33:33.433771 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9889 09:33:33.436984 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9890 09:33:33.444405 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9891 09:33:33.447115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9892 09:33:33.450684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9893 09:33:33.457193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9894 09:33:33.460875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9895 09:33:33.467618 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9896 09:33:33.470388 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9897 09:33:33.477190 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9898 09:33:33.480343 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9899 09:33:33.483605 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9900 09:33:33.490441 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9901 09:33:33.493498 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9902 09:33:33.500317 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9903 09:33:33.503416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9904 09:33:33.510058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9905 09:33:33.513040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9906 09:33:33.520185 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9907 09:33:33.523697 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9908 09:33:33.529794 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9909 09:33:33.532889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9910 09:33:33.536277 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9911 09:33:33.543430 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9912 09:33:33.546283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9913 09:33:33.552850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9914 09:33:33.556636 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9915 09:33:33.563004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9916 09:33:33.566235 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9917 09:33:33.572744 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9918 09:33:33.576434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9919 09:33:33.579539 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9920 09:33:33.586000 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9921 09:33:33.588967 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9922 09:33:33.595891 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9923 09:33:33.599174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9924 09:33:33.605560 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9925 09:33:33.609005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9926 09:33:33.615538 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9927 09:33:33.619073 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9928 09:33:33.622042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9929 09:33:33.628444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9930 09:33:33.632441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9931 09:33:33.638313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9932 09:33:33.641797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9933 09:33:33.648452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9934 09:33:33.651571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9935 09:33:33.658187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9936 09:33:33.661338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9937 09:33:33.668281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9938 09:33:33.671711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9939 09:33:33.677810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9940 09:33:33.680937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9941 09:33:33.684283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9942 09:33:33.690947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9943 09:33:33.694186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9944 09:33:33.700744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9945 09:33:33.704349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9946 09:33:33.711103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9947 09:33:33.714191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9948 09:33:33.720788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9949 09:33:33.723709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9950 09:33:33.731495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9951 09:33:33.734660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9952 09:33:33.740943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9953 09:33:33.744737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9954 09:33:33.751030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9955 09:33:33.757476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9956 09:33:33.760488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9957 09:33:33.767581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9958 09:33:33.770792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9959 09:33:33.777439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9960 09:33:33.780424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9961 09:33:33.784033 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9962 09:33:33.788045 INFO: [APUAPC] vio 0
9963 09:33:33.790402 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9964 09:33:33.797327 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9965 09:33:33.801140 INFO: [APUAPC] D0_APC_0: 0x400510
9966 09:33:33.804028 INFO: [APUAPC] D0_APC_1: 0x0
9967 09:33:33.807768 INFO: [APUAPC] D0_APC_2: 0x1540
9968 09:33:33.808332 INFO: [APUAPC] D0_APC_3: 0x0
9969 09:33:33.810409 INFO: [APUAPC] D1_APC_0: 0xffffffff
9970 09:33:33.817448 INFO: [APUAPC] D1_APC_1: 0xffffffff
9971 09:33:33.820435 INFO: [APUAPC] D1_APC_2: 0x3fffff
9972 09:33:33.820996 INFO: [APUAPC] D1_APC_3: 0x0
9973 09:33:33.823791 INFO: [APUAPC] D2_APC_0: 0xffffffff
9974 09:33:33.826916 INFO: [APUAPC] D2_APC_1: 0xffffffff
9975 09:33:33.830436 INFO: [APUAPC] D2_APC_2: 0x3fffff
9976 09:33:33.833507 INFO: [APUAPC] D2_APC_3: 0x0
9977 09:33:33.836894 INFO: [APUAPC] D3_APC_0: 0xffffffff
9978 09:33:33.839991 INFO: [APUAPC] D3_APC_1: 0xffffffff
9979 09:33:33.843364 INFO: [APUAPC] D3_APC_2: 0x3fffff
9980 09:33:33.846825 INFO: [APUAPC] D3_APC_3: 0x0
9981 09:33:33.850098 INFO: [APUAPC] D4_APC_0: 0xffffffff
9982 09:33:33.853639 INFO: [APUAPC] D4_APC_1: 0xffffffff
9983 09:33:33.856418 INFO: [APUAPC] D4_APC_2: 0x3fffff
9984 09:33:33.860451 INFO: [APUAPC] D4_APC_3: 0x0
9985 09:33:33.863832 INFO: [APUAPC] D5_APC_0: 0xffffffff
9986 09:33:33.866810 INFO: [APUAPC] D5_APC_1: 0xffffffff
9987 09:33:33.869602 INFO: [APUAPC] D5_APC_2: 0x3fffff
9988 09:33:33.873170 INFO: [APUAPC] D5_APC_3: 0x0
9989 09:33:33.876620 INFO: [APUAPC] D6_APC_0: 0xffffffff
9990 09:33:33.879905 INFO: [APUAPC] D6_APC_1: 0xffffffff
9991 09:33:33.882982 INFO: [APUAPC] D6_APC_2: 0x3fffff
9992 09:33:33.886598 INFO: [APUAPC] D6_APC_3: 0x0
9993 09:33:33.890155 INFO: [APUAPC] D7_APC_0: 0xffffffff
9994 09:33:33.892922 INFO: [APUAPC] D7_APC_1: 0xffffffff
9995 09:33:33.896263 INFO: [APUAPC] D7_APC_2: 0x3fffff
9996 09:33:33.899863 INFO: [APUAPC] D7_APC_3: 0x0
9997 09:33:33.903331 INFO: [APUAPC] D8_APC_0: 0xffffffff
9998 09:33:33.906199 INFO: [APUAPC] D8_APC_1: 0xffffffff
9999 09:33:33.909569 INFO: [APUAPC] D8_APC_2: 0x3fffff
10000 09:33:33.913018 INFO: [APUAPC] D8_APC_3: 0x0
10001 09:33:33.916594 INFO: [APUAPC] D9_APC_0: 0xffffffff
10002 09:33:33.919598 INFO: [APUAPC] D9_APC_1: 0xffffffff
10003 09:33:33.922986 INFO: [APUAPC] D9_APC_2: 0x3fffff
10004 09:33:33.926179 INFO: [APUAPC] D9_APC_3: 0x0
10005 09:33:33.929768 INFO: [APUAPC] D10_APC_0: 0xffffffff
10006 09:33:33.932624 INFO: [APUAPC] D10_APC_1: 0xffffffff
10007 09:33:33.935818 INFO: [APUAPC] D10_APC_2: 0x3fffff
10008 09:33:33.939233 INFO: [APUAPC] D10_APC_3: 0x0
10009 09:33:33.942646 INFO: [APUAPC] D11_APC_0: 0xffffffff
10010 09:33:33.945560 INFO: [APUAPC] D11_APC_1: 0xffffffff
10011 09:33:33.949053 INFO: [APUAPC] D11_APC_2: 0x3fffff
10012 09:33:33.952370 INFO: [APUAPC] D11_APC_3: 0x0
10013 09:33:33.955470 INFO: [APUAPC] D12_APC_0: 0xffffffff
10014 09:33:33.959271 INFO: [APUAPC] D12_APC_1: 0xffffffff
10015 09:33:33.962390 INFO: [APUAPC] D12_APC_2: 0x3fffff
10016 09:33:33.965701 INFO: [APUAPC] D12_APC_3: 0x0
10017 09:33:33.968725 INFO: [APUAPC] D13_APC_0: 0xffffffff
10018 09:33:33.972174 INFO: [APUAPC] D13_APC_1: 0xffffffff
10019 09:33:33.975842 INFO: [APUAPC] D13_APC_2: 0x3fffff
10020 09:33:33.979135 INFO: [APUAPC] D13_APC_3: 0x0
10021 09:33:33.982227 INFO: [APUAPC] D14_APC_0: 0xffffffff
10022 09:33:33.985333 INFO: [APUAPC] D14_APC_1: 0xffffffff
10023 09:33:33.988522 INFO: [APUAPC] D14_APC_2: 0x3fffff
10024 09:33:33.992102 INFO: [APUAPC] D14_APC_3: 0x0
10025 09:33:33.995297 INFO: [APUAPC] D15_APC_0: 0xffffffff
10026 09:33:33.999083 INFO: [APUAPC] D15_APC_1: 0xffffffff
10027 09:33:34.002181 INFO: [APUAPC] D15_APC_2: 0x3fffff
10028 09:33:34.005397 INFO: [APUAPC] D15_APC_3: 0x0
10029 09:33:34.008801 INFO: [APUAPC] APC_CON: 0x4
10030 09:33:34.011808 INFO: [NOCDAPC] D0_APC_0: 0x0
10031 09:33:34.014998 INFO: [NOCDAPC] D0_APC_1: 0x0
10032 09:33:34.019107 INFO: [NOCDAPC] D1_APC_0: 0x0
10033 09:33:34.022156 INFO: [NOCDAPC] D1_APC_1: 0xfff
10034 09:33:34.025137 INFO: [NOCDAPC] D2_APC_0: 0x0
10035 09:33:34.025691 INFO: [NOCDAPC] D2_APC_1: 0xfff
10036 09:33:34.028445 INFO: [NOCDAPC] D3_APC_0: 0x0
10037 09:33:34.031864 INFO: [NOCDAPC] D3_APC_1: 0xfff
10038 09:33:34.034831 INFO: [NOCDAPC] D4_APC_0: 0x0
10039 09:33:34.038158 INFO: [NOCDAPC] D4_APC_1: 0xfff
10040 09:33:34.041258 INFO: [NOCDAPC] D5_APC_0: 0x0
10041 09:33:34.044518 INFO: [NOCDAPC] D5_APC_1: 0xfff
10042 09:33:34.047990 INFO: [NOCDAPC] D6_APC_0: 0x0
10043 09:33:34.051971 INFO: [NOCDAPC] D6_APC_1: 0xfff
10044 09:33:34.054830 INFO: [NOCDAPC] D7_APC_0: 0x0
10045 09:33:34.058056 INFO: [NOCDAPC] D7_APC_1: 0xfff
10046 09:33:34.058617 INFO: [NOCDAPC] D8_APC_0: 0x0
10047 09:33:34.061508 INFO: [NOCDAPC] D8_APC_1: 0xfff
10048 09:33:34.064972 INFO: [NOCDAPC] D9_APC_0: 0x0
10049 09:33:34.068375 INFO: [NOCDAPC] D9_APC_1: 0xfff
10050 09:33:34.071325 INFO: [NOCDAPC] D10_APC_0: 0x0
10051 09:33:34.075033 INFO: [NOCDAPC] D10_APC_1: 0xfff
10052 09:33:34.078139 INFO: [NOCDAPC] D11_APC_0: 0x0
10053 09:33:34.081307 INFO: [NOCDAPC] D11_APC_1: 0xfff
10054 09:33:34.084993 INFO: [NOCDAPC] D12_APC_0: 0x0
10055 09:33:34.087921 INFO: [NOCDAPC] D12_APC_1: 0xfff
10056 09:33:34.091184 INFO: [NOCDAPC] D13_APC_0: 0x0
10057 09:33:34.094771 INFO: [NOCDAPC] D13_APC_1: 0xfff
10058 09:33:34.097866 INFO: [NOCDAPC] D14_APC_0: 0x0
10059 09:33:34.101344 INFO: [NOCDAPC] D14_APC_1: 0xfff
10060 09:33:34.104409 INFO: [NOCDAPC] D15_APC_0: 0x0
10061 09:33:34.107500 INFO: [NOCDAPC] D15_APC_1: 0xfff
10062 09:33:34.108022 INFO: [NOCDAPC] APC_CON: 0x4
10063 09:33:34.111207 INFO: [APUAPC] set_apusys_apc done
10064 09:33:34.114234 INFO: [DEVAPC] devapc_init done
10065 09:33:34.121302 INFO: GICv3 without legacy support detected.
10066 09:33:34.124432 INFO: ARM GICv3 driver initialized in EL3
10067 09:33:34.127681 INFO: Maximum SPI INTID supported: 639
10068 09:33:34.130953 INFO: BL31: Initializing runtime services
10069 09:33:34.137711 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10070 09:33:34.140862 INFO: SPM: enable CPC mode
10071 09:33:34.143647 INFO: mcdi ready for mcusys-off-idle and system suspend
10072 09:33:34.150403 INFO: BL31: Preparing for EL3 exit to normal world
10073 09:33:34.153856 INFO: Entry point address = 0x80000000
10074 09:33:34.154427 INFO: SPSR = 0x8
10075 09:33:34.160713
10076 09:33:34.161177
10077 09:33:34.161549
10078 09:33:34.164079 Starting depthcharge on Spherion...
10079 09:33:34.164544
10080 09:33:34.164911 Wipe memory regions:
10081 09:33:34.165260
10082 09:33:34.168086 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10083 09:33:34.168640 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10084 09:33:34.169090 Setting prompt string to ['asurada:']
10085 09:33:34.169533 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10086 09:33:34.170255 [0x00000040000000, 0x00000054600000)
10087 09:33:34.289784
10088 09:33:34.290420 [0x00000054660000, 0x00000080000000)
10089 09:33:34.550681
10090 09:33:34.551233 [0x000000821a7280, 0x000000ffe64000)
10091 09:33:35.295368
10092 09:33:35.295909 [0x00000100000000, 0x00000240000000)
10093 09:33:37.186197
10094 09:33:37.189112 Initializing XHCI USB controller at 0x11200000.
10095 09:33:38.170774
10096 09:33:38.171327 R8152: Initializing
10097 09:33:38.171698
10098 09:33:38.173643 Version 9 (ocp_data = 6010)
10099 09:33:38.174107
10100 09:33:38.177201 R8152: Done initializing
10101 09:33:38.177758
10102 09:33:38.178147 Adding net device
10103 09:33:38.700182
10104 09:33:38.702599 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10105 09:33:38.703158
10106 09:33:38.703527
10107 09:33:38.703931
10108 09:33:38.704733 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10110 09:33:38.806114 asurada: tftpboot 192.168.201.1 11826833/tftp-deploy-49sr7nl6/kernel/image.itb 11826833/tftp-deploy-49sr7nl6/kernel/cmdline
10111 09:33:38.806772 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 09:33:38.807269 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10113 09:33:38.811794 tftpboot 192.168.201.1 11826833/tftp-deploy-49sr7nl6/kernel/image.ittp-deploy-49sr7nl6/kernel/cmdline
10114 09:33:38.812264
10115 09:33:38.812643 Waiting for link
10116 09:33:39.014779
10117 09:33:39.015360 done.
10118 09:33:39.015794
10119 09:33:39.016151 MAC: f4:f5:e8:50:de:0a
10120 09:33:39.016480
10121 09:33:39.018048 Sending DHCP discover... done.
10122 09:33:39.018507
10123 09:33:39.020769 Waiting for reply... done.
10124 09:33:39.021231
10125 09:33:39.024095 Sending DHCP request... done.
10126 09:33:39.024571
10127 09:33:39.029515 Waiting for reply... done.
10128 09:33:39.030071
10129 09:33:39.030436 My ip is 192.168.201.14
10130 09:33:39.030771
10131 09:33:39.032404 The DHCP server ip is 192.168.201.1
10132 09:33:39.032869
10133 09:33:39.038803 TFTP server IP predefined by user: 192.168.201.1
10134 09:33:39.039363
10135 09:33:39.045414 Bootfile predefined by user: 11826833/tftp-deploy-49sr7nl6/kernel/image.itb
10136 09:33:39.045960
10137 09:33:39.048883 Sending tftp read request... done.
10138 09:33:39.049347
10139 09:33:39.055865 Waiting for the transfer...
10140 09:33:39.056421
10141 09:33:39.431805 00000000 ################################################################
10142 09:33:39.432314
10143 09:33:39.790174 00080000 ################################################################
10144 09:33:39.790843
10145 09:33:40.146029 00100000 ################################################################
10146 09:33:40.146689
10147 09:33:40.474919 00180000 ################################################################
10148 09:33:40.475090
10149 09:33:40.759438 00200000 ################################################################
10150 09:33:40.759611
10151 09:33:41.010206 00280000 ################################################################
10152 09:33:41.010350
10153 09:33:41.300449 00300000 ################################################################
10154 09:33:41.300597
10155 09:33:41.553592 00380000 ################################################################
10156 09:33:41.553743
10157 09:33:41.802859 00400000 ################################################################
10158 09:33:41.803005
10159 09:33:42.061099 00480000 ################################################################
10160 09:33:42.061251
10161 09:33:42.334853 00500000 ################################################################
10162 09:33:42.334999
10163 09:33:42.607046 00580000 ################################################################
10164 09:33:42.607196
10165 09:33:42.875912 00600000 ################################################################
10166 09:33:42.876087
10167 09:33:43.104536 00680000 ################################################################
10168 09:33:43.104687
10169 09:33:43.331859 00700000 ################################################################
10170 09:33:43.331999
10171 09:33:43.569176 00780000 ################################################################
10172 09:33:43.569318
10173 09:33:43.801834 00800000 ################################################################
10174 09:33:43.801976
10175 09:33:44.045588 00880000 ################################################################
10176 09:33:44.045734
10177 09:33:44.274780 00900000 ################################################################
10178 09:33:44.274927
10179 09:33:44.502378 00980000 ################################################################
10180 09:33:44.502520
10181 09:33:44.730649 00a00000 ################################################################
10182 09:33:44.730789
10183 09:33:44.958321 00a80000 ################################################################
10184 09:33:44.958459
10185 09:33:45.196460 00b00000 ################################################################
10186 09:33:45.196609
10187 09:33:45.427327 00b80000 ################################################################
10188 09:33:45.427468
10189 09:33:45.666259 00c00000 ################################################################
10190 09:33:45.666399
10191 09:33:45.895212 00c80000 ################################################################
10192 09:33:45.895350
10193 09:33:46.148144 00d00000 ################################################################
10194 09:33:46.148287
10195 09:33:46.384441 00d80000 ################################################################
10196 09:33:46.384580
10197 09:33:46.613438 00e00000 ################################################################
10198 09:33:46.613581
10199 09:33:46.874108 00e80000 ################################################################
10200 09:33:46.874247
10201 09:33:47.137696 00f00000 ################################################################
10202 09:33:47.137841
10203 09:33:47.408423 00f80000 ################################################################
10204 09:33:47.408567
10205 09:33:47.662823 01000000 ################################################################
10206 09:33:47.662968
10207 09:33:47.936317 01080000 ################################################################
10208 09:33:47.936463
10209 09:33:48.190923 01100000 ################################################################
10210 09:33:48.191065
10211 09:33:48.457218 01180000 ################################################################
10212 09:33:48.457398
10213 09:33:48.707559 01200000 ################################################################
10214 09:33:48.707755
10215 09:33:48.954669 01280000 ################################################################
10216 09:33:48.954812
10217 09:33:49.220288 01300000 ################################################################
10218 09:33:49.220433
10219 09:33:49.478008 01380000 ################################################################
10220 09:33:49.478149
10221 09:33:49.747359 01400000 ################################################################
10222 09:33:49.747507
10223 09:33:50.017952 01480000 ################################################################
10224 09:33:50.018098
10225 09:33:50.255476 01500000 ################################################################
10226 09:33:50.255615
10227 09:33:50.519416 01580000 ################################################################
10228 09:33:50.519581
10229 09:33:50.774461 01600000 ################################################################
10230 09:33:50.774605
10231 09:33:51.024653 01680000 ################################################################
10232 09:33:51.024793
10233 09:33:51.277496 01700000 ################################################################
10234 09:33:51.277635
10235 09:33:51.525636 01780000 ################################################################
10236 09:33:51.525778
10237 09:33:51.758616 01800000 ################################################################
10238 09:33:51.758760
10239 09:33:51.997047 01880000 ################################################################
10240 09:33:51.997191
10241 09:33:52.247884 01900000 ################################################################
10242 09:33:52.248055
10243 09:33:52.482136 01980000 ################################################################
10244 09:33:52.482275
10245 09:33:52.728952 01a00000 ################################################################
10246 09:33:52.729098
10247 09:33:52.980374 01a80000 ################################################################
10248 09:33:52.980518
10249 09:33:53.217853 01b00000 ################################################################
10250 09:33:53.217994
10251 09:33:53.478458 01b80000 ################################################################
10252 09:33:53.478599
10253 09:33:53.742047 01c00000 ################################################################
10254 09:33:53.742214
10255 09:33:53.979339 01c80000 ################################################################
10256 09:33:53.979510
10257 09:33:54.225822 01d00000 ################################################################
10258 09:33:54.225965
10259 09:33:54.472254 01d80000 ################################################################
10260 09:33:54.472399
10261 09:33:54.726136 01e00000 ################################################################
10262 09:33:54.726279
10263 09:33:54.980707 01e80000 ################################################################
10264 09:33:54.980855
10265 09:33:55.215957 01f00000 ################################################################
10266 09:33:55.216099
10267 09:33:55.458444 01f80000 ################################################################
10268 09:33:55.458587
10269 09:33:55.691908 02000000 ################################################################
10270 09:33:55.692046
10271 09:33:55.920147 02080000 ################################################################
10272 09:33:55.920288
10273 09:33:56.149257 02100000 ################################################################
10274 09:33:56.149400
10275 09:33:56.377240 02180000 ################################################################
10276 09:33:56.377383
10277 09:33:56.609188 02200000 ################################################################
10278 09:33:56.609330
10279 09:33:56.873431 02280000 ################################################################
10280 09:33:56.873574
10281 09:33:57.127363 02300000 ################################################################
10282 09:33:57.127508
10283 09:33:57.368374 02380000 ################################################################
10284 09:33:57.368518
10285 09:33:57.641122 02400000 ################################################################
10286 09:33:57.641266
10287 09:33:57.880832 02480000 ################################################################
10288 09:33:57.880978
10289 09:33:58.129939 02500000 ################################################################
10290 09:33:58.130080
10291 09:33:58.390617 02580000 ################################################################
10292 09:33:58.390759
10293 09:33:58.647442 02600000 ################################################################
10294 09:33:58.647586
10295 09:33:58.896015 02680000 ################################################################
10296 09:33:58.896154
10297 09:33:59.122806 02700000 ################################################################
10298 09:33:59.122944
10299 09:33:59.359737 02780000 ################################################################
10300 09:33:59.359877
10301 09:33:59.593850 02800000 ################################################################
10302 09:33:59.593993
10303 09:33:59.859963 02880000 ################################################################
10304 09:33:59.860113
10305 09:34:00.102086 02900000 ################################################################
10306 09:34:00.102225
10307 09:34:00.328586 02980000 ################################################################
10308 09:34:00.328729
10309 09:34:00.568021 02a00000 ################################################################
10310 09:34:00.568163
10311 09:34:00.820637 02a80000 ################################################################
10312 09:34:00.820778
10313 09:34:01.048466 02b00000 ################################################################
10314 09:34:01.048604
10315 09:34:01.309632 02b80000 ################################################################
10316 09:34:01.309773
10317 09:34:01.557596 02c00000 ################################################################
10318 09:34:01.557740
10319 09:34:01.803632 02c80000 ################################################################
10320 09:34:01.803837
10321 09:34:02.049293 02d00000 ################################################################
10322 09:34:02.049446
10323 09:34:02.276887 02d80000 ################################################################
10324 09:34:02.277029
10325 09:34:02.511467 02e00000 ################################################################
10326 09:34:02.511610
10327 09:34:02.793523 02e80000 ################################################################
10328 09:34:02.793678
10329 09:34:03.034968 02f00000 ################################################################
10330 09:34:03.035114
10331 09:34:03.278899 02f80000 ################################################################
10332 09:34:03.279043
10333 09:34:03.525505 03000000 ################################################################
10334 09:34:03.525650
10335 09:34:03.799338 03080000 ################################################################
10336 09:34:03.799516
10337 09:34:04.067002 03100000 ################################################################
10338 09:34:04.067152
10339 09:34:04.303063 03180000 ################################################################
10340 09:34:04.303244
10341 09:34:04.535371 03200000 ################################################################
10342 09:34:04.535512
10343 09:34:04.767410 03280000 ################################################################
10344 09:34:04.767582
10345 09:34:05.009864 03300000 ################################################################
10346 09:34:05.010011
10347 09:34:05.279815 03380000 ################################################################
10348 09:34:05.279964
10349 09:34:05.532837 03400000 ################################################################
10350 09:34:05.532980
10351 09:34:05.771053 03480000 ################################################################
10352 09:34:05.771196
10353 09:34:06.027964 03500000 ################################################################
10354 09:34:06.028116
10355 09:34:06.299069 03580000 ################################################################
10356 09:34:06.299212
10357 09:34:06.567566 03600000 ################################################################
10358 09:34:06.567711
10359 09:34:06.806168 03680000 ################################################################
10360 09:34:06.806310
10361 09:34:07.038531 03700000 ################################################################
10362 09:34:07.038680
10363 09:34:07.274288 03780000 ################################################################
10364 09:34:07.274428
10365 09:34:07.503648 03800000 ################################################################
10366 09:34:07.503826
10367 09:34:07.730706 03880000 ################################################################
10368 09:34:07.730850
10369 09:34:08.029083 03900000 ################################################################
10370 09:34:08.029220
10371 09:34:08.264854 03980000 ################################################################
10372 09:34:08.265000
10373 09:34:08.503923 03a00000 ################################################################
10374 09:34:08.504063
10375 09:34:08.744423 03a80000 ################################################################
10376 09:34:08.744561
10377 09:34:08.996969 03b00000 ################################################################
10378 09:34:08.997108
10379 09:34:09.245125 03b80000 ################################################################
10380 09:34:09.245270
10381 09:34:09.500073 03c00000 ################################################################
10382 09:34:09.500217
10383 09:34:09.752798 03c80000 ################################################################
10384 09:34:09.752941
10385 09:34:10.007673 03d00000 ################################################################
10386 09:34:10.007821
10387 09:34:10.278921 03d80000 ################################################################
10388 09:34:10.279080
10389 09:34:10.533269 03e00000 ################################################################
10390 09:34:10.533407
10391 09:34:10.790949 03e80000 ################################################################
10392 09:34:10.791088
10393 09:34:11.049125 03f00000 ################################################################
10394 09:34:11.049271
10395 09:34:11.312341 03f80000 ################################################################
10396 09:34:11.312483
10397 09:34:11.499463 04000000 ################################################### done.
10398 09:34:11.499605
10399 09:34:11.503150 The bootfile was 67518970 bytes long.
10400 09:34:11.503246
10401 09:34:11.505920 Sending tftp read request... done.
10402 09:34:11.506093
10403 09:34:11.506181 Waiting for the transfer...
10404 09:34:11.509391
10405 09:34:11.509564 00000000 # done.
10406 09:34:11.509666
10407 09:34:11.516156 Command line loaded dynamically from TFTP file: 11826833/tftp-deploy-49sr7nl6/kernel/cmdline
10408 09:34:11.516359
10409 09:34:11.529386 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10410 09:34:11.532490
10411 09:34:11.532657 Loading FIT.
10412 09:34:11.532778
10413 09:34:11.535780 Image ramdisk-1 has 56425397 bytes.
10414 09:34:11.535954
10415 09:34:11.539243 Image fdt-1 has 47278 bytes.
10416 09:34:11.539414
10417 09:34:11.542561 Image kernel-1 has 11044258 bytes.
10418 09:34:11.542761
10419 09:34:11.549204 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10420 09:34:11.549535
10421 09:34:11.569703 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10422 09:34:11.570277
10423 09:34:11.572338 Choosing best match conf-1 for compat google,spherion-rev2.
10424 09:34:11.577413
10425 09:34:11.581143 Connected to device vid:did:rid of 1ae0:0028:00
10426 09:34:11.589120
10427 09:34:11.592298 tpm_get_response: command 0x17b, return code 0x0
10428 09:34:11.592765
10429 09:34:11.595133 ec_init: CrosEC protocol v3 supported (256, 248)
10430 09:34:11.599088
10431 09:34:11.602491 tpm_cleanup: add release locality here.
10432 09:34:11.602906
10433 09:34:11.603259 Shutting down all USB controllers.
10434 09:34:11.605448
10435 09:34:11.605864 Removing current net device
10436 09:34:11.606197
10437 09:34:11.612480 Exiting depthcharge with code 4 at timestamp: 66902137
10438 09:34:11.612903
10439 09:34:11.615904 LZMA decompressing kernel-1 to 0x821a6718
10440 09:34:11.616425
10441 09:34:11.619305 LZMA decompressing kernel-1 to 0x40000000
10442 09:34:13.009485
10443 09:34:13.010077 jumping to kernel
10444 09:34:13.012633 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10445 09:34:13.013193 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10446 09:34:13.013613 Setting prompt string to ['Linux version [0-9]']
10447 09:34:13.013998 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10448 09:34:13.014392 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10449 09:34:13.091487
10450 09:34:13.094350 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10451 09:34:13.097954 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10452 09:34:13.098407 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10453 09:34:13.098763 Setting prompt string to []
10454 09:34:13.099165 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10455 09:34:13.099528 Using line separator: #'\n'#
10456 09:34:13.099873 No login prompt set.
10457 09:34:13.100189 Parsing kernel messages
10458 09:34:13.100536 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10459 09:34:13.101027 [login-action] Waiting for messages, (timeout 00:03:46)
10460 09:34:13.117313 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10461 09:34:13.120635 [ 0.000000] random: crng init done
10462 09:34:13.127215 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10463 09:34:13.130601 [ 0.000000] efi: UEFI not found.
10464 09:34:13.137291 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10465 09:34:13.143911 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10466 09:34:13.153891 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10467 09:34:13.163908 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10468 09:34:13.170370 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10469 09:34:13.177053 [ 0.000000] printk: bootconsole [mtk8250] enabled
10470 09:34:13.183901 [ 0.000000] NUMA: No NUMA configuration found
10471 09:34:13.190093 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10472 09:34:13.193594 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10473 09:34:13.196955 [ 0.000000] Zone ranges:
10474 09:34:13.203829 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10475 09:34:13.207261 [ 0.000000] DMA32 empty
10476 09:34:13.213640 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10477 09:34:13.216796 [ 0.000000] Movable zone start for each node
10478 09:34:13.219761 [ 0.000000] Early memory node ranges
10479 09:34:13.226529 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10480 09:34:13.233041 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10481 09:34:13.239544 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10482 09:34:13.246198 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10483 09:34:13.252546 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10484 09:34:13.259666 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10485 09:34:13.315921 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10486 09:34:13.321974 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10487 09:34:13.328375 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10488 09:34:13.332367 [ 0.000000] psci: probing for conduit method from DT.
10489 09:34:13.338605 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10490 09:34:13.342077 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10491 09:34:13.348622 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10492 09:34:13.351655 [ 0.000000] psci: SMC Calling Convention v1.2
10493 09:34:13.358305 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10494 09:34:13.361935 [ 0.000000] Detected VIPT I-cache on CPU0
10495 09:34:13.368446 [ 0.000000] CPU features: detected: GIC system register CPU interface
10496 09:34:13.374686 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10497 09:34:13.381196 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10498 09:34:13.387912 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10499 09:34:13.398015 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10500 09:34:13.404278 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10501 09:34:13.407749 [ 0.000000] alternatives: applying boot alternatives
10502 09:34:13.414489 [ 0.000000] Fallback order for Node 0: 0
10503 09:34:13.420875 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10504 09:34:13.424366 [ 0.000000] Policy zone: Normal
10505 09:34:13.437309 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10506 09:34:13.447470 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10507 09:34:13.459089 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10508 09:34:13.469167 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10509 09:34:13.476017 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10510 09:34:13.478807 <6>[ 0.000000] software IO TLB: area num 8.
10511 09:34:13.535829 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10512 09:34:13.684577 <6>[ 0.000000] Memory: 7914392K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 438376K reserved, 32768K cma-reserved)
10513 09:34:13.691613 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10514 09:34:13.697991 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10515 09:34:13.701342 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10516 09:34:13.707695 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10517 09:34:13.714398 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10518 09:34:13.721259 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10519 09:34:13.727477 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10520 09:34:13.734279 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10521 09:34:13.740878 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10522 09:34:13.747519 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10523 09:34:13.750958 <6>[ 0.000000] GICv3: 608 SPIs implemented
10524 09:34:13.753992 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10525 09:34:13.760440 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10526 09:34:13.763807 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10527 09:34:13.770340 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10528 09:34:13.783216 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10529 09:34:13.796566 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10530 09:34:13.802995 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10531 09:34:13.811795 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10532 09:34:13.824962 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10533 09:34:13.831864 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10534 09:34:13.838454 <6>[ 0.009178] Console: colour dummy device 80x25
10535 09:34:13.847597 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10536 09:34:13.854342 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10537 09:34:13.858175 <6>[ 0.029210] LSM: Security Framework initializing
10538 09:34:13.864428 <6>[ 0.034177] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10539 09:34:13.874713 <6>[ 0.041991] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10540 09:34:13.884311 <6>[ 0.051410] cblist_init_generic: Setting adjustable number of callback queues.
10541 09:34:13.890803 <6>[ 0.058854] cblist_init_generic: Setting shift to 3 and lim to 1.
10542 09:34:13.897594 <6>[ 0.065193] cblist_init_generic: Setting adjustable number of callback queues.
10543 09:34:13.904082 <6>[ 0.072620] cblist_init_generic: Setting shift to 3 and lim to 1.
10544 09:34:13.907377 <6>[ 0.079020] rcu: Hierarchical SRCU implementation.
10545 09:34:13.913541 <6>[ 0.084036] rcu: Max phase no-delay instances is 1000.
10546 09:34:13.920065 <6>[ 0.091065] EFI services will not be available.
10547 09:34:13.923507 <6>[ 0.096018] smp: Bringing up secondary CPUs ...
10548 09:34:13.932707 <6>[ 0.101066] Detected VIPT I-cache on CPU1
10549 09:34:13.938831 <6>[ 0.101135] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10550 09:34:13.945566 <6>[ 0.101166] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10551 09:34:13.948769 <6>[ 0.101497] Detected VIPT I-cache on CPU2
10552 09:34:13.958873 <6>[ 0.101545] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10553 09:34:13.965146 <6>[ 0.101560] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10554 09:34:13.969097 <6>[ 0.101815] Detected VIPT I-cache on CPU3
10555 09:34:13.975322 <6>[ 0.101861] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10556 09:34:13.982114 <6>[ 0.101875] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10557 09:34:13.985206 <6>[ 0.102181] CPU features: detected: Spectre-v4
10558 09:34:13.992219 <6>[ 0.102188] CPU features: detected: Spectre-BHB
10559 09:34:13.995328 <6>[ 0.102192] Detected PIPT I-cache on CPU4
10560 09:34:14.001879 <6>[ 0.102248] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10561 09:34:14.008267 <6>[ 0.102265] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10562 09:34:14.014823 <6>[ 0.102558] Detected PIPT I-cache on CPU5
10563 09:34:14.021115 <6>[ 0.102619] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10564 09:34:14.028208 <6>[ 0.102635] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10565 09:34:14.031181 <6>[ 0.102913] Detected PIPT I-cache on CPU6
10566 09:34:14.040945 <6>[ 0.102978] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10567 09:34:14.047382 <6>[ 0.102994] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10568 09:34:14.050891 <6>[ 0.103291] Detected PIPT I-cache on CPU7
10569 09:34:14.057543 <6>[ 0.103355] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10570 09:34:14.064453 <6>[ 0.103371] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10571 09:34:14.067350 <6>[ 0.103417] smp: Brought up 1 node, 8 CPUs
10572 09:34:14.074628 <6>[ 0.244825] SMP: Total of 8 processors activated.
10573 09:34:14.080975 <6>[ 0.249746] CPU features: detected: 32-bit EL0 Support
10574 09:34:14.087213 <6>[ 0.255142] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10575 09:34:14.094233 <6>[ 0.263942] CPU features: detected: Common not Private translations
10576 09:34:14.100555 <6>[ 0.270418] CPU features: detected: CRC32 instructions
10577 09:34:14.107610 <6>[ 0.275770] CPU features: detected: RCpc load-acquire (LDAPR)
10578 09:34:14.110544 <6>[ 0.281766] CPU features: detected: LSE atomic instructions
10579 09:34:14.116907 <6>[ 0.287548] CPU features: detected: Privileged Access Never
10580 09:34:14.123586 <6>[ 0.293364] CPU features: detected: RAS Extension Support
10581 09:34:14.130328 <6>[ 0.298972] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10582 09:34:14.133413 <6>[ 0.306193] CPU: All CPU(s) started at EL2
10583 09:34:14.139910 <6>[ 0.310536] alternatives: applying system-wide alternatives
10584 09:34:14.150191 <6>[ 0.321245] devtmpfs: initialized
10585 09:34:14.166374 <6>[ 0.330017] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10586 09:34:14.172645 <6>[ 0.339979] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10587 09:34:14.178948 <6>[ 0.347771] pinctrl core: initialized pinctrl subsystem
10588 09:34:14.182169 <6>[ 0.354407] DMI not present or invalid.
10589 09:34:14.189037 <6>[ 0.358813] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10590 09:34:14.198536 <6>[ 0.365654] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10591 09:34:14.205276 <6>[ 0.373239] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10592 09:34:14.214870 <6>[ 0.381450] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10593 09:34:14.218110 <6>[ 0.389695] audit: initializing netlink subsys (disabled)
10594 09:34:14.228232 <5>[ 0.395386] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10595 09:34:14.234301 <6>[ 0.396088] thermal_sys: Registered thermal governor 'step_wise'
10596 09:34:14.240868 <6>[ 0.403352] thermal_sys: Registered thermal governor 'power_allocator'
10597 09:34:14.244445 <6>[ 0.409609] cpuidle: using governor menu
10598 09:34:14.251276 <6>[ 0.420566] NET: Registered PF_QIPCRTR protocol family
10599 09:34:14.257711 <6>[ 0.426047] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10600 09:34:14.264375 <6>[ 0.433153] ASID allocator initialised with 32768 entries
10601 09:34:14.267120 <6>[ 0.439715] Serial: AMBA PL011 UART driver
10602 09:34:14.277384 <4>[ 0.448434] Trying to register duplicate clock ID: 134
10603 09:34:14.331836 <6>[ 0.506023] KASLR enabled
10604 09:34:14.346197 <6>[ 0.513711] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10605 09:34:14.352833 <6>[ 0.520729] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10606 09:34:14.359125 <6>[ 0.527219] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10607 09:34:14.365687 <6>[ 0.534225] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10608 09:34:14.372416 <6>[ 0.540713] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10609 09:34:14.379110 <6>[ 0.547719] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10610 09:34:14.385618 <6>[ 0.554208] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10611 09:34:14.392403 <6>[ 0.561211] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10612 09:34:14.395379 <6>[ 0.568733] ACPI: Interpreter disabled.
10613 09:34:14.403983 <6>[ 0.575132] iommu: Default domain type: Translated
10614 09:34:14.410735 <6>[ 0.580243] iommu: DMA domain TLB invalidation policy: strict mode
10615 09:34:14.414276 <5>[ 0.586902] SCSI subsystem initialized
10616 09:34:14.420736 <6>[ 0.591067] usbcore: registered new interface driver usbfs
10617 09:34:14.427291 <6>[ 0.596801] usbcore: registered new interface driver hub
10618 09:34:14.430566 <6>[ 0.602356] usbcore: registered new device driver usb
10619 09:34:14.437334 <6>[ 0.608454] pps_core: LinuxPPS API ver. 1 registered
10620 09:34:14.447273 <6>[ 0.613645] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10621 09:34:14.450303 <6>[ 0.622991] PTP clock support registered
10622 09:34:14.453722 <6>[ 0.627234] EDAC MC: Ver: 3.0.0
10623 09:34:14.461431 <6>[ 0.632391] FPGA manager framework
10624 09:34:14.468357 <6>[ 0.636073] Advanced Linux Sound Architecture Driver Initialized.
10625 09:34:14.471242 <6>[ 0.642839] vgaarb: loaded
10626 09:34:14.477352 <6>[ 0.645995] clocksource: Switched to clocksource arch_sys_counter
10627 09:34:14.480782 <5>[ 0.652434] VFS: Disk quotas dquot_6.6.0
10628 09:34:14.487960 <6>[ 0.656622] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10629 09:34:14.491114 <6>[ 0.663808] pnp: PnP ACPI: disabled
10630 09:34:14.499490 <6>[ 0.670543] NET: Registered PF_INET protocol family
10631 09:34:14.509391 <6>[ 0.676144] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10632 09:34:14.520410 <6>[ 0.688484] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10633 09:34:14.530540 <6>[ 0.697298] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10634 09:34:14.536926 <6>[ 0.705270] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10635 09:34:14.546973 <6>[ 0.713972] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10636 09:34:14.553898 <6>[ 0.723715] TCP: Hash tables configured (established 65536 bind 65536)
10637 09:34:14.559704 <6>[ 0.730581] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10638 09:34:14.569552 <6>[ 0.737776] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10639 09:34:14.576143 <6>[ 0.745475] NET: Registered PF_UNIX/PF_LOCAL protocol family
10640 09:34:14.582723 <6>[ 0.751551] RPC: Registered named UNIX socket transport module.
10641 09:34:14.586097 <6>[ 0.757698] RPC: Registered udp transport module.
10642 09:34:14.592653 <6>[ 0.762632] RPC: Registered tcp transport module.
10643 09:34:14.599361 <6>[ 0.767563] RPC: Registered tcp NFSv4.1 backchannel transport module.
10644 09:34:14.602595 <6>[ 0.774227] PCI: CLS 0 bytes, default 64
10645 09:34:14.606497 <6>[ 0.778567] Unpacking initramfs...
10646 09:34:14.631043 <6>[ 0.798131] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10647 09:34:14.640599 <6>[ 0.806789] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10648 09:34:14.644003 <6>[ 0.815632] kvm [1]: IPA Size Limit: 40 bits
10649 09:34:14.650289 <6>[ 0.820159] kvm [1]: GICv3: no GICV resource entry
10650 09:34:14.653632 <6>[ 0.825178] kvm [1]: disabling GICv2 emulation
10651 09:34:14.659847 <6>[ 0.829865] kvm [1]: GIC system register CPU interface enabled
10652 09:34:14.663414 <6>[ 0.836036] kvm [1]: vgic interrupt IRQ18
10653 09:34:14.670195 <6>[ 0.840399] kvm [1]: VHE mode initialized successfully
10654 09:34:14.676603 <5>[ 0.846880] Initialise system trusted keyrings
10655 09:34:14.682809 <6>[ 0.851722] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10656 09:34:14.690432 <6>[ 0.861683] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10657 09:34:14.697401 <5>[ 0.868057] NFS: Registering the id_resolver key type
10658 09:34:14.700172 <5>[ 0.873358] Key type id_resolver registered
10659 09:34:14.706964 <5>[ 0.877772] Key type id_legacy registered
10660 09:34:14.713525 <6>[ 0.882049] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10661 09:34:14.720026 <6>[ 0.888968] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10662 09:34:14.726369 <6>[ 0.896672] 9p: Installing v9fs 9p2000 file system support
10663 09:34:14.763383 <5>[ 0.934557] Key type asymmetric registered
10664 09:34:14.767123 <5>[ 0.938888] Asymmetric key parser 'x509' registered
10665 09:34:14.776559 <6>[ 0.944030] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10666 09:34:14.779860 <6>[ 0.951643] io scheduler mq-deadline registered
10667 09:34:14.783289 <6>[ 0.956399] io scheduler kyber registered
10668 09:34:14.802426 <6>[ 0.973458] EINJ: ACPI disabled.
10669 09:34:14.834751 <4>[ 0.999023] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 09:34:14.844424 <4>[ 1.009640] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 09:34:14.859286 <6>[ 1.030157] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10672 09:34:14.866838 <6>[ 1.038092] printk: console [ttyS0] disabled
10673 09:34:14.895219 <6>[ 1.062736] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10674 09:34:14.901861 <6>[ 1.072208] printk: console [ttyS0] enabled
10675 09:34:14.904531 <6>[ 1.072208] printk: console [ttyS0] enabled
10676 09:34:14.911347 <6>[ 1.081109] printk: bootconsole [mtk8250] disabled
10677 09:34:14.914931 <6>[ 1.081109] printk: bootconsole [mtk8250] disabled
10678 09:34:14.921317 <6>[ 1.092104] SuperH (H)SCI(F) driver initialized
10679 09:34:14.924631 <6>[ 1.097363] msm_serial: driver initialized
10680 09:34:14.938207 <6>[ 1.106207] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10681 09:34:14.947924 <6>[ 1.114758] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10682 09:34:14.954654 <6>[ 1.123299] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10683 09:34:14.964903 <6>[ 1.131926] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10684 09:34:14.975269 <6>[ 1.140632] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10685 09:34:14.980966 <6>[ 1.149343] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10686 09:34:14.991129 <6>[ 1.157884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10687 09:34:14.997776 <6>[ 1.166676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10688 09:34:15.007125 <6>[ 1.175217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10689 09:34:15.019672 <6>[ 1.190582] loop: module loaded
10690 09:34:15.026059 <6>[ 1.196631] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10691 09:34:15.047948 <4>[ 1.219360] mtk-pmic-keys: Failed to locate of_node [id: -1]
10692 09:34:15.055296 <6>[ 1.226105] megasas: 07.719.03.00-rc1
10693 09:34:15.064686 <6>[ 1.235579] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10694 09:34:15.070997 <6>[ 1.237420] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10695 09:34:15.085776 <6>[ 1.257064] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10696 09:34:15.144990 <6>[ 1.309814] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10697 09:34:16.991608 <6>[ 3.163005] Freeing initrd memory: 55096K
10698 09:34:17.001713 <6>[ 3.173527] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10699 09:34:17.013593 <6>[ 3.184531] tun: Universal TUN/TAP device driver, 1.6
10700 09:34:17.016734 <6>[ 3.190609] thunder_xcv, ver 1.0
10701 09:34:17.019889 <6>[ 3.194112] thunder_bgx, ver 1.0
10702 09:34:17.022979 <6>[ 3.197606] nicpf, ver 1.0
10703 09:34:17.034191 <6>[ 3.201629] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10704 09:34:17.036861 <6>[ 3.209106] hns3: Copyright (c) 2017 Huawei Corporation.
10705 09:34:17.043495 <6>[ 3.214696] hclge is initializing
10706 09:34:17.046996 <6>[ 3.218276] e1000: Intel(R) PRO/1000 Network Driver
10707 09:34:17.053521 <6>[ 3.223405] e1000: Copyright (c) 1999-2006 Intel Corporation.
10708 09:34:17.056554 <6>[ 3.229419] e1000e: Intel(R) PRO/1000 Network Driver
10709 09:34:17.063498 <6>[ 3.234634] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10710 09:34:17.070226 <6>[ 3.240819] igb: Intel(R) Gigabit Ethernet Network Driver
10711 09:34:17.076765 <6>[ 3.246469] igb: Copyright (c) 2007-2014 Intel Corporation.
10712 09:34:17.083482 <6>[ 3.252306] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10713 09:34:17.090035 <6>[ 3.258823] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10714 09:34:17.093356 <6>[ 3.265289] sky2: driver version 1.30
10715 09:34:17.099962 <6>[ 3.270298] VFIO - User Level meta-driver version: 0.3
10716 09:34:17.106880 <6>[ 3.278560] usbcore: registered new interface driver usb-storage
10717 09:34:17.113871 <6>[ 3.285009] usbcore: registered new device driver onboard-usb-hub
10718 09:34:17.123146 <6>[ 3.294208] mt6397-rtc mt6359-rtc: registered as rtc0
10719 09:34:17.133493 <6>[ 3.299674] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:34:18 UTC (1697794458)
10720 09:34:17.136599 <6>[ 3.309271] i2c_dev: i2c /dev entries driver
10721 09:34:17.152481 <6>[ 3.321003] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10722 09:34:17.172619 <6>[ 3.344010] cpu cpu0: EM: created perf domain
10723 09:34:17.175792 <6>[ 3.348954] cpu cpu4: EM: created perf domain
10724 09:34:17.183037 <6>[ 3.354589] sdhci: Secure Digital Host Controller Interface driver
10725 09:34:17.190167 <6>[ 3.361020] sdhci: Copyright(c) Pierre Ossman
10726 09:34:17.196285 <6>[ 3.365974] Synopsys Designware Multimedia Card Interface Driver
10727 09:34:17.203140 <6>[ 3.372609] sdhci-pltfm: SDHCI platform and OF driver helper
10728 09:34:17.206162 <6>[ 3.372653] mmc0: CQHCI version 5.10
10729 09:34:17.213152 <6>[ 3.382871] ledtrig-cpu: registered to indicate activity on CPUs
10730 09:34:17.220075 <6>[ 3.389919] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10731 09:34:17.226464 <6>[ 3.396980] usbcore: registered new interface driver usbhid
10732 09:34:17.229542 <6>[ 3.402805] usbhid: USB HID core driver
10733 09:34:17.235872 <6>[ 3.406991] spi_master spi0: will run message pump with realtime priority
10734 09:34:17.279931 <6>[ 3.444943] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10735 09:34:17.298670 <6>[ 3.460269] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10736 09:34:17.302270 <6>[ 3.473845] mmc0: Command Queue Engine enabled
10737 09:34:17.308567 <6>[ 3.478610] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10738 09:34:17.315480 <6>[ 3.486097] mmcblk0: mmc0:0001 DA4128 116 GiB
10739 09:34:17.318639 <6>[ 3.486156] cros-ec-spi spi0.0: Chrome EC device registered
10740 09:34:17.325392 <6>[ 3.495075] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10741 09:34:17.333118 <6>[ 3.504408] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10742 09:34:17.339466 <6>[ 3.510388] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10743 09:34:17.346325 <6>[ 3.516530] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10744 09:34:17.365390 <6>[ 3.533742] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10745 09:34:17.373578 <6>[ 3.544703] NET: Registered PF_PACKET protocol family
10746 09:34:17.376742 <6>[ 3.550116] 9pnet: Installing 9P2000 support
10747 09:34:17.383612 <5>[ 3.554689] Key type dns_resolver registered
10748 09:34:17.386355 <6>[ 3.559675] registered taskstats version 1
10749 09:34:17.392984 <5>[ 3.564064] Loading compiled-in X.509 certificates
10750 09:34:17.422176 <4>[ 3.587218] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10751 09:34:17.432385 <4>[ 3.597957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10752 09:34:17.439156 <3>[ 3.608493] debugfs: File 'uA_load' in directory '/' already present!
10753 09:34:17.445791 <3>[ 3.615193] debugfs: File 'min_uV' in directory '/' already present!
10754 09:34:17.452302 <3>[ 3.621800] debugfs: File 'max_uV' in directory '/' already present!
10755 09:34:17.458621 <3>[ 3.628407] debugfs: File 'constraint_flags' in directory '/' already present!
10756 09:34:17.470099 <3>[ 3.638120] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10757 09:34:17.483100 <6>[ 3.654117] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10758 09:34:17.489805 <6>[ 3.661024] xhci-mtk 11200000.usb: xHCI Host Controller
10759 09:34:17.496685 <6>[ 3.666535] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10760 09:34:17.506264 <6>[ 3.674499] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10761 09:34:17.513059 <6>[ 3.683935] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10762 09:34:17.519571 <6>[ 3.690050] xhci-mtk 11200000.usb: xHCI Host Controller
10763 09:34:17.526442 <6>[ 3.695529] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10764 09:34:17.532987 <6>[ 3.703179] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10765 09:34:17.539483 <6>[ 3.710967] hub 1-0:1.0: USB hub found
10766 09:34:17.543065 <6>[ 3.714990] hub 1-0:1.0: 1 port detected
10767 09:34:17.552715 <6>[ 3.719284] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10768 09:34:17.555773 <6>[ 3.728002] hub 2-0:1.0: USB hub found
10769 09:34:17.559035 <6>[ 3.732027] hub 2-0:1.0: 1 port detected
10770 09:34:17.566987 <6>[ 3.738631] mtk-msdc 11f70000.mmc: Got CD GPIO
10771 09:34:17.579498 <6>[ 3.747588] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10772 09:34:17.586284 <6>[ 3.755631] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10773 09:34:17.596098 <4>[ 3.763533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10774 09:34:17.606114 <6>[ 3.773057] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10775 09:34:17.612671 <6>[ 3.781134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10776 09:34:17.622454 <6>[ 3.789263] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10777 09:34:17.628822 <6>[ 3.797188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10778 09:34:17.636273 <6>[ 3.805005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10779 09:34:17.645476 <6>[ 3.812826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10780 09:34:17.655139 <6>[ 3.823287] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10781 09:34:17.662150 <6>[ 3.831652] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10782 09:34:17.672449 <6>[ 3.839995] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10783 09:34:17.681895 <6>[ 3.848334] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10784 09:34:17.688142 <6>[ 3.856675] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10785 09:34:17.698437 <6>[ 3.865017] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10786 09:34:17.705055 <6>[ 3.873355] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10787 09:34:17.714990 <6>[ 3.881694] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10788 09:34:17.721595 <6>[ 3.890085] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10789 09:34:17.732153 <6>[ 3.898427] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10790 09:34:17.737726 <6>[ 3.906764] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10791 09:34:17.747706 <6>[ 3.915104] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10792 09:34:17.754266 <6>[ 3.923442] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10793 09:34:17.764826 <6>[ 3.931792] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10794 09:34:17.771022 <6>[ 3.940130] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10795 09:34:17.777231 <6>[ 3.948856] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10796 09:34:17.784379 <6>[ 3.956009] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10797 09:34:17.791489 <6>[ 3.962776] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10798 09:34:17.801453 <6>[ 3.969532] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10799 09:34:17.807649 <6>[ 3.976472] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10800 09:34:17.814443 <6>[ 3.983328] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10801 09:34:17.824694 <6>[ 3.992484] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10802 09:34:17.834229 <6>[ 4.001613] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10803 09:34:17.844225 <6>[ 4.010909] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10804 09:34:17.853784 <6>[ 4.020377] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10805 09:34:17.864018 <6>[ 4.029844] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10806 09:34:17.870579 <6>[ 4.038965] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10807 09:34:17.880399 <6>[ 4.048433] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10808 09:34:17.890324 <6>[ 4.057554] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10809 09:34:17.900371 <6>[ 4.066849] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10810 09:34:17.910301 <6>[ 4.077009] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10811 09:34:17.920791 <6>[ 4.089173] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10812 09:34:17.949819 <6>[ 4.118475] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10813 09:34:17.979164 <6>[ 4.150891] hub 2-1:1.0: USB hub found
10814 09:34:17.982427 <6>[ 4.155410] hub 2-1:1.0: 3 ports detected
10815 09:34:18.101623 <6>[ 4.270165] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10816 09:34:18.256993 <6>[ 4.428274] hub 1-1:1.0: USB hub found
10817 09:34:18.260217 <6>[ 4.432785] hub 1-1:1.0: 4 ports detected
10818 09:34:18.582052 <6>[ 4.750317] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10819 09:34:18.713361 <6>[ 4.884436] hub 1-1.1:1.0: USB hub found
10820 09:34:18.716204 <6>[ 4.888785] hub 1-1.1:1.0: 4 ports detected
10821 09:34:18.830110 <6>[ 4.998309] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10822 09:34:18.961233 <6>[ 5.133168] hub 1-1.4:1.0: USB hub found
10823 09:34:18.965477 <6>[ 5.137804] hub 1-1.4:1.0: 2 ports detected
10824 09:34:19.041996 <6>[ 5.210321] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10825 09:34:19.234130 <6>[ 5.402257] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10826 09:34:19.318889 <3>[ 5.490443] usb 1-1.1.4: device descriptor read/64, error -32
10827 09:34:19.511191 <3>[ 5.682457] usb 1-1.1.4: device descriptor read/64, error -32
10828 09:34:19.705944 <6>[ 5.874317] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10829 09:34:19.893624 <6>[ 6.062298] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10830 09:34:19.978918 <3>[ 6.150499] usb 1-1.1.4: device descriptor read/64, error -32
10831 09:34:20.170757 <3>[ 6.342503] usb 1-1.1.4: device descriptor read/64, error -32
10832 09:34:20.283332 <6>[ 6.454851] usb 1-1.1-port4: attempt power cycle
10833 09:34:20.370215 <6>[ 6.538319] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10834 09:34:20.894189 <6>[ 7.062317] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10835 09:34:20.900409 <4>[ 7.069795] usb 1-1.1.4: Device not responding to setup address.
10836 09:34:21.110385 <4>[ 7.282542] usb 1-1.1.4: Device not responding to setup address.
10837 09:34:21.323060 <3>[ 7.494311] usb 1-1.1.4: device not accepting address 10, error -71
10838 09:34:21.410050 <6>[ 7.578318] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10839 09:34:21.416699 <4>[ 7.585806] usb 1-1.1.4: Device not responding to setup address.
10840 09:34:21.626243 <4>[ 7.798545] usb 1-1.1.4: Device not responding to setup address.
10841 09:34:21.839048 <3>[ 8.010353] usb 1-1.1.4: device not accepting address 11, error -71
10842 09:34:21.845348 <3>[ 8.017395] usb 1-1.1-port4: unable to enumerate USB device
10843 09:34:30.223003 <6>[ 16.399264] ALSA device list:
10844 09:34:30.229272 <6>[ 16.402549] No soundcards found.
10845 09:34:30.237309 <6>[ 16.410430] Freeing unused kernel memory: 8384K
10846 09:34:30.240453 <6>[ 16.415391] Run /init as init process
10847 09:34:30.288470 <6>[ 16.461590] NET: Registered PF_INET6 protocol family
10848 09:34:30.294934 <6>[ 16.467692] Segment Routing with IPv6
10849 09:34:30.298553 <6>[ 16.471646] In-situ OAM (IOAM) with IPv6
10850 09:34:30.333727 <30>[ 16.486583] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10851 09:34:30.336521 <30>[ 16.510536] systemd[1]: Detected architecture arm64.
10852 09:34:30.339798
10853 09:34:30.343574 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10854 09:34:30.344154
10855 09:34:30.357674 <30>[ 16.530345] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10856 09:34:30.505634 <30>[ 16.675281] systemd[1]: Queued start job for default target Graphical Interface.
10857 09:34:30.562358 <30>[ 16.735085] systemd[1]: Created slice system-getty.slice.
10858 09:34:30.568857 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10859 09:34:30.586492 <30>[ 16.759402] systemd[1]: Created slice system-modprobe.slice.
10860 09:34:30.593079 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10861 09:34:30.610402 <30>[ 16.782820] systemd[1]: Created slice system-serial\x2dgetty.slice.
10862 09:34:30.620454 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10863 09:34:30.634712 <30>[ 16.807769] systemd[1]: Created slice User and Session Slice.
10864 09:34:30.641444 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10865 09:34:30.660883 <30>[ 16.830515] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10866 09:34:30.671098 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10867 09:34:30.684917 <30>[ 16.854459] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10868 09:34:30.691365 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10869 09:34:30.712175 <30>[ 16.878348] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10870 09:34:30.719084 <30>[ 16.890498] systemd[1]: Reached target Local Encrypted Volumes.
10871 09:34:30.725100 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10872 09:34:30.741736 <30>[ 16.914649] systemd[1]: Reached target Paths.
10873 09:34:30.744707 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10874 09:34:30.761031 <30>[ 16.934282] systemd[1]: Reached target Remote File Systems.
10875 09:34:30.767610 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10876 09:34:30.781644 <30>[ 16.954271] systemd[1]: Reached target Slices.
10877 09:34:30.784710 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10878 09:34:30.801093 <30>[ 16.974289] systemd[1]: Reached target Swap.
10879 09:34:30.804704 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10880 09:34:30.825059 <30>[ 16.994759] systemd[1]: Listening on initctl Compatibility Named Pipe.
10881 09:34:30.831697 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10882 09:34:30.846765 <30>[ 17.019705] systemd[1]: Listening on Journal Audit Socket.
10883 09:34:30.853135 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10884 09:34:30.870416 <30>[ 17.043429] systemd[1]: Listening on Journal Socket (/dev/log).
10885 09:34:30.877117 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10886 09:34:30.894696 <30>[ 17.067457] systemd[1]: Listening on Journal Socket.
10887 09:34:30.900802 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10888 09:34:30.913971 <30>[ 17.086832] systemd[1]: Listening on udev Control Socket.
10889 09:34:30.920439 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10890 09:34:30.938288 <30>[ 17.111315] systemd[1]: Listening on udev Kernel Socket.
10891 09:34:30.944570 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10892 09:34:30.997694 <30>[ 17.170540] systemd[1]: Mounting Huge Pages File System...
10893 09:34:31.004342 Mounting [0;1;39mHuge Pages File System[0m...
10894 09:34:31.021428 <30>[ 17.194204] systemd[1]: Mounting POSIX Message Queue File System...
10895 09:34:31.028128 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10896 09:34:31.057505 <30>[ 17.230325] systemd[1]: Mounting Kernel Debug File System...
10897 09:34:31.064324 Mounting [0;1;39mKernel Debug File System[0m...
10898 09:34:31.080811 <30>[ 17.250677] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10899 09:34:31.093739 <30>[ 17.263669] systemd[1]: Starting Create list of static device nodes for the current kernel...
10900 09:34:31.100841 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10901 09:34:31.121729 <30>[ 17.294725] systemd[1]: Starting Load Kernel Module configfs...
10902 09:34:31.128811 Starting [0;1;39mLoad Kernel Module configfs[0m...
10903 09:34:31.145276 <30>[ 17.318273] systemd[1]: Starting Load Kernel Module drm...
10904 09:34:31.151704 Starting [0;1;39mLoad Kernel Module drm[0m...
10905 09:34:31.168530 <30>[ 17.338400] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10906 09:34:31.182880 <30>[ 17.355856] systemd[1]: Starting Journal Service...
10907 09:34:31.186585 Starting [0;1;39mJournal Service[0m...
10908 09:34:31.204205 <30>[ 17.377100] systemd[1]: Starting Load Kernel Modules...
10909 09:34:31.210793 Starting [0;1;39mLoad Kernel Modules[0m...
10910 09:34:31.233087 <30>[ 17.402990] systemd[1]: Starting Remount Root and Kernel File Systems...
10911 09:34:31.239558 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10912 09:34:31.256428 <30>[ 17.429582] systemd[1]: Starting Coldplug All udev Devices...
10913 09:34:31.263067 Starting [0;1;39mColdplug All udev Devices[0m...
10914 09:34:31.280905 <30>[ 17.454070] systemd[1]: Started Journal Service.
10915 09:34:31.287243 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10916 09:34:31.303805 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10917 09:34:31.322354 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10918 09:34:31.342502 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10919 09:34:31.366724 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10920 09:34:31.389377 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10921 09:34:31.410862 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10922 09:34:31.427867 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10923 09:34:31.447351 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10924 09:34:31.461439 See 'systemctl status systemd-remount-fs.service' for details.
10925 09:34:31.514665 Mounting [0;1;39mKernel Configuration File System[0m...
10926 09:34:31.537018 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10927 09:34:31.550259 <46>[ 17.719961] systemd-journald[188]: Received client request to flush runtime journal.
10928 09:34:31.560038 Starting [0;1;39mLoad/Save Random Seed[0m...
10929 09:34:31.581528 Starting [0;1;39mApply Kernel Variables[0m...
10930 09:34:31.606796 Starting [0;1;39mCreate System Users[0m...
10931 09:34:31.632083 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10932 09:34:31.650257 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10933 09:34:31.669909 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10934 09:34:31.683494 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10935 09:34:31.698895 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10936 09:34:31.715405 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10937 09:34:31.765958 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10938 09:34:31.794668 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10939 09:34:31.809798 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10940 09:34:31.825206 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10941 09:34:31.877427 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10942 09:34:31.902260 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10943 09:34:31.927322 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10944 09:34:31.946388 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10945 09:34:31.999120 Starting [0;1;39mNetwork Time Synchronization[0m...
10946 09:34:32.018039 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10947 09:34:32.055846 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10948 09:34:32.072421 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10949 09:34:32.094929 <6>[ 18.264901] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10950 09:34:32.101690 <6>[ 18.265061] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10951 09:34:32.112190 <6>[ 18.272585] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10952 09:34:32.115196 <6>[ 18.285484] remoteproc remoteproc0: scp is available
10953 09:34:32.124710 <6>[ 18.288781] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10954 09:34:32.127561 <6>[ 18.294900] remoteproc remoteproc0: powering up scp
10955 09:34:32.142146 [[0;32m OK [0m] Found device [0;1;39m/dev/t<6>[ 18.312510] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10956 09:34:32.145174 tyS0[0m.
10957 09:34:32.148756 <6>[ 18.321425] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10958 09:34:32.155544 <6>[ 18.321962] mc: Linux media interface: v0.10
10959 09:34:32.158861 <6>[ 18.330496] usbcore: registered new interface driver r8152
10960 09:34:32.168601 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10961 09:34:32.175104 <4>[ 18.347417] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10962 09:34:32.190034 [[0;32m OK [0m] Reached target [0;1;39mSyst<4>[ 18.359958] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10963 09:34:32.199957 em Time Set[0m.<6>[ 18.361768] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10964 09:34:32.200491
10965 09:34:32.206396 <3>[ 18.368184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 09:34:32.213032 <6>[ 18.378824] videodev: Linux video capture interface: v2.00
10967 09:34:32.222658 <3>[ 18.385417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10968 09:34:32.228961 <3>[ 18.399364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 09:34:32.239075 [[0;32m OK [<3>[ 18.409081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 09:34:32.248757 <4>[ 18.416753] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10971 09:34:32.252043 <4>[ 18.416753] Fallback method does not support PEC.
10972 09:34:32.262145 <3>[ 18.417500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10973 09:34:32.268950 <6>[ 18.418244] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10974 09:34:32.275856 0m] Reached targ<6>[ 18.423755] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10975 09:34:32.282242 et [0;1;39mSyst<6>[ 18.423765] pci_bus 0000:00: root bus resource [bus 00-ff]
10976 09:34:32.292346 <6>[ 18.423773] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10977 09:34:32.302299 em Time Synchron<6>[ 18.423781] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10978 09:34:32.309123 <6>[ 18.423831] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10979 09:34:32.315563 <6>[ 18.423863] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10980 09:34:32.316137 ized[0m.
10981 09:34:32.322052 <6>[ 18.423983] pci 0000:00:00.0: supports D1 D2
10982 09:34:32.328390 <6>[ 18.423987] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10983 09:34:32.335274 <6>[ 18.425256] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10984 09:34:32.341753 <6>[ 18.425351] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10985 09:34:32.348892 <6>[ 18.425379] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10986 09:34:32.358840 <6>[ 18.425397] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10987 09:34:32.365511 <6>[ 18.425412] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10988 09:34:32.368492 <6>[ 18.425518] pci 0000:01:00.0: supports D1 D2
10989 09:34:32.375400 <6>[ 18.425520] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10990 09:34:32.385247 <6>[ 18.438110] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10991 09:34:32.392110 <3>[ 18.439112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 09:34:32.398414 <6>[ 18.446454] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10993 09:34:32.409386 <3>[ 18.451439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 09:34:32.415920 <6>[ 18.453482] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10995 09:34:32.422757 <6>[ 18.453490] remoteproc remoteproc0: remote processor scp is now up
10996 09:34:32.429615 <6>[ 18.453491] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10997 09:34:32.439095 <3>[ 18.454671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10998 09:34:32.446687 <6>[ 18.461795] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10999 09:34:32.453727 <3>[ 18.468917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11000 09:34:32.463332 <6>[ 18.480212] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11001 09:34:32.470232 <3>[ 18.486511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11002 09:34:32.479609 <6>[ 18.487673] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11003 09:34:32.486359 <6>[ 18.488962] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11004 09:34:32.496198 <6>[ 18.493937] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11005 09:34:32.505994 <6>[ 18.497867] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11006 09:34:32.512590 <3>[ 18.499432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11007 09:34:32.522702 <6>[ 18.506274] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11008 09:34:32.532742 <6>[ 18.514517] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11009 09:34:32.538964 <6>[ 18.514914] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11010 09:34:32.549774 <3>[ 18.514930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11011 09:34:32.556648 <3>[ 18.514935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11012 09:34:32.566612 <3>[ 18.514968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 09:34:32.573105 <3>[ 18.514971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11014 09:34:32.579893 <3>[ 18.514974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11015 09:34:32.589853 <3>[ 18.514978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11016 09:34:32.596370 <3>[ 18.514981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11017 09:34:32.606497 <3>[ 18.514996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11018 09:34:32.613373 <3>[ 18.516092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 09:34:32.623006 <3>[ 18.520805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11020 09:34:32.626778 <6>[ 18.521322] pci 0000:00:00.0: PCI bridge to [bus 01]
11021 09:34:32.636572 <4>[ 18.532159] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11022 09:34:32.643330 <6>[ 18.536491] usbcore: registered new interface driver cdc_ether
11023 09:34:32.649736 <6>[ 18.537485] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11024 09:34:32.656284 <6>[ 18.537693] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11025 09:34:32.663137 <6>[ 18.540451] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11026 09:34:32.673108 <4>[ 18.543516] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11027 09:34:32.679682 <6>[ 18.547532] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11028 09:34:32.683054 <6>[ 18.570518] usbcore: registered new interface driver r8153_ecm
11029 09:34:32.689678 <6>[ 18.579492] Bluetooth: Core ver 2.22
11030 09:34:32.695766 <5>[ 18.581520] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11031 09:34:32.702859 <5>[ 18.592998] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11032 09:34:32.712497 <3>[ 18.594622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 09:34:32.715382 <6>[ 18.595332] NET: Registered PF_BLUETOOTH protocol family
11034 09:34:32.725841 <3>[ 18.595518] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11035 09:34:32.732949 <6>[ 18.596843] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11036 09:34:32.742930 <6>[ 18.597950] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11037 09:34:32.749647 <6>[ 18.598086] usbcore: registered new interface driver uvcvideo
11038 09:34:32.760123 <4>[ 18.601791] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11039 09:34:32.767142 <6>[ 18.608778] Bluetooth: HCI device and connection manager initialized
11040 09:34:32.770659 <6>[ 18.608814] Bluetooth: HCI socket layer initialized
11041 09:34:32.777180 <6>[ 18.608820] Bluetooth: L2CAP socket layer initialized
11042 09:34:32.780664 <6>[ 18.608834] Bluetooth: SCO socket layer initialized
11043 09:34:32.791169 <3>[ 18.616041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 09:34:32.794384 <6>[ 18.616951] cfg80211: failed to load regulatory.db
11045 09:34:32.801316 <6>[ 18.626860] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11046 09:34:32.811372 <3>[ 18.636592] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 09:34:32.814445 <6>[ 18.683838] usbcore: registered new interface driver btusb
11048 09:34:32.828119 <4>[ 18.692025] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11049 09:34:32.831290 <6>[ 18.699302] r8152 1-1.1.1:1.0 eth0: v1.12.13
11050 09:34:32.837929 <6>[ 18.712197] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11051 09:34:32.844335 <6>[ 18.717313] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11052 09:34:32.850894 <3>[ 18.718661] Bluetooth: hci0: Failed to load firmware file (-2)
11053 09:34:32.860800 <3>[ 18.721801] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11054 09:34:32.867761 <6>[ 18.726837] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11055 09:34:32.870466 <3>[ 18.734813] Bluetooth: hci0: Failed to set up firmware (-2)
11056 09:34:32.880751 <4>[ 18.734819] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11057 09:34:32.890888 <3>[ 18.744486] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 09:34:32.897287 <6>[ 18.762118] mt7921e 0000:01:00.0: ASIC revision: 79610010
11059 09:34:32.904145 <3>[ 18.791872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 09:34:32.916793 <4>[ 18.884940] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11061 09:34:32.923901 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11062 09:34:32.947336 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11063 09:34:33.034486 <4>[ 19.200326] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11064 09:34:33.110009 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11065 09:34:33.125160 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11066 09:34:33.148710 [[0;32m OK [<4>[ 19.316296] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11067 09:34:33.155365 0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11068 09:34:33.172534 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11069 09:34:33.189348 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11070 09:34:33.213248 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11071 09:34:33.229992 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11072 09:34:33.245214 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11073 09:34:33.269641 [[0;32m OK [<4>[ 19.436785] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11074 09:34:33.276525 0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11075 09:34:33.333854 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11076 09:34:33.365660 Starting [0;1;39mUser Login Management[0m...
11077 09:34:33.391236 <4>[ 19.557435] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11078 09:34:33.397241 Starting [0;1;39mPermit User Sessions[0m...
11079 09:34:33.417382 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11080 09:34:33.466238 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11081 09:34:33.491075 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11082 09:34:33.510626 [[0;32m OK [0m] Reached target [0;1;39mLogi<4>[ 19.677063] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11083 09:34:33.513864 n Prompts[0m.
11084 09:34:33.535178 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11085 09:34:33.558645 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11086 09:34:33.578046 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11087 09:34:33.586559 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11088 09:34:33.606140 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11089 09:34:33.630154 <4>[ 19.796147] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11090 09:34:33.670287 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11091 09:34:33.696515 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11092 09:34:33.734748
11093 09:34:33.735303
11094 09:34:33.737762 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11095 09:34:33.738224
11096 09:34:33.754870 debian-bullseye-arm64 login: root (automat<4>[ 19.919365] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11097 09:34:33.755439 ic login)
11098 09:34:33.755860
11099 09:34:33.756209
11100 09:34:33.783879 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
11101 09:34:33.784444
11102 09:34:33.790048 The programs included with the Debian GNU/Linux system are free software;
11103 09:34:33.796726 the exact distribution terms for each program are described in the
11104 09:34:33.800295 individual files in /usr/share/doc/*/copyright.
11105 09:34:33.800857
11106 09:34:33.806594 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11107 09:34:33.809667 permitted by applicable law.
11108 09:34:33.811097 Matched prompt #10: / #
11110 09:34:33.812261 Setting prompt string to ['/ #']
11111 09:34:33.812736 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11113 09:34:33.813868 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11114 09:34:33.814364 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
11115 09:34:33.814774 Setting prompt string to ['/ #']
11116 09:34:33.815122 Forcing a shell prompt, looking for ['/ #']
11118 09:34:33.865972 / #
11119 09:34:33.866605 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11120 09:34:33.867045 Waiting using forced prompt support (timeout 00:02:30)
11121 09:34:33.908387 <4>[ 20.040702] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11122 09:34:33.908974
11123 09:34:33.909726 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11124 09:34:33.910255 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
11125 09:34:33.910757 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11126 09:34:33.911222 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
11127 09:34:33.911678 end: 2 depthcharge-action (duration 00:01:35) [common]
11128 09:34:33.912204 start: 3 lava-test-retry (timeout 00:08:03) [common]
11129 09:34:33.912664 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11130 09:34:33.913061 Using namespace: common
11132 09:34:34.014279 / # #
11133 09:34:34.014924 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11134 09:34:34.015507 #<4>[ 20.160877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11135 09:34:34.020965
11136 09:34:34.021856 Using /lava-11826833
11138 09:34:34.123176 / # export SHELL=/bin/sh
11139 09:34:34.124014 export SHELL=/bin/sh<3>[ 20.278641] mt7921e 0000:01:00.0: hardware init failed
11140 09:34:34.129375
11142 09:34:34.230993 / # . /lava-11826833/environment
11143 09:34:34.237171 . /lava-11826833/environment
11145 09:34:34.338677 / # /lava-11826833/bin/lava-test-runner /lava-11826833/0
11146 09:34:34.339301 Test shell timeout: 10s (minimum of the action and connection timeout)
11147 09:34:34.345190 /lava-11826833/bin/lava-test-runner /lava-11826833/0
11148 09:34:34.370355 + export TESTRUN_ID=0_igt-kms-medi<8>[ 20.542861] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 11826833_1.5.2.3.1>
11149 09:34:34.371301 Received signal: <STARTRUN> 0_igt-kms-mediatek 11826833_1.5.2.3.1
11150 09:34:34.371774 Starting test lava.0_igt-kms-mediatek (11826833_1.5.2.3.1)
11151 09:34:34.372232 Skipping test definition patterns.
11152 09:34:34.374122 atek
11153 09:34:34.377324 + cd /lava-11826833/0/tests/0_igt-kms-mediatek
11154 09:34:34.377899 + cat uuid
11155 09:34:34.380264 + UUID=11826833_1.5.2.3.1
11156 09:34:34.380734 + set +x
11157 09:34:34.393897 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion<8>[ 20.567422] <LAVA_SIGNAL_TESTSET START core_auth>
11158 09:34:34.394762 Received signal: <TESTSET> START core_auth
11159 09:34:34.395180 Starting test_set core_auth
11160 09:34:34.407542 core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11161 09:34:34.410068 <14>[ 20.585269] [IGT] core_auth: executing
11162 09:34:34.420134 IGT-Version: 1.2<14>[ 20.589623] [IGT] core_auth: starting subtest getclient-simple
11163 09:34:34.426735 7.1-g621c2d3 (aa<14>[ 20.597489] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11164 09:34:34.433410 rch64) (Linux: 6<14>[ 20.605571] [IGT] core_auth: exiting, ret=0
11165 09:34:34.436251 .1.58-cip7 aarch64)
11166 09:34:34.439902 Starting subtest: getclient-simple
11167 09:34:34.446230 Opened <8>[ 20.616636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11168 09:34:34.447100 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11170 09:34:34.449739 device: /dev/dri/card0
11171 09:34:34.452701 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11172 09:34:34.463899 <14>[ 20.637037] [IGT] core_auth: executing
11173 09:34:34.470741 IGT-Version: 1.2<14>[ 20.641378] [IGT] core_auth: starting subtest getclient-master-drop
11174 09:34:34.480467 7.1-g621c2d3 (aa<14>[ 20.649400] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11175 09:34:34.486566 rch64) (Linux: 6<14>[ 20.658156] [IGT] core_auth: exiting, ret=0
11176 09:34:34.487133 .1.58-cip7 aarch64)
11177 09:34:34.490089 Starting subtest: getclient-master-drop
11178 09:34:34.500485 Opened device: /de<8>[ 20.669914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11179 09:34:34.501059 v/dri/card0
11180 09:34:34.501720 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11182 09:34:34.506514 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11183 09:34:34.517778 <14>[ 20.690636] [IGT] core_auth: executing
11184 09:34:34.524026 IGT-Version: 1.2<14>[ 20.695035] [IGT] core_auth: starting subtest basic-auth
11185 09:34:34.530361 7.1-g621c2d3 (aa<14>[ 20.702020] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11186 09:34:34.536928 rch64) (Linux: 6<14>[ 20.709822] [IGT] core_auth: exiting, ret=0
11187 09:34:34.540401 .1.58-cip7 aarch64)
11188 09:34:34.540862 Opened device: /dev/dri/card0
11189 09:34:34.543831 Starting subtest: basic-auth
11190 09:34:34.554092 [1mSubtest ba<8>[ 20.723466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11191 09:34:34.554964 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11193 09:34:34.557050 sic-auth: SUCCESS (0.000s)[0m
11194 09:34:34.572613 <14>[ 20.745905] [IGT] core_auth: executing
11195 09:34:34.579753 IGT-Version: 1.2<14>[ 20.750428] [IGT] core_auth: starting subtest many-magics
11196 09:34:34.582768 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11197 09:34:34.585668 Opened device: /dev/dri/card0
11198 09:34:34.592392 Starting sub<14>[ 20.764270] [IGT] core_auth: finished subtest many-magics, SUCCESS
11199 09:34:34.598560 test: many-magic<14>[ 20.772291] [IGT] core_auth: exiting, ret=0
11200 09:34:34.598987 s
11201 09:34:34.602136 Reopening device failed after 1020 opens
11202 09:34:34.612296 [1mSubtest many-ma<8>[ 20.783278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11203 09:34:34.612991 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11205 09:34:34.615258 gics: SUCCESS (0.007s)[0m
11206 09:34:34.618292 <8>[ 20.792367] <LAVA_SIGNAL_TESTSET STOP>
11207 09:34:34.618975 Received signal: <TESTSET> STOP
11208 09:34:34.619342 Closing test_set core_auth
11209 09:34:34.660686 <14>[ 20.833831] [IGT] core_getclient: executing
11210 09:34:34.666767 IGT-Version: 1.2<14>[ 20.838873] [IGT] core_getclient: exiting, ret=0
11211 09:34:34.671324 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11212 09:34:34.680230 Opened device: /dev/dri/car<8>[ 20.851084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11213 09:34:34.680800 d0
11214 09:34:34.681452 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11216 09:34:34.683588 SUCCESS (0.006s)
11217 09:34:34.720317 <14>[ 20.893739] [IGT] core_getstats: executing
11218 09:34:34.726704 IGT-Version: 1.2<14>[ 20.898514] [IGT] core_getstats: exiting, ret=0
11219 09:34:34.730404 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11220 09:34:34.739934 Opened devi<8>[ 20.909365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11221 09:34:34.740483 ce: /dev/dri/card0
11222 09:34:34.741121 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11224 09:34:34.743084 SUCCESS (0.006s)
11225 09:34:34.788008 <14>[ 20.961264] [IGT] core_getversion: executing
11226 09:34:34.794450 IGT-Version: 1.2<14>[ 20.966564] [IGT] core_getversion: exiting, ret=0
11227 09:34:34.798362 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11228 09:34:34.807663 Opened devi<8>[ 20.977852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11229 09:34:34.808270 ce: /dev/dri/card0
11230 09:34:34.808928 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11232 09:34:34.810499 SUCCESS (0.006s)
11233 09:34:34.848387 <14>[ 21.021588] [IGT] core_setmaster_vs_auth: executing
11234 09:34:34.855066 IGT-Version: 1.2<14>[ 21.027363] [IGT] core_setmaster_vs_auth: exiting, ret=0
11235 09:34:34.861286 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11236 09:34:34.867651 Opened devi<8>[ 21.039655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11237 09:34:34.868447 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11239 09:34:34.871281 ce: /dev/dri/card0
11240 09:34:34.871786 SUCCESS (0.007s)
11241 09:34:34.889729 <8>[ 21.063342] <LAVA_SIGNAL_TESTSET START drm_read>
11242 09:34:34.890550 Received signal: <TESTSET> START drm_read
11243 09:34:34.890946 Starting test_set drm_read
11244 09:34:34.916950 <14>[ 21.090429] [IGT] drm_read: executing
11245 09:34:34.923696 IGT-Version: 1.2<14>[ 21.095097] [IGT] drm_read: exiting, ret=77
11246 09:34:34.926887 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11247 09:34:34.930378 Opened device: /dev/dri/card0
11248 09:34:34.939890 No KMS driver or no outputs,<8>[ 21.110173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11249 09:34:34.940479 pipes: 8, outputs: 0
11250 09:34:34.941130 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11252 09:34:34.946584 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11253 09:34:34.959255 <14>[ 21.132799] [IGT] drm_read: executing
11254 09:34:34.965643 IGT-Version: 1.2<14>[ 21.137254] [IGT] drm_read: exiting, ret=77
11255 09:34:34.969418 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11256 09:34:34.975588 Opened devi<8>[ 21.148018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11257 09:34:34.976367 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11259 09:34:34.979110 ce: /dev/dri/card0
11260 09:34:34.982679 No KMS driver or no outputs, pipes: 8, outputs: 0
11261 09:34:34.985545 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11262 09:34:34.993189 <14>[ 21.166611] [IGT] drm_read: executing
11263 09:34:34.999683 IGT-Version: 1.2<14>[ 21.171140] [IGT] drm_read: exiting, ret=77
11264 09:34:35.003142 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11265 09:34:35.009350 Opened devi<8>[ 21.181753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11266 09:34:35.010030 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11268 09:34:35.012682 ce: /dev/dri/card0
11269 09:34:35.016029 No KMS driver or no outputs, pipes: 8, outputs: 0
11270 09:34:35.019589 [1mSubtest empty-block: SKIP (0.000s)[0m
11271 09:34:35.028283 <14>[ 21.201544] [IGT] drm_read: executing
11272 09:34:35.034642 IGT-Version: 1.2<14>[ 21.206008] [IGT] drm_read: exiting, ret=77
11273 09:34:35.038152 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11274 09:34:35.044563 Opened devi<8>[ 21.216749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11275 09:34:35.045404 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11277 09:34:35.047591 ce: /dev/dri/card0
11278 09:34:35.051184 No KMS driver or no outputs, pipes: 8, outputs: 0
11279 09:34:35.057636 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11280 09:34:35.072213 <14>[ 21.245695] [IGT] drm_read: executing
11281 09:34:35.079284 IGT-Version: 1.2<14>[ 21.250576] [IGT] drm_read: exiting, ret=77
11282 09:34:35.082293 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11283 09:34:35.091764 Opened device: /dev/dri/car<8>[ 21.261429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11284 09:34:35.092318 d0
11285 09:34:35.092954 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11287 09:34:35.095340 No KMS driver or no outputs, pipes: 8, outputs: 0
11288 09:34:35.101597 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11289 09:34:35.118556 <14>[ 21.292057] [IGT] drm_read: executing
11290 09:34:35.125474 IGT-Version: 1.2<14>[ 21.296821] [IGT] drm_read: exiting, ret=77
11291 09:34:35.128429 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11292 09:34:35.138572 Opened devi<8>[ 21.307832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11293 09:34:35.139137 ce: /dev/dri/card0
11294 09:34:35.139841 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11296 09:34:35.144860 No KMS driver or no outputs, pipes: 8, outputs: 0
11297 09:34:35.148330 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11298 09:34:35.156737 <14>[ 21.330240] [IGT] drm_read: executing
11299 09:34:35.163395 IGT-Version: 1.2<14>[ 21.334690] [IGT] drm_read: exiting, ret=77
11300 09:34:35.166460 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11301 09:34:35.174107 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11303 09:34:35.176204 Opened devi<8>[ 21.345133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11304 09:34:35.179551 ce: /dev/dri/car<8>[ 21.354789] <LAVA_SIGNAL_TESTSET STOP>
11305 09:34:35.180207 d0
11306 09:34:35.180846 Received signal: <TESTSET> STOP
11307 09:34:35.181210 Closing test_set drm_read
11308 09:34:35.186055 No KMS driver or no outputs, pipes: 8, outputs: 0
11309 09:34:35.189292 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11310 09:34:35.201214 <8>[ 21.374495] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11311 09:34:35.201887 Received signal: <TESTSET> START kms_addfb_basic
11312 09:34:35.202238 Starting test_set kms_addfb_basic
11313 09:34:35.218352 <14>[ 21.391899] [IGT] kms_addfb_basic: executing
11314 09:34:35.231851 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch<14>[ 21.400995] [IGT] kms_addfb_basic: starting subtest unused-handle
11315 09:34:35.232616 64)
11316 09:34:35.238359 Opened devi<14>[ 21.408876] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11317 09:34:35.241559 ce: /dev/dri/card0
11318 09:34:35.244812 Starting subtest: unused-handle
11319 09:34:35.248101 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11320 09:34:35.255159 Test requi<14>[ 21.425735] [IGT] kms_addfb_basic: exiting, ret=0
11321 09:34:35.261377 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11322 09:34:35.268145 Test re<8>[ 21.438755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11323 09:34:35.268885 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11325 09:34:35.271470 quirement: is_i915_device(fd)
11326 09:34:35.277656 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11327 09:34:35.281520 Test requirement: is_i915_device(fd)
11328 09:34:35.287624 No KMS d<14>[ 21.459244] [IGT] kms_addfb_basic: executing
11329 09:34:35.290943 river or no outputs, pipes: 8, outputs: 0
11330 09:34:35.297469 IGT-Version: 1.27.1-g<14>[ 21.469036] [IGT] kms_addfb_basic: starting subtest unused-pitches
11331 09:34:35.307399 621c2d3 (aarch64<14>[ 21.477064] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11332 09:34:35.310590 ) (Linux: 6.1.58-cip7 aarch64)
11333 09:34:35.314484 Opened device: /dev/dri/card0
11334 09:34:35.315006 Starting subtest: unused-pitches
11335 09:34:35.321387 <14>[ 21.493695] [IGT] kms_addfb_basic: exiting, ret=0
11336 09:34:35.321917
11337 09:34:35.324124 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11338 09:34:35.334079 Test requirement not met in f<8>[ 21.504728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11339 09:34:35.334768 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11341 09:34:35.340641 unction igt_require_i915, file ../lib/drmtest.c:720:
11342 09:34:35.343799 Test requirement: is_i915_device(fd)
11343 09:34:35.354214 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 21.525578] [IGT] kms_addfb_basic: executing
11344 09:34:35.354739 rmtest.c:720:
11345 09:34:35.357412 Test requirement: is_i915_device(fd)
11346 09:34:35.363710 No KMS driv<14>[ 21.535980] [IGT] kms_addfb_basic: starting subtest unused-offsets
11347 09:34:35.373878 er or no outputs<14>[ 21.543881] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11348 09:34:35.376770 , pipes: 8, outputs: 0
11349 09:34:35.383392 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11350 09:34:35.386677 Ope<14>[ 21.560511] [IGT] kms_addfb_basic: exiting, ret=0
11351 09:34:35.390477 ned device: /dev/dri/card0
11352 09:34:35.393771 Starting subtest: unused-offsets
11353 09:34:35.399701 [1mSubtest unused<8>[ 21.572716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11354 09:34:35.400574 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11356 09:34:35.403117 -offsets: SUCCESS (0.000s)[0m
11357 09:34:35.413143 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11358 09:34:35.416445 Test requirement: is_i915_device(fd)
11359 09:34:35.420020 Test re<14>[ 21.592751] [IGT] kms_addfb_basic: executing
11360 09:34:35.432599 quirement not met in function igt_require_i915, file ../lib/drmt<14>[ 21.603006] [IGT] kms_addfb_basic: starting subtest unused-modifier
11361 09:34:35.433135 est.c:720:
11362 09:34:35.439970 Test<14>[ 21.610917] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11363 09:34:35.443341 requirement: is_i915_device(fd)
11364 09:34:35.449498 No KMS driver or no outputs, pipes: 8, outputs: 0
11365 09:34:35.455895 IGT-Version<14>[ 21.627795] [IGT] kms_addfb_basic: exiting, ret=0
11366 09:34:35.459422 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11367 09:34:35.469572 Opened device: /dev/dr<8>[ 21.638931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11368 09:34:35.470134 i/card0
11369 09:34:35.470783 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11371 09:34:35.472494 Starting subtest: unused-modifier
11372 09:34:35.476407 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11373 09:34:35.486462 Test requirement not met in function igt_require_<14>[ 21.658863] [IGT] kms_addfb_basic: executing
11374 09:34:35.489231 i915, file ../lib/drmtest.c:720:
11375 09:34:35.499189 Test requirement: is_i915_devi<14>[ 21.668631] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11376 09:34:35.499789 ce(fd)
11377 09:34:35.508785 Test req<14>[ 21.677014] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11378 09:34:35.515622 uirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11379 09:34:35.521945 Test requirement: is_<14>[ 21.693900] [IGT] kms_addfb_basic: exiting, ret=77
11380 09:34:35.522519 i915_device(fd)
11381 09:34:35.525413 No KMS driver or no outputs, pipes: 8, outputs: 0
11382 09:34:35.538577 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<8>[ 21.708864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11383 09:34:35.539433 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11385 09:34:35.542054 x: 6.1.58-cip7 aarch64)
11386 09:34:35.542508 Opened device: /dev/dri/card0
11387 09:34:35.545242 Starting subtest: clobberred-modifier
11388 09:34:35.558513 Test requirement not met in function igt_require_i915, file ../li<14>[ 21.729840] [IGT] kms_addfb_basic: executing
11389 09:34:35.559084 b/drmtest.c:720:
11390 09:34:35.562262 Test requirement: is_i915_device(fd)
11391 09:34:35.571370 [1mSubt<14>[ 21.739581] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11392 09:34:35.578820 est clobberred-m<14>[ 21.748537] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11393 09:34:35.581583 odifier: SKIP (0.000s)[0m
11394 09:34:35.595043 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 21.766333] [IGT] kms_addfb_basic: exiting, ret=77
11395 09:34:35.595613 rmtest.c:720:
11396 09:34:35.597870 Test requirement: is_i915_device(fd)
11397 09:34:35.607630 Test requirement not met in<8>[ 21.777416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11398 09:34:35.608511 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11400 09:34:35.614530 function igt_require_i915, file ../lib/drmtest.c:720:
11401 09:34:35.617657 Test requirement: is_i915_device(fd)
11402 09:34:35.621202 No KMS driver or no outputs, pipes: 8, outputs: 0
11403 09:34:35.624109 <14>[ 21.798277] [IGT] kms_addfb_basic: executing
11404 09:34:35.624579
11405 09:34:35.637394 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarc<14>[ 21.808172] [IGT] kms_addfb_basic: starting subtest legacy-format
11406 09:34:35.637821 h64)
11407 09:34:35.640913 Opened device: /dev/dri/card0
11408 09:34:35.650965 Starting subtest: invalid-smem-bo-on-discre<14>[ 21.822739] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11409 09:34:35.651482 te
11410 09:34:35.660676 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:715:
11411 09:34:35.663997 Test req<14>[ 21.838100] [IGT] kms_addfb_basic: exiting, ret=0
11412 09:34:35.667131 uirement: is_intel_device(fd)
11413 09:34:35.680130 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.<8>[ 21.849524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11414 09:34:35.680690 000s)[0m
11415 09:34:35.681353 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11417 09:34:35.686768 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11418 09:34:35.690142 Test requirement: is_i915_device(fd)
11419 09:34:35.696711 Test requirement not met in <14>[ 21.870401] [IGT] kms_addfb_basic: executing
11420 09:34:35.703377 function igt_require_i915, file ../lib/drmtest.c:720:
11421 09:34:35.709752 Test requirement: is_i915<14>[ 21.882864] [IGT] kms_addfb_basic: starting subtest no-handle
11422 09:34:35.712966 _device(fd)
11423 09:34:35.720261 No <14>[ 21.889419] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11424 09:34:35.722582 KMS driver or no outputs, pipes: 8, outputs: 0
11425 09:34:35.729799 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.903639] [IGT] kms_addfb_basic: exiting, ret=0
11426 09:34:35.732730 rch64) (Linux: 6.1.58-cip7 aarch64)
11427 09:34:35.735966 Opened device: /dev/dri/card0
11428 09:34:35.746024 Starting sub<8>[ 21.916099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11429 09:34:35.746541 test: legacy-format
11430 09:34:35.747138 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11432 09:34:35.753168 Successfully fuzzed 10000 {bpp, depth} variations
11433 09:34:35.756326 [1mSubtest legacy-format: SUCCESS (0.007s)[0m
11434 09:34:35.762389 Test requirement not met in function ig<14>[ 21.936105] [IGT] kms_addfb_basic: executing
11435 09:34:35.766062 t_require_i915, file ../lib/drmtest.c:720:
11436 09:34:35.776395 Test requirement: is_i915_device(fd)<14>[ 21.948371] [IGT] kms_addfb_basic: starting subtest basic
11437 09:34:35.776958
11438 09:34:35.785346 Test requireme<14>[ 21.954773] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11439 09:34:35.789173 nt not met in function igt_require_i915, file ../lib/drmtest.c:720:
11440 09:34:35.795396 Test requir<14>[ 21.968510] [IGT] kms_addfb_basic: exiting, ret=0
11441 09:34:35.798786 ement: is_i915_device(fd)
11442 09:34:35.802572 No KMS driver or no outputs, pipes: 8, outputs: 0
11443 09:34:35.811982 IGT-Version: 1.27.<8>[ 21.981622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11444 09:34:35.812806 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11446 09:34:35.814996 1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11447 09:34:35.818771 Opened device: /dev/dri/card0
11448 09:34:35.822006 Starting subtest: no-handle
11449 09:34:35.825006 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11450 09:34:35.828463 Test<14>[ 22.002514] [IGT] kms_addfb_basic: executing
11451 09:34:35.835517 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11452 09:34:35.842235 T<14>[ 22.014629] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11453 09:34:35.851840 est requirement:<14>[ 22.021349] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11454 09:34:35.852303 is_i915_device(fd)
11455 09:34:35.864942 Test requirement not met in function igt_require_i915, file<14>[ 22.035584] [IGT] kms_addfb_basic: exiting, ret=0
11456 09:34:35.865494 ../lib/drmtest.c:720:
11457 09:34:35.867857 Test requirement: is_i915_device(fd)
11458 09:34:35.878045 No KMS driver or n<8>[ 22.048519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11459 09:34:35.878730 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11461 09:34:35.881244 o outputs, pipes: 8, outputs: 0
11462 09:34:35.884476 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11463 09:34:35.895248 Opened device: /dev/dri/ca<14>[ 22.066658] [IGT] kms_addfb_basic: executing
11464 09:34:35.895856 rd0
11465 09:34:35.896195 Starting subtest: basic
11466 09:34:35.897781 [1mSubtest basic: SUCCESS (0.000s)[0m
11467 09:34:35.907646 Test requ<14>[ 22.077661] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11468 09:34:35.914120 irement not met <14>[ 22.084877] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11469 09:34:35.921087 in function igt_require_i915, file ../lib/drmtest.c:720:
11470 09:34:35.927302 Test requirement: is_i<14>[ 22.099304] [IGT] kms_addfb_basic: exiting, ret=0
11471 09:34:35.927797 915_device(fd)
11472 09:34:35.940604 Test requirement not met in function igt_require_i915, file ../l<8>[ 22.111107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11473 09:34:35.941356 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11475 09:34:35.943802 ib/drmtest.c:720:
11476 09:34:35.947468 Test requirement: is_i915_device(fd)
11477 09:34:35.950351 No KMS driver or no outputs, pipes: 8, outputs: 0
11478 09:34:35.957673 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11479 09:34:35.960277 Opened device: /dev/dri/card0
11480 09:34:35.960695 Starting subtest: bad-pitch-0
11481 09:34:35.970755 [1mSubtest bad-pitch-0: SUCCESS <14>[ 22.141672] [IGT] kms_addfb_basic: executing
11482 09:34:35.971275 (0.000s)[0m
11483 09:34:35.977794 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11484 09:34:35.984311 <14>[ 22.154556] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11485 09:34:35.984827
11486 09:34:35.993587 Test requiremen<14>[ 22.162344] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11487 09:34:35.994106 t: is_i915_device(fd)
11488 09:34:36.003187 Test requirement not met in function igt_require_i915, fi<14>[ 22.177243] [IGT] kms_addfb_basic: exiting, ret=0
11489 09:34:36.006462 le ../lib/drmtest.c:720:
11490 09:34:36.009756 Test requirement: is_i915_device(fd)
11491 09:34:36.016564 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11493 09:34:36.019551 No KMS driver or<8>[ 22.188771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11494 09:34:36.020047 no outputs, pipes: 8, outputs: 0
11495 09:34:36.026321 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11496 09:34:36.029842 Opened device: /dev/dri/card0
11497 09:34:36.036180 Starting subtest: bad-pit<14>[ 22.209363] [IGT] kms_addfb_basic: executing
11498 09:34:36.036673 ch-32
11499 09:34:36.042911 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11500 09:34:36.049706 Test requirement not met <14>[ 22.221786] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11501 09:34:36.059714 in function igt_<14>[ 22.228884] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11502 09:34:36.062719 require_i915, file ../lib/drmtest.c:720:
11503 09:34:36.065817 Test requirement: is_i915_device(fd)
11504 09:34:36.069456 <14>[ 22.243521] [IGT] kms_addfb_basic: exiting, ret=0
11505 09:34:36.086170 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 22.256038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11506 09:34:36.086861 :
11507 09:34:36.087524 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11509 09:34:36.089084 Test requirement: is_i915_device(fd)
11510 09:34:36.092299 No KMS driver or no outputs, pipes: 8, outputs: 0
11511 09:34:36.099884 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11512 09:34:36.102734 Opened device: /dev/dri/card0
11513 09:34:36.105468 Starting subtest: bad-pitch-63
11514 09:34:36.112753 [1mSubtest bad-pitch-63: SUCCES<14>[ 22.285224] [IGT] kms_addfb_basic: executing
11515 09:34:36.113355 S (0.000s)[0m
11516 09:34:36.125194 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 22.297684] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11517 09:34:36.125755 :
11518 09:34:36.135716 Test requirem<14>[ 22.305380] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11519 09:34:36.138690 ent: is_i915_device(fd)
11520 09:34:36.148734 Test requirement not met in function igt_require_i915, <14>[ 22.320348] [IGT] kms_addfb_basic: exiting, ret=0
11521 09:34:36.149332 file ../lib/drmtest.c:720:
11522 09:34:36.151864 Test requirement: is_i915_device(fd)
11523 09:34:36.161883 No KMS driver <8>[ 22.331581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11524 09:34:36.162726 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11526 09:34:36.164970 or no outputs, pipes: 8, outputs: 0
11527 09:34:36.171649 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11528 09:34:36.172256 Opened device: /dev/dri/card0
11529 09:34:36.178467 Startin<14>[ 22.352383] [IGT] kms_addfb_basic: executing
11530 09:34:36.181727 g subtest: bad-pitch-128
11531 09:34:36.184579 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11532 09:34:36.191363 Test <14>[ 22.363611] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11533 09:34:36.201314 requirement not <14>[ 22.370725] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11534 09:34:36.205073 met in function igt_require_i915, file ../lib/drmtest.c:720:
11535 09:34:36.211349 Test requirement: <14>[ 22.385246] [IGT] kms_addfb_basic: exiting, ret=0
11536 09:34:36.215180 is_i915_device(fd)
11537 09:34:36.221305 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11538 09:34:36.231015 Test requ<8>[ 22.400812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11539 09:34:36.231572 irement: is_i915_device(fd)
11540 09:34:36.232264 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11542 09:34:36.237777 No KMS driver or no outputs, pipes: 8, outputs: 0
11543 09:34:36.244421 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 22.419319] [IGT] kms_addfb_basic: executing
11544 09:34:36.247460 .1.58-cip7 aarch64)
11545 09:34:36.250557 Opened device: /dev/dri/card0
11546 09:34:36.257661 Starting subtest: bad-pitch-<14>[ 22.430337] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11547 09:34:36.260967 256
11548 09:34:36.267338 [1mSubtest<14>[ 22.437597] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11549 09:34:36.270567 bad-pitch-256: SUCCESS (0.000s)[0m
11550 09:34:36.280590 Test requirement not met in function igt_r<14>[ 22.452014] [IGT] kms_addfb_basic: exiting, ret=0
11551 09:34:36.283889 equire_i915, file ../lib/drmtest.c:720:
11552 09:34:36.286918 Test requirement: is_i915_device(fd)
11553 09:34:36.293562 T<8>[ 22.463892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11554 09:34:36.294416 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11556 09:34:36.300529 est requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11557 09:34:36.303490 Test requirement: is_i915_device(fd)
11558 09:34:36.313346 No KMS driver or no outputs, pipes: 8, o<14>[ 22.485682] [IGT] kms_addfb_basic: executing
11559 09:34:36.313912 utputs: 0
11560 09:34:36.320355 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11561 09:34:36.326813 <14>[ 22.497274] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11562 09:34:36.333350 Opened device: /<14>[ 22.504664] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11563 09:34:36.336695 dev/dri/card0
11564 09:34:36.339581 Starting subtest: bad-pitch-1024
11565 09:34:36.346606 [1mSubtest bad-pitch-1024: SUC<14>[ 22.519156] [IGT] kms_addfb_basic: exiting, ret=0
11566 09:34:36.349872 CESS (0.000s)[0m
11567 09:34:36.356063 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11568 09:34:36.363530 Test requi<8>[ 22.534594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11569 09:34:36.364443 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11571 09:34:36.366350 rement: is_i915_device(fd)
11572 09:34:36.372567 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11573 09:34:36.376139 Test requirement: is_i915_device(fd)
11574 09:34:36.382924 No KMS driver or no outputs, pipes: 8, outputs: 0
11575 09:34:36.386106 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11576 09:34:36.392393 Ope<14>[ 22.564924] [IGT] kms_addfb_basic: executing
11577 09:34:36.395604 ned device: /dev/dri/card0
11578 09:34:36.396115 Starting subtest: bad-pitch-999
11579 09:34:36.402409 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11580 09:34:36.408846 Te<14>[ 22.580099] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11581 09:34:36.418848 st requirement n<14>[ 22.587480] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11582 09:34:36.422070 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11583 09:34:36.428764 <14>[ 22.601060] [IGT] kms_addfb_basic: exiting, ret=0
11584 09:34:36.429180
11585 09:34:36.431666 Test requirement: is_i915_device(fd)
11586 09:34:36.444878 Test requirement not met in function igt_require_i915, file ../lib/drmtes<8>[ 22.616416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11587 09:34:36.445652 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11589 09:34:36.448317 t.c:720:
11590 09:34:36.451633 Test requirement: is_i915_device(fd)
11591 09:34:36.454799 No KMS driver or no outputs, pipes: 8, outputs: 0
11592 09:34:36.464564 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aa<14>[ 22.637505] [IGT] kms_addfb_basic: executing
11593 09:34:36.465087 rch64)
11594 09:34:36.468282 Opened device: /dev/dri/card0
11595 09:34:36.471703 Starting subtest: bad-pitch-65536
11596 09:34:36.481588 [1mSubtest bad-pitch-65536: SUCCESS (<14>[ 22.651613] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11597 09:34:36.482115 0.000s)[0m
11598 09:34:36.491322 Tes<14>[ 22.659779] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11599 09:34:36.498279 t requirement not met in function igt_require_i9<14>[ 22.672650] [IGT] kms_addfb_basic: exiting, ret=0
11600 09:34:36.501416 15, file ../lib/drmtest.c:720:
11601 09:34:36.504673 Test requirement: is_i915_device(fd)
11602 09:34:36.514606 Test requi<8>[ 22.684493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11603 09:34:36.515458 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11605 09:34:36.521440 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11606 09:34:36.524804 Test requirement: is_i915_device(fd)
11607 09:34:36.530967 No KMS driver or <14>[ 22.702883] [IGT] kms_addfb_basic: executing
11608 09:34:36.531518 no outputs, pipes: 8, outputs: 0
11609 09:34:36.544437 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aar<14>[ 22.716011] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11610 09:34:36.545013 ch64)
11611 09:34:36.554124 Opened de<14>[ 22.723352] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11612 09:34:36.557742 vice: /dev/dri/card0
11613 09:34:36.564156 Starting subtest: invalid-<14>[ 22.736524] [IGT] kms_addfb_basic: exiting, ret=0
11614 09:34:36.564717 get-prop-any
11615 09:34:36.570355 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11616 09:34:36.577299 Test requi<8>[ 22.747660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11617 09:34:36.578148 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11619 09:34:36.583765 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11620 09:34:36.586926 Test requirement: is_i915_device(fd)
11621 09:34:36.596642 Test requirement not met in function igt_require_<14>[ 22.769173] [IGT] kms_addfb_basic: executing
11622 09:34:36.600277 i915, file ../lib/drmtest.c:720:
11623 09:34:36.603148 Test requirement: is_i915_device(fd)
11624 09:34:36.613229 No KMS driver or no outputs, pipes: 8, o<14>[ 22.783503] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11625 09:34:36.613760 utputs: 0
11626 09:34:36.623282 IGT-V<14>[ 22.791527] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11627 09:34:36.629685 ersion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58<14>[ 22.804306] [IGT] kms_addfb_basic: exiting, ret=0
11628 09:34:36.633204 -cip7 aarch64)
11629 09:34:36.636960 Opened device: /dev/dri/card0
11630 09:34:36.640315 Starting subtest: invalid-get-prop
11631 09:34:36.646259 [1mSubtest i<8>[ 22.816674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11632 09:34:36.647057 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11634 09:34:36.649322 nvalid-get-prop: SUCCESS (0.000s)[0m
11635 09:34:36.656170 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11636 09:34:36.659448 Test requirement: is_i915_device(fd)
11637 09:34:36.666132 <14>[ 22.838321] [IGT] kms_addfb_basic: executing
11638 09:34:36.672580 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11639 09:34:36.675829 Test requirement: is_i915_device(fd)
11640 09:34:36.682805 No KMS <14>[ 22.854174] [IGT] kms_addfb_basic: starting subtest master-rmfb
11641 09:34:36.692761 driver or no out<14>[ 22.861510] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11642 09:34:36.693309 puts, pipes: 8, outputs: 0
11643 09:34:36.699325 IGT-<14>[ 22.871888] [IGT] kms_addfb_basic: exiting, ret=0
11644 09:34:36.705616 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11645 09:34:36.712125 Opened device: <8>[ 22.883373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11646 09:34:36.712872 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11648 09:34:36.715388 /dev/dri/card0
11649 09:34:36.718882 Starting subtest: invalid-set-prop-any
11650 09:34:36.722445 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11651 09:34:36.731709 Test requirement not met in function igt_require<14>[ 22.904444] [IGT] kms_addfb_basic: executing
11652 09:34:36.734979 _i915, file ../lib/drmtest.c:720:
11653 09:34:36.738957 Test requirement: is_i915_device(fd)
11654 09:34:36.751485 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 22.922333] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11655 09:34:36.752075 est.c:720:
11656 09:34:36.761754 Test<14>[ 22.930176] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11657 09:34:36.768246 requirement: is<14>[ 22.939854] [IGT] kms_addfb_basic: exiting, ret=0
11658 09:34:36.768731 _i915_device(fd)
11659 09:34:36.774903 No KMS driver or no outputs, pipes: 8, outputs: 0
11660 09:34:36.781336 IGT-Version<8>[ 22.952642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11661 09:34:36.782181 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11663 09:34:36.788560 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11664 09:34:36.791400 Opened device: /dev/dri/card0
11665 09:34:36.794293 Starting subtest: invalid-set-prop
11666 09:34:36.798060 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11667 09:34:36.808042 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.982938] [IGT] kms_addfb_basic: executing
11668 09:34:36.811369 0:
11669 09:34:36.814387 Test requirement: is_i915_device(fd)
11670 09:34:36.821471 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11671 09:34:36.831044 Test requirement: is_i915_device(fd<14>[ 23.001468] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11672 09:34:36.831666 )
11673 09:34:36.834231 No KMS driver or no outputs, pipes: 8, outputs: 0
11674 09:34:36.844472 IGT-Version: 1.27.1-g621c2<14>[ 23.015466] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11675 09:34:36.850529 d3 (aarch64) (Li<14>[ 23.023722] [IGT] kms_addfb_basic: exiting, ret=98
11676 09:34:36.854077 nux: 6.1.58-cip7 aarch64)
11677 09:34:36.857815 Opened device: /dev/dri/card0
11678 09:34:36.867491 Starting subtest: mast<8>[ 23.035831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11679 09:34:36.868142 er-rmfb
11680 09:34:36.869066 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11682 09:34:36.870695 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11683 09:34:36.877181 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11684 09:34:36.883838 Test <14>[ 23.056785] [IGT] kms_addfb_basic: executing
11685 09:34:36.887016 requirement: is_i915_device(fd)
11686 09:34:36.893565 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11687 09:34:36.900349 Test requirement: is_i915_de<14>[ 23.074251] [IGT] kms_addfb_basic: exiting, ret=77
11688 09:34:36.900768 vice(fd)
11689 09:34:36.906918 No KMS driver or no outputs, pipes: 8, outputs: 0
11690 09:34:36.916602 IGT-Version: 1.27.1<8>[ 23.085998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11691 09:34:36.917287 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11693 09:34:36.920109 -g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11694 09:34:36.923391 Opened device: /dev/dri/card0
11695 09:34:36.926834 Starting subtest: addfb25-modifier-no-flag
11696 09:34:36.933249 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11697 09:34:36.943332 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 23.116911] [IGT] kms_addfb_basic: executing
11698 09:34:36.943873 est.c:720:
11699 09:34:36.946425 Test requirement: is_i915_device(fd)
11700 09:34:36.956052 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11701 09:34:36.960139 Test requirement: is_i915_device(fd)
11702 09:34:36.962759 No KM<14>[ 23.135828] [IGT] kms_addfb_basic: exiting, ret=77
11703 09:34:36.966225 S driver or no outputs, pipes: 8, outputs: 0
11704 09:34:36.980134 IGT-Version: 1.27.1-g621c2d3 (aarc<8>[ 23.148099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11705 09:34:36.980950 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11707 09:34:36.982882 h64) (Linux: 6.1.58-cip7 aarch64)
11708 09:34:36.983292 Opened device: /dev/dri/card0
11709 09:34:36.989440 Starting subtest: addfb25-bad-modifier
11710 09:34:36.995767 (kms_addfb_basic:438) CRITICAL: Test assertion failure<14>[ 23.169746] [IGT] kms_addfb_basic: executing
11711 09:34:37.002449 function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11712 09:34:37.015978 (kms_addfb_basic:438) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) |<14>[ 23.188311] [IGT] kms_addfb_basic: exiting, ret=77
11713 09:34:37.025639 ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11714 09:34:37.035521 (km<8>[ 23.204191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11715 09:34:37.036435 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11717 09:34:37.038917 s_addfb_basic:438) CRITICAL: error: 0 != -1
11718 09:34:37.039468 Stack trace:
11719 09:34:37.045196 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11720 09:34:37.045754 #1 [<unknown>+0xb64a47e0]
11721 09:34:37.051783 #2 [<unknown>+0xb64a6<14>[ 23.226167] [IGT] kms_addfb_basic: executing
11722 09:34:37.055414 278]
11723 09:34:37.056029 #3 [<unknown>+0xb64a167c]
11724 09:34:37.058702 #4 [__libc_start_main+0xe8]
11725 09:34:37.061881 #5 [<unknown>+0xb64a16b4]
11726 09:34:37.064859 #6 [<unknown>+0xb64a16b4]
11727 09:34:37.071873 Subtest addfb25-bad-<14>[ 23.244327] [IGT] kms_addfb_basic: exiting, ret=77
11728 09:34:37.072332 modifier failed.
11729 09:34:37.075340 **** DEBUG ****
11730 09:34:37.084968 (kms_addfb_basic:438) ioctl_w<8>[ 23.254656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11731 09:34:37.085822 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11733 09:34:37.087981 rappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11734 09:34:37.101430 (kms_addfb_basic:438) CRITICAL: Test assertion failure functio<14>[ 23.272966] [IGT] kms_addfb_basic: executing
11735 09:34:37.105021 n addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11736 09:34:37.117563 (kms_addfb_basic:438) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8<14>[ 23.290665] [IGT] kms_addfb_basic: exiting, ret=77
11737 09:34:37.131056 )+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cm<8>[ 23.301779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11738 09:34:37.131873 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11740 09:34:37.134877 d2)))) << ((0+8)+8)))), (&f)) == -1
11741 09:34:37.140888 (kms_addfb_basic:438) CRITICAL: error: 0 != -1
11742 09:34:37.144443 (kms_addfb_basic:438) igt_core-INFO: Stack trace:
11743 09:34:37.150937 (kms_addfb_basic:438) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11744 09:34:37.161128 (kms_addfb_basic:438) igt_core-INF<14>[ 23.333131] [IGT] kms_addfb_basic: executing
11745 09:34:37.161685 O: #1 [<unknown>+0xb64a47e0]
11746 09:34:37.167352 (kms_addfb_basic:438) igt_core-INFO: #2 [<unknown>+0xb64a6278]
11747 09:34:37.177294 (kms_addfb_basic:438) igt_core-INFO: #3 [<unknown>+0xb64a167<14>[ 23.351070] [IGT] kms_addfb_basic: exiting, ret=77
11748 09:34:37.180224 c]
11749 09:34:37.183662 (kms_addfb_basic:438) igt_core-INFO: #4 [__libc_start_main+0xe8]
11750 09:34:37.196875 (kms_addfb_basic:438) igt_core-INFO: #<8>[ 23.366379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11751 09:34:37.197377 5 [<unknown>+0xb64a16b4]
11752 09:34:37.197979 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11754 09:34:37.204051 (kms_addfb_basic:438) igt_core-INFO: #6 [<unknown>+0xb64a16b4]
11755 09:34:37.206659 **** END ****
11756 09:34:37.210100 [1mSubtest addfb25-bad-modifier: FAIL (0.006s)[0m
11757 09:34:37.216807 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11758 09:34:37.223505 Test requirement: is_i915_d<14>[ 23.396807] [IGT] kms_addfb_basic: executing
11759 09:34:37.227054 evice(fd)
11760 09:34:37.233261 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11761 09:34:37.236352 Test requirement: is_i915_device(fd)
11762 09:34:37.243206 No KMS driver or no outputs,<14>[ 23.416616] [IGT] kms_addfb_basic: exiting, ret=77
11763 09:34:37.246978 pipes: 8, outputs: 0
11764 09:34:37.256116 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip<8>[ 23.427813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11765 09:34:37.256965 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11767 09:34:37.259544 7 aarch64)
11768 09:34:37.263099 Opened device: /dev/dri/card0
11769 09:34:37.269552 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11770 09:34:37.276235 Test requirement: is_i915_device(f<14>[ 23.449096] [IGT] kms_addfb_basic: executing
11771 09:34:37.276702 d)
11772 09:34:37.282808 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11773 09:34:37.293062 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<14>[ 23.467428] [IGT] kms_addfb_basic: exiting, ret=77
11774 09:34:37.295873 :720:
11775 09:34:37.299301 Test requirement: is_i915_device(fd)
11776 09:34:37.302843 No KMS driver or no outputs, pipes: 8, outputs: 0
11777 09:34:37.309432 <8>[ 23.480054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11778 09:34:37.310247 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11780 09:34:37.315534 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11781 09:34:37.319803 Opened device: /dev/dri/card0
11782 09:34:37.325557 Test requirement not met in function igt_req<14>[ 23.499841] [IGT] kms_addfb_basic: executing
11783 09:34:37.329125 uire_i915, file ../lib/drmtest.c:720:
11784 09:34:37.332187 Test requirement: is_i915_device(fd)
11785 09:34:37.338718 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11786 09:34:37.345406 Test requirement not met in <14>[ 23.517318] [IGT] kms_addfb_basic: exiting, ret=77
11787 09:34:37.348502 function igt_require_i915, file ../lib/drmtest.c:720:
11788 09:34:37.358649 Test requ<8>[ 23.528931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11789 09:34:37.359206 irement: is_i915_device(fd)
11790 09:34:37.359863 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11792 09:34:37.365203 No KMS driver or no outputs, pipes: 8, outputs: 0
11793 09:34:37.371804 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 23.546582] [IGT] kms_addfb_basic: executing
11794 09:34:37.374829 .1.58-cip7 aarch64)
11795 09:34:37.378459 Opened device: /dev/dri/card0
11796 09:34:37.384690 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11797 09:34:37.391360 Test requ<14>[ 23.564064] [IGT] kms_addfb_basic: exiting, ret=77
11798 09:34:37.394806 irement: is_i915_device(fd)
11799 09:34:37.404502 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP<8>[ 23.575575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11800 09:34:37.405061 (0.000s)[0m
11801 09:34:37.405719 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11803 09:34:37.415017 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11804 09:34:37.417318 Test requirement: is_i915_device(fd)
11805 09:34:37.424088 No KMS driver or no outp<14>[ 23.596367] [IGT] kms_addfb_basic: executing
11806 09:34:37.424751 uts, pipes: 8, outputs: 0
11807 09:34:37.431549 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11808 09:34:37.433983 Opened device: /dev/dri/card0
11809 09:34:37.440676 Test requirement not met in funct<14>[ 23.614286] [IGT] kms_addfb_basic: exiting, ret=77
11810 09:34:37.447764 ion igt_require_i915, file ../lib/drmtest.c:720:
11811 09:34:37.457559 Test requirement: is_i915_devi<8>[ 23.627290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11812 09:34:37.458118 ce(fd)
11813 09:34:37.458770 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11815 09:34:37.463629 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11816 09:34:37.466954 Test requirement: is_i915_device(fd)
11817 09:34:37.470276 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11818 09:34:37.477241 No KMS driver or no outputs, pipes: 8, outputs: 0
11819 09:34:37.483646 IGT-Version: 1.27.1-g62<14>[ 23.656211] [IGT] kms_addfb_basic: executing
11820 09:34:37.487406 1c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11821 09:34:37.490343 Opened device: /dev/dri/card0
11822 09:34:37.496779 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11823 09:34:37.503345 Test requirement<14>[ 23.675545] [IGT] kms_addfb_basic: exiting, ret=77
11824 09:34:37.506264 : is_i915_device(fd)
11825 09:34:37.516326 Test requirement not met in function igt_require_i915, fil<8>[ 23.687672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11826 09:34:37.517073 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11828 09:34:37.520194 e ../lib/drmtest.c:720:
11829 09:34:37.523419 Test requirement: is_i915_device(fd)
11830 09:34:37.526788 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11831 09:34:37.532965 No KMS driver or no outputs, pipes: 8, outputs: 0
11832 09:34:37.536265 IGT-<14>[ 23.710422] [IGT] kms_addfb_basic: executing
11833 09:34:37.542631 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11834 09:34:37.546111 Opened device: /dev/dri/card0
11835 09:34:37.556029 Test requirement not met in function igt_require_i915, file ../l<14>[ 23.728242] [IGT] kms_addfb_basic: exiting, ret=77
11836 09:34:37.558956 ib/drmtest.c:720:
11837 09:34:37.562915 Test requirement: is_i915_device(fd)
11838 09:34:37.568802 Test re<8>[ 23.739538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11839 09:34:37.569677 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11841 09:34:37.575709 quirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11842 09:34:37.578670 Test requirement: is_i915_device(fd)
11843 09:34:37.585430 [1mSubtest tile-pitch-mismatc<14>[ 23.760499] [IGT] kms_addfb_basic: executing
11844 09:34:37.589541 h: SKIP (0.000s)[0m
11845 09:34:37.592310 No KMS driver or no outputs, pipes: 8, outputs: 0
11846 09:34:37.598635 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11847 09:34:37.605837 Opened device: /de<14>[ 23.778190] [IGT] kms_addfb_basic: exiting, ret=77
11848 09:34:37.608740 v/dri/card0
11849 09:34:37.622286 Test requirement not met in function igt_require_i915, file ../lib/<8>[ 23.790980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11850 09:34:37.623098 drmtest.c:720:
11851 09:34:37.623871 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11853 09:34:37.625190 Test requirement: is_i915_device(fd)
11854 09:34:37.631574 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11855 09:34:37.635062 Test requirement: is_i915_device(fd)
11856 09:34:37.641916 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11857 09:34:37.648061 No KMS driver or no outputs,<14>[ 23.821077] [IGT] kms_addfb_basic: executing
11858 09:34:37.648639 pipes: 8, outputs: 0
11859 09:34:37.654749 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11860 09:34:37.658313 Opened device: /dev/dri/card0
11861 09:34:37.668222 Test requirement not met in function igt_require_i915<14>[ 23.840441] [IGT] kms_addfb_basic: exiting, ret=77
11862 09:34:37.671106 , file ../lib/drmtest.c:720:
11863 09:34:37.674724 Test requirement: is_i915_device(fd)
11864 09:34:37.684537 Test require<8>[ 23.852583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11865 09:34:37.685301 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11867 09:34:37.687392 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11868 09:34:37.691402 Test requirement: is_i915_device(fd)
11869 09:34:37.697412 No KMS driver or no outputs, pipes: 8, outputs: 0
11870 09:34:37.704971 [1mSubtest size<14>[ 23.877050] [IGT] kms_addfb_basic: executing
11871 09:34:37.705540 -max: SKIP (0.000s)[0m
11872 09:34:37.710636 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11873 09:34:37.714031 Opened device: /dev/dri/card0
11874 09:34:37.720778 Test requirement not met in functio<14>[ 23.894590] [IGT] kms_addfb_basic: exiting, ret=77
11875 09:34:37.727527 n igt_require_i915, file ../lib/drmtest.c:720:
11876 09:34:37.736746 Test requirement<8>[ 23.905431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11877 09:34:37.737192 : is_i915_device(fd)
11878 09:34:37.737893 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11880 09:34:37.744442 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11881 09:34:37.747101 Test requirement: is_i915_device(fd)
11882 09:34:37.753558 N<14>[ 23.926798] [IGT] kms_addfb_basic: executing
11883 09:34:37.757059 o KMS driver or no outputs, pipes: 8, outputs: 0
11884 09:34:37.760004 [1mSubtest too-wide: SKIP (0.000s)[0m
11885 09:34:37.770193 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58<14>[ 23.944274] [IGT] kms_addfb_basic: exiting, ret=77
11886 09:34:37.774150 -cip7 aarch64)
11887 09:34:37.774697 Opened device: /dev/dri/card0
11888 09:34:37.786686 Test requirement not met in function igt_require_i915, file ../li<8>[ 23.958483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11889 09:34:37.787513 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11891 09:34:37.790494 b/drmtest.c:720:
11892 09:34:37.792922 Test requireme<8>[ 23.968299] <LAVA_SIGNAL_TESTSET STOP>
11893 09:34:37.793619 Received signal: <TESTSET> STOP
11894 09:34:37.793996 Closing test_set kms_addfb_basic
11895 09:34:37.796576 nt: is_i915_device(fd)
11896 09:34:37.803042 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11897 09:34:37.806684 Test requirement: is_i915_device(fd)
11898 09:34:37.813083 No KMS driver or no outputs, pipes: 8, outputs: 0
11899 09:34:37.816281 [1mSubtest too-high: SKIP (0.000s)[0m
11900 09:34:37.826521 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)<8>[ 23.998527] <LAVA_SIGNAL_TESTSET START kms_atomic>
11901 09:34:37.827181
11902 09:34:37.827970 Received signal: <TESTSET> START kms_atomic
11903 09:34:37.828353 Starting test_set kms_atomic
11904 09:34:37.829576 Opened device: /dev/dri/card0
11905 09:34:37.836252 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11906 09:34:37.842669 Test requirement: is_i915_de<14>[ 24.016880] [IGT] kms_atomic: executing
11907 09:34:37.843204 vice(fd)
11908 09:34:37.849452 Test r<14>[ 24.021884] [IGT] kms_atomic: exiting, ret=77
11909 09:34:37.862489 equirement not met in function igt_require_i915, file ../lib/drm<8>[ 24.032212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11910 09:34:37.863068 test.c:720:
11911 09:34:37.863873 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11913 09:34:37.865545 Test requirement: is_i915_device(fd)
11914 09:34:37.873339 No KMS driver or no outputs, pipes: 8, outputs: 0
11915 09:34:37.875574 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11916 09:34:37.882515 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11917 09:34:37.883090 Opened device: /dev/dri/card0
11918 09:34:37.888992 Test requ<14>[ 24.062991] [IGT] kms_atomic: executing
11919 09:34:37.895449 irement not met <14>[ 24.067958] [IGT] kms_atomic: exiting, ret=77
11920 09:34:37.898739 in function igt_require_i915, file ../lib/drmtest.c:720:
11921 09:34:37.908524 Test requirement: is_i<8>[ 24.079171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11922 09:34:37.909384 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11924 09:34:37.911879 915_device(fd)
11925 09:34:37.918420 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11926 09:34:37.922758 Test requirement: is_i915_device(fd)
11927 09:34:37.928658 No KMS driver or no out<14>[ 24.100696] [IGT] kms_atomic: executing
11928 09:34:37.934896 puts, pipes: 8, <14>[ 24.106570] [IGT] kms_atomic: exiting, ret=77
11929 09:34:37.935456 outputs: 0
11930 09:34:37.938943 [1mSubtest small-bo: SKIP (0.000s)[0m
11931 09:34:37.948249 IGT-Version: 1.27.1-g621c2d<8>[ 24.118567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11932 09:34:37.949107 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11934 09:34:37.951418 3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11935 09:34:37.954585 Opened device: /dev/dri/card0
11936 09:34:37.961309 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11937 09:34:37.965041 Test requirement: is_i915_device(fd)
11938 09:34:37.974586 Test requirement not met in function igt_require_i915, file ..<14>[ 24.149898] [IGT] kms_atomic: executing
11939 09:34:37.981139 /lib/drmtest.c:7<14>[ 24.155285] [IGT] kms_atomic: exiting, ret=77
11940 09:34:37.981610 20:
11941 09:34:37.984228 Test requirement: is_i915_device(fd)
11942 09:34:37.994963 No KMS driver or no o<8>[ 24.166063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11943 09:34:37.995858 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11945 09:34:37.997797 utputs, pipes: 8, outputs: 0
11946 09:34:38.004475 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11947 09:34:38.008010 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11948 09:34:38.014197 Opened device: /de<14>[ 24.189220] [IGT] kms_atomic: executing
11949 09:34:38.017829 v/dri/card0
11950 09:34:38.020912 Tes<14>[ 24.193848] [IGT] kms_atomic: exiting, ret=77
11951 09:34:38.027386 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11952 09:34:38.037641 Test requirement<8>[ 24.206924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11953 09:34:38.038203 : is_i915_device(fd)
11954 09:34:38.038854 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11956 09:34:38.043693 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11957 09:34:38.046874 Test requirement: is_i915_device(fd)
11958 09:34:38.057666 No KMS driver or no outputs, pipe<14>[ 24.229498] [IGT] kms_atomic: executing
11959 09:34:38.060355 s: 8, outputs: 0<14>[ 24.234551] [IGT] kms_atomic: exiting, ret=77
11960 09:34:38.060831
11961 09:34:38.067002 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11962 09:34:38.076589 IGT-Version: 1.27.1-g62<8>[ 24.246517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11963 09:34:38.077359 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11965 09:34:38.079823 1c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11966 09:34:38.083305 Opened device: /dev/dri/card0
11967 09:34:38.089698 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11968 09:34:38.092829 Test requirement: is_i915_device(fd)
11969 09:34:38.103464 Test requirement not met in function igt_require_i915, fil<14>[ 24.276661] [IGT] kms_atomic: executing
11970 09:34:38.109662 e ../lib/drmtest<14>[ 24.281941] [IGT] kms_atomic: exiting, ret=77
11971 09:34:38.110195 .c:720:
11972 09:34:38.113057 Test requirement: is_i915_device(fd)
11973 09:34:38.122972 No KMS driver or <8>[ 24.292747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11974 09:34:38.123869 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11976 09:34:38.125685 no outputs, pipes: 8, outputs: 0
11977 09:34:38.129213 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11978 09:34:38.135868 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11979 09:34:38.139011 O<14>[ 24.313260] [IGT] kms_atomic: executing
11980 09:34:38.145956 pened device: /d<14>[ 24.319174] [IGT] kms_atomic: exiting, ret=77
11981 09:34:38.149509 ev/dri/card0
11982 09:34:38.159168 Test requirement not met in function igt_require_i<8>[ 24.329823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11983 09:34:38.160002 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11985 09:34:38.162517 915, file ../lib/drmtest.c:720:
11986 09:34:38.165770 Test requirement: is_i915_device(fd)
11987 09:34:38.175449 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 24.350802] [IGT] kms_atomic: executing
11988 09:34:38.178252 t.c:720:
11989 09:34:38.181876 Test r<14>[ 24.355784] [IGT] kms_atomic: exiting, ret=77
11990 09:34:38.185600 equirement: is_i915_device(fd)
11991 09:34:38.188415 No KMS driver or no outputs, pipes: 8, outputs: 0
11992 09:34:38.198475 [1mSubtest addfb25-y-tiled-s<8>[ 24.370535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11993 09:34:38.199295 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11995 09:34:38.201452 mall-legacy: SKIP (0.000s)[0m
11996 09:34:38.208431 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
11997 09:34:38.211285 Opened device: /dev/dri/card0
11998 09:34:38.218541 Test requirement not met in <14>[ 24.391722] [IGT] kms_atomic: executing
11999 09:34:38.224784 function igt_req<14>[ 24.397574] [IGT] kms_atomic: exiting, ret=77
12000 09:34:38.227914 uire_i915, file ../lib/drmtest.c:720:
12001 09:34:38.237941 Test requirement: is_i915<8>[ 24.408097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12002 09:34:38.238496 _device(fd)
12003 09:34:38.239218 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12005 09:34:38.244400 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
12006 09:34:38.248091 Test requirement: is_i915_device(fd)
12007 09:34:38.254488 No KMS dri<14>[ 24.428878] [IGT] kms_atomic: executing
12008 09:34:38.261322 ver or no output<14>[ 24.433851] [IGT] kms_atomic: exiting, ret=77
12009 09:34:38.264889 s, pipes: 8, outputs: 0
12010 09:34:38.274219 [1mSubtest addfb25-4-tiled: SKIP (0.00<8>[ 24.444948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12011 09:34:38.274657 0s)[0m
12012 09:34:38.275371 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12014 09:34:38.280633 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12015 09:34:38.284350 Opened device: /dev/dri/card0
12016 09:34:38.291236 No KMS driver or no outputs, pipes:<14>[ 24.465131] [IGT] kms_atomic: executing
12017 09:34:38.291809 8, outputs: 0
12018 09:34:38.297886 <14>[ 24.470123] [IGT] kms_atomic: exiting, ret=77
12019 09:34:38.300618 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12020 09:34:38.310815 IGT-Version<8>[ 24.480556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
12021 09:34:38.311665 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
12023 09:34:38.317160 : 1.27.1-g621c2d3 (aarch64) (Lin<8>[ 24.490912] <LAVA_SIGNAL_TESTSET STOP>
12024 09:34:38.317948 Received signal: <TESTSET> STOP
12025 09:34:38.318327 Closing test_set kms_atomic
12026 09:34:38.320327 ux: 6.1.58-cip7 aarch64)
12027 09:34:38.320751 Opened device: /dev/dri/card0
12028 09:34:38.327405 No KMS driver or no outputs, pipes: 8, outputs: 0
12029 09:34:38.330558 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12030 09:34:38.337233 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12031 09:34:38.339937 Opened device: /dev/dri/card0
12032 09:34:38.350018 No KMS driver or no outputs, pipes: 8, outp<8>[ 24.521635] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12033 09:34:38.350680 uts: 0
12034 09:34:38.351384 Received signal: <TESTSET> START kms_flip_event_leak
12035 09:34:38.351800 Starting test_set kms_flip_event_leak
12036 09:34:38.357817 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12037 09:34:38.363767 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12038 09:34:38.366404 Opened device: /<14>[ 24.540565] [IGT] kms_flip_event_leak: executing
12039 09:34:38.369627 dev/dri/card0
12040 09:34:38.376431 N<14>[ 24.547236] [IGT] kms_flip_event_leak: exiting, ret=77
12041 09:34:38.380083 o KMS driver or no outputs, pipes: 8, outputs: 0
12042 09:34:38.386453 [1mSubtest pl<8>[ 24.558491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12043 09:34:38.387282 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12045 09:34:38.392866 ane-immutable-zpos: SKIP (0.000s<8>[ 24.567113] <LAVA_SIGNAL_TESTSET STOP>
12046 09:34:38.393390 )[0m
12047 09:34:38.394098 Received signal: <TESTSET> STOP
12048 09:34:38.394466 Closing test_set kms_flip_event_leak
12049 09:34:38.399479 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12050 09:34:38.403116 Opened device: /dev/dri/card0
12051 09:34:38.406860 No KMS driver or no outputs, pipes: 8, outputs: 0
12052 09:34:38.409748 [1mSubtest test-only: SKIP (0.000s)[0m
12053 09:34:38.416516 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12054 09:34:38.423031 Opened device: /dev<8>[ 24.597206] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12055 09:34:38.423883 Received signal: <TESTSET> START kms_prop_blob
12056 09:34:38.424283 Starting test_set kms_prop_blob
12057 09:34:38.426496 /dri/card0
12058 09:34:38.429205 No KMS driver or no outputs, pipes: 8, outputs: 0
12059 09:34:38.432637 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12060 09:34:38.442134 IGT-Version: 1.27.1-g621c2d3 <14>[ 24.615336] [IGT] kms_prop_blob: executing
12061 09:34:38.448950 (aarch64) (Linux<14>[ 24.620147] [IGT] kms_prop_blob: starting subtest basic
12062 09:34:38.455684 : 6.1.58-cip7 aa<14>[ 24.626886] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12063 09:34:38.456149 rch64)
12064 09:34:38.462263 Opened d<14>[ 24.634660] [IGT] kms_prop_blob: exiting, ret=0
12065 09:34:38.465559 evice: /dev/dri/card0
12066 09:34:38.468837 No KMS driver or no outputs, pipes: 8, outputs: 0
12067 09:34:38.475822 [1mSu<8>[ 24.646929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12068 09:34:38.476530 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12070 09:34:38.479007 btest plane-invalid-params: SKIP (0.000s)[0m
12071 09:34:38.485477 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12072 09:34:38.488865 Opened device: /dev/dri/card0
12073 09:34:38.491825 No KMS driver or no outputs, pipes: 8, outputs: 0
12074 09:34:38.498731 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12075 09:34:38.502064 <14>[ 24.676153] [IGT] kms_prop_blob: executing
12076 09:34:38.502496
12077 09:34:38.508523 IGT-Version: 1.<14>[ 24.681493] [IGT] kms_prop_blob: starting subtest blob-prop-core
12078 09:34:38.518464 27.1-g621c2d3 (a<14>[ 24.688782] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12079 09:34:38.525089 arch64) (Linux: <14>[ 24.697312] [IGT] kms_prop_blob: exiting, ret=0
12080 09:34:38.528059 6.1.58-cip7 aarch64)
12081 09:34:38.528542 Opened device: /dev/dri/card0
12082 09:34:38.538313 No KMS driver or no outputs<8>[ 24.709246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12083 09:34:38.539202 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12085 09:34:38.541300 , pipes: 8, outputs: 0
12086 09:34:38.544585 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12087 09:34:38.551887 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12088 09:34:38.554350 Opened device: /dev/dri/card0
12089 09:34:38.557861 No KMS driver or no outputs, pipes: 8, outputs: 0
12090 09:34:38.567891 [1mSubtest crtc-invalid-params-fence: SKIP (<14>[ 24.739919] [IGT] kms_prop_blob: executing
12091 09:34:38.568457 0.000s)[0m
12092 09:34:38.574669 IGT<14>[ 24.746140] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12093 09:34:38.584477 -Version: 1.27.1<14>[ 24.754181] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12094 09:34:38.590948 -g621c2d3 (aarch<14>[ 24.762784] [IGT] kms_prop_blob: exiting, ret=0
12095 09:34:38.594093 64) (Linux: 6.1.58-cip7 aarch64)
12096 09:34:38.597472 Opened device: /dev/dri/card0
12097 09:34:38.603525 No KMS driver o<8>[ 24.775916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12098 09:34:38.604407 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12100 09:34:38.607255 r no outputs, pipes: 8, outputs: 0
12101 09:34:38.613821 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12102 09:34:38.617143 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12103 09:34:38.623266 O<14>[ 24.796075] [IGT] kms_prop_blob: executing
12104 09:34:38.630129 pened device: /d<14>[ 24.802259] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12105 09:34:38.633332 ev/dri/card0
12106 09:34:38.640298 No<14>[ 24.810231] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12107 09:34:38.646632 KMS driver or n<14>[ 24.818961] [IGT] kms_prop_blob: exiting, ret=0
12108 09:34:38.650500 o outputs, pipes: 8, outputs: 0
12109 09:34:38.659581 [1mSubtest atomic_plane_damage<8>[ 24.829362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12110 09:34:38.660060 : SKIP (0.000s)[0m
12111 09:34:38.660761 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12113 09:34:38.666870 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12114 09:34:38.669658 Opened device: /dev/dri/card0
12115 09:34:38.676348 No KMS driver or no out<14>[ 24.850152] [IGT] kms_prop_blob: executing
12116 09:34:38.683029 puts, pipes: 8, <14>[ 24.855516] [IGT] kms_prop_blob: starting subtest blob-multiple
12117 09:34:38.686259 outputs: 0
12118 09:34:38.692589 [1m<14>[ 24.863051] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12119 09:34:38.699260 Subtest basic: S<14>[ 24.871413] [IGT] kms_prop_blob: exiting, ret=0
12120 09:34:38.699760 KIP (0.000s)[0m
12121 09:34:38.712284 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<8>[ 24.882526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12122 09:34:38.712868 6.1.58-cip7 aarch64)
12123 09:34:38.713694 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12125 09:34:38.715548 Opened device: /dev/dri/card0
12126 09:34:38.718817 Starting subtest: basic
12127 09:34:38.722548 [1mSubtest basic: SUCCESS (0.000s)[0m
12128 09:34:38.729030 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12129 09:34:38.729567 Opened device: /dev/dri/card0
12130 09:34:38.732167 Starting subtest: blob-prop-core
12131 09:34:38.739241 [<14>[ 24.912111] [IGT] kms_prop_blob: executing
12132 09:34:38.745465 1mSubtest blob-p<14>[ 24.917600] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12133 09:34:38.755244 rop-core: SUCCES<14>[ 24.925388] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12134 09:34:38.755677 S (0.000s)[0m
12135 09:34:38.763070 <14>[ 24.934400] [IGT] kms_prop_blob: exiting, ret=0
12136 09:34:38.768299 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12137 09:34:38.778393 Opened device: /dev/dri/car<8>[ 24.947786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12138 09:34:38.778931 d0
12139 09:34:38.779656 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12141 09:34:38.781800 Starting subtest: blob-prop-validate
12142 09:34:38.784955 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12143 09:34:38.791498 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12144 09:34:38.794931 Opened device: /dev/dri/card0
12145 09:34:38.798235 Starting subtest: blob-prop-lifetime
12146 09:34:38.805063 [1mSubtest blob-prop-<14>[ 24.978668] [IGT] kms_prop_blob: executing
12147 09:34:38.811714 lifetime: SUCCES<14>[ 24.983893] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12148 09:34:38.814971 S (0.000s)[0m
12149 09:34:38.821499 <14>[ 24.991453] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12150 09:34:38.827988 IGT-Version: 1.2<14>[ 25.000159] [IGT] kms_prop_blob: exiting, ret=0
12151 09:34:38.831248 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12152 09:34:38.841578 Opened devi<8>[ 25.011817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12153 09:34:38.842154 ce: /dev/dri/card0
12154 09:34:38.842806 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12156 09:34:38.844656 Starting subtest: blob-multiple
12157 09:34:38.847792 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12158 09:34:38.854398 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12159 09:34:38.857824 Opened device: /dev/dri/card0
12160 09:34:38.861807 Starting subtest: invalid-get-prop-any
12161 09:34:38.868013 [1mSubtest in<14>[ 25.041214] [IGT] kms_prop_blob: executing
12162 09:34:38.874043 valid-get-prop-a<14>[ 25.046671] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12163 09:34:38.884069 ny: SUCCESS (0.0<14>[ 25.054374] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12164 09:34:38.884590 00s)[0m
12165 09:34:38.891056 IGT-Ve<14>[ 25.063395] [IGT] kms_prop_blob: exiting, ret=0
12166 09:34:38.897730 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12167 09:34:38.898296 Opened device: /dev/dri/card0
12168 09:34:38.907261 St<8>[ 25.076651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12169 09:34:38.908187 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12171 09:34:38.910809 arting subtest: invalid-get-prop
12172 09:34:38.913977 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12173 09:34:38.920351 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12174 09:34:38.924019 Opened device: /dev/dri/card0
12175 09:34:38.927304 Starting subtest: invalid-set-prop-any
12176 09:34:38.933672 [1mSubtest invalid-set-prop-a<14>[ 25.107599] [IGT] kms_prop_blob: executing
12177 09:34:38.940480 ny: SUCCESS (0.0<14>[ 25.112998] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12178 09:34:38.943345 00s)[0m
12179 09:34:38.950667 IGT-Ve<14>[ 25.120437] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12180 09:34:38.956318 rsion: 1.27.1-g6<14>[ 25.129104] [IGT] kms_prop_blob: exiting, ret=0
12181 09:34:38.959532 21c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12182 09:34:38.963015 Opened device: /dev/dri/card0
12183 09:34:38.969531 St<8>[ 25.140959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12184 09:34:38.970371 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12186 09:34:38.976223 arting subtest: invalid-set-prop<8>[ 25.151640] <LAVA_SIGNAL_TESTSET STOP>
12187 09:34:38.976696
12188 09:34:38.977312 Received signal: <TESTSET> STOP
12189 09:34:38.977650 Closing test_set kms_prop_blob
12190 09:34:38.982703 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12191 09:34:39.008834 <8>[ 25.182924] <LAVA_SIGNAL_TESTSET START kms_setmode>
12192 09:34:39.009619 Received signal: <TESTSET> START kms_setmode
12193 09:34:39.009976 Starting test_set kms_setmode
12194 09:34:39.026425 <14>[ 25.200368] [IGT] kms_setmode: executing
12195 09:34:39.032943 IGT-Version: 1.2<14>[ 25.205022] [IGT] kms_setmode: starting subtest basic
12196 09:34:39.039589 7.1-g621c2d3 (aa<14>[ 25.211652] [IGT] kms_setmode: finished subtest basic, SKIP
12197 09:34:39.046026 rch64) (Linux: 6<14>[ 25.218995] [IGT] kms_setmode: exiting, ret=77
12198 09:34:39.049245 .1.58-cip7 aarch64)
12199 09:34:39.049678 Opened device: /dev/dri/card0
12200 09:34:39.059061 Starting sub<8>[ 25.229397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12201 09:34:39.059475 test: basic
12202 09:34:39.060176 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12204 09:34:39.062446 No dynamic tests executed.
12205 09:34:39.065647 [1mSubtest basic: SKIP (0.000s)[0m
12206 09:34:39.075399 <14>[ 25.249297] [IGT] kms_setmode: executing
12207 09:34:39.082018 IGT-Version: 1.2<14>[ 25.253928] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12208 09:34:39.092292 7.1-g621c2d3 (aa<14>[ 25.262171] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12209 09:34:39.098593 rch64) (Linux: 6<14>[ 25.270977] [IGT] kms_setmode: exiting, ret=77
12210 09:34:39.099166 .1.58-cip7 aarch64)
12211 09:34:39.101636 Opened device: /dev/dri/card0
12212 09:34:39.111849 Starting subtest: basic-clon<8>[ 25.283593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12213 09:34:39.112674 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12215 09:34:39.114864 e-single-crtc
12216 09:34:39.118659 No dynamic tests executed.
12217 09:34:39.121421 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12218 09:34:39.131515 <14>[ 25.305630] [IGT] kms_setmode: executing
12219 09:34:39.138589 IGT-Version: 1.2<14>[ 25.310371] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12220 09:34:39.148167 7.1-g621c2d3 (aa<14>[ 25.318604] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12221 09:34:39.154985 rch64) (Linux: 6<14>[ 25.327694] [IGT] kms_setmode: exiting, ret=77
12222 09:34:39.158111 .1.58-cip7 aarch64)
12223 09:34:39.158575 Opened device: /dev/dri/card0
12224 09:34:39.168661 Starting sub<8>[ 25.338638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12225 09:34:39.169506 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12227 09:34:39.172064 test: invalid-clone-single-crtc
12228 09:34:39.174498 No dynamic tests executed.
12229 09:34:39.177757 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12230 09:34:39.185577 <14>[ 25.359666] [IGT] kms_setmode: executing
12231 09:34:39.195497 IGT-Version: 1.2<14>[ 25.364468] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12232 09:34:39.202373 7.1-g621c2d3 (aa<14>[ 25.373095] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12233 09:34:39.209446 rch64) (Linux: 6<14>[ 25.382516] [IGT] kms_setmode: exiting, ret=77
12234 09:34:39.212105 .1.58-cip7 aarch64)
12235 09:34:39.215531 Opened device: /dev/dri/card0
12236 09:34:39.221938 Starting sub<8>[ 25.393189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12237 09:34:39.222768 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12239 09:34:39.225091 test: invalid-clone-exclusive-crtc
12240 09:34:39.228392 No dynamic tests executed.
12241 09:34:39.235106 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12242 09:34:39.243426 <14>[ 25.417501] [IGT] kms_setmode: executing
12243 09:34:39.249839 IGT-Version: 1.2<14>[ 25.422237] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12244 09:34:39.256696 <14>[ 25.430057] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12245 09:34:39.263820 7.1-g621c2d3 (aa<14>[ 25.437334] [IGT] kms_setmode: exiting, ret=77
12246 09:34:39.267009 rch64) (Linux: 6.1.58-cip7 aarch64)
12247 09:34:39.270196 Opened device: /dev/dri/card0
12248 09:34:39.280381 Starting sub<8>[ 25.449703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12249 09:34:39.281233 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12251 09:34:39.283471 test: clone-exclusive-crtc
12252 09:34:39.284049 No dynamic tests executed.
12253 09:34:39.290004 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12254 09:34:39.297365 <14>[ 25.471268] [IGT] kms_setmode: executing
12255 09:34:39.307583 IGT-Version: 1.2<14>[ 25.475889] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12256 09:34:39.317100 7.1-g621c2d3 (aa<14>[ 25.485053] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12257 09:34:39.323600 rch64) (Linux: 6<14>[ 25.494964] [IGT] kms_setmode: exiting, ret=77
12258 09:34:39.324203 .1.58-cip7 aarch64)
12259 09:34:39.327261 Opened device: /dev/dri/card0
12260 09:34:39.336591 Starting sub<8>[ 25.505815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12261 09:34:39.337473 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12263 09:34:39.343811 test: invalid-cl<8>[ 25.516687] <LAVA_SIGNAL_TESTSET STOP>
12264 09:34:39.344364 one-single-crtc-stealing
12265 09:34:39.345013 Received signal: <TESTSET> STOP
12266 09:34:39.345393 Closing test_set kms_setmode
12267 09:34:39.347029 No dynamic tests executed.
12268 09:34:39.353607 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12269 09:34:39.372300 <8>[ 25.546505] <LAVA_SIGNAL_TESTSET START kms_vblank>
12270 09:34:39.373114 Received signal: <TESTSET> START kms_vblank
12271 09:34:39.373506 Starting test_set kms_vblank
12272 09:34:39.396867 <14>[ 25.570733] [IGT] kms_vblank: executing
12273 09:34:39.403012 IGT-Version: 1.2<14>[ 25.575788] [IGT] kms_vblank: exiting, ret=77
12274 09:34:39.406472 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12275 09:34:39.416614 Opened device: /dev/dri/car<8>[ 25.586907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12276 09:34:39.417373 d0
12277 09:34:39.418102 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12279 09:34:39.419799 No KMS driver or no outputs, pipes: 8, outputs: 0
12280 09:34:39.423042 [1mSubtest invalid: SKIP (0.000s)[0m
12281 09:34:39.443245 <14>[ 25.617278] [IGT] kms_vblank: executing
12282 09:34:39.450017 IGT-Version: 1.2<14>[ 25.622369] [IGT] kms_vblank: exiting, ret=77
12283 09:34:39.453322 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12284 09:34:39.459799 Opened devi<8>[ 25.633198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12285 09:34:39.460542 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12287 09:34:39.463267 ce: /dev/dri/card0
12288 09:34:39.466323 No KMS driver or no outputs, pipes: 8, outputs: 0
12289 09:34:39.469914 [1mSubtest crtc-id: SKIP (0.000s)[0m
12290 09:34:39.479477 <14>[ 25.653107] [IGT] kms_vblank: executing
12291 09:34:39.485686 IGT-Version: 1.2<14>[ 25.657844] [IGT] kms_vblank: exiting, ret=77
12292 09:34:39.489079 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12293 09:34:39.499176 Opened devi<8>[ 25.668486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12294 09:34:39.499772 ce: /dev/dri/card0
12295 09:34:39.500434 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12297 09:34:39.505790 No KMS driver or no outputs, pipes: 8, outputs: 0
12298 09:34:39.508806 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12299 09:34:39.524491 <14>[ 25.698300] [IGT] kms_vblank: executing
12300 09:34:39.530954 IGT-Version: 1.2<14>[ 25.703415] [IGT] kms_vblank: exiting, ret=77
12301 09:34:39.534081 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12302 09:34:39.543848 Opened device: /dev/dri/car<8>[ 25.714464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12303 09:34:39.544417 d0
12304 09:34:39.545143 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12306 09:34:39.550353 No KMS driver or no outputs, pipes: 8, outputs: 0
12307 09:34:39.553594 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12308 09:34:39.561910 <14>[ 25.735997] [IGT] kms_vblank: executing
12309 09:34:39.568668 IGT-Version: 1.2<14>[ 25.740804] [IGT] kms_vblank: exiting, ret=77
12310 09:34:39.571962 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12311 09:34:39.581685 Opened devi<8>[ 25.751376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12312 09:34:39.582191 ce: /dev/dri/card0
12313 09:34:39.582851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12315 09:34:39.588250 No KMS driver or no outputs, pipes: 8, outputs: 0
12316 09:34:39.592380 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12317 09:34:39.599006 <14>[ 25.772092] [IGT] kms_vblank: executing
12318 09:34:39.605131 IGT-Version: 1.2<14>[ 25.776825] [IGT] kms_vblank: exiting, ret=77
12319 09:34:39.608225 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12320 09:34:39.618470 Opened devi<8>[ 25.787476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12321 09:34:39.619098 ce: /dev/dri/card0
12322 09:34:39.619783 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12324 09:34:39.621220 No KMS driver or no outputs, pipes: 8, outputs: 0
12325 09:34:39.628027 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12326 09:34:39.649220 <14>[ 25.823062] [IGT] kms_vblank: executing
12327 09:34:39.655624 IGT-Version: 1.2<14>[ 25.828147] [IGT] kms_vblank: exiting, ret=77
12328 09:34:39.659512 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12329 09:34:39.662458 Opened device: /dev/dri/card0
12330 09:34:39.671948 No KMS driver or no outputs,<8>[ 25.843069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12331 09:34:39.672815 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12333 09:34:39.675129 pipes: 8, outputs: 0
12334 09:34:39.678820 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12335 09:34:39.690635 <14>[ 25.864392] [IGT] kms_vblank: executing
12336 09:34:39.696971 IGT-Version: 1.2<14>[ 25.869161] [IGT] kms_vblank: exiting, ret=77
12337 09:34:39.700430 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12338 09:34:39.709983 Opened devi<8>[ 25.879861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12339 09:34:39.710431 ce: /dev/dri/card0
12340 09:34:39.711280 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12342 09:34:39.713271 No KMS driver or no outputs, pipes: 8, outputs: 0
12343 09:34:39.720429 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12344 09:34:39.727053 <14>[ 25.899914] [IGT] kms_vblank: executing
12345 09:34:39.730425 IGT-Version: 1.2<14>[ 25.904695] [IGT] kms_vblank: exiting, ret=77
12346 09:34:39.736495 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12347 09:34:39.743856 Opened devi<8>[ 25.915667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12348 09:34:39.744718 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12350 09:34:39.746391 ce: /dev/dri/card0
12351 09:34:39.749747 No KMS driver or no outputs, pipes: 8, outputs: 0
12352 09:34:39.756490 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12353 09:34:39.772371 <14>[ 25.946592] [IGT] kms_vblank: executing
12354 09:34:39.779397 IGT-Version: 1.2<14>[ 25.951661] [IGT] kms_vblank: exiting, ret=77
12355 09:34:39.782545 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12356 09:34:39.785740 Opened device: /dev/dri/card0
12357 09:34:39.795825 No KMS driver or no outputs,<8>[ 25.966613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12358 09:34:39.796710 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12360 09:34:39.799023 pipes: 8, outputs: 0
12361 09:34:39.802427 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12362 09:34:39.824083 <14>[ 25.997365] [IGT] kms_vblank: executing
12363 09:34:39.830105 IGT-Version: 1.2<14>[ 26.002589] [IGT] kms_vblank: exiting, ret=77
12364 09:34:39.833191 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12365 09:34:39.843334 Opened device: /dev/dri/car<8>[ 26.013691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12366 09:34:39.844092 d0
12367 09:34:39.844865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12369 09:34:39.849977 No KMS driver or no outputs, pipes: 8, outputs: 0
12370 09:34:39.852927 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12371 09:34:39.864671 <14>[ 26.038335] [IGT] kms_vblank: executing
12372 09:34:39.870998 IGT-Version: 1.2<14>[ 26.043078] [IGT] kms_vblank: exiting, ret=77
12373 09:34:39.873858 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12374 09:34:39.877957 Opened device: /dev/dri/card0
12375 09:34:39.887545 No KMS driver or no outputs,<8>[ 26.057101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12376 09:34:39.888262 pipes: 8, outputs: 0
12377 09:34:39.889036 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12379 09:34:39.893925 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12380 09:34:39.914843 <14>[ 26.088701] [IGT] kms_vblank: executing
12381 09:34:39.921549 IGT-Version: 1.2<14>[ 26.093906] [IGT] kms_vblank: exiting, ret=77
12382 09:34:39.924459 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12383 09:34:39.935114 Opened device: /dev/dri/car<8>[ 26.105176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12384 09:34:39.935694 d0
12385 09:34:39.936515 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12387 09:34:39.940959 No KMS driver or no outputs, pipes: 8, outputs: 0
12388 09:34:39.944310 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12389 09:34:39.962784 <14>[ 26.136742] [IGT] kms_vblank: executing
12390 09:34:39.969725 IGT-Version: 1.2<14>[ 26.141947] [IGT] kms_vblank: exiting, ret=77
12391 09:34:39.972879 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12392 09:34:39.982857 Opened device: /dev/dri/car<8>[ 26.153411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12393 09:34:39.983435 d0
12394 09:34:39.984321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12396 09:34:39.989004 No KMS driver or no outputs, pipes: 8, outputs: 0
12397 09:34:39.992189 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12398 09:34:40.002323 <14>[ 26.176138] [IGT] kms_vblank: executing
12399 09:34:40.008469 IGT-Version: 1.2<14>[ 26.180905] [IGT] kms_vblank: exiting, ret=77
12400 09:34:40.012084 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12401 09:34:40.022159 Opened device: /dev/dri/car<8>[ 26.192636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12402 09:34:40.022816 d0
12403 09:34:40.023593 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12405 09:34:40.028761 No KMS driver or no outputs, pipes: 8, outputs: 0
12406 09:34:40.031494 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12407 09:34:40.042056 <14>[ 26.216465] [IGT] kms_vblank: executing
12408 09:34:40.048692 IGT-Version: 1.2<14>[ 26.221184] [IGT] kms_vblank: exiting, ret=77
12409 09:34:40.051955 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12410 09:34:40.062206 Opened devi<8>[ 26.231711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12411 09:34:40.062806 ce: /dev/dri/card0
12412 09:34:40.063580 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12414 09:34:40.065084 No KMS driver or no outputs, pipes: 8, outputs: 0
12415 09:34:40.072002 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12416 09:34:40.081130 <14>[ 26.254803] [IGT] kms_vblank: executing
12417 09:34:40.087361 IGT-Version: 1.2<14>[ 26.259578] [IGT] kms_vblank: exiting, ret=77
12418 09:34:40.090471 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12419 09:34:40.100942 Opened devi<8>[ 26.270138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12420 09:34:40.101738 ce: /dev/dri/card0
12421 09:34:40.102415 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12423 09:34:40.107666 No KMS driver or no outputs, pipes: 8, outputs: 0
12424 09:34:40.111053 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12425 09:34:40.116920 <14>[ 26.290311] [IGT] kms_vblank: executing
12426 09:34:40.120719 IGT-Version: 1.2<14>[ 26.295055] [IGT] kms_vblank: exiting, ret=77
12427 09:34:40.126957 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12428 09:34:40.136650 Opened device: /dev/dri/car<8>[ 26.306938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12429 09:34:40.137439 d0
12430 09:34:40.138117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12432 09:34:40.139793 No KMS driver or no outputs, pipes: 8, outputs: 0
12433 09:34:40.146835 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12434 09:34:40.155901 <14>[ 26.328401] [IGT] kms_vblank: executing
12435 09:34:40.160855 IGT-Version: 1.2<14>[ 26.333126] [IGT] kms_vblank: exiting, ret=77
12436 09:34:40.164149 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12437 09:34:40.174018 Opened device: /dev/dri/car<8>[ 26.344946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12438 09:34:40.174501 d0
12439 09:34:40.175138 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12441 09:34:40.181134 No KMS driver or no outputs, pipes: 8, outputs: 0
12442 09:34:40.184109 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12443 09:34:40.201913 <14>[ 26.375858] [IGT] kms_vblank: executing
12444 09:34:40.208300 IGT-Version: 1.2<14>[ 26.380965] [IGT] kms_vblank: exiting, ret=77
12445 09:34:40.211704 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12446 09:34:40.221483 Opened devi<8>[ 26.391939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12447 09:34:40.221913 ce: /dev/dri/card0
12448 09:34:40.222512 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12450 09:34:40.228295 No KMS driver or no outputs, pipes: 8, outputs: 0
12451 09:34:40.231601 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12452 09:34:40.241420 <14>[ 26.415714] [IGT] kms_vblank: executing
12453 09:34:40.248825 IGT-Version: 1.2<14>[ 26.420470] [IGT] kms_vblank: exiting, ret=77
12454 09:34:40.251571 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12455 09:34:40.261485 Opened devi<8>[ 26.430748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12456 09:34:40.262231 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12458 09:34:40.264478 ce: /dev/dri/card0
12459 09:34:40.267807 No KMS driver or no outputs, pipes: 8, outputs: 0
12460 09:34:40.274254 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12461 09:34:40.288947 <14>[ 26.463062] [IGT] kms_vblank: executing
12462 09:34:40.296056 IGT-Version: 1.2<14>[ 26.468136] [IGT] kms_vblank: exiting, ret=77
12463 09:34:40.298823 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12464 09:34:40.309268 Opened device: /dev/dri/car<8>[ 26.479858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12465 09:34:40.310117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12467 09:34:40.311943 d0
12468 09:34:40.315663 No KMS driver or no outputs, pipes: 8, outputs: 0
12469 09:34:40.321938 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12470 09:34:40.328656 <14>[ 26.501941] [IGT] kms_vblank: executing
12471 09:34:40.331603 IGT-Version: 1.2<14>[ 26.506737] [IGT] kms_vblank: exiting, ret=77
12472 09:34:40.338183 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12473 09:34:40.348766 Opened devi<8>[ 26.517052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12474 09:34:40.349316 ce: /dev/dri/card0
12475 09:34:40.349958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12477 09:34:40.354724 No KMS driver or no outputs, pipes: 8, outputs: 0
12478 09:34:40.361424 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12479 09:34:40.364704 <14>[ 26.539042] [IGT] kms_vblank: executing
12480 09:34:40.371245 IGT-Version: 1.2<14>[ 26.543786] [IGT] kms_vblank: exiting, ret=77
12481 09:34:40.374519 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12482 09:34:40.384544 Opened devi<8>[ 26.554401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12483 09:34:40.385396 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12485 09:34:40.387716 ce: /dev/dri/card0
12486 09:34:40.391133 No KMS driver or no outputs, pipes: 8, outputs: 0
12487 09:34:40.397512 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12488 09:34:40.401340 <14>[ 26.575612] [IGT] kms_vblank: executing
12489 09:34:40.407933 IGT-Version: 1.2<14>[ 26.580388] [IGT] kms_vblank: exiting, ret=77
12490 09:34:40.410776 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12491 09:34:40.420671 Opened devi<8>[ 26.591098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12492 09:34:40.421472 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12494 09:34:40.423884 ce: /dev/dri/card0
12495 09:34:40.427884 No KMS driver or no outputs, pipes: 8, outputs: 0
12496 09:34:40.434106 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12497 09:34:40.447470 <14>[ 26.621539] [IGT] kms_vblank: executing
12498 09:34:40.454261 IGT-Version: 1.2<14>[ 26.626805] [IGT] kms_vblank: exiting, ret=77
12499 09:34:40.457223 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12500 09:34:40.467652 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12502 09:34:40.470668 Opened device: /dev/dri/car<8>[ 26.637594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12503 09:34:40.471241 d0
12504 09:34:40.473628 No KMS driver or no outputs, pipes: 8, outputs: 0
12505 09:34:40.480413 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12506 09:34:40.486766 <14>[ 26.661089] [IGT] kms_vblank: executing
12507 09:34:40.493304 IGT-Version: 1.2<14>[ 26.665892] [IGT] kms_vblank: exiting, ret=77
12508 09:34:40.497284 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12509 09:34:40.506942 Opened devi<8>[ 26.676404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12510 09:34:40.507853 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12512 09:34:40.510201 ce: /dev/dri/card0
12513 09:34:40.513473 No KMS driver or no outputs, pipes: 8, outputs: 0
12514 09:34:40.519978 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12515 09:34:40.523610 <14>[ 26.698331] [IGT] kms_vblank: executing
12516 09:34:40.530534 IGT-Version: 1.2<14>[ 26.703074] [IGT] kms_vblank: exiting, ret=77
12517 09:34:40.533876 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12518 09:34:40.543010 Opened devi<8>[ 26.713594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12519 09:34:40.543585 ce: /dev/dri/card0
12520 09:34:40.544296 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12522 09:34:40.550096 No KMS driver or no outputs, pipes: 8, outputs: 0
12523 09:34:40.552866 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12524 09:34:40.563320 <14>[ 26.737237] [IGT] kms_vblank: executing
12525 09:34:40.569519 IGT-Version: 1.2<14>[ 26.741977] [IGT] kms_vblank: exiting, ret=77
12526 09:34:40.572715 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12527 09:34:40.582843 Opened device: /dev/dri/car<8>[ 26.754182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12528 09:34:40.583435 d0
12529 09:34:40.584139 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12531 09:34:40.589775 No KMS driver or no outputs, pipes: 8, outputs: 0
12532 09:34:40.593201 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12533 09:34:40.600287 <14>[ 26.773805] [IGT] kms_vblank: executing
12534 09:34:40.606329 IGT-Version: 1.2<14>[ 26.778665] [IGT] kms_vblank: exiting, ret=77
12535 09:34:40.609401 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12536 09:34:40.619816 Opened devi<8>[ 26.789078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12537 09:34:40.620383 ce: /dev/dri/card0
12538 09:34:40.621152 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12540 09:34:40.626474 No KMS driver or no outputs, pipes: 8, outputs: 0
12541 09:34:40.629759 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12542 09:34:40.636112 <14>[ 26.809788] [IGT] kms_vblank: executing
12543 09:34:40.642645 IGT-Version: 1.2<14>[ 26.814621] [IGT] kms_vblank: exiting, ret=77
12544 09:34:40.645855 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12545 09:34:40.655834 Opened devi<8>[ 26.825138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12546 09:34:40.656452 ce: /dev/dri/card0
12547 09:34:40.657110 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12549 09:34:40.659079 No KMS driver or no outputs, pipes: 8, outputs: 0
12550 09:34:40.665640 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12551 09:34:40.672805 <14>[ 26.846096] [IGT] kms_vblank: executing
12552 09:34:40.678837 IGT-Version: 1.2<14>[ 26.850823] [IGT] kms_vblank: exiting, ret=77
12553 09:34:40.682481 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12554 09:34:40.692112 Opened device: /dev/dri/car<8>[ 26.862914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12555 09:34:40.692671 d0
12556 09:34:40.693395 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12558 09:34:40.698476 No KMS driver or no outputs, pipes: 8, outputs: 0
12559 09:34:40.701859 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12560 09:34:40.719212 <14>[ 26.893173] [IGT] kms_vblank: executing
12561 09:34:40.725947 IGT-Version: 1.2<14>[ 26.898547] [IGT] kms_vblank: exiting, ret=77
12562 09:34:40.729068 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12563 09:34:40.739179 Opened device: /dev/dri/car<8>[ 26.909468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12564 09:34:40.739806 d0
12565 09:34:40.740538 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12567 09:34:40.745523 No KMS driver or no outputs, pipes: 8, outputs: 0
12568 09:34:40.749092 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12569 09:34:40.758415 <14>[ 26.932289] [IGT] kms_vblank: executing
12570 09:34:40.764685 IGT-Version: 1.2<14>[ 26.937010] [IGT] kms_vblank: exiting, ret=77
12571 09:34:40.768127 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12572 09:34:40.778035 Opened device: /dev/dri/car<8>[ 26.949064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12573 09:34:40.778619 d0
12574 09:34:40.779294 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12576 09:34:40.784432 No KMS driver or no outputs, pipes: 8, outputs: 0
12577 09:34:40.787771 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12578 09:34:40.796881 <14>[ 26.970997] [IGT] kms_vblank: executing
12579 09:34:40.803870 IGT-Version: 1.2<14>[ 26.975798] [IGT] kms_vblank: exiting, ret=77
12580 09:34:40.806529 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12581 09:34:40.816565 Opened devi<8>[ 26.986535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12582 09:34:40.817155 ce: /dev/dri/card0
12583 09:34:40.817871 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12585 09:34:40.823199 No KMS driver or no outputs, pipes: 8, outputs: 0
12586 09:34:40.826456 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12587 09:34:40.849622 <14>[ 27.023585] [IGT] kms_vblank: executing
12588 09:34:40.856192 IGT-Version: 1.2<14>[ 27.028714] [IGT] kms_vblank: exiting, ret=77
12589 09:34:40.859141 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12590 09:34:40.862510 Opened device: /dev/dri/card0
12591 09:34:40.872714 No KMS driver or no outputs,<8>[ 27.043856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12592 09:34:40.873606 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12594 09:34:40.876281 pipes: 8, outputs: 0
12595 09:34:40.879545 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12596 09:34:40.892965 <14>[ 27.067137] [IGT] kms_vblank: executing
12597 09:34:40.899215 IGT-Version: 1.2<14>[ 27.071876] [IGT] kms_vblank: exiting, ret=77
12598 09:34:40.903089 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12599 09:34:40.912565 Opened devi<8>[ 27.082603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12600 09:34:40.913129 ce: /dev/dri/card0
12601 09:34:40.913792 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12603 09:34:40.918968 No KMS driver or no outputs, pipes: 8, outputs: 0
12604 09:34:40.922350 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12605 09:34:40.930753 <14>[ 27.104388] [IGT] kms_vblank: executing
12606 09:34:40.936603 IGT-Version: 1.2<14>[ 27.109160] [IGT] kms_vblank: exiting, ret=77
12607 09:34:40.940006 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12608 09:34:40.950144 Opened devi<8>[ 27.120039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12609 09:34:40.950722 ce: /dev/dri/card0
12610 09:34:40.951376 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12612 09:34:40.956707 No KMS driver or no outputs, pipes: 8, outputs: 0
12613 09:34:40.959715 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12614 09:34:40.975756 <14>[ 27.149938] [IGT] kms_vblank: executing
12615 09:34:40.982677 IGT-Version: 1.2<14>[ 27.155082] [IGT] kms_vblank: exiting, ret=77
12616 09:34:40.985670 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12617 09:34:40.995497 Opened device: /dev/dri/car<8>[ 27.166660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12618 09:34:40.996189 d0
12619 09:34:40.996853 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12621 09:34:41.002357 No KMS driver or no outputs, pipes: 8, outputs: 0
12622 09:34:41.005516 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12623 09:34:41.015995 <14>[ 27.189952] [IGT] kms_vblank: executing
12624 09:34:41.023110 IGT-Version: 1.2<14>[ 27.194716] [IGT] kms_vblank: exiting, ret=77
12625 09:34:41.025793 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12626 09:34:41.035699 Opened devi<8>[ 27.205171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12627 09:34:41.036324 ce: /dev/dri/card0
12628 09:34:41.036986 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12630 09:34:41.042366 No KMS driver or no outputs, pipes: 8, outputs: 0
12631 09:34:41.045688 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12632 09:34:41.052079 <14>[ 27.226012] [IGT] kms_vblank: executing
12633 09:34:41.059023 IGT-Version: 1.2<14>[ 27.230740] [IGT] kms_vblank: exiting, ret=77
12634 09:34:41.062262 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12635 09:34:41.068656 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12637 09:34:41.071686 Opened devi<8>[ 27.241393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12638 09:34:41.072198 ce: /dev/dri/card0
12639 09:34:41.075025 No KMS driver or no outputs, pipes: 8, outputs: 0
12640 09:34:41.081538 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12641 09:34:41.097963 <14>[ 27.271904] [IGT] kms_vblank: executing
12642 09:34:41.104481 IGT-Version: 1.2<14>[ 27.276975] [IGT] kms_vblank: exiting, ret=77
12643 09:34:41.107844 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12644 09:34:41.111101 Opened device: /dev/dri/card0
12645 09:34:41.120885 No KMS driver or no outputs, pipes: 8, outpu<8>[ 27.292171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12646 09:34:41.121751 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12648 09:34:41.124280 ts: 0
12649 09:34:41.126970 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12650 09:34:41.150192 <14>[ 27.324428] [IGT] kms_vblank: executing
12651 09:34:41.157569 IGT-Version: 1.2<14>[ 27.329838] [IGT] kms_vblank: exiting, ret=77
12652 09:34:41.159765 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12653 09:34:41.170374 Opened device: /dev/dri/car<8>[ 27.341347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12654 09:34:41.170953 d0
12655 09:34:41.171612 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12657 09:34:41.176244 No KMS driver or no outputs, pipes: 8, outputs: 0
12658 09:34:41.180238 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12659 09:34:41.189086 <14>[ 27.363107] [IGT] kms_vblank: executing
12660 09:34:41.195674 IGT-Version: 1.2<14>[ 27.367863] [IGT] kms_vblank: exiting, ret=77
12661 09:34:41.198813 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12662 09:34:41.202514 Opened device: /dev/dri/card0
12663 09:34:41.211946 No KMS driver or no outputs,<8>[ 27.382587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12664 09:34:41.212808 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12666 09:34:41.215985 pipes: 8, outputs: 0
12667 09:34:41.218628 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12668 09:34:41.230257 <14>[ 27.404380] [IGT] kms_vblank: executing
12669 09:34:41.236503 IGT-Version: 1.2<14>[ 27.409107] [IGT] kms_vblank: exiting, ret=77
12670 09:34:41.240054 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12671 09:34:41.249950 Opened devi<8>[ 27.419741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12672 09:34:41.250526 ce: /dev/dri/card0
12673 09:34:41.251182 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12675 09:34:41.256751 No KMS driver or no outputs, pipes: 8, outputs: 0
12676 09:34:41.259486 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12677 09:34:41.266982 <14>[ 27.440698] [IGT] kms_vblank: executing
12678 09:34:41.273700 IGT-Version: 1.2<14>[ 27.445548] [IGT] kms_vblank: exiting, ret=77
12679 09:34:41.276305 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12680 09:34:41.286118 Opened devi<8>[ 27.456173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12681 09:34:41.286974 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12683 09:34:41.289935 ce: /dev/dri/card0
12684 09:34:41.292390 No KMS driver or no outputs, pipes: 8, outputs: 0
12685 09:34:41.299034 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12686 09:34:41.302755 <14>[ 27.477752] [IGT] kms_vblank: executing
12687 09:34:41.308808 IGT-Version: 1.2<14>[ 27.482676] [IGT] kms_vblank: exiting, ret=77
12688 09:34:41.312249 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12689 09:34:41.322176 Opened devi<8>[ 27.493221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12690 09:34:41.322640 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12692 09:34:41.325572 ce: /dev/dri/card0
12693 09:34:41.328847 No KMS driver or no outputs, pipes: 8, outputs: 0
12694 09:34:41.335822 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12695 09:34:41.350121 <14>[ 27.523952] [IGT] kms_vblank: executing
12696 09:34:41.356172 IGT-Version: 1.2<14>[ 27.529084] [IGT] kms_vblank: exiting, ret=77
12697 09:34:41.359371 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12698 09:34:41.369819 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12700 09:34:41.372696 Opened device: /dev/dri/car<8>[ 27.540434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12701 09:34:41.373124 d0
12702 09:34:41.376002 No KMS driver or no outputs, pipes: 8, outputs: 0
12703 09:34:41.382516 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12704 09:34:41.397736 <14>[ 27.572064] [IGT] kms_vblank: executing
12705 09:34:41.404705 IGT-Version: 1.2<14>[ 27.577128] [IGT] kms_vblank: exiting, ret=77
12706 09:34:41.407627 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12707 09:34:41.417508 Opened devi<8>[ 27.588033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12708 09:34:41.418335 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12710 09:34:41.420662 ce: /dev/dri/card0
12711 09:34:41.424043 No KMS driver or no outputs, pipes: 8, outputs: 0
12712 09:34:41.431139 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12713 09:34:41.437865 <14>[ 27.612035] [IGT] kms_vblank: executing
12714 09:34:41.444271 IGT-Version: 1.2<14>[ 27.616810] [IGT] kms_vblank: exiting, ret=77
12715 09:34:41.447969 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12716 09:34:41.457280 Opened devi<8>[ 27.627567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12717 09:34:41.458156 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12719 09:34:41.460477 ce: /dev/dri/card0
12720 09:34:41.463860 No KMS driver or no outputs, pipes: 8, outputs: 0
12721 09:34:41.471083 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12722 09:34:41.478373 <14>[ 27.652168] [IGT] kms_vblank: executing
12723 09:34:41.484915 IGT-Version: 1.2<14>[ 27.656895] [IGT] kms_vblank: exiting, ret=77
12724 09:34:41.488117 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12725 09:34:41.497873 Opened device: /dev/dri/car<8>[ 27.669033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12726 09:34:41.498606 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12728 09:34:41.501361 d0
12729 09:34:41.504109 No KMS driver or no outputs, pipes: 8, outputs: 0
12730 09:34:41.511679 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12731 09:34:41.514643 <14>[ 27.690412] [IGT] kms_vblank: executing
12732 09:34:41.521230 IGT-Version: 1.2<14>[ 27.695167] [IGT] kms_vblank: exiting, ret=77
12733 09:34:41.527523 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12734 09:34:41.528134 Opened device: /dev/dri/card0
12735 09:34:41.537502 No KMS drive<8>[ 27.708204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12736 09:34:41.538400 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12738 09:34:41.544061 r or no outputs, pipes: 8, outputs: 0
12739 09:34:41.547020 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12740 09:34:41.565846 <14>[ 27.739892] [IGT] kms_vblank: executing
12741 09:34:41.572375 IGT-Version: 1.2<14>[ 27.745083] [IGT] kms_vblank: exiting, ret=77
12742 09:34:41.575472 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12743 09:34:41.585027 Opened devi<8>[ 27.755774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12744 09:34:41.585569 ce: /dev/dri/card0
12745 09:34:41.586206 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12747 09:34:41.592408 No KMS driver or no outputs, pipes: 8, outputs: 0
12748 09:34:41.594904 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12749 09:34:41.602381 <14>[ 27.776602] [IGT] kms_vblank: executing
12750 09:34:41.609033 IGT-Version: 1.2<14>[ 27.781363] [IGT] kms_vblank: exiting, ret=77
12751 09:34:41.612131 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12752 09:34:41.622388 Opened devi<8>[ 27.791935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12753 09:34:41.622950 ce: /dev/dri/card0
12754 09:34:41.623666 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12756 09:34:41.625324 No KMS driver or no outputs, pipes: 8, outputs: 0
12757 09:34:41.632367 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12758 09:34:41.638715 <14>[ 27.812178] [IGT] kms_vblank: executing
12759 09:34:41.642024 IGT-Version: 1.2<14>[ 27.816937] [IGT] kms_vblank: exiting, ret=77
12760 09:34:41.648513 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12761 09:34:41.657934 Opened device: /dev/dri/car<8>[ 27.829008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12762 09:34:41.658503 d0
12763 09:34:41.659228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12765 09:34:41.661743 No KMS driver or no outputs, pipes: 8, outputs: 0
12766 09:34:41.668177 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12767 09:34:41.677663 <14>[ 27.851654] [IGT] kms_vblank: executing
12768 09:34:41.683984 IGT-Version: 1.2<14>[ 27.856399] [IGT] kms_vblank: exiting, ret=77
12769 09:34:41.687231 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12770 09:34:41.697585 Opened devi<8>[ 27.867108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12771 09:34:41.698058 ce: /dev/dri/card0
12772 09:34:41.698987 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12774 09:34:41.704088 No KMS driver or no outputs, pipes: 8, outputs: 0
12775 09:34:41.706929 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12776 09:34:41.715691 <14>[ 27.889796] [IGT] kms_vblank: executing
12777 09:34:41.722282 IGT-Version: 1.2<14>[ 27.894687] [IGT] kms_vblank: exiting, ret=77
12778 09:34:41.725429 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12779 09:34:41.735373 Opened devi<8>[ 27.905479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12780 09:34:41.735995 ce: /dev/dri/card0
12781 09:34:41.736651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12783 09:34:41.741878 No KMS driver or no outputs, pipes: 8, outputs: 0
12784 09:34:41.745204 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12785 09:34:41.754428 <14>[ 27.928786] [IGT] kms_vblank: executing
12786 09:34:41.760819 IGT-Version: 1.2<14>[ 27.933508] [IGT] kms_vblank: exiting, ret=77
12787 09:34:41.764284 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12788 09:34:41.774517 Opened device: /dev/dri/car<8>[ 27.945831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12789 09:34:41.775058 d0
12790 09:34:41.775709 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12792 09:34:41.777604 No KMS driver or no outputs, pipes: 8, outputs: 0
12793 09:34:41.784245 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12794 09:34:41.793279 <14>[ 27.967701] [IGT] kms_vblank: executing
12795 09:34:41.800471 IGT-Version: 1.2<14>[ 27.972466] [IGT] kms_vblank: exiting, ret=77
12796 09:34:41.803285 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12797 09:34:41.813351 Opened device: /dev/dri/car<8>[ 27.984157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12798 09:34:41.813908 d0
12799 09:34:41.814566 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12801 09:34:41.820035 No KMS driver or no outputs, pipes: 8, outputs: 0
12802 09:34:41.823025 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12803 09:34:41.840163 <14>[ 28.014451] [IGT] kms_vblank: executing
12804 09:34:41.846907 IGT-Version: 1.2<14>[ 28.019596] [IGT] kms_vblank: exiting, ret=77
12805 09:34:41.850685 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12806 09:34:41.859655 Opened device: /dev/dri/car<8>[ 28.030796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12807 09:34:41.860189 d0
12808 09:34:41.860821 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12810 09:34:41.866445 No KMS driver or no outputs, pipes: 8, outputs: 0
12811 09:34:41.869365 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12812 09:34:41.878926 <14>[ 28.052902] [IGT] kms_vblank: executing
12813 09:34:41.885186 IGT-Version: 1.2<14>[ 28.057651] [IGT] kms_vblank: exiting, ret=77
12814 09:34:41.888218 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12815 09:34:41.892237 Opened device: /dev/dri/card0
12816 09:34:41.901533 No KMS driver or no outputs,<8>[ 28.071594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12817 09:34:41.902241 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12819 09:34:41.904709 pipes: 8, outputs: 0
12820 09:34:41.908022 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12821 09:34:41.921011 <14>[ 28.094829] [IGT] kms_vblank: executing
12822 09:34:41.926871 IGT-Version: 1.2<14>[ 28.099562] [IGT] kms_vblank: exiting, ret=77
12823 09:34:41.930399 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12824 09:34:41.940042 Opened device: /dev/dri/car<8>[ 28.111804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12825 09:34:41.940471 d0
12826 09:34:41.941063 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12828 09:34:41.943804 No KMS driver or no outputs, pipes: 8, outputs: 0
12829 09:34:41.950161 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12830 09:34:41.958199 <14>[ 28.132319] [IGT] kms_vblank: executing
12831 09:34:41.964827 IGT-Version: 1.2<14>[ 28.137067] [IGT] kms_vblank: exiting, ret=77
12832 09:34:41.968097 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12833 09:34:41.977836 Opened devi<8>[ 28.147997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12834 09:34:41.978408 ce: /dev/dri/card0
12835 09:34:41.979062 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12837 09:34:41.984597 No KMS driver or no outputs, pipes: 8, outputs: 0
12838 09:34:41.987539 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12839 09:34:41.998094 <14>[ 28.171601] [IGT] kms_vblank: executing
12840 09:34:42.004272 IGT-Version: 1.2<14>[ 28.176405] [IGT] kms_vblank: exiting, ret=77
12841 09:34:42.007609 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12842 09:34:42.017243 Opened devi<8>[ 28.187203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12843 09:34:42.017810 ce: /dev/dri/card0
12844 09:34:42.018465 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12846 09:34:42.020601 No KMS driver or no outputs, pipes: 8, outputs: 0
12847 09:34:42.027490 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12848 09:34:42.036226 <14>[ 28.209910] [IGT] kms_vblank: executing
12849 09:34:42.042157 IGT-Version: 1.2<14>[ 28.214695] [IGT] kms_vblank: exiting, ret=77
12850 09:34:42.045361 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12851 09:34:42.049302 Opened device: /dev/dri/card0
12852 09:34:42.059074 No KMS driver or no outputs,<8>[ 28.229013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12853 09:34:42.059995 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12855 09:34:42.061865 pipes: 8, outputs: 0
12856 09:34:42.065102 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12857 09:34:42.087109 <14>[ 28.260821] [IGT] kms_vblank: executing
12858 09:34:42.093344 IGT-Version: 1.2<14>[ 28.265899] [IGT] kms_vblank: exiting, ret=77
12859 09:34:42.096370 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12860 09:34:42.106540 Opened device: /dev/dri/car<8>[ 28.277136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12861 09:34:42.107106 d0
12862 09:34:42.107796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12864 09:34:42.109540 No KMS driver or no outputs, pipes: 8, outputs: 0
12865 09:34:42.116287 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12866 09:34:42.126507 <14>[ 28.300797] [IGT] kms_vblank: executing
12867 09:34:42.133423 IGT-Version: 1.2<14>[ 28.305575] [IGT] kms_vblank: exiting, ret=77
12868 09:34:42.136486 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12869 09:34:42.146094 Opened devi<8>[ 28.316201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12870 09:34:42.146649 ce: /dev/dri/card0
12871 09:34:42.147292 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12873 09:34:42.152967 No KMS driver or no outputs, pipes: 8, outputs: 0
12874 09:34:42.156134 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12875 09:34:42.162869 <14>[ 28.336830] [IGT] kms_vblank: executing
12876 09:34:42.169592 IGT-Version: 1.2<14>[ 28.341617] [IGT] kms_vblank: exiting, ret=77
12877 09:34:42.173066 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12878 09:34:42.183756 Opened devi<8>[ 28.352147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12879 09:34:42.184332 ce: /dev/dri/card0
12880 09:34:42.184983 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12882 09:34:42.189713 No KMS driver or no outputs, pipes: 8, outputs: 0
12883 09:34:42.192444 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12884 09:34:42.199054 <14>[ 28.373077] [IGT] kms_vblank: executing
12885 09:34:42.206095 IGT-Version: 1.2<14>[ 28.377825] [IGT] kms_vblank: exiting, ret=77
12886 09:34:42.208782 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12887 09:34:42.212070 Opened device: /dev/dri/card0
12888 09:34:42.222257 No KMS drive<8>[ 28.391160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12889 09:34:42.223253 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12891 09:34:42.225918 r or no outputs, pipes: 8, outputs: 0
12892 09:34:42.228585 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12893 09:34:42.248050 <14>[ 28.422134] [IGT] kms_vblank: executing
12894 09:34:42.255253 IGT-Version: 1.2<14>[ 28.427302] [IGT] kms_vblank: exiting, ret=77
12895 09:34:42.258265 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12896 09:34:42.268116 Opened devi<8>[ 28.438114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12897 09:34:42.268684 ce: /dev/dri/card0
12898 09:34:42.269335 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12900 09:34:42.274461 No KMS driver or no outputs, pipes: 8, outputs: 0
12901 09:34:42.277611 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12902 09:34:42.285575 <14>[ 28.459854] [IGT] kms_vblank: executing
12903 09:34:42.292176 IGT-Version: 1.2<14>[ 28.464676] [IGT] kms_vblank: exiting, ret=77
12904 09:34:42.295452 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12905 09:34:42.305799 Opened devi<8>[ 28.475443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12906 09:34:42.306655 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12908 09:34:42.308410 ce: /dev/dri/card0
12909 09:34:42.311642 No KMS driver or no outputs, pipes: 8, outputs: 0
12910 09:34:42.318283 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12911 09:34:42.325636 <14>[ 28.500200] [IGT] kms_vblank: executing
12912 09:34:42.332322 IGT-Version: 1.2<14>[ 28.505029] [IGT] kms_vblank: exiting, ret=77
12913 09:34:42.335890 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12914 09:34:42.345340 Opened devi<8>[ 28.515405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12915 09:34:42.346168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12917 09:34:42.348801 ce: /dev/dri/card0
12918 09:34:42.352500 No KMS driver or no outputs, pipes: 8, outputs: 0
12919 09:34:42.358793 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12920 09:34:42.362054 <14>[ 28.537015] [IGT] kms_vblank: executing
12921 09:34:42.368646 IGT-Version: 1.2<14>[ 28.541751] [IGT] kms_vblank: exiting, ret=77
12922 09:34:42.371839 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12923 09:34:42.382037 Opened devi<8>[ 28.552090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12924 09:34:42.382882 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12926 09:34:42.385234 ce: /dev/dri/card0
12927 09:34:42.388167 No KMS driver or no outputs, pipes: 8, outputs: 0
12928 09:34:42.395174 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12929 09:34:42.398637 <14>[ 28.573779] [IGT] kms_vblank: executing
12930 09:34:42.404826 IGT-Version: 1.2<14>[ 28.578914] [IGT] kms_vblank: exiting, ret=77
12931 09:34:42.411671 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12932 09:34:42.418373 Opened devi<8>[ 28.589166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12933 09:34:42.419218 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12935 09:34:42.421168 ce: /dev/dri/card0
12936 09:34:42.424485 No KMS driver or no outputs, pipes: 8, outputs: 0
12937 09:34:42.430995 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12938 09:34:42.447578 <14>[ 28.622224] [IGT] kms_vblank: executing
12939 09:34:42.454458 IGT-Version: 1.2<14>[ 28.627205] [IGT] kms_vblank: exiting, ret=77
12940 09:34:42.457825 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12941 09:34:42.461175 Opened device: /dev/dri/card0
12942 09:34:42.474623 No KMS driver or no outputs, pipes: 8, outpu<8>[ 28.642631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12943 09:34:42.475193 ts: 0
12944 09:34:42.475878 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12946 09:34:42.477757 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12947 09:34:42.493073 <14>[ 28.667197] [IGT] kms_vblank: executing
12948 09:34:42.499557 IGT-Version: 1.2<14>[ 28.671946] [IGT] kms_vblank: exiting, ret=77
12949 09:34:42.502783 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12950 09:34:42.512566 Opened device: /dev/dri/car<8>[ 28.684017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12951 09:34:42.513406 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12953 09:34:42.516023 d0
12954 09:34:42.519569 No KMS driver or no outputs, pipes: 8, outputs: 0
12955 09:34:42.525915 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12956 09:34:42.534481 <14>[ 28.708650] [IGT] kms_vblank: executing
12957 09:34:42.541088 IGT-Version: 1.2<14>[ 28.713417] [IGT] kms_vblank: exiting, ret=77
12958 09:34:42.544088 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12959 09:34:42.554307 Opened devi<8>[ 28.724114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12960 09:34:42.555159 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12962 09:34:42.557278 ce: /dev/dri/card0
12963 09:34:42.560749 No KMS driver or no outputs, pipes: 8, outputs: 0
12964 09:34:42.567424 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12965 09:34:42.570854 <14>[ 28.745525] [IGT] kms_vblank: executing
12966 09:34:42.577249 IGT-Version: 1.2<14>[ 28.750530] [IGT] kms_vblank: exiting, ret=77
12967 09:34:42.581272 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12968 09:34:42.590648 Opened devi<8>[ 28.760577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12969 09:34:42.591217 ce: /dev/dri/card0
12970 09:34:42.591900 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12972 09:34:42.597200 No KMS driver or no outputs, pipes: 8, outputs: 0
12973 09:34:42.600477 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12974 09:34:42.617580 <14>[ 28.791537] [IGT] kms_vblank: executing
12975 09:34:42.624156 IGT-Version: 1.2<14>[ 28.796643] [IGT] kms_vblank: exiting, ret=77
12976 09:34:42.627251 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12977 09:34:42.630669 Opened device: /dev/dri/card0
12978 09:34:42.640931 No KMS driver or no outputs,<8>[ 28.811593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12979 09:34:42.641504 pipes: 8, outputs: 0
12980 09:34:42.642158 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12982 09:34:42.646685 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12983 09:34:42.659332 <14>[ 28.833142] [IGT] kms_vblank: executing
12984 09:34:42.665599 IGT-Version: 1.2<14>[ 28.837899] [IGT] kms_vblank: exiting, ret=77
12985 09:34:42.668756 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12986 09:34:42.678822 Opened devi<8>[ 28.848582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12987 09:34:42.679393 ce: /dev/dri/card0
12988 09:34:42.680093 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12990 09:34:42.685250 No KMS driver or no outputs, pipes: 8, outputs: 0
12991 09:34:42.688070 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12992 09:34:42.695113 <14>[ 28.869300] [IGT] kms_vblank: executing
12993 09:34:42.701510 IGT-Version: 1.2<14>[ 28.874077] [IGT] kms_vblank: exiting, ret=77
12994 09:34:42.704603 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
12995 09:34:42.715016 Opened devi<8>[ 28.884751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12996 09:34:42.715580 ce: /dev/dri/card0
12997 09:34:42.716293 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12999 09:34:42.722055 No KMS driver or no outputs, pipes: 8, outputs: 0
13000 09:34:42.724858 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
13001 09:34:42.731423 <14>[ 28.905051] [IGT] kms_vblank: executing
13002 09:34:42.737917 IGT-Version: 1.2<14>[ 28.909820] [IGT] kms_vblank: exiting, ret=77
13003 09:34:42.741062 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13004 09:34:42.744609 Opened device: /dev/dri/card0
13005 09:34:42.754600 No KMS driver or no outputs,<8>[ 28.924364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
13006 09:34:42.755452 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
13008 09:34:42.757409 pipes: 8, outputs: 0
13009 09:34:42.760816 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
13010 09:34:42.781830 <14>[ 28.955954] [IGT] kms_vblank: executing
13011 09:34:42.787966 IGT-Version: 1.2<14>[ 28.961123] [IGT] kms_vblank: exiting, ret=77
13012 09:34:42.791448 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13013 09:34:42.801495 Opened device: /dev/dri/car<8>[ 28.972505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
13014 09:34:42.802074 d0
13015 09:34:42.802763 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
13017 09:34:42.807890 No KMS driver or no outputs, pipes: 8, outputs: 0
13018 09:34:42.811055 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
13019 09:34:42.819605 <14>[ 28.993882] [IGT] kms_vblank: executing
13020 09:34:42.826129 IGT-Version: 1.2<14>[ 28.998877] [IGT] kms_vblank: exiting, ret=77
13021 09:34:42.829308 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13022 09:34:42.839397 Opened devi<8>[ 29.009284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
13023 09:34:42.839995 ce: /dev/dri/card0
13024 09:34:42.840638 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
13026 09:34:42.845977 No KMS driver or no outputs, pipes: 8, outputs: 0
13027 09:34:42.849242 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
13028 09:34:42.866121 <14>[ 29.039868] [IGT] kms_vblank: executing
13029 09:34:42.872316 IGT-Version: 1.2<14>[ 29.044926] [IGT] kms_vblank: exiting, ret=77
13030 09:34:42.876139 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13031 09:34:42.885688 Opened device: /dev/dri/car<8>[ 29.056302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
13032 09:34:42.886277 d0
13033 09:34:42.887060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
13035 09:34:42.892187 No KMS driver or no outputs, pipes: 8, outputs: 0
13036 09:34:42.895228 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
13037 09:34:42.905924 <14>[ 29.079789] [IGT] kms_vblank: executing
13038 09:34:42.912055 IGT-Version: 1.2<14>[ 29.084582] [IGT] kms_vblank: exiting, ret=77
13039 09:34:42.915715 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13040 09:34:42.924900 Opened devi<8>[ 29.095166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
13041 09:34:42.925387 ce: /dev/dri/card0
13042 09:34:42.926157 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
13044 09:34:42.931705 No KMS driver or no outputs, pipes: 8, outputs: 0
13045 09:34:42.935016 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
13046 09:34:42.943707 <14>[ 29.117610] [IGT] kms_vblank: executing
13047 09:34:42.950039 IGT-Version: 1.2<14>[ 29.122647] [IGT] kms_vblank: exiting, ret=77
13048 09:34:42.953025 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13049 09:34:42.963463 Opened devi<8>[ 29.133076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
13050 09:34:42.964004 ce: /dev/dri/card0
13051 09:34:42.964771 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
13053 09:34:42.969302 No KMS driver or no outputs, pipes: 8, outputs: 0
13054 09:34:42.972827 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
13055 09:34:42.979405 <14>[ 29.153210] [IGT] kms_vblank: executing
13056 09:34:42.982881 IGT-Version: 1.2<14>[ 29.157942] [IGT] kms_vblank: exiting, ret=77
13057 09:34:42.989317 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13058 09:34:42.996375 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13060 09:34:42.998962 Opened devi<8>[ 29.168830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
13061 09:34:42.999468 ce: /dev/dri/card0
13062 09:34:43.002488 No KMS driver or no outputs, pipes: 8, outputs: 0
13063 09:34:43.009049 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13064 09:34:43.016538 <14>[ 29.191312] [IGT] kms_vblank: executing
13065 09:34:43.023308 IGT-Version: 1.2<14>[ 29.196129] [IGT] kms_vblank: exiting, ret=77
13066 09:34:43.026842 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13067 09:34:43.036420 Opened device: /dev/dri/car<8>[ 29.208226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13068 09:34:43.036854 d0
13069 09:34:43.037447 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13071 09:34:43.043077 No KMS driver or no outputs, pipes: 8, outputs: 0
13072 09:34:43.046581 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13073 09:34:43.056792 <14>[ 29.231573] [IGT] kms_vblank: executing
13074 09:34:43.063697 IGT-Version: 1.2<14>[ 29.236424] [IGT] kms_vblank: exiting, ret=77
13075 09:34:43.067019 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13076 09:34:43.077375 Opened devi<8>[ 29.247241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13077 09:34:43.077801 ce: /dev/dri/card0
13078 09:34:43.078531 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13080 09:34:43.083548 No KMS driver or no outputs, pipes: 8, outputs: 0
13081 09:34:43.086771 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13082 09:34:43.095689 <14>[ 29.270442] [IGT] kms_vblank: executing
13083 09:34:43.101938 IGT-Version: 1.2<14>[ 29.275199] [IGT] kms_vblank: exiting, ret=77
13084 09:34:43.105358 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13085 09:34:43.115311 Opened devi<8>[ 29.285511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13086 09:34:43.115396 ce: /dev/dri/card0
13087 09:34:43.115634 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13089 09:34:43.118551 No KMS driver or no outputs, pipes: 8, outputs: 0
13090 09:34:43.125047 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13091 09:34:43.141119 <14>[ 29.315704] [IGT] kms_vblank: executing
13092 09:34:43.148376 IGT-Version: 1.2<14>[ 29.321029] [IGT] kms_vblank: exiting, ret=77
13093 09:34:43.151508 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13094 09:34:43.154346 Opened device: /dev/dri/card0
13095 09:34:43.164482 No KMS driver or no outputs,<8>[ 29.335644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13096 09:34:43.165168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13098 09:34:43.167506 pipes: 8, outputs: 0
13099 09:34:43.171066 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13100 09:34:43.184538 <14>[ 29.358895] [IGT] kms_vblank: executing
13101 09:34:43.191112 IGT-Version: 1.2<14>[ 29.363657] [IGT] kms_vblank: exiting, ret=77
13102 09:34:43.194640 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13103 09:34:43.204236 Opened devi<8>[ 29.374711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13104 09:34:43.204772 ce: /dev/dri/card0
13105 09:34:43.205579 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13107 09:34:43.210539 No KMS driver or no outputs, pipes: 8, outputs: 0
13108 09:34:43.214106 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13109 09:34:43.220595 <14>[ 29.394659] [IGT] kms_vblank: executing
13110 09:34:43.227525 IGT-Version: 1.2<14>[ 29.399540] [IGT] kms_vblank: exiting, ret=77
13111 09:34:43.230495 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13112 09:34:43.241036 Opened devi<8>[ 29.410372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13113 09:34:43.241571 ce: /dev/dri/card0
13114 09:34:43.242178 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13116 09:34:43.246797 No KMS driver or no outputs, pipes: 8, outputs: 0
13117 09:34:43.250508 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13118 09:34:43.256906 <14>[ 29.431619] [IGT] kms_vblank: executing
13119 09:34:43.263762 IGT-Version: 1.2<14>[ 29.436370] [IGT] kms_vblank: exiting, ret=77
13120 09:34:43.267315 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13121 09:34:43.277055 Opened devi<8>[ 29.447268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13122 09:34:43.277622 ce: /dev/dri/card0
13123 09:34:43.278270 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13125 09:34:43.283369 No KMS driver or no outputs, pipes: 8, outputs: 0
13126 09:34:43.287386 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13127 09:34:43.309989 <14>[ 29.484369] [IGT] kms_vblank: executing
13128 09:34:43.316612 IGT-Version: 1.2<14>[ 29.489433] [IGT] kms_vblank: exiting, ret=77
13129 09:34:43.319623 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13130 09:34:43.322946 Opened device: /dev/dri/card0
13131 09:34:43.333043 No KMS driver or no outputs,<8>[ 29.504235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13132 09:34:43.333740 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13134 09:34:43.336379 pipes: 8, outputs: 0
13135 09:34:43.343036 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13136 09:34:43.353232 <14>[ 29.527077] [IGT] kms_vblank: executing
13137 09:34:43.359399 IGT-Version: 1.2<14>[ 29.531863] [IGT] kms_vblank: exiting, ret=77
13138 09:34:43.362312 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13139 09:34:43.373011 Opened devi<8>[ 29.542854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13140 09:34:43.373802 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13142 09:34:43.375454 ce: /dev/dri/card0
13143 09:34:43.379125 No KMS driver or no outputs, pipes: 8, outputs: 0
13144 09:34:43.385680 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13145 09:34:43.388727 <14>[ 29.563757] [IGT] kms_vblank: executing
13146 09:34:43.395787 IGT-Version: 1.2<14>[ 29.568503] [IGT] kms_vblank: exiting, ret=77
13147 09:34:43.399012 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13148 09:34:43.408572 Opened devi<8>[ 29.579665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13149 09:34:43.409406 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13151 09:34:43.412456 ce: /dev/dri/card0
13152 09:34:43.415118 No KMS driver or no outputs, pipes: 8, outputs: 0
13153 09:34:43.422110 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13154 09:34:43.425606 <14>[ 29.601016] [IGT] kms_vblank: executing
13155 09:34:43.431427 IGT-Version: 1.2<14>[ 29.605929] [IGT] kms_vblank: exiting, ret=77
13156 09:34:43.438663 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13157 09:34:43.445648 Opened devi<8>[ 29.616849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13158 09:34:43.446506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13160 09:34:43.447818 ce: /dev/dri/card0
13161 09:34:43.451512 No KMS driver or no outputs, pipes: 8, outputs: 0
13162 09:34:43.458398 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13163 09:34:43.473319 <14>[ 29.647529] [IGT] kms_vblank: executing
13164 09:34:43.479554 IGT-Version: 1.2<14>[ 29.652602] [IGT] kms_vblank: exiting, ret=77
13165 09:34:43.483158 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13166 09:34:43.486552 Opened device: /dev/dri/card0
13167 09:34:43.499380 No KMS driver or no outputs, pipes: 8, outpu<8>[ 29.667758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13168 09:34:43.500011 ts: 0
13169 09:34:43.500680 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13171 09:34:43.505812 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13172 09:34:43.517425 <14>[ 29.691995] [IGT] kms_vblank: executing
13173 09:34:43.524361 IGT-Version: 1.2<14>[ 29.696768] [IGT] kms_vblank: exiting, ret=77
13174 09:34:43.527701 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13175 09:34:43.537654 Opened devi<8>[ 29.707562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13176 09:34:43.538502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13178 09:34:43.541077 ce: /dev/dri/card0
13179 09:34:43.544082 No KMS driver or no outputs, pipes: 8, outputs: 0
13180 09:34:43.550437 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13181 09:34:43.553949 <14>[ 29.728964] [IGT] kms_vblank: executing
13182 09:34:43.560658 IGT-Version: 1.2<14>[ 29.734043] [IGT] kms_vblank: exiting, ret=77
13183 09:34:43.563560 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13184 09:34:43.573870 Opened devi<8>[ 29.744947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13185 09:34:43.574721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13187 09:34:43.576992 ce: /dev/dri/card0
13188 09:34:43.579947 No KMS driver or no outputs, pipes: 8, outputs: 0
13189 09:34:43.586965 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13190 09:34:43.594203 <14>[ 29.768746] [IGT] kms_vblank: executing
13191 09:34:43.600873 IGT-Version: 1.2<14>[ 29.773509] [IGT] kms_vblank: exiting, ret=77
13192 09:34:43.604352 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13193 09:34:43.613851 Opened device: /dev/dri/car<8>[ 29.785530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13194 09:34:43.614401 d0
13195 09:34:43.615049 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13197 09:34:43.621108 No KMS driver or no outputs, pipes: 8, outputs: 0
13198 09:34:43.624435 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13199 09:34:43.641494 <14>[ 29.815704] [IGT] kms_vblank: executing
13200 09:34:43.647910 IGT-Version: 1.2<14>[ 29.820933] [IGT] kms_vblank: exiting, ret=77
13201 09:34:43.650936 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13202 09:34:43.661586 Opened devi<8>[ 29.831931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13203 09:34:43.662159 ce: /dev/dri/card0
13204 09:34:43.662903 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13206 09:34:43.667916 No KMS driver or no outputs, pipes: 8, outputs: 0
13207 09:34:43.670867 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13208 09:34:43.677654 <14>[ 29.852091] [IGT] kms_vblank: executing
13209 09:34:43.684189 IGT-Version: 1.2<14>[ 29.856849] [IGT] kms_vblank: exiting, ret=77
13210 09:34:43.687867 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13211 09:34:43.697664 Opened devi<8>[ 29.867470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13212 09:34:43.698232 ce: /dev/dri/card0
13213 09:34:43.698878 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13215 09:34:43.703970 No KMS driver or no outputs, pipes: 8, outputs: 0
13216 09:34:43.706887 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13217 09:34:43.713719 <14>[ 29.888231] [IGT] kms_vblank: executing
13218 09:34:43.720152 IGT-Version: 1.2<14>[ 29.893102] [IGT] kms_vblank: exiting, ret=77
13219 09:34:43.723770 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13220 09:34:43.727145 Opened device: /dev/dri/card0
13221 09:34:43.734426 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13223 09:34:43.736970 No KMS drive<8>[ 29.906940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13224 09:34:43.740156 r or no outputs, pipes: 8, outputs: 0
13225 09:34:43.743229 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13226 09:34:43.753991 <14>[ 29.928582] [IGT] kms_vblank: executing
13227 09:34:43.760940 IGT-Version: 1.2<14>[ 29.933344] [IGT] kms_vblank: exiting, ret=77
13228 09:34:43.763911 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13229 09:34:43.767642 Opened device: /dev/dri/card0
13230 09:34:43.777095 No KMS driver or no outputs,<8>[ 29.947870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13231 09:34:43.777948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13233 09:34:43.780626 pipes: 8, outputs: 0
13234 09:34:43.784090 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13235 09:34:43.804548 <14>[ 29.978844] [IGT] kms_vblank: executing
13236 09:34:43.811151 IGT-Version: 1.2<14>[ 29.984019] [IGT] kms_vblank: exiting, ret=77
13237 09:34:43.814575 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13238 09:34:43.824128 Opened device: /dev/dri/car<8>[ 29.995399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13239 09:34:43.824684 d0
13240 09:34:43.825324 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13242 09:34:43.831201 No KMS driver or no outputs, pipes: 8, outputs: 0
13243 09:34:43.833923 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13244 09:34:43.851317 <14>[ 30.025670] [IGT] kms_vblank: executing
13245 09:34:43.857735 IGT-Version: 1.2<14>[ 30.031019] [IGT] kms_vblank: exiting, ret=77
13246 09:34:43.861189 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13247 09:34:43.871374 Opened device: /dev/dri/car<8>[ 30.042880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13248 09:34:43.871984 d0
13249 09:34:43.872630 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13251 09:34:43.877337 No KMS driver or no outputs, pipes: 8, outputs: 0
13252 09:34:43.880297 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13253 09:34:43.890800 <14>[ 30.065878] [IGT] kms_vblank: executing
13254 09:34:43.897412 IGT-Version: 1.2<14>[ 30.070708] [IGT] kms_vblank: exiting, ret=77
13255 09:34:43.901113 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13256 09:34:43.910548 Opened devi<8>[ 30.081138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13257 09:34:43.910633 ce: /dev/dri/card0
13258 09:34:43.910870 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13260 09:34:43.917332 No KMS driver or no outputs, pipes: 8, outputs: 0
13261 09:34:43.920622 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13262 09:34:43.927211 <14>[ 30.102286] [IGT] kms_vblank: executing
13263 09:34:43.933970 IGT-Version: 1.2<14>[ 30.107099] [IGT] kms_vblank: exiting, ret=77
13264 09:34:43.937395 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13265 09:34:43.947168 Opened devi<8>[ 30.117696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13266 09:34:43.947250 ce: /dev/dri/card0
13267 09:34:43.947485 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13269 09:34:43.954083 No KMS driver or no outputs, pipes: 8, outputs: 0
13270 09:34:43.957581 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13271 09:34:43.963839 <14>[ 30.138712] [IGT] kms_vblank: executing
13272 09:34:43.970841 IGT-Version: 1.2<14>[ 30.143469] [IGT] kms_vblank: exiting, ret=77
13273 09:34:43.973444 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13274 09:34:43.983788 Opened device: /dev/dri/car<8>[ 30.155749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13275 09:34:43.983874 d0
13276 09:34:43.984114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13278 09:34:43.986932 No KMS driver or no outputs, pipes: 8, outputs: 0
13279 09:34:43.993670 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13280 09:34:44.012060 <14>[ 30.186520] [IGT] kms_vblank: executing
13281 09:34:44.019075 IGT-Version: 1.2<14>[ 30.191693] [IGT] kms_vblank: exiting, ret=77
13282 09:34:44.022205 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13283 09:34:44.031914 Opened device: /dev/dri/car<8>[ 30.203107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13284 09:34:44.032454 d0
13285 09:34:44.033072 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13287 09:34:44.038651 No KMS driver or no outputs, pipes: 8, outputs: 0
13288 09:34:44.041515 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13289 09:34:44.053052 <14>[ 30.227344] [IGT] kms_vblank: executing
13290 09:34:44.059472 IGT-Version: 1.2<14>[ 30.232183] [IGT] kms_vblank: exiting, ret=77
13291 09:34:44.062679 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13292 09:34:44.072740 Opened device: /dev/dri/car<8>[ 30.243690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13293 09:34:44.073373 d0
13294 09:34:44.074090 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13296 09:34:44.079229 No KMS driver or no outputs, pipes: 8, outputs: 0
13297 09:34:44.082488 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13298 09:34:44.092657 <14>[ 30.267425] [IGT] kms_vblank: executing
13299 09:34:44.099790 IGT-Version: 1.2<14>[ 30.272241] [IGT] kms_vblank: exiting, ret=77
13300 09:34:44.103039 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13301 09:34:44.113060 Opened device: /dev/dri/car<8>[ 30.283729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13302 09:34:44.113528 d0
13303 09:34:44.114309 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13305 09:34:44.119237 No KMS driver or no outputs, pipes: 8, outputs: 0
13306 09:34:44.122481 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13307 09:34:44.139219 <14>[ 30.313892] [IGT] kms_vblank: executing
13308 09:34:44.145934 IGT-Version: 1.2<14>[ 30.319054] [IGT] kms_vblank: exiting, ret=77
13309 09:34:44.149284 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13310 09:34:44.159507 Opened device: /dev/dri/car<8>[ 30.330247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13311 09:34:44.160001 d0
13312 09:34:44.160716 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13314 09:34:44.165599 No KMS driver or no outputs, pipes: 8, outputs: 0
13315 09:34:44.168880 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13316 09:34:44.176753 <14>[ 30.351490] [IGT] kms_vblank: executing
13317 09:34:44.184303 IGT-Version: 1.2<14>[ 30.356229] [IGT] kms_vblank: exiting, ret=77
13318 09:34:44.187001 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13319 09:34:44.196631 Opened devi<8>[ 30.366482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13320 09:34:44.197071 ce: /dev/dri/card0
13321 09:34:44.197672 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13323 09:34:44.203422 No KMS driver or no outputs, pipes: 8, outputs: 0
13324 09:34:44.206609 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13325 09:34:44.209844 <14>[ 30.386764] [IGT] kms_vblank: executing
13326 09:34:44.216242 IGT-Version: 1.2<14>[ 30.391559] [IGT] kms_vblank: exiting, ret=77
13327 09:34:44.222998 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13328 09:34:44.233325 Opened device: /dev/dri/car<8>[ 30.403615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13329 09:34:44.233825 d0
13330 09:34:44.234434 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13332 09:34:44.236298 No KMS driver or no outputs, pipes: 8, outputs: 0
13333 09:34:44.243314 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13334 09:34:44.259527 <14>[ 30.433975] [IGT] kms_vblank: executing
13335 09:34:44.266488 IGT-Version: 1.2<14>[ 30.439213] [IGT] kms_vblank: exiting, ret=77
13336 09:34:44.269552 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13337 09:34:44.279480 Opened device: /dev/dri/car<8>[ 30.450679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13338 09:34:44.280350 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13340 09:34:44.282209 d0
13341 09:34:44.285649 No KMS driver or no outputs, pipes: 8, outputs: 0
13342 09:34:44.288966 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13343 09:34:44.300119 <14>[ 30.474413] [IGT] kms_vblank: executing
13344 09:34:44.306460 IGT-Version: 1.2<14>[ 30.479184] [IGT] kms_vblank: exiting, ret=77
13345 09:34:44.309837 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13346 09:34:44.319664 Opened devi<8>[ 30.489501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13347 09:34:44.320281 ce: /dev/dri/card0
13348 09:34:44.320938 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13350 09:34:44.326224 No KMS driver or no outputs, pipes: 8, outputs: 0
13351 09:34:44.329875 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13352 09:34:44.336102 <14>[ 30.510811] [IGT] kms_vblank: executing
13353 09:34:44.343046 IGT-Version: 1.2<14>[ 30.515555] [IGT] kms_vblank: exiting, ret=77
13354 09:34:44.346057 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13355 09:34:44.356392 Opened devi<8>[ 30.526414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13356 09:34:44.357260 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13358 09:34:44.359153 ce: /dev/dri/card0
13359 09:34:44.363052 No KMS driver or no outputs, pipes: 8, outputs: 0
13360 09:34:44.369573 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13361 09:34:44.373089 <14>[ 30.547481] [IGT] kms_vblank: executing
13362 09:34:44.379891 IGT-Version: 1.2<14>[ 30.552263] [IGT] kms_vblank: exiting, ret=77
13363 09:34:44.383653 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13364 09:34:44.392638 Opened devi<8>[ 30.563267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13365 09:34:44.393481 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13367 09:34:44.395422 ce: /dev/dri/card0
13368 09:34:44.399341 No KMS driver or no outputs, pipes: 8, outputs: 0
13369 09:34:44.407105 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13370 09:34:44.419843 <14>[ 30.593896] [IGT] kms_vblank: executing
13371 09:34:44.426235 IGT-Version: 1.2<14>[ 30.599055] [IGT] kms_vblank: exiting, ret=77
13372 09:34:44.429425 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13373 09:34:44.439331 Opened devi<8>[ 30.609941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13374 09:34:44.440228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13376 09:34:44.442328 ce: /dev/dri/card0
13377 09:34:44.445549 No KMS driver or no outputs, pipes: 8, outputs: 0
13378 09:34:44.452420 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13379 09:34:44.455919 <14>[ 30.631723] [IGT] kms_vblank: executing
13380 09:34:44.462387 IGT-Version: 1.2<14>[ 30.636470] [IGT] kms_vblank: exiting, ret=77
13381 09:34:44.469148 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13382 09:34:44.479048 Opened device: /dev/dri/car<8>[ 30.648228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13383 09:34:44.479610 d0
13384 09:34:44.480319 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13386 09:34:44.481533 No KMS driver or no outputs, pipes: 8, outputs: 0
13387 09:34:44.488668 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13388 09:34:44.496112 <14>[ 30.670774] [IGT] kms_vblank: executing
13389 09:34:44.502794 IGT-Version: 1.2<14>[ 30.675504] [IGT] kms_vblank: exiting, ret=77
13390 09:34:44.506050 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13391 09:34:44.509408 Opened device: /dev/dri/card0
13392 09:34:44.519421 No KMS drive<8>[ 30.688538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13393 09:34:44.520315 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13395 09:34:44.522411 r or no outputs, pipes: 8, outputs: 0
13396 09:34:44.529293 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13397 09:34:44.545751 <14>[ 30.720036] [IGT] kms_vblank: executing
13398 09:34:44.552085 IGT-Version: 1.2<14>[ 30.725263] [IGT] kms_vblank: exiting, ret=77
13399 09:34:44.555589 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13400 09:34:44.565502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13402 09:34:44.568335 Opened device: /dev/dri/car<8>[ 30.736230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13403 09:34:44.568802 d0
13404 09:34:44.571682 No KMS driver or no outputs, pipes: 8, outputs: 0
13405 09:34:44.578584 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13406 09:34:44.585435 <14>[ 30.758903] [IGT] kms_vblank: executing
13407 09:34:44.588603 IGT-Version: 1.2<14>[ 30.763626] [IGT] kms_vblank: exiting, ret=77
13408 09:34:44.595041 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13409 09:34:44.605018 Opened devi<8>[ 30.774412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13410 09:34:44.605580 ce: /dev/dri/card0
13411 09:34:44.606232 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13413 09:34:44.611088 No KMS driver or no outputs, pipes: 8, outputs: 0
13414 09:34:44.617876 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13415 09:34:44.621356 <14>[ 30.795715] [IGT] kms_vblank: executing
13416 09:34:44.627899 IGT-Version: 1.2<14>[ 30.800669] [IGT] kms_vblank: exiting, ret=77
13417 09:34:44.631487 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13418 09:34:44.634540 Opened device: /dev/dri/card0
13419 09:34:44.644927 No KMS driver or no outputs,<8>[ 30.815404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13420 09:34:44.645779 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13422 09:34:44.647478 pipes: 8, outputs: 0
13423 09:34:44.651239 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13424 09:34:44.662153 <14>[ 30.836797] [IGT] kms_vblank: executing
13425 09:34:44.668985 IGT-Version: 1.2<14>[ 30.841528] [IGT] kms_vblank: exiting, ret=77
13426 09:34:44.672136 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13427 09:34:44.681732 Opened devi<8>[ 30.852304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13428 09:34:44.682213 ce: /dev/dri/card0
13429 09:34:44.682851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13431 09:34:44.685267 No KMS driver or no outputs, pipes: 8, outputs: 0
13432 09:34:44.692032 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13433 09:34:44.698708 <14>[ 30.872593] [IGT] kms_vblank: executing
13434 09:34:44.704746 IGT-Version: 1.2<14>[ 30.877352] [IGT] kms_vblank: exiting, ret=77
13435 09:34:44.708364 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13436 09:34:44.718210 Opened devi<8>[ 30.888231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13437 09:34:44.718778 ce: /dev/dri/card0
13438 09:34:44.719430 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13440 09:34:44.724497 No KMS driver or no outputs, pipes: 8, outputs: 0
13441 09:34:44.728108 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13442 09:34:44.734976 <14>[ 30.909253] [IGT] kms_vblank: executing
13443 09:34:44.741416 IGT-Version: 1.2<14>[ 30.914168] [IGT] kms_vblank: exiting, ret=77
13444 09:34:44.744488 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13445 09:34:44.747632 Opened device: /dev/dri/card0
13446 09:34:44.758217 No KMS driver or no outputs,<8>[ 30.928416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13447 09:34:44.759095 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13449 09:34:44.761437 pipes: 8, outputs: 0
13450 09:34:44.764712 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13451 09:34:44.785232 <14>[ 30.959985] [IGT] kms_vblank: executing
13452 09:34:44.792385 IGT-Version: 1.2<14>[ 30.965115] [IGT] kms_vblank: exiting, ret=77
13453 09:34:44.795391 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13454 09:34:44.798440 Opened device: /dev/dri/card0
13455 09:34:44.808697 No KMS driver or no outputs,<8>[ 30.979425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13456 09:34:44.809551 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13458 09:34:44.811524 pipes: 8, outputs: 0
13459 09:34:44.814820 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13460 09:34:44.828134 <14>[ 31.002738] [IGT] kms_vblank: executing
13461 09:34:44.835070 IGT-Version: 1.2<14>[ 31.007491] [IGT] kms_vblank: exiting, ret=77
13462 09:34:44.837875 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13463 09:34:44.848014 Opened devi<8>[ 31.018284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13464 09:34:44.848608 ce: /dev/dri/card0
13465 09:34:44.849260 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13467 09:34:44.851265 No KMS driver or no outputs, pipes: 8, outputs: 0
13468 09:34:44.857557 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13469 09:34:44.866689 <14>[ 31.040994] [IGT] kms_vblank: executing
13470 09:34:44.873044 IGT-Version: 1.2<14>[ 31.045735] [IGT] kms_vblank: exiting, ret=77
13471 09:34:44.876451 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13472 09:34:44.886509 Opened devi<8>[ 31.056448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13473 09:34:44.887074 ce: /dev/dri/card0
13474 09:34:44.887764 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13476 09:34:44.892950 No KMS driver or no outputs, pipes: 8, outputs: 0
13477 09:34:44.896214 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13478 09:34:44.902701 <14>[ 31.077201] [IGT] kms_vblank: executing
13479 09:34:44.909926 IGT-Version: 1.2<14>[ 31.081940] [IGT] kms_vblank: exiting, ret=77
13480 09:34:44.913030 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13481 09:34:44.922567 Opened device: /dev/dri/car<8>[ 31.093220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13482 09:34:44.923168 d0
13483 09:34:44.923865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13485 09:34:44.929287 No KMS driver or no outputs, pipes: 8, outputs: 0
13486 09:34:44.931893 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13487 09:34:44.950303 <14>[ 31.124419] [IGT] kms_vblank: executing
13488 09:34:44.957161 IGT-Version: 1.2<14>[ 31.129534] [IGT] kms_vblank: exiting, ret=77
13489 09:34:44.960280 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13490 09:34:44.970306 Opened devi<8>[ 31.140472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13491 09:34:44.970883 ce: /dev/dri/card0
13492 09:34:44.971544 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13494 09:34:44.976287 No KMS driver or no outputs, pipes: 8, outputs: 0
13495 09:34:44.979714 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13496 09:34:44.987417 <14>[ 31.161888] [IGT] kms_vblank: executing
13497 09:34:44.994125 IGT-Version: 1.2<14>[ 31.166633] [IGT] kms_vblank: exiting, ret=77
13498 09:34:44.996799 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13499 09:34:45.006802 Opened devi<8>[ 31.177382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13500 09:34:45.007389 ce: /dev/dri/card0
13501 09:34:45.008082 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13503 09:34:45.013631 No KMS driver or no outputs, pipes: 8, outputs: 0
13504 09:34:45.016695 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13505 09:34:45.023343 <14>[ 31.197234] [IGT] kms_vblank: executing
13506 09:34:45.027097 IGT-Version: 1.2<14>[ 31.201961] [IGT] kms_vblank: exiting, ret=77
13507 09:34:45.033284 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13508 09:34:45.043165 Opened device: /dev/dri/car<8>[ 31.214203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13509 09:34:45.043779 d0
13510 09:34:45.044453 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13512 09:34:45.046333 No KMS driver or no outputs, pipes: 8, outputs: 0
13513 09:34:45.052942 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13514 09:34:45.062133 <14>[ 31.236207] [IGT] kms_vblank: executing
13515 09:34:45.068213 IGT-Version: 1.2<14>[ 31.240967] [IGT] kms_vblank: exiting, ret=77
13516 09:34:45.071689 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13517 09:34:45.081497 Opened device: /dev/dri/car<8>[ 31.253075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13518 09:34:45.082132 d0
13519 09:34:45.082786 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13521 09:34:45.084432 No KMS driver or no outputs, pipes: 8, outputs: 0
13522 09:34:45.091331 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13523 09:34:45.100930 <14>[ 31.275178] [IGT] kms_vblank: executing
13524 09:34:45.107352 IGT-Version: 1.2<14>[ 31.279953] [IGT] kms_vblank: exiting, ret=77
13525 09:34:45.110343 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13526 09:34:45.120319 Opened devi<8>[ 31.290818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13527 09:34:45.120782 ce: /dev/dri/card0
13528 09:34:45.121417 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13530 09:34:45.127131 No KMS driver or no outputs, pipes: 8, outputs: 0
13531 09:34:45.130204 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13532 09:34:45.138721 <14>[ 31.313501] [IGT] kms_vblank: executing
13533 09:34:45.145732 IGT-Version: 1.2<14>[ 31.318340] [IGT] kms_vblank: exiting, ret=77
13534 09:34:45.149016 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13535 09:34:45.155602 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13537 09:34:45.158622 Opened devi<8>[ 31.328903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13538 09:34:45.159087 ce: /dev/dri/card0
13539 09:34:45.161968 No KMS driver or no outputs, pipes: 8, outputs: 0
13540 09:34:45.168412 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13541 09:34:45.184110 <14>[ 31.358794] [IGT] kms_vblank: executing
13542 09:34:45.190773 IGT-Version: 1.2<14>[ 31.363863] [IGT] kms_vblank: exiting, ret=77
13543 09:34:45.194275 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13544 09:34:45.204690 Opened device: /dev/dri/car<8>[ 31.375073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13545 09:34:45.205268 d0
13546 09:34:45.205926 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13548 09:34:45.210660 No KMS driver or no outputs, pipes: 8, outputs: 0
13549 09:34:45.214443 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13550 09:34:45.230094 <14>[ 31.404552] [IGT] kms_vblank: executing
13551 09:34:45.236537 IGT-Version: 1.2<14>[ 31.409652] [IGT] kms_vblank: exiting, ret=77
13552 09:34:45.240049 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13553 09:34:45.249817 Opened device: /dev/dri/car<8>[ 31.421452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13554 09:34:45.250377 d0
13555 09:34:45.251093 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13557 09:34:45.256510 No KMS driver or no outputs, pipes: 8, outputs: 0
13558 09:34:45.259584 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13559 09:34:45.270408 <14>[ 31.444994] [IGT] kms_vblank: executing
13560 09:34:45.277273 IGT-Version: 1.2<14>[ 31.449741] [IGT] kms_vblank: exiting, ret=77
13561 09:34:45.280395 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13562 09:34:45.290058 Opened devi<8>[ 31.460444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13563 09:34:45.290156 ce: /dev/dri/card0
13564 09:34:45.290413 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13566 09:34:45.296107 No KMS driver or no outputs, pipes: 8, outputs: 0
13567 09:34:45.299973 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13568 09:34:45.306723 <14>[ 31.481720] [IGT] kms_vblank: executing
13569 09:34:45.313204 IGT-Version: 1.2<14>[ 31.486596] [IGT] kms_vblank: exiting, ret=77
13570 09:34:45.316239 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13571 09:34:45.326115 Opened device: /dev/dri/car<8>[ 31.498522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13572 09:34:45.326198 d0
13573 09:34:45.326438 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13575 09:34:45.332797 No KMS driver or no outputs, pipes: 8, outputs: 0
13576 09:34:45.336119 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13577 09:34:45.346980 <14>[ 31.522029] [IGT] kms_vblank: executing
13578 09:34:45.353487 IGT-Version: 1.2<14>[ 31.526794] [IGT] kms_vblank: exiting, ret=77
13579 09:34:45.356609 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13580 09:34:45.366702 Opened device: /dev/dri/car<8>[ 31.538636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13581 09:34:45.366958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13583 09:34:45.370062 d0
13584 09:34:45.373493 No KMS driver or no outputs, pipes: 8, outputs: 0
13585 09:34:45.379633 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13586 09:34:45.399862 <14>[ 31.574956] [IGT] kms_vblank: executing
13587 09:34:45.406507 IGT-Version: 1.2<14>[ 31.579922] [IGT] kms_vblank: exiting, ret=77
13588 09:34:45.410361 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13589 09:34:45.419352 Opened device: /dev/dri/car<8>[ 31.591691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13590 09:34:45.419608 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13592 09:34:45.423618 d0
13593 09:34:45.426350 No KMS driver or no outputs, pipes: 8, outputs: 0
13594 09:34:45.432264 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13595 09:34:45.446709 <14>[ 31.621791] [IGT] kms_vblank: executing
13596 09:34:45.453534 IGT-Version: 1.2<14>[ 31.626870] [IGT] kms_vblank: exiting, ret=77
13597 09:34:45.456786 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13598 09:34:45.466397 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13600 09:34:45.470050 Opened device: /dev/dri/car<8>[ 31.637869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13601 09:34:45.470287 d0
13602 09:34:45.473637 No KMS driver or no outputs, pipes: 8, outputs: 0
13603 09:34:45.479668 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13604 09:34:45.486602 <14>[ 31.660479] [IGT] kms_vblank: executing
13605 09:34:45.489457 IGT-Version: 1.2<14>[ 31.665249] [IGT] kms_vblank: exiting, ret=77
13606 09:34:45.495917 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13607 09:34:45.506200 Opened device: /dev/dri/car<8>[ 31.677283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13608 09:34:45.506381 d0
13609 09:34:45.506664 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13611 09:34:45.512630 No KMS driver or no outputs, pipes: 8, outputs: 0
13612 09:34:45.516223 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13613 09:34:45.532921 <14>[ 31.707865] [IGT] kms_vblank: executing
13614 09:34:45.539678 IGT-Version: 1.2<14>[ 31.712980] [IGT] kms_vblank: exiting, ret=77
13615 09:34:45.543634 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13616 09:34:45.552938 Opened device: /dev/dri/car<8>[ 31.724047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13617 09:34:45.553771 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13619 09:34:45.556062 d0
13620 09:34:45.559345 No KMS driver or no outputs, pipes: 8, outputs: 0
13621 09:34:45.566636 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13622 09:34:45.574215 <14>[ 31.748952] [IGT] kms_vblank: executing
13623 09:34:45.581157 IGT-Version: 1.2<14>[ 31.753703] [IGT] kms_vblank: exiting, ret=77
13624 09:34:45.584412 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13625 09:34:45.594263 Opened devi<8>[ 31.764371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13626 09:34:45.595004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13628 09:34:45.597555 ce: /dev/dri/card0
13629 09:34:45.600535 No KMS driver or no outputs, pipes: 8, outputs: 0
13630 09:34:45.607275 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13631 09:34:45.610491 <14>[ 31.786044] [IGT] kms_vblank: executing
13632 09:34:45.617248 IGT-Version: 1.2<14>[ 31.790810] [IGT] kms_vblank: exiting, ret=77
13633 09:34:45.620627 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13634 09:34:45.633982 Opened device: /dev/dri/car<8>[ 31.802749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13635 09:34:45.634408 d0
13636 09:34:45.635005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13638 09:34:45.636874 No KMS driver or no outputs, pipes: 8, outputs: 0
13639 09:34:45.643465 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13640 09:34:45.661771 <14>[ 31.835587] [IGT] kms_vblank: executing
13641 09:34:45.667840 IGT-Version: 1.2<14>[ 31.840572] [IGT] kms_vblank: exiting, ret=77
13642 09:34:45.670638 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13643 09:34:45.680298 Opened devi<8>[ 31.851448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13644 09:34:45.680765 ce: /dev/dri/card0
13645 09:34:45.681406 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13647 09:34:45.686869 No KMS driver or no outputs, pipes: 8, outputs: 0
13648 09:34:45.690622 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13649 09:34:45.696824 <14>[ 31.871590] [IGT] kms_vblank: executing
13650 09:34:45.703561 IGT-Version: 1.2<14>[ 31.876402] [IGT] kms_vblank: exiting, ret=77
13651 09:34:45.707233 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13652 09:34:45.716845 Opened devi<8>[ 31.886844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13653 09:34:45.717377 ce: /dev/dri/card0
13654 09:34:45.717982 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13656 09:34:45.720183 No KMS driver or no outputs, pipes: 8, outputs: 0
13657 09:34:45.726352 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13658 09:34:45.742353 <14>[ 31.916696] [IGT] kms_vblank: executing
13659 09:34:45.748615 IGT-Version: 1.2<14>[ 31.921868] [IGT] kms_vblank: exiting, ret=77
13660 09:34:45.752185 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13661 09:34:45.761806 Opened device: /dev/dri/car<8>[ 31.933389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13662 09:34:45.762330 d0
13663 09:34:45.762971 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13665 09:34:45.768243 No KMS driver or no outputs, pipes: 8, outputs: 0
13666 09:34:45.771715 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13667 09:34:45.789275 <14>[ 31.963927] [IGT] kms_vblank: executing
13668 09:34:45.795789 IGT-Version: 1.2<14>[ 31.969089] [IGT] kms_vblank: exiting, ret=77
13669 09:34:45.799021 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13670 09:34:45.809038 Opened device: /dev/dri/car<8>[ 31.980238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13671 09:34:45.809589 d0
13672 09:34:45.810222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13674 09:34:45.816308 No KMS driver or no outputs, pipes: 8, outputs: 0
13675 09:34:45.818841 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13676 09:34:45.836424 <14>[ 32.011100] [IGT] kms_vblank: executing
13677 09:34:45.842938 IGT-Version: 1.2<14>[ 32.016268] [IGT] kms_vblank: exiting, ret=77
13678 09:34:45.846430 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13679 09:34:45.856342 Opened device: /dev/dri/car<8>[ 32.027622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13680 09:34:45.856911 d0
13681 09:34:45.857557 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13683 09:34:45.862919 No KMS driver or no outputs, pipes: 8, outputs: 0
13684 09:34:45.866331 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13685 09:34:45.884743 <14>[ 32.059582] [IGT] kms_vblank: executing
13686 09:34:45.891186 IGT-Version: 1.2<14>[ 32.064666] [IGT] kms_vblank: exiting, ret=77
13687 09:34:45.894778 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13688 09:34:45.904662 Opened device: /dev/dri/car<8>[ 32.076102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13689 09:34:45.905058 d0
13690 09:34:45.905541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13692 09:34:45.908475 No KMS driver or no outputs, pipes: 8, outputs: 0
13693 09:34:45.914534 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13694 09:34:45.931580 <14>[ 32.106370] [IGT] kms_vblank: executing
13695 09:34:45.938882 IGT-Version: 1.2<14>[ 32.111521] [IGT] kms_vblank: exiting, ret=77
13696 09:34:45.942140 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13697 09:34:45.951422 Opened device: /dev/dri/car<8>[ 32.122637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13698 09:34:45.952118 d0
13699 09:34:45.952832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13701 09:34:45.958136 No KMS driver or no outputs, pipes: 8, outputs: 0
13702 09:34:45.961396 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13703 09:34:45.969935 <14>[ 32.144503] [IGT] kms_vblank: executing
13704 09:34:45.976273 IGT-Version: 1.2<14>[ 32.149261] [IGT] kms_vblank: exiting, ret=77
13705 09:34:45.979763 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13706 09:34:45.989725 Opened devi<8>[ 32.159955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13707 09:34:45.990283 ce: /dev/dri/card0
13708 09:34:45.990986 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13710 09:34:45.996358 No KMS driver or no outputs, pipes: 8, outputs: 0
13711 09:34:45.999896 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13712 09:34:46.006374 <14>[ 32.181065] [IGT] kms_vblank: executing
13713 09:34:46.013397 IGT-Version: 1.2<14>[ 32.185779] [IGT] kms_vblank: exiting, ret=77
13714 09:34:46.016690 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13715 09:34:46.020083 Opened device: /dev/dri/card0
13716 09:34:46.029466 No KMS driver or no outputs,<8>[ 32.199950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13717 09:34:46.030360 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13719 09:34:46.032915 pipes: 8, outputs: 0
13720 09:34:46.036096 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13721 09:34:46.057992 <14>[ 32.232541] [IGT] kms_vblank: executing
13722 09:34:46.064469 IGT-Version: 1.2<14>[ 32.237651] [IGT] kms_vblank: exiting, ret=77
13723 09:34:46.067718 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13724 09:34:46.077880 Opened device: /dev/dri/car<8>[ 32.249127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13725 09:34:46.078443 d0
13726 09:34:46.079089 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13728 09:34:46.081059 No KMS driver or no outputs, pipes: 8, outputs: 0
13729 09:34:46.088259 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13730 09:34:46.104704 <14>[ 32.279114] [IGT] kms_vblank: executing
13731 09:34:46.111207 IGT-Version: 1.2<14>[ 32.284270] [IGT] kms_vblank: exiting, ret=77
13732 09:34:46.113993 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13733 09:34:46.124278 Opened device: /dev/dri/car<8>[ 32.295409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13734 09:34:46.124737 d0
13735 09:34:46.125373 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13737 09:34:46.130990 No KMS driver or no outputs, pipes: 8, outputs: 0
13738 09:34:46.134175 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13739 09:34:46.142382 <14>[ 32.316913] [IGT] kms_vblank: executing
13740 09:34:46.149039 IGT-Version: 1.2<14>[ 32.321631] [IGT] kms_vblank: exiting, ret=77
13741 09:34:46.152265 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13742 09:34:46.155258 Opened device: /dev/dri/card0
13743 09:34:46.162100 No KMS drive<8>[ 32.335408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13744 09:34:46.162980 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13746 09:34:46.168488 r or no outputs, pipes: 8, outputs: 0
13747 09:34:46.171416 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13748 09:34:46.190753 <14>[ 32.365171] [IGT] kms_vblank: executing
13749 09:34:46.197243 IGT-Version: 1.2<14>[ 32.370294] [IGT] kms_vblank: exiting, ret=77
13750 09:34:46.200665 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13751 09:34:46.210318 Opened devi<8>[ 32.381013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13752 09:34:46.210871 ce: /dev/dri/card0
13753 09:34:46.211512 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13755 09:34:46.216727 No KMS driver or no outputs, pipes: 8, outputs: 0
13756 09:34:46.219844 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13757 09:34:46.227447 <14>[ 32.401826] [IGT] kms_vblank: executing
13758 09:34:46.234400 IGT-Version: 1.2<14>[ 32.406627] [IGT] kms_vblank: exiting, ret=77
13759 09:34:46.237457 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13760 09:34:46.244100 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13762 09:34:46.246962 Opened devi<8>[ 32.417291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13763 09:34:46.247517 ce: /dev/dri/card0
13764 09:34:46.250181 No KMS driver or no outputs, pipes: 8, outputs: 0
13765 09:34:46.256691 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13766 09:34:46.260403 <14>[ 32.437225] [IGT] kms_vblank: executing
13767 09:34:46.267051 IGT-Version: 1.2<14>[ 32.441934] [IGT] kms_vblank: exiting, ret=77
13768 09:34:46.273509 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13769 09:34:46.279780 Opened devi<8>[ 32.452653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13770 09:34:46.280651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13772 09:34:46.283834 ce: /dev/dri/card0
13773 09:34:46.286749 No KMS driver or no outputs, pipes: 8, outputs: 0
13774 09:34:46.293414 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13775 09:34:46.296625 <14>[ 32.472976] [IGT] kms_vblank: executing
13776 09:34:46.303281 IGT-Version: 1.2<14>[ 32.477706] [IGT] kms_vblank: exiting, ret=77
13777 09:34:46.310247 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13778 09:34:46.319474 Opened device: /dev/dri/car<8>[ 32.489706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13779 09:34:46.320070 d0
13780 09:34:46.321014 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13782 09:34:46.322921 No KMS driver or no outputs, pipes: 8, outputs: 0
13783 09:34:46.329868 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13784 09:34:46.345255 <14>[ 32.519914] [IGT] kms_vblank: executing
13785 09:34:46.352099 IGT-Version: 1.2<14>[ 32.525321] [IGT] kms_vblank: exiting, ret=77
13786 09:34:46.354858 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13787 09:34:46.365110 Opened device: /dev/dri/car<8>[ 32.536997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13788 09:34:46.365860 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13790 09:34:46.368218 d0
13791 09:34:46.371659 No KMS driver or no outputs, pipes: 8, outputs: 0
13792 09:34:46.375451 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13793 09:34:46.384219 <14>[ 32.559012] [IGT] kms_vblank: executing
13794 09:34:46.390776 IGT-Version: 1.2<14>[ 32.563764] [IGT] kms_vblank: exiting, ret=77
13795 09:34:46.393911 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13796 09:34:46.404143 Opened devi<8>[ 32.574452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13797 09:34:46.404703 ce: /dev/dri/card0
13798 09:34:46.405357 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13800 09:34:46.410916 No KMS driver or no outputs, pipes: 8, outputs: 0
13801 09:34:46.414456 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13802 09:34:46.421058 <14>[ 32.595409] [IGT] kms_vblank: executing
13803 09:34:46.427419 IGT-Version: 1.2<14>[ 32.600184] [IGT] kms_vblank: exiting, ret=77
13804 09:34:46.430433 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13805 09:34:46.440453 Opened devi<8>[ 32.610918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13806 09:34:46.441307 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13808 09:34:46.444234 ce: /dev/dri/card0
13809 09:34:46.447213 No KMS driver or no outputs, pipes: 8, outputs: 0
13810 09:34:46.453819 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13811 09:34:46.461209 <14>[ 32.635742] [IGT] kms_vblank: executing
13812 09:34:46.467760 IGT-Version: 1.2<14>[ 32.640467] [IGT] kms_vblank: exiting, ret=77
13813 09:34:46.471031 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13814 09:34:46.480383 Opened devi<8>[ 32.651299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13815 09:34:46.480848 ce: /dev/dri/card0
13816 09:34:46.481487 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13818 09:34:46.487507 No KMS driver or no outputs, pipes: 8, outputs: 0
13819 09:34:46.490888 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13820 09:34:46.506935 <14>[ 32.681637] [IGT] kms_vblank: executing
13821 09:34:46.513784 IGT-Version: 1.2<14>[ 32.686956] [IGT] kms_vblank: exiting, ret=77
13822 09:34:46.516867 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13823 09:34:46.526689 Opened devi<8>[ 32.697731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13824 09:34:46.527600 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13826 09:34:46.530048 ce: /dev/dri/card0
13827 09:34:46.533355 No KMS driver or no outputs, pipes: 8, outputs: 0
13828 09:34:46.539655 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13829 09:34:46.547364 <14>[ 32.721661] [IGT] kms_vblank: executing
13830 09:34:46.553652 IGT-Version: 1.2<14>[ 32.726523] [IGT] kms_vblank: exiting, ret=77
13831 09:34:46.556799 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13832 09:34:46.566563 Opened devi<8>[ 32.736866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13833 09:34:46.567134 ce: /dev/dri/card0
13834 09:34:46.567849 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13836 09:34:46.573509 No KMS driver or no outputs, pipes: 8, outputs: 0
13837 09:34:46.576846 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13838 09:34:46.582996 <14>[ 32.758066] [IGT] kms_vblank: executing
13839 09:34:46.589706 IGT-Version: 1.2<14>[ 32.762785] [IGT] kms_vblank: exiting, ret=77
13840 09:34:46.593170 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13841 09:34:46.603439 Opened devi<8>[ 32.773455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13842 09:34:46.604072 ce: /dev/dri/card0
13843 09:34:46.604846 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13845 09:34:46.609367 No KMS driver or no outputs, pipes: 8, outputs: 0
13846 09:34:46.613035 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13847 09:34:46.620047 <14>[ 32.795060] [IGT] kms_vblank: executing
13848 09:34:46.627312 IGT-Version: 1.2<14>[ 32.799845] [IGT] kms_vblank: exiting, ret=77
13849 09:34:46.630126 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13850 09:34:46.640051 Opened devi<8>[ 32.810661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13851 09:34:46.640897 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13853 09:34:46.643302 ce: /dev/dri/card0
13854 09:34:46.646852 No KMS driver or no outputs, pipes: 8, outputs: 0
13855 09:34:46.653540 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13856 09:34:46.666418 <14>[ 32.841411] [IGT] kms_vblank: executing
13857 09:34:46.673177 IGT-Version: 1.2<14>[ 32.846661] [IGT] kms_vblank: exiting, ret=77
13858 09:34:46.676187 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13859 09:34:46.686918 Opened devi<8>[ 32.857357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13860 09:34:46.687845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13862 09:34:46.689671 ce: /dev/dri/card0
13863 09:34:46.693177 No KMS driver or no outputs, pipes: 8, outputs: 0
13864 09:34:46.699966 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13865 09:34:46.706966 <14>[ 32.881337] [IGT] kms_vblank: executing
13866 09:34:46.713044 IGT-Version: 1.2<14>[ 32.886170] [IGT] kms_vblank: exiting, ret=77
13867 09:34:46.716638 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13868 09:34:46.726133 Opened devi<8>[ 32.896816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13869 09:34:46.726686 ce: /dev/dri/card0
13870 09:34:46.727326 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13872 09:34:46.732836 No KMS driver or no outputs, pipes: 8, outputs: 0
13873 09:34:46.736394 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13874 09:34:46.742794 <14>[ 32.917249] [IGT] kms_vblank: executing
13875 09:34:46.749287 IGT-Version: 1.2<14>[ 32.922096] [IGT] kms_vblank: exiting, ret=77
13876 09:34:46.752639 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13877 09:34:46.762319 Opened device: /dev/dri/car<8>[ 32.934022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13878 09:34:46.762785 d0
13879 09:34:46.763420 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13881 09:34:46.765730 No KMS driver or no outputs, pipes: 8, outputs: 0
13882 09:34:46.772125 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13883 09:34:46.789364 <14>[ 32.963769] [IGT] kms_vblank: executing
13884 09:34:46.796021 IGT-Version: 1.2<14>[ 32.968953] [IGT] kms_vblank: exiting, ret=77
13885 09:34:46.798837 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13886 09:34:46.808448 Opened device: /dev/dri/car<8>[ 32.980431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13887 09:34:46.809011 d0
13888 09:34:46.809658 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13890 09:34:46.815276 No KMS driver or no outputs, pipes: 8, outputs: 0
13891 09:34:46.818856 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13892 09:34:46.836174 <14>[ 33.011168] [IGT] kms_vblank: executing
13893 09:34:46.842919 IGT-Version: 1.2<14>[ 33.016328] [IGT] kms_vblank: exiting, ret=77
13894 09:34:46.846337 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13895 09:34:46.856330 Opened devi<8>[ 33.027197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13896 09:34:46.856881 ce: /dev/dri/card0
13897 09:34:46.857518 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13899 09:34:46.862561 No KMS driver or no outputs, pipes: 8, outputs: 0
13900 09:34:46.866384 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13901 09:34:46.874754 <14>[ 33.049609] [IGT] kms_vblank: executing
13902 09:34:46.881173 IGT-Version: 1.2<14>[ 33.054572] [IGT] kms_vblank: exiting, ret=77
13903 09:34:46.884971 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13904 09:34:46.894821 Opened devi<8>[ 33.064930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13905 09:34:46.895368 ce: /dev/dri/card0
13906 09:34:46.896044 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13908 09:34:46.901737 No KMS driver or no outputs, pipes: 8, outputs: 0
13909 09:34:46.904646 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13910 09:34:46.913937 <14>[ 33.088763] [IGT] kms_vblank: executing
13911 09:34:46.920397 IGT-Version: 1.2<14>[ 33.093483] [IGT] kms_vblank: exiting, ret=77
13912 09:34:46.923594 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13913 09:34:46.927232 Opened device: /dev/dri/card0
13914 09:34:46.937327 No KMS driver or no outputs,<8>[ 33.107963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13915 09:34:46.937793 pipes: 8, outputs: 0
13916 09:34:46.938518 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13918 09:34:46.943326 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13919 09:34:46.963817 <14>[ 33.138748] [IGT] kms_vblank: executing
13920 09:34:46.970245 IGT-Version: 1.2<14>[ 33.143860] [IGT] kms_vblank: exiting, ret=77
13921 09:34:46.973738 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13922 09:34:46.983907 Opened device: /dev/dri/car<8>[ 33.155272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13923 09:34:46.984335 d0
13924 09:34:46.984927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13926 09:34:46.991391 No KMS driver or no outputs, pipes: 8, outputs: 0
13927 09:34:46.993386 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13928 09:34:47.004967 <14>[ 33.179559] [IGT] kms_vblank: executing
13929 09:34:47.011813 IGT-Version: 1.2<14>[ 33.184298] [IGT] kms_vblank: exiting, ret=77
13930 09:34:47.015149 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13931 09:34:47.024237 Opened devi<8>[ 33.195166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13932 09:34:47.024822 ce: /dev/dri/card0
13933 09:34:47.025472 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13935 09:34:47.030840 No KMS driver or no outputs, pipes: 8, outputs: 0
13936 09:34:47.034124 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13937 09:34:47.043380 <14>[ 33.218240] [IGT] kms_vblank: executing
13938 09:34:47.050035 IGT-Version: 1.2<14>[ 33.223068] [IGT] kms_vblank: exiting, ret=77
13939 09:34:47.052901 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13940 09:34:47.063922 Opened device: /dev/dri/car<8>[ 33.235020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13941 09:34:47.064552 d0
13942 09:34:47.065265 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13944 09:34:47.069366 No KMS driver or no outputs, pipes: 8, outputs: 0
13945 09:34:47.072927 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13946 09:34:47.091027 <14>[ 33.265718] [IGT] kms_vblank: executing
13947 09:34:47.097770 IGT-Version: 1.2<14>[ 33.271054] [IGT] kms_vblank: exiting, ret=77
13948 09:34:47.101056 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13949 09:34:47.110893 Opened devi<8>[ 33.281843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13950 09:34:47.111510 ce: /dev/dri/card0
13951 09:34:47.112259 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13953 09:34:47.117268 No KMS driver or no outputs, pipes: 8, outputs: 0
13954 09:34:47.120746 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13955 09:34:47.127106 <14>[ 33.301877] [IGT] kms_vblank: executing
13956 09:34:47.133409 IGT-Version: 1.2<14>[ 33.306663] [IGT] kms_vblank: exiting, ret=77
13957 09:34:47.136851 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13958 09:34:47.147457 Opened devi<8>[ 33.317096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13959 09:34:47.148053 ce: /dev/dri/card0
13960 09:34:47.148664 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13962 09:34:47.153507 No KMS driver or no outputs, pipes: 8, outputs: 0
13963 09:34:47.156583 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13964 09:34:47.163322 <14>[ 33.337720] [IGT] kms_vblank: executing
13965 09:34:47.169781 IGT-Version: 1.2<14>[ 33.342570] [IGT] kms_vblank: exiting, ret=77
13966 09:34:47.173271 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13967 09:34:47.176382 Opened device: /dev/dri/card0
13968 09:34:47.186587 No KMS driver or no outputs,<8>[ 33.356635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13969 09:34:47.187110 pipes: 8, outputs: 0
13970 09:34:47.187780 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13972 09:34:47.193130 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13973 09:34:47.213076 <14>[ 33.388064] [IGT] kms_vblank: executing
13974 09:34:47.220307 IGT-Version: 1.2<14>[ 33.393246] [IGT] kms_vblank: exiting, ret=77
13975 09:34:47.223211 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13976 09:34:47.232646 Opened device: /dev/dri/car<8>[ 33.405002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13977 09:34:47.233116 d0
13978 09:34:47.233797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13980 09:34:47.239917 No KMS driver or no outputs, pipes: 8, outputs: 0
13981 09:34:47.242544 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13982 09:34:47.252827 <14>[ 33.427725] [IGT] kms_vblank: executing
13983 09:34:47.259960 IGT-Version: 1.2<14>[ 33.432481] [IGT] kms_vblank: exiting, ret=77
13984 09:34:47.262794 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13985 09:34:47.269361 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13987 09:34:47.272905 Opened devi<8>[ 33.443157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13988 09:34:47.273490 ce: /dev/dri/card0
13989 09:34:47.275847 No KMS driver or no outputs, pipes: 8, outputs: 0
13990 09:34:47.282468 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13991 09:34:47.291089 <14>[ 33.465813] [IGT] kms_vblank: executing
13992 09:34:47.297559 IGT-Version: 1.2<14>[ 33.470720] [IGT] kms_vblank: exiting, ret=77
13993 09:34:47.300665 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
13994 09:34:47.311119 Opened devi<8>[ 33.481279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13995 09:34:47.311642 ce: /dev/dri/card0
13996 09:34:47.312455 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13998 09:34:47.317582 No KMS driver or no outputs, pipes: 8, outputs: 0
13999 09:34:47.320653 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
14000 09:34:47.329567 <14>[ 33.504766] [IGT] kms_vblank: executing
14001 09:34:47.336144 IGT-Version: 1.2<14>[ 33.509525] [IGT] kms_vblank: exiting, ret=77
14002 09:34:47.340102 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14003 09:34:47.349750 Opened device: /dev/dri/car<8>[ 33.521639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
14004 09:34:47.350315 d0
14005 09:34:47.350963 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
14007 09:34:47.356038 No KMS driver or no outputs, pipes: 8, outputs: 0
14008 09:34:47.360093 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
14009 09:34:47.368995 <14>[ 33.544039] [IGT] kms_vblank: executing
14010 09:34:47.375902 IGT-Version: 1.2<14>[ 33.548775] [IGT] kms_vblank: exiting, ret=77
14011 09:34:47.379518 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14012 09:34:47.389023 Opened devi<8>[ 33.559491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
14013 09:34:47.389443 ce: /dev/dri/card0
14014 09:34:47.390082 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
14016 09:34:47.395648 No KMS driver or no outputs, pipes: 8, outputs: 0
14017 09:34:47.399259 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
14018 09:34:47.405403 <14>[ 33.580573] [IGT] kms_vblank: executing
14019 09:34:47.412194 IGT-Version: 1.2<14>[ 33.585316] [IGT] kms_vblank: exiting, ret=77
14020 09:34:47.415325 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14021 09:34:47.426028 Opened devi<8>[ 33.596018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
14022 09:34:47.426824 ce: /dev/dri/card0
14023 09:34:47.427491 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
14025 09:34:47.431921 No KMS driver or no outputs, pipes: 8, outputs: 0
14026 09:34:47.435233 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
14027 09:34:47.442658 <14>[ 33.617157] [IGT] kms_vblank: executing
14028 09:34:47.448897 IGT-Version: 1.2<14>[ 33.621910] [IGT] kms_vblank: exiting, ret=77
14029 09:34:47.452173 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14030 09:34:47.455419 Opened device: /dev/dri/card0
14031 09:34:47.465632 No KMS driver or no outputs,<8>[ 33.636060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
14032 09:34:47.466322 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
14034 09:34:47.468869 pipes: 8, outputs: 0
14035 09:34:47.475034 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
14036 09:34:47.494222 <14>[ 33.668830] [IGT] kms_vblank: executing
14037 09:34:47.500721 IGT-Version: 1.2<14>[ 33.673975] [IGT] kms_vblank: exiting, ret=77
14038 09:34:47.504152 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14039 09:34:47.513643 Opened device: /dev/dri/car<8>[ 33.685568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
14040 09:34:47.514498 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
14042 09:34:47.516861 d0
14043 09:34:47.520655 No KMS driver or no outputs, pipes: 8, outputs: 0
14044 09:34:47.527316 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
14045 09:34:47.533459 <14>[ 33.707746] [IGT] kms_vblank: executing
14046 09:34:47.540298 IGT-Version: 1.2<14>[ 33.712510] [IGT] kms_vblank: exiting, ret=77
14047 09:34:47.543102 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14048 09:34:47.553393 Opened devi<8>[ 33.723386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
14049 09:34:47.553966 ce: /dev/dri/card0
14050 09:34:47.554612 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
14052 09:34:47.560016 No KMS driver or no outputs, pipes: 8, outputs: 0
14053 09:34:47.566323 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
14054 09:34:47.569205 <14>[ 33.744873] [IGT] kms_vblank: executing
14055 09:34:47.576183 IGT-Version: 1.2<14>[ 33.749600] [IGT] kms_vblank: exiting, ret=77
14056 09:34:47.579936 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14057 09:34:47.589188 Opened devi<8>[ 33.760430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
14058 09:34:47.590034 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14060 09:34:47.592442 ce: /dev/dri/card0
14061 09:34:47.595619 No KMS driver or no outputs, pipes: 8, outputs: 0
14062 09:34:47.603118 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14063 09:34:47.615759 <14>[ 33.790859] [IGT] kms_vblank: executing
14064 09:34:47.622747 IGT-Version: 1.2<14>[ 33.796010] [IGT] kms_vblank: exiting, ret=77
14065 09:34:47.625531 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14066 09:34:47.636632 Opened device: /dev/dri/car<8>[ 33.807758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14067 09:34:47.637483 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14069 09:34:47.638796 d0
14070 09:34:47.642475 No KMS driver or no outputs, pipes: 8, outputs: 0
14071 09:34:47.649177 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14072 09:34:47.655471 <14>[ 33.829710] [IGT] kms_vblank: executing
14073 09:34:47.658633 IGT-Version: 1.2<14>[ 33.834619] [IGT] kms_vblank: exiting, ret=77
14074 09:34:47.664897 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14075 09:34:47.675053 Opened devi<8>[ 33.845051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14076 09:34:47.675476 ce: /dev/dri/card0
14077 09:34:47.676115 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14079 09:34:47.681880 No KMS driver or no outputs, pipes: 8, outputs: 0
14080 09:34:47.688586 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14081 09:34:47.692032 <14>[ 33.867086] [IGT] kms_vblank: executing
14082 09:34:47.698555 IGT-Version: 1.2<14>[ 33.871913] [IGT] kms_vblank: exiting, ret=77
14083 09:34:47.701890 7.1-g621c2d3 (aarch64) (Linux: 6.1.58-cip7 aarch64)
14084 09:34:47.711405 Opened devi<8>[ 33.882785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14085 09:34:47.712316 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14087 09:34:47.714641 ce: /dev/dri/card0
14088 09:34:47.718403 No KMS drive<8>[ 33.893481] <LAVA_SIGNAL_TESTSET STOP>
14089 09:34:47.719242 Received signal: <TESTSET> STOP
14090 09:34:47.719624 Closing test_set kms_vblank
14091 09:34:47.727623 r or no outputs,<8>[ 33.899630] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 11826833_1.5.2.3.1>
14092 09:34:47.728494 pipes: 8, outputs: 0
14093 09:34:47.729326 Received signal: <ENDRUN> 0_igt-kms-mediatek 11826833_1.5.2.3.1
14094 09:34:47.729780 Ending use of test pattern.
14095 09:34:47.730121 Ending test lava.0_igt-kms-mediatek (11826833_1.5.2.3.1), duration 13.36
14097 09:34:47.734203 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14098 09:34:47.734661 + set +x
14099 09:34:47.737252 <LAVA_TEST_RUNNER EXIT>
14100 09:34:47.738028 ok: lava_test_shell seems to have completed
14101 09:34:47.759632 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14102 09:34:47.760841 end: 3.1 lava-test-shell (duration 00:00:14) [common]
14103 09:34:47.761295 end: 3 lava-test-retry (duration 00:00:14) [common]
14104 09:34:47.761740 start: 4 finalize (timeout 00:07:49) [common]
14105 09:34:47.762181 start: 4.1 power-off (timeout 00:00:30) [common]
14106 09:34:47.762948 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
14107 09:34:47.872763 >> Command sent successfully.
14108 09:34:47.879943 Returned 0 in 0 seconds
14109 09:34:47.981128 end: 4.1 power-off (duration 00:00:00) [common]
14111 09:34:47.982919 start: 4.2 read-feedback (timeout 00:07:49) [common]
14112 09:34:47.984297 Listened to connection for namespace 'common' for up to 1s
14113 09:34:48.984026 Finalising connection for namespace 'common'
14114 09:34:48.984691 Disconnecting from shell: Finalise
14115 09:34:48.985122 / #
14116 09:34:49.086145 end: 4.2 read-feedback (duration 00:00:01) [common]
14117 09:34:49.086911 end: 4 finalize (duration 00:00:01) [common]
14118 09:34:49.087536 Cleaning after the job
14119 09:34:49.088134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/ramdisk
14120 09:34:49.121849 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/kernel
14121 09:34:49.137174 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/dtb
14122 09:34:49.137470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826833/tftp-deploy-49sr7nl6/modules
14123 09:34:49.146527 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826833
14124 09:34:49.265262 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826833
14125 09:34:49.265445 Job finished correctly