Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 38
- Errors: 0
- Boot result: PASS
1 09:31:20.954110 lava-dispatcher, installed at version: 2023.08
2 09:31:20.954332 start: 0 validate
3 09:31:20.954468 Start time: 2023-10-20 09:31:20.954460+00:00 (UTC)
4 09:31:20.954631 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:31:20.954864 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:31:21.215077 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:31:21.215241 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:31:21.481452 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:31:21.481636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:31:21.748297 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:31:21.748478 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:31:22.014898 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:31:22.015083 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:31:22.283721 validate duration: 1.33
16 09:31:22.284019 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:31:22.284122 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:31:22.284208 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:31:22.284332 Not decompressing ramdisk as can be used compressed.
20 09:31:22.284419 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 09:31:22.284487 saving as /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/ramdisk/initrd.cpio.gz
22 09:31:22.284552 total size: 5625687 (5 MB)
23 09:31:22.285786 progress 0 % (0 MB)
24 09:31:22.287612 progress 5 % (0 MB)
25 09:31:22.289320 progress 10 % (0 MB)
26 09:31:22.290871 progress 15 % (0 MB)
27 09:31:22.292463 progress 20 % (1 MB)
28 09:31:22.294085 progress 25 % (1 MB)
29 09:31:22.295712 progress 30 % (1 MB)
30 09:31:22.297349 progress 35 % (1 MB)
31 09:31:22.298773 progress 40 % (2 MB)
32 09:31:22.300356 progress 45 % (2 MB)
33 09:31:22.301749 progress 50 % (2 MB)
34 09:31:22.303403 progress 55 % (2 MB)
35 09:31:22.304975 progress 60 % (3 MB)
36 09:31:22.306371 progress 65 % (3 MB)
37 09:31:22.308055 progress 70 % (3 MB)
38 09:31:22.309525 progress 75 % (4 MB)
39 09:31:22.311185 progress 80 % (4 MB)
40 09:31:22.312579 progress 85 % (4 MB)
41 09:31:22.314143 progress 90 % (4 MB)
42 09:31:22.315726 progress 95 % (5 MB)
43 09:31:22.317136 progress 100 % (5 MB)
44 09:31:22.317334 5 MB downloaded in 0.03 s (163.66 MB/s)
45 09:31:22.317491 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:31:22.317730 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:31:22.317818 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:31:22.317903 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:31:22.318041 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:31:22.318109 saving as /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/kernel/Image
52 09:31:22.318172 total size: 49236480 (46 MB)
53 09:31:22.318234 No compression specified
54 09:31:22.319340 progress 0 % (0 MB)
55 09:31:22.332263 progress 5 % (2 MB)
56 09:31:22.345042 progress 10 % (4 MB)
57 09:31:22.357868 progress 15 % (7 MB)
58 09:31:22.370925 progress 20 % (9 MB)
59 09:31:22.383983 progress 25 % (11 MB)
60 09:31:22.396880 progress 30 % (14 MB)
61 09:31:22.409686 progress 35 % (16 MB)
62 09:31:22.422681 progress 40 % (18 MB)
63 09:31:22.436685 progress 45 % (21 MB)
64 09:31:22.449947 progress 50 % (23 MB)
65 09:31:22.462891 progress 55 % (25 MB)
66 09:31:22.475914 progress 60 % (28 MB)
67 09:31:22.489052 progress 65 % (30 MB)
68 09:31:22.501916 progress 70 % (32 MB)
69 09:31:22.514767 progress 75 % (35 MB)
70 09:31:22.527613 progress 80 % (37 MB)
71 09:31:22.540357 progress 85 % (39 MB)
72 09:31:22.553323 progress 90 % (42 MB)
73 09:31:22.565842 progress 95 % (44 MB)
74 09:31:22.578490 progress 100 % (46 MB)
75 09:31:22.578761 46 MB downloaded in 0.26 s (180.19 MB/s)
76 09:31:22.578935 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:31:22.579169 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:31:22.579257 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:31:22.579342 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:31:22.579481 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:31:22.579559 saving as /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/dtb/mt8192-asurada-spherion-r0.dtb
83 09:31:22.579621 total size: 47278 (0 MB)
84 09:31:22.579681 No compression specified
85 09:31:22.580850 progress 69 % (0 MB)
86 09:31:22.581127 progress 100 % (0 MB)
87 09:31:22.581285 0 MB downloaded in 0.00 s (27.13 MB/s)
88 09:31:22.581408 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:31:22.581630 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:31:22.581715 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:31:22.581797 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:31:22.581912 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 09:31:22.581980 saving as /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/nfsrootfs/full.rootfs.tar
95 09:31:22.582044 total size: 195204440 (186 MB)
96 09:31:22.582106 Using unxz to decompress xz
97 09:31:22.586141 progress 0 % (0 MB)
98 09:31:23.143372 progress 5 % (9 MB)
99 09:31:23.647758 progress 10 % (18 MB)
100 09:31:24.247091 progress 15 % (27 MB)
101 09:31:24.537229 progress 20 % (37 MB)
102 09:31:25.019329 progress 25 % (46 MB)
103 09:31:25.619302 progress 30 % (55 MB)
104 09:31:26.202088 progress 35 % (65 MB)
105 09:31:26.784989 progress 40 % (74 MB)
106 09:31:27.383136 progress 45 % (83 MB)
107 09:31:28.034461 progress 50 % (93 MB)
108 09:31:28.659744 progress 55 % (102 MB)
109 09:31:29.330238 progress 60 % (111 MB)
110 09:31:29.728218 progress 65 % (121 MB)
111 09:31:29.811811 progress 70 % (130 MB)
112 09:31:29.958376 progress 75 % (139 MB)
113 09:31:30.041985 progress 80 % (148 MB)
114 09:31:30.098301 progress 85 % (158 MB)
115 09:31:30.193361 progress 90 % (167 MB)
116 09:31:30.575973 progress 95 % (176 MB)
117 09:31:31.160019 progress 100 % (186 MB)
118 09:31:31.165003 186 MB downloaded in 8.58 s (21.69 MB/s)
119 09:31:31.165319 end: 1.4.1 http-download (duration 00:00:09) [common]
121 09:31:31.165747 end: 1.4 download-retry (duration 00:00:09) [common]
122 09:31:31.165857 start: 1.5 download-retry (timeout 00:09:51) [common]
123 09:31:31.165960 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 09:31:31.166131 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:31:31.166229 saving as /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/modules/modules.tar
126 09:31:31.166330 total size: 8614716 (8 MB)
127 09:31:31.166443 Using unxz to decompress xz
128 09:31:31.171070 progress 0 % (0 MB)
129 09:31:31.194359 progress 5 % (0 MB)
130 09:31:31.219179 progress 10 % (0 MB)
131 09:31:31.243095 progress 15 % (1 MB)
132 09:31:31.266880 progress 20 % (1 MB)
133 09:31:31.291529 progress 25 % (2 MB)
134 09:31:31.317406 progress 30 % (2 MB)
135 09:31:31.343933 progress 35 % (2 MB)
136 09:31:31.367686 progress 40 % (3 MB)
137 09:31:31.392474 progress 45 % (3 MB)
138 09:31:31.418130 progress 50 % (4 MB)
139 09:31:31.443152 progress 55 % (4 MB)
140 09:31:31.468971 progress 60 % (4 MB)
141 09:31:31.495495 progress 65 % (5 MB)
142 09:31:31.522856 progress 70 % (5 MB)
143 09:31:31.546500 progress 75 % (6 MB)
144 09:31:31.573882 progress 80 % (6 MB)
145 09:31:31.600275 progress 85 % (7 MB)
146 09:31:31.627615 progress 90 % (7 MB)
147 09:31:31.657650 progress 95 % (7 MB)
148 09:31:31.686286 progress 100 % (8 MB)
149 09:31:31.693015 8 MB downloaded in 0.53 s (15.60 MB/s)
150 09:31:31.693332 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:31:31.693736 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:31:31.693855 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 09:31:31.693956 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 09:31:36.036855 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv
156 09:31:36.037068 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 09:31:36.037171 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 09:31:36.037360 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8
159 09:31:36.037505 makedir: /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin
160 09:31:36.037617 makedir: /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/tests
161 09:31:36.037726 makedir: /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/results
162 09:31:36.037836 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-add-keys
163 09:31:36.038014 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-add-sources
164 09:31:36.038163 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-background-process-start
165 09:31:36.038304 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-background-process-stop
166 09:31:36.038432 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-common-functions
167 09:31:36.038569 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-echo-ipv4
168 09:31:36.038694 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-install-packages
169 09:31:36.038868 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-installed-packages
170 09:31:36.039002 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-os-build
171 09:31:36.039127 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-probe-channel
172 09:31:36.039289 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-probe-ip
173 09:31:36.039437 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-target-ip
174 09:31:36.039600 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-target-mac
175 09:31:36.039758 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-target-storage
176 09:31:36.039886 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-case
177 09:31:36.040024 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-event
178 09:31:36.040148 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-feedback
179 09:31:36.040286 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-raise
180 09:31:36.040411 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-reference
181 09:31:36.040548 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-runner
182 09:31:36.040673 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-set
183 09:31:36.040811 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-test-shell
184 09:31:36.040938 Updating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-add-keys (debian)
185 09:31:36.041103 Updating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-add-sources (debian)
186 09:31:36.041256 Updating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-install-packages (debian)
187 09:31:36.041413 Updating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-installed-packages (debian)
188 09:31:36.041574 Updating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/bin/lava-os-build (debian)
189 09:31:36.041713 Creating /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/environment
190 09:31:36.041826 LAVA metadata
191 09:31:36.041897 - LAVA_JOB_ID=11826827
192 09:31:36.041965 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:31:36.042072 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 09:31:36.042139 skipped lava-vland-overlay
195 09:31:36.042219 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:31:36.042304 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 09:31:36.042364 skipped lava-multinode-overlay
198 09:31:36.042436 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:31:36.042523 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 09:31:36.042596 Loading test definitions
201 09:31:36.042683 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 09:31:36.042807 Using /lava-11826827 at stage 0
203 09:31:36.043212 uuid=11826827_1.6.2.3.1 testdef=None
204 09:31:36.043336 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:31:36.043458 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 09:31:36.044118 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:31:36.044482 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 09:31:36.045203 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:31:36.045435 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 09:31:36.046027 runner path: /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/0/tests/0_timesync-off test_uuid 11826827_1.6.2.3.1
213 09:31:36.046183 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:31:36.046422 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 09:31:36.046505 Using /lava-11826827 at stage 0
217 09:31:36.046601 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:31:36.046678 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/0/tests/1_kselftest-alsa'
219 09:31:40.308138 Running '/usr/bin/git checkout kernelci.org
220 09:31:40.457534 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 09:31:40.458509 uuid=11826827_1.6.2.3.5 testdef=None
222 09:31:40.458710 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 09:31:40.459152 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 09:31:40.460325 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:31:40.460567 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 09:31:40.461693 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:31:40.461931 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 09:31:40.462968 runner path: /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/0/tests/1_kselftest-alsa test_uuid 11826827_1.6.2.3.5
232 09:31:40.463063 BOARD='mt8192-asurada-spherion-r0'
233 09:31:40.463133 BRANCH='cip'
234 09:31:40.463194 SKIPFILE='/dev/null'
235 09:31:40.463258 SKIP_INSTALL='True'
236 09:31:40.463314 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:31:40.463377 TST_CASENAME=''
238 09:31:40.463433 TST_CMDFILES='alsa'
239 09:31:40.463583 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:31:40.463803 Creating lava-test-runner.conf files
242 09:31:40.463872 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826827/lava-overlay-bmwofje8/lava-11826827/0 for stage 0
243 09:31:40.463967 - 0_timesync-off
244 09:31:40.464034 - 1_kselftest-alsa
245 09:31:40.464141 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 09:31:40.464228 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 09:31:48.504218 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:31:48.504411 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 09:31:48.504503 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:31:48.504608 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 09:31:48.504699 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 09:31:48.679563 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:31:48.680040 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 09:31:48.680169 extracting modules file /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv
255 09:31:48.921752 extracting modules file /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826827/extract-overlay-ramdisk-y4jbl9xe/ramdisk
256 09:31:49.168084 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:31:49.168270 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 09:31:49.168365 [common] Applying overlay to NFS
259 09:31:49.168434 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826827/compress-overlay-qvbij5m0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv
260 09:31:50.113097 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:31:50.113272 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 09:31:50.113374 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:31:50.113477 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 09:31:50.113581 Building ramdisk /var/lib/lava/dispatcher/tmp/11826827/extract-overlay-ramdisk-y4jbl9xe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826827/extract-overlay-ramdisk-y4jbl9xe/ramdisk
265 09:31:50.491256 >> 130490 blocks
266 09:31:52.577243 rename /var/lib/lava/dispatcher/tmp/11826827/extract-overlay-ramdisk-y4jbl9xe/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/ramdisk/ramdisk.cpio.gz
267 09:31:52.577695 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:31:52.577810 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 09:31:52.577910 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 09:31:52.578016 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/kernel/Image'
271 09:32:04.943893 Returned 0 in 12 seconds
272 09:32:05.044536 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/kernel/image.itb
273 09:32:05.413607 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:32:05.413988 output: Created: Fri Oct 20 10:32:05 2023
275 09:32:05.414068 output: Image 0 (kernel-1)
276 09:32:05.414136 output: Description:
277 09:32:05.414200 output: Created: Fri Oct 20 10:32:05 2023
278 09:32:05.414264 output: Type: Kernel Image
279 09:32:05.414327 output: Compression: lzma compressed
280 09:32:05.414388 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
281 09:32:05.414447 output: Architecture: AArch64
282 09:32:05.414505 output: OS: Linux
283 09:32:05.414562 output: Load Address: 0x00000000
284 09:32:05.414618 output: Entry Point: 0x00000000
285 09:32:05.414672 output: Hash algo: crc32
286 09:32:05.414735 output: Hash value: 05d3904e
287 09:32:05.414827 output: Image 1 (fdt-1)
288 09:32:05.414883 output: Description: mt8192-asurada-spherion-r0
289 09:32:05.414936 output: Created: Fri Oct 20 10:32:05 2023
290 09:32:05.414989 output: Type: Flat Device Tree
291 09:32:05.415042 output: Compression: uncompressed
292 09:32:05.415095 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 09:32:05.415147 output: Architecture: AArch64
294 09:32:05.415200 output: Hash algo: crc32
295 09:32:05.415252 output: Hash value: cc4352de
296 09:32:05.415305 output: Image 2 (ramdisk-1)
297 09:32:05.415357 output: Description: unavailable
298 09:32:05.415409 output: Created: Fri Oct 20 10:32:05 2023
299 09:32:05.415462 output: Type: RAMDisk Image
300 09:32:05.415514 output: Compression: Unknown Compression
301 09:32:05.415566 output: Data Size: 18748527 Bytes = 18309.11 KiB = 17.88 MiB
302 09:32:05.415619 output: Architecture: AArch64
303 09:32:05.415672 output: OS: Linux
304 09:32:05.415724 output: Load Address: unavailable
305 09:32:05.415777 output: Entry Point: unavailable
306 09:32:05.415829 output: Hash algo: crc32
307 09:32:05.415881 output: Hash value: c8eb824c
308 09:32:05.415933 output: Default Configuration: 'conf-1'
309 09:32:05.415985 output: Configuration 0 (conf-1)
310 09:32:05.416037 output: Description: mt8192-asurada-spherion-r0
311 09:32:05.416090 output: Kernel: kernel-1
312 09:32:05.416142 output: Init Ramdisk: ramdisk-1
313 09:32:05.416194 output: FDT: fdt-1
314 09:32:05.416246 output: Loadables: kernel-1
315 09:32:05.416298 output:
316 09:32:05.416537 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 09:32:05.416649 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 09:32:05.416788 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 09:32:05.416898 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 09:32:05.416978 No LXC device requested
321 09:32:05.417055 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:32:05.417138 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 09:32:05.417214 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:32:05.417286 Checking files for TFTP limit of 4294967296 bytes.
325 09:32:05.417800 end: 1 tftp-deploy (duration 00:00:43) [common]
326 09:32:05.417912 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:32:05.418007 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:32:05.418134 substitutions:
329 09:32:05.418204 - {DTB}: 11826827/tftp-deploy-jtsi5kkd/dtb/mt8192-asurada-spherion-r0.dtb
330 09:32:05.418269 - {INITRD}: 11826827/tftp-deploy-jtsi5kkd/ramdisk/ramdisk.cpio.gz
331 09:32:05.418327 - {KERNEL}: 11826827/tftp-deploy-jtsi5kkd/kernel/Image
332 09:32:05.418384 - {LAVA_MAC}: None
333 09:32:05.418440 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv
334 09:32:05.418495 - {NFS_SERVER_IP}: 192.168.201.1
335 09:32:05.418548 - {PRESEED_CONFIG}: None
336 09:32:05.418601 - {PRESEED_LOCAL}: None
337 09:32:05.418655 - {RAMDISK}: 11826827/tftp-deploy-jtsi5kkd/ramdisk/ramdisk.cpio.gz
338 09:32:05.418708 - {ROOT_PART}: None
339 09:32:05.418798 - {ROOT}: None
340 09:32:05.418852 - {SERVER_IP}: 192.168.201.1
341 09:32:05.418905 - {TEE}: None
342 09:32:05.418959 Parsed boot commands:
343 09:32:05.419012 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:32:05.419195 Parsed boot commands: tftpboot 192.168.201.1 11826827/tftp-deploy-jtsi5kkd/kernel/image.itb 11826827/tftp-deploy-jtsi5kkd/kernel/cmdline
345 09:32:05.419285 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:32:05.419371 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:32:05.419463 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:32:05.419550 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:32:05.419625 Not connected, no need to disconnect.
350 09:32:05.419699 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:32:05.419781 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:32:05.419849 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 09:32:05.423906 Setting prompt string to ['lava-test: # ']
354 09:32:05.424329 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:32:05.424440 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:32:05.424542 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:32:05.424669 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:32:05.424894 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 09:32:10.568325 >> Command sent successfully.
360 09:32:10.575850 Returned 0 in 5 seconds
361 09:32:10.676690 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 09:32:10.677353 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 09:32:10.677577 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 09:32:10.677762 Setting prompt string to 'Starting depthcharge on Spherion...'
366 09:32:10.677906 Changing prompt to 'Starting depthcharge on Spherion...'
367 09:32:10.678055 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 09:32:10.678603 [Enter `^Ec?' for help]
369 09:32:10.846961
370 09:32:10.847110
371 09:32:10.847183 F0: 102B 0000
372 09:32:10.847250
373 09:32:10.847309 F3: 1001 0000 [0200]
374 09:32:10.847368
375 09:32:10.850753 F3: 1001 0000
376 09:32:10.850851
377 09:32:10.850918 F7: 102D 0000
378 09:32:10.850980
379 09:32:10.851040 F1: 0000 0000
380 09:32:10.854408
381 09:32:10.854492 V0: 0000 0000 [0001]
382 09:32:10.854561
383 09:32:10.854623 00: 0007 8000
384 09:32:10.854686
385 09:32:10.858017 01: 0000 0000
386 09:32:10.858119
387 09:32:10.858199 BP: 0C00 0209 [0000]
388 09:32:10.858260
389 09:32:10.862086 G0: 1182 0000
390 09:32:10.862170
391 09:32:10.862235 EC: 0000 0021 [4000]
392 09:32:10.862297
393 09:32:10.862355 S7: 0000 0000 [0000]
394 09:32:10.865572
395 09:32:10.865656 CC: 0000 0000 [0001]
396 09:32:10.865722
397 09:32:10.869138 T0: 0000 0040 [010F]
398 09:32:10.869222
399 09:32:10.869288 Jump to BL
400 09:32:10.869350
401 09:32:10.893554
402 09:32:10.893699
403 09:32:10.893769
404 09:32:10.901098 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 09:32:10.904686 ARM64: Exception handlers installed.
406 09:32:10.908764 ARM64: Testing exception
407 09:32:10.912634 ARM64: Done test exception
408 09:32:10.920091 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 09:32:10.927013 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 09:32:10.934000 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 09:32:10.944747 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 09:32:10.951476 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 09:32:10.961503 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 09:32:10.972676 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 09:32:10.979596 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 09:32:10.996328 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 09:32:11.000106 WDT: Last reset was cold boot
418 09:32:11.002972 SPI1(PAD0) initialized at 2873684 Hz
419 09:32:11.006613 SPI5(PAD0) initialized at 992727 Hz
420 09:32:11.009910 VBOOT: Loading verstage.
421 09:32:11.016586 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:32:11.020117 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 09:32:11.023730 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 09:32:11.026555 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 09:32:11.033893 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 09:32:11.040737 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 09:32:11.051372 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 09:32:11.051466
429 09:32:11.051533
430 09:32:11.061301 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 09:32:11.065024 ARM64: Exception handlers installed.
432 09:32:11.068253 ARM64: Testing exception
433 09:32:11.068351 ARM64: Done test exception
434 09:32:11.074875 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 09:32:11.078446 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 09:32:11.092732 Probing TPM: . done!
437 09:32:11.092824 TPM ready after 0 ms
438 09:32:11.100544 Connected to device vid:did:rid of 1ae0:0028:00
439 09:32:11.106833 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 09:32:11.163907 Initialized TPM device CR50 revision 0
441 09:32:11.175924 tlcl_send_startup: Startup return code is 0
442 09:32:11.176056 TPM: setup succeeded
443 09:32:11.187736 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 09:32:11.195943 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:32:11.206974 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 09:32:11.217051 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 09:32:11.220481 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 09:32:11.229099 in-header: 03 07 00 00 08 00 00 00
449 09:32:11.232546 in-data: aa e4 47 04 13 02 00 00
450 09:32:11.236315 Chrome EC: UHEPI supported
451 09:32:11.243703 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 09:32:11.247787 in-header: 03 ad 00 00 08 00 00 00
453 09:32:11.247944 in-data: 00 20 20 08 00 00 00 00
454 09:32:11.251403 Phase 1
455 09:32:11.254884 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 09:32:11.258925 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 09:32:11.266443 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 09:32:11.270129 Recovery requested (1009000e)
459 09:32:11.277468 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 09:32:11.283486 tlcl_extend: response is 0
461 09:32:11.292717 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 09:32:11.297542 tlcl_extend: response is 0
463 09:32:11.304752 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 09:32:11.324776 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 09:32:11.331695 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 09:32:11.331809
467 09:32:11.331901
468 09:32:11.342086 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 09:32:11.346150 ARM64: Exception handlers installed.
470 09:32:11.346267 ARM64: Testing exception
471 09:32:11.349786 ARM64: Done test exception
472 09:32:11.370009 pmic_efuse_setting: Set efuses in 11 msecs
473 09:32:11.374156 pmwrap_interface_init: Select PMIF_VLD_RDY
474 09:32:11.381085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 09:32:11.384123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 09:32:11.387329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 09:32:11.394703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 09:32:11.398640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 09:32:11.401998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 09:32:11.409049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 09:32:11.413034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 09:32:11.416594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 09:32:11.424125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 09:32:11.427720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 09:32:11.431370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 09:32:11.434785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 09:32:11.442382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 09:32:11.449817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 09:32:11.452976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 09:32:11.460438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 09:32:11.464451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 09:32:11.472313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 09:32:11.475577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 09:32:11.483137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 09:32:11.486506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 09:32:11.494019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 09:32:11.497749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 09:32:11.504954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 09:32:11.508741 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 09:32:11.516238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 09:32:11.519925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 09:32:11.523472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 09:32:11.531314 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 09:32:11.534646 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 09:32:11.538645 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 09:32:11.545696 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 09:32:11.549730 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 09:32:11.553146 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 09:32:11.560324 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 09:32:11.564267 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 09:32:11.568496 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 09:32:11.571964 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 09:32:11.579190 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 09:32:11.582920 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 09:32:11.586419 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 09:32:11.590700 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 09:32:11.593976 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 09:32:11.601775 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 09:32:11.605097 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 09:32:11.609256 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 09:32:11.612654 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 09:32:11.616133 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 09:32:11.620305 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 09:32:11.623976 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 09:32:11.631432 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 09:32:11.642669 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 09:32:11.646734 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 09:32:11.653764 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 09:32:11.661127 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 09:32:11.668779 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 09:32:11.672776 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:32:11.675892 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 09:32:11.683603 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 09:32:11.687533 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 09:32:11.695411 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 09:32:11.698566 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 09:32:11.708024 [RTC]rtc_get_frequency_meter,154: input=15, output=791
538 09:32:11.717171 [RTC]rtc_get_frequency_meter,154: input=23, output=979
539 09:32:11.727163 [RTC]rtc_get_frequency_meter,154: input=19, output=882
540 09:32:11.735589 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 09:32:11.746061 [RTC]rtc_get_frequency_meter,154: input=16, output=812
542 09:32:11.755383 [RTC]rtc_get_frequency_meter,154: input=15, output=789
543 09:32:11.765230 [RTC]rtc_get_frequency_meter,154: input=16, output=812
544 09:32:11.768824 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 09:32:11.772094 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 09:32:11.779198 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 09:32:11.783520 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 09:32:11.786388 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 09:32:11.790126 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 09:32:11.793933 ADC[4]: Raw value=901328 ID=7
551 09:32:11.798086 ADC[3]: Raw value=213336 ID=1
552 09:32:11.798171 RAM Code: 0x71
553 09:32:11.801292 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 09:32:11.808876 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 09:32:11.816737 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 09:32:11.824005 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 09:32:11.827502 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 09:32:11.831440 in-header: 03 07 00 00 08 00 00 00
559 09:32:11.835155 in-data: aa e4 47 04 13 02 00 00
560 09:32:11.835240 Chrome EC: UHEPI supported
561 09:32:11.842178 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 09:32:11.845680 in-header: 03 ed 00 00 08 00 00 00
563 09:32:11.849869 in-data: 80 20 60 08 00 00 00 00
564 09:32:11.853395 MRC: failed to locate region type 0.
565 09:32:11.860869 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 09:32:11.860956 DRAM-K: Running full calibration
567 09:32:11.868407 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 09:32:11.871990 header.status = 0x0
569 09:32:11.872077 header.version = 0x6 (expected: 0x6)
570 09:32:11.876093 header.size = 0xd00 (expected: 0xd00)
571 09:32:11.879659 header.flags = 0x0
572 09:32:11.883110 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 09:32:11.903795 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 09:32:11.911305 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 09:32:11.911392 dram_init: ddr_geometry: 2
576 09:32:11.914726 [EMI] MDL number = 2
577 09:32:11.914827 [EMI] Get MDL freq = 0
578 09:32:11.919043 dram_init: ddr_type: 0
579 09:32:11.919127 is_discrete_lpddr4: 1
580 09:32:11.922184 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 09:32:11.922294
582 09:32:11.925800
583 09:32:11.925891 [Bian_co] ETT version 0.0.0.1
584 09:32:11.932825 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 09:32:11.932910
586 09:32:11.936530 dramc_set_vcore_voltage set vcore to 650000
587 09:32:11.936615 Read voltage for 800, 4
588 09:32:11.940555 Vio18 = 0
589 09:32:11.940654 Vcore = 650000
590 09:32:11.940724 Vdram = 0
591 09:32:11.940786 Vddq = 0
592 09:32:11.943652 Vmddr = 0
593 09:32:11.943736 dram_init: config_dvfs: 1
594 09:32:11.950578 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 09:32:11.953486 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 09:32:11.960306 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 09:32:11.963737 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 09:32:11.967181 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 09:32:11.970375 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 09:32:11.973543 MEM_TYPE=3, freq_sel=18
601 09:32:11.977218 sv_algorithm_assistance_LP4_1600
602 09:32:11.980216 ============ PULL DRAM RESETB DOWN ============
603 09:32:11.983739 ========== PULL DRAM RESETB DOWN end =========
604 09:32:11.987080 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 09:32:11.990574 ===================================
606 09:32:11.994072 LPDDR4 DRAM CONFIGURATION
607 09:32:11.996908 ===================================
608 09:32:12.000491 EX_ROW_EN[0] = 0x0
609 09:32:12.000576 EX_ROW_EN[1] = 0x0
610 09:32:12.003865 LP4Y_EN = 0x0
611 09:32:12.003949 WORK_FSP = 0x0
612 09:32:12.007014 WL = 0x2
613 09:32:12.007099 RL = 0x2
614 09:32:12.010673 BL = 0x2
615 09:32:12.010778 RPST = 0x0
616 09:32:12.014051 RD_PRE = 0x0
617 09:32:12.014136 WR_PRE = 0x1
618 09:32:12.017576 WR_PST = 0x0
619 09:32:12.017660 DBI_WR = 0x0
620 09:32:12.020499 DBI_RD = 0x0
621 09:32:12.020590 OTF = 0x1
622 09:32:12.024113 ===================================
623 09:32:12.027559 ===================================
624 09:32:12.030488 ANA top config
625 09:32:12.033914 ===================================
626 09:32:12.037228 DLL_ASYNC_EN = 0
627 09:32:12.037312 ALL_SLAVE_EN = 1
628 09:32:12.040838 NEW_RANK_MODE = 1
629 09:32:12.043963 DLL_IDLE_MODE = 1
630 09:32:12.047650 LP45_APHY_COMB_EN = 1
631 09:32:12.047734 TX_ODT_DIS = 1
632 09:32:12.050739 NEW_8X_MODE = 1
633 09:32:12.054063 ===================================
634 09:32:12.057606 ===================================
635 09:32:12.060771 data_rate = 1600
636 09:32:12.064791 CKR = 1
637 09:32:12.067800 DQ_P2S_RATIO = 8
638 09:32:12.071311 ===================================
639 09:32:12.071396 CA_P2S_RATIO = 8
640 09:32:12.074398 DQ_CA_OPEN = 0
641 09:32:12.077786 DQ_SEMI_OPEN = 0
642 09:32:12.081232 CA_SEMI_OPEN = 0
643 09:32:12.084789 CA_FULL_RATE = 0
644 09:32:12.084873 DQ_CKDIV4_EN = 1
645 09:32:12.088251 CA_CKDIV4_EN = 1
646 09:32:12.091793 CA_PREDIV_EN = 0
647 09:32:12.094869 PH8_DLY = 0
648 09:32:12.098346 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 09:32:12.101818 DQ_AAMCK_DIV = 4
650 09:32:12.101903 CA_AAMCK_DIV = 4
651 09:32:12.104773 CA_ADMCK_DIV = 4
652 09:32:12.108268 DQ_TRACK_CA_EN = 0
653 09:32:12.111690 CA_PICK = 800
654 09:32:12.115017 CA_MCKIO = 800
655 09:32:12.118434 MCKIO_SEMI = 0
656 09:32:12.118519 PLL_FREQ = 3068
657 09:32:12.122072 DQ_UI_PI_RATIO = 32
658 09:32:12.126138 CA_UI_PI_RATIO = 0
659 09:32:12.129691 ===================================
660 09:32:12.133168 ===================================
661 09:32:12.133253 memory_type:LPDDR4
662 09:32:12.137226 GP_NUM : 10
663 09:32:12.137310 SRAM_EN : 1
664 09:32:12.140777 MD32_EN : 0
665 09:32:12.144848 ===================================
666 09:32:12.144932 [ANA_INIT] >>>>>>>>>>>>>>
667 09:32:12.148318 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 09:32:12.151828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:32:12.155226 ===================================
670 09:32:12.158828 data_rate = 1600,PCW = 0X7600
671 09:32:12.162024 ===================================
672 09:32:12.165702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 09:32:12.172161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:32:12.175683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 09:32:12.182081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 09:32:12.185433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:32:12.188840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 09:32:12.188925 [ANA_INIT] flow start
679 09:32:12.192327 [ANA_INIT] PLL >>>>>>>>
680 09:32:12.195514 [ANA_INIT] PLL <<<<<<<<
681 09:32:12.195599 [ANA_INIT] MIDPI >>>>>>>>
682 09:32:12.198828 [ANA_INIT] MIDPI <<<<<<<<
683 09:32:12.202444 [ANA_INIT] DLL >>>>>>>>
684 09:32:12.202528 [ANA_INIT] flow end
685 09:32:12.208852 ============ LP4 DIFF to SE enter ============
686 09:32:12.212207 ============ LP4 DIFF to SE exit ============
687 09:32:12.212291 [ANA_INIT] <<<<<<<<<<<<<
688 09:32:12.215859 [Flow] Enable top DCM control >>>>>
689 09:32:12.219207 [Flow] Enable top DCM control <<<<<
690 09:32:12.222153 Enable DLL master slave shuffle
691 09:32:12.229024 ==============================================================
692 09:32:12.229109 Gating Mode config
693 09:32:12.235692 ==============================================================
694 09:32:12.239275 Config description:
695 09:32:12.249487 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 09:32:12.255797 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 09:32:12.259110 SELPH_MODE 0: By rank 1: By Phase
698 09:32:12.266244 ==============================================================
699 09:32:12.269654 GAT_TRACK_EN = 1
700 09:32:12.269739 RX_GATING_MODE = 2
701 09:32:12.273100 RX_GATING_TRACK_MODE = 2
702 09:32:12.276236 SELPH_MODE = 1
703 09:32:12.279707 PICG_EARLY_EN = 1
704 09:32:12.283070 VALID_LAT_VALUE = 1
705 09:32:12.289800 ==============================================================
706 09:32:12.292990 Enter into Gating configuration >>>>
707 09:32:12.296456 Exit from Gating configuration <<<<
708 09:32:12.299686 Enter into DVFS_PRE_config >>>>>
709 09:32:12.309713 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 09:32:12.312834 Exit from DVFS_PRE_config <<<<<
711 09:32:12.316232 Enter into PICG configuration >>>>
712 09:32:12.319711 Exit from PICG configuration <<<<
713 09:32:12.319788 [RX_INPUT] configuration >>>>>
714 09:32:12.323302 [RX_INPUT] configuration <<<<<
715 09:32:12.329817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 09:32:12.333246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 09:32:12.340688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 09:32:12.347942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 09:32:12.354289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 09:32:12.361124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 09:32:12.364070 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 09:32:12.367570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 09:32:12.371056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 09:32:12.374579 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 09:32:12.380922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 09:32:12.384500 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 09:32:12.387874 ===================================
728 09:32:12.391149 LPDDR4 DRAM CONFIGURATION
729 09:32:12.394519 ===================================
730 09:32:12.394621 EX_ROW_EN[0] = 0x0
731 09:32:12.398058 EX_ROW_EN[1] = 0x0
732 09:32:12.398136 LP4Y_EN = 0x0
733 09:32:12.401508 WORK_FSP = 0x0
734 09:32:12.401586 WL = 0x2
735 09:32:12.404493 RL = 0x2
736 09:32:12.404564 BL = 0x2
737 09:32:12.407931 RPST = 0x0
738 09:32:12.408001 RD_PRE = 0x0
739 09:32:12.411136 WR_PRE = 0x1
740 09:32:12.411213 WR_PST = 0x0
741 09:32:12.414853 DBI_WR = 0x0
742 09:32:12.414924 DBI_RD = 0x0
743 09:32:12.418100 OTF = 0x1
744 09:32:12.421598 ===================================
745 09:32:12.424662 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 09:32:12.428018 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 09:32:12.434628 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 09:32:12.438208 ===================================
749 09:32:12.438292 LPDDR4 DRAM CONFIGURATION
750 09:32:12.441719 ===================================
751 09:32:12.444835 EX_ROW_EN[0] = 0x10
752 09:32:12.448461 EX_ROW_EN[1] = 0x0
753 09:32:12.448545 LP4Y_EN = 0x0
754 09:32:12.451788 WORK_FSP = 0x0
755 09:32:12.451873 WL = 0x2
756 09:32:12.455251 RL = 0x2
757 09:32:12.455335 BL = 0x2
758 09:32:12.458778 RPST = 0x0
759 09:32:12.458862 RD_PRE = 0x0
760 09:32:12.461791 WR_PRE = 0x1
761 09:32:12.461875 WR_PST = 0x0
762 09:32:12.465230 DBI_WR = 0x0
763 09:32:12.465314 DBI_RD = 0x0
764 09:32:12.468560 OTF = 0x1
765 09:32:12.472008 ===================================
766 09:32:12.475480 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 09:32:12.480836 nWR fixed to 40
768 09:32:12.484040 [ModeRegInit_LP4] CH0 RK0
769 09:32:12.484124 [ModeRegInit_LP4] CH0 RK1
770 09:32:12.487551 [ModeRegInit_LP4] CH1 RK0
771 09:32:12.490907 [ModeRegInit_LP4] CH1 RK1
772 09:32:12.490991 match AC timing 13
773 09:32:12.497608 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 09:32:12.500940 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 09:32:12.504429 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 09:32:12.510727 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 09:32:12.514247 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 09:32:12.514330 [EMI DOE] emi_dcm 0
779 09:32:12.520935 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 09:32:12.521023 ==
781 09:32:12.524398 Dram Type= 6, Freq= 0, CH_0, rank 0
782 09:32:12.527280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 09:32:12.527365 ==
784 09:32:12.534898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 09:32:12.537484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 09:32:12.548337 [CA 0] Center 37 (7~68) winsize 62
787 09:32:12.551659 [CA 1] Center 37 (6~68) winsize 63
788 09:32:12.554949 [CA 2] Center 35 (5~66) winsize 62
789 09:32:12.558200 [CA 3] Center 35 (4~66) winsize 63
790 09:32:12.561568 [CA 4] Center 34 (3~65) winsize 63
791 09:32:12.565075 [CA 5] Center 33 (3~64) winsize 62
792 09:32:12.565160
793 09:32:12.568454 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 09:32:12.568539
795 09:32:12.571945 [CATrainingPosCal] consider 1 rank data
796 09:32:12.575439 u2DelayCellTimex100 = 270/100 ps
797 09:32:12.578942 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 09:32:12.581945 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 09:32:12.585516 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 09:32:12.591802 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 09:32:12.595590 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 09:32:12.598825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 09:32:12.598909
804 09:32:12.602067 CA PerBit enable=1, Macro0, CA PI delay=33
805 09:32:12.602151
806 09:32:12.605426 [CBTSetCACLKResult] CA Dly = 33
807 09:32:12.605511 CS Dly: 5 (0~36)
808 09:32:12.605578 ==
809 09:32:12.608799 Dram Type= 6, Freq= 0, CH_0, rank 1
810 09:32:12.615613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 09:32:12.615698 ==
812 09:32:12.619085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 09:32:12.625779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 09:32:12.634606 [CA 0] Center 37 (6~68) winsize 63
815 09:32:12.638169 [CA 1] Center 37 (7~68) winsize 62
816 09:32:12.641013 [CA 2] Center 35 (5~66) winsize 62
817 09:32:12.644388 [CA 3] Center 35 (4~66) winsize 63
818 09:32:12.648205 [CA 4] Center 34 (3~65) winsize 63
819 09:32:12.651480 [CA 5] Center 33 (3~64) winsize 62
820 09:32:12.651564
821 09:32:12.654792 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 09:32:12.654877
823 09:32:12.657892 [CATrainingPosCal] consider 2 rank data
824 09:32:12.661527 u2DelayCellTimex100 = 270/100 ps
825 09:32:12.664890 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 09:32:12.668088 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 09:32:12.671562 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 09:32:12.678319 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 09:32:12.681883 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 09:32:12.684865 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 09:32:12.684950
832 09:32:12.688373 CA PerBit enable=1, Macro0, CA PI delay=33
833 09:32:12.688457
834 09:32:12.691858 [CBTSetCACLKResult] CA Dly = 33
835 09:32:12.691942 CS Dly: 5 (0~37)
836 09:32:12.692009
837 09:32:12.694901 ----->DramcWriteLeveling(PI) begin...
838 09:32:12.698393 ==
839 09:32:12.698504 Dram Type= 6, Freq= 0, CH_0, rank 0
840 09:32:12.705693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 09:32:12.705785 ==
842 09:32:12.709435 Write leveling (Byte 0): 29 => 29
843 09:32:12.709521 Write leveling (Byte 1): 29 => 29
844 09:32:12.712713 DramcWriteLeveling(PI) end<-----
845 09:32:12.712797
846 09:32:12.712865 ==
847 09:32:12.716104 Dram Type= 6, Freq= 0, CH_0, rank 0
848 09:32:12.719664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 09:32:12.719749 ==
850 09:32:12.723177 [Gating] SW mode calibration
851 09:32:12.729984 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 09:32:12.736901 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 09:32:12.740440 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 09:32:12.743853 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 09:32:12.750488 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 09:32:12.753750 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
857 09:32:12.757125 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:32:12.764064 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:32:12.767418 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:32:12.770768 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:32:12.774003 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:32:12.781006 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:32:12.784500 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:32:12.787914 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:32:12.794492 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:32:12.797987 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:32:12.800982 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:32:12.808053 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:32:12.811099 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 09:32:12.814859 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 09:32:12.821344 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 09:32:12.824703 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 09:32:12.828122 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:32:12.831848 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:32:12.838349 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:32:12.841762 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:32:12.845065 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 09:32:12.851348 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 09:32:12.854904 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 09:32:12.858324 0 9 12 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
881 09:32:12.865056 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:32:12.868434 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:32:12.871616 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:32:12.878522 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 09:32:12.881771 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 09:32:12.885448 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 09:32:12.891989 0 10 8 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
888 09:32:12.894827 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
889 09:32:12.898564 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:32:12.902598 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:32:12.908497 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:32:12.911984 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:32:12.915432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 09:32:12.921910 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 09:32:12.925369 0 11 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
896 09:32:12.928793 0 11 12 | B1->B0 | 3737 4141 | 0 0 | (0 0) (1 1)
897 09:32:12.935466 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:32:12.938927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:32:12.942234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:32:12.949305 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 09:32:12.952576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 09:32:12.955926 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 09:32:12.958864 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
904 09:32:12.965801 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
905 09:32:12.969216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:32:12.972518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:32:12.979218 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:32:12.982615 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:32:12.986174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:32:12.992676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:32:12.996068 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:32:12.999622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:32:13.006040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:32:13.009734 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:32:13.012607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:32:13.019490 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 09:32:13.022838 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 09:32:13.026491 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 09:32:13.029886 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 09:32:13.036479 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
921 09:32:13.039568 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 09:32:13.043062 Total UI for P1: 0, mck2ui 16
923 09:32:13.046627 best dqsien dly found for B0: ( 0, 14, 10)
924 09:32:13.049555 Total UI for P1: 0, mck2ui 16
925 09:32:13.053006 best dqsien dly found for B1: ( 0, 14, 10)
926 09:32:13.056461 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
927 09:32:13.059508 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 09:32:13.059941
929 09:32:13.062872 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 09:32:13.066819 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 09:32:13.069723 [Gating] SW calibration Done
932 09:32:13.070156 ==
933 09:32:13.073216 Dram Type= 6, Freq= 0, CH_0, rank 0
934 09:32:13.076490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 09:32:13.079849 ==
936 09:32:13.080282 RX Vref Scan: 0
937 09:32:13.080628
938 09:32:13.083409 RX Vref 0 -> 0, step: 1
939 09:32:13.083899
940 09:32:13.086769 RX Delay -130 -> 252, step: 16
941 09:32:13.090321 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 09:32:13.093651 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 09:32:13.097157 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 09:32:13.100481 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 09:32:13.104125 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 09:32:13.110614 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 09:32:13.113965 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
948 09:32:13.117649 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 09:32:13.120423 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 09:32:13.123802 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 09:32:13.127136 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 09:32:13.134090 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 09:32:13.137422 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 09:32:13.140390 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 09:32:13.143668 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 09:32:13.150648 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 09:32:13.151126 ==
958 09:32:13.154119 Dram Type= 6, Freq= 0, CH_0, rank 0
959 09:32:13.157007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 09:32:13.157439 ==
961 09:32:13.157774 DQS Delay:
962 09:32:13.160698 DQS0 = 0, DQS1 = 0
963 09:32:13.161124 DQM Delay:
964 09:32:13.164002 DQM0 = 85, DQM1 = 78
965 09:32:13.164427 DQ Delay:
966 09:32:13.167233 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 09:32:13.170777 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
968 09:32:13.173887 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
969 09:32:13.177158 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 09:32:13.177587
971 09:32:13.177920
972 09:32:13.178233 ==
973 09:32:13.180545 Dram Type= 6, Freq= 0, CH_0, rank 0
974 09:32:13.183872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 09:32:13.184307 ==
976 09:32:13.184651
977 09:32:13.184967
978 09:32:13.187355 TX Vref Scan disable
979 09:32:13.190895 == TX Byte 0 ==
980 09:32:13.194203 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
981 09:32:13.197765 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
982 09:32:13.200691 == TX Byte 1 ==
983 09:32:13.204214 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 09:32:13.207514 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 09:32:13.207946 ==
986 09:32:13.210901 Dram Type= 6, Freq= 0, CH_0, rank 0
987 09:32:13.214037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 09:32:13.214503 ==
989 09:32:13.228348 TX Vref=22, minBit 0, minWin=27, winSum=441
990 09:32:13.232103 TX Vref=24, minBit 5, minWin=27, winSum=443
991 09:32:13.235624 TX Vref=26, minBit 3, minWin=27, winSum=446
992 09:32:13.239143 TX Vref=28, minBit 3, minWin=27, winSum=448
993 09:32:13.242466 TX Vref=30, minBit 1, minWin=28, winSum=452
994 09:32:13.245190 TX Vref=32, minBit 1, minWin=28, winSum=452
995 09:32:13.252415 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 30
996 09:32:13.253038
997 09:32:13.255386 Final TX Range 1 Vref 30
998 09:32:13.255880
999 09:32:13.256266 ==
1000 09:32:13.258508 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 09:32:13.262123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 09:32:13.262605 ==
1003 09:32:13.263040
1004 09:32:13.263395
1005 09:32:13.265619 TX Vref Scan disable
1006 09:32:13.268499 == TX Byte 0 ==
1007 09:32:13.271937 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 09:32:13.275864 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 09:32:13.278921 == TX Byte 1 ==
1010 09:32:13.282339 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 09:32:13.285242 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 09:32:13.285806
1013 09:32:13.288503 [DATLAT]
1014 09:32:13.288927 Freq=800, CH0 RK0
1015 09:32:13.289263
1016 09:32:13.292373 DATLAT Default: 0xa
1017 09:32:13.292855 0, 0xFFFF, sum = 0
1018 09:32:13.295467 1, 0xFFFF, sum = 0
1019 09:32:13.295916 2, 0xFFFF, sum = 0
1020 09:32:13.298691 3, 0xFFFF, sum = 0
1021 09:32:13.299204 4, 0xFFFF, sum = 0
1022 09:32:13.302590 5, 0xFFFF, sum = 0
1023 09:32:13.303071 6, 0xFFFF, sum = 0
1024 09:32:13.305476 7, 0xFFFF, sum = 0
1025 09:32:13.305939 8, 0xFFFF, sum = 0
1026 09:32:13.309169 9, 0x0, sum = 1
1027 09:32:13.309596 10, 0x0, sum = 2
1028 09:32:13.312696 11, 0x0, sum = 3
1029 09:32:13.313123 12, 0x0, sum = 4
1030 09:32:13.315598 best_step = 10
1031 09:32:13.316016
1032 09:32:13.316348 ==
1033 09:32:13.318837 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 09:32:13.322061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 09:32:13.322485 ==
1036 09:32:13.322944 RX Vref Scan: 1
1037 09:32:13.325934
1038 09:32:13.326503 Set Vref Range= 32 -> 127
1039 09:32:13.326892
1040 09:32:13.328958 RX Vref 32 -> 127, step: 1
1041 09:32:13.329379
1042 09:32:13.332695 RX Delay -95 -> 252, step: 8
1043 09:32:13.333173
1044 09:32:13.335390 Set Vref, RX VrefLevel [Byte0]: 32
1045 09:32:13.339857 [Byte1]: 32
1046 09:32:13.340275
1047 09:32:13.343127 Set Vref, RX VrefLevel [Byte0]: 33
1048 09:32:13.346707 [Byte1]: 33
1049 09:32:13.347255
1050 09:32:13.349539 Set Vref, RX VrefLevel [Byte0]: 34
1051 09:32:13.353134 [Byte1]: 34
1052 09:32:13.353555
1053 09:32:13.356647 Set Vref, RX VrefLevel [Byte0]: 35
1054 09:32:13.359485 [Byte1]: 35
1055 09:32:13.363655
1056 09:32:13.364083 Set Vref, RX VrefLevel [Byte0]: 36
1057 09:32:13.366970 [Byte1]: 36
1058 09:32:13.371850
1059 09:32:13.372467 Set Vref, RX VrefLevel [Byte0]: 37
1060 09:32:13.374988 [Byte1]: 37
1061 09:32:13.379324
1062 09:32:13.379771 Set Vref, RX VrefLevel [Byte0]: 38
1063 09:32:13.382846 [Byte1]: 38
1064 09:32:13.387397
1065 09:32:13.387948 Set Vref, RX VrefLevel [Byte0]: 39
1066 09:32:13.390451 [Byte1]: 39
1067 09:32:13.394382
1068 09:32:13.394840 Set Vref, RX VrefLevel [Byte0]: 40
1069 09:32:13.398089 [Byte1]: 40
1070 09:32:13.401826
1071 09:32:13.402248 Set Vref, RX VrefLevel [Byte0]: 41
1072 09:32:13.405187 [Byte1]: 41
1073 09:32:13.409620
1074 09:32:13.410098 Set Vref, RX VrefLevel [Byte0]: 42
1075 09:32:13.412602 [Byte1]: 42
1076 09:32:13.417340
1077 09:32:13.417814 Set Vref, RX VrefLevel [Byte0]: 43
1078 09:32:13.420175 [Byte1]: 43
1079 09:32:13.424680
1080 09:32:13.425093 Set Vref, RX VrefLevel [Byte0]: 44
1081 09:32:13.428097 [Byte1]: 44
1082 09:32:13.432338
1083 09:32:13.432826 Set Vref, RX VrefLevel [Byte0]: 45
1084 09:32:13.435414 [Byte1]: 45
1085 09:32:13.440043
1086 09:32:13.440518 Set Vref, RX VrefLevel [Byte0]: 46
1087 09:32:13.443525 [Byte1]: 46
1088 09:32:13.447276
1089 09:32:13.447813 Set Vref, RX VrefLevel [Byte0]: 47
1090 09:32:13.450667 [Byte1]: 47
1091 09:32:13.454888
1092 09:32:13.455373 Set Vref, RX VrefLevel [Byte0]: 48
1093 09:32:13.458457 [Byte1]: 48
1094 09:32:13.462650
1095 09:32:13.463129 Set Vref, RX VrefLevel [Byte0]: 49
1096 09:32:13.465591 [Byte1]: 49
1097 09:32:13.469983
1098 09:32:13.470398 Set Vref, RX VrefLevel [Byte0]: 50
1099 09:32:13.473973 [Byte1]: 50
1100 09:32:13.477735
1101 09:32:13.478362 Set Vref, RX VrefLevel [Byte0]: 51
1102 09:32:13.481259 [Byte1]: 51
1103 09:32:13.485412
1104 09:32:13.485825 Set Vref, RX VrefLevel [Byte0]: 52
1105 09:32:13.489126 [Byte1]: 52
1106 09:32:13.493201
1107 09:32:13.493785 Set Vref, RX VrefLevel [Byte0]: 53
1108 09:32:13.496268 [Byte1]: 53
1109 09:32:13.500733
1110 09:32:13.501216 Set Vref, RX VrefLevel [Byte0]: 54
1111 09:32:13.503939 [Byte1]: 54
1112 09:32:13.508042
1113 09:32:13.508454 Set Vref, RX VrefLevel [Byte0]: 55
1114 09:32:13.511359 [Byte1]: 55
1115 09:32:13.515506
1116 09:32:13.515922 Set Vref, RX VrefLevel [Byte0]: 56
1117 09:32:13.518831 [Byte1]: 56
1118 09:32:13.523528
1119 09:32:13.523992 Set Vref, RX VrefLevel [Byte0]: 57
1120 09:32:13.526790 [Byte1]: 57
1121 09:32:13.531448
1122 09:32:13.531907 Set Vref, RX VrefLevel [Byte0]: 58
1123 09:32:13.534306 [Byte1]: 58
1124 09:32:13.538290
1125 09:32:13.538706 Set Vref, RX VrefLevel [Byte0]: 59
1126 09:32:13.542105 [Byte1]: 59
1127 09:32:13.546164
1128 09:32:13.546584 Set Vref, RX VrefLevel [Byte0]: 60
1129 09:32:13.549665 [Byte1]: 60
1130 09:32:13.553724
1131 09:32:13.554141 Set Vref, RX VrefLevel [Byte0]: 61
1132 09:32:13.557363 [Byte1]: 61
1133 09:32:13.561454
1134 09:32:13.561870 Set Vref, RX VrefLevel [Byte0]: 62
1135 09:32:13.564451 [Byte1]: 62
1136 09:32:13.569124
1137 09:32:13.569541 Set Vref, RX VrefLevel [Byte0]: 63
1138 09:32:13.572134 [Byte1]: 63
1139 09:32:13.576968
1140 09:32:13.577391 Set Vref, RX VrefLevel [Byte0]: 64
1141 09:32:13.579980 [Byte1]: 64
1142 09:32:13.584185
1143 09:32:13.584752 Set Vref, RX VrefLevel [Byte0]: 65
1144 09:32:13.587697 [Byte1]: 65
1145 09:32:13.591889
1146 09:32:13.592307 Set Vref, RX VrefLevel [Byte0]: 66
1147 09:32:13.595397 [Byte1]: 66
1148 09:32:13.599372
1149 09:32:13.599790 Set Vref, RX VrefLevel [Byte0]: 67
1150 09:32:13.602443 [Byte1]: 67
1151 09:32:13.607047
1152 09:32:13.607467 Set Vref, RX VrefLevel [Byte0]: 68
1153 09:32:13.610208 [Byte1]: 68
1154 09:32:13.614539
1155 09:32:13.615135 Set Vref, RX VrefLevel [Byte0]: 69
1156 09:32:13.618114 [Byte1]: 69
1157 09:32:13.622245
1158 09:32:13.622660 Set Vref, RX VrefLevel [Byte0]: 70
1159 09:32:13.625603 [Byte1]: 70
1160 09:32:13.630018
1161 09:32:13.630467 Set Vref, RX VrefLevel [Byte0]: 71
1162 09:32:13.633231 [Byte1]: 71
1163 09:32:13.637310
1164 09:32:13.637728 Set Vref, RX VrefLevel [Byte0]: 72
1165 09:32:13.640935 [Byte1]: 72
1166 09:32:13.644978
1167 09:32:13.645424 Set Vref, RX VrefLevel [Byte0]: 73
1168 09:32:13.648482 [Byte1]: 73
1169 09:32:13.652393
1170 09:32:13.652809 Set Vref, RX VrefLevel [Byte0]: 74
1171 09:32:13.655434 [Byte1]: 74
1172 09:32:13.660054
1173 09:32:13.660498 Set Vref, RX VrefLevel [Byte0]: 75
1174 09:32:13.663178 [Byte1]: 75
1175 09:32:13.667615
1176 09:32:13.668033 Final RX Vref Byte 0 = 60 to rank0
1177 09:32:13.671102 Final RX Vref Byte 1 = 58 to rank0
1178 09:32:13.674653 Final RX Vref Byte 0 = 60 to rank1
1179 09:32:13.678045 Final RX Vref Byte 1 = 58 to rank1==
1180 09:32:13.680925 Dram Type= 6, Freq= 0, CH_0, rank 0
1181 09:32:13.684361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1182 09:32:13.687736 ==
1183 09:32:13.688234 DQS Delay:
1184 09:32:13.688617 DQS0 = 0, DQS1 = 0
1185 09:32:13.690969 DQM Delay:
1186 09:32:13.691449 DQM0 = 86, DQM1 = 78
1187 09:32:13.694773 DQ Delay:
1188 09:32:13.695280 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1189 09:32:13.698030 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1190 09:32:13.701599 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1191 09:32:13.705057 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1192 09:32:13.705482
1193 09:32:13.705812
1194 09:32:13.714805 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1195 09:32:13.718260 CH0 RK0: MR19=606, MR18=2C13
1196 09:32:13.721473 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1197 09:32:13.721895
1198 09:32:13.725265 ----->DramcWriteLeveling(PI) begin...
1199 09:32:13.728448 ==
1200 09:32:13.731800 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 09:32:13.735284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 09:32:13.735755 ==
1203 09:32:13.738493 Write leveling (Byte 0): 30 => 30
1204 09:32:13.741631 Write leveling (Byte 1): 28 => 28
1205 09:32:13.745011 DramcWriteLeveling(PI) end<-----
1206 09:32:13.745432
1207 09:32:13.745815 ==
1208 09:32:13.748403 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 09:32:13.751973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 09:32:13.752390 ==
1211 09:32:13.755505 [Gating] SW mode calibration
1212 09:32:13.761762 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1213 09:32:13.765367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1214 09:32:13.771961 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 09:32:13.775499 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 09:32:13.778370 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1217 09:32:13.822975 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 09:32:13.823505 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 09:32:13.824320 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:32:13.824932 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:32:13.825275 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:32:13.825584 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:32:13.825951 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:32:13.826260 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:32:13.826549 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:32:13.826873 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:32:13.860615 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:32:13.861257 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:32:13.862085 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:32:13.862463 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:32:13.862830 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1232 09:32:13.863145 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1233 09:32:13.863441 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1234 09:32:13.863794 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 09:32:13.864738 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:32:13.868627 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:32:13.871470 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 09:32:13.874867 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 09:32:13.881894 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1240 09:32:13.884983 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1241 09:32:13.888530 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1242 09:32:13.895113 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 09:32:13.898501 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 09:32:13.902129 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 09:32:13.908397 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 09:32:13.911716 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 09:32:13.915364 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1248 09:32:13.921824 0 10 8 | B1->B0 | 3434 2727 | 0 0 | (1 0) (0 0)
1249 09:32:13.925027 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 09:32:13.928616 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 09:32:13.931683 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:32:13.938550 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 09:32:13.941706 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 09:32:13.945223 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 09:32:13.952170 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1256 09:32:13.956264 0 11 8 | B1->B0 | 3030 4343 | 0 1 | (0 0) (0 0)
1257 09:32:13.959956 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1258 09:32:13.964625 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 09:32:13.967706 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 09:32:13.974560 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 09:32:13.977547 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 09:32:13.981472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 09:32:13.985000 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1264 09:32:13.991899 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1265 09:32:13.995438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1266 09:32:13.998584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 09:32:14.005356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 09:32:14.008889 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:32:14.011846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:32:14.018709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 09:32:14.022171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:32:14.025531 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:32:14.028885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:32:14.035652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:32:14.039365 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 09:32:14.042262 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 09:32:14.048902 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 09:32:14.052115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:32:14.055787 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1280 09:32:14.062623 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1281 09:32:14.063077 Total UI for P1: 0, mck2ui 16
1282 09:32:14.065926 best dqsien dly found for B0: ( 0, 14, 4)
1283 09:32:14.072920 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 09:32:14.075795 Total UI for P1: 0, mck2ui 16
1285 09:32:14.079045 best dqsien dly found for B1: ( 0, 14, 8)
1286 09:32:14.082434 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1287 09:32:14.085887 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1288 09:32:14.086496
1289 09:32:14.089389 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1290 09:32:14.092365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1291 09:32:14.096117 [Gating] SW calibration Done
1292 09:32:14.096541 ==
1293 09:32:14.099255 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 09:32:14.102501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 09:32:14.103058 ==
1296 09:32:14.105993 RX Vref Scan: 0
1297 09:32:14.106415
1298 09:32:14.106818 RX Vref 0 -> 0, step: 1
1299 09:32:14.107149
1300 09:32:14.109483 RX Delay -130 -> 252, step: 16
1301 09:32:14.112468 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1302 09:32:14.119554 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1303 09:32:14.122488 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1304 09:32:14.125867 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1305 09:32:14.129583 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1306 09:32:14.133144 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1307 09:32:14.139412 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1308 09:32:14.143034 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1309 09:32:14.146415 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1310 09:32:14.150010 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1311 09:32:14.153718 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1312 09:32:14.160070 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1313 09:32:14.163484 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1314 09:32:14.166413 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1315 09:32:14.170188 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1316 09:32:14.173417 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1317 09:32:14.173844 ==
1318 09:32:14.176871 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 09:32:14.183404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 09:32:14.183833 ==
1321 09:32:14.184175 DQS Delay:
1322 09:32:14.186628 DQS0 = 0, DQS1 = 0
1323 09:32:14.187121 DQM Delay:
1324 09:32:14.187463 DQM0 = 86, DQM1 = 74
1325 09:32:14.189888 DQ Delay:
1326 09:32:14.193631 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1327 09:32:14.196660 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1328 09:32:14.200123 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1329 09:32:14.203682 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1330 09:32:14.204106
1331 09:32:14.204441
1332 09:32:14.204795 ==
1333 09:32:14.207088 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 09:32:14.210569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 09:32:14.211063 ==
1336 09:32:14.211449
1337 09:32:14.211762
1338 09:32:14.213618 TX Vref Scan disable
1339 09:32:14.214042 == TX Byte 0 ==
1340 09:32:14.220148 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1341 09:32:14.223571 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1342 09:32:14.223998 == TX Byte 1 ==
1343 09:32:14.230509 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1344 09:32:14.233542 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1345 09:32:14.233968 ==
1346 09:32:14.237288 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 09:32:14.240508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 09:32:14.240938 ==
1349 09:32:14.254367 TX Vref=22, minBit 1, minWin=27, winSum=443
1350 09:32:14.258271 TX Vref=24, minBit 2, minWin=27, winSum=444
1351 09:32:14.261168 TX Vref=26, minBit 12, minWin=27, winSum=452
1352 09:32:14.264728 TX Vref=28, minBit 12, minWin=27, winSum=453
1353 09:32:14.268001 TX Vref=30, minBit 0, minWin=28, winSum=453
1354 09:32:14.274878 TX Vref=32, minBit 0, minWin=28, winSum=452
1355 09:32:14.277603 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1356 09:32:14.278076
1357 09:32:14.281152 Final TX Range 1 Vref 30
1358 09:32:14.281621
1359 09:32:14.281992 ==
1360 09:32:14.284433 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 09:32:14.287949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 09:32:14.288453 ==
1363 09:32:14.288824
1364 09:32:14.291047
1365 09:32:14.291511 TX Vref Scan disable
1366 09:32:14.294377 == TX Byte 0 ==
1367 09:32:14.297439 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1368 09:32:14.300883 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1369 09:32:14.304414 == TX Byte 1 ==
1370 09:32:14.307732 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1371 09:32:14.311012 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1372 09:32:14.314116
1373 09:32:14.314414 [DATLAT]
1374 09:32:14.314651 Freq=800, CH0 RK1
1375 09:32:14.314941
1376 09:32:14.317691 DATLAT Default: 0xa
1377 09:32:14.318114 0, 0xFFFF, sum = 0
1378 09:32:14.321287 1, 0xFFFF, sum = 0
1379 09:32:14.321866 2, 0xFFFF, sum = 0
1380 09:32:14.324750 3, 0xFFFF, sum = 0
1381 09:32:14.325177 4, 0xFFFF, sum = 0
1382 09:32:14.328340 5, 0xFFFF, sum = 0
1383 09:32:14.328765 6, 0xFFFF, sum = 0
1384 09:32:14.331256 7, 0xFFFF, sum = 0
1385 09:32:14.331679 8, 0xFFFF, sum = 0
1386 09:32:14.334846 9, 0x0, sum = 1
1387 09:32:14.335274 10, 0x0, sum = 2
1388 09:32:14.338305 11, 0x0, sum = 3
1389 09:32:14.338769 12, 0x0, sum = 4
1390 09:32:14.341225 best_step = 10
1391 09:32:14.341794
1392 09:32:14.342181 ==
1393 09:32:14.344448 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 09:32:14.348061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 09:32:14.348485 ==
1396 09:32:14.351505 RX Vref Scan: 0
1397 09:32:14.352104
1398 09:32:14.352473 RX Vref 0 -> 0, step: 1
1399 09:32:14.352790
1400 09:32:14.354868 RX Delay -111 -> 252, step: 8
1401 09:32:14.361813 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1402 09:32:14.364729 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1403 09:32:14.368157 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1404 09:32:14.371714 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1405 09:32:14.374625 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1406 09:32:14.378225 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1407 09:32:14.384748 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1408 09:32:14.388337 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1409 09:32:14.391693 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1410 09:32:14.394658 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1411 09:32:14.398160 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1412 09:32:14.405311 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1413 09:32:14.408616 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1414 09:32:14.412012 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1415 09:32:14.415186 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1416 09:32:14.418511 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1417 09:32:14.422234 ==
1418 09:32:14.422652 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 09:32:14.428882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 09:32:14.429308 ==
1421 09:32:14.429643 DQS Delay:
1422 09:32:14.432206 DQS0 = 0, DQS1 = 0
1423 09:32:14.432628 DQM Delay:
1424 09:32:14.432962 DQM0 = 87, DQM1 = 78
1425 09:32:14.435795 DQ Delay:
1426 09:32:14.438714 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1427 09:32:14.442184 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1428 09:32:14.445846 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1429 09:32:14.449309 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1430 09:32:14.449849
1431 09:32:14.450208
1432 09:32:14.455902 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1433 09:32:14.458669 CH0 RK1: MR19=606, MR18=2D17
1434 09:32:14.465756 CH0_RK1: MR19=0x606, MR18=0x2D17, DQSOSC=398, MR23=63, INC=93, DEC=62
1435 09:32:14.469248 [RxdqsGatingPostProcess] freq 800
1436 09:32:14.472746 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1437 09:32:14.475646 Pre-setting of DQS Precalculation
1438 09:32:14.482546 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1439 09:32:14.483026 ==
1440 09:32:14.486019 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 09:32:14.489017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 09:32:14.489537 ==
1443 09:32:14.496281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 09:32:14.498957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 09:32:14.509356 [CA 0] Center 36 (6~67) winsize 62
1446 09:32:14.512753 [CA 1] Center 36 (5~67) winsize 63
1447 09:32:14.516289 [CA 2] Center 34 (4~65) winsize 62
1448 09:32:14.519341 [CA 3] Center 33 (3~64) winsize 62
1449 09:32:14.523078 [CA 4] Center 34 (3~65) winsize 63
1450 09:32:14.526593 [CA 5] Center 33 (3~64) winsize 62
1451 09:32:14.527180
1452 09:32:14.529826 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1453 09:32:14.530273
1454 09:32:14.533031 [CATrainingPosCal] consider 1 rank data
1455 09:32:14.536392 u2DelayCellTimex100 = 270/100 ps
1456 09:32:14.539763 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1457 09:32:14.543110 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1458 09:32:14.546639 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1459 09:32:14.550056 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 09:32:14.556387 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1461 09:32:14.559904 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 09:32:14.560326
1463 09:32:14.563015 CA PerBit enable=1, Macro0, CA PI delay=33
1464 09:32:14.563098
1465 09:32:14.566299 [CBTSetCACLKResult] CA Dly = 33
1466 09:32:14.566381 CS Dly: 5 (0~36)
1467 09:32:14.566447 ==
1468 09:32:14.569570 Dram Type= 6, Freq= 0, CH_1, rank 1
1469 09:32:14.576169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 09:32:14.576252 ==
1471 09:32:14.579523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1472 09:32:14.586053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1473 09:32:14.595595 [CA 0] Center 36 (5~67) winsize 63
1474 09:32:14.598628 [CA 1] Center 36 (6~67) winsize 62
1475 09:32:14.602182 [CA 2] Center 33 (3~64) winsize 62
1476 09:32:14.605747 [CA 3] Center 33 (3~64) winsize 62
1477 09:32:14.608497 [CA 4] Center 34 (3~65) winsize 63
1478 09:32:14.611988 [CA 5] Center 33 (3~64) winsize 62
1479 09:32:14.612168
1480 09:32:14.615261 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1481 09:32:14.615449
1482 09:32:14.618685 [CATrainingPosCal] consider 2 rank data
1483 09:32:14.622793 u2DelayCellTimex100 = 270/100 ps
1484 09:32:14.626205 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1485 09:32:14.630334 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1486 09:32:14.633911 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1487 09:32:14.637459 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1488 09:32:14.641736 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1489 09:32:14.645050 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 09:32:14.645154
1491 09:32:14.648785 CA PerBit enable=1, Macro0, CA PI delay=33
1492 09:32:14.648898
1493 09:32:14.652763 [CBTSetCACLKResult] CA Dly = 33
1494 09:32:14.652886 CS Dly: 5 (0~37)
1495 09:32:14.652985
1496 09:32:14.656188 ----->DramcWriteLeveling(PI) begin...
1497 09:32:14.656420 ==
1498 09:32:14.659601 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 09:32:14.662743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 09:32:14.666277 ==
1501 09:32:14.666506 Write leveling (Byte 0): 27 => 27
1502 09:32:14.669666 Write leveling (Byte 1): 30 => 30
1503 09:32:14.673149 DramcWriteLeveling(PI) end<-----
1504 09:32:14.673441
1505 09:32:14.673616 ==
1506 09:32:14.676090 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 09:32:14.682964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 09:32:14.683282 ==
1509 09:32:14.683545 [Gating] SW mode calibration
1510 09:32:14.692994 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1511 09:32:14.696522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1512 09:32:14.700046 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1513 09:32:14.706596 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 09:32:14.710058 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1515 09:32:14.713026 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 09:32:14.719687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 09:32:14.723244 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:32:14.726764 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:32:14.733417 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:32:14.736892 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:32:14.740252 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:32:14.746503 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1523 09:32:14.749779 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:32:14.753297 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1525 09:32:14.756805 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1526 09:32:14.763679 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:32:14.766973 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1528 09:32:14.770095 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1529 09:32:14.776914 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1530 09:32:14.780375 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1531 09:32:14.783725 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 09:32:14.790424 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:32:14.794197 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:32:14.797359 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 09:32:14.804005 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 09:32:14.807381 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 09:32:14.811211 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 09:32:14.813989 0 9 8 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1539 09:32:14.820957 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1540 09:32:14.824273 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 09:32:14.827741 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 09:32:14.834311 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 09:32:14.837768 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1544 09:32:14.841098 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1545 09:32:14.847361 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
1546 09:32:14.850717 0 10 8 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (1 1)
1547 09:32:14.854538 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1548 09:32:14.861160 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 09:32:14.864514 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1550 09:32:14.867568 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 09:32:14.871431 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 09:32:14.877821 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 09:32:14.881473 0 11 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
1554 09:32:14.884630 0 11 8 | B1->B0 | 3838 3c3c | 0 1 | (0 0) (0 0)
1555 09:32:14.891228 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 09:32:14.894683 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 09:32:14.897685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 09:32:14.904655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 09:32:14.907585 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 09:32:14.911086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 09:32:14.918101 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1562 09:32:14.920939 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1563 09:32:14.924426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 09:32:14.931461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 09:32:14.934309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:32:14.938120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:32:14.944565 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:32:14.948004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:32:14.951577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:32:14.954510 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:32:14.961391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:32:14.964187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:32:14.968104 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:32:14.974438 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 09:32:14.977953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 09:32:14.981402 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 09:32:14.988159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 09:32:14.991501 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 09:32:14.994796 Total UI for P1: 0, mck2ui 16
1580 09:32:14.997851 best dqsien dly found for B0: ( 0, 14, 4)
1581 09:32:15.001440 Total UI for P1: 0, mck2ui 16
1582 09:32:15.004755 best dqsien dly found for B1: ( 0, 14, 4)
1583 09:32:15.008107 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1584 09:32:15.011284 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1585 09:32:15.011736
1586 09:32:15.014866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1587 09:32:15.017855 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1588 09:32:15.021386 [Gating] SW calibration Done
1589 09:32:15.021821 ==
1590 09:32:15.024941 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 09:32:15.027957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 09:32:15.028394 ==
1593 09:32:15.031385 RX Vref Scan: 0
1594 09:32:15.031957
1595 09:32:15.034837 RX Vref 0 -> 0, step: 1
1596 09:32:15.035273
1597 09:32:15.035710 RX Delay -130 -> 252, step: 16
1598 09:32:15.041233 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1599 09:32:15.044854 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1600 09:32:15.048083 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1601 09:32:15.051441 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1602 09:32:15.054843 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1603 09:32:15.061803 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1604 09:32:15.065082 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1605 09:32:15.068032 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1606 09:32:15.071602 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1607 09:32:15.074588 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1608 09:32:15.078114 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1609 09:32:15.084653 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1610 09:32:15.088278 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1611 09:32:15.091292 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1612 09:32:15.094843 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1613 09:32:15.098182 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1614 09:32:15.101432 ==
1615 09:32:15.104858 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 09:32:15.108392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 09:32:15.108498 ==
1618 09:32:15.108603 DQS Delay:
1619 09:32:15.111587 DQS0 = 0, DQS1 = 0
1620 09:32:15.111666 DQM Delay:
1621 09:32:15.114981 DQM0 = 80, DQM1 = 76
1622 09:32:15.115069 DQ Delay:
1623 09:32:15.118038 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1624 09:32:15.121417 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1625 09:32:15.124994 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1626 09:32:15.128413 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1627 09:32:15.128527
1628 09:32:15.128625
1629 09:32:15.128722 ==
1630 09:32:15.131955 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 09:32:15.134705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 09:32:15.134830 ==
1633 09:32:15.134924
1634 09:32:15.134995
1635 09:32:15.138625 TX Vref Scan disable
1636 09:32:15.141584 == TX Byte 0 ==
1637 09:32:15.145159 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1638 09:32:15.148588 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1639 09:32:15.148702 == TX Byte 1 ==
1640 09:32:15.155201 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1641 09:32:15.158667 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1642 09:32:15.158779 ==
1643 09:32:15.161583 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 09:32:15.165012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 09:32:15.165114 ==
1646 09:32:15.179699 TX Vref=22, minBit 8, minWin=26, winSum=431
1647 09:32:15.182954 TX Vref=24, minBit 11, minWin=26, winSum=438
1648 09:32:15.186388 TX Vref=26, minBit 11, minWin=26, winSum=442
1649 09:32:15.189397 TX Vref=28, minBit 3, minWin=27, winSum=448
1650 09:32:15.192828 TX Vref=30, minBit 13, minWin=27, winSum=449
1651 09:32:15.196617 TX Vref=32, minBit 5, minWin=28, winSum=454
1652 09:32:15.203634 [TxChooseVref] Worse bit 5, Min win 28, Win sum 454, Final Vref 32
1653 09:32:15.203742
1654 09:32:15.207222 Final TX Range 1 Vref 32
1655 09:32:15.207324
1656 09:32:15.207423 ==
1657 09:32:15.210699 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 09:32:15.214002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 09:32:15.214084 ==
1660 09:32:15.214184
1661 09:32:15.214282
1662 09:32:15.217557 TX Vref Scan disable
1663 09:32:15.220651 == TX Byte 0 ==
1664 09:32:15.224374 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1665 09:32:15.227252 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1666 09:32:15.230953 == TX Byte 1 ==
1667 09:32:15.233911 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1668 09:32:15.237407 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1669 09:32:15.237511
1670 09:32:15.237617 [DATLAT]
1671 09:32:15.240848 Freq=800, CH1 RK0
1672 09:32:15.240950
1673 09:32:15.244365 DATLAT Default: 0xa
1674 09:32:15.244464 0, 0xFFFF, sum = 0
1675 09:32:15.247342 1, 0xFFFF, sum = 0
1676 09:32:15.247425 2, 0xFFFF, sum = 0
1677 09:32:15.250853 3, 0xFFFF, sum = 0
1678 09:32:15.250938 4, 0xFFFF, sum = 0
1679 09:32:15.254342 5, 0xFFFF, sum = 0
1680 09:32:15.254442 6, 0xFFFF, sum = 0
1681 09:32:15.258002 7, 0xFFFF, sum = 0
1682 09:32:15.258102 8, 0xFFFF, sum = 0
1683 09:32:15.261433 9, 0x0, sum = 1
1684 09:32:15.261537 10, 0x0, sum = 2
1685 09:32:15.261630 11, 0x0, sum = 3
1686 09:32:15.264314 12, 0x0, sum = 4
1687 09:32:15.264406 best_step = 10
1688 09:32:15.264498
1689 09:32:15.267817 ==
1690 09:32:15.267916 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 09:32:15.274672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 09:32:15.274790 ==
1693 09:32:15.274897 RX Vref Scan: 1
1694 09:32:15.275031
1695 09:32:15.277626 Set Vref Range= 32 -> 127
1696 09:32:15.277780
1697 09:32:15.281300 RX Vref 32 -> 127, step: 1
1698 09:32:15.281426
1699 09:32:15.284650 RX Delay -111 -> 252, step: 8
1700 09:32:15.284820
1701 09:32:15.288162 Set Vref, RX VrefLevel [Byte0]: 32
1702 09:32:15.291891 [Byte1]: 32
1703 09:32:15.292493
1704 09:32:15.294852 Set Vref, RX VrefLevel [Byte0]: 33
1705 09:32:15.298306 [Byte1]: 33
1706 09:32:15.298763
1707 09:32:15.301810 Set Vref, RX VrefLevel [Byte0]: 34
1708 09:32:15.305134 [Byte1]: 34
1709 09:32:15.305558
1710 09:32:15.308320 Set Vref, RX VrefLevel [Byte0]: 35
1711 09:32:15.311758 [Byte1]: 35
1712 09:32:15.315849
1713 09:32:15.316272 Set Vref, RX VrefLevel [Byte0]: 36
1714 09:32:15.319024 [Byte1]: 36
1715 09:32:15.323382
1716 09:32:15.323801 Set Vref, RX VrefLevel [Byte0]: 37
1717 09:32:15.327197 [Byte1]: 37
1718 09:32:15.331316
1719 09:32:15.331774 Set Vref, RX VrefLevel [Byte0]: 38
1720 09:32:15.334440 [Byte1]: 38
1721 09:32:15.338755
1722 09:32:15.339175 Set Vref, RX VrefLevel [Byte0]: 39
1723 09:32:15.341855 [Byte1]: 39
1724 09:32:15.346256
1725 09:32:15.346691 Set Vref, RX VrefLevel [Byte0]: 40
1726 09:32:15.349564 [Byte1]: 40
1727 09:32:15.354257
1728 09:32:15.354688 Set Vref, RX VrefLevel [Byte0]: 41
1729 09:32:15.357857 [Byte1]: 41
1730 09:32:15.361901
1731 09:32:15.362441 Set Vref, RX VrefLevel [Byte0]: 42
1732 09:32:15.365222 [Byte1]: 42
1733 09:32:15.369344
1734 09:32:15.369764 Set Vref, RX VrefLevel [Byte0]: 43
1735 09:32:15.372857 [Byte1]: 43
1736 09:32:15.377318
1737 09:32:15.377742 Set Vref, RX VrefLevel [Byte0]: 44
1738 09:32:15.380097 [Byte1]: 44
1739 09:32:15.384784
1740 09:32:15.385216 Set Vref, RX VrefLevel [Byte0]: 45
1741 09:32:15.388554 [Byte1]: 45
1742 09:32:15.392428
1743 09:32:15.393015 Set Vref, RX VrefLevel [Byte0]: 46
1744 09:32:15.396027 [Byte1]: 46
1745 09:32:15.400115
1746 09:32:15.400534 Set Vref, RX VrefLevel [Byte0]: 47
1747 09:32:15.403010 [Byte1]: 47
1748 09:32:15.407527
1749 09:32:15.408082 Set Vref, RX VrefLevel [Byte0]: 48
1750 09:32:15.411002 [Byte1]: 48
1751 09:32:15.415228
1752 09:32:15.415667 Set Vref, RX VrefLevel [Byte0]: 49
1753 09:32:15.418792 [Byte1]: 49
1754 09:32:15.422717
1755 09:32:15.423181 Set Vref, RX VrefLevel [Byte0]: 50
1756 09:32:15.426335 [Byte1]: 50
1757 09:32:15.430707
1758 09:32:15.431168 Set Vref, RX VrefLevel [Byte0]: 51
1759 09:32:15.434415 [Byte1]: 51
1760 09:32:15.438224
1761 09:32:15.438858 Set Vref, RX VrefLevel [Byte0]: 52
1762 09:32:15.441400 [Byte1]: 52
1763 09:32:15.445775
1764 09:32:15.446209 Set Vref, RX VrefLevel [Byte0]: 53
1765 09:32:15.449323 [Byte1]: 53
1766 09:32:15.453994
1767 09:32:15.454528 Set Vref, RX VrefLevel [Byte0]: 54
1768 09:32:15.456889 [Byte1]: 54
1769 09:32:15.461572
1770 09:32:15.462101 Set Vref, RX VrefLevel [Byte0]: 55
1771 09:32:15.464508 [Byte1]: 55
1772 09:32:15.468946
1773 09:32:15.469467 Set Vref, RX VrefLevel [Byte0]: 56
1774 09:32:15.472196 [Byte1]: 56
1775 09:32:15.476891
1776 09:32:15.477387 Set Vref, RX VrefLevel [Byte0]: 57
1777 09:32:15.479571 [Byte1]: 57
1778 09:32:15.484129
1779 09:32:15.487303 Set Vref, RX VrefLevel [Byte0]: 58
1780 09:32:15.488001 [Byte1]: 58
1781 09:32:15.491887
1782 09:32:15.492481 Set Vref, RX VrefLevel [Byte0]: 59
1783 09:32:15.494713 [Byte1]: 59
1784 09:32:15.499216
1785 09:32:15.499812 Set Vref, RX VrefLevel [Byte0]: 60
1786 09:32:15.502810 [Byte1]: 60
1787 09:32:15.507002
1788 09:32:15.507506 Set Vref, RX VrefLevel [Byte0]: 61
1789 09:32:15.510394 [Byte1]: 61
1790 09:32:15.514850
1791 09:32:15.515530 Set Vref, RX VrefLevel [Byte0]: 62
1792 09:32:15.517705 [Byte1]: 62
1793 09:32:15.522438
1794 09:32:15.523003 Set Vref, RX VrefLevel [Byte0]: 63
1795 09:32:15.525424 [Byte1]: 63
1796 09:32:15.530220
1797 09:32:15.530839 Set Vref, RX VrefLevel [Byte0]: 64
1798 09:32:15.532953 [Byte1]: 64
1799 09:32:15.537622
1800 09:32:15.538224 Set Vref, RX VrefLevel [Byte0]: 65
1801 09:32:15.541093 [Byte1]: 65
1802 09:32:15.544923
1803 09:32:15.545357 Set Vref, RX VrefLevel [Byte0]: 66
1804 09:32:15.548497 [Byte1]: 66
1805 09:32:15.552915
1806 09:32:15.553493 Set Vref, RX VrefLevel [Byte0]: 67
1807 09:32:15.556035 [Byte1]: 67
1808 09:32:15.560372
1809 09:32:15.561002 Set Vref, RX VrefLevel [Byte0]: 68
1810 09:32:15.563917 [Byte1]: 68
1811 09:32:15.568139
1812 09:32:15.568703 Set Vref, RX VrefLevel [Byte0]: 69
1813 09:32:15.571272 [Byte1]: 69
1814 09:32:15.576229
1815 09:32:15.576783 Set Vref, RX VrefLevel [Byte0]: 70
1816 09:32:15.578894 [Byte1]: 70
1817 09:32:15.583305
1818 09:32:15.583845 Set Vref, RX VrefLevel [Byte0]: 71
1819 09:32:15.586440 [Byte1]: 71
1820 09:32:15.590865
1821 09:32:15.591492 Set Vref, RX VrefLevel [Byte0]: 72
1822 09:32:15.594565 [Byte1]: 72
1823 09:32:15.598682
1824 09:32:15.599250 Set Vref, RX VrefLevel [Byte0]: 73
1825 09:32:15.601952 [Byte1]: 73
1826 09:32:15.606519
1827 09:32:15.607107 Set Vref, RX VrefLevel [Byte0]: 74
1828 09:32:15.609446 [Byte1]: 74
1829 09:32:15.614144
1830 09:32:15.614582 Set Vref, RX VrefLevel [Byte0]: 75
1831 09:32:15.617456 [Byte1]: 75
1832 09:32:15.621539
1833 09:32:15.622090 Set Vref, RX VrefLevel [Byte0]: 76
1834 09:32:15.625286 [Byte1]: 76
1835 09:32:15.629341
1836 09:32:15.629753 Set Vref, RX VrefLevel [Byte0]: 77
1837 09:32:15.632891 [Byte1]: 77
1838 09:32:15.637100
1839 09:32:15.637509 Final RX Vref Byte 0 = 65 to rank0
1840 09:32:15.640503 Final RX Vref Byte 1 = 59 to rank0
1841 09:32:15.643945 Final RX Vref Byte 0 = 65 to rank1
1842 09:32:15.647013 Final RX Vref Byte 1 = 59 to rank1==
1843 09:32:15.650793 Dram Type= 6, Freq= 0, CH_1, rank 0
1844 09:32:15.653652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 09:32:15.657033 ==
1846 09:32:15.657522 DQS Delay:
1847 09:32:15.657988 DQS0 = 0, DQS1 = 0
1848 09:32:15.660430 DQM Delay:
1849 09:32:15.660981 DQM0 = 83, DQM1 = 74
1850 09:32:15.663813 DQ Delay:
1851 09:32:15.667261 DQ0 =92, DQ1 =76, DQ2 =76, DQ3 =80
1852 09:32:15.667703 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1853 09:32:15.670523 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =76
1854 09:32:15.673643 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1855 09:32:15.674120
1856 09:32:15.677415
1857 09:32:15.683709 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1858 09:32:15.687381 CH1 RK0: MR19=606, MR18=2B01
1859 09:32:15.693773 CH1_RK0: MR19=0x606, MR18=0x2B01, DQSOSC=398, MR23=63, INC=93, DEC=62
1860 09:32:15.694333
1861 09:32:15.697618 ----->DramcWriteLeveling(PI) begin...
1862 09:32:15.698038 ==
1863 09:32:15.700728 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 09:32:15.703970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 09:32:15.704391 ==
1866 09:32:15.707218 Write leveling (Byte 0): 29 => 29
1867 09:32:15.710779 Write leveling (Byte 1): 27 => 27
1868 09:32:15.713814 DramcWriteLeveling(PI) end<-----
1869 09:32:15.714331
1870 09:32:15.714773 ==
1871 09:32:15.717265 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 09:32:15.720929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 09:32:15.721505 ==
1874 09:32:15.724304 [Gating] SW mode calibration
1875 09:32:15.730778 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1876 09:32:15.734192 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1877 09:32:15.741270 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1878 09:32:15.744210 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1879 09:32:15.747594 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:32:15.754515 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 09:32:15.757944 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1882 09:32:15.761367 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 09:32:15.768068 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:32:15.771562 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:32:15.774691 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:32:15.781225 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:32:15.784882 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:32:15.788051 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1889 09:32:15.791312 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1890 09:32:15.798474 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 09:32:15.801922 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1892 09:32:15.805040 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1893 09:32:15.811556 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1894 09:32:15.815271 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1895 09:32:15.818384 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1896 09:32:15.825436 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:32:15.828313 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 09:32:15.831820 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1899 09:32:15.838334 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 09:32:15.841819 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 09:32:15.845185 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:32:15.851572 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1903 09:32:15.855097 0 9 8 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
1904 09:32:15.858494 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 09:32:15.862247 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 09:32:15.868482 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 09:32:15.871949 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1908 09:32:15.875469 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 09:32:15.881757 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 1) (1 0)
1910 09:32:15.885079 0 10 4 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
1911 09:32:15.888418 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1912 09:32:15.894968 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 09:32:15.898823 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 09:32:15.901974 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 09:32:15.908935 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 09:32:15.911813 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 09:32:15.915745 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 09:32:15.919110 0 11 4 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (0 0)
1919 09:32:15.925473 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1920 09:32:15.928695 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 09:32:15.932335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 09:32:15.938579 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 09:32:15.942077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 09:32:15.944974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 09:32:15.952097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 09:32:15.955036 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1927 09:32:15.958456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1928 09:32:15.965295 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 09:32:15.968818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 09:32:15.971651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 09:32:15.978740 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 09:32:15.982349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 09:32:15.985281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 09:32:15.988752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 09:32:15.995433 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 09:32:15.998767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 09:32:16.002414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 09:32:16.009157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 09:32:16.012203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 09:32:16.015762 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 09:32:16.022162 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 09:32:16.025573 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1943 09:32:16.029218 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 09:32:16.032486 Total UI for P1: 0, mck2ui 16
1945 09:32:16.035813 best dqsien dly found for B0: ( 0, 14, 4)
1946 09:32:16.039127 Total UI for P1: 0, mck2ui 16
1947 09:32:16.042258 best dqsien dly found for B1: ( 0, 14, 6)
1948 09:32:16.045814 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1949 09:32:16.049155 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1950 09:32:16.049238
1951 09:32:16.052632 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1952 09:32:16.059207 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1953 09:32:16.059289 [Gating] SW calibration Done
1954 09:32:16.059356 ==
1955 09:32:16.062865 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 09:32:16.069683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 09:32:16.069781 ==
1958 09:32:16.069857 RX Vref Scan: 0
1959 09:32:16.069927
1960 09:32:16.072604 RX Vref 0 -> 0, step: 1
1961 09:32:16.072707
1962 09:32:16.075855 RX Delay -130 -> 252, step: 16
1963 09:32:16.079292 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1964 09:32:16.082679 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1965 09:32:16.086279 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1966 09:32:16.089837 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1967 09:32:16.096141 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1968 09:32:16.099670 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1969 09:32:16.102647 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1970 09:32:16.106621 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1971 09:32:16.109869 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1972 09:32:16.116267 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1973 09:32:16.120020 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1974 09:32:16.123305 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1975 09:32:16.126948 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1976 09:32:16.129862 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1977 09:32:16.137017 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1978 09:32:16.139674 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1979 09:32:16.140104 ==
1980 09:32:16.143761 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 09:32:16.146630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 09:32:16.147122 ==
1983 09:32:16.147463 DQS Delay:
1984 09:32:16.149894 DQS0 = 0, DQS1 = 0
1985 09:32:16.150317 DQM Delay:
1986 09:32:16.153595 DQM0 = 79, DQM1 = 74
1987 09:32:16.154018 DQ Delay:
1988 09:32:16.156766 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1989 09:32:16.159942 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1990 09:32:16.163490 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1991 09:32:16.166956 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1992 09:32:16.167389
1993 09:32:16.167725
1994 09:32:16.168040 ==
1995 09:32:16.170416 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 09:32:16.173252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 09:32:16.176873 ==
1998 09:32:16.177286
1999 09:32:16.177659
2000 09:32:16.178010 TX Vref Scan disable
2001 09:32:16.180137 == TX Byte 0 ==
2002 09:32:16.183748 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2003 09:32:16.186781 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2004 09:32:16.190197 == TX Byte 1 ==
2005 09:32:16.193835 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2006 09:32:16.196667 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2007 09:32:16.197193 ==
2008 09:32:16.199989 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 09:32:16.206934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 09:32:16.207354 ==
2011 09:32:16.219009 TX Vref=22, minBit 15, minWin=26, winSum=441
2012 09:32:16.222268 TX Vref=24, minBit 8, minWin=27, winSum=442
2013 09:32:16.225902 TX Vref=26, minBit 9, minWin=27, winSum=446
2014 09:32:16.229056 TX Vref=28, minBit 12, minWin=26, winSum=446
2015 09:32:16.232671 TX Vref=30, minBit 10, minWin=27, winSum=450
2016 09:32:16.239086 TX Vref=32, minBit 11, minWin=27, winSum=451
2017 09:32:16.242821 [TxChooseVref] Worse bit 11, Min win 27, Win sum 451, Final Vref 32
2018 09:32:16.243247
2019 09:32:16.245530 Final TX Range 1 Vref 32
2020 09:32:16.245999
2021 09:32:16.246377 ==
2022 09:32:16.248744 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 09:32:16.252279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 09:32:16.252804 ==
2025 09:32:16.255862
2026 09:32:16.256339
2027 09:32:16.256731 TX Vref Scan disable
2028 09:32:16.259638 == TX Byte 0 ==
2029 09:32:16.262899 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2030 09:32:16.266253 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2031 09:32:16.269681 == TX Byte 1 ==
2032 09:32:16.273226 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2033 09:32:16.275997 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2034 09:32:16.279403
2035 09:32:16.279820 [DATLAT]
2036 09:32:16.280153 Freq=800, CH1 RK1
2037 09:32:16.280466
2038 09:32:16.282365 DATLAT Default: 0xa
2039 09:32:16.282815 0, 0xFFFF, sum = 0
2040 09:32:16.286210 1, 0xFFFF, sum = 0
2041 09:32:16.286635 2, 0xFFFF, sum = 0
2042 09:32:16.289247 3, 0xFFFF, sum = 0
2043 09:32:16.289671 4, 0xFFFF, sum = 0
2044 09:32:16.292796 5, 0xFFFF, sum = 0
2045 09:32:16.293220 6, 0xFFFF, sum = 0
2046 09:32:16.296395 7, 0xFFFF, sum = 0
2047 09:32:16.296943 8, 0xFFFF, sum = 0
2048 09:32:16.299328 9, 0x0, sum = 1
2049 09:32:16.299901 10, 0x0, sum = 2
2050 09:32:16.302695 11, 0x0, sum = 3
2051 09:32:16.303302 12, 0x0, sum = 4
2052 09:32:16.305988 best_step = 10
2053 09:32:16.306519
2054 09:32:16.307006 ==
2055 09:32:16.309615 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 09:32:16.313040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 09:32:16.313592 ==
2058 09:32:16.316011 RX Vref Scan: 0
2059 09:32:16.316590
2060 09:32:16.317114 RX Vref 0 -> 0, step: 1
2061 09:32:16.317572
2062 09:32:16.319558 RX Delay -111 -> 252, step: 8
2063 09:32:16.326325 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2064 09:32:16.329788 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2065 09:32:16.333154 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2066 09:32:16.336302 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2067 09:32:16.339349 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2068 09:32:16.342887 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2069 09:32:16.349665 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2070 09:32:16.352599 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2071 09:32:16.355958 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2072 09:32:16.359443 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2073 09:32:16.362863 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2074 09:32:16.369709 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2075 09:32:16.372928 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2076 09:32:16.376358 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2077 09:32:16.379800 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2078 09:32:16.383034 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2079 09:32:16.386024 ==
2080 09:32:16.389448 Dram Type= 6, Freq= 0, CH_1, rank 1
2081 09:32:16.392869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2082 09:32:16.392952 ==
2083 09:32:16.393017 DQS Delay:
2084 09:32:16.396397 DQS0 = 0, DQS1 = 0
2085 09:32:16.396478 DQM Delay:
2086 09:32:16.399416 DQM0 = 79, DQM1 = 76
2087 09:32:16.399498 DQ Delay:
2088 09:32:16.402877 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2089 09:32:16.406695 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2090 09:32:16.410041 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2091 09:32:16.412987 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2092 09:32:16.413070
2093 09:32:16.413134
2094 09:32:16.419938 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2095 09:32:16.423420 CH1 RK1: MR19=606, MR18=222D
2096 09:32:16.429733 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2097 09:32:16.433219 [RxdqsGatingPostProcess] freq 800
2098 09:32:16.436601 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2099 09:32:16.440194 Pre-setting of DQS Precalculation
2100 09:32:16.446472 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2101 09:32:16.453362 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2102 09:32:16.460057 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2103 09:32:16.460141
2104 09:32:16.460220
2105 09:32:16.463623 [Calibration Summary] 1600 Mbps
2106 09:32:16.463699 CH 0, Rank 0
2107 09:32:16.466874 SW Impedance : PASS
2108 09:32:16.470231 DUTY Scan : NO K
2109 09:32:16.470330 ZQ Calibration : PASS
2110 09:32:16.473715 Jitter Meter : NO K
2111 09:32:16.476671 CBT Training : PASS
2112 09:32:16.476745 Write leveling : PASS
2113 09:32:16.480795 RX DQS gating : PASS
2114 09:32:16.480867 RX DQ/DQS(RDDQC) : PASS
2115 09:32:16.483382 TX DQ/DQS : PASS
2116 09:32:16.486846 RX DATLAT : PASS
2117 09:32:16.486918 RX DQ/DQS(Engine): PASS
2118 09:32:16.490375 TX OE : NO K
2119 09:32:16.490454 All Pass.
2120 09:32:16.490514
2121 09:32:16.493713 CH 0, Rank 1
2122 09:32:16.493820 SW Impedance : PASS
2123 09:32:16.497231 DUTY Scan : NO K
2124 09:32:16.500786 ZQ Calibration : PASS
2125 09:32:16.500857 Jitter Meter : NO K
2126 09:32:16.503648 CBT Training : PASS
2127 09:32:16.507151 Write leveling : PASS
2128 09:32:16.507222 RX DQS gating : PASS
2129 09:32:16.510604 RX DQ/DQS(RDDQC) : PASS
2130 09:32:16.510698 TX DQ/DQS : PASS
2131 09:32:16.513971 RX DATLAT : PASS
2132 09:32:16.517468 RX DQ/DQS(Engine): PASS
2133 09:32:16.517543 TX OE : NO K
2134 09:32:16.520386 All Pass.
2135 09:32:16.520454
2136 09:32:16.520514 CH 1, Rank 0
2137 09:32:16.524046 SW Impedance : PASS
2138 09:32:16.524115 DUTY Scan : NO K
2139 09:32:16.527460 ZQ Calibration : PASS
2140 09:32:16.530744 Jitter Meter : NO K
2141 09:32:16.530818 CBT Training : PASS
2142 09:32:16.534230 Write leveling : PASS
2143 09:32:16.537085 RX DQS gating : PASS
2144 09:32:16.537156 RX DQ/DQS(RDDQC) : PASS
2145 09:32:16.540483 TX DQ/DQS : PASS
2146 09:32:16.544007 RX DATLAT : PASS
2147 09:32:16.544076 RX DQ/DQS(Engine): PASS
2148 09:32:16.547508 TX OE : NO K
2149 09:32:16.547576 All Pass.
2150 09:32:16.547643
2151 09:32:16.550465 CH 1, Rank 1
2152 09:32:16.550537 SW Impedance : PASS
2153 09:32:16.553959 DUTY Scan : NO K
2154 09:32:16.554029 ZQ Calibration : PASS
2155 09:32:16.557213 Jitter Meter : NO K
2156 09:32:16.560962 CBT Training : PASS
2157 09:32:16.561032 Write leveling : PASS
2158 09:32:16.564135 RX DQS gating : PASS
2159 09:32:16.567745 RX DQ/DQS(RDDQC) : PASS
2160 09:32:16.567825 TX DQ/DQS : PASS
2161 09:32:16.570692 RX DATLAT : PASS
2162 09:32:16.574415 RX DQ/DQS(Engine): PASS
2163 09:32:16.574485 TX OE : NO K
2164 09:32:16.574546 All Pass.
2165 09:32:16.577409
2166 09:32:16.577484 DramC Write-DBI off
2167 09:32:16.581125 PER_BANK_REFRESH: Hybrid Mode
2168 09:32:16.581199 TX_TRACKING: ON
2169 09:32:16.584432 [GetDramInforAfterCalByMRR] Vendor 6.
2170 09:32:16.587759 [GetDramInforAfterCalByMRR] Revision 606.
2171 09:32:16.594253 [GetDramInforAfterCalByMRR] Revision 2 0.
2172 09:32:16.594333 MR0 0x3b3b
2173 09:32:16.594406 MR8 0x5151
2174 09:32:16.597715 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 09:32:16.597789
2176 09:32:16.601100 MR0 0x3b3b
2177 09:32:16.601172 MR8 0x5151
2178 09:32:16.604184 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 09:32:16.604253
2180 09:32:16.614520 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2181 09:32:16.617883 [FAST_K] Save calibration result to emmc
2182 09:32:16.621224 [FAST_K] Save calibration result to emmc
2183 09:32:16.624731 dram_init: config_dvfs: 1
2184 09:32:16.627731 dramc_set_vcore_voltage set vcore to 662500
2185 09:32:16.627840 Read voltage for 1200, 2
2186 09:32:16.631257 Vio18 = 0
2187 09:32:16.631326 Vcore = 662500
2188 09:32:16.631386 Vdram = 0
2189 09:32:16.634584 Vddq = 0
2190 09:32:16.634662 Vmddr = 0
2191 09:32:16.637585 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2192 09:32:16.644830 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2193 09:32:16.647627 MEM_TYPE=3, freq_sel=15
2194 09:32:16.651233 sv_algorithm_assistance_LP4_1600
2195 09:32:16.654690 ============ PULL DRAM RESETB DOWN ============
2196 09:32:16.658180 ========== PULL DRAM RESETB DOWN end =========
2197 09:32:16.661251 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2198 09:32:16.664675 ===================================
2199 09:32:16.667939 LPDDR4 DRAM CONFIGURATION
2200 09:32:16.671167 ===================================
2201 09:32:16.674692 EX_ROW_EN[0] = 0x0
2202 09:32:16.674806 EX_ROW_EN[1] = 0x0
2203 09:32:16.678162 LP4Y_EN = 0x0
2204 09:32:16.678233 WORK_FSP = 0x0
2205 09:32:16.681122 WL = 0x4
2206 09:32:16.681191 RL = 0x4
2207 09:32:16.684885 BL = 0x2
2208 09:32:16.684983 RPST = 0x0
2209 09:32:16.687914 RD_PRE = 0x0
2210 09:32:16.687992 WR_PRE = 0x1
2211 09:32:16.691360 WR_PST = 0x0
2212 09:32:16.691443 DBI_WR = 0x0
2213 09:32:16.694940 DBI_RD = 0x0
2214 09:32:16.695017 OTF = 0x1
2215 09:32:16.698444 ===================================
2216 09:32:16.701793 ===================================
2217 09:32:16.704691 ANA top config
2218 09:32:16.708233 ===================================
2219 09:32:16.711796 DLL_ASYNC_EN = 0
2220 09:32:16.711868 ALL_SLAVE_EN = 0
2221 09:32:16.714716 NEW_RANK_MODE = 1
2222 09:32:16.718243 DLL_IDLE_MODE = 1
2223 09:32:16.721494 LP45_APHY_COMB_EN = 1
2224 09:32:16.721578 TX_ODT_DIS = 1
2225 09:32:16.724847 NEW_8X_MODE = 1
2226 09:32:16.728386 ===================================
2227 09:32:16.731858 ===================================
2228 09:32:16.735262 data_rate = 2400
2229 09:32:16.738707 CKR = 1
2230 09:32:16.741725 DQ_P2S_RATIO = 8
2231 09:32:16.745245 ===================================
2232 09:32:16.745317 CA_P2S_RATIO = 8
2233 09:32:16.748717 DQ_CA_OPEN = 0
2234 09:32:16.752144 DQ_SEMI_OPEN = 0
2235 09:32:16.755584 CA_SEMI_OPEN = 0
2236 09:32:16.758510 CA_FULL_RATE = 0
2237 09:32:16.762077 DQ_CKDIV4_EN = 0
2238 09:32:16.762146 CA_CKDIV4_EN = 0
2239 09:32:16.765561 CA_PREDIV_EN = 0
2240 09:32:16.769053 PH8_DLY = 17
2241 09:32:16.772042 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2242 09:32:16.775784 DQ_AAMCK_DIV = 4
2243 09:32:16.775860 CA_AAMCK_DIV = 4
2244 09:32:16.779006 CA_ADMCK_DIV = 4
2245 09:32:16.781912 DQ_TRACK_CA_EN = 0
2246 09:32:16.785365 CA_PICK = 1200
2247 09:32:16.789178 CA_MCKIO = 1200
2248 09:32:16.792159 MCKIO_SEMI = 0
2249 09:32:16.795455 PLL_FREQ = 2366
2250 09:32:16.798696 DQ_UI_PI_RATIO = 32
2251 09:32:16.798817 CA_UI_PI_RATIO = 0
2252 09:32:16.802393 ===================================
2253 09:32:16.805385 ===================================
2254 09:32:16.808509 memory_type:LPDDR4
2255 09:32:16.812276 GP_NUM : 10
2256 09:32:16.812348 SRAM_EN : 1
2257 09:32:16.815725 MD32_EN : 0
2258 09:32:16.818637 ===================================
2259 09:32:16.822282 [ANA_INIT] >>>>>>>>>>>>>>
2260 09:32:16.822364 <<<<<< [CONFIGURE PHASE]: ANA_TX
2261 09:32:16.829209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2262 09:32:16.829294 ===================================
2263 09:32:16.832187 data_rate = 2400,PCW = 0X5b00
2264 09:32:16.835794 ===================================
2265 09:32:16.839388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2266 09:32:16.845743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 09:32:16.852070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 09:32:16.855421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2269 09:32:16.858883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2270 09:32:16.862448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2271 09:32:16.865942 [ANA_INIT] flow start
2272 09:32:16.866011 [ANA_INIT] PLL >>>>>>>>
2273 09:32:16.868918 [ANA_INIT] PLL <<<<<<<<
2274 09:32:16.872388 [ANA_INIT] MIDPI >>>>>>>>
2275 09:32:16.872466 [ANA_INIT] MIDPI <<<<<<<<
2276 09:32:16.876221 [ANA_INIT] DLL >>>>>>>>
2277 09:32:16.879091 [ANA_INIT] DLL <<<<<<<<
2278 09:32:16.879161 [ANA_INIT] flow end
2279 09:32:16.885626 ============ LP4 DIFF to SE enter ============
2280 09:32:16.888943 ============ LP4 DIFF to SE exit ============
2281 09:32:16.889021 [ANA_INIT] <<<<<<<<<<<<<
2282 09:32:16.892372 [Flow] Enable top DCM control >>>>>
2283 09:32:16.895959 [Flow] Enable top DCM control <<<<<
2284 09:32:16.898977 Enable DLL master slave shuffle
2285 09:32:16.905721 ==============================================================
2286 09:32:16.905798 Gating Mode config
2287 09:32:16.912536 ==============================================================
2288 09:32:16.916278 Config description:
2289 09:32:16.926127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2290 09:32:16.932622 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2291 09:32:16.936299 SELPH_MODE 0: By rank 1: By Phase
2292 09:32:16.942908 ==============================================================
2293 09:32:16.946407 GAT_TRACK_EN = 1
2294 09:32:16.946489 RX_GATING_MODE = 2
2295 09:32:16.949961 RX_GATING_TRACK_MODE = 2
2296 09:32:16.952978 SELPH_MODE = 1
2297 09:32:16.956399 PICG_EARLY_EN = 1
2298 09:32:16.959747 VALID_LAT_VALUE = 1
2299 09:32:16.966092 ==============================================================
2300 09:32:16.969509 Enter into Gating configuration >>>>
2301 09:32:16.973131 Exit from Gating configuration <<<<
2302 09:32:16.976729 Enter into DVFS_PRE_config >>>>>
2303 09:32:16.986853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2304 09:32:16.989992 Exit from DVFS_PRE_config <<<<<
2305 09:32:16.993167 Enter into PICG configuration >>>>
2306 09:32:16.996734 Exit from PICG configuration <<<<
2307 09:32:16.996816 [RX_INPUT] configuration >>>>>
2308 09:32:17.000132 [RX_INPUT] configuration <<<<<
2309 09:32:17.006580 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2310 09:32:17.010089 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2311 09:32:17.016803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 09:32:17.023492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 09:32:17.029943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 09:32:17.036604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 09:32:17.040431 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2316 09:32:17.043591 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2317 09:32:17.046988 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2318 09:32:17.053536 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2319 09:32:17.056731 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2320 09:32:17.060199 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 09:32:17.063647 ===================================
2322 09:32:17.067054 LPDDR4 DRAM CONFIGURATION
2323 09:32:17.070588 ===================================
2324 09:32:17.073452 EX_ROW_EN[0] = 0x0
2325 09:32:17.073552 EX_ROW_EN[1] = 0x0
2326 09:32:17.076933 LP4Y_EN = 0x0
2327 09:32:17.077005 WORK_FSP = 0x0
2328 09:32:17.080260 WL = 0x4
2329 09:32:17.080337 RL = 0x4
2330 09:32:17.083759 BL = 0x2
2331 09:32:17.083834 RPST = 0x0
2332 09:32:17.087214 RD_PRE = 0x0
2333 09:32:17.087295 WR_PRE = 0x1
2334 09:32:17.090111 WR_PST = 0x0
2335 09:32:17.090222 DBI_WR = 0x0
2336 09:32:17.093695 DBI_RD = 0x0
2337 09:32:17.093793 OTF = 0x1
2338 09:32:17.097265 ===================================
2339 09:32:17.100122 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2340 09:32:17.106828 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2341 09:32:17.110598 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2342 09:32:17.113511 ===================================
2343 09:32:17.116781 LPDDR4 DRAM CONFIGURATION
2344 09:32:17.120500 ===================================
2345 09:32:17.120604 EX_ROW_EN[0] = 0x10
2346 09:32:17.123621 EX_ROW_EN[1] = 0x0
2347 09:32:17.126832 LP4Y_EN = 0x0
2348 09:32:17.126915 WORK_FSP = 0x0
2349 09:32:17.130121 WL = 0x4
2350 09:32:17.130223 RL = 0x4
2351 09:32:17.133414 BL = 0x2
2352 09:32:17.133510 RPST = 0x0
2353 09:32:17.136768 RD_PRE = 0x0
2354 09:32:17.136844 WR_PRE = 0x1
2355 09:32:17.140234 WR_PST = 0x0
2356 09:32:17.140310 DBI_WR = 0x0
2357 09:32:17.143423 DBI_RD = 0x0
2358 09:32:17.143492 OTF = 0x1
2359 09:32:17.146681 ===================================
2360 09:32:17.153718 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2361 09:32:17.153807 ==
2362 09:32:17.156925 Dram Type= 6, Freq= 0, CH_0, rank 0
2363 09:32:17.160578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 09:32:17.160660 ==
2365 09:32:17.163479 [Duty_Offset_Calibration]
2366 09:32:17.167317 B0:2 B1:-1 CA:1
2367 09:32:17.167400
2368 09:32:17.170419 [DutyScan_Calibration_Flow] k_type=0
2369 09:32:17.177416
2370 09:32:17.177497 ==CLK 0==
2371 09:32:17.180832 Final CLK duty delay cell = -4
2372 09:32:17.184339 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2373 09:32:17.187924 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2374 09:32:17.190898 [-4] AVG Duty = 4953%(X100)
2375 09:32:17.190980
2376 09:32:17.194465 CH0 CLK Duty spec in!! Max-Min= 156%
2377 09:32:17.197916 [DutyScan_Calibration_Flow] ====Done====
2378 09:32:17.197998
2379 09:32:17.200915 [DutyScan_Calibration_Flow] k_type=1
2380 09:32:17.216531
2381 09:32:17.216614 ==DQS 0 ==
2382 09:32:17.219746 Final DQS duty delay cell = 0
2383 09:32:17.223164 [0] MAX Duty = 5125%(X100), DQS PI = 46
2384 09:32:17.226411 [0] MIN Duty = 5000%(X100), DQS PI = 14
2385 09:32:17.226493 [0] AVG Duty = 5062%(X100)
2386 09:32:17.229869
2387 09:32:17.229951 ==DQS 1 ==
2388 09:32:17.233342 Final DQS duty delay cell = -4
2389 09:32:17.236863 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2390 09:32:17.240110 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2391 09:32:17.243112 [-4] AVG Duty = 5062%(X100)
2392 09:32:17.243194
2393 09:32:17.246574 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2394 09:32:17.246657
2395 09:32:17.250414 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2396 09:32:17.253211 [DutyScan_Calibration_Flow] ====Done====
2397 09:32:17.253293
2398 09:32:17.256525 [DutyScan_Calibration_Flow] k_type=3
2399 09:32:17.273635
2400 09:32:17.273717 ==DQM 0 ==
2401 09:32:17.276881 Final DQM duty delay cell = 0
2402 09:32:17.280143 [0] MAX Duty = 5031%(X100), DQS PI = 54
2403 09:32:17.283635 [0] MIN Duty = 4907%(X100), DQS PI = 2
2404 09:32:17.283718 [0] AVG Duty = 4969%(X100)
2405 09:32:17.283782
2406 09:32:17.287104 ==DQM 1 ==
2407 09:32:17.290015 Final DQM duty delay cell = 0
2408 09:32:17.293576 [0] MAX Duty = 5124%(X100), DQS PI = 32
2409 09:32:17.297177 [0] MIN Duty = 4969%(X100), DQS PI = 10
2410 09:32:17.297260 [0] AVG Duty = 5046%(X100)
2411 09:32:17.297324
2412 09:32:17.300221 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2413 09:32:17.303741
2414 09:32:17.307228 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2415 09:32:17.310097 [DutyScan_Calibration_Flow] ====Done====
2416 09:32:17.310178
2417 09:32:17.313575 [DutyScan_Calibration_Flow] k_type=2
2418 09:32:17.328678
2419 09:32:17.328759 ==DQ 0 ==
2420 09:32:17.332347 Final DQ duty delay cell = -4
2421 09:32:17.335453 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2422 09:32:17.339211 [-4] MIN Duty = 4875%(X100), DQS PI = 18
2423 09:32:17.339324 [-4] AVG Duty = 4953%(X100)
2424 09:32:17.342172
2425 09:32:17.342279 ==DQ 1 ==
2426 09:32:17.345442 Final DQ duty delay cell = 0
2427 09:32:17.349216 [0] MAX Duty = 5031%(X100), DQS PI = 18
2428 09:32:17.352502 [0] MIN Duty = 4907%(X100), DQS PI = 46
2429 09:32:17.352584 [0] AVG Duty = 4969%(X100)
2430 09:32:17.352648
2431 09:32:17.355968 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2432 09:32:17.356041
2433 09:32:17.359619 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2434 09:32:17.366238 [DutyScan_Calibration_Flow] ====Done====
2435 09:32:17.366425 ==
2436 09:32:17.369351 Dram Type= 6, Freq= 0, CH_1, rank 0
2437 09:32:17.372869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2438 09:32:17.373057 ==
2439 09:32:17.376057 [Duty_Offset_Calibration]
2440 09:32:17.376248 B0:1 B1:1 CA:2
2441 09:32:17.376343
2442 09:32:17.379757 [DutyScan_Calibration_Flow] k_type=0
2443 09:32:17.389225
2444 09:32:17.389501 ==CLK 0==
2445 09:32:17.392926 Final CLK duty delay cell = 0
2446 09:32:17.396358 [0] MAX Duty = 5156%(X100), DQS PI = 24
2447 09:32:17.399414 [0] MIN Duty = 4969%(X100), DQS PI = 38
2448 09:32:17.399834 [0] AVG Duty = 5062%(X100)
2449 09:32:17.402977
2450 09:32:17.403523 CH1 CLK Duty spec in!! Max-Min= 187%
2451 09:32:17.409816 [DutyScan_Calibration_Flow] ====Done====
2452 09:32:17.410277
2453 09:32:17.412755 [DutyScan_Calibration_Flow] k_type=1
2454 09:32:17.428574
2455 09:32:17.428988 ==DQS 0 ==
2456 09:32:17.431852 Final DQS duty delay cell = 0
2457 09:32:17.435692 [0] MAX Duty = 5031%(X100), DQS PI = 18
2458 09:32:17.438709 [0] MIN Duty = 4844%(X100), DQS PI = 48
2459 09:32:17.441998 [0] AVG Duty = 4937%(X100)
2460 09:32:17.442084
2461 09:32:17.442151 ==DQS 1 ==
2462 09:32:17.445303 Final DQS duty delay cell = 0
2463 09:32:17.448571 [0] MAX Duty = 5062%(X100), DQS PI = 36
2464 09:32:17.451562 [0] MIN Duty = 4907%(X100), DQS PI = 16
2465 09:32:17.455257 [0] AVG Duty = 4984%(X100)
2466 09:32:17.455358
2467 09:32:17.458320 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2468 09:32:17.458401
2469 09:32:17.461884 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2470 09:32:17.465285 [DutyScan_Calibration_Flow] ====Done====
2471 09:32:17.465366
2472 09:32:17.468386 [DutyScan_Calibration_Flow] k_type=3
2473 09:32:17.484886
2474 09:32:17.484968 ==DQM 0 ==
2475 09:32:17.488390 Final DQM duty delay cell = 0
2476 09:32:17.491802 [0] MAX Duty = 5093%(X100), DQS PI = 16
2477 09:32:17.495098 [0] MIN Duty = 4875%(X100), DQS PI = 50
2478 09:32:17.495180 [0] AVG Duty = 4984%(X100)
2479 09:32:17.498539
2480 09:32:17.498645 ==DQM 1 ==
2481 09:32:17.502096 Final DQM duty delay cell = 0
2482 09:32:17.505531 [0] MAX Duty = 5156%(X100), DQS PI = 62
2483 09:32:17.508460 [0] MIN Duty = 4938%(X100), DQS PI = 24
2484 09:32:17.508542 [0] AVG Duty = 5047%(X100)
2485 09:32:17.508605
2486 09:32:17.515509 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2487 09:32:17.515593
2488 09:32:17.518476 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2489 09:32:17.522022 [DutyScan_Calibration_Flow] ====Done====
2490 09:32:17.522104
2491 09:32:17.525516 [DutyScan_Calibration_Flow] k_type=2
2492 09:32:17.541846
2493 09:32:17.541928 ==DQ 0 ==
2494 09:32:17.545352 Final DQ duty delay cell = 0
2495 09:32:17.548434 [0] MAX Duty = 5156%(X100), DQS PI = 18
2496 09:32:17.552126 [0] MIN Duty = 4907%(X100), DQS PI = 50
2497 09:32:17.552208 [0] AVG Duty = 5031%(X100)
2498 09:32:17.552273
2499 09:32:17.554997 ==DQ 1 ==
2500 09:32:17.555126 Final DQ duty delay cell = 0
2501 09:32:17.561994 [0] MAX Duty = 5124%(X100), DQS PI = 56
2502 09:32:17.565390 [0] MIN Duty = 5031%(X100), DQS PI = 2
2503 09:32:17.565471 [0] AVG Duty = 5077%(X100)
2504 09:32:17.565536
2505 09:32:17.568589 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2506 09:32:17.568670
2507 09:32:17.572351 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2508 09:32:17.575200 [DutyScan_Calibration_Flow] ====Done====
2509 09:32:17.580369 nWR fixed to 30
2510 09:32:17.584274 [ModeRegInit_LP4] CH0 RK0
2511 09:32:17.584356 [ModeRegInit_LP4] CH0 RK1
2512 09:32:17.587466 [ModeRegInit_LP4] CH1 RK0
2513 09:32:17.590661 [ModeRegInit_LP4] CH1 RK1
2514 09:32:17.590782 match AC timing 7
2515 09:32:17.597559 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2516 09:32:17.600835 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2517 09:32:17.604147 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2518 09:32:17.610501 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2519 09:32:17.613995 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2520 09:32:17.614077 ==
2521 09:32:17.617379 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 09:32:17.620952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 09:32:17.621035 ==
2524 09:32:17.627397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2525 09:32:17.633892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2526 09:32:17.641398 [CA 0] Center 40 (10~71) winsize 62
2527 09:32:17.645141 [CA 1] Center 39 (9~70) winsize 62
2528 09:32:17.648435 [CA 2] Center 36 (6~67) winsize 62
2529 09:32:17.651394 [CA 3] Center 36 (5~67) winsize 63
2530 09:32:17.655279 [CA 4] Center 35 (5~65) winsize 61
2531 09:32:17.658388 [CA 5] Center 34 (4~64) winsize 61
2532 09:32:17.658470
2533 09:32:17.661691 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2534 09:32:17.661774
2535 09:32:17.664967 [CATrainingPosCal] consider 1 rank data
2536 09:32:17.668415 u2DelayCellTimex100 = 270/100 ps
2537 09:32:17.671895 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2538 09:32:17.675220 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2539 09:32:17.681827 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2540 09:32:17.685218 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2541 09:32:17.688873 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2542 09:32:17.691911 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2543 09:32:17.691994
2544 09:32:17.695607 CA PerBit enable=1, Macro0, CA PI delay=34
2545 09:32:17.695691
2546 09:32:17.698632 [CBTSetCACLKResult] CA Dly = 34
2547 09:32:17.698714 CS Dly: 7 (0~38)
2548 09:32:17.698791 ==
2549 09:32:17.702136 Dram Type= 6, Freq= 0, CH_0, rank 1
2550 09:32:17.708558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 09:32:17.708644 ==
2552 09:32:17.712018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2553 09:32:17.718635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2554 09:32:17.727531 [CA 0] Center 39 (9~70) winsize 62
2555 09:32:17.731123 [CA 1] Center 40 (10~70) winsize 61
2556 09:32:17.734585 [CA 2] Center 36 (6~67) winsize 62
2557 09:32:17.737540 [CA 3] Center 35 (5~66) winsize 62
2558 09:32:17.741125 [CA 4] Center 34 (4~65) winsize 62
2559 09:32:17.744620 [CA 5] Center 34 (4~64) winsize 61
2560 09:32:17.744722
2561 09:32:17.747600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2562 09:32:17.747713
2563 09:32:17.751304 [CATrainingPosCal] consider 2 rank data
2564 09:32:17.754599 u2DelayCellTimex100 = 270/100 ps
2565 09:32:17.757931 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2566 09:32:17.761420 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2567 09:32:17.768606 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2568 09:32:17.771321 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2569 09:32:17.774802 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2570 09:32:17.778347 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2571 09:32:17.778820
2572 09:32:17.781824 CA PerBit enable=1, Macro0, CA PI delay=34
2573 09:32:17.782382
2574 09:32:17.785091 [CBTSetCACLKResult] CA Dly = 34
2575 09:32:17.785685 CS Dly: 8 (0~41)
2576 09:32:17.786201
2577 09:32:17.788071 ----->DramcWriteLeveling(PI) begin...
2578 09:32:17.788735 ==
2579 09:32:17.791588 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 09:32:17.798201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 09:32:17.798631 ==
2582 09:32:17.802117 Write leveling (Byte 0): 30 => 30
2583 09:32:17.805083 Write leveling (Byte 1): 27 => 27
2584 09:32:17.805509 DramcWriteLeveling(PI) end<-----
2585 09:32:17.805848
2586 09:32:17.808660 ==
2587 09:32:17.811717 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 09:32:17.815272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 09:32:17.815699 ==
2590 09:32:17.818207 [Gating] SW mode calibration
2591 09:32:17.825015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2592 09:32:17.828651 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2593 09:32:17.835074 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 09:32:17.838648 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2595 09:32:17.842265 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2596 09:32:17.848599 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 09:32:17.852233 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 09:32:17.855582 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 09:32:17.858832 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 09:32:17.865727 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 09:32:17.869264 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2602 09:32:17.872608 1 0 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
2603 09:32:17.879390 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 09:32:17.882566 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 09:32:17.885606 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 09:32:17.892364 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 09:32:17.895875 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 09:32:17.898981 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 09:32:17.905518 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2610 09:32:17.909042 1 1 4 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2611 09:32:17.912463 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 09:32:17.919179 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 09:32:17.922272 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 09:32:17.926044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 09:32:17.929132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 09:32:17.935895 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 09:32:17.939399 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2618 09:32:17.942937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2619 09:32:17.949378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 09:32:17.952957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 09:32:17.956335 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 09:32:17.962583 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 09:32:17.966443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 09:32:17.969292 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 09:32:17.976046 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 09:32:17.979086 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 09:32:17.982388 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 09:32:17.985826 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 09:32:17.992504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 09:32:17.995775 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 09:32:17.999436 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 09:32:18.006016 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 09:32:18.009554 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2634 09:32:18.012640 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2635 09:32:18.015810 Total UI for P1: 0, mck2ui 16
2636 09:32:18.019278 best dqsien dly found for B0: ( 1, 4, 0)
2637 09:32:18.025958 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 09:32:18.026050 Total UI for P1: 0, mck2ui 16
2639 09:32:18.029458 best dqsien dly found for B1: ( 1, 4, 2)
2640 09:32:18.033027 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2641 09:32:18.039500 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2642 09:32:18.039617
2643 09:32:18.042906 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2644 09:32:18.046511 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2645 09:32:18.049856 [Gating] SW calibration Done
2646 09:32:18.049996 ==
2647 09:32:18.052838 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 09:32:18.056524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 09:32:18.056707 ==
2650 09:32:18.056891 RX Vref Scan: 0
2651 09:32:18.057067
2652 09:32:18.060032 RX Vref 0 -> 0, step: 1
2653 09:32:18.060212
2654 09:32:18.063013 RX Delay -40 -> 252, step: 8
2655 09:32:18.066580 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2656 09:32:18.069915 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2657 09:32:18.076630 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2658 09:32:18.080106 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2659 09:32:18.083380 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2660 09:32:18.086847 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2661 09:32:18.090339 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2662 09:32:18.093716 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2663 09:32:18.100191 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2664 09:32:18.103471 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2665 09:32:18.107259 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2666 09:32:18.110558 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2667 09:32:18.113931 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2668 09:32:18.120277 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2669 09:32:18.123837 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2670 09:32:18.127012 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2671 09:32:18.127412 ==
2672 09:32:18.130762 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 09:32:18.134037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 09:32:18.134443 ==
2675 09:32:18.137108 DQS Delay:
2676 09:32:18.137533 DQS0 = 0, DQS1 = 0
2677 09:32:18.137878 DQM Delay:
2678 09:32:18.140801 DQM0 = 116, DQM1 = 107
2679 09:32:18.141303 DQ Delay:
2680 09:32:18.144174 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2681 09:32:18.147343 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2682 09:32:18.150841 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2683 09:32:18.157294 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2684 09:32:18.157726
2685 09:32:18.158096
2686 09:32:18.158415 ==
2687 09:32:18.160848 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 09:32:18.164476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 09:32:18.164927 ==
2690 09:32:18.165277
2691 09:32:18.165625
2692 09:32:18.167356 TX Vref Scan disable
2693 09:32:18.167809 == TX Byte 0 ==
2694 09:32:18.174399 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2695 09:32:18.177760 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2696 09:32:18.178383 == TX Byte 1 ==
2697 09:32:18.183900 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2698 09:32:18.187747 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2699 09:32:18.188331 ==
2700 09:32:18.191045 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 09:32:18.193990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 09:32:18.194644 ==
2703 09:32:18.206842 TX Vref=22, minBit 7, minWin=24, winSum=422
2704 09:32:18.209821 TX Vref=24, minBit 1, minWin=24, winSum=421
2705 09:32:18.213278 TX Vref=26, minBit 5, minWin=25, winSum=427
2706 09:32:18.216854 TX Vref=28, minBit 1, minWin=26, winSum=437
2707 09:32:18.220078 TX Vref=30, minBit 1, minWin=26, winSum=437
2708 09:32:18.223487 TX Vref=32, minBit 4, minWin=26, winSum=436
2709 09:32:18.230113 [TxChooseVref] Worse bit 1, Min win 26, Win sum 437, Final Vref 28
2710 09:32:18.230401
2711 09:32:18.233381 Final TX Range 1 Vref 28
2712 09:32:18.233651
2713 09:32:18.233880 ==
2714 09:32:18.236381 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 09:32:18.240187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 09:32:18.240460 ==
2717 09:32:18.240694
2718 09:32:18.240913
2719 09:32:18.243144 TX Vref Scan disable
2720 09:32:18.246636 == TX Byte 0 ==
2721 09:32:18.249942 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2722 09:32:18.253473 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2723 09:32:18.256814 == TX Byte 1 ==
2724 09:32:18.260379 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2725 09:32:18.263285 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2726 09:32:18.263554
2727 09:32:18.266773 [DATLAT]
2728 09:32:18.267063 Freq=1200, CH0 RK0
2729 09:32:18.267298
2730 09:32:18.270282 DATLAT Default: 0xd
2731 09:32:18.270718 0, 0xFFFF, sum = 0
2732 09:32:18.273357 1, 0xFFFF, sum = 0
2733 09:32:18.273632 2, 0xFFFF, sum = 0
2734 09:32:18.276797 3, 0xFFFF, sum = 0
2735 09:32:18.277097 4, 0xFFFF, sum = 0
2736 09:32:18.280338 5, 0xFFFF, sum = 0
2737 09:32:18.280642 6, 0xFFFF, sum = 0
2738 09:32:18.283677 7, 0xFFFF, sum = 0
2739 09:32:18.283955 8, 0xFFFF, sum = 0
2740 09:32:18.286988 9, 0xFFFF, sum = 0
2741 09:32:18.287262 10, 0xFFFF, sum = 0
2742 09:32:18.290351 11, 0xFFFF, sum = 0
2743 09:32:18.290661 12, 0x0, sum = 1
2744 09:32:18.293704 13, 0x0, sum = 2
2745 09:32:18.294009 14, 0x0, sum = 3
2746 09:32:18.297240 15, 0x0, sum = 4
2747 09:32:18.297572 best_step = 13
2748 09:32:18.297832
2749 09:32:18.298066 ==
2750 09:32:18.300309 Dram Type= 6, Freq= 0, CH_0, rank 0
2751 09:32:18.307337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2752 09:32:18.307615 ==
2753 09:32:18.307885 RX Vref Scan: 1
2754 09:32:18.308113
2755 09:32:18.310658 Set Vref Range= 32 -> 127
2756 09:32:18.310977
2757 09:32:18.314041 RX Vref 32 -> 127, step: 1
2758 09:32:18.314281
2759 09:32:18.314482 RX Delay -21 -> 252, step: 4
2760 09:32:18.314705
2761 09:32:18.317661 Set Vref, RX VrefLevel [Byte0]: 32
2762 09:32:18.320532 [Byte1]: 32
2763 09:32:18.324859
2764 09:32:18.325329 Set Vref, RX VrefLevel [Byte0]: 33
2765 09:32:18.328120 [Byte1]: 33
2766 09:32:18.333219
2767 09:32:18.333748 Set Vref, RX VrefLevel [Byte0]: 34
2768 09:32:18.336046 [Byte1]: 34
2769 09:32:18.340661
2770 09:32:18.341213 Set Vref, RX VrefLevel [Byte0]: 35
2771 09:32:18.344328 [Byte1]: 35
2772 09:32:18.348978
2773 09:32:18.349582 Set Vref, RX VrefLevel [Byte0]: 36
2774 09:32:18.351883 [Byte1]: 36
2775 09:32:18.356723
2776 09:32:18.357215 Set Vref, RX VrefLevel [Byte0]: 37
2777 09:32:18.360375 [Byte1]: 37
2778 09:32:18.364758
2779 09:32:18.365238 Set Vref, RX VrefLevel [Byte0]: 38
2780 09:32:18.368169 [Byte1]: 38
2781 09:32:18.372528
2782 09:32:18.373278 Set Vref, RX VrefLevel [Byte0]: 39
2783 09:32:18.375924 [Byte1]: 39
2784 09:32:18.380841
2785 09:32:18.381465 Set Vref, RX VrefLevel [Byte0]: 40
2786 09:32:18.383784 [Byte1]: 40
2787 09:32:18.388357
2788 09:32:18.388851 Set Vref, RX VrefLevel [Byte0]: 41
2789 09:32:18.391517 [Byte1]: 41
2790 09:32:18.396370
2791 09:32:18.396860 Set Vref, RX VrefLevel [Byte0]: 42
2792 09:32:18.399523 [Byte1]: 42
2793 09:32:18.404266
2794 09:32:18.404735 Set Vref, RX VrefLevel [Byte0]: 43
2795 09:32:18.407777 [Byte1]: 43
2796 09:32:18.412411
2797 09:32:18.413019 Set Vref, RX VrefLevel [Byte0]: 44
2798 09:32:18.415314 [Byte1]: 44
2799 09:32:18.419988
2800 09:32:18.420437 Set Vref, RX VrefLevel [Byte0]: 45
2801 09:32:18.423320 [Byte1]: 45
2802 09:32:18.427982
2803 09:32:18.428598 Set Vref, RX VrefLevel [Byte0]: 46
2804 09:32:18.431709 [Byte1]: 46
2805 09:32:18.435870
2806 09:32:18.436379 Set Vref, RX VrefLevel [Byte0]: 47
2807 09:32:18.439471 [Byte1]: 47
2808 09:32:18.443637
2809 09:32:18.444118 Set Vref, RX VrefLevel [Byte0]: 48
2810 09:32:18.447188 [Byte1]: 48
2811 09:32:18.451733
2812 09:32:18.452204 Set Vref, RX VrefLevel [Byte0]: 49
2813 09:32:18.454985 [Byte1]: 49
2814 09:32:18.459618
2815 09:32:18.460086 Set Vref, RX VrefLevel [Byte0]: 50
2816 09:32:18.463028 [Byte1]: 50
2817 09:32:18.467782
2818 09:32:18.468275 Set Vref, RX VrefLevel [Byte0]: 51
2819 09:32:18.471141 [Byte1]: 51
2820 09:32:18.475429
2821 09:32:18.476007 Set Vref, RX VrefLevel [Byte0]: 52
2822 09:32:18.479125 [Byte1]: 52
2823 09:32:18.483705
2824 09:32:18.484320 Set Vref, RX VrefLevel [Byte0]: 53
2825 09:32:18.486882 [Byte1]: 53
2826 09:32:18.491353
2827 09:32:18.491827 Set Vref, RX VrefLevel [Byte0]: 54
2828 09:32:18.494909 [Byte1]: 54
2829 09:32:18.499351
2830 09:32:18.499831 Set Vref, RX VrefLevel [Byte0]: 55
2831 09:32:18.502680 [Byte1]: 55
2832 09:32:18.507614
2833 09:32:18.508237 Set Vref, RX VrefLevel [Byte0]: 56
2834 09:32:18.510393 [Byte1]: 56
2835 09:32:18.515202
2836 09:32:18.515673 Set Vref, RX VrefLevel [Byte0]: 57
2837 09:32:18.518669 [Byte1]: 57
2838 09:32:18.523411
2839 09:32:18.523934 Set Vref, RX VrefLevel [Byte0]: 58
2840 09:32:18.526276 [Byte1]: 58
2841 09:32:18.530968
2842 09:32:18.531410 Set Vref, RX VrefLevel [Byte0]: 59
2843 09:32:18.534492 [Byte1]: 59
2844 09:32:18.538976
2845 09:32:18.539571 Set Vref, RX VrefLevel [Byte0]: 60
2846 09:32:18.541925 [Byte1]: 60
2847 09:32:18.547018
2848 09:32:18.547557 Set Vref, RX VrefLevel [Byte0]: 61
2849 09:32:18.550237 [Byte1]: 61
2850 09:32:18.554811
2851 09:32:18.555240 Set Vref, RX VrefLevel [Byte0]: 62
2852 09:32:18.558493 [Byte1]: 62
2853 09:32:18.562934
2854 09:32:18.563371 Set Vref, RX VrefLevel [Byte0]: 63
2855 09:32:18.566308 [Byte1]: 63
2856 09:32:18.570675
2857 09:32:18.571157 Set Vref, RX VrefLevel [Byte0]: 64
2858 09:32:18.574176 [Byte1]: 64
2859 09:32:18.578369
2860 09:32:18.579037 Set Vref, RX VrefLevel [Byte0]: 65
2861 09:32:18.581797 [Byte1]: 65
2862 09:32:18.586320
2863 09:32:18.586845 Set Vref, RX VrefLevel [Byte0]: 66
2864 09:32:18.589872 [Byte1]: 66
2865 09:32:18.594495
2866 09:32:18.595148 Set Vref, RX VrefLevel [Byte0]: 67
2867 09:32:18.597935 [Byte1]: 67
2868 09:32:18.602434
2869 09:32:18.602989 Set Vref, RX VrefLevel [Byte0]: 68
2870 09:32:18.605748 [Byte1]: 68
2871 09:32:18.610133
2872 09:32:18.610643 Final RX Vref Byte 0 = 54 to rank0
2873 09:32:18.613500 Final RX Vref Byte 1 = 52 to rank0
2874 09:32:18.617086 Final RX Vref Byte 0 = 54 to rank1
2875 09:32:18.620595 Final RX Vref Byte 1 = 52 to rank1==
2876 09:32:18.624051 Dram Type= 6, Freq= 0, CH_0, rank 0
2877 09:32:18.627050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 09:32:18.630477 ==
2879 09:32:18.631027 DQS Delay:
2880 09:32:18.631391 DQS0 = 0, DQS1 = 0
2881 09:32:18.634027 DQM Delay:
2882 09:32:18.634414 DQM0 = 115, DQM1 = 104
2883 09:32:18.637563 DQ Delay:
2884 09:32:18.640298 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2885 09:32:18.643829 DQ4 =116, DQ5 =110, DQ6 =122, DQ7 =122
2886 09:32:18.647271 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2887 09:32:18.650509 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2888 09:32:18.650989
2889 09:32:18.651426
2890 09:32:18.657291 [DQSOSCAuto] RK0, (LSB)MR18= 0xef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2891 09:32:18.660644 CH0 RK0: MR19=403, MR18=EF
2892 09:32:18.667206 CH0_RK0: MR19=0x403, MR18=0xEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2893 09:32:18.667685
2894 09:32:18.670506 ----->DramcWriteLeveling(PI) begin...
2895 09:32:18.671085 ==
2896 09:32:18.673984 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 09:32:18.677381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 09:32:18.677836 ==
2899 09:32:18.680748 Write leveling (Byte 0): 31 => 31
2900 09:32:18.684199 Write leveling (Byte 1): 28 => 28
2901 09:32:18.687496 DramcWriteLeveling(PI) end<-----
2902 09:32:18.687913
2903 09:32:18.688240 ==
2904 09:32:18.690557 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 09:32:18.694104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 09:32:18.694754 ==
2907 09:32:18.697442 [Gating] SW mode calibration
2908 09:32:18.703823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2909 09:32:18.710520 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2910 09:32:18.713931 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 09:32:18.717106 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2912 09:32:18.724016 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 09:32:18.727375 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 09:32:18.730773 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 09:32:18.737206 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 09:32:18.740732 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2917 09:32:18.744111 0 15 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
2918 09:32:18.750651 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2919 09:32:18.754170 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2920 09:32:18.757738 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 09:32:18.764262 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 09:32:18.767919 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 09:32:18.770996 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 09:32:18.774224 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2925 09:32:18.781126 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2926 09:32:18.784127 1 1 0 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (1 1)
2927 09:32:18.787587 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2928 09:32:18.794613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 09:32:18.797766 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 09:32:18.801405 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 09:32:18.807861 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 09:32:18.811156 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 09:32:18.814439 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2934 09:32:18.821277 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2935 09:32:18.824420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2936 09:32:18.828030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 09:32:18.835058 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 09:32:18.837874 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 09:32:18.841378 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 09:32:18.844855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 09:32:18.851433 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 09:32:18.855022 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 09:32:18.858565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 09:32:18.865173 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 09:32:18.868011 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 09:32:18.871635 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 09:32:18.878615 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 09:32:18.881930 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 09:32:18.885167 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2950 09:32:18.891816 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2951 09:32:18.892317 Total UI for P1: 0, mck2ui 16
2952 09:32:18.895263 best dqsien dly found for B0: ( 1, 3, 28)
2953 09:32:18.901490 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 09:32:18.904914 Total UI for P1: 0, mck2ui 16
2955 09:32:18.908801 best dqsien dly found for B1: ( 1, 4, 0)
2956 09:32:18.911759 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2957 09:32:18.915530 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2958 09:32:18.916079
2959 09:32:18.918765 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2960 09:32:18.921945 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2961 09:32:18.925131 [Gating] SW calibration Done
2962 09:32:18.925655 ==
2963 09:32:18.928602 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 09:32:18.932052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 09:32:18.932612 ==
2966 09:32:18.935286 RX Vref Scan: 0
2967 09:32:18.935824
2968 09:32:18.936217 RX Vref 0 -> 0, step: 1
2969 09:32:18.936602
2970 09:32:18.938800 RX Delay -40 -> 252, step: 8
2971 09:32:18.942332 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2972 09:32:18.949055 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2973 09:32:18.952249 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2974 09:32:18.955738 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2975 09:32:18.958687 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2976 09:32:18.962164 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2977 09:32:18.968612 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2978 09:32:18.972272 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2979 09:32:18.975851 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2980 09:32:18.978791 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2981 09:32:18.982581 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2982 09:32:18.985868 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2983 09:32:18.992333 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2984 09:32:18.995651 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2985 09:32:18.999283 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2986 09:32:19.002432 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2987 09:32:19.002956 ==
2988 09:32:19.005804 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 09:32:19.009358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 09:32:19.012826 ==
2991 09:32:19.013246 DQS Delay:
2992 09:32:19.013573 DQS0 = 0, DQS1 = 0
2993 09:32:19.015979 DQM Delay:
2994 09:32:19.016428 DQM0 = 115, DQM1 = 105
2995 09:32:19.019126 DQ Delay:
2996 09:32:19.022838 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2997 09:32:19.025942 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2998 09:32:19.029584 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2999 09:32:19.032659 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3000 09:32:19.032975
3001 09:32:19.033270
3002 09:32:19.033494 ==
3003 09:32:19.036020 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 09:32:19.039189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 09:32:19.039437 ==
3006 09:32:19.039621
3007 09:32:19.039785
3008 09:32:19.042460 TX Vref Scan disable
3009 09:32:19.053594 == TX Byte 0 ==
3010 09:32:19.053978 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3011 09:32:19.054134 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3012 09:32:19.056049 == TX Byte 1 ==
3013 09:32:19.059518 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3014 09:32:19.063079 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3015 09:32:19.063183 ==
3016 09:32:19.065897 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 09:32:19.069544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 09:32:19.069640 ==
3019 09:32:19.082706 TX Vref=22, minBit 1, minWin=26, winSum=428
3020 09:32:19.085979 TX Vref=24, minBit 1, minWin=26, winSum=432
3021 09:32:19.089414 TX Vref=26, minBit 3, minWin=26, winSum=432
3022 09:32:19.092814 TX Vref=28, minBit 3, minWin=26, winSum=437
3023 09:32:19.096305 TX Vref=30, minBit 12, minWin=26, winSum=436
3024 09:32:19.099729 TX Vref=32, minBit 0, minWin=27, winSum=440
3025 09:32:19.106141 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 32
3026 09:32:19.106228
3027 09:32:19.109536 Final TX Range 1 Vref 32
3028 09:32:19.109622
3029 09:32:19.109708 ==
3030 09:32:19.113108 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 09:32:19.116361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 09:32:19.116459 ==
3033 09:32:19.116528
3034 09:32:19.116591
3035 09:32:19.120006 TX Vref Scan disable
3036 09:32:19.123064 == TX Byte 0 ==
3037 09:32:19.126541 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3038 09:32:19.129463 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3039 09:32:19.133181 == TX Byte 1 ==
3040 09:32:19.136401 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3041 09:32:19.139909 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3042 09:32:19.139996
3043 09:32:19.143014 [DATLAT]
3044 09:32:19.143107 Freq=1200, CH0 RK1
3045 09:32:19.143181
3046 09:32:19.146611 DATLAT Default: 0xd
3047 09:32:19.146754 0, 0xFFFF, sum = 0
3048 09:32:19.149737 1, 0xFFFF, sum = 0
3049 09:32:19.149840 2, 0xFFFF, sum = 0
3050 09:32:19.153383 3, 0xFFFF, sum = 0
3051 09:32:19.153494 4, 0xFFFF, sum = 0
3052 09:32:19.156469 5, 0xFFFF, sum = 0
3053 09:32:19.156591 6, 0xFFFF, sum = 0
3054 09:32:19.160131 7, 0xFFFF, sum = 0
3055 09:32:19.160335 8, 0xFFFF, sum = 0
3056 09:32:19.163719 9, 0xFFFF, sum = 0
3057 09:32:19.163939 10, 0xFFFF, sum = 0
3058 09:32:19.167255 11, 0xFFFF, sum = 0
3059 09:32:19.167494 12, 0x0, sum = 1
3060 09:32:19.170619 13, 0x0, sum = 2
3061 09:32:19.170872 14, 0x0, sum = 3
3062 09:32:19.173649 15, 0x0, sum = 4
3063 09:32:19.173913 best_step = 13
3064 09:32:19.174069
3065 09:32:19.174206 ==
3066 09:32:19.176931 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 09:32:19.180397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 09:32:19.183935 ==
3069 09:32:19.184266 RX Vref Scan: 0
3070 09:32:19.184470
3071 09:32:19.187403 RX Vref 0 -> 0, step: 1
3072 09:32:19.187807
3073 09:32:19.190543 RX Delay -21 -> 252, step: 4
3074 09:32:19.194066 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3075 09:32:19.197632 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3076 09:32:19.200522 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3077 09:32:19.207705 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3078 09:32:19.211458 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3079 09:32:19.214285 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3080 09:32:19.217503 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3081 09:32:19.221183 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3082 09:32:19.224073 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3083 09:32:19.230880 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3084 09:32:19.234228 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3085 09:32:19.237334 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3086 09:32:19.241101 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3087 09:32:19.244366 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3088 09:32:19.250889 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3089 09:32:19.254216 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3090 09:32:19.254687 ==
3091 09:32:19.257375 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 09:32:19.261250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 09:32:19.261692 ==
3094 09:32:19.264530 DQS Delay:
3095 09:32:19.264963 DQS0 = 0, DQS1 = 0
3096 09:32:19.265413 DQM Delay:
3097 09:32:19.267986 DQM0 = 114, DQM1 = 105
3098 09:32:19.268425 DQ Delay:
3099 09:32:19.270807 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3100 09:32:19.274279 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3101 09:32:19.277874 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =94
3102 09:32:19.281636 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3103 09:32:19.282183
3104 09:32:19.284883
3105 09:32:19.291309 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3106 09:32:19.294535 CH0 RK1: MR19=403, MR18=5F7
3107 09:32:19.297948 CH0_RK1: MR19=0x403, MR18=0x5F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3108 09:32:19.301423 [RxdqsGatingPostProcess] freq 1200
3109 09:32:19.307961 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 09:32:19.311389 best DQS0 dly(2T, 0.5T) = (0, 12)
3111 09:32:19.315270 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 09:32:19.318176 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3113 09:32:19.321782 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 09:32:19.325231 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 09:32:19.328462 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 09:32:19.331836 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 09:32:19.332284 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 09:32:19.335222 Pre-setting of DQS Precalculation
3119 09:32:19.341908 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 09:32:19.342441 ==
3121 09:32:19.345135 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 09:32:19.348552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 09:32:19.349159 ==
3124 09:32:19.355436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 09:32:19.361988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 09:32:19.368564 [CA 0] Center 38 (9~68) winsize 60
3127 09:32:19.372012 [CA 1] Center 38 (8~68) winsize 61
3128 09:32:19.375552 [CA 2] Center 35 (6~65) winsize 60
3129 09:32:19.378789 [CA 3] Center 34 (4~65) winsize 62
3130 09:32:19.381919 [CA 4] Center 34 (4~65) winsize 62
3131 09:32:19.385305 [CA 5] Center 34 (4~64) winsize 61
3132 09:32:19.385766
3133 09:32:19.388731 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3134 09:32:19.389203
3135 09:32:19.392210 [CATrainingPosCal] consider 1 rank data
3136 09:32:19.395262 u2DelayCellTimex100 = 270/100 ps
3137 09:32:19.398563 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3138 09:32:19.401933 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3139 09:32:19.405176 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3140 09:32:19.412159 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3141 09:32:19.415742 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3142 09:32:19.418819 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3143 09:32:19.419242
3144 09:32:19.422129 CA PerBit enable=1, Macro0, CA PI delay=34
3145 09:32:19.422548
3146 09:32:19.425597 [CBTSetCACLKResult] CA Dly = 34
3147 09:32:19.426025 CS Dly: 6 (0~37)
3148 09:32:19.426357 ==
3149 09:32:19.428966 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 09:32:19.432615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 09:32:19.436155 ==
3152 09:32:19.439675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 09:32:19.446224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 09:32:19.454161 [CA 0] Center 38 (8~68) winsize 61
3155 09:32:19.457885 [CA 1] Center 38 (9~68) winsize 60
3156 09:32:19.461078 [CA 2] Center 34 (4~65) winsize 62
3157 09:32:19.464690 [CA 3] Center 34 (4~65) winsize 62
3158 09:32:19.467637 [CA 4] Center 34 (4~65) winsize 62
3159 09:32:19.471128 [CA 5] Center 33 (3~64) winsize 62
3160 09:32:19.471646
3161 09:32:19.474430 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3162 09:32:19.474893
3163 09:32:19.477553 [CATrainingPosCal] consider 2 rank data
3164 09:32:19.481372 u2DelayCellTimex100 = 270/100 ps
3165 09:32:19.484316 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3166 09:32:19.488048 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3167 09:32:19.490933 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3168 09:32:19.498066 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3169 09:32:19.501495 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3170 09:32:19.504626 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3171 09:32:19.505046
3172 09:32:19.507973 CA PerBit enable=1, Macro0, CA PI delay=34
3173 09:32:19.508537
3174 09:32:19.511391 [CBTSetCACLKResult] CA Dly = 34
3175 09:32:19.511812 CS Dly: 7 (0~40)
3176 09:32:19.512145
3177 09:32:19.514986 ----->DramcWriteLeveling(PI) begin...
3178 09:32:19.515411 ==
3179 09:32:19.517802 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 09:32:19.525128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 09:32:19.525662 ==
3182 09:32:19.528384 Write leveling (Byte 0): 27 => 27
3183 09:32:19.528810 Write leveling (Byte 1): 29 => 29
3184 09:32:19.531606 DramcWriteLeveling(PI) end<-----
3185 09:32:19.532029
3186 09:32:19.534972 ==
3187 09:32:19.535414 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 09:32:19.541459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 09:32:19.541880 ==
3190 09:32:19.544532 [Gating] SW mode calibration
3191 09:32:19.551194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 09:32:19.554559 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 09:32:19.561648 0 15 0 | B1->B0 | 2929 2424 | 1 0 | (0 0) (0 0)
3194 09:32:19.564804 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 09:32:19.568358 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 09:32:19.575251 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 09:32:19.578602 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 09:32:19.581884 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3199 09:32:19.585436 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3200 09:32:19.591923 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3201 09:32:19.595176 1 0 0 | B1->B0 | 2424 2d2d | 0 1 | (1 0) (1 0)
3202 09:32:19.598616 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 09:32:19.605546 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 09:32:19.608654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 09:32:19.611913 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 09:32:19.618375 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 09:32:19.621801 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 09:32:19.625319 1 0 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3209 09:32:19.628961 1 1 0 | B1->B0 | 4444 3332 | 0 1 | (0 0) (0 0)
3210 09:32:19.635302 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 09:32:19.638538 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 09:32:19.641947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 09:32:19.649154 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 09:32:19.652766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 09:32:19.655268 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 09:32:19.662133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3217 09:32:19.665792 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3218 09:32:19.669113 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 09:32:19.675617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 09:32:19.679229 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 09:32:19.682650 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 09:32:19.689254 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 09:32:19.692697 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 09:32:19.696198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 09:32:19.699180 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 09:32:19.705716 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 09:32:19.709311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 09:32:19.712650 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 09:32:19.719211 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 09:32:19.722578 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 09:32:19.726010 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 09:32:19.732596 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3233 09:32:19.736063 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 09:32:19.739407 Total UI for P1: 0, mck2ui 16
3235 09:32:19.742882 best dqsien dly found for B0: ( 1, 3, 28)
3236 09:32:19.746372 Total UI for P1: 0, mck2ui 16
3237 09:32:19.749273 best dqsien dly found for B1: ( 1, 3, 30)
3238 09:32:19.752883 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3239 09:32:19.756334 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3240 09:32:19.756767
3241 09:32:19.759514 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3242 09:32:19.762989 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3243 09:32:19.766128 [Gating] SW calibration Done
3244 09:32:19.766574 ==
3245 09:32:19.769411 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 09:32:19.773055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 09:32:19.773558 ==
3248 09:32:19.776361 RX Vref Scan: 0
3249 09:32:19.776810
3250 09:32:19.777140 RX Vref 0 -> 0, step: 1
3251 09:32:19.779752
3252 09:32:19.780189 RX Delay -40 -> 252, step: 8
3253 09:32:19.786484 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3254 09:32:19.789888 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3255 09:32:19.793369 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3256 09:32:19.796556 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3257 09:32:19.799813 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3258 09:32:19.803372 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3259 09:32:19.809893 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3260 09:32:19.813154 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3261 09:32:19.816945 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3262 09:32:19.820187 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3263 09:32:19.823579 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3264 09:32:19.826687 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3265 09:32:19.833219 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3266 09:32:19.836755 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3267 09:32:19.840290 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3268 09:32:19.843710 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3269 09:32:19.844130 ==
3270 09:32:19.846509 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 09:32:19.853730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 09:32:19.854152 ==
3273 09:32:19.854487 DQS Delay:
3274 09:32:19.857291 DQS0 = 0, DQS1 = 0
3275 09:32:19.857707 DQM Delay:
3276 09:32:19.858037 DQM0 = 115, DQM1 = 108
3277 09:32:19.860297 DQ Delay:
3278 09:32:19.863742 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3279 09:32:19.867008 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3280 09:32:19.870316 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3281 09:32:19.873661 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3282 09:32:19.874078
3283 09:32:19.874405
3284 09:32:19.874713 ==
3285 09:32:19.877159 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 09:32:19.880753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 09:32:19.881174 ==
3288 09:32:19.881505
3289 09:32:19.883595
3290 09:32:19.884010 TX Vref Scan disable
3291 09:32:19.887075 == TX Byte 0 ==
3292 09:32:19.890222 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3293 09:32:19.893857 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3294 09:32:19.897018 == TX Byte 1 ==
3295 09:32:19.900317 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3296 09:32:19.904064 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3297 09:32:19.904478 ==
3298 09:32:19.907395 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 09:32:19.911021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 09:32:19.913869 ==
3301 09:32:19.924621 TX Vref=22, minBit 0, minWin=25, winSum=411
3302 09:32:19.927874 TX Vref=24, minBit 1, minWin=25, winSum=419
3303 09:32:19.931295 TX Vref=26, minBit 1, minWin=26, winSum=423
3304 09:32:19.934182 TX Vref=28, minBit 1, minWin=26, winSum=430
3305 09:32:19.937942 TX Vref=30, minBit 13, minWin=25, winSum=431
3306 09:32:19.941508 TX Vref=32, minBit 3, minWin=25, winSum=427
3307 09:32:19.947761 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3308 09:32:19.948231
3309 09:32:19.951177 Final TX Range 1 Vref 28
3310 09:32:19.951627
3311 09:32:19.951983 ==
3312 09:32:19.954699 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 09:32:19.957594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 09:32:19.958113 ==
3315 09:32:19.958600
3316 09:32:19.959052
3317 09:32:19.961249 TX Vref Scan disable
3318 09:32:19.964737 == TX Byte 0 ==
3319 09:32:19.967779 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3320 09:32:19.971509 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3321 09:32:19.974494 == TX Byte 1 ==
3322 09:32:19.978029 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3323 09:32:19.981648 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3324 09:32:19.982063
3325 09:32:19.984734 [DATLAT]
3326 09:32:19.985152 Freq=1200, CH1 RK0
3327 09:32:19.985485
3328 09:32:19.988279 DATLAT Default: 0xd
3329 09:32:19.988698 0, 0xFFFF, sum = 0
3330 09:32:19.991245 1, 0xFFFF, sum = 0
3331 09:32:19.991669 2, 0xFFFF, sum = 0
3332 09:32:19.994804 3, 0xFFFF, sum = 0
3333 09:32:19.995228 4, 0xFFFF, sum = 0
3334 09:32:19.998166 5, 0xFFFF, sum = 0
3335 09:32:19.998592 6, 0xFFFF, sum = 0
3336 09:32:20.001282 7, 0xFFFF, sum = 0
3337 09:32:20.001738 8, 0xFFFF, sum = 0
3338 09:32:20.005007 9, 0xFFFF, sum = 0
3339 09:32:20.005433 10, 0xFFFF, sum = 0
3340 09:32:20.008211 11, 0xFFFF, sum = 0
3341 09:32:20.008636 12, 0x0, sum = 1
3342 09:32:20.011505 13, 0x0, sum = 2
3343 09:32:20.011931 14, 0x0, sum = 3
3344 09:32:20.015323 15, 0x0, sum = 4
3345 09:32:20.015749 best_step = 13
3346 09:32:20.016086
3347 09:32:20.016395 ==
3348 09:32:20.018562 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 09:32:20.021326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 09:32:20.024870 ==
3351 09:32:20.025382 RX Vref Scan: 1
3352 09:32:20.025842
3353 09:32:20.028277 Set Vref Range= 32 -> 127
3354 09:32:20.028690
3355 09:32:20.031621 RX Vref 32 -> 127, step: 1
3356 09:32:20.032035
3357 09:32:20.032359 RX Delay -21 -> 252, step: 4
3358 09:32:20.032661
3359 09:32:20.035381 Set Vref, RX VrefLevel [Byte0]: 32
3360 09:32:20.038667 [Byte1]: 32
3361 09:32:20.042558
3362 09:32:20.043162 Set Vref, RX VrefLevel [Byte0]: 33
3363 09:32:20.045606 [Byte1]: 33
3364 09:32:20.050106
3365 09:32:20.050547 Set Vref, RX VrefLevel [Byte0]: 34
3366 09:32:20.053605 [Byte1]: 34
3367 09:32:20.058429
3368 09:32:20.058750 Set Vref, RX VrefLevel [Byte0]: 35
3369 09:32:20.061726 [Byte1]: 35
3370 09:32:20.066484
3371 09:32:20.066932 Set Vref, RX VrefLevel [Byte0]: 36
3372 09:32:20.069358 [Byte1]: 36
3373 09:32:20.074371
3374 09:32:20.074882 Set Vref, RX VrefLevel [Byte0]: 37
3375 09:32:20.077675 [Byte1]: 37
3376 09:32:20.082126
3377 09:32:20.082415 Set Vref, RX VrefLevel [Byte0]: 38
3378 09:32:20.085250 [Byte1]: 38
3379 09:32:20.089985
3380 09:32:20.090375 Set Vref, RX VrefLevel [Byte0]: 39
3381 09:32:20.093411 [Byte1]: 39
3382 09:32:20.098356
3383 09:32:20.098798 Set Vref, RX VrefLevel [Byte0]: 40
3384 09:32:20.101282 [Byte1]: 40
3385 09:32:20.105546
3386 09:32:20.105855 Set Vref, RX VrefLevel [Byte0]: 41
3387 09:32:20.108994 [Byte1]: 41
3388 09:32:20.113812
3389 09:32:20.114321 Set Vref, RX VrefLevel [Byte0]: 42
3390 09:32:20.117071 [Byte1]: 42
3391 09:32:20.121827
3392 09:32:20.122269 Set Vref, RX VrefLevel [Byte0]: 43
3393 09:32:20.125146 [Byte1]: 43
3394 09:32:20.129808
3395 09:32:20.130219 Set Vref, RX VrefLevel [Byte0]: 44
3396 09:32:20.132853 [Byte1]: 44
3397 09:32:20.137530
3398 09:32:20.138065 Set Vref, RX VrefLevel [Byte0]: 45
3399 09:32:20.140902 [Byte1]: 45
3400 09:32:20.145537
3401 09:32:20.146004 Set Vref, RX VrefLevel [Byte0]: 46
3402 09:32:20.149302 [Byte1]: 46
3403 09:32:20.153517
3404 09:32:20.154138 Set Vref, RX VrefLevel [Byte0]: 47
3405 09:32:20.156974 [Byte1]: 47
3406 09:32:20.161270
3407 09:32:20.161725 Set Vref, RX VrefLevel [Byte0]: 48
3408 09:32:20.164919 [Byte1]: 48
3409 09:32:20.169871
3410 09:32:20.170434 Set Vref, RX VrefLevel [Byte0]: 49
3411 09:32:20.172790 [Byte1]: 49
3412 09:32:20.177111
3413 09:32:20.177651 Set Vref, RX VrefLevel [Byte0]: 50
3414 09:32:20.180767 [Byte1]: 50
3415 09:32:20.185243
3416 09:32:20.185700 Set Vref, RX VrefLevel [Byte0]: 51
3417 09:32:20.188643 [Byte1]: 51
3418 09:32:20.192870
3419 09:32:20.193325 Set Vref, RX VrefLevel [Byte0]: 52
3420 09:32:20.196189 [Byte1]: 52
3421 09:32:20.200950
3422 09:32:20.201409 Set Vref, RX VrefLevel [Byte0]: 53
3423 09:32:20.204467 [Byte1]: 53
3424 09:32:20.209223
3425 09:32:20.209758 Set Vref, RX VrefLevel [Byte0]: 54
3426 09:32:20.212425 [Byte1]: 54
3427 09:32:20.216782
3428 09:32:20.217301 Set Vref, RX VrefLevel [Byte0]: 55
3429 09:32:20.219866 [Byte1]: 55
3430 09:32:20.224494
3431 09:32:20.224911 Set Vref, RX VrefLevel [Byte0]: 56
3432 09:32:20.227849 [Byte1]: 56
3433 09:32:20.232706
3434 09:32:20.233273 Set Vref, RX VrefLevel [Byte0]: 57
3435 09:32:20.236043 [Byte1]: 57
3436 09:32:20.240640
3437 09:32:20.241168 Set Vref, RX VrefLevel [Byte0]: 58
3438 09:32:20.244345 [Byte1]: 58
3439 09:32:20.248859
3440 09:32:20.249414 Set Vref, RX VrefLevel [Byte0]: 59
3441 09:32:20.251785 [Byte1]: 59
3442 09:32:20.256150
3443 09:32:20.256731 Set Vref, RX VrefLevel [Byte0]: 60
3444 09:32:20.259819 [Byte1]: 60
3445 09:32:20.264355
3446 09:32:20.264813 Set Vref, RX VrefLevel [Byte0]: 61
3447 09:32:20.267607 [Byte1]: 61
3448 09:32:20.272596
3449 09:32:20.273049 Set Vref, RX VrefLevel [Byte0]: 62
3450 09:32:20.275350 [Byte1]: 62
3451 09:32:20.279878
3452 09:32:20.280291 Set Vref, RX VrefLevel [Byte0]: 63
3453 09:32:20.283206 [Byte1]: 63
3454 09:32:20.288329
3455 09:32:20.288741 Set Vref, RX VrefLevel [Byte0]: 64
3456 09:32:20.291271 [Byte1]: 64
3457 09:32:20.296029
3458 09:32:20.296442 Set Vref, RX VrefLevel [Byte0]: 65
3459 09:32:20.299043 [Byte1]: 65
3460 09:32:20.303837
3461 09:32:20.304251 Set Vref, RX VrefLevel [Byte0]: 66
3462 09:32:20.307483 [Byte1]: 66
3463 09:32:20.311695
3464 09:32:20.312110 Set Vref, RX VrefLevel [Byte0]: 67
3465 09:32:20.315198 [Byte1]: 67
3466 09:32:20.319841
3467 09:32:20.320352 Set Vref, RX VrefLevel [Byte0]: 68
3468 09:32:20.323301 [Byte1]: 68
3469 09:32:20.328268
3470 09:32:20.328828 Set Vref, RX VrefLevel [Byte0]: 69
3471 09:32:20.331028 [Byte1]: 69
3472 09:32:20.336113
3473 09:32:20.336672 Set Vref, RX VrefLevel [Byte0]: 70
3474 09:32:20.339082 [Byte1]: 70
3475 09:32:20.343418
3476 09:32:20.343877 Final RX Vref Byte 0 = 57 to rank0
3477 09:32:20.346925 Final RX Vref Byte 1 = 49 to rank0
3478 09:32:20.350625 Final RX Vref Byte 0 = 57 to rank1
3479 09:32:20.353299 Final RX Vref Byte 1 = 49 to rank1==
3480 09:32:20.357188 Dram Type= 6, Freq= 0, CH_1, rank 0
3481 09:32:20.360718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 09:32:20.364077 ==
3483 09:32:20.364647 DQS Delay:
3484 09:32:20.365015 DQS0 = 0, DQS1 = 0
3485 09:32:20.367030 DQM Delay:
3486 09:32:20.367490 DQM0 = 116, DQM1 = 108
3487 09:32:20.370530 DQ Delay:
3488 09:32:20.373945 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3489 09:32:20.376898 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3490 09:32:20.380837 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =104
3491 09:32:20.383566 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3492 09:32:20.384027
3493 09:32:20.384438
3494 09:32:20.390762 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3495 09:32:20.394018 CH1 RK0: MR19=303, MR18=FCE1
3496 09:32:20.400499 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3497 09:32:20.400970
3498 09:32:20.403966 ----->DramcWriteLeveling(PI) begin...
3499 09:32:20.404391 ==
3500 09:32:20.407200 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 09:32:20.410635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 09:32:20.411112 ==
3503 09:32:20.413992 Write leveling (Byte 0): 27 => 27
3504 09:32:20.417651 Write leveling (Byte 1): 27 => 27
3505 09:32:20.420635 DramcWriteLeveling(PI) end<-----
3506 09:32:20.421158
3507 09:32:20.421494 ==
3508 09:32:20.423924 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 09:32:20.427632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 09:32:20.428171 ==
3511 09:32:20.430891 [Gating] SW mode calibration
3512 09:32:20.437793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3513 09:32:20.444239 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3514 09:32:20.447757 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3515 09:32:20.454597 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 09:32:20.457523 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 09:32:20.460994 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 09:32:20.464215 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 09:32:20.470852 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 09:32:20.474125 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3521 09:32:20.477775 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3522 09:32:20.484571 1 0 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3523 09:32:20.487991 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 09:32:20.491110 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 09:32:20.497831 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 09:32:20.501242 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 09:32:20.504920 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3528 09:32:20.511449 1 0 24 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
3529 09:32:20.514821 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3530 09:32:20.517993 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 09:32:20.521242 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 09:32:20.528022 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 09:32:20.531553 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 09:32:20.534553 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 09:32:20.541543 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3536 09:32:20.544809 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3537 09:32:20.548216 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3538 09:32:20.555046 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 09:32:20.558165 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 09:32:20.561602 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 09:32:20.568669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 09:32:20.571407 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 09:32:20.575136 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 09:32:20.581486 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 09:32:20.584907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 09:32:20.587992 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 09:32:20.594684 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 09:32:20.598501 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 09:32:20.601698 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 09:32:20.605001 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 09:32:20.611371 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3552 09:32:20.615014 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3553 09:32:20.618256 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3554 09:32:20.621736 Total UI for P1: 0, mck2ui 16
3555 09:32:20.624731 best dqsien dly found for B0: ( 1, 3, 22)
3556 09:32:20.631218 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 09:32:20.634677 Total UI for P1: 0, mck2ui 16
3558 09:32:20.638199 best dqsien dly found for B1: ( 1, 3, 26)
3559 09:32:20.641188 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3560 09:32:20.644815 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3561 09:32:20.645233
3562 09:32:20.648310 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3563 09:32:20.651150 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3564 09:32:20.654567 [Gating] SW calibration Done
3565 09:32:20.655081 ==
3566 09:32:20.657726 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 09:32:20.661623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 09:32:20.662044 ==
3569 09:32:20.664873 RX Vref Scan: 0
3570 09:32:20.665290
3571 09:32:20.665620 RX Vref 0 -> 0, step: 1
3572 09:32:20.665931
3573 09:32:20.668180 RX Delay -40 -> 252, step: 8
3574 09:32:20.671765 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3575 09:32:20.678280 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3576 09:32:20.681188 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3577 09:32:20.684543 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3578 09:32:20.688165 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3579 09:32:20.691335 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3580 09:32:20.698133 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3581 09:32:20.701460 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3582 09:32:20.704610 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3583 09:32:20.707836 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3584 09:32:20.711224 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3585 09:32:20.717998 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3586 09:32:20.721516 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3587 09:32:20.725090 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3588 09:32:20.728076 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3589 09:32:20.731536 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3590 09:32:20.731957 ==
3591 09:32:20.735090 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 09:32:20.741780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 09:32:20.742200 ==
3594 09:32:20.742533 DQS Delay:
3595 09:32:20.744796 DQS0 = 0, DQS1 = 0
3596 09:32:20.745209 DQM Delay:
3597 09:32:20.748343 DQM0 = 114, DQM1 = 109
3598 09:32:20.748760 DQ Delay:
3599 09:32:20.751792 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3600 09:32:20.754767 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3601 09:32:20.758230 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99
3602 09:32:20.761741 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
3603 09:32:20.762159
3604 09:32:20.762485
3605 09:32:20.762852 ==
3606 09:32:20.764952 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 09:32:20.768149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 09:32:20.771409 ==
3609 09:32:20.771824
3610 09:32:20.772154
3611 09:32:20.772460 TX Vref Scan disable
3612 09:32:20.774981 == TX Byte 0 ==
3613 09:32:20.778450 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3614 09:32:20.781347 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3615 09:32:20.784755 == TX Byte 1 ==
3616 09:32:20.788164 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3617 09:32:20.791774 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3618 09:32:20.792194 ==
3619 09:32:20.795076 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 09:32:20.801267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 09:32:20.801839 ==
3622 09:32:20.811932 TX Vref=22, minBit 1, minWin=25, winSum=415
3623 09:32:20.815212 TX Vref=24, minBit 0, minWin=26, winSum=425
3624 09:32:20.818793 TX Vref=26, minBit 7, minWin=25, winSum=428
3625 09:32:20.822107 TX Vref=28, minBit 4, minWin=26, winSum=432
3626 09:32:20.825620 TX Vref=30, minBit 2, minWin=26, winSum=432
3627 09:32:20.829223 TX Vref=32, minBit 0, minWin=26, winSum=431
3628 09:32:20.835804 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 28
3629 09:32:20.836222
3630 09:32:20.838624 Final TX Range 1 Vref 28
3631 09:32:20.839102
3632 09:32:20.839441 ==
3633 09:32:20.841919 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 09:32:20.845930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 09:32:20.846405 ==
3636 09:32:20.846921
3637 09:32:20.848809
3638 09:32:20.849411 TX Vref Scan disable
3639 09:32:20.852460 == TX Byte 0 ==
3640 09:32:20.855312 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3641 09:32:20.858918 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3642 09:32:20.862477 == TX Byte 1 ==
3643 09:32:20.865451 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3644 09:32:20.868844 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3645 09:32:20.869262
3646 09:32:20.872081 [DATLAT]
3647 09:32:20.872493 Freq=1200, CH1 RK1
3648 09:32:20.872823
3649 09:32:20.875831 DATLAT Default: 0xd
3650 09:32:20.876253 0, 0xFFFF, sum = 0
3651 09:32:20.879056 1, 0xFFFF, sum = 0
3652 09:32:20.879486 2, 0xFFFF, sum = 0
3653 09:32:20.882178 3, 0xFFFF, sum = 0
3654 09:32:20.882621 4, 0xFFFF, sum = 0
3655 09:32:20.885456 5, 0xFFFF, sum = 0
3656 09:32:20.885885 6, 0xFFFF, sum = 0
3657 09:32:20.889003 7, 0xFFFF, sum = 0
3658 09:32:20.889432 8, 0xFFFF, sum = 0
3659 09:32:20.892647 9, 0xFFFF, sum = 0
3660 09:32:20.893077 10, 0xFFFF, sum = 0
3661 09:32:20.896143 11, 0xFFFF, sum = 0
3662 09:32:20.896591 12, 0x0, sum = 1
3663 09:32:20.899168 13, 0x0, sum = 2
3664 09:32:20.899599 14, 0x0, sum = 3
3665 09:32:20.902609 15, 0x0, sum = 4
3666 09:32:20.903242 best_step = 13
3667 09:32:20.903590
3668 09:32:20.903902 ==
3669 09:32:20.905590 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 09:32:20.912614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 09:32:20.913039 ==
3672 09:32:20.913372 RX Vref Scan: 0
3673 09:32:20.913682
3674 09:32:20.915753 RX Vref 0 -> 0, step: 1
3675 09:32:20.916174
3676 09:32:20.919238 RX Delay -21 -> 252, step: 4
3677 09:32:20.922249 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3678 09:32:20.925781 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3679 09:32:20.932428 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3680 09:32:20.936015 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3681 09:32:20.939432 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3682 09:32:20.942583 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3683 09:32:20.946229 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3684 09:32:20.949684 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3685 09:32:20.955641 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3686 09:32:20.959364 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3687 09:32:20.962552 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3688 09:32:20.966360 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3689 09:32:20.969815 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3690 09:32:20.976083 iDelay=191, Bit 13, Center 118 (51 ~ 186) 136
3691 09:32:20.979719 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3692 09:32:20.983080 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3693 09:32:20.983680 ==
3694 09:32:20.985805 Dram Type= 6, Freq= 0, CH_1, rank 1
3695 09:32:20.989427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3696 09:32:20.989901 ==
3697 09:32:20.992684 DQS Delay:
3698 09:32:20.993151 DQS0 = 0, DQS1 = 0
3699 09:32:20.995887 DQM Delay:
3700 09:32:20.996389 DQM0 = 113, DQM1 = 108
3701 09:32:20.999303 DQ Delay:
3702 09:32:21.002925 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3703 09:32:21.005872 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3704 09:32:21.009402 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3705 09:32:21.012882 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =116
3706 09:32:21.013353
3707 09:32:21.013721
3708 09:32:21.019866 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3709 09:32:21.023458 CH1 RK1: MR19=304, MR18=FB02
3710 09:32:21.029598 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3711 09:32:21.033144 [RxdqsGatingPostProcess] freq 1200
3712 09:32:21.036437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3713 09:32:21.039517 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 09:32:21.043022 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 09:32:21.046512 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 09:32:21.049907 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 09:32:21.053491 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 09:32:21.056374 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 09:32:21.059711 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 09:32:21.063234 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 09:32:21.066521 Pre-setting of DQS Precalculation
3722 09:32:21.069691 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3723 09:32:21.076526 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3724 09:32:21.086673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3725 09:32:21.087210
3726 09:32:21.087582
3727 09:32:21.089853 [Calibration Summary] 2400 Mbps
3728 09:32:21.090278 CH 0, Rank 0
3729 09:32:21.092982 SW Impedance : PASS
3730 09:32:21.093405 DUTY Scan : NO K
3731 09:32:21.096310 ZQ Calibration : PASS
3732 09:32:21.099752 Jitter Meter : NO K
3733 09:32:21.100176 CBT Training : PASS
3734 09:32:21.103455 Write leveling : PASS
3735 09:32:21.103996 RX DQS gating : PASS
3736 09:32:21.106271 RX DQ/DQS(RDDQC) : PASS
3737 09:32:21.109802 TX DQ/DQS : PASS
3738 09:32:21.110228 RX DATLAT : PASS
3739 09:32:21.113407 RX DQ/DQS(Engine): PASS
3740 09:32:21.116346 TX OE : NO K
3741 09:32:21.116771 All Pass.
3742 09:32:21.117104
3743 09:32:21.117409 CH 0, Rank 1
3744 09:32:21.119740 SW Impedance : PASS
3745 09:32:21.123315 DUTY Scan : NO K
3746 09:32:21.123739 ZQ Calibration : PASS
3747 09:32:21.126387 Jitter Meter : NO K
3748 09:32:21.129854 CBT Training : PASS
3749 09:32:21.130278 Write leveling : PASS
3750 09:32:21.133124 RX DQS gating : PASS
3751 09:32:21.136816 RX DQ/DQS(RDDQC) : PASS
3752 09:32:21.137240 TX DQ/DQS : PASS
3753 09:32:21.139820 RX DATLAT : PASS
3754 09:32:21.140243 RX DQ/DQS(Engine): PASS
3755 09:32:21.143804 TX OE : NO K
3756 09:32:21.144230 All Pass.
3757 09:32:21.144564
3758 09:32:21.146458 CH 1, Rank 0
3759 09:32:21.146960 SW Impedance : PASS
3760 09:32:21.150053 DUTY Scan : NO K
3761 09:32:21.153545 ZQ Calibration : PASS
3762 09:32:21.153993 Jitter Meter : NO K
3763 09:32:21.156954 CBT Training : PASS
3764 09:32:21.160309 Write leveling : PASS
3765 09:32:21.160731 RX DQS gating : PASS
3766 09:32:21.163279 RX DQ/DQS(RDDQC) : PASS
3767 09:32:21.167193 TX DQ/DQS : PASS
3768 09:32:21.167711 RX DATLAT : PASS
3769 09:32:21.170663 RX DQ/DQS(Engine): PASS
3770 09:32:21.171222 TX OE : NO K
3771 09:32:21.173693 All Pass.
3772 09:32:21.174211
3773 09:32:21.174552 CH 1, Rank 1
3774 09:32:21.176975 SW Impedance : PASS
3775 09:32:21.177399 DUTY Scan : NO K
3776 09:32:21.180276 ZQ Calibration : PASS
3777 09:32:21.183533 Jitter Meter : NO K
3778 09:32:21.184075 CBT Training : PASS
3779 09:32:21.186941 Write leveling : PASS
3780 09:32:21.190099 RX DQS gating : PASS
3781 09:32:21.190600 RX DQ/DQS(RDDQC) : PASS
3782 09:32:21.193571 TX DQ/DQS : PASS
3783 09:32:21.197041 RX DATLAT : PASS
3784 09:32:21.197463 RX DQ/DQS(Engine): PASS
3785 09:32:21.200312 TX OE : NO K
3786 09:32:21.200737 All Pass.
3787 09:32:21.201189
3788 09:32:21.203831 DramC Write-DBI off
3789 09:32:21.207036 PER_BANK_REFRESH: Hybrid Mode
3790 09:32:21.207453 TX_TRACKING: ON
3791 09:32:21.216956 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3792 09:32:21.220436 [FAST_K] Save calibration result to emmc
3793 09:32:21.224047 dramc_set_vcore_voltage set vcore to 650000
3794 09:32:21.227014 Read voltage for 600, 5
3795 09:32:21.227436 Vio18 = 0
3796 09:32:21.227768 Vcore = 650000
3797 09:32:21.230512 Vdram = 0
3798 09:32:21.231019 Vddq = 0
3799 09:32:21.231358 Vmddr = 0
3800 09:32:21.236910 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3801 09:32:21.240326 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3802 09:32:21.243546 MEM_TYPE=3, freq_sel=19
3803 09:32:21.247054 sv_algorithm_assistance_LP4_1600
3804 09:32:21.250499 ============ PULL DRAM RESETB DOWN ============
3805 09:32:21.253942 ========== PULL DRAM RESETB DOWN end =========
3806 09:32:21.260652 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3807 09:32:21.263847 ===================================
3808 09:32:21.264276 LPDDR4 DRAM CONFIGURATION
3809 09:32:21.267281 ===================================
3810 09:32:21.270498 EX_ROW_EN[0] = 0x0
3811 09:32:21.270965 EX_ROW_EN[1] = 0x0
3812 09:32:21.273752 LP4Y_EN = 0x0
3813 09:32:21.274173 WORK_FSP = 0x0
3814 09:32:21.277289 WL = 0x2
3815 09:32:21.280746 RL = 0x2
3816 09:32:21.281169 BL = 0x2
3817 09:32:21.284431 RPST = 0x0
3818 09:32:21.284952 RD_PRE = 0x0
3819 09:32:21.287304 WR_PRE = 0x1
3820 09:32:21.287728 WR_PST = 0x0
3821 09:32:21.290652 DBI_WR = 0x0
3822 09:32:21.291133 DBI_RD = 0x0
3823 09:32:21.293893 OTF = 0x1
3824 09:32:21.297510 ===================================
3825 09:32:21.300424 ===================================
3826 09:32:21.300851 ANA top config
3827 09:32:21.304225 ===================================
3828 09:32:21.307736 DLL_ASYNC_EN = 0
3829 09:32:21.310978 ALL_SLAVE_EN = 1
3830 09:32:21.311579 NEW_RANK_MODE = 1
3831 09:32:21.314148 DLL_IDLE_MODE = 1
3832 09:32:21.317520 LP45_APHY_COMB_EN = 1
3833 09:32:21.320535 TX_ODT_DIS = 1
3834 09:32:21.320684 NEW_8X_MODE = 1
3835 09:32:21.323490 ===================================
3836 09:32:21.327118 ===================================
3837 09:32:21.330581 data_rate = 1200
3838 09:32:21.333524 CKR = 1
3839 09:32:21.336973 DQ_P2S_RATIO = 8
3840 09:32:21.340651 ===================================
3841 09:32:21.344009 CA_P2S_RATIO = 8
3842 09:32:21.347747 DQ_CA_OPEN = 0
3843 09:32:21.348171 DQ_SEMI_OPEN = 0
3844 09:32:21.350781 CA_SEMI_OPEN = 0
3845 09:32:21.354577 CA_FULL_RATE = 0
3846 09:32:21.357550 DQ_CKDIV4_EN = 1
3847 09:32:21.360785 CA_CKDIV4_EN = 1
3848 09:32:21.364622 CA_PREDIV_EN = 0
3849 09:32:21.365294 PH8_DLY = 0
3850 09:32:21.367414 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3851 09:32:21.370669 DQ_AAMCK_DIV = 4
3852 09:32:21.374038 CA_AAMCK_DIV = 4
3853 09:32:21.377456 CA_ADMCK_DIV = 4
3854 09:32:21.377875 DQ_TRACK_CA_EN = 0
3855 09:32:21.380579 CA_PICK = 600
3856 09:32:21.384489 CA_MCKIO = 600
3857 09:32:21.387701 MCKIO_SEMI = 0
3858 09:32:21.391082 PLL_FREQ = 2288
3859 09:32:21.393962 DQ_UI_PI_RATIO = 32
3860 09:32:21.397763 CA_UI_PI_RATIO = 0
3861 09:32:21.401179 ===================================
3862 09:32:21.404462 ===================================
3863 09:32:21.405052 memory_type:LPDDR4
3864 09:32:21.407532 GP_NUM : 10
3865 09:32:21.410977 SRAM_EN : 1
3866 09:32:21.411466 MD32_EN : 0
3867 09:32:21.414203 ===================================
3868 09:32:21.417123 [ANA_INIT] >>>>>>>>>>>>>>
3869 09:32:21.420931 <<<<<< [CONFIGURE PHASE]: ANA_TX
3870 09:32:21.424492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3871 09:32:21.427600 ===================================
3872 09:32:21.431183 data_rate = 1200,PCW = 0X5800
3873 09:32:21.434186 ===================================
3874 09:32:21.437991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3875 09:32:21.441653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3876 09:32:21.447892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 09:32:21.451149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3878 09:32:21.454686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3879 09:32:21.457978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3880 09:32:21.461206 [ANA_INIT] flow start
3881 09:32:21.464703 [ANA_INIT] PLL >>>>>>>>
3882 09:32:21.465237 [ANA_INIT] PLL <<<<<<<<
3883 09:32:21.467646 [ANA_INIT] MIDPI >>>>>>>>
3884 09:32:21.471194 [ANA_INIT] MIDPI <<<<<<<<
3885 09:32:21.471624 [ANA_INIT] DLL >>>>>>>>
3886 09:32:21.474556 [ANA_INIT] flow end
3887 09:32:21.478012 ============ LP4 DIFF to SE enter ============
3888 09:32:21.481780 ============ LP4 DIFF to SE exit ============
3889 09:32:21.484534 [ANA_INIT] <<<<<<<<<<<<<
3890 09:32:21.487672 [Flow] Enable top DCM control >>>>>
3891 09:32:21.491725 [Flow] Enable top DCM control <<<<<
3892 09:32:21.494551 Enable DLL master slave shuffle
3893 09:32:21.501571 ==============================================================
3894 09:32:21.502123 Gating Mode config
3895 09:32:21.508089 ==============================================================
3896 09:32:21.508555 Config description:
3897 09:32:21.517817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3898 09:32:21.524615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3899 09:32:21.531351 SELPH_MODE 0: By rank 1: By Phase
3900 09:32:21.534511 ==============================================================
3901 09:32:21.538119 GAT_TRACK_EN = 1
3902 09:32:21.541459 RX_GATING_MODE = 2
3903 09:32:21.544506 RX_GATING_TRACK_MODE = 2
3904 09:32:21.548187 SELPH_MODE = 1
3905 09:32:21.551104 PICG_EARLY_EN = 1
3906 09:32:21.554569 VALID_LAT_VALUE = 1
3907 09:32:21.558064 ==============================================================
3908 09:32:21.561410 Enter into Gating configuration >>>>
3909 09:32:21.564912 Exit from Gating configuration <<<<
3910 09:32:21.567610 Enter into DVFS_PRE_config >>>>>
3911 09:32:21.581517 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3912 09:32:21.584699 Exit from DVFS_PRE_config <<<<<
3913 09:32:21.585213 Enter into PICG configuration >>>>
3914 09:32:21.588148 Exit from PICG configuration <<<<
3915 09:32:21.591461 [RX_INPUT] configuration >>>>>
3916 09:32:21.594656 [RX_INPUT] configuration <<<<<
3917 09:32:21.601727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3918 09:32:21.604789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3919 09:32:21.610904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 09:32:21.617988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 09:32:21.624722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 09:32:21.631268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 09:32:21.634972 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3924 09:32:21.637853 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3925 09:32:21.641462 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3926 09:32:21.647995 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3927 09:32:21.651394 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3928 09:32:21.654590 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3929 09:32:21.657854 ===================================
3930 09:32:21.661492 LPDDR4 DRAM CONFIGURATION
3931 09:32:21.664833 ===================================
3932 09:32:21.665256 EX_ROW_EN[0] = 0x0
3933 09:32:21.668204 EX_ROW_EN[1] = 0x0
3934 09:32:21.668803 LP4Y_EN = 0x0
3935 09:32:21.671423 WORK_FSP = 0x0
3936 09:32:21.674923 WL = 0x2
3937 09:32:21.675343 RL = 0x2
3938 09:32:21.678485 BL = 0x2
3939 09:32:21.678943 RPST = 0x0
3940 09:32:21.681509 RD_PRE = 0x0
3941 09:32:21.681925 WR_PRE = 0x1
3942 09:32:21.685265 WR_PST = 0x0
3943 09:32:21.685782 DBI_WR = 0x0
3944 09:32:21.688491 DBI_RD = 0x0
3945 09:32:21.688936 OTF = 0x1
3946 09:32:21.691382 ===================================
3947 09:32:21.694828 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3948 09:32:21.701932 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3949 09:32:21.704887 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3950 09:32:21.708399 ===================================
3951 09:32:21.711192 LPDDR4 DRAM CONFIGURATION
3952 09:32:21.714473 ===================================
3953 09:32:21.715012 EX_ROW_EN[0] = 0x10
3954 09:32:21.717798 EX_ROW_EN[1] = 0x0
3955 09:32:21.718190 LP4Y_EN = 0x0
3956 09:32:21.721470 WORK_FSP = 0x0
3957 09:32:21.721931 WL = 0x2
3958 09:32:21.724868 RL = 0x2
3959 09:32:21.725292 BL = 0x2
3960 09:32:21.728059 RPST = 0x0
3961 09:32:21.728698 RD_PRE = 0x0
3962 09:32:21.731209 WR_PRE = 0x1
3963 09:32:21.731664 WR_PST = 0x0
3964 09:32:21.734786 DBI_WR = 0x0
3965 09:32:21.738021 DBI_RD = 0x0
3966 09:32:21.738433 OTF = 0x1
3967 09:32:21.741647 ===================================
3968 09:32:21.747962 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3969 09:32:21.751716 nWR fixed to 30
3970 09:32:21.755053 [ModeRegInit_LP4] CH0 RK0
3971 09:32:21.755475 [ModeRegInit_LP4] CH0 RK1
3972 09:32:21.758175 [ModeRegInit_LP4] CH1 RK0
3973 09:32:21.761413 [ModeRegInit_LP4] CH1 RK1
3974 09:32:21.761860 match AC timing 17
3975 09:32:21.768038 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3976 09:32:21.771277 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3977 09:32:21.774423 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3978 09:32:21.781447 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3979 09:32:21.784372 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3980 09:32:21.784453 ==
3981 09:32:21.787909 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 09:32:21.791392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 09:32:21.791474 ==
3984 09:32:21.797973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 09:32:21.804535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3986 09:32:21.808004 [CA 0] Center 36 (6~67) winsize 62
3987 09:32:21.811424 [CA 1] Center 36 (6~66) winsize 61
3988 09:32:21.814336 [CA 2] Center 34 (4~65) winsize 62
3989 09:32:21.818070 [CA 3] Center 34 (4~65) winsize 62
3990 09:32:21.821510 [CA 4] Center 34 (4~64) winsize 61
3991 09:32:21.824427 [CA 5] Center 33 (3~64) winsize 62
3992 09:32:21.824535
3993 09:32:21.827958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3994 09:32:21.828032
3995 09:32:21.831400 [CATrainingPosCal] consider 1 rank data
3996 09:32:21.834379 u2DelayCellTimex100 = 270/100 ps
3997 09:32:21.837828 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 09:32:21.841169 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3999 09:32:21.844220 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 09:32:21.847785 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 09:32:21.851076 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4002 09:32:21.854314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 09:32:21.854385
4004 09:32:21.861017 CA PerBit enable=1, Macro0, CA PI delay=33
4005 09:32:21.861103
4006 09:32:21.861170 [CBTSetCACLKResult] CA Dly = 33
4007 09:32:21.864799 CS Dly: 4 (0~35)
4008 09:32:21.864892 ==
4009 09:32:21.868381 Dram Type= 6, Freq= 0, CH_0, rank 1
4010 09:32:21.871875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 09:32:21.872068 ==
4012 09:32:21.878489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4013 09:32:21.884489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4014 09:32:21.887818 [CA 0] Center 35 (5~66) winsize 62
4015 09:32:21.891153 [CA 1] Center 35 (5~66) winsize 62
4016 09:32:21.895011 [CA 2] Center 34 (4~65) winsize 62
4017 09:32:21.898368 [CA 3] Center 34 (4~65) winsize 62
4018 09:32:21.901894 [CA 4] Center 33 (3~64) winsize 62
4019 09:32:21.904883 [CA 5] Center 33 (3~64) winsize 62
4020 09:32:21.905306
4021 09:32:21.908358 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4022 09:32:21.908780
4023 09:32:21.911939 [CATrainingPosCal] consider 2 rank data
4024 09:32:21.914868 u2DelayCellTimex100 = 270/100 ps
4025 09:32:21.918359 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4026 09:32:21.921847 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4027 09:32:21.924773 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4028 09:32:21.928279 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4029 09:32:21.931842 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4030 09:32:21.935311 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4031 09:32:21.935748
4032 09:32:21.938186 CA PerBit enable=1, Macro0, CA PI delay=33
4033 09:32:21.942061
4034 09:32:21.942479 [CBTSetCACLKResult] CA Dly = 33
4035 09:32:21.945476 CS Dly: 4 (0~36)
4036 09:32:21.945898
4037 09:32:21.948786 ----->DramcWriteLeveling(PI) begin...
4038 09:32:21.949218 ==
4039 09:32:21.951536 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 09:32:21.955212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 09:32:21.955638 ==
4042 09:32:21.958225 Write leveling (Byte 0): 35 => 35
4043 09:32:21.961791 Write leveling (Byte 1): 28 => 28
4044 09:32:21.965308 DramcWriteLeveling(PI) end<-----
4045 09:32:21.965731
4046 09:32:21.966125 ==
4047 09:32:21.968446 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 09:32:21.972117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 09:32:21.972420 ==
4050 09:32:21.975254 [Gating] SW mode calibration
4051 09:32:21.981865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4052 09:32:21.988399 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4053 09:32:21.991517 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 09:32:21.998199 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 09:32:22.001483 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 09:32:22.005130 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 09:32:22.008651 0 9 16 | B1->B0 | 3131 2525 | 1 1 | (0 1) (1 0)
4058 09:32:22.015049 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 09:32:22.018614 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 09:32:22.021445 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 09:32:22.028383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 09:32:22.031956 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 09:32:22.034804 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 09:32:22.041831 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 09:32:22.045143 0 10 16 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (1 1)
4066 09:32:22.048458 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4067 09:32:22.055398 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 09:32:22.058168 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 09:32:22.061644 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 09:32:22.068396 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 09:32:22.071831 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 09:32:22.075185 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4073 09:32:22.081731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4074 09:32:22.084685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 09:32:22.088608 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 09:32:22.091419 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 09:32:22.098340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 09:32:22.101816 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 09:32:22.104992 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 09:32:22.111729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 09:32:22.115347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 09:32:22.118376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 09:32:22.125369 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 09:32:22.128340 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 09:32:22.131888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 09:32:22.138612 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 09:32:22.141816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 09:32:22.145346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4089 09:32:22.152316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4090 09:32:22.155575 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4091 09:32:22.159058 Total UI for P1: 0, mck2ui 16
4092 09:32:22.162294 best dqsien dly found for B0: ( 0, 13, 14)
4093 09:32:22.165812 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 09:32:22.168718 Total UI for P1: 0, mck2ui 16
4095 09:32:22.172075 best dqsien dly found for B1: ( 0, 13, 20)
4096 09:32:22.175302 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4097 09:32:22.178974 best DQS1 dly(MCK, UI, PI) = (0, 13, 20)
4098 09:32:22.179429
4099 09:32:22.181877 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4100 09:32:22.188828 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 20)
4101 09:32:22.189222 [Gating] SW calibration Done
4102 09:32:22.189647 ==
4103 09:32:22.192182 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 09:32:22.198970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 09:32:22.199421 ==
4106 09:32:22.199764 RX Vref Scan: 0
4107 09:32:22.200100
4108 09:32:22.202171 RX Vref 0 -> 0, step: 1
4109 09:32:22.202590
4110 09:32:22.205527 RX Delay -230 -> 252, step: 16
4111 09:32:22.209048 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4112 09:32:22.212484 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4113 09:32:22.215587 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4114 09:32:22.222361 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4115 09:32:22.225675 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4116 09:32:22.228769 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4117 09:32:22.232324 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4118 09:32:22.238938 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4119 09:32:22.242597 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4120 09:32:22.245369 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4121 09:32:22.248861 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4122 09:32:22.252633 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4123 09:32:22.258808 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4124 09:32:22.261975 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4125 09:32:22.265864 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4126 09:32:22.268698 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4127 09:32:22.269202 ==
4128 09:32:22.272295 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 09:32:22.278800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 09:32:22.279175 ==
4131 09:32:22.279527 DQS Delay:
4132 09:32:22.282369 DQS0 = 0, DQS1 = 0
4133 09:32:22.282655 DQM Delay:
4134 09:32:22.282909 DQM0 = 40, DQM1 = 32
4135 09:32:22.285781 DQ Delay:
4136 09:32:22.289273 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4137 09:32:22.292343 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4138 09:32:22.295860 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4139 09:32:22.299417 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4140 09:32:22.299677
4141 09:32:22.299924
4142 09:32:22.300152 ==
4143 09:32:22.302853 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 09:32:22.306052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 09:32:22.306276 ==
4146 09:32:22.306448
4147 09:32:22.306601
4148 09:32:22.309193 TX Vref Scan disable
4149 09:32:22.309393 == TX Byte 0 ==
4150 09:32:22.316112 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4151 09:32:22.319223 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4152 09:32:22.319528 == TX Byte 1 ==
4153 09:32:22.326159 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4154 09:32:22.329594 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4155 09:32:22.329825 ==
4156 09:32:22.333088 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 09:32:22.336335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 09:32:22.336550 ==
4159 09:32:22.336719
4160 09:32:22.336954
4161 09:32:22.339211 TX Vref Scan disable
4162 09:32:22.342941 == TX Byte 0 ==
4163 09:32:22.345727 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4164 09:32:22.349371 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4165 09:32:22.352950 == TX Byte 1 ==
4166 09:32:22.355797 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4167 09:32:22.359359 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4168 09:32:22.362902
4169 09:32:22.363112 [DATLAT]
4170 09:32:22.363279 Freq=600, CH0 RK0
4171 09:32:22.363437
4172 09:32:22.366091 DATLAT Default: 0x9
4173 09:32:22.366309 0, 0xFFFF, sum = 0
4174 09:32:22.369350 1, 0xFFFF, sum = 0
4175 09:32:22.369637 2, 0xFFFF, sum = 0
4176 09:32:22.372685 3, 0xFFFF, sum = 0
4177 09:32:22.372912 4, 0xFFFF, sum = 0
4178 09:32:22.376059 5, 0xFFFF, sum = 0
4179 09:32:22.376318 6, 0xFFFF, sum = 0
4180 09:32:22.379765 7, 0xFFFF, sum = 0
4181 09:32:22.380001 8, 0x0, sum = 1
4182 09:32:22.383008 9, 0x0, sum = 2
4183 09:32:22.383223 10, 0x0, sum = 3
4184 09:32:22.386465 11, 0x0, sum = 4
4185 09:32:22.386705 best_step = 9
4186 09:32:22.386909
4187 09:32:22.387070 ==
4188 09:32:22.389698 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 09:32:22.396226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 09:32:22.396441 ==
4191 09:32:22.396610 RX Vref Scan: 1
4192 09:32:22.396776
4193 09:32:22.399227 RX Vref 0 -> 0, step: 1
4194 09:32:22.399447
4195 09:32:22.402757 RX Delay -195 -> 252, step: 8
4196 09:32:22.402970
4197 09:32:22.406486 Set Vref, RX VrefLevel [Byte0]: 54
4198 09:32:22.409827 [Byte1]: 52
4199 09:32:22.410039
4200 09:32:22.412661 Final RX Vref Byte 0 = 54 to rank0
4201 09:32:22.416183 Final RX Vref Byte 1 = 52 to rank0
4202 09:32:22.419533 Final RX Vref Byte 0 = 54 to rank1
4203 09:32:22.422913 Final RX Vref Byte 1 = 52 to rank1==
4204 09:32:22.426376 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 09:32:22.430081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 09:32:22.430408 ==
4207 09:32:22.430665 DQS Delay:
4208 09:32:22.432747 DQS0 = 0, DQS1 = 0
4209 09:32:22.433090 DQM Delay:
4210 09:32:22.436321 DQM0 = 43, DQM1 = 33
4211 09:32:22.436645 DQ Delay:
4212 09:32:22.439926 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4213 09:32:22.442766 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4214 09:32:22.446187 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4215 09:32:22.449386 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4216 09:32:22.449712
4217 09:32:22.450101
4218 09:32:22.459416 [DQSOSCAuto] RK0, (LSB)MR18= 0x4524, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4219 09:32:22.459745 CH0 RK0: MR19=808, MR18=4524
4220 09:32:22.466321 CH0_RK0: MR19=0x808, MR18=0x4524, DQSOSC=396, MR23=63, INC=167, DEC=111
4221 09:32:22.466645
4222 09:32:22.469745 ----->DramcWriteLeveling(PI) begin...
4223 09:32:22.470072 ==
4224 09:32:22.472507 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 09:32:22.479749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 09:32:22.480078 ==
4227 09:32:22.482674 Write leveling (Byte 0): 32 => 32
4228 09:32:22.486207 Write leveling (Byte 1): 31 => 31
4229 09:32:22.486597 DramcWriteLeveling(PI) end<-----
4230 09:32:22.489616
4231 09:32:22.489854 ==
4232 09:32:22.492841 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 09:32:22.496331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 09:32:22.496522 ==
4235 09:32:22.499361 [Gating] SW mode calibration
4236 09:32:22.505893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 09:32:22.509329 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4238 09:32:22.516232 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 09:32:22.519617 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 09:32:22.522625 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 09:32:22.529692 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4242 09:32:22.532751 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
4243 09:32:22.536097 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 09:32:22.542816 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 09:32:22.546177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 09:32:22.549633 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 09:32:22.556065 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 09:32:22.559647 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 09:32:22.562777 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
4250 09:32:22.566223 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4251 09:32:22.573267 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 09:32:22.576174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 09:32:22.579670 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 09:32:22.586549 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 09:32:22.590042 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 09:32:22.593048 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 09:32:22.599733 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4258 09:32:22.602714 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4259 09:32:22.606117 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 09:32:22.613262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 09:32:22.616229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 09:32:22.619537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 09:32:22.626078 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 09:32:22.629474 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 09:32:22.632877 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 09:32:22.639689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 09:32:22.642963 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 09:32:22.646410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 09:32:22.649818 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 09:32:22.656646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 09:32:22.660172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 09:32:22.663128 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 09:32:22.670146 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4274 09:32:22.673306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4275 09:32:22.676754 Total UI for P1: 0, mck2ui 16
4276 09:32:22.680079 best dqsien dly found for B0: ( 0, 13, 12)
4277 09:32:22.683585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 09:32:22.687148 Total UI for P1: 0, mck2ui 16
4279 09:32:22.690238 best dqsien dly found for B1: ( 0, 13, 14)
4280 09:32:22.693275 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4281 09:32:22.697032 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4282 09:32:22.697439
4283 09:32:22.703467 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4284 09:32:22.706915 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4285 09:32:22.707216 [Gating] SW calibration Done
4286 09:32:22.709913 ==
4287 09:32:22.710212 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 09:32:22.716826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 09:32:22.717130 ==
4290 09:32:22.717394 RX Vref Scan: 0
4291 09:32:22.717632
4292 09:32:22.720275 RX Vref 0 -> 0, step: 1
4293 09:32:22.720588
4294 09:32:22.723226 RX Delay -230 -> 252, step: 16
4295 09:32:22.726509 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4296 09:32:22.729915 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4297 09:32:22.736525 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4298 09:32:22.739865 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4299 09:32:22.743285 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4300 09:32:22.746492 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4301 09:32:22.749871 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4302 09:32:22.756767 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4303 09:32:22.760277 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4304 09:32:22.763313 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4305 09:32:22.766361 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4306 09:32:22.769864 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4307 09:32:22.776753 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4308 09:32:22.780080 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4309 09:32:22.783226 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4310 09:32:22.786714 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4311 09:32:22.789894 ==
4312 09:32:22.789977 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 09:32:22.796669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 09:32:22.796751 ==
4315 09:32:22.796815 DQS Delay:
4316 09:32:22.800172 DQS0 = 0, DQS1 = 0
4317 09:32:22.800253 DQM Delay:
4318 09:32:22.803179 DQM0 = 40, DQM1 = 32
4319 09:32:22.803260 DQ Delay:
4320 09:32:22.806429 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4321 09:32:22.809760 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4322 09:32:22.813267 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4323 09:32:22.816777 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4324 09:32:22.816859
4325 09:32:22.816923
4326 09:32:22.816982 ==
4327 09:32:22.820349 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 09:32:22.823941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 09:32:22.824023 ==
4330 09:32:22.824087
4331 09:32:22.824147
4332 09:32:22.826883 TX Vref Scan disable
4333 09:32:22.830452 == TX Byte 0 ==
4334 09:32:22.833338 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4335 09:32:22.836746 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4336 09:32:22.836828 == TX Byte 1 ==
4337 09:32:22.843539 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4338 09:32:22.847074 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4339 09:32:22.847156 ==
4340 09:32:22.850404 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 09:32:22.853801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 09:32:22.853895 ==
4343 09:32:22.853969
4344 09:32:22.854037
4345 09:32:22.856695 TX Vref Scan disable
4346 09:32:22.860705 == TX Byte 0 ==
4347 09:32:22.863514 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4348 09:32:22.867184 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4349 09:32:22.870625 == TX Byte 1 ==
4350 09:32:22.873801 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4351 09:32:22.877044 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4352 09:32:22.880567
4353 09:32:22.880700 [DATLAT]
4354 09:32:22.880806 Freq=600, CH0 RK1
4355 09:32:22.880906
4356 09:32:22.884004 DATLAT Default: 0x9
4357 09:32:22.884137 0, 0xFFFF, sum = 0
4358 09:32:22.887419 1, 0xFFFF, sum = 0
4359 09:32:22.887556 2, 0xFFFF, sum = 0
4360 09:32:22.890693 3, 0xFFFF, sum = 0
4361 09:32:22.890849 4, 0xFFFF, sum = 0
4362 09:32:22.893947 5, 0xFFFF, sum = 0
4363 09:32:22.894093 6, 0xFFFF, sum = 0
4364 09:32:22.897046 7, 0xFFFF, sum = 0
4365 09:32:22.897216 8, 0x0, sum = 1
4366 09:32:22.900636 9, 0x0, sum = 2
4367 09:32:22.900774 10, 0x0, sum = 3
4368 09:32:22.903912 11, 0x0, sum = 4
4369 09:32:22.904048 best_step = 9
4370 09:32:22.904154
4371 09:32:22.904253 ==
4372 09:32:22.907206 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 09:32:22.913598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 09:32:22.913800 ==
4375 09:32:22.913912 RX Vref Scan: 0
4376 09:32:22.914032
4377 09:32:22.917262 RX Vref 0 -> 0, step: 1
4378 09:32:22.917413
4379 09:32:22.920691 RX Delay -195 -> 252, step: 8
4380 09:32:22.923677 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4381 09:32:22.930684 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4382 09:32:22.933726 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4383 09:32:22.937204 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4384 09:32:22.940523 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4385 09:32:22.943869 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4386 09:32:22.950475 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4387 09:32:22.953924 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4388 09:32:22.957296 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4389 09:32:22.960349 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4390 09:32:22.963900 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4391 09:32:22.970580 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4392 09:32:22.974214 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4393 09:32:22.977215 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4394 09:32:22.980637 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4395 09:32:22.987437 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4396 09:32:22.987564 ==
4397 09:32:22.990976 Dram Type= 6, Freq= 0, CH_0, rank 1
4398 09:32:22.993774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 09:32:22.993857 ==
4400 09:32:22.993923 DQS Delay:
4401 09:32:22.997113 DQS0 = 0, DQS1 = 0
4402 09:32:22.997195 DQM Delay:
4403 09:32:23.000678 DQM0 = 39, DQM1 = 32
4404 09:32:23.000760 DQ Delay:
4405 09:32:23.004058 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4406 09:32:23.007233 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4407 09:32:23.010443 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4408 09:32:23.013910 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4409 09:32:23.013994
4410 09:32:23.014058
4411 09:32:23.020701 [DQSOSCAuto] RK1, (LSB)MR18= 0x492c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4412 09:32:23.023992 CH0 RK1: MR19=808, MR18=492C
4413 09:32:23.030960 CH0_RK1: MR19=0x808, MR18=0x492C, DQSOSC=396, MR23=63, INC=167, DEC=111
4414 09:32:23.034504 [RxdqsGatingPostProcess] freq 600
4415 09:32:23.040842 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4416 09:32:23.040924 Pre-setting of DQS Precalculation
4417 09:32:23.047445 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4418 09:32:23.047530 ==
4419 09:32:23.051392 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 09:32:23.054446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 09:32:23.054528 ==
4422 09:32:23.061366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4423 09:32:23.067788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4424 09:32:23.071478 [CA 0] Center 35 (5~66) winsize 62
4425 09:32:23.074776 [CA 1] Center 35 (5~66) winsize 62
4426 09:32:23.078153 [CA 2] Center 34 (4~64) winsize 61
4427 09:32:23.081673 [CA 3] Center 33 (2~64) winsize 63
4428 09:32:23.084560 [CA 4] Center 33 (3~64) winsize 62
4429 09:32:23.088182 [CA 5] Center 33 (2~64) winsize 63
4430 09:32:23.088605
4431 09:32:23.091140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4432 09:32:23.091560
4433 09:32:23.094841 [CATrainingPosCal] consider 1 rank data
4434 09:32:23.098313 u2DelayCellTimex100 = 270/100 ps
4435 09:32:23.101422 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 09:32:23.104802 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4437 09:32:23.108284 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4438 09:32:23.111648 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
4439 09:32:23.114896 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 09:32:23.118089 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4441 09:32:23.118389
4442 09:32:23.121442 CA PerBit enable=1, Macro0, CA PI delay=33
4443 09:32:23.121743
4444 09:32:23.124941 [CBTSetCACLKResult] CA Dly = 33
4445 09:32:23.128210 CS Dly: 5 (0~36)
4446 09:32:23.128508 ==
4447 09:32:23.131791 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 09:32:23.134963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 09:32:23.135269 ==
4450 09:32:23.141768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 09:32:23.148039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4452 09:32:23.151550 [CA 0] Center 35 (5~66) winsize 62
4453 09:32:23.154799 [CA 1] Center 35 (5~66) winsize 62
4454 09:32:23.158279 [CA 2] Center 34 (3~65) winsize 63
4455 09:32:23.163212 [CA 3] Center 33 (3~64) winsize 62
4456 09:32:23.165020 [CA 4] Center 34 (3~65) winsize 63
4457 09:32:23.168255 [CA 5] Center 33 (2~64) winsize 63
4458 09:32:23.168557
4459 09:32:23.171504 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4460 09:32:23.171804
4461 09:32:23.174855 [CATrainingPosCal] consider 2 rank data
4462 09:32:23.178055 u2DelayCellTimex100 = 270/100 ps
4463 09:32:23.181551 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 09:32:23.184884 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 09:32:23.188267 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4466 09:32:23.191560 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 09:32:23.194884 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4468 09:32:23.198257 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4469 09:32:23.198677
4470 09:32:23.201873 CA PerBit enable=1, Macro0, CA PI delay=33
4471 09:32:23.202293
4472 09:32:23.204916 [CBTSetCACLKResult] CA Dly = 33
4473 09:32:23.208692 CS Dly: 5 (0~36)
4474 09:32:23.209114
4475 09:32:23.211790 ----->DramcWriteLeveling(PI) begin...
4476 09:32:23.212357 ==
4477 09:32:23.215225 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 09:32:23.218568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 09:32:23.219103 ==
4480 09:32:23.221786 Write leveling (Byte 0): 31 => 31
4481 09:32:23.224980 Write leveling (Byte 1): 32 => 32
4482 09:32:23.228588 DramcWriteLeveling(PI) end<-----
4483 09:32:23.229136
4484 09:32:23.229666 ==
4485 09:32:23.231889 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 09:32:23.235280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 09:32:23.235700 ==
4488 09:32:23.238491 [Gating] SW mode calibration
4489 09:32:23.245027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4490 09:32:23.252199 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4491 09:32:23.255213 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 09:32:23.258563 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 09:32:23.265112 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 09:32:23.268594 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (0 1)
4495 09:32:23.271785 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4496 09:32:23.278562 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 09:32:23.282070 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 09:32:23.285339 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 09:32:23.291896 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4500 09:32:23.295102 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 09:32:23.298521 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 09:32:23.305176 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4503 09:32:23.308368 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (1 1) (1 1)
4504 09:32:23.311743 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 09:32:23.318196 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 09:32:23.321408 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 09:32:23.325225 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 09:32:23.328642 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 09:32:23.334726 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 09:32:23.338418 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4511 09:32:23.341916 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4512 09:32:23.348233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 09:32:23.351877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 09:32:23.355129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 09:32:23.361665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 09:32:23.365353 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 09:32:23.368300 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 09:32:23.375441 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 09:32:23.378268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 09:32:23.382043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 09:32:23.388742 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 09:32:23.392268 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 09:32:23.395486 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 09:32:23.402263 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 09:32:23.404962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 09:32:23.408710 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4527 09:32:23.411780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 09:32:23.415575 Total UI for P1: 0, mck2ui 16
4529 09:32:23.418449 best dqsien dly found for B0: ( 0, 13, 12)
4530 09:32:23.422169 Total UI for P1: 0, mck2ui 16
4531 09:32:23.425507 best dqsien dly found for B1: ( 0, 13, 14)
4532 09:32:23.429088 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4533 09:32:23.432352 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4534 09:32:23.432435
4535 09:32:23.438580 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4536 09:32:23.442330 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4537 09:32:23.445568 [Gating] SW calibration Done
4538 09:32:23.445654 ==
4539 09:32:23.448733 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 09:32:23.452344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 09:32:23.452426 ==
4542 09:32:23.452491 RX Vref Scan: 0
4543 09:32:23.452551
4544 09:32:23.455752 RX Vref 0 -> 0, step: 1
4545 09:32:23.455834
4546 09:32:23.458883 RX Delay -230 -> 252, step: 16
4547 09:32:23.461957 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4548 09:32:23.465674 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4549 09:32:23.472397 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4550 09:32:23.475785 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4551 09:32:23.478641 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4552 09:32:23.482219 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4553 09:32:23.488740 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4554 09:32:23.491896 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4555 09:32:23.495719 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4556 09:32:23.498501 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4557 09:32:23.501914 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4558 09:32:23.508439 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4559 09:32:23.511819 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4560 09:32:23.515505 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4561 09:32:23.518894 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4562 09:32:23.525115 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4563 09:32:23.525198 ==
4564 09:32:23.528522 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 09:32:23.531992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 09:32:23.532074 ==
4567 09:32:23.532138 DQS Delay:
4568 09:32:23.535391 DQS0 = 0, DQS1 = 0
4569 09:32:23.535472 DQM Delay:
4570 09:32:23.538943 DQM0 = 43, DQM1 = 36
4571 09:32:23.539025 DQ Delay:
4572 09:32:23.542060 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4573 09:32:23.545242 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4574 09:32:23.548838 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4575 09:32:23.551868 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4576 09:32:23.551950
4577 09:32:23.552014
4578 09:32:23.552074 ==
4579 09:32:23.555282 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 09:32:23.558902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 09:32:23.558984 ==
4582 09:32:23.559048
4583 09:32:23.562164
4584 09:32:23.562245 TX Vref Scan disable
4585 09:32:23.565637 == TX Byte 0 ==
4586 09:32:23.568402 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4587 09:32:23.571893 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4588 09:32:23.575441 == TX Byte 1 ==
4589 09:32:23.578515 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 09:32:23.581881 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 09:32:23.581963 ==
4592 09:32:23.585346 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 09:32:23.592019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 09:32:23.592102 ==
4595 09:32:23.592166
4596 09:32:23.592225
4597 09:32:23.592282 TX Vref Scan disable
4598 09:32:23.596497 == TX Byte 0 ==
4599 09:32:23.599744 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4600 09:32:23.606546 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4601 09:32:23.606628 == TX Byte 1 ==
4602 09:32:23.609553 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4603 09:32:23.616534 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4604 09:32:23.616665
4605 09:32:23.616761 [DATLAT]
4606 09:32:23.616835 Freq=600, CH1 RK0
4607 09:32:23.616922
4608 09:32:23.619516 DATLAT Default: 0x9
4609 09:32:23.619626 0, 0xFFFF, sum = 0
4610 09:32:23.622728 1, 0xFFFF, sum = 0
4611 09:32:23.622914 2, 0xFFFF, sum = 0
4612 09:32:23.626631 3, 0xFFFF, sum = 0
4613 09:32:23.626915 4, 0xFFFF, sum = 0
4614 09:32:23.629938 5, 0xFFFF, sum = 0
4615 09:32:23.630100 6, 0xFFFF, sum = 0
4616 09:32:23.633419 7, 0xFFFF, sum = 0
4617 09:32:23.633587 8, 0x0, sum = 1
4618 09:32:23.636705 9, 0x0, sum = 2
4619 09:32:23.636835 10, 0x0, sum = 3
4620 09:32:23.639426 11, 0x0, sum = 4
4621 09:32:23.639560 best_step = 9
4622 09:32:23.639661
4623 09:32:23.639753 ==
4624 09:32:23.642906 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 09:32:23.649592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 09:32:23.649750 ==
4627 09:32:23.649824 RX Vref Scan: 1
4628 09:32:23.649914
4629 09:32:23.652831 RX Vref 0 -> 0, step: 1
4630 09:32:23.652913
4631 09:32:23.656401 RX Delay -179 -> 252, step: 8
4632 09:32:23.656512
4633 09:32:23.659685 Set Vref, RX VrefLevel [Byte0]: 57
4634 09:32:23.663381 [Byte1]: 49
4635 09:32:23.663462
4636 09:32:23.666709 Final RX Vref Byte 0 = 57 to rank0
4637 09:32:23.669724 Final RX Vref Byte 1 = 49 to rank0
4638 09:32:23.672932 Final RX Vref Byte 0 = 57 to rank1
4639 09:32:23.676832 Final RX Vref Byte 1 = 49 to rank1==
4640 09:32:23.679762 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 09:32:23.683017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 09:32:23.683123 ==
4643 09:32:23.686368 DQS Delay:
4644 09:32:23.686497 DQS0 = 0, DQS1 = 0
4645 09:32:23.686587 DQM Delay:
4646 09:32:23.689885 DQM0 = 41, DQM1 = 32
4647 09:32:23.689971 DQ Delay:
4648 09:32:23.693680 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4649 09:32:23.696334 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4650 09:32:23.699711 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4651 09:32:23.703430 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4652 09:32:23.703572
4653 09:32:23.703693
4654 09:32:23.713645 [DQSOSCAuto] RK0, (LSB)MR18= 0x450b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4655 09:32:23.713876 CH1 RK0: MR19=808, MR18=450B
4656 09:32:23.720224 CH1_RK0: MR19=0x808, MR18=0x450B, DQSOSC=396, MR23=63, INC=167, DEC=111
4657 09:32:23.720690
4658 09:32:23.723464 ----->DramcWriteLeveling(PI) begin...
4659 09:32:23.723895 ==
4660 09:32:23.726930 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 09:32:23.733866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 09:32:23.734291 ==
4663 09:32:23.737631 Write leveling (Byte 0): 32 => 32
4664 09:32:23.740512 Write leveling (Byte 1): 29 => 29
4665 09:32:23.741031 DramcWriteLeveling(PI) end<-----
4666 09:32:23.741392
4667 09:32:23.744119 ==
4668 09:32:23.747138 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 09:32:23.750895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 09:32:23.751457 ==
4671 09:32:23.753725 [Gating] SW mode calibration
4672 09:32:23.760114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 09:32:23.763400 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 09:32:23.770816 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4675 09:32:23.773803 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 09:32:23.777206 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 1) (1 0)
4677 09:32:23.783869 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
4678 09:32:23.787331 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4679 09:32:23.790890 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4680 09:32:23.797073 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 09:32:23.800401 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 09:32:23.804125 0 10 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
4683 09:32:23.807298 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 09:32:23.813641 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4685 09:32:23.817275 0 10 12 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
4686 09:32:23.820290 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 09:32:23.827065 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 09:32:23.830247 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 09:32:23.833889 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 09:32:23.840875 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 09:32:23.844190 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 09:32:23.847113 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 09:32:23.854302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4694 09:32:23.857487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 09:32:23.860797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 09:32:23.867805 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 09:32:23.871498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 09:32:23.874192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 09:32:23.877838 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 09:32:23.884340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 09:32:23.887388 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 09:32:23.890981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 09:32:23.897647 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 09:32:23.900594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 09:32:23.904787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 09:32:23.911337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 09:32:23.914207 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 09:32:23.917520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4709 09:32:23.924336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4710 09:32:23.927555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 09:32:23.930963 Total UI for P1: 0, mck2ui 16
4712 09:32:23.934942 best dqsien dly found for B0: ( 0, 13, 10)
4713 09:32:23.937576 Total UI for P1: 0, mck2ui 16
4714 09:32:23.940718 best dqsien dly found for B1: ( 0, 13, 14)
4715 09:32:23.944839 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4716 09:32:23.947496 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4717 09:32:23.948009
4718 09:32:23.951048 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4719 09:32:23.954246 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4720 09:32:23.957910 [Gating] SW calibration Done
4721 09:32:23.958556 ==
4722 09:32:23.961109 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 09:32:23.964382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 09:32:23.964851 ==
4725 09:32:23.967600 RX Vref Scan: 0
4726 09:32:23.968063
4727 09:32:23.971080 RX Vref 0 -> 0, step: 1
4728 09:32:23.971546
4729 09:32:23.971911 RX Delay -230 -> 252, step: 16
4730 09:32:23.978098 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4731 09:32:23.980881 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4732 09:32:23.984914 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4733 09:32:23.987593 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4734 09:32:23.994817 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4735 09:32:23.997901 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4736 09:32:24.000997 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4737 09:32:24.004006 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4738 09:32:24.007653 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4739 09:32:24.014506 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4740 09:32:24.018073 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4741 09:32:24.021519 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4742 09:32:24.024414 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4743 09:32:24.031087 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4744 09:32:24.034492 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4745 09:32:24.037704 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4746 09:32:24.038286 ==
4747 09:32:24.041086 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 09:32:24.044429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 09:32:24.044894 ==
4750 09:32:24.047588 DQS Delay:
4751 09:32:24.048050 DQS0 = 0, DQS1 = 0
4752 09:32:24.051113 DQM Delay:
4753 09:32:24.051573 DQM0 = 38, DQM1 = 34
4754 09:32:24.051939 DQ Delay:
4755 09:32:24.054206 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4756 09:32:24.057780 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4757 09:32:24.060919 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4758 09:32:24.064325 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4759 09:32:24.064789
4760 09:32:24.065152
4761 09:32:24.068039 ==
4762 09:32:24.068503 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 09:32:24.074363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 09:32:24.074953 ==
4765 09:32:24.075328
4766 09:32:24.075665
4767 09:32:24.077800 TX Vref Scan disable
4768 09:32:24.078261 == TX Byte 0 ==
4769 09:32:24.081221 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4770 09:32:24.088290 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4771 09:32:24.088851 == TX Byte 1 ==
4772 09:32:24.091344 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4773 09:32:24.097811 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4774 09:32:24.098450 ==
4775 09:32:24.101230 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 09:32:24.104311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 09:32:24.104778 ==
4778 09:32:24.105143
4779 09:32:24.105613
4780 09:32:24.107983 TX Vref Scan disable
4781 09:32:24.111318 == TX Byte 0 ==
4782 09:32:24.114541 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4783 09:32:24.117688 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4784 09:32:24.120998 == TX Byte 1 ==
4785 09:32:24.124175 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4786 09:32:24.128033 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4787 09:32:24.128497
4788 09:32:24.130972 [DATLAT]
4789 09:32:24.131437 Freq=600, CH1 RK1
4790 09:32:24.131803
4791 09:32:24.134415 DATLAT Default: 0x9
4792 09:32:24.134878 0, 0xFFFF, sum = 0
4793 09:32:24.137771 1, 0xFFFF, sum = 0
4794 09:32:24.138387 2, 0xFFFF, sum = 0
4795 09:32:24.141298 3, 0xFFFF, sum = 0
4796 09:32:24.141721 4, 0xFFFF, sum = 0
4797 09:32:24.144424 5, 0xFFFF, sum = 0
4798 09:32:24.144849 6, 0xFFFF, sum = 0
4799 09:32:24.147731 7, 0xFFFF, sum = 0
4800 09:32:24.148036 8, 0x0, sum = 1
4801 09:32:24.150958 9, 0x0, sum = 2
4802 09:32:24.151262 10, 0x0, sum = 3
4803 09:32:24.154182 11, 0x0, sum = 4
4804 09:32:24.154412 best_step = 9
4805 09:32:24.154593
4806 09:32:24.154822 ==
4807 09:32:24.157641 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 09:32:24.161102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 09:32:24.161282 ==
4810 09:32:24.163906 RX Vref Scan: 0
4811 09:32:24.164057
4812 09:32:24.167481 RX Vref 0 -> 0, step: 1
4813 09:32:24.167612
4814 09:32:24.167714 RX Delay -195 -> 252, step: 8
4815 09:32:24.175317 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4816 09:32:24.178749 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4817 09:32:24.181963 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4818 09:32:24.185300 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4819 09:32:24.192216 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4820 09:32:24.195591 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4821 09:32:24.198846 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4822 09:32:24.202323 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4823 09:32:24.205692 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4824 09:32:24.211962 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4825 09:32:24.215411 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4826 09:32:24.218601 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4827 09:32:24.222173 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4828 09:32:24.228674 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4829 09:32:24.232059 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4830 09:32:24.235306 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4831 09:32:24.235389 ==
4832 09:32:24.238991 Dram Type= 6, Freq= 0, CH_1, rank 1
4833 09:32:24.242108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4834 09:32:24.245525 ==
4835 09:32:24.245942 DQS Delay:
4836 09:32:24.246273 DQS0 = 0, DQS1 = 0
4837 09:32:24.248995 DQM Delay:
4838 09:32:24.249413 DQM0 = 36, DQM1 = 32
4839 09:32:24.249742 DQ Delay:
4840 09:32:24.252296 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4841 09:32:24.255626 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4842 09:32:24.258825 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4843 09:32:24.262769 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4844 09:32:24.263445
4845 09:32:24.263792
4846 09:32:24.272689 [DQSOSCAuto] RK1, (LSB)MR18= 0x3745, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4847 09:32:24.275988 CH1 RK1: MR19=808, MR18=3745
4848 09:32:24.282104 CH1_RK1: MR19=0x808, MR18=0x3745, DQSOSC=396, MR23=63, INC=167, DEC=111
4849 09:32:24.282575 [RxdqsGatingPostProcess] freq 600
4850 09:32:24.288956 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4851 09:32:24.292344 Pre-setting of DQS Precalculation
4852 09:32:24.295729 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4853 09:32:24.305664 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4854 09:32:24.312573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4855 09:32:24.313133
4856 09:32:24.313502
4857 09:32:24.315568 [Calibration Summary] 1200 Mbps
4858 09:32:24.316030 CH 0, Rank 0
4859 09:32:24.319172 SW Impedance : PASS
4860 09:32:24.319728 DUTY Scan : NO K
4861 09:32:24.322174 ZQ Calibration : PASS
4862 09:32:24.325693 Jitter Meter : NO K
4863 09:32:24.326251 CBT Training : PASS
4864 09:32:24.328966 Write leveling : PASS
4865 09:32:24.332100 RX DQS gating : PASS
4866 09:32:24.332668 RX DQ/DQS(RDDQC) : PASS
4867 09:32:24.335437 TX DQ/DQS : PASS
4868 09:32:24.338583 RX DATLAT : PASS
4869 09:32:24.339217 RX DQ/DQS(Engine): PASS
4870 09:32:24.341990 TX OE : NO K
4871 09:32:24.342709 All Pass.
4872 09:32:24.343230
4873 09:32:24.345159 CH 0, Rank 1
4874 09:32:24.345819 SW Impedance : PASS
4875 09:32:24.348285 DUTY Scan : NO K
4876 09:32:24.351807 ZQ Calibration : PASS
4877 09:32:24.351888 Jitter Meter : NO K
4878 09:32:24.354999 CBT Training : PASS
4879 09:32:24.358085 Write leveling : PASS
4880 09:32:24.358167 RX DQS gating : PASS
4881 09:32:24.361674 RX DQ/DQS(RDDQC) : PASS
4882 09:32:24.361754 TX DQ/DQS : PASS
4883 09:32:24.365228 RX DATLAT : PASS
4884 09:32:24.368244 RX DQ/DQS(Engine): PASS
4885 09:32:24.368338 TX OE : NO K
4886 09:32:24.371325 All Pass.
4887 09:32:24.371405
4888 09:32:24.371469 CH 1, Rank 0
4889 09:32:24.375154 SW Impedance : PASS
4890 09:32:24.375235 DUTY Scan : NO K
4891 09:32:24.378582 ZQ Calibration : PASS
4892 09:32:24.381790 Jitter Meter : NO K
4893 09:32:24.381905 CBT Training : PASS
4894 09:32:24.385383 Write leveling : PASS
4895 09:32:24.388623 RX DQS gating : PASS
4896 09:32:24.388803 RX DQ/DQS(RDDQC) : PASS
4897 09:32:24.391766 TX DQ/DQS : PASS
4898 09:32:24.395554 RX DATLAT : PASS
4899 09:32:24.395744 RX DQ/DQS(Engine): PASS
4900 09:32:24.398926 TX OE : NO K
4901 09:32:24.399139 All Pass.
4902 09:32:24.399293
4903 09:32:24.402052 CH 1, Rank 1
4904 09:32:24.402209 SW Impedance : PASS
4905 09:32:24.405271 DUTY Scan : NO K
4906 09:32:24.405430 ZQ Calibration : PASS
4907 09:32:24.408672 Jitter Meter : NO K
4908 09:32:24.412408 CBT Training : PASS
4909 09:32:24.412667 Write leveling : PASS
4910 09:32:24.415447 RX DQS gating : PASS
4911 09:32:24.418824 RX DQ/DQS(RDDQC) : PASS
4912 09:32:24.419115 TX DQ/DQS : PASS
4913 09:32:24.422291 RX DATLAT : PASS
4914 09:32:24.425542 RX DQ/DQS(Engine): PASS
4915 09:32:24.425872 TX OE : NO K
4916 09:32:24.428885 All Pass.
4917 09:32:24.429185
4918 09:32:24.429422 DramC Write-DBI off
4919 09:32:24.432109 PER_BANK_REFRESH: Hybrid Mode
4920 09:32:24.432453 TX_TRACKING: ON
4921 09:32:24.442647 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4922 09:32:24.445795 [FAST_K] Save calibration result to emmc
4923 09:32:24.449136 dramc_set_vcore_voltage set vcore to 662500
4924 09:32:24.452038 Read voltage for 933, 3
4925 09:32:24.452500 Vio18 = 0
4926 09:32:24.455673 Vcore = 662500
4927 09:32:24.456135 Vdram = 0
4928 09:32:24.456504 Vddq = 0
4929 09:32:24.456845 Vmddr = 0
4930 09:32:24.462334 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4931 09:32:24.468776 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4932 09:32:24.469247 MEM_TYPE=3, freq_sel=17
4933 09:32:24.472014 sv_algorithm_assistance_LP4_1600
4934 09:32:24.475769 ============ PULL DRAM RESETB DOWN ============
4935 09:32:24.482273 ========== PULL DRAM RESETB DOWN end =========
4936 09:32:24.485992 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4937 09:32:24.489079 ===================================
4938 09:32:24.492549 LPDDR4 DRAM CONFIGURATION
4939 09:32:24.496008 ===================================
4940 09:32:24.496572 EX_ROW_EN[0] = 0x0
4941 09:32:24.498792 EX_ROW_EN[1] = 0x0
4942 09:32:24.499252 LP4Y_EN = 0x0
4943 09:32:24.501945 WORK_FSP = 0x0
4944 09:32:24.502405 WL = 0x3
4945 09:32:24.505654 RL = 0x3
4946 09:32:24.506110 BL = 0x2
4947 09:32:24.508864 RPST = 0x0
4948 09:32:24.509323 RD_PRE = 0x0
4949 09:32:24.512457 WR_PRE = 0x1
4950 09:32:24.512916 WR_PST = 0x0
4951 09:32:24.515837 DBI_WR = 0x0
4952 09:32:24.516295 DBI_RD = 0x0
4953 09:32:24.519180 OTF = 0x1
4954 09:32:24.522704 ===================================
4955 09:32:24.526015 ===================================
4956 09:32:24.526588 ANA top config
4957 09:32:24.528889 ===================================
4958 09:32:24.532285 DLL_ASYNC_EN = 0
4959 09:32:24.535526 ALL_SLAVE_EN = 1
4960 09:32:24.539118 NEW_RANK_MODE = 1
4961 09:32:24.539577 DLL_IDLE_MODE = 1
4962 09:32:24.542765 LP45_APHY_COMB_EN = 1
4963 09:32:24.546150 TX_ODT_DIS = 1
4964 09:32:24.549056 NEW_8X_MODE = 1
4965 09:32:24.552201 ===================================
4966 09:32:24.555717 ===================================
4967 09:32:24.559442 data_rate = 1866
4968 09:32:24.560007 CKR = 1
4969 09:32:24.562800 DQ_P2S_RATIO = 8
4970 09:32:24.565951 ===================================
4971 09:32:24.568930 CA_P2S_RATIO = 8
4972 09:32:24.572286 DQ_CA_OPEN = 0
4973 09:32:24.575870 DQ_SEMI_OPEN = 0
4974 09:32:24.579324 CA_SEMI_OPEN = 0
4975 09:32:24.579897 CA_FULL_RATE = 0
4976 09:32:24.582399 DQ_CKDIV4_EN = 1
4977 09:32:24.585953 CA_CKDIV4_EN = 1
4978 09:32:24.589450 CA_PREDIV_EN = 0
4979 09:32:24.592847 PH8_DLY = 0
4980 09:32:24.596124 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4981 09:32:24.596709 DQ_AAMCK_DIV = 4
4982 09:32:24.599051 CA_AAMCK_DIV = 4
4983 09:32:24.603199 CA_ADMCK_DIV = 4
4984 09:32:24.606097 DQ_TRACK_CA_EN = 0
4985 09:32:24.609178 CA_PICK = 933
4986 09:32:24.612780 CA_MCKIO = 933
4987 09:32:24.613340 MCKIO_SEMI = 0
4988 09:32:24.616012 PLL_FREQ = 3732
4989 09:32:24.619437 DQ_UI_PI_RATIO = 32
4990 09:32:24.622807 CA_UI_PI_RATIO = 0
4991 09:32:24.626170 ===================================
4992 09:32:24.629451 ===================================
4993 09:32:24.632721 memory_type:LPDDR4
4994 09:32:24.633189 GP_NUM : 10
4995 09:32:24.636068 SRAM_EN : 1
4996 09:32:24.636530 MD32_EN : 0
4997 09:32:24.639339 ===================================
4998 09:32:24.642680 [ANA_INIT] >>>>>>>>>>>>>>
4999 09:32:24.646040 <<<<<< [CONFIGURE PHASE]: ANA_TX
5000 09:32:24.649080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5001 09:32:24.652253 ===================================
5002 09:32:24.655601 data_rate = 1866,PCW = 0X8f00
5003 09:32:24.658955 ===================================
5004 09:32:24.662325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5005 09:32:24.669102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 09:32:24.672363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 09:32:24.678748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5008 09:32:24.682383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5009 09:32:24.685641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5010 09:32:24.685806 [ANA_INIT] flow start
5011 09:32:24.688823 [ANA_INIT] PLL >>>>>>>>
5012 09:32:24.692355 [ANA_INIT] PLL <<<<<<<<
5013 09:32:24.692655 [ANA_INIT] MIDPI >>>>>>>>
5014 09:32:24.695692 [ANA_INIT] MIDPI <<<<<<<<
5015 09:32:24.698988 [ANA_INIT] DLL >>>>>>>>
5016 09:32:24.699186 [ANA_INIT] flow end
5017 09:32:24.705620 ============ LP4 DIFF to SE enter ============
5018 09:32:24.709291 ============ LP4 DIFF to SE exit ============
5019 09:32:24.709601 [ANA_INIT] <<<<<<<<<<<<<
5020 09:32:24.712291 [Flow] Enable top DCM control >>>>>
5021 09:32:24.715715 [Flow] Enable top DCM control <<<<<
5022 09:32:24.719229 Enable DLL master slave shuffle
5023 09:32:24.725799 ==============================================================
5024 09:32:24.729063 Gating Mode config
5025 09:32:24.732885 ==============================================================
5026 09:32:24.736131 Config description:
5027 09:32:24.746159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5028 09:32:24.752851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5029 09:32:24.756474 SELPH_MODE 0: By rank 1: By Phase
5030 09:32:24.762484 ==============================================================
5031 09:32:24.765889 GAT_TRACK_EN = 1
5032 09:32:24.769307 RX_GATING_MODE = 2
5033 09:32:24.769720 RX_GATING_TRACK_MODE = 2
5034 09:32:24.772764 SELPH_MODE = 1
5035 09:32:24.775999 PICG_EARLY_EN = 1
5036 09:32:24.779171 VALID_LAT_VALUE = 1
5037 09:32:24.786213 ==============================================================
5038 09:32:24.789565 Enter into Gating configuration >>>>
5039 09:32:24.792438 Exit from Gating configuration <<<<
5040 09:32:24.795737 Enter into DVFS_PRE_config >>>>>
5041 09:32:24.806334 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5042 09:32:24.809556 Exit from DVFS_PRE_config <<<<<
5043 09:32:24.812962 Enter into PICG configuration >>>>
5044 09:32:24.816134 Exit from PICG configuration <<<<
5045 09:32:24.819549 [RX_INPUT] configuration >>>>>
5046 09:32:24.819965 [RX_INPUT] configuration <<<<<
5047 09:32:24.825990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5048 09:32:24.833239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5049 09:32:24.836477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 09:32:24.843383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 09:32:24.850012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 09:32:24.856708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 09:32:24.860041 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5054 09:32:24.863411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5055 09:32:24.870232 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5056 09:32:24.873595 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5057 09:32:24.876892 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5058 09:32:24.880075 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 09:32:24.883160 ===================================
5060 09:32:24.886641 LPDDR4 DRAM CONFIGURATION
5061 09:32:24.889803 ===================================
5062 09:32:24.893838 EX_ROW_EN[0] = 0x0
5063 09:32:24.894399 EX_ROW_EN[1] = 0x0
5064 09:32:24.896698 LP4Y_EN = 0x0
5065 09:32:24.897402 WORK_FSP = 0x0
5066 09:32:24.899720 WL = 0x3
5067 09:32:24.900179 RL = 0x3
5068 09:32:24.903363 BL = 0x2
5069 09:32:24.903951 RPST = 0x0
5070 09:32:24.906694 RD_PRE = 0x0
5071 09:32:24.907264 WR_PRE = 0x1
5072 09:32:24.910268 WR_PST = 0x0
5073 09:32:24.910757 DBI_WR = 0x0
5074 09:32:24.913278 DBI_RD = 0x0
5075 09:32:24.913909 OTF = 0x1
5076 09:32:24.916733 ===================================
5077 09:32:24.923549 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5078 09:32:24.926755 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5079 09:32:24.930108 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5080 09:32:24.933820 ===================================
5081 09:32:24.936939 LPDDR4 DRAM CONFIGURATION
5082 09:32:24.940254 ===================================
5083 09:32:24.940717 EX_ROW_EN[0] = 0x10
5084 09:32:24.943500 EX_ROW_EN[1] = 0x0
5085 09:32:24.947030 LP4Y_EN = 0x0
5086 09:32:24.947471 WORK_FSP = 0x0
5087 09:32:24.950331 WL = 0x3
5088 09:32:24.950797 RL = 0x3
5089 09:32:24.953832 BL = 0x2
5090 09:32:24.954250 RPST = 0x0
5091 09:32:24.957150 RD_PRE = 0x0
5092 09:32:24.957711 WR_PRE = 0x1
5093 09:32:24.960086 WR_PST = 0x0
5094 09:32:24.960506 DBI_WR = 0x0
5095 09:32:24.963333 DBI_RD = 0x0
5096 09:32:24.963752 OTF = 0x1
5097 09:32:24.967354 ===================================
5098 09:32:24.973771 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5099 09:32:24.977809 nWR fixed to 30
5100 09:32:24.981268 [ModeRegInit_LP4] CH0 RK0
5101 09:32:24.981784 [ModeRegInit_LP4] CH0 RK1
5102 09:32:24.984401 [ModeRegInit_LP4] CH1 RK0
5103 09:32:24.987782 [ModeRegInit_LP4] CH1 RK1
5104 09:32:24.988302 match AC timing 9
5105 09:32:24.994566 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5106 09:32:24.998101 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5107 09:32:25.001249 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5108 09:32:25.007919 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5109 09:32:25.011334 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5110 09:32:25.011858 ==
5111 09:32:25.014595 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 09:32:25.017407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 09:32:25.017888 ==
5114 09:32:25.024287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 09:32:25.030971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5116 09:32:25.033968 [CA 0] Center 38 (8~69) winsize 62
5117 09:32:25.037220 [CA 1] Center 38 (7~69) winsize 63
5118 09:32:25.040625 [CA 2] Center 35 (5~66) winsize 62
5119 09:32:25.044278 [CA 3] Center 35 (5~66) winsize 62
5120 09:32:25.047411 [CA 4] Center 34 (4~64) winsize 61
5121 09:32:25.050860 [CA 5] Center 34 (4~64) winsize 61
5122 09:32:25.051281
5123 09:32:25.054230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5124 09:32:25.054649
5125 09:32:25.057648 [CATrainingPosCal] consider 1 rank data
5126 09:32:25.060885 u2DelayCellTimex100 = 270/100 ps
5127 09:32:25.064171 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5128 09:32:25.067680 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5129 09:32:25.071045 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5130 09:32:25.073897 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5131 09:32:25.077332 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5132 09:32:25.080729 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5133 09:32:25.081149
5134 09:32:25.087265 CA PerBit enable=1, Macro0, CA PI delay=34
5135 09:32:25.087684
5136 09:32:25.088010 [CBTSetCACLKResult] CA Dly = 34
5137 09:32:25.090616 CS Dly: 6 (0~37)
5138 09:32:25.091064 ==
5139 09:32:25.094700 Dram Type= 6, Freq= 0, CH_0, rank 1
5140 09:32:25.098179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 09:32:25.098761 ==
5142 09:32:25.104769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5143 09:32:25.111245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5144 09:32:25.114661 [CA 0] Center 38 (7~69) winsize 63
5145 09:32:25.117486 [CA 1] Center 38 (7~69) winsize 63
5146 09:32:25.121425 [CA 2] Center 35 (5~66) winsize 62
5147 09:32:25.124434 [CA 3] Center 35 (4~66) winsize 63
5148 09:32:25.127390 [CA 4] Center 34 (3~65) winsize 63
5149 09:32:25.131407 [CA 5] Center 33 (3~64) winsize 62
5150 09:32:25.131928
5151 09:32:25.134261 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5152 09:32:25.134678
5153 09:32:25.137883 [CATrainingPosCal] consider 2 rank data
5154 09:32:25.141105 u2DelayCellTimex100 = 270/100 ps
5155 09:32:25.144086 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5156 09:32:25.148214 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5157 09:32:25.151145 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5158 09:32:25.154504 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5159 09:32:25.157925 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5160 09:32:25.160971 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5161 09:32:25.161391
5162 09:32:25.167541 CA PerBit enable=1, Macro0, CA PI delay=34
5163 09:32:25.167961
5164 09:32:25.168291 [CBTSetCACLKResult] CA Dly = 34
5165 09:32:25.170589 CS Dly: 7 (0~39)
5166 09:32:25.171128
5167 09:32:25.174220 ----->DramcWriteLeveling(PI) begin...
5168 09:32:25.174643 ==
5169 09:32:25.177674 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 09:32:25.180857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 09:32:25.181389 ==
5172 09:32:25.184406 Write leveling (Byte 0): 33 => 33
5173 09:32:25.187887 Write leveling (Byte 1): 28 => 28
5174 09:32:25.190997 DramcWriteLeveling(PI) end<-----
5175 09:32:25.191627
5176 09:32:25.192206 ==
5177 09:32:25.194176 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 09:32:25.197593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 09:32:25.201164 ==
5180 09:32:25.201700 [Gating] SW mode calibration
5181 09:32:25.207584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5182 09:32:25.213622 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5183 09:32:25.217130 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5184 09:32:25.223836 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5185 09:32:25.227129 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 09:32:25.230556 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 09:32:25.237482 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 09:32:25.241149 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 09:32:25.244504 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 09:32:25.251420 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5191 09:32:25.254389 0 15 0 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 1)
5192 09:32:25.257551 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5193 09:32:25.261321 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 09:32:25.267550 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 09:32:25.270857 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 09:32:25.274529 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 09:32:25.281561 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 09:32:25.284712 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 09:32:25.287883 1 0 0 | B1->B0 | 3232 3d3d | 1 0 | (0 0) (0 0)
5200 09:32:25.294787 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5201 09:32:25.297981 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 09:32:25.301064 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 09:32:25.307477 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 09:32:25.310928 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 09:32:25.314140 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 09:32:25.320828 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 09:32:25.324003 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5208 09:32:25.327835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5209 09:32:25.334408 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 09:32:25.338039 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 09:32:25.341012 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 09:32:25.344204 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 09:32:25.351465 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 09:32:25.354646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 09:32:25.358037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 09:32:25.364528 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 09:32:25.368149 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 09:32:25.371634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 09:32:25.377892 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 09:32:25.381174 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 09:32:25.384941 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 09:32:25.391144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5223 09:32:25.395019 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5224 09:32:25.398120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5225 09:32:25.401486 Total UI for P1: 0, mck2ui 16
5226 09:32:25.404692 best dqsien dly found for B1: ( 1, 2, 30)
5227 09:32:25.408099 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 09:32:25.411096 Total UI for P1: 0, mck2ui 16
5229 09:32:25.414682 best dqsien dly found for B0: ( 1, 3, 0)
5230 09:32:25.418466 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5231 09:32:25.424853 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5232 09:32:25.425402
5233 09:32:25.428190 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5234 09:32:25.431809 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5235 09:32:25.434489 [Gating] SW calibration Done
5236 09:32:25.435046 ==
5237 09:32:25.437865 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 09:32:25.441438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 09:32:25.442187 ==
5240 09:32:25.442759 RX Vref Scan: 0
5241 09:32:25.444432
5242 09:32:25.444986 RX Vref 0 -> 0, step: 1
5243 09:32:25.445488
5244 09:32:25.447703 RX Delay -80 -> 252, step: 8
5245 09:32:25.451115 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5246 09:32:25.454306 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5247 09:32:25.457509 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5248 09:32:25.464403 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5249 09:32:25.467634 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5250 09:32:25.471059 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5251 09:32:25.474508 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5252 09:32:25.478073 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5253 09:32:25.481258 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5254 09:32:25.487791 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5255 09:32:25.491237 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5256 09:32:25.494585 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5257 09:32:25.497732 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5258 09:32:25.501132 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5259 09:32:25.508520 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5260 09:32:25.511018 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5261 09:32:25.511443 ==
5262 09:32:25.514234 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 09:32:25.517709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 09:32:25.518015 ==
5265 09:32:25.518256 DQS Delay:
5266 09:32:25.521124 DQS0 = 0, DQS1 = 0
5267 09:32:25.521494 DQM Delay:
5268 09:32:25.524287 DQM0 = 97, DQM1 = 88
5269 09:32:25.524515 DQ Delay:
5270 09:32:25.527956 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5271 09:32:25.530917 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5272 09:32:25.534576 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5273 09:32:25.537691 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5274 09:32:25.537842
5275 09:32:25.537961
5276 09:32:25.538071 ==
5277 09:32:25.541180 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 09:32:25.544534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 09:32:25.544686 ==
5280 09:32:25.547991
5281 09:32:25.548141
5282 09:32:25.548258 TX Vref Scan disable
5283 09:32:25.551394 == TX Byte 0 ==
5284 09:32:25.554283 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5285 09:32:25.557979 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5286 09:32:25.561159 == TX Byte 1 ==
5287 09:32:25.564355 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5288 09:32:25.567618 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5289 09:32:25.567700 ==
5290 09:32:25.570941 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 09:32:25.577707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 09:32:25.577789 ==
5293 09:32:25.577853
5294 09:32:25.577912
5295 09:32:25.577969 TX Vref Scan disable
5296 09:32:25.581644 == TX Byte 0 ==
5297 09:32:25.585207 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5298 09:32:25.588377 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5299 09:32:25.591723 == TX Byte 1 ==
5300 09:32:25.595410 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5301 09:32:25.598366 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5302 09:32:25.601727
5303 09:32:25.601807 [DATLAT]
5304 09:32:25.601871 Freq=933, CH0 RK0
5305 09:32:25.601931
5306 09:32:25.605072 DATLAT Default: 0xd
5307 09:32:25.605154 0, 0xFFFF, sum = 0
5308 09:32:25.608566 1, 0xFFFF, sum = 0
5309 09:32:25.608649 2, 0xFFFF, sum = 0
5310 09:32:25.611825 3, 0xFFFF, sum = 0
5311 09:32:25.611907 4, 0xFFFF, sum = 0
5312 09:32:25.615694 5, 0xFFFF, sum = 0
5313 09:32:25.615776 6, 0xFFFF, sum = 0
5314 09:32:25.618682 7, 0xFFFF, sum = 0
5315 09:32:25.622139 8, 0xFFFF, sum = 0
5316 09:32:25.622223 9, 0xFFFF, sum = 0
5317 09:32:25.622288 10, 0x0, sum = 1
5318 09:32:25.625128 11, 0x0, sum = 2
5319 09:32:25.625212 12, 0x0, sum = 3
5320 09:32:25.628656 13, 0x0, sum = 4
5321 09:32:25.628738 best_step = 11
5322 09:32:25.628803
5323 09:32:25.628864 ==
5324 09:32:25.632119 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 09:32:25.638951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 09:32:25.639034 ==
5327 09:32:25.639098 RX Vref Scan: 1
5328 09:32:25.639158
5329 09:32:25.642066 RX Vref 0 -> 0, step: 1
5330 09:32:25.642147
5331 09:32:25.645534 RX Delay -61 -> 252, step: 4
5332 09:32:25.645616
5333 09:32:25.648811 Set Vref, RX VrefLevel [Byte0]: 54
5334 09:32:25.652055 [Byte1]: 52
5335 09:32:25.652137
5336 09:32:25.655488 Final RX Vref Byte 0 = 54 to rank0
5337 09:32:25.658991 Final RX Vref Byte 1 = 52 to rank0
5338 09:32:25.662026 Final RX Vref Byte 0 = 54 to rank1
5339 09:32:25.665182 Final RX Vref Byte 1 = 52 to rank1==
5340 09:32:25.668838 Dram Type= 6, Freq= 0, CH_0, rank 0
5341 09:32:25.672145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 09:32:25.672231 ==
5343 09:32:25.675532 DQS Delay:
5344 09:32:25.675613 DQS0 = 0, DQS1 = 0
5345 09:32:25.675677 DQM Delay:
5346 09:32:25.678888 DQM0 = 97, DQM1 = 88
5347 09:32:25.678969 DQ Delay:
5348 09:32:25.682215 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5349 09:32:25.685676 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5350 09:32:25.689087 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =80
5351 09:32:25.691934 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5352 09:32:25.692014
5353 09:32:25.692078
5354 09:32:25.702107 [DQSOSCAuto] RK0, (LSB)MR18= 0x1803, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5355 09:32:25.705349 CH0 RK0: MR19=505, MR18=1803
5356 09:32:25.709115 CH0_RK0: MR19=0x505, MR18=0x1803, DQSOSC=414, MR23=63, INC=63, DEC=42
5357 09:32:25.709209
5358 09:32:25.712343 ----->DramcWriteLeveling(PI) begin...
5359 09:32:25.712445 ==
5360 09:32:25.715721 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 09:32:25.722584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 09:32:25.722706 ==
5363 09:32:25.725943 Write leveling (Byte 0): 32 => 32
5364 09:32:25.729047 Write leveling (Byte 1): 32 => 32
5365 09:32:25.729190 DramcWriteLeveling(PI) end<-----
5366 09:32:25.729300
5367 09:32:25.732770 ==
5368 09:32:25.735867 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 09:32:25.739377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 09:32:25.739549 ==
5371 09:32:25.742648 [Gating] SW mode calibration
5372 09:32:25.749265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5373 09:32:25.752522 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5374 09:32:25.759332 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5375 09:32:25.762777 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5376 09:32:25.766158 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 09:32:25.772499 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 09:32:25.775951 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 09:32:25.779168 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 09:32:25.785768 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5381 09:32:25.789107 0 14 28 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
5382 09:32:25.792478 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5383 09:32:25.799282 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5384 09:32:25.802762 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 09:32:25.806310 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 09:32:25.812933 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 09:32:25.816158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 09:32:25.819576 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 09:32:25.822521 0 15 28 | B1->B0 | 2727 3a3a | 1 0 | (0 0) (0 0)
5390 09:32:25.829135 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5391 09:32:25.832638 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 09:32:25.836126 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 09:32:25.843181 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 09:32:25.845954 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 09:32:25.849557 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 09:32:25.855910 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 09:32:25.859363 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5398 09:32:25.862854 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 09:32:25.869365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5400 09:32:25.872711 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 09:32:25.875635 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 09:32:25.882473 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 09:32:25.885762 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 09:32:25.889280 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 09:32:25.895919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 09:32:25.899194 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 09:32:25.902811 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 09:32:25.909126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 09:32:25.912688 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 09:32:25.915912 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 09:32:25.919054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 09:32:25.926002 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 09:32:25.928989 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5414 09:32:25.932747 Total UI for P1: 0, mck2ui 16
5415 09:32:25.935772 best dqsien dly found for B0: ( 1, 2, 26)
5416 09:32:25.939393 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5417 09:32:25.946160 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 09:32:25.946246 Total UI for P1: 0, mck2ui 16
5419 09:32:25.952373 best dqsien dly found for B1: ( 1, 2, 30)
5420 09:32:25.955901 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5421 09:32:25.959309 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5422 09:32:25.959385
5423 09:32:25.962444 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5424 09:32:25.966077 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5425 09:32:25.969011 [Gating] SW calibration Done
5426 09:32:25.969092 ==
5427 09:32:25.972420 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 09:32:25.975977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 09:32:25.976058 ==
5430 09:32:25.979381 RX Vref Scan: 0
5431 09:32:25.979461
5432 09:32:25.979525 RX Vref 0 -> 0, step: 1
5433 09:32:25.979585
5434 09:32:25.982350 RX Delay -80 -> 252, step: 8
5435 09:32:25.986058 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5436 09:32:25.989207 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5437 09:32:25.996028 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5438 09:32:25.999396 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5439 09:32:26.002669 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5440 09:32:26.006374 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5441 09:32:26.009526 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5442 09:32:26.012771 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5443 09:32:26.019208 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5444 09:32:26.022910 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5445 09:32:26.026140 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5446 09:32:26.029597 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5447 09:32:26.033008 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5448 09:32:26.039451 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5449 09:32:26.042947 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5450 09:32:26.046276 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5451 09:32:26.046357 ==
5452 09:32:26.049494 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 09:32:26.052774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 09:32:26.052856 ==
5455 09:32:26.056106 DQS Delay:
5456 09:32:26.056187 DQS0 = 0, DQS1 = 0
5457 09:32:26.056251 DQM Delay:
5458 09:32:26.059852 DQM0 = 96, DQM1 = 86
5459 09:32:26.059932 DQ Delay:
5460 09:32:26.062941 DQ0 =99, DQ1 =95, DQ2 =91, DQ3 =91
5461 09:32:26.066348 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5462 09:32:26.069733 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =79
5463 09:32:26.072930 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5464 09:32:26.073017
5465 09:32:26.073085
5466 09:32:26.073148 ==
5467 09:32:26.076170 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 09:32:26.083147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 09:32:26.083324 ==
5470 09:32:26.083416
5471 09:32:26.083497
5472 09:32:26.083575 TX Vref Scan disable
5473 09:32:26.086376 == TX Byte 0 ==
5474 09:32:26.089593 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5475 09:32:26.096277 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5476 09:32:26.096492 == TX Byte 1 ==
5477 09:32:26.099779 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5478 09:32:26.106290 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5479 09:32:26.106500 ==
5480 09:32:26.110130 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 09:32:26.113701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 09:32:26.113985 ==
5483 09:32:26.114157
5484 09:32:26.114312
5485 09:32:26.116488 TX Vref Scan disable
5486 09:32:26.116691 == TX Byte 0 ==
5487 09:32:26.123169 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5488 09:32:26.126473 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5489 09:32:26.126808 == TX Byte 1 ==
5490 09:32:26.133236 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5491 09:32:26.136894 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5492 09:32:26.137433
5493 09:32:26.137976 [DATLAT]
5494 09:32:26.139912 Freq=933, CH0 RK1
5495 09:32:26.140378
5496 09:32:26.140738 DATLAT Default: 0xb
5497 09:32:26.143692 0, 0xFFFF, sum = 0
5498 09:32:26.144165 1, 0xFFFF, sum = 0
5499 09:32:26.146899 2, 0xFFFF, sum = 0
5500 09:32:26.147372 3, 0xFFFF, sum = 0
5501 09:32:26.149907 4, 0xFFFF, sum = 0
5502 09:32:26.150328 5, 0xFFFF, sum = 0
5503 09:32:26.153407 6, 0xFFFF, sum = 0
5504 09:32:26.153829 7, 0xFFFF, sum = 0
5505 09:32:26.156497 8, 0xFFFF, sum = 0
5506 09:32:26.156919 9, 0xFFFF, sum = 0
5507 09:32:26.159985 10, 0x0, sum = 1
5508 09:32:26.160407 11, 0x0, sum = 2
5509 09:32:26.163186 12, 0x0, sum = 3
5510 09:32:26.163610 13, 0x0, sum = 4
5511 09:32:26.166140 best_step = 11
5512 09:32:26.166246
5513 09:32:26.166323 ==
5514 09:32:26.169810 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 09:32:26.172992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 09:32:26.173074 ==
5517 09:32:26.176226 RX Vref Scan: 0
5518 09:32:26.176308
5519 09:32:26.176372 RX Vref 0 -> 0, step: 1
5520 09:32:26.176432
5521 09:32:26.179519 RX Delay -69 -> 252, step: 4
5522 09:32:26.186663 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5523 09:32:26.190127 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5524 09:32:26.193050 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5525 09:32:26.196866 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5526 09:32:26.200256 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5527 09:32:26.203258 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5528 09:32:26.210174 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5529 09:32:26.213446 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5530 09:32:26.216551 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5531 09:32:26.220017 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5532 09:32:26.223378 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5533 09:32:26.226694 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5534 09:32:26.233219 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5535 09:32:26.236786 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5536 09:32:26.239888 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5537 09:32:26.243334 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5538 09:32:26.243416 ==
5539 09:32:26.246984 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 09:32:26.250458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 09:32:26.253167 ==
5542 09:32:26.253247 DQS Delay:
5543 09:32:26.253311 DQS0 = 0, DQS1 = 0
5544 09:32:26.256945 DQM Delay:
5545 09:32:26.257026 DQM0 = 95, DQM1 = 87
5546 09:32:26.260166 DQ Delay:
5547 09:32:26.260246 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5548 09:32:26.263497 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104
5549 09:32:26.266982 DQ8 =80, DQ9 =80, DQ10 =86, DQ11 =78
5550 09:32:26.270294 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5551 09:32:26.270376
5552 09:32:26.273437
5553 09:32:26.280061 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5554 09:32:26.283850 CH0 RK1: MR19=505, MR18=1B08
5555 09:32:26.289989 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5556 09:32:26.290071 [RxdqsGatingPostProcess] freq 933
5557 09:32:26.296634 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 09:32:26.300396 best DQS0 dly(2T, 0.5T) = (0, 11)
5559 09:32:26.303726 best DQS1 dly(2T, 0.5T) = (0, 10)
5560 09:32:26.307039 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5561 09:32:26.310196 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5562 09:32:26.313783 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 09:32:26.316688 best DQS1 dly(2T, 0.5T) = (0, 10)
5564 09:32:26.320223 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 09:32:26.323522 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5566 09:32:26.326914 Pre-setting of DQS Precalculation
5567 09:32:26.330275 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 09:32:26.330358 ==
5569 09:32:26.333619 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 09:32:26.336845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 09:32:26.336927 ==
5572 09:32:26.343609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 09:32:26.350713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5574 09:32:26.353666 [CA 0] Center 37 (7~67) winsize 61
5575 09:32:26.357049 [CA 1] Center 36 (6~67) winsize 62
5576 09:32:26.360512 [CA 2] Center 34 (4~65) winsize 62
5577 09:32:26.363746 [CA 3] Center 33 (3~64) winsize 62
5578 09:32:26.367441 [CA 4] Center 34 (4~65) winsize 62
5579 09:32:26.370741 [CA 5] Center 33 (3~63) winsize 61
5580 09:32:26.370823
5581 09:32:26.373836 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5582 09:32:26.373918
5583 09:32:26.377303 [CATrainingPosCal] consider 1 rank data
5584 09:32:26.380417 u2DelayCellTimex100 = 270/100 ps
5585 09:32:26.384109 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5586 09:32:26.387321 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 09:32:26.390331 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5588 09:32:26.394184 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5589 09:32:26.397575 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5590 09:32:26.400313 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5591 09:32:26.400395
5592 09:32:26.407184 CA PerBit enable=1, Macro0, CA PI delay=33
5593 09:32:26.407266
5594 09:32:26.407330 [CBTSetCACLKResult] CA Dly = 33
5595 09:32:26.410663 CS Dly: 4 (0~35)
5596 09:32:26.410799 ==
5597 09:32:26.413825 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 09:32:26.417074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 09:32:26.417156 ==
5600 09:32:26.423867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 09:32:26.430644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 09:32:26.433885 [CA 0] Center 36 (6~67) winsize 62
5603 09:32:26.437504 [CA 1] Center 37 (7~67) winsize 61
5604 09:32:26.440850 [CA 2] Center 34 (3~65) winsize 63
5605 09:32:26.444059 [CA 3] Center 33 (3~64) winsize 62
5606 09:32:26.447394 [CA 4] Center 34 (3~65) winsize 63
5607 09:32:26.450668 [CA 5] Center 32 (2~63) winsize 62
5608 09:32:26.450802
5609 09:32:26.454403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 09:32:26.454485
5611 09:32:26.457543 [CATrainingPosCal] consider 2 rank data
5612 09:32:26.460841 u2DelayCellTimex100 = 270/100 ps
5613 09:32:26.464377 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5614 09:32:26.467913 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5615 09:32:26.470963 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5616 09:32:26.474272 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5617 09:32:26.477302 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5618 09:32:26.480677 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5619 09:32:26.480759
5620 09:32:26.484389 CA PerBit enable=1, Macro0, CA PI delay=33
5621 09:32:26.487652
5622 09:32:26.487759 [CBTSetCACLKResult] CA Dly = 33
5623 09:32:26.491057 CS Dly: 5 (0~38)
5624 09:32:26.491138
5625 09:32:26.494304 ----->DramcWriteLeveling(PI) begin...
5626 09:32:26.494387 ==
5627 09:32:26.497764 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 09:32:26.500729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 09:32:26.500811 ==
5630 09:32:26.504246 Write leveling (Byte 0): 26 => 26
5631 09:32:26.507519 Write leveling (Byte 1): 30 => 30
5632 09:32:26.511292 DramcWriteLeveling(PI) end<-----
5633 09:32:26.511373
5634 09:32:26.511437 ==
5635 09:32:26.514051 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 09:32:26.517629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 09:32:26.517710 ==
5638 09:32:26.521023 [Gating] SW mode calibration
5639 09:32:26.527561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 09:32:26.534560 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 09:32:26.538078 0 14 0 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
5642 09:32:26.540882 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 09:32:26.547432 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5644 09:32:26.550888 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 09:32:26.554374 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 09:32:26.560915 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 09:32:26.564146 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5648 09:32:26.567513 0 14 28 | B1->B0 | 3030 3333 | 0 1 | (0 1) (1 0)
5649 09:32:26.574152 0 15 0 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5650 09:32:26.577945 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 09:32:26.580908 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 09:32:26.588075 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 09:32:26.591380 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 09:32:26.594426 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 09:32:26.601066 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5656 09:32:26.604435 0 15 28 | B1->B0 | 2b2b 2828 | 0 1 | (0 0) (0 0)
5657 09:32:26.607817 1 0 0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5658 09:32:26.614310 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 09:32:26.617872 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 09:32:26.621176 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 09:32:26.627698 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 09:32:26.631013 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 09:32:26.634182 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 09:32:26.637901 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5665 09:32:26.644410 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5666 09:32:26.647658 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 09:32:26.650986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 09:32:26.657321 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 09:32:26.661065 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 09:32:26.664662 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 09:32:26.671273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 09:32:26.674090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 09:32:26.677433 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 09:32:26.684880 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 09:32:26.687564 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 09:32:26.690848 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 09:32:26.697853 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 09:32:26.701317 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 09:32:26.704227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5680 09:32:26.711135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5681 09:32:26.711229 Total UI for P1: 0, mck2ui 16
5682 09:32:26.714339 best dqsien dly found for B1: ( 1, 2, 26)
5683 09:32:26.721274 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 09:32:26.724704 Total UI for P1: 0, mck2ui 16
5685 09:32:26.728416 best dqsien dly found for B0: ( 1, 2, 26)
5686 09:32:26.731009 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5687 09:32:26.734582 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5688 09:32:26.734786
5689 09:32:26.737631 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5690 09:32:26.741969 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5691 09:32:26.744773 [Gating] SW calibration Done
5692 09:32:26.744971 ==
5693 09:32:26.748162 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 09:32:26.751361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 09:32:26.751603 ==
5696 09:32:26.754761 RX Vref Scan: 0
5697 09:32:26.755061
5698 09:32:26.755298 RX Vref 0 -> 0, step: 1
5699 09:32:26.755521
5700 09:32:26.758035 RX Delay -80 -> 252, step: 8
5701 09:32:26.761264 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5702 09:32:26.768366 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5703 09:32:26.771427 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5704 09:32:26.774312 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5705 09:32:26.777777 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5706 09:32:26.781313 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5707 09:32:26.784708 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5708 09:32:26.791458 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5709 09:32:26.794374 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5710 09:32:26.797693 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5711 09:32:26.801118 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5712 09:32:26.804498 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5713 09:32:26.811375 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5714 09:32:26.814438 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5715 09:32:26.817764 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5716 09:32:26.821289 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5717 09:32:26.821371 ==
5718 09:32:26.824625 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 09:32:26.827767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 09:32:26.827850 ==
5721 09:32:26.830979 DQS Delay:
5722 09:32:26.831061 DQS0 = 0, DQS1 = 0
5723 09:32:26.834731 DQM Delay:
5724 09:32:26.834844 DQM0 = 96, DQM1 = 88
5725 09:32:26.834908 DQ Delay:
5726 09:32:26.837728 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =99
5727 09:32:26.841185 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5728 09:32:26.844585 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5729 09:32:26.848036 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5730 09:32:26.848121
5731 09:32:26.848186
5732 09:32:26.848246 ==
5733 09:32:26.851599 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 09:32:26.858090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 09:32:26.858172 ==
5736 09:32:26.858236
5737 09:32:26.858295
5738 09:32:26.858352 TX Vref Scan disable
5739 09:32:26.861619 == TX Byte 0 ==
5740 09:32:26.865027 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5741 09:32:26.868591 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5742 09:32:26.872209 == TX Byte 1 ==
5743 09:32:26.875265 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5744 09:32:26.878640 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5745 09:32:26.882209 ==
5746 09:32:26.885477 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 09:32:26.888643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 09:32:26.888721 ==
5749 09:32:26.888785
5750 09:32:26.888844
5751 09:32:26.892377 TX Vref Scan disable
5752 09:32:26.892450 == TX Byte 0 ==
5753 09:32:26.898450 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5754 09:32:26.901923 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5755 09:32:26.902005 == TX Byte 1 ==
5756 09:32:26.908658 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5757 09:32:26.912138 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5758 09:32:26.912220
5759 09:32:26.912285 [DATLAT]
5760 09:32:26.915032 Freq=933, CH1 RK0
5761 09:32:26.915115
5762 09:32:26.915179 DATLAT Default: 0xd
5763 09:32:26.918923 0, 0xFFFF, sum = 0
5764 09:32:26.919006 1, 0xFFFF, sum = 0
5765 09:32:26.921958 2, 0xFFFF, sum = 0
5766 09:32:26.922041 3, 0xFFFF, sum = 0
5767 09:32:26.925101 4, 0xFFFF, sum = 0
5768 09:32:26.925185 5, 0xFFFF, sum = 0
5769 09:32:26.928297 6, 0xFFFF, sum = 0
5770 09:32:26.928407 7, 0xFFFF, sum = 0
5771 09:32:26.932474 8, 0xFFFF, sum = 0
5772 09:32:26.932558 9, 0xFFFF, sum = 0
5773 09:32:26.935218 10, 0x0, sum = 1
5774 09:32:26.935302 11, 0x0, sum = 2
5775 09:32:26.938613 12, 0x0, sum = 3
5776 09:32:26.938759 13, 0x0, sum = 4
5777 09:32:26.941775 best_step = 11
5778 09:32:26.941857
5779 09:32:26.941921 ==
5780 09:32:26.945558 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 09:32:26.948874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 09:32:26.948957 ==
5783 09:32:26.951889 RX Vref Scan: 1
5784 09:32:26.951971
5785 09:32:26.952035 RX Vref 0 -> 0, step: 1
5786 09:32:26.952096
5787 09:32:26.955095 RX Delay -61 -> 252, step: 4
5788 09:32:26.955177
5789 09:32:26.958443 Set Vref, RX VrefLevel [Byte0]: 57
5790 09:32:26.961863 [Byte1]: 49
5791 09:32:26.966126
5792 09:32:26.966209 Final RX Vref Byte 0 = 57 to rank0
5793 09:32:26.969356 Final RX Vref Byte 1 = 49 to rank0
5794 09:32:26.972441 Final RX Vref Byte 0 = 57 to rank1
5795 09:32:26.975484 Final RX Vref Byte 1 = 49 to rank1==
5796 09:32:26.978892 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 09:32:26.985572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 09:32:26.985655 ==
5799 09:32:26.985720 DQS Delay:
5800 09:32:26.985780 DQS0 = 0, DQS1 = 0
5801 09:32:26.989385 DQM Delay:
5802 09:32:26.989467 DQM0 = 97, DQM1 = 89
5803 09:32:26.992591 DQ Delay:
5804 09:32:26.995492 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5805 09:32:26.998761 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5806 09:32:27.002592 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =86
5807 09:32:27.005944 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =94
5808 09:32:27.006026
5809 09:32:27.006090
5810 09:32:27.012200 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5811 09:32:27.015688 CH1 RK0: MR19=504, MR18=13F0
5812 09:32:27.022333 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5813 09:32:27.022415
5814 09:32:27.025570 ----->DramcWriteLeveling(PI) begin...
5815 09:32:27.025653 ==
5816 09:32:27.029135 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 09:32:27.032675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 09:32:27.032758 ==
5819 09:32:27.035971 Write leveling (Byte 0): 25 => 25
5820 09:32:27.039502 Write leveling (Byte 1): 26 => 26
5821 09:32:27.042621 DramcWriteLeveling(PI) end<-----
5822 09:32:27.042733
5823 09:32:27.042832 ==
5824 09:32:27.046079 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 09:32:27.048963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 09:32:27.049045 ==
5827 09:32:27.052418 [Gating] SW mode calibration
5828 09:32:27.059343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 09:32:27.065875 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 09:32:27.070117 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5831 09:32:27.072684 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 09:32:27.079319 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5833 09:32:27.082437 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 09:32:27.086317 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 09:32:27.092424 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5836 09:32:27.096344 0 14 24 | B1->B0 | 3131 2c2c | 0 1 | (0 0) (1 0)
5837 09:32:27.099188 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5838 09:32:27.105765 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5839 09:32:27.109658 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 09:32:27.113362 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 09:32:27.116785 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 09:32:27.123182 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5843 09:32:27.126814 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 09:32:27.129779 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5845 09:32:27.136349 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5846 09:32:27.140356 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 09:32:27.143011 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 09:32:27.149970 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 09:32:27.153169 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 09:32:27.156378 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 09:32:27.162962 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 09:32:27.166562 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5853 09:32:27.170041 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5854 09:32:27.176327 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 09:32:27.180187 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 09:32:27.183172 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 09:32:27.189816 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 09:32:27.193070 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 09:32:27.196761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 09:32:27.203233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 09:32:27.206536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 09:32:27.210093 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 09:32:27.216526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 09:32:27.220211 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 09:32:27.223242 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 09:32:27.226759 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 09:32:27.233533 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 09:32:27.236856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5869 09:32:27.239647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5870 09:32:27.242985 Total UI for P1: 0, mck2ui 16
5871 09:32:27.246314 best dqsien dly found for B0: ( 1, 2, 24)
5872 09:32:27.253101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5873 09:32:27.257056 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 09:32:27.260003 Total UI for P1: 0, mck2ui 16
5875 09:32:27.262999 best dqsien dly found for B1: ( 1, 2, 30)
5876 09:32:27.266648 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5877 09:32:27.269931 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5878 09:32:27.270353
5879 09:32:27.273329 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5880 09:32:27.276692 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5881 09:32:27.280066 [Gating] SW calibration Done
5882 09:32:27.280489 ==
5883 09:32:27.282954 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 09:32:27.286342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 09:32:27.289802 ==
5886 09:32:27.290217 RX Vref Scan: 0
5887 09:32:27.290552
5888 09:32:27.293358 RX Vref 0 -> 0, step: 1
5889 09:32:27.293872
5890 09:32:27.296487 RX Delay -80 -> 252, step: 8
5891 09:32:27.299614 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5892 09:32:27.303174 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5893 09:32:27.306871 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5894 09:32:27.309573 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5895 09:32:27.313125 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5896 09:32:27.319590 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5897 09:32:27.322953 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5898 09:32:27.326397 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5899 09:32:27.329603 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5900 09:32:27.333029 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5901 09:32:27.336495 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5902 09:32:27.342881 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5903 09:32:27.346384 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5904 09:32:27.349698 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5905 09:32:27.352705 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5906 09:32:27.356435 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5907 09:32:27.356518 ==
5908 09:32:27.359312 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 09:32:27.363159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 09:32:27.365974 ==
5911 09:32:27.366056 DQS Delay:
5912 09:32:27.366120 DQS0 = 0, DQS1 = 0
5913 09:32:27.369845 DQM Delay:
5914 09:32:27.369927 DQM0 = 95, DQM1 = 89
5915 09:32:27.372927 DQ Delay:
5916 09:32:27.373013 DQ0 =95, DQ1 =95, DQ2 =83, DQ3 =95
5917 09:32:27.376270 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5918 09:32:27.379944 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5919 09:32:27.383144 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =99
5920 09:32:27.386146
5921 09:32:27.386227
5922 09:32:27.386291 ==
5923 09:32:27.389807 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 09:32:27.393194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 09:32:27.393276 ==
5926 09:32:27.393342
5927 09:32:27.393402
5928 09:32:27.396334 TX Vref Scan disable
5929 09:32:27.396416 == TX Byte 0 ==
5930 09:32:27.400124 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5931 09:32:27.406745 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5932 09:32:27.406842 == TX Byte 1 ==
5933 09:32:27.409699 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5934 09:32:27.416616 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5935 09:32:27.416698 ==
5936 09:32:27.420074 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 09:32:27.422961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 09:32:27.423043 ==
5939 09:32:27.423108
5940 09:32:27.423168
5941 09:32:27.426506 TX Vref Scan disable
5942 09:32:27.429795 == TX Byte 0 ==
5943 09:32:27.433074 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5944 09:32:27.436284 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5945 09:32:27.439860 == TX Byte 1 ==
5946 09:32:27.443174 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5947 09:32:27.446474 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5948 09:32:27.446555
5949 09:32:27.446620 [DATLAT]
5950 09:32:27.449984 Freq=933, CH1 RK1
5951 09:32:27.450067
5952 09:32:27.452958 DATLAT Default: 0xb
5953 09:32:27.453051 0, 0xFFFF, sum = 0
5954 09:32:27.456267 1, 0xFFFF, sum = 0
5955 09:32:27.456393 2, 0xFFFF, sum = 0
5956 09:32:27.459721 3, 0xFFFF, sum = 0
5957 09:32:27.459805 4, 0xFFFF, sum = 0
5958 09:32:27.462937 5, 0xFFFF, sum = 0
5959 09:32:27.463021 6, 0xFFFF, sum = 0
5960 09:32:27.466750 7, 0xFFFF, sum = 0
5961 09:32:27.466848 8, 0xFFFF, sum = 0
5962 09:32:27.469585 9, 0xFFFF, sum = 0
5963 09:32:27.469668 10, 0x0, sum = 1
5964 09:32:27.473274 11, 0x0, sum = 2
5965 09:32:27.473358 12, 0x0, sum = 3
5966 09:32:27.476624 13, 0x0, sum = 4
5967 09:32:27.476707 best_step = 11
5968 09:32:27.476771
5969 09:32:27.476831 ==
5970 09:32:27.480163 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 09:32:27.483178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 09:32:27.483282 ==
5973 09:32:27.486379 RX Vref Scan: 0
5974 09:32:27.486473
5975 09:32:27.489698 RX Vref 0 -> 0, step: 1
5976 09:32:27.489795
5977 09:32:27.489888 RX Delay -61 -> 252, step: 4
5978 09:32:27.497722 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5979 09:32:27.501547 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5980 09:32:27.504666 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5981 09:32:27.507405 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5982 09:32:27.510903 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5983 09:32:27.514291 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5984 09:32:27.521078 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5985 09:32:27.524595 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5986 09:32:27.527794 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5987 09:32:27.530985 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5988 09:32:27.534648 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5989 09:32:27.541121 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5990 09:32:27.544336 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5991 09:32:27.547700 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5992 09:32:27.550930 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5993 09:32:27.554116 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5994 09:32:27.554212 ==
5995 09:32:27.557731 Dram Type= 6, Freq= 0, CH_1, rank 1
5996 09:32:27.564509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5997 09:32:27.564611 ==
5998 09:32:27.564702 DQS Delay:
5999 09:32:27.564790 DQS0 = 0, DQS1 = 0
6000 09:32:27.567436 DQM Delay:
6001 09:32:27.567529 DQM0 = 95, DQM1 = 90
6002 09:32:27.571218 DQ Delay:
6003 09:32:27.574471 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
6004 09:32:27.574546 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =92
6005 09:32:27.577850 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =84
6006 09:32:27.584530 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
6007 09:32:27.584599
6008 09:32:27.584662
6009 09:32:27.591417 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6010 09:32:27.594240 CH1 RK1: MR19=505, MR18=E17
6011 09:32:27.601179 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
6012 09:32:27.601250 [RxdqsGatingPostProcess] freq 933
6013 09:32:27.607597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6014 09:32:27.610879 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 09:32:27.614282 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 09:32:27.617615 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 09:32:27.620993 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 09:32:27.624237 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 09:32:27.627756 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 09:32:27.631195 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 09:32:27.634386 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 09:32:27.637789 Pre-setting of DQS Precalculation
6023 09:32:27.641335 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6024 09:32:27.647612 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6025 09:32:27.654433 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6026 09:32:27.654533
6027 09:32:27.657632
6028 09:32:27.657701 [Calibration Summary] 1866 Mbps
6029 09:32:27.661005 CH 0, Rank 0
6030 09:32:27.661071 SW Impedance : PASS
6031 09:32:27.664385 DUTY Scan : NO K
6032 09:32:27.667728 ZQ Calibration : PASS
6033 09:32:27.667821 Jitter Meter : NO K
6034 09:32:27.671224 CBT Training : PASS
6035 09:32:27.674528 Write leveling : PASS
6036 09:32:27.674625 RX DQS gating : PASS
6037 09:32:27.677747 RX DQ/DQS(RDDQC) : PASS
6038 09:32:27.681568 TX DQ/DQS : PASS
6039 09:32:27.681651 RX DATLAT : PASS
6040 09:32:27.684622 RX DQ/DQS(Engine): PASS
6041 09:32:27.684704 TX OE : NO K
6042 09:32:27.688039 All Pass.
6043 09:32:27.688120
6044 09:32:27.688185 CH 0, Rank 1
6045 09:32:27.691063 SW Impedance : PASS
6046 09:32:27.691145 DUTY Scan : NO K
6047 09:32:27.694355 ZQ Calibration : PASS
6048 09:32:27.697870 Jitter Meter : NO K
6049 09:32:27.697953 CBT Training : PASS
6050 09:32:27.701680 Write leveling : PASS
6051 09:32:27.704298 RX DQS gating : PASS
6052 09:32:27.704379 RX DQ/DQS(RDDQC) : PASS
6053 09:32:27.707691 TX DQ/DQS : PASS
6054 09:32:27.711652 RX DATLAT : PASS
6055 09:32:27.711814 RX DQ/DQS(Engine): PASS
6056 09:32:27.714631 TX OE : NO K
6057 09:32:27.714819 All Pass.
6058 09:32:27.714909
6059 09:32:27.718124 CH 1, Rank 0
6060 09:32:27.718250 SW Impedance : PASS
6061 09:32:27.721707 DUTY Scan : NO K
6062 09:32:27.724937 ZQ Calibration : PASS
6063 09:32:27.725095 Jitter Meter : NO K
6064 09:32:27.728319 CBT Training : PASS
6065 09:32:27.728485 Write leveling : PASS
6066 09:32:27.731848 RX DQS gating : PASS
6067 09:32:27.734495 RX DQ/DQS(RDDQC) : PASS
6068 09:32:27.734682 TX DQ/DQS : PASS
6069 09:32:27.738004 RX DATLAT : PASS
6070 09:32:27.741364 RX DQ/DQS(Engine): PASS
6071 09:32:27.741503 TX OE : NO K
6072 09:32:27.744601 All Pass.
6073 09:32:27.744754
6074 09:32:27.744875 CH 1, Rank 1
6075 09:32:27.747848 SW Impedance : PASS
6076 09:32:27.748022 DUTY Scan : NO K
6077 09:32:27.751276 ZQ Calibration : PASS
6078 09:32:27.754701 Jitter Meter : NO K
6079 09:32:27.754927 CBT Training : PASS
6080 09:32:27.758177 Write leveling : PASS
6081 09:32:27.761656 RX DQS gating : PASS
6082 09:32:27.761898 RX DQ/DQS(RDDQC) : PASS
6083 09:32:27.764962 TX DQ/DQS : PASS
6084 09:32:27.768384 RX DATLAT : PASS
6085 09:32:27.768773 RX DQ/DQS(Engine): PASS
6086 09:32:27.771891 TX OE : NO K
6087 09:32:27.772293 All Pass.
6088 09:32:27.772642
6089 09:32:27.774850 DramC Write-DBI off
6090 09:32:27.778269 PER_BANK_REFRESH: Hybrid Mode
6091 09:32:27.778691 TX_TRACKING: ON
6092 09:32:27.788082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6093 09:32:27.791722 [FAST_K] Save calibration result to emmc
6094 09:32:27.794891 dramc_set_vcore_voltage set vcore to 650000
6095 09:32:27.795318 Read voltage for 400, 6
6096 09:32:27.797793 Vio18 = 0
6097 09:32:27.797874 Vcore = 650000
6098 09:32:27.797938 Vdram = 0
6099 09:32:27.801500 Vddq = 0
6100 09:32:27.801581 Vmddr = 0
6101 09:32:27.807930 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6102 09:32:27.811426 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6103 09:32:27.814670 MEM_TYPE=3, freq_sel=20
6104 09:32:27.818031 sv_algorithm_assistance_LP4_800
6105 09:32:27.821506 ============ PULL DRAM RESETB DOWN ============
6106 09:32:27.824952 ========== PULL DRAM RESETB DOWN end =========
6107 09:32:27.831113 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6108 09:32:27.834716 ===================================
6109 09:32:27.834821 LPDDR4 DRAM CONFIGURATION
6110 09:32:27.837880 ===================================
6111 09:32:27.841352 EX_ROW_EN[0] = 0x0
6112 09:32:27.841433 EX_ROW_EN[1] = 0x0
6113 09:32:27.844597 LP4Y_EN = 0x0
6114 09:32:27.844679 WORK_FSP = 0x0
6115 09:32:27.847981 WL = 0x2
6116 09:32:27.848063 RL = 0x2
6117 09:32:27.851575 BL = 0x2
6118 09:32:27.854659 RPST = 0x0
6119 09:32:27.854763 RD_PRE = 0x0
6120 09:32:27.857771 WR_PRE = 0x1
6121 09:32:27.857853 WR_PST = 0x0
6122 09:32:27.861104 DBI_WR = 0x0
6123 09:32:27.861193 DBI_RD = 0x0
6124 09:32:27.864752 OTF = 0x1
6125 09:32:27.867776 ===================================
6126 09:32:27.871560 ===================================
6127 09:32:27.871643 ANA top config
6128 09:32:27.874572 ===================================
6129 09:32:27.877963 DLL_ASYNC_EN = 0
6130 09:32:27.881442 ALL_SLAVE_EN = 1
6131 09:32:27.881524 NEW_RANK_MODE = 1
6132 09:32:27.884871 DLL_IDLE_MODE = 1
6133 09:32:27.887978 LP45_APHY_COMB_EN = 1
6134 09:32:27.891285 TX_ODT_DIS = 1
6135 09:32:27.891368 NEW_8X_MODE = 1
6136 09:32:27.895090 ===================================
6137 09:32:27.898078 ===================================
6138 09:32:27.901345 data_rate = 800
6139 09:32:27.905154 CKR = 1
6140 09:32:27.907914 DQ_P2S_RATIO = 4
6141 09:32:27.911589 ===================================
6142 09:32:27.915094 CA_P2S_RATIO = 4
6143 09:32:27.917801 DQ_CA_OPEN = 0
6144 09:32:27.917883 DQ_SEMI_OPEN = 1
6145 09:32:27.921648 CA_SEMI_OPEN = 1
6146 09:32:27.925096 CA_FULL_RATE = 0
6147 09:32:27.928207 DQ_CKDIV4_EN = 0
6148 09:32:27.931176 CA_CKDIV4_EN = 1
6149 09:32:27.931261 CA_PREDIV_EN = 0
6150 09:32:27.934579 PH8_DLY = 0
6151 09:32:27.938429 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6152 09:32:27.941354 DQ_AAMCK_DIV = 0
6153 09:32:27.945197 CA_AAMCK_DIV = 0
6154 09:32:27.948247 CA_ADMCK_DIV = 4
6155 09:32:27.948354 DQ_TRACK_CA_EN = 0
6156 09:32:27.951427 CA_PICK = 800
6157 09:32:27.954797 CA_MCKIO = 400
6158 09:32:27.958178 MCKIO_SEMI = 400
6159 09:32:27.961665 PLL_FREQ = 3016
6160 09:32:27.965311 DQ_UI_PI_RATIO = 32
6161 09:32:27.968660 CA_UI_PI_RATIO = 32
6162 09:32:27.972094 ===================================
6163 09:32:27.975238 ===================================
6164 09:32:27.975702 memory_type:LPDDR4
6165 09:32:27.978214 GP_NUM : 10
6166 09:32:27.981962 SRAM_EN : 1
6167 09:32:27.982394 MD32_EN : 0
6168 09:32:27.985281 ===================================
6169 09:32:27.988723 [ANA_INIT] >>>>>>>>>>>>>>
6170 09:32:27.991875 <<<<<< [CONFIGURE PHASE]: ANA_TX
6171 09:32:27.995037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6172 09:32:27.998617 ===================================
6173 09:32:28.001634 data_rate = 800,PCW = 0X7400
6174 09:32:28.005330 ===================================
6175 09:32:28.008583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6176 09:32:28.011762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 09:32:28.025299 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 09:32:28.028549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6179 09:32:28.031919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6180 09:32:28.035278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6181 09:32:28.038411 [ANA_INIT] flow start
6182 09:32:28.038868 [ANA_INIT] PLL >>>>>>>>
6183 09:32:28.042103 [ANA_INIT] PLL <<<<<<<<
6184 09:32:28.045222 [ANA_INIT] MIDPI >>>>>>>>
6185 09:32:28.048959 [ANA_INIT] MIDPI <<<<<<<<
6186 09:32:28.049495 [ANA_INIT] DLL >>>>>>>>
6187 09:32:28.051987 [ANA_INIT] flow end
6188 09:32:28.055462 ============ LP4 DIFF to SE enter ============
6189 09:32:28.058613 ============ LP4 DIFF to SE exit ============
6190 09:32:28.062003 [ANA_INIT] <<<<<<<<<<<<<
6191 09:32:28.064996 [Flow] Enable top DCM control >>>>>
6192 09:32:28.068723 [Flow] Enable top DCM control <<<<<
6193 09:32:28.071805 Enable DLL master slave shuffle
6194 09:32:28.075205 ==============================================================
6195 09:32:28.078714 Gating Mode config
6196 09:32:28.085216 ==============================================================
6197 09:32:28.085770 Config description:
6198 09:32:28.095323 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6199 09:32:28.101888 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6200 09:32:28.108537 SELPH_MODE 0: By rank 1: By Phase
6201 09:32:28.111752 ==============================================================
6202 09:32:28.115071 GAT_TRACK_EN = 0
6203 09:32:28.118443 RX_GATING_MODE = 2
6204 09:32:28.121852 RX_GATING_TRACK_MODE = 2
6205 09:32:28.125404 SELPH_MODE = 1
6206 09:32:28.128684 PICG_EARLY_EN = 1
6207 09:32:28.132272 VALID_LAT_VALUE = 1
6208 09:32:28.135348 ==============================================================
6209 09:32:28.138355 Enter into Gating configuration >>>>
6210 09:32:28.141789 Exit from Gating configuration <<<<
6211 09:32:28.144927 Enter into DVFS_PRE_config >>>>>
6212 09:32:28.158353 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6213 09:32:28.158926 Exit from DVFS_PRE_config <<<<<
6214 09:32:28.161598 Enter into PICG configuration >>>>
6215 09:32:28.165109 Exit from PICG configuration <<<<
6216 09:32:28.169016 [RX_INPUT] configuration >>>>>
6217 09:32:28.172053 [RX_INPUT] configuration <<<<<
6218 09:32:28.178468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6219 09:32:28.181895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6220 09:32:28.188805 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 09:32:28.195625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 09:32:28.202079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 09:32:28.208903 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 09:32:28.212094 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6225 09:32:28.215624 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6226 09:32:28.218814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6227 09:32:28.222335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6228 09:32:28.228532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6229 09:32:28.232368 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 09:32:28.235654 ===================================
6231 09:32:28.239205 LPDDR4 DRAM CONFIGURATION
6232 09:32:28.242449 ===================================
6233 09:32:28.242986 EX_ROW_EN[0] = 0x0
6234 09:32:28.245785 EX_ROW_EN[1] = 0x0
6235 09:32:28.246272 LP4Y_EN = 0x0
6236 09:32:28.249232 WORK_FSP = 0x0
6237 09:32:28.249649 WL = 0x2
6238 09:32:28.252654 RL = 0x2
6239 09:32:28.253137 BL = 0x2
6240 09:32:28.255864 RPST = 0x0
6241 09:32:28.256277 RD_PRE = 0x0
6242 09:32:28.258974 WR_PRE = 0x1
6243 09:32:28.259387 WR_PST = 0x0
6244 09:32:28.262386 DBI_WR = 0x0
6245 09:32:28.266292 DBI_RD = 0x0
6246 09:32:28.266861 OTF = 0x1
6247 09:32:28.269089 ===================================
6248 09:32:28.272295 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6249 09:32:28.275400 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6250 09:32:28.282337 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 09:32:28.285580 ===================================
6252 09:32:28.288839 LPDDR4 DRAM CONFIGURATION
6253 09:32:28.289405 ===================================
6254 09:32:28.292231 EX_ROW_EN[0] = 0x10
6255 09:32:28.295394 EX_ROW_EN[1] = 0x0
6256 09:32:28.295828 LP4Y_EN = 0x0
6257 09:32:28.298586 WORK_FSP = 0x0
6258 09:32:28.299086 WL = 0x2
6259 09:32:28.301998 RL = 0x2
6260 09:32:28.302512 BL = 0x2
6261 09:32:28.305774 RPST = 0x0
6262 09:32:28.306212 RD_PRE = 0x0
6263 09:32:28.308650 WR_PRE = 0x1
6264 09:32:28.309088 WR_PST = 0x0
6265 09:32:28.311971 DBI_WR = 0x0
6266 09:32:28.312419 DBI_RD = 0x0
6267 09:32:28.315486 OTF = 0x1
6268 09:32:28.318670 ===================================
6269 09:32:28.325272 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6270 09:32:28.328742 nWR fixed to 30
6271 09:32:28.332245 [ModeRegInit_LP4] CH0 RK0
6272 09:32:28.332682 [ModeRegInit_LP4] CH0 RK1
6273 09:32:28.335475 [ModeRegInit_LP4] CH1 RK0
6274 09:32:28.338889 [ModeRegInit_LP4] CH1 RK1
6275 09:32:28.339304 match AC timing 19
6276 09:32:28.345495 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6277 09:32:28.348964 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6278 09:32:28.352070 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6279 09:32:28.359003 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6280 09:32:28.362240 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6281 09:32:28.362688 ==
6282 09:32:28.365684 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 09:32:28.368960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 09:32:28.369408 ==
6285 09:32:28.375779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 09:32:28.382430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6287 09:32:28.382976 [CA 0] Center 36 (8~64) winsize 57
6288 09:32:28.385352 [CA 1] Center 36 (8~64) winsize 57
6289 09:32:28.388725 [CA 2] Center 36 (8~64) winsize 57
6290 09:32:28.392035 [CA 3] Center 36 (8~64) winsize 57
6291 09:32:28.395539 [CA 4] Center 36 (8~64) winsize 57
6292 09:32:28.398809 [CA 5] Center 36 (8~64) winsize 57
6293 09:32:28.399253
6294 09:32:28.402384 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6295 09:32:28.402851
6296 09:32:28.405485 [CATrainingPosCal] consider 1 rank data
6297 09:32:28.408901 u2DelayCellTimex100 = 270/100 ps
6298 09:32:28.412082 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:32:28.415881 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 09:32:28.422085 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 09:32:28.425583 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 09:32:28.429275 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 09:32:28.432223 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 09:32:28.432647
6305 09:32:28.435713 CA PerBit enable=1, Macro0, CA PI delay=36
6306 09:32:28.436137
6307 09:32:28.438833 [CBTSetCACLKResult] CA Dly = 36
6308 09:32:28.439261 CS Dly: 1 (0~32)
6309 09:32:28.439597 ==
6310 09:32:28.442357 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 09:32:28.449015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 09:32:28.449441 ==
6313 09:32:28.452900 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6314 09:32:28.459034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6315 09:32:28.462444 [CA 0] Center 36 (8~64) winsize 57
6316 09:32:28.465864 [CA 1] Center 36 (8~64) winsize 57
6317 09:32:28.469059 [CA 2] Center 36 (8~64) winsize 57
6318 09:32:28.472390 [CA 3] Center 36 (8~64) winsize 57
6319 09:32:28.475792 [CA 4] Center 36 (8~64) winsize 57
6320 09:32:28.479242 [CA 5] Center 36 (8~64) winsize 57
6321 09:32:28.479662
6322 09:32:28.482596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6323 09:32:28.483048
6324 09:32:28.486011 [CATrainingPosCal] consider 2 rank data
6325 09:32:28.489516 u2DelayCellTimex100 = 270/100 ps
6326 09:32:28.492626 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 09:32:28.495826 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 09:32:28.499365 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 09:32:28.502234 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 09:32:28.505770 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 09:32:28.508862 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 09:32:28.509286
6333 09:32:28.515782 CA PerBit enable=1, Macro0, CA PI delay=36
6334 09:32:28.516285
6335 09:32:28.516618 [CBTSetCACLKResult] CA Dly = 36
6336 09:32:28.518989 CS Dly: 1 (0~32)
6337 09:32:28.519439
6338 09:32:28.522313 ----->DramcWriteLeveling(PI) begin...
6339 09:32:28.522781 ==
6340 09:32:28.525714 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 09:32:28.529261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 09:32:28.529689 ==
6343 09:32:28.532394 Write leveling (Byte 0): 40 => 8
6344 09:32:28.535740 Write leveling (Byte 1): 32 => 0
6345 09:32:28.538853 DramcWriteLeveling(PI) end<-----
6346 09:32:28.539285
6347 09:32:28.539623 ==
6348 09:32:28.542391 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 09:32:28.545662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 09:32:28.546088 ==
6351 09:32:28.549142 [Gating] SW mode calibration
6352 09:32:28.555718 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6353 09:32:28.562518 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6354 09:32:28.566025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 09:32:28.573085 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 09:32:28.576240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 09:32:28.579675 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 09:32:28.586344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 09:32:28.589482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 09:32:28.592627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 09:32:28.595983 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 09:32:28.602589 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 09:32:28.605898 Total UI for P1: 0, mck2ui 16
6364 09:32:28.609112 best dqsien dly found for B0: ( 0, 14, 24)
6365 09:32:28.609194 Total UI for P1: 0, mck2ui 16
6366 09:32:28.615864 best dqsien dly found for B1: ( 0, 14, 24)
6367 09:32:28.618819 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6368 09:32:28.622432 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6369 09:32:28.622514
6370 09:32:28.625555 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 09:32:28.628853 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 09:32:28.632158 [Gating] SW calibration Done
6373 09:32:28.632270 ==
6374 09:32:28.635846 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 09:32:28.638983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 09:32:28.639071 ==
6377 09:32:28.642276 RX Vref Scan: 0
6378 09:32:28.642381
6379 09:32:28.642455 RX Vref 0 -> 0, step: 1
6380 09:32:28.642523
6381 09:32:28.645805 RX Delay -410 -> 252, step: 16
6382 09:32:28.653106 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6383 09:32:28.656068 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6384 09:32:28.659726 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6385 09:32:28.662864 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6386 09:32:28.669599 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6387 09:32:28.673123 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6388 09:32:28.676504 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6389 09:32:28.679163 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6390 09:32:28.682646 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6391 09:32:28.689539 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6392 09:32:28.692524 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6393 09:32:28.695831 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6394 09:32:28.702520 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6395 09:32:28.705963 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6396 09:32:28.709650 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6397 09:32:28.712475 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6398 09:32:28.712569 ==
6399 09:32:28.715975 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 09:32:28.723053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 09:32:28.723165 ==
6402 09:32:28.723252 DQS Delay:
6403 09:32:28.725952 DQS0 = 43, DQS1 = 51
6404 09:32:28.726148 DQM Delay:
6405 09:32:28.726252 DQM0 = 13, DQM1 = 10
6406 09:32:28.729216 DQ Delay:
6407 09:32:28.732641 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6408 09:32:28.735965 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6409 09:32:28.736060 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6410 09:32:28.739350 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6411 09:32:28.742641
6412 09:32:28.742747
6413 09:32:28.742829 ==
6414 09:32:28.745903 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 09:32:28.749527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 09:32:28.749615 ==
6417 09:32:28.749679
6418 09:32:28.749739
6419 09:32:28.752548 TX Vref Scan disable
6420 09:32:28.752630 == TX Byte 0 ==
6421 09:32:28.756115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 09:32:28.762586 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 09:32:28.762669 == TX Byte 1 ==
6424 09:32:28.766194 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6425 09:32:28.772693 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6426 09:32:28.772776 ==
6427 09:32:28.775918 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 09:32:28.779337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 09:32:28.779419 ==
6430 09:32:28.779484
6431 09:32:28.779543
6432 09:32:28.782994 TX Vref Scan disable
6433 09:32:28.783081 == TX Byte 0 ==
6434 09:32:28.786329 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 09:32:28.793204 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 09:32:28.793387 == TX Byte 1 ==
6437 09:32:28.796721 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6438 09:32:28.802537 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6439 09:32:28.802662
6440 09:32:28.802742 [DATLAT]
6441 09:32:28.802805 Freq=400, CH0 RK0
6442 09:32:28.806049
6443 09:32:28.806118 DATLAT Default: 0xf
6444 09:32:28.809454 0, 0xFFFF, sum = 0
6445 09:32:28.809559 1, 0xFFFF, sum = 0
6446 09:32:28.812577 2, 0xFFFF, sum = 0
6447 09:32:28.812659 3, 0xFFFF, sum = 0
6448 09:32:28.816385 4, 0xFFFF, sum = 0
6449 09:32:28.816482 5, 0xFFFF, sum = 0
6450 09:32:28.819869 6, 0xFFFF, sum = 0
6451 09:32:28.819951 7, 0xFFFF, sum = 0
6452 09:32:28.822898 8, 0xFFFF, sum = 0
6453 09:32:28.822980 9, 0xFFFF, sum = 0
6454 09:32:28.826383 10, 0xFFFF, sum = 0
6455 09:32:28.826464 11, 0xFFFF, sum = 0
6456 09:32:28.829562 12, 0xFFFF, sum = 0
6457 09:32:28.829643 13, 0x0, sum = 1
6458 09:32:28.833115 14, 0x0, sum = 2
6459 09:32:28.833196 15, 0x0, sum = 3
6460 09:32:28.836692 16, 0x0, sum = 4
6461 09:32:28.836780 best_step = 14
6462 09:32:28.836844
6463 09:32:28.836903 ==
6464 09:32:28.839724 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 09:32:28.842944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 09:32:28.846336 ==
6467 09:32:28.846417 RX Vref Scan: 1
6468 09:32:28.846480
6469 09:32:28.849486 RX Vref 0 -> 0, step: 1
6470 09:32:28.849566
6471 09:32:28.853088 RX Delay -343 -> 252, step: 8
6472 09:32:28.853174
6473 09:32:28.856333 Set Vref, RX VrefLevel [Byte0]: 54
6474 09:32:28.859824 [Byte1]: 52
6475 09:32:28.859917
6476 09:32:28.862879 Final RX Vref Byte 0 = 54 to rank0
6477 09:32:28.866285 Final RX Vref Byte 1 = 52 to rank0
6478 09:32:28.869323 Final RX Vref Byte 0 = 54 to rank1
6479 09:32:28.872679 Final RX Vref Byte 1 = 52 to rank1==
6480 09:32:28.876166 Dram Type= 6, Freq= 0, CH_0, rank 0
6481 09:32:28.879668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 09:32:28.879803 ==
6483 09:32:28.882726 DQS Delay:
6484 09:32:28.882840 DQS0 = 44, DQS1 = 60
6485 09:32:28.886474 DQM Delay:
6486 09:32:28.886555 DQM0 = 11, DQM1 = 16
6487 09:32:28.886619 DQ Delay:
6488 09:32:28.889322 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6489 09:32:28.892974 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6490 09:32:28.896344 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6491 09:32:28.899478 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =28
6492 09:32:28.899558
6493 09:32:28.899622
6494 09:32:28.909470 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6495 09:32:28.912449 CH0 RK0: MR19=C0C, MR18=8A57
6496 09:32:28.916248 CH0_RK0: MR19=0xC0C, MR18=0x8A57, DQSOSC=392, MR23=63, INC=384, DEC=256
6497 09:32:28.919515 ==
6498 09:32:28.919598 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 09:32:28.926681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 09:32:28.927149 ==
6501 09:32:28.929825 [Gating] SW mode calibration
6502 09:32:28.936638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6503 09:32:28.939978 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6504 09:32:28.946778 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 09:32:28.950140 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 09:32:28.953559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 09:32:28.959864 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 09:32:28.963216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 09:32:28.966533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 09:32:28.969909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 09:32:28.976611 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 09:32:28.979892 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 09:32:28.983277 Total UI for P1: 0, mck2ui 16
6514 09:32:28.986431 best dqsien dly found for B0: ( 0, 14, 24)
6515 09:32:28.989793 Total UI for P1: 0, mck2ui 16
6516 09:32:28.993162 best dqsien dly found for B1: ( 0, 14, 24)
6517 09:32:28.996726 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6518 09:32:28.999617 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6519 09:32:28.999705
6520 09:32:29.003069 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 09:32:29.006245 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 09:32:29.009934 [Gating] SW calibration Done
6523 09:32:29.010037 ==
6524 09:32:29.013189 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 09:32:29.019799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 09:32:29.019923 ==
6527 09:32:29.020020 RX Vref Scan: 0
6528 09:32:29.020111
6529 09:32:29.022931 RX Vref 0 -> 0, step: 1
6530 09:32:29.023013
6531 09:32:29.026342 RX Delay -410 -> 252, step: 16
6532 09:32:29.029537 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6533 09:32:29.033131 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6534 09:32:29.036595 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6535 09:32:29.043340 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6536 09:32:29.046288 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6537 09:32:29.049681 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6538 09:32:29.053303 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6539 09:32:29.059446 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6540 09:32:29.062893 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6541 09:32:29.066353 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6542 09:32:29.069653 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6543 09:32:29.076832 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6544 09:32:29.080149 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6545 09:32:29.083488 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6546 09:32:29.086853 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6547 09:32:29.093332 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6548 09:32:29.093757 ==
6549 09:32:29.096704 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 09:32:29.099867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 09:32:29.100294 ==
6552 09:32:29.100630 DQS Delay:
6553 09:32:29.103237 DQS0 = 43, DQS1 = 51
6554 09:32:29.103660 DQM Delay:
6555 09:32:29.106182 DQM0 = 11, DQM1 = 10
6556 09:32:29.106264 DQ Delay:
6557 09:32:29.109656 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6558 09:32:29.112855 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6559 09:32:29.116149 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6560 09:32:29.119387 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6561 09:32:29.119469
6562 09:32:29.119534
6563 09:32:29.119594 ==
6564 09:32:29.122689 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 09:32:29.125990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 09:32:29.126073 ==
6567 09:32:29.126138
6568 09:32:29.126198
6569 09:32:29.129775 TX Vref Scan disable
6570 09:32:29.133101 == TX Byte 0 ==
6571 09:32:29.136125 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6572 09:32:29.139817 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6573 09:32:29.139900 == TX Byte 1 ==
6574 09:32:29.146456 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6575 09:32:29.149772 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6576 09:32:29.149946 ==
6577 09:32:29.153227 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 09:32:29.156845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 09:32:29.157028 ==
6580 09:32:29.157140
6581 09:32:29.157231
6582 09:32:29.159753 TX Vref Scan disable
6583 09:32:29.163434 == TX Byte 0 ==
6584 09:32:29.166715 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6585 09:32:29.169416 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6586 09:32:29.169503 == TX Byte 1 ==
6587 09:32:29.176335 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6588 09:32:29.179691 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6589 09:32:29.179775
6590 09:32:29.179840 [DATLAT]
6591 09:32:29.182939 Freq=400, CH0 RK1
6592 09:32:29.183022
6593 09:32:29.183087 DATLAT Default: 0xe
6594 09:32:29.186384 0, 0xFFFF, sum = 0
6595 09:32:29.186468 1, 0xFFFF, sum = 0
6596 09:32:29.189795 2, 0xFFFF, sum = 0
6597 09:32:29.189879 3, 0xFFFF, sum = 0
6598 09:32:29.192951 4, 0xFFFF, sum = 0
6599 09:32:29.193034 5, 0xFFFF, sum = 0
6600 09:32:29.196439 6, 0xFFFF, sum = 0
6601 09:32:29.196523 7, 0xFFFF, sum = 0
6602 09:32:29.199586 8, 0xFFFF, sum = 0
6603 09:32:29.199669 9, 0xFFFF, sum = 0
6604 09:32:29.203113 10, 0xFFFF, sum = 0
6605 09:32:29.206444 11, 0xFFFF, sum = 0
6606 09:32:29.206528 12, 0xFFFF, sum = 0
6607 09:32:29.209862 13, 0x0, sum = 1
6608 09:32:29.209947 14, 0x0, sum = 2
6609 09:32:29.210013 15, 0x0, sum = 3
6610 09:32:29.213313 16, 0x0, sum = 4
6611 09:32:29.213402 best_step = 14
6612 09:32:29.213472
6613 09:32:29.216651 ==
6614 09:32:29.216739 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 09:32:29.223441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 09:32:29.223624 ==
6617 09:32:29.223717 RX Vref Scan: 0
6618 09:32:29.223799
6619 09:32:29.226829 RX Vref 0 -> 0, step: 1
6620 09:32:29.226993
6621 09:32:29.229649 RX Delay -343 -> 252, step: 8
6622 09:32:29.237031 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6623 09:32:29.240509 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6624 09:32:29.243406 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6625 09:32:29.246529 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6626 09:32:29.253282 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6627 09:32:29.256549 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6628 09:32:29.259840 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6629 09:32:29.263266 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6630 09:32:29.269790 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6631 09:32:29.272885 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6632 09:32:29.276867 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6633 09:32:29.279966 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6634 09:32:29.286370 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6635 09:32:29.289970 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6636 09:32:29.293430 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6637 09:32:29.299650 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6638 09:32:29.299753 ==
6639 09:32:29.303215 Dram Type= 6, Freq= 0, CH_0, rank 1
6640 09:32:29.306553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 09:32:29.306665 ==
6642 09:32:29.306773 DQS Delay:
6643 09:32:29.310071 DQS0 = 48, DQS1 = 60
6644 09:32:29.310193 DQM Delay:
6645 09:32:29.313318 DQM0 = 12, DQM1 = 13
6646 09:32:29.313454 DQ Delay:
6647 09:32:29.316569 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6648 09:32:29.319760 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6649 09:32:29.323254 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6650 09:32:29.326616 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6651 09:32:29.326699
6652 09:32:29.326823
6653 09:32:29.332823 [DQSOSCAuto] RK1, (LSB)MR18= 0x9769, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6654 09:32:29.336097 CH0 RK1: MR19=C0C, MR18=9769
6655 09:32:29.343291 CH0_RK1: MR19=0xC0C, MR18=0x9769, DQSOSC=390, MR23=63, INC=388, DEC=258
6656 09:32:29.346553 [RxdqsGatingPostProcess] freq 400
6657 09:32:29.349612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6658 09:32:29.353319 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 09:32:29.356783 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 09:32:29.359625 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 09:32:29.363407 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 09:32:29.366893 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 09:32:29.369851 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 09:32:29.373241 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 09:32:29.376991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 09:32:29.379792 Pre-setting of DQS Precalculation
6667 09:32:29.383566 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6668 09:32:29.383735 ==
6669 09:32:29.386680 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 09:32:29.393366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 09:32:29.393547 ==
6672 09:32:29.396637 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 09:32:29.403106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 09:32:29.406629 [CA 0] Center 36 (8~64) winsize 57
6675 09:32:29.409871 [CA 1] Center 36 (8~64) winsize 57
6676 09:32:29.413280 [CA 2] Center 36 (8~64) winsize 57
6677 09:32:29.416416 [CA 3] Center 36 (8~64) winsize 57
6678 09:32:29.419780 [CA 4] Center 36 (8~64) winsize 57
6679 09:32:29.423098 [CA 5] Center 36 (8~64) winsize 57
6680 09:32:29.423181
6681 09:32:29.426448 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 09:32:29.426530
6683 09:32:29.429951 [CATrainingPosCal] consider 1 rank data
6684 09:32:29.433042 u2DelayCellTimex100 = 270/100 ps
6685 09:32:29.436651 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:32:29.440015 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 09:32:29.443725 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 09:32:29.446900 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 09:32:29.449877 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 09:32:29.453368 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 09:32:29.453451
6692 09:32:29.459755 CA PerBit enable=1, Macro0, CA PI delay=36
6693 09:32:29.459837
6694 09:32:29.459902 [CBTSetCACLKResult] CA Dly = 36
6695 09:32:29.463060 CS Dly: 1 (0~32)
6696 09:32:29.463142 ==
6697 09:32:29.466531 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 09:32:29.469682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 09:32:29.469764 ==
6700 09:32:29.476336 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6701 09:32:29.483544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6702 09:32:29.486659 [CA 0] Center 36 (8~64) winsize 57
6703 09:32:29.489842 [CA 1] Center 36 (8~64) winsize 57
6704 09:32:29.493254 [CA 2] Center 36 (8~64) winsize 57
6705 09:32:29.496517 [CA 3] Center 36 (8~64) winsize 57
6706 09:32:29.496599 [CA 4] Center 36 (8~64) winsize 57
6707 09:32:29.499730 [CA 5] Center 36 (8~64) winsize 57
6708 09:32:29.499812
6709 09:32:29.506689 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6710 09:32:29.506794
6711 09:32:29.509594 [CATrainingPosCal] consider 2 rank data
6712 09:32:29.512981 u2DelayCellTimex100 = 270/100 ps
6713 09:32:29.516308 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 09:32:29.520157 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 09:32:29.522971 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 09:32:29.526267 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 09:32:29.529801 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 09:32:29.533637 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 09:32:29.534170
6720 09:32:29.536710 CA PerBit enable=1, Macro0, CA PI delay=36
6721 09:32:29.537330
6722 09:32:29.540481 [CBTSetCACLKResult] CA Dly = 36
6723 09:32:29.543371 CS Dly: 1 (0~32)
6724 09:32:29.543793
6725 09:32:29.546872 ----->DramcWriteLeveling(PI) begin...
6726 09:32:29.547311 ==
6727 09:32:29.550194 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 09:32:29.553681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 09:32:29.554155 ==
6730 09:32:29.556696 Write leveling (Byte 0): 40 => 8
6731 09:32:29.560247 Write leveling (Byte 1): 40 => 8
6732 09:32:29.563736 DramcWriteLeveling(PI) end<-----
6733 09:32:29.564226
6734 09:32:29.564563 ==
6735 09:32:29.567318 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 09:32:29.570596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 09:32:29.571088 ==
6738 09:32:29.574037 [Gating] SW mode calibration
6739 09:32:29.580804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6740 09:32:29.587203 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6741 09:32:29.590542 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6742 09:32:29.593621 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6743 09:32:29.597415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 09:32:29.603875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 09:32:29.607376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 09:32:29.610691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 09:32:29.617375 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 09:32:29.620317 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 09:32:29.623705 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 09:32:29.627166 Total UI for P1: 0, mck2ui 16
6751 09:32:29.630524 best dqsien dly found for B0: ( 0, 14, 24)
6752 09:32:29.633832 Total UI for P1: 0, mck2ui 16
6753 09:32:29.637423 best dqsien dly found for B1: ( 0, 14, 24)
6754 09:32:29.640710 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6755 09:32:29.644131 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6756 09:32:29.644556
6757 09:32:29.651085 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 09:32:29.653738 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 09:32:29.657318 [Gating] SW calibration Done
6760 09:32:29.657910 ==
6761 09:32:29.660596 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 09:32:29.663966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 09:32:29.664459 ==
6764 09:32:29.664794 RX Vref Scan: 0
6765 09:32:29.665122
6766 09:32:29.667201 RX Vref 0 -> 0, step: 1
6767 09:32:29.667792
6768 09:32:29.670689 RX Delay -410 -> 252, step: 16
6769 09:32:29.673770 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6770 09:32:29.680668 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6771 09:32:29.683723 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6772 09:32:29.686876 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6773 09:32:29.690607 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6774 09:32:29.694105 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6775 09:32:29.700356 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6776 09:32:29.704137 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6777 09:32:29.706981 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6778 09:32:29.710792 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6779 09:32:29.717427 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6780 09:32:29.720419 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6781 09:32:29.723895 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6782 09:32:29.730654 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6783 09:32:29.733748 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6784 09:32:29.737119 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6785 09:32:29.737539 ==
6786 09:32:29.740394 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 09:32:29.744059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 09:32:29.744482 ==
6789 09:32:29.747157 DQS Delay:
6790 09:32:29.747590 DQS0 = 51, DQS1 = 59
6791 09:32:29.750485 DQM Delay:
6792 09:32:29.751024 DQM0 = 19, DQM1 = 17
6793 09:32:29.753484 DQ Delay:
6794 09:32:29.753901 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6795 09:32:29.756898 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6796 09:32:29.760152 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6797 09:32:29.763748 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6798 09:32:29.764227
6799 09:32:29.764747
6800 09:32:29.767003 ==
6801 09:32:29.770608 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 09:32:29.773991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 09:32:29.774456 ==
6804 09:32:29.774954
6805 09:32:29.775270
6806 09:32:29.776927 TX Vref Scan disable
6807 09:32:29.777385 == TX Byte 0 ==
6808 09:32:29.780623 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 09:32:29.787282 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 09:32:29.787779 == TX Byte 1 ==
6811 09:32:29.790002 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 09:32:29.793481 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 09:32:29.796967 ==
6814 09:32:29.800355 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 09:32:29.803428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 09:32:29.803930 ==
6817 09:32:29.804386
6818 09:32:29.804882
6819 09:32:29.806756 TX Vref Scan disable
6820 09:32:29.807183 == TX Byte 0 ==
6821 09:32:29.810796 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 09:32:29.817044 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 09:32:29.817597 == TX Byte 1 ==
6824 09:32:29.820547 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 09:32:29.823821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 09:32:29.827098
6827 09:32:29.827517 [DATLAT]
6828 09:32:29.827881 Freq=400, CH1 RK0
6829 09:32:29.828200
6830 09:32:29.830564 DATLAT Default: 0xf
6831 09:32:29.831061 0, 0xFFFF, sum = 0
6832 09:32:29.833367 1, 0xFFFF, sum = 0
6833 09:32:29.833895 2, 0xFFFF, sum = 0
6834 09:32:29.837026 3, 0xFFFF, sum = 0
6835 09:32:29.840433 4, 0xFFFF, sum = 0
6836 09:32:29.840982 5, 0xFFFF, sum = 0
6837 09:32:29.843511 6, 0xFFFF, sum = 0
6838 09:32:29.843957 7, 0xFFFF, sum = 0
6839 09:32:29.846697 8, 0xFFFF, sum = 0
6840 09:32:29.847132 9, 0xFFFF, sum = 0
6841 09:32:29.850196 10, 0xFFFF, sum = 0
6842 09:32:29.850696 11, 0xFFFF, sum = 0
6843 09:32:29.853606 12, 0xFFFF, sum = 0
6844 09:32:29.854027 13, 0x0, sum = 1
6845 09:32:29.857252 14, 0x0, sum = 2
6846 09:32:29.857679 15, 0x0, sum = 3
6847 09:32:29.860539 16, 0x0, sum = 4
6848 09:32:29.861010 best_step = 14
6849 09:32:29.861376
6850 09:32:29.861798 ==
6851 09:32:29.863629 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 09:32:29.866952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 09:32:29.867611 ==
6854 09:32:29.870641 RX Vref Scan: 1
6855 09:32:29.871182
6856 09:32:29.873898 RX Vref 0 -> 0, step: 1
6857 09:32:29.874313
6858 09:32:29.874640 RX Delay -359 -> 252, step: 8
6859 09:32:29.875025
6860 09:32:29.877004 Set Vref, RX VrefLevel [Byte0]: 57
6861 09:32:29.880443 [Byte1]: 49
6862 09:32:29.885716
6863 09:32:29.886130 Final RX Vref Byte 0 = 57 to rank0
6864 09:32:29.888534 Final RX Vref Byte 1 = 49 to rank0
6865 09:32:29.892477 Final RX Vref Byte 0 = 57 to rank1
6866 09:32:29.895374 Final RX Vref Byte 1 = 49 to rank1==
6867 09:32:29.899007 Dram Type= 6, Freq= 0, CH_1, rank 0
6868 09:32:29.902419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 09:32:29.905313 ==
6870 09:32:29.905394 DQS Delay:
6871 09:32:29.905460 DQS0 = 48, DQS1 = 64
6872 09:32:29.908965 DQM Delay:
6873 09:32:29.909047 DQM0 = 12, DQM1 = 17
6874 09:32:29.912256 DQ Delay:
6875 09:32:29.912340 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6876 09:32:29.915589 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6877 09:32:29.918823 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6878 09:32:29.922243 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =24
6879 09:32:29.922346
6880 09:32:29.922419
6881 09:32:29.932717 [DQSOSCAuto] RK0, (LSB)MR18= 0x852d, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6882 09:32:29.935754 CH1 RK0: MR19=C0C, MR18=852D
6883 09:32:29.942278 CH1_RK0: MR19=0xC0C, MR18=0x852D, DQSOSC=393, MR23=63, INC=382, DEC=254
6884 09:32:29.942505 ==
6885 09:32:29.945744 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 09:32:29.948965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 09:32:29.949181 ==
6888 09:32:29.952260 [Gating] SW mode calibration
6889 09:32:29.959019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6890 09:32:29.962262 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6891 09:32:29.969093 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 09:32:29.972847 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6893 09:32:29.976067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 09:32:29.982682 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 09:32:29.986205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 09:32:29.989489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 09:32:29.995745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 09:32:29.999314 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 09:32:30.002609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 09:32:30.006074 Total UI for P1: 0, mck2ui 16
6901 09:32:30.009484 best dqsien dly found for B0: ( 0, 14, 24)
6902 09:32:30.012580 Total UI for P1: 0, mck2ui 16
6903 09:32:30.016055 best dqsien dly found for B1: ( 0, 14, 24)
6904 09:32:30.019399 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6905 09:32:30.022559 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6906 09:32:30.023121
6907 09:32:30.029426 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 09:32:30.032525 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 09:32:30.032950 [Gating] SW calibration Done
6910 09:32:30.033284 ==
6911 09:32:30.036032 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 09:32:30.042600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 09:32:30.043244 ==
6914 09:32:30.043829 RX Vref Scan: 0
6915 09:32:30.044340
6916 09:32:30.046272 RX Vref 0 -> 0, step: 1
6917 09:32:30.046895
6918 09:32:30.049916 RX Delay -410 -> 252, step: 16
6919 09:32:30.052650 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6920 09:32:30.056625 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6921 09:32:30.063109 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6922 09:32:30.066242 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6923 09:32:30.069392 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6924 09:32:30.072555 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6925 09:32:30.079398 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6926 09:32:30.082684 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6927 09:32:30.085552 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6928 09:32:30.089022 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6929 09:32:30.095426 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6930 09:32:30.098880 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6931 09:32:30.102246 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6932 09:32:30.105820 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6933 09:32:30.112407 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6934 09:32:30.115881 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6935 09:32:30.115966 ==
6936 09:32:30.119485 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 09:32:30.122636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 09:32:30.122742 ==
6939 09:32:30.126084 DQS Delay:
6940 09:32:30.126178 DQS0 = 43, DQS1 = 59
6941 09:32:30.126252 DQM Delay:
6942 09:32:30.129489 DQM0 = 9, DQM1 = 17
6943 09:32:30.129910 DQ Delay:
6944 09:32:30.132740 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6945 09:32:30.136199 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6946 09:32:30.139682 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6947 09:32:30.143034 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6948 09:32:30.143460
6949 09:32:30.143792
6950 09:32:30.144104 ==
6951 09:32:30.145908 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 09:32:30.149805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 09:32:30.150231 ==
6954 09:32:30.153441
6955 09:32:30.153967
6956 09:32:30.154305 TX Vref Scan disable
6957 09:32:30.156960 == TX Byte 0 ==
6958 09:32:30.159544 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6959 09:32:30.162838 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6960 09:32:30.166258 == TX Byte 1 ==
6961 09:32:30.169848 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 09:32:30.172762 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 09:32:30.173184 ==
6964 09:32:30.176043 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 09:32:30.179502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 09:32:30.179974 ==
6967 09:32:30.182859
6968 09:32:30.183441
6969 09:32:30.183812 TX Vref Scan disable
6970 09:32:30.185918 == TX Byte 0 ==
6971 09:32:30.189568 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6972 09:32:30.192947 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6973 09:32:30.196388 == TX Byte 1 ==
6974 09:32:30.199661 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6975 09:32:30.202857 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6976 09:32:30.203280
6977 09:32:30.203608 [DATLAT]
6978 09:32:30.206133 Freq=400, CH1 RK1
6979 09:32:30.206551
6980 09:32:30.206915 DATLAT Default: 0xe
6981 09:32:30.209486 0, 0xFFFF, sum = 0
6982 09:32:30.209913 1, 0xFFFF, sum = 0
6983 09:32:30.212867 2, 0xFFFF, sum = 0
6984 09:32:30.216030 3, 0xFFFF, sum = 0
6985 09:32:30.216460 4, 0xFFFF, sum = 0
6986 09:32:30.219645 5, 0xFFFF, sum = 0
6987 09:32:30.220076 6, 0xFFFF, sum = 0
6988 09:32:30.222967 7, 0xFFFF, sum = 0
6989 09:32:30.223411 8, 0xFFFF, sum = 0
6990 09:32:30.225858 9, 0xFFFF, sum = 0
6991 09:32:30.226333 10, 0xFFFF, sum = 0
6992 09:32:30.229215 11, 0xFFFF, sum = 0
6993 09:32:30.229647 12, 0xFFFF, sum = 0
6994 09:32:30.232881 13, 0x0, sum = 1
6995 09:32:30.233310 14, 0x0, sum = 2
6996 09:32:30.236090 15, 0x0, sum = 3
6997 09:32:30.236521 16, 0x0, sum = 4
6998 09:32:30.239342 best_step = 14
6999 09:32:30.239791
7000 09:32:30.240127 ==
7001 09:32:30.242939 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 09:32:30.246314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 09:32:30.246780 ==
7004 09:32:30.247147 RX Vref Scan: 0
7005 09:32:30.247467
7006 09:32:30.249724 RX Vref 0 -> 0, step: 1
7007 09:32:30.250105
7008 09:32:30.252801 RX Delay -359 -> 252, step: 8
7009 09:32:30.260396 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
7010 09:32:30.263849 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7011 09:32:30.267033 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
7012 09:32:30.270273 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7013 09:32:30.276726 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7014 09:32:30.280650 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7015 09:32:30.283799 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7016 09:32:30.286970 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7017 09:32:30.293149 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7018 09:32:30.296514 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7019 09:32:30.300028 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7020 09:32:30.303343 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7021 09:32:30.310102 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7022 09:32:30.313502 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7023 09:32:30.316820 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7024 09:32:30.320199 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7025 09:32:30.323342 ==
7026 09:32:30.326616 Dram Type= 6, Freq= 0, CH_1, rank 1
7027 09:32:30.329886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7028 09:32:30.329969 ==
7029 09:32:30.330034 DQS Delay:
7030 09:32:30.333428 DQS0 = 48, DQS1 = 60
7031 09:32:30.333509 DQM Delay:
7032 09:32:30.336827 DQM0 = 10, DQM1 = 13
7033 09:32:30.336908 DQ Delay:
7034 09:32:30.340101 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7035 09:32:30.342979 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7036 09:32:30.346288 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
7037 09:32:30.349796 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7038 09:32:30.349871
7039 09:32:30.349933
7040 09:32:30.356713 [DQSOSCAuto] RK1, (LSB)MR18= 0x7a90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
7041 09:32:30.359792 CH1 RK1: MR19=C0C, MR18=7A90
7042 09:32:30.366452 CH1_RK1: MR19=0xC0C, MR18=0x7A90, DQSOSC=391, MR23=63, INC=386, DEC=257
7043 09:32:30.369871 [RxdqsGatingPostProcess] freq 400
7044 09:32:30.373461 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7045 09:32:30.376548 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 09:32:30.379968 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 09:32:30.383463 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 09:32:30.386629 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 09:32:30.390066 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 09:32:30.393395 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 09:32:30.396660 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 09:32:30.399905 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 09:32:30.403228 Pre-setting of DQS Precalculation
7054 09:32:30.406443 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7055 09:32:30.413028 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7056 09:32:30.423338 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7057 09:32:30.423421
7058 09:32:30.423485
7059 09:32:30.427023 [Calibration Summary] 800 Mbps
7060 09:32:30.427104 CH 0, Rank 0
7061 09:32:30.430322 SW Impedance : PASS
7062 09:32:30.430404 DUTY Scan : NO K
7063 09:32:30.432907 ZQ Calibration : PASS
7064 09:32:30.436387 Jitter Meter : NO K
7065 09:32:30.436468 CBT Training : PASS
7066 09:32:30.439687 Write leveling : PASS
7067 09:32:30.439769 RX DQS gating : PASS
7068 09:32:30.443285 RX DQ/DQS(RDDQC) : PASS
7069 09:32:30.446564 TX DQ/DQS : PASS
7070 09:32:30.446646 RX DATLAT : PASS
7071 09:32:30.449899 RX DQ/DQS(Engine): PASS
7072 09:32:30.453394 TX OE : NO K
7073 09:32:30.453476 All Pass.
7074 09:32:30.453540
7075 09:32:30.453600 CH 0, Rank 1
7076 09:32:30.456636 SW Impedance : PASS
7077 09:32:30.460019 DUTY Scan : NO K
7078 09:32:30.460101 ZQ Calibration : PASS
7079 09:32:30.463372 Jitter Meter : NO K
7080 09:32:30.466490 CBT Training : PASS
7081 09:32:30.466573 Write leveling : NO K
7082 09:32:30.469880 RX DQS gating : PASS
7083 09:32:30.473300 RX DQ/DQS(RDDQC) : PASS
7084 09:32:30.473382 TX DQ/DQS : PASS
7085 09:32:30.476579 RX DATLAT : PASS
7086 09:32:30.476660 RX DQ/DQS(Engine): PASS
7087 09:32:30.480180 TX OE : NO K
7088 09:32:30.480281 All Pass.
7089 09:32:30.480360
7090 09:32:30.483392 CH 1, Rank 0
7091 09:32:30.483474 SW Impedance : PASS
7092 09:32:30.486670 DUTY Scan : NO K
7093 09:32:30.489634 ZQ Calibration : PASS
7094 09:32:30.489716 Jitter Meter : NO K
7095 09:32:30.493048 CBT Training : PASS
7096 09:32:30.496835 Write leveling : PASS
7097 09:32:30.496916 RX DQS gating : PASS
7098 09:32:30.500072 RX DQ/DQS(RDDQC) : PASS
7099 09:32:30.503322 TX DQ/DQS : PASS
7100 09:32:30.503403 RX DATLAT : PASS
7101 09:32:30.506891 RX DQ/DQS(Engine): PASS
7102 09:32:30.510095 TX OE : NO K
7103 09:32:30.510176 All Pass.
7104 09:32:30.510240
7105 09:32:30.510299 CH 1, Rank 1
7106 09:32:30.513382 SW Impedance : PASS
7107 09:32:30.516873 DUTY Scan : NO K
7108 09:32:30.516955 ZQ Calibration : PASS
7109 09:32:30.519782 Jitter Meter : NO K
7110 09:32:30.519864 CBT Training : PASS
7111 09:32:30.523514 Write leveling : NO K
7112 09:32:30.526805 RX DQS gating : PASS
7113 09:32:30.526887 RX DQ/DQS(RDDQC) : PASS
7114 09:32:30.530159 TX DQ/DQS : PASS
7115 09:32:30.533720 RX DATLAT : PASS
7116 09:32:30.533801 RX DQ/DQS(Engine): PASS
7117 09:32:30.536463 TX OE : NO K
7118 09:32:30.536544 All Pass.
7119 09:32:30.536608
7120 09:32:30.539921 DramC Write-DBI off
7121 09:32:30.543176 PER_BANK_REFRESH: Hybrid Mode
7122 09:32:30.543258 TX_TRACKING: ON
7123 09:32:30.553139 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7124 09:32:30.556581 [FAST_K] Save calibration result to emmc
7125 09:32:30.559868 dramc_set_vcore_voltage set vcore to 725000
7126 09:32:30.563164 Read voltage for 1600, 0
7127 09:32:30.563246 Vio18 = 0
7128 09:32:30.563310 Vcore = 725000
7129 09:32:30.566534 Vdram = 0
7130 09:32:30.566615 Vddq = 0
7131 09:32:30.566679 Vmddr = 0
7132 09:32:30.573399 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7133 09:32:30.576796 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7134 09:32:30.579980 MEM_TYPE=3, freq_sel=13
7135 09:32:30.583200 sv_algorithm_assistance_LP4_3733
7136 09:32:30.586632 ============ PULL DRAM RESETB DOWN ============
7137 09:32:30.589945 ========== PULL DRAM RESETB DOWN end =========
7138 09:32:30.596936 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7139 09:32:30.599956 ===================================
7140 09:32:30.600037 LPDDR4 DRAM CONFIGURATION
7141 09:32:30.603244 ===================================
7142 09:32:30.606627 EX_ROW_EN[0] = 0x0
7143 09:32:30.609931 EX_ROW_EN[1] = 0x0
7144 09:32:30.610012 LP4Y_EN = 0x0
7145 09:32:30.613636 WORK_FSP = 0x1
7146 09:32:30.613718 WL = 0x5
7147 09:32:30.616992 RL = 0x5
7148 09:32:30.617073 BL = 0x2
7149 09:32:30.619973 RPST = 0x0
7150 09:32:30.620053 RD_PRE = 0x0
7151 09:32:30.623391 WR_PRE = 0x1
7152 09:32:30.623472 WR_PST = 0x1
7153 09:32:30.626523 DBI_WR = 0x0
7154 09:32:30.626604 DBI_RD = 0x0
7155 09:32:30.630273 OTF = 0x1
7156 09:32:30.633038 ===================================
7157 09:32:30.636675 ===================================
7158 09:32:30.636756 ANA top config
7159 09:32:30.640311 ===================================
7160 09:32:30.643379 DLL_ASYNC_EN = 0
7161 09:32:30.646755 ALL_SLAVE_EN = 0
7162 09:32:30.650156 NEW_RANK_MODE = 1
7163 09:32:30.650238 DLL_IDLE_MODE = 1
7164 09:32:30.653468 LP45_APHY_COMB_EN = 1
7165 09:32:30.656323 TX_ODT_DIS = 0
7166 09:32:30.660206 NEW_8X_MODE = 1
7167 09:32:30.663023 ===================================
7168 09:32:30.666511 ===================================
7169 09:32:30.669973 data_rate = 3200
7170 09:32:30.670054 CKR = 1
7171 09:32:30.673378 DQ_P2S_RATIO = 8
7172 09:32:30.676689 ===================================
7173 09:32:30.679852 CA_P2S_RATIO = 8
7174 09:32:30.683138 DQ_CA_OPEN = 0
7175 09:32:30.686739 DQ_SEMI_OPEN = 0
7176 09:32:30.686822 CA_SEMI_OPEN = 0
7177 09:32:30.689968 CA_FULL_RATE = 0
7178 09:32:30.693599 DQ_CKDIV4_EN = 0
7179 09:32:30.696622 CA_CKDIV4_EN = 0
7180 09:32:30.699902 CA_PREDIV_EN = 0
7181 09:32:30.703875 PH8_DLY = 12
7182 09:32:30.703957 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7183 09:32:30.707088 DQ_AAMCK_DIV = 4
7184 09:32:30.709845 CA_AAMCK_DIV = 4
7185 09:32:30.713448 CA_ADMCK_DIV = 4
7186 09:32:30.716647 DQ_TRACK_CA_EN = 0
7187 09:32:30.720144 CA_PICK = 1600
7188 09:32:30.723328 CA_MCKIO = 1600
7189 09:32:30.723411 MCKIO_SEMI = 0
7190 09:32:30.726584 PLL_FREQ = 3068
7191 09:32:30.730195 DQ_UI_PI_RATIO = 32
7192 09:32:30.733549 CA_UI_PI_RATIO = 0
7193 09:32:30.736900 ===================================
7194 09:32:30.740346 ===================================
7195 09:32:30.743264 memory_type:LPDDR4
7196 09:32:30.743346 GP_NUM : 10
7197 09:32:30.746933 SRAM_EN : 1
7198 09:32:30.747015 MD32_EN : 0
7199 09:32:30.750483 ===================================
7200 09:32:30.753293 [ANA_INIT] >>>>>>>>>>>>>>
7201 09:32:30.756691 <<<<<< [CONFIGURE PHASE]: ANA_TX
7202 09:32:30.760070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7203 09:32:30.763504 ===================================
7204 09:32:30.766757 data_rate = 3200,PCW = 0X7600
7205 09:32:30.770134 ===================================
7206 09:32:30.773680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7207 09:32:30.780206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 09:32:30.783783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 09:32:30.789829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7210 09:32:30.793527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7211 09:32:30.796794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7212 09:32:30.796876 [ANA_INIT] flow start
7213 09:32:30.800102 [ANA_INIT] PLL >>>>>>>>
7214 09:32:30.803398 [ANA_INIT] PLL <<<<<<<<
7215 09:32:30.803479 [ANA_INIT] MIDPI >>>>>>>>
7216 09:32:30.806712 [ANA_INIT] MIDPI <<<<<<<<
7217 09:32:30.809836 [ANA_INIT] DLL >>>>>>>>
7218 09:32:30.809918 [ANA_INIT] DLL <<<<<<<<
7219 09:32:30.813164 [ANA_INIT] flow end
7220 09:32:30.816543 ============ LP4 DIFF to SE enter ============
7221 09:32:30.820009 ============ LP4 DIFF to SE exit ============
7222 09:32:30.823349 [ANA_INIT] <<<<<<<<<<<<<
7223 09:32:30.827044 [Flow] Enable top DCM control >>>>>
7224 09:32:30.830085 [Flow] Enable top DCM control <<<<<
7225 09:32:30.833555 Enable DLL master slave shuffle
7226 09:32:30.840151 ==============================================================
7227 09:32:30.840235 Gating Mode config
7228 09:32:30.846798 ==============================================================
7229 09:32:30.846882 Config description:
7230 09:32:30.856933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7231 09:32:30.863671 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7232 09:32:30.870281 SELPH_MODE 0: By rank 1: By Phase
7233 09:32:30.873380 ==============================================================
7234 09:32:30.876629 GAT_TRACK_EN = 1
7235 09:32:30.879951 RX_GATING_MODE = 2
7236 09:32:30.883257 RX_GATING_TRACK_MODE = 2
7237 09:32:30.887192 SELPH_MODE = 1
7238 09:32:30.890377 PICG_EARLY_EN = 1
7239 09:32:30.893637 VALID_LAT_VALUE = 1
7240 09:32:30.896765 ==============================================================
7241 09:32:30.899888 Enter into Gating configuration >>>>
7242 09:32:30.903743 Exit from Gating configuration <<<<
7243 09:32:30.907202 Enter into DVFS_PRE_config >>>>>
7244 09:32:30.920218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7245 09:32:30.923677 Exit from DVFS_PRE_config <<<<<
7246 09:32:30.926504 Enter into PICG configuration >>>>
7247 09:32:30.929969 Exit from PICG configuration <<<<
7248 09:32:30.930051 [RX_INPUT] configuration >>>>>
7249 09:32:30.933449 [RX_INPUT] configuration <<<<<
7250 09:32:30.940735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7251 09:32:30.943460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7252 09:32:30.950208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 09:32:30.956792 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 09:32:30.963344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 09:32:30.970047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 09:32:30.973605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7257 09:32:30.976919 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7258 09:32:30.980004 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7259 09:32:30.986875 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7260 09:32:30.990218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7261 09:32:30.993555 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 09:32:30.996820 ===================================
7263 09:32:30.999960 LPDDR4 DRAM CONFIGURATION
7264 09:32:31.003135 ===================================
7265 09:32:31.006778 EX_ROW_EN[0] = 0x0
7266 09:32:31.006862 EX_ROW_EN[1] = 0x0
7267 09:32:31.010148 LP4Y_EN = 0x0
7268 09:32:31.010230 WORK_FSP = 0x1
7269 09:32:31.013588 WL = 0x5
7270 09:32:31.013672 RL = 0x5
7271 09:32:31.016923 BL = 0x2
7272 09:32:31.017005 RPST = 0x0
7273 09:32:31.020275 RD_PRE = 0x0
7274 09:32:31.020358 WR_PRE = 0x1
7275 09:32:31.023505 WR_PST = 0x1
7276 09:32:31.023587 DBI_WR = 0x0
7277 09:32:31.026760 DBI_RD = 0x0
7278 09:32:31.026843 OTF = 0x1
7279 09:32:31.030181 ===================================
7280 09:32:31.033470 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7281 09:32:31.040068 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7282 09:32:31.043497 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 09:32:31.046895 ===================================
7284 09:32:31.049857 LPDDR4 DRAM CONFIGURATION
7285 09:32:31.053127 ===================================
7286 09:32:31.053209 EX_ROW_EN[0] = 0x10
7287 09:32:31.056777 EX_ROW_EN[1] = 0x0
7288 09:32:31.060323 LP4Y_EN = 0x0
7289 09:32:31.060405 WORK_FSP = 0x1
7290 09:32:31.063598 WL = 0x5
7291 09:32:31.063680 RL = 0x5
7292 09:32:31.066664 BL = 0x2
7293 09:32:31.066772 RPST = 0x0
7294 09:32:31.070203 RD_PRE = 0x0
7295 09:32:31.070285 WR_PRE = 0x1
7296 09:32:31.073058 WR_PST = 0x1
7297 09:32:31.073140 DBI_WR = 0x0
7298 09:32:31.076572 DBI_RD = 0x0
7299 09:32:31.076653 OTF = 0x1
7300 09:32:31.079860 ===================================
7301 09:32:31.086953 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7302 09:32:31.087034 ==
7303 09:32:31.090002 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 09:32:31.093212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 09:32:31.093294 ==
7306 09:32:31.096624 [Duty_Offset_Calibration]
7307 09:32:31.099993 B0:2 B1:-1 CA:1
7308 09:32:31.100074
7309 09:32:31.103257 [DutyScan_Calibration_Flow] k_type=0
7310 09:32:31.111087
7311 09:32:31.111169 ==CLK 0==
7312 09:32:31.114405 Final CLK duty delay cell = -4
7313 09:32:31.117620 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7314 09:32:31.120985 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7315 09:32:31.124262 [-4] AVG Duty = 4937%(X100)
7316 09:32:31.124343
7317 09:32:31.127557 CH0 CLK Duty spec in!! Max-Min= 187%
7318 09:32:31.131198 [DutyScan_Calibration_Flow] ====Done====
7319 09:32:31.131280
7320 09:32:31.134341 [DutyScan_Calibration_Flow] k_type=1
7321 09:32:31.150647
7322 09:32:31.150782 ==DQS 0 ==
7323 09:32:31.154341 Final DQS duty delay cell = 0
7324 09:32:31.157423 [0] MAX Duty = 5125%(X100), DQS PI = 22
7325 09:32:31.160864 [0] MIN Duty = 5000%(X100), DQS PI = 16
7326 09:32:31.160947 [0] AVG Duty = 5062%(X100)
7327 09:32:31.164361
7328 09:32:31.164442 ==DQS 1 ==
7329 09:32:31.167633 Final DQS duty delay cell = -4
7330 09:32:31.170985 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7331 09:32:31.174567 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7332 09:32:31.177736 [-4] AVG Duty = 5062%(X100)
7333 09:32:31.177819
7334 09:32:31.181184 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7335 09:32:31.181284
7336 09:32:31.183819 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7337 09:32:31.187363 [DutyScan_Calibration_Flow] ====Done====
7338 09:32:31.187446
7339 09:32:31.190848 [DutyScan_Calibration_Flow] k_type=3
7340 09:32:31.208278
7341 09:32:31.208361 ==DQM 0 ==
7342 09:32:31.211615 Final DQM duty delay cell = 0
7343 09:32:31.214480 [0] MAX Duty = 5000%(X100), DQS PI = 20
7344 09:32:31.218225 [0] MIN Duty = 4875%(X100), DQS PI = 4
7345 09:32:31.218308 [0] AVG Duty = 4937%(X100)
7346 09:32:31.221434
7347 09:32:31.221516 ==DQM 1 ==
7348 09:32:31.224835 Final DQM duty delay cell = 0
7349 09:32:31.228318 [0] MAX Duty = 5218%(X100), DQS PI = 58
7350 09:32:31.231240 [0] MIN Duty = 4969%(X100), DQS PI = 18
7351 09:32:31.231323 [0] AVG Duty = 5093%(X100)
7352 09:32:31.234874
7353 09:32:31.238441 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7354 09:32:31.238549
7355 09:32:31.241628 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7356 09:32:31.244993 [DutyScan_Calibration_Flow] ====Done====
7357 09:32:31.245076
7358 09:32:31.248287 [DutyScan_Calibration_Flow] k_type=2
7359 09:32:31.265261
7360 09:32:31.265364 ==DQ 0 ==
7361 09:32:31.268311 Final DQ duty delay cell = 0
7362 09:32:31.271706 [0] MAX Duty = 5156%(X100), DQS PI = 0
7363 09:32:31.275380 [0] MIN Duty = 5031%(X100), DQS PI = 12
7364 09:32:31.275492 [0] AVG Duty = 5093%(X100)
7365 09:32:31.275579
7366 09:32:31.278664 ==DQ 1 ==
7367 09:32:31.281830 Final DQ duty delay cell = 0
7368 09:32:31.285211 [0] MAX Duty = 5031%(X100), DQS PI = 30
7369 09:32:31.289581 [0] MIN Duty = 4907%(X100), DQS PI = 18
7370 09:32:31.289663 [0] AVG Duty = 4969%(X100)
7371 09:32:31.289728
7372 09:32:31.291985 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7373 09:32:31.292067
7374 09:32:31.295383 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7375 09:32:31.302010 [DutyScan_Calibration_Flow] ====Done====
7376 09:32:31.302092 ==
7377 09:32:31.305380 Dram Type= 6, Freq= 0, CH_1, rank 0
7378 09:32:31.308751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7379 09:32:31.308833 ==
7380 09:32:31.312021 [Duty_Offset_Calibration]
7381 09:32:31.312102 B0:1 B1:1 CA:2
7382 09:32:31.312166
7383 09:32:31.314940 [DutyScan_Calibration_Flow] k_type=0
7384 09:32:31.325438
7385 09:32:31.325533 ==CLK 0==
7386 09:32:31.328506 Final CLK duty delay cell = 0
7387 09:32:31.331856 [0] MAX Duty = 5187%(X100), DQS PI = 24
7388 09:32:31.335353 [0] MIN Duty = 4938%(X100), DQS PI = 48
7389 09:32:31.335425 [0] AVG Duty = 5062%(X100)
7390 09:32:31.338524
7391 09:32:31.338624 CH1 CLK Duty spec in!! Max-Min= 249%
7392 09:32:31.345497 [DutyScan_Calibration_Flow] ====Done====
7393 09:32:31.345574
7394 09:32:31.348643 [DutyScan_Calibration_Flow] k_type=1
7395 09:32:31.364868
7396 09:32:31.364942 ==DQS 0 ==
7397 09:32:31.368847 Final DQS duty delay cell = 0
7398 09:32:31.372206 [0] MAX Duty = 5062%(X100), DQS PI = 22
7399 09:32:31.375395 [0] MIN Duty = 4813%(X100), DQS PI = 52
7400 09:32:31.375478 [0] AVG Duty = 4937%(X100)
7401 09:32:31.378690
7402 09:32:31.378796 ==DQS 1 ==
7403 09:32:31.382196 Final DQS duty delay cell = 0
7404 09:32:31.385384 [0] MAX Duty = 5062%(X100), DQS PI = 58
7405 09:32:31.388584 [0] MIN Duty = 4969%(X100), DQS PI = 0
7406 09:32:31.388656 [0] AVG Duty = 5015%(X100)
7407 09:32:31.391938
7408 09:32:31.395379 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7409 09:32:31.395463
7410 09:32:31.398468 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7411 09:32:31.401953 [DutyScan_Calibration_Flow] ====Done====
7412 09:32:31.402039
7413 09:32:31.405297 [DutyScan_Calibration_Flow] k_type=3
7414 09:32:31.421893
7415 09:32:31.422012 ==DQM 0 ==
7416 09:32:31.425145 Final DQM duty delay cell = 0
7417 09:32:31.428848 [0] MAX Duty = 5156%(X100), DQS PI = 20
7418 09:32:31.431802 [0] MIN Duty = 4844%(X100), DQS PI = 52
7419 09:32:31.435392 [0] AVG Duty = 5000%(X100)
7420 09:32:31.435578
7421 09:32:31.435726 ==DQM 1 ==
7422 09:32:31.438658 Final DQM duty delay cell = 0
7423 09:32:31.441966 [0] MAX Duty = 5125%(X100), DQS PI = 10
7424 09:32:31.445537 [0] MIN Duty = 4907%(X100), DQS PI = 18
7425 09:32:31.448928 [0] AVG Duty = 5016%(X100)
7426 09:32:31.449239
7427 09:32:31.452215 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7428 09:32:31.452628
7429 09:32:31.455706 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7430 09:32:31.459154 [DutyScan_Calibration_Flow] ====Done====
7431 09:32:31.459661
7432 09:32:31.462026 [DutyScan_Calibration_Flow] k_type=2
7433 09:32:31.478999
7434 09:32:31.479426 ==DQ 0 ==
7435 09:32:31.482351 Final DQ duty delay cell = 0
7436 09:32:31.486018 [0] MAX Duty = 5156%(X100), DQS PI = 20
7437 09:32:31.489500 [0] MIN Duty = 4907%(X100), DQS PI = 54
7438 09:32:31.489970 [0] AVG Duty = 5031%(X100)
7439 09:32:31.492662
7440 09:32:31.493108 ==DQ 1 ==
7441 09:32:31.495821 Final DQ duty delay cell = 0
7442 09:32:31.499246 [0] MAX Duty = 5093%(X100), DQS PI = 6
7443 09:32:31.502552 [0] MIN Duty = 5031%(X100), DQS PI = 0
7444 09:32:31.503017 [0] AVG Duty = 5062%(X100)
7445 09:32:31.503345
7446 09:32:31.505904 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7447 09:32:31.506371
7448 09:32:31.509272 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7449 09:32:31.515564 [DutyScan_Calibration_Flow] ====Done====
7450 09:32:31.519197 nWR fixed to 30
7451 09:32:31.519766 [ModeRegInit_LP4] CH0 RK0
7452 09:32:31.522538 [ModeRegInit_LP4] CH0 RK1
7453 09:32:31.525835 [ModeRegInit_LP4] CH1 RK0
7454 09:32:31.526284 [ModeRegInit_LP4] CH1 RK1
7455 09:32:31.528924 match AC timing 5
7456 09:32:31.532209 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7457 09:32:31.535849 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7458 09:32:31.542084 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7459 09:32:31.545781 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7460 09:32:31.552265 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7461 09:32:31.552781 [MiockJmeterHQA]
7462 09:32:31.553175
7463 09:32:31.555585 [DramcMiockJmeter] u1RxGatingPI = 0
7464 09:32:31.558820 0 : 4254, 4029
7465 09:32:31.559271 4 : 4363, 4138
7466 09:32:31.559601 8 : 4254, 4027
7467 09:32:31.562194 12 : 4252, 4027
7468 09:32:31.562660 16 : 4255, 4029
7469 09:32:31.565502 20 : 4252, 4027
7470 09:32:31.565991 24 : 4363, 4138
7471 09:32:31.568866 28 : 4363, 4137
7472 09:32:31.569357 32 : 4252, 4027
7473 09:32:31.569775 36 : 4253, 4026
7474 09:32:31.572384 40 : 4252, 4027
7475 09:32:31.572907 44 : 4252, 4027
7476 09:32:31.575431 48 : 4255, 4029
7477 09:32:31.575921 52 : 4363, 4137
7478 09:32:31.578955 56 : 4253, 4026
7479 09:32:31.579453 60 : 4250, 4027
7480 09:32:31.582300 64 : 4250, 4027
7481 09:32:31.582861 68 : 4253, 4029
7482 09:32:31.583208 72 : 4249, 4027
7483 09:32:31.585575 76 : 4360, 4137
7484 09:32:31.585999 80 : 4361, 4137
7485 09:32:31.588876 84 : 4250, 4027
7486 09:32:31.589300 88 : 4250, 4026
7487 09:32:31.592423 92 : 4250, 4027
7488 09:32:31.592875 96 : 4250, 3348
7489 09:32:31.593311 100 : 4253, 0
7490 09:32:31.595695 104 : 4360, 0
7491 09:32:31.596179 108 : 4360, 0
7492 09:32:31.599014 112 : 4361, 0
7493 09:32:31.599474 116 : 4253, 0
7494 09:32:31.599839 120 : 4360, 0
7495 09:32:31.602386 124 : 4250, 0
7496 09:32:31.603004 128 : 4250, 0
7497 09:32:31.603415 132 : 4252, 0
7498 09:32:31.605621 136 : 4250, 0
7499 09:32:31.606256 140 : 4363, 0
7500 09:32:31.609112 144 : 4252, 0
7501 09:32:31.609752 148 : 4250, 0
7502 09:32:31.610259 152 : 4250, 0
7503 09:32:31.612315 156 : 4252, 0
7504 09:32:31.612796 160 : 4250, 0
7505 09:32:31.615653 164 : 4361, 0
7506 09:32:31.616136 168 : 4250, 0
7507 09:32:31.616482 172 : 4363, 0
7508 09:32:31.619144 176 : 4250, 0
7509 09:32:31.619569 180 : 4253, 0
7510 09:32:31.619917 184 : 4252, 0
7511 09:32:31.622444 188 : 4250, 0
7512 09:32:31.622974 192 : 4363, 0
7513 09:32:31.625821 196 : 4252, 0
7514 09:32:31.626276 200 : 4250, 0
7515 09:32:31.626611 204 : 4250, 0
7516 09:32:31.629181 208 : 4360, 0
7517 09:32:31.629666 212 : 4250, 109
7518 09:32:31.632867 216 : 4250, 3604
7519 09:32:31.633345 220 : 4250, 4026
7520 09:32:31.636072 224 : 4250, 4027
7521 09:32:31.636544 228 : 4249, 4027
7522 09:32:31.639260 232 : 4360, 4137
7523 09:32:31.639684 236 : 4250, 4027
7524 09:32:31.640144 240 : 4250, 4027
7525 09:32:31.642534 244 : 4360, 4137
7526 09:32:31.643092 248 : 4250, 4027
7527 09:32:31.646024 252 : 4250, 4026
7528 09:32:31.646651 256 : 4363, 4140
7529 09:32:31.649374 260 : 4250, 4027
7530 09:32:31.649836 264 : 4249, 4027
7531 09:32:31.652933 268 : 4250, 4026
7532 09:32:31.653362 272 : 4253, 4029
7533 09:32:31.656337 276 : 4250, 4027
7534 09:32:31.656764 280 : 4250, 4027
7535 09:32:31.659591 284 : 4360, 4137
7536 09:32:31.660021 288 : 4250, 4027
7537 09:32:31.662509 292 : 4250, 4026
7538 09:32:31.662992 296 : 4361, 4138
7539 09:32:31.663339 300 : 4250, 4027
7540 09:32:31.666227 304 : 4250, 4027
7541 09:32:31.666656 308 : 4363, 4140
7542 09:32:31.669457 312 : 4249, 4027
7543 09:32:31.669885 316 : 4250, 4027
7544 09:32:31.672618 320 : 4250, 4026
7545 09:32:31.673048 324 : 4253, 4029
7546 09:32:31.675925 328 : 4250, 4027
7547 09:32:31.676354 332 : 4250, 2778
7548 09:32:31.679411 336 : 4360, 59
7549 09:32:31.679890
7550 09:32:31.680223 MIOCK jitter meter ch=0
7551 09:32:31.680529
7552 09:32:31.682824 1T = (336-100) = 236 dly cells
7553 09:32:31.689486 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7554 09:32:31.690007 ==
7555 09:32:31.692775 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 09:32:31.695884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 09:32:31.696301 ==
7558 09:32:31.702651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 09:32:31.706297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 09:32:31.709175 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 09:32:31.716176 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 09:32:31.725841 [CA 0] Center 44 (14~75) winsize 62
7563 09:32:31.729050 [CA 1] Center 44 (14~74) winsize 61
7564 09:32:31.732358 [CA 2] Center 39 (10~68) winsize 59
7565 09:32:31.735834 [CA 3] Center 39 (10~68) winsize 59
7566 09:32:31.739236 [CA 4] Center 37 (7~67) winsize 61
7567 09:32:31.742418 [CA 5] Center 37 (7~67) winsize 61
7568 09:32:31.743130
7569 09:32:31.746040 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 09:32:31.746510
7571 09:32:31.749035 [CATrainingPosCal] consider 1 rank data
7572 09:32:31.752626 u2DelayCellTimex100 = 275/100 ps
7573 09:32:31.755557 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7574 09:32:31.762158 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7575 09:32:31.765584 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7576 09:32:31.769050 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7577 09:32:31.772309 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7578 09:32:31.775657 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7579 09:32:31.776133
7580 09:32:31.779301 CA PerBit enable=1, Macro0, CA PI delay=37
7581 09:32:31.779848
7582 09:32:31.782586 [CBTSetCACLKResult] CA Dly = 37
7583 09:32:31.785761 CS Dly: 10 (0~41)
7584 09:32:31.789244 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 09:32:31.792608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 09:32:31.793134 ==
7587 09:32:31.796046 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 09:32:31.799325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 09:32:31.799756 ==
7590 09:32:31.805976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 09:32:31.809558 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 09:32:31.816329 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 09:32:31.819089 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 09:32:31.829468 [CA 0] Center 44 (14~74) winsize 61
7595 09:32:31.832714 [CA 1] Center 44 (14~74) winsize 61
7596 09:32:31.835803 [CA 2] Center 40 (11~69) winsize 59
7597 09:32:31.839174 [CA 3] Center 39 (10~68) winsize 59
7598 09:32:31.842478 [CA 4] Center 37 (8~67) winsize 60
7599 09:32:31.846446 [CA 5] Center 37 (7~67) winsize 61
7600 09:32:31.846947
7601 09:32:31.849353 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7602 09:32:31.849777
7603 09:32:31.852968 [CATrainingPosCal] consider 2 rank data
7604 09:32:31.856224 u2DelayCellTimex100 = 275/100 ps
7605 09:32:31.859692 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7606 09:32:31.865810 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7607 09:32:31.869419 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7608 09:32:31.873036 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7609 09:32:31.876163 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7610 09:32:31.879460 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7611 09:32:31.879941
7612 09:32:31.882935 CA PerBit enable=1, Macro0, CA PI delay=37
7613 09:32:31.883362
7614 09:32:31.885660 [CBTSetCACLKResult] CA Dly = 37
7615 09:32:31.889258 CS Dly: 11 (0~44)
7616 09:32:31.892975 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 09:32:31.895907 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 09:32:31.896359
7619 09:32:31.899342 ----->DramcWriteLeveling(PI) begin...
7620 09:32:31.899822 ==
7621 09:32:31.902567 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 09:32:31.906001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 09:32:31.909371 ==
7624 09:32:31.909831 Write leveling (Byte 0): 33 => 33
7625 09:32:31.912931 Write leveling (Byte 1): 29 => 29
7626 09:32:31.916011 DramcWriteLeveling(PI) end<-----
7627 09:32:31.916442
7628 09:32:31.916789 ==
7629 09:32:31.919542 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 09:32:31.925898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 09:32:31.926353 ==
7632 09:32:31.926712 [Gating] SW mode calibration
7633 09:32:31.936152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 09:32:31.939515 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 09:32:31.942966 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 09:32:31.949422 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 09:32:31.953031 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 09:32:31.956114 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 09:32:31.962640 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7640 09:32:31.966293 1 4 20 | B1->B0 | 2423 3333 | 1 0 | (0 0) (0 0)
7641 09:32:31.969463 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7642 09:32:31.976084 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 09:32:31.979215 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 09:32:31.982399 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 09:32:31.989278 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 09:32:31.992808 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 09:32:31.995696 1 5 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7648 09:32:32.002785 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7649 09:32:32.006031 1 5 24 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7650 09:32:32.009370 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 09:32:32.015667 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 09:32:32.019388 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 09:32:32.022684 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 09:32:32.029062 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 09:32:32.032446 1 6 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7656 09:32:32.035915 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7657 09:32:32.038899 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7658 09:32:32.045960 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 09:32:32.048924 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 09:32:32.052225 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 09:32:32.059260 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 09:32:32.062376 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 09:32:32.065980 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 09:32:32.072330 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7665 09:32:32.075526 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7666 09:32:32.078994 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 09:32:32.085687 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 09:32:32.088797 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 09:32:32.092568 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 09:32:32.098959 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 09:32:32.102704 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 09:32:32.105892 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 09:32:32.112546 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 09:32:32.115868 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 09:32:32.119245 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 09:32:32.125885 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 09:32:32.129261 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 09:32:32.132784 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7679 09:32:32.136117 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 09:32:32.142339 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7681 09:32:32.145739 Total UI for P1: 0, mck2ui 16
7682 09:32:32.149172 best dqsien dly found for B0: ( 1, 9, 14)
7683 09:32:32.152419 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 09:32:32.155812 Total UI for P1: 0, mck2ui 16
7685 09:32:32.159310 best dqsien dly found for B1: ( 1, 9, 20)
7686 09:32:32.162704 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7687 09:32:32.166082 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7688 09:32:32.166320
7689 09:32:32.169983 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7690 09:32:32.172840 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7691 09:32:32.176619 [Gating] SW calibration Done
7692 09:32:32.176913 ==
7693 09:32:32.179408 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 09:32:32.185956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 09:32:32.186258 ==
7696 09:32:32.186510 RX Vref Scan: 0
7697 09:32:32.186765
7698 09:32:32.189534 RX Vref 0 -> 0, step: 1
7699 09:32:32.190036
7700 09:32:32.192768 RX Delay 0 -> 252, step: 8
7701 09:32:32.196202 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7702 09:32:32.199494 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7703 09:32:32.202882 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7704 09:32:32.206040 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7705 09:32:32.212526 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7706 09:32:32.215874 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7707 09:32:32.219108 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7708 09:32:32.223338 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7709 09:32:32.225994 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7710 09:32:32.229236 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7711 09:32:32.235918 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7712 09:32:32.239267 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7713 09:32:32.242906 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7714 09:32:32.246142 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7715 09:32:32.249650 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7716 09:32:32.256455 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7717 09:32:32.256579 ==
7718 09:32:32.259261 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 09:32:32.263022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 09:32:32.263176 ==
7721 09:32:32.263297 DQS Delay:
7722 09:32:32.265925 DQS0 = 0, DQS1 = 0
7723 09:32:32.266077 DQM Delay:
7724 09:32:32.269827 DQM0 = 132, DQM1 = 123
7725 09:32:32.270020 DQ Delay:
7726 09:32:32.272665 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7727 09:32:32.276044 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7728 09:32:32.279503 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7729 09:32:32.283212 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7730 09:32:32.286516
7731 09:32:32.286847
7732 09:32:32.287091 ==
7733 09:32:32.289716 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 09:32:32.293019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 09:32:32.293443 ==
7736 09:32:32.293777
7737 09:32:32.294087
7738 09:32:32.296399 TX Vref Scan disable
7739 09:32:32.296822 == TX Byte 0 ==
7740 09:32:32.303042 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7741 09:32:32.306511 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7742 09:32:32.306975 == TX Byte 1 ==
7743 09:32:32.312820 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7744 09:32:32.316437 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7745 09:32:32.316862 ==
7746 09:32:32.320054 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 09:32:32.322926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 09:32:32.323355 ==
7749 09:32:32.337018
7750 09:32:32.340396 TX Vref early break, caculate TX vref
7751 09:32:32.343338 TX Vref=16, minBit 1, minWin=22, winSum=365
7752 09:32:32.347005 TX Vref=18, minBit 2, minWin=22, winSum=378
7753 09:32:32.350259 TX Vref=20, minBit 0, minWin=23, winSum=388
7754 09:32:32.353689 TX Vref=22, minBit 0, minWin=24, winSum=399
7755 09:32:32.356708 TX Vref=24, minBit 0, minWin=24, winSum=407
7756 09:32:32.363880 TX Vref=26, minBit 1, minWin=25, winSum=419
7757 09:32:32.366771 TX Vref=28, minBit 3, minWin=25, winSum=424
7758 09:32:32.369997 TX Vref=30, minBit 3, minWin=25, winSum=425
7759 09:32:32.373467 TX Vref=32, minBit 3, minWin=25, winSum=420
7760 09:32:32.376999 TX Vref=34, minBit 3, minWin=24, winSum=402
7761 09:32:32.383425 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 30
7762 09:32:32.383922
7763 09:32:32.386858 Final TX Range 0 Vref 30
7764 09:32:32.387294
7765 09:32:32.387630 ==
7766 09:32:32.390082 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 09:32:32.393760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 09:32:32.394334 ==
7769 09:32:32.394677
7770 09:32:32.395038
7771 09:32:32.396621 TX Vref Scan disable
7772 09:32:32.404073 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7773 09:32:32.404601 == TX Byte 0 ==
7774 09:32:32.407249 u2DelayCellOfst[0]=14 cells (4 PI)
7775 09:32:32.409921 u2DelayCellOfst[1]=21 cells (6 PI)
7776 09:32:32.413229 u2DelayCellOfst[2]=14 cells (4 PI)
7777 09:32:32.416755 u2DelayCellOfst[3]=17 cells (5 PI)
7778 09:32:32.420219 u2DelayCellOfst[4]=10 cells (3 PI)
7779 09:32:32.423970 u2DelayCellOfst[5]=0 cells (0 PI)
7780 09:32:32.426895 u2DelayCellOfst[6]=21 cells (6 PI)
7781 09:32:32.427342 u2DelayCellOfst[7]=21 cells (6 PI)
7782 09:32:32.433979 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7783 09:32:32.436649 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7784 09:32:32.437088 == TX Byte 1 ==
7785 09:32:32.440470 u2DelayCellOfst[8]=0 cells (0 PI)
7786 09:32:32.443582 u2DelayCellOfst[9]=0 cells (0 PI)
7787 09:32:32.447298 u2DelayCellOfst[10]=7 cells (2 PI)
7788 09:32:32.450568 u2DelayCellOfst[11]=0 cells (0 PI)
7789 09:32:32.453916 u2DelayCellOfst[12]=10 cells (3 PI)
7790 09:32:32.457276 u2DelayCellOfst[13]=10 cells (3 PI)
7791 09:32:32.460756 u2DelayCellOfst[14]=14 cells (4 PI)
7792 09:32:32.463791 u2DelayCellOfst[15]=7 cells (2 PI)
7793 09:32:32.467339 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7794 09:32:32.470312 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7795 09:32:32.473770 DramC Write-DBI on
7796 09:32:32.474300 ==
7797 09:32:32.477360 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 09:32:32.480633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 09:32:32.481135 ==
7800 09:32:32.481481
7801 09:32:32.481788
7802 09:32:32.483502 TX Vref Scan disable
7803 09:32:32.487022 == TX Byte 0 ==
7804 09:32:32.490599 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7805 09:32:32.491071 == TX Byte 1 ==
7806 09:32:32.496972 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7807 09:32:32.497395 DramC Write-DBI off
7808 09:32:32.497729
7809 09:32:32.500259 [DATLAT]
7810 09:32:32.500677 Freq=1600, CH0 RK0
7811 09:32:32.501011
7812 09:32:32.503562 DATLAT Default: 0xf
7813 09:32:32.503981 0, 0xFFFF, sum = 0
7814 09:32:32.507374 1, 0xFFFF, sum = 0
7815 09:32:32.507799 2, 0xFFFF, sum = 0
7816 09:32:32.510378 3, 0xFFFF, sum = 0
7817 09:32:32.510886 4, 0xFFFF, sum = 0
7818 09:32:32.513885 5, 0xFFFF, sum = 0
7819 09:32:32.514325 6, 0xFFFF, sum = 0
7820 09:32:32.517231 7, 0xFFFF, sum = 0
7821 09:32:32.517669 8, 0xFFFF, sum = 0
7822 09:32:32.520515 9, 0xFFFF, sum = 0
7823 09:32:32.520956 10, 0xFFFF, sum = 0
7824 09:32:32.524000 11, 0xFFFF, sum = 0
7825 09:32:32.524440 12, 0xFFFF, sum = 0
7826 09:32:32.527331 13, 0xFFFF, sum = 0
7827 09:32:32.527773 14, 0x0, sum = 1
7828 09:32:32.530870 15, 0x0, sum = 2
7829 09:32:32.531313 16, 0x0, sum = 3
7830 09:32:32.533792 17, 0x0, sum = 4
7831 09:32:32.534273 best_step = 15
7832 09:32:32.534712
7833 09:32:32.535165 ==
7834 09:32:32.537486 Dram Type= 6, Freq= 0, CH_0, rank 0
7835 09:32:32.543918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7836 09:32:32.544475 ==
7837 09:32:32.544988 RX Vref Scan: 1
7838 09:32:32.545317
7839 09:32:32.547237 Set Vref Range= 24 -> 127
7840 09:32:32.547656
7841 09:32:32.550218 RX Vref 24 -> 127, step: 1
7842 09:32:32.550652
7843 09:32:32.551044 RX Delay 11 -> 252, step: 4
7844 09:32:32.554026
7845 09:32:32.554441 Set Vref, RX VrefLevel [Byte0]: 24
7846 09:32:32.557250 [Byte1]: 24
7847 09:32:32.561949
7848 09:32:32.562367 Set Vref, RX VrefLevel [Byte0]: 25
7849 09:32:32.564732 [Byte1]: 25
7850 09:32:32.569098
7851 09:32:32.569513 Set Vref, RX VrefLevel [Byte0]: 26
7852 09:32:32.572433 [Byte1]: 26
7853 09:32:32.576996
7854 09:32:32.577413 Set Vref, RX VrefLevel [Byte0]: 27
7855 09:32:32.580041 [Byte1]: 27
7856 09:32:32.584226
7857 09:32:32.584776 Set Vref, RX VrefLevel [Byte0]: 28
7858 09:32:32.588033 [Byte1]: 28
7859 09:32:32.592085
7860 09:32:32.592551 Set Vref, RX VrefLevel [Byte0]: 29
7861 09:32:32.595249 [Byte1]: 29
7862 09:32:32.599581
7863 09:32:32.599996 Set Vref, RX VrefLevel [Byte0]: 30
7864 09:32:32.602957 [Byte1]: 30
7865 09:32:32.606992
7866 09:32:32.607421 Set Vref, RX VrefLevel [Byte0]: 31
7867 09:32:32.610249 [Byte1]: 31
7868 09:32:32.614855
7869 09:32:32.615272 Set Vref, RX VrefLevel [Byte0]: 32
7870 09:32:32.617976 [Byte1]: 32
7871 09:32:32.622437
7872 09:32:32.623027 Set Vref, RX VrefLevel [Byte0]: 33
7873 09:32:32.625561 [Byte1]: 33
7874 09:32:32.630021
7875 09:32:32.630512 Set Vref, RX VrefLevel [Byte0]: 34
7876 09:32:32.633693 [Byte1]: 34
7877 09:32:32.637895
7878 09:32:32.638405 Set Vref, RX VrefLevel [Byte0]: 35
7879 09:32:32.640990 [Byte1]: 35
7880 09:32:32.644966
7881 09:32:32.645557 Set Vref, RX VrefLevel [Byte0]: 36
7882 09:32:32.648444 [Byte1]: 36
7883 09:32:32.652705
7884 09:32:32.653391 Set Vref, RX VrefLevel [Byte0]: 37
7885 09:32:32.655880 [Byte1]: 37
7886 09:32:32.660300
7887 09:32:32.660959 Set Vref, RX VrefLevel [Byte0]: 38
7888 09:32:32.663662 [Byte1]: 38
7889 09:32:32.668365
7890 09:32:32.669012 Set Vref, RX VrefLevel [Byte0]: 39
7891 09:32:32.671003 [Byte1]: 39
7892 09:32:32.675918
7893 09:32:32.676565 Set Vref, RX VrefLevel [Byte0]: 40
7894 09:32:32.678797 [Byte1]: 40
7895 09:32:32.683174
7896 09:32:32.683861 Set Vref, RX VrefLevel [Byte0]: 41
7897 09:32:32.686667 [Byte1]: 41
7898 09:32:32.690815
7899 09:32:32.691217 Set Vref, RX VrefLevel [Byte0]: 42
7900 09:32:32.694014 [Byte1]: 42
7901 09:32:32.698320
7902 09:32:32.698811 Set Vref, RX VrefLevel [Byte0]: 43
7903 09:32:32.701590 [Byte1]: 43
7904 09:32:32.706257
7905 09:32:32.706747 Set Vref, RX VrefLevel [Byte0]: 44
7906 09:32:32.709029 [Byte1]: 44
7907 09:32:32.713548
7908 09:32:32.713982 Set Vref, RX VrefLevel [Byte0]: 45
7909 09:32:32.716873 [Byte1]: 45
7910 09:32:32.720924
7911 09:32:32.721331 Set Vref, RX VrefLevel [Byte0]: 46
7912 09:32:32.724340 [Byte1]: 46
7913 09:32:32.728591
7914 09:32:32.729010 Set Vref, RX VrefLevel [Byte0]: 47
7915 09:32:32.732075 [Byte1]: 47
7916 09:32:32.736672
7917 09:32:32.737089 Set Vref, RX VrefLevel [Byte0]: 48
7918 09:32:32.739978 [Byte1]: 48
7919 09:32:32.743872
7920 09:32:32.744290 Set Vref, RX VrefLevel [Byte0]: 49
7921 09:32:32.747516 [Byte1]: 49
7922 09:32:32.751601
7923 09:32:32.752039 Set Vref, RX VrefLevel [Byte0]: 50
7924 09:32:32.754652 [Byte1]: 50
7925 09:32:32.759525
7926 09:32:32.759874 Set Vref, RX VrefLevel [Byte0]: 51
7927 09:32:32.762465 [Byte1]: 51
7928 09:32:32.766823
7929 09:32:32.767170 Set Vref, RX VrefLevel [Byte0]: 52
7930 09:32:32.770174 [Byte1]: 52
7931 09:32:32.774281
7932 09:32:32.774757 Set Vref, RX VrefLevel [Byte0]: 53
7933 09:32:32.777537 [Byte1]: 53
7934 09:32:32.782204
7935 09:32:32.782605 Set Vref, RX VrefLevel [Byte0]: 54
7936 09:32:32.785471 [Byte1]: 54
7937 09:32:32.789397
7938 09:32:32.789755 Set Vref, RX VrefLevel [Byte0]: 55
7939 09:32:32.792973 [Byte1]: 55
7940 09:32:32.797325
7941 09:32:32.797679 Set Vref, RX VrefLevel [Byte0]: 56
7942 09:32:32.800551 [Byte1]: 56
7943 09:32:32.805013
7944 09:32:32.805404 Set Vref, RX VrefLevel [Byte0]: 57
7945 09:32:32.808268 [Byte1]: 57
7946 09:32:32.812560
7947 09:32:32.812895 Set Vref, RX VrefLevel [Byte0]: 58
7948 09:32:32.815646 [Byte1]: 58
7949 09:32:32.820052
7950 09:32:32.820350 Set Vref, RX VrefLevel [Byte0]: 59
7951 09:32:32.823911 [Byte1]: 59
7952 09:32:32.827919
7953 09:32:32.828345 Set Vref, RX VrefLevel [Byte0]: 60
7954 09:32:32.831330 [Byte1]: 60
7955 09:32:32.835535
7956 09:32:32.835952 Set Vref, RX VrefLevel [Byte0]: 61
7957 09:32:32.838629 [Byte1]: 61
7958 09:32:32.843049
7959 09:32:32.843466 Set Vref, RX VrefLevel [Byte0]: 62
7960 09:32:32.846769 [Byte1]: 62
7961 09:32:32.850793
7962 09:32:32.851213 Set Vref, RX VrefLevel [Byte0]: 63
7963 09:32:32.854098 [Byte1]: 63
7964 09:32:32.858609
7965 09:32:32.859066 Set Vref, RX VrefLevel [Byte0]: 64
7966 09:32:32.861561 [Byte1]: 64
7967 09:32:32.865956
7968 09:32:32.866402 Set Vref, RX VrefLevel [Byte0]: 65
7969 09:32:32.869176 [Byte1]: 65
7970 09:32:32.873382
7971 09:32:32.873799 Set Vref, RX VrefLevel [Byte0]: 66
7972 09:32:32.876978 [Byte1]: 66
7973 09:32:32.881364
7974 09:32:32.881790 Set Vref, RX VrefLevel [Byte0]: 67
7975 09:32:32.884815 [Byte1]: 67
7976 09:32:32.888822
7977 09:32:32.889238 Set Vref, RX VrefLevel [Byte0]: 68
7978 09:32:32.892209 [Byte1]: 68
7979 09:32:32.896641
7980 09:32:32.897060 Set Vref, RX VrefLevel [Byte0]: 69
7981 09:32:32.899544 [Byte1]: 69
7982 09:32:32.904324
7983 09:32:32.904737 Set Vref, RX VrefLevel [Byte0]: 70
7984 09:32:32.907506 [Byte1]: 70
7985 09:32:32.911508
7986 09:32:32.911939 Set Vref, RX VrefLevel [Byte0]: 71
7987 09:32:32.914964 [Byte1]: 71
7988 09:32:32.919621
7989 09:32:32.920061 Set Vref, RX VrefLevel [Byte0]: 72
7990 09:32:32.922621 [Byte1]: 72
7991 09:32:32.926828
7992 09:32:32.927393 Set Vref, RX VrefLevel [Byte0]: 73
7993 09:32:32.930516 [Byte1]: 73
7994 09:32:32.934408
7995 09:32:32.934983 Set Vref, RX VrefLevel [Byte0]: 74
7996 09:32:32.937869 [Byte1]: 74
7997 09:32:32.942243
7998 09:32:32.942772 Set Vref, RX VrefLevel [Byte0]: 75
7999 09:32:32.945230 [Byte1]: 75
8000 09:32:32.949636
8001 09:32:32.950100 Set Vref, RX VrefLevel [Byte0]: 76
8002 09:32:32.953366 [Byte1]: 76
8003 09:32:32.957168
8004 09:32:32.957747 Final RX Vref Byte 0 = 56 to rank0
8005 09:32:32.960599 Final RX Vref Byte 1 = 61 to rank0
8006 09:32:32.964327 Final RX Vref Byte 0 = 56 to rank1
8007 09:32:32.967088 Final RX Vref Byte 1 = 61 to rank1==
8008 09:32:32.970834 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 09:32:32.977237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 09:32:32.977654 ==
8011 09:32:32.977982 DQS Delay:
8012 09:32:32.978283 DQS0 = 0, DQS1 = 0
8013 09:32:32.980805 DQM Delay:
8014 09:32:32.981218 DQM0 = 128, DQM1 = 121
8015 09:32:32.983916 DQ Delay:
8016 09:32:32.987440 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =126
8017 09:32:32.990627 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
8018 09:32:32.994388 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8019 09:32:32.997673 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8020 09:32:32.998100
8021 09:32:32.998437
8022 09:32:32.998790
8023 09:32:33.000494 [DramC_TX_OE_Calibration] TA2
8024 09:32:33.003779 Original DQ_B0 (3 6) =30, OEN = 27
8025 09:32:33.007102 Original DQ_B1 (3 6) =30, OEN = 27
8026 09:32:33.010453 24, 0x0, End_B0=24 End_B1=24
8027 09:32:33.010958 25, 0x0, End_B0=25 End_B1=25
8028 09:32:33.013881 26, 0x0, End_B0=26 End_B1=26
8029 09:32:33.017205 27, 0x0, End_B0=27 End_B1=27
8030 09:32:33.020609 28, 0x0, End_B0=28 End_B1=28
8031 09:32:33.021042 29, 0x0, End_B0=29 End_B1=29
8032 09:32:33.024122 30, 0x0, End_B0=30 End_B1=30
8033 09:32:33.027508 31, 0x4141, End_B0=30 End_B1=30
8034 09:32:33.030707 Byte0 end_step=30 best_step=27
8035 09:32:33.034148 Byte1 end_step=30 best_step=27
8036 09:32:33.037270 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 09:32:33.037694 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 09:32:33.038026
8039 09:32:33.038340
8040 09:32:33.047268 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8041 09:32:33.050824 CH0 RK0: MR19=303, MR18=1206
8042 09:32:33.057155 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
8043 09:32:33.057695
8044 09:32:33.060608 ----->DramcWriteLeveling(PI) begin...
8045 09:32:33.061041 ==
8046 09:32:33.064014 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 09:32:33.067257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 09:32:33.067710 ==
8049 09:32:33.070808 Write leveling (Byte 0): 34 => 34
8050 09:32:33.074353 Write leveling (Byte 1): 25 => 25
8051 09:32:33.077667 DramcWriteLeveling(PI) end<-----
8052 09:32:33.078088
8053 09:32:33.078423 ==
8054 09:32:33.081152 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 09:32:33.083999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 09:32:33.084428 ==
8057 09:32:33.087331 [Gating] SW mode calibration
8058 09:32:33.094062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 09:32:33.100593 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 09:32:33.103976 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 09:32:33.107613 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 09:32:33.113996 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 09:32:33.117220 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8064 09:32:33.120680 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8065 09:32:33.127523 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
8066 09:32:33.131012 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 09:32:33.133990 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 09:32:33.137403 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 09:32:33.144125 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 09:32:33.147451 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8071 09:32:33.150647 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8072 09:32:33.157446 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8073 09:32:33.160508 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8074 09:32:33.164374 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 09:32:33.170675 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 09:32:33.174392 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 09:32:33.177565 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 09:32:33.184306 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8079 09:32:33.187468 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8080 09:32:33.190764 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8081 09:32:33.197367 1 6 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8082 09:32:33.200877 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 09:32:33.204076 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 09:32:33.211046 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 09:32:33.213939 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 09:32:33.217719 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 09:32:33.220833 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8088 09:32:33.227896 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8089 09:32:33.230771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 09:32:33.234259 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 09:32:33.241001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 09:32:33.244806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 09:32:33.247793 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 09:32:33.254659 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 09:32:33.257948 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 09:32:33.261553 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 09:32:33.267962 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 09:32:33.271071 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 09:32:33.274351 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 09:32:33.281326 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 09:32:33.285051 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 09:32:33.287737 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 09:32:33.294535 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8104 09:32:33.295108 Total UI for P1: 0, mck2ui 16
8105 09:32:33.297900 best dqsien dly found for B0: ( 1, 9, 8)
8106 09:32:33.304574 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8107 09:32:33.307803 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 09:32:33.311366 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 09:32:33.317738 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 09:32:33.321138 Total UI for P1: 0, mck2ui 16
8111 09:32:33.324275 best dqsien dly found for B1: ( 1, 9, 22)
8112 09:32:33.327690 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8113 09:32:33.331244 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8114 09:32:33.331832
8115 09:32:33.334619 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8116 09:32:33.338350 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8117 09:32:33.341286 [Gating] SW calibration Done
8118 09:32:33.341819 ==
8119 09:32:33.344591 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 09:32:33.348138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 09:32:33.348753 ==
8122 09:32:33.350801 RX Vref Scan: 0
8123 09:32:33.351227
8124 09:32:33.351562 RX Vref 0 -> 0, step: 1
8125 09:32:33.351878
8126 09:32:33.354849 RX Delay 0 -> 252, step: 8
8127 09:32:33.357692 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8128 09:32:33.364236 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8129 09:32:33.367644 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8130 09:32:33.371063 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8131 09:32:33.374349 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8132 09:32:33.377961 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8133 09:32:33.384400 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 09:32:33.388121 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8135 09:32:33.391165 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8136 09:32:33.394384 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8137 09:32:33.397579 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8138 09:32:33.401399 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8139 09:32:33.407679 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8140 09:32:33.411198 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8141 09:32:33.414672 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8142 09:32:33.417845 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8143 09:32:33.418423 ==
8144 09:32:33.421458 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 09:32:33.427784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 09:32:33.428378 ==
8147 09:32:33.428908 DQS Delay:
8148 09:32:33.431161 DQS0 = 0, DQS1 = 0
8149 09:32:33.431627 DQM Delay:
8150 09:32:33.434703 DQM0 = 131, DQM1 = 125
8151 09:32:33.435218 DQ Delay:
8152 09:32:33.437824 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8153 09:32:33.441603 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8154 09:32:33.445015 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8155 09:32:33.448285 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8156 09:32:33.448733
8157 09:32:33.449103
8158 09:32:33.449415 ==
8159 09:32:33.451351 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 09:32:33.454654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 09:32:33.458328 ==
8162 09:32:33.458937
8163 09:32:33.459324
8164 09:32:33.459639 TX Vref Scan disable
8165 09:32:33.462047 == TX Byte 0 ==
8166 09:32:33.464792 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8167 09:32:33.468591 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8168 09:32:33.471327 == TX Byte 1 ==
8169 09:32:33.474827 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8170 09:32:33.478329 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8171 09:32:33.478787 ==
8172 09:32:33.481592 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 09:32:33.488507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 09:32:33.488930 ==
8175 09:32:33.502207
8176 09:32:33.505655 TX Vref early break, caculate TX vref
8177 09:32:33.509286 TX Vref=16, minBit 8, minWin=22, winSum=375
8178 09:32:33.512458 TX Vref=18, minBit 9, minWin=22, winSum=382
8179 09:32:33.515750 TX Vref=20, minBit 8, minWin=23, winSum=390
8180 09:32:33.519061 TX Vref=22, minBit 9, minWin=23, winSum=401
8181 09:32:33.522399 TX Vref=24, minBit 8, minWin=24, winSum=408
8182 09:32:33.529073 TX Vref=26, minBit 3, minWin=25, winSum=412
8183 09:32:33.532330 TX Vref=28, minBit 8, minWin=25, winSum=419
8184 09:32:33.536004 TX Vref=30, minBit 0, minWin=26, winSum=424
8185 09:32:33.539135 TX Vref=32, minBit 1, minWin=25, winSum=412
8186 09:32:33.542313 TX Vref=34, minBit 4, minWin=24, winSum=405
8187 09:32:33.545907 TX Vref=36, minBit 8, minWin=23, winSum=395
8188 09:32:33.552431 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
8189 09:32:33.552915
8190 09:32:33.555764 Final TX Range 0 Vref 30
8191 09:32:33.556243
8192 09:32:33.556680 ==
8193 09:32:33.558934 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 09:32:33.562794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 09:32:33.563231 ==
8196 09:32:33.563664
8197 09:32:33.564070
8198 09:32:33.565567 TX Vref Scan disable
8199 09:32:33.572262 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8200 09:32:33.572718 == TX Byte 0 ==
8201 09:32:33.575782 u2DelayCellOfst[0]=14 cells (4 PI)
8202 09:32:33.579038 u2DelayCellOfst[1]=17 cells (5 PI)
8203 09:32:33.582492 u2DelayCellOfst[2]=10 cells (3 PI)
8204 09:32:33.586030 u2DelayCellOfst[3]=10 cells (3 PI)
8205 09:32:33.589260 u2DelayCellOfst[4]=7 cells (2 PI)
8206 09:32:33.592822 u2DelayCellOfst[5]=0 cells (0 PI)
8207 09:32:33.595634 u2DelayCellOfst[6]=17 cells (5 PI)
8208 09:32:33.599057 u2DelayCellOfst[7]=17 cells (5 PI)
8209 09:32:33.602439 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8210 09:32:33.606009 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8211 09:32:33.609141 == TX Byte 1 ==
8212 09:32:33.609575 u2DelayCellOfst[8]=0 cells (0 PI)
8213 09:32:33.612359 u2DelayCellOfst[9]=0 cells (0 PI)
8214 09:32:33.615765 u2DelayCellOfst[10]=3 cells (1 PI)
8215 09:32:33.619009 u2DelayCellOfst[11]=0 cells (0 PI)
8216 09:32:33.622506 u2DelayCellOfst[12]=10 cells (3 PI)
8217 09:32:33.625492 u2DelayCellOfst[13]=10 cells (3 PI)
8218 09:32:33.628922 u2DelayCellOfst[14]=14 cells (4 PI)
8219 09:32:33.632048 u2DelayCellOfst[15]=10 cells (3 PI)
8220 09:32:33.635455 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8221 09:32:33.642051 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8222 09:32:33.642487 DramC Write-DBI on
8223 09:32:33.642997 ==
8224 09:32:33.645830 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 09:32:33.648771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 09:32:33.652465 ==
8227 09:32:33.652888
8228 09:32:33.653216
8229 09:32:33.653518 TX Vref Scan disable
8230 09:32:33.655827 == TX Byte 0 ==
8231 09:32:33.659362 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8232 09:32:33.662287 == TX Byte 1 ==
8233 09:32:33.666013 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8234 09:32:33.669356 DramC Write-DBI off
8235 09:32:33.669773
8236 09:32:33.670100 [DATLAT]
8237 09:32:33.670408 Freq=1600, CH0 RK1
8238 09:32:33.670707
8239 09:32:33.672732 DATLAT Default: 0xf
8240 09:32:33.673221 0, 0xFFFF, sum = 0
8241 09:32:33.676172 1, 0xFFFF, sum = 0
8242 09:32:33.676672 2, 0xFFFF, sum = 0
8243 09:32:33.678829 3, 0xFFFF, sum = 0
8244 09:32:33.682338 4, 0xFFFF, sum = 0
8245 09:32:33.682802 5, 0xFFFF, sum = 0
8246 09:32:33.685972 6, 0xFFFF, sum = 0
8247 09:32:33.686405 7, 0xFFFF, sum = 0
8248 09:32:33.689513 8, 0xFFFF, sum = 0
8249 09:32:33.689938 9, 0xFFFF, sum = 0
8250 09:32:33.692555 10, 0xFFFF, sum = 0
8251 09:32:33.692979 11, 0xFFFF, sum = 0
8252 09:32:33.695673 12, 0xFFFF, sum = 0
8253 09:32:33.696179 13, 0xFFFF, sum = 0
8254 09:32:33.698860 14, 0x0, sum = 1
8255 09:32:33.699285 15, 0x0, sum = 2
8256 09:32:33.702313 16, 0x0, sum = 3
8257 09:32:33.702775 17, 0x0, sum = 4
8258 09:32:33.705506 best_step = 15
8259 09:32:33.705919
8260 09:32:33.706244 ==
8261 09:32:33.709377 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 09:32:33.712325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 09:32:33.712828 ==
8264 09:32:33.713177 RX Vref Scan: 0
8265 09:32:33.715602
8266 09:32:33.716159 RX Vref 0 -> 0, step: 1
8267 09:32:33.716630
8268 09:32:33.719355 RX Delay 11 -> 252, step: 4
8269 09:32:33.722260 iDelay=191, Bit 0, Center 128 (75 ~ 182) 108
8270 09:32:33.729311 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8271 09:32:33.732884 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8272 09:32:33.735957 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8273 09:32:33.739038 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8274 09:32:33.742678 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8275 09:32:33.748787 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8276 09:32:33.752204 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8277 09:32:33.756209 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8278 09:32:33.759050 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8279 09:32:33.762354 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8280 09:32:33.768858 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8281 09:32:33.772364 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8282 09:32:33.775697 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8283 09:32:33.779006 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8284 09:32:33.782478 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8285 09:32:33.782958 ==
8286 09:32:33.785920 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 09:32:33.792329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 09:32:33.792787 ==
8289 09:32:33.793124 DQS Delay:
8290 09:32:33.795550 DQS0 = 0, DQS1 = 0
8291 09:32:33.795976 DQM Delay:
8292 09:32:33.798831 DQM0 = 127, DQM1 = 122
8293 09:32:33.799257 DQ Delay:
8294 09:32:33.802391 DQ0 =128, DQ1 =130, DQ2 =122, DQ3 =126
8295 09:32:33.805717 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8296 09:32:33.808926 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8297 09:32:33.812706 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8298 09:32:33.813132
8299 09:32:33.813465
8300 09:32:33.813774
8301 09:32:33.815413 [DramC_TX_OE_Calibration] TA2
8302 09:32:33.819537 Original DQ_B0 (3 6) =30, OEN = 27
8303 09:32:33.822811 Original DQ_B1 (3 6) =30, OEN = 27
8304 09:32:33.825568 24, 0x0, End_B0=24 End_B1=24
8305 09:32:33.826000 25, 0x0, End_B0=25 End_B1=25
8306 09:32:33.828936 26, 0x0, End_B0=26 End_B1=26
8307 09:32:33.832713 27, 0x0, End_B0=27 End_B1=27
8308 09:32:33.836507 28, 0x0, End_B0=28 End_B1=28
8309 09:32:33.838976 29, 0x0, End_B0=29 End_B1=29
8310 09:32:33.839475 30, 0x0, End_B0=30 End_B1=30
8311 09:32:33.842507 31, 0x4141, End_B0=30 End_B1=30
8312 09:32:33.845789 Byte0 end_step=30 best_step=27
8313 09:32:33.848977 Byte1 end_step=30 best_step=27
8314 09:32:33.852575 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 09:32:33.855831 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 09:32:33.856256
8317 09:32:33.856604
8318 09:32:33.862655 [DQSOSCAuto] RK1, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8319 09:32:33.866022 CH0 RK1: MR19=303, MR18=190E
8320 09:32:33.872670 CH0_RK1: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8321 09:32:33.876303 [RxdqsGatingPostProcess] freq 1600
8322 09:32:33.879973 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 09:32:33.882441 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 09:32:33.886262 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 09:32:33.889842 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 09:32:33.892888 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 09:32:33.896250 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 09:32:33.899540 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 09:32:33.902718 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 09:32:33.906181 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 09:32:33.906603 Pre-setting of DQS Precalculation
8332 09:32:33.912690 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 09:32:33.913114 ==
8334 09:32:33.915808 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 09:32:33.919208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 09:32:33.919636 ==
8337 09:32:33.926171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 09:32:33.929453 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 09:32:33.933053 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 09:32:33.939433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 09:32:33.948927 [CA 0] Center 43 (15~72) winsize 58
8342 09:32:33.952290 [CA 1] Center 43 (14~72) winsize 59
8343 09:32:33.955726 [CA 2] Center 38 (9~67) winsize 59
8344 09:32:33.958900 [CA 3] Center 37 (8~66) winsize 59
8345 09:32:33.962068 [CA 4] Center 38 (9~68) winsize 60
8346 09:32:33.965710 [CA 5] Center 37 (8~66) winsize 59
8347 09:32:33.966137
8348 09:32:33.969197 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 09:32:33.969694
8350 09:32:33.972332 [CATrainingPosCal] consider 1 rank data
8351 09:32:33.975898 u2DelayCellTimex100 = 275/100 ps
8352 09:32:33.979253 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8353 09:32:33.985538 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8354 09:32:33.989660 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8355 09:32:33.992637 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8356 09:32:33.996059 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8357 09:32:33.999023 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8358 09:32:33.999448
8359 09:32:34.002458 CA PerBit enable=1, Macro0, CA PI delay=37
8360 09:32:34.002938
8361 09:32:34.005741 [CBTSetCACLKResult] CA Dly = 37
8362 09:32:34.006158 CS Dly: 8 (0~39)
8363 09:32:34.012615 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 09:32:34.015871 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 09:32:34.016323 ==
8366 09:32:34.019176 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 09:32:34.022391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 09:32:34.022842 ==
8369 09:32:34.029253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 09:32:34.033657 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 09:32:34.035952 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 09:32:34.042999 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 09:32:34.052103 [CA 0] Center 42 (13~72) winsize 60
8374 09:32:34.055589 [CA 1] Center 42 (13~71) winsize 59
8375 09:32:34.058910 [CA 2] Center 37 (9~66) winsize 58
8376 09:32:34.062236 [CA 3] Center 37 (8~66) winsize 59
8377 09:32:34.065519 [CA 4] Center 37 (8~67) winsize 60
8378 09:32:34.068879 [CA 5] Center 36 (7~66) winsize 60
8379 09:32:34.069297
8380 09:32:34.071790 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 09:32:34.072235
8382 09:32:34.075272 [CATrainingPosCal] consider 2 rank data
8383 09:32:34.078550 u2DelayCellTimex100 = 275/100 ps
8384 09:32:34.082141 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8385 09:32:34.088833 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8386 09:32:34.091734 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8387 09:32:34.095293 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8388 09:32:34.098637 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8389 09:32:34.101914 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8390 09:32:34.102336
8391 09:32:34.105305 CA PerBit enable=1, Macro0, CA PI delay=37
8392 09:32:34.105720
8393 09:32:34.108500 [CBTSetCACLKResult] CA Dly = 37
8394 09:32:34.112354 CS Dly: 11 (0~45)
8395 09:32:34.115418 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 09:32:34.118772 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 09:32:34.119191
8398 09:32:34.122245 ----->DramcWriteLeveling(PI) begin...
8399 09:32:34.122673 ==
8400 09:32:34.125476 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 09:32:34.128897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 09:32:34.129432 ==
8403 09:32:34.132651 Write leveling (Byte 0): 26 => 26
8404 09:32:34.135640 Write leveling (Byte 1): 28 => 28
8405 09:32:34.138972 DramcWriteLeveling(PI) end<-----
8406 09:32:34.139385
8407 09:32:34.139710 ==
8408 09:32:34.142269 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 09:32:34.148906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 09:32:34.149346 ==
8411 09:32:34.149771 [Gating] SW mode calibration
8412 09:32:34.158606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 09:32:34.162664 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 09:32:34.165950 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 09:32:34.172302 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 09:32:34.175213 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 09:32:34.178781 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 09:32:34.185608 1 4 16 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
8419 09:32:34.189142 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 09:32:34.192070 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 09:32:34.199141 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 09:32:34.202629 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 09:32:34.205416 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 09:32:34.212030 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 09:32:34.215562 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8426 09:32:34.218670 1 5 16 | B1->B0 | 2929 3232 | 0 0 | (1 0) (0 1)
8427 09:32:34.225545 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8428 09:32:34.229333 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 09:32:34.231927 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 09:32:34.235504 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 09:32:34.241959 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 09:32:34.245243 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 09:32:34.248815 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 09:32:34.255741 1 6 16 | B1->B0 | 4444 3333 | 0 0 | (1 1) (0 0)
8435 09:32:34.258621 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 09:32:34.262026 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 09:32:34.268617 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 09:32:34.272251 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 09:32:34.275513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 09:32:34.282464 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 09:32:34.285109 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 09:32:34.288919 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8443 09:32:34.295587 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8444 09:32:34.298837 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 09:32:34.302641 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 09:32:34.309026 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 09:32:34.312002 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 09:32:34.315346 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 09:32:34.322333 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 09:32:34.325525 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 09:32:34.329145 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 09:32:34.332178 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 09:32:34.338692 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 09:32:34.342427 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 09:32:34.345719 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 09:32:34.352692 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 09:32:34.355806 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 09:32:34.358809 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 09:32:34.365398 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8460 09:32:34.365823 Total UI for P1: 0, mck2ui 16
8461 09:32:34.372420 best dqsien dly found for B0: ( 1, 9, 16)
8462 09:32:34.375952 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 09:32:34.379533 Total UI for P1: 0, mck2ui 16
8464 09:32:34.382323 best dqsien dly found for B1: ( 1, 9, 18)
8465 09:32:34.385796 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8466 09:32:34.389129 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8467 09:32:34.389584
8468 09:32:34.392243 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8469 09:32:34.395987 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8470 09:32:34.399332 [Gating] SW calibration Done
8471 09:32:34.399750 ==
8472 09:32:34.402174 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 09:32:34.405934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 09:32:34.406355 ==
8475 09:32:34.408980 RX Vref Scan: 0
8476 09:32:34.409396
8477 09:32:34.412626 RX Vref 0 -> 0, step: 1
8478 09:32:34.413043
8479 09:32:34.413372 RX Delay 0 -> 252, step: 8
8480 09:32:34.419023 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8481 09:32:34.422381 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8482 09:32:34.425824 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8483 09:32:34.429130 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8484 09:32:34.432719 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8485 09:32:34.439425 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8486 09:32:34.442433 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8487 09:32:34.446014 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8488 09:32:34.449714 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8489 09:32:34.452662 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8490 09:32:34.455865 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8491 09:32:34.462664 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8492 09:32:34.466250 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8493 09:32:34.469685 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8494 09:32:34.472566 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8495 09:32:34.479169 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8496 09:32:34.479595 ==
8497 09:32:34.482478 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 09:32:34.485791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 09:32:34.486214 ==
8500 09:32:34.486552 DQS Delay:
8501 09:32:34.489266 DQS0 = 0, DQS1 = 0
8502 09:32:34.489686 DQM Delay:
8503 09:32:34.492789 DQM0 = 134, DQM1 = 127
8504 09:32:34.493215 DQ Delay:
8505 09:32:34.496136 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8506 09:32:34.499383 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8507 09:32:34.503107 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8508 09:32:34.506360 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8509 09:32:34.506815
8510 09:32:34.507152
8511 09:32:34.507461 ==
8512 09:32:34.509748 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 09:32:34.516628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 09:32:34.517114 ==
8515 09:32:34.517454
8516 09:32:34.517767
8517 09:32:34.518066 TX Vref Scan disable
8518 09:32:34.519351 == TX Byte 0 ==
8519 09:32:34.523544 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8520 09:32:34.526192 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8521 09:32:34.529692 == TX Byte 1 ==
8522 09:32:34.533161 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8523 09:32:34.536406 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8524 09:32:34.539462 ==
8525 09:32:34.543056 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 09:32:34.546467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 09:32:34.547018 ==
8528 09:32:34.558771
8529 09:32:34.561876 TX Vref early break, caculate TX vref
8530 09:32:34.565099 TX Vref=16, minBit 8, minWin=21, winSum=359
8531 09:32:34.568798 TX Vref=18, minBit 8, minWin=21, winSum=371
8532 09:32:34.571689 TX Vref=20, minBit 8, minWin=22, winSum=381
8533 09:32:34.575153 TX Vref=22, minBit 11, minWin=22, winSum=388
8534 09:32:34.578401 TX Vref=24, minBit 8, minWin=23, winSum=402
8535 09:32:34.585330 TX Vref=26, minBit 5, minWin=24, winSum=410
8536 09:32:34.588636 TX Vref=28, minBit 15, minWin=25, winSum=419
8537 09:32:34.592131 TX Vref=30, minBit 5, minWin=25, winSum=417
8538 09:32:34.595250 TX Vref=32, minBit 0, minWin=25, winSum=410
8539 09:32:34.598776 TX Vref=34, minBit 9, minWin=23, winSum=395
8540 09:32:34.605269 [TxChooseVref] Worse bit 15, Min win 25, Win sum 419, Final Vref 28
8541 09:32:34.605696
8542 09:32:34.608583 Final TX Range 0 Vref 28
8543 09:32:34.609007
8544 09:32:34.609339 ==
8545 09:32:34.611926 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 09:32:34.615217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 09:32:34.615643 ==
8548 09:32:34.615976
8549 09:32:34.616283
8550 09:32:34.618670 TX Vref Scan disable
8551 09:32:34.625148 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8552 09:32:34.625573 == TX Byte 0 ==
8553 09:32:34.628751 u2DelayCellOfst[0]=17 cells (5 PI)
8554 09:32:34.632079 u2DelayCellOfst[1]=10 cells (3 PI)
8555 09:32:34.635516 u2DelayCellOfst[2]=0 cells (0 PI)
8556 09:32:34.638379 u2DelayCellOfst[3]=7 cells (2 PI)
8557 09:32:34.642237 u2DelayCellOfst[4]=10 cells (3 PI)
8558 09:32:34.645384 u2DelayCellOfst[5]=17 cells (5 PI)
8559 09:32:34.645808 u2DelayCellOfst[6]=17 cells (5 PI)
8560 09:32:34.648763 u2DelayCellOfst[7]=7 cells (2 PI)
8561 09:32:34.655166 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8562 09:32:34.658922 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8563 09:32:34.659342 == TX Byte 1 ==
8564 09:32:34.661758 u2DelayCellOfst[8]=0 cells (0 PI)
8565 09:32:34.664975 u2DelayCellOfst[9]=7 cells (2 PI)
8566 09:32:34.668151 u2DelayCellOfst[10]=10 cells (3 PI)
8567 09:32:34.671858 u2DelayCellOfst[11]=7 cells (2 PI)
8568 09:32:34.675184 u2DelayCellOfst[12]=14 cells (4 PI)
8569 09:32:34.678443 u2DelayCellOfst[13]=14 cells (4 PI)
8570 09:32:34.681946 u2DelayCellOfst[14]=17 cells (5 PI)
8571 09:32:34.685240 u2DelayCellOfst[15]=17 cells (5 PI)
8572 09:32:34.688758 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8573 09:32:34.691967 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8574 09:32:34.695427 DramC Write-DBI on
8575 09:32:34.695862 ==
8576 09:32:34.698697 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 09:32:34.701608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 09:32:34.702062 ==
8579 09:32:34.702431
8580 09:32:34.702770
8581 09:32:34.705419 TX Vref Scan disable
8582 09:32:34.708800 == TX Byte 0 ==
8583 09:32:34.712423 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8584 09:32:34.715164 == TX Byte 1 ==
8585 09:32:34.718782 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8586 09:32:34.719210 DramC Write-DBI off
8587 09:32:34.719542
8588 09:32:34.721887 [DATLAT]
8589 09:32:34.722348 Freq=1600, CH1 RK0
8590 09:32:34.722686
8591 09:32:34.725365 DATLAT Default: 0xf
8592 09:32:34.725785 0, 0xFFFF, sum = 0
8593 09:32:34.728175 1, 0xFFFF, sum = 0
8594 09:32:34.728644 2, 0xFFFF, sum = 0
8595 09:32:34.731666 3, 0xFFFF, sum = 0
8596 09:32:34.732095 4, 0xFFFF, sum = 0
8597 09:32:34.735290 5, 0xFFFF, sum = 0
8598 09:32:34.735718 6, 0xFFFF, sum = 0
8599 09:32:34.738431 7, 0xFFFF, sum = 0
8600 09:32:34.738896 8, 0xFFFF, sum = 0
8601 09:32:34.741755 9, 0xFFFF, sum = 0
8602 09:32:34.744844 10, 0xFFFF, sum = 0
8603 09:32:34.745275 11, 0xFFFF, sum = 0
8604 09:32:34.748434 12, 0xFFFF, sum = 0
8605 09:32:34.748865 13, 0xFFFF, sum = 0
8606 09:32:34.752049 14, 0x0, sum = 1
8607 09:32:34.752476 15, 0x0, sum = 2
8608 09:32:34.755066 16, 0x0, sum = 3
8609 09:32:34.755636 17, 0x0, sum = 4
8610 09:32:34.756084 best_step = 15
8611 09:32:34.756543
8612 09:32:34.758299 ==
8613 09:32:34.758765 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 09:32:34.765174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 09:32:34.765736 ==
8616 09:32:34.766176 RX Vref Scan: 1
8617 09:32:34.766681
8618 09:32:34.768893 Set Vref Range= 24 -> 127
8619 09:32:34.769323
8620 09:32:34.771700 RX Vref 24 -> 127, step: 1
8621 09:32:34.772192
8622 09:32:34.775200 RX Delay 19 -> 252, step: 4
8623 09:32:34.775670
8624 09:32:34.778481 Set Vref, RX VrefLevel [Byte0]: 24
8625 09:32:34.782069 [Byte1]: 24
8626 09:32:34.782679
8627 09:32:34.784953 Set Vref, RX VrefLevel [Byte0]: 25
8628 09:32:34.788557 [Byte1]: 25
8629 09:32:34.788976
8630 09:32:34.791698 Set Vref, RX VrefLevel [Byte0]: 26
8631 09:32:34.794847 [Byte1]: 26
8632 09:32:34.798632
8633 09:32:34.799097 Set Vref, RX VrefLevel [Byte0]: 27
8634 09:32:34.801523 [Byte1]: 27
8635 09:32:34.805962
8636 09:32:34.806635 Set Vref, RX VrefLevel [Byte0]: 28
8637 09:32:34.809330 [Byte1]: 28
8638 09:32:34.813625
8639 09:32:34.814254 Set Vref, RX VrefLevel [Byte0]: 29
8640 09:32:34.817035 [Byte1]: 29
8641 09:32:34.820911
8642 09:32:34.821447 Set Vref, RX VrefLevel [Byte0]: 30
8643 09:32:34.824259 [Byte1]: 30
8644 09:32:34.828541
8645 09:32:34.828986 Set Vref, RX VrefLevel [Byte0]: 31
8646 09:32:34.831955 [Byte1]: 31
8647 09:32:34.836358
8648 09:32:34.836790 Set Vref, RX VrefLevel [Byte0]: 32
8649 09:32:34.839795 [Byte1]: 32
8650 09:32:34.843956
8651 09:32:34.844415 Set Vref, RX VrefLevel [Byte0]: 33
8652 09:32:34.846903 [Byte1]: 33
8653 09:32:34.851419
8654 09:32:34.851841 Set Vref, RX VrefLevel [Byte0]: 34
8655 09:32:34.854314 [Byte1]: 34
8656 09:32:34.858647
8657 09:32:34.859113 Set Vref, RX VrefLevel [Byte0]: 35
8658 09:32:34.862074 [Byte1]: 35
8659 09:32:34.866617
8660 09:32:34.867086 Set Vref, RX VrefLevel [Byte0]: 36
8661 09:32:34.869631 [Byte1]: 36
8662 09:32:34.873943
8663 09:32:34.874365 Set Vref, RX VrefLevel [Byte0]: 37
8664 09:32:34.877612 [Byte1]: 37
8665 09:32:34.881454
8666 09:32:34.881876 Set Vref, RX VrefLevel [Byte0]: 38
8667 09:32:34.884890 [Byte1]: 38
8668 09:32:34.889745
8669 09:32:34.890171 Set Vref, RX VrefLevel [Byte0]: 39
8670 09:32:34.892503 [Byte1]: 39
8671 09:32:34.896627
8672 09:32:34.897048 Set Vref, RX VrefLevel [Byte0]: 40
8673 09:32:34.900463 [Byte1]: 40
8674 09:32:34.904527
8675 09:32:34.904968 Set Vref, RX VrefLevel [Byte0]: 41
8676 09:32:34.908210 [Byte1]: 41
8677 09:32:34.912085
8678 09:32:34.912507 Set Vref, RX VrefLevel [Byte0]: 42
8679 09:32:34.915560 [Byte1]: 42
8680 09:32:34.919620
8681 09:32:34.920066 Set Vref, RX VrefLevel [Byte0]: 43
8682 09:32:34.922913 [Byte1]: 43
8683 09:32:34.926779
8684 09:32:34.930423 Set Vref, RX VrefLevel [Byte0]: 44
8685 09:32:34.933328 [Byte1]: 44
8686 09:32:34.933745
8687 09:32:34.937070 Set Vref, RX VrefLevel [Byte0]: 45
8688 09:32:34.939908 [Byte1]: 45
8689 09:32:34.940464
8690 09:32:34.943356 Set Vref, RX VrefLevel [Byte0]: 46
8691 09:32:34.946809 [Byte1]: 46
8692 09:32:34.947291
8693 09:32:34.950041 Set Vref, RX VrefLevel [Byte0]: 47
8694 09:32:34.953300 [Byte1]: 47
8695 09:32:34.957461
8696 09:32:34.957879 Set Vref, RX VrefLevel [Byte0]: 48
8697 09:32:34.960925 [Byte1]: 48
8698 09:32:34.965047
8699 09:32:34.965464 Set Vref, RX VrefLevel [Byte0]: 49
8700 09:32:34.968459 [Byte1]: 49
8701 09:32:34.972471
8702 09:32:34.972886 Set Vref, RX VrefLevel [Byte0]: 50
8703 09:32:34.975594 [Byte1]: 50
8704 09:32:34.980047
8705 09:32:34.980463 Set Vref, RX VrefLevel [Byte0]: 51
8706 09:32:34.983430 [Byte1]: 51
8707 09:32:34.987843
8708 09:32:34.988257 Set Vref, RX VrefLevel [Byte0]: 52
8709 09:32:34.991085 [Byte1]: 52
8710 09:32:34.995264
8711 09:32:34.995775 Set Vref, RX VrefLevel [Byte0]: 53
8712 09:32:34.998452 [Byte1]: 53
8713 09:32:35.002683
8714 09:32:35.003145 Set Vref, RX VrefLevel [Byte0]: 54
8715 09:32:35.005966 [Byte1]: 54
8716 09:32:35.010783
8717 09:32:35.011255 Set Vref, RX VrefLevel [Byte0]: 55
8718 09:32:35.013701 [Byte1]: 55
8719 09:32:35.018149
8720 09:32:35.018565 Set Vref, RX VrefLevel [Byte0]: 56
8721 09:32:35.021384 [Byte1]: 56
8722 09:32:35.025146
8723 09:32:35.025741 Set Vref, RX VrefLevel [Byte0]: 57
8724 09:32:35.028707 [Byte1]: 57
8725 09:32:35.033010
8726 09:32:35.033471 Set Vref, RX VrefLevel [Byte0]: 58
8727 09:32:35.036473 [Byte1]: 58
8728 09:32:35.040846
8729 09:32:35.041261 Set Vref, RX VrefLevel [Byte0]: 59
8730 09:32:35.043903 [Byte1]: 59
8731 09:32:35.048402
8732 09:32:35.048826 Set Vref, RX VrefLevel [Byte0]: 60
8733 09:32:35.051316 [Byte1]: 60
8734 09:32:35.055871
8735 09:32:35.059137 Set Vref, RX VrefLevel [Byte0]: 61
8736 09:32:35.059560 [Byte1]: 61
8737 09:32:35.063501
8738 09:32:35.064016 Set Vref, RX VrefLevel [Byte0]: 62
8739 09:32:35.066894 [Byte1]: 62
8740 09:32:35.071044
8741 09:32:35.071579 Set Vref, RX VrefLevel [Byte0]: 63
8742 09:32:35.074017 [Byte1]: 63
8743 09:32:35.078413
8744 09:32:35.078976 Set Vref, RX VrefLevel [Byte0]: 64
8745 09:32:35.081626 [Byte1]: 64
8746 09:32:35.085856
8747 09:32:35.086305 Set Vref, RX VrefLevel [Byte0]: 65
8748 09:32:35.089100 [Byte1]: 65
8749 09:32:35.093673
8750 09:32:35.094293 Set Vref, RX VrefLevel [Byte0]: 66
8751 09:32:35.096731 [Byte1]: 66
8752 09:32:35.101285
8753 09:32:35.101701 Set Vref, RX VrefLevel [Byte0]: 67
8754 09:32:35.104617 [Byte1]: 67
8755 09:32:35.108991
8756 09:32:35.109452 Set Vref, RX VrefLevel [Byte0]: 68
8757 09:32:35.112250 [Byte1]: 68
8758 09:32:35.116205
8759 09:32:35.116622 Set Vref, RX VrefLevel [Byte0]: 69
8760 09:32:35.119422 [Byte1]: 69
8761 09:32:35.123806
8762 09:32:35.124224 Set Vref, RX VrefLevel [Byte0]: 70
8763 09:32:35.127297 [Byte1]: 70
8764 09:32:35.132105
8765 09:32:35.132620 Set Vref, RX VrefLevel [Byte0]: 71
8766 09:32:35.134943 [Byte1]: 71
8767 09:32:35.139163
8768 09:32:35.139695 Set Vref, RX VrefLevel [Byte0]: 72
8769 09:32:35.142608 [Byte1]: 72
8770 09:32:35.146441
8771 09:32:35.147010 Set Vref, RX VrefLevel [Byte0]: 73
8772 09:32:35.149694 [Byte1]: 73
8773 09:32:35.154457
8774 09:32:35.155022 Set Vref, RX VrefLevel [Byte0]: 74
8775 09:32:35.157322 [Byte1]: 74
8776 09:32:35.161829
8777 09:32:35.162380 Set Vref, RX VrefLevel [Byte0]: 75
8778 09:32:35.164935 [Byte1]: 75
8779 09:32:35.169495
8780 09:32:35.170148 Set Vref, RX VrefLevel [Byte0]: 76
8781 09:32:35.172842 [Byte1]: 76
8782 09:32:35.176714
8783 09:32:35.177172 Final RX Vref Byte 0 = 61 to rank0
8784 09:32:35.180379 Final RX Vref Byte 1 = 56 to rank0
8785 09:32:35.183267 Final RX Vref Byte 0 = 61 to rank1
8786 09:32:35.186505 Final RX Vref Byte 1 = 56 to rank1==
8787 09:32:35.190268 Dram Type= 6, Freq= 0, CH_1, rank 0
8788 09:32:35.197095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 09:32:35.197586 ==
8790 09:32:35.197920 DQS Delay:
8791 09:32:35.198231 DQS0 = 0, DQS1 = 0
8792 09:32:35.200671 DQM Delay:
8793 09:32:35.201112 DQM0 = 131, DQM1 = 124
8794 09:32:35.203705 DQ Delay:
8795 09:32:35.206941 DQ0 =136, DQ1 =124, DQ2 =120, DQ3 =130
8796 09:32:35.210519 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8797 09:32:35.213942 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8798 09:32:35.217263 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8799 09:32:35.217755
8800 09:32:35.218090
8801 09:32:35.218465
8802 09:32:35.220425 [DramC_TX_OE_Calibration] TA2
8803 09:32:35.223824 Original DQ_B0 (3 6) =30, OEN = 27
8804 09:32:35.226892 Original DQ_B1 (3 6) =30, OEN = 27
8805 09:32:35.230364 24, 0x0, End_B0=24 End_B1=24
8806 09:32:35.230854 25, 0x0, End_B0=25 End_B1=25
8807 09:32:35.233516 26, 0x0, End_B0=26 End_B1=26
8808 09:32:35.237111 27, 0x0, End_B0=27 End_B1=27
8809 09:32:35.240165 28, 0x0, End_B0=28 End_B1=28
8810 09:32:35.240599 29, 0x0, End_B0=29 End_B1=29
8811 09:32:35.243978 30, 0x0, End_B0=30 End_B1=30
8812 09:32:35.247082 31, 0x4141, End_B0=30 End_B1=30
8813 09:32:35.250596 Byte0 end_step=30 best_step=27
8814 09:32:35.253562 Byte1 end_step=30 best_step=27
8815 09:32:35.257011 Byte0 TX OE(2T, 0.5T) = (3, 3)
8816 09:32:35.257437 Byte1 TX OE(2T, 0.5T) = (3, 3)
8817 09:32:35.257788
8818 09:32:35.258164
8819 09:32:35.266923 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8820 09:32:35.270698 CH1 RK0: MR19=302, MR18=12FE
8821 09:32:35.277017 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8822 09:32:35.277455
8823 09:32:35.280292 ----->DramcWriteLeveling(PI) begin...
8824 09:32:35.280754 ==
8825 09:32:35.283953 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 09:32:35.287363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 09:32:35.287799 ==
8828 09:32:35.290842 Write leveling (Byte 0): 25 => 25
8829 09:32:35.293984 Write leveling (Byte 1): 26 => 26
8830 09:32:35.297390 DramcWriteLeveling(PI) end<-----
8831 09:32:35.297910
8832 09:32:35.298437 ==
8833 09:32:35.300813 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 09:32:35.304115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 09:32:35.304579 ==
8836 09:32:35.307201 [Gating] SW mode calibration
8837 09:32:35.314409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8838 09:32:35.320376 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8839 09:32:35.323838 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 09:32:35.326988 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 09:32:35.334079 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8842 09:32:35.337011 1 4 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
8843 09:32:35.340468 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 09:32:35.344059 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 09:32:35.350520 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 09:32:35.353750 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 09:32:35.357183 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 09:32:35.363944 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8849 09:32:35.367217 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8850 09:32:35.370409 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8851 09:32:35.377094 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 09:32:35.380480 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 09:32:35.383996 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 09:32:35.390261 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 09:32:35.394118 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 09:32:35.397415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 09:32:35.404424 1 6 8 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (1 1)
8858 09:32:35.407261 1 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8859 09:32:35.410919 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 09:32:35.417429 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 09:32:35.420764 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 09:32:35.423549 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 09:32:35.430348 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 09:32:35.433599 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8865 09:32:35.436770 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8866 09:32:35.443550 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8867 09:32:35.447216 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8868 09:32:35.450505 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 09:32:35.456839 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 09:32:35.459855 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 09:32:35.463678 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 09:32:35.466845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 09:32:35.473534 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 09:32:35.476897 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 09:32:35.480011 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 09:32:35.486659 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 09:32:35.490141 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 09:32:35.493343 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 09:32:35.500268 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 09:32:35.503681 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 09:32:35.506612 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8882 09:32:35.513360 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8883 09:32:35.513927 Total UI for P1: 0, mck2ui 16
8884 09:32:35.519934 best dqsien dly found for B0: ( 1, 9, 8)
8885 09:32:35.523769 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8886 09:32:35.526474 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 09:32:35.529879 Total UI for P1: 0, mck2ui 16
8888 09:32:35.533457 best dqsien dly found for B1: ( 1, 9, 12)
8889 09:32:35.536823 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8890 09:32:35.540000 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8891 09:32:35.540460
8892 09:32:35.543328 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8893 09:32:35.550296 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8894 09:32:35.550713 [Gating] SW calibration Done
8895 09:32:35.551097 ==
8896 09:32:35.553042 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 09:32:35.559878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 09:32:35.560303 ==
8899 09:32:35.560635 RX Vref Scan: 0
8900 09:32:35.560941
8901 09:32:35.563505 RX Vref 0 -> 0, step: 1
8902 09:32:35.563920
8903 09:32:35.567187 RX Delay 0 -> 252, step: 8
8904 09:32:35.569984 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8905 09:32:35.573738 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8906 09:32:35.576909 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8907 09:32:35.583532 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8908 09:32:35.586972 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8909 09:32:35.590360 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8910 09:32:35.593793 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8911 09:32:35.597106 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8912 09:32:35.600386 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8913 09:32:35.607052 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8914 09:32:35.610155 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8915 09:32:35.613745 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8916 09:32:35.616869 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8917 09:32:35.620294 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8918 09:32:35.627102 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8919 09:32:35.630428 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8920 09:32:35.630878 ==
8921 09:32:35.633748 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 09:32:35.637376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 09:32:35.637862 ==
8924 09:32:35.640555 DQS Delay:
8925 09:32:35.640970 DQS0 = 0, DQS1 = 0
8926 09:32:35.641298 DQM Delay:
8927 09:32:35.643448 DQM0 = 133, DQM1 = 127
8928 09:32:35.643887 DQ Delay:
8929 09:32:35.647035 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8930 09:32:35.650403 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8931 09:32:35.653578 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8932 09:32:35.660345 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8933 09:32:35.660825
8934 09:32:35.661178
8935 09:32:35.661491 ==
8936 09:32:35.663730 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 09:32:35.666792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 09:32:35.667218 ==
8939 09:32:35.667544
8940 09:32:35.667848
8941 09:32:35.670051 TX Vref Scan disable
8942 09:32:35.670467 == TX Byte 0 ==
8943 09:32:35.677033 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8944 09:32:35.680308 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8945 09:32:35.680729 == TX Byte 1 ==
8946 09:32:35.687404 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8947 09:32:35.690039 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 09:32:35.690462 ==
8949 09:32:35.693807 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 09:32:35.697162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 09:32:35.697658 ==
8952 09:32:35.712075
8953 09:32:35.714783 TX Vref early break, caculate TX vref
8954 09:32:35.718452 TX Vref=16, minBit 1, minWin=23, winSum=379
8955 09:32:35.721688 TX Vref=18, minBit 6, minWin=23, winSum=387
8956 09:32:35.725107 TX Vref=20, minBit 5, minWin=24, winSum=398
8957 09:32:35.727933 TX Vref=22, minBit 15, minWin=24, winSum=406
8958 09:32:35.731699 TX Vref=24, minBit 15, minWin=24, winSum=414
8959 09:32:35.738230 TX Vref=26, minBit 0, minWin=25, winSum=422
8960 09:32:35.741657 TX Vref=28, minBit 0, minWin=26, winSum=428
8961 09:32:35.744899 TX Vref=30, minBit 13, minWin=25, winSum=425
8962 09:32:35.748384 TX Vref=32, minBit 0, minWin=25, winSum=418
8963 09:32:35.751778 TX Vref=34, minBit 5, minWin=24, winSum=410
8964 09:32:35.754770 TX Vref=36, minBit 0, minWin=23, winSum=399
8965 09:32:35.761444 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8966 09:32:35.761917
8967 09:32:35.764759 Final TX Range 0 Vref 28
8968 09:32:35.765348
8969 09:32:35.765928 ==
8970 09:32:35.767962 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 09:32:35.771673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 09:32:35.772347 ==
8973 09:32:35.772726
8974 09:32:35.774842
8975 09:32:35.775272 TX Vref Scan disable
8976 09:32:35.781338 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8977 09:32:35.781969 == TX Byte 0 ==
8978 09:32:35.784481 u2DelayCellOfst[0]=17 cells (5 PI)
8979 09:32:35.788102 u2DelayCellOfst[1]=10 cells (3 PI)
8980 09:32:35.791046 u2DelayCellOfst[2]=0 cells (0 PI)
8981 09:32:35.794598 u2DelayCellOfst[3]=7 cells (2 PI)
8982 09:32:35.798004 u2DelayCellOfst[4]=7 cells (2 PI)
8983 09:32:35.801437 u2DelayCellOfst[5]=21 cells (6 PI)
8984 09:32:35.804699 u2DelayCellOfst[6]=17 cells (5 PI)
8985 09:32:35.807752 u2DelayCellOfst[7]=7 cells (2 PI)
8986 09:32:35.811662 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8987 09:32:35.814774 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8988 09:32:35.817995 == TX Byte 1 ==
8989 09:32:35.821260 u2DelayCellOfst[8]=0 cells (0 PI)
8990 09:32:35.821790 u2DelayCellOfst[9]=3 cells (1 PI)
8991 09:32:35.824775 u2DelayCellOfst[10]=10 cells (3 PI)
8992 09:32:35.828140 u2DelayCellOfst[11]=7 cells (2 PI)
8993 09:32:35.831413 u2DelayCellOfst[12]=14 cells (4 PI)
8994 09:32:35.834832 u2DelayCellOfst[13]=14 cells (4 PI)
8995 09:32:35.837904 u2DelayCellOfst[14]=17 cells (5 PI)
8996 09:32:35.841504 u2DelayCellOfst[15]=14 cells (4 PI)
8997 09:32:35.844741 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8998 09:32:35.851427 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8999 09:32:35.852008 DramC Write-DBI on
9000 09:32:35.852513 ==
9001 09:32:35.854309 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 09:32:35.860989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 09:32:35.861559 ==
9004 09:32:35.862085
9005 09:32:35.862411
9006 09:32:35.862712 TX Vref Scan disable
9007 09:32:35.864890 == TX Byte 0 ==
9008 09:32:35.868340 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9009 09:32:35.871597 == TX Byte 1 ==
9010 09:32:35.875297 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9011 09:32:35.875716 DramC Write-DBI off
9012 09:32:35.878099
9013 09:32:35.878615 [DATLAT]
9014 09:32:35.878994 Freq=1600, CH1 RK1
9015 09:32:35.879309
9016 09:32:35.881711 DATLAT Default: 0xf
9017 09:32:35.882112 0, 0xFFFF, sum = 0
9018 09:32:35.885068 1, 0xFFFF, sum = 0
9019 09:32:35.885475 2, 0xFFFF, sum = 0
9020 09:32:35.888432 3, 0xFFFF, sum = 0
9021 09:32:35.888858 4, 0xFFFF, sum = 0
9022 09:32:35.891353 5, 0xFFFF, sum = 0
9023 09:32:35.894713 6, 0xFFFF, sum = 0
9024 09:32:35.895260 7, 0xFFFF, sum = 0
9025 09:32:35.898593 8, 0xFFFF, sum = 0
9026 09:32:35.899134 9, 0xFFFF, sum = 0
9027 09:32:35.901830 10, 0xFFFF, sum = 0
9028 09:32:35.902257 11, 0xFFFF, sum = 0
9029 09:32:35.905437 12, 0xFFFF, sum = 0
9030 09:32:35.905866 13, 0xFFFF, sum = 0
9031 09:32:35.908635 14, 0x0, sum = 1
9032 09:32:35.909060 15, 0x0, sum = 2
9033 09:32:35.911472 16, 0x0, sum = 3
9034 09:32:35.911899 17, 0x0, sum = 4
9035 09:32:35.915167 best_step = 15
9036 09:32:35.915585
9037 09:32:35.915913 ==
9038 09:32:35.918222 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 09:32:35.921865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 09:32:35.922283 ==
9041 09:32:35.922666 RX Vref Scan: 0
9042 09:32:35.923078
9043 09:32:35.924734 RX Vref 0 -> 0, step: 1
9044 09:32:35.925133
9045 09:32:35.928316 RX Delay 11 -> 252, step: 4
9046 09:32:35.931765 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9047 09:32:35.935554 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9048 09:32:35.941934 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9049 09:32:35.945445 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9050 09:32:35.948740 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9051 09:32:35.951666 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9052 09:32:35.955154 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9053 09:32:35.962317 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9054 09:32:35.965218 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9055 09:32:35.968579 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9056 09:32:35.971888 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9057 09:32:35.975216 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
9058 09:32:35.981908 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9059 09:32:35.985391 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9060 09:32:35.988978 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9061 09:32:35.992347 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9062 09:32:35.992770 ==
9063 09:32:35.995391 Dram Type= 6, Freq= 0, CH_1, rank 1
9064 09:32:35.998826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9065 09:32:36.002656 ==
9066 09:32:36.003349 DQS Delay:
9067 09:32:36.003848 DQS0 = 0, DQS1 = 0
9068 09:32:36.005232 DQM Delay:
9069 09:32:36.005646 DQM0 = 130, DQM1 = 126
9070 09:32:36.009057 DQ Delay:
9071 09:32:36.012819 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =130
9072 09:32:36.015318 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
9073 09:32:36.018628 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =116
9074 09:32:36.022379 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9075 09:32:36.022831
9076 09:32:36.023167
9077 09:32:36.023475
9078 09:32:36.025927 [DramC_TX_OE_Calibration] TA2
9079 09:32:36.028702 Original DQ_B0 (3 6) =30, OEN = 27
9080 09:32:36.032595 Original DQ_B1 (3 6) =30, OEN = 27
9081 09:32:36.033141 24, 0x0, End_B0=24 End_B1=24
9082 09:32:36.035488 25, 0x0, End_B0=25 End_B1=25
9083 09:32:36.039303 26, 0x0, End_B0=26 End_B1=26
9084 09:32:36.042570 27, 0x0, End_B0=27 End_B1=27
9085 09:32:36.046140 28, 0x0, End_B0=28 End_B1=28
9086 09:32:36.046668 29, 0x0, End_B0=29 End_B1=29
9087 09:32:36.048996 30, 0x0, End_B0=30 End_B1=30
9088 09:32:36.052166 31, 0x4141, End_B0=30 End_B1=30
9089 09:32:36.055936 Byte0 end_step=30 best_step=27
9090 09:32:36.059293 Byte1 end_step=30 best_step=27
9091 09:32:36.062426 Byte0 TX OE(2T, 0.5T) = (3, 3)
9092 09:32:36.063081 Byte1 TX OE(2T, 0.5T) = (3, 3)
9093 09:32:36.063515
9094 09:32:36.063833
9095 09:32:36.072621 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9096 09:32:36.075652 CH1 RK1: MR19=303, MR18=1117
9097 09:32:36.079008 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9098 09:32:36.082591 [RxdqsGatingPostProcess] freq 1600
9099 09:32:36.089098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9100 09:32:36.092378 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 09:32:36.095743 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 09:32:36.099083 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 09:32:36.102330 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 09:32:36.105833 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 09:32:36.106252 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 09:32:36.109526 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 09:32:36.112761 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 09:32:36.116028 Pre-setting of DQS Precalculation
9109 09:32:36.122413 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9110 09:32:36.129288 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9111 09:32:36.135637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 09:32:36.136184
9113 09:32:36.136707
9114 09:32:36.139240 [Calibration Summary] 3200 Mbps
9115 09:32:36.139766 CH 0, Rank 0
9116 09:32:36.142719 SW Impedance : PASS
9117 09:32:36.145655 DUTY Scan : NO K
9118 09:32:36.146283 ZQ Calibration : PASS
9119 09:32:36.149346 Jitter Meter : NO K
9120 09:32:36.152507 CBT Training : PASS
9121 09:32:36.153173 Write leveling : PASS
9122 09:32:36.155929 RX DQS gating : PASS
9123 09:32:36.159038 RX DQ/DQS(RDDQC) : PASS
9124 09:32:36.159614 TX DQ/DQS : PASS
9125 09:32:36.162372 RX DATLAT : PASS
9126 09:32:36.165740 RX DQ/DQS(Engine): PASS
9127 09:32:36.166290 TX OE : PASS
9128 09:32:36.166794 All Pass.
9129 09:32:36.169428
9130 09:32:36.169836 CH 0, Rank 1
9131 09:32:36.170161 SW Impedance : PASS
9132 09:32:36.172456 DUTY Scan : NO K
9133 09:32:36.175936 ZQ Calibration : PASS
9134 09:32:36.176347 Jitter Meter : NO K
9135 09:32:36.179215 CBT Training : PASS
9136 09:32:36.182689 Write leveling : PASS
9137 09:32:36.183151 RX DQS gating : PASS
9138 09:32:36.185847 RX DQ/DQS(RDDQC) : PASS
9139 09:32:36.189497 TX DQ/DQS : PASS
9140 09:32:36.190064 RX DATLAT : PASS
9141 09:32:36.192209 RX DQ/DQS(Engine): PASS
9142 09:32:36.195678 TX OE : PASS
9143 09:32:36.196094 All Pass.
9144 09:32:36.196421
9145 09:32:36.196722 CH 1, Rank 0
9146 09:32:36.199098 SW Impedance : PASS
9147 09:32:36.202598 DUTY Scan : NO K
9148 09:32:36.203134 ZQ Calibration : PASS
9149 09:32:36.205693 Jitter Meter : NO K
9150 09:32:36.209169 CBT Training : PASS
9151 09:32:36.209619 Write leveling : PASS
9152 09:32:36.212489 RX DQS gating : PASS
9153 09:32:36.212905 RX DQ/DQS(RDDQC) : PASS
9154 09:32:36.215905 TX DQ/DQS : PASS
9155 09:32:36.219213 RX DATLAT : PASS
9156 09:32:36.219663 RX DQ/DQS(Engine): PASS
9157 09:32:36.222453 TX OE : PASS
9158 09:32:36.222911 All Pass.
9159 09:32:36.223247
9160 09:32:36.225921 CH 1, Rank 1
9161 09:32:36.226332 SW Impedance : PASS
9162 09:32:36.229317 DUTY Scan : NO K
9163 09:32:36.232892 ZQ Calibration : PASS
9164 09:32:36.233367 Jitter Meter : NO K
9165 09:32:36.235862 CBT Training : PASS
9166 09:32:36.239322 Write leveling : PASS
9167 09:32:36.239808 RX DQS gating : PASS
9168 09:32:36.242717 RX DQ/DQS(RDDQC) : PASS
9169 09:32:36.245755 TX DQ/DQS : PASS
9170 09:32:36.246175 RX DATLAT : PASS
9171 09:32:36.249119 RX DQ/DQS(Engine): PASS
9172 09:32:36.249550 TX OE : PASS
9173 09:32:36.252866 All Pass.
9174 09:32:36.253281
9175 09:32:36.253626 DramC Write-DBI on
9176 09:32:36.256353 PER_BANK_REFRESH: Hybrid Mode
9177 09:32:36.259535 TX_TRACKING: ON
9178 09:32:36.266152 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9179 09:32:36.276093 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9180 09:32:36.283014 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9181 09:32:36.285845 [FAST_K] Save calibration result to emmc
9182 09:32:36.289577 sync common calibartion params.
9183 09:32:36.290041 sync cbt_mode0:1, 1:1
9184 09:32:36.292975 dram_init: ddr_geometry: 2
9185 09:32:36.296441 dram_init: ddr_geometry: 2
9186 09:32:36.299486 dram_init: ddr_geometry: 2
9187 09:32:36.299900 0:dram_rank_size:100000000
9188 09:32:36.302791 1:dram_rank_size:100000000
9189 09:32:36.309404 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9190 09:32:36.309856 DFS_SHUFFLE_HW_MODE: ON
9191 09:32:36.312657 dramc_set_vcore_voltage set vcore to 725000
9192 09:32:36.315954 Read voltage for 1600, 0
9193 09:32:36.316387 Vio18 = 0
9194 09:32:36.319174 Vcore = 725000
9195 09:32:36.319590 Vdram = 0
9196 09:32:36.319918 Vddq = 0
9197 09:32:36.322478 Vmddr = 0
9198 09:32:36.322947 switch to 3200 Mbps bootup
9199 09:32:36.325825 [DramcRunTimeConfig]
9200 09:32:36.326260 PHYPLL
9201 09:32:36.329428 DPM_CONTROL_AFTERK: ON
9202 09:32:36.329843 PER_BANK_REFRESH: ON
9203 09:32:36.332661 REFRESH_OVERHEAD_REDUCTION: ON
9204 09:32:36.335896 CMD_PICG_NEW_MODE: OFF
9205 09:32:36.336311 XRTWTW_NEW_MODE: ON
9206 09:32:36.339372 XRTRTR_NEW_MODE: ON
9207 09:32:36.339784 TX_TRACKING: ON
9208 09:32:36.342704 RDSEL_TRACKING: OFF
9209 09:32:36.346119 DQS Precalculation for DVFS: ON
9210 09:32:36.346534 RX_TRACKING: OFF
9211 09:32:36.349866 HW_GATING DBG: ON
9212 09:32:36.350306 ZQCS_ENABLE_LP4: ON
9213 09:32:36.353075 RX_PICG_NEW_MODE: ON
9214 09:32:36.353493 TX_PICG_NEW_MODE: ON
9215 09:32:36.355995 ENABLE_RX_DCM_DPHY: ON
9216 09:32:36.359149 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9217 09:32:36.363024 DUMMY_READ_FOR_TRACKING: OFF
9218 09:32:36.363660 !!! SPM_CONTROL_AFTERK: OFF
9219 09:32:36.365920 !!! SPM could not control APHY
9220 09:32:36.369451 IMPEDANCE_TRACKING: ON
9221 09:32:36.369908 TEMP_SENSOR: ON
9222 09:32:36.372755 HW_SAVE_FOR_SR: OFF
9223 09:32:36.376071 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9224 09:32:36.379574 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9225 09:32:36.380123 Read ODT Tracking: ON
9226 09:32:36.382831 Refresh Rate DeBounce: ON
9227 09:32:36.386231 DFS_NO_QUEUE_FLUSH: ON
9228 09:32:36.389569 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9229 09:32:36.390076 ENABLE_DFS_RUNTIME_MRW: OFF
9230 09:32:36.392908 DDR_RESERVE_NEW_MODE: ON
9231 09:32:36.396135 MR_CBT_SWITCH_FREQ: ON
9232 09:32:36.396529 =========================
9233 09:32:36.416518 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9234 09:32:36.420077 dram_init: ddr_geometry: 2
9235 09:32:36.438127 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9236 09:32:36.441130 dram_init: dram init end (result: 0)
9237 09:32:36.447716 DRAM-K: Full calibration passed in 24573 msecs
9238 09:32:36.451377 MRC: failed to locate region type 0.
9239 09:32:36.451826 DRAM rank0 size:0x100000000,
9240 09:32:36.454679 DRAM rank1 size=0x100000000
9241 09:32:36.464521 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9242 09:32:36.471547 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9243 09:32:36.478041 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9244 09:32:36.484929 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9245 09:32:36.487904 DRAM rank0 size:0x100000000,
9246 09:32:36.491260 DRAM rank1 size=0x100000000
9247 09:32:36.491699 CBMEM:
9248 09:32:36.494719 IMD: root @ 0xfffff000 254 entries.
9249 09:32:36.497997 IMD: root @ 0xffffec00 62 entries.
9250 09:32:36.501662 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9251 09:32:36.504838 WARNING: RO_VPD is uninitialized or empty.
9252 09:32:36.511435 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9253 09:32:36.518137 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9254 09:32:36.530933 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9255 09:32:36.542290 BS: romstage times (exec / console): total (unknown) / 24080 ms
9256 09:32:36.542883
9257 09:32:36.543299
9258 09:32:36.552010 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9259 09:32:36.555667 ARM64: Exception handlers installed.
9260 09:32:36.559300 ARM64: Testing exception
9261 09:32:36.562364 ARM64: Done test exception
9262 09:32:36.562846 Enumerating buses...
9263 09:32:36.565783 Show all devs... Before device enumeration.
9264 09:32:36.569337 Root Device: enabled 1
9265 09:32:36.572302 CPU_CLUSTER: 0: enabled 1
9266 09:32:36.572822 CPU: 00: enabled 1
9267 09:32:36.575736 Compare with tree...
9268 09:32:36.576159 Root Device: enabled 1
9269 09:32:36.578862 CPU_CLUSTER: 0: enabled 1
9270 09:32:36.582084 CPU: 00: enabled 1
9271 09:32:36.582693 Root Device scanning...
9272 09:32:36.585356 scan_static_bus for Root Device
9273 09:32:36.588878 CPU_CLUSTER: 0 enabled
9274 09:32:36.592024 scan_static_bus for Root Device done
9275 09:32:36.595619 scan_bus: bus Root Device finished in 8 msecs
9276 09:32:36.596170 done
9277 09:32:36.601987 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9278 09:32:36.605499 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9279 09:32:36.611985 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9280 09:32:36.615325 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9281 09:32:36.618822 Allocating resources...
9282 09:32:36.619237 Reading resources...
9283 09:32:36.625237 Root Device read_resources bus 0 link: 0
9284 09:32:36.625658 DRAM rank0 size:0x100000000,
9285 09:32:36.628587 DRAM rank1 size=0x100000000
9286 09:32:36.631982 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9287 09:32:36.635280 CPU: 00 missing read_resources
9288 09:32:36.638716 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9289 09:32:36.645256 Root Device read_resources bus 0 link: 0 done
9290 09:32:36.645677 Done reading resources.
9291 09:32:36.652377 Show resources in subtree (Root Device)...After reading.
9292 09:32:36.655744 Root Device child on link 0 CPU_CLUSTER: 0
9293 09:32:36.659104 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 09:32:36.669188 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 09:32:36.669617 CPU: 00
9296 09:32:36.672608 Root Device assign_resources, bus 0 link: 0
9297 09:32:36.675582 CPU_CLUSTER: 0 missing set_resources
9298 09:32:36.679004 Root Device assign_resources, bus 0 link: 0 done
9299 09:32:36.682481 Done setting resources.
9300 09:32:36.689090 Show resources in subtree (Root Device)...After assigning values.
9301 09:32:36.692491 Root Device child on link 0 CPU_CLUSTER: 0
9302 09:32:36.695631 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 09:32:36.705554 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 09:32:36.705983 CPU: 00
9305 09:32:36.709122 Done allocating resources.
9306 09:32:36.712500 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9307 09:32:36.715646 Enabling resources...
9308 09:32:36.716171 done.
9309 09:32:36.719178 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9310 09:32:36.722201 Initializing devices...
9311 09:32:36.725651 Root Device init
9312 09:32:36.726072 init hardware done!
9313 09:32:36.728793 0x00000018: ctrlr->caps
9314 09:32:36.729227 52.000 MHz: ctrlr->f_max
9315 09:32:36.732176 0.400 MHz: ctrlr->f_min
9316 09:32:36.735509 0x40ff8080: ctrlr->voltages
9317 09:32:36.735943 sclk: 390625
9318 09:32:36.738696 Bus Width = 1
9319 09:32:36.739157 sclk: 390625
9320 09:32:36.739494 Bus Width = 1
9321 09:32:36.742191 Early init status = 3
9322 09:32:36.745440 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9323 09:32:36.750370 in-header: 03 fc 00 00 01 00 00 00
9324 09:32:36.753531 in-data: 00
9325 09:32:36.756962 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9326 09:32:36.762827 in-header: 03 fd 00 00 00 00 00 00
9327 09:32:36.766163 in-data:
9328 09:32:36.769467 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9329 09:32:36.774016 in-header: 03 fc 00 00 01 00 00 00
9330 09:32:36.776821 in-data: 00
9331 09:32:36.780488 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9332 09:32:36.785683 in-header: 03 fd 00 00 00 00 00 00
9333 09:32:36.789244 in-data:
9334 09:32:36.792404 [SSUSB] Setting up USB HOST controller...
9335 09:32:36.795738 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9336 09:32:36.799461 [SSUSB] phy power-on done.
9337 09:32:36.802568 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9338 09:32:36.809095 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9339 09:32:36.813099 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9340 09:32:36.819322 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9341 09:32:36.825859 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9342 09:32:36.832886 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9343 09:32:36.839231 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9344 09:32:36.845967 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9345 09:32:36.846437 SPM: binary array size = 0x9dc
9346 09:32:36.852766 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9347 09:32:36.859243 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9348 09:32:36.866429 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9349 09:32:36.869088 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9350 09:32:36.872455 configure_display: Starting display init
9351 09:32:36.909360 anx7625_power_on_init: Init interface.
9352 09:32:36.912955 anx7625_disable_pd_protocol: Disabled PD feature.
9353 09:32:36.916164 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9354 09:32:36.943536 anx7625_start_dp_work: Secure OCM version=00
9355 09:32:36.947140 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9356 09:32:36.961441 sp_tx_get_edid_block: EDID Block = 1
9357 09:32:37.064402 Extracted contents:
9358 09:32:37.067984 header: 00 ff ff ff ff ff ff 00
9359 09:32:37.071010 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9360 09:32:37.074399 version: 01 04
9361 09:32:37.077477 basic params: 95 1f 11 78 0a
9362 09:32:37.080887 chroma info: 76 90 94 55 54 90 27 21 50 54
9363 09:32:37.084461 established: 00 00 00
9364 09:32:37.090672 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9365 09:32:37.094022 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9366 09:32:37.100784 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 09:32:37.108562 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9368 09:32:37.114101 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9369 09:32:37.117764 extensions: 00
9370 09:32:37.118293 checksum: fb
9371 09:32:37.118674
9372 09:32:37.121527 Manufacturer: IVO Model 57d Serial Number 0
9373 09:32:37.124291 Made week 0 of 2020
9374 09:32:37.124708 EDID version: 1.4
9375 09:32:37.127402 Digital display
9376 09:32:37.130990 6 bits per primary color channel
9377 09:32:37.131414 DisplayPort interface
9378 09:32:37.134646 Maximum image size: 31 cm x 17 cm
9379 09:32:37.135140 Gamma: 220%
9380 09:32:37.137597 Check DPMS levels
9381 09:32:37.141582 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9382 09:32:37.144743 First detailed timing is preferred timing
9383 09:32:37.147547 Established timings supported:
9384 09:32:37.150860 Standard timings supported:
9385 09:32:37.151427 Detailed timings
9386 09:32:37.157507 Hex of detail: 383680a07038204018303c0035ae10000019
9387 09:32:37.161609 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9388 09:32:37.164713 0780 0798 07c8 0820 hborder 0
9389 09:32:37.171307 0438 043b 0447 0458 vborder 0
9390 09:32:37.171730 -hsync -vsync
9391 09:32:37.174217 Did detailed timing
9392 09:32:37.177467 Hex of detail: 000000000000000000000000000000000000
9393 09:32:37.180948 Manufacturer-specified data, tag 0
9394 09:32:37.187642 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9395 09:32:37.188097 ASCII string: InfoVision
9396 09:32:37.194525 Hex of detail: 000000fe00523134304e574635205248200a
9397 09:32:37.195004 ASCII string: R140NWF5 RH
9398 09:32:37.197721 Checksum
9399 09:32:37.198151 Checksum: 0xfb (valid)
9400 09:32:37.204472 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9401 09:32:37.204894 DSI data_rate: 832800000 bps
9402 09:32:37.211805 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9403 09:32:37.215365 anx7625_parse_edid: pixelclock(138800).
9404 09:32:37.218282 hactive(1920), hsync(48), hfp(24), hbp(88)
9405 09:32:37.221749 vactive(1080), vsync(12), vfp(3), vbp(17)
9406 09:32:37.225195 anx7625_dsi_config: config dsi.
9407 09:32:37.232146 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9408 09:32:37.246275 anx7625_dsi_config: success to config DSI
9409 09:32:37.249296 anx7625_dp_start: MIPI phy setup OK.
9410 09:32:37.253052 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9411 09:32:37.256272 mtk_ddp_mode_set invalid vrefresh 60
9412 09:32:37.259543 main_disp_path_setup
9413 09:32:37.260011 ovl_layer_smi_id_en
9414 09:32:37.263114 ovl_layer_smi_id_en
9415 09:32:37.263536 ccorr_config
9416 09:32:37.263868 aal_config
9417 09:32:37.266207 gamma_config
9418 09:32:37.266626 postmask_config
9419 09:32:37.269303 dither_config
9420 09:32:37.273080 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9421 09:32:37.279462 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9422 09:32:37.283284 Root Device init finished in 555 msecs
9423 09:32:37.283717 CPU_CLUSTER: 0 init
9424 09:32:37.292648 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9425 09:32:37.296279 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9426 09:32:37.299669 APU_MBOX 0x190000b0 = 0x10001
9427 09:32:37.302908 APU_MBOX 0x190001b0 = 0x10001
9428 09:32:37.306159 APU_MBOX 0x190005b0 = 0x10001
9429 09:32:37.309524 APU_MBOX 0x190006b0 = 0x10001
9430 09:32:37.312887 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9431 09:32:37.325771 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9432 09:32:37.337994 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9433 09:32:37.344126 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9434 09:32:37.356385 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9435 09:32:37.364866 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9436 09:32:37.368701 CPU_CLUSTER: 0 init finished in 81 msecs
9437 09:32:37.371520 Devices initialized
9438 09:32:37.375093 Show all devs... After init.
9439 09:32:37.375539 Root Device: enabled 1
9440 09:32:37.378231 CPU_CLUSTER: 0: enabled 1
9441 09:32:37.381716 CPU: 00: enabled 1
9442 09:32:37.385581 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9443 09:32:37.388668 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9444 09:32:37.391781 ELOG: NV offset 0x57f000 size 0x1000
9445 09:32:37.398345 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9446 09:32:37.405300 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9447 09:32:37.408269 ELOG: Event(17) added with size 13 at 2023-10-20 09:32:37 UTC
9448 09:32:37.412080 out: cmd=0x121: 03 db 21 01 00 00 00 00
9449 09:32:37.416472 in-header: 03 d6 00 00 2c 00 00 00
9450 09:32:37.429043 in-data: 89 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9451 09:32:37.436004 ELOG: Event(A1) added with size 10 at 2023-10-20 09:32:37 UTC
9452 09:32:37.442354 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9453 09:32:37.449499 ELOG: Event(A0) added with size 9 at 2023-10-20 09:32:37 UTC
9454 09:32:37.452808 elog_add_boot_reason: Logged dev mode boot
9455 09:32:37.456068 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9456 09:32:37.459617 Finalize devices...
9457 09:32:37.459708 Devices finalized
9458 09:32:37.466142 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9459 09:32:37.469489 Writing coreboot table at 0xffe64000
9460 09:32:37.472990 0. 000000000010a000-0000000000113fff: RAMSTAGE
9461 09:32:37.476404 1. 0000000040000000-00000000400fffff: RAM
9462 09:32:37.479733 2. 0000000040100000-000000004032afff: RAMSTAGE
9463 09:32:37.483122 3. 000000004032b000-00000000545fffff: RAM
9464 09:32:37.489675 4. 0000000054600000-000000005465ffff: BL31
9465 09:32:37.493070 5. 0000000054660000-00000000ffe63fff: RAM
9466 09:32:37.496414 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9467 09:32:37.503158 7. 0000000100000000-000000023fffffff: RAM
9468 09:32:37.503247 Passing 5 GPIOs to payload:
9469 09:32:37.509474 NAME | PORT | POLARITY | VALUE
9470 09:32:37.512851 EC in RW | 0x000000aa | low | undefined
9471 09:32:37.516264 EC interrupt | 0x00000005 | low | undefined
9472 09:32:37.522740 TPM interrupt | 0x000000ab | high | undefined
9473 09:32:37.525948 SD card detect | 0x00000011 | high | undefined
9474 09:32:37.532849 speaker enable | 0x00000093 | high | undefined
9475 09:32:37.535942 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9476 09:32:37.539643 in-header: 03 f9 00 00 02 00 00 00
9477 09:32:37.539725 in-data: 02 00
9478 09:32:37.542690 ADC[4]: Raw value=900590 ID=7
9479 09:32:37.546132 ADC[3]: Raw value=213336 ID=1
9480 09:32:37.546215 RAM Code: 0x71
9481 09:32:37.549426 ADC[6]: Raw value=74557 ID=0
9482 09:32:37.552900 ADC[5]: Raw value=211860 ID=1
9483 09:32:37.552983 SKU Code: 0x1
9484 09:32:37.559324 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b061
9485 09:32:37.562604 coreboot table: 964 bytes.
9486 09:32:37.565870 IMD ROOT 0. 0xfffff000 0x00001000
9487 09:32:37.569653 IMD SMALL 1. 0xffffe000 0x00001000
9488 09:32:37.572916 RO MCACHE 2. 0xffffc000 0x00001104
9489 09:32:37.576414 CONSOLE 3. 0xfff7c000 0x00080000
9490 09:32:37.579270 FMAP 4. 0xfff7b000 0x00000452
9491 09:32:37.583056 TIME STAMP 5. 0xfff7a000 0x00000910
9492 09:32:37.586514 VBOOT WORK 6. 0xfff66000 0x00014000
9493 09:32:37.586597 RAMOOPS 7. 0xffe66000 0x00100000
9494 09:32:37.589352 COREBOOT 8. 0xffe64000 0x00002000
9495 09:32:37.592624 IMD small region:
9496 09:32:37.596256 IMD ROOT 0. 0xffffec00 0x00000400
9497 09:32:37.599367 VPD 1. 0xffffeb80 0x0000006c
9498 09:32:37.602873 MMC STATUS 2. 0xffffeb60 0x00000004
9499 09:32:37.609285 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9500 09:32:37.609368 Probing TPM: done!
9501 09:32:37.616471 Connected to device vid:did:rid of 1ae0:0028:00
9502 09:32:37.622814 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9503 09:32:37.626313 Initialized TPM device CR50 revision 0
9504 09:32:37.629687 Checking cr50 for pending updates
9505 09:32:37.635473 Reading cr50 TPM mode
9506 09:32:37.643914 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9507 09:32:37.650498 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9508 09:32:37.690512 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9509 09:32:37.694340 Checking segment from ROM address 0x40100000
9510 09:32:37.697384 Checking segment from ROM address 0x4010001c
9511 09:32:37.704102 Loading segment from ROM address 0x40100000
9512 09:32:37.704185 code (compression=0)
9513 09:32:37.714386 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9514 09:32:37.720982 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9515 09:32:37.721065 it's not compressed!
9516 09:32:37.727571 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9517 09:32:37.730867 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9518 09:32:37.751109 Loading segment from ROM address 0x4010001c
9519 09:32:37.751203 Entry Point 0x80000000
9520 09:32:37.754802 Loaded segments
9521 09:32:37.758008 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9522 09:32:37.764364 Jumping to boot code at 0x80000000(0xffe64000)
9523 09:32:37.771408 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9524 09:32:37.777737 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9525 09:32:37.785769 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9526 09:32:37.789221 Checking segment from ROM address 0x40100000
9527 09:32:37.792232 Checking segment from ROM address 0x4010001c
9528 09:32:37.799035 Loading segment from ROM address 0x40100000
9529 09:32:37.799119 code (compression=1)
9530 09:32:37.805574 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9531 09:32:37.815503 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9532 09:32:37.815587 using LZMA
9533 09:32:37.824126 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9534 09:32:37.830993 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9535 09:32:37.834219 Loading segment from ROM address 0x4010001c
9536 09:32:37.834301 Entry Point 0x54601000
9537 09:32:37.837675 Loaded segments
9538 09:32:37.840583 NOTICE: MT8192 bl31_setup
9539 09:32:37.847970 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9540 09:32:37.851086 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9541 09:32:37.854303 WARNING: region 0:
9542 09:32:37.857241 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 09:32:37.857324 WARNING: region 1:
9544 09:32:37.864493 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9545 09:32:37.867961 WARNING: region 2:
9546 09:32:37.870829 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9547 09:32:37.874329 WARNING: region 3:
9548 09:32:37.877970 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9549 09:32:37.881024 WARNING: region 4:
9550 09:32:37.884437 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9551 09:32:37.888055 WARNING: region 5:
9552 09:32:37.891267 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 09:32:37.894614 WARNING: region 6:
9554 09:32:37.898059 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 09:32:37.898157 WARNING: region 7:
9556 09:32:37.904575 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 09:32:37.911350 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9558 09:32:37.914952 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9559 09:32:37.918239 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9560 09:32:37.924680 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9561 09:32:37.927860 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9562 09:32:37.931326 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9563 09:32:37.938429 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9564 09:32:37.941777 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9565 09:32:37.944684 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9566 09:32:37.951352 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9567 09:32:37.954739 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9568 09:32:37.958546 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9569 09:32:37.965214 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9570 09:32:37.968493 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9571 09:32:37.975219 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9572 09:32:37.978497 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9573 09:32:37.981558 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9574 09:32:37.988376 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9575 09:32:37.991888 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9576 09:32:37.995309 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9577 09:32:38.002009 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9578 09:32:38.005449 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9579 09:32:38.008896 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9580 09:32:38.015195 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9581 09:32:38.018915 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9582 09:32:38.025395 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9583 09:32:38.028780 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9584 09:32:38.032249 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9585 09:32:38.038826 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9586 09:32:38.042117 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9587 09:32:38.049015 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9588 09:32:38.052258 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9589 09:32:38.055584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9590 09:32:38.058966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9591 09:32:38.065647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9592 09:32:38.069190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9593 09:32:38.072297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9594 09:32:38.075802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9595 09:32:38.082370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9596 09:32:38.085813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9597 09:32:38.089066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9598 09:32:38.092752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9599 09:32:38.095722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9600 09:32:38.103026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9601 09:32:38.105905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9602 09:32:38.109069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9603 09:32:38.115994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9604 09:32:38.119110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9605 09:32:38.122570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9606 09:32:38.129435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9607 09:32:38.132441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9608 09:32:38.136128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9609 09:32:38.142756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9610 09:32:38.146108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9611 09:32:38.152832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9612 09:32:38.156100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9613 09:32:38.159415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9614 09:32:38.166100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9615 09:32:38.169611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9616 09:32:38.176310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9617 09:32:38.179836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9618 09:32:38.186390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9619 09:32:38.189596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9620 09:32:38.196370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9621 09:32:38.199909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9622 09:32:38.203424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9623 09:32:38.209839 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9624 09:32:38.213492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9625 09:32:38.220036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9626 09:32:38.223165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9627 09:32:38.226644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9628 09:32:38.233473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9629 09:32:38.236762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9630 09:32:38.243390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9631 09:32:38.246760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9632 09:32:38.253435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9633 09:32:38.256912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9634 09:32:38.260397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9635 09:32:38.267099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9636 09:32:38.270517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9637 09:32:38.277219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9638 09:32:38.280690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9639 09:32:38.283660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9640 09:32:38.290896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9641 09:32:38.294181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9642 09:32:38.300320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9643 09:32:38.303984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9644 09:32:38.310941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9645 09:32:38.314131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9646 09:32:38.317289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9647 09:32:38.323851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9648 09:32:38.327402 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9649 09:32:38.333906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9650 09:32:38.337547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9651 09:32:38.344318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9652 09:32:38.347826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9653 09:32:38.351137 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9654 09:32:38.354227 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9655 09:32:38.360788 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9656 09:32:38.364242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9657 09:32:38.367786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9658 09:32:38.374010 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9659 09:32:38.377378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9660 09:32:38.380848 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9661 09:32:38.387562 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9662 09:32:38.390786 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9663 09:32:38.397481 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9664 09:32:38.400951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9665 09:32:38.404396 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9666 09:32:38.410970 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9667 09:32:38.414163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9668 09:32:38.421186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9669 09:32:38.424685 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9670 09:32:38.427582 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9671 09:32:38.434648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9672 09:32:38.437985 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9673 09:32:38.441298 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9674 09:32:38.447666 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9675 09:32:38.451465 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9676 09:32:38.454417 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9677 09:32:38.457692 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9678 09:32:38.464817 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9679 09:32:38.468003 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9680 09:32:38.471701 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9681 09:32:38.475018 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9682 09:32:38.481682 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9683 09:32:38.484546 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9684 09:32:38.491795 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9685 09:32:38.495082 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9686 09:32:38.497936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9687 09:32:38.504742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9688 09:32:38.508147 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9689 09:32:38.514747 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9690 09:32:38.518417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9691 09:32:38.521770 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9692 09:32:38.528213 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9693 09:32:38.531476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9694 09:32:38.534807 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9695 09:32:38.541646 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9696 09:32:38.544955 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9697 09:32:38.551851 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9698 09:32:38.555487 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9699 09:32:38.558776 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9700 09:32:38.565738 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9701 09:32:38.568906 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9702 09:32:38.572384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9703 09:32:38.578716 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9704 09:32:38.582050 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9705 09:32:38.588727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9706 09:32:38.592311 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9707 09:32:38.595795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9708 09:32:38.601980 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9709 09:32:38.605496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9710 09:32:38.608770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9711 09:32:38.615572 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9712 09:32:38.619037 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9713 09:32:38.625875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9714 09:32:38.629246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9715 09:32:38.632560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9716 09:32:38.639421 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9717 09:32:38.642398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9718 09:32:38.645749 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9719 09:32:38.652815 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9720 09:32:38.656110 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9721 09:32:38.662568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9722 09:32:38.666146 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9723 09:32:38.669228 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9724 09:32:38.675719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9725 09:32:38.679111 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9726 09:32:38.685932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9727 09:32:38.689630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9728 09:32:38.692296 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9729 09:32:38.698980 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9730 09:32:38.702500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9731 09:32:38.705995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9732 09:32:38.712164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9733 09:32:38.715763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9734 09:32:38.722491 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9735 09:32:38.725640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9736 09:32:38.728828 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9737 09:32:38.736006 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9738 09:32:38.739215 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9739 09:32:38.742726 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9740 09:32:38.749355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9741 09:32:38.752294 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9742 09:32:38.758986 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9743 09:32:38.762494 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9744 09:32:38.766182 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9745 09:32:38.772660 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9746 09:32:38.775998 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9747 09:32:38.782979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9748 09:32:38.786155 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9749 09:32:38.789573 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9750 09:32:38.795965 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9751 09:32:38.799427 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9752 09:32:38.806156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9753 09:32:38.809414 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9754 09:32:38.812849 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9755 09:32:38.819270 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9756 09:32:38.822687 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9757 09:32:38.829213 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9758 09:32:38.832538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9759 09:32:38.836156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9760 09:32:38.842867 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9761 09:32:38.846135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9762 09:32:38.852897 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9763 09:32:38.856361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9764 09:32:38.859622 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9765 09:32:38.866273 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9766 09:32:38.869596 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9767 09:32:38.876612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9768 09:32:38.879914 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9769 09:32:38.886502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9770 09:32:38.889493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9771 09:32:38.892820 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9772 09:32:38.899994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9773 09:32:38.903572 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9774 09:32:38.910506 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9775 09:32:38.913274 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9776 09:32:38.916423 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9777 09:32:38.922805 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9778 09:32:38.926310 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9779 09:32:38.932948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9780 09:32:38.936419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9781 09:32:38.940030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9782 09:32:38.946447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9783 09:32:38.949765 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9784 09:32:38.956496 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9785 09:32:38.960100 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9786 09:32:38.963236 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9787 09:32:38.966382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9788 09:32:38.973089 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9789 09:32:38.976523 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9790 09:32:38.979663 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9791 09:32:38.986519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9792 09:32:38.989622 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9793 09:32:38.993138 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9794 09:32:38.999569 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9795 09:32:39.003076 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9796 09:32:39.006302 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9797 09:32:39.012990 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9798 09:32:39.016410 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9799 09:32:39.019771 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9800 09:32:39.026710 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9801 09:32:39.029898 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9802 09:32:39.033279 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9803 09:32:39.040218 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9804 09:32:39.043462 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9805 09:32:39.046668 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9806 09:32:39.053540 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9807 09:32:39.056312 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9808 09:32:39.063411 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9809 09:32:39.066481 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9810 09:32:39.070144 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9811 09:32:39.076622 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9812 09:32:39.079947 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9813 09:32:39.083284 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9814 09:32:39.089643 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9815 09:32:39.093053 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9816 09:32:39.096379 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9817 09:32:39.103314 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9818 09:32:39.106658 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9819 09:32:39.113283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9820 09:32:39.116595 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9821 09:32:39.120189 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9822 09:32:39.127025 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9823 09:32:39.129626 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9824 09:32:39.136524 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9825 09:32:39.139546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9826 09:32:39.143188 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9827 09:32:39.146210 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9828 09:32:39.149866 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9829 09:32:39.156331 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9830 09:32:39.160043 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9831 09:32:39.163428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9832 09:32:39.166602 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9833 09:32:39.172742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9834 09:32:39.176629 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9835 09:32:39.179974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9836 09:32:39.183251 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9837 09:32:39.189511 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9838 09:32:39.193393 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9839 09:32:39.196364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9840 09:32:39.203325 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9841 09:32:39.206622 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9842 09:32:39.212936 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9843 09:32:39.216628 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9844 09:32:39.220022 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9845 09:32:39.226663 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9846 09:32:39.229586 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9847 09:32:39.236398 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9848 09:32:39.240143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9849 09:32:39.243338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9850 09:32:39.249902 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9851 09:32:39.252949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9852 09:32:39.259795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9853 09:32:39.263330 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9854 09:32:39.266503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9855 09:32:39.273123 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9856 09:32:39.276552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9857 09:32:39.283256 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9858 09:32:39.286553 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9859 09:32:39.289881 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9860 09:32:39.296774 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9861 09:32:39.300171 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9862 09:32:39.303351 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9863 09:32:39.310376 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9864 09:32:39.313749 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9865 09:32:39.320184 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9866 09:32:39.323753 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9867 09:32:39.326896 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9868 09:32:39.333630 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9869 09:32:39.336758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9870 09:32:39.343524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9871 09:32:39.347213 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9872 09:32:39.350484 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9873 09:32:39.357201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9874 09:32:39.360374 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9875 09:32:39.367053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9876 09:32:39.370254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9877 09:32:39.376980 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9878 09:32:39.380358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9879 09:32:39.383520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9880 09:32:39.390188 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9881 09:32:39.393866 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9882 09:32:39.400076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9883 09:32:39.403489 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9884 09:32:39.407257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9885 09:32:39.413431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9886 09:32:39.417313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9887 09:32:39.420541 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9888 09:32:39.426827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9889 09:32:39.430216 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9890 09:32:39.436877 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9891 09:32:39.440073 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9892 09:32:39.447068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9893 09:32:39.450315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9894 09:32:39.453990 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9895 09:32:39.460583 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9896 09:32:39.463814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9897 09:32:39.467230 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9898 09:32:39.474248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9899 09:32:39.477246 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9900 09:32:39.483824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9901 09:32:39.487191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9902 09:32:39.490522 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9903 09:32:39.496948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9904 09:32:39.500247 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9905 09:32:39.507142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9906 09:32:39.510427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9907 09:32:39.513906 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9908 09:32:39.520977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9909 09:32:39.523982 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9910 09:32:39.530588 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9911 09:32:39.533946 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9912 09:32:39.540703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9913 09:32:39.544184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9914 09:32:39.547063 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9915 09:32:39.554086 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9916 09:32:39.557016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9917 09:32:39.563551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9918 09:32:39.567070 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9919 09:32:39.574065 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9920 09:32:39.577528 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9921 09:32:39.580511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9922 09:32:39.587609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9923 09:32:39.590346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9924 09:32:39.597181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9925 09:32:39.600320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9926 09:32:39.607254 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9927 09:32:39.610641 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9928 09:32:39.614142 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9929 09:32:39.620774 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9930 09:32:39.624308 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9931 09:32:39.630838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9932 09:32:39.634008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9933 09:32:39.640647 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9934 09:32:39.644254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9935 09:32:39.647407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9936 09:32:39.654514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9937 09:32:39.657815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9938 09:32:39.664191 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9939 09:32:39.667774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9940 09:32:39.674090 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9941 09:32:39.677544 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9942 09:32:39.680875 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9943 09:32:39.687651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9944 09:32:39.690878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9945 09:32:39.697364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9946 09:32:39.700986 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9947 09:32:39.707462 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9948 09:32:39.710851 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9949 09:32:39.714152 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9950 09:32:39.721202 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9951 09:32:39.724074 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9952 09:32:39.730828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9953 09:32:39.734324 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9954 09:32:39.741140 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9955 09:32:39.744390 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9956 09:32:39.747752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9957 09:32:39.754588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9958 09:32:39.757465 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9959 09:32:39.761199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9960 09:32:39.767958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9961 09:32:39.770870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9962 09:32:39.777576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9963 09:32:39.780896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9964 09:32:39.787457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9965 09:32:39.791101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9966 09:32:39.797617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9967 09:32:39.801300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9968 09:32:39.807910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9969 09:32:39.810978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9970 09:32:39.817626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9971 09:32:39.821368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9972 09:32:39.824537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9973 09:32:39.831359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9974 09:32:39.834614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9975 09:32:39.841202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9976 09:32:39.844667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9977 09:32:39.851133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9978 09:32:39.854875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9979 09:32:39.861282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9980 09:32:39.864572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9981 09:32:39.871832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9982 09:32:39.874601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9983 09:32:39.881469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9984 09:32:39.884625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9985 09:32:39.891248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9986 09:32:39.894929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9987 09:32:39.901482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9988 09:32:39.904710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9989 09:32:39.911355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9990 09:32:39.914640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9991 09:32:39.921330 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9992 09:32:39.921752 INFO: [APUAPC] vio 0
9993 09:32:39.928116 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9994 09:32:39.931213 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9995 09:32:39.934538 INFO: [APUAPC] D0_APC_0: 0x400510
9996 09:32:39.938086 INFO: [APUAPC] D0_APC_1: 0x0
9997 09:32:39.941786 INFO: [APUAPC] D0_APC_2: 0x1540
9998 09:32:39.944785 INFO: [APUAPC] D0_APC_3: 0x0
9999 09:32:39.948248 INFO: [APUAPC] D1_APC_0: 0xffffffff
10000 09:32:39.951522 INFO: [APUAPC] D1_APC_1: 0xffffffff
10001 09:32:39.954653 INFO: [APUAPC] D1_APC_2: 0x3fffff
10002 09:32:39.958122 INFO: [APUAPC] D1_APC_3: 0x0
10003 09:32:39.961204 INFO: [APUAPC] D2_APC_0: 0xffffffff
10004 09:32:39.964737 INFO: [APUAPC] D2_APC_1: 0xffffffff
10005 09:32:39.968084 INFO: [APUAPC] D2_APC_2: 0x3fffff
10006 09:32:39.968570 INFO: [APUAPC] D2_APC_3: 0x0
10007 09:32:39.971693 INFO: [APUAPC] D3_APC_0: 0xffffffff
10008 09:32:39.978004 INFO: [APUAPC] D3_APC_1: 0xffffffff
10009 09:32:39.978426 INFO: [APUAPC] D3_APC_2: 0x3fffff
10010 09:32:39.981386 INFO: [APUAPC] D3_APC_3: 0x0
10011 09:32:39.984922 INFO: [APUAPC] D4_APC_0: 0xffffffff
10012 09:32:39.988287 INFO: [APUAPC] D4_APC_1: 0xffffffff
10013 09:32:39.991475 INFO: [APUAPC] D4_APC_2: 0x3fffff
10014 09:32:39.994853 INFO: [APUAPC] D4_APC_3: 0x0
10015 09:32:39.998093 INFO: [APUAPC] D5_APC_0: 0xffffffff
10016 09:32:40.001584 INFO: [APUAPC] D5_APC_1: 0xffffffff
10017 09:32:40.005048 INFO: [APUAPC] D5_APC_2: 0x3fffff
10018 09:32:40.008527 INFO: [APUAPC] D5_APC_3: 0x0
10019 09:32:40.011703 INFO: [APUAPC] D6_APC_0: 0xffffffff
10020 09:32:40.015069 INFO: [APUAPC] D6_APC_1: 0xffffffff
10021 09:32:40.018345 INFO: [APUAPC] D6_APC_2: 0x3fffff
10022 09:32:40.021491 INFO: [APUAPC] D6_APC_3: 0x0
10023 09:32:40.024781 INFO: [APUAPC] D7_APC_0: 0xffffffff
10024 09:32:40.028460 INFO: [APUAPC] D7_APC_1: 0xffffffff
10025 09:32:40.031591 INFO: [APUAPC] D7_APC_2: 0x3fffff
10026 09:32:40.034826 INFO: [APUAPC] D7_APC_3: 0x0
10027 09:32:40.038096 INFO: [APUAPC] D8_APC_0: 0xffffffff
10028 09:32:40.041156 INFO: [APUAPC] D8_APC_1: 0xffffffff
10029 09:32:40.044697 INFO: [APUAPC] D8_APC_2: 0x3fffff
10030 09:32:40.048053 INFO: [APUAPC] D8_APC_3: 0x0
10031 09:32:40.051319 INFO: [APUAPC] D9_APC_0: 0xffffffff
10032 09:32:40.054618 INFO: [APUAPC] D9_APC_1: 0xffffffff
10033 09:32:40.058216 INFO: [APUAPC] D9_APC_2: 0x3fffff
10034 09:32:40.061702 INFO: [APUAPC] D9_APC_3: 0x0
10035 09:32:40.064783 INFO: [APUAPC] D10_APC_0: 0xffffffff
10036 09:32:40.068668 INFO: [APUAPC] D10_APC_1: 0xffffffff
10037 09:32:40.071723 INFO: [APUAPC] D10_APC_2: 0x3fffff
10038 09:32:40.074876 INFO: [APUAPC] D10_APC_3: 0x0
10039 09:32:40.078689 INFO: [APUAPC] D11_APC_0: 0xffffffff
10040 09:32:40.081840 INFO: [APUAPC] D11_APC_1: 0xffffffff
10041 09:32:40.085157 INFO: [APUAPC] D11_APC_2: 0x3fffff
10042 09:32:40.088437 INFO: [APUAPC] D11_APC_3: 0x0
10043 09:32:40.091882 INFO: [APUAPC] D12_APC_0: 0xffffffff
10044 09:32:40.095207 INFO: [APUAPC] D12_APC_1: 0xffffffff
10045 09:32:40.098454 INFO: [APUAPC] D12_APC_2: 0x3fffff
10046 09:32:40.101752 INFO: [APUAPC] D12_APC_3: 0x0
10047 09:32:40.105166 INFO: [APUAPC] D13_APC_0: 0xffffffff
10048 09:32:40.108365 INFO: [APUAPC] D13_APC_1: 0xffffffff
10049 09:32:40.111898 INFO: [APUAPC] D13_APC_2: 0x3fffff
10050 09:32:40.115362 INFO: [APUAPC] D13_APC_3: 0x0
10051 09:32:40.118713 INFO: [APUAPC] D14_APC_0: 0xffffffff
10052 09:32:40.121751 INFO: [APUAPC] D14_APC_1: 0xffffffff
10053 09:32:40.124905 INFO: [APUAPC] D14_APC_2: 0x3fffff
10054 09:32:40.128276 INFO: [APUAPC] D14_APC_3: 0x0
10055 09:32:40.131947 INFO: [APUAPC] D15_APC_0: 0xffffffff
10056 09:32:40.135231 INFO: [APUAPC] D15_APC_1: 0xffffffff
10057 09:32:40.138629 INFO: [APUAPC] D15_APC_2: 0x3fffff
10058 09:32:40.141742 INFO: [APUAPC] D15_APC_3: 0x0
10059 09:32:40.145365 INFO: [APUAPC] APC_CON: 0x4
10060 09:32:40.145782 INFO: [NOCDAPC] D0_APC_0: 0x0
10061 09:32:40.148752 INFO: [NOCDAPC] D0_APC_1: 0x0
10062 09:32:40.151855 INFO: [NOCDAPC] D1_APC_0: 0x0
10063 09:32:40.155356 INFO: [NOCDAPC] D1_APC_1: 0xfff
10064 09:32:40.158913 INFO: [NOCDAPC] D2_APC_0: 0x0
10065 09:32:40.162402 INFO: [NOCDAPC] D2_APC_1: 0xfff
10066 09:32:40.165125 INFO: [NOCDAPC] D3_APC_0: 0x0
10067 09:32:40.169100 INFO: [NOCDAPC] D3_APC_1: 0xfff
10068 09:32:40.171657 INFO: [NOCDAPC] D4_APC_0: 0x0
10069 09:32:40.175329 INFO: [NOCDAPC] D4_APC_1: 0xfff
10070 09:32:40.175928 INFO: [NOCDAPC] D5_APC_0: 0x0
10071 09:32:40.178474 INFO: [NOCDAPC] D5_APC_1: 0xfff
10072 09:32:40.181721 INFO: [NOCDAPC] D6_APC_0: 0x0
10073 09:32:40.184996 INFO: [NOCDAPC] D6_APC_1: 0xfff
10074 09:32:40.188778 INFO: [NOCDAPC] D7_APC_0: 0x0
10075 09:32:40.191869 INFO: [NOCDAPC] D7_APC_1: 0xfff
10076 09:32:40.195092 INFO: [NOCDAPC] D8_APC_0: 0x0
10077 09:32:40.198665 INFO: [NOCDAPC] D8_APC_1: 0xfff
10078 09:32:40.201707 INFO: [NOCDAPC] D9_APC_0: 0x0
10079 09:32:40.205062 INFO: [NOCDAPC] D9_APC_1: 0xfff
10080 09:32:40.205486 INFO: [NOCDAPC] D10_APC_0: 0x0
10081 09:32:40.208474 INFO: [NOCDAPC] D10_APC_1: 0xfff
10082 09:32:40.211704 INFO: [NOCDAPC] D11_APC_0: 0x0
10083 09:32:40.215124 INFO: [NOCDAPC] D11_APC_1: 0xfff
10084 09:32:40.218501 INFO: [NOCDAPC] D12_APC_0: 0x0
10085 09:32:40.222102 INFO: [NOCDAPC] D12_APC_1: 0xfff
10086 09:32:40.225416 INFO: [NOCDAPC] D13_APC_0: 0x0
10087 09:32:40.228601 INFO: [NOCDAPC] D13_APC_1: 0xfff
10088 09:32:40.231854 INFO: [NOCDAPC] D14_APC_0: 0x0
10089 09:32:40.235303 INFO: [NOCDAPC] D14_APC_1: 0xfff
10090 09:32:40.238625 INFO: [NOCDAPC] D15_APC_0: 0x0
10091 09:32:40.241795 INFO: [NOCDAPC] D15_APC_1: 0xfff
10092 09:32:40.245445 INFO: [NOCDAPC] APC_CON: 0x4
10093 09:32:40.248809 INFO: [APUAPC] set_apusys_apc done
10094 09:32:40.249230 INFO: [DEVAPC] devapc_init done
10095 09:32:40.255418 INFO: GICv3 without legacy support detected.
10096 09:32:40.258369 INFO: ARM GICv3 driver initialized in EL3
10097 09:32:40.262059 INFO: Maximum SPI INTID supported: 639
10098 09:32:40.265513 INFO: BL31: Initializing runtime services
10099 09:32:40.272090 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10100 09:32:40.275632 INFO: SPM: enable CPC mode
10101 09:32:40.278905 INFO: mcdi ready for mcusys-off-idle and system suspend
10102 09:32:40.285293 INFO: BL31: Preparing for EL3 exit to normal world
10103 09:32:40.288668 INFO: Entry point address = 0x80000000
10104 09:32:40.289153 INFO: SPSR = 0x8
10105 09:32:40.295851
10106 09:32:40.296354
10107 09:32:40.296688
10108 09:32:40.299107 Starting depthcharge on Spherion...
10109 09:32:40.299532
10110 09:32:40.299865 Wipe memory regions:
10111 09:32:40.300173
10112 09:32:40.302819 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10113 09:32:40.303331 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10114 09:32:40.303750 Setting prompt string to ['asurada:']
10115 09:32:40.304166 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10116 09:32:40.304824 [0x00000040000000, 0x00000054600000)
10117 09:32:40.424667
10118 09:32:40.425161 [0x00000054660000, 0x00000080000000)
10119 09:32:40.685626
10120 09:32:40.686130 [0x000000821a7280, 0x000000ffe64000)
10121 09:32:41.430361
10122 09:32:41.430904 [0x00000100000000, 0x00000240000000)
10123 09:32:43.320708
10124 09:32:43.323416 Initializing XHCI USB controller at 0x11200000.
10125 09:32:44.361815
10126 09:32:44.365077 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10127 09:32:44.365501
10128 09:32:44.365832
10129 09:32:44.366190
10130 09:32:44.366992 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10132 09:32:44.468160 asurada: tftpboot 192.168.201.1 11826827/tftp-deploy-jtsi5kkd/kernel/image.itb 11826827/tftp-deploy-jtsi5kkd/kernel/cmdline
10133 09:32:44.468795 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10134 09:32:44.469229 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10135 09:32:44.473967 tftpboot 192.168.201.1 11826827/tftp-deploy-jtsi5kkd/kernel/image.itbtp-deploy-jtsi5kkd/kernel/cmdline
10136 09:32:44.474437
10137 09:32:44.474813 Waiting for link
10138 09:32:44.633966
10139 09:32:44.634440 R8152: Initializing
10140 09:32:44.634807
10141 09:32:44.637335 Version 6 (ocp_data = 5c30)
10142 09:32:44.637757
10143 09:32:44.640651 R8152: Done initializing
10144 09:32:44.641066
10145 09:32:44.641395 Adding net device
10146 09:32:46.508539
10147 09:32:46.509036 done.
10148 09:32:46.509371
10149 09:32:46.509682 MAC: 00:24:32:30:78:52
10150 09:32:46.509980
10151 09:32:46.511959 Sending DHCP discover... done.
10152 09:32:46.512490
10153 09:32:46.515099 Waiting for reply... done.
10154 09:32:46.515536
10155 09:32:46.518711 Sending DHCP request... done.
10156 09:32:46.519174
10157 09:32:46.522859 Waiting for reply... done.
10158 09:32:46.523277
10159 09:32:46.523614 My ip is 192.168.201.14
10160 09:32:46.524001
10161 09:32:46.525818 The DHCP server ip is 192.168.201.1
10162 09:32:46.526252
10163 09:32:46.532769 TFTP server IP predefined by user: 192.168.201.1
10164 09:32:46.533191
10165 09:32:46.539338 Bootfile predefined by user: 11826827/tftp-deploy-jtsi5kkd/kernel/image.itb
10166 09:32:46.539761
10167 09:32:46.540092 Sending tftp read request... done.
10168 09:32:46.540403
10169 09:32:46.548718 Waiting for the transfer...
10170 09:32:46.549141
10171 09:32:47.170146 00000000 ################################################################
10172 09:32:47.170648
10173 09:32:47.773130 00080000 ################################################################
10174 09:32:47.773264
10175 09:32:48.357262 00100000 ################################################################
10176 09:32:48.357402
10177 09:32:48.923242 00180000 ################################################################
10178 09:32:48.923383
10179 09:32:49.467846 00200000 ################################################################
10180 09:32:49.467982
10181 09:32:50.040632 00280000 ################################################################
10182 09:32:50.041132
10183 09:32:50.591707 00300000 ################################################################
10184 09:32:50.591943
10185 09:32:51.240022 00380000 ################################################################
10186 09:32:51.240526
10187 09:32:51.803282 00400000 ################################################################
10188 09:32:51.803423
10189 09:32:52.407505 00480000 ################################################################
10190 09:32:52.407643
10191 09:32:53.044834 00500000 ################################################################
10192 09:32:53.045327
10193 09:32:53.690701 00580000 ################################################################
10194 09:32:53.691260
10195 09:32:54.318234 00600000 ################################################################
10196 09:32:54.318372
10197 09:32:54.934986 00680000 ################################################################
10198 09:32:54.935119
10199 09:32:55.489269 00700000 ################################################################
10200 09:32:55.489407
10201 09:32:56.107035 00780000 ################################################################
10202 09:32:56.107533
10203 09:32:56.775197 00800000 ################################################################
10204 09:32:56.775694
10205 09:32:57.448673 00880000 ################################################################
10206 09:32:57.449200
10207 09:32:58.108607 00900000 ################################################################
10208 09:32:58.108775
10209 09:32:58.692944 00980000 ################################################################
10210 09:32:58.693082
10211 09:32:59.248918 00a00000 ################################################################
10212 09:32:59.249057
10213 09:32:59.831201 00a80000 ################################################################
10214 09:32:59.831697
10215 09:33:00.405244 00b00000 ################################################################
10216 09:33:00.405380
10217 09:33:00.991915 00b80000 ################################################################
10218 09:33:00.992412
10219 09:33:01.574130 00c00000 ################################################################
10220 09:33:01.574664
10221 09:33:02.173637 00c80000 ################################################################
10222 09:33:02.173775
10223 09:33:02.741268 00d00000 ################################################################
10224 09:33:02.741402
10225 09:33:03.368046 00d80000 ################################################################
10226 09:33:03.368212
10227 09:33:04.027527 00e00000 ################################################################
10228 09:33:04.027716
10229 09:33:04.595160 00e80000 ################################################################
10230 09:33:04.595299
10231 09:33:05.226413 00f00000 ################################################################
10232 09:33:05.226555
10233 09:33:05.808026 00f80000 ################################################################
10234 09:33:05.808166
10235 09:33:06.462096 01000000 ################################################################
10236 09:33:06.462613
10237 09:33:07.167989 01080000 ################################################################
10238 09:33:07.168518
10239 09:33:07.756633 01100000 ################################################################
10240 09:33:07.756789
10241 09:33:08.326133 01180000 ################################################################
10242 09:33:08.326279
10243 09:33:08.997368 01200000 ################################################################
10244 09:33:08.997795
10245 09:33:09.701528 01280000 ################################################################
10246 09:33:09.702044
10247 09:33:10.415717 01300000 ################################################################
10248 09:33:10.415983
10249 09:33:11.132179 01380000 ################################################################
10250 09:33:11.132453
10251 09:33:11.853947 01400000 ################################################################
10252 09:33:11.854513
10253 09:33:12.562628 01480000 ################################################################
10254 09:33:12.563232
10255 09:33:13.260212 01500000 ################################################################
10256 09:33:13.260767
10257 09:33:13.930327 01580000 ################################################################
10258 09:33:13.930908
10259 09:33:14.623234 01600000 ################################################################
10260 09:33:14.623751
10261 09:33:15.344034 01680000 ################################################################
10262 09:33:15.344574
10263 09:33:16.040832 01700000 ################################################################
10264 09:33:16.041348
10265 09:33:16.738698 01780000 ################################################################
10266 09:33:16.739264
10267 09:33:17.457396 01800000 ################################################################
10268 09:33:17.457931
10269 09:33:18.163782 01880000 ################################################################
10270 09:33:18.164300
10271 09:33:18.861627 01900000 ################################################################
10272 09:33:18.862158
10273 09:33:19.551216 01980000 ################################################################
10274 09:33:19.551722
10275 09:33:20.245871 01a00000 ################################################################
10276 09:33:20.246386
10277 09:33:20.920934 01a80000 ################################################################
10278 09:33:20.921184
10279 09:33:21.636522 01b00000 ################################################################
10280 09:33:21.637032
10281 09:33:22.342775 01b80000 ################################################################
10282 09:33:22.343309
10283 09:33:23.000252 01c00000 ########################################################### done.
10284 09:33:23.000766
10285 09:33:23.003686 The bootfile was 29842098 bytes long.
10286 09:33:23.004110
10287 09:33:23.006903 Sending tftp read request... done.
10288 09:33:23.007321
10289 09:33:23.011121 Waiting for the transfer...
10290 09:33:23.011538
10291 09:33:23.011866 00000000 # done.
10292 09:33:23.012183
10293 09:33:23.017311 Command line loaded dynamically from TFTP file: 11826827/tftp-deploy-jtsi5kkd/kernel/cmdline
10294 09:33:23.017747
10295 09:33:23.040808 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10296 09:33:23.041379
10297 09:33:23.041745 Loading FIT.
10298 09:33:23.042086
10299 09:33:23.044045 Image ramdisk-1 has 18748527 bytes.
10300 09:33:23.044507
10301 09:33:23.047343 Image fdt-1 has 47278 bytes.
10302 09:33:23.047882
10303 09:33:23.050806 Image kernel-1 has 11044258 bytes.
10304 09:33:23.051266
10305 09:33:23.061366 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10306 09:33:23.061940
10307 09:33:23.077428 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10308 09:33:23.078020
10309 09:33:23.084106 Choosing best match conf-1 for compat google,spherion-rev2.
10310 09:33:23.084657
10311 09:33:23.088164 Connected to device vid:did:rid of 1ae0:0028:00
10312 09:33:23.099960
10313 09:33:23.103067 tpm_get_response: command 0x17b, return code 0x0
10314 09:33:23.103536
10315 09:33:23.106232 ec_init: CrosEC protocol v3 supported (256, 248)
10316 09:33:23.110108
10317 09:33:23.113746 tpm_cleanup: add release locality here.
10318 09:33:23.114211
10319 09:33:23.114577 Shutting down all USB controllers.
10320 09:33:23.114962
10321 09:33:23.116934 Removing current net device
10322 09:33:23.117393
10323 09:33:23.123732 Exiting depthcharge with code 4 at timestamp: 72226146
10324 09:33:23.124283
10325 09:33:23.127020 LZMA decompressing kernel-1 to 0x821a6718
10326 09:33:23.127483
10327 09:33:23.130628 LZMA decompressing kernel-1 to 0x40000000
10328 09:33:24.520114
10329 09:33:24.520669 jumping to kernel
10330 09:33:24.522382 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10331 09:33:24.523006 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10332 09:33:24.523431 Setting prompt string to ['Linux version [0-9]']
10333 09:33:24.523812 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10334 09:33:24.524194 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10335 09:33:24.601920
10336 09:33:24.605193 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10337 09:33:24.608687 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10338 09:33:24.609198 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10339 09:33:24.609595 Setting prompt string to []
10340 09:33:24.610008 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 09:33:24.610409 Using line separator: #'\n'#
10342 09:33:24.610791 No login prompt set.
10343 09:33:24.611163 Parsing kernel messages
10344 09:33:24.611475 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 09:33:24.612036 [login-action] Waiting for messages, (timeout 00:03:41)
10346 09:33:24.628350 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10347 09:33:24.632093 [ 0.000000] random: crng init done
10348 09:33:24.635191 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10349 09:33:24.638257 [ 0.000000] efi: UEFI not found.
10350 09:33:24.648274 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10351 09:33:24.655359 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10352 09:33:24.665177 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10353 09:33:24.674815 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10354 09:33:24.681952 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10355 09:33:24.685346 [ 0.000000] printk: bootconsole [mtk8250] enabled
10356 09:33:24.693514 [ 0.000000] NUMA: No NUMA configuration found
10357 09:33:24.700047 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10358 09:33:24.707017 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10359 09:33:24.707570 [ 0.000000] Zone ranges:
10360 09:33:24.713749 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10361 09:33:24.717272 [ 0.000000] DMA32 empty
10362 09:33:24.724024 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10363 09:33:24.727003 [ 0.000000] Movable zone start for each node
10364 09:33:24.729755 [ 0.000000] Early memory node ranges
10365 09:33:24.736625 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10366 09:33:24.743578 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10367 09:33:24.749888 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10368 09:33:24.757060 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10369 09:33:24.763248 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10370 09:33:24.770095 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10371 09:33:24.825788 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10372 09:33:24.832133 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10373 09:33:24.838914 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10374 09:33:24.842706 [ 0.000000] psci: probing for conduit method from DT.
10375 09:33:24.849177 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10376 09:33:24.852314 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10377 09:33:24.859140 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10378 09:33:24.862002 [ 0.000000] psci: SMC Calling Convention v1.2
10379 09:33:24.868825 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10380 09:33:24.872329 [ 0.000000] Detected VIPT I-cache on CPU0
10381 09:33:24.878815 [ 0.000000] CPU features: detected: GIC system register CPU interface
10382 09:33:24.885590 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10383 09:33:24.891868 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10384 09:33:24.898769 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10385 09:33:24.905453 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10386 09:33:24.912011 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10387 09:33:24.918664 [ 0.000000] alternatives: applying boot alternatives
10388 09:33:24.922376 [ 0.000000] Fallback order for Node 0: 0
10389 09:33:24.928713 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10390 09:33:24.932096 [ 0.000000] Policy zone: Normal
10391 09:33:24.955871 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10392 09:33:24.965318 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10393 09:33:24.978714 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10394 09:33:24.988615 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10395 09:33:24.995419 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10396 09:33:24.998501 <6>[ 0.000000] software IO TLB: area num 8.
10397 09:33:25.055925 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10398 09:33:25.204952 <6>[ 0.000000] Memory: 7951180K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 401588K reserved, 32768K cma-reserved)
10399 09:33:25.211719 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10400 09:33:25.218461 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10401 09:33:25.221562 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10402 09:33:25.228521 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10403 09:33:25.235085 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10404 09:33:25.238026 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10405 09:33:25.248803 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10406 09:33:25.254965 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10407 09:33:25.258109 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10408 09:33:25.266077 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10409 09:33:25.269142 <6>[ 0.000000] GICv3: 608 SPIs implemented
10410 09:33:25.275977 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10411 09:33:25.279457 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10412 09:33:25.282992 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10413 09:33:25.292469 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10414 09:33:25.302355 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10415 09:33:25.316247 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10416 09:33:25.322400 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10417 09:33:25.331578 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10418 09:33:25.344511 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10419 09:33:25.351137 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10420 09:33:25.357772 <6>[ 0.009231] Console: colour dummy device 80x25
10421 09:33:25.367983 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10422 09:33:25.371439 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10423 09:33:25.377781 <6>[ 0.029270] LSM: Security Framework initializing
10424 09:33:25.384607 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 09:33:25.394517 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 09:33:25.401511 <6>[ 0.051486] cblist_init_generic: Setting adjustable number of callback queues.
10427 09:33:25.407663 <6>[ 0.058928] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 09:33:25.418133 <6>[ 0.065267] cblist_init_generic: Setting adjustable number of callback queues.
10429 09:33:25.421389 <6>[ 0.072694] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 09:33:25.427946 <6>[ 0.079130] rcu: Hierarchical SRCU implementation.
10431 09:33:25.434786 <6>[ 0.084146] rcu: Max phase no-delay instances is 1000.
10432 09:33:25.441155 <6>[ 0.091174] EFI services will not be available.
10433 09:33:25.444409 <6>[ 0.096130] smp: Bringing up secondary CPUs ...
10434 09:33:25.452529 <6>[ 0.101208] Detected VIPT I-cache on CPU1
10435 09:33:25.458920 <6>[ 0.101277] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10436 09:33:25.466036 <6>[ 0.101307] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10437 09:33:25.469508 <6>[ 0.101641] Detected VIPT I-cache on CPU2
10438 09:33:25.475432 <6>[ 0.101692] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10439 09:33:25.482571 <6>[ 0.101709] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10440 09:33:25.488915 <6>[ 0.101967] Detected VIPT I-cache on CPU3
10441 09:33:25.495427 <6>[ 0.102016] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10442 09:33:25.502446 <6>[ 0.102030] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10443 09:33:25.506020 <6>[ 0.102338] CPU features: detected: Spectre-v4
10444 09:33:25.512082 <6>[ 0.102344] CPU features: detected: Spectre-BHB
10445 09:33:25.515628 <6>[ 0.102349] Detected PIPT I-cache on CPU4
10446 09:33:25.522212 <6>[ 0.102407] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10447 09:33:25.529007 <6>[ 0.102425] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10448 09:33:25.532267 <6>[ 0.102718] Detected PIPT I-cache on CPU5
10449 09:33:25.542193 <6>[ 0.102781] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10450 09:33:25.548520 <6>[ 0.102798] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10451 09:33:25.551865 <6>[ 0.103079] Detected PIPT I-cache on CPU6
10452 09:33:25.558380 <6>[ 0.103145] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10453 09:33:25.565704 <6>[ 0.103162] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10454 09:33:25.568817 <6>[ 0.103458] Detected PIPT I-cache on CPU7
10455 09:33:25.578499 <6>[ 0.103522] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10456 09:33:25.585220 <6>[ 0.103538] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10457 09:33:25.588430 <6>[ 0.103586] smp: Brought up 1 node, 8 CPUs
10458 09:33:25.595249 <6>[ 0.244851] SMP: Total of 8 processors activated.
10459 09:33:25.598681 <6>[ 0.249772] CPU features: detected: 32-bit EL0 Support
10460 09:33:25.608662 <6>[ 0.255135] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10461 09:33:25.615234 <6>[ 0.263990] CPU features: detected: Common not Private translations
10462 09:33:25.618278 <6>[ 0.270466] CPU features: detected: CRC32 instructions
10463 09:33:25.625488 <6>[ 0.275818] CPU features: detected: RCpc load-acquire (LDAPR)
10464 09:33:25.631720 <6>[ 0.281778] CPU features: detected: LSE atomic instructions
10465 09:33:25.638509 <6>[ 0.287559] CPU features: detected: Privileged Access Never
10466 09:33:25.641658 <6>[ 0.293339] CPU features: detected: RAS Extension Support
10467 09:33:25.648181 <6>[ 0.298948] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10468 09:33:25.654943 <6>[ 0.306188] CPU: All CPU(s) started at EL2
10469 09:33:25.661356 <6>[ 0.310531] alternatives: applying system-wide alternatives
10470 09:33:25.669597 <6>[ 0.321280] devtmpfs: initialized
10471 09:33:25.682492 <6>[ 0.330379] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10472 09:33:25.692187 <6>[ 0.340339] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10473 09:33:25.698847 <6>[ 0.348345] pinctrl core: initialized pinctrl subsystem
10474 09:33:25.702404 <6>[ 0.354994] DMI not present or invalid.
10475 09:33:25.709506 <6>[ 0.359402] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10476 09:33:25.718839 <6>[ 0.366266] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10477 09:33:25.725841 <6>[ 0.373845] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10478 09:33:25.735563 <6>[ 0.382056] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10479 09:33:25.738857 <6>[ 0.390296] audit: initializing netlink subsys (disabled)
10480 09:33:25.749212 <5>[ 0.395984] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10481 09:33:25.752450 <6>[ 0.396688] thermal_sys: Registered thermal governor 'step_wise'
10482 09:33:25.762468 <6>[ 0.403949] thermal_sys: Registered thermal governor 'power_allocator'
10483 09:33:25.765486 <6>[ 0.410201] cpuidle: using governor menu
10484 09:33:25.769098 <6>[ 0.421156] NET: Registered PF_QIPCRTR protocol family
10485 09:33:25.779104 <6>[ 0.426648] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10486 09:33:25.782459 <6>[ 0.433754] ASID allocator initialised with 32768 entries
10487 09:33:25.788892 <6>[ 0.440317] Serial: AMBA PL011 UART driver
10488 09:33:25.798102 <4>[ 0.449082] Trying to register duplicate clock ID: 134
10489 09:33:25.852490 <6>[ 0.506786] KASLR enabled
10490 09:33:25.866579 <6>[ 0.514544] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10491 09:33:25.872985 <6>[ 0.521557] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10492 09:33:25.880047 <6>[ 0.528046] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10493 09:33:25.886563 <6>[ 0.535053] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10494 09:33:25.893117 <6>[ 0.541537] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10495 09:33:25.899851 <6>[ 0.548539] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10496 09:33:25.906835 <6>[ 0.555025] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10497 09:33:25.913500 <6>[ 0.562032] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10498 09:33:25.916633 <6>[ 0.569543] ACPI: Interpreter disabled.
10499 09:33:25.924549 <6>[ 0.575901] iommu: Default domain type: Translated
10500 09:33:25.930982 <6>[ 0.581013] iommu: DMA domain TLB invalidation policy: strict mode
10501 09:33:25.934543 <5>[ 0.587670] SCSI subsystem initialized
10502 09:33:25.941432 <6>[ 0.591817] usbcore: registered new interface driver usbfs
10503 09:33:25.947992 <6>[ 0.597550] usbcore: registered new interface driver hub
10504 09:33:25.951332 <6>[ 0.603103] usbcore: registered new device driver usb
10505 09:33:25.958126 <6>[ 0.609181] pps_core: LinuxPPS API ver. 1 registered
10506 09:33:25.968078 <6>[ 0.614374] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10507 09:33:25.971621 <6>[ 0.623715] PTP clock support registered
10508 09:33:25.974911 <6>[ 0.627957] EDAC MC: Ver: 3.0.0
10509 09:33:25.982101 <6>[ 0.633112] FPGA manager framework
10510 09:33:25.985044 <6>[ 0.636791] Advanced Linux Sound Architecture Driver Initialized.
10511 09:33:25.988848 <6>[ 0.643558] vgaarb: loaded
10512 09:33:25.995325 <6>[ 0.646734] clocksource: Switched to clocksource arch_sys_counter
10513 09:33:26.002310 <5>[ 0.653171] VFS: Disk quotas dquot_6.6.0
10514 09:33:26.008436 <6>[ 0.657357] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10515 09:33:26.011717 <6>[ 0.664548] pnp: PnP ACPI: disabled
10516 09:33:26.019961 <6>[ 0.671236] NET: Registered PF_INET protocol family
10517 09:33:26.026765 <6>[ 0.676822] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10518 09:33:26.041092 <6>[ 0.689108] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10519 09:33:26.050880 <6>[ 0.697922] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10520 09:33:26.057788 <6>[ 0.705892] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10521 09:33:26.064655 <6>[ 0.714588] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10522 09:33:26.077186 <6>[ 0.724329] TCP: Hash tables configured (established 65536 bind 65536)
10523 09:33:26.083184 <6>[ 0.731187] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 09:33:26.089883 <6>[ 0.738386] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 09:33:26.096461 <6>[ 0.746083] NET: Registered PF_UNIX/PF_LOCAL protocol family
10526 09:33:26.103337 <6>[ 0.752259] RPC: Registered named UNIX socket transport module.
10527 09:33:26.106757 <6>[ 0.758408] RPC: Registered udp transport module.
10528 09:33:26.113116 <6>[ 0.763341] RPC: Registered tcp transport module.
10529 09:33:26.119599 <6>[ 0.768275] RPC: Registered tcp NFSv4.1 backchannel transport module.
10530 09:33:26.123504 <6>[ 0.774939] PCI: CLS 0 bytes, default 64
10531 09:33:26.126756 <6>[ 0.779335] Unpacking initramfs...
10532 09:33:26.150842 <6>[ 0.798844] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10533 09:33:26.160814 <6>[ 0.807517] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10534 09:33:26.164201 <6>[ 0.816383] kvm [1]: IPA Size Limit: 40 bits
10535 09:33:26.170913 <6>[ 0.820915] kvm [1]: GICv3: no GICV resource entry
10536 09:33:26.174184 <6>[ 0.825938] kvm [1]: disabling GICv2 emulation
10537 09:33:26.181422 <6>[ 0.830624] kvm [1]: GIC system register CPU interface enabled
10538 09:33:26.184212 <6>[ 0.836808] kvm [1]: vgic interrupt IRQ18
10539 09:33:26.190973 <6>[ 0.841173] kvm [1]: VHE mode initialized successfully
10540 09:33:26.197840 <5>[ 0.847751] Initialise system trusted keyrings
10541 09:33:26.203956 <6>[ 0.852576] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10542 09:33:26.211331 <6>[ 0.862558] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10543 09:33:26.217818 <5>[ 0.869032] NFS: Registering the id_resolver key type
10544 09:33:26.221106 <5>[ 0.874334] Key type id_resolver registered
10545 09:33:26.228083 <5>[ 0.878750] Key type id_legacy registered
10546 09:33:26.234454 <6>[ 0.883027] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10547 09:33:26.241415 <6>[ 0.889947] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10548 09:33:26.248050 <6>[ 0.897662] 9p: Installing v9fs 9p2000 file system support
10549 09:33:26.283841 <5>[ 0.935201] Key type asymmetric registered
10550 09:33:26.286818 <5>[ 0.939534] Asymmetric key parser 'x509' registered
10551 09:33:26.297613 <6>[ 0.944719] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10552 09:33:26.300705 <6>[ 0.952342] io scheduler mq-deadline registered
10553 09:33:26.303565 <6>[ 0.957109] io scheduler kyber registered
10554 09:33:26.319819 <6>[ 0.974314] EINJ: ACPI disabled.
10555 09:33:26.354986 <4>[ 1.000143] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 09:33:26.364945 <4>[ 1.010762] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 09:33:26.379777 <6>[ 1.031594] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10558 09:33:26.387890 <6>[ 1.039573] printk: console [ttyS0] disabled
10559 09:33:26.416642 <6>[ 1.064236] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10560 09:33:26.422832 <6>[ 1.073706] printk: console [ttyS0] enabled
10561 09:33:26.426403 <6>[ 1.073706] printk: console [ttyS0] enabled
10562 09:33:26.429795 <6>[ 1.082598] printk: bootconsole [mtk8250] disabled
10563 09:33:26.436312 <6>[ 1.082598] printk: bootconsole [mtk8250] disabled
10564 09:33:26.442774 <6>[ 1.093811] SuperH (H)SCI(F) driver initialized
10565 09:33:26.446501 <6>[ 1.099109] msm_serial: driver initialized
10566 09:33:26.460459 <6>[ 1.108082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10567 09:33:26.469739 <6>[ 1.116631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10568 09:33:26.476916 <6>[ 1.125172] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10569 09:33:26.487030 <6>[ 1.133805] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10570 09:33:26.493593 <6>[ 1.142511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10571 09:33:26.503409 <6>[ 1.151231] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10572 09:33:26.513027 <6>[ 1.159776] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10573 09:33:26.519932 <6>[ 1.168575] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10574 09:33:26.530077 <6>[ 1.177119] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10575 09:33:26.541326 <6>[ 1.192758] loop: module loaded
10576 09:33:26.548277 <6>[ 1.198826] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10577 09:33:26.570672 <4>[ 1.222154] mtk-pmic-keys: Failed to locate of_node [id: -1]
10578 09:33:26.577370 <6>[ 1.228961] megasas: 07.719.03.00-rc1
10579 09:33:26.587227 <6>[ 1.238690] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10580 09:33:26.595045 <6>[ 1.246117] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10581 09:33:26.611427 <6>[ 1.262670] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10582 09:33:26.668177 <6>[ 1.312818] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10583 09:33:26.917175 <6>[ 1.569326] Freeing initrd memory: 18304K
10584 09:33:26.929210 <6>[ 1.580996] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10585 09:33:26.940411 <6>[ 1.591937] tun: Universal TUN/TAP device driver, 1.6
10586 09:33:26.944283 <6>[ 1.597978] thunder_xcv, ver 1.0
10587 09:33:26.947755 <6>[ 1.601482] thunder_bgx, ver 1.0
10588 09:33:26.950413 <6>[ 1.604978] nicpf, ver 1.0
10589 09:33:26.960599 <6>[ 1.609017] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10590 09:33:26.964175 <6>[ 1.616494] hns3: Copyright (c) 2017 Huawei Corporation.
10591 09:33:26.967489 <6>[ 1.622083] hclge is initializing
10592 09:33:26.974234 <6>[ 1.625658] e1000: Intel(R) PRO/1000 Network Driver
10593 09:33:26.981454 <6>[ 1.630788] e1000: Copyright (c) 1999-2006 Intel Corporation.
10594 09:33:26.984279 <6>[ 1.636799] e1000e: Intel(R) PRO/1000 Network Driver
10595 09:33:26.991087 <6>[ 1.642015] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10596 09:33:26.997634 <6>[ 1.648203] igb: Intel(R) Gigabit Ethernet Network Driver
10597 09:33:27.004261 <6>[ 1.653852] igb: Copyright (c) 2007-2014 Intel Corporation.
10598 09:33:27.011193 <6>[ 1.659689] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10599 09:33:27.014671 <6>[ 1.666207] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10600 09:33:27.021163 <6>[ 1.672669] sky2: driver version 1.30
10601 09:33:27.027819 <6>[ 1.677687] VFIO - User Level meta-driver version: 0.3
10602 09:33:27.034190 <6>[ 1.685929] usbcore: registered new interface driver usb-storage
10603 09:33:27.041339 <6>[ 1.692375] usbcore: registered new device driver onboard-usb-hub
10604 09:33:27.050592 <6>[ 1.701500] mt6397-rtc mt6359-rtc: registered as rtc0
10605 09:33:27.059931 <6>[ 1.706968] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:33:27 UTC (1697794407)
10606 09:33:27.063396 <6>[ 1.716534] i2c_dev: i2c /dev entries driver
10607 09:33:27.080507 <6>[ 1.728243] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10608 09:33:27.101396 <6>[ 1.752237] cpu cpu0: EM: created perf domain
10609 09:33:27.104435 <6>[ 1.757177] cpu cpu4: EM: created perf domain
10610 09:33:27.111705 <6>[ 1.762780] sdhci: Secure Digital Host Controller Interface driver
10611 09:33:27.118311 <6>[ 1.769209] sdhci: Copyright(c) Pierre Ossman
10612 09:33:27.124767 <6>[ 1.774174] Synopsys Designware Multimedia Card Interface Driver
10613 09:33:27.131347 <6>[ 1.780806] sdhci-pltfm: SDHCI platform and OF driver helper
10614 09:33:27.134849 <6>[ 1.780936] mmc0: CQHCI version 5.10
10615 09:33:27.141627 <6>[ 1.790783] ledtrig-cpu: registered to indicate activity on CPUs
10616 09:33:27.148415 <6>[ 1.797764] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10617 09:33:27.155388 <6>[ 1.804809] usbcore: registered new interface driver usbhid
10618 09:33:27.158439 <6>[ 1.810634] usbhid: USB HID core driver
10619 09:33:27.165147 <6>[ 1.814835] spi_master spi0: will run message pump with realtime priority
10620 09:33:27.209736 <6>[ 1.854664] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10621 09:33:27.229379 <6>[ 1.870618] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10622 09:33:27.236382 <6>[ 1.885429] cros-ec-spi spi0.0: Chrome EC device registered
10623 09:33:27.239548 <6>[ 1.891429] mmc0: Command Queue Engine enabled
10624 09:33:27.246893 <6>[ 1.896172] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10625 09:33:27.257004 <6>[ 1.903901] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10626 09:33:27.259870 <6>[ 1.904002] mmcblk0: mmc0:0001 DA4128 116 GiB
10627 09:33:27.267070 <6>[ 1.914328] NET: Registered PF_PACKET protocol family
10628 09:33:27.269918 <6>[ 1.923313] 9pnet: Installing 9P2000 support
10629 09:33:27.276469 <6>[ 1.925491] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10630 09:33:27.283341 <5>[ 1.927895] Key type dns_resolver registered
10631 09:33:27.287134 <6>[ 1.935094] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10632 09:33:27.290670 <6>[ 1.938603] registered taskstats version 1
10633 09:33:27.296758 <6>[ 1.944308] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10634 09:33:27.300079 <5>[ 1.947874] Loading compiled-in X.509 certificates
10635 09:33:27.308194 <6>[ 1.959222] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 09:33:27.322427 <4>[ 1.967651] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 09:33:27.332462 <4>[ 1.978402] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 09:33:27.339037 <3>[ 1.988930] debugfs: File 'uA_load' in directory '/' already present!
10639 09:33:27.346279 <3>[ 1.995632] debugfs: File 'min_uV' in directory '/' already present!
10640 09:33:27.352407 <3>[ 2.002240] debugfs: File 'max_uV' in directory '/' already present!
10641 09:33:27.359618 <3>[ 2.008848] debugfs: File 'constraint_flags' in directory '/' already present!
10642 09:33:27.369821 <3>[ 2.018339] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10643 09:33:27.381374 <6>[ 2.032531] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 09:33:27.387646 <6>[ 2.039352] xhci-mtk 11200000.usb: xHCI Host Controller
10645 09:33:27.394568 <6>[ 2.044849] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 09:33:27.404867 <6>[ 2.052756] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 09:33:27.411658 <6>[ 2.062222] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 09:33:27.418251 <6>[ 2.068321] xhci-mtk 11200000.usb: xHCI Host Controller
10649 09:33:27.425237 <6>[ 2.073809] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 09:33:27.431574 <6>[ 2.081472] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 09:33:27.438290 <6>[ 2.089365] hub 1-0:1.0: USB hub found
10652 09:33:27.441607 <6>[ 2.093390] hub 1-0:1.0: 1 port detected
10653 09:33:27.448979 <6>[ 2.097703] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 09:33:27.455239 <6>[ 2.106491] hub 2-0:1.0: USB hub found
10655 09:33:27.458189 <6>[ 2.110512] hub 2-0:1.0: 1 port detected
10656 09:33:27.466951 <6>[ 2.118628] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 09:33:27.478310 <6>[ 2.126304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10658 09:33:27.485227 <6>[ 2.134325] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10659 09:33:27.495015 <4>[ 2.142237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10660 09:33:27.501931 <6>[ 2.151768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10661 09:33:27.512105 <6>[ 2.159845] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10662 09:33:27.518598 <6>[ 2.167869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10663 09:33:27.528227 <6>[ 2.175792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10664 09:33:27.535189 <6>[ 2.183611] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10665 09:33:27.544871 <6>[ 2.191429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10666 09:33:27.551627 <6>[ 2.201392] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10667 09:33:27.562178 <6>[ 2.209753] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10668 09:33:27.568574 <6>[ 2.218099] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10669 09:33:27.578324 <6>[ 2.226437] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10670 09:33:27.585148 <6>[ 2.234777] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10671 09:33:27.595475 <6>[ 2.243117] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10672 09:33:27.601972 <6>[ 2.251462] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10673 09:33:27.612325 <6>[ 2.259801] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10674 09:33:27.618505 <6>[ 2.268139] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10675 09:33:27.628593 <6>[ 2.276476] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10676 09:33:27.635356 <6>[ 2.284815] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10677 09:33:27.645709 <6>[ 2.293154] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10678 09:33:27.652252 <6>[ 2.301498] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10679 09:33:27.662582 <6>[ 2.309837] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10680 09:33:27.668479 <6>[ 2.318176] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10681 09:33:27.675274 <6>[ 2.326899] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10682 09:33:27.682384 <6>[ 2.334031] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10683 09:33:27.689411 <6>[ 2.340787] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10684 09:33:27.699534 <6>[ 2.347545] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10685 09:33:27.706052 <6>[ 2.354482] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10686 09:33:27.712611 <6>[ 2.361340] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10687 09:33:27.722702 <6>[ 2.370473] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10688 09:33:27.733004 <6>[ 2.379593] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10689 09:33:27.742898 <6>[ 2.388887] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10690 09:33:27.752911 <6>[ 2.398356] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10691 09:33:27.759200 <6>[ 2.407823] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10692 09:33:27.769404 <6>[ 2.416944] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10693 09:33:27.779292 <6>[ 2.426411] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10694 09:33:27.789322 <6>[ 2.435532] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10695 09:33:27.798792 <6>[ 2.444828] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10696 09:33:27.808728 <6>[ 2.454988] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10697 09:33:27.818656 <6>[ 2.466535] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10698 09:33:27.825202 <6>[ 2.476437] Trying to probe devices needed for running init ...
10699 09:33:27.870404 <6>[ 2.518975] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10700 09:33:28.025836 <6>[ 2.677145] hub 1-1:1.0: USB hub found
10701 09:33:28.028832 <6>[ 2.681663] hub 1-1:1.0: 4 ports detected
10702 09:33:28.150376 <6>[ 2.798997] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10703 09:33:28.177157 <6>[ 2.828451] hub 2-1:1.0: USB hub found
10704 09:33:28.180316 <6>[ 2.832921] hub 2-1:1.0: 3 ports detected
10705 09:33:28.350835 <6>[ 2.999092] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10706 09:33:28.482270 <6>[ 3.133802] hub 1-1.4:1.0: USB hub found
10707 09:33:28.486286 <6>[ 3.138376] hub 1-1.4:1.0: 2 ports detected
10708 09:33:28.562538 <6>[ 3.211057] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10709 09:33:28.782364 <6>[ 3.431021] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10710 09:33:28.974301 <6>[ 3.623030] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10711 09:33:40.111858 <6>[ 14.768074] ALSA device list:
10712 09:33:40.117945 <6>[ 14.771365] No soundcards found.
10713 09:33:40.125895 <6>[ 14.779280] Freeing unused kernel memory: 8384K
10714 09:33:40.129816 <6>[ 14.784272] Run /init as init process
10715 09:33:40.140947 Loading, please wait...
10716 09:33:40.170791 Starting systemd-udevd version 252.6-1
10717 09:33:40.397114 <6>[ 15.046604] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10718 09:33:40.414374 <6>[ 15.064285] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10719 09:33:40.424754 <6>[ 15.074156] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10720 09:33:40.431371 <6>[ 15.076288] remoteproc remoteproc0: scp is available
10721 09:33:40.438263 <6>[ 15.083659] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 09:33:40.444910 <6>[ 15.088280] remoteproc remoteproc0: powering up scp
10723 09:33:40.451423 <6>[ 15.102146] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10724 09:33:40.458179 <6>[ 15.102610] mc: Linux media interface: v0.10
10725 09:33:40.461464 <6>[ 15.105830] usbcore: registered new interface driver r8152
10726 09:33:40.468204 <6>[ 15.110608] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10727 09:33:40.478046 <3>[ 15.127938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 09:33:40.485150 <3>[ 15.136159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 09:33:40.491251 <6>[ 15.136376] usbcore: registered new interface driver cdc_ether
10730 09:33:40.501904 <3>[ 15.144269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 09:33:40.508381 <4>[ 15.144896] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10732 09:33:40.514902 <4>[ 15.144990] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10733 09:33:40.525378 <3>[ 15.174025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 09:33:40.531343 <6>[ 15.174892] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10735 09:33:40.543512 <3>[ 15.192519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 09:33:40.546103 <6>[ 15.192610] Bluetooth: Core ver 2.22
10737 09:33:40.556032 <3>[ 15.200700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 09:33:40.559509 <6>[ 15.202540] videodev: Linux video capture interface: v2.00
10739 09:33:40.565960 <6>[ 15.205620] NET: Registered PF_BLUETOOTH protocol family
10740 09:33:40.572770 <3>[ 15.212612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 09:33:40.582635 <3>[ 15.212624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 09:33:40.589244 <3>[ 15.212776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 09:33:40.596211 <6>[ 15.218918] Bluetooth: HCI device and connection manager initialized
10744 09:33:40.602696 <6>[ 15.221531] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10745 09:33:40.609240 <6>[ 15.221539] pci_bus 0000:00: root bus resource [bus 00-ff]
10746 09:33:40.616314 <6>[ 15.221547] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10747 09:33:40.625651 <6>[ 15.221552] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10748 09:33:40.632603 <6>[ 15.221629] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10749 09:33:40.640129 <6>[ 15.221658] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10750 09:33:40.643386 <6>[ 15.221773] pci 0000:00:00.0: supports D1 D2
10751 09:33:40.653448 <6>[ 15.221778] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10752 09:33:40.660149 <3>[ 15.224251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 09:33:40.666377 <6>[ 15.224550] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10754 09:33:40.673252 <6>[ 15.224897] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10755 09:33:40.683317 <6>[ 15.224934] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10756 09:33:40.689847 <6>[ 15.224960] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10757 09:33:40.696606 <6>[ 15.224980] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10758 09:33:40.702920 <6>[ 15.225139] pci 0000:01:00.0: supports D1 D2
10759 09:33:40.709563 <6>[ 15.225142] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 09:33:40.716434 <6>[ 15.231547] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10761 09:33:40.722808 <6>[ 15.232193] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10762 09:33:40.733348 <3>[ 15.240213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 09:33:40.736465 <6>[ 15.240502] Bluetooth: HCI socket layer initialized
10764 09:33:40.742827 <6>[ 15.240507] Bluetooth: L2CAP socket layer initialized
10765 09:33:40.746263 <6>[ 15.240519] Bluetooth: SCO socket layer initialized
10766 09:33:40.753267 <6>[ 15.242833] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10767 09:33:40.762807 <6>[ 15.242880] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10768 09:33:40.769267 <6>[ 15.242888] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10769 09:33:40.779641 <6>[ 15.242901] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10770 09:33:40.786138 <6>[ 15.242917] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10771 09:33:40.796074 <6>[ 15.242933] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10772 09:33:40.799654 <6>[ 15.242950] pci 0000:00:00.0: PCI bridge to [bus 01]
10773 09:33:40.809506 <6>[ 15.242958] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10774 09:33:40.812773 <6>[ 15.243210] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10775 09:33:40.818977 <6>[ 15.248301] remoteproc remoteproc0: remote processor scp is now up
10776 09:33:40.825539 <6>[ 15.250676] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10777 09:33:40.832287 <6>[ 15.250950] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10778 09:33:40.842230 <6>[ 15.251289] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10779 09:33:40.852131 <6>[ 15.251548] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10780 09:33:40.862822 <6>[ 15.254673] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10781 09:33:40.869074 <3>[ 15.254893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 09:33:40.875683 <6>[ 15.262454] usbcore: registered new interface driver r8153_ecm
10783 09:33:40.882387 <6>[ 15.263409] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10784 09:33:40.889222 <3>[ 15.267670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 09:33:40.899073 <4>[ 15.268582] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10786 09:33:40.902267 <4>[ 15.268582] Fallback method does not support PEC.
10787 09:33:40.912082 <5>[ 15.269607] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10788 09:33:40.918878 <6>[ 15.274831] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10789 09:33:40.925417 <5>[ 15.282879] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10790 09:33:40.935925 <4>[ 15.282934] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10791 09:33:40.941710 <6>[ 15.282939] cfg80211: failed to load regulatory.db
10792 09:33:40.948471 <3>[ 15.284595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 09:33:40.955304 <3>[ 15.284602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 09:33:40.965259 <3>[ 15.284607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 09:33:40.971671 <3>[ 15.284610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 09:33:40.981969 <3>[ 15.284637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 09:33:40.991665 <4>[ 15.291371] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10798 09:33:40.998380 <6>[ 15.293800] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10799 09:33:41.004774 <6>[ 15.304898] usbcore: registered new interface driver btusb
10800 09:33:41.014992 <4>[ 15.305241] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10801 09:33:41.021597 <3>[ 15.305248] Bluetooth: hci0: Failed to load firmware file (-2)
10802 09:33:41.025247 <3>[ 15.305250] Bluetooth: hci0: Failed to set up firmware (-2)
10803 09:33:41.038062 <4>[ 15.305252] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10804 09:33:41.044883 <4>[ 15.310077] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10805 09:33:41.051348 <6>[ 15.311301] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10806 09:33:41.064695 <6>[ 15.312399] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10807 09:33:41.071615 <6>[ 15.312489] usbcore: registered new interface driver uvcvideo
10808 09:33:41.078180 <6>[ 15.341213] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10809 09:33:41.084757 <3>[ 15.348717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 09:33:41.091447 <6>[ 15.362322] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10811 09:33:41.097948 <6>[ 15.751362] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10812 09:33:41.114024 <6>[ 15.766830] r8152 2-1.3:1.0 eth0: v1.12.13
10813 09:33:41.125161 <6>[ 15.778081] mt7921e 0000:01:00.0: ASIC revision: 79610010
10814 09:33:41.135360 <3>[ 15.778640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 09:33:41.141685 <6>[ 15.788482] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10816 09:33:41.232485 <4>[ 15.878711] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 09:33:41.235520 Begin: Loading essential drivers ... done.
10818 09:33:41.242982 Begin: Running /scripts/init-premount ... done.
10819 09:33:41.249591 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10820 09:33:41.259844 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10821 09:33:41.262919 Device /sys/class/net/enx002432307852 found
10822 09:33:41.263354 done.
10823 09:33:41.275876 Begin: Waiting up to 180 secs for any network device to become available ... done.
10824 09:33:41.329481 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10825 09:33:41.350814 <4>[ 15.997404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 09:33:41.469510 <4>[ 16.116294] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 09:33:41.585497 <4>[ 16.232021] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 09:33:41.701648 <4>[ 16.348013] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 09:33:41.817184 <4>[ 16.463916] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 09:33:41.933262 <4>[ 16.579900] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 09:33:42.049701 <4>[ 16.695760] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10832 09:33:42.165099 <4>[ 16.811747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10833 09:33:42.280712 <4>[ 16.927558] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 09:33:42.388515 <3>[ 17.041631] mt7921e 0000:01:00.0: hardware init failed
10835 09:33:42.510911 <6>[ 17.164279] r8152 2-1.3:1.0 enx002432307852: carrier on
10836 09:33:42.553797 IP-Config: no response after 2 secs - giving up
10837 09:33:42.600492 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10838 09:33:43.699999 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10839 09:33:43.706572 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10840 09:33:43.713491 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10841 09:33:43.719979 host : mt8192-asurada-spherion-r0-cbg-3
10842 09:33:43.726972 domain : lava-rack
10843 09:33:43.730294 rootserver: 192.168.201.1 rootpath:
10844 09:33:43.733104 filename :
10845 09:33:43.840091 done.
10846 09:33:43.848142 Begin: Running /scripts/nfs-bottom ... done.
10847 09:33:43.870381 Begin: Running /scripts/init-bottom ... done.
10848 09:33:45.314680 <6>[ 19.968090] NET: Registered PF_INET6 protocol family
10849 09:33:45.321874 <6>[ 19.975466] Segment Routing with IPv6
10850 09:33:45.324966 <6>[ 19.979493] In-situ OAM (IOAM) with IPv6
10851 09:33:45.523509 <30>[ 20.150672] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10852 09:33:45.530106 <30>[ 20.183025] systemd[1]: Detected architecture arm64.
10853 09:33:45.540232
10854 09:33:45.543600 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10855 09:33:45.544177
10856 09:33:45.567693 <30>[ 20.221190] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10857 09:33:46.808570 <30>[ 21.459015] systemd[1]: Queued start job for default target graphical.target.
10858 09:33:46.853720 <30>[ 21.504155] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10859 09:33:46.860329 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10860 09:33:46.882785 <30>[ 21.532856] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10861 09:33:46.888966 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10862 09:33:46.910589 <30>[ 21.560760] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10863 09:33:46.920578 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10864 09:33:46.938904 <30>[ 21.589204] systemd[1]: Created slice user.slice - User and Session Slice.
10865 09:33:46.945426 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10866 09:33:46.968729 <30>[ 21.615802] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10867 09:33:46.975675 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10868 09:33:46.996602 <30>[ 21.643275] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10869 09:33:47.002648 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10870 09:33:47.031593 <30>[ 21.671696] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10871 09:33:47.041339 <30>[ 21.691689] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10872 09:33:47.047997 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10873 09:33:47.069316 <30>[ 21.719505] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10874 09:33:47.078918 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10875 09:33:47.093914 <30>[ 21.747547] systemd[1]: Reached target paths.target - Path Units.
10876 09:33:47.100651 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10877 09:33:47.121216 <30>[ 21.771517] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10878 09:33:47.128132 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10879 09:33:47.141487 <30>[ 21.795020] systemd[1]: Reached target slices.target - Slice Units.
10880 09:33:47.151583 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10881 09:33:47.166040 <30>[ 21.819521] systemd[1]: Reached target swap.target - Swaps.
10882 09:33:47.172805 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10883 09:33:47.192888 <30>[ 21.843112] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10884 09:33:47.202500 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10885 09:33:47.221803 <30>[ 21.871935] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10886 09:33:47.231953 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10887 09:33:47.252025 <30>[ 21.902715] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10888 09:33:47.262260 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10889 09:33:47.278237 <30>[ 21.928688] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10890 09:33:47.288329 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10891 09:33:47.305132 <30>[ 21.955668] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10892 09:33:47.312238 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10893 09:33:47.329999 <30>[ 21.980724] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10894 09:33:47.340068 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10895 09:33:47.361114 <30>[ 22.011599] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10896 09:33:47.371126 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10897 09:33:47.389270 <30>[ 22.039533] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10898 09:33:47.398940 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10899 09:33:47.456776 <30>[ 22.107156] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10900 09:33:47.463408 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10901 09:33:47.484320 <30>[ 22.135057] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10902 09:33:47.491165 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10903 09:33:47.513326 <30>[ 22.164056] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10904 09:33:47.520110 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10905 09:33:47.547727 <30>[ 22.191642] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10906 09:33:47.560876 <30>[ 22.211486] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10907 09:33:47.571374 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10908 09:33:47.594166 <30>[ 22.244872] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10909 09:33:47.600912 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10910 09:33:47.625481 <30>[ 22.275380] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10911 09:33:47.634235 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10912 09:33:47.657783 <30>[ 22.308513] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10913 09:33:47.664661 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10914 09:33:47.674578 <6>[ 22.323447] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10915 09:33:47.686563 <30>[ 22.337550] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10916 09:33:47.696509 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10917 09:33:47.718457 <30>[ 22.368991] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10918 09:33:47.725420 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10919 09:33:47.748564 <30>[ 22.399186] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10920 09:33:47.754996 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10921 09:33:47.762885 <6>[ 22.416856] fuse: init (API version 7.37)
10922 09:33:47.813343 <30>[ 22.463912] systemd[1]: Starting systemd-journald.service - Journal Service...
10923 09:33:47.820084 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10924 09:33:47.854559 <30>[ 22.505340] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10925 09:33:47.860839 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10926 09:33:47.887233 <30>[ 22.534986] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10927 09:33:47.893952 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10928 09:33:47.916268 <30>[ 22.567239] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10929 09:33:47.926150 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10930 09:33:47.948895 <30>[ 22.599624] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10931 09:33:47.958697 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10932 09:33:47.985351 <30>[ 22.635824] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10933 09:33:47.991971 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10934 09:33:48.011502 <3>[ 22.662077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 09:33:48.021953 <30>[ 22.672239] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10936 09:33:48.028265 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10937 09:33:48.044950 <3>[ 22.695472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 09:33:48.054856 <30>[ 22.704846] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10939 09:33:48.061382 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10940 09:33:48.081373 <30>[ 22.732059] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10941 09:33:48.091334 <3>[ 22.733437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 09:33:48.097947 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10943 09:33:48.118532 <30>[ 22.768761] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10944 09:33:48.125425 <3>[ 22.772757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 09:33:48.134921 <30>[ 22.777014] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10946 09:33:48.141893 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10947 09:33:48.159311 <3>[ 22.809392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 09:33:48.168525 <30>[ 22.819358] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10949 09:33:48.175724 <30>[ 22.827176] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10950 09:33:48.192786 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 22.840162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 09:33:48.193232 - Load Kernel Module dm_mod.
10952 09:33:48.211653 <30>[ 22.864766] systemd[1]: modprobe@drm.service: Deactivated successfully.
10953 09:33:48.222016 <3>[ 22.872287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 09:33:48.228363 <30>[ 22.872578] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10955 09:33:48.238505 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10956 09:33:48.251310 <3>[ 22.902295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 09:33:48.263106 <30>[ 22.913442] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10958 09:33:48.272846 <30>[ 22.922008] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10959 09:33:48.279550 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10960 09:33:48.299446 <3>[ 22.950338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 09:33:48.310371 <30>[ 22.961236] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10962 09:33:48.317340 <30>[ 22.969777] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10963 09:33:48.327925 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10964 09:33:48.346261 <3>[ 22.996639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 09:33:48.357148 <30>[ 23.007770] systemd[1]: modprobe@loop.service: Deactivated successfully.
10966 09:33:48.363477 <30>[ 23.016155] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10967 09:33:48.373845 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10968 09:33:48.398679 <30>[ 23.048722] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10969 09:33:48.405858 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10970 09:33:48.423152 <4>[ 23.065992] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10971 09:33:48.430002 <3>[ 23.081644] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10972 09:33:48.439846 <30>[ 23.083664] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10973 09:33:48.450482 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10974 09:33:48.474523 <30>[ 23.125270] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10975 09:33:48.484904 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10976 09:33:48.504859 <30>[ 23.155993] systemd[1]: Started systemd-journald.service - Journal Service.
10977 09:33:48.511678 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10978 09:33:48.536809 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10979 09:33:48.554803 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10980 09:33:48.596567 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10981 09:33:48.617698 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10982 09:33:48.642100 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10983 09:33:48.665055 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10984 09:33:48.690397 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10985 09:33:48.722054 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10986 09:33:48.733481 <46>[ 23.384354] systemd-journald[300]: Received client request to flush runtime journal.
10987 09:33:48.765963 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10988 09:33:48.786447 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10989 09:33:48.806668 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10990 09:33:48.826688 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10991 09:33:49.849638 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10992 09:33:49.888838 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10993 09:33:50.166217 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10994 09:33:50.293248 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10995 09:33:50.313399 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10996 09:33:50.332894 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10997 09:33:50.392503 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10998 09:33:50.413927 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10999 09:33:50.438175 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11000 09:33:50.469558 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11001 09:33:50.484908 See 'systemctl status systemd-binfmt.service' for details.
11002 09:33:50.763289 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11003 09:33:50.835337 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11004 09:33:50.902486 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11005 09:33:51.123873 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11006 09:33:51.300696 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11007 09:33:51.325747 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11008 09:33:51.387997 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11009 09:33:51.404280 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11010 09:33:51.420592 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11011 09:33:51.476655 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11012 09:33:51.500622 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11013 09:33:51.538924 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11014 09:33:51.602348 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11015 09:33:51.616051 <46>[ 26.270072] systemd-journald[300]: Time jumped backwards, rotating.
11016 09:33:51.628097 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11017 09:33:51.647764 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11018 09:33:51.669735 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11019 09:33:51.691756 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11020 09:33:51.708841 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11021 09:33:51.732242 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11022 09:33:52.425553 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11023 09:33:52.750370 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11024 09:33:52.768392 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11025 09:33:53.110401 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11026 09:33:53.131978 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11027 09:33:53.148313 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11028 09:33:53.163836 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11029 09:33:53.414542 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11030 09:33:53.431638 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11031 09:33:53.447992 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11032 09:33:53.517305 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11033 09:33:53.556709 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11034 09:33:53.628887 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11035 09:33:53.652555 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11036 09:33:53.893236 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11037 09:33:53.941285 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11038 09:33:53.955672 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11039 09:33:53.971722 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11040 09:33:53.992695 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11041 09:33:54.025845 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11042 09:33:54.046930 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11043 09:33:54.082858 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11044 09:33:54.105097 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11045 09:33:54.161326 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11046 09:33:54.186678 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11047 09:33:54.248686 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11048 09:33:54.320444 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11049 09:33:54.420540
11050 09:33:54.421069
11051 09:33:54.423740 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11052 09:33:54.424162
11053 09:33:54.427319 debian-bookworm-arm64 login: root (automatic login)
11054 09:33:54.427742
11055 09:33:54.428071
11056 09:33:54.782384 Linux debian-bookworm-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
11057 09:33:54.782920
11058 09:33:54.788961 The programs included with the Debian GNU/Linux system are free software;
11059 09:33:54.796334 the exact distribution terms for each program are described in the
11060 09:33:54.799274 individual files in /usr/share/doc/*/copyright.
11061 09:33:54.799694
11062 09:33:54.806316 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11063 09:33:54.809012 permitted by applicable law.
11064 09:33:56.008414 Matched prompt #10: / #
11066 09:33:56.009559 Setting prompt string to ['/ #']
11067 09:33:56.009987 end: 2.2.5.1 login-action (duration 00:00:31) [common]
11069 09:33:56.010989 end: 2.2.5 auto-login-action (duration 00:00:31) [common]
11070 09:33:56.011443 start: 2.2.6 expect-shell-connection (timeout 00:03:09) [common]
11071 09:33:56.011789 Setting prompt string to ['/ #']
11072 09:33:56.012098 Forcing a shell prompt, looking for ['/ #']
11074 09:33:56.062883 / #
11075 09:33:56.063481 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11076 09:33:56.063867 Waiting using forced prompt support (timeout 00:02:30)
11077 09:33:56.068903
11078 09:33:56.069806 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11079 09:33:56.070293 start: 2.2.7 export-device-env (timeout 00:03:09) [common]
11081 09:33:56.171586 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv'
11082 09:33:56.178272 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826827/extract-nfsrootfs-8wjpbsrv'
11084 09:33:56.280048 / # export NFS_SERVER_IP='192.168.201.1'
11085 09:33:56.285637 export NFS_SERVER_IP='192.168.201.1'
11086 09:33:56.285947 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11087 09:33:56.286049 end: 2.2 depthcharge-retry (duration 00:01:51) [common]
11088 09:33:56.286136 end: 2 depthcharge-action (duration 00:01:51) [common]
11089 09:33:56.286225 start: 3 lava-test-retry (timeout 00:07:26) [common]
11090 09:33:56.286313 start: 3.1 lava-test-shell (timeout 00:07:26) [common]
11091 09:33:56.286387 Using namespace: common
11093 09:33:56.386882 / # #
11094 09:33:56.387450 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11095 09:33:56.392869 #
11096 09:33:56.393599 Using /lava-11826827
11098 09:33:56.494633 / # export SHELL=/bin/bash
11099 09:33:56.500798 export SHELL=/bin/bash
11101 09:33:56.602280 / # . /lava-11826827/environment
11102 09:33:56.608610 . /lava-11826827/environment
11104 09:33:56.717144 / # /lava-11826827/bin/lava-test-runner /lava-11826827/0
11105 09:33:56.717800 Test shell timeout: 10s (minimum of the action and connection timeout)
11106 09:33:56.723798 /lava-11826827/bin/lava-test-runner /lava-11826827/0
11107 09:33:57.077275 + export TESTRUN_ID=0_timesync-off
11108 09:33:57.080600 + TESTRUN_ID=0_timesync-off
11109 09:33:57.083600 + cd /lava-11826827/0/tests/0_timesync-off
11110 09:33:57.087109 ++ cat uuid
11111 09:33:57.096608 + UUID=11826827_1.6.2.3.1
11112 09:33:57.097032 + set +x
11113 09:33:57.103235 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11826827_1.6.2.3.1>
11114 09:33:57.104292 Received signal: <STARTRUN> 0_timesync-off 11826827_1.6.2.3.1
11115 09:33:57.104781 Starting test lava.0_timesync-off (11826827_1.6.2.3.1)
11116 09:33:57.105206 Skipping test definition patterns.
11117 09:33:57.106587 + systemctl stop systemd-timesyncd
11118 09:33:57.189822 + set +x
11119 09:33:57.193418 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11826827_1.6.2.3.1>
11120 09:33:57.194103 Received signal: <ENDRUN> 0_timesync-off 11826827_1.6.2.3.1
11121 09:33:57.194511 Ending use of test pattern.
11122 09:33:57.194876 Ending test lava.0_timesync-off (11826827_1.6.2.3.1), duration 0.09
11124 09:33:57.290791 + export TESTRUN_ID=1_kselftest-alsa
11125 09:33:57.294014 + TESTRUN_ID=1_kselftest-alsa
11126 09:33:57.297445 + cd /lava-11826827/0/tests/1_kselftest-alsa
11127 09:33:57.301425 ++ cat uuid
11128 09:33:57.305759 + UUID=11826827_1.6.2.3.5
11129 09:33:57.305850 + set +x
11130 09:33:57.312339 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 11826827_1.6.2.3.5>
11131 09:33:57.312598 Received signal: <STARTRUN> 1_kselftest-alsa 11826827_1.6.2.3.5
11132 09:33:57.312673 Starting test lava.1_kselftest-alsa (11826827_1.6.2.3.5)
11133 09:33:57.312755 Skipping test definition patterns.
11134 09:33:57.315902 + cd ./automated/linux/kselftest/
11135 09:33:57.342454 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11136 09:33:57.387665 INFO: install_deps skipped
11137 09:33:57.906683 --2023-10-20 09:33:57-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11138 09:33:57.921265 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11139 09:33:58.056417 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11140 09:33:58.190169 HTTP request sent, awaiting response... 200 OK
11141 09:33:58.193267 Length: 2964156 (2.8M) [application/octet-stream]
11142 09:33:58.196446 Saving to: 'kselftest.tar.xz'
11143 09:33:58.196910
11144 09:33:58.197279
11145 09:33:58.458322 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11146 09:33:58.726266 kselftest.tar.xz 1%[ ] 47.81K 179KB/s
11147 09:33:59.050910 kselftest.tar.xz 7%[> ] 217.50K 407KB/s
11148 09:33:59.395341 kselftest.tar.xz 28%[====> ] 811.40K 944KB/s
11149 09:33:59.429831 kselftest.tar.xz 48%[========> ] 1.36M 1.13MB/s
11150 09:33:59.436509 kselftest.tar.xz 100%[===================>] 2.83M 2.28MB/s in 1.2s
11151 09:33:59.436937
11152 09:33:59.693945 2023-10-20 09:33:59 (2.28 MB/s) - 'kselftest.tar.xz' saved [2964156/2964156]
11153 09:33:59.694121
11154 09:34:06.677674 skiplist:
11155 09:34:06.680333 ========================================
11156 09:34:06.683654 ========================================
11157 09:34:06.744510 alsa:mixer-test
11158 09:34:06.771085 ============== Tests to run ===============
11159 09:34:06.774573 alsa:mixer-test
11160 09:34:06.778894 ===========End Tests to run ===============
11161 09:34:06.784726 shardfile-alsa pass
11162 09:34:06.918594 <12>[ 41.574653] kselftest: Running tests in alsa
11163 09:34:06.930298 TAP version 13
11164 09:34:06.948032 1..1
11165 09:34:06.969434 # selftests: alsa: mixer-test
11166 09:34:07.500498 # TAP version 13
11167 09:34:07.501058 # 1..0
11168 09:34:07.507210 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11169 09:34:07.510036 ok 1 selftests: alsa: mixer-test
11170 09:34:08.266663 alsa_mixer-test pass
11171 09:34:08.310955 + ../../utils/send-to-lava.sh ./output/result.txt
11172 09:34:08.407764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11173 09:34:08.408696 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11175 09:34:08.475754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11176 09:34:08.476270 + set +x
11177 09:34:08.476876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11179 09:34:08.482643 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 11826827_1.6.2.3.5>
11180 09:34:08.483456 Received signal: <ENDRUN> 1_kselftest-alsa 11826827_1.6.2.3.5
11181 09:34:08.483836 Ending use of test pattern.
11182 09:34:08.484155 Ending test lava.1_kselftest-alsa (11826827_1.6.2.3.5), duration 11.17
11184 09:34:08.485732 <LAVA_TEST_RUNNER EXIT>
11185 09:34:08.486477 ok: lava_test_shell seems to have completed
11186 09:34:08.487086 alsa_mixer-test: pass
shardfile-alsa: pass
11187 09:34:08.487518 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11188 09:34:08.487934 end: 3 lava-test-retry (duration 00:00:12) [common]
11189 09:34:08.488463 start: 4 finalize (timeout 00:07:14) [common]
11190 09:34:08.488915 start: 4.1 power-off (timeout 00:00:30) [common]
11191 09:34:08.489647 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11192 09:34:08.613952 >> Command sent successfully.
11193 09:34:08.618576 Returned 0 in 0 seconds
11194 09:34:08.719552 end: 4.1 power-off (duration 00:00:00) [common]
11196 09:34:08.721119 start: 4.2 read-feedback (timeout 00:07:14) [common]
11197 09:34:08.722472 Listened to connection for namespace 'common' for up to 1s
11198 09:34:09.722935 Finalising connection for namespace 'common'
11199 09:34:09.723665 Disconnecting from shell: Finalise
11200 09:34:09.724126 / #
11201 09:34:09.825049 end: 4.2 read-feedback (duration 00:00:01) [common]
11202 09:34:09.825801 end: 4 finalize (duration 00:00:01) [common]
11203 09:34:09.826385 Cleaning after the job
11204 09:34:09.827024 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/ramdisk
11205 09:34:09.841639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/kernel
11206 09:34:09.874093 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/dtb
11207 09:34:09.874421 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/nfsrootfs
11208 09:34:09.975918 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826827/tftp-deploy-jtsi5kkd/modules
11209 09:34:09.983059 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826827
11210 09:34:10.633715 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826827
11211 09:34:10.633901 Job finished correctly