Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 26
- Kernel Errors: 39
- Errors: 0
- Boot result: PASS
1 09:26:20.764414 lava-dispatcher, installed at version: 2023.08
2 09:26:20.764617 start: 0 validate
3 09:26:20.764748 Start time: 2023-10-20 09:26:20.764741+00:00 (UTC)
4 09:26:20.764870 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:26:20.765001 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:26:21.033685 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:26:21.033861 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:26:21.304643 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:26:21.305462 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:12.932351 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:12.933065 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:27:13.463366 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:27:13.464102 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:27:13.734700 validate duration: 52.97
16 09:27:13.736000 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:27:13.736555 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:27:13.737032 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:27:13.737675 Not decompressing ramdisk as can be used compressed.
20 09:27:13.738146 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 09:27:13.738547 saving as /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/ramdisk/initrd.cpio.gz
22 09:27:13.739038 total size: 4665395 (4 MB)
23 09:27:16.444269 progress 0 % (0 MB)
24 09:27:16.453364 progress 5 % (0 MB)
25 09:27:16.460755 progress 10 % (0 MB)
26 09:27:16.468009 progress 15 % (0 MB)
27 09:27:16.474629 progress 20 % (0 MB)
28 09:27:16.479488 progress 25 % (1 MB)
29 09:27:16.483257 progress 30 % (1 MB)
30 09:27:16.486488 progress 35 % (1 MB)
31 09:27:16.489182 progress 40 % (1 MB)
32 09:27:16.492051 progress 45 % (2 MB)
33 09:27:16.494298 progress 50 % (2 MB)
34 09:27:16.496512 progress 55 % (2 MB)
35 09:27:16.498461 progress 60 % (2 MB)
36 09:27:16.500407 progress 65 % (2 MB)
37 09:27:16.502194 progress 70 % (3 MB)
38 09:27:16.503910 progress 75 % (3 MB)
39 09:27:16.505626 progress 80 % (3 MB)
40 09:27:16.507427 progress 85 % (3 MB)
41 09:27:16.508950 progress 90 % (4 MB)
42 09:27:16.510468 progress 95 % (4 MB)
43 09:27:16.511935 progress 100 % (4 MB)
44 09:27:16.512106 4 MB downloaded in 2.77 s (1.60 MB/s)
45 09:27:16.512278 end: 1.1.1 http-download (duration 00:00:03) [common]
47 09:27:16.512537 end: 1.1 download-retry (duration 00:00:03) [common]
48 09:27:16.512633 start: 1.2 download-retry (timeout 00:09:57) [common]
49 09:27:16.512727 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 09:27:16.512877 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:27:16.512953 saving as /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/kernel/Image
52 09:27:16.513021 total size: 49236480 (46 MB)
53 09:27:16.513090 No compression specified
54 09:27:16.514320 progress 0 % (0 MB)
55 09:27:16.527517 progress 5 % (2 MB)
56 09:27:16.540226 progress 10 % (4 MB)
57 09:27:16.553021 progress 15 % (7 MB)
58 09:27:16.565616 progress 20 % (9 MB)
59 09:27:16.578093 progress 25 % (11 MB)
60 09:27:16.590458 progress 30 % (14 MB)
61 09:27:16.602998 progress 35 % (16 MB)
62 09:27:16.615798 progress 40 % (18 MB)
63 09:27:16.632320 progress 45 % (21 MB)
64 09:27:16.652759 progress 50 % (23 MB)
65 09:27:16.672803 progress 55 % (25 MB)
66 09:27:16.693311 progress 60 % (28 MB)
67 09:27:16.714123 progress 65 % (30 MB)
68 09:27:16.728829 progress 70 % (32 MB)
69 09:27:16.741718 progress 75 % (35 MB)
70 09:27:16.754975 progress 80 % (37 MB)
71 09:27:16.767903 progress 85 % (39 MB)
72 09:27:16.780542 progress 90 % (42 MB)
73 09:27:16.793043 progress 95 % (44 MB)
74 09:27:16.805408 progress 100 % (46 MB)
75 09:27:16.805644 46 MB downloaded in 0.29 s (160.47 MB/s)
76 09:27:16.805799 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:27:16.806028 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:27:16.806115 start: 1.3 download-retry (timeout 00:09:57) [common]
80 09:27:16.806201 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 09:27:16.806339 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:27:16.806416 saving as /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/dtb/mt8192-asurada-spherion-r0.dtb
83 09:27:16.806478 total size: 47278 (0 MB)
84 09:27:16.806540 No compression specified
85 09:27:16.807708 progress 69 % (0 MB)
86 09:27:16.808008 progress 100 % (0 MB)
87 09:27:16.808204 0 MB downloaded in 0.00 s (26.16 MB/s)
88 09:27:16.808326 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:27:16.808545 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:27:16.808630 start: 1.4 download-retry (timeout 00:09:57) [common]
92 09:27:16.808761 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 09:27:16.808891 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 09:27:16.808959 saving as /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/nfsrootfs/full.rootfs.tar
95 09:27:16.809023 total size: 200813988 (191 MB)
96 09:27:16.809085 Using unxz to decompress xz
97 09:27:16.813329 progress 0 % (0 MB)
98 09:27:17.347629 progress 5 % (9 MB)
99 09:27:17.876442 progress 10 % (19 MB)
100 09:27:18.476480 progress 15 % (28 MB)
101 09:27:18.851771 progress 20 % (38 MB)
102 09:27:19.179336 progress 25 % (47 MB)
103 09:27:19.773329 progress 30 % (57 MB)
104 09:27:20.327013 progress 35 % (67 MB)
105 09:27:20.932689 progress 40 % (76 MB)
106 09:27:21.504385 progress 45 % (86 MB)
107 09:27:22.090531 progress 50 % (95 MB)
108 09:27:22.740067 progress 55 % (105 MB)
109 09:27:23.406198 progress 60 % (114 MB)
110 09:27:23.524778 progress 65 % (124 MB)
111 09:27:23.665609 progress 70 % (134 MB)
112 09:27:23.765047 progress 75 % (143 MB)
113 09:27:23.843029 progress 80 % (153 MB)
114 09:27:23.918309 progress 85 % (162 MB)
115 09:27:24.027480 progress 90 % (172 MB)
116 09:27:24.312036 progress 95 % (181 MB)
117 09:27:24.908035 progress 100 % (191 MB)
118 09:27:24.913344 191 MB downloaded in 8.10 s (23.63 MB/s)
119 09:27:24.913602 end: 1.4.1 http-download (duration 00:00:08) [common]
121 09:27:24.913859 end: 1.4 download-retry (duration 00:00:08) [common]
122 09:27:24.913948 start: 1.5 download-retry (timeout 00:09:49) [common]
123 09:27:24.914033 start: 1.5.1 http-download (timeout 00:09:49) [common]
124 09:27:24.914187 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:27:24.914256 saving as /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/modules/modules.tar
126 09:27:24.914318 total size: 8614716 (8 MB)
127 09:27:24.914382 Using unxz to decompress xz
128 09:27:25.183397 progress 0 % (0 MB)
129 09:27:25.204667 progress 5 % (0 MB)
130 09:27:25.228212 progress 10 % (0 MB)
131 09:27:25.251894 progress 15 % (1 MB)
132 09:27:25.275999 progress 20 % (1 MB)
133 09:27:25.300192 progress 25 % (2 MB)
134 09:27:25.326185 progress 30 % (2 MB)
135 09:27:25.352625 progress 35 % (2 MB)
136 09:27:25.376464 progress 40 % (3 MB)
137 09:27:25.400804 progress 45 % (3 MB)
138 09:27:25.426206 progress 50 % (4 MB)
139 09:27:25.450784 progress 55 % (4 MB)
140 09:27:25.476207 progress 60 % (4 MB)
141 09:27:25.502534 progress 65 % (5 MB)
142 09:27:25.530797 progress 70 % (5 MB)
143 09:27:25.555849 progress 75 % (6 MB)
144 09:27:25.583327 progress 80 % (6 MB)
145 09:27:25.609283 progress 85 % (7 MB)
146 09:27:25.634627 progress 90 % (7 MB)
147 09:27:25.664569 progress 95 % (7 MB)
148 09:27:25.693840 progress 100 % (8 MB)
149 09:27:25.700429 8 MB downloaded in 0.79 s (10.45 MB/s)
150 09:27:25.700697 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:27:25.700964 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:27:25.701054 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 09:27:25.701149 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 09:27:29.224802 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv
156 09:27:29.225020 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 09:27:29.225126 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 09:27:29.225289 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc
159 09:27:29.225426 makedir: /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin
160 09:27:29.225529 makedir: /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/tests
161 09:27:29.225625 makedir: /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/results
162 09:27:29.225726 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-add-keys
163 09:27:29.225871 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-add-sources
164 09:27:29.225999 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-background-process-start
165 09:27:29.226125 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-background-process-stop
166 09:27:29.226250 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-common-functions
167 09:27:29.226374 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-echo-ipv4
168 09:27:29.226498 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-install-packages
169 09:27:29.226622 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-installed-packages
170 09:27:29.226776 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-os-build
171 09:27:29.226916 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-probe-channel
172 09:27:29.227040 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-probe-ip
173 09:27:29.227164 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-target-ip
174 09:27:29.227288 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-target-mac
175 09:27:29.227410 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-target-storage
176 09:27:29.227535 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-case
177 09:27:29.227662 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-event
178 09:27:29.227785 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-feedback
179 09:27:29.227908 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-raise
180 09:27:29.228030 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-reference
181 09:27:29.228155 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-runner
182 09:27:29.228278 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-set
183 09:27:29.228402 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-test-shell
184 09:27:29.228528 Updating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-add-keys (debian)
185 09:27:29.228678 Updating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-add-sources (debian)
186 09:27:29.228820 Updating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-install-packages (debian)
187 09:27:29.228960 Updating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-installed-packages (debian)
188 09:27:29.229097 Updating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/bin/lava-os-build (debian)
189 09:27:29.229217 Creating /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/environment
190 09:27:29.229313 LAVA metadata
191 09:27:29.229384 - LAVA_JOB_ID=11826801
192 09:27:29.229447 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:27:29.229559 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 09:27:29.229625 skipped lava-vland-overlay
195 09:27:29.229700 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:27:29.229778 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 09:27:29.229836 skipped lava-multinode-overlay
198 09:27:29.229906 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:27:29.229998 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 09:27:29.230070 Loading test definitions
201 09:27:29.230158 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 09:27:29.230229 Using /lava-11826801 at stage 0
203 09:27:29.230507 uuid=11826801_1.6.2.3.1 testdef=None
204 09:27:29.230594 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:27:29.230677 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 09:27:29.231131 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:27:29.231347 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 09:27:29.231898 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:27:29.232122 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 09:27:29.232658 runner path: /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/0/tests/0_timesync-off test_uuid 11826801_1.6.2.3.1
213 09:27:29.232814 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:27:29.233034 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 09:27:29.233104 Using /lava-11826801 at stage 0
217 09:27:29.233197 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:27:29.233275 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/0/tests/1_kselftest-arm64'
219 09:27:36.897292 Running '/usr/bin/git checkout kernelci.org
220 09:27:37.045110 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 09:27:37.045846 uuid=11826801_1.6.2.3.5 testdef=None
222 09:27:37.046005 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 09:27:37.046251 start: 1.6.2.3.6 test-overlay (timeout 00:09:37) [common]
225 09:27:37.047050 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:27:37.047281 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:37) [common]
228 09:27:37.048236 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:27:37.048467 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:37) [common]
231 09:27:37.049398 runner path: /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/0/tests/1_kselftest-arm64 test_uuid 11826801_1.6.2.3.5
232 09:27:37.049493 BOARD='mt8192-asurada-spherion-r0'
233 09:27:37.049558 BRANCH='cip'
234 09:27:37.049618 SKIPFILE='/dev/null'
235 09:27:37.049675 SKIP_INSTALL='True'
236 09:27:37.049730 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:27:37.049788 TST_CASENAME=''
238 09:27:37.049843 TST_CMDFILES='arm64'
239 09:27:37.049983 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:27:37.050188 Creating lava-test-runner.conf files
242 09:27:37.050250 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826801/lava-overlay-ryscorpc/lava-11826801/0 for stage 0
243 09:27:37.050342 - 0_timesync-off
244 09:27:37.050411 - 1_kselftest-arm64
245 09:27:37.050505 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 09:27:37.050589 start: 1.6.2.4 compress-overlay (timeout 00:09:37) [common]
247 09:27:44.543904 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 09:27:44.544070 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:29) [common]
249 09:27:44.544208 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:27:44.544311 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 09:27:44.544403 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:29) [common]
252 09:27:44.665228 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:27:44.665624 start: 1.6.4 extract-modules (timeout 00:09:29) [common]
254 09:27:44.665741 extracting modules file /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv
255 09:27:44.888982 extracting modules file /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826801/extract-overlay-ramdisk-0vnqj4il/ramdisk
256 09:27:45.115971 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:27:45.116143 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
258 09:27:45.116239 [common] Applying overlay to NFS
259 09:27:45.116308 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826801/compress-overlay-tiyhtf9i/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv
260 09:27:46.045212 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:27:46.045383 start: 1.6.6 configure-preseed-file (timeout 00:09:28) [common]
262 09:27:46.045482 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:27:46.045574 start: 1.6.7 compress-ramdisk (timeout 00:09:28) [common]
264 09:27:46.045659 Building ramdisk /var/lib/lava/dispatcher/tmp/11826801/extract-overlay-ramdisk-0vnqj4il/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826801/extract-overlay-ramdisk-0vnqj4il/ramdisk
265 09:27:46.373400 >> 119368 blocks
266 09:27:48.283592 rename /var/lib/lava/dispatcher/tmp/11826801/extract-overlay-ramdisk-0vnqj4il/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/ramdisk/ramdisk.cpio.gz
267 09:27:48.284059 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:27:48.284180 start: 1.6.8 prepare-kernel (timeout 00:09:25) [common]
269 09:27:48.284281 start: 1.6.8.1 prepare-fit (timeout 00:09:25) [common]
270 09:27:48.284384 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/kernel/Image'
271 09:28:01.537865 Returned 0 in 13 seconds
272 09:28:01.638635 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/kernel/image.itb
273 09:28:01.987782 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:28:01.988249 output: Created: Fri Oct 20 10:28:01 2023
275 09:28:01.988359 output: Image 0 (kernel-1)
276 09:28:01.988449 output: Description:
277 09:28:01.988555 output: Created: Fri Oct 20 10:28:01 2023
278 09:28:01.988646 output: Type: Kernel Image
279 09:28:01.988735 output: Compression: lzma compressed
280 09:28:01.988835 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
281 09:28:01.988961 output: Architecture: AArch64
282 09:28:01.989052 output: OS: Linux
283 09:28:01.989143 output: Load Address: 0x00000000
284 09:28:01.989228 output: Entry Point: 0x00000000
285 09:28:01.989319 output: Hash algo: crc32
286 09:28:01.989400 output: Hash value: 05d3904e
287 09:28:01.989480 output: Image 1 (fdt-1)
288 09:28:01.989573 output: Description: mt8192-asurada-spherion-r0
289 09:28:01.989654 output: Created: Fri Oct 20 10:28:01 2023
290 09:28:01.989731 output: Type: Flat Device Tree
291 09:28:01.989822 output: Compression: uncompressed
292 09:28:01.989901 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 09:28:01.989979 output: Architecture: AArch64
294 09:28:01.990068 output: Hash algo: crc32
295 09:28:01.990145 output: Hash value: cc4352de
296 09:28:01.990221 output: Image 2 (ramdisk-1)
297 09:28:01.990307 output: Description: unavailable
298 09:28:01.990385 output: Created: Fri Oct 20 10:28:01 2023
299 09:28:01.990462 output: Type: RAMDisk Image
300 09:28:01.990553 output: Compression: Unknown Compression
301 09:28:01.990632 output: Data Size: 17791065 Bytes = 17374.09 KiB = 16.97 MiB
302 09:28:01.990709 output: Architecture: AArch64
303 09:28:01.990840 output: OS: Linux
304 09:28:01.990918 output: Load Address: unavailable
305 09:28:01.990994 output: Entry Point: unavailable
306 09:28:01.991082 output: Hash algo: crc32
307 09:28:01.991160 output: Hash value: e5e4db31
308 09:28:01.991236 output: Default Configuration: 'conf-1'
309 09:28:01.991323 output: Configuration 0 (conf-1)
310 09:28:01.991401 output: Description: mt8192-asurada-spherion-r0
311 09:28:01.991477 output: Kernel: kernel-1
312 09:28:01.991569 output: Init Ramdisk: ramdisk-1
313 09:28:01.991647 output: FDT: fdt-1
314 09:28:01.991723 output: Loadables: kernel-1
315 09:28:01.991813 output:
316 09:28:01.992072 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:28:01.992207 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:28:01.992354 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 09:28:01.992484 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:12) [common]
320 09:28:01.992603 No LXC device requested
321 09:28:01.992712 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:28:01.992838 start: 1.8 deploy-device-env (timeout 00:09:12) [common]
323 09:28:01.992943 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:28:01.993048 Checking files for TFTP limit of 4294967296 bytes.
325 09:28:01.993732 end: 1 tftp-deploy (duration 00:00:48) [common]
326 09:28:01.993876 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:28:01.994002 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:28:01.994174 substitutions:
329 09:28:01.994272 - {DTB}: 11826801/tftp-deploy-umtcdiai/dtb/mt8192-asurada-spherion-r0.dtb
330 09:28:01.994363 - {INITRD}: 11826801/tftp-deploy-umtcdiai/ramdisk/ramdisk.cpio.gz
331 09:28:01.994446 - {KERNEL}: 11826801/tftp-deploy-umtcdiai/kernel/Image
332 09:28:01.994543 - {LAVA_MAC}: None
333 09:28:01.994626 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv
334 09:28:01.994710 - {NFS_SERVER_IP}: 192.168.201.1
335 09:28:01.994842 - {PRESEED_CONFIG}: None
336 09:28:01.994924 - {PRESEED_LOCAL}: None
337 09:28:01.995007 - {RAMDISK}: 11826801/tftp-deploy-umtcdiai/ramdisk/ramdisk.cpio.gz
338 09:28:01.995097 - {ROOT_PART}: None
339 09:28:01.995176 - {ROOT}: None
340 09:28:01.995261 - {SERVER_IP}: 192.168.201.1
341 09:28:01.995346 - {TEE}: None
342 09:28:01.995424 Parsed boot commands:
343 09:28:01.995511 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:28:01.995770 Parsed boot commands: tftpboot 192.168.201.1 11826801/tftp-deploy-umtcdiai/kernel/image.itb 11826801/tftp-deploy-umtcdiai/kernel/cmdline
345 09:28:01.995893 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:28:01.996018 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:28:01.996147 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:28:01.996273 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:28:01.996375 Not connected, no need to disconnect.
350 09:28:01.996482 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:28:01.996604 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:28:01.996698 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 09:28:02.001588 Setting prompt string to ['lava-test: # ']
354 09:28:02.002111 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:28:02.002267 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:28:02.002419 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:28:02.002545 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:28:02.002891 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 09:28:07.135671 >> Command sent successfully.
360 09:28:07.138123 Returned 0 in 5 seconds
361 09:28:07.238529 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 09:28:07.238898 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 09:28:07.239004 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 09:28:07.239089 Setting prompt string to 'Starting depthcharge on Spherion...'
366 09:28:07.239159 Changing prompt to 'Starting depthcharge on Spherion...'
367 09:28:07.239227 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 09:28:07.239492 [Enter `^Ec?' for help]
369 09:28:07.413768
370 09:28:07.413913
371 09:28:07.414008 F0: 102B 0000
372 09:28:07.414106
373 09:28:07.414171 F3: 1001 0000 [0200]
374 09:28:07.416937
375 09:28:07.417019 F3: 1001 0000
376 09:28:07.417084
377 09:28:07.417144 F7: 102D 0000
378 09:28:07.417203
379 09:28:07.420056 F1: 0000 0000
380 09:28:07.420138
381 09:28:07.420203 V0: 0000 0000 [0001]
382 09:28:07.420266
383 09:28:07.423664 00: 0007 8000
384 09:28:07.423750
385 09:28:07.423815 01: 0000 0000
386 09:28:07.423877
387 09:28:07.426900 BP: 0C00 0209 [0000]
388 09:28:07.426982
389 09:28:07.427047 G0: 1182 0000
390 09:28:07.427108
391 09:28:07.430617 EC: 0000 0021 [4000]
392 09:28:07.430732
393 09:28:07.430800 S7: 0000 0000 [0000]
394 09:28:07.430861
395 09:28:07.433970 CC: 0000 0000 [0001]
396 09:28:07.434052
397 09:28:07.434116 T0: 0000 0040 [010F]
398 09:28:07.434177
399 09:28:07.434235 Jump to BL
400 09:28:07.434291
401 09:28:07.460579
402 09:28:07.460672
403 09:28:07.460738
404 09:28:07.468470 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 09:28:07.471708 ARM64: Exception handlers installed.
406 09:28:07.475635 ARM64: Testing exception
407 09:28:07.478677 ARM64: Done test exception
408 09:28:07.485761 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 09:28:07.496226 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 09:28:07.503131 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 09:28:07.512809 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 09:28:07.519665 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 09:28:07.526504 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 09:28:07.537456 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 09:28:07.545041 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 09:28:07.563709 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 09:28:07.566852 WDT: Last reset was cold boot
418 09:28:07.570339 SPI1(PAD0) initialized at 2873684 Hz
419 09:28:07.573593 SPI5(PAD0) initialized at 992727 Hz
420 09:28:07.577346 VBOOT: Loading verstage.
421 09:28:07.583327 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:28:07.586696 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 09:28:07.590629 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 09:28:07.593916 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 09:28:07.601136 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 09:28:07.608064 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 09:28:07.618277 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
428 09:28:07.618361
429 09:28:07.618426
430 09:28:07.628394 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 09:28:07.632162 ARM64: Exception handlers installed.
432 09:28:07.635304 ARM64: Testing exception
433 09:28:07.635386 ARM64: Done test exception
434 09:28:07.642387 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 09:28:07.645159 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 09:28:07.659399 Probing TPM: . done!
437 09:28:07.659482 TPM ready after 0 ms
438 09:28:07.666121 Connected to device vid:did:rid of 1ae0:0028:00
439 09:28:07.673355 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 09:28:07.730849 Initialized TPM device CR50 revision 0
441 09:28:07.743243 tlcl_send_startup: Startup return code is 0
442 09:28:07.743334 TPM: setup succeeded
443 09:28:07.754696 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 09:28:07.763820 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:28:07.775027 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 09:28:07.784680 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 09:28:07.787585 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 09:28:07.795989 in-header: 03 07 00 00 08 00 00 00
449 09:28:07.799296 in-data: aa e4 47 04 13 02 00 00
450 09:28:07.803232 Chrome EC: UHEPI supported
451 09:28:07.810101 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 09:28:07.814246 in-header: 03 ad 00 00 08 00 00 00
453 09:28:07.817548 in-data: 00 20 20 08 00 00 00 00
454 09:28:07.817679 Phase 1
455 09:28:07.821497 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 09:28:07.829107 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 09:28:07.832458 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 09:28:07.836473 Recovery requested (1009000e)
459 09:28:07.844260 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 09:28:07.849555 tlcl_extend: response is 0
461 09:28:07.858644 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 09:28:07.864648 tlcl_extend: response is 0
463 09:28:07.872088 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 09:28:07.891341 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
465 09:28:07.898158 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 09:28:07.898258
467 09:28:07.898339
468 09:28:07.908620 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 09:28:07.912586 ARM64: Exception handlers installed.
470 09:28:07.912700 ARM64: Testing exception
471 09:28:07.915352 ARM64: Done test exception
472 09:28:07.936929 pmic_efuse_setting: Set efuses in 11 msecs
473 09:28:07.940851 pmwrap_interface_init: Select PMIF_VLD_RDY
474 09:28:07.947159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 09:28:07.950549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 09:28:07.957480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 09:28:07.961314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 09:28:07.965230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 09:28:07.968738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 09:28:07.976289 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 09:28:07.980083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 09:28:07.983903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 09:28:07.990911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 09:28:07.994891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 09:28:07.998920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 09:28:08.002051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 09:28:08.009658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 09:28:08.016616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 09:28:08.020596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 09:28:08.028434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 09:28:08.032213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 09:28:08.036629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 09:28:08.043665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 09:28:08.047307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 09:28:08.054604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 09:28:08.058583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 09:28:08.065791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 09:28:08.069799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 09:28:08.077354 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 09:28:08.080815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 09:28:08.087791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 09:28:08.091335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 09:28:08.095358 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 09:28:08.102334 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 09:28:08.106259 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 09:28:08.110238 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 09:28:08.117503 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 09:28:08.120640 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 09:28:08.124517 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 09:28:08.131966 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 09:28:08.136580 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 09:28:08.139499 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 09:28:08.143508 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 09:28:08.151214 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 09:28:08.154424 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 09:28:08.158474 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 09:28:08.161792 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 09:28:08.166219 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 09:28:08.169760 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 09:28:08.173874 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 09:28:08.177713 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 09:28:08.184953 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 09:28:08.188837 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 09:28:08.192266 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 09:28:08.199756 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 09:28:08.207180 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 09:28:08.214426 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 09:28:08.221631 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 09:28:08.229082 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 09:28:08.233103 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 09:28:08.237250 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:28:08.244334 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 09:28:08.251908 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 09:28:08.254912 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 09:28:08.259227 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 09:28:08.262548 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 09:28:08.274548 [RTC]rtc_get_frequency_meter,154: input=15, output=789
538 09:28:08.283688 [RTC]rtc_get_frequency_meter,154: input=23, output=980
539 09:28:08.294243 [RTC]rtc_get_frequency_meter,154: input=19, output=885
540 09:28:08.302510 [RTC]rtc_get_frequency_meter,154: input=17, output=836
541 09:28:08.311881 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 09:28:08.321795 [RTC]rtc_get_frequency_meter,154: input=15, output=791
543 09:28:08.331817 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 09:28:08.335641 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 09:28:08.339230 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 09:28:08.346343 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 09:28:08.350124 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 09:28:08.354268 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 09:28:08.357462 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 09:28:08.361274 ADC[4]: Raw value=900590 ID=7
551 09:28:08.364765 ADC[3]: Raw value=213336 ID=1
552 09:28:08.364882 RAM Code: 0x71
553 09:28:08.368911 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 09:28:08.372783 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 09:28:08.384328 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 09:28:08.388126 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 09:28:08.391303 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 09:28:08.395442 in-header: 03 07 00 00 08 00 00 00
559 09:28:08.399416 in-data: aa e4 47 04 13 02 00 00
560 09:28:08.402644 Chrome EC: UHEPI supported
561 09:28:08.410465 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 09:28:08.414350 in-header: 03 ed 00 00 08 00 00 00
563 09:28:08.414436 in-data: 80 20 60 08 00 00 00 00
564 09:28:08.417914 MRC: failed to locate region type 0.
565 09:28:08.425149 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 09:28:08.429230 DRAM-K: Running full calibration
567 09:28:08.432836 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 09:28:08.436462 header.status = 0x0
569 09:28:08.440405 header.version = 0x6 (expected: 0x6)
570 09:28:08.444143 header.size = 0xd00 (expected: 0xd00)
571 09:28:08.444230 header.flags = 0x0
572 09:28:08.450752 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 09:28:08.469061 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
574 09:28:08.477127 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 09:28:08.477221 dram_init: ddr_geometry: 2
576 09:28:08.480697 [EMI] MDL number = 2
577 09:28:08.480780 [EMI] Get MDL freq = 0
578 09:28:08.484406 dram_init: ddr_type: 0
579 09:28:08.488134 is_discrete_lpddr4: 1
580 09:28:08.488213 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 09:28:08.488277
582 09:28:08.491707
583 09:28:08.491780 [Bian_co] ETT version 0.0.0.1
584 09:28:08.498979 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 09:28:08.499083
586 09:28:08.502583 dramc_set_vcore_voltage set vcore to 650000
587 09:28:08.502690 Read voltage for 800, 4
588 09:28:08.502802 Vio18 = 0
589 09:28:08.506240 Vcore = 650000
590 09:28:08.506314 Vdram = 0
591 09:28:08.506375 Vddq = 0
592 09:28:08.509937 Vmddr = 0
593 09:28:08.510037 dram_init: config_dvfs: 1
594 09:28:08.517669 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 09:28:08.521593 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 09:28:08.524988 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 09:28:08.528472 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 09:28:08.532184 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 09:28:08.535476 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 09:28:08.538868 MEM_TYPE=3, freq_sel=18
601 09:28:08.541722 sv_algorithm_assistance_LP4_1600
602 09:28:08.545354 ============ PULL DRAM RESETB DOWN ============
603 09:28:08.548882 ========== PULL DRAM RESETB DOWN end =========
604 09:28:08.555725 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 09:28:08.558786 ===================================
606 09:28:08.558874 LPDDR4 DRAM CONFIGURATION
607 09:28:08.561863 ===================================
608 09:28:08.565914 EX_ROW_EN[0] = 0x0
609 09:28:08.569240 EX_ROW_EN[1] = 0x0
610 09:28:08.569323 LP4Y_EN = 0x0
611 09:28:08.572272 WORK_FSP = 0x0
612 09:28:08.572355 WL = 0x2
613 09:28:08.575512 RL = 0x2
614 09:28:08.575614 BL = 0x2
615 09:28:08.578936 RPST = 0x0
616 09:28:08.579019 RD_PRE = 0x0
617 09:28:08.582115 WR_PRE = 0x1
618 09:28:08.582198 WR_PST = 0x0
619 09:28:08.585949 DBI_WR = 0x0
620 09:28:08.586032 DBI_RD = 0x0
621 09:28:08.588653 OTF = 0x1
622 09:28:08.592312 ===================================
623 09:28:08.595806 ===================================
624 09:28:08.595888 ANA top config
625 09:28:08.599007 ===================================
626 09:28:08.602797 DLL_ASYNC_EN = 0
627 09:28:08.605733 ALL_SLAVE_EN = 1
628 09:28:08.605816 NEW_RANK_MODE = 1
629 09:28:08.609253 DLL_IDLE_MODE = 1
630 09:28:08.612312 LP45_APHY_COMB_EN = 1
631 09:28:08.615593 TX_ODT_DIS = 1
632 09:28:08.615676 NEW_8X_MODE = 1
633 09:28:08.619400 ===================================
634 09:28:08.622474 ===================================
635 09:28:08.625710 data_rate = 1600
636 09:28:08.629274 CKR = 1
637 09:28:08.632737 DQ_P2S_RATIO = 8
638 09:28:08.636216 ===================================
639 09:28:08.639360 CA_P2S_RATIO = 8
640 09:28:08.642319 DQ_CA_OPEN = 0
641 09:28:08.642402 DQ_SEMI_OPEN = 0
642 09:28:08.645719 CA_SEMI_OPEN = 0
643 09:28:08.649437 CA_FULL_RATE = 0
644 09:28:08.652886 DQ_CKDIV4_EN = 1
645 09:28:08.655911 CA_CKDIV4_EN = 1
646 09:28:08.659317 CA_PREDIV_EN = 0
647 09:28:08.659399 PH8_DLY = 0
648 09:28:08.662590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 09:28:08.666080 DQ_AAMCK_DIV = 4
650 09:28:08.669127 CA_AAMCK_DIV = 4
651 09:28:08.672962 CA_ADMCK_DIV = 4
652 09:28:08.675849 DQ_TRACK_CA_EN = 0
653 09:28:08.675932 CA_PICK = 800
654 09:28:08.679665 CA_MCKIO = 800
655 09:28:08.682544 MCKIO_SEMI = 0
656 09:28:08.686457 PLL_FREQ = 3068
657 09:28:08.690112 DQ_UI_PI_RATIO = 32
658 09:28:08.690195 CA_UI_PI_RATIO = 0
659 09:28:08.693827 ===================================
660 09:28:08.697455 ===================================
661 09:28:08.700911 memory_type:LPDDR4
662 09:28:08.704099 GP_NUM : 10
663 09:28:08.704182 SRAM_EN : 1
664 09:28:08.707579 MD32_EN : 0
665 09:28:08.711672 ===================================
666 09:28:08.711755 [ANA_INIT] >>>>>>>>>>>>>>
667 09:28:08.715135 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 09:28:08.719204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:28:08.722666 ===================================
670 09:28:08.725849 data_rate = 1600,PCW = 0X7600
671 09:28:08.729466 ===================================
672 09:28:08.732706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 09:28:08.736187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:28:08.742750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 09:28:08.746369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 09:28:08.749568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:28:08.752597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 09:28:08.756081 [ANA_INIT] flow start
679 09:28:08.759474 [ANA_INIT] PLL >>>>>>>>
680 09:28:08.759560 [ANA_INIT] PLL <<<<<<<<
681 09:28:08.762838 [ANA_INIT] MIDPI >>>>>>>>
682 09:28:08.766188 [ANA_INIT] MIDPI <<<<<<<<
683 09:28:08.766272 [ANA_INIT] DLL >>>>>>>>
684 09:28:08.769573 [ANA_INIT] flow end
685 09:28:08.772817 ============ LP4 DIFF to SE enter ============
686 09:28:08.776361 ============ LP4 DIFF to SE exit ============
687 09:28:08.779759 [ANA_INIT] <<<<<<<<<<<<<
688 09:28:08.783271 [Flow] Enable top DCM control >>>>>
689 09:28:08.786249 [Flow] Enable top DCM control <<<<<
690 09:28:08.789707 Enable DLL master slave shuffle
691 09:28:08.796496 ==============================================================
692 09:28:08.796581 Gating Mode config
693 09:28:08.803156 ==============================================================
694 09:28:08.803241 Config description:
695 09:28:08.813300 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 09:28:08.820038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 09:28:08.826645 SELPH_MODE 0: By rank 1: By Phase
698 09:28:08.830372 ==============================================================
699 09:28:08.833729 GAT_TRACK_EN = 1
700 09:28:08.836676 RX_GATING_MODE = 2
701 09:28:08.840502 RX_GATING_TRACK_MODE = 2
702 09:28:08.843292 SELPH_MODE = 1
703 09:28:08.846681 PICG_EARLY_EN = 1
704 09:28:08.850127 VALID_LAT_VALUE = 1
705 09:28:08.853863 ==============================================================
706 09:28:08.857156 Enter into Gating configuration >>>>
707 09:28:08.860013 Exit from Gating configuration <<<<
708 09:28:08.863456 Enter into DVFS_PRE_config >>>>>
709 09:28:08.873879 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 09:28:08.877267 Exit from DVFS_PRE_config <<<<<
711 09:28:08.880185 Enter into PICG configuration >>>>
712 09:28:08.883639 Exit from PICG configuration <<<<
713 09:28:08.887181 [RX_INPUT] configuration >>>>>
714 09:28:08.890300 [RX_INPUT] configuration <<<<<
715 09:28:08.897538 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 09:28:08.900665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 09:28:08.907708 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 09:28:08.914490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 09:28:08.917988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 09:28:08.924847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 09:28:08.928091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 09:28:08.931695 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 09:28:08.938458 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 09:28:08.941616 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 09:28:08.945209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 09:28:08.951631 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 09:28:08.954819 ===================================
728 09:28:08.954896 LPDDR4 DRAM CONFIGURATION
729 09:28:08.958743 ===================================
730 09:28:08.961930 EX_ROW_EN[0] = 0x0
731 09:28:08.962004 EX_ROW_EN[1] = 0x0
732 09:28:08.965019 LP4Y_EN = 0x0
733 09:28:08.965105 WORK_FSP = 0x0
734 09:28:08.969062 WL = 0x2
735 09:28:08.969152 RL = 0x2
736 09:28:08.971928 BL = 0x2
737 09:28:08.975592 RPST = 0x0
738 09:28:08.975675 RD_PRE = 0x0
739 09:28:08.978956 WR_PRE = 0x1
740 09:28:08.979039 WR_PST = 0x0
741 09:28:08.982104 DBI_WR = 0x0
742 09:28:08.982186 DBI_RD = 0x0
743 09:28:08.985638 OTF = 0x1
744 09:28:08.988624 ===================================
745 09:28:08.992202 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 09:28:08.995511 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 09:28:08.998931 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 09:28:09.001968 ===================================
749 09:28:09.005904 LPDDR4 DRAM CONFIGURATION
750 09:28:09.008651 ===================================
751 09:28:09.012305 EX_ROW_EN[0] = 0x10
752 09:28:09.012434 EX_ROW_EN[1] = 0x0
753 09:28:09.015568 LP4Y_EN = 0x0
754 09:28:09.015651 WORK_FSP = 0x0
755 09:28:09.019493 WL = 0x2
756 09:28:09.019576 RL = 0x2
757 09:28:09.022118 BL = 0x2
758 09:28:09.022201 RPST = 0x0
759 09:28:09.025450 RD_PRE = 0x0
760 09:28:09.025532 WR_PRE = 0x1
761 09:28:09.028926 WR_PST = 0x0
762 09:28:09.029007 DBI_WR = 0x0
763 09:28:09.032611 DBI_RD = 0x0
764 09:28:09.032704 OTF = 0x1
765 09:28:09.035700 ===================================
766 09:28:09.042268 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 09:28:09.047027 nWR fixed to 40
768 09:28:09.050065 [ModeRegInit_LP4] CH0 RK0
769 09:28:09.050148 [ModeRegInit_LP4] CH0 RK1
770 09:28:09.053768 [ModeRegInit_LP4] CH1 RK0
771 09:28:09.056831 [ModeRegInit_LP4] CH1 RK1
772 09:28:09.056905 match AC timing 13
773 09:28:09.063631 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 09:28:09.067419 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 09:28:09.070508 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 09:28:09.077007 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 09:28:09.080583 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 09:28:09.080666 [EMI DOE] emi_dcm 0
779 09:28:09.087235 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 09:28:09.087319 ==
781 09:28:09.090392 Dram Type= 6, Freq= 0, CH_0, rank 0
782 09:28:09.093883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 09:28:09.093980 ==
784 09:28:09.100385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 09:28:09.103921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 09:28:09.114044 [CA 0] Center 37 (7~68) winsize 62
787 09:28:09.117552 [CA 1] Center 37 (6~68) winsize 63
788 09:28:09.121122 [CA 2] Center 35 (5~66) winsize 62
789 09:28:09.124453 [CA 3] Center 34 (4~65) winsize 62
790 09:28:09.127633 [CA 4] Center 34 (3~65) winsize 63
791 09:28:09.131139 [CA 5] Center 33 (3~64) winsize 62
792 09:28:09.131222
793 09:28:09.134861 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 09:28:09.134944
795 09:28:09.137988 [CATrainingPosCal] consider 1 rank data
796 09:28:09.141621 u2DelayCellTimex100 = 270/100 ps
797 09:28:09.144685 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 09:28:09.147846 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 09:28:09.151684 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 09:28:09.158276 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 09:28:09.161731 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 09:28:09.164742 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 09:28:09.164825
804 09:28:09.168235 CA PerBit enable=1, Macro0, CA PI delay=33
805 09:28:09.168319
806 09:28:09.171541 [CBTSetCACLKResult] CA Dly = 33
807 09:28:09.171624 CS Dly: 5 (0~36)
808 09:28:09.171689 ==
809 09:28:09.174935 Dram Type= 6, Freq= 0, CH_0, rank 1
810 09:28:09.178254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 09:28:09.182018 ==
812 09:28:09.185083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 09:28:09.191789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 09:28:09.200541 [CA 0] Center 37 (6~68) winsize 63
815 09:28:09.203839 [CA 1] Center 37 (7~68) winsize 62
816 09:28:09.207265 [CA 2] Center 35 (5~66) winsize 62
817 09:28:09.210924 [CA 3] Center 35 (4~66) winsize 63
818 09:28:09.213790 [CA 4] Center 33 (3~64) winsize 62
819 09:28:09.217511 [CA 5] Center 33 (3~64) winsize 62
820 09:28:09.217594
821 09:28:09.221447 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 09:28:09.221530
823 09:28:09.224651 [CATrainingPosCal] consider 2 rank data
824 09:28:09.227623 u2DelayCellTimex100 = 270/100 ps
825 09:28:09.231070 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 09:28:09.234167 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 09:28:09.237516 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 09:28:09.244562 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 09:28:09.248022 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 09:28:09.251216 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 09:28:09.251298
832 09:28:09.254492 CA PerBit enable=1, Macro0, CA PI delay=33
833 09:28:09.254575
834 09:28:09.257795 [CBTSetCACLKResult] CA Dly = 33
835 09:28:09.257878 CS Dly: 5 (0~37)
836 09:28:09.257944
837 09:28:09.261064 ----->DramcWriteLeveling(PI) begin...
838 09:28:09.261151 ==
839 09:28:09.264377 Dram Type= 6, Freq= 0, CH_0, rank 0
840 09:28:09.268556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 09:28:09.272072 ==
842 09:28:09.272155 Write leveling (Byte 0): 29 => 29
843 09:28:09.275878 Write leveling (Byte 1): 29 => 29
844 09:28:09.278993 DramcWriteLeveling(PI) end<-----
845 09:28:09.279076
846 09:28:09.279156 ==
847 09:28:09.283087 Dram Type= 6, Freq= 0, CH_0, rank 0
848 09:28:09.286020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 09:28:09.286103 ==
850 09:28:09.289682 [Gating] SW mode calibration
851 09:28:09.296306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 09:28:09.303374 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 09:28:09.306663 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 09:28:09.310141 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 09:28:09.313318 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 09:28:09.320453 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 09:28:09.324137 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:28:09.327390 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:28:09.334250 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:28:09.337210 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:28:09.340815 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:28:09.347314 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:28:09.350712 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:28:09.353832 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:28:09.360365 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:28:09.364108 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:28:09.367391 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:28:09.370549 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:28:09.377282 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 09:28:09.380596 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 09:28:09.383960 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 09:28:09.391207 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
873 09:28:09.394204 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:28:09.397559 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:28:09.404544 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:28:09.407841 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:28:09.410974 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 09:28:09.417595 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 09:28:09.421412 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 09:28:09.424583 0 9 12 | B1->B0 | 2c2c 3232 | 0 1 | (0 0) (0 0)
881 09:28:09.428207 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:28:09.434477 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:28:09.437661 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:28:09.441178 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 09:28:09.448236 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 09:28:09.451274 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 09:28:09.454358 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
888 09:28:09.461229 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
889 09:28:09.465139 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:28:09.467747 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:28:09.474874 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:28:09.478046 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:28:09.481260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 09:28:09.488036 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 09:28:09.491379 0 11 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
896 09:28:09.495313 0 11 12 | B1->B0 | 3b3b 4343 | 0 0 | (1 1) (0 0)
897 09:28:09.498270 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:28:09.505363 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:28:09.508854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:28:09.511629 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 09:28:09.518583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 09:28:09.522019 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 09:28:09.525210 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 09:28:09.531863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
905 09:28:09.535430 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:28:09.538616 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:28:09.542271 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:28:09.549062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:28:09.552411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:28:09.555693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:28:09.562495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:28:09.565750 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:28:09.569214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:28:09.576247 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:28:09.578987 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:28:09.582609 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 09:28:09.589376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 09:28:09.592671 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 09:28:09.595771 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 09:28:09.599100 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 09:28:09.602639 Total UI for P1: 0, mck2ui 16
922 09:28:09.605836 best dqsien dly found for B0: ( 0, 14, 8)
923 09:28:09.612503 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 09:28:09.612580 Total UI for P1: 0, mck2ui 16
925 09:28:09.619403 best dqsien dly found for B1: ( 0, 14, 10)
926 09:28:09.622838 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 09:28:09.626284 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 09:28:09.626356
929 09:28:09.629488 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 09:28:09.632599 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 09:28:09.636210 [Gating] SW calibration Done
932 09:28:09.636283 ==
933 09:28:09.639743 Dram Type= 6, Freq= 0, CH_0, rank 0
934 09:28:09.642706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 09:28:09.642818 ==
936 09:28:09.646307 RX Vref Scan: 0
937 09:28:09.646390
938 09:28:09.646453 RX Vref 0 -> 0, step: 1
939 09:28:09.646510
940 09:28:09.649475 RX Delay -130 -> 252, step: 16
941 09:28:09.653068 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 09:28:09.659638 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 09:28:09.663032 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 09:28:09.666448 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 09:28:09.669849 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 09:28:09.673338 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 09:28:09.677099 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 09:28:09.683439 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 09:28:09.686903 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 09:28:09.690217 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 09:28:09.693970 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 09:28:09.697120 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 09:28:09.703697 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 09:28:09.707054 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
955 09:28:09.710039 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 09:28:09.713479 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 09:28:09.713553 ==
958 09:28:09.716959 Dram Type= 6, Freq= 0, CH_0, rank 0
959 09:28:09.723560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 09:28:09.723652 ==
961 09:28:09.723721 DQS Delay:
962 09:28:09.723785 DQS0 = 0, DQS1 = 0
963 09:28:09.726960 DQM Delay:
964 09:28:09.727064 DQM0 = 87, DQM1 = 77
965 09:28:09.730204 DQ Delay:
966 09:28:09.733612 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 09:28:09.733693 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
968 09:28:09.737180 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
969 09:28:09.740449 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
970 09:28:09.743914
971 09:28:09.743986
972 09:28:09.744048 ==
973 09:28:09.747346 Dram Type= 6, Freq= 0, CH_0, rank 0
974 09:28:09.750393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 09:28:09.750470 ==
976 09:28:09.750542
977 09:28:09.750627
978 09:28:09.753643 TX Vref Scan disable
979 09:28:09.753715 == TX Byte 0 ==
980 09:28:09.760286 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
981 09:28:09.763898 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
982 09:28:09.764001 == TX Byte 1 ==
983 09:28:09.770595 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 09:28:09.773786 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 09:28:09.773865 ==
986 09:28:09.777784 Dram Type= 6, Freq= 0, CH_0, rank 0
987 09:28:09.780676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 09:28:09.780769 ==
989 09:28:09.794200 TX Vref=22, minBit 0, minWin=27, winSum=439
990 09:28:09.797551 TX Vref=24, minBit 5, minWin=27, winSum=445
991 09:28:09.801049 TX Vref=26, minBit 8, minWin=27, winSum=446
992 09:28:09.804268 TX Vref=28, minBit 12, minWin=27, winSum=448
993 09:28:09.807495 TX Vref=30, minBit 2, minWin=28, winSum=454
994 09:28:09.810662 TX Vref=32, minBit 3, minWin=27, winSum=451
995 09:28:09.817521 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
996 09:28:09.817605
997 09:28:09.821044 Final TX Range 1 Vref 30
998 09:28:09.821127
999 09:28:09.821192 ==
1000 09:28:09.824483 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 09:28:09.827626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 09:28:09.827743 ==
1003 09:28:09.827903
1004 09:28:09.828002
1005 09:28:09.830981 TX Vref Scan disable
1006 09:28:09.834465 == TX Byte 0 ==
1007 09:28:09.837781 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 09:28:09.840808 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 09:28:09.844601 == TX Byte 1 ==
1010 09:28:09.847541 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 09:28:09.851051 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 09:28:09.851130
1013 09:28:09.854311 [DATLAT]
1014 09:28:09.854412 Freq=800, CH0 RK0
1015 09:28:09.854540
1016 09:28:09.857552 DATLAT Default: 0xa
1017 09:28:09.857661 0, 0xFFFF, sum = 0
1018 09:28:09.861541 1, 0xFFFF, sum = 0
1019 09:28:09.861660 2, 0xFFFF, sum = 0
1020 09:28:09.864684 3, 0xFFFF, sum = 0
1021 09:28:09.864790 4, 0xFFFF, sum = 0
1022 09:28:09.867825 5, 0xFFFF, sum = 0
1023 09:28:09.867909 6, 0xFFFF, sum = 0
1024 09:28:09.871321 7, 0xFFFF, sum = 0
1025 09:28:09.871412 8, 0xFFFF, sum = 0
1026 09:28:09.874925 9, 0x0, sum = 1
1027 09:28:09.875008 10, 0x0, sum = 2
1028 09:28:09.877926 11, 0x0, sum = 3
1029 09:28:09.878008 12, 0x0, sum = 4
1030 09:28:09.881416 best_step = 10
1031 09:28:09.881497
1032 09:28:09.881561 ==
1033 09:28:09.884937 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 09:28:09.888190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 09:28:09.888298 ==
1036 09:28:09.888410 RX Vref Scan: 1
1037 09:28:09.888555
1038 09:28:09.891424 Set Vref Range= 32 -> 127
1039 09:28:09.891505
1040 09:28:09.895067 RX Vref 32 -> 127, step: 1
1041 09:28:09.895164
1042 09:28:09.897995 RX Delay -95 -> 252, step: 8
1043 09:28:09.898079
1044 09:28:09.901698 Set Vref, RX VrefLevel [Byte0]: 32
1045 09:28:09.905005 [Byte1]: 32
1046 09:28:09.905116
1047 09:28:09.909386 Set Vref, RX VrefLevel [Byte0]: 33
1048 09:28:09.912249 [Byte1]: 33
1049 09:28:09.912366
1050 09:28:09.915867 Set Vref, RX VrefLevel [Byte0]: 34
1051 09:28:09.919002 [Byte1]: 34
1052 09:28:09.919095
1053 09:28:09.922150 Set Vref, RX VrefLevel [Byte0]: 35
1054 09:28:09.925258 [Byte1]: 35
1055 09:28:09.929815
1056 09:28:09.929908 Set Vref, RX VrefLevel [Byte0]: 36
1057 09:28:09.932822 [Byte1]: 36
1058 09:28:09.938133
1059 09:28:09.938215 Set Vref, RX VrefLevel [Byte0]: 37
1060 09:28:09.941462 [Byte1]: 37
1061 09:28:09.945050
1062 09:28:09.945130 Set Vref, RX VrefLevel [Byte0]: 38
1063 09:28:09.948284 [Byte1]: 38
1064 09:28:09.952800
1065 09:28:09.952884 Set Vref, RX VrefLevel [Byte0]: 39
1066 09:28:09.956167 [Byte1]: 39
1067 09:28:09.959860
1068 09:28:09.959942 Set Vref, RX VrefLevel [Byte0]: 40
1069 09:28:09.963415 [Byte1]: 40
1070 09:28:09.967295
1071 09:28:09.967384 Set Vref, RX VrefLevel [Byte0]: 41
1072 09:28:09.971032 [Byte1]: 41
1073 09:28:09.975196
1074 09:28:09.975278 Set Vref, RX VrefLevel [Byte0]: 42
1075 09:28:09.978219 [Byte1]: 42
1076 09:28:09.982774
1077 09:28:09.982857 Set Vref, RX VrefLevel [Byte0]: 43
1078 09:28:09.986094 [Byte1]: 43
1079 09:28:09.990458
1080 09:28:09.990539 Set Vref, RX VrefLevel [Byte0]: 44
1081 09:28:09.993744 [Byte1]: 44
1082 09:28:09.998171
1083 09:28:09.998255 Set Vref, RX VrefLevel [Byte0]: 45
1084 09:28:10.001119 [Byte1]: 45
1085 09:28:10.005313
1086 09:28:10.005394 Set Vref, RX VrefLevel [Byte0]: 46
1087 09:28:10.008713 [Byte1]: 46
1088 09:28:10.013026
1089 09:28:10.013114 Set Vref, RX VrefLevel [Byte0]: 47
1090 09:28:10.016177 [Byte1]: 47
1091 09:28:10.020714
1092 09:28:10.020794 Set Vref, RX VrefLevel [Byte0]: 48
1093 09:28:10.023845 [Byte1]: 48
1094 09:28:10.028465
1095 09:28:10.028547 Set Vref, RX VrefLevel [Byte0]: 49
1096 09:28:10.031351 [Byte1]: 49
1097 09:28:10.035541
1098 09:28:10.035622 Set Vref, RX VrefLevel [Byte0]: 50
1099 09:28:10.039472 [Byte1]: 50
1100 09:28:10.043260
1101 09:28:10.043341 Set Vref, RX VrefLevel [Byte0]: 51
1102 09:28:10.047510 [Byte1]: 51
1103 09:28:10.050918
1104 09:28:10.051000 Set Vref, RX VrefLevel [Byte0]: 52
1105 09:28:10.054330 [Byte1]: 52
1106 09:28:10.058881
1107 09:28:10.058973 Set Vref, RX VrefLevel [Byte0]: 53
1108 09:28:10.062513 [Byte1]: 53
1109 09:28:10.066621
1110 09:28:10.066748 Set Vref, RX VrefLevel [Byte0]: 54
1111 09:28:10.069743 [Byte1]: 54
1112 09:28:10.073907
1113 09:28:10.074034 Set Vref, RX VrefLevel [Byte0]: 55
1114 09:28:10.077887 [Byte1]: 55
1115 09:28:10.081354
1116 09:28:10.081455 Set Vref, RX VrefLevel [Byte0]: 56
1117 09:28:10.084889 [Byte1]: 56
1118 09:28:10.088753
1119 09:28:10.088840 Set Vref, RX VrefLevel [Byte0]: 57
1120 09:28:10.092177 [Byte1]: 57
1121 09:28:10.096358
1122 09:28:10.096442 Set Vref, RX VrefLevel [Byte0]: 58
1123 09:28:10.100077 [Byte1]: 58
1124 09:28:10.104433
1125 09:28:10.104514 Set Vref, RX VrefLevel [Byte0]: 59
1126 09:28:10.107262 [Byte1]: 59
1127 09:28:10.111976
1128 09:28:10.112056 Set Vref, RX VrefLevel [Byte0]: 60
1129 09:28:10.115208 [Byte1]: 60
1130 09:28:10.119171
1131 09:28:10.119252 Set Vref, RX VrefLevel [Byte0]: 61
1132 09:28:10.122670 [Byte1]: 61
1133 09:28:10.126688
1134 09:28:10.126817 Set Vref, RX VrefLevel [Byte0]: 62
1135 09:28:10.130588 [Byte1]: 62
1136 09:28:10.134565
1137 09:28:10.134646 Set Vref, RX VrefLevel [Byte0]: 63
1138 09:28:10.137901 [Byte1]: 63
1139 09:28:10.141998
1140 09:28:10.142079 Set Vref, RX VrefLevel [Byte0]: 64
1141 09:28:10.145360 [Byte1]: 64
1142 09:28:10.149857
1143 09:28:10.149938 Set Vref, RX VrefLevel [Byte0]: 65
1144 09:28:10.153018 [Byte1]: 65
1145 09:28:10.157399
1146 09:28:10.157482 Set Vref, RX VrefLevel [Byte0]: 66
1147 09:28:10.160478 [Byte1]: 66
1148 09:28:10.164741
1149 09:28:10.164848 Set Vref, RX VrefLevel [Byte0]: 67
1150 09:28:10.168442 [Byte1]: 67
1151 09:28:10.172345
1152 09:28:10.172429 Set Vref, RX VrefLevel [Byte0]: 68
1153 09:28:10.175877 [Byte1]: 68
1154 09:28:10.180111
1155 09:28:10.180192 Set Vref, RX VrefLevel [Byte0]: 69
1156 09:28:10.183689 [Byte1]: 69
1157 09:28:10.187880
1158 09:28:10.187962 Set Vref, RX VrefLevel [Byte0]: 70
1159 09:28:10.191293 [Byte1]: 70
1160 09:28:10.195134
1161 09:28:10.195220 Set Vref, RX VrefLevel [Byte0]: 71
1162 09:28:10.198661 [Byte1]: 71
1163 09:28:10.202707
1164 09:28:10.202815 Set Vref, RX VrefLevel [Byte0]: 72
1165 09:28:10.205991 [Byte1]: 72
1166 09:28:10.210913
1167 09:28:10.211001 Set Vref, RX VrefLevel [Byte0]: 73
1168 09:28:10.213921 [Byte1]: 73
1169 09:28:10.218402
1170 09:28:10.218489 Set Vref, RX VrefLevel [Byte0]: 74
1171 09:28:10.221471 [Byte1]: 74
1172 09:28:10.225534
1173 09:28:10.225624 Set Vref, RX VrefLevel [Byte0]: 75
1174 09:28:10.229482 [Byte1]: 75
1175 09:28:10.233216
1176 09:28:10.233305 Final RX Vref Byte 0 = 62 to rank0
1177 09:28:10.236620 Final RX Vref Byte 1 = 61 to rank0
1178 09:28:10.239908 Final RX Vref Byte 0 = 62 to rank1
1179 09:28:10.243352 Final RX Vref Byte 1 = 61 to rank1==
1180 09:28:10.247034 Dram Type= 6, Freq= 0, CH_0, rank 0
1181 09:28:10.250054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1182 09:28:10.253333 ==
1183 09:28:10.253425 DQS Delay:
1184 09:28:10.253491 DQS0 = 0, DQS1 = 0
1185 09:28:10.256879 DQM Delay:
1186 09:28:10.256962 DQM0 = 88, DQM1 = 78
1187 09:28:10.260165 DQ Delay:
1188 09:28:10.260250 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1189 09:28:10.263563 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =96
1190 09:28:10.267023 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1191 09:28:10.270239 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1192 09:28:10.270324
1193 09:28:10.270388
1194 09:28:10.280324 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1195 09:28:10.283767 CH0 RK0: MR19=606, MR18=2D14
1196 09:28:10.287126 CH0_RK0: MR19=0x606, MR18=0x2D14, DQSOSC=398, MR23=63, INC=93, DEC=62
1197 09:28:10.290610
1198 09:28:10.293639 ----->DramcWriteLeveling(PI) begin...
1199 09:28:10.293748 ==
1200 09:28:10.297104 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 09:28:10.300712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 09:28:10.300804 ==
1203 09:28:10.304060 Write leveling (Byte 0): 29 => 29
1204 09:28:10.307521 Write leveling (Byte 1): 29 => 29
1205 09:28:10.311126 DramcWriteLeveling(PI) end<-----
1206 09:28:10.311212
1207 09:28:10.311276 ==
1208 09:28:10.314253 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 09:28:10.317382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 09:28:10.317466 ==
1211 09:28:10.320868 [Gating] SW mode calibration
1212 09:28:10.326917 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1213 09:28:10.334181 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1214 09:28:10.337270 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 09:28:10.340620 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1216 09:28:10.344076 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1217 09:28:10.391580 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 09:28:10.391735 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 09:28:10.392128 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:28:10.392493 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:28:10.392770 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:28:10.392850 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:28:10.392914 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:28:10.393184 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:28:10.393325 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:28:10.393452 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:28:10.427604 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:28:10.427789 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:28:10.427899 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:28:10.428243 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:28:10.428393 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1232 09:28:10.428536 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1233 09:28:10.428660 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 09:28:10.428800 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 09:28:10.431527 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:28:10.434894 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:28:10.438242 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 09:28:10.441723 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 09:28:10.445642 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 09:28:10.451682 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1241 09:28:10.455038 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1242 09:28:10.458621 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 09:28:10.465395 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 09:28:10.468409 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 09:28:10.471657 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 09:28:10.478357 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 09:28:10.482016 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1248 09:28:10.485016 0 10 8 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
1249 09:28:10.488854 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 09:28:10.495204 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 09:28:10.498687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:28:10.502012 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 09:28:10.508865 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 09:28:10.512428 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 09:28:10.515575 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1256 09:28:10.522900 0 11 8 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
1257 09:28:10.527114 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 09:28:10.531276 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 09:28:10.534856 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 09:28:10.537976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 09:28:10.544557 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 09:28:10.548666 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 09:28:10.552020 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1264 09:28:10.555262 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1265 09:28:10.561922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 09:28:10.565689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 09:28:10.568920 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 09:28:10.575756 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:28:10.578965 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:28:10.582462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 09:28:10.585528 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:28:10.592119 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:28:10.595787 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:28:10.599178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:28:10.605692 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 09:28:10.609149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 09:28:10.612334 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 09:28:10.619165 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:28:10.622331 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1280 09:28:10.625842 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 09:28:10.629255 Total UI for P1: 0, mck2ui 16
1282 09:28:10.632920 best dqsien dly found for B0: ( 0, 14, 4)
1283 09:28:10.636281 Total UI for P1: 0, mck2ui 16
1284 09:28:10.639646 best dqsien dly found for B1: ( 0, 14, 6)
1285 09:28:10.642665 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1286 09:28:10.645852 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1287 09:28:10.645934
1288 09:28:10.649751 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 09:28:10.652681 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1290 09:28:10.656030 [Gating] SW calibration Done
1291 09:28:10.656111 ==
1292 09:28:10.659569 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 09:28:10.662877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 09:28:10.666083 ==
1295 09:28:10.666166 RX Vref Scan: 0
1296 09:28:10.666245
1297 09:28:10.669732 RX Vref 0 -> 0, step: 1
1298 09:28:10.669814
1299 09:28:10.672883 RX Delay -130 -> 252, step: 16
1300 09:28:10.676458 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1301 09:28:10.680102 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1302 09:28:10.683126 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1303 09:28:10.686449 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1304 09:28:10.690154 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1305 09:28:10.696325 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1306 09:28:10.699793 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1307 09:28:10.703163 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1308 09:28:10.706641 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1309 09:28:10.710135 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1310 09:28:10.716357 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1311 09:28:10.719701 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1312 09:28:10.723438 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1313 09:28:10.726675 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1314 09:28:10.730126 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1315 09:28:10.736942 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1316 09:28:10.737025 ==
1317 09:28:10.740021 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 09:28:10.743844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 09:28:10.743975 ==
1320 09:28:10.744094 DQS Delay:
1321 09:28:10.746730 DQS0 = 0, DQS1 = 0
1322 09:28:10.746892 DQM Delay:
1323 09:28:10.750437 DQM0 = 83, DQM1 = 71
1324 09:28:10.750568 DQ Delay:
1325 09:28:10.753907 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1326 09:28:10.756791 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1327 09:28:10.760055 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1328 09:28:10.763414 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
1329 09:28:10.763545
1330 09:28:10.763665
1331 09:28:10.763782 ==
1332 09:28:10.767373 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 09:28:10.770061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 09:28:10.770197 ==
1335 09:28:10.770320
1336 09:28:10.770439
1337 09:28:10.773581 TX Vref Scan disable
1338 09:28:10.776791 == TX Byte 0 ==
1339 09:28:10.780105 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1340 09:28:10.783955 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1341 09:28:10.786663 == TX Byte 1 ==
1342 09:28:10.790659 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1343 09:28:10.794026 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1344 09:28:10.794159 ==
1345 09:28:10.797018 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 09:28:10.800760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 09:28:10.804003 ==
1348 09:28:10.814989 TX Vref=22, minBit 1, minWin=27, winSum=440
1349 09:28:10.818883 TX Vref=24, minBit 8, minWin=27, winSum=448
1350 09:28:10.821565 TX Vref=26, minBit 3, minWin=27, winSum=449
1351 09:28:10.825331 TX Vref=28, minBit 3, minWin=27, winSum=448
1352 09:28:10.828291 TX Vref=30, minBit 7, minWin=27, winSum=453
1353 09:28:10.831559 TX Vref=32, minBit 13, minWin=27, winSum=453
1354 09:28:10.838728 [TxChooseVref] Worse bit 7, Min win 27, Win sum 453, Final Vref 30
1355 09:28:10.838861
1356 09:28:10.841965 Final TX Range 1 Vref 30
1357 09:28:10.842097
1358 09:28:10.842219 ==
1359 09:28:10.845616 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 09:28:10.848681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 09:28:10.848766 ==
1362 09:28:10.848829
1363 09:28:10.848888
1364 09:28:10.852058 TX Vref Scan disable
1365 09:28:10.855202 == TX Byte 0 ==
1366 09:28:10.858477 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1367 09:28:10.862355 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1368 09:28:10.865240 == TX Byte 1 ==
1369 09:28:10.868571 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1370 09:28:10.871854 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1371 09:28:10.871938
1372 09:28:10.875360 [DATLAT]
1373 09:28:10.875441 Freq=800, CH0 RK1
1374 09:28:10.875506
1375 09:28:10.878718 DATLAT Default: 0xa
1376 09:28:10.878821 0, 0xFFFF, sum = 0
1377 09:28:10.882420 1, 0xFFFF, sum = 0
1378 09:28:10.882503 2, 0xFFFF, sum = 0
1379 09:28:10.885716 3, 0xFFFF, sum = 0
1380 09:28:10.885787 4, 0xFFFF, sum = 0
1381 09:28:10.888906 5, 0xFFFF, sum = 0
1382 09:28:10.888988 6, 0xFFFF, sum = 0
1383 09:28:10.891987 7, 0xFFFF, sum = 0
1384 09:28:10.892070 8, 0xFFFF, sum = 0
1385 09:28:10.895266 9, 0x0, sum = 1
1386 09:28:10.895348 10, 0x0, sum = 2
1387 09:28:10.898687 11, 0x0, sum = 3
1388 09:28:10.898806 12, 0x0, sum = 4
1389 09:28:10.902160 best_step = 10
1390 09:28:10.902241
1391 09:28:10.902304 ==
1392 09:28:10.905572 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 09:28:10.908614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 09:28:10.908696 ==
1395 09:28:10.912485 RX Vref Scan: 0
1396 09:28:10.912565
1397 09:28:10.912629 RX Vref 0 -> 0, step: 1
1398 09:28:10.912688
1399 09:28:10.915593 RX Delay -95 -> 252, step: 8
1400 09:28:10.918876 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1401 09:28:10.925815 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1402 09:28:10.929096 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1403 09:28:10.932175 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1404 09:28:10.936075 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1405 09:28:10.940028 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1406 09:28:10.945951 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1407 09:28:10.949159 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1408 09:28:10.952319 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1409 09:28:10.955814 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1410 09:28:10.959145 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1411 09:28:10.965840 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1412 09:28:10.969748 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1413 09:28:10.972831 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1414 09:28:10.975928 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1415 09:28:10.979516 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1416 09:28:10.979597 ==
1417 09:28:10.982998 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 09:28:10.989909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 09:28:10.990014 ==
1420 09:28:10.990106 DQS Delay:
1421 09:28:10.993448 DQS0 = 0, DQS1 = 0
1422 09:28:10.993545 DQM Delay:
1423 09:28:10.993641 DQM0 = 87, DQM1 = 79
1424 09:28:10.996254 DQ Delay:
1425 09:28:10.999325 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1426 09:28:11.002857 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1427 09:28:11.002954 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1428 09:28:11.009746 DQ12 =84, DQ13 =88, DQ14 =88, DQ15 =88
1429 09:28:11.009844
1430 09:28:11.009940
1431 09:28:11.016500 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1432 09:28:11.020355 CH0 RK1: MR19=606, MR18=2C16
1433 09:28:11.026774 CH0_RK1: MR19=0x606, MR18=0x2C16, DQSOSC=398, MR23=63, INC=93, DEC=62
1434 09:28:11.029732 [RxdqsGatingPostProcess] freq 800
1435 09:28:11.033524 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 09:28:11.036462 Pre-setting of DQS Precalculation
1437 09:28:11.043431 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 09:28:11.043521 ==
1439 09:28:11.046543 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 09:28:11.049879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 09:28:11.049956 ==
1442 09:28:11.053396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 09:28:11.060009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 09:28:11.070371 [CA 0] Center 36 (6~67) winsize 62
1445 09:28:11.073283 [CA 1] Center 36 (6~67) winsize 62
1446 09:28:11.076812 [CA 2] Center 34 (4~64) winsize 61
1447 09:28:11.079902 [CA 3] Center 33 (3~64) winsize 62
1448 09:28:11.083090 [CA 4] Center 34 (3~65) winsize 63
1449 09:28:11.086615 [CA 5] Center 33 (3~64) winsize 62
1450 09:28:11.086731
1451 09:28:11.089911 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1452 09:28:11.089991
1453 09:28:11.093829 [CATrainingPosCal] consider 1 rank data
1454 09:28:11.096898 u2DelayCellTimex100 = 270/100 ps
1455 09:28:11.100083 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 09:28:11.103739 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1457 09:28:11.106917 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1458 09:28:11.113546 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 09:28:11.116789 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1460 09:28:11.120382 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1461 09:28:11.120464
1462 09:28:11.123816 CA PerBit enable=1, Macro0, CA PI delay=33
1463 09:28:11.123884
1464 09:28:11.127007 [CBTSetCACLKResult] CA Dly = 33
1465 09:28:11.127100 CS Dly: 5 (0~36)
1466 09:28:11.127197 ==
1467 09:28:11.130139 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 09:28:11.133589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 09:28:11.137086 ==
1470 09:28:11.140637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 09:28:11.146875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 09:28:11.155849 [CA 0] Center 36 (6~67) winsize 62
1473 09:28:11.159013 [CA 1] Center 36 (5~67) winsize 63
1474 09:28:11.162503 [CA 2] Center 33 (3~64) winsize 62
1475 09:28:11.165978 [CA 3] Center 33 (3~64) winsize 62
1476 09:28:11.169391 [CA 4] Center 34 (3~65) winsize 63
1477 09:28:11.172559 [CA 5] Center 33 (3~64) winsize 62
1478 09:28:11.172657
1479 09:28:11.176278 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1480 09:28:11.176369
1481 09:28:11.179368 [CATrainingPosCal] consider 2 rank data
1482 09:28:11.182893 u2DelayCellTimex100 = 270/100 ps
1483 09:28:11.187249 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1484 09:28:11.190902 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1485 09:28:11.195051 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1486 09:28:11.198296 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1487 09:28:11.202044 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1488 09:28:11.205325 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1489 09:28:11.205407
1490 09:28:11.209106 CA PerBit enable=1, Macro0, CA PI delay=33
1491 09:28:11.209187
1492 09:28:11.213107 [CBTSetCACLKResult] CA Dly = 33
1493 09:28:11.213189 CS Dly: 5 (0~36)
1494 09:28:11.213253
1495 09:28:11.216524 ----->DramcWriteLeveling(PI) begin...
1496 09:28:11.216640 ==
1497 09:28:11.220113 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 09:28:11.223639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 09:28:11.226756 ==
1500 09:28:11.226851 Write leveling (Byte 0): 28 => 28
1501 09:28:11.230401 Write leveling (Byte 1): 29 => 29
1502 09:28:11.233926 DramcWriteLeveling(PI) end<-----
1503 09:28:11.234008
1504 09:28:11.234072 ==
1505 09:28:11.236766 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 09:28:11.243761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 09:28:11.243843 ==
1508 09:28:11.243907 [Gating] SW mode calibration
1509 09:28:11.253708 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 09:28:11.257369 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 09:28:11.260557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 09:28:11.266917 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1513 09:28:11.270433 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 09:28:11.273793 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 09:28:11.280425 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 09:28:11.283727 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 09:28:11.287350 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:28:11.294195 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:28:11.297283 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1520 09:28:11.300582 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:28:11.304070 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:28:11.310867 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1523 09:28:11.314004 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1524 09:28:11.317710 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:28:11.324094 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:28:11.328016 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:28:11.331109 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1528 09:28:11.337760 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1529 09:28:11.341351 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1530 09:28:11.344659 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 09:28:11.348151 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1532 09:28:11.354519 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:28:11.357774 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:28:11.361354 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1535 09:28:11.368218 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 09:28:11.371599 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 09:28:11.374587 0 9 8 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
1538 09:28:11.381545 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 09:28:11.384739 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 09:28:11.388091 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 09:28:11.394914 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 09:28:11.398533 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 09:28:11.401693 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 09:28:11.404975 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1545 09:28:11.411640 0 10 8 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 0)
1546 09:28:11.415297 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 09:28:11.418369 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1548 09:28:11.425427 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 09:28:11.428652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 09:28:11.432453 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 09:28:11.439192 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 09:28:11.441953 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1553 09:28:11.445682 0 11 8 | B1->B0 | 3737 3c3c | 1 0 | (0 0) (0 0)
1554 09:28:11.452173 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 09:28:11.455609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 09:28:11.458579 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 09:28:11.462319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 09:28:11.469038 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 09:28:11.472114 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 09:28:11.475370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 09:28:11.482508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1562 09:28:11.485385 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 09:28:11.489220 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 09:28:11.495336 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 09:28:11.498626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:28:11.502294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:28:11.508875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:28:11.512653 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:28:11.516051 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:28:11.522672 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:28:11.525423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:28:11.528738 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:28:11.535800 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:28:11.539103 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 09:28:11.542427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 09:28:11.545596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 09:28:11.552422 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 09:28:11.555505 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 09:28:11.559053 Total UI for P1: 0, mck2ui 16
1580 09:28:11.562185 best dqsien dly found for B0: ( 0, 14, 8)
1581 09:28:11.565697 Total UI for P1: 0, mck2ui 16
1582 09:28:11.569059 best dqsien dly found for B1: ( 0, 14, 8)
1583 09:28:11.572624 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1584 09:28:11.576163 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1585 09:28:11.576241
1586 09:28:11.579096 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1587 09:28:11.582782 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1588 09:28:11.585732 [Gating] SW calibration Done
1589 09:28:11.585801 ==
1590 09:28:11.589403 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 09:28:11.592630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 09:28:11.592701 ==
1593 09:28:11.595787 RX Vref Scan: 0
1594 09:28:11.595861
1595 09:28:11.599353 RX Vref 0 -> 0, step: 1
1596 09:28:11.599422
1597 09:28:11.599482 RX Delay -130 -> 252, step: 16
1598 09:28:11.606015 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1599 09:28:11.609591 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1600 09:28:11.612642 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1601 09:28:11.616255 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1602 09:28:11.619366 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1603 09:28:11.626353 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1604 09:28:11.629328 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1605 09:28:11.632751 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1606 09:28:11.636566 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1607 09:28:11.639823 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1608 09:28:11.643017 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1609 09:28:11.650412 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1610 09:28:11.653109 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1611 09:28:11.656418 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1612 09:28:11.660045 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1613 09:28:11.666516 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1614 09:28:11.666620 ==
1615 09:28:11.669797 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 09:28:11.672957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 09:28:11.673053 ==
1618 09:28:11.673144 DQS Delay:
1619 09:28:11.676622 DQS0 = 0, DQS1 = 0
1620 09:28:11.676693 DQM Delay:
1621 09:28:11.679788 DQM0 = 83, DQM1 = 76
1622 09:28:11.679864 DQ Delay:
1623 09:28:11.683553 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1624 09:28:11.686362 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1625 09:28:11.690281 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1626 09:28:11.693443 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1627 09:28:11.693520
1628 09:28:11.693580
1629 09:28:11.693637 ==
1630 09:28:11.696449 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 09:28:11.700104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 09:28:11.700184 ==
1633 09:28:11.700244
1634 09:28:11.700300
1635 09:28:11.703148 TX Vref Scan disable
1636 09:28:11.707073 == TX Byte 0 ==
1637 09:28:11.710238 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 09:28:11.713296 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 09:28:11.717253 == TX Byte 1 ==
1640 09:28:11.720227 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1641 09:28:11.723477 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1642 09:28:11.723568 ==
1643 09:28:11.726677 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 09:28:11.730074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 09:28:11.730173 ==
1646 09:28:11.744508 TX Vref=22, minBit 0, minWin=27, winSum=439
1647 09:28:11.747966 TX Vref=24, minBit 9, minWin=27, winSum=443
1648 09:28:11.751237 TX Vref=26, minBit 10, minWin=27, winSum=447
1649 09:28:11.754869 TX Vref=28, minBit 13, minWin=27, winSum=453
1650 09:28:11.758080 TX Vref=30, minBit 2, minWin=28, winSum=455
1651 09:28:11.761055 TX Vref=32, minBit 0, minWin=28, winSum=453
1652 09:28:11.768273 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
1653 09:28:11.768447
1654 09:28:11.772017 Final TX Range 1 Vref 30
1655 09:28:11.772108
1656 09:28:11.772173 ==
1657 09:28:11.775836 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 09:28:11.778826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 09:28:11.778913 ==
1660 09:28:11.779008
1661 09:28:11.779108
1662 09:28:11.782788 TX Vref Scan disable
1663 09:28:11.785510 == TX Byte 0 ==
1664 09:28:11.788952 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 09:28:11.792415 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 09:28:11.795590 == TX Byte 1 ==
1667 09:28:11.799198 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1668 09:28:11.802867 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1669 09:28:11.802949
1670 09:28:11.803013 [DATLAT]
1671 09:28:11.806011 Freq=800, CH1 RK0
1672 09:28:11.806093
1673 09:28:11.809523 DATLAT Default: 0xa
1674 09:28:11.809604 0, 0xFFFF, sum = 0
1675 09:28:11.812669 1, 0xFFFF, sum = 0
1676 09:28:11.812752 2, 0xFFFF, sum = 0
1677 09:28:11.816314 3, 0xFFFF, sum = 0
1678 09:28:11.816396 4, 0xFFFF, sum = 0
1679 09:28:11.819069 5, 0xFFFF, sum = 0
1680 09:28:11.819152 6, 0xFFFF, sum = 0
1681 09:28:11.822894 7, 0xFFFF, sum = 0
1682 09:28:11.822976 8, 0xFFFF, sum = 0
1683 09:28:11.826256 9, 0x0, sum = 1
1684 09:28:11.826339 10, 0x0, sum = 2
1685 09:28:11.826404 11, 0x0, sum = 3
1686 09:28:11.829148 12, 0x0, sum = 4
1687 09:28:11.829261 best_step = 10
1688 09:28:11.829327
1689 09:28:11.832420 ==
1690 09:28:11.832497 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 09:28:11.839514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 09:28:11.839592 ==
1693 09:28:11.839672 RX Vref Scan: 1
1694 09:28:11.839731
1695 09:28:11.842853 Set Vref Range= 32 -> 127
1696 09:28:11.842929
1697 09:28:11.846180 RX Vref 32 -> 127, step: 1
1698 09:28:11.846254
1699 09:28:11.849415 RX Delay -111 -> 252, step: 8
1700 09:28:11.849491
1701 09:28:11.852979 Set Vref, RX VrefLevel [Byte0]: 32
1702 09:28:11.856026 [Byte1]: 32
1703 09:28:11.856100
1704 09:28:11.859399 Set Vref, RX VrefLevel [Byte0]: 33
1705 09:28:11.862966 [Byte1]: 33
1706 09:28:11.863052
1707 09:28:11.866171 Set Vref, RX VrefLevel [Byte0]: 34
1708 09:28:11.869565 [Byte1]: 34
1709 09:28:11.872872
1710 09:28:11.872954 Set Vref, RX VrefLevel [Byte0]: 35
1711 09:28:11.876161 [Byte1]: 35
1712 09:28:11.880203
1713 09:28:11.880284 Set Vref, RX VrefLevel [Byte0]: 36
1714 09:28:11.883526 [Byte1]: 36
1715 09:28:11.887829
1716 09:28:11.887915 Set Vref, RX VrefLevel [Byte0]: 37
1717 09:28:11.891309 [Byte1]: 37
1718 09:28:11.895720
1719 09:28:11.895798 Set Vref, RX VrefLevel [Byte0]: 38
1720 09:28:11.898826 [Byte1]: 38
1721 09:28:11.903177
1722 09:28:11.903260 Set Vref, RX VrefLevel [Byte0]: 39
1723 09:28:11.906416 [Byte1]: 39
1724 09:28:11.910736
1725 09:28:11.910829 Set Vref, RX VrefLevel [Byte0]: 40
1726 09:28:11.914167 [Byte1]: 40
1727 09:28:11.918619
1728 09:28:11.918695 Set Vref, RX VrefLevel [Byte0]: 41
1729 09:28:11.921884 [Byte1]: 41
1730 09:28:11.926399
1731 09:28:11.926476 Set Vref, RX VrefLevel [Byte0]: 42
1732 09:28:11.929576 [Byte1]: 42
1733 09:28:11.933786
1734 09:28:11.933870 Set Vref, RX VrefLevel [Byte0]: 43
1735 09:28:11.936909 [Byte1]: 43
1736 09:28:11.941361
1737 09:28:11.941434 Set Vref, RX VrefLevel [Byte0]: 44
1738 09:28:11.944773 [Byte1]: 44
1739 09:28:11.948971
1740 09:28:11.949086 Set Vref, RX VrefLevel [Byte0]: 45
1741 09:28:11.952790 [Byte1]: 45
1742 09:28:11.957113
1743 09:28:11.957189 Set Vref, RX VrefLevel [Byte0]: 46
1744 09:28:11.960344 [Byte1]: 46
1745 09:28:11.964431
1746 09:28:11.964509 Set Vref, RX VrefLevel [Byte0]: 47
1747 09:28:11.968193 [Byte1]: 47
1748 09:28:11.972143
1749 09:28:11.972228 Set Vref, RX VrefLevel [Byte0]: 48
1750 09:28:11.975415 [Byte1]: 48
1751 09:28:11.979713
1752 09:28:11.979795 Set Vref, RX VrefLevel [Byte0]: 49
1753 09:28:11.983185 [Byte1]: 49
1754 09:28:11.987382
1755 09:28:11.987463 Set Vref, RX VrefLevel [Byte0]: 50
1756 09:28:11.990538 [Byte1]: 50
1757 09:28:11.994764
1758 09:28:11.994846 Set Vref, RX VrefLevel [Byte0]: 51
1759 09:28:11.998735 [Byte1]: 51
1760 09:28:12.002829
1761 09:28:12.002911 Set Vref, RX VrefLevel [Byte0]: 52
1762 09:28:12.005981 [Byte1]: 52
1763 09:28:12.010652
1764 09:28:12.010742 Set Vref, RX VrefLevel [Byte0]: 53
1765 09:28:12.013823 [Byte1]: 53
1766 09:28:12.017713
1767 09:28:12.017795 Set Vref, RX VrefLevel [Byte0]: 54
1768 09:28:12.021546 [Byte1]: 54
1769 09:28:12.025473
1770 09:28:12.025555 Set Vref, RX VrefLevel [Byte0]: 55
1771 09:28:12.029108 [Byte1]: 55
1772 09:28:12.033010
1773 09:28:12.033094 Set Vref, RX VrefLevel [Byte0]: 56
1774 09:28:12.036872 [Byte1]: 56
1775 09:28:12.041205
1776 09:28:12.041288 Set Vref, RX VrefLevel [Byte0]: 57
1777 09:28:12.044103 [Byte1]: 57
1778 09:28:12.048425
1779 09:28:12.048506 Set Vref, RX VrefLevel [Byte0]: 58
1780 09:28:12.051890 [Byte1]: 58
1781 09:28:12.056288
1782 09:28:12.056370 Set Vref, RX VrefLevel [Byte0]: 59
1783 09:28:12.059823 [Byte1]: 59
1784 09:28:12.063499
1785 09:28:12.063581 Set Vref, RX VrefLevel [Byte0]: 60
1786 09:28:12.067100 [Byte1]: 60
1787 09:28:12.071776
1788 09:28:12.071860 Set Vref, RX VrefLevel [Byte0]: 61
1789 09:28:12.074612 [Byte1]: 61
1790 09:28:12.079447
1791 09:28:12.079532 Set Vref, RX VrefLevel [Byte0]: 62
1792 09:28:12.082163 [Byte1]: 62
1793 09:28:12.086877
1794 09:28:12.086959 Set Vref, RX VrefLevel [Byte0]: 63
1795 09:28:12.090022 [Byte1]: 63
1796 09:28:12.094289
1797 09:28:12.094371 Set Vref, RX VrefLevel [Byte0]: 64
1798 09:28:12.097652 [Byte1]: 64
1799 09:28:12.102009
1800 09:28:12.102091 Set Vref, RX VrefLevel [Byte0]: 65
1801 09:28:12.105342 [Byte1]: 65
1802 09:28:12.109675
1803 09:28:12.109757 Set Vref, RX VrefLevel [Byte0]: 66
1804 09:28:12.112829 [Byte1]: 66
1805 09:28:12.117191
1806 09:28:12.117268 Set Vref, RX VrefLevel [Byte0]: 67
1807 09:28:12.120513 [Byte1]: 67
1808 09:28:12.125340
1809 09:28:12.125418 Set Vref, RX VrefLevel [Byte0]: 68
1810 09:28:12.128545 [Byte1]: 68
1811 09:28:12.132414
1812 09:28:12.132539 Set Vref, RX VrefLevel [Byte0]: 69
1813 09:28:12.136128 [Byte1]: 69
1814 09:28:12.140332
1815 09:28:12.140434 Set Vref, RX VrefLevel [Byte0]: 70
1816 09:28:12.143796 [Byte1]: 70
1817 09:28:12.147664
1818 09:28:12.147738 Set Vref, RX VrefLevel [Byte0]: 71
1819 09:28:12.151234 [Byte1]: 71
1820 09:28:12.155601
1821 09:28:12.155708 Set Vref, RX VrefLevel [Byte0]: 72
1822 09:28:12.159006 [Byte1]: 72
1823 09:28:12.163154
1824 09:28:12.163229 Set Vref, RX VrefLevel [Byte0]: 73
1825 09:28:12.166391 [Byte1]: 73
1826 09:28:12.171008
1827 09:28:12.171092 Set Vref, RX VrefLevel [Byte0]: 74
1828 09:28:12.174335 [Byte1]: 74
1829 09:28:12.178677
1830 09:28:12.178803 Set Vref, RX VrefLevel [Byte0]: 75
1831 09:28:12.181990 [Byte1]: 75
1832 09:28:12.186325
1833 09:28:12.186452 Set Vref, RX VrefLevel [Byte0]: 76
1834 09:28:12.189234 [Byte1]: 76
1835 09:28:12.193888
1836 09:28:12.193968 Set Vref, RX VrefLevel [Byte0]: 77
1837 09:28:12.196907 [Byte1]: 77
1838 09:28:12.201696
1839 09:28:12.201794 Set Vref, RX VrefLevel [Byte0]: 78
1840 09:28:12.204618 [Byte1]: 78
1841 09:28:12.209237
1842 09:28:12.209313 Final RX Vref Byte 0 = 59 to rank0
1843 09:28:12.212592 Final RX Vref Byte 1 = 56 to rank0
1844 09:28:12.216139 Final RX Vref Byte 0 = 59 to rank1
1845 09:28:12.219377 Final RX Vref Byte 1 = 56 to rank1==
1846 09:28:12.222997 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 09:28:12.225666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 09:28:12.229112 ==
1849 09:28:12.229190 DQS Delay:
1850 09:28:12.229252 DQS0 = 0, DQS1 = 0
1851 09:28:12.232534 DQM Delay:
1852 09:28:12.232617 DQM0 = 84, DQM1 = 73
1853 09:28:12.236141 DQ Delay:
1854 09:28:12.236303 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1855 09:28:12.239586 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1856 09:28:12.242649 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1857 09:28:12.246293 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1858 09:28:12.246368
1859 09:28:12.249219
1860 09:28:12.255858 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1861 09:28:12.259545 CH1 RK0: MR19=605, MR18=27FC
1862 09:28:12.265865 CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61
1863 09:28:12.265951
1864 09:28:12.269610 ----->DramcWriteLeveling(PI) begin...
1865 09:28:12.269700 ==
1866 09:28:12.272770 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 09:28:12.276343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 09:28:12.276421 ==
1869 09:28:12.279595 Write leveling (Byte 0): 28 => 28
1870 09:28:12.282706 Write leveling (Byte 1): 28 => 28
1871 09:28:12.285971 DramcWriteLeveling(PI) end<-----
1872 09:28:12.286058
1873 09:28:12.286119 ==
1874 09:28:12.289477 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 09:28:12.292636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 09:28:12.292716 ==
1877 09:28:12.296272 [Gating] SW mode calibration
1878 09:28:12.302884 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 09:28:12.309787 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 09:28:12.312962 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1881 09:28:12.316285 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1882 09:28:12.319541 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1883 09:28:12.326181 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:28:12.330213 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:28:12.333295 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:28:12.339640 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:28:12.343245 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:28:12.346611 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 09:28:12.353335 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1890 09:28:12.356874 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 09:28:12.360632 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1892 09:28:12.366705 0 7 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1893 09:28:12.370306 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 09:28:12.373747 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1895 09:28:12.376691 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 09:28:12.383241 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1897 09:28:12.387007 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1898 09:28:12.390673 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 09:28:12.397264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 09:28:12.400413 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 09:28:12.403397 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:28:12.410293 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 09:28:12.413931 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 09:28:12.417272 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 09:28:12.423901 0 9 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
1906 09:28:12.427417 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1907 09:28:12.430596 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 09:28:12.433830 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 09:28:12.440645 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 09:28:12.444004 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 09:28:12.448034 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 09:28:12.454115 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1913 09:28:12.457532 0 10 4 | B1->B0 | 3030 2a2a | 0 1 | (0 0) (1 0)
1914 09:28:12.460966 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1915 09:28:12.467432 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 09:28:12.471431 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 09:28:12.474083 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 09:28:12.477877 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1919 09:28:12.484306 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1920 09:28:12.487914 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 09:28:12.491508 0 11 4 | B1->B0 | 2929 3c3c | 1 0 | (0 0) (0 0)
1922 09:28:12.497845 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1923 09:28:12.501344 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 09:28:12.504414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 09:28:12.511186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 09:28:12.515077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 09:28:12.517953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 09:28:12.524753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 09:28:12.528125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1930 09:28:12.531483 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 09:28:12.534647 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 09:28:12.541439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 09:28:12.545200 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 09:28:12.548228 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 09:28:12.554896 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 09:28:12.558295 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 09:28:12.562170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 09:28:12.568833 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 09:28:12.571615 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 09:28:12.574848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 09:28:12.581960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 09:28:12.585118 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 09:28:12.588501 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 09:28:12.591941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1945 09:28:12.598531 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1946 09:28:12.602274 Total UI for P1: 0, mck2ui 16
1947 09:28:12.605454 best dqsien dly found for B0: ( 0, 14, 0)
1948 09:28:12.608839 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 09:28:12.612004 Total UI for P1: 0, mck2ui 16
1950 09:28:12.615515 best dqsien dly found for B1: ( 0, 14, 4)
1951 09:28:12.618995 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1952 09:28:12.622036 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1953 09:28:12.622127
1954 09:28:12.626208 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1955 09:28:12.628936 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 09:28:12.632146 [Gating] SW calibration Done
1957 09:28:12.632233 ==
1958 09:28:12.635658 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 09:28:12.638871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 09:28:12.642154 ==
1961 09:28:12.642237 RX Vref Scan: 0
1962 09:28:12.642309
1963 09:28:12.645683 RX Vref 0 -> 0, step: 1
1964 09:28:12.645757
1965 09:28:12.648941 RX Delay -130 -> 252, step: 16
1966 09:28:12.652611 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1967 09:28:12.655880 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1968 09:28:12.658686 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1969 09:28:12.662582 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1970 09:28:12.665462 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1971 09:28:12.672713 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1972 09:28:12.675772 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1973 09:28:12.679374 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1974 09:28:12.682563 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1975 09:28:12.685912 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1976 09:28:12.692667 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1977 09:28:12.695984 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1978 09:28:12.699617 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1979 09:28:12.702568 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1980 09:28:12.706276 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1981 09:28:12.713061 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1982 09:28:12.713170 ==
1983 09:28:12.716199 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 09:28:12.719289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 09:28:12.719379 ==
1986 09:28:12.719446 DQS Delay:
1987 09:28:12.722566 DQS0 = 0, DQS1 = 0
1988 09:28:12.722651 DQM Delay:
1989 09:28:12.726378 DQM0 = 82, DQM1 = 78
1990 09:28:12.726464 DQ Delay:
1991 09:28:12.729354 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1992 09:28:12.732837 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1993 09:28:12.735963 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1994 09:28:12.739527 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1995 09:28:12.739613
1996 09:28:12.739677
1997 09:28:12.739746 ==
1998 09:28:12.742808 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 09:28:12.745875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 09:28:12.745980 ==
2001 09:28:12.746078
2002 09:28:12.746166
2003 09:28:12.749477 TX Vref Scan disable
2004 09:28:12.752507 == TX Byte 0 ==
2005 09:28:12.756047 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 09:28:12.759379 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 09:28:12.762744 == TX Byte 1 ==
2008 09:28:12.766493 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2009 09:28:12.769520 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2010 09:28:12.769648 ==
2011 09:28:12.772912 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 09:28:12.776556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 09:28:12.779319 ==
2014 09:28:12.790953 TX Vref=22, minBit 11, minWin=26, winSum=436
2015 09:28:12.794395 TX Vref=24, minBit 3, minWin=27, winSum=444
2016 09:28:12.797498 TX Vref=26, minBit 10, minWin=27, winSum=447
2017 09:28:12.800621 TX Vref=28, minBit 10, minWin=27, winSum=446
2018 09:28:12.804115 TX Vref=30, minBit 8, minWin=27, winSum=451
2019 09:28:12.810484 TX Vref=32, minBit 15, minWin=27, winSum=450
2020 09:28:12.814048 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 30
2021 09:28:12.814156
2022 09:28:12.817282 Final TX Range 1 Vref 30
2023 09:28:12.817391
2024 09:28:12.817481 ==
2025 09:28:12.820621 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 09:28:12.824284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 09:28:12.824377 ==
2028 09:28:12.827832
2029 09:28:12.827936
2030 09:28:12.828022 TX Vref Scan disable
2031 09:28:12.831140 == TX Byte 0 ==
2032 09:28:12.834149 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2033 09:28:12.837427 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2034 09:28:12.841120 == TX Byte 1 ==
2035 09:28:12.844236 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2036 09:28:12.850831 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2037 09:28:12.850936
2038 09:28:12.851001 [DATLAT]
2039 09:28:12.851060 Freq=800, CH1 RK1
2040 09:28:12.851123
2041 09:28:12.854405 DATLAT Default: 0xa
2042 09:28:12.854488 0, 0xFFFF, sum = 0
2043 09:28:12.857361 1, 0xFFFF, sum = 0
2044 09:28:12.857478 2, 0xFFFF, sum = 0
2045 09:28:12.860680 3, 0xFFFF, sum = 0
2046 09:28:12.860810 4, 0xFFFF, sum = 0
2047 09:28:12.864615 5, 0xFFFF, sum = 0
2048 09:28:12.864711 6, 0xFFFF, sum = 0
2049 09:28:12.867470 7, 0xFFFF, sum = 0
2050 09:28:12.867554 8, 0xFFFF, sum = 0
2051 09:28:12.871124 9, 0x0, sum = 1
2052 09:28:12.871233 10, 0x0, sum = 2
2053 09:28:12.874686 11, 0x0, sum = 3
2054 09:28:12.874820 12, 0x0, sum = 4
2055 09:28:12.877672 best_step = 10
2056 09:28:12.877782
2057 09:28:12.877875 ==
2058 09:28:12.881159 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 09:28:12.884518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 09:28:12.884600 ==
2061 09:28:12.888288 RX Vref Scan: 0
2062 09:28:12.888363
2063 09:28:12.888431 RX Vref 0 -> 0, step: 1
2064 09:28:12.888489
2065 09:28:12.891440 RX Delay -111 -> 252, step: 8
2066 09:28:12.897736 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2067 09:28:12.901283 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2068 09:28:12.904735 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2069 09:28:12.907977 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2070 09:28:12.911504 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2071 09:28:12.914742 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2072 09:28:12.921478 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2073 09:28:12.924864 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2074 09:28:12.928269 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2075 09:28:12.931531 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2076 09:28:12.934706 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2077 09:28:12.941980 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2078 09:28:12.945518 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2079 09:28:12.948680 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2080 09:28:12.951962 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2081 09:28:12.954950 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2082 09:28:12.958795 ==
2083 09:28:12.958880 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 09:28:12.965092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 09:28:12.965219 ==
2086 09:28:12.965320 DQS Delay:
2087 09:28:12.968500 DQS0 = 0, DQS1 = 0
2088 09:28:12.968579 DQM Delay:
2089 09:28:12.971732 DQM0 = 81, DQM1 = 75
2090 09:28:12.971818 DQ Delay:
2091 09:28:12.975175 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2092 09:28:12.978360 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2093 09:28:12.981964 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2094 09:28:12.985499 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2095 09:28:12.985588
2096 09:28:12.985654
2097 09:28:12.992087 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2098 09:28:12.995321 CH1 RK1: MR19=606, MR18=232E
2099 09:28:13.002200 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2100 09:28:13.005605 [RxdqsGatingPostProcess] freq 800
2101 09:28:13.008784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 09:28:13.012334 Pre-setting of DQS Precalculation
2103 09:28:13.019361 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 09:28:13.025926 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 09:28:13.032787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 09:28:13.032942
2107 09:28:13.033045
2108 09:28:13.036087 [Calibration Summary] 1600 Mbps
2109 09:28:13.036171 CH 0, Rank 0
2110 09:28:13.039604 SW Impedance : PASS
2111 09:28:13.039704 DUTY Scan : NO K
2112 09:28:13.042811 ZQ Calibration : PASS
2113 09:28:13.046046 Jitter Meter : NO K
2114 09:28:13.046136 CBT Training : PASS
2115 09:28:13.049374 Write leveling : PASS
2116 09:28:13.052463 RX DQS gating : PASS
2117 09:28:13.052550 RX DQ/DQS(RDDQC) : PASS
2118 09:28:13.055904 TX DQ/DQS : PASS
2119 09:28:13.059237 RX DATLAT : PASS
2120 09:28:13.059321 RX DQ/DQS(Engine): PASS
2121 09:28:13.062944 TX OE : NO K
2122 09:28:13.063028 All Pass.
2123 09:28:13.063092
2124 09:28:13.066191 CH 0, Rank 1
2125 09:28:13.066273 SW Impedance : PASS
2126 09:28:13.069708 DUTY Scan : NO K
2127 09:28:13.072762 ZQ Calibration : PASS
2128 09:28:13.072850 Jitter Meter : NO K
2129 09:28:13.076541 CBT Training : PASS
2130 09:28:13.076624 Write leveling : PASS
2131 09:28:13.079693 RX DQS gating : PASS
2132 09:28:13.082709 RX DQ/DQS(RDDQC) : PASS
2133 09:28:13.082802 TX DQ/DQS : PASS
2134 09:28:13.085885 RX DATLAT : PASS
2135 09:28:13.089837 RX DQ/DQS(Engine): PASS
2136 09:28:13.089921 TX OE : NO K
2137 09:28:13.092947 All Pass.
2138 09:28:13.093029
2139 09:28:13.093127 CH 1, Rank 0
2140 09:28:13.096130 SW Impedance : PASS
2141 09:28:13.096211 DUTY Scan : NO K
2142 09:28:13.099559 ZQ Calibration : PASS
2143 09:28:13.102913 Jitter Meter : NO K
2144 09:28:13.102994 CBT Training : PASS
2145 09:28:13.106152 Write leveling : PASS
2146 09:28:13.109577 RX DQS gating : PASS
2147 09:28:13.109650 RX DQ/DQS(RDDQC) : PASS
2148 09:28:13.113246 TX DQ/DQS : PASS
2149 09:28:13.113316 RX DATLAT : PASS
2150 09:28:13.116362 RX DQ/DQS(Engine): PASS
2151 09:28:13.119601 TX OE : NO K
2152 09:28:13.119682 All Pass.
2153 09:28:13.119743
2154 09:28:13.119809 CH 1, Rank 1
2155 09:28:13.122897 SW Impedance : PASS
2156 09:28:13.126499 DUTY Scan : NO K
2157 09:28:13.126609 ZQ Calibration : PASS
2158 09:28:13.129892 Jitter Meter : NO K
2159 09:28:13.132854 CBT Training : PASS
2160 09:28:13.132933 Write leveling : PASS
2161 09:28:13.136591 RX DQS gating : PASS
2162 09:28:13.140306 RX DQ/DQS(RDDQC) : PASS
2163 09:28:13.140384 TX DQ/DQS : PASS
2164 09:28:13.143168 RX DATLAT : PASS
2165 09:28:13.143245 RX DQ/DQS(Engine): PASS
2166 09:28:13.146406 TX OE : NO K
2167 09:28:13.146475 All Pass.
2168 09:28:13.146535
2169 09:28:13.150167 DramC Write-DBI off
2170 09:28:13.153738 PER_BANK_REFRESH: Hybrid Mode
2171 09:28:13.153848 TX_TRACKING: ON
2172 09:28:13.156995 [GetDramInforAfterCalByMRR] Vendor 6.
2173 09:28:13.160179 [GetDramInforAfterCalByMRR] Revision 606.
2174 09:28:13.163336 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 09:28:13.166812 MR0 0x3b3b
2176 09:28:13.166887 MR8 0x5151
2177 09:28:13.170686 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 09:28:13.170784
2179 09:28:13.170852 MR0 0x3b3b
2180 09:28:13.173513 MR8 0x5151
2181 09:28:13.176818 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 09:28:13.176902
2183 09:28:13.187209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 09:28:13.190320 [FAST_K] Save calibration result to emmc
2185 09:28:13.193633 [FAST_K] Save calibration result to emmc
2186 09:28:13.193719 dram_init: config_dvfs: 1
2187 09:28:13.200592 dramc_set_vcore_voltage set vcore to 662500
2188 09:28:13.200689 Read voltage for 1200, 2
2189 09:28:13.203766 Vio18 = 0
2190 09:28:13.203851 Vcore = 662500
2191 09:28:13.203917 Vdram = 0
2192 09:28:13.203977 Vddq = 0
2193 09:28:13.207133 Vmddr = 0
2194 09:28:13.210743 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 09:28:13.217697 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 09:28:13.217786 MEM_TYPE=3, freq_sel=15
2197 09:28:13.220936 sv_algorithm_assistance_LP4_1600
2198 09:28:13.227632 ============ PULL DRAM RESETB DOWN ============
2199 09:28:13.230699 ========== PULL DRAM RESETB DOWN end =========
2200 09:28:13.234076 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 09:28:13.237721 ===================================
2202 09:28:13.241035 LPDDR4 DRAM CONFIGURATION
2203 09:28:13.244059 ===================================
2204 09:28:13.244147 EX_ROW_EN[0] = 0x0
2205 09:28:13.247665 EX_ROW_EN[1] = 0x0
2206 09:28:13.251470 LP4Y_EN = 0x0
2207 09:28:13.251568 WORK_FSP = 0x0
2208 09:28:13.254157 WL = 0x4
2209 09:28:13.254241 RL = 0x4
2210 09:28:13.257593 BL = 0x2
2211 09:28:13.257694 RPST = 0x0
2212 09:28:13.261209 RD_PRE = 0x0
2213 09:28:13.261292 WR_PRE = 0x1
2214 09:28:13.264248 WR_PST = 0x0
2215 09:28:13.264334 DBI_WR = 0x0
2216 09:28:13.268287 DBI_RD = 0x0
2217 09:28:13.268375 OTF = 0x1
2218 09:28:13.270946 ===================================
2219 09:28:13.274832 ===================================
2220 09:28:13.277751 ANA top config
2221 09:28:13.281051 ===================================
2222 09:28:13.281158 DLL_ASYNC_EN = 0
2223 09:28:13.284314 ALL_SLAVE_EN = 0
2224 09:28:13.287909 NEW_RANK_MODE = 1
2225 09:28:13.291171 DLL_IDLE_MODE = 1
2226 09:28:13.291268 LP45_APHY_COMB_EN = 1
2227 09:28:13.294484 TX_ODT_DIS = 1
2228 09:28:13.297943 NEW_8X_MODE = 1
2229 09:28:13.301379 ===================================
2230 09:28:13.304611 ===================================
2231 09:28:13.308175 data_rate = 2400
2232 09:28:13.311643 CKR = 1
2233 09:28:13.311791 DQ_P2S_RATIO = 8
2234 09:28:13.315003 ===================================
2235 09:28:13.318305 CA_P2S_RATIO = 8
2236 09:28:13.321451 DQ_CA_OPEN = 0
2237 09:28:13.324973 DQ_SEMI_OPEN = 0
2238 09:28:13.328031 CA_SEMI_OPEN = 0
2239 09:28:13.328140 CA_FULL_RATE = 0
2240 09:28:13.331509 DQ_CKDIV4_EN = 0
2241 09:28:13.334734 CA_CKDIV4_EN = 0
2242 09:28:13.338132 CA_PREDIV_EN = 0
2243 09:28:13.341767 PH8_DLY = 17
2244 09:28:13.345177 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 09:28:13.345270 DQ_AAMCK_DIV = 4
2246 09:28:13.348327 CA_AAMCK_DIV = 4
2247 09:28:13.351729 CA_ADMCK_DIV = 4
2248 09:28:13.355172 DQ_TRACK_CA_EN = 0
2249 09:28:13.358148 CA_PICK = 1200
2250 09:28:13.361876 CA_MCKIO = 1200
2251 09:28:13.365023 MCKIO_SEMI = 0
2252 09:28:13.365103 PLL_FREQ = 2366
2253 09:28:13.368744 DQ_UI_PI_RATIO = 32
2254 09:28:13.372348 CA_UI_PI_RATIO = 0
2255 09:28:13.375334 ===================================
2256 09:28:13.378935 ===================================
2257 09:28:13.382122 memory_type:LPDDR4
2258 09:28:13.382219 GP_NUM : 10
2259 09:28:13.385454 SRAM_EN : 1
2260 09:28:13.388915 MD32_EN : 0
2261 09:28:13.392007 ===================================
2262 09:28:13.392099 [ANA_INIT] >>>>>>>>>>>>>>
2263 09:28:13.395175 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 09:28:13.398859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 09:28:13.402330 ===================================
2266 09:28:13.405691 data_rate = 2400,PCW = 0X5b00
2267 09:28:13.408739 ===================================
2268 09:28:13.411949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 09:28:13.418856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 09:28:13.422248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 09:28:13.429088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 09:28:13.432472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 09:28:13.435696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 09:28:13.435807 [ANA_INIT] flow start
2275 09:28:13.439202 [ANA_INIT] PLL >>>>>>>>
2276 09:28:13.442789 [ANA_INIT] PLL <<<<<<<<
2277 09:28:13.442886 [ANA_INIT] MIDPI >>>>>>>>
2278 09:28:13.446073 [ANA_INIT] MIDPI <<<<<<<<
2279 09:28:13.449385 [ANA_INIT] DLL >>>>>>>>
2280 09:28:13.449474 [ANA_INIT] DLL <<<<<<<<
2281 09:28:13.452412 [ANA_INIT] flow end
2282 09:28:13.456063 ============ LP4 DIFF to SE enter ============
2283 09:28:13.459130 ============ LP4 DIFF to SE exit ============
2284 09:28:13.462673 [ANA_INIT] <<<<<<<<<<<<<
2285 09:28:13.466263 [Flow] Enable top DCM control >>>>>
2286 09:28:13.469332 [Flow] Enable top DCM control <<<<<
2287 09:28:13.472940 Enable DLL master slave shuffle
2288 09:28:13.479374 ==============================================================
2289 09:28:13.479508 Gating Mode config
2290 09:28:13.486187 ==============================================================
2291 09:28:13.486291 Config description:
2292 09:28:13.496343 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 09:28:13.503343 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 09:28:13.506401 SELPH_MODE 0: By rank 1: By Phase
2295 09:28:13.513456 ==============================================================
2296 09:28:13.516374 GAT_TRACK_EN = 1
2297 09:28:13.519864 RX_GATING_MODE = 2
2298 09:28:13.523318 RX_GATING_TRACK_MODE = 2
2299 09:28:13.526487 SELPH_MODE = 1
2300 09:28:13.530013 PICG_EARLY_EN = 1
2301 09:28:13.533633 VALID_LAT_VALUE = 1
2302 09:28:13.536555 ==============================================================
2303 09:28:13.539830 Enter into Gating configuration >>>>
2304 09:28:13.544086 Exit from Gating configuration <<<<
2305 09:28:13.546820 Enter into DVFS_PRE_config >>>>>
2306 09:28:13.557072 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 09:28:13.560273 Exit from DVFS_PRE_config <<<<<
2308 09:28:13.563460 Enter into PICG configuration >>>>
2309 09:28:13.567352 Exit from PICG configuration <<<<
2310 09:28:13.570628 [RX_INPUT] configuration >>>>>
2311 09:28:13.573928 [RX_INPUT] configuration <<<<<
2312 09:28:13.577160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 09:28:13.583621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 09:28:13.590732 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 09:28:13.597460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 09:28:13.600722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 09:28:13.607767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 09:28:13.610447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 09:28:13.617256 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 09:28:13.620535 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 09:28:13.624093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 09:28:13.627382 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 09:28:13.634402 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 09:28:13.637458 ===================================
2325 09:28:13.637547 LPDDR4 DRAM CONFIGURATION
2326 09:28:13.641101 ===================================
2327 09:28:13.644017 EX_ROW_EN[0] = 0x0
2328 09:28:13.647825 EX_ROW_EN[1] = 0x0
2329 09:28:13.647899 LP4Y_EN = 0x0
2330 09:28:13.651509 WORK_FSP = 0x0
2331 09:28:13.651584 WL = 0x4
2332 09:28:13.654416 RL = 0x4
2333 09:28:13.654512 BL = 0x2
2334 09:28:13.657447 RPST = 0x0
2335 09:28:13.657528 RD_PRE = 0x0
2336 09:28:13.660870 WR_PRE = 0x1
2337 09:28:13.660951 WR_PST = 0x0
2338 09:28:13.664310 DBI_WR = 0x0
2339 09:28:13.664383 DBI_RD = 0x0
2340 09:28:13.667779 OTF = 0x1
2341 09:28:13.671217 ===================================
2342 09:28:13.674361 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 09:28:13.677627 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 09:28:13.681458 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 09:28:13.684533 ===================================
2346 09:28:13.688157 LPDDR4 DRAM CONFIGURATION
2347 09:28:13.691780 ===================================
2348 09:28:13.694480 EX_ROW_EN[0] = 0x10
2349 09:28:13.694557 EX_ROW_EN[1] = 0x0
2350 09:28:13.698394 LP4Y_EN = 0x0
2351 09:28:13.698471 WORK_FSP = 0x0
2352 09:28:13.701256 WL = 0x4
2353 09:28:13.701341 RL = 0x4
2354 09:28:13.704982 BL = 0x2
2355 09:28:13.705056 RPST = 0x0
2356 09:28:13.707984 RD_PRE = 0x0
2357 09:28:13.708056 WR_PRE = 0x1
2358 09:28:13.711537 WR_PST = 0x0
2359 09:28:13.711613 DBI_WR = 0x0
2360 09:28:13.715248 DBI_RD = 0x0
2361 09:28:13.715328 OTF = 0x1
2362 09:28:13.718357 ===================================
2363 09:28:13.724488 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 09:28:13.724572 ==
2365 09:28:13.727884 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 09:28:13.735029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 09:28:13.735125 ==
2368 09:28:13.735190 [Duty_Offset_Calibration]
2369 09:28:13.738400 B0:2 B1:-1 CA:1
2370 09:28:13.738501
2371 09:28:13.741389 [DutyScan_Calibration_Flow] k_type=0
2372 09:28:13.749645
2373 09:28:13.749799 ==CLK 0==
2374 09:28:13.752786 Final CLK duty delay cell = -4
2375 09:28:13.756156 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2376 09:28:13.759973 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2377 09:28:13.763091 [-4] AVG Duty = 4953%(X100)
2378 09:28:13.763175
2379 09:28:13.766697 CH0 CLK Duty spec in!! Max-Min= 156%
2380 09:28:13.769654 [DutyScan_Calibration_Flow] ====Done====
2381 09:28:13.769735
2382 09:28:13.772859 [DutyScan_Calibration_Flow] k_type=1
2383 09:28:13.788358
2384 09:28:13.788478 ==DQS 0 ==
2385 09:28:13.791561 Final DQS duty delay cell = 0
2386 09:28:13.795044 [0] MAX Duty = 5125%(X100), DQS PI = 46
2387 09:28:13.798600 [0] MIN Duty = 5000%(X100), DQS PI = 12
2388 09:28:13.798699 [0] AVG Duty = 5062%(X100)
2389 09:28:13.801907
2390 09:28:13.801985 ==DQS 1 ==
2391 09:28:13.805061 Final DQS duty delay cell = -4
2392 09:28:13.808604 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2393 09:28:13.812235 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2394 09:28:13.815364 [-4] AVG Duty = 5062%(X100)
2395 09:28:13.815438
2396 09:28:13.818739 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2397 09:28:13.818840
2398 09:28:13.822063 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2399 09:28:13.825358 [DutyScan_Calibration_Flow] ====Done====
2400 09:28:13.825449
2401 09:28:13.828379 [DutyScan_Calibration_Flow] k_type=3
2402 09:28:13.845401
2403 09:28:13.845492 ==DQM 0 ==
2404 09:28:13.848872 Final DQM duty delay cell = 0
2405 09:28:13.852246 [0] MAX Duty = 5000%(X100), DQS PI = 54
2406 09:28:13.855823 [0] MIN Duty = 4907%(X100), DQS PI = 2
2407 09:28:13.855901 [0] AVG Duty = 4953%(X100)
2408 09:28:13.855966
2409 09:28:13.858698 ==DQM 1 ==
2410 09:28:13.862420 Final DQM duty delay cell = 0
2411 09:28:13.865478 [0] MAX Duty = 5124%(X100), DQS PI = 32
2412 09:28:13.869084 [0] MIN Duty = 4969%(X100), DQS PI = 10
2413 09:28:13.869160 [0] AVG Duty = 5046%(X100)
2414 09:28:13.869227
2415 09:28:13.872380 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2416 09:28:13.875729
2417 09:28:13.879012 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2418 09:28:13.882573 [DutyScan_Calibration_Flow] ====Done====
2419 09:28:13.882650
2420 09:28:13.885547 [DutyScan_Calibration_Flow] k_type=2
2421 09:28:13.900831
2422 09:28:13.900922 ==DQ 0 ==
2423 09:28:13.904794 Final DQ duty delay cell = -4
2424 09:28:13.907656 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2425 09:28:13.911286 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2426 09:28:13.914593 [-4] AVG Duty = 4984%(X100)
2427 09:28:13.914666
2428 09:28:13.914742 ==DQ 1 ==
2429 09:28:13.917798 Final DQ duty delay cell = 0
2430 09:28:13.921319 [0] MAX Duty = 5031%(X100), DQS PI = 16
2431 09:28:13.924499 [0] MIN Duty = 4907%(X100), DQS PI = 46
2432 09:28:13.924573 [0] AVG Duty = 4969%(X100)
2433 09:28:13.927927
2434 09:28:13.931154 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2435 09:28:13.931228
2436 09:28:13.934796 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2437 09:28:13.937757 [DutyScan_Calibration_Flow] ====Done====
2438 09:28:13.937826 ==
2439 09:28:13.941105 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 09:28:13.944347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 09:28:13.944417 ==
2442 09:28:13.948009 [Duty_Offset_Calibration]
2443 09:28:13.948079 B0:1 B1:1 CA:2
2444 09:28:13.948139
2445 09:28:13.951213 [DutyScan_Calibration_Flow] k_type=0
2446 09:28:13.961420
2447 09:28:13.961507 ==CLK 0==
2448 09:28:13.964474 Final CLK duty delay cell = 0
2449 09:28:13.967819 [0] MAX Duty = 5187%(X100), DQS PI = 24
2450 09:28:13.971378 [0] MIN Duty = 4969%(X100), DQS PI = 38
2451 09:28:13.971452 [0] AVG Duty = 5078%(X100)
2452 09:28:13.975110
2453 09:28:13.975205 CH1 CLK Duty spec in!! Max-Min= 218%
2454 09:28:13.981554 [DutyScan_Calibration_Flow] ====Done====
2455 09:28:13.981640
2456 09:28:13.984736 [DutyScan_Calibration_Flow] k_type=1
2457 09:28:14.000526
2458 09:28:14.000618 ==DQS 0 ==
2459 09:28:14.004119 Final DQS duty delay cell = 0
2460 09:28:14.007286 [0] MAX Duty = 5031%(X100), DQS PI = 18
2461 09:28:14.010576 [0] MIN Duty = 4813%(X100), DQS PI = 50
2462 09:28:14.013976 [0] AVG Duty = 4922%(X100)
2463 09:28:14.014060
2464 09:28:14.014124 ==DQS 1 ==
2465 09:28:14.017669 Final DQS duty delay cell = 0
2466 09:28:14.020981 [0] MAX Duty = 5062%(X100), DQS PI = 36
2467 09:28:14.023993 [0] MIN Duty = 4907%(X100), DQS PI = 8
2468 09:28:14.024080 [0] AVG Duty = 4984%(X100)
2469 09:28:14.027512
2470 09:28:14.030654 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2471 09:28:14.030759
2472 09:28:14.034190 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2473 09:28:14.037723 [DutyScan_Calibration_Flow] ====Done====
2474 09:28:14.037813
2475 09:28:14.040439 [DutyScan_Calibration_Flow] k_type=3
2476 09:28:14.057083
2477 09:28:14.057228 ==DQM 0 ==
2478 09:28:14.060607 Final DQM duty delay cell = 0
2479 09:28:14.063764 [0] MAX Duty = 5093%(X100), DQS PI = 18
2480 09:28:14.067619 [0] MIN Duty = 4875%(X100), DQS PI = 48
2481 09:28:14.067710 [0] AVG Duty = 4984%(X100)
2482 09:28:14.070929
2483 09:28:14.071017 ==DQM 1 ==
2484 09:28:14.073966 Final DQM duty delay cell = 0
2485 09:28:14.077308 [0] MAX Duty = 5125%(X100), DQS PI = 0
2486 09:28:14.080856 [0] MIN Duty = 4969%(X100), DQS PI = 4
2487 09:28:14.080955 [0] AVG Duty = 5047%(X100)
2488 09:28:14.081023
2489 09:28:14.083975 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2490 09:28:14.087339
2491 09:28:14.090681 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2492 09:28:14.094521 [DutyScan_Calibration_Flow] ====Done====
2493 09:28:14.094662
2494 09:28:14.097776 [DutyScan_Calibration_Flow] k_type=2
2495 09:28:14.113631
2496 09:28:14.113778 ==DQ 0 ==
2497 09:28:14.117111 Final DQ duty delay cell = 0
2498 09:28:14.120866 [0] MAX Duty = 5156%(X100), DQS PI = 18
2499 09:28:14.123473 [0] MIN Duty = 4938%(X100), DQS PI = 50
2500 09:28:14.123564 [0] AVG Duty = 5047%(X100)
2501 09:28:14.126986
2502 09:28:14.127072 ==DQ 1 ==
2503 09:28:14.130538 Final DQ duty delay cell = 0
2504 09:28:14.133972 [0] MAX Duty = 5124%(X100), DQS PI = 58
2505 09:28:14.137307 [0] MIN Duty = 5000%(X100), DQS PI = 50
2506 09:28:14.137396 [0] AVG Duty = 5062%(X100)
2507 09:28:14.137462
2508 09:28:14.140634 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2509 09:28:14.140733
2510 09:28:14.143630 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2511 09:28:14.150496 [DutyScan_Calibration_Flow] ====Done====
2512 09:28:14.153971 nWR fixed to 30
2513 09:28:14.154071 [ModeRegInit_LP4] CH0 RK0
2514 09:28:14.157159 [ModeRegInit_LP4] CH0 RK1
2515 09:28:14.160358 [ModeRegInit_LP4] CH1 RK0
2516 09:28:14.160445 [ModeRegInit_LP4] CH1 RK1
2517 09:28:14.164118 match AC timing 7
2518 09:28:14.167326 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 09:28:14.170564 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 09:28:14.177352 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 09:28:14.180639 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 09:28:14.187116 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 09:28:14.187245 ==
2524 09:28:14.190673 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 09:28:14.193715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 09:28:14.193800 ==
2527 09:28:14.200606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 09:28:14.203933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 09:28:14.213440 [CA 0] Center 40 (10~71) winsize 62
2530 09:28:14.216721 [CA 1] Center 39 (9~70) winsize 62
2531 09:28:14.220272 [CA 2] Center 36 (6~67) winsize 62
2532 09:28:14.224072 [CA 3] Center 35 (5~66) winsize 62
2533 09:28:14.227225 [CA 4] Center 35 (5~65) winsize 61
2534 09:28:14.230582 [CA 5] Center 34 (4~65) winsize 62
2535 09:28:14.230682
2536 09:28:14.233662 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2537 09:28:14.233747
2538 09:28:14.237209 [CATrainingPosCal] consider 1 rank data
2539 09:28:14.240967 u2DelayCellTimex100 = 270/100 ps
2540 09:28:14.244036 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2541 09:28:14.247549 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2542 09:28:14.254054 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2543 09:28:14.257304 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2544 09:28:14.260950 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2545 09:28:14.264306 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2546 09:28:14.264389
2547 09:28:14.267311 CA PerBit enable=1, Macro0, CA PI delay=34
2548 09:28:14.267393
2549 09:28:14.270481 [CBTSetCACLKResult] CA Dly = 34
2550 09:28:14.270563 CS Dly: 7 (0~38)
2551 09:28:14.270629 ==
2552 09:28:14.274217 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 09:28:14.281078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 09:28:14.281170 ==
2555 09:28:14.284213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 09:28:14.291019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2557 09:28:14.299964 [CA 0] Center 39 (9~70) winsize 62
2558 09:28:14.303455 [CA 1] Center 40 (10~70) winsize 61
2559 09:28:14.306330 [CA 2] Center 36 (6~67) winsize 62
2560 09:28:14.309732 [CA 3] Center 36 (5~67) winsize 63
2561 09:28:14.313134 [CA 4] Center 34 (4~65) winsize 62
2562 09:28:14.316573 [CA 5] Center 34 (4~64) winsize 61
2563 09:28:14.316676
2564 09:28:14.319712 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2565 09:28:14.319795
2566 09:28:14.323102 [CATrainingPosCal] consider 2 rank data
2567 09:28:14.326529 u2DelayCellTimex100 = 270/100 ps
2568 09:28:14.330152 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2569 09:28:14.333115 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2570 09:28:14.336616 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2571 09:28:14.343232 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2572 09:28:14.347190 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2573 09:28:14.350530 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2574 09:28:14.350616
2575 09:28:14.353388 CA PerBit enable=1, Macro0, CA PI delay=34
2576 09:28:14.353472
2577 09:28:14.356522 [CBTSetCACLKResult] CA Dly = 34
2578 09:28:14.356605 CS Dly: 8 (0~41)
2579 09:28:14.356669
2580 09:28:14.360065 ----->DramcWriteLeveling(PI) begin...
2581 09:28:14.360150 ==
2582 09:28:14.363391 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 09:28:14.370440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 09:28:14.370536 ==
2585 09:28:14.373500 Write leveling (Byte 0): 30 => 30
2586 09:28:14.377019 Write leveling (Byte 1): 28 => 28
2587 09:28:14.377124 DramcWriteLeveling(PI) end<-----
2588 09:28:14.377206
2589 09:28:14.380176 ==
2590 09:28:14.383650 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 09:28:14.386899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 09:28:14.386985 ==
2593 09:28:14.390529 [Gating] SW mode calibration
2594 09:28:14.397205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 09:28:14.400607 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 09:28:14.406911 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 09:28:14.410571 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2598 09:28:14.413899 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2599 09:28:14.420735 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 09:28:14.423907 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 09:28:14.426971 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 09:28:14.430896 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 09:28:14.437621 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 09:28:14.440727 1 0 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
2605 09:28:14.444069 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
2606 09:28:14.451047 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 09:28:14.454625 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 09:28:14.458003 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 09:28:14.464482 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 09:28:14.467631 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 09:28:14.471398 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 09:28:14.474598 1 1 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2613 09:28:14.480993 1 1 4 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
2614 09:28:14.484863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 09:28:14.487815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 09:28:14.494804 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 09:28:14.498164 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 09:28:14.501727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 09:28:14.507984 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 09:28:14.511341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2621 09:28:14.515230 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 09:28:14.521336 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 09:28:14.525060 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 09:28:14.528481 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 09:28:14.531716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 09:28:14.538507 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 09:28:14.541578 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 09:28:14.545014 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 09:28:14.552003 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 09:28:14.555018 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 09:28:14.558374 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 09:28:14.565437 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 09:28:14.568627 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 09:28:14.572151 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 09:28:14.578966 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 09:28:14.582110 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2637 09:28:14.585851 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 09:28:14.588631 Total UI for P1: 0, mck2ui 16
2639 09:28:14.592152 best dqsien dly found for B0: ( 1, 4, 0)
2640 09:28:14.595530 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 09:28:14.599325 Total UI for P1: 0, mck2ui 16
2642 09:28:14.602203 best dqsien dly found for B1: ( 1, 4, 2)
2643 09:28:14.606332 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2644 09:28:14.608899 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2645 09:28:14.608987
2646 09:28:14.612372 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2647 09:28:14.619319 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2648 09:28:14.619453 [Gating] SW calibration Done
2649 09:28:14.619524 ==
2650 09:28:14.623165 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 09:28:14.629377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 09:28:14.629492 ==
2653 09:28:14.629561 RX Vref Scan: 0
2654 09:28:14.629622
2655 09:28:14.632460 RX Vref 0 -> 0, step: 1
2656 09:28:14.632535
2657 09:28:14.636230 RX Delay -40 -> 252, step: 8
2658 09:28:14.639004 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2659 09:28:14.642647 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2660 09:28:14.646006 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2661 09:28:14.649272 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2662 09:28:14.656341 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2663 09:28:14.659377 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2664 09:28:14.662636 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2665 09:28:14.666509 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2666 09:28:14.669980 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2667 09:28:14.672796 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2668 09:28:14.679820 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2669 09:28:14.683032 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2670 09:28:14.686761 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2671 09:28:14.689940 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2672 09:28:14.693118 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2673 09:28:14.699820 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2674 09:28:14.699941 ==
2675 09:28:14.702621 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 09:28:14.705994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 09:28:14.706088 ==
2678 09:28:14.706156 DQS Delay:
2679 09:28:14.709526 DQS0 = 0, DQS1 = 0
2680 09:28:14.709629 DQM Delay:
2681 09:28:14.713252 DQM0 = 116, DQM1 = 106
2682 09:28:14.713341 DQ Delay:
2683 09:28:14.716190 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2684 09:28:14.719878 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2685 09:28:14.723036 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2686 09:28:14.726397 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2687 09:28:14.726488
2688 09:28:14.726554
2689 09:28:14.729805 ==
2690 09:28:14.732892 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 09:28:14.736665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 09:28:14.736765 ==
2693 09:28:14.736832
2694 09:28:14.736893
2695 09:28:14.739447 TX Vref Scan disable
2696 09:28:14.739531 == TX Byte 0 ==
2697 09:28:14.743181 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2698 09:28:14.749710 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2699 09:28:14.749818 == TX Byte 1 ==
2700 09:28:14.753086 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2701 09:28:14.760015 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2702 09:28:14.760134 ==
2703 09:28:14.763437 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 09:28:14.766528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 09:28:14.766621 ==
2706 09:28:14.778286 TX Vref=22, minBit 1, minWin=24, winSum=415
2707 09:28:14.782000 TX Vref=24, minBit 7, minWin=25, winSum=422
2708 09:28:14.785114 TX Vref=26, minBit 1, minWin=26, winSum=430
2709 09:28:14.789151 TX Vref=28, minBit 4, minWin=26, winSum=436
2710 09:28:14.791947 TX Vref=30, minBit 1, minWin=26, winSum=435
2711 09:28:14.795342 TX Vref=32, minBit 1, minWin=26, winSum=432
2712 09:28:14.801892 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 28
2713 09:28:14.802002
2714 09:28:14.805444 Final TX Range 1 Vref 28
2715 09:28:14.805528
2716 09:28:14.805592 ==
2717 09:28:14.808837 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 09:28:14.812207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 09:28:14.812296 ==
2720 09:28:14.812360
2721 09:28:14.812420
2722 09:28:14.815955 TX Vref Scan disable
2723 09:28:14.818656 == TX Byte 0 ==
2724 09:28:14.821980 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2725 09:28:14.825714 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2726 09:28:14.828919 == TX Byte 1 ==
2727 09:28:14.832153 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2728 09:28:14.835656 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2729 09:28:14.835781
2730 09:28:14.839041 [DATLAT]
2731 09:28:14.839123 Freq=1200, CH0 RK0
2732 09:28:14.839194
2733 09:28:14.842247 DATLAT Default: 0xd
2734 09:28:14.842351 0, 0xFFFF, sum = 0
2735 09:28:14.845638 1, 0xFFFF, sum = 0
2736 09:28:14.845720 2, 0xFFFF, sum = 0
2737 09:28:14.849020 3, 0xFFFF, sum = 0
2738 09:28:14.849097 4, 0xFFFF, sum = 0
2739 09:28:14.852426 5, 0xFFFF, sum = 0
2740 09:28:14.852514 6, 0xFFFF, sum = 0
2741 09:28:14.856187 7, 0xFFFF, sum = 0
2742 09:28:14.856274 8, 0xFFFF, sum = 0
2743 09:28:14.858989 9, 0xFFFF, sum = 0
2744 09:28:14.859062 10, 0xFFFF, sum = 0
2745 09:28:14.862998 11, 0xFFFF, sum = 0
2746 09:28:14.863087 12, 0x0, sum = 1
2747 09:28:14.866096 13, 0x0, sum = 2
2748 09:28:14.866205 14, 0x0, sum = 3
2749 09:28:14.869380 15, 0x0, sum = 4
2750 09:28:14.869489 best_step = 13
2751 09:28:14.869582
2752 09:28:14.869675 ==
2753 09:28:14.873322 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 09:28:14.876061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 09:28:14.879274 ==
2756 09:28:14.879369 RX Vref Scan: 1
2757 09:28:14.879436
2758 09:28:14.882834 Set Vref Range= 32 -> 127
2759 09:28:14.882922
2760 09:28:14.882989 RX Vref 32 -> 127, step: 1
2761 09:28:14.886157
2762 09:28:14.886244 RX Delay -21 -> 252, step: 4
2763 09:28:14.886311
2764 09:28:14.889472 Set Vref, RX VrefLevel [Byte0]: 32
2765 09:28:14.893152 [Byte1]: 32
2766 09:28:14.897070
2767 09:28:14.897171 Set Vref, RX VrefLevel [Byte0]: 33
2768 09:28:14.900193 [Byte1]: 33
2769 09:28:14.904552
2770 09:28:14.904677 Set Vref, RX VrefLevel [Byte0]: 34
2771 09:28:14.907878 [Byte1]: 34
2772 09:28:14.912515
2773 09:28:14.912613 Set Vref, RX VrefLevel [Byte0]: 35
2774 09:28:14.916036 [Byte1]: 35
2775 09:28:14.920511
2776 09:28:14.920629 Set Vref, RX VrefLevel [Byte0]: 36
2777 09:28:14.923527 [Byte1]: 36
2778 09:28:14.928620
2779 09:28:14.928738 Set Vref, RX VrefLevel [Byte0]: 37
2780 09:28:14.932292 [Byte1]: 37
2781 09:28:14.936105
2782 09:28:14.936202 Set Vref, RX VrefLevel [Byte0]: 38
2783 09:28:14.939553 [Byte1]: 38
2784 09:28:14.944508
2785 09:28:14.944606 Set Vref, RX VrefLevel [Byte0]: 39
2786 09:28:14.947420 [Byte1]: 39
2787 09:28:14.952275
2788 09:28:14.952368 Set Vref, RX VrefLevel [Byte0]: 40
2789 09:28:14.955278 [Byte1]: 40
2790 09:28:14.960855
2791 09:28:14.960978 Set Vref, RX VrefLevel [Byte0]: 41
2792 09:28:14.963489 [Byte1]: 41
2793 09:28:14.967853
2794 09:28:14.967953 Set Vref, RX VrefLevel [Byte0]: 42
2795 09:28:14.971436 [Byte1]: 42
2796 09:28:14.975723
2797 09:28:14.975855 Set Vref, RX VrefLevel [Byte0]: 43
2798 09:28:14.979408 [Byte1]: 43
2799 09:28:14.984003
2800 09:28:14.984101 Set Vref, RX VrefLevel [Byte0]: 44
2801 09:28:14.987367 [Byte1]: 44
2802 09:28:14.992210
2803 09:28:14.992307 Set Vref, RX VrefLevel [Byte0]: 45
2804 09:28:14.995318 [Byte1]: 45
2805 09:28:14.999807
2806 09:28:14.999935 Set Vref, RX VrefLevel [Byte0]: 46
2807 09:28:15.003278 [Byte1]: 46
2808 09:28:15.008042
2809 09:28:15.008175 Set Vref, RX VrefLevel [Byte0]: 47
2810 09:28:15.010875 [Byte1]: 47
2811 09:28:15.015290
2812 09:28:15.015400 Set Vref, RX VrefLevel [Byte0]: 48
2813 09:28:15.018964 [Byte1]: 48
2814 09:28:15.023540
2815 09:28:15.023681 Set Vref, RX VrefLevel [Byte0]: 49
2816 09:28:15.026589 [Byte1]: 49
2817 09:28:15.031459
2818 09:28:15.031570 Set Vref, RX VrefLevel [Byte0]: 50
2819 09:28:15.035070 [Byte1]: 50
2820 09:28:15.039406
2821 09:28:15.039522 Set Vref, RX VrefLevel [Byte0]: 51
2822 09:28:15.043237 [Byte1]: 51
2823 09:28:15.047259
2824 09:28:15.047352 Set Vref, RX VrefLevel [Byte0]: 52
2825 09:28:15.051020 [Byte1]: 52
2826 09:28:15.055292
2827 09:28:15.055383 Set Vref, RX VrefLevel [Byte0]: 53
2828 09:28:15.058354 [Byte1]: 53
2829 09:28:15.063433
2830 09:28:15.063529 Set Vref, RX VrefLevel [Byte0]: 54
2831 09:28:15.066442 [Byte1]: 54
2832 09:28:15.071103
2833 09:28:15.071194 Set Vref, RX VrefLevel [Byte0]: 55
2834 09:28:15.074371 [Byte1]: 55
2835 09:28:15.078674
2836 09:28:15.078831 Set Vref, RX VrefLevel [Byte0]: 56
2837 09:28:15.082113 [Byte1]: 56
2838 09:28:15.087188
2839 09:28:15.087265 Set Vref, RX VrefLevel [Byte0]: 57
2840 09:28:15.090007 [Byte1]: 57
2841 09:28:15.095017
2842 09:28:15.095091 Set Vref, RX VrefLevel [Byte0]: 58
2843 09:28:15.097890 [Byte1]: 58
2844 09:28:15.102626
2845 09:28:15.102750 Set Vref, RX VrefLevel [Byte0]: 59
2846 09:28:15.105948 [Byte1]: 59
2847 09:28:15.110778
2848 09:28:15.110895 Set Vref, RX VrefLevel [Byte0]: 60
2849 09:28:15.113852 [Byte1]: 60
2850 09:28:15.118611
2851 09:28:15.118716 Set Vref, RX VrefLevel [Byte0]: 61
2852 09:28:15.122104 [Byte1]: 61
2853 09:28:15.126305
2854 09:28:15.126411 Set Vref, RX VrefLevel [Byte0]: 62
2855 09:28:15.130203 [Byte1]: 62
2856 09:28:15.134468
2857 09:28:15.134574 Set Vref, RX VrefLevel [Byte0]: 63
2858 09:28:15.138081 [Byte1]: 63
2859 09:28:15.142373
2860 09:28:15.142480 Set Vref, RX VrefLevel [Byte0]: 64
2861 09:28:15.145919 [Byte1]: 64
2862 09:28:15.150322
2863 09:28:15.150440 Set Vref, RX VrefLevel [Byte0]: 65
2864 09:28:15.153815 [Byte1]: 65
2865 09:28:15.158384
2866 09:28:15.158486 Set Vref, RX VrefLevel [Byte0]: 66
2867 09:28:15.161420 [Byte1]: 66
2868 09:28:15.166445
2869 09:28:15.166560 Set Vref, RX VrefLevel [Byte0]: 67
2870 09:28:15.169745 [Byte1]: 67
2871 09:28:15.173826
2872 09:28:15.173930 Set Vref, RX VrefLevel [Byte0]: 68
2873 09:28:15.177326 [Byte1]: 68
2874 09:28:15.181745
2875 09:28:15.181856 Set Vref, RX VrefLevel [Byte0]: 69
2876 09:28:15.185336 [Byte1]: 69
2877 09:28:15.189721
2878 09:28:15.189831 Final RX Vref Byte 0 = 53 to rank0
2879 09:28:15.193001 Final RX Vref Byte 1 = 51 to rank0
2880 09:28:15.196707 Final RX Vref Byte 0 = 53 to rank1
2881 09:28:15.199631 Final RX Vref Byte 1 = 51 to rank1==
2882 09:28:15.203232 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 09:28:15.209727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 09:28:15.209846 ==
2885 09:28:15.209941 DQS Delay:
2886 09:28:15.210031 DQS0 = 0, DQS1 = 0
2887 09:28:15.213051 DQM Delay:
2888 09:28:15.213156 DQM0 = 115, DQM1 = 104
2889 09:28:15.216348 DQ Delay:
2890 09:28:15.220434 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2891 09:28:15.223465 DQ4 =116, DQ5 =110, DQ6 =122, DQ7 =122
2892 09:28:15.226408 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2893 09:28:15.229969 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2894 09:28:15.230072
2895 09:28:15.230178
2896 09:28:15.236537 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2897 09:28:15.240309 CH0 RK0: MR19=403, MR18=2F1
2898 09:28:15.246898 CH0_RK0: MR19=0x403, MR18=0x2F1, DQSOSC=409, MR23=63, INC=39, DEC=26
2899 09:28:15.246981
2900 09:28:15.249994 ----->DramcWriteLeveling(PI) begin...
2901 09:28:15.250095 ==
2902 09:28:15.253320 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 09:28:15.256977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 09:28:15.257052 ==
2905 09:28:15.260261 Write leveling (Byte 0): 34 => 34
2906 09:28:15.263292 Write leveling (Byte 1): 30 => 30
2907 09:28:15.266994 DramcWriteLeveling(PI) end<-----
2908 09:28:15.267068
2909 09:28:15.267132 ==
2910 09:28:15.270068 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 09:28:15.273785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 09:28:15.273888 ==
2913 09:28:15.277080 [Gating] SW mode calibration
2914 09:28:15.283425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 09:28:15.290220 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 09:28:15.293980 0 15 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
2917 09:28:15.300608 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2918 09:28:15.303985 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 09:28:15.307107 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 09:28:15.310740 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 09:28:15.317342 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 09:28:15.320576 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2923 09:28:15.323690 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 1)
2924 09:28:15.330492 1 0 0 | B1->B0 | 2e2e 2626 | 0 1 | (0 1) (0 0)
2925 09:28:15.334263 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2926 09:28:15.337079 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 09:28:15.344278 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 09:28:15.347166 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 09:28:15.351074 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 09:28:15.357653 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2931 09:28:15.361114 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2932 09:28:15.363889 1 1 0 | B1->B0 | 3a3a 4545 | 0 0 | (1 1) (0 0)
2933 09:28:15.367335 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 09:28:15.374512 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 09:28:15.377746 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 09:28:15.380824 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 09:28:15.387727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 09:28:15.390813 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 09:28:15.394806 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2940 09:28:15.400957 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2941 09:28:15.404767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2942 09:28:15.407640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 09:28:15.414799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 09:28:15.417729 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 09:28:15.421266 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 09:28:15.424602 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 09:28:15.431604 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 09:28:15.434978 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 09:28:15.438342 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 09:28:15.445175 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 09:28:15.448572 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 09:28:15.451492 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 09:28:15.458210 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 09:28:15.461295 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 09:28:15.464476 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2956 09:28:15.471638 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2957 09:28:15.471762 Total UI for P1: 0, mck2ui 16
2958 09:28:15.478263 best dqsien dly found for B0: ( 1, 3, 28)
2959 09:28:15.481500 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 09:28:15.485300 Total UI for P1: 0, mck2ui 16
2961 09:28:15.488205 best dqsien dly found for B1: ( 1, 4, 0)
2962 09:28:15.491713 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2963 09:28:15.494665 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2964 09:28:15.494776
2965 09:28:15.498418 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 09:28:15.501814 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2967 09:28:15.505187 [Gating] SW calibration Done
2968 09:28:15.505280 ==
2969 09:28:15.508270 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 09:28:15.511874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 09:28:15.511970 ==
2972 09:28:15.515345 RX Vref Scan: 0
2973 09:28:15.515428
2974 09:28:15.515510 RX Vref 0 -> 0, step: 1
2975 09:28:15.515590
2976 09:28:15.518644 RX Delay -40 -> 252, step: 8
2977 09:28:15.521792 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2978 09:28:15.528558 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2979 09:28:15.532113 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2980 09:28:15.535248 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2981 09:28:15.538441 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2982 09:28:15.542112 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2983 09:28:15.548593 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2984 09:28:15.551681 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2985 09:28:15.555522 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2986 09:28:15.558601 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2987 09:28:15.562307 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2988 09:28:15.565746 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2989 09:28:15.571957 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2990 09:28:15.575638 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2991 09:28:15.578675 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2992 09:28:15.582356 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2993 09:28:15.582470 ==
2994 09:28:15.585586 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 09:28:15.592624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 09:28:15.592727 ==
2997 09:28:15.592810 DQS Delay:
2998 09:28:15.592885 DQS0 = 0, DQS1 = 0
2999 09:28:15.595940 DQM Delay:
3000 09:28:15.596021 DQM0 = 115, DQM1 = 106
3001 09:28:15.598931 DQ Delay:
3002 09:28:15.602214 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3003 09:28:15.605910 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3004 09:28:15.609225 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3005 09:28:15.612497 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3006 09:28:15.612588
3007 09:28:15.612657
3008 09:28:15.612718 ==
3009 09:28:15.616294 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 09:28:15.619335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 09:28:15.619423 ==
3012 09:28:15.619490
3013 09:28:15.619551
3014 09:28:15.622863 TX Vref Scan disable
3015 09:28:15.625909 == TX Byte 0 ==
3016 09:28:15.629219 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3017 09:28:15.632870 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3018 09:28:15.635996 == TX Byte 1 ==
3019 09:28:15.639558 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3020 09:28:15.642639 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3021 09:28:15.642737 ==
3022 09:28:15.645947 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 09:28:15.649328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 09:28:15.649415 ==
3025 09:28:15.662778 TX Vref=22, minBit 1, minWin=25, winSum=419
3026 09:28:15.666091 TX Vref=24, minBit 3, minWin=25, winSum=423
3027 09:28:15.669579 TX Vref=26, minBit 1, minWin=26, winSum=431
3028 09:28:15.672988 TX Vref=28, minBit 2, minWin=26, winSum=433
3029 09:28:15.676513 TX Vref=30, minBit 1, minWin=26, winSum=431
3030 09:28:15.679913 TX Vref=32, minBit 3, minWin=26, winSum=432
3031 09:28:15.686454 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 28
3032 09:28:15.686565
3033 09:28:15.690179 Final TX Range 1 Vref 28
3034 09:28:15.690269
3035 09:28:15.690335 ==
3036 09:28:15.693541 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 09:28:15.696247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 09:28:15.696332 ==
3039 09:28:15.696397
3040 09:28:15.696458
3041 09:28:15.699773 TX Vref Scan disable
3042 09:28:15.703099 == TX Byte 0 ==
3043 09:28:15.706572 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3044 09:28:15.710144 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3045 09:28:15.713595 == TX Byte 1 ==
3046 09:28:15.716673 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3047 09:28:15.720118 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3048 09:28:15.720232
3049 09:28:15.723309 [DATLAT]
3050 09:28:15.723403 Freq=1200, CH0 RK1
3051 09:28:15.723473
3052 09:28:15.726694 DATLAT Default: 0xd
3053 09:28:15.726801 0, 0xFFFF, sum = 0
3054 09:28:15.730250 1, 0xFFFF, sum = 0
3055 09:28:15.730339 2, 0xFFFF, sum = 0
3056 09:28:15.733485 3, 0xFFFF, sum = 0
3057 09:28:15.733589 4, 0xFFFF, sum = 0
3058 09:28:15.736633 5, 0xFFFF, sum = 0
3059 09:28:15.736722 6, 0xFFFF, sum = 0
3060 09:28:15.740190 7, 0xFFFF, sum = 0
3061 09:28:15.740277 8, 0xFFFF, sum = 0
3062 09:28:15.743589 9, 0xFFFF, sum = 0
3063 09:28:15.743704 10, 0xFFFF, sum = 0
3064 09:28:15.747053 11, 0xFFFF, sum = 0
3065 09:28:15.747139 12, 0x0, sum = 1
3066 09:28:15.750855 13, 0x0, sum = 2
3067 09:28:15.750944 14, 0x0, sum = 3
3068 09:28:15.753445 15, 0x0, sum = 4
3069 09:28:15.753533 best_step = 13
3070 09:28:15.753600
3071 09:28:15.753663 ==
3072 09:28:15.756966 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 09:28:15.760340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 09:28:15.764037 ==
3075 09:28:15.764155 RX Vref Scan: 0
3076 09:28:15.764254
3077 09:28:15.767272 RX Vref 0 -> 0, step: 1
3078 09:28:15.767358
3079 09:28:15.770212 RX Delay -21 -> 252, step: 4
3080 09:28:15.773723 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3081 09:28:15.777150 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3082 09:28:15.780418 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3083 09:28:15.787600 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3084 09:28:15.790702 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3085 09:28:15.793897 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3086 09:28:15.797794 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3087 09:28:15.801096 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3088 09:28:15.807154 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3089 09:28:15.810646 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3090 09:28:15.813729 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3091 09:28:15.817133 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3092 09:28:15.820573 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3093 09:28:15.823942 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3094 09:28:15.830859 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3095 09:28:15.834320 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3096 09:28:15.834412 ==
3097 09:28:15.837384 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 09:28:15.841006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 09:28:15.841111 ==
3100 09:28:15.844671 DQS Delay:
3101 09:28:15.844796 DQS0 = 0, DQS1 = 0
3102 09:28:15.844895 DQM Delay:
3103 09:28:15.847520 DQM0 = 114, DQM1 = 104
3104 09:28:15.847610 DQ Delay:
3105 09:28:15.851053 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3106 09:28:15.854594 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3107 09:28:15.857433 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =94
3108 09:28:15.861187 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3109 09:28:15.861277
3110 09:28:15.864667
3111 09:28:15.871213 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3112 09:28:15.874471 CH0 RK1: MR19=403, MR18=F1
3113 09:28:15.878031 CH0_RK1: MR19=0x403, MR18=0xF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3114 09:28:15.881130 [RxdqsGatingPostProcess] freq 1200
3115 09:28:15.887914 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3116 09:28:15.891821 best DQS0 dly(2T, 0.5T) = (0, 12)
3117 09:28:15.894541 best DQS1 dly(2T, 0.5T) = (0, 12)
3118 09:28:15.897880 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3119 09:28:15.901121 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3120 09:28:15.904762 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 09:28:15.904859 best DQS1 dly(2T, 0.5T) = (0, 12)
3122 09:28:15.908015 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 09:28:15.911371 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3124 09:28:15.914540 Pre-setting of DQS Precalculation
3125 09:28:15.921335 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3126 09:28:15.921455 ==
3127 09:28:15.925236 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 09:28:15.927975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 09:28:15.928065 ==
3130 09:28:15.934886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 09:28:15.938083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3132 09:28:15.948330 [CA 0] Center 38 (9~68) winsize 60
3133 09:28:15.951971 [CA 1] Center 38 (8~68) winsize 61
3134 09:28:15.955126 [CA 2] Center 35 (5~65) winsize 61
3135 09:28:15.958289 [CA 3] Center 34 (4~65) winsize 62
3136 09:28:15.961756 [CA 4] Center 34 (4~65) winsize 62
3137 09:28:15.964934 [CA 5] Center 34 (4~64) winsize 61
3138 09:28:15.965025
3139 09:28:15.968315 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3140 09:28:15.968404
3141 09:28:15.972262 [CATrainingPosCal] consider 1 rank data
3142 09:28:15.975229 u2DelayCellTimex100 = 270/100 ps
3143 09:28:15.978430 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3144 09:28:15.981939 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3145 09:28:15.985150 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3146 09:28:15.988893 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3147 09:28:15.995249 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3148 09:28:15.998875 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3149 09:28:15.998969
3150 09:28:16.001885 CA PerBit enable=1, Macro0, CA PI delay=34
3151 09:28:16.001999
3152 09:28:16.005314 [CBTSetCACLKResult] CA Dly = 34
3153 09:28:16.005398 CS Dly: 6 (0~37)
3154 09:28:16.005464 ==
3155 09:28:16.008983 Dram Type= 6, Freq= 0, CH_1, rank 1
3156 09:28:16.015298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 09:28:16.015392 ==
3158 09:28:16.018647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 09:28:16.025479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3160 09:28:16.034098 [CA 0] Center 38 (8~68) winsize 61
3161 09:28:16.036927 [CA 1] Center 38 (8~68) winsize 61
3162 09:28:16.040655 [CA 2] Center 34 (4~65) winsize 62
3163 09:28:16.043720 [CA 3] Center 34 (4~65) winsize 62
3164 09:28:16.047435 [CA 4] Center 34 (4~65) winsize 62
3165 09:28:16.050622 [CA 5] Center 33 (3~63) winsize 61
3166 09:28:16.050707
3167 09:28:16.053740 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3168 09:28:16.053839
3169 09:28:16.057286 [CATrainingPosCal] consider 2 rank data
3170 09:28:16.060524 u2DelayCellTimex100 = 270/100 ps
3171 09:28:16.063906 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3172 09:28:16.067208 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3173 09:28:16.070441 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3174 09:28:16.077319 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3175 09:28:16.080964 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3176 09:28:16.084088 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3177 09:28:16.084176
3178 09:28:16.087689 CA PerBit enable=1, Macro0, CA PI delay=33
3179 09:28:16.087774
3180 09:28:16.090932 [CBTSetCACLKResult] CA Dly = 33
3181 09:28:16.091045 CS Dly: 7 (0~40)
3182 09:28:16.091125
3183 09:28:16.094338 ----->DramcWriteLeveling(PI) begin...
3184 09:28:16.094423 ==
3185 09:28:16.097873 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 09:28:16.104650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 09:28:16.104775 ==
3188 09:28:16.107302 Write leveling (Byte 0): 26 => 26
3189 09:28:16.110871 Write leveling (Byte 1): 28 => 28
3190 09:28:16.110960 DramcWriteLeveling(PI) end<-----
3191 09:28:16.111026
3192 09:28:16.114073 ==
3193 09:28:16.117305 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 09:28:16.121149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 09:28:16.121236 ==
3196 09:28:16.124257 [Gating] SW mode calibration
3197 09:28:16.131126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3198 09:28:16.134558 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3199 09:28:16.141211 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
3200 09:28:16.144875 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3201 09:28:16.147879 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 09:28:16.154557 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 09:28:16.158094 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 09:28:16.160957 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 09:28:16.165238 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 09:28:16.171428 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3207 09:28:16.174535 1 0 0 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
3208 09:28:16.177915 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 09:28:16.184493 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3210 09:28:16.187913 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 09:28:16.191583 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3212 09:28:16.198374 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 09:28:16.201548 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 09:28:16.204738 1 0 28 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
3215 09:28:16.211348 1 1 0 | B1->B0 | 4242 3131 | 0 0 | (0 0) (0 0)
3216 09:28:16.215226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 09:28:16.218256 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 09:28:16.221456 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 09:28:16.228522 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 09:28:16.231683 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 09:28:16.235560 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 09:28:16.241769 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 09:28:16.245220 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3224 09:28:16.248914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 09:28:16.255240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 09:28:16.258493 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 09:28:16.262057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 09:28:16.268824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 09:28:16.272191 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 09:28:16.275338 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 09:28:16.278995 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 09:28:16.285444 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 09:28:16.289201 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 09:28:16.292187 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 09:28:16.299034 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 09:28:16.302006 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 09:28:16.305456 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 09:28:16.312227 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3239 09:28:16.315747 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3240 09:28:16.319316 Total UI for P1: 0, mck2ui 16
3241 09:28:16.322648 best dqsien dly found for B1: ( 1, 3, 28)
3242 09:28:16.325876 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 09:28:16.329057 Total UI for P1: 0, mck2ui 16
3244 09:28:16.332226 best dqsien dly found for B0: ( 1, 3, 30)
3245 09:28:16.335988 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3246 09:28:16.339243 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3247 09:28:16.339343
3248 09:28:16.342964 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3249 09:28:16.345803 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3250 09:28:16.349300 [Gating] SW calibration Done
3251 09:28:16.349399 ==
3252 09:28:16.352914 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 09:28:16.358990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 09:28:16.359106 ==
3255 09:28:16.359173 RX Vref Scan: 0
3256 09:28:16.359233
3257 09:28:16.362658 RX Vref 0 -> 0, step: 1
3258 09:28:16.362781
3259 09:28:16.365947 RX Delay -40 -> 252, step: 8
3260 09:28:16.369508 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3261 09:28:16.373068 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3262 09:28:16.375777 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3263 09:28:16.379571 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3264 09:28:16.386082 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3265 09:28:16.389952 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3266 09:28:16.392648 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3267 09:28:16.396001 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3268 09:28:16.399709 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3269 09:28:16.402659 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3270 09:28:16.409415 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3271 09:28:16.413090 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3272 09:28:16.416421 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3273 09:28:16.419650 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3274 09:28:16.423254 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3275 09:28:16.429624 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3276 09:28:16.429729 ==
3277 09:28:16.432948 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 09:28:16.436448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 09:28:16.436579 ==
3280 09:28:16.436683 DQS Delay:
3281 09:28:16.440032 DQS0 = 0, DQS1 = 0
3282 09:28:16.440119 DQM Delay:
3283 09:28:16.443382 DQM0 = 115, DQM1 = 108
3284 09:28:16.443470 DQ Delay:
3285 09:28:16.446606 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3286 09:28:16.450270 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3287 09:28:16.453211 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3288 09:28:16.456492 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3289 09:28:16.456611
3290 09:28:16.456703
3291 09:28:16.459726 ==
3292 09:28:16.459812 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 09:28:16.466801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 09:28:16.466906 ==
3295 09:28:16.466977
3296 09:28:16.467039
3297 09:28:16.469650 TX Vref Scan disable
3298 09:28:16.469737 == TX Byte 0 ==
3299 09:28:16.473490 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3300 09:28:16.480067 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3301 09:28:16.480211 == TX Byte 1 ==
3302 09:28:16.483069 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3303 09:28:16.490310 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3304 09:28:16.490418 ==
3305 09:28:16.493493 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 09:28:16.496356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 09:28:16.496445 ==
3308 09:28:16.508226 TX Vref=22, minBit 0, minWin=25, winSum=412
3309 09:28:16.511509 TX Vref=24, minBit 1, minWin=25, winSum=415
3310 09:28:16.515227 TX Vref=26, minBit 1, minWin=26, winSum=424
3311 09:28:16.518147 TX Vref=28, minBit 0, minWin=26, winSum=427
3312 09:28:16.521590 TX Vref=30, minBit 3, minWin=25, winSum=428
3313 09:28:16.528242 TX Vref=32, minBit 11, minWin=25, winSum=429
3314 09:28:16.532352 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
3315 09:28:16.532449
3316 09:28:16.535409 Final TX Range 1 Vref 28
3317 09:28:16.535495
3318 09:28:16.535560 ==
3319 09:28:16.538274 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 09:28:16.541555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 09:28:16.541642 ==
3322 09:28:16.541708
3323 09:28:16.541768
3324 09:28:16.545065 TX Vref Scan disable
3325 09:28:16.548696 == TX Byte 0 ==
3326 09:28:16.551661 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3327 09:28:16.555291 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3328 09:28:16.558264 == TX Byte 1 ==
3329 09:28:16.561941 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3330 09:28:16.565176 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3331 09:28:16.565262
3332 09:28:16.568500 [DATLAT]
3333 09:28:16.568614 Freq=1200, CH1 RK0
3334 09:28:16.568711
3335 09:28:16.572116 DATLAT Default: 0xd
3336 09:28:16.572200 0, 0xFFFF, sum = 0
3337 09:28:16.575375 1, 0xFFFF, sum = 0
3338 09:28:16.575463 2, 0xFFFF, sum = 0
3339 09:28:16.578645 3, 0xFFFF, sum = 0
3340 09:28:16.578768 4, 0xFFFF, sum = 0
3341 09:28:16.582126 5, 0xFFFF, sum = 0
3342 09:28:16.582213 6, 0xFFFF, sum = 0
3343 09:28:16.585339 7, 0xFFFF, sum = 0
3344 09:28:16.585426 8, 0xFFFF, sum = 0
3345 09:28:16.588821 9, 0xFFFF, sum = 0
3346 09:28:16.588910 10, 0xFFFF, sum = 0
3347 09:28:16.592209 11, 0xFFFF, sum = 0
3348 09:28:16.592345 12, 0x0, sum = 1
3349 09:28:16.595175 13, 0x0, sum = 2
3350 09:28:16.595263 14, 0x0, sum = 3
3351 09:28:16.598878 15, 0x0, sum = 4
3352 09:28:16.598965 best_step = 13
3353 09:28:16.599030
3354 09:28:16.599090 ==
3355 09:28:16.602078 Dram Type= 6, Freq= 0, CH_1, rank 0
3356 09:28:16.608751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3357 09:28:16.608850 ==
3358 09:28:16.608917 RX Vref Scan: 1
3359 09:28:16.608978
3360 09:28:16.612169 Set Vref Range= 32 -> 127
3361 09:28:16.612255
3362 09:28:16.615559 RX Vref 32 -> 127, step: 1
3363 09:28:16.615724
3364 09:28:16.615805 RX Delay -21 -> 252, step: 4
3365 09:28:16.615865
3366 09:28:16.618947 Set Vref, RX VrefLevel [Byte0]: 32
3367 09:28:16.622164 [Byte1]: 32
3368 09:28:16.626783
3369 09:28:16.626877 Set Vref, RX VrefLevel [Byte0]: 33
3370 09:28:16.629900 [Byte1]: 33
3371 09:28:16.634599
3372 09:28:16.634692 Set Vref, RX VrefLevel [Byte0]: 34
3373 09:28:16.637921 [Byte1]: 34
3374 09:28:16.642490
3375 09:28:16.642631 Set Vref, RX VrefLevel [Byte0]: 35
3376 09:28:16.645777 [Byte1]: 35
3377 09:28:16.650289
3378 09:28:16.650378 Set Vref, RX VrefLevel [Byte0]: 36
3379 09:28:16.653382 [Byte1]: 36
3380 09:28:16.658544
3381 09:28:16.658670 Set Vref, RX VrefLevel [Byte0]: 37
3382 09:28:16.661870 [Byte1]: 37
3383 09:28:16.666348
3384 09:28:16.666474 Set Vref, RX VrefLevel [Byte0]: 38
3385 09:28:16.669538 [Byte1]: 38
3386 09:28:16.674132
3387 09:28:16.674225 Set Vref, RX VrefLevel [Byte0]: 39
3388 09:28:16.677261 [Byte1]: 39
3389 09:28:16.681839
3390 09:28:16.681935 Set Vref, RX VrefLevel [Byte0]: 40
3391 09:28:16.685091 [Byte1]: 40
3392 09:28:16.689807
3393 09:28:16.689897 Set Vref, RX VrefLevel [Byte0]: 41
3394 09:28:16.693479 [Byte1]: 41
3395 09:28:16.697645
3396 09:28:16.697755 Set Vref, RX VrefLevel [Byte0]: 42
3397 09:28:16.701054 [Byte1]: 42
3398 09:28:16.706178
3399 09:28:16.706275 Set Vref, RX VrefLevel [Byte0]: 43
3400 09:28:16.709130 [Byte1]: 43
3401 09:28:16.713714
3402 09:28:16.713805 Set Vref, RX VrefLevel [Byte0]: 44
3403 09:28:16.717021 [Byte1]: 44
3404 09:28:16.721527
3405 09:28:16.721615 Set Vref, RX VrefLevel [Byte0]: 45
3406 09:28:16.725441 [Byte1]: 45
3407 09:28:16.729360
3408 09:28:16.729452 Set Vref, RX VrefLevel [Byte0]: 46
3409 09:28:16.732876 [Byte1]: 46
3410 09:28:16.737707
3411 09:28:16.737802 Set Vref, RX VrefLevel [Byte0]: 47
3412 09:28:16.741165 [Byte1]: 47
3413 09:28:16.745601
3414 09:28:16.745698 Set Vref, RX VrefLevel [Byte0]: 48
3415 09:28:16.748818 [Byte1]: 48
3416 09:28:16.753241
3417 09:28:16.753340 Set Vref, RX VrefLevel [Byte0]: 49
3418 09:28:16.756641 [Byte1]: 49
3419 09:28:16.761076
3420 09:28:16.761185 Set Vref, RX VrefLevel [Byte0]: 50
3421 09:28:16.764358 [Byte1]: 50
3422 09:28:16.769473
3423 09:28:16.769586 Set Vref, RX VrefLevel [Byte0]: 51
3424 09:28:16.772395 [Byte1]: 51
3425 09:28:16.776973
3426 09:28:16.777065 Set Vref, RX VrefLevel [Byte0]: 52
3427 09:28:16.780181 [Byte1]: 52
3428 09:28:16.785181
3429 09:28:16.785278 Set Vref, RX VrefLevel [Byte0]: 53
3430 09:28:16.788113 [Byte1]: 53
3431 09:28:16.792766
3432 09:28:16.792856 Set Vref, RX VrefLevel [Byte0]: 54
3433 09:28:16.796103 [Byte1]: 54
3434 09:28:16.800734
3435 09:28:16.800827 Set Vref, RX VrefLevel [Byte0]: 55
3436 09:28:16.803972 [Byte1]: 55
3437 09:28:16.808455
3438 09:28:16.808573 Set Vref, RX VrefLevel [Byte0]: 56
3439 09:28:16.811803 [Byte1]: 56
3440 09:28:16.816662
3441 09:28:16.816761 Set Vref, RX VrefLevel [Byte0]: 57
3442 09:28:16.819878 [Byte1]: 57
3443 09:28:16.824910
3444 09:28:16.825008 Set Vref, RX VrefLevel [Byte0]: 58
3445 09:28:16.828250 [Byte1]: 58
3446 09:28:16.832780
3447 09:28:16.832878 Set Vref, RX VrefLevel [Byte0]: 59
3448 09:28:16.835936 [Byte1]: 59
3449 09:28:16.840306
3450 09:28:16.840406 Set Vref, RX VrefLevel [Byte0]: 60
3451 09:28:16.843731 [Byte1]: 60
3452 09:28:16.848471
3453 09:28:16.848565 Set Vref, RX VrefLevel [Byte0]: 61
3454 09:28:16.851491 [Byte1]: 61
3455 09:28:16.856338
3456 09:28:16.856445 Set Vref, RX VrefLevel [Byte0]: 62
3457 09:28:16.859669 [Byte1]: 62
3458 09:28:16.864423
3459 09:28:16.864519 Set Vref, RX VrefLevel [Byte0]: 63
3460 09:28:16.867373 [Byte1]: 63
3461 09:28:16.872054
3462 09:28:16.872149 Set Vref, RX VrefLevel [Byte0]: 64
3463 09:28:16.875332 [Byte1]: 64
3464 09:28:16.880156
3465 09:28:16.880266 Set Vref, RX VrefLevel [Byte0]: 65
3466 09:28:16.883509 [Byte1]: 65
3467 09:28:16.887915
3468 09:28:16.888011 Set Vref, RX VrefLevel [Byte0]: 66
3469 09:28:16.891329 [Byte1]: 66
3470 09:28:16.895878
3471 09:28:16.895972 Set Vref, RX VrefLevel [Byte0]: 67
3472 09:28:16.898981 [Byte1]: 67
3473 09:28:16.903783
3474 09:28:16.903878 Set Vref, RX VrefLevel [Byte0]: 68
3475 09:28:16.907441 [Byte1]: 68
3476 09:28:16.911785
3477 09:28:16.911875 Set Vref, RX VrefLevel [Byte0]: 69
3478 09:28:16.914912 [Byte1]: 69
3479 09:28:16.919602
3480 09:28:16.919696 Set Vref, RX VrefLevel [Byte0]: 70
3481 09:28:16.926097 [Byte1]: 70
3482 09:28:16.926202
3483 09:28:16.929491 Set Vref, RX VrefLevel [Byte0]: 71
3484 09:28:16.933086 [Byte1]: 71
3485 09:28:16.933166
3486 09:28:16.936095 Set Vref, RX VrefLevel [Byte0]: 72
3487 09:28:16.939867 [Byte1]: 72
3488 09:28:16.943773
3489 09:28:16.943863 Final RX Vref Byte 0 = 58 to rank0
3490 09:28:16.946465 Final RX Vref Byte 1 = 53 to rank0
3491 09:28:16.950102 Final RX Vref Byte 0 = 58 to rank1
3492 09:28:16.953167 Final RX Vref Byte 1 = 53 to rank1==
3493 09:28:16.956883 Dram Type= 6, Freq= 0, CH_1, rank 0
3494 09:28:16.960734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 09:28:16.963276 ==
3496 09:28:16.963397 DQS Delay:
3497 09:28:16.963462 DQS0 = 0, DQS1 = 0
3498 09:28:16.966692 DQM Delay:
3499 09:28:16.966803 DQM0 = 116, DQM1 = 109
3500 09:28:16.970352 DQ Delay:
3501 09:28:16.973710 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3502 09:28:16.977065 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3503 09:28:16.980202 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3504 09:28:16.983401 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =114
3505 09:28:16.983493
3506 09:28:16.983559
3507 09:28:16.990162 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3508 09:28:16.993457 CH1 RK0: MR19=303, MR18=FCE0
3509 09:28:17.000119 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3510 09:28:17.000249
3511 09:28:17.003609 ----->DramcWriteLeveling(PI) begin...
3512 09:28:17.003730 ==
3513 09:28:17.006901 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 09:28:17.010750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 09:28:17.010857 ==
3516 09:28:17.013944 Write leveling (Byte 0): 25 => 25
3517 09:28:17.017335 Write leveling (Byte 1): 27 => 27
3518 09:28:17.020606 DramcWriteLeveling(PI) end<-----
3519 09:28:17.020696
3520 09:28:17.020760 ==
3521 09:28:17.023956 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 09:28:17.027423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 09:28:17.027528 ==
3524 09:28:17.030766 [Gating] SW mode calibration
3525 09:28:17.037377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3526 09:28:17.044385 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3527 09:28:17.047500 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3528 09:28:17.050744 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3529 09:28:17.057561 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 09:28:17.061477 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 09:28:17.064476 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 09:28:17.071557 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3533 09:28:17.074629 0 15 24 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
3534 09:28:17.077832 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3535 09:28:17.084658 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 09:28:17.088372 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 09:28:17.091139 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 09:28:17.097665 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 09:28:17.101092 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 09:28:17.104486 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3541 09:28:17.110893 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3542 09:28:17.114600 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3543 09:28:17.117853 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 09:28:17.121362 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 09:28:17.127841 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 09:28:17.131606 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 09:28:17.134815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 09:28:17.141147 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 09:28:17.144747 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3550 09:28:17.148039 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3551 09:28:17.154644 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 09:28:17.157800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 09:28:17.161488 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 09:28:17.168043 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 09:28:17.171398 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 09:28:17.174371 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 09:28:17.181691 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 09:28:17.185055 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 09:28:17.187804 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 09:28:17.195173 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 09:28:17.198191 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 09:28:17.201680 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 09:28:17.205078 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 09:28:17.211662 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 09:28:17.214710 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3566 09:28:17.218106 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3567 09:28:17.221767 Total UI for P1: 0, mck2ui 16
3568 09:28:17.225239 best dqsien dly found for B0: ( 1, 3, 24)
3569 09:28:17.231453 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 09:28:17.231561 Total UI for P1: 0, mck2ui 16
3571 09:28:17.238088 best dqsien dly found for B1: ( 1, 3, 26)
3572 09:28:17.241312 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3573 09:28:17.244850 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3574 09:28:17.244965
3575 09:28:17.248532 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3576 09:28:17.251613 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3577 09:28:17.254790 [Gating] SW calibration Done
3578 09:28:17.254903 ==
3579 09:28:17.258492 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 09:28:17.261466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 09:28:17.261568 ==
3582 09:28:17.264773 RX Vref Scan: 0
3583 09:28:17.264856
3584 09:28:17.264919 RX Vref 0 -> 0, step: 1
3585 09:28:17.264977
3586 09:28:17.268191 RX Delay -40 -> 252, step: 8
3587 09:28:17.271576 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3588 09:28:17.278145 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3589 09:28:17.281620 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3590 09:28:17.284828 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3591 09:28:17.288036 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3592 09:28:17.291622 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3593 09:28:17.298295 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3594 09:28:17.302048 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3595 09:28:17.304919 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3596 09:28:17.308757 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3597 09:28:17.311814 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3598 09:28:17.314957 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3599 09:28:17.321702 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3600 09:28:17.325094 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3601 09:28:17.329130 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3602 09:28:17.331876 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3603 09:28:17.331957 ==
3604 09:28:17.335170 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 09:28:17.341872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 09:28:17.341976 ==
3607 09:28:17.342044 DQS Delay:
3608 09:28:17.342119 DQS0 = 0, DQS1 = 0
3609 09:28:17.345370 DQM Delay:
3610 09:28:17.345449 DQM0 = 113, DQM1 = 110
3611 09:28:17.349162 DQ Delay:
3612 09:28:17.351851 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3613 09:28:17.355388 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3614 09:28:17.358774 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3615 09:28:17.362242 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3616 09:28:17.362332
3617 09:28:17.362395
3618 09:28:17.362453 ==
3619 09:28:17.365383 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 09:28:17.368774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 09:28:17.368860 ==
3622 09:28:17.368923
3623 09:28:17.372180
3624 09:28:17.372263 TX Vref Scan disable
3625 09:28:17.375791 == TX Byte 0 ==
3626 09:28:17.378842 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3627 09:28:17.382266 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3628 09:28:17.385263 == TX Byte 1 ==
3629 09:28:17.388754 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3630 09:28:17.392286 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3631 09:28:17.392387 ==
3632 09:28:17.396058 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 09:28:17.402097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 09:28:17.402263 ==
3635 09:28:17.412545 TX Vref=22, minBit 3, minWin=25, winSum=417
3636 09:28:17.416187 TX Vref=24, minBit 0, minWin=26, winSum=425
3637 09:28:17.419296 TX Vref=26, minBit 0, minWin=26, winSum=430
3638 09:28:17.423197 TX Vref=28, minBit 1, minWin=26, winSum=433
3639 09:28:17.425934 TX Vref=30, minBit 9, minWin=26, winSum=431
3640 09:28:17.429180 TX Vref=32, minBit 4, minWin=26, winSum=430
3641 09:28:17.435899 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3642 09:28:17.436004
3643 09:28:17.439217 Final TX Range 1 Vref 28
3644 09:28:17.439302
3645 09:28:17.439365 ==
3646 09:28:17.442996 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 09:28:17.445919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 09:28:17.445999 ==
3649 09:28:17.446060
3650 09:28:17.446117
3651 09:28:17.449717 TX Vref Scan disable
3652 09:28:17.452544 == TX Byte 0 ==
3653 09:28:17.455802 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3654 09:28:17.459330 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3655 09:28:17.462405 == TX Byte 1 ==
3656 09:28:17.465583 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3657 09:28:17.468999 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3658 09:28:17.469085
3659 09:28:17.472488 [DATLAT]
3660 09:28:17.472561 Freq=1200, CH1 RK1
3661 09:28:17.472623
3662 09:28:17.475569 DATLAT Default: 0xd
3663 09:28:17.475641 0, 0xFFFF, sum = 0
3664 09:28:17.479139 1, 0xFFFF, sum = 0
3665 09:28:17.479241 2, 0xFFFF, sum = 0
3666 09:28:17.482467 3, 0xFFFF, sum = 0
3667 09:28:17.482569 4, 0xFFFF, sum = 0
3668 09:28:17.485704 5, 0xFFFF, sum = 0
3669 09:28:17.485813 6, 0xFFFF, sum = 0
3670 09:28:17.488952 7, 0xFFFF, sum = 0
3671 09:28:17.493014 8, 0xFFFF, sum = 0
3672 09:28:17.493135 9, 0xFFFF, sum = 0
3673 09:28:17.495447 10, 0xFFFF, sum = 0
3674 09:28:17.495529 11, 0xFFFF, sum = 0
3675 09:28:17.499020 12, 0x0, sum = 1
3676 09:28:17.499099 13, 0x0, sum = 2
3677 09:28:17.502344 14, 0x0, sum = 3
3678 09:28:17.502450 15, 0x0, sum = 4
3679 09:28:17.502511 best_step = 13
3680 09:28:17.502566
3681 09:28:17.505998 ==
3682 09:28:17.508969 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 09:28:17.512242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 09:28:17.512350 ==
3685 09:28:17.512443 RX Vref Scan: 0
3686 09:28:17.512505
3687 09:28:17.515598 RX Vref 0 -> 0, step: 1
3688 09:28:17.515674
3689 09:28:17.518832 RX Delay -21 -> 252, step: 4
3690 09:28:17.522000 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3691 09:28:17.528808 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3692 09:28:17.532486 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3693 09:28:17.535312 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3694 09:28:17.538977 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3695 09:28:17.542152 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3696 09:28:17.549017 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3697 09:28:17.552559 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3698 09:28:17.555434 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3699 09:28:17.558602 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3700 09:28:17.561988 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3701 09:28:17.569016 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3702 09:28:17.571775 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3703 09:28:17.575432 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3704 09:28:17.578866 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3705 09:28:17.582007 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3706 09:28:17.582136 ==
3707 09:28:17.585085 Dram Type= 6, Freq= 0, CH_1, rank 1
3708 09:28:17.591772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3709 09:28:17.591904 ==
3710 09:28:17.591997 DQS Delay:
3711 09:28:17.595385 DQS0 = 0, DQS1 = 0
3712 09:28:17.595465 DQM Delay:
3713 09:28:17.598365 DQM0 = 113, DQM1 = 110
3714 09:28:17.598437 DQ Delay:
3715 09:28:17.602353 DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =110
3716 09:28:17.605283 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3717 09:28:17.608526 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3718 09:28:17.612004 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =120
3719 09:28:17.612089
3720 09:28:17.612155
3721 09:28:17.621908 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3722 09:28:17.622065 CH1 RK1: MR19=304, MR18=FA02
3723 09:28:17.628496 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3724 09:28:17.631839 [RxdqsGatingPostProcess] freq 1200
3725 09:28:17.639170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3726 09:28:17.641924 best DQS0 dly(2T, 0.5T) = (0, 11)
3727 09:28:17.645306 best DQS1 dly(2T, 0.5T) = (0, 11)
3728 09:28:17.648602 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3729 09:28:17.651876 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3730 09:28:17.651988 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 09:28:17.655322 best DQS1 dly(2T, 0.5T) = (0, 11)
3732 09:28:17.658674 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 09:28:17.662149 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3734 09:28:17.665731 Pre-setting of DQS Precalculation
3735 09:28:17.672187 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3736 09:28:17.678640 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3737 09:28:17.685314 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3738 09:28:17.685466
3739 09:28:17.685563
3740 09:28:17.688720 [Calibration Summary] 2400 Mbps
3741 09:28:17.688822 CH 0, Rank 0
3742 09:28:17.692183 SW Impedance : PASS
3743 09:28:17.695363 DUTY Scan : NO K
3744 09:28:17.695447 ZQ Calibration : PASS
3745 09:28:17.699103 Jitter Meter : NO K
3746 09:28:17.702160 CBT Training : PASS
3747 09:28:17.702284 Write leveling : PASS
3748 09:28:17.705910 RX DQS gating : PASS
3749 09:28:17.706016 RX DQ/DQS(RDDQC) : PASS
3750 09:28:17.708887 TX DQ/DQS : PASS
3751 09:28:17.712291 RX DATLAT : PASS
3752 09:28:17.712437 RX DQ/DQS(Engine): PASS
3753 09:28:17.716189 TX OE : NO K
3754 09:28:17.716311 All Pass.
3755 09:28:17.716378
3756 09:28:17.719325 CH 0, Rank 1
3757 09:28:17.719430 SW Impedance : PASS
3758 09:28:17.722635 DUTY Scan : NO K
3759 09:28:17.725883 ZQ Calibration : PASS
3760 09:28:17.725975 Jitter Meter : NO K
3761 09:28:17.729154 CBT Training : PASS
3762 09:28:17.732695 Write leveling : PASS
3763 09:28:17.732802 RX DQS gating : PASS
3764 09:28:17.736193 RX DQ/DQS(RDDQC) : PASS
3765 09:28:17.736283 TX DQ/DQS : PASS
3766 09:28:17.739039 RX DATLAT : PASS
3767 09:28:17.742540 RX DQ/DQS(Engine): PASS
3768 09:28:17.742628 TX OE : NO K
3769 09:28:17.745841 All Pass.
3770 09:28:17.745935
3771 09:28:17.746006 CH 1, Rank 0
3772 09:28:17.749631 SW Impedance : PASS
3773 09:28:17.749718 DUTY Scan : NO K
3774 09:28:17.752757 ZQ Calibration : PASS
3775 09:28:17.755884 Jitter Meter : NO K
3776 09:28:17.755970 CBT Training : PASS
3777 09:28:17.759689 Write leveling : PASS
3778 09:28:17.762752 RX DQS gating : PASS
3779 09:28:17.762851 RX DQ/DQS(RDDQC) : PASS
3780 09:28:17.766156 TX DQ/DQS : PASS
3781 09:28:17.769052 RX DATLAT : PASS
3782 09:28:17.769141 RX DQ/DQS(Engine): PASS
3783 09:28:17.772459 TX OE : NO K
3784 09:28:17.772540 All Pass.
3785 09:28:17.772620
3786 09:28:17.775870 CH 1, Rank 1
3787 09:28:17.775949 SW Impedance : PASS
3788 09:28:17.779050 DUTY Scan : NO K
3789 09:28:17.782921 ZQ Calibration : PASS
3790 09:28:17.783022 Jitter Meter : NO K
3791 09:28:17.785743 CBT Training : PASS
3792 09:28:17.785828 Write leveling : PASS
3793 09:28:17.789173 RX DQS gating : PASS
3794 09:28:17.792668 RX DQ/DQS(RDDQC) : PASS
3795 09:28:17.792754 TX DQ/DQS : PASS
3796 09:28:17.795972 RX DATLAT : PASS
3797 09:28:17.799422 RX DQ/DQS(Engine): PASS
3798 09:28:17.799513 TX OE : NO K
3799 09:28:17.802549 All Pass.
3800 09:28:17.802664
3801 09:28:17.802771 DramC Write-DBI off
3802 09:28:17.805762 PER_BANK_REFRESH: Hybrid Mode
3803 09:28:17.805842 TX_TRACKING: ON
3804 09:28:17.816577 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3805 09:28:17.819195 [FAST_K] Save calibration result to emmc
3806 09:28:17.822575 dramc_set_vcore_voltage set vcore to 650000
3807 09:28:17.826237 Read voltage for 600, 5
3808 09:28:17.826325 Vio18 = 0
3809 09:28:17.829402 Vcore = 650000
3810 09:28:17.829487 Vdram = 0
3811 09:28:17.829553 Vddq = 0
3812 09:28:17.832770 Vmddr = 0
3813 09:28:17.836182 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3814 09:28:17.842415 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3815 09:28:17.842533 MEM_TYPE=3, freq_sel=19
3816 09:28:17.846074 sv_algorithm_assistance_LP4_1600
3817 09:28:17.848991 ============ PULL DRAM RESETB DOWN ============
3818 09:28:17.855714 ========== PULL DRAM RESETB DOWN end =========
3819 09:28:17.859295 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3820 09:28:17.862587 ===================================
3821 09:28:17.865835 LPDDR4 DRAM CONFIGURATION
3822 09:28:17.869159 ===================================
3823 09:28:17.869250 EX_ROW_EN[0] = 0x0
3824 09:28:17.872485 EX_ROW_EN[1] = 0x0
3825 09:28:17.875735 LP4Y_EN = 0x0
3826 09:28:17.875822 WORK_FSP = 0x0
3827 09:28:17.879228 WL = 0x2
3828 09:28:17.879338 RL = 0x2
3829 09:28:17.882443 BL = 0x2
3830 09:28:17.882557 RPST = 0x0
3831 09:28:17.886276 RD_PRE = 0x0
3832 09:28:17.886363 WR_PRE = 0x1
3833 09:28:17.889646 WR_PST = 0x0
3834 09:28:17.889726 DBI_WR = 0x0
3835 09:28:17.892636 DBI_RD = 0x0
3836 09:28:17.892715 OTF = 0x1
3837 09:28:17.896221 ===================================
3838 09:28:17.899500 ===================================
3839 09:28:17.903245 ANA top config
3840 09:28:17.905838 ===================================
3841 09:28:17.905917 DLL_ASYNC_EN = 0
3842 09:28:17.909210 ALL_SLAVE_EN = 1
3843 09:28:17.912465 NEW_RANK_MODE = 1
3844 09:28:17.916004 DLL_IDLE_MODE = 1
3845 09:28:17.916091 LP45_APHY_COMB_EN = 1
3846 09:28:17.919155 TX_ODT_DIS = 1
3847 09:28:17.922596 NEW_8X_MODE = 1
3848 09:28:17.925895 ===================================
3849 09:28:17.929398 ===================================
3850 09:28:17.932626 data_rate = 1200
3851 09:28:17.936623 CKR = 1
3852 09:28:17.936708 DQ_P2S_RATIO = 8
3853 09:28:17.939795 ===================================
3854 09:28:17.942777 CA_P2S_RATIO = 8
3855 09:28:17.946133 DQ_CA_OPEN = 0
3856 09:28:17.949399 DQ_SEMI_OPEN = 0
3857 09:28:17.952666 CA_SEMI_OPEN = 0
3858 09:28:17.955909 CA_FULL_RATE = 0
3859 09:28:17.955997 DQ_CKDIV4_EN = 1
3860 09:28:17.959572 CA_CKDIV4_EN = 1
3861 09:28:17.963259 CA_PREDIV_EN = 0
3862 09:28:17.966348 PH8_DLY = 0
3863 09:28:17.969533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3864 09:28:17.969623 DQ_AAMCK_DIV = 4
3865 09:28:17.973299 CA_AAMCK_DIV = 4
3866 09:28:17.976233 CA_ADMCK_DIV = 4
3867 09:28:17.979423 DQ_TRACK_CA_EN = 0
3868 09:28:17.982515 CA_PICK = 600
3869 09:28:17.986127 CA_MCKIO = 600
3870 09:28:17.989240 MCKIO_SEMI = 0
3871 09:28:17.993015 PLL_FREQ = 2288
3872 09:28:17.993121 DQ_UI_PI_RATIO = 32
3873 09:28:17.995850 CA_UI_PI_RATIO = 0
3874 09:28:17.999317 ===================================
3875 09:28:18.003037 ===================================
3876 09:28:18.006046 memory_type:LPDDR4
3877 09:28:18.006147 GP_NUM : 10
3878 09:28:18.009622 SRAM_EN : 1
3879 09:28:18.012919 MD32_EN : 0
3880 09:28:18.016359 ===================================
3881 09:28:18.016452 [ANA_INIT] >>>>>>>>>>>>>>
3882 09:28:18.019678 <<<<<< [CONFIGURE PHASE]: ANA_TX
3883 09:28:18.023082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3884 09:28:18.026003 ===================================
3885 09:28:18.029578 data_rate = 1200,PCW = 0X5800
3886 09:28:18.033219 ===================================
3887 09:28:18.036259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3888 09:28:18.042840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 09:28:18.046672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3890 09:28:18.053335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3891 09:28:18.056554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3892 09:28:18.059579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3893 09:28:18.059682 [ANA_INIT] flow start
3894 09:28:18.063036 [ANA_INIT] PLL >>>>>>>>
3895 09:28:18.066598 [ANA_INIT] PLL <<<<<<<<
3896 09:28:18.066710 [ANA_INIT] MIDPI >>>>>>>>
3897 09:28:18.069463 [ANA_INIT] MIDPI <<<<<<<<
3898 09:28:18.073295 [ANA_INIT] DLL >>>>>>>>
3899 09:28:18.073379 [ANA_INIT] flow end
3900 09:28:18.079522 ============ LP4 DIFF to SE enter ============
3901 09:28:18.083054 ============ LP4 DIFF to SE exit ============
3902 09:28:18.086217 [ANA_INIT] <<<<<<<<<<<<<
3903 09:28:18.090131 [Flow] Enable top DCM control >>>>>
3904 09:28:18.093701 [Flow] Enable top DCM control <<<<<
3905 09:28:18.093788 Enable DLL master slave shuffle
3906 09:28:18.100075 ==============================================================
3907 09:28:18.103279 Gating Mode config
3908 09:28:18.107060 ==============================================================
3909 09:28:18.110083 Config description:
3910 09:28:18.120111 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3911 09:28:18.126738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3912 09:28:18.129979 SELPH_MODE 0: By rank 1: By Phase
3913 09:28:18.136712 ==============================================================
3914 09:28:18.139771 GAT_TRACK_EN = 1
3915 09:28:18.143513 RX_GATING_MODE = 2
3916 09:28:18.143601 RX_GATING_TRACK_MODE = 2
3917 09:28:18.146591 SELPH_MODE = 1
3918 09:28:18.150056 PICG_EARLY_EN = 1
3919 09:28:18.153768 VALID_LAT_VALUE = 1
3920 09:28:18.160021 ==============================================================
3921 09:28:18.163160 Enter into Gating configuration >>>>
3922 09:28:18.166573 Exit from Gating configuration <<<<
3923 09:28:18.170035 Enter into DVFS_PRE_config >>>>>
3924 09:28:18.180036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3925 09:28:18.183178 Exit from DVFS_PRE_config <<<<<
3926 09:28:18.186831 Enter into PICG configuration >>>>
3927 09:28:18.189799 Exit from PICG configuration <<<<
3928 09:28:18.193865 [RX_INPUT] configuration >>>>>
3929 09:28:18.196721 [RX_INPUT] configuration <<<<<
3930 09:28:18.200055 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3931 09:28:18.206718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3932 09:28:18.213492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3933 09:28:18.216887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3934 09:28:18.223846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3935 09:28:18.230371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3936 09:28:18.233886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3937 09:28:18.237042 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3938 09:28:18.243611 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3939 09:28:18.247245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3940 09:28:18.250499 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3941 09:28:18.257247 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 09:28:18.257362 ===================================
3943 09:28:18.260435 LPDDR4 DRAM CONFIGURATION
3944 09:28:18.263741 ===================================
3945 09:28:18.267188 EX_ROW_EN[0] = 0x0
3946 09:28:18.267279 EX_ROW_EN[1] = 0x0
3947 09:28:18.270340 LP4Y_EN = 0x0
3948 09:28:18.270428 WORK_FSP = 0x0
3949 09:28:18.273583 WL = 0x2
3950 09:28:18.273680 RL = 0x2
3951 09:28:18.277435 BL = 0x2
3952 09:28:18.277527 RPST = 0x0
3953 09:28:18.280649 RD_PRE = 0x0
3954 09:28:18.280744 WR_PRE = 0x1
3955 09:28:18.284046 WR_PST = 0x0
3956 09:28:18.287503 DBI_WR = 0x0
3957 09:28:18.287597 DBI_RD = 0x0
3958 09:28:18.290566 OTF = 0x1
3959 09:28:18.294323 ===================================
3960 09:28:18.297563 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3961 09:28:18.300613 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3962 09:28:18.303980 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3963 09:28:18.307191 ===================================
3964 09:28:18.310475 LPDDR4 DRAM CONFIGURATION
3965 09:28:18.313831 ===================================
3966 09:28:18.317177 EX_ROW_EN[0] = 0x10
3967 09:28:18.317261 EX_ROW_EN[1] = 0x0
3968 09:28:18.320416 LP4Y_EN = 0x0
3969 09:28:18.320495 WORK_FSP = 0x0
3970 09:28:18.323937 WL = 0x2
3971 09:28:18.324009 RL = 0x2
3972 09:28:18.327182 BL = 0x2
3973 09:28:18.327255 RPST = 0x0
3974 09:28:18.330603 RD_PRE = 0x0
3975 09:28:18.330702 WR_PRE = 0x1
3976 09:28:18.334230 WR_PST = 0x0
3977 09:28:18.334307 DBI_WR = 0x0
3978 09:28:18.337358 DBI_RD = 0x0
3979 09:28:18.337429 OTF = 0x1
3980 09:28:18.340751 ===================================
3981 09:28:18.347104 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3982 09:28:18.351693 nWR fixed to 30
3983 09:28:18.355272 [ModeRegInit_LP4] CH0 RK0
3984 09:28:18.355352 [ModeRegInit_LP4] CH0 RK1
3985 09:28:18.358748 [ModeRegInit_LP4] CH1 RK0
3986 09:28:18.361932 [ModeRegInit_LP4] CH1 RK1
3987 09:28:18.362016 match AC timing 17
3988 09:28:18.368670 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3989 09:28:18.371803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3990 09:28:18.375422 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3991 09:28:18.382224 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3992 09:28:18.385165 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3993 09:28:18.385291 ==
3994 09:28:18.388627 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 09:28:18.392068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 09:28:18.392157 ==
3997 09:28:18.399020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3998 09:28:18.405141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3999 09:28:18.408308 [CA 0] Center 36 (6~66) winsize 61
4000 09:28:18.412227 [CA 1] Center 36 (6~66) winsize 61
4001 09:28:18.415571 [CA 2] Center 34 (4~65) winsize 62
4002 09:28:18.418671 [CA 3] Center 34 (4~64) winsize 61
4003 09:28:18.421869 [CA 4] Center 34 (4~64) winsize 61
4004 09:28:18.425930 [CA 5] Center 33 (3~64) winsize 62
4005 09:28:18.426024
4006 09:28:18.428755 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4007 09:28:18.428828
4008 09:28:18.432407 [CATrainingPosCal] consider 1 rank data
4009 09:28:18.435355 u2DelayCellTimex100 = 270/100 ps
4010 09:28:18.438986 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4011 09:28:18.442230 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 09:28:18.445778 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4013 09:28:18.448958 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4014 09:28:18.452078 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4015 09:28:18.455609 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 09:28:18.455693
4017 09:28:18.458468 CA PerBit enable=1, Macro0, CA PI delay=33
4018 09:28:18.462217
4019 09:28:18.462290 [CBTSetCACLKResult] CA Dly = 33
4020 09:28:18.465498 CS Dly: 4 (0~35)
4021 09:28:18.465573 ==
4022 09:28:18.468565 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 09:28:18.471989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 09:28:18.472069 ==
4025 09:28:18.478879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4026 09:28:18.485739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4027 09:28:18.488885 [CA 0] Center 36 (6~67) winsize 62
4028 09:28:18.492080 [CA 1] Center 36 (6~66) winsize 61
4029 09:28:18.495510 [CA 2] Center 34 (4~65) winsize 62
4030 09:28:18.498943 [CA 3] Center 34 (4~65) winsize 62
4031 09:28:18.502450 [CA 4] Center 33 (3~64) winsize 62
4032 09:28:18.505798 [CA 5] Center 33 (3~64) winsize 62
4033 09:28:18.505896
4034 09:28:18.508981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4035 09:28:18.509084
4036 09:28:18.512868 [CATrainingPosCal] consider 2 rank data
4037 09:28:18.515766 u2DelayCellTimex100 = 270/100 ps
4038 09:28:18.519386 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4039 09:28:18.522263 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4040 09:28:18.525920 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4041 09:28:18.529207 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4042 09:28:18.532366 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4043 09:28:18.535964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4044 09:28:18.536055
4045 09:28:18.539425 CA PerBit enable=1, Macro0, CA PI delay=33
4046 09:28:18.539521
4047 09:28:18.542394 [CBTSetCACLKResult] CA Dly = 33
4048 09:28:18.545678 CS Dly: 4 (0~36)
4049 09:28:18.545766
4050 09:28:18.548924 ----->DramcWriteLeveling(PI) begin...
4051 09:28:18.549012 ==
4052 09:28:18.552617 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 09:28:18.555661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 09:28:18.555749 ==
4055 09:28:18.558921 Write leveling (Byte 0): 33 => 33
4056 09:28:18.562238 Write leveling (Byte 1): 29 => 29
4057 09:28:18.565703 DramcWriteLeveling(PI) end<-----
4058 09:28:18.565790
4059 09:28:18.565854 ==
4060 09:28:18.569306 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 09:28:18.572194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 09:28:18.572280 ==
4063 09:28:18.575731 [Gating] SW mode calibration
4064 09:28:18.582146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4065 09:28:18.588835 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4066 09:28:18.592096 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 09:28:18.598913 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 09:28:18.602357 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4069 09:28:18.605669 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4070 09:28:18.611880 0 9 16 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 1)
4071 09:28:18.615283 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4072 09:28:18.618675 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 09:28:18.625505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 09:28:18.628575 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 09:28:18.631978 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 09:28:18.635431 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 09:28:18.642259 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4078 09:28:18.645255 0 10 16 | B1->B0 | 3131 3c3c | 0 0 | (1 1) (0 0)
4079 09:28:18.648628 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4080 09:28:18.655651 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 09:28:18.658655 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 09:28:18.662064 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 09:28:18.668585 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 09:28:18.672204 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 09:28:18.675818 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 09:28:18.681874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4087 09:28:18.685744 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4088 09:28:18.688756 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 09:28:18.695614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 09:28:18.698784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 09:28:18.702338 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 09:28:18.708655 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 09:28:18.712029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 09:28:18.715481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 09:28:18.718649 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 09:28:18.726085 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 09:28:18.729070 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 09:28:18.732498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 09:28:18.739112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 09:28:18.742718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 09:28:18.745701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 09:28:18.752481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4103 09:28:18.752597 Total UI for P1: 0, mck2ui 16
4104 09:28:18.758935 best dqsien dly found for B0: ( 0, 13, 14)
4105 09:28:18.762664 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 09:28:18.765709 Total UI for P1: 0, mck2ui 16
4107 09:28:18.769359 best dqsien dly found for B1: ( 0, 13, 16)
4108 09:28:18.772405 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4109 09:28:18.775793 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4110 09:28:18.775888
4111 09:28:18.779323 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4112 09:28:18.782387 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4113 09:28:18.785832 [Gating] SW calibration Done
4114 09:28:18.785932 ==
4115 09:28:18.789556 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 09:28:18.792464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 09:28:18.792573 ==
4118 09:28:18.795900 RX Vref Scan: 0
4119 09:28:18.795989
4120 09:28:18.799171 RX Vref 0 -> 0, step: 1
4121 09:28:18.799258
4122 09:28:18.799343 RX Delay -230 -> 252, step: 16
4123 09:28:18.805997 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4124 09:28:18.809373 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4125 09:28:18.812960 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4126 09:28:18.816374 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4127 09:28:18.822598 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4128 09:28:18.826021 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4129 09:28:18.829418 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4130 09:28:18.832851 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4131 09:28:18.836126 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4132 09:28:18.842589 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4133 09:28:18.846355 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4134 09:28:18.849560 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4135 09:28:18.852609 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4136 09:28:18.859625 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4137 09:28:18.862561 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4138 09:28:18.866048 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4139 09:28:18.866160 ==
4140 09:28:18.869748 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 09:28:18.872738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 09:28:18.872845 ==
4143 09:28:18.876084 DQS Delay:
4144 09:28:18.876187 DQS0 = 0, DQS1 = 0
4145 09:28:18.879278 DQM Delay:
4146 09:28:18.879381 DQM0 = 39, DQM1 = 32
4147 09:28:18.879471 DQ Delay:
4148 09:28:18.883169 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4149 09:28:18.886079 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4150 09:28:18.889424 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4151 09:28:18.892754 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4152 09:28:18.892842
4153 09:28:18.892907
4154 09:28:18.896179 ==
4155 09:28:18.896280 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 09:28:18.902976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 09:28:18.903076 ==
4158 09:28:18.903142
4159 09:28:18.903202
4160 09:28:18.905955 TX Vref Scan disable
4161 09:28:18.906042 == TX Byte 0 ==
4162 09:28:18.909568 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4163 09:28:18.916262 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4164 09:28:18.916368 == TX Byte 1 ==
4165 09:28:18.920038 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4166 09:28:18.925991 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4167 09:28:18.926109 ==
4168 09:28:18.929698 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 09:28:18.933066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 09:28:18.933162 ==
4171 09:28:18.933229
4172 09:28:18.933289
4173 09:28:18.936120 TX Vref Scan disable
4174 09:28:18.939840 == TX Byte 0 ==
4175 09:28:18.943275 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4176 09:28:18.946481 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4177 09:28:18.949762 == TX Byte 1 ==
4178 09:28:18.953430 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4179 09:28:18.956039 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4180 09:28:18.956130
4181 09:28:18.959864 [DATLAT]
4182 09:28:18.959955 Freq=600, CH0 RK0
4183 09:28:18.960041
4184 09:28:18.963166 DATLAT Default: 0x9
4185 09:28:18.963258 0, 0xFFFF, sum = 0
4186 09:28:18.966235 1, 0xFFFF, sum = 0
4187 09:28:18.966323 2, 0xFFFF, sum = 0
4188 09:28:18.969675 3, 0xFFFF, sum = 0
4189 09:28:18.969828 4, 0xFFFF, sum = 0
4190 09:28:18.973010 5, 0xFFFF, sum = 0
4191 09:28:18.973194 6, 0xFFFF, sum = 0
4192 09:28:18.975981 7, 0xFFFF, sum = 0
4193 09:28:18.976098 8, 0x0, sum = 1
4194 09:28:18.979695 9, 0x0, sum = 2
4195 09:28:18.979802 10, 0x0, sum = 3
4196 09:28:18.982813 11, 0x0, sum = 4
4197 09:28:18.982901 best_step = 9
4198 09:28:18.982978
4199 09:28:18.983041 ==
4200 09:28:18.986141 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 09:28:18.989440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 09:28:18.989563 ==
4203 09:28:18.992885 RX Vref Scan: 1
4204 09:28:18.992985
4205 09:28:18.996267 RX Vref 0 -> 0, step: 1
4206 09:28:18.996377
4207 09:28:18.996467 RX Delay -195 -> 252, step: 8
4208 09:28:18.996555
4209 09:28:18.999821 Set Vref, RX VrefLevel [Byte0]: 53
4210 09:28:19.003337 [Byte1]: 51
4211 09:28:19.007316
4212 09:28:19.007425 Final RX Vref Byte 0 = 53 to rank0
4213 09:28:19.010992 Final RX Vref Byte 1 = 51 to rank0
4214 09:28:19.013930 Final RX Vref Byte 0 = 53 to rank1
4215 09:28:19.017375 Final RX Vref Byte 1 = 51 to rank1==
4216 09:28:19.020791 Dram Type= 6, Freq= 0, CH_0, rank 0
4217 09:28:19.027711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 09:28:19.027811 ==
4219 09:28:19.027883 DQS Delay:
4220 09:28:19.027942 DQS0 = 0, DQS1 = 0
4221 09:28:19.031096 DQM Delay:
4222 09:28:19.031170 DQM0 = 42, DQM1 = 34
4223 09:28:19.033967 DQ Delay:
4224 09:28:19.037805 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4225 09:28:19.037930 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4226 09:28:19.040713 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4227 09:28:19.044321 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4228 09:28:19.044428
4229 09:28:19.047550
4230 09:28:19.054282 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4231 09:28:19.058243 CH0 RK0: MR19=808, MR18=4120
4232 09:28:19.064440 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4233 09:28:19.064540
4234 09:28:19.067730 ----->DramcWriteLeveling(PI) begin...
4235 09:28:19.067902 ==
4236 09:28:19.070833 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 09:28:19.074071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 09:28:19.074145 ==
4239 09:28:19.077662 Write leveling (Byte 0): 35 => 35
4240 09:28:19.081010 Write leveling (Byte 1): 29 => 29
4241 09:28:19.084273 DramcWriteLeveling(PI) end<-----
4242 09:28:19.084388
4243 09:28:19.084482 ==
4244 09:28:19.087460 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 09:28:19.091057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 09:28:19.091139 ==
4247 09:28:19.094567 [Gating] SW mode calibration
4248 09:28:19.101050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4249 09:28:19.107641 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4250 09:28:19.111321 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 09:28:19.114621 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 09:28:19.121053 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4253 09:28:19.124303 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
4254 09:28:19.127677 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4255 09:28:19.134575 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4256 09:28:19.137952 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 09:28:19.141044 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 09:28:19.144441 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 09:28:19.151336 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 09:28:19.154261 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 09:28:19.158030 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4262 09:28:19.164804 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4263 09:28:19.167766 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 09:28:19.170961 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 09:28:19.177591 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 09:28:19.180829 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 09:28:19.184968 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 09:28:19.190982 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 09:28:19.194898 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4270 09:28:19.197892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4271 09:28:19.204849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 09:28:19.207898 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 09:28:19.211239 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 09:28:19.218306 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 09:28:19.221310 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 09:28:19.224700 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 09:28:19.231073 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 09:28:19.234582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 09:28:19.237968 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 09:28:19.241256 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 09:28:19.247769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 09:28:19.251191 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 09:28:19.255001 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 09:28:19.261448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4285 09:28:19.265115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 09:28:19.268376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4287 09:28:19.271356 Total UI for P1: 0, mck2ui 16
4288 09:28:19.275173 best dqsien dly found for B0: ( 0, 13, 14)
4289 09:28:19.281209 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 09:28:19.281333 Total UI for P1: 0, mck2ui 16
4291 09:28:19.288093 best dqsien dly found for B1: ( 0, 13, 16)
4292 09:28:19.291681 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4293 09:28:19.295115 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4294 09:28:19.295217
4295 09:28:19.298202 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4296 09:28:19.301567 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4297 09:28:19.305232 [Gating] SW calibration Done
4298 09:28:19.305322 ==
4299 09:28:19.307951 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 09:28:19.311530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 09:28:19.311621 ==
4302 09:28:19.314912 RX Vref Scan: 0
4303 09:28:19.314998
4304 09:28:19.315064 RX Vref 0 -> 0, step: 1
4305 09:28:19.315124
4306 09:28:19.317812 RX Delay -230 -> 252, step: 16
4307 09:28:19.321251 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4308 09:28:19.328289 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4309 09:28:19.331442 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4310 09:28:19.335062 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4311 09:28:19.338151 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4312 09:28:19.341540 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4313 09:28:19.348570 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4314 09:28:19.351966 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4315 09:28:19.355431 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4316 09:28:19.358346 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4317 09:28:19.365066 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4318 09:28:19.368203 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4319 09:28:19.371770 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4320 09:28:19.374877 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4321 09:28:19.381806 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4322 09:28:19.385146 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4323 09:28:19.385253 ==
4324 09:28:19.388383 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 09:28:19.391465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 09:28:19.391553 ==
4327 09:28:19.391619 DQS Delay:
4328 09:28:19.395039 DQS0 = 0, DQS1 = 0
4329 09:28:19.395123 DQM Delay:
4330 09:28:19.398935 DQM0 = 41, DQM1 = 34
4331 09:28:19.399037 DQ Delay:
4332 09:28:19.401823 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4333 09:28:19.405484 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4334 09:28:19.409215 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4335 09:28:19.411801 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4336 09:28:19.411893
4337 09:28:19.411960
4338 09:28:19.412020 ==
4339 09:28:19.415106 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 09:28:19.418562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 09:28:19.421660 ==
4342 09:28:19.421748
4343 09:28:19.421813
4344 09:28:19.421874 TX Vref Scan disable
4345 09:28:19.425058 == TX Byte 0 ==
4346 09:28:19.428694 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4347 09:28:19.431886 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4348 09:28:19.434967 == TX Byte 1 ==
4349 09:28:19.438412 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4350 09:28:19.442123 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4351 09:28:19.445499 ==
4352 09:28:19.445593 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 09:28:19.451990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 09:28:19.452101 ==
4355 09:28:19.452172
4356 09:28:19.452232
4357 09:28:19.455170 TX Vref Scan disable
4358 09:28:19.455256 == TX Byte 0 ==
4359 09:28:19.461989 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4360 09:28:19.465146 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4361 09:28:19.465295 == TX Byte 1 ==
4362 09:28:19.471624 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4363 09:28:19.475449 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4364 09:28:19.475547
4365 09:28:19.475613 [DATLAT]
4366 09:28:19.478556 Freq=600, CH0 RK1
4367 09:28:19.478641
4368 09:28:19.478704 DATLAT Default: 0x9
4369 09:28:19.482102 0, 0xFFFF, sum = 0
4370 09:28:19.482188 1, 0xFFFF, sum = 0
4371 09:28:19.485147 2, 0xFFFF, sum = 0
4372 09:28:19.485239 3, 0xFFFF, sum = 0
4373 09:28:19.488718 4, 0xFFFF, sum = 0
4374 09:28:19.488805 5, 0xFFFF, sum = 0
4375 09:28:19.492092 6, 0xFFFF, sum = 0
4376 09:28:19.492177 7, 0xFFFF, sum = 0
4377 09:28:19.495629 8, 0x0, sum = 1
4378 09:28:19.495715 9, 0x0, sum = 2
4379 09:28:19.499132 10, 0x0, sum = 3
4380 09:28:19.499219 11, 0x0, sum = 4
4381 09:28:19.501858 best_step = 9
4382 09:28:19.501942
4383 09:28:19.502007 ==
4384 09:28:19.505205 Dram Type= 6, Freq= 0, CH_0, rank 1
4385 09:28:19.508673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 09:28:19.508776 ==
4387 09:28:19.512093 RX Vref Scan: 0
4388 09:28:19.512179
4389 09:28:19.512244 RX Vref 0 -> 0, step: 1
4390 09:28:19.512305
4391 09:28:19.514895 RX Delay -179 -> 252, step: 8
4392 09:28:19.522143 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4393 09:28:19.525461 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4394 09:28:19.528781 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4395 09:28:19.532467 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4396 09:28:19.538862 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4397 09:28:19.542061 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4398 09:28:19.545443 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4399 09:28:19.548796 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4400 09:28:19.552243 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4401 09:28:19.558919 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4402 09:28:19.562226 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4403 09:28:19.565536 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4404 09:28:19.569161 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4405 09:28:19.576012 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4406 09:28:19.578953 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4407 09:28:19.582422 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4408 09:28:19.582510 ==
4409 09:28:19.585773 Dram Type= 6, Freq= 0, CH_0, rank 1
4410 09:28:19.589291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 09:28:19.589383 ==
4412 09:28:19.592934 DQS Delay:
4413 09:28:19.593020 DQS0 = 0, DQS1 = 0
4414 09:28:19.595944 DQM Delay:
4415 09:28:19.596028 DQM0 = 39, DQM1 = 33
4416 09:28:19.596092 DQ Delay:
4417 09:28:19.599220 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4418 09:28:19.602334 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4419 09:28:19.606052 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4420 09:28:19.609145 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4421 09:28:19.609231
4422 09:28:19.609296
4423 09:28:19.618957 [DQSOSCAuto] RK1, (LSB)MR18= 0x5134, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4424 09:28:19.622357 CH0 RK1: MR19=808, MR18=5134
4425 09:28:19.625626 CH0_RK1: MR19=0x808, MR18=0x5134, DQSOSC=394, MR23=63, INC=168, DEC=112
4426 09:28:19.629434 [RxdqsGatingPostProcess] freq 600
4427 09:28:19.635771 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4428 09:28:19.639127 Pre-setting of DQS Precalculation
4429 09:28:19.642519 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4430 09:28:19.642614 ==
4431 09:28:19.645867 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 09:28:19.652737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 09:28:19.652847 ==
4434 09:28:19.656462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 09:28:19.662398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4436 09:28:19.666277 [CA 0] Center 35 (5~65) winsize 61
4437 09:28:19.669380 [CA 1] Center 35 (5~66) winsize 62
4438 09:28:19.672397 [CA 2] Center 34 (4~65) winsize 62
4439 09:28:19.675615 [CA 3] Center 34 (3~65) winsize 63
4440 09:28:19.679166 [CA 4] Center 34 (3~65) winsize 63
4441 09:28:19.682275 [CA 5] Center 33 (3~64) winsize 62
4442 09:28:19.682363
4443 09:28:19.685872 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4444 09:28:19.685967
4445 09:28:19.689340 [CATrainingPosCal] consider 1 rank data
4446 09:28:19.692840 u2DelayCellTimex100 = 270/100 ps
4447 09:28:19.696041 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4448 09:28:19.699300 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4449 09:28:19.705637 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 09:28:19.708940 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4451 09:28:19.712685 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4452 09:28:19.715991 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 09:28:19.716079
4454 09:28:19.719038 CA PerBit enable=1, Macro0, CA PI delay=33
4455 09:28:19.719123
4456 09:28:19.722611 [CBTSetCACLKResult] CA Dly = 33
4457 09:28:19.722699 CS Dly: 4 (0~35)
4458 09:28:19.722790 ==
4459 09:28:19.725847 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 09:28:19.732633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 09:28:19.732734 ==
4462 09:28:19.735750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4463 09:28:19.742573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4464 09:28:19.745751 [CA 0] Center 35 (5~66) winsize 62
4465 09:28:19.749398 [CA 1] Center 36 (6~66) winsize 61
4466 09:28:19.752898 [CA 2] Center 34 (4~65) winsize 62
4467 09:28:19.755973 [CA 3] Center 34 (3~65) winsize 63
4468 09:28:19.759169 [CA 4] Center 34 (3~65) winsize 63
4469 09:28:19.762946 [CA 5] Center 33 (3~64) winsize 62
4470 09:28:19.763084
4471 09:28:19.766035 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4472 09:28:19.766118
4473 09:28:19.769156 [CATrainingPosCal] consider 2 rank data
4474 09:28:19.772394 u2DelayCellTimex100 = 270/100 ps
4475 09:28:19.775756 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4476 09:28:19.779712 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4477 09:28:19.785848 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4478 09:28:19.789362 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4479 09:28:19.792470 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4480 09:28:19.795706 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4481 09:28:19.795797
4482 09:28:19.799755 CA PerBit enable=1, Macro0, CA PI delay=33
4483 09:28:19.799924
4484 09:28:19.802946 [CBTSetCACLKResult] CA Dly = 33
4485 09:28:19.803070 CS Dly: 3 (0~34)
4486 09:28:19.803135
4487 09:28:19.806369 ----->DramcWriteLeveling(PI) begin...
4488 09:28:19.806456 ==
4489 09:28:19.809407 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 09:28:19.816184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 09:28:19.816289 ==
4492 09:28:19.819877 Write leveling (Byte 0): 28 => 28
4493 09:28:19.822554 Write leveling (Byte 1): 31 => 31
4494 09:28:19.822639 DramcWriteLeveling(PI) end<-----
4495 09:28:19.826133
4496 09:28:19.826220 ==
4497 09:28:19.829122 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 09:28:19.832664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 09:28:19.832753 ==
4500 09:28:19.835872 [Gating] SW mode calibration
4501 09:28:19.842580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4502 09:28:19.846014 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4503 09:28:19.852570 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4504 09:28:19.856048 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 09:28:19.859973 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4506 09:28:19.866212 0 9 12 | B1->B0 | 3535 3333 | 0 0 | (0 1) (0 1)
4507 09:28:19.869274 0 9 16 | B1->B0 | 2929 2b2b | 0 0 | (0 0) (0 0)
4508 09:28:19.872555 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 09:28:19.879829 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 09:28:19.882401 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 09:28:19.885941 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 09:28:19.892472 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 09:28:19.895844 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 09:28:19.899588 0 10 12 | B1->B0 | 2828 2c2c | 1 0 | (0 0) (0 0)
4515 09:28:19.905933 0 10 16 | B1->B0 | 3d3d 4545 | 0 0 | (1 1) (0 0)
4516 09:28:19.908987 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 09:28:19.912527 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 09:28:19.916130 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 09:28:19.922620 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 09:28:19.926051 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 09:28:19.929299 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 09:28:19.936125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 09:28:19.939234 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4524 09:28:19.942663 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 09:28:19.949256 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 09:28:19.953178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 09:28:19.956365 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 09:28:19.962596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 09:28:19.965941 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 09:28:19.969691 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 09:28:19.975940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 09:28:19.979436 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 09:28:19.982755 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 09:28:19.989613 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 09:28:19.992981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 09:28:19.996043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 09:28:19.999584 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 09:28:20.006097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4539 09:28:20.009484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 09:28:20.012592 Total UI for P1: 0, mck2ui 16
4541 09:28:20.016178 best dqsien dly found for B0: ( 0, 13, 12)
4542 09:28:20.019269 Total UI for P1: 0, mck2ui 16
4543 09:28:20.023386 best dqsien dly found for B1: ( 0, 13, 12)
4544 09:28:20.026345 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4545 09:28:20.029580 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4546 09:28:20.029686
4547 09:28:20.033147 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4548 09:28:20.036415 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4549 09:28:20.039577 [Gating] SW calibration Done
4550 09:28:20.039688 ==
4551 09:28:20.042825 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 09:28:20.046188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 09:28:20.049614 ==
4554 09:28:20.049723 RX Vref Scan: 0
4555 09:28:20.049829
4556 09:28:20.053036 RX Vref 0 -> 0, step: 1
4557 09:28:20.053139
4558 09:28:20.056215 RX Delay -230 -> 252, step: 16
4559 09:28:20.060176 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4560 09:28:20.063092 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4561 09:28:20.066273 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4562 09:28:20.069983 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4563 09:28:20.076568 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4564 09:28:20.079808 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4565 09:28:20.082986 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4566 09:28:20.086441 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4567 09:28:20.092966 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4568 09:28:20.096444 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4569 09:28:20.099773 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4570 09:28:20.103054 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4571 09:28:20.109592 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4572 09:28:20.112970 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4573 09:28:20.116587 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4574 09:28:20.120090 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4575 09:28:20.120184 ==
4576 09:28:20.123012 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 09:28:20.130097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 09:28:20.130196 ==
4579 09:28:20.130263 DQS Delay:
4580 09:28:20.130323 DQS0 = 0, DQS1 = 0
4581 09:28:20.132935 DQM Delay:
4582 09:28:20.133019 DQM0 = 43, DQM1 = 35
4583 09:28:20.136312 DQ Delay:
4584 09:28:20.139949 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4585 09:28:20.140062 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4586 09:28:20.143291 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4587 09:28:20.146746 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4588 09:28:20.149859
4589 09:28:20.149960
4590 09:28:20.150070 ==
4591 09:28:20.153811 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 09:28:20.156402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 09:28:20.156489 ==
4594 09:28:20.156555
4595 09:28:20.156615
4596 09:28:20.159899 TX Vref Scan disable
4597 09:28:20.159981 == TX Byte 0 ==
4598 09:28:20.166747 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4599 09:28:20.169839 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4600 09:28:20.169926 == TX Byte 1 ==
4601 09:28:20.176787 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4602 09:28:20.180184 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4603 09:28:20.180277 ==
4604 09:28:20.183101 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 09:28:20.186475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 09:28:20.186572 ==
4607 09:28:20.186638
4608 09:28:20.186698
4609 09:28:20.190175 TX Vref Scan disable
4610 09:28:20.193184 == TX Byte 0 ==
4611 09:28:20.196639 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4612 09:28:20.200090 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4613 09:28:20.203393 == TX Byte 1 ==
4614 09:28:20.206617 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4615 09:28:20.210055 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4616 09:28:20.210168
4617 09:28:20.213106 [DATLAT]
4618 09:28:20.213191 Freq=600, CH1 RK0
4619 09:28:20.213257
4620 09:28:20.216864 DATLAT Default: 0x9
4621 09:28:20.216949 0, 0xFFFF, sum = 0
4622 09:28:20.219943 1, 0xFFFF, sum = 0
4623 09:28:20.220066 2, 0xFFFF, sum = 0
4624 09:28:20.223280 3, 0xFFFF, sum = 0
4625 09:28:20.223361 4, 0xFFFF, sum = 0
4626 09:28:20.226659 5, 0xFFFF, sum = 0
4627 09:28:20.226781 6, 0xFFFF, sum = 0
4628 09:28:20.229896 7, 0xFFFF, sum = 0
4629 09:28:20.229973 8, 0x0, sum = 1
4630 09:28:20.233445 9, 0x0, sum = 2
4631 09:28:20.233528 10, 0x0, sum = 3
4632 09:28:20.236550 11, 0x0, sum = 4
4633 09:28:20.236627 best_step = 9
4634 09:28:20.236687
4635 09:28:20.236744 ==
4636 09:28:20.240256 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 09:28:20.243872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 09:28:20.243963 ==
4639 09:28:20.246893 RX Vref Scan: 1
4640 09:28:20.246977
4641 09:28:20.249893 RX Vref 0 -> 0, step: 1
4642 09:28:20.249978
4643 09:28:20.250042 RX Delay -195 -> 252, step: 8
4644 09:28:20.253801
4645 09:28:20.253887 Set Vref, RX VrefLevel [Byte0]: 58
4646 09:28:20.256938 [Byte1]: 53
4647 09:28:20.261893
4648 09:28:20.261983 Final RX Vref Byte 0 = 58 to rank0
4649 09:28:20.264802 Final RX Vref Byte 1 = 53 to rank0
4650 09:28:20.268246 Final RX Vref Byte 0 = 58 to rank1
4651 09:28:20.271634 Final RX Vref Byte 1 = 53 to rank1==
4652 09:28:20.274989 Dram Type= 6, Freq= 0, CH_1, rank 0
4653 09:28:20.281611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 09:28:20.281735 ==
4655 09:28:20.281832 DQS Delay:
4656 09:28:20.281924 DQS0 = 0, DQS1 = 0
4657 09:28:20.285158 DQM Delay:
4658 09:28:20.285457 DQM0 = 40, DQM1 = 34
4659 09:28:20.288524 DQ Delay:
4660 09:28:20.291807 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4661 09:28:20.291889 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4662 09:28:20.295104 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4663 09:28:20.298264 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4664 09:28:20.301964
4665 09:28:20.302042
4666 09:28:20.308206 [DQSOSCAuto] RK0, (LSB)MR18= 0x490f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4667 09:28:20.311799 CH1 RK0: MR19=808, MR18=490F
4668 09:28:20.318344 CH1_RK0: MR19=0x808, MR18=0x490F, DQSOSC=396, MR23=63, INC=167, DEC=111
4669 09:28:20.318436
4670 09:28:20.321393 ----->DramcWriteLeveling(PI) begin...
4671 09:28:20.321466 ==
4672 09:28:20.325102 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 09:28:20.328751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 09:28:20.328827 ==
4675 09:28:20.332231 Write leveling (Byte 0): 29 => 29
4676 09:28:20.334874 Write leveling (Byte 1): 33 => 33
4677 09:28:20.338236 DramcWriteLeveling(PI) end<-----
4678 09:28:20.338312
4679 09:28:20.338374 ==
4680 09:28:20.341695 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 09:28:20.345043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 09:28:20.345134 ==
4683 09:28:20.348153 [Gating] SW mode calibration
4684 09:28:20.354931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4685 09:28:20.361375 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4686 09:28:20.365210 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4687 09:28:20.368330 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4688 09:28:20.374904 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4689 09:28:20.378333 0 9 12 | B1->B0 | 3232 2e2e | 0 0 | (1 1) (1 1)
4690 09:28:20.382011 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4691 09:28:20.388406 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4692 09:28:20.391777 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 09:28:20.395310 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 09:28:20.401932 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 09:28:20.405021 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 09:28:20.408273 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4697 09:28:20.415467 0 10 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
4698 09:28:20.418459 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4699 09:28:20.422121 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 09:28:20.425620 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 09:28:20.431683 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 09:28:20.435267 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 09:28:20.438540 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 09:28:20.445301 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 09:28:20.448328 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 09:28:20.452259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 09:28:20.458303 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 09:28:20.461922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 09:28:20.465030 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 09:28:20.472017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 09:28:20.474996 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 09:28:20.478186 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 09:28:20.484938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 09:28:20.488391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 09:28:20.491996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 09:28:20.498880 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 09:28:20.502068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 09:28:20.505028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 09:28:20.508366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 09:28:20.515275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4721 09:28:20.518620 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4722 09:28:20.521722 Total UI for P1: 0, mck2ui 16
4723 09:28:20.525193 best dqsien dly found for B0: ( 0, 13, 8)
4724 09:28:20.528462 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 09:28:20.532923 Total UI for P1: 0, mck2ui 16
4726 09:28:20.535134 best dqsien dly found for B1: ( 0, 13, 14)
4727 09:28:20.539046 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4728 09:28:20.542319 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4729 09:28:20.542412
4730 09:28:20.548666 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4731 09:28:20.551893 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4732 09:28:20.555494 [Gating] SW calibration Done
4733 09:28:20.555582 ==
4734 09:28:20.558796 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 09:28:20.562065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 09:28:20.562152 ==
4737 09:28:20.562217 RX Vref Scan: 0
4738 09:28:20.562277
4739 09:28:20.565344 RX Vref 0 -> 0, step: 1
4740 09:28:20.565429
4741 09:28:20.568799 RX Delay -230 -> 252, step: 16
4742 09:28:20.571912 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4743 09:28:20.575147 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4744 09:28:20.581951 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4745 09:28:20.585372 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4746 09:28:20.588476 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4747 09:28:20.591936 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4748 09:28:20.595408 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4749 09:28:20.601876 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4750 09:28:20.605343 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4751 09:28:20.608658 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4752 09:28:20.612029 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4753 09:28:20.618879 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4754 09:28:20.621960 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4755 09:28:20.625479 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4756 09:28:20.628900 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4757 09:28:20.635688 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4758 09:28:20.635792 ==
4759 09:28:20.638880 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 09:28:20.642442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 09:28:20.642534 ==
4762 09:28:20.642601 DQS Delay:
4763 09:28:20.645673 DQS0 = 0, DQS1 = 0
4764 09:28:20.645760 DQM Delay:
4765 09:28:20.649052 DQM0 = 42, DQM1 = 37
4766 09:28:20.649138 DQ Delay:
4767 09:28:20.652171 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4768 09:28:20.655251 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4769 09:28:20.658592 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4770 09:28:20.662148 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4771 09:28:20.662264
4772 09:28:20.662366
4773 09:28:20.662425 ==
4774 09:28:20.665281 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 09:28:20.669025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 09:28:20.669140 ==
4777 09:28:20.669212
4778 09:28:20.669274
4779 09:28:20.671958 TX Vref Scan disable
4780 09:28:20.675786 == TX Byte 0 ==
4781 09:28:20.678886 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4782 09:28:20.682360 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4783 09:28:20.685665 == TX Byte 1 ==
4784 09:28:20.688969 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4785 09:28:20.692183 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4786 09:28:20.692292 ==
4787 09:28:20.695398 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 09:28:20.699187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 09:28:20.702104 ==
4790 09:28:20.702219
4791 09:28:20.702288
4792 09:28:20.702379 TX Vref Scan disable
4793 09:28:20.706081 == TX Byte 0 ==
4794 09:28:20.709689 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4795 09:28:20.716009 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4796 09:28:20.716198 == TX Byte 1 ==
4797 09:28:20.719925 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4798 09:28:20.722883 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4799 09:28:20.726980
4800 09:28:20.727195 [DATLAT]
4801 09:28:20.727353 Freq=600, CH1 RK1
4802 09:28:20.727539
4803 09:28:20.729685 DATLAT Default: 0x9
4804 09:28:20.729795 0, 0xFFFF, sum = 0
4805 09:28:20.732771 1, 0xFFFF, sum = 0
4806 09:28:20.732880 2, 0xFFFF, sum = 0
4807 09:28:20.736384 3, 0xFFFF, sum = 0
4808 09:28:20.736500 4, 0xFFFF, sum = 0
4809 09:28:20.739251 5, 0xFFFF, sum = 0
4810 09:28:20.742956 6, 0xFFFF, sum = 0
4811 09:28:20.743146 7, 0xFFFF, sum = 0
4812 09:28:20.743219 8, 0x0, sum = 1
4813 09:28:20.746359 9, 0x0, sum = 2
4814 09:28:20.746463 10, 0x0, sum = 3
4815 09:28:20.749911 11, 0x0, sum = 4
4816 09:28:20.750008 best_step = 9
4817 09:28:20.750074
4818 09:28:20.750135 ==
4819 09:28:20.753058 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 09:28:20.759735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 09:28:20.759884 ==
4822 09:28:20.759952 RX Vref Scan: 0
4823 09:28:20.760014
4824 09:28:20.762981 RX Vref 0 -> 0, step: 1
4825 09:28:20.763159
4826 09:28:20.766244 RX Delay -179 -> 252, step: 8
4827 09:28:20.769646 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4828 09:28:20.776277 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4829 09:28:20.779627 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4830 09:28:20.783134 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4831 09:28:20.786135 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4832 09:28:20.790394 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4833 09:28:20.796376 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4834 09:28:20.800137 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4835 09:28:20.803218 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4836 09:28:20.806476 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4837 09:28:20.809653 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4838 09:28:20.816424 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4839 09:28:20.819930 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4840 09:28:20.823080 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4841 09:28:20.826391 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4842 09:28:20.832862 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4843 09:28:20.832998 ==
4844 09:28:20.836221 Dram Type= 6, Freq= 0, CH_1, rank 1
4845 09:28:20.839741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4846 09:28:20.839872 ==
4847 09:28:20.839943 DQS Delay:
4848 09:28:20.842986 DQS0 = 0, DQS1 = 0
4849 09:28:20.843091 DQM Delay:
4850 09:28:20.846260 DQM0 = 38, DQM1 = 33
4851 09:28:20.846347 DQ Delay:
4852 09:28:20.849692 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4853 09:28:20.852988 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4854 09:28:20.856882 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4855 09:28:20.859585 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4856 09:28:20.859688
4857 09:28:20.859757
4858 09:28:20.866630 [DQSOSCAuto] RK1, (LSB)MR18= 0x3644, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4859 09:28:20.869752 CH1 RK1: MR19=808, MR18=3644
4860 09:28:20.876268 CH1_RK1: MR19=0x808, MR18=0x3644, DQSOSC=396, MR23=63, INC=167, DEC=111
4861 09:28:20.879766 [RxdqsGatingPostProcess] freq 600
4862 09:28:20.886367 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4863 09:28:20.890059 Pre-setting of DQS Precalculation
4864 09:28:20.893113 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4865 09:28:20.899858 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4866 09:28:20.906660 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4867 09:28:20.906790
4868 09:28:20.906858
4869 09:28:20.909978 [Calibration Summary] 1200 Mbps
4870 09:28:20.913535 CH 0, Rank 0
4871 09:28:20.913626 SW Impedance : PASS
4872 09:28:20.916791 DUTY Scan : NO K
4873 09:28:20.920428 ZQ Calibration : PASS
4874 09:28:20.920529 Jitter Meter : NO K
4875 09:28:20.923397 CBT Training : PASS
4876 09:28:20.923496 Write leveling : PASS
4877 09:28:20.927079 RX DQS gating : PASS
4878 09:28:20.929839 RX DQ/DQS(RDDQC) : PASS
4879 09:28:20.929922 TX DQ/DQS : PASS
4880 09:28:20.933291 RX DATLAT : PASS
4881 09:28:20.936515 RX DQ/DQS(Engine): PASS
4882 09:28:20.936639 TX OE : NO K
4883 09:28:20.940002 All Pass.
4884 09:28:20.940116
4885 09:28:20.940218 CH 0, Rank 1
4886 09:28:20.943633 SW Impedance : PASS
4887 09:28:20.943725 DUTY Scan : NO K
4888 09:28:20.947430 ZQ Calibration : PASS
4889 09:28:20.949861 Jitter Meter : NO K
4890 09:28:20.949949 CBT Training : PASS
4891 09:28:20.953411 Write leveling : PASS
4892 09:28:20.956500 RX DQS gating : PASS
4893 09:28:20.956588 RX DQ/DQS(RDDQC) : PASS
4894 09:28:20.960208 TX DQ/DQS : PASS
4895 09:28:20.960328 RX DATLAT : PASS
4896 09:28:20.963266 RX DQ/DQS(Engine): PASS
4897 09:28:20.966854 TX OE : NO K
4898 09:28:20.966945 All Pass.
4899 09:28:20.967031
4900 09:28:20.967114 CH 1, Rank 0
4901 09:28:20.970241 SW Impedance : PASS
4902 09:28:20.973475 DUTY Scan : NO K
4903 09:28:20.973581 ZQ Calibration : PASS
4904 09:28:20.977082 Jitter Meter : NO K
4905 09:28:20.980167 CBT Training : PASS
4906 09:28:20.980275 Write leveling : PASS
4907 09:28:20.983921 RX DQS gating : PASS
4908 09:28:20.987042 RX DQ/DQS(RDDQC) : PASS
4909 09:28:20.987161 TX DQ/DQS : PASS
4910 09:28:20.990068 RX DATLAT : PASS
4911 09:28:20.990161 RX DQ/DQS(Engine): PASS
4912 09:28:20.993939 TX OE : NO K
4913 09:28:20.994037 All Pass.
4914 09:28:20.994140
4915 09:28:20.996926 CH 1, Rank 1
4916 09:28:20.997036 SW Impedance : PASS
4917 09:28:21.000290 DUTY Scan : NO K
4918 09:28:21.003620 ZQ Calibration : PASS
4919 09:28:21.003727 Jitter Meter : NO K
4920 09:28:21.007022 CBT Training : PASS
4921 09:28:21.010335 Write leveling : PASS
4922 09:28:21.010439 RX DQS gating : PASS
4923 09:28:21.013900 RX DQ/DQS(RDDQC) : PASS
4924 09:28:21.016908 TX DQ/DQS : PASS
4925 09:28:21.016996 RX DATLAT : PASS
4926 09:28:21.020433 RX DQ/DQS(Engine): PASS
4927 09:28:21.023743 TX OE : NO K
4928 09:28:21.023830 All Pass.
4929 09:28:21.023897
4930 09:28:21.023960 DramC Write-DBI off
4931 09:28:21.026953 PER_BANK_REFRESH: Hybrid Mode
4932 09:28:21.030317 TX_TRACKING: ON
4933 09:28:21.036854 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4934 09:28:21.040416 [FAST_K] Save calibration result to emmc
4935 09:28:21.047217 dramc_set_vcore_voltage set vcore to 662500
4936 09:28:21.047392 Read voltage for 933, 3
4937 09:28:21.047503 Vio18 = 0
4938 09:28:21.050512 Vcore = 662500
4939 09:28:21.050647 Vdram = 0
4940 09:28:21.050757 Vddq = 0
4941 09:28:21.054356 Vmddr = 0
4942 09:28:21.057184 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4943 09:28:21.064080 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4944 09:28:21.067223 MEM_TYPE=3, freq_sel=17
4945 09:28:21.067367 sv_algorithm_assistance_LP4_1600
4946 09:28:21.073544 ============ PULL DRAM RESETB DOWN ============
4947 09:28:21.076853 ========== PULL DRAM RESETB DOWN end =========
4948 09:28:21.080358 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4949 09:28:21.084184 ===================================
4950 09:28:21.087483 LPDDR4 DRAM CONFIGURATION
4951 09:28:21.090281 ===================================
4952 09:28:21.093796 EX_ROW_EN[0] = 0x0
4953 09:28:21.093927 EX_ROW_EN[1] = 0x0
4954 09:28:21.097224 LP4Y_EN = 0x0
4955 09:28:21.097374 WORK_FSP = 0x0
4956 09:28:21.100512 WL = 0x3
4957 09:28:21.100643 RL = 0x3
4958 09:28:21.104125 BL = 0x2
4959 09:28:21.104274 RPST = 0x0
4960 09:28:21.106908 RD_PRE = 0x0
4961 09:28:21.107035 WR_PRE = 0x1
4962 09:28:21.110292 WR_PST = 0x0
4963 09:28:21.110425 DBI_WR = 0x0
4964 09:28:21.113730 DBI_RD = 0x0
4965 09:28:21.113854 OTF = 0x1
4966 09:28:21.117410 ===================================
4967 09:28:21.120881 ===================================
4968 09:28:21.123991 ANA top config
4969 09:28:21.127314 ===================================
4970 09:28:21.127476 DLL_ASYNC_EN = 0
4971 09:28:21.130625 ALL_SLAVE_EN = 1
4972 09:28:21.134066 NEW_RANK_MODE = 1
4973 09:28:21.137211 DLL_IDLE_MODE = 1
4974 09:28:21.140833 LP45_APHY_COMB_EN = 1
4975 09:28:21.140990 TX_ODT_DIS = 1
4976 09:28:21.143867 NEW_8X_MODE = 1
4977 09:28:21.147336 ===================================
4978 09:28:21.150509 ===================================
4979 09:28:21.153971 data_rate = 1866
4980 09:28:21.157159 CKR = 1
4981 09:28:21.161235 DQ_P2S_RATIO = 8
4982 09:28:21.163919 ===================================
4983 09:28:21.164062 CA_P2S_RATIO = 8
4984 09:28:21.167444 DQ_CA_OPEN = 0
4985 09:28:21.170683 DQ_SEMI_OPEN = 0
4986 09:28:21.173886 CA_SEMI_OPEN = 0
4987 09:28:21.177255 CA_FULL_RATE = 0
4988 09:28:21.180761 DQ_CKDIV4_EN = 1
4989 09:28:21.180925 CA_CKDIV4_EN = 1
4990 09:28:21.184259 CA_PREDIV_EN = 0
4991 09:28:21.187577 PH8_DLY = 0
4992 09:28:21.190599 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4993 09:28:21.194042 DQ_AAMCK_DIV = 4
4994 09:28:21.194196 CA_AAMCK_DIV = 4
4995 09:28:21.197264 CA_ADMCK_DIV = 4
4996 09:28:21.200641 DQ_TRACK_CA_EN = 0
4997 09:28:21.204211 CA_PICK = 933
4998 09:28:21.207950 CA_MCKIO = 933
4999 09:28:21.210774 MCKIO_SEMI = 0
5000 09:28:21.214087 PLL_FREQ = 3732
5001 09:28:21.214264 DQ_UI_PI_RATIO = 32
5002 09:28:21.217490 CA_UI_PI_RATIO = 0
5003 09:28:21.221245 ===================================
5004 09:28:21.224454 ===================================
5005 09:28:21.227289 memory_type:LPDDR4
5006 09:28:21.230545 GP_NUM : 10
5007 09:28:21.230664 SRAM_EN : 1
5008 09:28:21.234404 MD32_EN : 0
5009 09:28:21.237585 ===================================
5010 09:28:21.240901 [ANA_INIT] >>>>>>>>>>>>>>
5011 09:28:21.241037 <<<<<< [CONFIGURE PHASE]: ANA_TX
5012 09:28:21.243966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5013 09:28:21.247228 ===================================
5014 09:28:21.250650 data_rate = 1866,PCW = 0X8f00
5015 09:28:21.254101 ===================================
5016 09:28:21.257643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5017 09:28:21.264157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5018 09:28:21.270813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5019 09:28:21.274339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5020 09:28:21.277173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5021 09:28:21.280534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5022 09:28:21.284267 [ANA_INIT] flow start
5023 09:28:21.284396 [ANA_INIT] PLL >>>>>>>>
5024 09:28:21.287138 [ANA_INIT] PLL <<<<<<<<
5025 09:28:21.290846 [ANA_INIT] MIDPI >>>>>>>>
5026 09:28:21.290989 [ANA_INIT] MIDPI <<<<<<<<
5027 09:28:21.293970 [ANA_INIT] DLL >>>>>>>>
5028 09:28:21.297428 [ANA_INIT] flow end
5029 09:28:21.300835 ============ LP4 DIFF to SE enter ============
5030 09:28:21.304175 ============ LP4 DIFF to SE exit ============
5031 09:28:21.307189 [ANA_INIT] <<<<<<<<<<<<<
5032 09:28:21.310835 [Flow] Enable top DCM control >>>>>
5033 09:28:21.314052 [Flow] Enable top DCM control <<<<<
5034 09:28:21.317913 Enable DLL master slave shuffle
5035 09:28:21.320746 ==============================================================
5036 09:28:21.324106 Gating Mode config
5037 09:28:21.327395 ==============================================================
5038 09:28:21.330858 Config description:
5039 09:28:21.340942 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5040 09:28:21.348068 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5041 09:28:21.351232 SELPH_MODE 0: By rank 1: By Phase
5042 09:28:21.358075 ==============================================================
5043 09:28:21.360935 GAT_TRACK_EN = 1
5044 09:28:21.364506 RX_GATING_MODE = 2
5045 09:28:21.368161 RX_GATING_TRACK_MODE = 2
5046 09:28:21.371434 SELPH_MODE = 1
5047 09:28:21.371564 PICG_EARLY_EN = 1
5048 09:28:21.374634 VALID_LAT_VALUE = 1
5049 09:28:21.381290 ==============================================================
5050 09:28:21.384674 Enter into Gating configuration >>>>
5051 09:28:21.387715 Exit from Gating configuration <<<<
5052 09:28:21.391707 Enter into DVFS_PRE_config >>>>>
5053 09:28:21.400975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5054 09:28:21.404476 Exit from DVFS_PRE_config <<<<<
5055 09:28:21.407957 Enter into PICG configuration >>>>
5056 09:28:21.411282 Exit from PICG configuration <<<<
5057 09:28:21.414244 [RX_INPUT] configuration >>>>>
5058 09:28:21.417586 [RX_INPUT] configuration <<<<<
5059 09:28:21.421527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5060 09:28:21.428364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5061 09:28:21.434799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 09:28:21.441241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 09:28:21.444626 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5064 09:28:21.451300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5065 09:28:21.454630 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5066 09:28:21.461857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5067 09:28:21.464858 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5068 09:28:21.468048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5069 09:28:21.471707 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5070 09:28:21.478043 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 09:28:21.481735 ===================================
5072 09:28:21.481870 LPDDR4 DRAM CONFIGURATION
5073 09:28:21.484528 ===================================
5074 09:28:21.488014 EX_ROW_EN[0] = 0x0
5075 09:28:21.491401 EX_ROW_EN[1] = 0x0
5076 09:28:21.491522 LP4Y_EN = 0x0
5077 09:28:21.494937 WORK_FSP = 0x0
5078 09:28:21.495055 WL = 0x3
5079 09:28:21.497799 RL = 0x3
5080 09:28:21.497907 BL = 0x2
5081 09:28:21.501739 RPST = 0x0
5082 09:28:21.501850 RD_PRE = 0x0
5083 09:28:21.504753 WR_PRE = 0x1
5084 09:28:21.504863 WR_PST = 0x0
5085 09:28:21.507887 DBI_WR = 0x0
5086 09:28:21.508001 DBI_RD = 0x0
5087 09:28:21.511831 OTF = 0x1
5088 09:28:21.514890 ===================================
5089 09:28:21.517978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5090 09:28:21.521726 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5091 09:28:21.528092 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5092 09:28:21.531356 ===================================
5093 09:28:21.531503 LPDDR4 DRAM CONFIGURATION
5094 09:28:21.535008 ===================================
5095 09:28:21.537916 EX_ROW_EN[0] = 0x10
5096 09:28:21.538061 EX_ROW_EN[1] = 0x0
5097 09:28:21.541810 LP4Y_EN = 0x0
5098 09:28:21.541956 WORK_FSP = 0x0
5099 09:28:21.544792 WL = 0x3
5100 09:28:21.548353 RL = 0x3
5101 09:28:21.548506 BL = 0x2
5102 09:28:21.551852 RPST = 0x0
5103 09:28:21.551990 RD_PRE = 0x0
5104 09:28:21.554913 WR_PRE = 0x1
5105 09:28:21.555034 WR_PST = 0x0
5106 09:28:21.558447 DBI_WR = 0x0
5107 09:28:21.558586 DBI_RD = 0x0
5108 09:28:21.561715 OTF = 0x1
5109 09:28:21.564943 ===================================
5110 09:28:21.569702 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5111 09:28:21.573857 nWR fixed to 30
5112 09:28:21.576743 [ModeRegInit_LP4] CH0 RK0
5113 09:28:21.576898 [ModeRegInit_LP4] CH0 RK1
5114 09:28:21.580447 [ModeRegInit_LP4] CH1 RK0
5115 09:28:21.584014 [ModeRegInit_LP4] CH1 RK1
5116 09:28:21.584171 match AC timing 9
5117 09:28:21.590600 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5118 09:28:21.593904 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5119 09:28:21.597197 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5120 09:28:21.603435 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5121 09:28:21.607186 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5122 09:28:21.607357 ==
5123 09:28:21.610267 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 09:28:21.613550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 09:28:21.613722 ==
5126 09:28:21.620342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 09:28:21.627080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5128 09:28:21.630180 [CA 0] Center 38 (8~69) winsize 62
5129 09:28:21.633712 [CA 1] Center 38 (7~69) winsize 63
5130 09:28:21.637005 [CA 2] Center 35 (5~66) winsize 62
5131 09:28:21.640479 [CA 3] Center 35 (4~66) winsize 63
5132 09:28:21.643870 [CA 4] Center 34 (4~64) winsize 61
5133 09:28:21.646972 [CA 5] Center 34 (4~64) winsize 61
5134 09:28:21.647136
5135 09:28:21.650087 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5136 09:28:21.650239
5137 09:28:21.653705 [CATrainingPosCal] consider 1 rank data
5138 09:28:21.657132 u2DelayCellTimex100 = 270/100 ps
5139 09:28:21.660173 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5140 09:28:21.663622 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5141 09:28:21.667002 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5142 09:28:21.670422 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5143 09:28:21.673460 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5144 09:28:21.677114 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5145 09:28:21.677292
5146 09:28:21.683946 CA PerBit enable=1, Macro0, CA PI delay=34
5147 09:28:21.684150
5148 09:28:21.684252 [CBTSetCACLKResult] CA Dly = 34
5149 09:28:21.687500 CS Dly: 6 (0~37)
5150 09:28:21.687644 ==
5151 09:28:21.690254 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 09:28:21.693839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 09:28:21.694006 ==
5154 09:28:21.700518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5155 09:28:21.707287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5156 09:28:21.710760 [CA 0] Center 38 (7~69) winsize 63
5157 09:28:21.714086 [CA 1] Center 38 (8~69) winsize 62
5158 09:28:21.717093 [CA 2] Center 35 (5~66) winsize 62
5159 09:28:21.720511 [CA 3] Center 35 (5~66) winsize 62
5160 09:28:21.723649 [CA 4] Center 34 (3~65) winsize 63
5161 09:28:21.727101 [CA 5] Center 33 (3~64) winsize 62
5162 09:28:21.727262
5163 09:28:21.730350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5164 09:28:21.730467
5165 09:28:21.734178 [CATrainingPosCal] consider 2 rank data
5166 09:28:21.737078 u2DelayCellTimex100 = 270/100 ps
5167 09:28:21.740782 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5168 09:28:21.744267 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5169 09:28:21.747251 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5170 09:28:21.750487 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5171 09:28:21.754047 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5172 09:28:21.757524 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5173 09:28:21.757694
5174 09:28:21.760593 CA PerBit enable=1, Macro0, CA PI delay=34
5175 09:28:21.760761
5176 09:28:21.764242 [CBTSetCACLKResult] CA Dly = 34
5177 09:28:21.767387 CS Dly: 7 (0~39)
5178 09:28:21.767536
5179 09:28:21.770388 ----->DramcWriteLeveling(PI) begin...
5180 09:28:21.770528 ==
5181 09:28:21.773716 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 09:28:21.777166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 09:28:21.777329 ==
5184 09:28:21.780744 Write leveling (Byte 0): 33 => 33
5185 09:28:21.783883 Write leveling (Byte 1): 29 => 29
5186 09:28:21.787364 DramcWriteLeveling(PI) end<-----
5187 09:28:21.787497
5188 09:28:21.787571 ==
5189 09:28:21.790458 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 09:28:21.793866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 09:28:21.793994 ==
5192 09:28:21.797756 [Gating] SW mode calibration
5193 09:28:21.804315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5194 09:28:21.810345 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5195 09:28:21.813767 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5196 09:28:21.820913 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5197 09:28:21.823822 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 09:28:21.827762 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 09:28:21.831046 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 09:28:21.837481 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 09:28:21.840610 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 09:28:21.844192 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5203 09:28:21.850445 0 15 0 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (1 1)
5204 09:28:21.853860 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5205 09:28:21.857321 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 09:28:21.864186 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 09:28:21.867303 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 09:28:21.870406 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 09:28:21.877056 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 09:28:21.880545 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5211 09:28:21.884548 1 0 0 | B1->B0 | 3030 4040 | 0 1 | (0 0) (0 0)
5212 09:28:21.891018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 09:28:21.894451 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 09:28:21.897258 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 09:28:21.904341 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 09:28:21.907361 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 09:28:21.911092 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 09:28:21.914127 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 09:28:21.921217 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 09:28:21.924044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 09:28:21.927510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 09:28:21.934417 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 09:28:21.937345 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 09:28:21.940692 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 09:28:21.947266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 09:28:21.950564 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 09:28:21.954428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 09:28:21.961082 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 09:28:21.964185 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 09:28:21.967579 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 09:28:21.974234 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 09:28:21.977406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 09:28:21.980999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 09:28:21.987426 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 09:28:21.990927 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5236 09:28:21.994184 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5237 09:28:21.997401 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 09:28:22.000868 Total UI for P1: 0, mck2ui 16
5239 09:28:22.004263 best dqsien dly found for B0: ( 1, 3, 2)
5240 09:28:22.007459 Total UI for P1: 0, mck2ui 16
5241 09:28:22.010968 best dqsien dly found for B1: ( 1, 3, 2)
5242 09:28:22.014808 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5243 09:28:22.018203 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5244 09:28:22.018327
5245 09:28:22.024311 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5246 09:28:22.027836 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5247 09:28:22.027972 [Gating] SW calibration Done
5248 09:28:22.030997 ==
5249 09:28:22.031111 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 09:28:22.037878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 09:28:22.038019 ==
5252 09:28:22.038094 RX Vref Scan: 0
5253 09:28:22.038156
5254 09:28:22.041119 RX Vref 0 -> 0, step: 1
5255 09:28:22.041220
5256 09:28:22.044302 RX Delay -80 -> 252, step: 8
5257 09:28:22.047821 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5258 09:28:22.051360 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5259 09:28:22.054376 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5260 09:28:22.057974 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5261 09:28:22.064277 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5262 09:28:22.067953 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5263 09:28:22.070850 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5264 09:28:22.074412 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5265 09:28:22.077782 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5266 09:28:22.081063 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5267 09:28:22.087603 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5268 09:28:22.091094 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5269 09:28:22.094370 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5270 09:28:22.097896 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5271 09:28:22.101047 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5272 09:28:22.104298 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5273 09:28:22.107596 ==
5274 09:28:22.111359 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 09:28:22.114538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 09:28:22.114735 ==
5277 09:28:22.114850 DQS Delay:
5278 09:28:22.118037 DQS0 = 0, DQS1 = 0
5279 09:28:22.118187 DQM Delay:
5280 09:28:22.121103 DQM0 = 98, DQM1 = 87
5281 09:28:22.121255 DQ Delay:
5282 09:28:22.124834 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5283 09:28:22.128190 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5284 09:28:22.131318 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5285 09:28:22.134776 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5286 09:28:22.134959
5287 09:28:22.135069
5288 09:28:22.135168 ==
5289 09:28:22.137597 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 09:28:22.141179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 09:28:22.141360 ==
5292 09:28:22.141464
5293 09:28:22.141568
5294 09:28:22.144650 TX Vref Scan disable
5295 09:28:22.147751 == TX Byte 0 ==
5296 09:28:22.151136 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5297 09:28:22.154343 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5298 09:28:22.158011 == TX Byte 1 ==
5299 09:28:22.161097 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5300 09:28:22.164583 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5301 09:28:22.164715 ==
5302 09:28:22.168061 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 09:28:22.171280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 09:28:22.174326 ==
5305 09:28:22.174494
5306 09:28:22.174600
5307 09:28:22.174700 TX Vref Scan disable
5308 09:28:22.178356 == TX Byte 0 ==
5309 09:28:22.181919 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5310 09:28:22.184906 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5311 09:28:22.188263 == TX Byte 1 ==
5312 09:28:22.191720 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5313 09:28:22.194851 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5314 09:28:22.198536
5315 09:28:22.198713 [DATLAT]
5316 09:28:22.198846 Freq=933, CH0 RK0
5317 09:28:22.198942
5318 09:28:22.201931 DATLAT Default: 0xd
5319 09:28:22.202082 0, 0xFFFF, sum = 0
5320 09:28:22.205088 1, 0xFFFF, sum = 0
5321 09:28:22.205244 2, 0xFFFF, sum = 0
5322 09:28:22.208313 3, 0xFFFF, sum = 0
5323 09:28:22.208462 4, 0xFFFF, sum = 0
5324 09:28:22.212103 5, 0xFFFF, sum = 0
5325 09:28:22.212279 6, 0xFFFF, sum = 0
5326 09:28:22.215128 7, 0xFFFF, sum = 0
5327 09:28:22.215285 8, 0xFFFF, sum = 0
5328 09:28:22.218756 9, 0xFFFF, sum = 0
5329 09:28:22.218914 10, 0x0, sum = 1
5330 09:28:22.221905 11, 0x0, sum = 2
5331 09:28:22.222062 12, 0x0, sum = 3
5332 09:28:22.225197 13, 0x0, sum = 4
5333 09:28:22.225349 best_step = 11
5334 09:28:22.225452
5335 09:28:22.225545 ==
5336 09:28:22.228696 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 09:28:22.235023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 09:28:22.235216 ==
5339 09:28:22.235322 RX Vref Scan: 1
5340 09:28:22.235432
5341 09:28:22.238372 RX Vref 0 -> 0, step: 1
5342 09:28:22.238504
5343 09:28:22.241839 RX Delay -61 -> 252, step: 4
5344 09:28:22.241990
5345 09:28:22.245311 Set Vref, RX VrefLevel [Byte0]: 53
5346 09:28:22.248815 [Byte1]: 51
5347 09:28:22.248989
5348 09:28:22.251756 Final RX Vref Byte 0 = 53 to rank0
5349 09:28:22.255478 Final RX Vref Byte 1 = 51 to rank0
5350 09:28:22.258512 Final RX Vref Byte 0 = 53 to rank1
5351 09:28:22.262089 Final RX Vref Byte 1 = 51 to rank1==
5352 09:28:22.265417 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 09:28:22.268842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 09:28:22.269011 ==
5355 09:28:22.272246 DQS Delay:
5356 09:28:22.272382 DQS0 = 0, DQS1 = 0
5357 09:28:22.272481 DQM Delay:
5358 09:28:22.275276 DQM0 = 97, DQM1 = 88
5359 09:28:22.275403 DQ Delay:
5360 09:28:22.278528 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5361 09:28:22.282168 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5362 09:28:22.285446 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5363 09:28:22.288795 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5364 09:28:22.288942
5365 09:28:22.289040
5366 09:28:22.298577 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5367 09:28:22.302220 CH0 RK0: MR19=504, MR18=12FD
5368 09:28:22.305595 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5369 09:28:22.305743
5370 09:28:22.308895 ----->DramcWriteLeveling(PI) begin...
5371 09:28:22.312000 ==
5372 09:28:22.312137 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 09:28:22.318695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 09:28:22.318879 ==
5375 09:28:22.322171 Write leveling (Byte 0): 28 => 28
5376 09:28:22.325499 Write leveling (Byte 1): 26 => 26
5377 09:28:22.328897 DramcWriteLeveling(PI) end<-----
5378 09:28:22.329062
5379 09:28:22.329161 ==
5380 09:28:22.331968 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 09:28:22.335658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 09:28:22.335842 ==
5383 09:28:22.338841 [Gating] SW mode calibration
5384 09:28:22.345335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5385 09:28:22.348763 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5386 09:28:22.355420 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
5387 09:28:22.358665 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5388 09:28:22.362212 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 09:28:22.368799 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 09:28:22.372373 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 09:28:22.375806 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 09:28:22.382410 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 09:28:22.385637 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5394 09:28:22.388475 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5395 09:28:22.395183 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5396 09:28:22.398469 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 09:28:22.401885 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 09:28:22.408569 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 09:28:22.412200 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 09:28:22.415526 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 09:28:22.422052 0 15 28 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)
5402 09:28:22.425612 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5403 09:28:22.428686 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 09:28:22.435279 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 09:28:22.438640 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 09:28:22.442047 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 09:28:22.445185 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 09:28:22.452021 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 09:28:22.455416 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5410 09:28:22.458481 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5411 09:28:22.464967 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 09:28:22.468402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 09:28:22.471944 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 09:28:22.478405 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 09:28:22.482203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 09:28:22.485333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 09:28:22.491756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 09:28:22.495320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 09:28:22.498434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 09:28:22.505199 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 09:28:22.509246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 09:28:22.511904 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 09:28:22.518492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 09:28:22.522186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5425 09:28:22.525600 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5426 09:28:22.529368 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5427 09:28:22.531733 Total UI for P1: 0, mck2ui 16
5428 09:28:22.535668 best dqsien dly found for B0: ( 1, 2, 26)
5429 09:28:22.541833 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5430 09:28:22.545332 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 09:28:22.548800 Total UI for P1: 0, mck2ui 16
5432 09:28:22.552007 best dqsien dly found for B1: ( 1, 3, 0)
5433 09:28:22.555774 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5434 09:28:22.558740 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5435 09:28:22.558912
5436 09:28:22.562182 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5437 09:28:22.565595 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5438 09:28:22.568747 [Gating] SW calibration Done
5439 09:28:22.568879 ==
5440 09:28:22.572152 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 09:28:22.575499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 09:28:22.575665 ==
5443 09:28:22.579147 RX Vref Scan: 0
5444 09:28:22.579306
5445 09:28:22.582150 RX Vref 0 -> 0, step: 1
5446 09:28:22.582276
5447 09:28:22.582378 RX Delay -80 -> 252, step: 8
5448 09:28:22.588801 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5449 09:28:22.592682 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5450 09:28:22.596055 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5451 09:28:22.599001 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5452 09:28:22.602248 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5453 09:28:22.605631 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5454 09:28:22.612228 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5455 09:28:22.615727 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5456 09:28:22.618867 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5457 09:28:22.622493 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5458 09:28:22.625578 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5459 09:28:22.629043 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5460 09:28:22.636145 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5461 09:28:22.639320 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5462 09:28:22.642865 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5463 09:28:22.646487 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5464 09:28:22.646684 ==
5465 09:28:22.649852 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 09:28:22.652454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 09:28:22.652625 ==
5468 09:28:22.655839 DQS Delay:
5469 09:28:22.655982 DQS0 = 0, DQS1 = 0
5470 09:28:22.658961 DQM Delay:
5471 09:28:22.659129 DQM0 = 97, DQM1 = 87
5472 09:28:22.659232 DQ Delay:
5473 09:28:22.662219 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5474 09:28:22.666085 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5475 09:28:22.669306 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5476 09:28:22.672472 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5477 09:28:22.672625
5478 09:28:22.672721
5479 09:28:22.675984 ==
5480 09:28:22.679106 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 09:28:22.682911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 09:28:22.683120 ==
5483 09:28:22.683255
5484 09:28:22.683369
5485 09:28:22.685626 TX Vref Scan disable
5486 09:28:22.685748 == TX Byte 0 ==
5487 09:28:22.689002 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5488 09:28:22.695832 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5489 09:28:22.696034 == TX Byte 1 ==
5490 09:28:22.699296 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5491 09:28:22.706038 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5492 09:28:22.706238 ==
5493 09:28:22.709398 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 09:28:22.712812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 09:28:22.712995 ==
5496 09:28:22.713107
5497 09:28:22.713198
5498 09:28:22.716605 TX Vref Scan disable
5499 09:28:22.719295 == TX Byte 0 ==
5500 09:28:22.722706 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5501 09:28:22.725991 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5502 09:28:22.729726 == TX Byte 1 ==
5503 09:28:22.732546 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5504 09:28:22.735767 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5505 09:28:22.735927
5506 09:28:22.736064 [DATLAT]
5507 09:28:22.739882 Freq=933, CH0 RK1
5508 09:28:22.739998
5509 09:28:22.742737 DATLAT Default: 0xb
5510 09:28:22.742852 0, 0xFFFF, sum = 0
5511 09:28:22.746128 1, 0xFFFF, sum = 0
5512 09:28:22.746296 2, 0xFFFF, sum = 0
5513 09:28:22.749170 3, 0xFFFF, sum = 0
5514 09:28:22.749338 4, 0xFFFF, sum = 0
5515 09:28:22.752519 5, 0xFFFF, sum = 0
5516 09:28:22.752675 6, 0xFFFF, sum = 0
5517 09:28:22.756251 7, 0xFFFF, sum = 0
5518 09:28:22.756458 8, 0xFFFF, sum = 0
5519 09:28:22.759539 9, 0xFFFF, sum = 0
5520 09:28:22.759731 10, 0x0, sum = 1
5521 09:28:22.762738 11, 0x0, sum = 2
5522 09:28:22.762876 12, 0x0, sum = 3
5523 09:28:22.766294 13, 0x0, sum = 4
5524 09:28:22.766444 best_step = 11
5525 09:28:22.766543
5526 09:28:22.766671 ==
5527 09:28:22.769262 Dram Type= 6, Freq= 0, CH_0, rank 1
5528 09:28:22.772645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 09:28:22.772810 ==
5530 09:28:22.776171 RX Vref Scan: 0
5531 09:28:22.776316
5532 09:28:22.779493 RX Vref 0 -> 0, step: 1
5533 09:28:22.779651
5534 09:28:22.779750 RX Delay -61 -> 252, step: 4
5535 09:28:22.787049 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5536 09:28:22.790773 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5537 09:28:22.793967 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5538 09:28:22.796994 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5539 09:28:22.800563 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5540 09:28:22.803770 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5541 09:28:22.811098 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5542 09:28:22.813929 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5543 09:28:22.817139 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5544 09:28:22.820850 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5545 09:28:22.823860 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5546 09:28:22.827585 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5547 09:28:22.834144 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5548 09:28:22.837502 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5549 09:28:22.840522 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5550 09:28:22.843943 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5551 09:28:22.844155 ==
5552 09:28:22.847444 Dram Type= 6, Freq= 0, CH_0, rank 1
5553 09:28:22.851527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 09:28:22.851670 ==
5555 09:28:22.854225 DQS Delay:
5556 09:28:22.854345 DQS0 = 0, DQS1 = 0
5557 09:28:22.857466 DQM Delay:
5558 09:28:22.857637 DQM0 = 96, DQM1 = 87
5559 09:28:22.857746 DQ Delay:
5560 09:28:22.860799 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5561 09:28:22.864214 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5562 09:28:22.867632 DQ8 =82, DQ9 =78, DQ10 =86, DQ11 =80
5563 09:28:22.870867 DQ12 =90, DQ13 =92, DQ14 =100, DQ15 =94
5564 09:28:22.871052
5565 09:28:22.874241
5566 09:28:22.880771 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5567 09:28:22.884113 CH0 RK1: MR19=505, MR18=1805
5568 09:28:22.890923 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5569 09:28:22.891116 [RxdqsGatingPostProcess] freq 933
5570 09:28:22.897480 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5571 09:28:22.900842 best DQS0 dly(2T, 0.5T) = (0, 11)
5572 09:28:22.904147 best DQS1 dly(2T, 0.5T) = (0, 11)
5573 09:28:22.907849 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5574 09:28:22.911065 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5575 09:28:22.914236 best DQS0 dly(2T, 0.5T) = (0, 10)
5576 09:28:22.917945 best DQS1 dly(2T, 0.5T) = (0, 11)
5577 09:28:22.920883 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5578 09:28:22.924488 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5579 09:28:22.928069 Pre-setting of DQS Precalculation
5580 09:28:22.931170 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5581 09:28:22.931333 ==
5582 09:28:22.934095 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 09:28:22.937875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 09:28:22.938025 ==
5585 09:28:22.944623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 09:28:22.951552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5587 09:28:22.954778 [CA 0] Center 37 (7~67) winsize 61
5588 09:28:22.958607 [CA 1] Center 36 (6~67) winsize 62
5589 09:28:22.961541 [CA 2] Center 34 (4~65) winsize 62
5590 09:28:22.965439 [CA 3] Center 33 (3~64) winsize 62
5591 09:28:22.968539 [CA 4] Center 34 (4~64) winsize 61
5592 09:28:22.971414 [CA 5] Center 33 (3~64) winsize 62
5593 09:28:22.971544
5594 09:28:22.975348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5595 09:28:22.975485
5596 09:28:22.978280 [CATrainingPosCal] consider 1 rank data
5597 09:28:22.981509 u2DelayCellTimex100 = 270/100 ps
5598 09:28:22.984719 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5599 09:28:22.988411 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5600 09:28:22.992208 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5601 09:28:22.994922 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 09:28:22.998364 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5603 09:28:23.001608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5604 09:28:23.001766
5605 09:28:23.004827 CA PerBit enable=1, Macro0, CA PI delay=33
5606 09:28:23.008502
5607 09:28:23.008645 [CBTSetCACLKResult] CA Dly = 33
5608 09:28:23.011675 CS Dly: 4 (0~35)
5609 09:28:23.011797 ==
5610 09:28:23.015222 Dram Type= 6, Freq= 0, CH_1, rank 1
5611 09:28:23.018096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 09:28:23.018236 ==
5613 09:28:23.025246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5614 09:28:23.032038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5615 09:28:23.034921 [CA 0] Center 36 (6~67) winsize 62
5616 09:28:23.038058 [CA 1] Center 37 (7~67) winsize 61
5617 09:28:23.041933 [CA 2] Center 34 (3~65) winsize 63
5618 09:28:23.044942 [CA 3] Center 33 (3~64) winsize 62
5619 09:28:23.048358 [CA 4] Center 33 (3~64) winsize 62
5620 09:28:23.051839 [CA 5] Center 33 (3~63) winsize 61
5621 09:28:23.052014
5622 09:28:23.055067 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5623 09:28:23.055200
5624 09:28:23.058366 [CATrainingPosCal] consider 2 rank data
5625 09:28:23.061632 u2DelayCellTimex100 = 270/100 ps
5626 09:28:23.065878 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5627 09:28:23.068832 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5628 09:28:23.071648 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5629 09:28:23.075100 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5630 09:28:23.078555 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5631 09:28:23.081609 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5632 09:28:23.081752
5633 09:28:23.085352 CA PerBit enable=1, Macro0, CA PI delay=33
5634 09:28:23.085505
5635 09:28:23.088251 [CBTSetCACLKResult] CA Dly = 33
5636 09:28:23.091883 CS Dly: 5 (0~38)
5637 09:28:23.092058
5638 09:28:23.095408 ----->DramcWriteLeveling(PI) begin...
5639 09:28:23.095575 ==
5640 09:28:23.098642 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 09:28:23.101600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 09:28:23.101732 ==
5643 09:28:23.104902 Write leveling (Byte 0): 25 => 25
5644 09:28:23.108662 Write leveling (Byte 1): 29 => 29
5645 09:28:23.111793 DramcWriteLeveling(PI) end<-----
5646 09:28:23.111934
5647 09:28:23.112030 ==
5648 09:28:23.115092 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 09:28:23.118913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 09:28:23.119057 ==
5651 09:28:23.121745 [Gating] SW mode calibration
5652 09:28:23.128473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5653 09:28:23.135352 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5654 09:28:23.138513 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5655 09:28:23.142291 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 09:28:23.148901 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 09:28:23.152168 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 09:28:23.155309 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5659 09:28:23.162046 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 09:28:23.165761 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 09:28:23.168890 0 14 28 | B1->B0 | 2a2a 3030 | 0 0 | (1 1) (1 1)
5662 09:28:23.175458 0 15 0 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (1 1)
5663 09:28:23.178760 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 09:28:23.182122 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 09:28:23.189088 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5666 09:28:23.191933 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5667 09:28:23.195416 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 09:28:23.199111 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 09:28:23.205596 0 15 28 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5670 09:28:23.208835 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5671 09:28:23.212359 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 09:28:23.219284 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 09:28:23.221921 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 09:28:23.225796 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 09:28:23.232102 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 09:28:23.235408 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 09:28:23.238963 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5678 09:28:23.245312 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5679 09:28:23.248853 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 09:28:23.252784 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 09:28:23.258919 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 09:28:23.262067 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 09:28:23.265788 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 09:28:23.272087 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 09:28:23.275859 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 09:28:23.279015 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 09:28:23.285690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 09:28:23.289094 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 09:28:23.292355 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 09:28:23.295687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 09:28:23.302432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 09:28:23.305748 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 09:28:23.309117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5694 09:28:23.312253 Total UI for P1: 0, mck2ui 16
5695 09:28:23.315640 best dqsien dly found for B0: ( 1, 2, 26)
5696 09:28:23.322562 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 09:28:23.322744 Total UI for P1: 0, mck2ui 16
5698 09:28:23.328988 best dqsien dly found for B1: ( 1, 2, 28)
5699 09:28:23.332417 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5700 09:28:23.336215 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5701 09:28:23.336338
5702 09:28:23.339155 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5703 09:28:23.342642 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5704 09:28:23.346192 [Gating] SW calibration Done
5705 09:28:23.346346 ==
5706 09:28:23.348756 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 09:28:23.352321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 09:28:23.352468 ==
5709 09:28:23.355509 RX Vref Scan: 0
5710 09:28:23.355635
5711 09:28:23.355740 RX Vref 0 -> 0, step: 1
5712 09:28:23.355841
5713 09:28:23.358762 RX Delay -80 -> 252, step: 8
5714 09:28:23.362755 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5715 09:28:23.369520 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5716 09:28:23.372404 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5717 09:28:23.375913 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5718 09:28:23.379339 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5719 09:28:23.382507 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5720 09:28:23.386169 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5721 09:28:23.389334 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5722 09:28:23.395772 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5723 09:28:23.399176 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5724 09:28:23.402344 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5725 09:28:23.405808 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5726 09:28:23.409239 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5727 09:28:23.415768 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5728 09:28:23.419169 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5729 09:28:23.422556 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5730 09:28:23.422711 ==
5731 09:28:23.425835 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 09:28:23.429136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 09:28:23.429269 ==
5734 09:28:23.432554 DQS Delay:
5735 09:28:23.432676 DQS0 = 0, DQS1 = 0
5736 09:28:23.432770 DQM Delay:
5737 09:28:23.436168 DQM0 = 95, DQM1 = 88
5738 09:28:23.436334 DQ Delay:
5739 09:28:23.438925 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5740 09:28:23.442298 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5741 09:28:23.446057 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5742 09:28:23.449415 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5743 09:28:23.449602
5744 09:28:23.449703
5745 09:28:23.449807 ==
5746 09:28:23.452647 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 09:28:23.459316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 09:28:23.459469 ==
5749 09:28:23.459565
5750 09:28:23.459657
5751 09:28:23.459741 TX Vref Scan disable
5752 09:28:23.462651 == TX Byte 0 ==
5753 09:28:23.466541 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5754 09:28:23.469859 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5755 09:28:23.472878 == TX Byte 1 ==
5756 09:28:23.475986 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5757 09:28:23.479373 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5758 09:28:23.482953 ==
5759 09:28:23.485938 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 09:28:23.489481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 09:28:23.489676 ==
5762 09:28:23.489776
5763 09:28:23.489876
5764 09:28:23.492844 TX Vref Scan disable
5765 09:28:23.493036 == TX Byte 0 ==
5766 09:28:23.499597 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5767 09:28:23.503194 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5768 09:28:23.503382 == TX Byte 1 ==
5769 09:28:23.509818 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5770 09:28:23.512671 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5771 09:28:23.512840
5772 09:28:23.512959 [DATLAT]
5773 09:28:23.516284 Freq=933, CH1 RK0
5774 09:28:23.516455
5775 09:28:23.516549 DATLAT Default: 0xd
5776 09:28:23.519744 0, 0xFFFF, sum = 0
5777 09:28:23.519911 1, 0xFFFF, sum = 0
5778 09:28:23.523211 2, 0xFFFF, sum = 0
5779 09:28:23.523372 3, 0xFFFF, sum = 0
5780 09:28:23.525984 4, 0xFFFF, sum = 0
5781 09:28:23.526165 5, 0xFFFF, sum = 0
5782 09:28:23.529697 6, 0xFFFF, sum = 0
5783 09:28:23.529828 7, 0xFFFF, sum = 0
5784 09:28:23.532988 8, 0xFFFF, sum = 0
5785 09:28:23.533108 9, 0xFFFF, sum = 0
5786 09:28:23.536139 10, 0x0, sum = 1
5787 09:28:23.536253 11, 0x0, sum = 2
5788 09:28:23.539872 12, 0x0, sum = 3
5789 09:28:23.540007 13, 0x0, sum = 4
5790 09:28:23.543065 best_step = 11
5791 09:28:23.543201
5792 09:28:23.543302 ==
5793 09:28:23.546327 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 09:28:23.549508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 09:28:23.549612 ==
5796 09:28:23.552996 RX Vref Scan: 1
5797 09:28:23.553094
5798 09:28:23.553167 RX Vref 0 -> 0, step: 1
5799 09:28:23.553238
5800 09:28:23.556527 RX Delay -69 -> 252, step: 4
5801 09:28:23.556627
5802 09:28:23.559827 Set Vref, RX VrefLevel [Byte0]: 58
5803 09:28:23.563103 [Byte1]: 53
5804 09:28:23.566836
5805 09:28:23.566938 Final RX Vref Byte 0 = 58 to rank0
5806 09:28:23.570101 Final RX Vref Byte 1 = 53 to rank0
5807 09:28:23.573595 Final RX Vref Byte 0 = 58 to rank1
5808 09:28:23.577278 Final RX Vref Byte 1 = 53 to rank1==
5809 09:28:23.580038 Dram Type= 6, Freq= 0, CH_1, rank 0
5810 09:28:23.583524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 09:28:23.587066 ==
5812 09:28:23.587170 DQS Delay:
5813 09:28:23.587236 DQS0 = 0, DQS1 = 0
5814 09:28:23.590262 DQM Delay:
5815 09:28:23.590343 DQM0 = 97, DQM1 = 90
5816 09:28:23.593566 DQ Delay:
5817 09:28:23.596985 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =96
5818 09:28:23.600193 DQ4 =98, DQ5 =108, DQ6 =106, DQ7 =94
5819 09:28:23.600291 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5820 09:28:23.603562 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5821 09:28:23.606864
5822 09:28:23.606967
5823 09:28:23.613521 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ef, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 416 ps
5824 09:28:23.617489 CH1 RK0: MR19=504, MR18=12EF
5825 09:28:23.623626 CH1_RK0: MR19=0x504, MR18=0x12EF, DQSOSC=416, MR23=63, INC=62, DEC=41
5826 09:28:23.623759
5827 09:28:23.626936 ----->DramcWriteLeveling(PI) begin...
5828 09:28:23.627091 ==
5829 09:28:23.630347 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 09:28:23.633472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 09:28:23.633580 ==
5832 09:28:23.637064 Write leveling (Byte 0): 28 => 28
5833 09:28:23.640686 Write leveling (Byte 1): 28 => 28
5834 09:28:23.643615 DramcWriteLeveling(PI) end<-----
5835 09:28:23.643739
5836 09:28:23.643852 ==
5837 09:28:23.647307 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 09:28:23.650503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 09:28:23.650632 ==
5840 09:28:23.653845 [Gating] SW mode calibration
5841 09:28:23.660857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5842 09:28:23.667140 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5843 09:28:23.670527 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5844 09:28:23.674288 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 09:28:23.680571 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5846 09:28:23.683622 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5847 09:28:23.686976 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 09:28:23.694094 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5849 09:28:23.697246 0 14 24 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
5850 09:28:23.700448 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 09:28:23.704429 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 09:28:23.710280 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 09:28:23.713923 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 09:28:23.716902 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 09:28:23.724001 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 09:28:23.727255 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 09:28:23.730507 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (0 0) (1 1)
5858 09:28:23.736927 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 09:28:23.740468 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 09:28:23.744578 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 09:28:23.750566 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 09:28:23.753678 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 09:28:23.757122 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 09:28:23.763940 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 09:28:23.766903 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5866 09:28:23.770562 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 09:28:23.776841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 09:28:23.780465 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 09:28:23.783804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 09:28:23.790272 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 09:28:23.793751 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 09:28:23.796988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 09:28:23.803996 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 09:28:23.807842 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 09:28:23.810425 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 09:28:23.813730 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 09:28:23.820851 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 09:28:23.824063 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 09:28:23.827392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 09:28:23.833639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5881 09:28:23.837169 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5882 09:28:23.840708 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 09:28:23.844148 Total UI for P1: 0, mck2ui 16
5884 09:28:23.847195 best dqsien dly found for B0: ( 1, 2, 22)
5885 09:28:23.850631 Total UI for P1: 0, mck2ui 16
5886 09:28:23.853815 best dqsien dly found for B1: ( 1, 2, 22)
5887 09:28:23.857081 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5888 09:28:23.860952 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5889 09:28:23.861067
5890 09:28:23.867187 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5891 09:28:23.870631 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5892 09:28:23.870810 [Gating] SW calibration Done
5893 09:28:23.874023 ==
5894 09:28:23.874151 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 09:28:23.880780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 09:28:23.880960 ==
5897 09:28:23.881065 RX Vref Scan: 0
5898 09:28:23.881156
5899 09:28:23.884061 RX Vref 0 -> 0, step: 1
5900 09:28:23.884173
5901 09:28:23.887540 RX Delay -80 -> 252, step: 8
5902 09:28:23.890814 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5903 09:28:23.894164 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5904 09:28:23.897380 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5905 09:28:23.901088 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5906 09:28:23.907998 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5907 09:28:23.910888 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5908 09:28:23.914301 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5909 09:28:23.917191 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5910 09:28:23.920785 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5911 09:28:23.924262 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5912 09:28:23.931086 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5913 09:28:23.934368 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5914 09:28:23.938053 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5915 09:28:23.940917 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5916 09:28:23.943939 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5917 09:28:23.947377 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5918 09:28:23.951105 ==
5919 09:28:23.951283 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 09:28:23.957707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 09:28:23.957858 ==
5922 09:28:23.957931 DQS Delay:
5923 09:28:23.961222 DQS0 = 0, DQS1 = 0
5924 09:28:23.961332 DQM Delay:
5925 09:28:23.964549 DQM0 = 95, DQM1 = 90
5926 09:28:23.964652 DQ Delay:
5927 09:28:23.967441 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =95
5928 09:28:23.971566 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5929 09:28:23.974120 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5930 09:28:23.978210 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5931 09:28:23.978342
5932 09:28:23.978414
5933 09:28:23.978516 ==
5934 09:28:23.981147 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 09:28:23.984307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 09:28:23.984415 ==
5937 09:28:23.984484
5938 09:28:23.984545
5939 09:28:23.987759 TX Vref Scan disable
5940 09:28:23.991070 == TX Byte 0 ==
5941 09:28:23.994581 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5942 09:28:23.997852 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5943 09:28:23.997999 == TX Byte 1 ==
5944 09:28:24.004781 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 09:28:24.007866 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 09:28:24.007983 ==
5947 09:28:24.010950 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 09:28:24.014571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 09:28:24.014743 ==
5950 09:28:24.014848
5951 09:28:24.017915
5952 09:28:24.018048 TX Vref Scan disable
5953 09:28:24.020838 == TX Byte 0 ==
5954 09:28:24.024375 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5955 09:28:24.027945 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5956 09:28:24.031294 == TX Byte 1 ==
5957 09:28:24.034328 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5958 09:28:24.037636 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5959 09:28:24.037792
5960 09:28:24.040877 [DATLAT]
5961 09:28:24.041008 Freq=933, CH1 RK1
5962 09:28:24.041078
5963 09:28:24.044493 DATLAT Default: 0xb
5964 09:28:24.044620 0, 0xFFFF, sum = 0
5965 09:28:24.047584 1, 0xFFFF, sum = 0
5966 09:28:24.047728 2, 0xFFFF, sum = 0
5967 09:28:24.050826 3, 0xFFFF, sum = 0
5968 09:28:24.050938 4, 0xFFFF, sum = 0
5969 09:28:24.054812 5, 0xFFFF, sum = 0
5970 09:28:24.054970 6, 0xFFFF, sum = 0
5971 09:28:24.057807 7, 0xFFFF, sum = 0
5972 09:28:24.057954 8, 0xFFFF, sum = 0
5973 09:28:24.061178 9, 0xFFFF, sum = 0
5974 09:28:24.061333 10, 0x0, sum = 1
5975 09:28:24.064283 11, 0x0, sum = 2
5976 09:28:24.064445 12, 0x0, sum = 3
5977 09:28:24.068116 13, 0x0, sum = 4
5978 09:28:24.068287 best_step = 11
5979 09:28:24.068390
5980 09:28:24.068516 ==
5981 09:28:24.071149 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 09:28:24.078009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 09:28:24.078208 ==
5984 09:28:24.078320 RX Vref Scan: 0
5985 09:28:24.078442
5986 09:28:24.081020 RX Vref 0 -> 0, step: 1
5987 09:28:24.081131
5988 09:28:24.084963 RX Delay -61 -> 252, step: 4
5989 09:28:24.088267 iDelay=195, Bit 0, Center 96 (7 ~ 186) 180
5990 09:28:24.091733 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5991 09:28:24.097888 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5992 09:28:24.101200 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5993 09:28:24.104371 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5994 09:28:24.108034 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5995 09:28:24.111406 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5996 09:28:24.114464 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5997 09:28:24.118232 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5998 09:28:24.124921 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5999 09:28:24.128313 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
6000 09:28:24.131597 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
6001 09:28:24.134700 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
6002 09:28:24.138250 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
6003 09:28:24.141152 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
6004 09:28:24.147816 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
6005 09:28:24.148008 ==
6006 09:28:24.150991 Dram Type= 6, Freq= 0, CH_1, rank 1
6007 09:28:24.154906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6008 09:28:24.155098 ==
6009 09:28:24.155203 DQS Delay:
6010 09:28:24.158019 DQS0 = 0, DQS1 = 0
6011 09:28:24.158165 DQM Delay:
6012 09:28:24.161041 DQM0 = 95, DQM1 = 90
6013 09:28:24.161180 DQ Delay:
6014 09:28:24.164699 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
6015 09:28:24.168264 DQ4 =98, DQ5 =104, DQ6 =104, DQ7 =92
6016 09:28:24.171013 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =82
6017 09:28:24.174803 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6018 09:28:24.174937
6019 09:28:24.175011
6020 09:28:24.184771 [DQSOSCAuto] RK1, (LSB)MR18= 0xc15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
6021 09:28:24.184955 CH1 RK1: MR19=505, MR18=C15
6022 09:28:24.191308 CH1_RK1: MR19=0x505, MR18=0xC15, DQSOSC=415, MR23=63, INC=62, DEC=41
6023 09:28:24.194478 [RxdqsGatingPostProcess] freq 933
6024 09:28:24.201582 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6025 09:28:24.204687 best DQS0 dly(2T, 0.5T) = (0, 10)
6026 09:28:24.204829 best DQS1 dly(2T, 0.5T) = (0, 10)
6027 09:28:24.207883 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6028 09:28:24.211456 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6029 09:28:24.214890 best DQS0 dly(2T, 0.5T) = (0, 10)
6030 09:28:24.217999 best DQS1 dly(2T, 0.5T) = (0, 10)
6031 09:28:24.221547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6032 09:28:24.224811 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6033 09:28:24.227981 Pre-setting of DQS Precalculation
6034 09:28:24.235014 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6035 09:28:24.241070 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6036 09:28:24.247895 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6037 09:28:24.248054
6038 09:28:24.248130
6039 09:28:24.251131 [Calibration Summary] 1866 Mbps
6040 09:28:24.251227 CH 0, Rank 0
6041 09:28:24.254680 SW Impedance : PASS
6042 09:28:24.254819 DUTY Scan : NO K
6043 09:28:24.258365 ZQ Calibration : PASS
6044 09:28:24.261420 Jitter Meter : NO K
6045 09:28:24.261522 CBT Training : PASS
6046 09:28:24.264859 Write leveling : PASS
6047 09:28:24.268116 RX DQS gating : PASS
6048 09:28:24.268232 RX DQ/DQS(RDDQC) : PASS
6049 09:28:24.271341 TX DQ/DQS : PASS
6050 09:28:24.274475 RX DATLAT : PASS
6051 09:28:24.274635 RX DQ/DQS(Engine): PASS
6052 09:28:24.278223 TX OE : NO K
6053 09:28:24.278358 All Pass.
6054 09:28:24.278470
6055 09:28:24.281740 CH 0, Rank 1
6056 09:28:24.281871 SW Impedance : PASS
6057 09:28:24.284726 DUTY Scan : NO K
6058 09:28:24.288381 ZQ Calibration : PASS
6059 09:28:24.288536 Jitter Meter : NO K
6060 09:28:24.291249 CBT Training : PASS
6061 09:28:24.291366 Write leveling : PASS
6062 09:28:24.294796 RX DQS gating : PASS
6063 09:28:24.298027 RX DQ/DQS(RDDQC) : PASS
6064 09:28:24.298177 TX DQ/DQS : PASS
6065 09:28:24.301694 RX DATLAT : PASS
6066 09:28:24.304661 RX DQ/DQS(Engine): PASS
6067 09:28:24.304804 TX OE : NO K
6068 09:28:24.308118 All Pass.
6069 09:28:24.308222
6070 09:28:24.308316 CH 1, Rank 0
6071 09:28:24.311257 SW Impedance : PASS
6072 09:28:24.311394 DUTY Scan : NO K
6073 09:28:24.314736 ZQ Calibration : PASS
6074 09:28:24.318039 Jitter Meter : NO K
6075 09:28:24.318194 CBT Training : PASS
6076 09:28:24.321869 Write leveling : PASS
6077 09:28:24.324756 RX DQS gating : PASS
6078 09:28:24.324919 RX DQ/DQS(RDDQC) : PASS
6079 09:28:24.328124 TX DQ/DQS : PASS
6080 09:28:24.328285 RX DATLAT : PASS
6081 09:28:24.331777 RX DQ/DQS(Engine): PASS
6082 09:28:24.334860 TX OE : NO K
6083 09:28:24.334994 All Pass.
6084 09:28:24.335064
6085 09:28:24.335124 CH 1, Rank 1
6086 09:28:24.338463 SW Impedance : PASS
6087 09:28:24.341452 DUTY Scan : NO K
6088 09:28:24.341594 ZQ Calibration : PASS
6089 09:28:24.345125 Jitter Meter : NO K
6090 09:28:24.348254 CBT Training : PASS
6091 09:28:24.348401 Write leveling : PASS
6092 09:28:24.351874 RX DQS gating : PASS
6093 09:28:24.355389 RX DQ/DQS(RDDQC) : PASS
6094 09:28:24.355506 TX DQ/DQS : PASS
6095 09:28:24.358010 RX DATLAT : PASS
6096 09:28:24.361828 RX DQ/DQS(Engine): PASS
6097 09:28:24.361943 TX OE : NO K
6098 09:28:24.365408 All Pass.
6099 09:28:24.365521
6100 09:28:24.365590 DramC Write-DBI off
6101 09:28:24.368515 PER_BANK_REFRESH: Hybrid Mode
6102 09:28:24.368617 TX_TRACKING: ON
6103 09:28:24.378250 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6104 09:28:24.381432 [FAST_K] Save calibration result to emmc
6105 09:28:24.385320 dramc_set_vcore_voltage set vcore to 650000
6106 09:28:24.388356 Read voltage for 400, 6
6107 09:28:24.388519 Vio18 = 0
6108 09:28:24.392216 Vcore = 650000
6109 09:28:24.392367 Vdram = 0
6110 09:28:24.392473 Vddq = 0
6111 09:28:24.392573 Vmddr = 0
6112 09:28:24.398450 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6113 09:28:24.401698 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6114 09:28:24.405183 MEM_TYPE=3, freq_sel=20
6115 09:28:24.408437 sv_algorithm_assistance_LP4_800
6116 09:28:24.411685 ============ PULL DRAM RESETB DOWN ============
6117 09:28:24.418842 ========== PULL DRAM RESETB DOWN end =========
6118 09:28:24.421762 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6119 09:28:24.425225 ===================================
6120 09:28:24.428559 LPDDR4 DRAM CONFIGURATION
6121 09:28:24.431816 ===================================
6122 09:28:24.431978 EX_ROW_EN[0] = 0x0
6123 09:28:24.434983 EX_ROW_EN[1] = 0x0
6124 09:28:24.435126 LP4Y_EN = 0x0
6125 09:28:24.438615 WORK_FSP = 0x0
6126 09:28:24.438780 WL = 0x2
6127 09:28:24.441673 RL = 0x2
6128 09:28:24.441809 BL = 0x2
6129 09:28:24.444884 RPST = 0x0
6130 09:28:24.445042 RD_PRE = 0x0
6131 09:28:24.448407 WR_PRE = 0x1
6132 09:28:24.448580 WR_PST = 0x0
6133 09:28:24.451880 DBI_WR = 0x0
6134 09:28:24.452038 DBI_RD = 0x0
6135 09:28:24.455260 OTF = 0x1
6136 09:28:24.458270 ===================================
6137 09:28:24.462072 ===================================
6138 09:28:24.462183 ANA top config
6139 09:28:24.465029 ===================================
6140 09:28:24.468652 DLL_ASYNC_EN = 0
6141 09:28:24.471688 ALL_SLAVE_EN = 1
6142 09:28:24.475405 NEW_RANK_MODE = 1
6143 09:28:24.475523 DLL_IDLE_MODE = 1
6144 09:28:24.478393 LP45_APHY_COMB_EN = 1
6145 09:28:24.482039 TX_ODT_DIS = 1
6146 09:28:24.485768 NEW_8X_MODE = 1
6147 09:28:24.488361 ===================================
6148 09:28:24.492079 ===================================
6149 09:28:24.495570 data_rate = 800
6150 09:28:24.495729 CKR = 1
6151 09:28:24.498474 DQ_P2S_RATIO = 4
6152 09:28:24.502225 ===================================
6153 09:28:24.505243 CA_P2S_RATIO = 4
6154 09:28:24.508789 DQ_CA_OPEN = 0
6155 09:28:24.511994 DQ_SEMI_OPEN = 1
6156 09:28:24.515164 CA_SEMI_OPEN = 1
6157 09:28:24.515264 CA_FULL_RATE = 0
6158 09:28:24.518476 DQ_CKDIV4_EN = 0
6159 09:28:24.522176 CA_CKDIV4_EN = 1
6160 09:28:24.525225 CA_PREDIV_EN = 0
6161 09:28:24.528610 PH8_DLY = 0
6162 09:28:24.528728 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6163 09:28:24.532108 DQ_AAMCK_DIV = 0
6164 09:28:24.535151 CA_AAMCK_DIV = 0
6165 09:28:24.538599 CA_ADMCK_DIV = 4
6166 09:28:24.542394 DQ_TRACK_CA_EN = 0
6167 09:28:24.545227 CA_PICK = 800
6168 09:28:24.548530 CA_MCKIO = 400
6169 09:28:24.548645 MCKIO_SEMI = 400
6170 09:28:24.552094 PLL_FREQ = 3016
6171 09:28:24.555211 DQ_UI_PI_RATIO = 32
6172 09:28:24.558872 CA_UI_PI_RATIO = 32
6173 09:28:24.561860 ===================================
6174 09:28:24.565274 ===================================
6175 09:28:24.568486 memory_type:LPDDR4
6176 09:28:24.568647 GP_NUM : 10
6177 09:28:24.571775 SRAM_EN : 1
6178 09:28:24.575155 MD32_EN : 0
6179 09:28:24.578603 ===================================
6180 09:28:24.578745 [ANA_INIT] >>>>>>>>>>>>>>
6181 09:28:24.581942 <<<<<< [CONFIGURE PHASE]: ANA_TX
6182 09:28:24.585771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6183 09:28:24.588896 ===================================
6184 09:28:24.591881 data_rate = 800,PCW = 0X7400
6185 09:28:24.595335 ===================================
6186 09:28:24.599152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6187 09:28:24.605418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6188 09:28:24.615181 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6189 09:28:24.618665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6190 09:28:24.621780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6191 09:28:24.625154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6192 09:28:24.628722 [ANA_INIT] flow start
6193 09:28:24.632093 [ANA_INIT] PLL >>>>>>>>
6194 09:28:24.632221 [ANA_INIT] PLL <<<<<<<<
6195 09:28:24.635061 [ANA_INIT] MIDPI >>>>>>>>
6196 09:28:24.638543 [ANA_INIT] MIDPI <<<<<<<<
6197 09:28:24.641842 [ANA_INIT] DLL >>>>>>>>
6198 09:28:24.641977 [ANA_INIT] flow end
6199 09:28:24.645016 ============ LP4 DIFF to SE enter ============
6200 09:28:24.651981 ============ LP4 DIFF to SE exit ============
6201 09:28:24.652167 [ANA_INIT] <<<<<<<<<<<<<
6202 09:28:24.655129 [Flow] Enable top DCM control >>>>>
6203 09:28:24.658407 [Flow] Enable top DCM control <<<<<
6204 09:28:24.662072 Enable DLL master slave shuffle
6205 09:28:24.668557 ==============================================================
6206 09:28:24.668783 Gating Mode config
6207 09:28:24.675422 ==============================================================
6208 09:28:24.678739 Config description:
6209 09:28:24.685912 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6210 09:28:24.692010 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6211 09:28:24.699049 SELPH_MODE 0: By rank 1: By Phase
6212 09:28:24.705870 ==============================================================
6213 09:28:24.706015 GAT_TRACK_EN = 0
6214 09:28:24.709229 RX_GATING_MODE = 2
6215 09:28:24.711975 RX_GATING_TRACK_MODE = 2
6216 09:28:24.715850 SELPH_MODE = 1
6217 09:28:24.719062 PICG_EARLY_EN = 1
6218 09:28:24.722230 VALID_LAT_VALUE = 1
6219 09:28:24.728940 ==============================================================
6220 09:28:24.732258 Enter into Gating configuration >>>>
6221 09:28:24.735342 Exit from Gating configuration <<<<
6222 09:28:24.738715 Enter into DVFS_PRE_config >>>>>
6223 09:28:24.749114 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6224 09:28:24.752221 Exit from DVFS_PRE_config <<<<<
6225 09:28:24.755813 Enter into PICG configuration >>>>
6226 09:28:24.758613 Exit from PICG configuration <<<<
6227 09:28:24.758762 [RX_INPUT] configuration >>>>>
6228 09:28:24.762235 [RX_INPUT] configuration <<<<<
6229 09:28:24.769006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6230 09:28:24.772475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6231 09:28:24.779037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6232 09:28:24.785408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6233 09:28:24.792294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6234 09:28:24.799199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6235 09:28:24.802247 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6236 09:28:24.805763 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6237 09:28:24.812364 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6238 09:28:24.815420 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6239 09:28:24.819059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6240 09:28:24.822264 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 09:28:24.825925 ===================================
6242 09:28:24.828906 LPDDR4 DRAM CONFIGURATION
6243 09:28:24.832015 ===================================
6244 09:28:24.835399 EX_ROW_EN[0] = 0x0
6245 09:28:24.835544 EX_ROW_EN[1] = 0x0
6246 09:28:24.838860 LP4Y_EN = 0x0
6247 09:28:24.838977 WORK_FSP = 0x0
6248 09:28:24.842399 WL = 0x2
6249 09:28:24.842547 RL = 0x2
6250 09:28:24.845713 BL = 0x2
6251 09:28:24.845862 RPST = 0x0
6252 09:28:24.848986 RD_PRE = 0x0
6253 09:28:24.849114 WR_PRE = 0x1
6254 09:28:24.852154 WR_PST = 0x0
6255 09:28:24.852313 DBI_WR = 0x0
6256 09:28:24.855674 DBI_RD = 0x0
6257 09:28:24.855825 OTF = 0x1
6258 09:28:24.859424 ===================================
6259 09:28:24.865632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6260 09:28:24.869118 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6261 09:28:24.872739 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6262 09:28:24.875728 ===================================
6263 09:28:24.879155 LPDDR4 DRAM CONFIGURATION
6264 09:28:24.882582 ===================================
6265 09:28:24.882765 EX_ROW_EN[0] = 0x10
6266 09:28:24.885899 EX_ROW_EN[1] = 0x0
6267 09:28:24.889065 LP4Y_EN = 0x0
6268 09:28:24.889214 WORK_FSP = 0x0
6269 09:28:24.892400 WL = 0x2
6270 09:28:24.892530 RL = 0x2
6271 09:28:24.895521 BL = 0x2
6272 09:28:24.895669 RPST = 0x0
6273 09:28:24.898953 RD_PRE = 0x0
6274 09:28:24.899108 WR_PRE = 0x1
6275 09:28:24.902128 WR_PST = 0x0
6276 09:28:24.902262 DBI_WR = 0x0
6277 09:28:24.905627 DBI_RD = 0x0
6278 09:28:24.905773 OTF = 0x1
6279 09:28:24.909219 ===================================
6280 09:28:24.915987 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6281 09:28:24.919906 nWR fixed to 30
6282 09:28:24.923252 [ModeRegInit_LP4] CH0 RK0
6283 09:28:24.923429 [ModeRegInit_LP4] CH0 RK1
6284 09:28:24.926793 [ModeRegInit_LP4] CH1 RK0
6285 09:28:24.929923 [ModeRegInit_LP4] CH1 RK1
6286 09:28:24.930121 match AC timing 19
6287 09:28:24.936606 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6288 09:28:24.940025 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6289 09:28:24.943144 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6290 09:28:24.950124 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6291 09:28:24.953673 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6292 09:28:24.953811 ==
6293 09:28:24.956531 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 09:28:24.960114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 09:28:24.960273 ==
6296 09:28:24.966825 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6297 09:28:24.973553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6298 09:28:24.977080 [CA 0] Center 36 (8~64) winsize 57
6299 09:28:24.979818 [CA 1] Center 36 (8~64) winsize 57
6300 09:28:24.979970 [CA 2] Center 36 (8~64) winsize 57
6301 09:28:24.983357 [CA 3] Center 36 (8~64) winsize 57
6302 09:28:24.986933 [CA 4] Center 36 (8~64) winsize 57
6303 09:28:24.990164 [CA 5] Center 36 (8~64) winsize 57
6304 09:28:24.990335
6305 09:28:24.993515 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6306 09:28:24.993667
6307 09:28:25.000132 [CATrainingPosCal] consider 1 rank data
6308 09:28:25.000317 u2DelayCellTimex100 = 270/100 ps
6309 09:28:25.003308 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 09:28:25.010132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 09:28:25.013646 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 09:28:25.017070 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 09:28:25.020133 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 09:28:25.023711 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 09:28:25.023830
6316 09:28:25.026650 CA PerBit enable=1, Macro0, CA PI delay=36
6317 09:28:25.026758
6318 09:28:25.030274 [CBTSetCACLKResult] CA Dly = 36
6319 09:28:25.030384 CS Dly: 1 (0~32)
6320 09:28:25.030455 ==
6321 09:28:25.033279 Dram Type= 6, Freq= 0, CH_0, rank 1
6322 09:28:25.040142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 09:28:25.040312 ==
6324 09:28:25.043881 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6325 09:28:25.050420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6326 09:28:25.053806 [CA 0] Center 36 (8~64) winsize 57
6327 09:28:25.056898 [CA 1] Center 36 (8~64) winsize 57
6328 09:28:25.060280 [CA 2] Center 36 (8~64) winsize 57
6329 09:28:25.063641 [CA 3] Center 36 (8~64) winsize 57
6330 09:28:25.067251 [CA 4] Center 36 (8~64) winsize 57
6331 09:28:25.070774 [CA 5] Center 36 (8~64) winsize 57
6332 09:28:25.070906
6333 09:28:25.073562 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6334 09:28:25.073668
6335 09:28:25.076889 [CATrainingPosCal] consider 2 rank data
6336 09:28:25.080672 u2DelayCellTimex100 = 270/100 ps
6337 09:28:25.083869 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 09:28:25.087161 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 09:28:25.090955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 09:28:25.094069 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 09:28:25.097560 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 09:28:25.100560 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 09:28:25.100679
6344 09:28:25.107555 CA PerBit enable=1, Macro0, CA PI delay=36
6345 09:28:25.107747
6346 09:28:25.107865 [CBTSetCACLKResult] CA Dly = 36
6347 09:28:25.110598 CS Dly: 1 (0~32)
6348 09:28:25.110743
6349 09:28:25.113807 ----->DramcWriteLeveling(PI) begin...
6350 09:28:25.113936 ==
6351 09:28:25.117283 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 09:28:25.120555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 09:28:25.120675 ==
6354 09:28:25.123942 Write leveling (Byte 0): 40 => 8
6355 09:28:25.127423 Write leveling (Byte 1): 32 => 0
6356 09:28:25.130844 DramcWriteLeveling(PI) end<-----
6357 09:28:25.130996
6358 09:28:25.131066 ==
6359 09:28:25.133830 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 09:28:25.137108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 09:28:25.137212 ==
6362 09:28:25.140524 [Gating] SW mode calibration
6363 09:28:25.147541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6364 09:28:25.153812 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6365 09:28:25.157571 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6366 09:28:25.164011 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6367 09:28:25.167325 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 09:28:25.171103 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6369 09:28:25.173894 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 09:28:25.180770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 09:28:25.183911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 09:28:25.187395 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 09:28:25.193853 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6374 09:28:25.197681 Total UI for P1: 0, mck2ui 16
6375 09:28:25.200838 best dqsien dly found for B0: ( 0, 14, 24)
6376 09:28:25.200990 Total UI for P1: 0, mck2ui 16
6377 09:28:25.207711 best dqsien dly found for B1: ( 0, 14, 24)
6378 09:28:25.210814 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6379 09:28:25.214204 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6380 09:28:25.214365
6381 09:28:25.217573 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6382 09:28:25.220805 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6383 09:28:25.224183 [Gating] SW calibration Done
6384 09:28:25.224330 ==
6385 09:28:25.227887 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 09:28:25.230851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 09:28:25.231009 ==
6388 09:28:25.234235 RX Vref Scan: 0
6389 09:28:25.234361
6390 09:28:25.234465 RX Vref 0 -> 0, step: 1
6391 09:28:25.234558
6392 09:28:25.237604 RX Delay -410 -> 252, step: 16
6393 09:28:25.244071 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6394 09:28:25.247519 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6395 09:28:25.250710 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6396 09:28:25.254386 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6397 09:28:25.260916 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6398 09:28:25.265033 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6399 09:28:25.267510 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6400 09:28:25.271489 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6401 09:28:25.277363 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6402 09:28:25.280928 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6403 09:28:25.284062 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6404 09:28:25.287446 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6405 09:28:25.293906 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6406 09:28:25.297751 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6407 09:28:25.301104 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6408 09:28:25.304107 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6409 09:28:25.307982 ==
6410 09:28:25.308133 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 09:28:25.314135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 09:28:25.314305 ==
6413 09:28:25.314408 DQS Delay:
6414 09:28:25.317999 DQS0 = 35, DQS1 = 51
6415 09:28:25.318131 DQM Delay:
6416 09:28:25.321014 DQM0 = 6, DQM1 = 10
6417 09:28:25.321130 DQ Delay:
6418 09:28:25.323941 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6419 09:28:25.327344 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6420 09:28:25.327472 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6421 09:28:25.330692 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6422 09:28:25.334095
6423 09:28:25.334241
6424 09:28:25.334315 ==
6425 09:28:25.337767 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 09:28:25.340584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 09:28:25.340729 ==
6428 09:28:25.340830
6429 09:28:25.340926
6430 09:28:25.344116 TX Vref Scan disable
6431 09:28:25.344240 == TX Byte 0 ==
6432 09:28:25.347243 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 09:28:25.354568 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 09:28:25.354758 == TX Byte 1 ==
6435 09:28:25.357320 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6436 09:28:25.364116 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6437 09:28:25.364286 ==
6438 09:28:25.367432 Dram Type= 6, Freq= 0, CH_0, rank 0
6439 09:28:25.371033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 09:28:25.371168 ==
6441 09:28:25.371243
6442 09:28:25.371305
6443 09:28:25.374943 TX Vref Scan disable
6444 09:28:25.375084 == TX Byte 0 ==
6445 09:28:25.377902 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6446 09:28:25.383778 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6447 09:28:25.383898 == TX Byte 1 ==
6448 09:28:25.387536 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6449 09:28:25.394014 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6450 09:28:25.394158
6451 09:28:25.394264 [DATLAT]
6452 09:28:25.397162 Freq=400, CH0 RK0
6453 09:28:25.397288
6454 09:28:25.397385 DATLAT Default: 0xf
6455 09:28:25.400859 0, 0xFFFF, sum = 0
6456 09:28:25.400952 1, 0xFFFF, sum = 0
6457 09:28:25.403790 2, 0xFFFF, sum = 0
6458 09:28:25.403884 3, 0xFFFF, sum = 0
6459 09:28:25.407631 4, 0xFFFF, sum = 0
6460 09:28:25.407727 5, 0xFFFF, sum = 0
6461 09:28:25.410781 6, 0xFFFF, sum = 0
6462 09:28:25.410875 7, 0xFFFF, sum = 0
6463 09:28:25.413818 8, 0xFFFF, sum = 0
6464 09:28:25.413909 9, 0xFFFF, sum = 0
6465 09:28:25.417404 10, 0xFFFF, sum = 0
6466 09:28:25.417529 11, 0xFFFF, sum = 0
6467 09:28:25.420896 12, 0xFFFF, sum = 0
6468 09:28:25.420988 13, 0x0, sum = 1
6469 09:28:25.424267 14, 0x0, sum = 2
6470 09:28:25.424363 15, 0x0, sum = 3
6471 09:28:25.427837 16, 0x0, sum = 4
6472 09:28:25.427929 best_step = 14
6473 09:28:25.427996
6474 09:28:25.428058 ==
6475 09:28:25.431009 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 09:28:25.437587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 09:28:25.437698 ==
6478 09:28:25.437768 RX Vref Scan: 1
6479 09:28:25.437829
6480 09:28:25.441311 RX Vref 0 -> 0, step: 1
6481 09:28:25.441399
6482 09:28:25.444295 RX Delay -343 -> 252, step: 8
6483 09:28:25.444384
6484 09:28:25.447620 Set Vref, RX VrefLevel [Byte0]: 53
6485 09:28:25.450920 [Byte1]: 51
6486 09:28:25.451031
6487 09:28:25.454147 Final RX Vref Byte 0 = 53 to rank0
6488 09:28:25.457632 Final RX Vref Byte 1 = 51 to rank0
6489 09:28:25.461103 Final RX Vref Byte 0 = 53 to rank1
6490 09:28:25.464138 Final RX Vref Byte 1 = 51 to rank1==
6491 09:28:25.467951 Dram Type= 6, Freq= 0, CH_0, rank 0
6492 09:28:25.470901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 09:28:25.471051 ==
6494 09:28:25.474708 DQS Delay:
6495 09:28:25.474846 DQS0 = 44, DQS1 = 60
6496 09:28:25.477873 DQM Delay:
6497 09:28:25.478002 DQM0 = 11, DQM1 = 15
6498 09:28:25.478099 DQ Delay:
6499 09:28:25.481071 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =12
6500 09:28:25.484363 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6501 09:28:25.487689 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6502 09:28:25.491483 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6503 09:28:25.491601
6504 09:28:25.491674
6505 09:28:25.501224 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6506 09:28:25.501373 CH0 RK0: MR19=C0C, MR18=8E5C
6507 09:28:25.508255 CH0_RK0: MR19=0xC0C, MR18=0x8E5C, DQSOSC=392, MR23=63, INC=384, DEC=256
6508 09:28:25.508389 ==
6509 09:28:25.511101 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 09:28:25.517933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 09:28:25.518096 ==
6512 09:28:25.521275 [Gating] SW mode calibration
6513 09:28:25.528017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6514 09:28:25.531436 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6515 09:28:25.538045 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 09:28:25.541433 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6517 09:28:25.544763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 09:28:25.548149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 09:28:25.554633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 09:28:25.558066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 09:28:25.561166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 09:28:25.568019 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 09:28:25.571395 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6524 09:28:25.574438 Total UI for P1: 0, mck2ui 16
6525 09:28:25.577812 best dqsien dly found for B0: ( 0, 14, 24)
6526 09:28:25.581384 Total UI for P1: 0, mck2ui 16
6527 09:28:25.584959 best dqsien dly found for B1: ( 0, 14, 24)
6528 09:28:25.588441 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6529 09:28:25.591419 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6530 09:28:25.591555
6531 09:28:25.594765 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6532 09:28:25.598191 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6533 09:28:25.601376 [Gating] SW calibration Done
6534 09:28:25.601515 ==
6535 09:28:25.604716 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 09:28:25.608524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 09:28:25.611666 ==
6538 09:28:25.611798 RX Vref Scan: 0
6539 09:28:25.611873
6540 09:28:25.614968 RX Vref 0 -> 0, step: 1
6541 09:28:25.615075
6542 09:28:25.617872 RX Delay -410 -> 252, step: 16
6543 09:28:25.621473 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6544 09:28:25.624641 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6545 09:28:25.627938 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6546 09:28:25.634858 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6547 09:28:25.638127 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6548 09:28:25.641860 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6549 09:28:25.644799 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6550 09:28:25.651730 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6551 09:28:25.654830 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6552 09:28:25.658270 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6553 09:28:25.661543 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6554 09:28:25.668118 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6555 09:28:25.671259 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6556 09:28:25.674894 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6557 09:28:25.677976 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6558 09:28:25.684738 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6559 09:28:25.684919 ==
6560 09:28:25.688378 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 09:28:25.691563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 09:28:25.691723 ==
6563 09:28:25.691824 DQS Delay:
6564 09:28:25.694763 DQS0 = 43, DQS1 = 51
6565 09:28:25.694892 DQM Delay:
6566 09:28:25.698099 DQM0 = 11, DQM1 = 9
6567 09:28:25.698296 DQ Delay:
6568 09:28:25.701414 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6569 09:28:25.705384 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6570 09:28:25.708347 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6571 09:28:25.711678 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6572 09:28:25.711805
6573 09:28:25.711874
6574 09:28:25.711936 ==
6575 09:28:25.715206 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 09:28:25.718540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 09:28:25.718658 ==
6578 09:28:25.718791
6579 09:28:25.718856
6580 09:28:25.721566 TX Vref Scan disable
6581 09:28:25.721662 == TX Byte 0 ==
6582 09:28:25.728464 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6583 09:28:25.731882 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6584 09:28:25.732013 == TX Byte 1 ==
6585 09:28:25.735159 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6586 09:28:25.741971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6587 09:28:25.742257 ==
6588 09:28:25.745496 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 09:28:25.748552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 09:28:25.748727 ==
6591 09:28:25.748821
6592 09:28:25.748905
6593 09:28:25.751759 TX Vref Scan disable
6594 09:28:25.751874 == TX Byte 0 ==
6595 09:28:25.755709 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6596 09:28:25.762157 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6597 09:28:25.762326 == TX Byte 1 ==
6598 09:28:25.765093 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6599 09:28:25.772244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6600 09:28:25.772381
6601 09:28:25.772477 [DATLAT]
6602 09:28:25.772560 Freq=400, CH0 RK1
6603 09:28:25.772640
6604 09:28:25.775918 DATLAT Default: 0xe
6605 09:28:25.778604 0, 0xFFFF, sum = 0
6606 09:28:25.778708 1, 0xFFFF, sum = 0
6607 09:28:25.782410 2, 0xFFFF, sum = 0
6608 09:28:25.782543 3, 0xFFFF, sum = 0
6609 09:28:25.785433 4, 0xFFFF, sum = 0
6610 09:28:25.785537 5, 0xFFFF, sum = 0
6611 09:28:25.789014 6, 0xFFFF, sum = 0
6612 09:28:25.789215 7, 0xFFFF, sum = 0
6613 09:28:25.791920 8, 0xFFFF, sum = 0
6614 09:28:25.792021 9, 0xFFFF, sum = 0
6615 09:28:25.795434 10, 0xFFFF, sum = 0
6616 09:28:25.795571 11, 0xFFFF, sum = 0
6617 09:28:25.798623 12, 0xFFFF, sum = 0
6618 09:28:25.798765 13, 0x0, sum = 1
6619 09:28:25.802143 14, 0x0, sum = 2
6620 09:28:25.802238 15, 0x0, sum = 3
6621 09:28:25.805371 16, 0x0, sum = 4
6622 09:28:25.805478 best_step = 14
6623 09:28:25.805543
6624 09:28:25.805604 ==
6625 09:28:25.808544 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 09:28:25.811868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 09:28:25.815917 ==
6628 09:28:25.816077 RX Vref Scan: 0
6629 09:28:25.816181
6630 09:28:25.818733 RX Vref 0 -> 0, step: 1
6631 09:28:25.818864
6632 09:28:25.821836 RX Delay -343 -> 252, step: 8
6633 09:28:25.825916 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6634 09:28:25.832110 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6635 09:28:25.835784 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6636 09:28:25.838663 iDelay=217, Bit 3, Center -32 (-271 ~ 208) 480
6637 09:28:25.842304 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6638 09:28:25.848823 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6639 09:28:25.852017 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6640 09:28:25.855466 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6641 09:28:25.858604 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6642 09:28:25.865700 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6643 09:28:25.868906 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6644 09:28:25.871920 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6645 09:28:25.875322 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6646 09:28:25.881883 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6647 09:28:25.885237 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6648 09:28:25.888458 iDelay=217, Bit 15, Center -32 (-271 ~ 208) 480
6649 09:28:25.888623 ==
6650 09:28:25.891993 Dram Type= 6, Freq= 0, CH_0, rank 1
6651 09:28:25.898633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 09:28:25.898771 ==
6653 09:28:25.898844 DQS Delay:
6654 09:28:25.902263 DQS0 = 44, DQS1 = 60
6655 09:28:25.902348 DQM Delay:
6656 09:28:25.902413 DQM0 = 10, DQM1 = 14
6657 09:28:25.905461 DQ Delay:
6658 09:28:25.908706 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6659 09:28:25.908815 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6660 09:28:25.912245 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =4
6661 09:28:25.915997 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =28
6662 09:28:25.916089
6663 09:28:25.916153
6664 09:28:25.925331 [DQSOSCAuto] RK1, (LSB)MR18= 0x9b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6665 09:28:25.928775 CH0 RK1: MR19=C0C, MR18=9B6E
6666 09:28:25.935796 CH0_RK1: MR19=0xC0C, MR18=0x9B6E, DQSOSC=390, MR23=63, INC=388, DEC=258
6667 09:28:25.935908 [RxdqsGatingPostProcess] freq 400
6668 09:28:25.942119 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6669 09:28:25.945613 best DQS0 dly(2T, 0.5T) = (0, 10)
6670 09:28:25.949069 best DQS1 dly(2T, 0.5T) = (0, 10)
6671 09:28:25.952204 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6672 09:28:25.955497 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6673 09:28:25.958888 best DQS0 dly(2T, 0.5T) = (0, 10)
6674 09:28:25.962384 best DQS1 dly(2T, 0.5T) = (0, 10)
6675 09:28:25.965569 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6676 09:28:25.969101 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6677 09:28:25.972309 Pre-setting of DQS Precalculation
6678 09:28:25.975561 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6679 09:28:25.975677 ==
6680 09:28:25.978960 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 09:28:25.982333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 09:28:25.982448 ==
6683 09:28:25.989966 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6684 09:28:25.995769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6685 09:28:25.999238 [CA 0] Center 36 (8~64) winsize 57
6686 09:28:26.002520 [CA 1] Center 36 (8~64) winsize 57
6687 09:28:26.006003 [CA 2] Center 36 (8~64) winsize 57
6688 09:28:26.006124 [CA 3] Center 36 (8~64) winsize 57
6689 09:28:26.009138 [CA 4] Center 36 (8~64) winsize 57
6690 09:28:26.012528 [CA 5] Center 36 (8~64) winsize 57
6691 09:28:26.012643
6692 09:28:26.019052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6693 09:28:26.019179
6694 09:28:26.022651 [CATrainingPosCal] consider 1 rank data
6695 09:28:26.025870 u2DelayCellTimex100 = 270/100 ps
6696 09:28:26.029205 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 09:28:26.032959 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 09:28:26.036275 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 09:28:26.039245 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 09:28:26.042400 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 09:28:26.045736 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 09:28:26.045856
6703 09:28:26.049355 CA PerBit enable=1, Macro0, CA PI delay=36
6704 09:28:26.049474
6705 09:28:26.052417 [CBTSetCACLKResult] CA Dly = 36
6706 09:28:26.056290 CS Dly: 1 (0~32)
6707 09:28:26.056410 ==
6708 09:28:26.059052 Dram Type= 6, Freq= 0, CH_1, rank 1
6709 09:28:26.062990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 09:28:26.063121 ==
6711 09:28:26.069609 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6712 09:28:26.072673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6713 09:28:26.075821 [CA 0] Center 36 (8~64) winsize 57
6714 09:28:26.079270 [CA 1] Center 36 (8~64) winsize 57
6715 09:28:26.082620 [CA 2] Center 36 (8~64) winsize 57
6716 09:28:26.086123 [CA 3] Center 36 (8~64) winsize 57
6717 09:28:26.089082 [CA 4] Center 36 (8~64) winsize 57
6718 09:28:26.092559 [CA 5] Center 36 (8~64) winsize 57
6719 09:28:26.092699
6720 09:28:26.095945 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6721 09:28:26.096078
6722 09:28:26.099700 [CATrainingPosCal] consider 2 rank data
6723 09:28:26.102609 u2DelayCellTimex100 = 270/100 ps
6724 09:28:26.106125 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 09:28:26.109632 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 09:28:26.112449 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 09:28:26.116183 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 09:28:26.122883 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 09:28:26.126069 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 09:28:26.126189
6731 09:28:26.129198 CA PerBit enable=1, Macro0, CA PI delay=36
6732 09:28:26.129312
6733 09:28:26.132603 [CBTSetCACLKResult] CA Dly = 36
6734 09:28:26.132717 CS Dly: 1 (0~32)
6735 09:28:26.132818
6736 09:28:26.136017 ----->DramcWriteLeveling(PI) begin...
6737 09:28:26.136131 ==
6738 09:28:26.139099 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 09:28:26.145771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 09:28:26.145891 ==
6741 09:28:26.149395 Write leveling (Byte 0): 40 => 8
6742 09:28:26.149545 Write leveling (Byte 1): 40 => 8
6743 09:28:26.152751 DramcWriteLeveling(PI) end<-----
6744 09:28:26.152868
6745 09:28:26.152964 ==
6746 09:28:26.155987 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 09:28:26.162849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 09:28:26.162968 ==
6749 09:28:26.165736 [Gating] SW mode calibration
6750 09:28:26.172266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6751 09:28:26.175653 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6752 09:28:26.182705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6753 09:28:26.185781 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6754 09:28:26.188988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 09:28:26.196190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6756 09:28:26.199196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 09:28:26.202968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 09:28:26.205974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 09:28:26.212674 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 09:28:26.216056 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6761 09:28:26.219184 Total UI for P1: 0, mck2ui 16
6762 09:28:26.223081 best dqsien dly found for B0: ( 0, 14, 24)
6763 09:28:26.225936 Total UI for P1: 0, mck2ui 16
6764 09:28:26.229332 best dqsien dly found for B1: ( 0, 14, 24)
6765 09:28:26.232604 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6766 09:28:26.235855 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6767 09:28:26.235985
6768 09:28:26.239264 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6769 09:28:26.242696 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6770 09:28:26.246462 [Gating] SW calibration Done
6771 09:28:26.246624 ==
6772 09:28:26.249357 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 09:28:26.255911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 09:28:26.256073 ==
6775 09:28:26.256180 RX Vref Scan: 0
6776 09:28:26.256279
6777 09:28:26.259182 RX Vref 0 -> 0, step: 1
6778 09:28:26.259296
6779 09:28:26.262632 RX Delay -410 -> 252, step: 16
6780 09:28:26.265879 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6781 09:28:26.269368 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6782 09:28:26.272906 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6783 09:28:26.279407 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6784 09:28:26.283095 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6785 09:28:26.285921 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6786 09:28:26.289559 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6787 09:28:26.296263 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6788 09:28:26.299313 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6789 09:28:26.302892 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6790 09:28:26.306149 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6791 09:28:26.313120 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6792 09:28:26.316188 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6793 09:28:26.319653 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6794 09:28:26.322686 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6795 09:28:26.329463 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6796 09:28:26.329574 ==
6797 09:28:26.332911 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 09:28:26.336323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 09:28:26.336431 ==
6800 09:28:26.336519 DQS Delay:
6801 09:28:26.339367 DQS0 = 51, DQS1 = 59
6802 09:28:26.339443 DQM Delay:
6803 09:28:26.343155 DQM0 = 19, DQM1 = 16
6804 09:28:26.343232 DQ Delay:
6805 09:28:26.346170 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6806 09:28:26.349599 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6807 09:28:26.352858 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6808 09:28:26.356562 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6809 09:28:26.356642
6810 09:28:26.356706
6811 09:28:26.356765 ==
6812 09:28:26.359439 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 09:28:26.363121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 09:28:26.363213 ==
6815 09:28:26.363281
6816 09:28:26.363341
6817 09:28:26.366249 TX Vref Scan disable
6818 09:28:26.369442 == TX Byte 0 ==
6819 09:28:26.372861 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 09:28:26.376171 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 09:28:26.379837 == TX Byte 1 ==
6822 09:28:26.382881 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 09:28:26.386659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 09:28:26.386767 ==
6825 09:28:26.389877 Dram Type= 6, Freq= 0, CH_1, rank 0
6826 09:28:26.392912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 09:28:26.392998 ==
6828 09:28:26.393063
6829 09:28:26.393123
6830 09:28:26.396549 TX Vref Scan disable
6831 09:28:26.399670 == TX Byte 0 ==
6832 09:28:26.403266 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 09:28:26.406671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 09:28:26.406847 == TX Byte 1 ==
6835 09:28:26.413397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 09:28:26.416760 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 09:28:26.416918
6838 09:28:26.417016 [DATLAT]
6839 09:28:26.419734 Freq=400, CH1 RK0
6840 09:28:26.419881
6841 09:28:26.419979 DATLAT Default: 0xf
6842 09:28:26.423612 0, 0xFFFF, sum = 0
6843 09:28:26.423744 1, 0xFFFF, sum = 0
6844 09:28:26.426376 2, 0xFFFF, sum = 0
6845 09:28:26.426458 3, 0xFFFF, sum = 0
6846 09:28:26.430120 4, 0xFFFF, sum = 0
6847 09:28:26.430204 5, 0xFFFF, sum = 0
6848 09:28:26.433363 6, 0xFFFF, sum = 0
6849 09:28:26.433447 7, 0xFFFF, sum = 0
6850 09:28:26.436501 8, 0xFFFF, sum = 0
6851 09:28:26.436584 9, 0xFFFF, sum = 0
6852 09:28:26.439961 10, 0xFFFF, sum = 0
6853 09:28:26.443490 11, 0xFFFF, sum = 0
6854 09:28:26.443574 12, 0xFFFF, sum = 0
6855 09:28:26.446600 13, 0x0, sum = 1
6856 09:28:26.446714 14, 0x0, sum = 2
6857 09:28:26.449814 15, 0x0, sum = 3
6858 09:28:26.449904 16, 0x0, sum = 4
6859 09:28:26.449983 best_step = 14
6860 09:28:26.450041
6861 09:28:26.453297 ==
6862 09:28:26.453380 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 09:28:26.460368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 09:28:26.460525 ==
6865 09:28:26.460674 RX Vref Scan: 1
6866 09:28:26.460818
6867 09:28:26.463374 RX Vref 0 -> 0, step: 1
6868 09:28:26.463455
6869 09:28:26.466912 RX Delay -359 -> 252, step: 8
6870 09:28:26.466994
6871 09:28:26.469877 Set Vref, RX VrefLevel [Byte0]: 58
6872 09:28:26.473353 [Byte1]: 53
6873 09:28:26.476919
6874 09:28:26.477051 Final RX Vref Byte 0 = 58 to rank0
6875 09:28:26.480034 Final RX Vref Byte 1 = 53 to rank0
6876 09:28:26.483370 Final RX Vref Byte 0 = 58 to rank1
6877 09:28:26.486815 Final RX Vref Byte 1 = 53 to rank1==
6878 09:28:26.490026 Dram Type= 6, Freq= 0, CH_1, rank 0
6879 09:28:26.497306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 09:28:26.497431 ==
6881 09:28:26.497514 DQS Delay:
6882 09:28:26.497592 DQS0 = 48, DQS1 = 60
6883 09:28:26.500041 DQM Delay:
6884 09:28:26.500144 DQM0 = 11, DQM1 = 13
6885 09:28:26.503687 DQ Delay:
6886 09:28:26.506915 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6887 09:28:26.507017 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6888 09:28:26.510453 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6889 09:28:26.513807 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6890 09:28:26.513909
6891 09:28:26.514005
6892 09:28:26.523827 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e36, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6893 09:28:26.526915 CH1 RK0: MR19=C0C, MR18=8E36
6894 09:28:26.534069 CH1_RK0: MR19=0xC0C, MR18=0x8E36, DQSOSC=392, MR23=63, INC=384, DEC=256
6895 09:28:26.534162 ==
6896 09:28:26.536880 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 09:28:26.540479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 09:28:26.540565 ==
6899 09:28:26.543564 [Gating] SW mode calibration
6900 09:28:26.550399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6901 09:28:26.553619 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6902 09:28:26.560539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6903 09:28:26.563756 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6904 09:28:26.567112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 09:28:26.574084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6906 09:28:26.577031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 09:28:26.580486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 09:28:26.587312 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 09:28:26.590660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 09:28:26.593950 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6911 09:28:26.597323 Total UI for P1: 0, mck2ui 16
6912 09:28:26.601002 best dqsien dly found for B0: ( 0, 14, 24)
6913 09:28:26.603980 Total UI for P1: 0, mck2ui 16
6914 09:28:26.606947 best dqsien dly found for B1: ( 0, 14, 24)
6915 09:28:26.610379 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6916 09:28:26.613925 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6917 09:28:26.614029
6918 09:28:26.617353 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6919 09:28:26.623694 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6920 09:28:26.623811 [Gating] SW calibration Done
6921 09:28:26.623893 ==
6922 09:28:26.627436 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 09:28:26.634165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 09:28:26.634270 ==
6925 09:28:26.634369 RX Vref Scan: 0
6926 09:28:26.634445
6927 09:28:26.637788 RX Vref 0 -> 0, step: 1
6928 09:28:26.637886
6929 09:28:26.640806 RX Delay -410 -> 252, step: 16
6930 09:28:26.644319 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6931 09:28:26.647659 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6932 09:28:26.653941 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6933 09:28:26.657306 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6934 09:28:26.660734 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6935 09:28:26.664296 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6936 09:28:26.667242 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6937 09:28:26.673864 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6938 09:28:26.677742 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6939 09:28:26.680739 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6940 09:28:26.684242 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6941 09:28:26.690667 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6942 09:28:26.694128 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6943 09:28:26.697403 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6944 09:28:26.703878 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6945 09:28:26.707626 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6946 09:28:26.707794 ==
6947 09:28:26.710718 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 09:28:26.714193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 09:28:26.714295 ==
6950 09:28:26.717421 DQS Delay:
6951 09:28:26.717520 DQS0 = 43, DQS1 = 59
6952 09:28:26.717616 DQM Delay:
6953 09:28:26.720857 DQM0 = 10, DQM1 = 19
6954 09:28:26.720961 DQ Delay:
6955 09:28:26.724024 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6956 09:28:26.727537 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6957 09:28:26.730875 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6958 09:28:26.733888 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6959 09:28:26.734006
6960 09:28:26.734088
6961 09:28:26.734165 ==
6962 09:28:26.738284 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 09:28:26.740715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 09:28:26.740838 ==
6965 09:28:26.740918
6966 09:28:26.743977
6967 09:28:26.744088 TX Vref Scan disable
6968 09:28:26.747616 == TX Byte 0 ==
6969 09:28:26.751100 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6970 09:28:26.753962 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6971 09:28:26.757462 == TX Byte 1 ==
6972 09:28:26.761359 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6973 09:28:26.764343 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6974 09:28:26.764450 ==
6975 09:28:26.767677 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 09:28:26.770764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 09:28:26.770874 ==
6978 09:28:26.770972
6979 09:28:26.771048
6980 09:28:26.773996 TX Vref Scan disable
6981 09:28:26.777847 == TX Byte 0 ==
6982 09:28:26.781157 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6983 09:28:26.784099 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6984 09:28:26.784200 == TX Byte 1 ==
6985 09:28:26.791124 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6986 09:28:26.794396 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6987 09:28:26.794481
6988 09:28:26.794544 [DATLAT]
6989 09:28:26.797405 Freq=400, CH1 RK1
6990 09:28:26.797489
6991 09:28:26.797572 DATLAT Default: 0xe
6992 09:28:26.800677 0, 0xFFFF, sum = 0
6993 09:28:26.800766 1, 0xFFFF, sum = 0
6994 09:28:26.804609 2, 0xFFFF, sum = 0
6995 09:28:26.804695 3, 0xFFFF, sum = 0
6996 09:28:26.807655 4, 0xFFFF, sum = 0
6997 09:28:26.807796 5, 0xFFFF, sum = 0
6998 09:28:26.810868 6, 0xFFFF, sum = 0
6999 09:28:26.810955 7, 0xFFFF, sum = 0
7000 09:28:26.813995 8, 0xFFFF, sum = 0
7001 09:28:26.817958 9, 0xFFFF, sum = 0
7002 09:28:26.818077 10, 0xFFFF, sum = 0
7003 09:28:26.820889 11, 0xFFFF, sum = 0
7004 09:28:26.820978 12, 0xFFFF, sum = 0
7005 09:28:26.824185 13, 0x0, sum = 1
7006 09:28:26.824271 14, 0x0, sum = 2
7007 09:28:26.827316 15, 0x0, sum = 3
7008 09:28:26.827426 16, 0x0, sum = 4
7009 09:28:26.827514 best_step = 14
7010 09:28:26.827582
7011 09:28:26.831191 ==
7012 09:28:26.834477 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 09:28:26.837601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 09:28:26.837688 ==
7015 09:28:26.837761 RX Vref Scan: 0
7016 09:28:26.837860
7017 09:28:26.841021 RX Vref 0 -> 0, step: 1
7018 09:28:26.841106
7019 09:28:26.844324 RX Delay -359 -> 252, step: 8
7020 09:28:26.851172 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7021 09:28:26.854705 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7022 09:28:26.858286 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7023 09:28:26.861577 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7024 09:28:26.868106 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7025 09:28:26.871329 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7026 09:28:26.874414 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7027 09:28:26.877835 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7028 09:28:26.885067 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7029 09:28:26.887979 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7030 09:28:26.891422 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7031 09:28:26.895127 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
7032 09:28:26.901391 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7033 09:28:26.904802 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7034 09:28:26.908222 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7035 09:28:26.911847 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7036 09:28:26.915031 ==
7037 09:28:26.915210 Dram Type= 6, Freq= 0, CH_1, rank 1
7038 09:28:26.921886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7039 09:28:26.921979 ==
7040 09:28:26.922076 DQS Delay:
7041 09:28:26.924760 DQS0 = 52, DQS1 = 56
7042 09:28:26.924844 DQM Delay:
7043 09:28:26.928195 DQM0 = 13, DQM1 = 9
7044 09:28:26.928278 DQ Delay:
7045 09:28:26.931467 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7046 09:28:26.935448 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7047 09:28:26.935535 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7048 09:28:26.938505 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7049 09:28:26.941768
7050 09:28:26.941851
7051 09:28:26.948187 [DQSOSCAuto] RK1, (LSB)MR18= 0x798e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7052 09:28:26.951629 CH1 RK1: MR19=C0C, MR18=798E
7053 09:28:26.958641 CH1_RK1: MR19=0xC0C, MR18=0x798E, DQSOSC=392, MR23=63, INC=384, DEC=256
7054 09:28:26.962047 [RxdqsGatingPostProcess] freq 400
7055 09:28:26.965290 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7056 09:28:26.968259 best DQS0 dly(2T, 0.5T) = (0, 10)
7057 09:28:26.971690 best DQS1 dly(2T, 0.5T) = (0, 10)
7058 09:28:26.975246 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7059 09:28:26.978513 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7060 09:28:26.982023 best DQS0 dly(2T, 0.5T) = (0, 10)
7061 09:28:26.985294 best DQS1 dly(2T, 0.5T) = (0, 10)
7062 09:28:26.988622 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7063 09:28:26.991804 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7064 09:28:26.995333 Pre-setting of DQS Precalculation
7065 09:28:26.998494 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7066 09:28:27.005455 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7067 09:28:27.012624 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7068 09:28:27.015783
7069 09:28:27.015880
7070 09:28:27.015966 [Calibration Summary] 800 Mbps
7071 09:28:27.018688 CH 0, Rank 0
7072 09:28:27.018826 SW Impedance : PASS
7073 09:28:27.021861 DUTY Scan : NO K
7074 09:28:27.025216 ZQ Calibration : PASS
7075 09:28:27.025305 Jitter Meter : NO K
7076 09:28:27.028669 CBT Training : PASS
7077 09:28:27.032015 Write leveling : PASS
7078 09:28:27.032103 RX DQS gating : PASS
7079 09:28:27.035426 RX DQ/DQS(RDDQC) : PASS
7080 09:28:27.038641 TX DQ/DQS : PASS
7081 09:28:27.038774 RX DATLAT : PASS
7082 09:28:27.041897 RX DQ/DQS(Engine): PASS
7083 09:28:27.042001 TX OE : NO K
7084 09:28:27.045125 All Pass.
7085 09:28:27.045243
7086 09:28:27.045347 CH 0, Rank 1
7087 09:28:27.048636 SW Impedance : PASS
7088 09:28:27.048750 DUTY Scan : NO K
7089 09:28:27.051938 ZQ Calibration : PASS
7090 09:28:27.055431 Jitter Meter : NO K
7091 09:28:27.055548 CBT Training : PASS
7092 09:28:27.058596 Write leveling : NO K
7093 09:28:27.062296 RX DQS gating : PASS
7094 09:28:27.062412 RX DQ/DQS(RDDQC) : PASS
7095 09:28:27.065142 TX DQ/DQS : PASS
7096 09:28:27.068672 RX DATLAT : PASS
7097 09:28:27.068804 RX DQ/DQS(Engine): PASS
7098 09:28:27.071900 TX OE : NO K
7099 09:28:27.072030 All Pass.
7100 09:28:27.072135
7101 09:28:27.075159 CH 1, Rank 0
7102 09:28:27.075273 SW Impedance : PASS
7103 09:28:27.078835 DUTY Scan : NO K
7104 09:28:27.081703 ZQ Calibration : PASS
7105 09:28:27.081818 Jitter Meter : NO K
7106 09:28:27.085792 CBT Training : PASS
7107 09:28:27.088587 Write leveling : PASS
7108 09:28:27.088703 RX DQS gating : PASS
7109 09:28:27.091898 RX DQ/DQS(RDDQC) : PASS
7110 09:28:27.092012 TX DQ/DQS : PASS
7111 09:28:27.095015 RX DATLAT : PASS
7112 09:28:27.098802 RX DQ/DQS(Engine): PASS
7113 09:28:27.098937 TX OE : NO K
7114 09:28:27.101951 All Pass.
7115 09:28:27.102071
7116 09:28:27.102172 CH 1, Rank 1
7117 09:28:27.105270 SW Impedance : PASS
7118 09:28:27.105386 DUTY Scan : NO K
7119 09:28:27.108424 ZQ Calibration : PASS
7120 09:28:27.112146 Jitter Meter : NO K
7121 09:28:27.112260 CBT Training : PASS
7122 09:28:27.115118 Write leveling : NO K
7123 09:28:27.118663 RX DQS gating : PASS
7124 09:28:27.118813 RX DQ/DQS(RDDQC) : PASS
7125 09:28:27.122359 TX DQ/DQS : PASS
7126 09:28:27.125168 RX DATLAT : PASS
7127 09:28:27.125282 RX DQ/DQS(Engine): PASS
7128 09:28:27.128650 TX OE : NO K
7129 09:28:27.128765 All Pass.
7130 09:28:27.128865
7131 09:28:27.131817 DramC Write-DBI off
7132 09:28:27.135330 PER_BANK_REFRESH: Hybrid Mode
7133 09:28:27.135449 TX_TRACKING: ON
7134 09:28:27.145769 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7135 09:28:27.148694 [FAST_K] Save calibration result to emmc
7136 09:28:27.151863 dramc_set_vcore_voltage set vcore to 725000
7137 09:28:27.156166 Read voltage for 1600, 0
7138 09:28:27.156287 Vio18 = 0
7139 09:28:27.156391 Vcore = 725000
7140 09:28:27.156491 Vdram = 0
7141 09:28:27.158326 Vddq = 0
7142 09:28:27.158437 Vmddr = 0
7143 09:28:27.165398 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7144 09:28:27.168732 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7145 09:28:27.171916 MEM_TYPE=3, freq_sel=13
7146 09:28:27.175583 sv_algorithm_assistance_LP4_3733
7147 09:28:27.178433 ============ PULL DRAM RESETB DOWN ============
7148 09:28:27.182103 ========== PULL DRAM RESETB DOWN end =========
7149 09:28:27.188695 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7150 09:28:27.192047 ===================================
7151 09:28:27.192172 LPDDR4 DRAM CONFIGURATION
7152 09:28:27.195215 ===================================
7153 09:28:27.198876 EX_ROW_EN[0] = 0x0
7154 09:28:27.199023 EX_ROW_EN[1] = 0x0
7155 09:28:27.201993 LP4Y_EN = 0x0
7156 09:28:27.205233 WORK_FSP = 0x1
7157 09:28:27.205351 WL = 0x5
7158 09:28:27.208961 RL = 0x5
7159 09:28:27.209076 BL = 0x2
7160 09:28:27.212045 RPST = 0x0
7161 09:28:27.212159 RD_PRE = 0x0
7162 09:28:27.215196 WR_PRE = 0x1
7163 09:28:27.215309 WR_PST = 0x1
7164 09:28:27.218914 DBI_WR = 0x0
7165 09:28:27.219040 DBI_RD = 0x0
7166 09:28:27.222268 OTF = 0x1
7167 09:28:27.225423 ===================================
7168 09:28:27.228683 ===================================
7169 09:28:27.228797 ANA top config
7170 09:28:27.232011 ===================================
7171 09:28:27.235391 DLL_ASYNC_EN = 0
7172 09:28:27.238428 ALL_SLAVE_EN = 0
7173 09:28:27.238540 NEW_RANK_MODE = 1
7174 09:28:27.241996 DLL_IDLE_MODE = 1
7175 09:28:27.245646 LP45_APHY_COMB_EN = 1
7176 09:28:27.248619 TX_ODT_DIS = 0
7177 09:28:27.248747 NEW_8X_MODE = 1
7178 09:28:27.252177 ===================================
7179 09:28:27.255324 ===================================
7180 09:28:27.258858 data_rate = 3200
7181 09:28:27.262139 CKR = 1
7182 09:28:27.265625 DQ_P2S_RATIO = 8
7183 09:28:27.268448 ===================================
7184 09:28:27.272107 CA_P2S_RATIO = 8
7185 09:28:27.275345 DQ_CA_OPEN = 0
7186 09:28:27.275464 DQ_SEMI_OPEN = 0
7187 09:28:27.278500 CA_SEMI_OPEN = 0
7188 09:28:27.281947 CA_FULL_RATE = 0
7189 09:28:27.285377 DQ_CKDIV4_EN = 0
7190 09:28:27.288691 CA_CKDIV4_EN = 0
7191 09:28:27.292001 CA_PREDIV_EN = 0
7192 09:28:27.292123 PH8_DLY = 12
7193 09:28:27.295160 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7194 09:28:27.298566 DQ_AAMCK_DIV = 4
7195 09:28:27.301951 CA_AAMCK_DIV = 4
7196 09:28:27.305323 CA_ADMCK_DIV = 4
7197 09:28:27.308914 DQ_TRACK_CA_EN = 0
7198 09:28:27.309022 CA_PICK = 1600
7199 09:28:27.311907 CA_MCKIO = 1600
7200 09:28:27.315602 MCKIO_SEMI = 0
7201 09:28:27.318677 PLL_FREQ = 3068
7202 09:28:27.322384 DQ_UI_PI_RATIO = 32
7203 09:28:27.325792 CA_UI_PI_RATIO = 0
7204 09:28:27.328689 ===================================
7205 09:28:27.331890 ===================================
7206 09:28:27.331980 memory_type:LPDDR4
7207 09:28:27.335327 GP_NUM : 10
7208 09:28:27.339271 SRAM_EN : 1
7209 09:28:27.339361 MD32_EN : 0
7210 09:28:27.342311 ===================================
7211 09:28:27.345633 [ANA_INIT] >>>>>>>>>>>>>>
7212 09:28:27.348647 <<<<<< [CONFIGURE PHASE]: ANA_TX
7213 09:28:27.351833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7214 09:28:27.355387 ===================================
7215 09:28:27.358700 data_rate = 3200,PCW = 0X7600
7216 09:28:27.362315 ===================================
7217 09:28:27.365721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7218 09:28:27.369026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7219 09:28:27.375571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7220 09:28:27.379012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7221 09:28:27.382043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7222 09:28:27.385692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7223 09:28:27.388774 [ANA_INIT] flow start
7224 09:28:27.392209 [ANA_INIT] PLL >>>>>>>>
7225 09:28:27.392302 [ANA_INIT] PLL <<<<<<<<
7226 09:28:27.395366 [ANA_INIT] MIDPI >>>>>>>>
7227 09:28:27.398862 [ANA_INIT] MIDPI <<<<<<<<
7228 09:28:27.402485 [ANA_INIT] DLL >>>>>>>>
7229 09:28:27.402587 [ANA_INIT] DLL <<<<<<<<
7230 09:28:27.405481 [ANA_INIT] flow end
7231 09:28:27.409131 ============ LP4 DIFF to SE enter ============
7232 09:28:27.412173 ============ LP4 DIFF to SE exit ============
7233 09:28:27.415597 [ANA_INIT] <<<<<<<<<<<<<
7234 09:28:27.419065 [Flow] Enable top DCM control >>>>>
7235 09:28:27.421846 [Flow] Enable top DCM control <<<<<
7236 09:28:27.425332 Enable DLL master slave shuffle
7237 09:28:27.429108 ==============================================================
7238 09:28:27.432628 Gating Mode config
7239 09:28:27.439104 ==============================================================
7240 09:28:27.439232 Config description:
7241 09:28:27.448686 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7242 09:28:27.455934 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7243 09:28:27.459003 SELPH_MODE 0: By rank 1: By Phase
7244 09:28:27.465816 ==============================================================
7245 09:28:27.469091 GAT_TRACK_EN = 1
7246 09:28:27.472330 RX_GATING_MODE = 2
7247 09:28:27.476088 RX_GATING_TRACK_MODE = 2
7248 09:28:27.479499 SELPH_MODE = 1
7249 09:28:27.482624 PICG_EARLY_EN = 1
7250 09:28:27.485661 VALID_LAT_VALUE = 1
7251 09:28:27.489534 ==============================================================
7252 09:28:27.492672 Enter into Gating configuration >>>>
7253 09:28:27.495831 Exit from Gating configuration <<<<
7254 09:28:27.499194 Enter into DVFS_PRE_config >>>>>
7255 09:28:27.509267 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7256 09:28:27.512526 Exit from DVFS_PRE_config <<<<<
7257 09:28:27.516122 Enter into PICG configuration >>>>
7258 09:28:27.519139 Exit from PICG configuration <<<<
7259 09:28:27.522889 [RX_INPUT] configuration >>>>>
7260 09:28:27.526225 [RX_INPUT] configuration <<<<<
7261 09:28:27.529392 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7262 09:28:27.536333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7263 09:28:27.542682 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7264 09:28:27.549642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7265 09:28:27.556752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7266 09:28:27.559500 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7267 09:28:27.566392 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7268 09:28:27.569478 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7269 09:28:27.572972 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7270 09:28:27.576161 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7271 09:28:27.579635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7272 09:28:27.586410 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 09:28:27.589189 ===================================
7274 09:28:27.592938 LPDDR4 DRAM CONFIGURATION
7275 09:28:27.596193 ===================================
7276 09:28:27.596314 EX_ROW_EN[0] = 0x0
7277 09:28:27.599820 EX_ROW_EN[1] = 0x0
7278 09:28:27.599937 LP4Y_EN = 0x0
7279 09:28:27.602622 WORK_FSP = 0x1
7280 09:28:27.602764 WL = 0x5
7281 09:28:27.606285 RL = 0x5
7282 09:28:27.606432 BL = 0x2
7283 09:28:27.609520 RPST = 0x0
7284 09:28:27.609634 RD_PRE = 0x0
7285 09:28:27.612669 WR_PRE = 0x1
7286 09:28:27.612752 WR_PST = 0x1
7287 09:28:27.616451 DBI_WR = 0x0
7288 09:28:27.616533 DBI_RD = 0x0
7289 09:28:27.619506 OTF = 0x1
7290 09:28:27.622687 ===================================
7291 09:28:27.626118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7292 09:28:27.629324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7293 09:28:27.636068 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7294 09:28:27.639381 ===================================
7295 09:28:27.639466 LPDDR4 DRAM CONFIGURATION
7296 09:28:27.642649 ===================================
7297 09:28:27.646315 EX_ROW_EN[0] = 0x10
7298 09:28:27.649276 EX_ROW_EN[1] = 0x0
7299 09:28:27.649371 LP4Y_EN = 0x0
7300 09:28:27.653037 WORK_FSP = 0x1
7301 09:28:27.653120 WL = 0x5
7302 09:28:27.656122 RL = 0x5
7303 09:28:27.656204 BL = 0x2
7304 09:28:27.659104 RPST = 0x0
7305 09:28:27.659185 RD_PRE = 0x0
7306 09:28:27.662454 WR_PRE = 0x1
7307 09:28:27.662535 WR_PST = 0x1
7308 09:28:27.666033 DBI_WR = 0x0
7309 09:28:27.666115 DBI_RD = 0x0
7310 09:28:27.669247 OTF = 0x1
7311 09:28:27.672676 ===================================
7312 09:28:27.679743 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7313 09:28:27.679825 ==
7314 09:28:27.683108 Dram Type= 6, Freq= 0, CH_0, rank 0
7315 09:28:27.685888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7316 09:28:27.685989 ==
7317 09:28:27.689928 [Duty_Offset_Calibration]
7318 09:28:27.690010 B0:2 B1:-1 CA:1
7319 09:28:27.690073
7320 09:28:27.693049 [DutyScan_Calibration_Flow] k_type=0
7321 09:28:27.702313
7322 09:28:27.702439 ==CLK 0==
7323 09:28:27.705586 Final CLK duty delay cell = -4
7324 09:28:27.709220 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7325 09:28:27.712876 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7326 09:28:27.715626 [-4] AVG Duty = 4937%(X100)
7327 09:28:27.715708
7328 09:28:27.719022 CH0 CLK Duty spec in!! Max-Min= 187%
7329 09:28:27.722450 [DutyScan_Calibration_Flow] ====Done====
7330 09:28:27.722541
7331 09:28:27.725994 [DutyScan_Calibration_Flow] k_type=1
7332 09:28:27.742013
7333 09:28:27.742121 ==DQS 0 ==
7334 09:28:27.745176 Final DQS duty delay cell = 0
7335 09:28:27.748483 [0] MAX Duty = 5125%(X100), DQS PI = 56
7336 09:28:27.751701 [0] MIN Duty = 5000%(X100), DQS PI = 16
7337 09:28:27.755349 [0] AVG Duty = 5062%(X100)
7338 09:28:27.755436
7339 09:28:27.755537 ==DQS 1 ==
7340 09:28:27.758630 Final DQS duty delay cell = -4
7341 09:28:27.761649 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7342 09:28:27.765302 [-4] MIN Duty = 5031%(X100), DQS PI = 18
7343 09:28:27.768512 [-4] AVG Duty = 5062%(X100)
7344 09:28:27.768612
7345 09:28:27.771962 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7346 09:28:27.772044
7347 09:28:27.775290 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7348 09:28:27.778869 [DutyScan_Calibration_Flow] ====Done====
7349 09:28:27.778951
7350 09:28:27.781835 [DutyScan_Calibration_Flow] k_type=3
7351 09:28:27.799316
7352 09:28:27.799443 ==DQM 0 ==
7353 09:28:27.802573 Final DQM duty delay cell = 0
7354 09:28:27.805832 [0] MAX Duty = 5000%(X100), DQS PI = 18
7355 09:28:27.809200 [0] MIN Duty = 4875%(X100), DQS PI = 4
7356 09:28:27.809308 [0] AVG Duty = 4937%(X100)
7357 09:28:27.812461
7358 09:28:27.812571 ==DQM 1 ==
7359 09:28:27.816011 Final DQM duty delay cell = 0
7360 09:28:27.819227 [0] MAX Duty = 5218%(X100), DQS PI = 58
7361 09:28:27.822474 [0] MIN Duty = 4969%(X100), DQS PI = 18
7362 09:28:27.822561 [0] AVG Duty = 5093%(X100)
7363 09:28:27.825831
7364 09:28:27.829654 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7365 09:28:27.829741
7366 09:28:27.833152 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7367 09:28:27.835925 [DutyScan_Calibration_Flow] ====Done====
7368 09:28:27.836031
7369 09:28:27.839570 [DutyScan_Calibration_Flow] k_type=2
7370 09:28:27.855449
7371 09:28:27.855661 ==DQ 0 ==
7372 09:28:27.858690 Final DQ duty delay cell = -4
7373 09:28:27.862478 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7374 09:28:27.865869 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7375 09:28:27.869093 [-4] AVG Duty = 4937%(X100)
7376 09:28:27.869239
7377 09:28:27.869361 ==DQ 1 ==
7378 09:28:27.872204 Final DQ duty delay cell = 0
7379 09:28:27.875698 [0] MAX Duty = 5031%(X100), DQS PI = 38
7380 09:28:27.878843 [0] MIN Duty = 4907%(X100), DQS PI = 18
7381 09:28:27.878931 [0] AVG Duty = 4969%(X100)
7382 09:28:27.882510
7383 09:28:27.882595 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7384 09:28:27.885578
7385 09:28:27.889349 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7386 09:28:27.892619 [DutyScan_Calibration_Flow] ====Done====
7387 09:28:27.892759 ==
7388 09:28:27.895622 Dram Type= 6, Freq= 0, CH_1, rank 0
7389 09:28:27.899277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7390 09:28:27.899385 ==
7391 09:28:27.902488 [Duty_Offset_Calibration]
7392 09:28:27.902601 B0:1 B1:1 CA:2
7393 09:28:27.902695
7394 09:28:27.905444 [DutyScan_Calibration_Flow] k_type=0
7395 09:28:27.915996
7396 09:28:27.916114 ==CLK 0==
7397 09:28:27.919219 Final CLK duty delay cell = 0
7398 09:28:27.922697 [0] MAX Duty = 5187%(X100), DQS PI = 24
7399 09:28:27.926152 [0] MIN Duty = 4938%(X100), DQS PI = 56
7400 09:28:27.926277 [0] AVG Duty = 5062%(X100)
7401 09:28:27.929601
7402 09:28:27.932631 CH1 CLK Duty spec in!! Max-Min= 249%
7403 09:28:27.936275 [DutyScan_Calibration_Flow] ====Done====
7404 09:28:27.936382
7405 09:28:27.939389 [DutyScan_Calibration_Flow] k_type=1
7406 09:28:27.956035
7407 09:28:27.956162 ==DQS 0 ==
7408 09:28:27.958740 Final DQS duty delay cell = 0
7409 09:28:27.962216 [0] MAX Duty = 5062%(X100), DQS PI = 20
7410 09:28:27.965838 [0] MIN Duty = 4813%(X100), DQS PI = 50
7411 09:28:27.965946 [0] AVG Duty = 4937%(X100)
7412 09:28:27.969719
7413 09:28:27.969823 ==DQS 1 ==
7414 09:28:27.972306 Final DQS duty delay cell = 0
7415 09:28:27.975730 [0] MAX Duty = 5062%(X100), DQS PI = 58
7416 09:28:27.978950 [0] MIN Duty = 4938%(X100), DQS PI = 12
7417 09:28:27.979057 [0] AVG Duty = 5000%(X100)
7418 09:28:27.982563
7419 09:28:27.986001 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7420 09:28:27.986106
7421 09:28:27.989476 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7422 09:28:27.992506 [DutyScan_Calibration_Flow] ====Done====
7423 09:28:27.992610
7424 09:28:27.995729 [DutyScan_Calibration_Flow] k_type=3
7425 09:28:28.012854
7426 09:28:28.012980 ==DQM 0 ==
7427 09:28:28.015815 Final DQM duty delay cell = 0
7428 09:28:28.019264 [0] MAX Duty = 5156%(X100), DQS PI = 20
7429 09:28:28.022650 [0] MIN Duty = 4844%(X100), DQS PI = 52
7430 09:28:28.022767 [0] AVG Duty = 5000%(X100)
7431 09:28:28.025728
7432 09:28:28.025859 ==DQM 1 ==
7433 09:28:28.029254 Final DQM duty delay cell = 0
7434 09:28:28.032775 [0] MAX Duty = 5125%(X100), DQS PI = 8
7435 09:28:28.035910 [0] MIN Duty = 4907%(X100), DQS PI = 20
7436 09:28:28.036023 [0] AVG Duty = 5016%(X100)
7437 09:28:28.039304
7438 09:28:28.042651 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7439 09:28:28.042774
7440 09:28:28.045809 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7441 09:28:28.049258 [DutyScan_Calibration_Flow] ====Done====
7442 09:28:28.049391
7443 09:28:28.052795 [DutyScan_Calibration_Flow] k_type=2
7444 09:28:28.069552
7445 09:28:28.069643 ==DQ 0 ==
7446 09:28:28.073184 Final DQ duty delay cell = 0
7447 09:28:28.076411 [0] MAX Duty = 5156%(X100), DQS PI = 20
7448 09:28:28.079430 [0] MIN Duty = 4907%(X100), DQS PI = 52
7449 09:28:28.079511 [0] AVG Duty = 5031%(X100)
7450 09:28:28.082546
7451 09:28:28.082653 ==DQ 1 ==
7452 09:28:28.086124 Final DQ duty delay cell = 0
7453 09:28:28.089690 [0] MAX Duty = 5093%(X100), DQS PI = 6
7454 09:28:28.092595 [0] MIN Duty = 5031%(X100), DQS PI = 0
7455 09:28:28.092684 [0] AVG Duty = 5062%(X100)
7456 09:28:28.092749
7457 09:28:28.096079 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7458 09:28:28.096161
7459 09:28:28.099403 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7460 09:28:28.106079 [DutyScan_Calibration_Flow] ====Done====
7461 09:28:28.109677 nWR fixed to 30
7462 09:28:28.109784 [ModeRegInit_LP4] CH0 RK0
7463 09:28:28.112583 [ModeRegInit_LP4] CH0 RK1
7464 09:28:28.116185 [ModeRegInit_LP4] CH1 RK0
7465 09:28:28.116289 [ModeRegInit_LP4] CH1 RK1
7466 09:28:28.119142 match AC timing 5
7467 09:28:28.122416 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7468 09:28:28.125788 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7469 09:28:28.132583 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7470 09:28:28.135650 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7471 09:28:28.142296 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7472 09:28:28.142382 [MiockJmeterHQA]
7473 09:28:28.142453
7474 09:28:28.145729 [DramcMiockJmeter] u1RxGatingPI = 0
7475 09:28:28.149186 0 : 4258, 4030
7476 09:28:28.149290 4 : 4253, 4027
7477 09:28:28.149389 8 : 4255, 4029
7478 09:28:28.152137 12 : 4255, 4029
7479 09:28:28.152227 16 : 4366, 4140
7480 09:28:28.155888 20 : 4258, 4030
7481 09:28:28.155966 24 : 4252, 4027
7482 09:28:28.158998 28 : 4252, 4027
7483 09:28:28.159103 32 : 4258, 4032
7484 09:28:28.159207 36 : 4254, 4029
7485 09:28:28.162185 40 : 4252, 4027
7486 09:28:28.162288 44 : 4368, 4142
7487 09:28:28.165976 48 : 4254, 4029
7488 09:28:28.166088 52 : 4253, 4027
7489 09:28:28.169172 56 : 4365, 4140
7490 09:28:28.169280 60 : 4250, 4027
7491 09:28:28.172230 64 : 4250, 4027
7492 09:28:28.172328 68 : 4360, 4137
7493 09:28:28.172401 72 : 4363, 4140
7494 09:28:28.175763 76 : 4250, 4027
7495 09:28:28.175857 80 : 4363, 4140
7496 09:28:28.179264 84 : 4253, 4029
7497 09:28:28.179368 88 : 4252, 4030
7498 09:28:28.182554 92 : 4253, 4029
7499 09:28:28.182676 96 : 4257, 3402
7500 09:28:28.182785 100 : 4365, 0
7501 09:28:28.185571 104 : 4250, 0
7502 09:28:28.185675 108 : 4363, 0
7503 09:28:28.189093 112 : 4254, 0
7504 09:28:28.189168 116 : 4252, 0
7505 09:28:28.189232 120 : 4250, 0
7506 09:28:28.192652 124 : 4255, 0
7507 09:28:28.192763 128 : 4361, 0
7508 09:28:28.195767 132 : 4249, 0
7509 09:28:28.195870 136 : 4255, 0
7510 09:28:28.195962 140 : 4366, 0
7511 09:28:28.199207 144 : 4363, 0
7512 09:28:28.199320 148 : 4250, 0
7513 09:28:28.202383 152 : 4255, 0
7514 09:28:28.202498 156 : 4363, 0
7515 09:28:28.202594 160 : 4250, 0
7516 09:28:28.205914 164 : 4250, 0
7517 09:28:28.206005 168 : 4250, 0
7518 09:28:28.206073 172 : 4257, 0
7519 09:28:28.208860 176 : 4252, 0
7520 09:28:28.208976 180 : 4252, 0
7521 09:28:28.212632 184 : 4255, 0
7522 09:28:28.212747 188 : 4253, 0
7523 09:28:28.212843 192 : 4366, 0
7524 09:28:28.215627 196 : 4360, 0
7525 09:28:28.215711 200 : 4253, 0
7526 09:28:28.219324 204 : 4361, 0
7527 09:28:28.219408 208 : 4252, 0
7528 09:28:28.219475 212 : 4250, 161
7529 09:28:28.222373 216 : 4250, 3828
7530 09:28:28.222450 220 : 4254, 4029
7531 09:28:28.226099 224 : 4253, 4029
7532 09:28:28.226176 228 : 4255, 4032
7533 09:28:28.229431 232 : 4361, 4138
7534 09:28:28.229514 236 : 4363, 4137
7535 09:28:28.232405 240 : 4361, 4137
7536 09:28:28.232482 244 : 4250, 4027
7537 09:28:28.235954 248 : 4250, 4027
7538 09:28:28.236030 252 : 4250, 4026
7539 09:28:28.236093 256 : 4252, 4029
7540 09:28:28.239080 260 : 4250, 4027
7541 09:28:28.239158 264 : 4253, 4029
7542 09:28:28.242590 268 : 4363, 4140
7543 09:28:28.242664 272 : 4252, 4029
7544 09:28:28.245854 276 : 4365, 4139
7545 09:28:28.245930 280 : 4252, 4029
7546 09:28:28.249148 284 : 4363, 4137
7547 09:28:28.249251 288 : 4363, 4137
7548 09:28:28.252394 292 : 4253, 4029
7549 09:28:28.252505 296 : 4253, 4029
7550 09:28:28.255993 300 : 4363, 4139
7551 09:28:28.256075 304 : 4250, 4026
7552 09:28:28.259282 308 : 4252, 4029
7553 09:28:28.259362 312 : 4250, 4027
7554 09:28:28.259429 316 : 4255, 4032
7555 09:28:28.262944 320 : 4252, 4029
7556 09:28:28.263016 324 : 4365, 4139
7557 09:28:28.266045 328 : 4365, 4140
7558 09:28:28.266129 332 : 4255, 2841
7559 09:28:28.269440 336 : 4250, 62
7560 09:28:28.269524
7561 09:28:28.269590 MIOCK jitter meter ch=0
7562 09:28:28.269651
7563 09:28:28.272420 1T = (336-100) = 236 dly cells
7564 09:28:28.279444 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7565 09:28:28.279529 ==
7566 09:28:28.282649 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 09:28:28.285907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 09:28:28.285990 ==
7569 09:28:28.292745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7570 09:28:28.295940 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7571 09:28:28.299072 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7572 09:28:28.306299 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7573 09:28:28.316397 [CA 0] Center 44 (14~75) winsize 62
7574 09:28:28.319597 [CA 1] Center 44 (13~75) winsize 63
7575 09:28:28.322363 [CA 2] Center 40 (11~69) winsize 59
7576 09:28:28.325712 [CA 3] Center 39 (10~69) winsize 60
7577 09:28:28.329458 [CA 4] Center 38 (8~68) winsize 61
7578 09:28:28.332556 [CA 5] Center 37 (7~67) winsize 61
7579 09:28:28.332638
7580 09:28:28.336120 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7581 09:28:28.336201
7582 09:28:28.339572 [CATrainingPosCal] consider 1 rank data
7583 09:28:28.342665 u2DelayCellTimex100 = 275/100 ps
7584 09:28:28.346069 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7585 09:28:28.352814 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7586 09:28:28.356418 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7587 09:28:28.359097 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7588 09:28:28.362518 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7589 09:28:28.366223 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7590 09:28:28.366312
7591 09:28:28.369447 CA PerBit enable=1, Macro0, CA PI delay=37
7592 09:28:28.369556
7593 09:28:28.372974 [CBTSetCACLKResult] CA Dly = 37
7594 09:28:28.376074 CS Dly: 10 (0~41)
7595 09:28:28.379286 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7596 09:28:28.382706 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7597 09:28:28.382803 ==
7598 09:28:28.386172 Dram Type= 6, Freq= 0, CH_0, rank 1
7599 09:28:28.389535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 09:28:28.389644 ==
7601 09:28:28.396312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7602 09:28:28.399449 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7603 09:28:28.406097 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7604 09:28:28.409153 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7605 09:28:28.419625 [CA 0] Center 43 (13~74) winsize 62
7606 09:28:28.423029 [CA 1] Center 43 (13~74) winsize 62
7607 09:28:28.426448 [CA 2] Center 39 (10~69) winsize 60
7608 09:28:28.429559 [CA 3] Center 38 (9~68) winsize 60
7609 09:28:28.433113 [CA 4] Center 37 (7~67) winsize 61
7610 09:28:28.436349 [CA 5] Center 37 (7~67) winsize 61
7611 09:28:28.436459
7612 09:28:28.439900 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7613 09:28:28.440010
7614 09:28:28.443436 [CATrainingPosCal] consider 2 rank data
7615 09:28:28.446737 u2DelayCellTimex100 = 275/100 ps
7616 09:28:28.449742 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7617 09:28:28.456655 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7618 09:28:28.460357 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7619 09:28:28.463027 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7620 09:28:28.466341 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7621 09:28:28.470239 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7622 09:28:28.470323
7623 09:28:28.473159 CA PerBit enable=1, Macro0, CA PI delay=37
7624 09:28:28.473242
7625 09:28:28.476734 [CBTSetCACLKResult] CA Dly = 37
7626 09:28:28.479811 CS Dly: 11 (0~44)
7627 09:28:28.484003 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7628 09:28:28.486411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7629 09:28:28.486524
7630 09:28:28.489619 ----->DramcWriteLeveling(PI) begin...
7631 09:28:28.489704 ==
7632 09:28:28.493496 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 09:28:28.496392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 09:28:28.499740 ==
7635 09:28:28.499852 Write leveling (Byte 0): 34 => 34
7636 09:28:28.503409 Write leveling (Byte 1): 26 => 26
7637 09:28:28.506247 DramcWriteLeveling(PI) end<-----
7638 09:28:28.506353
7639 09:28:28.506447 ==
7640 09:28:28.509726 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 09:28:28.516475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 09:28:28.516582 ==
7643 09:28:28.516676 [Gating] SW mode calibration
7644 09:28:28.526658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7645 09:28:28.530238 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7646 09:28:28.533372 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 09:28:28.539915 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 09:28:28.543272 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 09:28:28.546665 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 09:28:28.553607 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7651 09:28:28.557040 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7652 09:28:28.560358 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
7653 09:28:28.566700 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 09:28:28.570057 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 09:28:28.573515 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 09:28:28.579982 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 09:28:28.583280 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 09:28:28.586512 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7659 09:28:28.593409 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7660 09:28:28.596426 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7661 09:28:28.600085 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 09:28:28.607131 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 09:28:28.610011 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 09:28:28.613527 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 09:28:28.620675 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 09:28:28.623196 1 6 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7667 09:28:28.627047 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7668 09:28:28.630367 1 6 24 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
7669 09:28:28.636895 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 09:28:28.641872 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 09:28:28.643649 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 09:28:28.649916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 09:28:28.653887 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 09:28:28.656630 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 09:28:28.663496 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7676 09:28:28.666612 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 09:28:28.670372 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7678 09:28:28.677079 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 09:28:28.680164 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 09:28:28.683398 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 09:28:28.690253 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 09:28:28.693628 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 09:28:28.696854 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 09:28:28.700308 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 09:28:28.706678 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 09:28:28.710274 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 09:28:28.713280 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 09:28:28.720528 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 09:28:28.723924 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7690 09:28:28.726748 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7691 09:28:28.733591 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 09:28:28.733696 Total UI for P1: 0, mck2ui 16
7693 09:28:28.740130 best dqsien dly found for B0: ( 1, 9, 14)
7694 09:28:28.743701 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 09:28:28.747111 Total UI for P1: 0, mck2ui 16
7696 09:28:28.750197 best dqsien dly found for B1: ( 1, 9, 20)
7697 09:28:28.753370 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7698 09:28:28.756917 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7699 09:28:28.757034
7700 09:28:28.760247 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7701 09:28:28.763986 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7702 09:28:28.767032 [Gating] SW calibration Done
7703 09:28:28.767135 ==
7704 09:28:28.770930 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 09:28:28.773851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 09:28:28.777062 ==
7707 09:28:28.777149 RX Vref Scan: 0
7708 09:28:28.777235
7709 09:28:28.780791 RX Vref 0 -> 0, step: 1
7710 09:28:28.780878
7711 09:28:28.780965 RX Delay 0 -> 252, step: 8
7712 09:28:28.787253 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7713 09:28:28.790690 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7714 09:28:28.793568 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7715 09:28:28.798111 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7716 09:28:28.800383 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7717 09:28:28.806955 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7718 09:28:28.810168 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7719 09:28:28.813410 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7720 09:28:28.817138 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7721 09:28:28.820274 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7722 09:28:28.826663 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7723 09:28:28.830200 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7724 09:28:28.833864 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7725 09:28:28.837069 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7726 09:28:28.840346 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7727 09:28:28.846824 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7728 09:28:28.846948 ==
7729 09:28:28.850596 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 09:28:28.853673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 09:28:28.853769 ==
7732 09:28:28.853836 DQS Delay:
7733 09:28:28.856856 DQS0 = 0, DQS1 = 0
7734 09:28:28.856941 DQM Delay:
7735 09:28:28.860617 DQM0 = 132, DQM1 = 123
7736 09:28:28.860701 DQ Delay:
7737 09:28:28.863884 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7738 09:28:28.867179 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7739 09:28:28.870573 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7740 09:28:28.873812 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7741 09:28:28.873902
7742 09:28:28.873968
7743 09:28:28.877093 ==
7744 09:28:28.880141 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 09:28:28.883627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 09:28:28.883714 ==
7747 09:28:28.883780
7748 09:28:28.883841
7749 09:28:28.887485 TX Vref Scan disable
7750 09:28:28.887569 == TX Byte 0 ==
7751 09:28:28.890626 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7752 09:28:28.897059 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7753 09:28:28.897166 == TX Byte 1 ==
7754 09:28:28.900255 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7755 09:28:28.907298 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7756 09:28:28.907442 ==
7757 09:28:28.910503 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 09:28:28.913755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 09:28:28.913869 ==
7760 09:28:28.929084
7761 09:28:28.932390 TX Vref early break, caculate TX vref
7762 09:28:28.935729 TX Vref=16, minBit 1, minWin=20, winSum=351
7763 09:28:28.938617 TX Vref=18, minBit 8, minWin=21, winSum=365
7764 09:28:28.942137 TX Vref=20, minBit 1, minWin=22, winSum=376
7765 09:28:28.945472 TX Vref=22, minBit 1, minWin=23, winSum=389
7766 09:28:28.948659 TX Vref=24, minBit 4, minWin=24, winSum=399
7767 09:28:28.955531 TX Vref=26, minBit 4, minWin=23, winSum=407
7768 09:28:28.958939 TX Vref=28, minBit 4, minWin=24, winSum=413
7769 09:28:28.962331 TX Vref=30, minBit 4, minWin=24, winSum=411
7770 09:28:28.965593 TX Vref=32, minBit 4, minWin=24, winSum=412
7771 09:28:28.969286 TX Vref=34, minBit 0, minWin=24, winSum=399
7772 09:28:28.972384 TX Vref=36, minBit 0, minWin=23, winSum=388
7773 09:28:28.979076 [TxChooseVref] Worse bit 4, Min win 24, Win sum 413, Final Vref 28
7774 09:28:28.979201
7775 09:28:28.982110 Final TX Range 0 Vref 28
7776 09:28:28.982227
7777 09:28:28.982324 ==
7778 09:28:28.985910 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 09:28:28.989201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 09:28:28.989316 ==
7781 09:28:28.989415
7782 09:28:28.989510
7783 09:28:28.992542 TX Vref Scan disable
7784 09:28:28.999078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7785 09:28:28.999198 == TX Byte 0 ==
7786 09:28:29.002256 u2DelayCellOfst[0]=14 cells (4 PI)
7787 09:28:29.005824 u2DelayCellOfst[1]=17 cells (5 PI)
7788 09:28:29.009107 u2DelayCellOfst[2]=10 cells (3 PI)
7789 09:28:29.012532 u2DelayCellOfst[3]=14 cells (4 PI)
7790 09:28:29.015962 u2DelayCellOfst[4]=7 cells (2 PI)
7791 09:28:29.018945 u2DelayCellOfst[5]=0 cells (0 PI)
7792 09:28:29.022870 u2DelayCellOfst[6]=17 cells (5 PI)
7793 09:28:29.025828 u2DelayCellOfst[7]=17 cells (5 PI)
7794 09:28:29.028699 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7795 09:28:29.032591 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7796 09:28:29.035804 == TX Byte 1 ==
7797 09:28:29.035918 u2DelayCellOfst[8]=0 cells (0 PI)
7798 09:28:29.039239 u2DelayCellOfst[9]=0 cells (0 PI)
7799 09:28:29.042533 u2DelayCellOfst[10]=7 cells (2 PI)
7800 09:28:29.045776 u2DelayCellOfst[11]=0 cells (0 PI)
7801 09:28:29.048799 u2DelayCellOfst[12]=10 cells (3 PI)
7802 09:28:29.052147 u2DelayCellOfst[13]=10 cells (3 PI)
7803 09:28:29.055575 u2DelayCellOfst[14]=14 cells (4 PI)
7804 09:28:29.059063 u2DelayCellOfst[15]=10 cells (3 PI)
7805 09:28:29.062462 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7806 09:28:29.068913 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7807 09:28:29.069043 DramC Write-DBI on
7808 09:28:29.069116 ==
7809 09:28:29.072214 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 09:28:29.075853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 09:28:29.075933 ==
7812 09:28:29.079253
7813 09:28:29.079329
7814 09:28:29.079392 TX Vref Scan disable
7815 09:28:29.082425 == TX Byte 0 ==
7816 09:28:29.085695 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7817 09:28:29.089218 == TX Byte 1 ==
7818 09:28:29.092346 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7819 09:28:29.092426 DramC Write-DBI off
7820 09:28:29.095808
7821 09:28:29.095893 [DATLAT]
7822 09:28:29.095962 Freq=1600, CH0 RK0
7823 09:28:29.096025
7824 09:28:29.098840 DATLAT Default: 0xf
7825 09:28:29.098941 0, 0xFFFF, sum = 0
7826 09:28:29.102529 1, 0xFFFF, sum = 0
7827 09:28:29.102643 2, 0xFFFF, sum = 0
7828 09:28:29.105885 3, 0xFFFF, sum = 0
7829 09:28:29.109029 4, 0xFFFF, sum = 0
7830 09:28:29.109148 5, 0xFFFF, sum = 0
7831 09:28:29.112430 6, 0xFFFF, sum = 0
7832 09:28:29.112547 7, 0xFFFF, sum = 0
7833 09:28:29.115774 8, 0xFFFF, sum = 0
7834 09:28:29.115892 9, 0xFFFF, sum = 0
7835 09:28:29.119065 10, 0xFFFF, sum = 0
7836 09:28:29.119180 11, 0xFFFF, sum = 0
7837 09:28:29.122568 12, 0xFFFF, sum = 0
7838 09:28:29.122679 13, 0xFFFF, sum = 0
7839 09:28:29.125790 14, 0x0, sum = 1
7840 09:28:29.125896 15, 0x0, sum = 2
7841 09:28:29.129032 16, 0x0, sum = 3
7842 09:28:29.129140 17, 0x0, sum = 4
7843 09:28:29.129245 best_step = 15
7844 09:28:29.132517
7845 09:28:29.132624 ==
7846 09:28:29.135622 Dram Type= 6, Freq= 0, CH_0, rank 0
7847 09:28:29.139521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7848 09:28:29.139604 ==
7849 09:28:29.139670 RX Vref Scan: 1
7850 09:28:29.139731
7851 09:28:29.142401 Set Vref Range= 24 -> 127
7852 09:28:29.142500
7853 09:28:29.146760 RX Vref 24 -> 127, step: 1
7854 09:28:29.146871
7855 09:28:29.149594 RX Delay 11 -> 252, step: 4
7856 09:28:29.149703
7857 09:28:29.152808 Set Vref, RX VrefLevel [Byte0]: 24
7858 09:28:29.156129 [Byte1]: 24
7859 09:28:29.156214
7860 09:28:29.159442 Set Vref, RX VrefLevel [Byte0]: 25
7861 09:28:29.163070 [Byte1]: 25
7862 09:28:29.163177
7863 09:28:29.166097 Set Vref, RX VrefLevel [Byte0]: 26
7864 09:28:29.169339 [Byte1]: 26
7865 09:28:29.172871
7866 09:28:29.172955 Set Vref, RX VrefLevel [Byte0]: 27
7867 09:28:29.175850 [Byte1]: 27
7868 09:28:29.180311
7869 09:28:29.180397 Set Vref, RX VrefLevel [Byte0]: 28
7870 09:28:29.183741 [Byte1]: 28
7871 09:28:29.187874
7872 09:28:29.187990 Set Vref, RX VrefLevel [Byte0]: 29
7873 09:28:29.191156 [Byte1]: 29
7874 09:28:29.195509
7875 09:28:29.195594 Set Vref, RX VrefLevel [Byte0]: 30
7876 09:28:29.198818 [Byte1]: 30
7877 09:28:29.203034
7878 09:28:29.203145 Set Vref, RX VrefLevel [Byte0]: 31
7879 09:28:29.206684 [Byte1]: 31
7880 09:28:29.210487
7881 09:28:29.210602 Set Vref, RX VrefLevel [Byte0]: 32
7882 09:28:29.213904 [Byte1]: 32
7883 09:28:29.218117
7884 09:28:29.218234 Set Vref, RX VrefLevel [Byte0]: 33
7885 09:28:29.221621 [Byte1]: 33
7886 09:28:29.225730
7887 09:28:29.225843 Set Vref, RX VrefLevel [Byte0]: 34
7888 09:28:29.229253 [Byte1]: 34
7889 09:28:29.233501
7890 09:28:29.233609 Set Vref, RX VrefLevel [Byte0]: 35
7891 09:28:29.237048 [Byte1]: 35
7892 09:28:29.241062
7893 09:28:29.241170 Set Vref, RX VrefLevel [Byte0]: 36
7894 09:28:29.244377 [Byte1]: 36
7895 09:28:29.249018
7896 09:28:29.249104 Set Vref, RX VrefLevel [Byte0]: 37
7897 09:28:29.252181 [Byte1]: 37
7898 09:28:29.257004
7899 09:28:29.257093 Set Vref, RX VrefLevel [Byte0]: 38
7900 09:28:29.259745 [Byte1]: 38
7901 09:28:29.264163
7902 09:28:29.264252 Set Vref, RX VrefLevel [Byte0]: 39
7903 09:28:29.267444 [Byte1]: 39
7904 09:28:29.271789
7905 09:28:29.271881 Set Vref, RX VrefLevel [Byte0]: 40
7906 09:28:29.274739 [Byte1]: 40
7907 09:28:29.279243
7908 09:28:29.279327 Set Vref, RX VrefLevel [Byte0]: 41
7909 09:28:29.282605 [Byte1]: 41
7910 09:28:29.286600
7911 09:28:29.286713 Set Vref, RX VrefLevel [Byte0]: 42
7912 09:28:29.290067 [Byte1]: 42
7913 09:28:29.294465
7914 09:28:29.294580 Set Vref, RX VrefLevel [Byte0]: 43
7915 09:28:29.297799 [Byte1]: 43
7916 09:28:29.302188
7917 09:28:29.302300 Set Vref, RX VrefLevel [Byte0]: 44
7918 09:28:29.305483 [Byte1]: 44
7919 09:28:29.309946
7920 09:28:29.310062 Set Vref, RX VrefLevel [Byte0]: 45
7921 09:28:29.312905 [Byte1]: 45
7922 09:28:29.317463
7923 09:28:29.317574 Set Vref, RX VrefLevel [Byte0]: 46
7924 09:28:29.320924 [Byte1]: 46
7925 09:28:29.324856
7926 09:28:29.324965 Set Vref, RX VrefLevel [Byte0]: 47
7927 09:28:29.328668 [Byte1]: 47
7928 09:28:29.332724
7929 09:28:29.332835 Set Vref, RX VrefLevel [Byte0]: 48
7930 09:28:29.335917 [Byte1]: 48
7931 09:28:29.340205
7932 09:28:29.340314 Set Vref, RX VrefLevel [Byte0]: 49
7933 09:28:29.343886 [Byte1]: 49
7934 09:28:29.347665
7935 09:28:29.347775 Set Vref, RX VrefLevel [Byte0]: 50
7936 09:28:29.351121 [Byte1]: 50
7937 09:28:29.355561
7938 09:28:29.355673 Set Vref, RX VrefLevel [Byte0]: 51
7939 09:28:29.358415 [Byte1]: 51
7940 09:28:29.362977
7941 09:28:29.363090 Set Vref, RX VrefLevel [Byte0]: 52
7942 09:28:29.366194 [Byte1]: 52
7943 09:28:29.370571
7944 09:28:29.370680 Set Vref, RX VrefLevel [Byte0]: 53
7945 09:28:29.373875 [Byte1]: 53
7946 09:28:29.378502
7947 09:28:29.381579 Set Vref, RX VrefLevel [Byte0]: 54
7948 09:28:29.381691 [Byte1]: 54
7949 09:28:29.385721
7950 09:28:29.385829 Set Vref, RX VrefLevel [Byte0]: 55
7951 09:28:29.389172 [Byte1]: 55
7952 09:28:29.393422
7953 09:28:29.393532 Set Vref, RX VrefLevel [Byte0]: 56
7954 09:28:29.396928 [Byte1]: 56
7955 09:28:29.401115
7956 09:28:29.401226 Set Vref, RX VrefLevel [Byte0]: 57
7957 09:28:29.404292 [Byte1]: 57
7958 09:28:29.408432
7959 09:28:29.408551 Set Vref, RX VrefLevel [Byte0]: 58
7960 09:28:29.411841 [Byte1]: 58
7961 09:28:29.416343
7962 09:28:29.416459 Set Vref, RX VrefLevel [Byte0]: 59
7963 09:28:29.419373 [Byte1]: 59
7964 09:28:29.424228
7965 09:28:29.424345 Set Vref, RX VrefLevel [Byte0]: 60
7966 09:28:29.427619 [Byte1]: 60
7967 09:28:29.431564
7968 09:28:29.431679 Set Vref, RX VrefLevel [Byte0]: 61
7969 09:28:29.434704 [Byte1]: 61
7970 09:28:29.439377
7971 09:28:29.439490 Set Vref, RX VrefLevel [Byte0]: 62
7972 09:28:29.442341 [Byte1]: 62
7973 09:28:29.446798
7974 09:28:29.446910 Set Vref, RX VrefLevel [Byte0]: 63
7975 09:28:29.449996 [Byte1]: 63
7976 09:28:29.454329
7977 09:28:29.454442 Set Vref, RX VrefLevel [Byte0]: 64
7978 09:28:29.457516 [Byte1]: 64
7979 09:28:29.462144
7980 09:28:29.462254 Set Vref, RX VrefLevel [Byte0]: 65
7981 09:28:29.465495 [Byte1]: 65
7982 09:28:29.469527
7983 09:28:29.469643 Set Vref, RX VrefLevel [Byte0]: 66
7984 09:28:29.472684 [Byte1]: 66
7985 09:28:29.477055
7986 09:28:29.477185 Set Vref, RX VrefLevel [Byte0]: 67
7987 09:28:29.480593 [Byte1]: 67
7988 09:28:29.484667
7989 09:28:29.484780 Set Vref, RX VrefLevel [Byte0]: 68
7990 09:28:29.487972 [Byte1]: 68
7991 09:28:29.492429
7992 09:28:29.492516 Set Vref, RX VrefLevel [Byte0]: 69
7993 09:28:29.495719 [Byte1]: 69
7994 09:28:29.500226
7995 09:28:29.500310 Set Vref, RX VrefLevel [Byte0]: 70
7996 09:28:29.503083 [Byte1]: 70
7997 09:28:29.507750
7998 09:28:29.507840 Set Vref, RX VrefLevel [Byte0]: 71
7999 09:28:29.511253 [Byte1]: 71
8000 09:28:29.515077
8001 09:28:29.515189 Set Vref, RX VrefLevel [Byte0]: 72
8002 09:28:29.518651 [Byte1]: 72
8003 09:28:29.523286
8004 09:28:29.523375 Set Vref, RX VrefLevel [Byte0]: 73
8005 09:28:29.526118 [Byte1]: 73
8006 09:28:29.530641
8007 09:28:29.530756 Set Vref, RX VrefLevel [Byte0]: 74
8008 09:28:29.534113 [Byte1]: 74
8009 09:28:29.538346
8010 09:28:29.538456 Set Vref, RX VrefLevel [Byte0]: 75
8011 09:28:29.541472 [Byte1]: 75
8012 09:28:29.545613
8013 09:28:29.545697 Set Vref, RX VrefLevel [Byte0]: 76
8014 09:28:29.548993 [Byte1]: 76
8015 09:28:29.553617
8016 09:28:29.553734 Final RX Vref Byte 0 = 56 to rank0
8017 09:28:29.557018 Final RX Vref Byte 1 = 62 to rank0
8018 09:28:29.559986 Final RX Vref Byte 0 = 56 to rank1
8019 09:28:29.563279 Final RX Vref Byte 1 = 62 to rank1==
8020 09:28:29.566776 Dram Type= 6, Freq= 0, CH_0, rank 0
8021 09:28:29.573516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 09:28:29.573632 ==
8023 09:28:29.573734 DQS Delay:
8024 09:28:29.573832 DQS0 = 0, DQS1 = 0
8025 09:28:29.576992 DQM Delay:
8026 09:28:29.577101 DQM0 = 129, DQM1 = 121
8027 09:28:29.580713 DQ Delay:
8028 09:28:29.584212 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
8029 09:28:29.586906 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8030 09:28:29.590557 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
8031 09:28:29.593771 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8032 09:28:29.593877
8033 09:28:29.593976
8034 09:28:29.594070
8035 09:28:29.597187 [DramC_TX_OE_Calibration] TA2
8036 09:28:29.600438 Original DQ_B0 (3 6) =30, OEN = 27
8037 09:28:29.603914 Original DQ_B1 (3 6) =30, OEN = 27
8038 09:28:29.604022 24, 0x0, End_B0=24 End_B1=24
8039 09:28:29.607403 25, 0x0, End_B0=25 End_B1=25
8040 09:28:29.610470 26, 0x0, End_B0=26 End_B1=26
8041 09:28:29.613712 27, 0x0, End_B0=27 End_B1=27
8042 09:28:29.617229 28, 0x0, End_B0=28 End_B1=28
8043 09:28:29.617339 29, 0x0, End_B0=29 End_B1=29
8044 09:28:29.620407 30, 0x0, End_B0=30 End_B1=30
8045 09:28:29.624011 31, 0x4141, End_B0=30 End_B1=30
8046 09:28:29.627346 Byte0 end_step=30 best_step=27
8047 09:28:29.631026 Byte1 end_step=30 best_step=27
8048 09:28:29.631135 Byte0 TX OE(2T, 0.5T) = (3, 3)
8049 09:28:29.634111 Byte1 TX OE(2T, 0.5T) = (3, 3)
8050 09:28:29.634191
8051 09:28:29.634254
8052 09:28:29.643765 [DQSOSCAuto] RK0, (LSB)MR18= 0x1306, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8053 09:28:29.647187 CH0 RK0: MR19=303, MR18=1306
8054 09:28:29.650641 CH0_RK0: MR19=0x303, MR18=0x1306, DQSOSC=400, MR23=63, INC=23, DEC=15
8055 09:28:29.650770
8056 09:28:29.654248 ----->DramcWriteLeveling(PI) begin...
8057 09:28:29.657236 ==
8058 09:28:29.657317 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 09:28:29.664063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 09:28:29.664146 ==
8061 09:28:29.667543 Write leveling (Byte 0): 32 => 32
8062 09:28:29.670588 Write leveling (Byte 1): 26 => 26
8063 09:28:29.673814 DramcWriteLeveling(PI) end<-----
8064 09:28:29.673895
8065 09:28:29.673958 ==
8066 09:28:29.677718 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 09:28:29.680708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 09:28:29.680789 ==
8069 09:28:29.684152 [Gating] SW mode calibration
8070 09:28:29.690633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8071 09:28:29.693983 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8072 09:28:29.700651 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 09:28:29.703988 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 09:28:29.707443 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8075 09:28:29.714015 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8076 09:28:29.717412 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8077 09:28:29.720983 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8078 09:28:29.727468 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 09:28:29.730687 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 09:28:29.734109 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 09:28:29.740838 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8082 09:28:29.744048 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8083 09:28:29.747617 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8084 09:28:29.754497 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8085 09:28:29.757586 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8086 09:28:29.760761 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 09:28:29.764065 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 09:28:29.771022 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 09:28:29.774193 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 09:28:29.777435 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8091 09:28:29.784700 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8092 09:28:29.787882 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8093 09:28:29.791239 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8094 09:28:29.797487 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 09:28:29.800858 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 09:28:29.804217 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 09:28:29.811433 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 09:28:29.814535 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8099 09:28:29.817818 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8100 09:28:29.824586 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8101 09:28:29.827623 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8102 09:28:29.830975 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8103 09:28:29.834312 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 09:28:29.841527 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 09:28:29.844530 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 09:28:29.848065 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 09:28:29.854398 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 09:28:29.857952 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 09:28:29.861234 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 09:28:29.868048 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 09:28:29.871837 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 09:28:29.874514 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 09:28:29.881737 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8114 09:28:29.884855 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 09:28:29.887858 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8116 09:28:29.891628 Total UI for P1: 0, mck2ui 16
8117 09:28:29.894628 best dqsien dly found for B0: ( 1, 9, 6)
8118 09:28:29.897965 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8119 09:28:29.904487 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8120 09:28:29.908194 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8121 09:28:29.911537 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 09:28:29.915037 Total UI for P1: 0, mck2ui 16
8123 09:28:29.918580 best dqsien dly found for B1: ( 1, 9, 22)
8124 09:28:29.921788 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8125 09:28:29.925015 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8126 09:28:29.925096
8127 09:28:29.931944 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8128 09:28:29.934996 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8129 09:28:29.938098 [Gating] SW calibration Done
8130 09:28:29.938178 ==
8131 09:28:29.941647 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 09:28:29.945029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 09:28:29.945110 ==
8134 09:28:29.945173 RX Vref Scan: 0
8135 09:28:29.948440
8136 09:28:29.948519 RX Vref 0 -> 0, step: 1
8137 09:28:29.948582
8138 09:28:29.951612 RX Delay 0 -> 252, step: 8
8139 09:28:29.955004 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8140 09:28:29.958168 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8141 09:28:29.964742 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8142 09:28:29.967984 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8143 09:28:29.971722 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8144 09:28:29.975012 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8145 09:28:29.977819 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8146 09:28:29.981873 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8147 09:28:29.988221 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8148 09:28:29.991346 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8149 09:28:29.994411 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8150 09:28:29.998523 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8151 09:28:30.001168 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8152 09:28:30.008174 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8153 09:28:30.011502 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8154 09:28:30.014808 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8155 09:28:30.014889 ==
8156 09:28:30.018267 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 09:28:30.021267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 09:28:30.024646 ==
8159 09:28:30.024743 DQS Delay:
8160 09:28:30.024808 DQS0 = 0, DQS1 = 0
8161 09:28:30.028392 DQM Delay:
8162 09:28:30.028474 DQM0 = 131, DQM1 = 124
8163 09:28:30.031216 DQ Delay:
8164 09:28:30.034855 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8165 09:28:30.037965 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8166 09:28:30.041154 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8167 09:28:30.044726 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8168 09:28:30.044846
8169 09:28:30.044913
8170 09:28:30.044971 ==
8171 09:28:30.047737 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 09:28:30.051123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 09:28:30.051233 ==
8174 09:28:30.051296
8175 09:28:30.054525
8176 09:28:30.054621 TX Vref Scan disable
8177 09:28:30.057957 == TX Byte 0 ==
8178 09:28:30.061318 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8179 09:28:30.064901 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8180 09:28:30.067978 == TX Byte 1 ==
8181 09:28:30.071356 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8182 09:28:30.074755 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8183 09:28:30.074875 ==
8184 09:28:30.078060 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 09:28:30.084636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 09:28:30.084741 ==
8187 09:28:30.098120
8188 09:28:30.101223 TX Vref early break, caculate TX vref
8189 09:28:30.104231 TX Vref=16, minBit 1, minWin=22, winSum=371
8190 09:28:30.108080 TX Vref=18, minBit 9, minWin=22, winSum=378
8191 09:28:30.110988 TX Vref=20, minBit 8, minWin=23, winSum=384
8192 09:28:30.114551 TX Vref=22, minBit 1, minWin=24, winSum=397
8193 09:28:30.118242 TX Vref=24, minBit 1, minWin=24, winSum=403
8194 09:28:30.121680 TX Vref=26, minBit 0, minWin=25, winSum=411
8195 09:28:30.128120 TX Vref=28, minBit 1, minWin=25, winSum=412
8196 09:28:30.131462 TX Vref=30, minBit 1, minWin=25, winSum=412
8197 09:28:30.134446 TX Vref=32, minBit 0, minWin=24, winSum=405
8198 09:28:30.138472 TX Vref=34, minBit 1, minWin=23, winSum=396
8199 09:28:30.141588 TX Vref=36, minBit 0, minWin=23, winSum=389
8200 09:28:30.148169 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 28
8201 09:28:30.148255
8202 09:28:30.151335 Final TX Range 0 Vref 28
8203 09:28:30.151420
8204 09:28:30.151485 ==
8205 09:28:30.154640 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 09:28:30.158286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 09:28:30.158371 ==
8208 09:28:30.158437
8209 09:28:30.158498
8210 09:28:30.161869 TX Vref Scan disable
8211 09:28:30.167981 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8212 09:28:30.168067 == TX Byte 0 ==
8213 09:28:30.171940 u2DelayCellOfst[0]=14 cells (4 PI)
8214 09:28:30.175162 u2DelayCellOfst[1]=17 cells (5 PI)
8215 09:28:30.178211 u2DelayCellOfst[2]=10 cells (3 PI)
8216 09:28:30.181755 u2DelayCellOfst[3]=14 cells (4 PI)
8217 09:28:30.185168 u2DelayCellOfst[4]=10 cells (3 PI)
8218 09:28:30.188326 u2DelayCellOfst[5]=0 cells (0 PI)
8219 09:28:30.191664 u2DelayCellOfst[6]=17 cells (5 PI)
8220 09:28:30.191745 u2DelayCellOfst[7]=17 cells (5 PI)
8221 09:28:30.198132 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8222 09:28:30.201376 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8223 09:28:30.201465 == TX Byte 1 ==
8224 09:28:30.204927 u2DelayCellOfst[8]=0 cells (0 PI)
8225 09:28:30.208476 u2DelayCellOfst[9]=0 cells (0 PI)
8226 09:28:30.211454 u2DelayCellOfst[10]=7 cells (2 PI)
8227 09:28:30.215000 u2DelayCellOfst[11]=0 cells (0 PI)
8228 09:28:30.217938 u2DelayCellOfst[12]=10 cells (3 PI)
8229 09:28:30.221623 u2DelayCellOfst[13]=7 cells (2 PI)
8230 09:28:30.225113 u2DelayCellOfst[14]=14 cells (4 PI)
8231 09:28:30.228463 u2DelayCellOfst[15]=10 cells (3 PI)
8232 09:28:30.231626 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8233 09:28:30.235108 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8234 09:28:30.238477 DramC Write-DBI on
8235 09:28:30.238561 ==
8236 09:28:30.241577 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 09:28:30.244905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 09:28:30.244988 ==
8239 09:28:30.245053
8240 09:28:30.245113
8241 09:28:30.248265 TX Vref Scan disable
8242 09:28:30.251277 == TX Byte 0 ==
8243 09:28:30.255067 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8244 09:28:30.258202 == TX Byte 1 ==
8245 09:28:30.261940 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8246 09:28:30.262053 DramC Write-DBI off
8247 09:28:30.262147
8248 09:28:30.265173 [DATLAT]
8249 09:28:30.265250 Freq=1600, CH0 RK1
8250 09:28:30.265314
8251 09:28:30.268777 DATLAT Default: 0xf
8252 09:28:30.268854 0, 0xFFFF, sum = 0
8253 09:28:30.271681 1, 0xFFFF, sum = 0
8254 09:28:30.271757 2, 0xFFFF, sum = 0
8255 09:28:30.275160 3, 0xFFFF, sum = 0
8256 09:28:30.275237 4, 0xFFFF, sum = 0
8257 09:28:30.278349 5, 0xFFFF, sum = 0
8258 09:28:30.278440 6, 0xFFFF, sum = 0
8259 09:28:30.282145 7, 0xFFFF, sum = 0
8260 09:28:30.282240 8, 0xFFFF, sum = 0
8261 09:28:30.285469 9, 0xFFFF, sum = 0
8262 09:28:30.285594 10, 0xFFFF, sum = 0
8263 09:28:30.288697 11, 0xFFFF, sum = 0
8264 09:28:30.292042 12, 0xFFFF, sum = 0
8265 09:28:30.292148 13, 0xFFFF, sum = 0
8266 09:28:30.295048 14, 0x0, sum = 1
8267 09:28:30.295132 15, 0x0, sum = 2
8268 09:28:30.295199 16, 0x0, sum = 3
8269 09:28:30.298926 17, 0x0, sum = 4
8270 09:28:30.299010 best_step = 15
8271 09:28:30.299075
8272 09:28:30.301763 ==
8273 09:28:30.301846 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 09:28:30.308631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 09:28:30.308717 ==
8276 09:28:30.308782 RX Vref Scan: 0
8277 09:28:30.308843
8278 09:28:30.311813 RX Vref 0 -> 0, step: 1
8279 09:28:30.311895
8280 09:28:30.315223 RX Delay 11 -> 252, step: 4
8281 09:28:30.318513 iDelay=191, Bit 0, Center 128 (75 ~ 182) 108
8282 09:28:30.321648 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8283 09:28:30.328729 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8284 09:28:30.332284 iDelay=191, Bit 3, Center 128 (71 ~ 186) 116
8285 09:28:30.335471 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8286 09:28:30.338577 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8287 09:28:30.341760 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8288 09:28:30.345379 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8289 09:28:30.351896 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8290 09:28:30.355456 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8291 09:28:30.358404 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8292 09:28:30.362491 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8293 09:28:30.365145 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8294 09:28:30.371915 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8295 09:28:30.375620 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8296 09:28:30.378920 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8297 09:28:30.379003 ==
8298 09:28:30.382455 Dram Type= 6, Freq= 0, CH_0, rank 1
8299 09:28:30.385463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 09:28:30.385547 ==
8301 09:28:30.388626 DQS Delay:
8302 09:28:30.388709 DQS0 = 0, DQS1 = 0
8303 09:28:30.392313 DQM Delay:
8304 09:28:30.392396 DQM0 = 127, DQM1 = 122
8305 09:28:30.395477 DQ Delay:
8306 09:28:30.398707 DQ0 =128, DQ1 =130, DQ2 =122, DQ3 =128
8307 09:28:30.401984 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8308 09:28:30.405289 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8309 09:28:30.408606 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8310 09:28:30.408687
8311 09:28:30.408751
8312 09:28:30.408809
8313 09:28:30.411968 [DramC_TX_OE_Calibration] TA2
8314 09:28:30.415311 Original DQ_B0 (3 6) =30, OEN = 27
8315 09:28:30.418647 Original DQ_B1 (3 6) =30, OEN = 27
8316 09:28:30.418756 24, 0x0, End_B0=24 End_B1=24
8317 09:28:30.422093 25, 0x0, End_B0=25 End_B1=25
8318 09:28:30.425715 26, 0x0, End_B0=26 End_B1=26
8319 09:28:30.429117 27, 0x0, End_B0=27 End_B1=27
8320 09:28:30.432157 28, 0x0, End_B0=28 End_B1=28
8321 09:28:30.432241 29, 0x0, End_B0=29 End_B1=29
8322 09:28:30.435763 30, 0x0, End_B0=30 End_B1=30
8323 09:28:30.438659 31, 0x4141, End_B0=30 End_B1=30
8324 09:28:30.442011 Byte0 end_step=30 best_step=27
8325 09:28:30.445231 Byte1 end_step=30 best_step=27
8326 09:28:30.448325 Byte0 TX OE(2T, 0.5T) = (3, 3)
8327 09:28:30.448407 Byte1 TX OE(2T, 0.5T) = (3, 3)
8328 09:28:30.448472
8329 09:28:30.448532
8330 09:28:30.458280 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8331 09:28:30.461697 CH0 RK1: MR19=303, MR18=1A0E
8332 09:28:30.468311 CH0_RK1: MR19=0x303, MR18=0x1A0E, DQSOSC=396, MR23=63, INC=23, DEC=15
8333 09:28:30.468392 [RxdqsGatingPostProcess] freq 1600
8334 09:28:30.474922 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8335 09:28:30.478360 best DQS0 dly(2T, 0.5T) = (1, 1)
8336 09:28:30.481695 best DQS1 dly(2T, 0.5T) = (1, 1)
8337 09:28:30.485135 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8338 09:28:30.488364 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8339 09:28:30.491716 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 09:28:30.494706 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 09:28:30.498392 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 09:28:30.498474 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 09:28:30.501604 Pre-setting of DQS Precalculation
8344 09:28:30.508276 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8345 09:28:30.508426 ==
8346 09:28:30.511718 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 09:28:30.514997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 09:28:30.515080 ==
8349 09:28:30.521832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 09:28:30.525095 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 09:28:30.528445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 09:28:30.534599 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 09:28:30.544444 [CA 0] Center 42 (14~71) winsize 58
8354 09:28:30.547517 [CA 1] Center 42 (13~71) winsize 59
8355 09:28:30.550862 [CA 2] Center 37 (9~66) winsize 58
8356 09:28:30.554424 [CA 3] Center 36 (7~65) winsize 59
8357 09:28:30.557915 [CA 4] Center 37 (7~67) winsize 61
8358 09:28:30.561076 [CA 5] Center 36 (7~66) winsize 60
8359 09:28:30.561157
8360 09:28:30.564409 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8361 09:28:30.564489
8362 09:28:30.567706 [CATrainingPosCal] consider 1 rank data
8363 09:28:30.570892 u2DelayCellTimex100 = 275/100 ps
8364 09:28:30.574480 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8365 09:28:30.580748 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8366 09:28:30.584326 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8367 09:28:30.587675 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8368 09:28:30.591012 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8369 09:28:30.594345 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8370 09:28:30.594425
8371 09:28:30.597615 CA PerBit enable=1, Macro0, CA PI delay=36
8372 09:28:30.597695
8373 09:28:30.601307 [CBTSetCACLKResult] CA Dly = 36
8374 09:28:30.601387 CS Dly: 9 (0~40)
8375 09:28:30.607211 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 09:28:30.610525 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 09:28:30.610633 ==
8378 09:28:30.614108 Dram Type= 6, Freq= 0, CH_1, rank 1
8379 09:28:30.617548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 09:28:30.617628 ==
8381 09:28:30.624266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8382 09:28:30.627631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8383 09:28:30.634302 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8384 09:28:30.637663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8385 09:28:30.647895 [CA 0] Center 43 (14~72) winsize 59
8386 09:28:30.650943 [CA 1] Center 43 (14~72) winsize 59
8387 09:28:30.654073 [CA 2] Center 38 (9~67) winsize 59
8388 09:28:30.657804 [CA 3] Center 37 (8~67) winsize 60
8389 09:28:30.660717 [CA 4] Center 38 (9~67) winsize 59
8390 09:28:30.663968 [CA 5] Center 37 (8~66) winsize 59
8391 09:28:30.664050
8392 09:28:30.667771 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8393 09:28:30.667852
8394 09:28:30.670943 [CATrainingPosCal] consider 2 rank data
8395 09:28:30.674240 u2DelayCellTimex100 = 275/100 ps
8396 09:28:30.677680 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8397 09:28:30.681389 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8398 09:28:30.687773 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8399 09:28:30.691084 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8400 09:28:30.694669 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8401 09:28:30.697572 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8402 09:28:30.697653
8403 09:28:30.700857 CA PerBit enable=1, Macro0, CA PI delay=36
8404 09:28:30.700938
8405 09:28:30.704385 [CBTSetCACLKResult] CA Dly = 36
8406 09:28:30.704465 CS Dly: 11 (0~44)
8407 09:28:30.711372 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8408 09:28:30.714672 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8409 09:28:30.714805
8410 09:28:30.717766 ----->DramcWriteLeveling(PI) begin...
8411 09:28:30.717873 ==
8412 09:28:30.720969 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 09:28:30.724237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 09:28:30.724321 ==
8415 09:28:30.728166 Write leveling (Byte 0): 25 => 25
8416 09:28:30.731144 Write leveling (Byte 1): 29 => 29
8417 09:28:30.734425 DramcWriteLeveling(PI) end<-----
8418 09:28:30.734506
8419 09:28:30.734569 ==
8420 09:28:30.737831 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 09:28:30.741075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 09:28:30.744225 ==
8423 09:28:30.744321 [Gating] SW mode calibration
8424 09:28:30.750964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8425 09:28:30.757730 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8426 09:28:30.761179 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 09:28:30.767568 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 09:28:30.771063 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 09:28:30.774438 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 09:28:30.781151 1 4 16 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
8431 09:28:30.784544 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 09:28:30.787856 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 09:28:30.794693 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 09:28:30.797824 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 09:28:30.801009 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 09:28:30.804720 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 09:28:30.811450 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 09:28:30.814460 1 5 16 | B1->B0 | 2c2c 3131 | 0 1 | (1 0) (1 0)
8439 09:28:30.817825 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
8440 09:28:30.824623 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 09:28:30.827998 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 09:28:30.831185 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 09:28:30.837830 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 09:28:30.841548 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 09:28:30.844628 1 6 12 | B1->B0 | 2424 2525 | 0 0 | (1 1) (0 0)
8446 09:28:30.851162 1 6 16 | B1->B0 | 3838 2b2b | 0 0 | (0 0) (1 1)
8447 09:28:30.854553 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 09:28:30.857844 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 09:28:30.864863 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 09:28:30.868219 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 09:28:30.871479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 09:28:30.877954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 09:28:30.881539 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 09:28:30.884483 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8455 09:28:30.887881 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8456 09:28:30.894881 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 09:28:30.898047 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 09:28:30.901162 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 09:28:30.907815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 09:28:30.911178 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 09:28:30.915414 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 09:28:30.921242 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 09:28:30.924733 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 09:28:30.928180 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 09:28:30.934461 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 09:28:30.938103 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 09:28:30.941294 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 09:28:30.947958 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 09:28:30.951542 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 09:28:30.954476 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8471 09:28:30.961379 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 09:28:30.961479 Total UI for P1: 0, mck2ui 16
8473 09:28:30.964575 best dqsien dly found for B0: ( 1, 9, 16)
8474 09:28:30.968012 Total UI for P1: 0, mck2ui 16
8475 09:28:30.971831 best dqsien dly found for B1: ( 1, 9, 16)
8476 09:28:30.974641 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8477 09:28:30.981407 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8478 09:28:30.981498
8479 09:28:30.984800 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8480 09:28:30.988151 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8481 09:28:30.991931 [Gating] SW calibration Done
8482 09:28:30.992016 ==
8483 09:28:30.994651 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 09:28:30.998196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 09:28:30.998280 ==
8486 09:28:30.998345 RX Vref Scan: 0
8487 09:28:31.001491
8488 09:28:31.001573 RX Vref 0 -> 0, step: 1
8489 09:28:31.001639
8490 09:28:31.004872 RX Delay 0 -> 252, step: 8
8491 09:28:31.008316 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8492 09:28:31.011899 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8493 09:28:31.018569 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8494 09:28:31.021960 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8495 09:28:31.024900 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8496 09:28:31.028265 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8497 09:28:31.031733 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8498 09:28:31.038047 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8499 09:28:31.041632 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8500 09:28:31.044744 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8501 09:28:31.048119 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8502 09:28:31.051654 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8503 09:28:31.058533 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8504 09:28:31.061806 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8505 09:28:31.064750 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8506 09:28:31.068020 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8507 09:28:31.068133 ==
8508 09:28:31.071423 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 09:28:31.075096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 09:28:31.077979 ==
8511 09:28:31.078060 DQS Delay:
8512 09:28:31.078123 DQS0 = 0, DQS1 = 0
8513 09:28:31.081899 DQM Delay:
8514 09:28:31.081999 DQM0 = 135, DQM1 = 126
8515 09:28:31.084803 DQ Delay:
8516 09:28:31.088060 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8517 09:28:31.091821 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8518 09:28:31.094876 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8519 09:28:31.098442 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8520 09:28:31.098551
8521 09:28:31.098618
8522 09:28:31.098679 ==
8523 09:28:31.101792 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 09:28:31.105242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 09:28:31.105342 ==
8526 09:28:31.105409
8527 09:28:31.105471
8528 09:28:31.108356 TX Vref Scan disable
8529 09:28:31.111309 == TX Byte 0 ==
8530 09:28:31.114986 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8531 09:28:31.118024 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8532 09:28:31.121689 == TX Byte 1 ==
8533 09:28:31.124755 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8534 09:28:31.128266 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8535 09:28:31.128360 ==
8536 09:28:31.131401 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 09:28:31.134845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 09:28:31.138262 ==
8539 09:28:31.150554
8540 09:28:31.154227 TX Vref early break, caculate TX vref
8541 09:28:31.157319 TX Vref=16, minBit 11, minWin=20, winSum=359
8542 09:28:31.160794 TX Vref=18, minBit 8, minWin=21, winSum=371
8543 09:28:31.164323 TX Vref=20, minBit 8, minWin=22, winSum=384
8544 09:28:31.167551 TX Vref=22, minBit 8, minWin=22, winSum=392
8545 09:28:31.170643 TX Vref=24, minBit 8, minWin=23, winSum=405
8546 09:28:31.177229 TX Vref=26, minBit 8, minWin=24, winSum=409
8547 09:28:31.181139 TX Vref=28, minBit 11, minWin=24, winSum=419
8548 09:28:31.184250 TX Vref=30, minBit 1, minWin=25, winSum=415
8549 09:28:31.187142 TX Vref=32, minBit 0, minWin=25, winSum=409
8550 09:28:31.190629 TX Vref=34, minBit 8, minWin=24, winSum=399
8551 09:28:31.193911 TX Vref=36, minBit 8, minWin=23, winSum=389
8552 09:28:31.200602 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
8553 09:28:31.200726
8554 09:28:31.203923 Final TX Range 0 Vref 30
8555 09:28:31.204025
8556 09:28:31.204091 ==
8557 09:28:31.207121 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 09:28:31.210608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 09:28:31.210789 ==
8560 09:28:31.210924
8561 09:28:31.211060
8562 09:28:31.213812 TX Vref Scan disable
8563 09:28:31.220628 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8564 09:28:31.220821 == TX Byte 0 ==
8565 09:28:31.223915 u2DelayCellOfst[0]=17 cells (5 PI)
8566 09:28:31.227535 u2DelayCellOfst[1]=14 cells (4 PI)
8567 09:28:31.230892 u2DelayCellOfst[2]=0 cells (0 PI)
8568 09:28:31.234019 u2DelayCellOfst[3]=7 cells (2 PI)
8569 09:28:31.237508 u2DelayCellOfst[4]=7 cells (2 PI)
8570 09:28:31.240923 u2DelayCellOfst[5]=17 cells (5 PI)
8571 09:28:31.244554 u2DelayCellOfst[6]=17 cells (5 PI)
8572 09:28:31.247750 u2DelayCellOfst[7]=7 cells (2 PI)
8573 09:28:31.250734 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8574 09:28:31.254477 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8575 09:28:31.257565 == TX Byte 1 ==
8576 09:28:31.257748 u2DelayCellOfst[8]=0 cells (0 PI)
8577 09:28:31.260985 u2DelayCellOfst[9]=7 cells (2 PI)
8578 09:28:31.264173 u2DelayCellOfst[10]=10 cells (3 PI)
8579 09:28:31.267479 u2DelayCellOfst[11]=7 cells (2 PI)
8580 09:28:31.270816 u2DelayCellOfst[12]=14 cells (4 PI)
8581 09:28:31.274221 u2DelayCellOfst[13]=17 cells (5 PI)
8582 09:28:31.277332 u2DelayCellOfst[14]=17 cells (5 PI)
8583 09:28:31.280793 u2DelayCellOfst[15]=21 cells (6 PI)
8584 09:28:31.284399 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8585 09:28:31.290663 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8586 09:28:31.290790 DramC Write-DBI on
8587 09:28:31.290861 ==
8588 09:28:31.294469 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 09:28:31.297963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 09:28:31.298052 ==
8591 09:28:31.300945
8592 09:28:31.301030
8593 09:28:31.301094 TX Vref Scan disable
8594 09:28:31.304135 == TX Byte 0 ==
8595 09:28:31.307737 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8596 09:28:31.311185 == TX Byte 1 ==
8597 09:28:31.314596 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8598 09:28:31.314717 DramC Write-DBI off
8599 09:28:31.317425
8600 09:28:31.317513 [DATLAT]
8601 09:28:31.317578 Freq=1600, CH1 RK0
8602 09:28:31.317638
8603 09:28:31.320757 DATLAT Default: 0xf
8604 09:28:31.320842 0, 0xFFFF, sum = 0
8605 09:28:31.323887 1, 0xFFFF, sum = 0
8606 09:28:31.324038 2, 0xFFFF, sum = 0
8607 09:28:31.327303 3, 0xFFFF, sum = 0
8608 09:28:31.331068 4, 0xFFFF, sum = 0
8609 09:28:31.331210 5, 0xFFFF, sum = 0
8610 09:28:31.333945 6, 0xFFFF, sum = 0
8611 09:28:31.334035 7, 0xFFFF, sum = 0
8612 09:28:31.337765 8, 0xFFFF, sum = 0
8613 09:28:31.337857 9, 0xFFFF, sum = 0
8614 09:28:31.340830 10, 0xFFFF, sum = 0
8615 09:28:31.340918 11, 0xFFFF, sum = 0
8616 09:28:31.344224 12, 0xFFFF, sum = 0
8617 09:28:31.344312 13, 0xFFFF, sum = 0
8618 09:28:31.347586 14, 0x0, sum = 1
8619 09:28:31.347675 15, 0x0, sum = 2
8620 09:28:31.350685 16, 0x0, sum = 3
8621 09:28:31.350825 17, 0x0, sum = 4
8622 09:28:31.350896 best_step = 15
8623 09:28:31.354381
8624 09:28:31.354470 ==
8625 09:28:31.357885 Dram Type= 6, Freq= 0, CH_1, rank 0
8626 09:28:31.361365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8627 09:28:31.361462 ==
8628 09:28:31.361529 RX Vref Scan: 1
8629 09:28:31.361589
8630 09:28:31.364540 Set Vref Range= 24 -> 127
8631 09:28:31.364626
8632 09:28:31.367749 RX Vref 24 -> 127, step: 1
8633 09:28:31.367834
8634 09:28:31.371016 RX Delay 11 -> 252, step: 4
8635 09:28:31.371103
8636 09:28:31.374281 Set Vref, RX VrefLevel [Byte0]: 24
8637 09:28:31.377502 [Byte1]: 24
8638 09:28:31.377620
8639 09:28:31.381255 Set Vref, RX VrefLevel [Byte0]: 25
8640 09:28:31.384755 [Byte1]: 25
8641 09:28:31.384851
8642 09:28:31.387845 Set Vref, RX VrefLevel [Byte0]: 26
8643 09:28:31.390948 [Byte1]: 26
8644 09:28:31.394747
8645 09:28:31.394849 Set Vref, RX VrefLevel [Byte0]: 27
8646 09:28:31.398220 [Byte1]: 27
8647 09:28:31.401998
8648 09:28:31.402100 Set Vref, RX VrefLevel [Byte0]: 28
8649 09:28:31.405706 [Byte1]: 28
8650 09:28:31.409919
8651 09:28:31.410043 Set Vref, RX VrefLevel [Byte0]: 29
8652 09:28:31.413011 [Byte1]: 29
8653 09:28:31.417502
8654 09:28:31.417614 Set Vref, RX VrefLevel [Byte0]: 30
8655 09:28:31.420985 [Byte1]: 30
8656 09:28:31.424724
8657 09:28:31.424836 Set Vref, RX VrefLevel [Byte0]: 31
8658 09:28:31.428602 [Byte1]: 31
8659 09:28:31.432807
8660 09:28:31.432922 Set Vref, RX VrefLevel [Byte0]: 32
8661 09:28:31.435988 [Byte1]: 32
8662 09:28:31.440106
8663 09:28:31.440340 Set Vref, RX VrefLevel [Byte0]: 33
8664 09:28:31.443889 [Byte1]: 33
8665 09:28:31.447840
8666 09:28:31.447957 Set Vref, RX VrefLevel [Byte0]: 34
8667 09:28:31.451079 [Byte1]: 34
8668 09:28:31.455352
8669 09:28:31.455469 Set Vref, RX VrefLevel [Byte0]: 35
8670 09:28:31.458580 [Byte1]: 35
8671 09:28:31.463114
8672 09:28:31.463254 Set Vref, RX VrefLevel [Byte0]: 36
8673 09:28:31.466269 [Byte1]: 36
8674 09:28:31.470683
8675 09:28:31.470829 Set Vref, RX VrefLevel [Byte0]: 37
8676 09:28:31.474248 [Byte1]: 37
8677 09:28:31.478263
8678 09:28:31.478376 Set Vref, RX VrefLevel [Byte0]: 38
8679 09:28:31.481739 [Byte1]: 38
8680 09:28:31.485818
8681 09:28:31.485930 Set Vref, RX VrefLevel [Byte0]: 39
8682 09:28:31.488967 [Byte1]: 39
8683 09:28:31.493534
8684 09:28:31.493646 Set Vref, RX VrefLevel [Byte0]: 40
8685 09:28:31.496615 [Byte1]: 40
8686 09:28:31.501255
8687 09:28:31.501365 Set Vref, RX VrefLevel [Byte0]: 41
8688 09:28:31.504758 [Byte1]: 41
8689 09:28:31.508568
8690 09:28:31.508710 Set Vref, RX VrefLevel [Byte0]: 42
8691 09:28:31.512246 [Byte1]: 42
8692 09:28:31.516285
8693 09:28:31.516398 Set Vref, RX VrefLevel [Byte0]: 43
8694 09:28:31.519882 [Byte1]: 43
8695 09:28:31.523973
8696 09:28:31.524080 Set Vref, RX VrefLevel [Byte0]: 44
8697 09:28:31.526996 [Byte1]: 44
8698 09:28:31.531869
8699 09:28:31.531986 Set Vref, RX VrefLevel [Byte0]: 45
8700 09:28:31.534943 [Byte1]: 45
8701 09:28:31.539043
8702 09:28:31.539150 Set Vref, RX VrefLevel [Byte0]: 46
8703 09:28:31.542257 [Byte1]: 46
8704 09:28:31.546621
8705 09:28:31.546773 Set Vref, RX VrefLevel [Byte0]: 47
8706 09:28:31.549927 [Byte1]: 47
8707 09:28:31.554471
8708 09:28:31.554583 Set Vref, RX VrefLevel [Byte0]: 48
8709 09:28:31.558063 [Byte1]: 48
8710 09:28:31.562282
8711 09:28:31.562443 Set Vref, RX VrefLevel [Byte0]: 49
8712 09:28:31.565735 [Byte1]: 49
8713 09:28:31.569390
8714 09:28:31.569571 Set Vref, RX VrefLevel [Byte0]: 50
8715 09:28:31.572750 [Byte1]: 50
8716 09:28:31.577289
8717 09:28:31.577408 Set Vref, RX VrefLevel [Byte0]: 51
8718 09:28:31.580380 [Byte1]: 51
8719 09:28:31.584636
8720 09:28:31.584748 Set Vref, RX VrefLevel [Byte0]: 52
8721 09:28:31.588146 [Byte1]: 52
8722 09:28:31.592451
8723 09:28:31.592602 Set Vref, RX VrefLevel [Byte0]: 53
8724 09:28:31.595472 [Byte1]: 53
8725 09:28:31.599986
8726 09:28:31.600092 Set Vref, RX VrefLevel [Byte0]: 54
8727 09:28:31.603254 [Byte1]: 54
8728 09:28:31.607768
8729 09:28:31.607905 Set Vref, RX VrefLevel [Byte0]: 55
8730 09:28:31.610861 [Byte1]: 55
8731 09:28:31.615142
8732 09:28:31.615242 Set Vref, RX VrefLevel [Byte0]: 56
8733 09:28:31.618851 [Byte1]: 56
8734 09:28:31.622984
8735 09:28:31.623100 Set Vref, RX VrefLevel [Byte0]: 57
8736 09:28:31.626674 [Byte1]: 57
8737 09:28:31.630289
8738 09:28:31.630362 Set Vref, RX VrefLevel [Byte0]: 58
8739 09:28:31.633508 [Byte1]: 58
8740 09:28:31.638408
8741 09:28:31.638501 Set Vref, RX VrefLevel [Byte0]: 59
8742 09:28:31.641534 [Byte1]: 59
8743 09:28:31.646012
8744 09:28:31.646102 Set Vref, RX VrefLevel [Byte0]: 60
8745 09:28:31.649394 [Byte1]: 60
8746 09:28:31.653121
8747 09:28:31.653204 Set Vref, RX VrefLevel [Byte0]: 61
8748 09:28:31.656493 [Byte1]: 61
8749 09:28:31.661100
8750 09:28:31.661193 Set Vref, RX VrefLevel [Byte0]: 62
8751 09:28:31.664340 [Byte1]: 62
8752 09:28:31.668588
8753 09:28:31.668670 Set Vref, RX VrefLevel [Byte0]: 63
8754 09:28:31.671562 [Byte1]: 63
8755 09:28:31.676572
8756 09:28:31.676657 Set Vref, RX VrefLevel [Byte0]: 64
8757 09:28:31.679285 [Byte1]: 64
8758 09:28:31.683982
8759 09:28:31.684064 Set Vref, RX VrefLevel [Byte0]: 65
8760 09:28:31.687032 [Byte1]: 65
8761 09:28:31.691596
8762 09:28:31.691679 Set Vref, RX VrefLevel [Byte0]: 66
8763 09:28:31.694594 [Byte1]: 66
8764 09:28:31.699190
8765 09:28:31.699264 Set Vref, RX VrefLevel [Byte0]: 67
8766 09:28:31.702384 [Byte1]: 67
8767 09:28:31.706435
8768 09:28:31.706519 Set Vref, RX VrefLevel [Byte0]: 68
8769 09:28:31.709870 [Byte1]: 68
8770 09:28:31.714068
8771 09:28:31.714144 Set Vref, RX VrefLevel [Byte0]: 69
8772 09:28:31.717391 [Byte1]: 69
8773 09:28:31.722079
8774 09:28:31.722162 Set Vref, RX VrefLevel [Byte0]: 70
8775 09:28:31.725144 [Byte1]: 70
8776 09:28:31.729595
8777 09:28:31.729679 Set Vref, RX VrefLevel [Byte0]: 71
8778 09:28:31.732677 [Byte1]: 71
8779 09:28:31.737391
8780 09:28:31.737507 Set Vref, RX VrefLevel [Byte0]: 72
8781 09:28:31.740408 [Byte1]: 72
8782 09:28:31.745080
8783 09:28:31.745174 Set Vref, RX VrefLevel [Byte0]: 73
8784 09:28:31.748440 [Byte1]: 73
8785 09:28:31.752170
8786 09:28:31.752262 Set Vref, RX VrefLevel [Byte0]: 74
8787 09:28:31.755503 [Byte1]: 74
8788 09:28:31.759873
8789 09:28:31.759964 Set Vref, RX VrefLevel [Byte0]: 75
8790 09:28:31.763025 [Byte1]: 75
8791 09:28:31.767868
8792 09:28:31.767957 Final RX Vref Byte 0 = 58 to rank0
8793 09:28:31.770913 Final RX Vref Byte 1 = 55 to rank0
8794 09:28:31.774026 Final RX Vref Byte 0 = 58 to rank1
8795 09:28:31.777840 Final RX Vref Byte 1 = 55 to rank1==
8796 09:28:31.781299 Dram Type= 6, Freq= 0, CH_1, rank 0
8797 09:28:31.784458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 09:28:31.787673 ==
8799 09:28:31.787755 DQS Delay:
8800 09:28:31.787820 DQS0 = 0, DQS1 = 0
8801 09:28:31.791041 DQM Delay:
8802 09:28:31.791124 DQM0 = 131, DQM1 = 124
8803 09:28:31.794109 DQ Delay:
8804 09:28:31.797459 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8805 09:28:31.801214 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8806 09:28:31.804510 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8807 09:28:31.807853 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8808 09:28:31.807936
8809 09:28:31.808000
8810 09:28:31.808060
8811 09:28:31.811206 [DramC_TX_OE_Calibration] TA2
8812 09:28:31.814909 Original DQ_B0 (3 6) =30, OEN = 27
8813 09:28:31.818086 Original DQ_B1 (3 6) =30, OEN = 27
8814 09:28:31.818171 24, 0x0, End_B0=24 End_B1=24
8815 09:28:31.821319 25, 0x0, End_B0=25 End_B1=25
8816 09:28:31.824915 26, 0x0, End_B0=26 End_B1=26
8817 09:28:31.828074 27, 0x0, End_B0=27 End_B1=27
8818 09:28:31.831288 28, 0x0, End_B0=28 End_B1=28
8819 09:28:31.831372 29, 0x0, End_B0=29 End_B1=29
8820 09:28:31.834542 30, 0x0, End_B0=30 End_B1=30
8821 09:28:31.837915 31, 0x4141, End_B0=30 End_B1=30
8822 09:28:31.841005 Byte0 end_step=30 best_step=27
8823 09:28:31.845195 Byte1 end_step=30 best_step=27
8824 09:28:31.845277 Byte0 TX OE(2T, 0.5T) = (3, 3)
8825 09:28:31.847902 Byte1 TX OE(2T, 0.5T) = (3, 3)
8826 09:28:31.847984
8827 09:28:31.848112
8828 09:28:31.857763 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8829 09:28:31.861403 CH1 RK0: MR19=303, MR18=1701
8830 09:28:31.864877 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8831 09:28:31.864960
8832 09:28:31.868134 ----->DramcWriteLeveling(PI) begin...
8833 09:28:31.871125 ==
8834 09:28:31.874916 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 09:28:31.878258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 09:28:31.878340 ==
8837 09:28:31.881071 Write leveling (Byte 0): 27 => 27
8838 09:28:31.884520 Write leveling (Byte 1): 27 => 27
8839 09:28:31.888003 DramcWriteLeveling(PI) end<-----
8840 09:28:31.888103
8841 09:28:31.888195 ==
8842 09:28:31.891040 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 09:28:31.894881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 09:28:31.894964 ==
8845 09:28:31.898097 [Gating] SW mode calibration
8846 09:28:31.904746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8847 09:28:31.907869 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8848 09:28:31.914374 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 09:28:31.918197 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 09:28:31.921397 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 09:28:31.928127 1 4 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8852 09:28:31.931132 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 09:28:31.935101 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 09:28:31.941815 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 09:28:31.945140 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 09:28:31.948240 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 09:28:31.954956 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8858 09:28:31.958229 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8859 09:28:31.961591 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
8860 09:28:31.968069 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 09:28:31.971499 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 09:28:31.974858 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 09:28:31.981745 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 09:28:31.985094 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 09:28:31.988214 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8866 09:28:31.994699 1 6 8 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
8867 09:28:31.997906 1 6 12 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8868 09:28:32.001467 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 09:28:32.004734 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 09:28:32.011268 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 09:28:32.014673 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 09:28:32.018161 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 09:28:32.025149 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 09:28:32.028432 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8875 09:28:32.031328 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8876 09:28:32.038315 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8877 09:28:32.041530 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 09:28:32.045326 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 09:28:32.051460 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 09:28:32.054685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 09:28:32.058108 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 09:28:32.064986 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 09:28:32.068415 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 09:28:32.071817 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 09:28:32.075074 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 09:28:32.081726 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 09:28:32.085167 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 09:28:32.088495 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 09:28:32.095274 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8890 09:28:32.098501 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8891 09:28:32.101694 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8892 09:28:32.105273 Total UI for P1: 0, mck2ui 16
8893 09:28:32.108642 best dqsien dly found for B0: ( 1, 9, 6)
8894 09:28:32.115436 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8895 09:28:32.118411 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 09:28:32.121545 Total UI for P1: 0, mck2ui 16
8897 09:28:32.125121 best dqsien dly found for B1: ( 1, 9, 12)
8898 09:28:32.128166 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8899 09:28:32.131871 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8900 09:28:32.131961
8901 09:28:32.134995 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8902 09:28:32.138432 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8903 09:28:32.141972 [Gating] SW calibration Done
8904 09:28:32.142093 ==
8905 09:28:32.144930 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 09:28:32.148671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 09:28:32.148755 ==
8908 09:28:32.152087 RX Vref Scan: 0
8909 09:28:32.152169
8910 09:28:32.155039 RX Vref 0 -> 0, step: 1
8911 09:28:32.155121
8912 09:28:32.155185 RX Delay 0 -> 252, step: 8
8913 09:28:32.161633 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8914 09:28:32.165364 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8915 09:28:32.168345 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8916 09:28:32.171713 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8917 09:28:32.175062 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8918 09:28:32.182043 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8919 09:28:32.185250 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8920 09:28:32.188307 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8921 09:28:32.191908 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8922 09:28:32.195117 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8923 09:28:32.201924 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8924 09:28:32.205436 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8925 09:28:32.208292 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8926 09:28:32.211948 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8927 09:28:32.214988 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8928 09:28:32.222113 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8929 09:28:32.222247 ==
8930 09:28:32.225217 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 09:28:32.228337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 09:28:32.228433 ==
8933 09:28:32.228500 DQS Delay:
8934 09:28:32.232056 DQS0 = 0, DQS1 = 0
8935 09:28:32.232142 DQM Delay:
8936 09:28:32.234996 DQM0 = 132, DQM1 = 127
8937 09:28:32.235078 DQ Delay:
8938 09:28:32.238562 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8939 09:28:32.241723 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8940 09:28:32.244857 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8941 09:28:32.248345 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8942 09:28:32.248434
8943 09:28:32.248498
8944 09:28:32.251723 ==
8945 09:28:32.251805 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 09:28:32.258305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 09:28:32.258392 ==
8948 09:28:32.258456
8949 09:28:32.258514
8950 09:28:32.261973 TX Vref Scan disable
8951 09:28:32.262055 == TX Byte 0 ==
8952 09:28:32.264961 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8953 09:28:32.272091 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8954 09:28:32.272209 == TX Byte 1 ==
8955 09:28:32.275456 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8956 09:28:32.281904 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8957 09:28:32.282010 ==
8958 09:28:32.284928 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 09:28:32.288304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 09:28:32.288392 ==
8961 09:28:32.303376
8962 09:28:32.306504 TX Vref early break, caculate TX vref
8963 09:28:32.310059 TX Vref=16, minBit 8, minWin=22, winSum=375
8964 09:28:32.313759 TX Vref=18, minBit 0, minWin=23, winSum=384
8965 09:28:32.316608 TX Vref=20, minBit 1, minWin=23, winSum=390
8966 09:28:32.320281 TX Vref=22, minBit 5, minWin=24, winSum=397
8967 09:28:32.323269 TX Vref=24, minBit 0, minWin=25, winSum=408
8968 09:28:32.326830 TX Vref=26, minBit 0, minWin=25, winSum=416
8969 09:28:32.333771 TX Vref=28, minBit 5, minWin=25, winSum=418
8970 09:28:32.336973 TX Vref=30, minBit 0, minWin=24, winSum=419
8971 09:28:32.340150 TX Vref=32, minBit 0, minWin=25, winSum=413
8972 09:28:32.343442 TX Vref=34, minBit 3, minWin=24, winSum=402
8973 09:28:32.347160 TX Vref=36, minBit 0, minWin=24, winSum=400
8974 09:28:32.350039 TX Vref=38, minBit 0, minWin=23, winSum=391
8975 09:28:32.356691 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 28
8976 09:28:32.356878
8977 09:28:32.360405 Final TX Range 0 Vref 28
8978 09:28:32.360563
8979 09:28:32.360696 ==
8980 09:28:32.363848 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 09:28:32.367019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 09:28:32.367157 ==
8983 09:28:32.367280
8984 09:28:32.370270
8985 09:28:32.370399 TX Vref Scan disable
8986 09:28:32.377154 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8987 09:28:32.377287 == TX Byte 0 ==
8988 09:28:32.380336 u2DelayCellOfst[0]=17 cells (5 PI)
8989 09:28:32.383189 u2DelayCellOfst[1]=10 cells (3 PI)
8990 09:28:32.386614 u2DelayCellOfst[2]=0 cells (0 PI)
8991 09:28:32.390135 u2DelayCellOfst[3]=7 cells (2 PI)
8992 09:28:32.393171 u2DelayCellOfst[4]=10 cells (3 PI)
8993 09:28:32.396772 u2DelayCellOfst[5]=17 cells (5 PI)
8994 09:28:32.400095 u2DelayCellOfst[6]=17 cells (5 PI)
8995 09:28:32.403516 u2DelayCellOfst[7]=7 cells (2 PI)
8996 09:28:32.407308 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8997 09:28:32.410284 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8998 09:28:32.413088 == TX Byte 1 ==
8999 09:28:32.417020 u2DelayCellOfst[8]=0 cells (0 PI)
9000 09:28:32.417162 u2DelayCellOfst[9]=3 cells (1 PI)
9001 09:28:32.420395 u2DelayCellOfst[10]=10 cells (3 PI)
9002 09:28:32.423236 u2DelayCellOfst[11]=3 cells (1 PI)
9003 09:28:32.426456 u2DelayCellOfst[12]=14 cells (4 PI)
9004 09:28:32.429665 u2DelayCellOfst[13]=17 cells (5 PI)
9005 09:28:32.433560 u2DelayCellOfst[14]=17 cells (5 PI)
9006 09:28:32.436922 u2DelayCellOfst[15]=14 cells (4 PI)
9007 09:28:32.440000 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9008 09:28:32.446881 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9009 09:28:32.447026 DramC Write-DBI on
9010 09:28:32.447152 ==
9011 09:28:32.449972 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 09:28:32.456404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 09:28:32.456583 ==
9014 09:28:32.456721
9015 09:28:32.456847
9016 09:28:32.456972 TX Vref Scan disable
9017 09:28:32.460638 == TX Byte 0 ==
9018 09:28:32.463452 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9019 09:28:32.467244 == TX Byte 1 ==
9020 09:28:32.470291 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9021 09:28:32.473719 DramC Write-DBI off
9022 09:28:32.473852
9023 09:28:32.473972 [DATLAT]
9024 09:28:32.474094 Freq=1600, CH1 RK1
9025 09:28:32.474212
9026 09:28:32.477413 DATLAT Default: 0xf
9027 09:28:32.477546 0, 0xFFFF, sum = 0
9028 09:28:32.480267 1, 0xFFFF, sum = 0
9029 09:28:32.480402 2, 0xFFFF, sum = 0
9030 09:28:32.483899 3, 0xFFFF, sum = 0
9031 09:28:32.484055 4, 0xFFFF, sum = 0
9032 09:28:32.487123 5, 0xFFFF, sum = 0
9033 09:28:32.490667 6, 0xFFFF, sum = 0
9034 09:28:32.490817 7, 0xFFFF, sum = 0
9035 09:28:32.493715 8, 0xFFFF, sum = 0
9036 09:28:32.493852 9, 0xFFFF, sum = 0
9037 09:28:32.496919 10, 0xFFFF, sum = 0
9038 09:28:32.497056 11, 0xFFFF, sum = 0
9039 09:28:32.500430 12, 0xFFFF, sum = 0
9040 09:28:32.500567 13, 0xFFFF, sum = 0
9041 09:28:32.504268 14, 0x0, sum = 1
9042 09:28:32.504405 15, 0x0, sum = 2
9043 09:28:32.507338 16, 0x0, sum = 3
9044 09:28:32.507467 17, 0x0, sum = 4
9045 09:28:32.507585 best_step = 15
9046 09:28:32.510638
9047 09:28:32.510815 ==
9048 09:28:32.513960 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 09:28:32.517251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 09:28:32.517403 ==
9051 09:28:32.517532 RX Vref Scan: 0
9052 09:28:32.517656
9053 09:28:32.520987 RX Vref 0 -> 0, step: 1
9054 09:28:32.521128
9055 09:28:32.523752 RX Delay 11 -> 252, step: 4
9056 09:28:32.527331 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9057 09:28:32.530436 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9058 09:28:32.537233 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9059 09:28:32.541170 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9060 09:28:32.544418 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9061 09:28:32.547250 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9062 09:28:32.550826 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9063 09:28:32.557311 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9064 09:28:32.560904 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9065 09:28:32.563976 iDelay=195, Bit 9, Center 112 (55 ~ 170) 116
9066 09:28:32.567806 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9067 09:28:32.570875 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9068 09:28:32.577303 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9069 09:28:32.581111 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9070 09:28:32.584296 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9071 09:28:32.587645 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9072 09:28:32.587730 ==
9073 09:28:32.590919 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 09:28:32.597794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 09:28:32.597879 ==
9076 09:28:32.597944 DQS Delay:
9077 09:28:32.598004 DQS0 = 0, DQS1 = 0
9078 09:28:32.601101 DQM Delay:
9079 09:28:32.601183 DQM0 = 129, DQM1 = 126
9080 09:28:32.604062 DQ Delay:
9081 09:28:32.607737 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9082 09:28:32.610998 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
9083 09:28:32.614208 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9084 09:28:32.617900 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =136
9085 09:28:32.617986
9086 09:28:32.618050
9087 09:28:32.618109
9088 09:28:32.620916 [DramC_TX_OE_Calibration] TA2
9089 09:28:32.624333 Original DQ_B0 (3 6) =30, OEN = 27
9090 09:28:32.627642 Original DQ_B1 (3 6) =30, OEN = 27
9091 09:28:32.630607 24, 0x0, End_B0=24 End_B1=24
9092 09:28:32.630731 25, 0x0, End_B0=25 End_B1=25
9093 09:28:32.633867 26, 0x0, End_B0=26 End_B1=26
9094 09:28:32.637184 27, 0x0, End_B0=27 End_B1=27
9095 09:28:32.641144 28, 0x0, End_B0=28 End_B1=28
9096 09:28:32.641250 29, 0x0, End_B0=29 End_B1=29
9097 09:28:32.644073 30, 0x0, End_B0=30 End_B1=30
9098 09:28:32.647506 31, 0x4141, End_B0=30 End_B1=30
9099 09:28:32.650933 Byte0 end_step=30 best_step=27
9100 09:28:32.654057 Byte1 end_step=30 best_step=27
9101 09:28:32.657635 Byte0 TX OE(2T, 0.5T) = (3, 3)
9102 09:28:32.657847 Byte1 TX OE(2T, 0.5T) = (3, 3)
9103 09:28:32.657979
9104 09:28:32.658098
9105 09:28:32.667860 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9106 09:28:32.670675 CH1 RK1: MR19=303, MR18=1117
9107 09:28:32.677574 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9108 09:28:32.677779 [RxdqsGatingPostProcess] freq 1600
9109 09:28:32.684139 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9110 09:28:32.687609 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 09:28:32.691034 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 09:28:32.694450 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 09:28:32.697942 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 09:28:32.701248 best DQS0 dly(2T, 0.5T) = (1, 1)
9115 09:28:32.701366 best DQS1 dly(2T, 0.5T) = (1, 1)
9116 09:28:32.704570 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9117 09:28:32.707956 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9118 09:28:32.711406 Pre-setting of DQS Precalculation
9119 09:28:32.717697 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9120 09:28:32.724459 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9121 09:28:32.731021 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 09:28:32.731137
9123 09:28:32.731228
9124 09:28:32.734582 [Calibration Summary] 3200 Mbps
9125 09:28:32.734701 CH 0, Rank 0
9126 09:28:32.737983 SW Impedance : PASS
9127 09:28:32.741270 DUTY Scan : NO K
9128 09:28:32.741350 ZQ Calibration : PASS
9129 09:28:32.744598 Jitter Meter : NO K
9130 09:28:32.748215 CBT Training : PASS
9131 09:28:32.748295 Write leveling : PASS
9132 09:28:32.751259 RX DQS gating : PASS
9133 09:28:32.754565 RX DQ/DQS(RDDQC) : PASS
9134 09:28:32.754645 TX DQ/DQS : PASS
9135 09:28:32.757958 RX DATLAT : PASS
9136 09:28:32.761408 RX DQ/DQS(Engine): PASS
9137 09:28:32.761514 TX OE : PASS
9138 09:28:32.761606 All Pass.
9139 09:28:32.764911
9140 09:28:32.764990 CH 0, Rank 1
9141 09:28:32.767999 SW Impedance : PASS
9142 09:28:32.768079 DUTY Scan : NO K
9143 09:28:32.771232 ZQ Calibration : PASS
9144 09:28:32.771312 Jitter Meter : NO K
9145 09:28:32.774700 CBT Training : PASS
9146 09:28:32.777981 Write leveling : PASS
9147 09:28:32.778061 RX DQS gating : PASS
9148 09:28:32.781370 RX DQ/DQS(RDDQC) : PASS
9149 09:28:32.784672 TX DQ/DQS : PASS
9150 09:28:32.784752 RX DATLAT : PASS
9151 09:28:32.787989 RX DQ/DQS(Engine): PASS
9152 09:28:32.791530 TX OE : PASS
9153 09:28:32.791611 All Pass.
9154 09:28:32.791674
9155 09:28:32.791732 CH 1, Rank 0
9156 09:28:32.794605 SW Impedance : PASS
9157 09:28:32.798101 DUTY Scan : NO K
9158 09:28:32.798181 ZQ Calibration : PASS
9159 09:28:32.801298 Jitter Meter : NO K
9160 09:28:32.804836 CBT Training : PASS
9161 09:28:32.804916 Write leveling : PASS
9162 09:28:32.808113 RX DQS gating : PASS
9163 09:28:32.808193 RX DQ/DQS(RDDQC) : PASS
9164 09:28:32.811392 TX DQ/DQS : PASS
9165 09:28:32.814563 RX DATLAT : PASS
9166 09:28:32.814649 RX DQ/DQS(Engine): PASS
9167 09:28:32.818025 TX OE : PASS
9168 09:28:32.818110 All Pass.
9169 09:28:32.818196
9170 09:28:32.821559 CH 1, Rank 1
9171 09:28:32.821643 SW Impedance : PASS
9172 09:28:32.824985 DUTY Scan : NO K
9173 09:28:32.827907 ZQ Calibration : PASS
9174 09:28:32.827992 Jitter Meter : NO K
9175 09:28:32.831445 CBT Training : PASS
9176 09:28:32.834855 Write leveling : PASS
9177 09:28:32.834937 RX DQS gating : PASS
9178 09:28:32.837753 RX DQ/DQS(RDDQC) : PASS
9179 09:28:32.841309 TX DQ/DQS : PASS
9180 09:28:32.841391 RX DATLAT : PASS
9181 09:28:32.844507 RX DQ/DQS(Engine): PASS
9182 09:28:32.847917 TX OE : PASS
9183 09:28:32.848009 All Pass.
9184 09:28:32.848075
9185 09:28:32.848134 DramC Write-DBI on
9186 09:28:32.851382 PER_BANK_REFRESH: Hybrid Mode
9187 09:28:32.854703 TX_TRACKING: ON
9188 09:28:32.861524 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9189 09:28:32.871481 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9190 09:28:32.877887 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9191 09:28:32.881247 [FAST_K] Save calibration result to emmc
9192 09:28:32.884668 sync common calibartion params.
9193 09:28:32.884774 sync cbt_mode0:1, 1:1
9194 09:28:32.888049 dram_init: ddr_geometry: 2
9195 09:28:32.891322 dram_init: ddr_geometry: 2
9196 09:28:32.894446 dram_init: ddr_geometry: 2
9197 09:28:32.894526 0:dram_rank_size:100000000
9198 09:28:32.898013 1:dram_rank_size:100000000
9199 09:28:32.904823 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9200 09:28:32.904905 DFS_SHUFFLE_HW_MODE: ON
9201 09:28:32.911569 dramc_set_vcore_voltage set vcore to 725000
9202 09:28:32.911671 Read voltage for 1600, 0
9203 09:28:32.911738 Vio18 = 0
9204 09:28:32.914985 Vcore = 725000
9205 09:28:32.915066 Vdram = 0
9206 09:28:32.915129 Vddq = 0
9207 09:28:32.918334 Vmddr = 0
9208 09:28:32.918415 switch to 3200 Mbps bootup
9209 09:28:32.921584 [DramcRunTimeConfig]
9210 09:28:32.921665 PHYPLL
9211 09:28:32.924914 DPM_CONTROL_AFTERK: ON
9212 09:28:32.924995 PER_BANK_REFRESH: ON
9213 09:28:32.927964 REFRESH_OVERHEAD_REDUCTION: ON
9214 09:28:32.931330 CMD_PICG_NEW_MODE: OFF
9215 09:28:32.931410 XRTWTW_NEW_MODE: ON
9216 09:28:32.935043 XRTRTR_NEW_MODE: ON
9217 09:28:32.935124 TX_TRACKING: ON
9218 09:28:32.938114 RDSEL_TRACKING: OFF
9219 09:28:32.941296 DQS Precalculation for DVFS: ON
9220 09:28:32.941377 RX_TRACKING: OFF
9221 09:28:32.944520 HW_GATING DBG: ON
9222 09:28:32.944601 ZQCS_ENABLE_LP4: ON
9223 09:28:32.947929 RX_PICG_NEW_MODE: ON
9224 09:28:32.948009 TX_PICG_NEW_MODE: ON
9225 09:28:32.951197 ENABLE_RX_DCM_DPHY: ON
9226 09:28:32.954710 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9227 09:28:32.958115 DUMMY_READ_FOR_TRACKING: OFF
9228 09:28:32.958199 !!! SPM_CONTROL_AFTERK: OFF
9229 09:28:32.961356 !!! SPM could not control APHY
9230 09:28:32.964619 IMPEDANCE_TRACKING: ON
9231 09:28:32.964700 TEMP_SENSOR: ON
9232 09:28:32.968033 HW_SAVE_FOR_SR: OFF
9233 09:28:32.971722 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9234 09:28:32.974609 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9235 09:28:32.974690 Read ODT Tracking: ON
9236 09:28:32.978421 Refresh Rate DeBounce: ON
9237 09:28:32.981295 DFS_NO_QUEUE_FLUSH: ON
9238 09:28:32.984964 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9239 09:28:32.985050 ENABLE_DFS_RUNTIME_MRW: OFF
9240 09:28:32.988147 DDR_RESERVE_NEW_MODE: ON
9241 09:28:32.991586 MR_CBT_SWITCH_FREQ: ON
9242 09:28:32.991668 =========================
9243 09:28:33.012035 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9244 09:28:33.015358 dram_init: ddr_geometry: 2
9245 09:28:33.033422 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9246 09:28:33.036675 dram_init: dram init end (result: 0)
9247 09:28:33.043568 DRAM-K: Full calibration passed in 24603 msecs
9248 09:28:33.046897 MRC: failed to locate region type 0.
9249 09:28:33.046979 DRAM rank0 size:0x100000000,
9250 09:28:33.049965 DRAM rank1 size=0x100000000
9251 09:28:33.060286 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9252 09:28:33.067048 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9253 09:28:33.073307 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9254 09:28:33.080207 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9255 09:28:33.083696 DRAM rank0 size:0x100000000,
9256 09:28:33.086934 DRAM rank1 size=0x100000000
9257 09:28:33.087015 CBMEM:
9258 09:28:33.090223 IMD: root @ 0xfffff000 254 entries.
9259 09:28:33.093725 IMD: root @ 0xffffec00 62 entries.
9260 09:28:33.096931 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9261 09:28:33.100282 WARNING: RO_VPD is uninitialized or empty.
9262 09:28:33.107088 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9263 09:28:33.113267 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9264 09:28:33.126182 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9265 09:28:33.137853 BS: romstage times (exec / console): total (unknown) / 24101 ms
9266 09:28:33.137959
9267 09:28:33.138024
9268 09:28:33.147565 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9269 09:28:33.151205 ARM64: Exception handlers installed.
9270 09:28:33.154348 ARM64: Testing exception
9271 09:28:33.158038 ARM64: Done test exception
9272 09:28:33.158124 Enumerating buses...
9273 09:28:33.161154 Show all devs... Before device enumeration.
9274 09:28:33.164951 Root Device: enabled 1
9275 09:28:33.167654 CPU_CLUSTER: 0: enabled 1
9276 09:28:33.167735 CPU: 00: enabled 1
9277 09:28:33.170950 Compare with tree...
9278 09:28:33.171031 Root Device: enabled 1
9279 09:28:33.174853 CPU_CLUSTER: 0: enabled 1
9280 09:28:33.178061 CPU: 00: enabled 1
9281 09:28:33.178142 Root Device scanning...
9282 09:28:33.181532 scan_static_bus for Root Device
9283 09:28:33.184668 CPU_CLUSTER: 0 enabled
9284 09:28:33.188095 scan_static_bus for Root Device done
9285 09:28:33.191625 scan_bus: bus Root Device finished in 8 msecs
9286 09:28:33.191706 done
9287 09:28:33.198091 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9288 09:28:33.201331 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9289 09:28:33.204615 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9290 09:28:33.211642 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9291 09:28:33.214944 Allocating resources...
9292 09:28:33.215028 Reading resources...
9293 09:28:33.218259 Root Device read_resources bus 0 link: 0
9294 09:28:33.221671 DRAM rank0 size:0x100000000,
9295 09:28:33.225296 DRAM rank1 size=0x100000000
9296 09:28:33.227933 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9297 09:28:33.231215 CPU: 00 missing read_resources
9298 09:28:33.234874 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9299 09:28:33.238406 Root Device read_resources bus 0 link: 0 done
9300 09:28:33.241339 Done reading resources.
9301 09:28:33.248103 Show resources in subtree (Root Device)...After reading.
9302 09:28:33.251786 Root Device child on link 0 CPU_CLUSTER: 0
9303 09:28:33.254500 CPU_CLUSTER: 0 child on link 0 CPU: 00
9304 09:28:33.261070 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9305 09:28:33.264783 CPU: 00
9306 09:28:33.267963 Root Device assign_resources, bus 0 link: 0
9307 09:28:33.271360 CPU_CLUSTER: 0 missing set_resources
9308 09:28:33.274569 Root Device assign_resources, bus 0 link: 0 done
9309 09:28:33.277844 Done setting resources.
9310 09:28:33.284750 Show resources in subtree (Root Device)...After assigning values.
9311 09:28:33.288433 Root Device child on link 0 CPU_CLUSTER: 0
9312 09:28:33.291217 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 09:28:33.301380 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 09:28:33.301465 CPU: 00
9315 09:28:33.304999 Done allocating resources.
9316 09:28:33.307822 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9317 09:28:33.311146 Enabling resources...
9318 09:28:33.311227 done.
9319 09:28:33.315005 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9320 09:28:33.317884 Initializing devices...
9321 09:28:33.317966 Root Device init
9322 09:28:33.321860 init hardware done!
9323 09:28:33.324638 0x00000018: ctrlr->caps
9324 09:28:33.324722 52.000 MHz: ctrlr->f_max
9325 09:28:33.328028 0.400 MHz: ctrlr->f_min
9326 09:28:33.331205 0x40ff8080: ctrlr->voltages
9327 09:28:33.331288 sclk: 390625
9328 09:28:33.331352 Bus Width = 1
9329 09:28:33.334575 sclk: 390625
9330 09:28:33.334656 Bus Width = 1
9331 09:28:33.338255 Early init status = 3
9332 09:28:33.341652 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9333 09:28:33.346227 in-header: 03 fc 00 00 01 00 00 00
9334 09:28:33.349195 in-data: 00
9335 09:28:33.352619 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9336 09:28:33.358432 in-header: 03 fd 00 00 00 00 00 00
9337 09:28:33.361597 in-data:
9338 09:28:33.364672 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9339 09:28:33.369069 in-header: 03 fc 00 00 01 00 00 00
9340 09:28:33.372656 in-data: 00
9341 09:28:33.375933 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9342 09:28:33.381462 in-header: 03 fd 00 00 00 00 00 00
9343 09:28:33.385120 in-data:
9344 09:28:33.388199 [SSUSB] Setting up USB HOST controller...
9345 09:28:33.391338 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9346 09:28:33.395145 [SSUSB] phy power-on done.
9347 09:28:33.398451 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9348 09:28:33.405036 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9349 09:28:33.408614 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9350 09:28:33.415142 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9351 09:28:33.421800 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9352 09:28:33.428252 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9353 09:28:33.434626 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9354 09:28:33.441428 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9355 09:28:33.441549 SPM: binary array size = 0x9dc
9356 09:28:33.448428 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9357 09:28:33.454947 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9358 09:28:33.461736 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9359 09:28:33.464864 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9360 09:28:33.468099 configure_display: Starting display init
9361 09:28:33.504469 anx7625_power_on_init: Init interface.
9362 09:28:33.507919 anx7625_disable_pd_protocol: Disabled PD feature.
9363 09:28:33.511349 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9364 09:28:33.539038 anx7625_start_dp_work: Secure OCM version=00
9365 09:28:33.542643 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9366 09:28:33.557552 sp_tx_get_edid_block: EDID Block = 1
9367 09:28:33.660358 Extracted contents:
9368 09:28:33.663339 header: 00 ff ff ff ff ff ff 00
9369 09:28:33.666208 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9370 09:28:33.669665 version: 01 04
9371 09:28:33.672886 basic params: 95 1f 11 78 0a
9372 09:28:33.676190 chroma info: 76 90 94 55 54 90 27 21 50 54
9373 09:28:33.679642 established: 00 00 00
9374 09:28:33.686153 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9375 09:28:33.689894 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9376 09:28:33.696326 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 09:28:33.703264 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9378 09:28:33.709610 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9379 09:28:33.712702 extensions: 00
9380 09:28:33.712844 checksum: fb
9381 09:28:33.712920
9382 09:28:33.716443 Manufacturer: IVO Model 57d Serial Number 0
9383 09:28:33.719873 Made week 0 of 2020
9384 09:28:33.719966 EDID version: 1.4
9385 09:28:33.723450 Digital display
9386 09:28:33.726660 6 bits per primary color channel
9387 09:28:33.726803 DisplayPort interface
9388 09:28:33.729883 Maximum image size: 31 cm x 17 cm
9389 09:28:33.729973 Gamma: 220%
9390 09:28:33.733026 Check DPMS levels
9391 09:28:33.736800 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9392 09:28:33.739705 First detailed timing is preferred timing
9393 09:28:33.743327 Established timings supported:
9394 09:28:33.746258 Standard timings supported:
9395 09:28:33.746360 Detailed timings
9396 09:28:33.753265 Hex of detail: 383680a07038204018303c0035ae10000019
9397 09:28:33.756601 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9398 09:28:33.759819 0780 0798 07c8 0820 hborder 0
9399 09:28:33.766121 0438 043b 0447 0458 vborder 0
9400 09:28:33.766254 -hsync -vsync
9401 09:28:33.769600 Did detailed timing
9402 09:28:33.772881 Hex of detail: 000000000000000000000000000000000000
9403 09:28:33.776418 Manufacturer-specified data, tag 0
9404 09:28:33.783087 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9405 09:28:33.783185 ASCII string: InfoVision
9406 09:28:33.790036 Hex of detail: 000000fe00523134304e574635205248200a
9407 09:28:33.790139 ASCII string: R140NWF5 RH
9408 09:28:33.792861 Checksum
9409 09:28:33.792952 Checksum: 0xfb (valid)
9410 09:28:33.799428 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9411 09:28:33.799523 DSI data_rate: 832800000 bps
9412 09:28:33.807883 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9413 09:28:33.811148 anx7625_parse_edid: pixelclock(138800).
9414 09:28:33.814432 hactive(1920), hsync(48), hfp(24), hbp(88)
9415 09:28:33.817379 vactive(1080), vsync(12), vfp(3), vbp(17)
9416 09:28:33.820737 anx7625_dsi_config: config dsi.
9417 09:28:33.827759 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9418 09:28:33.841690 anx7625_dsi_config: success to config DSI
9419 09:28:33.845431 anx7625_dp_start: MIPI phy setup OK.
9420 09:28:33.848387 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9421 09:28:33.851831 mtk_ddp_mode_set invalid vrefresh 60
9422 09:28:33.855051 main_disp_path_setup
9423 09:28:33.855149 ovl_layer_smi_id_en
9424 09:28:33.858622 ovl_layer_smi_id_en
9425 09:28:33.858716 ccorr_config
9426 09:28:33.858806 aal_config
9427 09:28:33.861954 gamma_config
9428 09:28:33.862036 postmask_config
9429 09:28:33.865248 dither_config
9430 09:28:33.868833 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9431 09:28:33.875232 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9432 09:28:33.878615 Root Device init finished in 555 msecs
9433 09:28:33.878705 CPU_CLUSTER: 0 init
9434 09:28:33.888770 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9435 09:28:33.891868 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9436 09:28:33.895009 APU_MBOX 0x190000b0 = 0x10001
9437 09:28:33.898621 APU_MBOX 0x190001b0 = 0x10001
9438 09:28:33.901746 APU_MBOX 0x190005b0 = 0x10001
9439 09:28:33.905385 APU_MBOX 0x190006b0 = 0x10001
9440 09:28:33.908350 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9441 09:28:33.920614 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9442 09:28:33.933481 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9443 09:28:33.939883 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9444 09:28:33.951196 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9445 09:28:33.960867 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9446 09:28:33.963878 CPU_CLUSTER: 0 init finished in 81 msecs
9447 09:28:33.967300 Devices initialized
9448 09:28:33.970576 Show all devs... After init.
9449 09:28:33.970659 Root Device: enabled 1
9450 09:28:33.974390 CPU_CLUSTER: 0: enabled 1
9451 09:28:33.977177 CPU: 00: enabled 1
9452 09:28:33.980899 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9453 09:28:33.984113 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9454 09:28:33.987607 ELOG: NV offset 0x57f000 size 0x1000
9455 09:28:33.994524 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9456 09:28:34.001012 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9457 09:28:34.004093 ELOG: Event(17) added with size 13 at 2023-10-20 09:28:35 UTC
9458 09:28:34.007324 out: cmd=0x121: 03 db 21 01 00 00 00 00
9459 09:28:34.011144 in-header: 03 be 00 00 2c 00 00 00
9460 09:28:34.024533 in-data: a1 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9461 09:28:34.030839 ELOG: Event(A1) added with size 10 at 2023-10-20 09:28:35 UTC
9462 09:28:34.037801 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9463 09:28:34.041048 ELOG: Event(A0) added with size 9 at 2023-10-20 09:28:35 UTC
9464 09:28:34.047951 elog_add_boot_reason: Logged dev mode boot
9465 09:28:34.051221 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9466 09:28:34.054659 Finalize devices...
9467 09:28:34.054824 Devices finalized
9468 09:28:34.061191 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9469 09:28:34.064472 Writing coreboot table at 0xffe64000
9470 09:28:34.067734 0. 000000000010a000-0000000000113fff: RAMSTAGE
9471 09:28:34.071899 1. 0000000040000000-00000000400fffff: RAM
9472 09:28:34.074779 2. 0000000040100000-000000004032afff: RAMSTAGE
9473 09:28:34.078356 3. 000000004032b000-00000000545fffff: RAM
9474 09:28:34.084564 4. 0000000054600000-000000005465ffff: BL31
9475 09:28:34.087991 5. 0000000054660000-00000000ffe63fff: RAM
9476 09:28:34.091744 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9477 09:28:34.094727 7. 0000000100000000-000000023fffffff: RAM
9478 09:28:34.098111 Passing 5 GPIOs to payload:
9479 09:28:34.105548 NAME | PORT | POLARITY | VALUE
9480 09:28:34.108229 EC in RW | 0x000000aa | low | undefined
9481 09:28:34.111731 EC interrupt | 0x00000005 | low | undefined
9482 09:28:34.118505 TPM interrupt | 0x000000ab | high | undefined
9483 09:28:34.121684 SD card detect | 0x00000011 | high | undefined
9484 09:28:34.128471 speaker enable | 0x00000093 | high | undefined
9485 09:28:34.131642 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9486 09:28:34.134986 in-header: 03 f9 00 00 02 00 00 00
9487 09:28:34.135081 in-data: 02 00
9488 09:28:34.138284 ADC[4]: Raw value=899852 ID=7
9489 09:28:34.141624 ADC[3]: Raw value=213336 ID=1
9490 09:28:34.141779 RAM Code: 0x71
9491 09:28:34.145044 ADC[6]: Raw value=74926 ID=0
9492 09:28:34.148391 ADC[5]: Raw value=212229 ID=1
9493 09:28:34.148488 SKU Code: 0x1
9494 09:28:34.154913 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b061
9495 09:28:34.158406 coreboot table: 964 bytes.
9496 09:28:34.158540 IMD ROOT 0. 0xfffff000 0x00001000
9497 09:28:34.164547 IMD SMALL 1. 0xffffe000 0x00001000
9498 09:28:34.164672 RO MCACHE 2. 0xffffc000 0x00001104
9499 09:28:34.168257 CONSOLE 3. 0xfff7c000 0x00080000
9500 09:28:34.171611 FMAP 4. 0xfff7b000 0x00000452
9501 09:28:34.174713 TIME STAMP 5. 0xfff7a000 0x00000910
9502 09:28:34.178500 VBOOT WORK 6. 0xfff66000 0x00014000
9503 09:28:34.181842 RAMOOPS 7. 0xffe66000 0x00100000
9504 09:28:34.184727 COREBOOT 8. 0xffe64000 0x00002000
9505 09:28:34.188288 IMD small region:
9506 09:28:34.191338 IMD ROOT 0. 0xffffec00 0x00000400
9507 09:28:34.194656 VPD 1. 0xffffeb80 0x0000006c
9508 09:28:34.197944 MMC STATUS 2. 0xffffeb60 0x00000004
9509 09:28:34.204868 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9510 09:28:34.204979 Probing TPM: done!
9511 09:28:34.208536 Connected to device vid:did:rid of 1ae0:0028:00
9512 09:28:34.219772 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9513 09:28:34.223527 Initialized TPM device CR50 revision 0
9514 09:28:34.226957 Checking cr50 for pending updates
9515 09:28:34.230227 Reading cr50 TPM mode
9516 09:28:34.239307 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9517 09:28:34.245602 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9518 09:28:34.285580 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9519 09:28:34.289495 Checking segment from ROM address 0x40100000
9520 09:28:34.292388 Checking segment from ROM address 0x4010001c
9521 09:28:34.299170 Loading segment from ROM address 0x40100000
9522 09:28:34.299265 code (compression=0)
9523 09:28:34.305865 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9524 09:28:34.315946 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9525 09:28:34.316052 it's not compressed!
9526 09:28:34.323199 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9527 09:28:34.325841 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9528 09:28:34.346158 Loading segment from ROM address 0x4010001c
9529 09:28:34.346281 Entry Point 0x80000000
9530 09:28:34.349398 Loaded segments
9531 09:28:34.353058 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9532 09:28:34.359471 Jumping to boot code at 0x80000000(0xffe64000)
9533 09:28:34.366231 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9534 09:28:34.373034 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9535 09:28:34.380601 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9536 09:28:34.383867 Checking segment from ROM address 0x40100000
9537 09:28:34.387559 Checking segment from ROM address 0x4010001c
9538 09:28:34.394666 Loading segment from ROM address 0x40100000
9539 09:28:34.394810 code (compression=1)
9540 09:28:34.400904 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9541 09:28:34.411106 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9542 09:28:34.411235 using LZMA
9543 09:28:34.419409 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9544 09:28:34.425805 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9545 09:28:34.429623 Loading segment from ROM address 0x4010001c
9546 09:28:34.429723 Entry Point 0x54601000
9547 09:28:34.432740 Loaded segments
9548 09:28:34.435812 NOTICE: MT8192 bl31_setup
9549 09:28:34.442501 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9550 09:28:34.445967 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9551 09:28:34.449386 WARNING: region 0:
9552 09:28:34.452870 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 09:28:34.452976 WARNING: region 1:
9554 09:28:34.459490 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9555 09:28:34.462696 WARNING: region 2:
9556 09:28:34.466244 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9557 09:28:34.469563 WARNING: region 3:
9558 09:28:34.473009 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9559 09:28:34.476609 WARNING: region 4:
9560 09:28:34.479362 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 09:28:34.483050 WARNING: region 5:
9562 09:28:34.486475 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 09:28:34.489533 WARNING: region 6:
9564 09:28:34.493242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 09:28:34.493342 WARNING: region 7:
9566 09:28:34.499821 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 09:28:34.506208 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9568 09:28:34.509572 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9569 09:28:34.513127 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9570 09:28:34.516163 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9571 09:28:34.523316 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9572 09:28:34.526883 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9573 09:28:34.533360 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9574 09:28:34.536478 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9575 09:28:34.539951 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9576 09:28:34.546535 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9577 09:28:34.549966 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9578 09:28:34.553741 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9579 09:28:34.560277 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9580 09:28:34.563333 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9581 09:28:34.570168 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9582 09:28:34.573456 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9583 09:28:34.576671 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9584 09:28:34.583424 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9585 09:28:34.586917 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9586 09:28:34.590227 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9587 09:28:34.596745 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9588 09:28:34.600147 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9589 09:28:34.603822 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9590 09:28:34.610632 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9591 09:28:34.614072 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9592 09:28:34.620503 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9593 09:28:34.623804 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9594 09:28:34.627168 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9595 09:28:34.634133 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9596 09:28:34.637363 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9597 09:28:34.644057 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9598 09:28:34.647531 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9599 09:28:34.651010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9600 09:28:34.654222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9601 09:28:34.660975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9602 09:28:34.664131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9603 09:28:34.667620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9604 09:28:34.670829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9605 09:28:34.674496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9606 09:28:34.681196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9607 09:28:34.684640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9608 09:28:34.687897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9609 09:28:34.691704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9610 09:28:34.697946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9611 09:28:34.701077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9612 09:28:34.704777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9613 09:28:34.707969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9614 09:28:34.714554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9615 09:28:34.717958 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9616 09:28:34.721564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9617 09:28:34.728255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9618 09:28:34.731491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9619 09:28:34.738599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9620 09:28:34.741666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9621 09:28:34.747963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9622 09:28:34.751660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9623 09:28:34.755250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9624 09:28:34.761722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9625 09:28:34.764723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9626 09:28:34.772188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9627 09:28:34.774859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9628 09:28:34.781642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9629 09:28:34.784775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9630 09:28:34.791452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9631 09:28:34.795019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9632 09:28:34.798108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9633 09:28:34.804878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9634 09:28:34.808656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9635 09:28:34.814821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9636 09:28:34.818517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9637 09:28:34.821903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9638 09:28:34.828413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9639 09:28:34.831837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9640 09:28:34.838734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9641 09:28:34.842097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9642 09:28:34.848893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9643 09:28:34.852412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9644 09:28:34.855360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9645 09:28:34.861991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9646 09:28:34.865699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9647 09:28:34.872064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9648 09:28:34.875310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9649 09:28:34.882260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9650 09:28:34.885607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9651 09:28:34.889321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9652 09:28:34.895599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9653 09:28:34.898808 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9654 09:28:34.905666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9655 09:28:34.909429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9656 09:28:34.912041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9657 09:28:34.919397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9658 09:28:34.922308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9659 09:28:34.929227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9660 09:28:34.932528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9661 09:28:34.939041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9662 09:28:34.942618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9663 09:28:34.946115 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9664 09:28:34.952336 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9665 09:28:34.956169 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9666 09:28:34.959420 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9667 09:28:34.962914 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9668 09:28:34.969498 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9669 09:28:34.972818 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9670 09:28:34.976208 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9671 09:28:34.982733 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9672 09:28:34.985958 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9673 09:28:34.992941 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9674 09:28:34.996509 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9675 09:28:34.999847 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9676 09:28:35.006288 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9677 09:28:35.009881 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9678 09:28:35.013441 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9679 09:28:35.020348 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9680 09:28:35.023561 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9681 09:28:35.030128 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9682 09:28:35.033422 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9683 09:28:35.036782 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9684 09:28:35.040066 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9685 09:28:35.046742 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9686 09:28:35.049999 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9687 09:28:35.053252 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9688 09:28:35.056885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9689 09:28:35.063337 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9690 09:28:35.066639 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9691 09:28:35.070232 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9692 09:28:35.077163 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9693 09:28:35.080564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9694 09:28:35.087620 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9695 09:28:35.090488 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9696 09:28:35.093782 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9697 09:28:35.100621 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9698 09:28:35.104126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9699 09:28:35.107256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9700 09:28:35.114060 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9701 09:28:35.117532 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9702 09:28:35.124244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9703 09:28:35.127008 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9704 09:28:35.130461 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9705 09:28:35.137503 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9706 09:28:35.141032 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9707 09:28:35.144268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9708 09:28:35.150917 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9709 09:28:35.154000 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9710 09:28:35.161094 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9711 09:28:35.164485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9712 09:28:35.167587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9713 09:28:35.174820 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9714 09:28:35.178532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9715 09:28:35.181225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9716 09:28:35.187912 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9717 09:28:35.191199 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9718 09:28:35.194486 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9719 09:28:35.201609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9720 09:28:35.205112 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9721 09:28:35.211647 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9722 09:28:35.215103 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9723 09:28:35.218200 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9724 09:28:35.224854 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9725 09:28:35.228194 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9726 09:28:35.231461 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9727 09:28:35.238321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9728 09:28:35.242050 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9729 09:28:35.248855 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9730 09:28:35.252191 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9731 09:28:35.255075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9732 09:28:35.261801 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9733 09:28:35.265435 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9734 09:28:35.268803 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9735 09:28:35.275446 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9736 09:28:35.278616 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9737 09:28:35.285390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9738 09:28:35.288390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9739 09:28:35.291743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9740 09:28:35.298660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9741 09:28:35.301891 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9742 09:28:35.308588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9743 09:28:35.311831 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9744 09:28:35.315199 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9745 09:28:35.321370 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9746 09:28:35.325034 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9747 09:28:35.328445 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9748 09:28:35.334860 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9749 09:28:35.338479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9750 09:28:35.345402 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9751 09:28:35.348150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9752 09:28:35.352041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9753 09:28:35.358248 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9754 09:28:35.361798 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9755 09:28:35.368698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9756 09:28:35.371691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9757 09:28:35.375081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9758 09:28:35.381719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9759 09:28:35.384912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9760 09:28:35.391447 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9761 09:28:35.395091 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9762 09:28:35.398254 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9763 09:28:35.404773 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9764 09:28:35.408622 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9765 09:28:35.414798 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9766 09:28:35.418563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9767 09:28:35.425146 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9768 09:28:35.428223 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9769 09:28:35.431843 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9770 09:28:35.438401 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9771 09:28:35.441471 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9772 09:28:35.448388 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9773 09:28:35.451875 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9774 09:28:35.454873 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9775 09:28:35.461919 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9776 09:28:35.465377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9777 09:28:35.471896 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9778 09:28:35.475074 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9779 09:28:35.478421 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9780 09:28:35.485498 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9781 09:28:35.488716 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9782 09:28:35.495109 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9783 09:28:35.498290 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9784 09:28:35.504959 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9785 09:28:35.508279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9786 09:28:35.512049 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9787 09:28:35.518834 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9788 09:28:35.522060 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9789 09:28:35.528238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9790 09:28:35.531640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9791 09:28:35.535386 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9792 09:28:35.542009 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9793 09:28:35.545298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9794 09:28:35.551932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9795 09:28:35.555246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9796 09:28:35.558431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9797 09:28:35.561492 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9798 09:28:35.568210 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9799 09:28:35.571559 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9800 09:28:35.574925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9801 09:28:35.578630 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9802 09:28:35.585261 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9803 09:28:35.588700 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9804 09:28:35.595546 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9805 09:28:35.598748 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9806 09:28:35.602249 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9807 09:28:35.608705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9808 09:28:35.611956 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9809 09:28:35.615477 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9810 09:28:35.621972 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9811 09:28:35.625116 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9812 09:28:35.628656 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9813 09:28:35.635583 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9814 09:28:35.638751 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9815 09:28:35.641982 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9816 09:28:35.648907 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9817 09:28:35.652226 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9818 09:28:35.659096 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9819 09:28:35.661966 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9820 09:28:35.665332 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9821 09:28:35.672388 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9822 09:28:35.675984 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9823 09:28:35.679166 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9824 09:28:35.685612 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9825 09:28:35.688766 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9826 09:28:35.692047 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9827 09:28:35.699388 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9828 09:28:35.702587 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9829 09:28:35.705868 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9830 09:28:35.712493 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9831 09:28:35.716065 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9832 09:28:35.719194 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9833 09:28:35.725825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9834 09:28:35.729111 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9835 09:28:35.732325 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9836 09:28:35.739148 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9837 09:28:35.742268 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9838 09:28:35.745533 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9839 09:28:35.749033 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9840 09:28:35.752175 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9841 09:28:35.758889 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9842 09:28:35.762225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9843 09:28:35.765700 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9844 09:28:35.772221 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9845 09:28:35.775568 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9846 09:28:35.778991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9847 09:28:35.782194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9848 09:28:35.789466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9849 09:28:35.792615 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9850 09:28:35.796037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9851 09:28:35.802644 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9852 09:28:35.806017 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9853 09:28:35.812491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9854 09:28:35.815696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9855 09:28:35.822516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9856 09:28:35.826051 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9857 09:28:35.829608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9858 09:28:35.835871 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9859 09:28:35.839113 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9860 09:28:35.842447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9861 09:28:35.849592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9862 09:28:35.852421 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9863 09:28:35.859493 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9864 09:28:35.862495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9865 09:28:35.865734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9866 09:28:35.872727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9867 09:28:35.876070 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9868 09:28:35.882341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9869 09:28:35.885906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9870 09:28:35.889366 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9871 09:28:35.896421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9872 09:28:35.899862 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9873 09:28:35.906066 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9874 09:28:35.909242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9875 09:28:35.912578 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9876 09:28:35.919536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9877 09:28:35.922950 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9878 09:28:35.929536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9879 09:28:35.932608 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9880 09:28:35.936018 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9881 09:28:35.942664 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9882 09:28:35.946128 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9883 09:28:35.953148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9884 09:28:35.956552 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9885 09:28:35.959303 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9886 09:28:35.966591 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9887 09:28:35.969963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9888 09:28:35.976073 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9889 09:28:35.979373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9890 09:28:35.983000 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9891 09:28:35.989695 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9892 09:28:35.993091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9893 09:28:35.999716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9894 09:28:36.003151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9895 09:28:36.006573 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9896 09:28:36.013143 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9897 09:28:36.016636 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9898 09:28:36.022754 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9899 09:28:36.026654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9900 09:28:36.029917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9901 09:28:36.036521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9902 09:28:37.494920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9903 09:28:37.496025 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9904 09:28:37.496457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9905 09:28:37.496961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9906 09:28:37.497294 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9907 09:28:37.497632 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9908 09:28:37.497939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9909 09:28:37.498228 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9910 09:28:37.498515 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9911 09:28:37.498995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9912 09:28:37.499333 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9913 09:28:37.499535 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9914 09:28:37.499591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9915 09:28:37.499674 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9916 09:28:37.499732 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9917 09:28:37.499800 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9918 09:28:37.499870 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9919 09:28:37.499925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9920 09:28:37.500002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9921 09:28:37.500058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9922 09:28:37.500113 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9923 09:28:37.500199 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9924 09:28:37.500255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9925 09:28:37.500319 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9926 09:28:37.500387 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9927 09:28:37.500443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9928 09:28:37.500514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9929 09:28:37.500579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9930 09:28:37.500634 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9931 09:28:37.500720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9932 09:28:37.500806 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9933 09:28:37.500901 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9934 09:28:37.500987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9935 09:28:37.501083 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9936 09:28:37.501168 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9937 09:28:37.501254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9938 09:28:37.501336 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9939 09:28:37.501392 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9940 09:28:37.501449 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9941 09:28:37.501520 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9942 09:28:37.501575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9943 09:28:37.501629 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9944 09:28:37.501701 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9945 09:28:37.501764 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9946 09:28:37.501818 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9947 09:28:37.501899 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9948 09:28:37.501955 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9949 09:28:37.502037 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9950 09:28:37.502095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9951 09:28:37.502164 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9952 09:28:37.502226 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9953 09:28:37.502282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9954 09:28:37.502375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9955 09:28:37.502470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9956 09:28:37.502564 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9957 09:28:37.502662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9958 09:28:37.502760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9959 09:28:37.502857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9960 09:28:37.502950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9961 09:28:37.503009 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9962 09:28:37.503064 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9963 09:28:37.503145 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9964 09:28:37.503202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9965 09:28:37.503260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9966 09:28:37.503339 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9967 09:28:37.503394 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9968 09:28:37.503478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9969 09:28:37.503534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9970 09:28:37.503609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9971 09:28:37.503666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9972 09:28:37.503746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9973 09:28:37.503833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9974 09:28:37.503928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9975 09:28:37.504015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9976 09:28:37.504111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9977 09:28:37.504433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9978 09:28:37.504498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9979 09:28:37.504562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9980 09:28:37.504637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9981 09:28:37.504696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9982 09:28:37.504780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9983 09:28:37.504836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9984 09:28:37.504912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9985 09:28:37.504968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9986 09:28:37.505023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9987 09:28:37.505107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9988 09:28:37.505162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9989 09:28:37.505216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9990 09:28:37.505286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9991 09:28:37.505348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9992 09:28:37.505428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9993 09:28:37.505485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9994 09:28:37.505567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9995 09:28:37.505665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9996 09:28:37.505760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9997 09:28:37.505862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9998 09:28:37.506013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9999 09:28:37.506110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10000 09:28:37.506192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10001 09:28:37.506274 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10002 09:28:37.506402 INFO: [APUAPC] vio 0
10003 09:28:37.506526 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10004 09:28:37.506624 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10005 09:28:37.506707 INFO: [APUAPC] D0_APC_0: 0x400510
10006 09:28:37.506778 INFO: [APUAPC] D0_APC_1: 0x0
10007 09:28:37.506832 INFO: [APUAPC] D0_APC_2: 0x1540
10008 09:28:37.506886 INFO: [APUAPC] D0_APC_3: 0x0
10009 09:28:37.506940 INFO: [APUAPC] D1_APC_0: 0xffffffff
10010 09:28:37.506993 INFO: [APUAPC] D1_APC_1: 0xffffffff
10011 09:28:37.507047 INFO: [APUAPC] D1_APC_2: 0x3fffff
10012 09:28:37.507100 INFO: [APUAPC] D1_APC_3: 0x0
10013 09:28:37.507153 INFO: [APUAPC] D2_APC_0: 0xffffffff
10014 09:28:37.507206 INFO: [APUAPC] D2_APC_1: 0xffffffff
10015 09:28:37.507259 INFO: [APUAPC] D2_APC_2: 0x3fffff
10016 09:28:37.507311 INFO: [APUAPC] D2_APC_3: 0x0
10017 09:28:37.507365 INFO: [APUAPC] D3_APC_0: 0xffffffff
10018 09:28:37.507418 INFO: [APUAPC] D3_APC_1: 0xffffffff
10019 09:28:37.507470 INFO: [APUAPC] D3_APC_2: 0x3fffff
10020 09:28:37.507523 INFO: [APUAPC] D3_APC_3: 0x0
10021 09:28:37.507576 INFO: [APUAPC] D4_APC_0: 0xffffffff
10022 09:28:37.507629 INFO: [APUAPC] D4_APC_1: 0xffffffff
10023 09:28:37.507681 INFO: [APUAPC] D4_APC_2: 0x3fffff
10024 09:28:37.507734 INFO: [APUAPC] D4_APC_3: 0x0
10025 09:28:37.507787 INFO: [APUAPC] D5_APC_0: 0xffffffff
10026 09:28:37.507839 INFO: [APUAPC] D5_APC_1: 0xffffffff
10027 09:28:37.507892 INFO: [APUAPC] D5_APC_2: 0x3fffff
10028 09:28:37.507945 INFO: [APUAPC] D5_APC_3: 0x0
10029 09:28:37.507998 INFO: [APUAPC] D6_APC_0: 0xffffffff
10030 09:28:37.508050 INFO: [APUAPC] D6_APC_1: 0xffffffff
10031 09:28:37.508103 INFO: [APUAPC] D6_APC_2: 0x3fffff
10032 09:28:37.508156 INFO: [APUAPC] D6_APC_3: 0x0
10033 09:28:37.508209 INFO: [APUAPC] D7_APC_0: 0xffffffff
10034 09:28:37.508261 INFO: [APUAPC] D7_APC_1: 0xffffffff
10035 09:28:37.508314 INFO: [APUAPC] D7_APC_2: 0x3fffff
10036 09:28:37.508366 INFO: [APUAPC] D7_APC_3: 0x0
10037 09:28:37.508420 INFO: [APUAPC] D8_APC_0: 0xffffffff
10038 09:28:37.508472 INFO: [APUAPC] D8_APC_1: 0xffffffff
10039 09:28:37.508525 INFO: [APUAPC] D8_APC_2: 0x3fffff
10040 09:28:37.508577 INFO: [APUAPC] D8_APC_3: 0x0
10041 09:28:37.508660 INFO: [APUAPC] D9_APC_0: 0xffffffff
10042 09:28:37.508749 INFO: [APUAPC] D9_APC_1: 0xffffffff
10043 09:28:37.508833 INFO: [APUAPC] D9_APC_2: 0x3fffff
10044 09:28:37.508914 INFO: [APUAPC] D9_APC_3: 0x0
10045 09:28:37.508985 INFO: [APUAPC] D10_APC_0: 0xffffffff
10046 09:28:37.509049 INFO: [APUAPC] D10_APC_1: 0xffffffff
10047 09:28:37.509145 INFO: [APUAPC] D10_APC_2: 0x3fffff
10048 09:28:37.509241 INFO: [APUAPC] D10_APC_3: 0x0
10049 09:28:37.509337 INFO: [APUAPC] D11_APC_0: 0xffffffff
10050 09:28:37.509429 INFO: [APUAPC] D11_APC_1: 0xffffffff
10051 09:28:37.509525 INFO: [APUAPC] D11_APC_2: 0x3fffff
10052 09:28:37.509621 INFO: [APUAPC] D11_APC_3: 0x0
10053 09:28:37.509717 INFO: [APUAPC] D12_APC_0: 0xffffffff
10054 09:28:37.509810 INFO: [APUAPC] D12_APC_1: 0xffffffff
10055 09:28:37.509909 INFO: [APUAPC] D12_APC_2: 0x3fffff
10056 09:28:37.510004 INFO: [APUAPC] D12_APC_3: 0x0
10057 09:28:37.510102 INFO: [APUAPC] D13_APC_0: 0xffffffff
10058 09:28:37.510192 INFO: [APUAPC] D13_APC_1: 0xffffffff
10059 09:28:37.510285 INFO: [APUAPC] D13_APC_2: 0x3fffff
10060 09:28:37.510383 INFO: [APUAPC] D13_APC_3: 0x0
10061 09:28:37.510478 INFO: [APUAPC] D14_APC_0: 0xffffffff
10062 09:28:37.510582 INFO: [APUAPC] D14_APC_1: 0xffffffff
10063 09:28:37.510681 INFO: [APUAPC] D14_APC_2: 0x3fffff
10064 09:28:37.510785 INFO: [APUAPC] D14_APC_3: 0x0
10065 09:28:37.510882 INFO: [APUAPC] D15_APC_0: 0xffffffff
10066 09:28:37.510978 INFO: [APUAPC] D15_APC_1: 0xffffffff
10067 09:28:37.511075 INFO: [APUAPC] D15_APC_2: 0x3fffff
10068 09:28:37.511168 INFO: [APUAPC] D15_APC_3: 0x0
10069 09:28:37.511263 INFO: [APUAPC] APC_CON: 0x4
10070 09:28:37.511354 INFO: [NOCDAPC] D0_APC_0: 0x0
10071 09:28:37.511453 INFO: [NOCDAPC] D0_APC_1: 0x0
10072 09:28:37.511548 INFO: [NOCDAPC] D1_APC_0: 0x0
10073 09:28:37.511862 INFO: [NOCDAPC] D1_APC_1: 0xfff
10074 09:28:37.511967 INFO: [NOCDAPC] D2_APC_0: 0x0
10075 09:28:37.512072 INFO: [NOCDAPC] D2_APC_1: 0xfff
10076 09:28:37.512174 INFO: [NOCDAPC] D3_APC_0: 0x0
10077 09:28:37.512272 INFO: [NOCDAPC] D3_APC_1: 0xfff
10078 09:28:37.512373 INFO: [NOCDAPC] D4_APC_0: 0x0
10079 09:28:37.512466 INFO: [NOCDAPC] D4_APC_1: 0xfff
10080 09:28:37.512563 INFO: [NOCDAPC] D5_APC_0: 0x0
10081 09:28:37.512660 INFO: [NOCDAPC] D5_APC_1: 0xfff
10082 09:28:37.512757 INFO: [NOCDAPC] D6_APC_0: 0x0
10083 09:28:37.512852 INFO: [NOCDAPC] D6_APC_1: 0xfff
10084 09:28:37.512938 INFO: [NOCDAPC] D7_APC_0: 0x0
10085 09:28:37.513034 INFO: [NOCDAPC] D7_APC_1: 0xfff
10086 09:28:37.513131 INFO: [NOCDAPC] D8_APC_0: 0x0
10087 09:28:37.513228 INFO: [NOCDAPC] D8_APC_1: 0xfff
10088 09:28:37.513328 INFO: [NOCDAPC] D9_APC_0: 0x0
10089 09:28:37.513422 INFO: [NOCDAPC] D9_APC_1: 0xfff
10090 09:28:37.513514 INFO: [NOCDAPC] D10_APC_0: 0x0
10091 09:28:37.513611 INFO: [NOCDAPC] D10_APC_1: 0xfff
10092 09:28:37.513711 INFO: [NOCDAPC] D11_APC_0: 0x0
10093 09:28:37.513796 INFO: [NOCDAPC] D11_APC_1: 0xfff
10094 09:28:37.513888 INFO: [NOCDAPC] D12_APC_0: 0x0
10095 09:28:37.513985 INFO: [NOCDAPC] D12_APC_1: 0xfff
10096 09:28:37.514076 INFO: [NOCDAPC] D13_APC_0: 0x0
10097 09:28:37.514171 INFO: [NOCDAPC] D13_APC_1: 0xfff
10098 09:28:37.514259 INFO: [NOCDAPC] D14_APC_0: 0x0
10099 09:28:37.514345 INFO: [NOCDAPC] D14_APC_1: 0xfff
10100 09:28:37.514419 INFO: [NOCDAPC] D15_APC_0: 0x0
10101 09:28:37.514510 INFO: [NOCDAPC] D15_APC_1: 0xfff
10102 09:28:37.514608 INFO: [NOCDAPC] APC_CON: 0x4
10103 09:28:37.514703 INFO: [APUAPC] set_apusys_apc done
10104 09:28:37.514792 INFO: [DEVAPC] devapc_init done
10105 09:28:37.514892 INFO: GICv3 without legacy support detected.
10106 09:28:37.514989 INFO: ARM GICv3 driver initialized in EL3
10107 09:28:37.515090 INFO: Maximum SPI INTID supported: 639
10108 09:28:37.515188 INFO: BL31: Initializing runtime services
10109 09:28:37.515281 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10110 09:28:37.515380 INFO: SPM: enable CPC mode
10111 09:28:37.515474 INFO: mcdi ready for mcusys-off-idle and system suspend
10112 09:28:37.515569 INFO: BL31: Preparing for EL3 exit to normal world
10113 09:28:37.515664 INFO: Entry point address = 0x80000000
10114 09:28:37.515760 INFO: SPSR = 0x8
10115 09:28:37.515845
10116 09:28:37.515938
10117 09:28:37.516022
10118 09:28:37.516113 Starting depthcharge on Spherion...
10119 09:28:37.516170
10120 09:28:37.516254 Wipe memory regions:
10121 09:28:37.516310
10122 09:28:37.516387 [0x00000040000000, 0x00000054600000)
10123 09:28:37.516478
10124 09:28:37.516567 [0x00000054660000, 0x00000080000000)
10125 09:28:37.516662
10126 09:28:37.516748 [0x000000821a7280, 0x000000ffe64000)
10127 09:28:37.517664 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10128 09:28:37.517808 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10129 09:28:37.517931 Setting prompt string to ['asurada:']
10130 09:28:37.518047 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10131 09:28:38.025270
10132 09:28:38.025878 [0x00000100000000, 0x00000240000000)
10133 09:28:39.915606
10134 09:28:39.918771 Initializing XHCI USB controller at 0x11200000.
10135 09:28:42.586609
10136 09:28:42.586785 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10137 09:28:42.586872
10138 09:28:42.586934
10139 09:28:42.587022
10140 09:28:42.587344 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10142 09:28:42.687737 asurada: tftpboot 192.168.201.1 11826801/tftp-deploy-umtcdiai/kernel/image.itb 11826801/tftp-deploy-umtcdiai/kernel/cmdline
10143 09:28:42.687929 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10144 09:28:42.688012 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
10145 09:28:42.692189 tftpboot 192.168.201.1 11826801/tftp-deploy-umtcdiai/kernel/image.ittp-deploy-umtcdiai/kernel/cmdline
10146 09:28:42.692279
10147 09:28:42.692344 Waiting for link
10148 09:28:42.852578
10149 09:28:42.852751 R8152: Initializing
10150 09:28:42.852849
10151 09:28:42.855891 Version 6 (ocp_data = 5c30)
10152 09:28:42.855974
10153 09:28:42.859025 R8152: Done initializing
10154 09:28:42.859121
10155 09:28:42.859215 Adding net device
10156 09:28:43.103639
10157 09:28:43.103869 done.
10158 09:28:43.104036
10159 09:28:43.104213 MAC: 00:24:32:30:78:52
10160 09:28:43.104362
10161 09:28:43.107220 Sending DHCP discover... done.
10162 09:28:43.107370
10163 09:28:43.110503 Waiting for reply... done.
10164 09:28:43.110629
10165 09:28:43.113840 Sending DHCP request... done.
10166 09:28:43.113995
10167 09:28:49.255248 Waiting for reply... done.
10168 09:28:49.255785
10169 09:28:49.256128 My ip is 192.168.201.14
10170 09:28:49.256462
10171 09:28:49.257111 The DHCP server ip is 192.168.201.1
10172 09:28:49.257436
10173 09:28:49.257761 TFTP server IP predefined by user: 192.168.201.1
10174 09:28:49.258055
10175 09:28:49.258352 Bootfile predefined by user: 11826801/tftp-deploy-umtcdiai/kernel/image.itb
10176 09:28:49.258638
10177 09:28:49.258998 Sending tftp read request... done.
10178 09:28:49.259292
10179 09:28:49.259567 Waiting for the transfer...
10180 09:28:49.259855
10181 09:28:49.260131 00000000 ################################################################
10182 09:28:49.260435
10183 09:28:49.260707 00080000 ################################################################
10184 09:28:49.260795
10185 09:28:50.027835 00100000 ################################################################
10186 09:28:50.028539
10187 09:28:50.262002 00180000 ################################################################
10188 09:28:50.262162
10189 09:28:50.870864 00200000 ################################################################
10190 09:28:50.871017
10191 09:28:51.422454 00280000 ################################################################
10192 09:28:51.422664
10193 09:28:51.955260 00300000 ################################################################
10194 09:28:51.955434
10195 09:28:52.511459 00380000 ################################################################
10196 09:28:52.511638
10197 09:28:53.053357 00400000 ################################################################
10198 09:28:53.053503
10199 09:28:53.594503 00480000 ################################################################
10200 09:28:53.594683
10201 09:28:54.147152 00500000 ################################################################
10202 09:28:54.147317
10203 09:28:54.694353 00580000 ################################################################
10204 09:28:54.694525
10205 09:28:55.247483 00600000 ################################################################
10206 09:28:55.247650
10207 09:28:55.779783 00680000 ################################################################
10208 09:28:55.779946
10209 09:28:56.306975 00700000 ################################################################
10210 09:28:56.307155
10211 09:28:56.852452 00780000 ################################################################
10212 09:28:56.852588
10213 09:28:57.404033 00800000 ################################################################
10214 09:28:57.404167
10215 09:28:58.192990 00880000 ################################################################
10216 09:28:58.193613
10217 09:28:58.517769 00900000 ################################################################
10218 09:28:58.517902
10219 09:28:59.076609 00980000 ################################################################
10220 09:28:59.076740
10221 09:28:59.641883 00a00000 ################################################################
10222 09:28:59.642059
10223 09:29:00.197811 00a80000 ################################################################
10224 09:29:00.197950
10225 09:29:00.759480 00b00000 ################################################################
10226 09:29:00.759613
10227 09:29:01.334205 00b80000 ################################################################
10228 09:29:01.334341
10229 09:29:01.890564 00c00000 ################################################################
10230 09:29:01.890756
10231 09:29:02.443675 00c80000 ################################################################
10232 09:29:02.443806
10233 09:29:02.993693 00d00000 ################################################################
10234 09:29:02.993835
10235 09:29:03.550787 00d80000 ################################################################
10236 09:29:03.550935
10237 09:29:04.117187 00e00000 ################################################################
10238 09:29:04.117356
10239 09:29:04.669412 00e80000 ################################################################
10240 09:29:04.669665
10241 09:29:05.218291 00f00000 ################################################################
10242 09:29:05.218448
10243 09:29:05.761814 00f80000 ################################################################
10244 09:29:05.761967
10245 09:29:06.346535 01000000 ################################################################
10246 09:29:06.346682
10247 09:29:06.890909 01080000 ################################################################
10248 09:29:06.891084
10249 09:29:07.463763 01100000 ################################################################
10250 09:29:07.463940
10251 09:29:07.996548 01180000 ################################################################
10252 09:29:07.996728
10253 09:29:08.521355 01200000 ################################################################
10254 09:29:08.521490
10255 09:29:09.047387 01280000 ################################################################
10256 09:29:09.047539
10257 09:29:09.574490 01300000 ################################################################
10258 09:29:09.574644
10259 09:29:10.101025 01380000 ################################################################
10260 09:29:10.101210
10261 09:29:10.639345 01400000 ################################################################
10262 09:29:10.639524
10263 09:29:11.181909 01480000 ################################################################
10264 09:29:11.182062
10265 09:29:11.728988 01500000 ################################################################
10266 09:29:11.729141
10267 09:29:12.302248 01580000 ################################################################
10268 09:29:12.302425
10269 09:29:12.849627 01600000 ################################################################
10270 09:29:12.849766
10271 09:29:13.420386 01680000 ################################################################
10272 09:29:13.420561
10273 09:29:13.967108 01700000 ################################################################
10274 09:29:13.967251
10275 09:29:14.645476 01780000 ################################################################
10276 09:29:14.645982
10277 09:29:16.442528 01800000 ################################################################
10278 09:29:16.442704
10279 09:29:16.442862 01880000 ################################################################
10280 09:29:16.442956
10281 09:29:16.478816 01900000 ################################################################
10282 09:29:16.478930
10283 09:29:17.017788 01980000 ################################################################
10284 09:29:17.017927
10285 09:29:17.547878 01a00000 ################################################################
10286 09:29:17.548010
10287 09:29:18.101094 01a80000 ################################################################
10288 09:29:18.101279
10289 09:29:18.664278 01b00000 ################################################################
10290 09:29:18.664414
10291 09:29:18.715834 01b80000 ###### done.
10292 09:29:18.715940
10293 09:29:18.719423 The bootfile was 28884638 bytes long.
10294 09:29:18.719515
10295 09:29:18.723142 Sending tftp read request... done.
10296 09:29:18.723236
10297 09:29:18.723305 Waiting for the transfer...
10298 09:29:18.723369
10299 09:29:18.725899 00000000 # done.
10300 09:29:18.726022
10301 09:29:18.732774 Command line loaded dynamically from TFTP file: 11826801/tftp-deploy-umtcdiai/kernel/cmdline
10302 09:29:18.732879
10303 09:29:18.756061 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10304 09:29:18.756245
10305 09:29:18.756403 Loading FIT.
10306 09:29:18.756564
10307 09:29:18.759507 Image ramdisk-1 has 17791065 bytes.
10308 09:29:18.759818
10309 09:29:18.762687 Image fdt-1 has 47278 bytes.
10310 09:29:18.762913
10311 09:29:18.766366 Image kernel-1 has 11044258 bytes.
10312 09:29:18.766690
10313 09:29:18.775930 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10314 09:29:18.776174
10315 09:29:18.792419 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10316 09:29:18.792753
10317 09:29:18.796121 Choosing best match conf-1 for compat google,spherion-rev2.
10318 09:29:18.799107
10319 09:29:18.803192 Connected to device vid:did:rid of 1ae0:0028:00
10320 09:29:18.813807
10321 09:29:18.816761 tpm_get_response: command 0x17b, return code 0x0
10322 09:29:18.817004
10323 09:29:18.823539 ec_init: CrosEC protocol v3 supported (256, 248)
10324 09:29:18.823780
10325 09:29:18.826638 tpm_cleanup: add release locality here.
10326 09:29:18.826957
10327 09:29:18.830372 Shutting down all USB controllers.
10328 09:29:18.830612
10329 09:29:18.833251 Removing current net device
10330 09:29:18.833527
10331 09:29:18.836929 Exiting depthcharge with code 4 at timestamp: 71375076
10332 09:29:18.837232
10333 09:29:18.840322 LZMA decompressing kernel-1 to 0x821a6718
10334 09:29:18.843640
10335 09:29:18.846800 LZMA decompressing kernel-1 to 0x40000000
10336 09:29:20.235657
10337 09:29:20.236142 jumping to kernel
10338 09:29:20.237790 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10339 09:29:20.238336 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10340 09:29:20.238924 Setting prompt string to ['Linux version [0-9]']
10341 09:29:20.239390 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10342 09:29:20.239760 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10343 09:29:20.318657
10344 09:29:20.322273 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10345 09:29:20.325636 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10346 09:29:20.326102 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10347 09:29:20.326627 Setting prompt string to []
10348 09:29:20.327087 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10349 09:29:20.327476 Using line separator: #'\n'#
10350 09:29:20.327809 No login prompt set.
10351 09:29:20.328148 Parsing kernel messages
10352 09:29:20.328479 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10353 09:29:20.329060 [login-action] Waiting for messages, (timeout 00:03:42)
10354 09:29:20.345572 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10355 09:29:20.348417 [ 0.000000] random: crng init done
10356 09:29:20.355324 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10357 09:29:20.355745 [ 0.000000] efi: UEFI not found.
10358 09:29:20.365022 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10359 09:29:20.372006 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10360 09:29:20.382128 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10361 09:29:20.391697 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10362 09:29:20.398551 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10363 09:29:20.401949 [ 0.000000] printk: bootconsole [mtk8250] enabled
10364 09:29:20.410952 [ 0.000000] NUMA: No NUMA configuration found
10365 09:29:20.417521 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10366 09:29:20.424002 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10367 09:29:20.424548 [ 0.000000] Zone ranges:
10368 09:29:20.430999 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10369 09:29:20.434030 [ 0.000000] DMA32 empty
10370 09:29:20.440642 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10371 09:29:20.444351 [ 0.000000] Movable zone start for each node
10372 09:29:20.447399 [ 0.000000] Early memory node ranges
10373 09:29:20.454177 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10374 09:29:20.460695 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10375 09:29:20.467257 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10376 09:29:20.474008 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10377 09:29:20.477726 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10378 09:29:20.487450 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10379 09:29:20.542397 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10380 09:29:20.549170 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10381 09:29:20.555757 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10382 09:29:20.559400 [ 0.000000] psci: probing for conduit method from DT.
10383 09:29:20.565569 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10384 09:29:20.569280 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10385 09:29:20.575946 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10386 09:29:20.578766 [ 0.000000] psci: SMC Calling Convention v1.2
10387 09:29:20.585672 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10388 09:29:20.589336 [ 0.000000] Detected VIPT I-cache on CPU0
10389 09:29:20.595697 [ 0.000000] CPU features: detected: GIC system register CPU interface
10390 09:29:20.602330 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10391 09:29:20.609218 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10392 09:29:20.615855 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10393 09:29:20.622410 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10394 09:29:20.629051 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10395 09:29:20.635900 [ 0.000000] alternatives: applying boot alternatives
10396 09:29:20.639250 [ 0.000000] Fallback order for Node 0: 0
10397 09:29:20.645759 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10398 09:29:20.649453 [ 0.000000] Policy zone: Normal
10399 09:29:20.672755 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10400 09:29:20.682566 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10401 09:29:20.695142 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10402 09:29:20.705307 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10403 09:29:20.711908 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10404 09:29:20.715085 <6>[ 0.000000] software IO TLB: area num 8.
10405 09:29:20.771901 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10406 09:29:20.920898 <6>[ 0.000000] Memory: 7952120K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400648K reserved, 32768K cma-reserved)
10407 09:29:20.927419 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10408 09:29:20.933801 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10409 09:29:20.937812 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10410 09:29:20.944144 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10411 09:29:20.951116 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10412 09:29:20.954079 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10413 09:29:20.964401 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10414 09:29:20.970949 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10415 09:29:20.973943 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10416 09:29:20.981690 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10417 09:29:20.985282 <6>[ 0.000000] GICv3: 608 SPIs implemented
10418 09:29:20.991836 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10419 09:29:20.995186 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10420 09:29:20.998610 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10421 09:29:21.008535 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10422 09:29:21.018118 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10423 09:29:21.031736 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10424 09:29:21.038386 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10425 09:29:21.047597 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10426 09:29:21.060648 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10427 09:29:21.067186 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10428 09:29:21.074120 <6>[ 0.009180] Console: colour dummy device 80x25
10429 09:29:21.084124 <6>[ 0.013896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10430 09:29:21.087037 <6>[ 0.024338] pid_max: default: 32768 minimum: 301
10431 09:29:21.094446 <6>[ 0.029239] LSM: Security Framework initializing
10432 09:29:21.100992 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 09:29:21.110504 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 09:29:21.117510 <6>[ 0.051476] cblist_init_generic: Setting adjustable number of callback queues.
10435 09:29:21.124090 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 09:29:21.130587 <6>[ 0.065299] cblist_init_generic: Setting adjustable number of callback queues.
10437 09:29:21.137694 <6>[ 0.072726] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 09:29:21.144159 <6>[ 0.079125] rcu: Hierarchical SRCU implementation.
10439 09:29:21.150749 <6>[ 0.084141] rcu: Max phase no-delay instances is 1000.
10440 09:29:21.153653 <6>[ 0.091167] EFI services will not be available.
10441 09:29:21.160481 <6>[ 0.096155] smp: Bringing up secondary CPUs ...
10442 09:29:21.167893 <6>[ 0.101204] Detected VIPT I-cache on CPU1
10443 09:29:21.174590 <6>[ 0.101272] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10444 09:29:21.181601 <6>[ 0.101303] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10445 09:29:21.184509 <6>[ 0.101632] Detected VIPT I-cache on CPU2
10446 09:29:21.191716 <6>[ 0.101682] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10447 09:29:21.198367 <6>[ 0.101697] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10448 09:29:21.204943 <6>[ 0.101954] Detected VIPT I-cache on CPU3
10449 09:29:21.211601 <6>[ 0.102000] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10450 09:29:21.218242 <6>[ 0.102014] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10451 09:29:21.221541 <6>[ 0.102319] CPU features: detected: Spectre-v4
10452 09:29:21.228243 <6>[ 0.102325] CPU features: detected: Spectre-BHB
10453 09:29:21.231619 <6>[ 0.102330] Detected PIPT I-cache on CPU4
10454 09:29:21.238702 <6>[ 0.102388] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10455 09:29:21.245660 <6>[ 0.102405] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10456 09:29:21.248435 <6>[ 0.102692] Detected PIPT I-cache on CPU5
10457 09:29:21.258236 <6>[ 0.102754] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10458 09:29:21.264902 <6>[ 0.102770] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10459 09:29:21.268309 <6>[ 0.103049] Detected PIPT I-cache on CPU6
10460 09:29:21.275123 <6>[ 0.103112] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10461 09:29:21.281875 <6>[ 0.103127] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10462 09:29:21.284566 <6>[ 0.103422] Detected PIPT I-cache on CPU7
10463 09:29:21.295006 <6>[ 0.103487] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10464 09:29:21.301689 <6>[ 0.103503] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10465 09:29:21.304709 <6>[ 0.103551] smp: Brought up 1 node, 8 CPUs
10466 09:29:21.308169 <6>[ 0.244860] SMP: Total of 8 processors activated.
10467 09:29:21.314824 <6>[ 0.249781] CPU features: detected: 32-bit EL0 Support
10468 09:29:21.324210 <6>[ 0.255177] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 09:29:21.331527 <6>[ 0.263978] CPU features: detected: Common not Private translations
10470 09:29:21.334564 <6>[ 0.270455] CPU features: detected: CRC32 instructions
10471 09:29:21.341178 <6>[ 0.275806] CPU features: detected: RCpc load-acquire (LDAPR)
10472 09:29:21.347958 <6>[ 0.281765] CPU features: detected: LSE atomic instructions
10473 09:29:21.354759 <6>[ 0.287583] CPU features: detected: Privileged Access Never
10474 09:29:21.357801 <6>[ 0.293363] CPU features: detected: RAS Extension Support
10475 09:29:21.364442 <6>[ 0.299006] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 09:29:21.371357 <6>[ 0.306270] CPU: All CPU(s) started at EL2
10477 09:29:21.374651 <6>[ 0.310613] alternatives: applying system-wide alternatives
10478 09:29:21.385735 <6>[ 0.321322] devtmpfs: initialized
10479 09:29:21.397856 <6>[ 0.330128] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10480 09:29:21.407937 <6>[ 0.340088] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10481 09:29:21.414545 <6>[ 0.348105] pinctrl core: initialized pinctrl subsystem
10482 09:29:21.418119 <6>[ 0.354739] DMI not present or invalid.
10483 09:29:21.424718 <6>[ 0.359146] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10484 09:29:21.431343 <6>[ 0.365942] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10485 09:29:21.441632 <6>[ 0.373527] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10486 09:29:21.448414 <6>[ 0.381742] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10487 09:29:21.454707 <6>[ 0.389980] audit: initializing netlink subsys (disabled)
10488 09:29:21.461576 <5>[ 0.395671] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10489 09:29:21.468155 <6>[ 0.396371] thermal_sys: Registered thermal governor 'step_wise'
10490 09:29:21.474815 <6>[ 0.403635] thermal_sys: Registered thermal governor 'power_allocator'
10491 09:29:21.481604 <6>[ 0.409892] cpuidle: using governor menu
10492 09:29:21.484964 <6>[ 0.420852] NET: Registered PF_QIPCRTR protocol family
10493 09:29:21.491361 <6>[ 0.426344] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10494 09:29:21.497953 <6>[ 0.433447] ASID allocator initialised with 32768 entries
10495 09:29:21.504769 <6>[ 0.440003] Serial: AMBA PL011 UART driver
10496 09:29:21.512890 <4>[ 0.448758] Trying to register duplicate clock ID: 134
10497 09:29:21.567466 <6>[ 0.506303] KASLR enabled
10498 09:29:21.581612 <6>[ 0.513990] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10499 09:29:21.588411 <6>[ 0.521006] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10500 09:29:21.595069 <6>[ 0.527493] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10501 09:29:21.602283 <6>[ 0.534501] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10502 09:29:21.608937 <6>[ 0.540988] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10503 09:29:21.615062 <6>[ 0.547992] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10504 09:29:21.622035 <6>[ 0.554481] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10505 09:29:21.628847 <6>[ 0.561486] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10506 09:29:21.631631 <6>[ 0.568992] ACPI: Interpreter disabled.
10507 09:29:21.640015 <6>[ 0.575390] iommu: Default domain type: Translated
10508 09:29:21.646619 <6>[ 0.580499] iommu: DMA domain TLB invalidation policy: strict mode
10509 09:29:21.649575 <5>[ 0.587152] SCSI subsystem initialized
10510 09:29:21.656270 <6>[ 0.591314] usbcore: registered new interface driver usbfs
10511 09:29:21.663378 <6>[ 0.597045] usbcore: registered new interface driver hub
10512 09:29:21.666175 <6>[ 0.602597] usbcore: registered new device driver usb
10513 09:29:21.673103 <6>[ 0.608695] pps_core: LinuxPPS API ver. 1 registered
10514 09:29:21.683245 <6>[ 0.613886] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10515 09:29:21.686435 <6>[ 0.623230] PTP clock support registered
10516 09:29:21.690002 <6>[ 0.627472] EDAC MC: Ver: 3.0.0
10517 09:29:21.697194 <6>[ 0.632623] FPGA manager framework
10518 09:29:21.700309 <6>[ 0.636301] Advanced Linux Sound Architecture Driver Initialized.
10519 09:29:21.704560 <6>[ 0.643073] vgaarb: loaded
10520 09:29:21.711022 <6>[ 0.646234] clocksource: Switched to clocksource arch_sys_counter
10521 09:29:21.717720 <5>[ 0.652675] VFS: Disk quotas dquot_6.6.0
10522 09:29:21.724498 <6>[ 0.656863] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10523 09:29:21.727510 <6>[ 0.664050] pnp: PnP ACPI: disabled
10524 09:29:21.735283 <6>[ 0.670715] NET: Registered PF_INET protocol family
10525 09:29:21.742042 <6>[ 0.676299] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10526 09:29:21.756422 <6>[ 0.688599] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10527 09:29:21.766595 <6>[ 0.697414] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10528 09:29:21.773324 <6>[ 0.705382] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10529 09:29:21.779799 <6>[ 0.714083] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10530 09:29:21.791629 <6>[ 0.723825] TCP: Hash tables configured (established 65536 bind 65536)
10531 09:29:21.798143 <6>[ 0.730681] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 09:29:21.805009 <6>[ 0.737880] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 09:29:21.811272 <6>[ 0.745577] NET: Registered PF_UNIX/PF_LOCAL protocol family
10534 09:29:21.817894 <6>[ 0.751726] RPC: Registered named UNIX socket transport module.
10535 09:29:21.821722 <6>[ 0.757878] RPC: Registered udp transport module.
10536 09:29:21.828051 <6>[ 0.762809] RPC: Registered tcp transport module.
10537 09:29:21.834911 <6>[ 0.767740] RPC: Registered tcp NFSv4.1 backchannel transport module.
10538 09:29:21.838352 <6>[ 0.774408] PCI: CLS 0 bytes, default 64
10539 09:29:21.841434 <6>[ 0.778813] Unpacking initramfs...
10540 09:29:21.851353 <6>[ 0.783012] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10541 09:29:21.857932 <6>[ 0.791654] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10542 09:29:21.865083 <6>[ 0.800493] kvm [1]: IPA Size Limit: 40 bits
10543 09:29:21.868066 <6>[ 0.805023] kvm [1]: GICv3: no GICV resource entry
10544 09:29:21.874756 <6>[ 0.810043] kvm [1]: disabling GICv2 emulation
10545 09:29:21.881643 <6>[ 0.814727] kvm [1]: GIC system register CPU interface enabled
10546 09:29:21.885038 <6>[ 0.820899] kvm [1]: vgic interrupt IRQ18
10547 09:29:21.891499 <6>[ 0.826296] kvm [1]: VHE mode initialized successfully
10548 09:29:21.898027 <5>[ 0.832821] Initialise system trusted keyrings
10549 09:29:21.905018 <6>[ 0.837639] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10550 09:29:21.912312 <6>[ 0.847618] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10551 09:29:21.918657 <5>[ 0.853979] NFS: Registering the id_resolver key type
10552 09:29:21.922135 <5>[ 0.859275] Key type id_resolver registered
10553 09:29:21.928261 <5>[ 0.863690] Key type id_legacy registered
10554 09:29:21.935108 <6>[ 0.867970] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10555 09:29:21.941801 <6>[ 0.874889] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10556 09:29:21.948306 <6>[ 0.882590] 9p: Installing v9fs 9p2000 file system support
10557 09:29:21.985121 <5>[ 0.920509] Key type asymmetric registered
10558 09:29:21.988167 <5>[ 0.924839] Asymmetric key parser 'x509' registered
10559 09:29:21.998636 <6>[ 0.929973] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10560 09:29:22.002031 <6>[ 0.937589] io scheduler mq-deadline registered
10561 09:29:22.005287 <6>[ 0.942351] io scheduler kyber registered
10562 09:29:22.024039 <6>[ 0.959384] EINJ: ACPI disabled.
10563 09:29:22.056107 <4>[ 0.984874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 09:29:22.066223 <4>[ 0.995500] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 09:29:22.080587 <6>[ 1.015998] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10566 09:29:22.088075 <6>[ 1.023832] printk: console [ttyS0] disabled
10567 09:29:22.116177 <6>[ 1.048476] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10568 09:29:22.122850 <6>[ 1.057943] printk: console [ttyS0] enabled
10569 09:29:22.126277 <6>[ 1.057943] printk: console [ttyS0] enabled
10570 09:29:22.133251 <6>[ 1.066836] printk: bootconsole [mtk8250] disabled
10571 09:29:22.136321 <6>[ 1.066836] printk: bootconsole [mtk8250] disabled
10572 09:29:22.143032 <6>[ 1.077850] SuperH (H)SCI(F) driver initialized
10573 09:29:22.146446 <6>[ 1.083117] msm_serial: driver initialized
10574 09:29:22.160227 <6>[ 1.091985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10575 09:29:22.169787 <6>[ 1.100533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10576 09:29:22.176610 <6>[ 1.109077] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10577 09:29:22.186993 <6>[ 1.117706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10578 09:29:22.193424 <6>[ 1.126412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10579 09:29:22.203275 <6>[ 1.135125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10580 09:29:22.213489 <6>[ 1.143667] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10581 09:29:22.220036 <6>[ 1.152479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10582 09:29:22.229816 <6>[ 1.161021] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10583 09:29:22.241006 <6>[ 1.176410] loop: module loaded
10584 09:29:22.247417 <6>[ 1.182368] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10585 09:29:22.270007 <4>[ 1.205475] mtk-pmic-keys: Failed to locate of_node [id: -1]
10586 09:29:22.276921 <6>[ 1.212230] megasas: 07.719.03.00-rc1
10587 09:29:22.286507 <6>[ 1.221727] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10588 09:29:22.294333 <6>[ 1.229644] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10589 09:29:22.310902 <6>[ 1.246366] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10590 09:29:22.367918 <6>[ 1.296452] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10591 09:29:22.581434 <6>[ 1.516588] Freeing initrd memory: 17368K
10592 09:29:22.591598 <6>[ 1.526824] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10593 09:29:22.602396 <6>[ 1.537858] tun: Universal TUN/TAP device driver, 1.6
10594 09:29:22.606257 <6>[ 1.543917] thunder_xcv, ver 1.0
10595 09:29:22.609700 <6>[ 1.547425] thunder_bgx, ver 1.0
10596 09:29:22.612746 <6>[ 1.550922] nicpf, ver 1.0
10597 09:29:22.622843 <6>[ 1.554939] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10598 09:29:22.626144 <6>[ 1.562414] hns3: Copyright (c) 2017 Huawei Corporation.
10599 09:29:22.629344 <6>[ 1.568003] hclge is initializing
10600 09:29:22.636371 <6>[ 1.571583] e1000: Intel(R) PRO/1000 Network Driver
10601 09:29:22.643061 <6>[ 1.576712] e1000: Copyright (c) 1999-2006 Intel Corporation.
10602 09:29:22.646530 <6>[ 1.582725] e1000e: Intel(R) PRO/1000 Network Driver
10603 09:29:22.653429 <6>[ 1.587941] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10604 09:29:22.659980 <6>[ 1.594125] igb: Intel(R) Gigabit Ethernet Network Driver
10605 09:29:22.666443 <6>[ 1.599776] igb: Copyright (c) 2007-2014 Intel Corporation.
10606 09:29:22.673133 <6>[ 1.605612] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10607 09:29:22.676826 <6>[ 1.612130] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10608 09:29:22.683452 <6>[ 1.618595] sky2: driver version 1.30
10609 09:29:22.690173 <6>[ 1.623585] VFIO - User Level meta-driver version: 0.3
10610 09:29:22.696664 <6>[ 1.631832] usbcore: registered new interface driver usb-storage
10611 09:29:22.703325 <6>[ 1.638281] usbcore: registered new device driver onboard-usb-hub
10612 09:29:22.712425 <6>[ 1.647425] mt6397-rtc mt6359-rtc: registered as rtc0
10613 09:29:22.721904 <6>[ 1.652896] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:29:24 UTC (1697794164)
10614 09:29:22.725410 <6>[ 1.662509] i2c_dev: i2c /dev entries driver
10615 09:29:22.741964 <6>[ 1.674105] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10616 09:29:22.762473 <6>[ 1.698101] cpu cpu0: EM: created perf domain
10617 09:29:22.765639 <6>[ 1.703018] cpu cpu4: EM: created perf domain
10618 09:29:22.772999 <6>[ 1.708556] sdhci: Secure Digital Host Controller Interface driver
10619 09:29:22.779947 <6>[ 1.714989] sdhci: Copyright(c) Pierre Ossman
10620 09:29:22.786260 <6>[ 1.719946] Synopsys Designware Multimedia Card Interface Driver
10621 09:29:22.793138 <6>[ 1.726578] sdhci-pltfm: SDHCI platform and OF driver helper
10622 09:29:22.796697 <6>[ 1.726649] mmc0: CQHCI version 5.10
10623 09:29:22.803014 <6>[ 1.736741] ledtrig-cpu: registered to indicate activity on CPUs
10624 09:29:22.809559 <6>[ 1.743684] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10625 09:29:22.816144 <6>[ 1.750764] usbcore: registered new interface driver usbhid
10626 09:29:22.819733 <6>[ 1.756589] usbhid: USB HID core driver
10627 09:29:22.826226 <6>[ 1.760791] spi_master spi0: will run message pump with realtime priority
10628 09:29:22.868959 <6>[ 1.798184] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10629 09:29:22.884688 <6>[ 1.813867] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10630 09:29:22.893841 <6>[ 1.829903] mmc0: Command Queue Engine enabled
10631 09:29:22.901079 <6>[ 1.834680] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10632 09:29:22.907831 <6>[ 1.841405] cros-ec-spi spi0.0: Chrome EC device registered
10633 09:29:22.910716 <6>[ 1.841936] mmcblk0: mmc0:0001 DA4128 116 GiB
10634 09:29:22.923365 <6>[ 1.859168] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10635 09:29:22.930628 <6>[ 1.866041] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10636 09:29:22.937101 <6>[ 1.872350] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10637 09:29:22.947389 <6>[ 1.877107] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10638 09:29:22.954281 <6>[ 1.878357] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10639 09:29:22.957316 <6>[ 1.888081] NET: Registered PF_PACKET protocol family
10640 09:29:22.963964 <6>[ 1.898789] 9pnet: Installing 9P2000 support
10641 09:29:22.967037 <5>[ 1.903374] Key type dns_resolver registered
10642 09:29:22.970823 <6>[ 1.908332] registered taskstats version 1
10643 09:29:22.977450 <5>[ 1.912716] Loading compiled-in X.509 certificates
10644 09:29:23.008176 <4>[ 1.937315] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 09:29:23.018297 <4>[ 1.948244] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 09:29:23.025278 <3>[ 1.958830] debugfs: File 'uA_load' in directory '/' already present!
10647 09:29:23.031799 <3>[ 1.965550] debugfs: File 'min_uV' in directory '/' already present!
10648 09:29:23.038344 <3>[ 1.972181] debugfs: File 'max_uV' in directory '/' already present!
10649 09:29:23.044875 <3>[ 1.978807] debugfs: File 'constraint_flags' in directory '/' already present!
10650 09:29:23.056251 <3>[ 1.988603] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10651 09:29:23.065277 <6>[ 2.001081] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10652 09:29:23.072674 <6>[ 2.008026] xhci-mtk 11200000.usb: xHCI Host Controller
10653 09:29:23.079355 <6>[ 2.013525] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10654 09:29:23.089047 <6>[ 2.021372] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10655 09:29:23.095999 <6>[ 2.030792] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10656 09:29:23.102418 <6>[ 2.036859] xhci-mtk 11200000.usb: xHCI Host Controller
10657 09:29:23.109340 <6>[ 2.042335] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10658 09:29:23.115961 <6>[ 2.049980] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10659 09:29:23.122581 <6>[ 2.057643] hub 1-0:1.0: USB hub found
10660 09:29:23.126134 <6>[ 2.061651] hub 1-0:1.0: 1 port detected
10661 09:29:23.132451 <6>[ 2.065919] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10662 09:29:23.139430 <6>[ 2.074428] hub 2-0:1.0: USB hub found
10663 09:29:23.143003 <6>[ 2.078432] hub 2-0:1.0: 1 port detected
10664 09:29:23.150769 <6>[ 2.086423] mtk-msdc 11f70000.mmc: Got CD GPIO
10665 09:29:23.161313 <6>[ 2.093251] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10666 09:29:23.167992 <6>[ 2.101281] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10667 09:29:23.178176 <4>[ 2.109175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10668 09:29:23.184702 <6>[ 2.118705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10669 09:29:23.194708 <6>[ 2.126782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10670 09:29:23.201667 <6>[ 2.134810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10671 09:29:23.211141 <6>[ 2.142728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10672 09:29:23.218020 <6>[ 2.150546] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10673 09:29:23.228000 <6>[ 2.158363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10674 09:29:23.238093 <6>[ 2.168777] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10675 09:29:23.244894 <6>[ 2.177136] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10676 09:29:23.254614 <6>[ 2.185481] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10677 09:29:23.261256 <6>[ 2.193820] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10678 09:29:23.271760 <6>[ 2.202158] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10679 09:29:23.278413 <6>[ 2.210503] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10680 09:29:23.285224 <6>[ 2.218843] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10681 09:29:23.294834 <6>[ 2.227181] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10682 09:29:23.301930 <6>[ 2.235520] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10683 09:29:23.312017 <6>[ 2.243859] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10684 09:29:23.318271 <6>[ 2.252206] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10685 09:29:23.328493 <6>[ 2.260544] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10686 09:29:23.335030 <6>[ 2.268882] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10687 09:29:23.345179 <6>[ 2.277220] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10688 09:29:23.351967 <6>[ 2.285558] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10689 09:29:23.358646 <6>[ 2.294273] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10690 09:29:23.365710 <6>[ 2.301436] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10691 09:29:23.372599 <6>[ 2.308191] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10692 09:29:23.382846 <6>[ 2.314949] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10693 09:29:23.389487 <6>[ 2.321888] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10694 09:29:23.396106 <6>[ 2.328744] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10695 09:29:23.406107 <6>[ 2.337878] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10696 09:29:23.416112 <6>[ 2.346997] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10697 09:29:23.425756 <6>[ 2.356292] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10698 09:29:23.435952 <6>[ 2.365760] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10699 09:29:23.442288 <6>[ 2.375227] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10700 09:29:23.452505 <6>[ 2.384347] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10701 09:29:23.462188 <6>[ 2.393823] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10702 09:29:23.472166 <6>[ 2.402944] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10703 09:29:23.482411 <6>[ 2.412240] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10704 09:29:23.491977 <6>[ 2.422400] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10705 09:29:23.502307 <6>[ 2.433941] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10706 09:29:23.508997 <6>[ 2.443753] Trying to probe devices needed for running init ...
10707 09:29:23.550251 <6>[ 2.482506] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10708 09:29:23.704478 <6>[ 2.640412] hub 1-1:1.0: USB hub found
10709 09:29:23.707519 <6>[ 2.644910] hub 1-1:1.0: 4 ports detected
10710 09:29:23.829801 <6>[ 2.762812] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10711 09:29:23.856210 <6>[ 2.792301] hub 2-1:1.0: USB hub found
10712 09:29:23.859534 <6>[ 2.796797] hub 2-1:1.0: 3 ports detected
10713 09:29:24.030040 <6>[ 2.962537] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10714 09:29:24.162247 <6>[ 3.098078] hub 1-1.4:1.0: USB hub found
10715 09:29:24.165208 <6>[ 3.102675] hub 1-1.4:1.0: 2 ports detected
10716 09:29:24.241860 <6>[ 3.174686] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10717 09:29:24.461742 <6>[ 3.394551] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10718 09:29:24.653953 <6>[ 3.586550] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10719 09:29:35.795392 <6>[ 14.735525] ALSA device list:
10720 09:29:35.801377 <6>[ 14.738819] No soundcards found.
10721 09:29:35.809682 <6>[ 14.746762] Freeing unused kernel memory: 8384K
10722 09:29:35.813041 <6>[ 14.751783] Run /init as init process
10723 09:29:35.824531 Loading, please wait...
10724 09:29:35.844666 Starting version 247.3-7+deb11u2
10725 09:29:36.100909 <6>[ 14.998656] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10726 09:29:36.102967 <6>[ 15.008905] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10727 09:29:36.103608 <6>[ 15.010489] remoteproc remoteproc0: scp is available
10728 09:29:36.104190 <6>[ 15.016739] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10729 09:29:36.104731 <6>[ 15.022513] remoteproc remoteproc0: powering up scp
10730 09:29:36.105256 <6>[ 15.030722] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10731 09:29:36.111512 <6>[ 15.035827] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10732 09:29:36.114933 <6>[ 15.035843] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10733 09:29:36.127177 <3>[ 15.060992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 09:29:36.133848 <3>[ 15.069167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 09:29:36.144124 <6>[ 15.072646] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10736 09:29:36.150547 <3>[ 15.077266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 09:29:36.156885 <6>[ 15.086951] usbcore: registered new interface driver r8152
10738 09:29:36.163836 <3>[ 15.093114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 09:29:36.169908 <6>[ 15.093239] mc: Linux media interface: v0.10
10740 09:29:36.176968 <3>[ 15.111562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 09:29:36.186670 <4>[ 15.112578] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10742 09:29:36.190258 <4>[ 15.112578] Fallback method does not support PEC.
10743 09:29:36.200202 <3>[ 15.119715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 09:29:36.207458 <3>[ 15.141392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 09:29:36.215020 <3>[ 15.149479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 09:29:36.224472 <3>[ 15.150929] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10747 09:29:36.231226 <3>[ 15.157646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 09:29:36.237648 <6>[ 15.163533] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10749 09:29:36.244690 <6>[ 15.163540] pci_bus 0000:00: root bus resource [bus 00-ff]
10750 09:29:36.251176 <6>[ 15.163546] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10751 09:29:36.261912 <6>[ 15.163552] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10752 09:29:36.268365 <6>[ 15.163584] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10753 09:29:36.275165 <6>[ 15.163604] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10754 09:29:36.281465 <6>[ 15.163685] pci 0000:00:00.0: supports D1 D2
10755 09:29:36.288344 <6>[ 15.163689] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10756 09:29:36.294677 <6>[ 15.165342] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10757 09:29:36.301831 <6>[ 15.165477] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10758 09:29:36.308028 <6>[ 15.165508] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10759 09:29:36.318085 <6>[ 15.165531] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10760 09:29:36.325072 <6>[ 15.165549] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10761 09:29:36.327869 <6>[ 15.165670] pci 0000:01:00.0: supports D1 D2
10762 09:29:36.334628 <6>[ 15.165674] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10763 09:29:36.341381 <6>[ 15.174345] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10764 09:29:36.351400 <3>[ 15.174486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 09:29:36.358198 <4>[ 15.177301] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10766 09:29:36.365080 <6>[ 15.180988] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10767 09:29:36.374363 <6>[ 15.181415] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10768 09:29:36.378187 <6>[ 15.182567] videodev: Linux video capture interface: v2.00
10769 09:29:36.384665 <4>[ 15.183674] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10770 09:29:36.394575 <6>[ 15.187061] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10771 09:29:36.401325 <3>[ 15.187615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 09:29:36.411020 <3>[ 15.187628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 09:29:36.417934 <3>[ 15.187721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 09:29:36.427689 <3>[ 15.187731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 09:29:36.434626 <3>[ 15.187739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 09:29:36.444514 <3>[ 15.187747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 09:29:36.450743 <3>[ 15.187755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 09:29:36.457544 <3>[ 15.187793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 09:29:36.467509 <6>[ 15.191144] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10780 09:29:36.476935 <6>[ 15.191663] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10781 09:29:36.487369 <6>[ 15.194187] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10782 09:29:36.493774 <6>[ 15.194240] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10783 09:29:36.500703 <6>[ 15.204113] remoteproc remoteproc0: remote processor scp is now up
10784 09:29:36.510463 <3>[ 15.208676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10785 09:29:36.516964 <6>[ 15.210431] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10786 09:29:36.527422 <6>[ 15.230602] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10787 09:29:36.533986 <6>[ 15.237658] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10788 09:29:36.540471 <6>[ 15.246160] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10789 09:29:36.547482 <6>[ 15.251473] pci 0000:00:00.0: PCI bridge to [bus 01]
10790 09:29:36.553915 <6>[ 15.258690] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10791 09:29:36.563786 <4>[ 15.281894] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10792 09:29:36.570074 <6>[ 15.284603] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10793 09:29:36.580330 <4>[ 15.292723] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10794 09:29:36.587063 <6>[ 15.294108] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10795 09:29:36.593569 <6>[ 15.300484] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10796 09:29:36.600177 <6>[ 15.307638] usbcore: registered new interface driver cdc_ether
10797 09:29:36.606793 <6>[ 15.315924] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10798 09:29:36.609952 <6>[ 15.321569] Bluetooth: Core ver 2.22
10799 09:29:36.616938 <6>[ 15.328461] usbcore: registered new interface driver r8153_ecm
10800 09:29:36.623556 <6>[ 15.328573] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10801 09:29:36.630359 <6>[ 15.336798] NET: Registered PF_BLUETOOTH protocol family
10802 09:29:36.637420 <6>[ 15.345687] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10803 09:29:36.643237 <6>[ 15.352866] Bluetooth: HCI device and connection manager initialized
10804 09:29:36.646609 <6>[ 15.352885] Bluetooth: HCI socket layer initialized
10805 09:29:36.650219 <6>[ 15.354500] r8152 2-1.3:1.0 eth0: v1.12.13
10806 09:29:36.660192 <5>[ 15.356076] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10807 09:29:36.673377 <6>[ 15.362715] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10808 09:29:36.677281 <6>[ 15.363706] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10809 09:29:36.683845 <5>[ 15.368204] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10810 09:29:36.690633 <6>[ 15.369042] Bluetooth: L2CAP socket layer initialized
10811 09:29:36.693455 <6>[ 15.369053] Bluetooth: SCO socket layer initialized
10812 09:29:36.700398 <6>[ 15.377420] usbcore: registered new interface driver uvcvideo
10813 09:29:36.706881 <6>[ 15.387463] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10814 09:29:36.713421 <6>[ 15.443454] usbcore: registered new interface driver btusb
10815 09:29:36.723831 <4>[ 15.444659] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10816 09:29:36.730157 <3>[ 15.444666] Bluetooth: hci0: Failed to load firmware file (-2)
10817 09:29:36.736980 <3>[ 15.444668] Bluetooth: hci0: Failed to set up firmware (-2)
10818 09:29:36.747062 <4>[ 15.444671] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10819 09:29:36.756706 <4>[ 15.458749] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10820 09:29:36.763612 <6>[ 15.516787] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10821 09:29:36.766647 <6>[ 15.521783] cfg80211: failed to load regulatory.db
10822 09:29:36.773481 <6>[ 15.531157] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10823 09:29:36.797127 <6>[ 15.734442] mt7921e 0000:01:00.0: ASIC revision: 79610010
10824 09:29:36.903678 <4>[ 15.834644] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 09:29:36.907271 Begin: Loading essential drivers ... done.
10826 09:29:36.914074 Begin: Running /scripts/init-premount ... done.
10827 09:29:36.920510 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10828 09:29:36.930653 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10829 09:29:36.933766 Device /sys/class/net/enx002432307852 found
10830 09:29:36.933883 done.
10831 09:29:37.023777 IP-Config: enx002432307852 hardw<4>[ 15.952968] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10832 09:29:37.026745 are address 00:24:32:30:78:52 mtu 1500 DHCP
10833 09:29:37.140667 <4>[ 16.071637] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 09:29:37.256527 <4>[ 16.187455] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10835 09:29:37.372217 <4>[ 16.303375] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10836 09:29:37.488482 <4>[ 16.419300] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10837 09:29:37.604402 <4>[ 16.535260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 09:29:37.720069 <4>[ 16.651139] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 09:29:37.836285 <4>[ 16.767210] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 09:29:37.952388 <4>[ 16.883111] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 09:29:38.059752 <3>[ 16.997173] mt7921e 0000:01:00.0: hardware init failed
10842 09:29:38.067334 <6>[ 17.004869] r8152 2-1.3:1.0 enx002432307852: carrier on
10843 09:29:38.215311 IP-Config: no response after 2 secs - giving up
10844 09:29:38.260730 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10845 09:29:38.267615 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10846 09:29:38.273939 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10847 09:29:38.280640 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10848 09:29:38.287676 host : mt8192-asurada-spherion-r0-cbg-3
10849 09:29:38.294264 domain : lava-rack
10850 09:29:38.297284 rootserver: 192.168.201.1 rootpath:
10851 09:29:38.300734 filename :
10852 09:29:38.370996 done.
10853 09:29:38.378505 Begin: Running /scripts/nfs-bottom ... done.
10854 09:29:38.402922 Begin: Running /scripts/init-bottom ... done.
10855 09:29:39.647753 <6>[ 18.585246] NET: Registered PF_INET6 protocol family
10856 09:29:39.654637 <6>[ 18.592481] Segment Routing with IPv6
10857 09:29:39.658111 <6>[ 18.596504] In-situ OAM (IOAM) with IPv6
10858 09:29:39.786082 <30>[ 18.707243] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10859 09:29:39.793664 <30>[ 18.731633] systemd[1]: Detected architecture arm64.
10860 09:29:39.814784
10861 09:29:39.817949 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10862 09:29:39.818054
10863 09:29:39.835281 <30>[ 18.773141] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10864 09:29:40.695533 <30>[ 19.630557] systemd[1]: Queued start job for default target Graphical Interface.
10865 09:29:40.727161 <30>[ 19.664931] systemd[1]: Created slice system-getty.slice.
10866 09:29:40.733523 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10867 09:29:40.749691 <30>[ 19.687936] systemd[1]: Created slice system-modprobe.slice.
10868 09:29:40.756473 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10869 09:29:40.773998 <30>[ 19.711810] systemd[1]: Created slice system-serial\x2dgetty.slice.
10870 09:29:40.783874 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10871 09:29:40.797347 <30>[ 19.735603] systemd[1]: Created slice User and Session Slice.
10872 09:29:40.804180 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10873 09:29:40.824527 <30>[ 19.759278] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10874 09:29:40.834438 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10875 09:29:40.852705 <30>[ 19.787281] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10876 09:29:40.859245 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10877 09:29:40.883405 <30>[ 19.814676] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10878 09:29:40.890110 <30>[ 19.826846] systemd[1]: Reached target Local Encrypted Volumes.
10879 09:29:40.896754 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10880 09:29:40.912554 <30>[ 19.850629] systemd[1]: Reached target Paths.
10881 09:29:40.916092 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10882 09:29:40.932371 <30>[ 19.870507] systemd[1]: Reached target Remote File Systems.
10883 09:29:40.938842 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10884 09:29:40.956756 <30>[ 19.894892] systemd[1]: Reached target Slices.
10885 09:29:40.963676 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10886 09:29:40.976435 <30>[ 19.914544] systemd[1]: Reached target Swap.
10887 09:29:40.979964 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10888 09:29:41.000361 <30>[ 19.935034] systemd[1]: Listening on initctl Compatibility Named Pipe.
10889 09:29:41.006626 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10890 09:29:41.013494 <30>[ 19.951156] systemd[1]: Listening on Journal Audit Socket.
10891 09:29:41.019784 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10892 09:29:41.037948 <30>[ 19.975738] systemd[1]: Listening on Journal Socket (/dev/log).
10893 09:29:41.044372 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10894 09:29:41.061512 <30>[ 19.999789] systemd[1]: Listening on Journal Socket.
10895 09:29:41.068596 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10896 09:29:41.085619 <30>[ 20.020225] systemd[1]: Listening on Network Service Netlink Socket.
10897 09:29:41.092183 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10898 09:29:41.107141 <30>[ 20.045276] systemd[1]: Listening on udev Control Socket.
10899 09:29:41.113704 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10900 09:29:41.128841 <30>[ 20.066981] systemd[1]: Listening on udev Kernel Socket.
10901 09:29:41.135336 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10902 09:29:41.192751 <30>[ 20.130740] systemd[1]: Mounting Huge Pages File System...
10903 09:29:41.199491 Mounting [0;1;39mHuge Pages File System[0m...
10904 09:29:41.216529 <30>[ 20.154796] systemd[1]: Mounting POSIX Message Queue File System...
10905 09:29:41.223481 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10906 09:29:41.244710 <30>[ 20.182577] systemd[1]: Mounting Kernel Debug File System...
10907 09:29:41.251365 Mounting [0;1;39mKernel Debug File System[0m...
10908 09:29:41.268314 <30>[ 20.202901] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10909 09:29:41.284116 <30>[ 20.218712] systemd[1]: Starting Create list of static device nodes for the current kernel...
10910 09:29:41.290872 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10911 09:29:41.312302 <30>[ 20.250100] systemd[1]: Starting Load Kernel Module configfs...
10912 09:29:41.318887 Starting [0;1;39mLoad Kernel Module configfs[0m...
10913 09:29:41.337463 <30>[ 20.275728] systemd[1]: Starting Load Kernel Module drm...
10914 09:29:41.344063 Starting [0;1;39mLoad Kernel Module drm[0m...
10915 09:29:41.360477 <30>[ 20.298368] systemd[1]: Starting Load Kernel Module fuse...
10916 09:29:41.367129 Starting [0;1;39mLoad Kernel Module fuse[0m...
10917 09:29:41.390673 <30>[ 20.325605] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10918 09:29:41.405666 <6>[ 20.343937] fuse: init (API version 7.37)
10919 09:29:41.432820 <30>[ 20.371218] systemd[1]: Starting Journal Service...
10920 09:29:41.439726 Starting [0;1;39mJournal Service[0m...
10921 09:29:41.461119 <30>[ 20.399474] systemd[1]: Starting Load Kernel Modules...
10922 09:29:41.467941 Starting [0;1;39mLoad Kernel Modules[0m...
10923 09:29:41.487100 <30>[ 20.421694] systemd[1]: Starting Remount Root and Kernel File Systems...
10924 09:29:41.493168 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10925 09:29:41.513509 <30>[ 20.451464] systemd[1]: Starting Coldplug All udev Devices...
10926 09:29:41.519744 Starting [0;1;39mColdplug All udev Devices[0m...
10927 09:29:41.538431 <30>[ 20.476580] systemd[1]: Mounted Huge Pages File System.
10928 09:29:41.545134 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10929 09:29:41.561195 <30>[ 20.499244] systemd[1]: Mounted POSIX Message Queue File System.
10930 09:29:41.567796 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10931 09:29:41.585043 <30>[ 20.523188] systemd[1]: Mounted Kernel Debug File System.
10932 09:29:41.591732 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10933 09:29:41.613579 <30>[ 20.548318] systemd[1]: Finished Create list of static device nodes for the current kernel.
10934 09:29:41.623357 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10935 09:29:41.637997 <30>[ 20.576223] systemd[1]: modprobe@configfs.service: Succeeded.
10936 09:29:41.646318 <30>[ 20.584128] systemd[1]: Finished Load Kernel Module configfs.
10937 09:29:41.652748 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10938 09:29:41.669615 <30>[ 20.607528] systemd[1]: modprobe@drm.service: Succeeded.
10939 09:29:41.676300 <30>[ 20.614106] systemd[1]: Finished Load Kernel Module drm.
10940 09:29:41.682532 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10941 09:29:41.697475 <30>[ 20.635424] systemd[1]: modprobe@fuse.service: Succeeded.
10942 09:29:41.704150 <30>[ 20.642296] systemd[1]: Finished Load Kernel Module fuse.
10943 09:29:41.710905 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10944 09:29:41.725563 <30>[ 20.663598] systemd[1]: Finished Load Kernel Modules.
10945 09:29:41.735701 <3>[ 20.667384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 09:29:41.739095 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10947 09:29:41.761028 <30>[ 20.695564] systemd[1]: Finished Remount Root and Kernel File Systems.
10948 09:29:41.768626 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10949 09:29:41.778519 <3>[ 20.712270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 09:29:41.832528 <3>[ 20.766988] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 09:29:41.838880 <30>[ 20.773393] systemd[1]: Mounting FUSE Control File System...
10952 09:29:41.845630 Mounting [0;1;39mFUSE Control File System[0m...
10953 09:29:41.860892 <3>[ 20.795785] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 09:29:41.867585 <30>[ 20.797086] systemd[1]: Mounting Kernel Configuration File System...
10955 09:29:41.874580 Mounting [0;1;39mKernel Configuration File System[0m...
10956 09:29:41.895210 <3>[ 20.829780] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 09:29:41.905459 <30>[ 20.831015] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10958 09:29:41.915563 <30>[ 20.847719] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10959 09:29:41.927538 <3>[ 20.862745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 09:29:41.948931 <30>[ 20.886983] systemd[1]: Starting Load/Save Random Seed...
10961 09:29:41.959444 <3>[ 20.892314] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 09:29:41.962875 Starting [0;1;39mLoad/Save Random Seed[0m...
10963 09:29:41.975112 <3>[ 20.909847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 09:29:41.985307 <30>[ 20.923305] systemd[1]: Starting Apply Kernel Variables...
10965 09:29:41.991636 Starting [0;1;39mApply Kernel Variables[0m...
10966 09:29:42.011987 <30>[ 20.949538] systemd[1]: Starting Create System Users...
10967 09:29:42.019321 Starting [0;1;39mCreate System Users[0m...
10968 09:29:42.029044 <3>[ 20.962303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 09:29:42.038898 <3>[ 20.971832] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10970 09:29:42.053166 <4>[ 20.980672] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10971 09:29:42.059898 <30>[ 20.983206] systemd[1]: Mounted FUSE Control File System.
10972 09:29:42.066542 <3>[ 20.996323] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10973 09:29:42.073455 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10974 09:29:42.089289 <30>[ 21.027339] systemd[1]: Mounted Kernel Configuration File System.
10975 09:29:42.096694 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10976 09:29:42.120849 <29>[ 21.055339] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10977 09:29:42.131164 <28>[ 21.065597] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10978 09:29:42.138309 <27>[ 21.075169] systemd[1]: Failed to start Coldplug All udev Devices.
10979 09:29:42.144662 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10980 09:29:42.160263 See 'systemctl status systemd-udev-trigger.service' for details.
10981 09:29:42.177176 <30>[ 21.115316] systemd[1]: Started Journal Service.
10982 09:29:42.183464 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10983 09:29:42.205666 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10984 09:29:42.222341 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10985 09:29:42.237924 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10986 09:29:42.285661 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10987 09:29:42.303141 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10988 09:29:42.343120 <46>[ 21.278182] systemd-journald[295]: Received client request to flush runtime journal.
10989 09:29:42.395876 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10990 09:29:42.413714 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10991 09:29:42.432394 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10992 09:29:42.492890 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10993 09:29:43.762322 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10994 09:29:43.821349 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10995 09:29:43.840504 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10996 09:29:43.873859 Starting [0;1;39mNetwork Service[0m...
10997 09:29:44.211252 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10998 09:29:44.233266 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10999 09:29:44.277080 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11000 09:29:44.562595 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11001 09:29:44.579759 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11002 09:29:44.617020 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11003 09:29:44.637528 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11004 09:29:44.653329 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11005 09:29:44.681293 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11006 09:29:44.725880 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11007 09:29:44.764943 Starting [0;1;39mNetwork Name Resolution[0m...
11008 09:29:44.792408 Starting [0;1;39mNetwork Time Synchronization[0m...
11009 09:29:44.813792 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11010 09:29:44.887064 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11011 09:29:44.990008 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11012 09:29:45.012803 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11013 09:29:45.035301 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11014 09:29:45.052324 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11015 09:29:45.068121 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11016 09:29:45.200098 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11017 09:29:45.230618 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11018 09:29:45.266659 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11019 09:29:45.551143 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11020 09:29:45.567868 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11021 09:29:45.821640 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11022 09:29:45.836327 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11023 09:29:45.851878 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11024 09:29:45.912977 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11025 09:29:46.080849 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11026 09:29:46.416624 Starting [0;1;39mUser Login Management[0m...
11027 09:29:46.524546 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11028 09:29:46.544551 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11029 09:29:46.567187 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11030 09:29:46.600565 Starting [0;1;39mPermit User Sessions[0m...
11031 09:29:46.678425 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11032 09:29:46.691850 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11033 09:29:46.736447 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11034 09:29:46.801729 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11035 09:29:46.816482 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11036 09:29:46.836783 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11037 09:29:46.855088 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11038 09:29:46.874012 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11039 09:29:46.931586 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11040 09:29:46.971171 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11041 09:29:47.078481
11042 09:29:47.078621
11043 09:29:47.081855 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11044 09:29:47.081933
11045 09:29:47.084898 debian-bullseye-arm64 login: root (automatic login)
11046 09:29:47.085013
11047 09:29:47.085117
11048 09:29:47.432213 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
11049 09:29:47.432351
11050 09:29:47.439046 The programs included with the Debian GNU/Linux system are free software;
11051 09:29:47.445572 the exact distribution terms for each program are described in the
11052 09:29:47.449027 individual files in /usr/share/doc/*/copyright.
11053 09:29:47.449110
11054 09:29:47.455467 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11055 09:29:47.458798 permitted by applicable law.
11056 09:29:48.346906 Matched prompt #10: / #
11058 09:29:48.347215 Setting prompt string to ['/ #']
11059 09:29:48.347314 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11061 09:29:48.347524 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11062 09:29:48.347624 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11063 09:29:48.347694 Setting prompt string to ['/ #']
11064 09:29:48.347766 Forcing a shell prompt, looking for ['/ #']
11066 09:29:48.397962 / #
11067 09:29:48.398120 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11068 09:29:48.398296 Waiting using forced prompt support (timeout 00:02:30)
11069 09:29:48.403304
11070 09:29:48.403588 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11071 09:29:48.403683 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11073 09:29:48.504024 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv'
11074 09:29:48.509139 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826801/extract-nfsrootfs-9e_4_pvv'
11076 09:29:48.609714 / # export NFS_SERVER_IP='192.168.201.1'
11077 09:29:48.615390 export NFS_SERVER_IP='192.168.201.1'
11078 09:29:48.615685 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11079 09:29:48.615788 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11080 09:29:48.615876 end: 2 depthcharge-action (duration 00:01:47) [common]
11081 09:29:48.615964 start: 3 lava-test-retry (timeout 00:07:25) [common]
11082 09:29:48.616051 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11083 09:29:48.616125 Using namespace: common
11085 09:29:48.716429 / # #
11086 09:29:48.716650 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11087 09:29:48.722075 #
11088 09:29:48.722344 Using /lava-11826801
11090 09:29:48.822697 / # export SHELL=/bin/bash
11091 09:29:48.828149 export SHELL=/bin/bash
11093 09:29:48.928681 / # . /lava-11826801/environment
11094 09:29:48.934451 . /lava-11826801/environment
11096 09:29:49.040856 / # /lava-11826801/bin/lava-test-runner /lava-11826801/0
11097 09:29:49.041034 Test shell timeout: 10s (minimum of the action and connection timeout)
11098 09:29:49.046059 /lava-11826801/bin/lava-test-runner /lava-11826801/0
11099 09:29:49.347833 + export TESTRUN_ID=0_timesync-off
11100 09:29:49.351518 + TESTRUN_ID=0_timesync-off
11101 09:29:49.354186 + cd /lava-11826801/0/tests/0_timesync-off
11102 09:29:49.357701 ++ cat uuid
11103 09:29:49.361924 + UUID=11826801_1.6.2.3.1
11104 09:29:49.362016 + set +x
11105 09:29:49.368543 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11826801_1.6.2.3.1>
11106 09:29:49.368801 Received signal: <STARTRUN> 0_timesync-off 11826801_1.6.2.3.1
11107 09:29:49.368897 Starting test lava.0_timesync-off (11826801_1.6.2.3.1)
11108 09:29:49.369008 Skipping test definition patterns.
11109 09:29:49.371920 + systemctl stop systemd-timesyncd
11110 09:29:49.464382 + set +x
11111 09:29:49.467349 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11826801_1.6.2.3.1>
11112 09:29:49.467615 Received signal: <ENDRUN> 0_timesync-off 11826801_1.6.2.3.1
11113 09:29:49.467711 Ending use of test pattern.
11114 09:29:49.467801 Ending test lava.0_timesync-off (11826801_1.6.2.3.1), duration 0.10
11116 09:29:49.554689 + export TESTRUN_ID=1_kselftest-arm64
11117 09:29:49.554846 + TESTRUN_ID=1_kselftest-arm64
11118 09:29:49.561156 + cd /lava-11826801/0/tests/1_kselftest-arm64
11119 09:29:49.561247 ++ cat uuid
11120 09:29:49.566077 + UUID=11826801_1.6.2.3.5
11121 09:29:49.566173 + set +x
11122 09:29:49.572741 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 11826801_1.6.2.3.5>
11123 09:29:49.573000 Received signal: <STARTRUN> 1_kselftest-arm64 11826801_1.6.2.3.5
11124 09:29:49.573081 Starting test lava.1_kselftest-arm64 (11826801_1.6.2.3.5)
11125 09:29:49.573207 Skipping test definition patterns.
11126 09:29:49.576372 + cd ./automated/linux/kselftest/
11127 09:29:49.602678 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11128 09:29:49.640812 INFO: install_deps skipped
11129 09:29:49.769239 --2023-10-20 09:29:49-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11130 09:29:49.789718 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11131 09:29:49.924109 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11132 09:29:50.057255 HTTP request sent, awaiting response... 200 OK
11133 09:29:50.060767 Length: 2964156 (2.8M) [application/octet-stream]
11134 09:29:50.064320 Saving to: 'kselftest.tar.xz'
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11152 09:29:53.402924
11153 09:29:59.965598 skiplist:
11154 09:29:59.968591 ========================================
11155 09:29:59.972018 ========================================
11156 09:30:00.031704 arm64:tags_test
11157 09:30:00.034707 arm64:run_tags_test.sh
11158 09:30:00.035409 arm64:fake_sigreturn_bad_magic
11159 09:30:00.037878 arm64:fake_sigreturn_bad_size
11160 09:30:00.041624 arm64:fake_sigreturn_bad_size_for_magic0
11161 09:30:00.044760 arm64:fake_sigreturn_duplicated_fpsimd
11162 09:30:00.047518 arm64:fake_sigreturn_misaligned_sp
11163 09:30:00.050960 arm64:fake_sigreturn_missing_fpsimd
11164 09:30:00.054633 arm64:fake_sigreturn_sme_change_vl
11165 09:30:00.057813 arm64:fake_sigreturn_sve_change_vl
11166 09:30:00.061102 arm64:mangle_pstate_invalid_compat_toggle
11167 09:30:00.064477 arm64:mangle_pstate_invalid_daif_bits
11168 09:30:00.067905 arm64:mangle_pstate_invalid_mode_el1h
11169 09:30:00.070702 arm64:mangle_pstate_invalid_mode_el1t
11170 09:30:00.074562 arm64:mangle_pstate_invalid_mode_el2h
11171 09:30:00.077318 arm64:mangle_pstate_invalid_mode_el2t
11172 09:30:00.081120 arm64:mangle_pstate_invalid_mode_el3h
11173 09:30:00.084316 arm64:mangle_pstate_invalid_mode_el3t
11174 09:30:00.087387 arm64:sme_trap_no_sm
11175 09:30:00.090473 arm64:sme_trap_non_streaming
11176 09:30:00.090579 arm64:sme_trap_za
11177 09:30:00.094109 arm64:sme_vl
11178 09:30:00.094238 arm64:ssve_regs
11179 09:30:00.097123 arm64:sve_regs
11180 09:30:00.097251 arm64:sve_vl
11181 09:30:00.097370 arm64:za_no_regs
11182 09:30:00.100446 arm64:za_regs
11183 09:30:00.100527 arm64:pac
11184 09:30:00.100612 arm64:fp-stress
11185 09:30:00.103917 arm64:sve-ptrace
11186 09:30:00.104000 arm64:sve-probe-vls
11187 09:30:00.107560 arm64:vec-syscfg
11188 09:30:00.107656 arm64:za-fork
11189 09:30:00.111082 arm64:za-ptrace
11190 09:30:00.111163 arm64:check_buffer_fill
11191 09:30:00.114024 arm64:check_child_memory
11192 09:30:00.117434 arm64:check_gcr_el1_cswitch
11193 09:30:00.120558 arm64:check_ksm_options
11194 09:30:00.120639 arm64:check_mmap_options
11195 09:30:00.124449 arm64:check_prctl
11196 09:30:00.124529 arm64:check_tags_inclusion
11197 09:30:00.127212 arm64:check_user_mem
11198 09:30:00.127293 arm64:btitest
11199 09:30:00.130622 arm64:nobtitest
11200 09:30:00.130717 arm64:hwcap
11201 09:30:00.134225 arm64:ptrace
11202 09:30:00.134306 arm64:syscall-abi
11203 09:30:00.134368 arm64:tpidr2
11204 09:30:00.140588 ============== Tests to run ===============
11205 09:30:00.140671 arm64:tags_test
11206 09:30:00.144011 arm64:run_tags_test.sh
11207 09:30:00.147291 arm64:fake_sigreturn_bad_magic
11208 09:30:00.147372 arm64:fake_sigreturn_bad_size
11209 09:30:00.150669 arm64:fake_sigreturn_bad_size_for_magic0
11210 09:30:00.154143 arm64:fake_sigreturn_duplicated_fpsimd
11211 09:30:00.157584 arm64:fake_sigreturn_misaligned_sp
11212 09:30:00.160682 arm64:fake_sigreturn_missing_fpsimd
11213 09:30:00.164243 arm64:fake_sigreturn_sme_change_vl
11214 09:30:00.167064 arm64:fake_sigreturn_sve_change_vl
11215 09:30:00.170339 arm64:mangle_pstate_invalid_compat_toggle
11216 09:30:00.173809 arm64:mangle_pstate_invalid_daif_bits
11217 09:30:00.177028 arm64:mangle_pstate_invalid_mode_el1h
11218 09:30:00.180566 arm64:mangle_pstate_invalid_mode_el1t
11219 09:30:00.183759 arm64:mangle_pstate_invalid_mode_el2h
11220 09:30:00.186996 arm64:mangle_pstate_invalid_mode_el2t
11221 09:30:00.190284 arm64:mangle_pstate_invalid_mode_el3h
11222 09:30:00.196880 arm64:mangle_pstate_invalid_mode_el3t
11223 09:30:00.196961 arm64:sme_trap_no_sm
11224 09:30:00.200205 arm64:sme_trap_non_streaming
11225 09:30:00.200286 arm64:sme_trap_za
11226 09:30:00.203910 arm64:sme_vl
11227 09:30:00.203990 arm64:ssve_regs
11228 09:30:00.206852 arm64:sve_regs
11229 09:30:00.206933 arm64:sve_vl
11230 09:30:00.206996 arm64:za_no_regs
11231 09:30:00.210589 arm64:za_regs
11232 09:30:00.210685 arm64:pac
11233 09:30:00.213638 arm64:fp-stress
11234 09:30:00.213706 arm64:sve-ptrace
11235 09:30:00.217080 arm64:sve-probe-vls
11236 09:30:00.217148 arm64:vec-syscfg
11237 09:30:00.217207 arm64:za-fork
11238 09:30:00.220366 arm64:za-ptrace
11239 09:30:00.220435 arm64:check_buffer_fill
11240 09:30:00.223946 arm64:check_child_memory
11241 09:30:00.226760 arm64:check_gcr_el1_cswitch
11242 09:30:00.230325 arm64:check_ksm_options
11243 09:30:00.230393 arm64:check_mmap_options
11244 09:30:00.233592 arm64:check_prctl
11245 09:30:00.237507 arm64:check_tags_inclusion
11246 09:30:00.237582 arm64:check_user_mem
11247 09:30:00.237643 arm64:btitest
11248 09:30:00.240246 arm64:nobtitest
11249 09:30:00.240315 arm64:hwcap
11250 09:30:00.243779 arm64:ptrace
11251 09:30:00.243850 arm64:syscall-abi
11252 09:30:00.243911 arm64:tpidr2
11253 09:30:00.250159 ===========End Tests to run ===============
11254 09:30:00.250231 shardfile-arm64 pass
11255 09:30:00.534587 <12>[ 39.475216] kselftest: Running tests in arm64
11256 09:30:00.545783 TAP version 13
11257 09:30:00.559019 1..48
11258 09:30:00.578002 # selftests: arm64: tags_test
11259 09:30:01.035456 ok 1 selftests: arm64: tags_test
11260 09:30:01.053584 # selftests: arm64: run_tags_test.sh
11261 09:30:01.111017 # --------------------
11262 09:30:01.113703 # running tags test
11263 09:30:01.113796 # --------------------
11264 09:30:01.116908 # [PASS]
11265 09:30:01.120447 ok 2 selftests: arm64: run_tags_test.sh
11266 09:30:01.135441 # selftests: arm64: fake_sigreturn_bad_magic
11267 09:30:01.175410 # Registered handlers for all signals.
11268 09:30:01.175546 # Detected MINSTKSIGSZ:4720
11269 09:30:01.178659 # Testcase initialized.
11270 09:30:01.181848 # uc context validated.
11271 09:30:01.185246 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11272 09:30:01.188545 # Handled SIG_COPYCTX
11273 09:30:01.188632 # Available space:3568
11274 09:30:01.195205 # Using badly built context - ERR: BAD MAGIC !
11275 09:30:01.201765 # SIG_OK -- SP:0xFFFFED694C10 si_addr@:0xffffed694c10 si_code:2 token@:0xffffed6939b0 offset:-4704
11276 09:30:01.205354 # ==>> completed. PASS(1)
11277 09:30:01.212017 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11278 09:30:01.218686 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFED6939B0
11279 09:30:01.221949 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11280 09:30:01.228595 # selftests: arm64: fake_sigreturn_bad_size
11281 09:30:01.264593 # Registered handlers for all signals.
11282 09:30:01.265039 # Detected MINSTKSIGSZ:4720
11283 09:30:01.268220 # Testcase initialized.
11284 09:30:01.271306 # uc context validated.
11285 09:30:01.274786 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11286 09:30:01.278181 # Handled SIG_COPYCTX
11287 09:30:01.278623 # Available space:3568
11288 09:30:01.281503 # uc context validated.
11289 09:30:01.288213 # Using badly built context - ERR: Bad size for esr_context
11290 09:30:01.294847 # SIG_OK -- SP:0xFFFFD4168A70 si_addr@:0xffffd4168a70 si_code:2 token@:0xffffd4167810 offset:-4704
11291 09:30:01.297931 # ==>> completed. PASS(1)
11292 09:30:01.304546 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11293 09:30:01.311188 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD4167810
11294 09:30:01.314444 ok 4 selftests: arm64: fake_sigreturn_bad_size
11295 09:30:01.321238 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11296 09:30:01.362237 # Registered handlers for all signals.
11297 09:30:01.362686 # Detected MINSTKSIGSZ:4720
11298 09:30:01.365149 # Testcase initialized.
11299 09:30:01.368419 # uc context validated.
11300 09:30:01.371856 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11301 09:30:01.374946 # Handled SIG_COPYCTX
11302 09:30:01.375434 # Available space:3568
11303 09:30:01.381839 # Using badly built context - ERR: Bad size for terminator
11304 09:30:01.392064 # SIG_OK -- SP:0xFFFFDABADA20 si_addr@:0xffffdabada20 si_code:2 token@:0xffffdabac7c0 offset:-4704
11305 09:30:01.392638 # ==>> completed. PASS(1)
11306 09:30:01.401741 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11307 09:30:01.408529 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDABAC7C0
11308 09:30:01.411777 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11309 09:30:01.418433 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11310 09:30:01.470233 # Registered handlers for all signals.
11311 09:30:01.470693 # Detected MINSTKSIGSZ:4720
11312 09:30:01.473595 # Testcase initialized.
11313 09:30:01.476788 # uc context validated.
11314 09:30:01.480302 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11315 09:30:01.483514 # Handled SIG_COPYCTX
11316 09:30:01.483984 # Available space:3568
11317 09:30:01.489821 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11318 09:30:01.500236 # SIG_OK -- SP:0xFFFFC110D250 si_addr@:0xffffc110d250 si_code:2 token@:0xffffc110bff0 offset:-4704
11319 09:30:01.500768 # ==>> completed. PASS(1)
11320 09:30:01.509853 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11321 09:30:01.516855 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC110BFF0
11322 09:30:01.520366 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11323 09:30:01.523690 # selftests: arm64: fake_sigreturn_misaligned_sp
11324 09:30:01.567825 # Registered handlers for all signals.
11325 09:30:01.568453 # Detected MINSTKSIGSZ:4720
11326 09:30:01.570908 # Testcase initialized.
11327 09:30:01.574194 # uc context validated.
11328 09:30:01.577809 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11329 09:30:01.581372 # Handled SIG_COPYCTX
11330 09:30:01.587423 # SIG_OK -- SP:0xFFFFED123C93 si_addr@:0xffffed123c93 si_code:2 token@:0xffffed123c93 offset:0
11331 09:30:01.590695 # ==>> completed. PASS(1)
11332 09:30:01.597375 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11333 09:30:01.603837 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFED123C93
11334 09:30:01.610875 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11335 09:30:01.613879 # selftests: arm64: fake_sigreturn_missing_fpsimd
11336 09:30:01.660827 # Registered handlers for all signals.
11337 09:30:01.661360 # Detected MINSTKSIGSZ:4720
11338 09:30:01.663999 # Testcase initialized.
11339 09:30:01.667294 # uc context validated.
11340 09:30:01.670476 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11341 09:30:01.674088 # Handled SIG_COPYCTX
11342 09:30:01.677354 # Mangling template header. Spare space:4096
11343 09:30:01.680263 # Using badly built context - ERR: Missing FPSIMD
11344 09:30:01.690534 # SIG_OK -- SP:0xFFFFEDB02240 si_addr@:0xffffedb02240 si_code:2 token@:0xffffedb00fe0 offset:-4704
11345 09:30:01.693819 # ==>> completed. PASS(1)
11346 09:30:01.700694 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11347 09:30:01.707083 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEDB00FE0
11348 09:30:01.710174 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11349 09:30:01.717304 # selftests: arm64: fake_sigreturn_sme_change_vl
11350 09:30:01.753478 # Registered handlers for all signals.
11351 09:30:01.753937 # Detected MINSTKSIGSZ:4720
11352 09:30:01.757056 # ==>> completed. SKIP.
11353 09:30:01.763751 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11354 09:30:01.766882 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11355 09:30:01.776618 # selftests: arm64: fake_sigreturn_sve_change_vl
11356 09:30:01.849537 # Registered handlers for all signals.
11357 09:30:01.850002 # Detected MINSTKSIGSZ:4720
11358 09:30:01.853041 # ==>> completed. SKIP.
11359 09:30:01.859295 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11360 09:30:01.862785 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11361 09:30:01.873979 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11362 09:30:01.931862 # Registered handlers for all signals.
11363 09:30:01.932340 # Detected MINSTKSIGSZ:4720
11364 09:30:01.934885 # Testcase initialized.
11365 09:30:01.938523 # uc context validated.
11366 09:30:01.939030 # Handled SIG_TRIG
11367 09:30:01.948256 # SIG_OK -- SP:0xFFFFF4DA6AF0 si_addr@:0xfffff4da6af0 si_code:2 token@:(nil) offset:-281474789698288
11368 09:30:01.951409 # ==>> completed. PASS(1)
11369 09:30:01.957969 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11370 09:30:01.964514 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11371 09:30:01.967841 # selftests: arm64: mangle_pstate_invalid_daif_bits
11372 09:30:02.026536 # Registered handlers for all signals.
11373 09:30:02.027189 # Detected MINSTKSIGSZ:4720
11374 09:30:02.029443 # Testcase initialized.
11375 09:30:02.032732 # uc context validated.
11376 09:30:02.033327 # Handled SIG_TRIG
11377 09:30:02.043527 # SIG_OK -- SP:0xFFFFCCD14170 si_addr@:0xffffccd14170 si_code:2 token@:(nil) offset:-281474118009200
11378 09:30:02.046356 # ==>> completed. PASS(1)
11379 09:30:02.052851 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11380 09:30:02.056151 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11381 09:30:02.062697 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11382 09:30:02.116987 # Registered handlers for all signals.
11383 09:30:02.117424 # Detected MINSTKSIGSZ:4720
11384 09:30:02.120290 # Testcase initialized.
11385 09:30:02.123737 # uc context validated.
11386 09:30:02.124180 # Handled SIG_TRIG
11387 09:30:02.133759 # SIG_OK -- SP:0xFFFFC8D17430 si_addr@:0xffffc8d17430 si_code:2 token@:(nil) offset:-281474050913328
11388 09:30:02.136969 # ==>> completed. PASS(1)
11389 09:30:02.144213 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11390 09:30:02.147090 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11391 09:30:02.153527 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11392 09:30:02.185799 # Registered handlers for all signals.
11393 09:30:02.186242 # Detected MINSTKSIGSZ:4720
11394 09:30:02.189303 # Testcase initialized.
11395 09:30:02.192377 # uc context validated.
11396 09:30:02.192815 # Handled SIG_TRIG
11397 09:30:02.202424 # SIG_OK -- SP:0xFFFFEF8DE380 si_addr@:0xffffef8de380 si_code:2 token@:(nil) offset:-281474700796800
11398 09:30:02.205924 # ==>> completed. PASS(1)
11399 09:30:02.212414 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11400 09:30:02.215897 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11401 09:30:02.221735 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11402 09:30:02.276435 # Registered handlers for all signals.
11403 09:30:02.276564 # Detected MINSTKSIGSZ:4720
11404 09:30:02.279708 # Testcase initialized.
11405 09:30:02.282651 # uc context validated.
11406 09:30:02.282795 # Handled SIG_TRIG
11407 09:30:02.292640 # SIG_OK -- SP:0xFFFFFD8069C0 si_addr@:0xfffffd8069c0 si_code:2 token@:(nil) offset:-281474934794688
11408 09:30:02.296342 # ==>> completed. PASS(1)
11409 09:30:02.302760 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11410 09:30:02.305856 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11411 09:30:02.312665 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11412 09:30:02.366707 # Registered handlers for all signals.
11413 09:30:02.366879 # Detected MINSTKSIGSZ:4720
11414 09:30:02.369546 # Testcase initialized.
11415 09:30:02.373300 # uc context validated.
11416 09:30:02.373384 # Handled SIG_TRIG
11417 09:30:02.383036 # SIG_OK -- SP:0xFFFFFF8C2BC0 si_addr@:0xffffff8c2bc0 si_code:2 token@:(nil) offset:-281474969119680
11418 09:30:02.386271 # ==>> completed. PASS(1)
11419 09:30:02.393071 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11420 09:30:02.396595 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11421 09:30:02.402620 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11422 09:30:02.456830 # Registered handlers for all signals.
11423 09:30:02.456971 # Detected MINSTKSIGSZ:4720
11424 09:30:02.459762 # Testcase initialized.
11425 09:30:02.462676 # uc context validated.
11426 09:30:02.462851 # Handled SIG_TRIG
11427 09:30:02.472713 # SIG_OK -- SP:0xFFFFF5AC8680 si_addr@:0xfffff5ac8680 si_code:2 token@:(nil) offset:-281474803467904
11428 09:30:02.476026 # ==>> completed. PASS(1)
11429 09:30:02.482601 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11430 09:30:02.486161 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11431 09:30:02.492891 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11432 09:30:02.540716 # Registered handlers for all signals.
11433 09:30:02.540858 # Detected MINSTKSIGSZ:4720
11434 09:30:02.543749 # Testcase initialized.
11435 09:30:02.547094 # uc context validated.
11436 09:30:02.547182 # Handled SIG_TRIG
11437 09:30:02.556845 # SIG_OK -- SP:0xFFFFE97838A0 si_addr@:0xffffe97838a0 si_code:2 token@:(nil) offset:-281474598713504
11438 09:30:02.560383 # ==>> completed. PASS(1)
11439 09:30:02.567095 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11440 09:30:02.570265 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11441 09:30:02.573448 # selftests: arm64: sme_trap_no_sm
11442 09:30:02.626553 # Registered handlers for all signals.
11443 09:30:02.626715 # Detected MINSTKSIGSZ:4720
11444 09:30:02.629943 # ==>> completed. SKIP.
11445 09:30:02.639790 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11446 09:30:02.643703 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11447 09:30:02.646415 # selftests: arm64: sme_trap_non_streaming
11448 09:30:02.714252 # Registered handlers for all signals.
11449 09:30:02.714421 # Detected MINSTKSIGSZ:4720
11450 09:30:02.717812 # ==>> completed. SKIP.
11451 09:30:02.727749 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11452 09:30:02.734335 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11453 09:30:02.739422 # selftests: arm64: sme_trap_za
11454 09:30:02.799723 # Registered handlers for all signals.
11455 09:30:02.799871 # Detected MINSTKSIGSZ:4720
11456 09:30:02.803386 # Testcase initialized.
11457 09:30:02.813620 # SIG_OK -- SP:0xFFFFCD52E7D0 si_addr@:0xaaaac7e62510 si_code:1 token@:(nil) offset:-187650474910992
11458 09:30:02.813729 # ==>> completed. PASS(1)
11459 09:30:02.823359 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11460 09:30:02.823481 ok 21 selftests: arm64: sme_trap_za
11461 09:30:02.826495 # selftests: arm64: sme_vl
11462 09:30:02.893408 # Registered handlers for all signals.
11463 09:30:02.893552 # Detected MINSTKSIGSZ:4720
11464 09:30:02.896606 # ==>> completed. SKIP.
11465 09:30:02.903128 # # SME VL :: Check that we get the right SME VL reported
11466 09:30:02.906187 ok 22 selftests: arm64: sme_vl # SKIP
11467 09:30:02.916422 # selftests: arm64: ssve_regs
11468 09:30:02.979160 # Registered handlers for all signals.
11469 09:30:02.979336 # Detected MINSTKSIGSZ:4720
11470 09:30:02.982470 # ==>> completed. SKIP.
11471 09:30:02.989080 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11472 09:30:02.992711 ok 23 selftests: arm64: ssve_regs # SKIP
11473 09:30:02.996000 # selftests: arm64: sve_regs
11474 09:30:03.066925 # Registered handlers for all signals.
11475 09:30:03.067066 # Detected MINSTKSIGSZ:4720
11476 09:30:03.069952 # ==>> completed. SKIP.
11477 09:30:03.076805 # # SVE registers :: Check that we get the right SVE registers reported
11478 09:30:03.079945 ok 24 selftests: arm64: sve_regs # SKIP
11479 09:30:03.088414 # selftests: arm64: sve_vl
11480 09:30:03.146011 # Registered handlers for all signals.
11481 09:30:03.146187 # Detected MINSTKSIGSZ:4720
11482 09:30:03.150226 # ==>> completed. SKIP.
11483 09:30:03.156208 # # SVE VL :: Check that we get the right SVE VL reported
11484 09:30:03.159353 ok 25 selftests: arm64: sve_vl # SKIP
11485 09:30:03.164650 # selftests: arm64: za_no_regs
11486 09:30:03.244751 # Registered handlers for all signals.
11487 09:30:03.244923 # Detected MINSTKSIGSZ:4720
11488 09:30:03.248201 # ==>> completed. SKIP.
11489 09:30:03.254648 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11490 09:30:03.257982 ok 26 selftests: arm64: za_no_regs # SKIP
11491 09:30:03.262498 # selftests: arm64: za_regs
11492 09:30:03.323076 # Registered handlers for all signals.
11493 09:30:03.323243 # Detected MINSTKSIGSZ:4720
11494 09:30:03.326317 # ==>> completed. SKIP.
11495 09:30:03.333133 # # ZA register :: Check that we get the right ZA registers reported
11496 09:30:03.336454 ok 27 selftests: arm64: za_regs # SKIP
11497 09:30:03.340165 # selftests: arm64: pac
11498 09:30:03.400645 # TAP version 13
11499 09:30:03.400792 # 1..7
11500 09:30:03.403560 # # Starting 7 tests from 1 test cases.
11501 09:30:03.407046 # # RUN global.corrupt_pac ...
11502 09:30:03.410292 # # SKIP PAUTH not enabled
11503 09:30:03.413132 # # OK global.corrupt_pac
11504 09:30:03.416919 # ok 1 # SKIP PAUTH not enabled
11505 09:30:03.423467 # # RUN global.pac_instructions_not_nop ...
11506 09:30:03.426546 # # SKIP PAUTH not enabled
11507 09:30:03.430259 # # OK global.pac_instructions_not_nop
11508 09:30:03.433353 # ok 2 # SKIP PAUTH not enabled
11509 09:30:03.440144 # # RUN global.pac_instructions_not_nop_generic ...
11510 09:30:03.443651 # # SKIP Generic PAUTH not enabled
11511 09:30:03.446502 # # OK global.pac_instructions_not_nop_generic
11512 09:30:03.450026 # ok 3 # SKIP Generic PAUTH not enabled
11513 09:30:03.456813 # # RUN global.single_thread_different_keys ...
11514 09:30:03.460082 # # SKIP PAUTH not enabled
11515 09:30:03.463364 # # OK global.single_thread_different_keys
11516 09:30:03.466588 # ok 4 # SKIP PAUTH not enabled
11517 09:30:03.473666 # # RUN global.exec_changed_keys ...
11518 09:30:03.473749 # # SKIP PAUTH not enabled
11519 09:30:03.480085 # # OK global.exec_changed_keys
11520 09:30:03.483419 # ok 5 # SKIP PAUTH not enabled
11521 09:30:03.487388 # # RUN global.context_switch_keep_keys ...
11522 09:30:03.490305 # # SKIP PAUTH not enabled
11523 09:30:03.493824 # # OK global.context_switch_keep_keys
11524 09:30:03.496741 # ok 6 # SKIP PAUTH not enabled
11525 09:30:03.503713 # # RUN global.context_switch_keep_keys_generic ...
11526 09:30:03.506949 # # SKIP Generic PAUTH not enabled
11527 09:30:03.513502 # # OK global.context_switch_keep_keys_generic
11528 09:30:03.517102 # ok 7 # SKIP Generic PAUTH not enabled
11529 09:30:03.520181 # # PASSED: 7 / 7 tests passed.
11530 09:30:03.523470 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11531 09:30:03.526843 ok 28 selftests: arm64: pac
11532 09:30:03.529862 # selftests: arm64: fp-stress
11533 09:30:07.213957 <6>[ 46.158314] vpu: disabling
11534 09:30:07.217341 <6>[ 46.161361] vproc2: disabling
11535 09:30:07.220292 <6>[ 46.164634] vproc1: disabling
11536 09:30:07.223700 <6>[ 46.167905] vaud18: disabling
11537 09:30:07.230996 <6>[ 46.171323] vsram_others: disabling
11538 09:30:07.231080 <6>[ 46.175206] va09: disabling
11539 09:30:07.237347 <6>[ 46.178320] vsram_md: disabling
11540 09:30:07.237431 <6>[ 46.181813] Vgpu: disabling
11541 09:30:13.478643 # TAP version 13
11542 09:30:13.478842 # 1..16
11543 09:30:13.481602 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11544 09:30:13.484867 # # Will run for 10s
11545 09:30:13.484976 # # Started FPSIMD-0-0
11546 09:30:13.487978 # # Started FPSIMD-0-1
11547 09:30:13.491456 # # Started FPSIMD-1-0
11548 09:30:13.491573 # # Started FPSIMD-1-1
11549 09:30:13.494469 # # Started FPSIMD-2-0
11550 09:30:13.497711 # # Started FPSIMD-2-1
11551 09:30:13.497817 # # Started FPSIMD-3-0
11552 09:30:13.501164 # # Started FPSIMD-3-1
11553 09:30:13.501273 # # Started FPSIMD-4-0
11554 09:30:13.504740 # # Started FPSIMD-4-1
11555 09:30:13.507768 # # Started FPSIMD-5-0
11556 09:30:13.507881 # # Started FPSIMD-5-1
11557 09:30:13.511458 # # Started FPSIMD-6-0
11558 09:30:13.514636 # # Started FPSIMD-6-1
11559 09:30:13.514763 # # Started FPSIMD-7-0
11560 09:30:13.517898 # # Started FPSIMD-7-1
11561 09:30:13.521297 # # FPSIMD-0-0: Vector length: 128 bits
11562 09:30:13.524385 # # FPSIMD-0-0: PID: 1163
11563 09:30:13.527835 # # FPSIMD-0-1: Vector length: 128 bits
11564 09:30:13.527952 # # FPSIMD-0-1: PID: 1164
11565 09:30:13.531158 # # FPSIMD-1-0: Vector length: 128 bits
11566 09:30:13.534466 # # FPSIMD-1-0: PID: 1165
11567 09:30:13.538032 # # FPSIMD-2-1: Vector length: 128 bits
11568 09:30:13.541292 # # FPSIMD-2-1: PID: 1168
11569 09:30:13.544693 # # FPSIMD-5-0: Vector length: 128 bits
11570 09:30:13.547880 # # FPSIMD-5-0: PID: 1173
11571 09:30:13.551276 # # FPSIMD-4-1: Vector length: 128 bits
11572 09:30:13.551392 # # FPSIMD-4-1: PID: 1172
11573 09:30:13.557876 # # FPSIMD-2-0: Vector length: 128 bits
11574 09:30:13.557982 # # FPSIMD-2-0: PID: 1167
11575 09:30:13.561253 # # FPSIMD-3-0: Vector length: 128 bits
11576 09:30:13.564668 # # FPSIMD-3-0: PID: 1169
11577 09:30:13.568207 # # FPSIMD-4-0: Vector length: 128 bits
11578 09:30:13.571210 # # FPSIMD-4-0: PID: 1171
11579 09:30:13.574496 # # FPSIMD-6-0: Vector length: 128 bits
11580 09:30:13.578079 # # FPSIMD-6-0: PID: 1175
11581 09:30:13.581532 # # FPSIMD-3-1: Vector length: 128 bits
11582 09:30:13.581640 # # FPSIMD-3-1: PID: 1170
11583 09:30:13.584906 # # FPSIMD-5-1: Vector length: 128 bits
11584 09:30:13.588138 # # FPSIMD-5-1: PID: 1174
11585 09:30:13.591670 # # FPSIMD-7-0: Vector length: 128 bits
11586 09:30:13.594597 # # FPSIMD-7-0: PID: 1177
11587 09:30:13.598155 # # FPSIMD-1-1: Vector length: 128 bits
11588 09:30:13.601351 # # FPSIMD-1-1: PID: 1166
11589 09:30:13.604616 # # FPSIMD-7-1: Vector length: 128 bits
11590 09:30:13.604726 # # FPSIMD-7-1: PID: 1178
11591 09:30:13.607971 # # FPSIMD-6-1: Vector length: 128 bits
11592 09:30:13.611234 # # FPSIMD-6-1: PID: 1176
11593 09:30:13.614714 # # Finishing up...
11594 09:30:13.614868 # ok 1 FPSIMD-0-0
11595 09:30:13.618003 # ok 2 FPSIMD-0-1
11596 09:30:13.618112 # ok 3 FPSIMD-1-0
11597 09:30:13.621230 # ok 4 FPSIMD-1-1
11598 09:30:13.621339 # ok 5 FPSIMD-2-0
11599 09:30:13.624623 # ok 6 FPSIMD-2-1
11600 09:30:13.624734 # ok 7 FPSIMD-3-0
11601 09:30:13.628188 # ok 8 FPSIMD-3-1
11602 09:30:13.628300 # ok 9 FPSIMD-4-0
11603 09:30:13.631033 # ok 10 FPSIMD-4-1
11604 09:30:13.631136 # ok 11 FPSIMD-5-0
11605 09:30:13.634387 # ok 12 FPSIMD-5-1
11606 09:30:13.634493 # ok 13 FPSIMD-6-0
11607 09:30:13.638061 # ok 14 FPSIMD-6-1
11608 09:30:13.638180 # ok 15 FPSIMD-7-0
11609 09:30:13.641193 # ok 16 FPSIMD-7-1
11610 09:30:13.647495 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1029699, signals=10
11611 09:30:13.654299 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=2015932, signals=10
11612 09:30:13.661174 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1144605, signals=10
11613 09:30:13.670928 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=2100528, signals=10
11614 09:30:13.677247 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1632591, signals=10
11615 09:30:13.684603 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2017221, signals=10
11616 09:30:13.690956 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=962329, signals=10
11617 09:30:13.697098 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1195626, signals=9
11618 09:30:13.704268 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1152747, signals=9
11619 09:30:13.710715 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=973823, signals=10
11620 09:30:13.720465 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1156703, signals=10
11621 09:30:13.727100 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1024190, signals=10
11622 09:30:13.733881 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=947379, signals=10
11623 09:30:13.740498 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=965930, signals=10
11624 09:30:13.747188 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1237107, signals=9
11625 09:30:13.753768 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=926030, signals=10
11626 09:30:13.760606 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11627 09:30:13.763869 ok 29 selftests: arm64: fp-stress
11628 09:30:13.767193 # selftests: arm64: sve-ptrace
11629 09:30:13.767305 # TAP version 13
11630 09:30:13.767406 # 1..4104
11631 09:30:13.770344 # ok 2 # SKIP SVE not available
11632 09:30:13.773655 # # Planned tests != run tests (4104 != 1)
11633 09:30:13.780368 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11634 09:30:13.783651 ok 30 selftests: arm64: sve-ptrace # SKIP
11635 09:30:13.787121 # selftests: arm64: sve-probe-vls
11636 09:30:13.787238 # TAP version 13
11637 09:30:13.790795 # 1..2
11638 09:30:13.793484 # ok 2 # SKIP SVE not available
11639 09:30:13.797177 # # Planned tests != run tests (2 != 1)
11640 09:30:13.800460 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11641 09:30:13.803566 ok 31 selftests: arm64: sve-probe-vls # SKIP
11642 09:30:13.807388 # selftests: arm64: vec-syscfg
11643 09:30:13.810486 # TAP version 13
11644 09:30:13.810598 # 1..20
11645 09:30:13.813766 # ok 1 # SKIP SVE not supported
11646 09:30:13.817733 # ok 2 # SKIP SVE not supported
11647 09:30:13.817846 # ok 3 # SKIP SVE not supported
11648 09:30:13.820639 # ok 4 # SKIP SVE not supported
11649 09:30:13.823471 # ok 5 # SKIP SVE not supported
11650 09:30:13.826837 # ok 6 # SKIP SVE not supported
11651 09:30:13.830503 # ok 7 # SKIP SVE not supported
11652 09:30:13.833539 # ok 8 # SKIP SVE not supported
11653 09:30:13.837008 # ok 9 # SKIP SVE not supported
11654 09:30:13.840572 # ok 10 # SKIP SVE not supported
11655 09:30:13.840690 # ok 11 # SKIP SME not supported
11656 09:30:13.843461 # ok 12 # SKIP SME not supported
11657 09:30:13.846748 # ok 13 # SKIP SME not supported
11658 09:30:13.849894 # ok 14 # SKIP SME not supported
11659 09:30:13.853265 # ok 15 # SKIP SME not supported
11660 09:30:13.856848 # ok 16 # SKIP SME not supported
11661 09:30:13.859839 # ok 17 # SKIP SME not supported
11662 09:30:13.863289 # ok 18 # SKIP SME not supported
11663 09:30:13.866781 # ok 19 # SKIP SME not supported
11664 09:30:13.866889 # ok 20 # SKIP SME not supported
11665 09:30:13.873368 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11666 09:30:13.876543 ok 32 selftests: arm64: vec-syscfg
11667 09:30:13.879978 # selftests: arm64: za-fork
11668 09:30:13.880060 # TAP version 13
11669 09:30:13.880152 # 1..1
11670 09:30:13.883092 # # PID: 1253
11671 09:30:13.886374 # # SME support not present
11672 09:30:13.886483 # ok 0 skipped
11673 09:30:13.889903 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11674 09:30:13.892899 ok 33 selftests: arm64: za-fork
11675 09:30:13.896409 # selftests: arm64: za-ptrace
11676 09:30:13.909688 # TAP version 13
11677 09:30:13.909849 # 1..1
11678 09:30:13.913190 # ok 2 # SKIP SME not available
11679 09:30:13.920038 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11680 09:30:13.923222 ok 34 selftests: arm64: za-ptrace # SKIP
11681 09:30:13.933858 # selftests: arm64: check_buffer_fill
11682 09:30:13.983160 # # SKIP: MTE features unavailable
11683 09:30:13.989850 ok 35 selftests: arm64: check_buffer_fill # SKIP
11684 09:30:14.004979 # selftests: arm64: check_child_memory
11685 09:30:14.063132 # # SKIP: MTE features unavailable
11686 09:30:14.071278 ok 36 selftests: arm64: check_child_memory # SKIP
11687 09:30:14.087736 # selftests: arm64: check_gcr_el1_cswitch
11688 09:30:14.188083 # # SKIP: MTE features unavailable
11689 09:30:14.195886 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11690 09:30:14.214123 # selftests: arm64: check_ksm_options
11691 09:30:14.267401 # # SKIP: MTE features unavailable
11692 09:30:14.274689 ok 38 selftests: arm64: check_ksm_options # SKIP
11693 09:30:14.294619 # selftests: arm64: check_mmap_options
11694 09:30:14.364690 # # SKIP: MTE features unavailable
11695 09:30:14.372127 ok 39 selftests: arm64: check_mmap_options # SKIP
11696 09:30:14.386867 # selftests: arm64: check_prctl
11697 09:30:14.462047 # TAP version 13
11698 09:30:14.462204 # 1..5
11699 09:30:14.465235 # ok 1 check_basic_read
11700 09:30:14.465323 # ok 2 NONE
11701 09:30:14.468813 # ok 3 # SKIP SYNC
11702 09:30:14.468906 # ok 4 # SKIP ASYNC
11703 09:30:14.471768 # ok 5 # SKIP SYNC+ASYNC
11704 09:30:14.475069 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11705 09:30:14.478378 ok 40 selftests: arm64: check_prctl
11706 09:30:14.492051 # selftests: arm64: check_tags_inclusion
11707 09:30:14.554293 # # SKIP: MTE features unavailable
11708 09:30:14.562595 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11709 09:30:14.575855 # selftests: arm64: check_user_mem
11710 09:30:14.643895 # # SKIP: MTE features unavailable
11711 09:30:14.652587 ok 42 selftests: arm64: check_user_mem # SKIP
11712 09:30:14.666417 # selftests: arm64: btitest
11713 09:30:14.711166 # TAP version 13
11714 09:30:14.711324 # 1..18
11715 09:30:14.714396 # # HWCAP_PACA not present
11716 09:30:14.717627 # # HWCAP2_BTI not present
11717 09:30:14.717717 # # Test binary built for BTI
11718 09:30:14.724384 # ok 1 nohint_func/call_using_br_x0 # SKIP
11719 09:30:14.727471 # ok 1 nohint_func/call_using_br_x16 # SKIP
11720 09:30:14.730664 # ok 1 nohint_func/call_using_blr # SKIP
11721 09:30:14.734485 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11722 09:30:14.737763 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11723 09:30:14.740617 # ok 1 bti_none_func/call_using_blr # SKIP
11724 09:30:14.747135 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11725 09:30:14.751183 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11726 09:30:14.754006 # ok 1 bti_c_func/call_using_blr # SKIP
11727 09:30:14.757180 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11728 09:30:14.760945 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11729 09:30:14.764217 # ok 1 bti_j_func/call_using_blr # SKIP
11730 09:30:14.767379 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11731 09:30:14.773970 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11732 09:30:14.777402 # ok 1 bti_jc_func/call_using_blr # SKIP
11733 09:30:14.780922 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11734 09:30:14.783706 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11735 09:30:14.787079 # ok 1 paciasp_func/call_using_blr # SKIP
11736 09:30:14.793925 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11737 09:30:14.797754 # # WARNING - EXPECTED TEST COUNT WRONG
11738 09:30:14.800355 ok 43 selftests: arm64: btitest
11739 09:30:14.800442 # selftests: arm64: nobtitest
11740 09:30:14.807513 # TAP version 13
11741 09:30:14.807620 # 1..18
11742 09:30:14.810973 # # HWCAP_PACA not present
11743 09:30:14.814214 # # HWCAP2_BTI not present
11744 09:30:14.817592 # # Test binary not built for BTI
11745 09:30:14.820736 # ok 1 nohint_func/call_using_br_x0 # SKIP
11746 09:30:14.823962 # ok 1 nohint_func/call_using_br_x16 # SKIP
11747 09:30:14.827434 # ok 1 nohint_func/call_using_blr # SKIP
11748 09:30:14.830947 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11749 09:30:14.833892 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11750 09:30:14.841002 # ok 1 bti_none_func/call_using_blr # SKIP
11751 09:30:14.843899 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11752 09:30:14.848152 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11753 09:30:14.850729 # ok 1 bti_c_func/call_using_blr # SKIP
11754 09:30:14.854196 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11755 09:30:14.857365 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11756 09:30:14.860941 # ok 1 bti_j_func/call_using_blr # SKIP
11757 09:30:14.863941 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11758 09:30:14.870888 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11759 09:30:14.874019 # ok 1 bti_jc_func/call_using_blr # SKIP
11760 09:30:14.877636 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11761 09:30:14.881128 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11762 09:30:14.884294 # ok 1 paciasp_func/call_using_blr # SKIP
11763 09:30:14.890887 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11764 09:30:14.894162 # # WARNING - EXPECTED TEST COUNT WRONG
11765 09:30:14.897249 ok 44 selftests: arm64: nobtitest
11766 09:30:14.897340 # selftests: arm64: hwcap
11767 09:30:14.900587 # TAP version 13
11768 09:30:14.900672 # 1..28
11769 09:30:14.904498 # ok 1 cpuinfo_match_RNG
11770 09:30:14.907178 # # SIGILL reported for RNG
11771 09:30:14.907269 # ok 2 # SKIP sigill_RNG
11772 09:30:14.911071 # ok 3 cpuinfo_match_SME
11773 09:30:14.911157 # ok 4 sigill_SME
11774 09:30:14.914301 # ok 5 cpuinfo_match_SVE
11775 09:30:14.917264 # ok 6 sigill_SVE
11776 09:30:14.917349 # ok 7 cpuinfo_match_SVE 2
11777 09:30:14.921037 # # SIGILL reported for SVE 2
11778 09:30:14.923818 # ok 8 # SKIP sigill_SVE 2
11779 09:30:14.927050 # ok 9 cpuinfo_match_SVE AES
11780 09:30:14.927134 # # SIGILL reported for SVE AES
11781 09:30:14.930605 # ok 10 # SKIP sigill_SVE AES
11782 09:30:14.933767 # ok 11 cpuinfo_match_SVE2 PMULL
11783 09:30:14.937129 # # SIGILL reported for SVE2 PMULL
11784 09:30:14.941059 # ok 12 # SKIP sigill_SVE2 PMULL
11785 09:30:14.944132 # ok 13 cpuinfo_match_SVE2 BITPERM
11786 09:30:14.947078 # # SIGILL reported for SVE2 BITPERM
11787 09:30:14.950896 # ok 14 # SKIP sigill_SVE2 BITPERM
11788 09:30:14.953568 # ok 15 cpuinfo_match_SVE2 SHA3
11789 09:30:14.957321 # # SIGILL reported for SVE2 SHA3
11790 09:30:14.960254 # ok 16 # SKIP sigill_SVE2 SHA3
11791 09:30:14.960342 # ok 17 cpuinfo_match_SVE2 SM4
11792 09:30:14.963491 # # SIGILL reported for SVE2 SM4
11793 09:30:14.967081 # ok 18 # SKIP sigill_SVE2 SM4
11794 09:30:14.970166 # ok 19 cpuinfo_match_SVE2 I8MM
11795 09:30:14.973835 # # SIGILL reported for SVE2 I8MM
11796 09:30:14.977023 # ok 20 # SKIP sigill_SVE2 I8MM
11797 09:30:14.980404 # ok 21 cpuinfo_match_SVE2 F32MM
11798 09:30:14.983578 # # SIGILL reported for SVE2 F32MM
11799 09:30:14.983667 # ok 22 # SKIP sigill_SVE2 F32MM
11800 09:30:14.986706 # ok 23 cpuinfo_match_SVE2 F64MM
11801 09:30:14.990442 # # SIGILL reported for SVE2 F64MM
11802 09:30:14.993916 # ok 24 # SKIP sigill_SVE2 F64MM
11803 09:30:14.996866 # ok 25 cpuinfo_match_SVE2 BF16
11804 09:30:14.999999 # # SIGILL reported for SVE2 BF16
11805 09:30:15.003752 # ok 26 # SKIP sigill_SVE2 BF16
11806 09:30:15.006930 # ok 27 cpuinfo_match_SVE2 EBF16
11807 09:30:15.010109 # ok 28 # SKIP sigill_SVE2 EBF16
11808 09:30:15.013566 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11809 09:30:15.016492 ok 45 selftests: arm64: hwcap
11810 09:30:15.020220 # selftests: arm64: ptrace
11811 09:30:15.020301 # TAP version 13
11812 09:30:15.020365 # 1..7
11813 09:30:15.023751 # # Parent is 1495, child is 1496
11814 09:30:15.026646 # ok 1 read_tpidr_one
11815 09:30:15.029927 # ok 2 write_tpidr_one
11816 09:30:15.030011 # ok 3 verify_tpidr_one
11817 09:30:15.033194 # ok 4 count_tpidrs
11818 09:30:15.033281 # ok 5 tpidr2_write
11819 09:30:15.036954 # ok 6 tpidr2_read
11820 09:30:15.037036 # ok 7 write_tpidr_only
11821 09:30:15.043342 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11822 09:30:15.046551 ok 46 selftests: arm64: ptrace
11823 09:30:15.049984 # selftests: arm64: syscall-abi
11824 09:30:15.057063 # TAP version 13
11825 09:30:15.057177 # 1..2
11826 09:30:15.059973 # ok 1 getpid() FPSIMD
11827 09:30:15.063564 # ok 2 sched_yield() FPSIMD
11828 09:30:15.066860 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11829 09:30:15.069866 ok 47 selftests: arm64: syscall-abi
11830 09:30:15.078443 # selftests: arm64: tpidr2
11831 09:30:15.135719 # TAP version 13
11832 09:30:15.135877 # 1..5
11833 09:30:15.138844 # # PID: 1532
11834 09:30:15.138929 # # SME support not present
11835 09:30:15.142595 # ok 0 skipped, TPIDR2 not supported
11836 09:30:15.145499 # ok 1 skipped, TPIDR2 not supported
11837 09:30:15.148920 # ok 2 skipped, TPIDR2 not supported
11838 09:30:15.152343 # ok 3 skipped, TPIDR2 not supported
11839 09:30:15.155483 # ok 4 skipped, TPIDR2 not supported
11840 09:30:15.162282 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11841 09:30:15.165527 ok 48 selftests: arm64: tpidr2
11842 09:30:15.817941 arm64_tags_test pass
11843 09:30:15.821678 arm64_run_tags_test_sh pass
11844 09:30:15.824761 arm64_fake_sigreturn_bad_magic pass
11845 09:30:15.827836 arm64_fake_sigreturn_bad_size pass
11846 09:30:15.831314 arm64_fake_sigreturn_bad_size_for_magic0 pass
11847 09:30:15.834640 arm64_fake_sigreturn_duplicated_fpsimd pass
11848 09:30:15.837680 arm64_fake_sigreturn_misaligned_sp pass
11849 09:30:15.841455 arm64_fake_sigreturn_missing_fpsimd pass
11850 09:30:15.844434 arm64_fake_sigreturn_sme_change_vl skip
11851 09:30:15.847913 arm64_fake_sigreturn_sve_change_vl skip
11852 09:30:15.854612 arm64_mangle_pstate_invalid_compat_toggle pass
11853 09:30:15.858282 arm64_mangle_pstate_invalid_daif_bits pass
11854 09:30:15.861519 arm64_mangle_pstate_invalid_mode_el1h pass
11855 09:30:15.864468 arm64_mangle_pstate_invalid_mode_el1t pass
11856 09:30:15.868242 arm64_mangle_pstate_invalid_mode_el2h pass
11857 09:30:15.870992 arm64_mangle_pstate_invalid_mode_el2t pass
11858 09:30:15.877671 arm64_mangle_pstate_invalid_mode_el3h pass
11859 09:30:15.880805 arm64_mangle_pstate_invalid_mode_el3t pass
11860 09:30:15.880888 arm64_sme_trap_no_sm skip
11861 09:30:15.885148 arm64_sme_trap_non_streaming skip
11862 09:30:15.888049 arm64_sme_trap_za pass
11863 09:30:15.891598 arm64_sme_vl skip
11864 09:30:15.891681 arm64_ssve_regs skip
11865 09:30:15.894243 arm64_sve_regs skip
11866 09:30:15.894324 arm64_sve_vl skip
11867 09:30:15.897895 arm64_za_no_regs skip
11868 09:30:15.897996 arm64_za_regs skip
11869 09:30:15.901049 arm64_pac_pauth_not_enabled skip
11870 09:30:15.904596 arm64_pac_pauth_not_enabled skip
11871 09:30:15.907796 arm64_pac_generic_pauth_not_enabled skip
11872 09:30:15.910943 arm64_pac_pauth_not_enabled skip
11873 09:30:15.914562 arm64_pac_pauth_not_enabled skip
11874 09:30:15.917891 arm64_pac_pauth_not_enabled skip
11875 09:30:15.920709 arm64_pac_generic_pauth_not_enabled skip
11876 09:30:15.920815 arm64_pac pass
11877 09:30:15.924160 arm64_fp-stress_FPSIMD-0-0 pass
11878 09:30:15.927623 arm64_fp-stress_FPSIMD-0-1 pass
11879 09:30:15.930759 arm64_fp-stress_FPSIMD-1-0 pass
11880 09:30:15.934450 arm64_fp-stress_FPSIMD-1-1 pass
11881 09:30:15.937439 arm64_fp-stress_FPSIMD-2-0 pass
11882 09:30:15.937541 arm64_fp-stress_FPSIMD-2-1 pass
11883 09:30:15.940920 arm64_fp-stress_FPSIMD-3-0 pass
11884 09:30:15.944239 arm64_fp-stress_FPSIMD-3-1 pass
11885 09:30:15.947255 arm64_fp-stress_FPSIMD-4-0 pass
11886 09:30:15.951220 arm64_fp-stress_FPSIMD-4-1 pass
11887 09:30:15.953748 arm64_fp-stress_FPSIMD-5-0 pass
11888 09:30:15.957435 arm64_fp-stress_FPSIMD-5-1 pass
11889 09:30:15.960611 arm64_fp-stress_FPSIMD-6-0 pass
11890 09:30:15.960695 arm64_fp-stress_FPSIMD-6-1 pass
11891 09:30:15.963828 arm64_fp-stress_FPSIMD-7-0 pass
11892 09:30:15.967060 arm64_fp-stress_FPSIMD-7-1 pass
11893 09:30:15.970459 arm64_fp-stress pass
11894 09:30:15.973839 arm64_sve-ptrace_sve_not_available skip
11895 09:30:15.973921 arm64_sve-ptrace skip
11896 09:30:15.980235 arm64_sve-probe-vls_sve_not_available skip
11897 09:30:15.980335 arm64_sve-probe-vls skip
11898 09:30:15.983868 arm64_vec-syscfg_sve_not_supported skip
11899 09:30:15.987549 arm64_vec-syscfg_sve_not_supported skip
11900 09:30:15.990846 arm64_vec-syscfg_sve_not_supported skip
11901 09:30:15.997071 arm64_vec-syscfg_sve_not_supported skip
11902 09:30:16.000343 arm64_vec-syscfg_sve_not_supported skip
11903 09:30:16.003801 arm64_vec-syscfg_sve_not_supported skip
11904 09:30:16.006912 arm64_vec-syscfg_sve_not_supported skip
11905 09:30:16.010562 arm64_vec-syscfg_sve_not_supported skip
11906 09:30:16.013600 arm64_vec-syscfg_sve_not_supported skip
11907 09:30:16.017001 arm64_vec-syscfg_sve_not_supported skip
11908 09:30:16.020217 arm64_vec-syscfg_sme_not_supported skip
11909 09:30:16.023722 arm64_vec-syscfg_sme_not_supported skip
11910 09:30:16.027037 arm64_vec-syscfg_sme_not_supported skip
11911 09:30:16.030331 arm64_vec-syscfg_sme_not_supported skip
11912 09:30:16.033614 arm64_vec-syscfg_sme_not_supported skip
11913 09:30:16.036671 arm64_vec-syscfg_sme_not_supported skip
11914 09:30:16.040748 arm64_vec-syscfg_sme_not_supported skip
11915 09:30:16.047288 arm64_vec-syscfg_sme_not_supported skip
11916 09:30:16.050201 arm64_vec-syscfg_sme_not_supported skip
11917 09:30:16.053343 arm64_vec-syscfg_sme_not_supported skip
11918 09:30:16.053425 arm64_vec-syscfg pass
11919 09:30:16.056803 arm64_za-fork_skipped pass
11920 09:30:16.060157 arm64_za-fork pass
11921 09:30:16.063679 arm64_za-ptrace_sme_not_available skip
11922 09:30:16.063759 arm64_za-ptrace skip
11923 09:30:16.066990 arm64_check_buffer_fill skip
11924 09:30:16.070084 arm64_check_child_memory skip
11925 09:30:16.073615 arm64_check_gcr_el1_cswitch skip
11926 09:30:16.073696 arm64_check_ksm_options skip
11927 09:30:16.076732 arm64_check_mmap_options skip
11928 09:30:16.079958 arm64_check_prctl_check_basic_read pass
11929 09:30:16.083355 arm64_check_prctl_NONE pass
11930 09:30:16.086708 arm64_check_prctl_sync skip
11931 09:30:16.090150 arm64_check_prctl_async skip
11932 09:30:16.093490 arm64_check_prctl_sync_async skip
11933 09:30:16.093571 arm64_check_prctl pass
11934 09:30:16.096697 arm64_check_tags_inclusion skip
11935 09:30:16.100042 arm64_check_user_mem skip
11936 09:30:16.103687 arm64_btitest_nohint_func_call_using_br_x0 skip
11937 09:30:16.106492 arm64_btitest_nohint_func_call_using_br_x16 skip
11938 09:30:16.113210 arm64_btitest_nohint_func_call_using_blr skip
11939 09:30:16.116527 arm64_btitest_bti_none_func_call_using_br_x0 skip
11940 09:30:16.119980 arm64_btitest_bti_none_func_call_using_br_x16 skip
11941 09:30:16.126639 arm64_btitest_bti_none_func_call_using_blr skip
11942 09:30:16.129731 arm64_btitest_bti_c_func_call_using_br_x0 skip
11943 09:30:16.133189 arm64_btitest_bti_c_func_call_using_br_x16 skip
11944 09:30:16.136270 arm64_btitest_bti_c_func_call_using_blr skip
11945 09:30:16.143645 arm64_btitest_bti_j_func_call_using_br_x0 skip
11946 09:30:16.146432 arm64_btitest_bti_j_func_call_using_br_x16 skip
11947 09:30:16.149581 arm64_btitest_bti_j_func_call_using_blr skip
11948 09:30:16.153629 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11949 09:30:16.159557 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11950 09:30:16.163082 arm64_btitest_bti_jc_func_call_using_blr skip
11951 09:30:16.166163 arm64_btitest_paciasp_func_call_using_br_x0 skip
11952 09:30:16.169607 arm64_btitest_paciasp_func_call_using_br_x16 skip
11953 09:30:16.176034 arm64_btitest_paciasp_func_call_using_blr skip
11954 09:30:16.176110 arm64_btitest pass
11955 09:30:16.182989 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11956 09:30:16.185960 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11957 09:30:16.189303 arm64_nobtitest_nohint_func_call_using_blr skip
11958 09:30:16.196314 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11959 09:30:16.199548 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11960 09:30:16.202861 arm64_nobtitest_bti_none_func_call_using_blr skip
11961 09:30:16.209808 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11962 09:30:16.212973 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11963 09:30:16.216078 arm64_nobtitest_bti_c_func_call_using_blr skip
11964 09:30:16.222887 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11965 09:30:16.226156 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11966 09:30:16.229384 arm64_nobtitest_bti_j_func_call_using_blr skip
11967 09:30:16.232533 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11968 09:30:16.239017 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11969 09:30:16.242418 arm64_nobtitest_bti_jc_func_call_using_blr skip
11970 09:30:16.246243 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11971 09:30:16.252513 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11972 09:30:16.256152 arm64_nobtitest_paciasp_func_call_using_blr skip
11973 09:30:16.259352 arm64_nobtitest pass
11974 09:30:16.262680 arm64_hwcap_cpuinfo_match_RNG pass
11975 09:30:16.262811 arm64_hwcap_sigill_rng skip
11976 09:30:16.265655 arm64_hwcap_cpuinfo_match_SME pass
11977 09:30:16.269221 arm64_hwcap_sigill_SME pass
11978 09:30:16.272472 arm64_hwcap_cpuinfo_match_SVE pass
11979 09:30:16.275904 arm64_hwcap_sigill_SVE pass
11980 09:30:16.279220 arm64_hwcap_cpuinfo_match_SVE_2 pass
11981 09:30:16.282590 arm64_hwcap_sigill_sve_2 skip
11982 09:30:16.285588 arm64_hwcap_cpuinfo_match_SVE_AES pass
11983 09:30:16.289319 arm64_hwcap_sigill_sve_aes skip
11984 09:30:16.292572 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11985 09:30:16.295815 arm64_hwcap_sigill_sve2_pmull skip
11986 09:30:16.299226 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11987 09:30:16.302437 arm64_hwcap_sigill_sve2_bitperm skip
11988 09:30:16.305663 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11989 09:30:16.308898 arm64_hwcap_sigill_sve2_sha3 skip
11990 09:30:16.312478 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11991 09:30:16.316016 arm64_hwcap_sigill_sve2_sm4 skip
11992 09:30:16.318919 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11993 09:30:16.322288 arm64_hwcap_sigill_sve2_i8mm skip
11994 09:30:16.325809 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11995 09:30:16.329117 arm64_hwcap_sigill_sve2_f32mm skip
11996 09:30:16.332058 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11997 09:30:16.335770 arm64_hwcap_sigill_sve2_f64mm skip
11998 09:30:16.338757 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11999 09:30:16.342316 arm64_hwcap_sigill_sve2_bf16 skip
12000 09:30:16.345645 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12001 09:30:16.349016 arm64_hwcap_sigill_sve2_ebf16 skip
12002 09:30:16.349099 arm64_hwcap pass
12003 09:30:16.352252 arm64_ptrace_read_tpidr_one pass
12004 09:30:16.355239 arm64_ptrace_write_tpidr_one pass
12005 09:30:16.358677 arm64_ptrace_verify_tpidr_one pass
12006 09:30:16.361950 arm64_ptrace_count_tpidrs pass
12007 09:30:16.365146 arm64_ptrace_tpidr2_write pass
12008 09:30:16.368803 arm64_ptrace_tpidr2_read pass
12009 09:30:16.371671 arm64_ptrace_write_tpidr_only pass
12010 09:30:16.371748 arm64_ptrace pass
12011 09:30:16.375680 arm64_syscall-abi_getpid_FPSIMD pass
12012 09:30:16.378884 arm64_syscall-abi_sched_yield_FPSIMD pass
12013 09:30:16.381873 arm64_syscall-abi pass
12014 09:30:16.385532 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12015 09:30:16.388644 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12016 09:30:16.395016 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12017 09:30:16.398537 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12018 09:30:16.401500 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12019 09:30:16.405289 arm64_tpidr2 pass
12020 09:30:16.408135 + ../../utils/send-to-lava.sh ./output/result.txt
12021 09:30:16.414950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12022 09:30:16.415244 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12024 09:30:16.418302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12025 09:30:16.418546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12027 09:30:16.424828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12028 09:30:16.425085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12030 09:30:16.431412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12031 09:30:16.431663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12033 09:30:16.459681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12034 09:30:16.460026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12036 09:30:16.516176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12037 09:30:16.516532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12039 09:30:16.571821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12040 09:30:16.572180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12042 09:30:16.628266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12043 09:30:16.628622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12045 09:30:16.680172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12046 09:30:16.680503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12048 09:30:16.736770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12049 09:30:16.737094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12051 09:30:16.790361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12052 09:30:16.790689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12054 09:30:16.843607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12055 09:30:16.843927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12057 09:30:16.897949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12058 09:30:16.898488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12060 09:30:16.953529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12061 09:30:16.953850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12063 09:30:17.008167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12064 09:30:17.008493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12066 09:30:17.062699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12067 09:30:17.063074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12069 09:30:17.119744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12070 09:30:17.120186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12072 09:30:17.174680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12073 09:30:17.175042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12075 09:30:17.230425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12076 09:30:17.230780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12078 09:30:17.283338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12079 09:30:17.283667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12081 09:30:17.336731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12083 09:30:17.340310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12084 09:30:17.390309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12085 09:30:17.390638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12087 09:30:17.446585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12088 09:30:17.446934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12090 09:30:17.501176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12091 09:30:17.501502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12093 09:30:17.554499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12094 09:30:17.554826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12096 09:30:17.610630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12097 09:30:17.610984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12099 09:30:17.668415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12100 09:30:17.668744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12102 09:30:17.722000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12103 09:30:17.722327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12105 09:30:17.771544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12106 09:30:17.771874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12108 09:30:17.829178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12110 09:30:17.832035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12111 09:30:17.887216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12112 09:30:17.887612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12114 09:30:17.939643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12115 09:30:17.939990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12117 09:30:17.993443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12118 09:30:17.993786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12120 09:30:18.048797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12122 09:30:18.051570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12123 09:30:18.106052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12124 09:30:18.106378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12126 09:30:18.156375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12127 09:30:18.156699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12129 09:30:18.214642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12130 09:30:18.215037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12132 09:30:18.269396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12133 09:30:18.269719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12135 09:30:18.326003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12136 09:30:18.326327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12138 09:30:18.383576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12139 09:30:18.383924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12141 09:30:18.441252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12142 09:30:18.441574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12144 09:30:18.497989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12145 09:30:18.498309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12147 09:30:18.555946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12149 09:30:18.558542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12150 09:30:18.610179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12151 09:30:18.610502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12153 09:30:18.667227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12154 09:30:18.667553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12156 09:30:18.721262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12157 09:30:18.721592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12159 09:30:18.778447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12160 09:30:18.778765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12162 09:30:18.835080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12163 09:30:18.835386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12165 09:30:18.890646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12166 09:30:18.891001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12168 09:30:18.947338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12169 09:30:18.947657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12171 09:30:19.005935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12172 09:30:19.006257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12174 09:30:19.061569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12175 09:30:19.061903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12177 09:30:19.118984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12178 09:30:19.119301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12180 09:30:19.180127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12181 09:30:19.180473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12183 09:30:19.228914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12184 09:30:19.229226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12186 09:30:19.288924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12187 09:30:19.289299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12189 09:30:19.343018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12190 09:30:19.343339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12192 09:30:19.402467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12193 09:30:19.402778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12195 09:30:19.462964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12196 09:30:19.463277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12198 09:30:19.512143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12199 09:30:19.512457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12201 09:30:19.565306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12202 09:30:19.565625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12204 09:30:19.620479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12205 09:30:19.620798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12207 09:30:19.674976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12208 09:30:19.675295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12210 09:30:19.729427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12211 09:30:19.729748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12213 09:30:19.779751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12214 09:30:19.780072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12216 09:30:19.835107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12217 09:30:19.835427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12219 09:30:19.889592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12220 09:30:19.889913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12222 09:30:19.942942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12223 09:30:19.943301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12225 09:30:20.000387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12226 09:30:20.000770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12228 09:30:20.050640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12229 09:30:20.050995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12231 09:30:20.105986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12232 09:30:20.106337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12234 09:30:20.156464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12235 09:30:20.156779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12237 09:30:20.208938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12238 09:30:20.209261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12240 09:30:20.262078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12241 09:30:20.262400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12243 09:30:20.314747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12244 09:30:20.315085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12246 09:30:20.366975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12247 09:30:20.367303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12249 09:30:20.420811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12250 09:30:20.421137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12252 09:30:20.470546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12253 09:30:20.470868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12255 09:30:20.528046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12256 09:30:20.528365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12258 09:30:20.584564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12259 09:30:20.584887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12261 09:30:20.641919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12262 09:30:20.642401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12264 09:30:20.696816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12265 09:30:20.697148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12267 09:30:20.752831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12268 09:30:20.753156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12270 09:30:20.810188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12271 09:30:20.810514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12273 09:30:20.865754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12274 09:30:20.866077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12276 09:30:20.925014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12277 09:30:20.925345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12279 09:30:20.986574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12280 09:30:20.986943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12282 09:30:21.050989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12283 09:30:21.051312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12285 09:30:21.109049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12286 09:30:21.109359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12288 09:30:21.165521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12289 09:30:21.165870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12291 09:30:21.223703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12292 09:30:21.224013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12294 09:30:21.282092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12296 09:30:21.285142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12297 09:30:21.336775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12298 09:30:21.337082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12300 09:30:21.394285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12301 09:30:21.394595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12303 09:30:21.451559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12304 09:30:21.451866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12306 09:30:21.511356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12307 09:30:21.511639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12309 09:30:21.567143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12310 09:30:21.567480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12312 09:30:21.628931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12313 09:30:21.629255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12315 09:30:21.687950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12316 09:30:21.688261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12318 09:30:21.745997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12319 09:30:21.746349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12321 09:30:21.807462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12322 09:30:21.807788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12324 09:30:21.866310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12325 09:30:21.866646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12327 09:30:21.923495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12328 09:30:21.923819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12330 09:30:21.980259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12331 09:30:21.980572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12333 09:30:22.038692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12334 09:30:22.039020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12336 09:30:22.094178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12337 09:30:22.094503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12339 09:30:22.150956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12340 09:30:22.151249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12342 09:30:22.208364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12343 09:30:22.208709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12345 09:30:22.266754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12346 09:30:22.267085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12348 09:30:22.321870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12349 09:30:22.322172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12351 09:30:22.384131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12352 09:30:22.384421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12354 09:30:22.443050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12355 09:30:22.443311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12357 09:30:22.503227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12358 09:30:22.503527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12360 09:30:22.562759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12361 09:30:22.563044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12363 09:30:22.627762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12364 09:30:22.628062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12366 09:30:22.688573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12367 09:30:22.688846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12369 09:30:22.746076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12370 09:30:22.746335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12372 09:30:22.803388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12373 09:30:22.803664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12375 09:30:22.861281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12376 09:30:22.861543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12378 09:30:22.920415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12379 09:30:22.920707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12381 09:30:22.977014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12382 09:30:22.977307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12384 09:30:23.036091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12385 09:30:23.036360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12387 09:30:23.095424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12388 09:30:23.095716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12390 09:30:23.156996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12391 09:30:23.157683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12393 09:30:23.228728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12394 09:30:23.229686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12396 09:30:23.298670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12397 09:30:23.299415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12399 09:30:23.367674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12400 09:30:23.368399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12402 09:30:23.437907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12403 09:30:23.438634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12405 09:30:23.509676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12406 09:30:23.510535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12408 09:30:23.578715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12409 09:30:23.579481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12411 09:30:23.653321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12412 09:30:23.654018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12414 09:30:23.723626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12415 09:30:23.724330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12417 09:30:23.783985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12418 09:30:23.784690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12420 09:30:23.861115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12421 09:30:23.861814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12423 09:30:23.922689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12424 09:30:23.923453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12426 09:30:23.983199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12428 09:30:23.985915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12429 09:30:24.048550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12430 09:30:24.049463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12432 09:30:24.114790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12433 09:30:24.115548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12435 09:30:24.177536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12436 09:30:24.178299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12438 09:30:24.246066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12439 09:30:24.246824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12441 09:30:24.310188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12442 09:30:24.310897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12444 09:30:24.384052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12445 09:30:24.384775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12447 09:30:24.446266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12448 09:30:24.446545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12450 09:30:24.509625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12451 09:30:24.509903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12453 09:30:24.569551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12454 09:30:24.569823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12456 09:30:24.629831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12457 09:30:24.630107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12459 09:30:24.689155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12460 09:30:24.689436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12462 09:30:24.746456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12463 09:30:24.746726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12465 09:30:24.800169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12467 09:30:24.803668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12468 09:30:24.859625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12469 09:30:24.859885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12471 09:30:24.915437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12473 09:30:24.918451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12474 09:30:24.975902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12475 09:30:24.976176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12477 09:30:25.029368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12479 09:30:25.032157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12480 09:30:25.092305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12481 09:30:25.092578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12483 09:30:25.153441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12484 09:30:25.153743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12486 09:30:25.212177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12487 09:30:25.212473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12489 09:30:25.270065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12490 09:30:25.270340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12492 09:30:25.328072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12493 09:30:25.328349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12495 09:30:25.382392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12497 09:30:25.385608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12498 09:30:25.441466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12499 09:30:25.441748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12501 09:30:25.497071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12502 09:30:25.497373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12504 09:30:25.546944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12505 09:30:25.547216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12507 09:30:25.601054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12509 09:30:25.604238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12510 09:30:25.655098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12512 09:30:25.658092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12513 09:30:25.713160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12514 09:30:25.713485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12516 09:30:25.767397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12517 09:30:25.767670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12519 09:30:25.822360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12520 09:30:25.822645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12522 09:30:25.882490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12523 09:30:25.882777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12525 09:30:25.945770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12526 09:30:25.946037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12528 09:30:25.999866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12529 09:30:26.000135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12531 09:30:26.063442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12532 09:30:26.063707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12534 09:30:26.120466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12535 09:30:26.120740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12537 09:30:26.179112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12538 09:30:26.179383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12540 09:30:26.238606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12541 09:30:26.238931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12543 09:30:26.295025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12544 09:30:26.295297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12546 09:30:26.352501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12547 09:30:26.352766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12549 09:30:26.411899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12550 09:30:26.412260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12552 09:30:26.467861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12553 09:30:26.468123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12555 09:30:26.524188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12556 09:30:26.524287 + set +x
12557 09:30:26.524527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12559 09:30:26.531211 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 11826801_1.6.2.3.5>
12560 09:30:26.531465 Received signal: <ENDRUN> 1_kselftest-arm64 11826801_1.6.2.3.5
12561 09:30:26.531542 Ending use of test pattern.
12562 09:30:26.531605 Ending test lava.1_kselftest-arm64 (11826801_1.6.2.3.5), duration 36.96
12564 09:30:26.534368 <LAVA_TEST_RUNNER EXIT>
12565 09:30:26.534621 ok: lava_test_shell seems to have completed
12566 09:30:26.535618 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12567 09:30:26.535764 end: 3.1 lava-test-shell (duration 00:00:38) [common]
12568 09:30:26.535854 end: 3 lava-test-retry (duration 00:00:38) [common]
12569 09:30:26.535943 start: 4 finalize (timeout 00:06:47) [common]
12570 09:30:26.536032 start: 4.1 power-off (timeout 00:00:30) [common]
12571 09:30:26.536189 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
12572 09:30:26.614755 >> Command sent successfully.
12573 09:30:26.617136 Returned 0 in 0 seconds
12574 09:30:26.717709 end: 4.1 power-off (duration 00:00:00) [common]
12576 09:30:26.718051 start: 4.2 read-feedback (timeout 00:06:47) [common]
12577 09:30:26.718318 Listened to connection for namespace 'common' for up to 1s
12578 09:30:27.718819 Finalising connection for namespace 'common'
12579 09:30:27.719046 Disconnecting from shell: Finalise
12580 09:30:27.719159 / #
12581 09:30:27.819798 end: 4.2 read-feedback (duration 00:00:01) [common]
12582 09:30:27.820587 end: 4 finalize (duration 00:00:01) [common]
12583 09:30:27.821444 Cleaning after the job
12584 09:30:27.821933 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/ramdisk
12585 09:30:27.827132 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/kernel
12586 09:30:27.839735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/dtb
12587 09:30:27.839916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/nfsrootfs
12588 09:30:27.931314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826801/tftp-deploy-umtcdiai/modules
12589 09:30:27.938411 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826801
12590 09:30:28.604177 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826801
12591 09:30:28.604369 Job finished correctly