Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 38
- Errors: 0
- Boot result: PASS
1 09:30:06.362715 lava-dispatcher, installed at version: 2023.08
2 09:30:06.362915 start: 0 validate
3 09:30:06.363050 Start time: 2023-10-20 09:30:06.363037+00:00 (UTC)
4 09:30:06.363162 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:30:06.363293 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:30:06.642835 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:30:06.643581 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:30:06.914888 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:30:06.915726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:30:07.186815 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:30:07.187573 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:30:07.459396 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:30:07.460220 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:30:07.737221 validate duration: 1.37
16 09:30:07.738544 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:30:07.739121 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:30:07.739614 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:30:07.740267 Not decompressing ramdisk as can be used compressed.
20 09:30:07.740750 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 09:30:07.741148 saving as /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/ramdisk/initrd.cpio.gz
22 09:30:07.741527 total size: 4665395 (4 MB)
23 09:30:07.746810 progress 0 % (0 MB)
24 09:30:07.754873 progress 5 % (0 MB)
25 09:30:07.761239 progress 10 % (0 MB)
26 09:30:07.765698 progress 15 % (0 MB)
27 09:30:07.769276 progress 20 % (0 MB)
28 09:30:07.772153 progress 25 % (1 MB)
29 09:30:07.774924 progress 30 % (1 MB)
30 09:30:07.777285 progress 35 % (1 MB)
31 09:30:07.779598 progress 40 % (1 MB)
32 09:30:07.781874 progress 45 % (2 MB)
33 09:30:07.783908 progress 50 % (2 MB)
34 09:30:07.785759 progress 55 % (2 MB)
35 09:30:07.787513 progress 60 % (2 MB)
36 09:30:07.789276 progress 65 % (2 MB)
37 09:30:07.790861 progress 70 % (3 MB)
38 09:30:07.792425 progress 75 % (3 MB)
39 09:30:07.793976 progress 80 % (3 MB)
40 09:30:07.795636 progress 85 % (3 MB)
41 09:30:07.797044 progress 90 % (4 MB)
42 09:30:07.798438 progress 95 % (4 MB)
43 09:30:07.799829 progress 100 % (4 MB)
44 09:30:07.799988 4 MB downloaded in 0.06 s (76.07 MB/s)
45 09:30:07.800144 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:30:07.800398 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:30:07.800489 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:30:07.800577 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:30:07.800714 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:30:07.800786 saving as /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/kernel/Image
52 09:30:07.800851 total size: 49236480 (46 MB)
53 09:30:07.800917 No compression specified
54 09:30:07.802038 progress 0 % (0 MB)
55 09:30:07.814719 progress 5 % (2 MB)
56 09:30:07.827396 progress 10 % (4 MB)
57 09:30:07.840431 progress 15 % (7 MB)
58 09:30:07.853143 progress 20 % (9 MB)
59 09:30:07.865852 progress 25 % (11 MB)
60 09:30:07.878514 progress 30 % (14 MB)
61 09:30:07.891313 progress 35 % (16 MB)
62 09:30:07.904065 progress 40 % (18 MB)
63 09:30:07.916653 progress 45 % (21 MB)
64 09:30:07.929459 progress 50 % (23 MB)
65 09:30:07.942106 progress 55 % (25 MB)
66 09:30:07.955122 progress 60 % (28 MB)
67 09:30:07.970115 progress 65 % (30 MB)
68 09:30:07.982829 progress 70 % (32 MB)
69 09:30:07.995913 progress 75 % (35 MB)
70 09:30:08.008603 progress 80 % (37 MB)
71 09:30:08.021053 progress 85 % (39 MB)
72 09:30:08.033732 progress 90 % (42 MB)
73 09:30:08.046394 progress 95 % (44 MB)
74 09:30:08.058924 progress 100 % (46 MB)
75 09:30:08.059132 46 MB downloaded in 0.26 s (181.80 MB/s)
76 09:30:08.059286 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:30:08.059519 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:30:08.059608 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:30:08.059694 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:30:08.059832 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:30:08.059909 saving as /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/dtb/mt8192-asurada-spherion-r0.dtb
83 09:30:08.059972 total size: 47278 (0 MB)
84 09:30:08.060033 No compression specified
85 09:30:08.061202 progress 69 % (0 MB)
86 09:30:08.061479 progress 100 % (0 MB)
87 09:30:08.061636 0 MB downloaded in 0.00 s (27.15 MB/s)
88 09:30:08.061760 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:30:08.061985 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:30:08.062071 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:30:08.062155 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:30:08.062268 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 09:30:08.062338 saving as /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/nfsrootfs/full.rootfs.tar
95 09:30:08.062405 total size: 200813988 (191 MB)
96 09:30:08.062469 Using unxz to decompress xz
97 09:30:08.066546 progress 0 % (0 MB)
98 09:30:08.588559 progress 5 % (9 MB)
99 09:30:09.094387 progress 10 % (19 MB)
100 09:30:09.667407 progress 15 % (28 MB)
101 09:30:10.032703 progress 20 % (38 MB)
102 09:30:10.350176 progress 25 % (47 MB)
103 09:30:10.926502 progress 30 % (57 MB)
104 09:30:11.468722 progress 35 % (67 MB)
105 09:30:12.051415 progress 40 % (76 MB)
106 09:30:12.598868 progress 45 % (86 MB)
107 09:30:13.170496 progress 50 % (95 MB)
108 09:30:13.791399 progress 55 % (105 MB)
109 09:30:14.440695 progress 60 % (114 MB)
110 09:30:14.557583 progress 65 % (124 MB)
111 09:30:14.694747 progress 70 % (134 MB)
112 09:30:14.789786 progress 75 % (143 MB)
113 09:30:14.859765 progress 80 % (153 MB)
114 09:30:14.927203 progress 85 % (162 MB)
115 09:30:15.026708 progress 90 % (172 MB)
116 09:30:15.299107 progress 95 % (181 MB)
117 09:30:15.862339 progress 100 % (191 MB)
118 09:30:15.867527 191 MB downloaded in 7.81 s (24.54 MB/s)
119 09:30:15.867791 end: 1.4.1 http-download (duration 00:00:08) [common]
121 09:30:15.868049 end: 1.4 download-retry (duration 00:00:08) [common]
122 09:30:15.868140 start: 1.5 download-retry (timeout 00:09:52) [common]
123 09:30:15.868288 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 09:30:15.868445 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:30:15.868515 saving as /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/modules/modules.tar
126 09:30:15.868578 total size: 8614716 (8 MB)
127 09:30:15.868643 Using unxz to decompress xz
128 09:30:15.873104 progress 0 % (0 MB)
129 09:30:15.893807 progress 5 % (0 MB)
130 09:30:15.917040 progress 10 % (0 MB)
131 09:30:15.939948 progress 15 % (1 MB)
132 09:30:15.963122 progress 20 % (1 MB)
133 09:30:15.986934 progress 25 % (2 MB)
134 09:30:16.012170 progress 30 % (2 MB)
135 09:30:16.037963 progress 35 % (2 MB)
136 09:30:16.061149 progress 40 % (3 MB)
137 09:30:16.084908 progress 45 % (3 MB)
138 09:30:16.109992 progress 50 % (4 MB)
139 09:30:16.133920 progress 55 % (4 MB)
140 09:30:16.158388 progress 60 % (4 MB)
141 09:30:16.183480 progress 65 % (5 MB)
142 09:30:16.209941 progress 70 % (5 MB)
143 09:30:16.233105 progress 75 % (6 MB)
144 09:30:16.259457 progress 80 % (6 MB)
145 09:30:16.284536 progress 85 % (7 MB)
146 09:30:16.308945 progress 90 % (7 MB)
147 09:30:16.337877 progress 95 % (7 MB)
148 09:30:16.365475 progress 100 % (8 MB)
149 09:30:16.371600 8 MB downloaded in 0.50 s (16.33 MB/s)
150 09:30:16.371863 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:30:16.372124 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:30:16.372267 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 09:30:16.372366 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 09:30:19.845857 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f
156 09:30:19.846060 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 09:30:19.846166 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 09:30:19.846336 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x
159 09:30:19.846470 makedir: /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin
160 09:30:19.846574 makedir: /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/tests
161 09:30:19.846675 makedir: /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/results
162 09:30:19.846779 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-add-keys
163 09:30:19.846930 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-add-sources
164 09:30:19.847071 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-background-process-start
165 09:30:19.847203 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-background-process-stop
166 09:30:19.847331 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-common-functions
167 09:30:19.847459 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-echo-ipv4
168 09:30:19.847586 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-install-packages
169 09:30:19.847714 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-installed-packages
170 09:30:19.847853 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-os-build
171 09:30:19.848014 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-probe-channel
172 09:30:19.848143 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-probe-ip
173 09:30:19.848278 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-target-ip
174 09:30:19.848406 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-target-mac
175 09:30:19.848533 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-target-storage
176 09:30:19.848662 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-case
177 09:30:19.848792 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-event
178 09:30:19.848917 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-feedback
179 09:30:19.849045 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-raise
180 09:30:19.849169 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-reference
181 09:30:19.849296 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-runner
182 09:30:19.849422 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-set
183 09:30:19.849548 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-test-shell
184 09:30:19.849676 Updating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-add-keys (debian)
185 09:30:19.849833 Updating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-add-sources (debian)
186 09:30:19.849979 Updating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-install-packages (debian)
187 09:30:19.850122 Updating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-installed-packages (debian)
188 09:30:19.850262 Updating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/bin/lava-os-build (debian)
189 09:30:19.850387 Creating /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/environment
190 09:30:19.850485 LAVA metadata
191 09:30:19.850557 - LAVA_JOB_ID=11826813
192 09:30:19.850621 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:30:19.850736 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 09:30:19.850803 skipped lava-vland-overlay
195 09:30:19.850878 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:30:19.850959 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 09:30:19.851029 skipped lava-multinode-overlay
198 09:30:19.851152 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:30:19.851238 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 09:30:19.851315 Loading test definitions
201 09:30:19.851405 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 09:30:19.851479 Using /lava-11826813 at stage 0
203 09:30:19.851768 uuid=11826813_1.6.2.3.1 testdef=None
204 09:30:19.851858 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:30:19.851945 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 09:30:19.852632 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:30:19.852855 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 09:30:19.853414 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:30:19.853645 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 09:30:19.854188 runner path: /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/0/tests/0_timesync-off test_uuid 11826813_1.6.2.3.1
213 09:30:19.854346 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:30:19.854573 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 09:30:19.854647 Using /lava-11826813 at stage 0
217 09:30:19.854744 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:30:19.854822 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/0/tests/1_kselftest-rtc'
219 09:30:23.606534 Running '/usr/bin/git checkout kernelci.org
220 09:30:23.755244 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 09:30:23.756007 uuid=11826813_1.6.2.3.5 testdef=None
222 09:30:23.756172 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 09:30:23.756475 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 09:30:23.757224 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:30:23.757466 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 09:30:23.758441 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:30:23.758689 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 09:30:23.759634 runner path: /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/0/tests/1_kselftest-rtc test_uuid 11826813_1.6.2.3.5
232 09:30:23.759729 BOARD='mt8192-asurada-spherion-r0'
233 09:30:23.759795 BRANCH='cip'
234 09:30:23.759856 SKIPFILE='/dev/null'
235 09:30:23.759915 SKIP_INSTALL='True'
236 09:30:23.759972 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:30:23.760033 TST_CASENAME=''
238 09:30:23.760089 TST_CMDFILES='rtc'
239 09:30:23.760272 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:30:23.760486 Creating lava-test-runner.conf files
242 09:30:23.760550 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826813/lava-overlay-z5n2ry0x/lava-11826813/0 for stage 0
243 09:30:23.760644 - 0_timesync-off
244 09:30:23.760712 - 1_kselftest-rtc
245 09:30:23.760809 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 09:30:23.760900 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 09:30:31.201067 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 09:30:31.201219 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 09:30:31.201349 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:30:31.201452 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 09:30:31.201544 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 09:30:31.322177 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:30:31.322570 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 09:30:31.322687 extracting modules file /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f
255 09:30:31.545976 extracting modules file /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826813/extract-overlay-ramdisk-8p16h6lx/ramdisk
256 09:30:31.775894 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:30:31.776072 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 09:30:31.776172 [common] Applying overlay to NFS
259 09:30:31.776299 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826813/compress-overlay-nonmjose/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f
260 09:30:32.680348 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:30:32.680518 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 09:30:32.680615 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:30:32.680705 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 09:30:32.680790 Building ramdisk /var/lib/lava/dispatcher/tmp/11826813/extract-overlay-ramdisk-8p16h6lx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826813/extract-overlay-ramdisk-8p16h6lx/ramdisk
265 09:30:32.997217 >> 119368 blocks
266 09:30:34.879238 rename /var/lib/lava/dispatcher/tmp/11826813/extract-overlay-ramdisk-8p16h6lx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/ramdisk/ramdisk.cpio.gz
267 09:30:34.879706 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:30:34.879830 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 09:30:34.879931 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 09:30:34.880037 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/kernel/Image'
271 09:30:46.845371 Returned 0 in 11 seconds
272 09:30:46.946541 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/kernel/image.itb
273 09:30:47.319068 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:30:47.319472 output: Created: Fri Oct 20 10:30:47 2023
275 09:30:47.319554 output: Image 0 (kernel-1)
276 09:30:47.319623 output: Description:
277 09:30:47.319688 output: Created: Fri Oct 20 10:30:47 2023
278 09:30:47.319750 output: Type: Kernel Image
279 09:30:47.319811 output: Compression: lzma compressed
280 09:30:47.319870 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
281 09:30:47.319929 output: Architecture: AArch64
282 09:30:47.319987 output: OS: Linux
283 09:30:47.320042 output: Load Address: 0x00000000
284 09:30:47.320099 output: Entry Point: 0x00000000
285 09:30:47.320157 output: Hash algo: crc32
286 09:30:47.320272 output: Hash value: 05d3904e
287 09:30:47.320330 output: Image 1 (fdt-1)
288 09:30:47.320385 output: Description: mt8192-asurada-spherion-r0
289 09:30:47.320439 output: Created: Fri Oct 20 10:30:47 2023
290 09:30:47.320493 output: Type: Flat Device Tree
291 09:30:47.320547 output: Compression: uncompressed
292 09:30:47.320599 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 09:30:47.320652 output: Architecture: AArch64
294 09:30:47.320705 output: Hash algo: crc32
295 09:30:47.320758 output: Hash value: cc4352de
296 09:30:47.320811 output: Image 2 (ramdisk-1)
297 09:30:47.320864 output: Description: unavailable
298 09:30:47.320916 output: Created: Fri Oct 20 10:30:47 2023
299 09:30:47.320969 output: Type: RAMDisk Image
300 09:30:47.321022 output: Compression: Unknown Compression
301 09:30:47.321075 output: Data Size: 17790622 Bytes = 17373.65 KiB = 16.97 MiB
302 09:30:47.321128 output: Architecture: AArch64
303 09:30:47.321181 output: OS: Linux
304 09:30:47.321234 output: Load Address: unavailable
305 09:30:47.321286 output: Entry Point: unavailable
306 09:30:47.321339 output: Hash algo: crc32
307 09:30:47.321391 output: Hash value: 5dc11906
308 09:30:47.321443 output: Default Configuration: 'conf-1'
309 09:30:47.321497 output: Configuration 0 (conf-1)
310 09:30:47.321550 output: Description: mt8192-asurada-spherion-r0
311 09:30:47.321602 output: Kernel: kernel-1
312 09:30:47.321654 output: Init Ramdisk: ramdisk-1
313 09:30:47.321707 output: FDT: fdt-1
314 09:30:47.321759 output: Loadables: kernel-1
315 09:30:47.321812 output:
316 09:30:47.322016 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 09:30:47.322120 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 09:30:47.322226 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 09:30:47.322323 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 09:30:47.322402 No LXC device requested
321 09:30:47.322479 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:30:47.322563 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 09:30:47.322642 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:30:47.322735 Checking files for TFTP limit of 4294967296 bytes.
325 09:30:47.323262 end: 1 tftp-deploy (duration 00:00:40) [common]
326 09:30:47.323372 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:30:47.323463 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:30:47.323583 substitutions:
329 09:30:47.323650 - {DTB}: 11826813/tftp-deploy-pt1lsnrn/dtb/mt8192-asurada-spherion-r0.dtb
330 09:30:47.323715 - {INITRD}: 11826813/tftp-deploy-pt1lsnrn/ramdisk/ramdisk.cpio.gz
331 09:30:47.323776 - {KERNEL}: 11826813/tftp-deploy-pt1lsnrn/kernel/Image
332 09:30:47.323834 - {LAVA_MAC}: None
333 09:30:47.323891 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f
334 09:30:47.323948 - {NFS_SERVER_IP}: 192.168.201.1
335 09:30:47.324003 - {PRESEED_CONFIG}: None
336 09:30:47.324058 - {PRESEED_LOCAL}: None
337 09:30:47.324113 - {RAMDISK}: 11826813/tftp-deploy-pt1lsnrn/ramdisk/ramdisk.cpio.gz
338 09:30:47.324167 - {ROOT_PART}: None
339 09:30:47.324298 - {ROOT}: None
340 09:30:47.324353 - {SERVER_IP}: 192.168.201.1
341 09:30:47.324408 - {TEE}: None
342 09:30:47.324462 Parsed boot commands:
343 09:30:47.324515 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:30:47.324701 Parsed boot commands: tftpboot 192.168.201.1 11826813/tftp-deploy-pt1lsnrn/kernel/image.itb 11826813/tftp-deploy-pt1lsnrn/kernel/cmdline
345 09:30:47.324787 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:30:47.324875 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:30:47.324969 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:30:47.325060 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:30:47.325134 Not connected, no need to disconnect.
350 09:30:47.325209 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:30:47.325292 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:30:47.325363 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 09:30:47.329336 Setting prompt string to ['lava-test: # ']
354 09:30:47.329735 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:30:47.329848 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:30:47.329974 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:30:47.330096 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:30:47.330359 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 09:30:52.480969 >> Command sent successfully.
360 09:30:52.492743 Returned 0 in 5 seconds
361 09:30:52.594114 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 09:30:52.595920 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 09:30:52.596584 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 09:30:52.597096 Setting prompt string to 'Starting depthcharge on Spherion...'
366 09:30:52.597501 Changing prompt to 'Starting depthcharge on Spherion...'
367 09:30:52.598048 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 09:30:52.599510 [Enter `^Ec?' for help]
369 09:30:52.762164
370 09:30:52.762768
371 09:30:52.763181 F0: 102B 0000
372 09:30:52.763593
373 09:30:52.764156 F3: 1001 0000 [0200]
374 09:30:52.766081
375 09:30:52.766555 F3: 1001 0000
376 09:30:52.766939
377 09:30:52.767295 F7: 102D 0000
378 09:30:52.767677
379 09:30:52.769381 F1: 0000 0000
380 09:30:52.769860
381 09:30:52.770242 V0: 0000 0000 [0001]
382 09:30:52.770598
383 09:30:52.770936 00: 0007 8000
384 09:30:52.773038
385 09:30:52.773513 01: 0000 0000
386 09:30:52.774062
387 09:30:52.774566 BP: 0C00 0209 [0000]
388 09:30:52.774932
389 09:30:52.776654 G0: 1182 0000
390 09:30:52.777132
391 09:30:52.777512 EC: 0000 0021 [4000]
392 09:30:52.777865
393 09:30:52.780145 S7: 0000 0000 [0000]
394 09:30:52.780608
395 09:30:52.780950 CC: 0000 0000 [0001]
396 09:30:52.781271
397 09:30:52.783545 T0: 0000 0040 [010F]
398 09:30:52.783982
399 09:30:52.784358 Jump to BL
400 09:30:52.784684
401 09:30:52.809830
402 09:30:52.810408
403 09:30:52.810788
404 09:30:52.817101 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 09:30:52.820668 ARM64: Exception handlers installed.
406 09:30:52.824629 ARM64: Testing exception
407 09:30:52.828320 ARM64: Done test exception
408 09:30:52.835067 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 09:30:52.842526 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 09:30:52.849663 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 09:30:52.860440 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 09:30:52.866960 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 09:30:52.876968 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 09:30:52.887030 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 09:30:52.893685 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 09:30:52.912009 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 09:30:52.915778 WDT: Last reset was cold boot
418 09:30:52.918937 SPI1(PAD0) initialized at 2873684 Hz
419 09:30:52.922474 SPI5(PAD0) initialized at 992727 Hz
420 09:30:52.925713 VBOOT: Loading verstage.
421 09:30:52.932156 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:30:52.935505 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 09:30:52.939134 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 09:30:52.942635 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 09:30:52.949750 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 09:30:52.956125 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 09:30:52.967285 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 09:30:52.967868
429 09:30:52.968388
430 09:30:52.977328 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 09:30:52.980748 ARM64: Exception handlers installed.
432 09:30:52.983925 ARM64: Testing exception
433 09:30:52.984458 ARM64: Done test exception
434 09:30:52.990720 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 09:30:52.994365 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 09:30:53.008486 Probing TPM: . done!
437 09:30:53.009067 TPM ready after 0 ms
438 09:30:53.015422 Connected to device vid:did:rid of 1ae0:0028:00
439 09:30:53.021906 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 09:30:53.069401 Initialized TPM device CR50 revision 0
441 09:30:53.082798 tlcl_send_startup: Startup return code is 0
442 09:30:53.083407 TPM: setup succeeded
443 09:30:53.096394 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 09:30:53.105238 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:30:53.114955 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 09:30:53.124125 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 09:30:53.127598 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 09:30:53.130811 in-header: 03 07 00 00 08 00 00 00
449 09:30:53.134252 in-data: aa e4 47 04 13 02 00 00
450 09:30:53.137371 Chrome EC: UHEPI supported
451 09:30:53.143945 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 09:30:53.147505 in-header: 03 95 00 00 08 00 00 00
453 09:30:53.150957 in-data: 18 20 20 08 00 00 00 00
454 09:30:53.151613 Phase 1
455 09:30:53.154955 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 09:30:53.162535 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 09:30:53.165957 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 09:30:53.169896 Recovery requested (1009000e)
459 09:30:53.179010 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 09:30:53.184359 tlcl_extend: response is 0
461 09:30:53.193623 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 09:30:53.199200 tlcl_extend: response is 0
463 09:30:53.205947 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 09:30:53.226694 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 09:30:53.234077 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 09:30:53.234668
467 09:30:53.235071
468 09:30:53.241757 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 09:30:53.245083 ARM64: Exception handlers installed.
470 09:30:53.248543 ARM64: Testing exception
471 09:30:53.251573 ARM64: Done test exception
472 09:30:53.271622 pmic_efuse_setting: Set efuses in 11 msecs
473 09:30:53.275059 pmwrap_interface_init: Select PMIF_VLD_RDY
474 09:30:53.281711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 09:30:53.284898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 09:30:53.291574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 09:30:53.295096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 09:30:53.301588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 09:30:53.305141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 09:30:53.308624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 09:30:53.314966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 09:30:53.318520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 09:30:53.324951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 09:30:53.328712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 09:30:53.331654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 09:30:53.338644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 09:30:53.345342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 09:30:53.348675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 09:30:53.356226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 09:30:53.359634 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 09:30:53.366881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 09:30:53.373946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 09:30:53.377636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 09:30:53.384896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 09:30:53.388641 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 09:30:53.395829 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 09:30:53.399539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 09:30:53.403706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 09:30:53.410963 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 09:30:53.414613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 09:30:53.421899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 09:30:53.425654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 09:30:53.429235 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 09:30:53.436859 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 09:30:53.440778 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 09:30:53.444026 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 09:30:53.451671 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 09:30:53.455153 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 09:30:53.462386 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 09:30:53.466010 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 09:30:53.469617 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 09:30:53.476739 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 09:30:53.480386 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 09:30:53.483962 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 09:30:53.487990 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 09:30:53.491385 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 09:30:53.495311 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 09:30:53.502835 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 09:30:53.506417 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 09:30:53.510213 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 09:30:53.514039 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 09:30:53.517587 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 09:30:53.521247 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 09:30:53.525134 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 09:30:53.535849 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 09:30:53.542626 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 09:30:53.546118 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 09:30:53.557022 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 09:30:53.564338 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 09:30:53.567411 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 09:30:53.574981 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:30:53.578306 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 09:30:53.585402 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
534 09:30:53.588351 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 09:30:53.596619 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 09:30:53.599615 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 09:30:53.608834 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 09:30:53.618781 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 09:30:53.627746 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 09:30:53.637386 [RTC]rtc_get_frequency_meter,154: input=17, output=811
541 09:30:53.646827 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 09:30:53.656691 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 09:30:53.666186 [RTC]rtc_get_frequency_meter,154: input=17, output=809
544 09:30:53.670051 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 09:30:53.677104 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 09:30:53.680698 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 09:30:53.684400 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 09:30:53.687864 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 09:30:53.691771 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 09:30:53.695122 ADC[4]: Raw value=670432 ID=5
551 09:30:53.698757 ADC[3]: Raw value=212549 ID=1
552 09:30:53.699241 RAM Code: 0x51
553 09:30:53.702899 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 09:30:53.709853 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 09:30:53.717044 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 09:30:53.720946 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 09:30:53.724287 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 09:30:53.728420 in-header: 03 07 00 00 08 00 00 00
559 09:30:53.732323 in-data: aa e4 47 04 13 02 00 00
560 09:30:53.735947 Chrome EC: UHEPI supported
561 09:30:53.742899 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 09:30:53.746585 in-header: 03 95 00 00 08 00 00 00
563 09:30:53.750433 in-data: 18 20 20 08 00 00 00 00
564 09:30:53.751041 MRC: failed to locate region type 0.
565 09:30:53.757383 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 09:30:53.761294 DRAM-K: Running full calibration
567 09:30:53.768709 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 09:30:53.769210 header.status = 0x0
569 09:30:53.772691 header.version = 0x6 (expected: 0x6)
570 09:30:53.776437 header.size = 0xd00 (expected: 0xd00)
571 09:30:53.776920 header.flags = 0x0
572 09:30:53.783167 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 09:30:53.802028 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 09:30:53.808870 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 09:30:53.812205 dram_init: ddr_geometry: 0
576 09:30:53.812695 [EMI] MDL number = 0
577 09:30:53.815966 [EMI] Get MDL freq = 0
578 09:30:53.816628 dram_init: ddr_type: 0
579 09:30:53.819623 is_discrete_lpddr4: 1
580 09:30:53.822870 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 09:30:53.823464
582 09:30:53.823894
583 09:30:53.826924 [Bian_co] ETT version 0.0.0.1
584 09:30:53.830268 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 09:30:53.830788
586 09:30:53.833941 dramc_set_vcore_voltage set vcore to 650000
587 09:30:53.838038 Read voltage for 800, 4
588 09:30:53.838517 Vio18 = 0
589 09:30:53.838899 Vcore = 650000
590 09:30:53.839301 Vdram = 0
591 09:30:53.841201 Vddq = 0
592 09:30:53.841613 Vmddr = 0
593 09:30:53.845134 dram_init: config_dvfs: 1
594 09:30:53.848658 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 09:30:53.852485 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 09:30:53.856522 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 09:30:53.859673 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 09:30:53.863732 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 09:30:53.870720 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 09:30:53.871298 MEM_TYPE=3, freq_sel=18
601 09:30:53.874643 sv_algorithm_assistance_LP4_1600
602 09:30:53.878450 ============ PULL DRAM RESETB DOWN ============
603 09:30:53.881788 ========== PULL DRAM RESETB DOWN end =========
604 09:30:53.889319 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 09:30:53.889937 ===================================
606 09:30:53.893032 LPDDR4 DRAM CONFIGURATION
607 09:30:53.896358 ===================================
608 09:30:53.900452 EX_ROW_EN[0] = 0x0
609 09:30:53.901042 EX_ROW_EN[1] = 0x0
610 09:30:53.903903 LP4Y_EN = 0x0
611 09:30:53.904562 WORK_FSP = 0x0
612 09:30:53.904955 WL = 0x2
613 09:30:53.907447 RL = 0x2
614 09:30:53.908066 BL = 0x2
615 09:30:53.911457 RPST = 0x0
616 09:30:53.912045 RD_PRE = 0x0
617 09:30:53.914743 WR_PRE = 0x1
618 09:30:53.915438 WR_PST = 0x0
619 09:30:53.918529 DBI_WR = 0x0
620 09:30:53.919124 DBI_RD = 0x0
621 09:30:53.922178 OTF = 0x1
622 09:30:53.925857 ===================================
623 09:30:53.926353 ===================================
624 09:30:53.929121 ANA top config
625 09:30:53.932845 ===================================
626 09:30:53.933369 DLL_ASYNC_EN = 0
627 09:30:53.936441 ALL_SLAVE_EN = 1
628 09:30:53.939895 NEW_RANK_MODE = 1
629 09:30:53.943146 DLL_IDLE_MODE = 1
630 09:30:53.943629 LP45_APHY_COMB_EN = 1
631 09:30:53.946652 TX_ODT_DIS = 1
632 09:30:53.950215 NEW_8X_MODE = 1
633 09:30:53.953458 ===================================
634 09:30:53.957121 ===================================
635 09:30:53.960228 data_rate = 1600
636 09:30:53.964087 CKR = 1
637 09:30:53.964732 DQ_P2S_RATIO = 8
638 09:30:53.967429 ===================================
639 09:30:53.971328 CA_P2S_RATIO = 8
640 09:30:53.974922 DQ_CA_OPEN = 0
641 09:30:53.978701 DQ_SEMI_OPEN = 0
642 09:30:53.979284 CA_SEMI_OPEN = 0
643 09:30:53.982521 CA_FULL_RATE = 0
644 09:30:53.985899 DQ_CKDIV4_EN = 1
645 09:30:53.989034 CA_CKDIV4_EN = 1
646 09:30:53.989627 CA_PREDIV_EN = 0
647 09:30:53.992521 PH8_DLY = 0
648 09:30:53.995900 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 09:30:53.999168 DQ_AAMCK_DIV = 4
650 09:30:54.003157 CA_AAMCK_DIV = 4
651 09:30:54.003759 CA_ADMCK_DIV = 4
652 09:30:54.006408 DQ_TRACK_CA_EN = 0
653 09:30:54.010490 CA_PICK = 800
654 09:30:54.014145 CA_MCKIO = 800
655 09:30:54.017190 MCKIO_SEMI = 0
656 09:30:54.017682 PLL_FREQ = 3068
657 09:30:54.020755 DQ_UI_PI_RATIO = 32
658 09:30:54.024385 CA_UI_PI_RATIO = 0
659 09:30:54.027341 ===================================
660 09:30:54.030829 ===================================
661 09:30:54.034365 memory_type:LPDDR4
662 09:30:54.034847 GP_NUM : 10
663 09:30:54.038110 SRAM_EN : 1
664 09:30:54.038733 MD32_EN : 0
665 09:30:54.040953 ===================================
666 09:30:54.044862 [ANA_INIT] >>>>>>>>>>>>>>
667 09:30:54.048567 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 09:30:54.052116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:30:54.055803 ===================================
670 09:30:54.056459 data_rate = 1600,PCW = 0X7600
671 09:30:54.059445 ===================================
672 09:30:54.063275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 09:30:54.070595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:30:54.073736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 09:30:54.080612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 09:30:54.083871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:30:54.087029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 09:30:54.087513 [ANA_INIT] flow start
679 09:30:54.090702 [ANA_INIT] PLL >>>>>>>>
680 09:30:54.093947 [ANA_INIT] PLL <<<<<<<<
681 09:30:54.097227 [ANA_INIT] MIDPI >>>>>>>>
682 09:30:54.097858 [ANA_INIT] MIDPI <<<<<<<<
683 09:30:54.100354 [ANA_INIT] DLL >>>>>>>>
684 09:30:54.103844 [ANA_INIT] flow end
685 09:30:54.107009 ============ LP4 DIFF to SE enter ============
686 09:30:54.110608 ============ LP4 DIFF to SE exit ============
687 09:30:54.114015 [ANA_INIT] <<<<<<<<<<<<<
688 09:30:54.117151 [Flow] Enable top DCM control >>>>>
689 09:30:54.120545 [Flow] Enable top DCM control <<<<<
690 09:30:54.123991 Enable DLL master slave shuffle
691 09:30:54.127352 ==============================================================
692 09:30:54.130467 Gating Mode config
693 09:30:54.133772 ==============================================================
694 09:30:54.136873 Config description:
695 09:30:54.146959 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 09:30:54.153546 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 09:30:54.157335 SELPH_MODE 0: By rank 1: By Phase
698 09:30:54.163745 ==============================================================
699 09:30:54.167278 GAT_TRACK_EN = 1
700 09:30:54.170510 RX_GATING_MODE = 2
701 09:30:54.174222 RX_GATING_TRACK_MODE = 2
702 09:30:54.177012 SELPH_MODE = 1
703 09:30:54.177833 PICG_EARLY_EN = 1
704 09:30:54.180404 VALID_LAT_VALUE = 1
705 09:30:54.187322 ==============================================================
706 09:30:54.190290 Enter into Gating configuration >>>>
707 09:30:54.193785 Exit from Gating configuration <<<<
708 09:30:54.197197 Enter into DVFS_PRE_config >>>>>
709 09:30:54.206949 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 09:30:54.210447 Exit from DVFS_PRE_config <<<<<
711 09:30:54.214078 Enter into PICG configuration >>>>
712 09:30:54.216921 Exit from PICG configuration <<<<
713 09:30:54.220333 [RX_INPUT] configuration >>>>>
714 09:30:54.223815 [RX_INPUT] configuration <<<<<
715 09:30:54.227450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 09:30:54.233976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 09:30:54.240513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 09:30:54.247066 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 09:30:54.250320 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 09:30:54.257319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 09:30:54.260306 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 09:30:54.267070 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 09:30:54.270153 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 09:30:54.273574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 09:30:54.277058 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 09:30:54.283650 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 09:30:54.287013 ===================================
728 09:30:54.287118 LPDDR4 DRAM CONFIGURATION
729 09:30:54.290440 ===================================
730 09:30:54.294117 EX_ROW_EN[0] = 0x0
731 09:30:54.296816 EX_ROW_EN[1] = 0x0
732 09:30:54.296932 LP4Y_EN = 0x0
733 09:30:54.300430 WORK_FSP = 0x0
734 09:30:54.300518 WL = 0x2
735 09:30:54.304486 RL = 0x2
736 09:30:54.305183 BL = 0x2
737 09:30:54.307528 RPST = 0x0
738 09:30:54.308232 RD_PRE = 0x0
739 09:30:54.310779 WR_PRE = 0x1
740 09:30:54.311455 WR_PST = 0x0
741 09:30:54.314091 DBI_WR = 0x0
742 09:30:54.314562 DBI_RD = 0x0
743 09:30:54.317382 OTF = 0x1
744 09:30:54.320517 ===================================
745 09:30:54.323897 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 09:30:54.327200 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 09:30:54.333798 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 09:30:54.337080 ===================================
749 09:30:54.337308 LPDDR4 DRAM CONFIGURATION
750 09:30:54.340783 ===================================
751 09:30:54.344235 EX_ROW_EN[0] = 0x10
752 09:30:54.344683 EX_ROW_EN[1] = 0x0
753 09:30:54.347553 LP4Y_EN = 0x0
754 09:30:54.348029 WORK_FSP = 0x0
755 09:30:54.350720 WL = 0x2
756 09:30:54.351027 RL = 0x2
757 09:30:54.353823 BL = 0x2
758 09:30:54.354057 RPST = 0x0
759 09:30:54.357219 RD_PRE = 0x0
760 09:30:54.360625 WR_PRE = 0x1
761 09:30:54.360815 WR_PST = 0x0
762 09:30:54.363758 DBI_WR = 0x0
763 09:30:54.363916 DBI_RD = 0x0
764 09:30:54.367270 OTF = 0x1
765 09:30:54.370884 ===================================
766 09:30:54.373741 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 09:30:54.379336 nWR fixed to 40
768 09:30:54.382115 [ModeRegInit_LP4] CH0 RK0
769 09:30:54.382235 [ModeRegInit_LP4] CH0 RK1
770 09:30:54.385966 [ModeRegInit_LP4] CH1 RK0
771 09:30:54.389055 [ModeRegInit_LP4] CH1 RK1
772 09:30:54.389177 match AC timing 12
773 09:30:54.395467 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 09:30:54.399298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 09:30:54.402319 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 09:30:54.409073 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 09:30:54.412528 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 09:30:54.412639 [EMI DOE] emi_dcm 0
779 09:30:54.419205 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 09:30:54.419313 ==
781 09:30:54.422619 Dram Type= 6, Freq= 0, CH_0, rank 0
782 09:30:54.426102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 09:30:54.426209 ==
784 09:30:54.432733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 09:30:54.436012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 09:30:54.446764 [CA 0] Center 37 (7~68) winsize 62
787 09:30:54.449833 [CA 1] Center 37 (7~68) winsize 62
788 09:30:54.453362 [CA 2] Center 35 (5~66) winsize 62
789 09:30:54.456469 [CA 3] Center 35 (5~66) winsize 62
790 09:30:54.460161 [CA 4] Center 34 (3~65) winsize 63
791 09:30:54.463261 [CA 5] Center 34 (3~65) winsize 63
792 09:30:54.463675
793 09:30:54.466586 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 09:30:54.466893
795 09:30:54.469791 [CATrainingPosCal] consider 1 rank data
796 09:30:54.473094 u2DelayCellTimex100 = 270/100 ps
797 09:30:54.476421 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 09:30:54.480073 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 09:30:54.486338 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 09:30:54.489852 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 09:30:54.492959 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
802 09:30:54.496519 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
803 09:30:54.496677
804 09:30:54.499684 CA PerBit enable=1, Macro0, CA PI delay=34
805 09:30:54.499818
806 09:30:54.502941 [CBTSetCACLKResult] CA Dly = 34
807 09:30:54.503076 CS Dly: 5 (0~36)
808 09:30:54.503184 ==
809 09:30:54.506725 Dram Type= 6, Freq= 0, CH_0, rank 1
810 09:30:54.513755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 09:30:54.513891 ==
812 09:30:54.516476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 09:30:54.523023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 09:30:54.532187 [CA 0] Center 37 (6~68) winsize 63
815 09:30:54.535533 [CA 1] Center 37 (6~68) winsize 63
816 09:30:54.538844 [CA 2] Center 35 (5~66) winsize 62
817 09:30:54.542191 [CA 3] Center 34 (4~65) winsize 62
818 09:30:54.545555 [CA 4] Center 33 (3~64) winsize 62
819 09:30:54.548942 [CA 5] Center 33 (3~64) winsize 62
820 09:30:54.549049
821 09:30:54.552007 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 09:30:54.552144
823 09:30:54.555352 [CATrainingPosCal] consider 2 rank data
824 09:30:54.558831 u2DelayCellTimex100 = 270/100 ps
825 09:30:54.561976 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 09:30:54.565352 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 09:30:54.572292 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 09:30:54.575583 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
829 09:30:54.579457 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 09:30:54.582336 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 09:30:54.582467
832 09:30:54.585706 CA PerBit enable=1, Macro0, CA PI delay=33
833 09:30:54.585820
834 09:30:54.588951 [CBTSetCACLKResult] CA Dly = 33
835 09:30:54.589077 CS Dly: 6 (0~38)
836 09:30:54.589179
837 09:30:54.592533 ----->DramcWriteLeveling(PI) begin...
838 09:30:54.595874 ==
839 09:30:54.596001 Dram Type= 6, Freq= 0, CH_0, rank 0
840 09:30:54.602231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 09:30:54.602363 ==
842 09:30:54.605751 Write leveling (Byte 0): 30 => 30
843 09:30:54.609728 Write leveling (Byte 1): 30 => 30
844 09:30:54.610164 DramcWriteLeveling(PI) end<-----
845 09:30:54.613005
846 09:30:54.613744 ==
847 09:30:54.616715 Dram Type= 6, Freq= 0, CH_0, rank 0
848 09:30:54.620381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 09:30:54.621050 ==
850 09:30:54.621686 [Gating] SW mode calibration
851 09:30:54.627755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 09:30:54.634311 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 09:30:54.638161 0 6 0 | B1->B0 | 3232 3131 | 0 1 | (0 1) (1 0)
854 09:30:54.641498 0 6 4 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
855 09:30:54.648470 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:30:54.651486 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:30:54.655004 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:30:54.661461 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:30:54.665221 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:30:54.668019 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:30:54.674879 0 7 0 | B1->B0 | 2323 2f2f | 1 0 | (0 0) (0 0)
862 09:30:54.678279 0 7 4 | B1->B0 | 3939 3e3e | 1 0 | (0 0) (0 0)
863 09:30:54.681413 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 09:30:54.688365 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 09:30:54.691563 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 09:30:54.694943 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 09:30:54.698576 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 09:30:54.705162 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 09:30:54.708544 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 09:30:54.712024 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 09:30:54.718278 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 09:30:54.721867 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 09:30:54.725277 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 09:30:54.731861 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 09:30:54.734953 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 09:30:54.738868 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 09:30:54.744946 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 09:30:54.748279 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 09:30:54.752085 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 09:30:54.758623 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 09:30:54.762000 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 09:30:54.764956 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 09:30:54.771664 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 09:30:54.775159 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 09:30:54.778214 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 09:30:54.784964 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 09:30:54.785412 Total UI for P1: 0, mck2ui 16
888 09:30:54.788289 best dqsien dly found for B0: ( 0, 10, 2)
889 09:30:54.791684 Total UI for P1: 0, mck2ui 16
890 09:30:54.795068 best dqsien dly found for B1: ( 0, 10, 2)
891 09:30:54.798841 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 09:30:54.804843 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
893 09:30:54.805311
894 09:30:54.808508 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 09:30:54.811475 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
896 09:30:54.815070 [Gating] SW calibration Done
897 09:30:54.815533 ==
898 09:30:54.818787 Dram Type= 6, Freq= 0, CH_0, rank 0
899 09:30:54.821769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 09:30:54.822260 ==
901 09:30:54.822744 RX Vref Scan: 0
902 09:30:54.825063
903 09:30:54.825508 RX Vref 0 -> 0, step: 1
904 09:30:54.825979
905 09:30:54.828350 RX Delay -130 -> 252, step: 16
906 09:30:54.831770 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
907 09:30:54.835386 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 09:30:54.841877 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
909 09:30:54.844987 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 09:30:54.848056 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 09:30:54.851631 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
912 09:30:54.854913 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 09:30:54.861829 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 09:30:54.864874 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 09:30:54.868349 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
916 09:30:54.871542 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
917 09:30:54.874883 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 09:30:54.881634 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 09:30:54.885228 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 09:30:54.888126 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 09:30:54.891942 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 09:30:54.892421 ==
923 09:30:54.894821 Dram Type= 6, Freq= 0, CH_0, rank 0
924 09:30:54.901451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 09:30:54.901925 ==
926 09:30:54.902277 DQS Delay:
927 09:30:54.904838 DQS0 = 0, DQS1 = 0
928 09:30:54.905278 DQM Delay:
929 09:30:54.905632 DQM0 = 85, DQM1 = 76
930 09:30:54.908330 DQ Delay:
931 09:30:54.911538 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
932 09:30:54.914733 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
933 09:30:54.918311 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
934 09:30:54.921813 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 09:30:54.922254
936 09:30:54.922602
937 09:30:54.922929 ==
938 09:30:54.924767 Dram Type= 6, Freq= 0, CH_0, rank 0
939 09:30:54.928159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 09:30:54.928636 ==
941 09:30:54.928988
942 09:30:54.929312
943 09:30:54.931671 TX Vref Scan disable
944 09:30:54.932109 == TX Byte 0 ==
945 09:30:54.938440 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 09:30:54.941900 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 09:30:54.942343 == TX Byte 1 ==
948 09:30:54.948449 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 09:30:54.951816 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 09:30:54.952307 ==
951 09:30:54.954807 Dram Type= 6, Freq= 0, CH_0, rank 0
952 09:30:54.958241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 09:30:54.958682 ==
954 09:30:54.971755 TX Vref=22, minBit 0, minWin=27, winSum=441
955 09:30:54.975466 TX Vref=24, minBit 0, minWin=27, winSum=447
956 09:30:54.978693 TX Vref=26, minBit 4, minWin=27, winSum=453
957 09:30:54.981856 TX Vref=28, minBit 5, minWin=27, winSum=455
958 09:30:54.985192 TX Vref=30, minBit 1, minWin=28, winSum=453
959 09:30:54.991774 TX Vref=32, minBit 5, minWin=27, winSum=454
960 09:30:54.995059 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
961 09:30:54.995502
962 09:30:54.998689 Final TX Range 1 Vref 30
963 09:30:54.999176
964 09:30:54.999528 ==
965 09:30:55.001866 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:30:55.006128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 09:30:55.006593 ==
968 09:30:55.006942
969 09:30:55.009142
970 09:30:55.009580 TX Vref Scan disable
971 09:30:55.012239 == TX Byte 0 ==
972 09:30:55.015697 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 09:30:55.018945 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 09:30:55.022361 == TX Byte 1 ==
975 09:30:55.025770 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 09:30:55.028684 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 09:30:55.028769
978 09:30:55.032104 [DATLAT]
979 09:30:55.032195 Freq=800, CH0 RK0
980 09:30:55.032264
981 09:30:55.035144 DATLAT Default: 0xa
982 09:30:55.035228 0, 0xFFFF, sum = 0
983 09:30:55.038497 1, 0xFFFF, sum = 0
984 09:30:55.038592 2, 0xFFFF, sum = 0
985 09:30:55.041921 3, 0xFFFF, sum = 0
986 09:30:55.042022 4, 0xFFFF, sum = 0
987 09:30:55.045363 5, 0xFFFF, sum = 0
988 09:30:55.045449 6, 0xFFFF, sum = 0
989 09:30:55.048537 7, 0xFFFF, sum = 0
990 09:30:55.048624 8, 0x0, sum = 1
991 09:30:55.051841 9, 0x0, sum = 2
992 09:30:55.051933 10, 0x0, sum = 3
993 09:30:55.055106 11, 0x0, sum = 4
994 09:30:55.055199 best_step = 9
995 09:30:55.055272
996 09:30:55.055340 ==
997 09:30:55.058657 Dram Type= 6, Freq= 0, CH_0, rank 0
998 09:30:55.061736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 09:30:55.065016 ==
1000 09:30:55.065102 RX Vref Scan: 1
1001 09:30:55.065170
1002 09:30:55.068389 Set Vref Range= 32 -> 127
1003 09:30:55.068474
1004 09:30:55.068542 RX Vref 32 -> 127, step: 1
1005 09:30:55.072096
1006 09:30:55.072232 RX Delay -95 -> 252, step: 8
1007 09:30:55.072302
1008 09:30:55.075643 Set Vref, RX VrefLevel [Byte0]: 32
1009 09:30:55.078553 [Byte1]: 32
1010 09:30:55.082397
1011 09:30:55.082495 Set Vref, RX VrefLevel [Byte0]: 33
1012 09:30:55.085292 [Byte1]: 33
1013 09:30:55.089502
1014 09:30:55.089587 Set Vref, RX VrefLevel [Byte0]: 34
1015 09:30:55.093150 [Byte1]: 34
1016 09:30:55.097413
1017 09:30:55.097504 Set Vref, RX VrefLevel [Byte0]: 35
1018 09:30:55.100664 [Byte1]: 35
1019 09:30:55.104983
1020 09:30:55.105080 Set Vref, RX VrefLevel [Byte0]: 36
1021 09:30:55.108170 [Byte1]: 36
1022 09:30:55.112439
1023 09:30:55.112554 Set Vref, RX VrefLevel [Byte0]: 37
1024 09:30:55.115788 [Byte1]: 37
1025 09:30:55.120227
1026 09:30:55.120355 Set Vref, RX VrefLevel [Byte0]: 38
1027 09:30:55.123530 [Byte1]: 38
1028 09:30:55.128340
1029 09:30:55.128770 Set Vref, RX VrefLevel [Byte0]: 39
1030 09:30:55.131766 [Byte1]: 39
1031 09:30:55.135749
1032 09:30:55.135832 Set Vref, RX VrefLevel [Byte0]: 40
1033 09:30:55.138611 [Byte1]: 40
1034 09:30:55.142751
1035 09:30:55.142836 Set Vref, RX VrefLevel [Byte0]: 41
1036 09:30:55.146037 [Byte1]: 41
1037 09:30:55.150719
1038 09:30:55.150816 Set Vref, RX VrefLevel [Byte0]: 42
1039 09:30:55.153915 [Byte1]: 42
1040 09:30:55.158216
1041 09:30:55.158320 Set Vref, RX VrefLevel [Byte0]: 43
1042 09:30:55.161578 [Byte1]: 43
1043 09:30:55.165815
1044 09:30:55.165939 Set Vref, RX VrefLevel [Byte0]: 44
1045 09:30:55.169327 [Byte1]: 44
1046 09:30:55.173577
1047 09:30:55.173715 Set Vref, RX VrefLevel [Byte0]: 45
1048 09:30:55.177535 [Byte1]: 45
1049 09:30:55.181367
1050 09:30:55.181795 Set Vref, RX VrefLevel [Byte0]: 46
1051 09:30:55.184568 [Byte1]: 46
1052 09:30:55.188800
1053 09:30:55.189228 Set Vref, RX VrefLevel [Byte0]: 47
1054 09:30:55.192122 [Byte1]: 47
1055 09:30:55.196647
1056 09:30:55.197079 Set Vref, RX VrefLevel [Byte0]: 48
1057 09:30:55.199860 [Byte1]: 48
1058 09:30:55.203872
1059 09:30:55.204480 Set Vref, RX VrefLevel [Byte0]: 49
1060 09:30:55.207428 [Byte1]: 49
1061 09:30:55.211774
1062 09:30:55.212241 Set Vref, RX VrefLevel [Byte0]: 50
1063 09:30:55.214903 [Byte1]: 50
1064 09:30:55.219120
1065 09:30:55.219604 Set Vref, RX VrefLevel [Byte0]: 51
1066 09:30:55.222430 [Byte1]: 51
1067 09:30:55.226994
1068 09:30:55.227528 Set Vref, RX VrefLevel [Byte0]: 52
1069 09:30:55.230397 [Byte1]: 52
1070 09:30:55.234372
1071 09:30:55.234798 Set Vref, RX VrefLevel [Byte0]: 53
1072 09:30:55.237907 [Byte1]: 53
1073 09:30:55.242211
1074 09:30:55.242643 Set Vref, RX VrefLevel [Byte0]: 54
1075 09:30:55.245638 [Byte1]: 54
1076 09:30:55.249995
1077 09:30:55.250429 Set Vref, RX VrefLevel [Byte0]: 55
1078 09:30:55.252835 [Byte1]: 55
1079 09:30:55.257065
1080 09:30:55.257536 Set Vref, RX VrefLevel [Byte0]: 56
1081 09:30:55.260635 [Byte1]: 56
1082 09:30:55.264798
1083 09:30:55.265229 Set Vref, RX VrefLevel [Byte0]: 57
1084 09:30:55.268096 [Byte1]: 57
1085 09:30:55.272496
1086 09:30:55.272955 Set Vref, RX VrefLevel [Byte0]: 58
1087 09:30:55.276118 [Byte1]: 58
1088 09:30:55.280293
1089 09:30:55.280733 Set Vref, RX VrefLevel [Byte0]: 59
1090 09:30:55.283570 [Byte1]: 59
1091 09:30:55.287845
1092 09:30:55.288445 Set Vref, RX VrefLevel [Byte0]: 60
1093 09:30:55.291145 [Byte1]: 60
1094 09:30:55.295293
1095 09:30:55.295723 Set Vref, RX VrefLevel [Byte0]: 61
1096 09:30:55.298651 [Byte1]: 61
1097 09:30:55.302479
1098 09:30:55.302921 Set Vref, RX VrefLevel [Byte0]: 62
1099 09:30:55.306131 [Byte1]: 62
1100 09:30:55.310510
1101 09:30:55.310937 Set Vref, RX VrefLevel [Byte0]: 63
1102 09:30:55.314121 [Byte1]: 63
1103 09:30:55.318118
1104 09:30:55.318547 Set Vref, RX VrefLevel [Byte0]: 64
1105 09:30:55.321344 [Byte1]: 64
1106 09:30:55.325408
1107 09:30:55.325838 Set Vref, RX VrefLevel [Byte0]: 65
1108 09:30:55.328967 [Byte1]: 65
1109 09:30:55.333066
1110 09:30:55.333494 Set Vref, RX VrefLevel [Byte0]: 66
1111 09:30:55.336233 [Byte1]: 66
1112 09:30:55.340792
1113 09:30:55.341223 Set Vref, RX VrefLevel [Byte0]: 67
1114 09:30:55.343837 [Byte1]: 67
1115 09:30:55.348408
1116 09:30:55.349031 Set Vref, RX VrefLevel [Byte0]: 68
1117 09:30:55.351914 [Byte1]: 68
1118 09:30:55.356286
1119 09:30:55.356784 Set Vref, RX VrefLevel [Byte0]: 69
1120 09:30:55.359197 [Byte1]: 69
1121 09:30:55.363467
1122 09:30:55.363897 Set Vref, RX VrefLevel [Byte0]: 70
1123 09:30:55.366811 [Byte1]: 70
1124 09:30:55.371324
1125 09:30:55.371752 Set Vref, RX VrefLevel [Byte0]: 71
1126 09:30:55.374264 [Byte1]: 71
1127 09:30:55.378933
1128 09:30:55.379360 Set Vref, RX VrefLevel [Byte0]: 72
1129 09:30:55.381841 [Byte1]: 72
1130 09:30:55.386287
1131 09:30:55.386713 Set Vref, RX VrefLevel [Byte0]: 73
1132 09:30:55.389514 [Byte1]: 73
1133 09:30:55.393837
1134 09:30:55.394264 Final RX Vref Byte 0 = 51 to rank0
1135 09:30:55.397109 Final RX Vref Byte 1 = 56 to rank0
1136 09:30:55.400418 Final RX Vref Byte 0 = 51 to rank1
1137 09:30:55.404218 Final RX Vref Byte 1 = 56 to rank1==
1138 09:30:55.407145 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 09:30:55.414084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 09:30:55.414519 ==
1141 09:30:55.414864 DQS Delay:
1142 09:30:55.415293 DQS0 = 0, DQS1 = 0
1143 09:30:55.417432 DQM Delay:
1144 09:30:55.417865 DQM0 = 83, DQM1 = 73
1145 09:30:55.420545 DQ Delay:
1146 09:30:55.424060 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1147 09:30:55.424529 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1148 09:30:55.427290 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1149 09:30:55.430321 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1150 09:30:55.433748
1151 09:30:55.434175
1152 09:30:55.440657 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1153 09:30:55.444023 CH0 RK0: MR19=606, MR18=3D3D
1154 09:30:55.450424 CH0_RK0: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1155 09:30:55.450859
1156 09:30:55.453940 ----->DramcWriteLeveling(PI) begin...
1157 09:30:55.454381 ==
1158 09:30:55.457019 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 09:30:55.460899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 09:30:55.461334 ==
1161 09:30:55.463701 Write leveling (Byte 0): 29 => 29
1162 09:30:55.466919 Write leveling (Byte 1): 29 => 29
1163 09:30:55.470277 DramcWriteLeveling(PI) end<-----
1164 09:30:55.470733
1165 09:30:55.471075 ==
1166 09:30:55.474082 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 09:30:55.477127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 09:30:55.477559 ==
1169 09:30:55.480549 [Gating] SW mode calibration
1170 09:30:55.487578 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 09:30:55.494168 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 09:30:55.497293 0 6 0 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 1)
1173 09:30:55.500659 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1174 09:30:55.507136 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:30:55.510772 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:30:55.514025 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:30:55.520623 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:30:55.524028 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:30:55.527279 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:30:55.534061 0 7 0 | B1->B0 | 2a2a 2d2d | 0 1 | (0 0) (0 0)
1181 09:30:55.537215 0 7 4 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1182 09:30:55.540751 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 09:30:55.543893 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 09:30:55.550714 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 09:30:55.554138 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 09:30:55.557533 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 09:30:55.563976 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 09:30:55.567368 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1189 09:30:55.570605 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1190 09:30:55.577522 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 09:30:55.580778 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 09:30:55.584238 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 09:30:55.590804 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 09:30:55.594072 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 09:30:55.597621 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 09:30:55.604138 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 09:30:55.607436 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 09:30:55.610603 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 09:30:55.617377 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 09:30:55.620669 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 09:30:55.623950 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 09:30:55.627589 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 09:30:55.634131 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1204 09:30:55.637807 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 09:30:55.641022 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1206 09:30:55.644169 Total UI for P1: 0, mck2ui 16
1207 09:30:55.647714 best dqsien dly found for B1: ( 0, 9, 30)
1208 09:30:55.654240 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 09:30:55.654674 Total UI for P1: 0, mck2ui 16
1210 09:30:55.660952 best dqsien dly found for B0: ( 0, 10, 2)
1211 09:30:55.664146 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1212 09:30:55.667533 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1213 09:30:55.667966
1214 09:30:55.670901 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1215 09:30:55.674083 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1216 09:30:55.677546 [Gating] SW calibration Done
1217 09:30:55.677976 ==
1218 09:30:55.681245 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 09:30:55.684041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 09:30:55.684522 ==
1221 09:30:55.687591 RX Vref Scan: 0
1222 09:30:55.688025
1223 09:30:55.688462 RX Vref 0 -> 0, step: 1
1224 09:30:55.688799
1225 09:30:55.731638 RX Delay -130 -> 252, step: 16
1226 09:30:55.732257 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1227 09:30:55.732657 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1228 09:30:55.733367 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1229 09:30:55.733759 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1230 09:30:55.734110 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1231 09:30:55.734445 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1232 09:30:55.734771 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1233 09:30:55.735163 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1234 09:30:55.735507 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1235 09:30:55.735831 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1236 09:30:55.737004 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1237 09:30:55.740286 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1238 09:30:55.744107 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1239 09:30:55.746977 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1240 09:30:55.750217 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1241 09:30:55.756985 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1242 09:30:55.757431 ==
1243 09:30:55.760131 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 09:30:55.763703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1245 09:30:55.764316 ==
1246 09:30:55.764853 DQS Delay:
1247 09:30:55.767111 DQS0 = 0, DQS1 = 0
1248 09:30:55.767556 DQM Delay:
1249 09:30:55.770457 DQM0 = 82, DQM1 = 74
1250 09:30:55.770886 DQ Delay:
1251 09:30:55.773458 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1252 09:30:55.777377 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1253 09:30:55.780368 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1254 09:30:55.783322 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 09:30:55.783879
1256 09:30:55.784418
1257 09:30:55.784835 ==
1258 09:30:55.786985 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 09:30:55.790392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 09:30:55.790970 ==
1261 09:30:55.791501
1262 09:30:55.793579
1263 09:30:55.794016 TX Vref Scan disable
1264 09:30:55.797319 == TX Byte 0 ==
1265 09:30:55.800323 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1266 09:30:55.803591 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1267 09:30:55.806993 == TX Byte 1 ==
1268 09:30:55.810205 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1269 09:30:55.813630 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1270 09:30:55.814066 ==
1271 09:30:55.816755 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 09:30:55.823614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 09:30:55.824055 ==
1274 09:30:55.835166 TX Vref=22, minBit 0, minWin=27, winSum=450
1275 09:30:55.838550 TX Vref=24, minBit 0, minWin=27, winSum=451
1276 09:30:55.841871 TX Vref=26, minBit 2, minWin=28, winSum=457
1277 09:30:55.845181 TX Vref=28, minBit 2, minWin=28, winSum=457
1278 09:30:55.848437 TX Vref=30, minBit 2, minWin=28, winSum=459
1279 09:30:55.852259 TX Vref=32, minBit 2, minWin=28, winSum=458
1280 09:30:55.858967 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1281 09:30:55.859556
1282 09:30:55.862816 Final TX Range 1 Vref 30
1283 09:30:55.863243
1284 09:30:55.863579 ==
1285 09:30:55.866383 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 09:30:55.870467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 09:30:55.871036 ==
1288 09:30:55.871527
1289 09:30:55.871855
1290 09:30:55.872326 TX Vref Scan disable
1291 09:30:55.875109 == TX Byte 0 ==
1292 09:30:55.878406 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1293 09:30:55.881759 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1294 09:30:55.885194 == TX Byte 1 ==
1295 09:30:55.888998 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1296 09:30:55.891522 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1297 09:30:55.895260
1298 09:30:55.895684 [DATLAT]
1299 09:30:55.896025 Freq=800, CH0 RK1
1300 09:30:55.896401
1301 09:30:55.898586 DATLAT Default: 0x9
1302 09:30:55.899009 0, 0xFFFF, sum = 0
1303 09:30:55.901937 1, 0xFFFF, sum = 0
1304 09:30:55.902370 2, 0xFFFF, sum = 0
1305 09:30:55.905029 3, 0xFFFF, sum = 0
1306 09:30:55.905463 4, 0xFFFF, sum = 0
1307 09:30:55.908452 5, 0xFFFF, sum = 0
1308 09:30:55.908887 6, 0xFFFF, sum = 0
1309 09:30:55.911603 7, 0xFFFF, sum = 0
1310 09:30:55.912033 8, 0x0, sum = 1
1311 09:30:55.914874 9, 0x0, sum = 2
1312 09:30:55.915305 10, 0x0, sum = 3
1313 09:30:55.918405 11, 0x0, sum = 4
1314 09:30:55.918795 best_step = 9
1315 09:30:55.919116
1316 09:30:55.919421 ==
1317 09:30:55.921962 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 09:30:55.928616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 09:30:55.929045 ==
1320 09:30:55.929382 RX Vref Scan: 0
1321 09:30:55.929703
1322 09:30:55.931711 RX Vref 0 -> 0, step: 1
1323 09:30:55.932136
1324 09:30:55.935165 RX Delay -111 -> 252, step: 8
1325 09:30:55.938847 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1326 09:30:55.942102 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1327 09:30:55.945407 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1328 09:30:55.951896 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1329 09:30:55.955109 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1330 09:30:55.958452 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1331 09:30:55.961728 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1332 09:30:55.965584 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1333 09:30:55.972077 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1334 09:30:55.975144 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1335 09:30:55.978598 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1336 09:30:55.981870 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1337 09:30:55.985281 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1338 09:30:55.992025 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1339 09:30:55.995398 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1340 09:30:55.998637 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1341 09:30:55.999064 ==
1342 09:30:56.001794 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 09:30:56.005154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1344 09:30:56.005587 ==
1345 09:30:56.008599 DQS Delay:
1346 09:30:56.009025 DQS0 = 0, DQS1 = 0
1347 09:30:56.011890 DQM Delay:
1348 09:30:56.012348 DQM0 = 86, DQM1 = 74
1349 09:30:56.012693 DQ Delay:
1350 09:30:56.015445 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1351 09:30:56.018773 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1352 09:30:56.021796 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1353 09:30:56.025622 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1354 09:30:56.026050
1355 09:30:56.026386
1356 09:30:56.035027 [DQSOSCAuto] RK1, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1357 09:30:56.038512 CH0 RK1: MR19=606, MR18=4747
1358 09:30:56.044979 CH0_RK1: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1359 09:30:56.045408 [RxdqsGatingPostProcess] freq 800
1360 09:30:56.051457 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 09:30:56.055270 Pre-setting of DQS Precalculation
1362 09:30:56.058445 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1363 09:30:56.061592 ==
1364 09:30:56.062014 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 09:30:56.067947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 09:30:56.068441 ==
1367 09:30:56.071275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 09:30:56.078132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 09:30:56.087950 [CA 0] Center 37 (6~68) winsize 63
1370 09:30:56.091107 [CA 1] Center 37 (6~68) winsize 63
1371 09:30:56.094648 [CA 2] Center 34 (4~65) winsize 62
1372 09:30:56.097825 [CA 3] Center 34 (4~65) winsize 62
1373 09:30:56.100940 [CA 4] Center 33 (3~64) winsize 62
1374 09:30:56.104236 [CA 5] Center 33 (3~64) winsize 62
1375 09:30:56.104664
1376 09:30:56.107742 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 09:30:56.108225
1378 09:30:56.111053 [CATrainingPosCal] consider 1 rank data
1379 09:30:56.114478 u2DelayCellTimex100 = 270/100 ps
1380 09:30:56.117661 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 09:30:56.120867 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 09:30:56.127906 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 09:30:56.130784 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 09:30:56.134940 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1385 09:30:56.137781 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 09:30:56.138208
1387 09:30:56.141129 CA PerBit enable=1, Macro0, CA PI delay=33
1388 09:30:56.141552
1389 09:30:56.144235 [CBTSetCACLKResult] CA Dly = 33
1390 09:30:56.144676 CS Dly: 4 (0~35)
1391 09:30:56.147468 ==
1392 09:30:56.147891 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 09:30:56.154036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1394 09:30:56.154477 ==
1395 09:30:56.157506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 09:30:56.164279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 09:30:56.173644 [CA 0] Center 36 (6~67) winsize 62
1398 09:30:56.177018 [CA 1] Center 37 (6~68) winsize 63
1399 09:30:56.180584 [CA 2] Center 34 (4~65) winsize 62
1400 09:30:56.183707 [CA 3] Center 34 (4~65) winsize 62
1401 09:30:56.186773 [CA 4] Center 33 (3~64) winsize 62
1402 09:30:56.190228 [CA 5] Center 33 (3~64) winsize 62
1403 09:30:56.190651
1404 09:30:56.193995 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1405 09:30:56.194419
1406 09:30:56.196978 [CATrainingPosCal] consider 2 rank data
1407 09:30:56.200395 u2DelayCellTimex100 = 270/100 ps
1408 09:30:56.203542 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1409 09:30:56.207129 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1410 09:30:56.213842 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 09:30:56.216916 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 09:30:56.220686 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 09:30:56.223819 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 09:30:56.224285
1415 09:30:56.227178 CA PerBit enable=1, Macro0, CA PI delay=33
1416 09:30:56.227602
1417 09:30:56.230816 [CBTSetCACLKResult] CA Dly = 33
1418 09:30:56.231337 CS Dly: 4 (0~36)
1419 09:30:56.231713
1420 09:30:56.233509 ----->DramcWriteLeveling(PI) begin...
1421 09:30:56.237007 ==
1422 09:30:56.237485 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 09:30:56.243704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 09:30:56.244131 ==
1425 09:30:56.246825 Write leveling (Byte 0): 24 => 24
1426 09:30:56.250110 Write leveling (Byte 1): 25 => 25
1427 09:30:56.253374 DramcWriteLeveling(PI) end<-----
1428 09:30:56.253932
1429 09:30:56.254325 ==
1430 09:30:56.257281 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 09:30:56.260126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 09:30:56.260718 ==
1433 09:30:56.263331 [Gating] SW mode calibration
1434 09:30:56.270034 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 09:30:56.276825 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 09:30:56.280091 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
1437 09:30:56.283215 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1438 09:30:56.286877 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 09:30:56.293452 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 09:30:56.296986 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 09:30:56.299964 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 09:30:56.306463 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 09:30:56.310070 0 6 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1444 09:30:56.313372 0 7 0 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
1445 09:30:56.320227 0 7 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1446 09:30:56.323249 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 09:30:56.327152 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 09:30:56.333329 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 09:30:56.336656 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 09:30:56.340274 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 09:30:56.346961 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 09:30:56.350260 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1453 09:30:56.353507 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 09:30:56.356942 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 09:30:56.363584 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 09:30:56.366987 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 09:30:56.370512 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 09:30:56.377532 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 09:30:56.380097 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 09:30:56.383521 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 09:30:56.390130 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 09:30:56.393482 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 09:30:56.396715 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 09:30:56.403845 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 09:30:56.407556 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 09:30:56.410281 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 09:30:56.416953 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1468 09:30:56.420796 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1469 09:30:56.424055 Total UI for P1: 0, mck2ui 16
1470 09:30:56.427143 best dqsien dly found for B0: ( 0, 9, 28)
1471 09:30:56.430718 Total UI for P1: 0, mck2ui 16
1472 09:30:56.433665 best dqsien dly found for B1: ( 0, 9, 28)
1473 09:30:56.436677 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1474 09:30:56.440545 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1475 09:30:56.441114
1476 09:30:56.443776 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1477 09:30:56.447128 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1478 09:30:56.450498 [Gating] SW calibration Done
1479 09:30:56.451065 ==
1480 09:30:56.453841 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 09:30:56.457118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 09:30:56.457597 ==
1483 09:30:56.460377 RX Vref Scan: 0
1484 09:30:56.460844
1485 09:30:56.463646 RX Vref 0 -> 0, step: 1
1486 09:30:56.464112
1487 09:30:56.464522 RX Delay -130 -> 252, step: 16
1488 09:30:56.470297 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1489 09:30:56.473770 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1490 09:30:56.477314 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1491 09:30:56.480741 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1492 09:30:56.483958 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1493 09:30:56.490652 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1494 09:30:56.494461 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1495 09:30:56.496955 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1496 09:30:56.500164 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1497 09:30:56.503562 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1498 09:30:56.510569 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1499 09:30:56.513676 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1500 09:30:56.517422 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1501 09:30:56.521453 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1502 09:30:56.524832 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1503 09:30:56.528718 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1504 09:30:56.529315 ==
1505 09:30:56.532010 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 09:30:56.536051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1507 09:30:56.536709 ==
1508 09:30:56.539717 DQS Delay:
1509 09:30:56.540359 DQS0 = 0, DQS1 = 0
1510 09:30:56.540892 DQM Delay:
1511 09:30:56.543481 DQM0 = 80, DQM1 = 73
1512 09:30:56.544074 DQ Delay:
1513 09:30:56.546767 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1514 09:30:56.550477 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1515 09:30:56.554384 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1516 09:30:56.557554 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1517 09:30:56.558046
1518 09:30:56.558538
1519 09:30:56.559007 ==
1520 09:30:56.560684 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 09:30:56.564097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1522 09:30:56.564650 ==
1523 09:30:56.565145
1524 09:30:56.565605
1525 09:30:56.567582 TX Vref Scan disable
1526 09:30:56.570890 == TX Byte 0 ==
1527 09:30:56.573948 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1528 09:30:56.577724 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1529 09:30:56.580946 == TX Byte 1 ==
1530 09:30:56.584264 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1531 09:30:56.588148 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1532 09:30:56.588778 ==
1533 09:30:56.591134 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 09:30:56.597794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1535 09:30:56.598376 ==
1536 09:30:56.609102 TX Vref=22, minBit 3, minWin=27, winSum=448
1537 09:30:56.612261 TX Vref=24, minBit 3, minWin=27, winSum=449
1538 09:30:56.615502 TX Vref=26, minBit 8, minWin=27, winSum=450
1539 09:30:56.618696 TX Vref=28, minBit 3, minWin=27, winSum=455
1540 09:30:56.622495 TX Vref=30, minBit 1, minWin=28, winSum=461
1541 09:30:56.625617 TX Vref=32, minBit 0, minWin=28, winSum=456
1542 09:30:56.632372 [TxChooseVref] Worse bit 1, Min win 28, Win sum 461, Final Vref 30
1543 09:30:56.632952
1544 09:30:56.635428 Final TX Range 1 Vref 30
1545 09:30:56.635897
1546 09:30:56.636320 ==
1547 09:30:56.638699 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 09:30:56.642043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1549 09:30:56.642516 ==
1550 09:30:56.642892
1551 09:30:56.645683
1552 09:30:56.646263 TX Vref Scan disable
1553 09:30:56.649000 == TX Byte 0 ==
1554 09:30:56.652386 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1555 09:30:56.655479 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1556 09:30:56.658797 == TX Byte 1 ==
1557 09:30:56.662128 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1558 09:30:56.665837 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1559 09:30:56.668836
1560 09:30:56.669328 [DATLAT]
1561 09:30:56.669821 Freq=800, CH1 RK0
1562 09:30:56.670289
1563 09:30:56.672070 DATLAT Default: 0xa
1564 09:30:56.672600 0, 0xFFFF, sum = 0
1565 09:30:56.675559 1, 0xFFFF, sum = 0
1566 09:30:56.676146 2, 0xFFFF, sum = 0
1567 09:30:56.678845 3, 0xFFFF, sum = 0
1568 09:30:56.679418 4, 0xFFFF, sum = 0
1569 09:30:56.682222 5, 0xFFFF, sum = 0
1570 09:30:56.682817 6, 0xFFFF, sum = 0
1571 09:30:56.685612 7, 0xFFFF, sum = 0
1572 09:30:56.686110 8, 0x0, sum = 1
1573 09:30:56.689043 9, 0x0, sum = 2
1574 09:30:56.689535 10, 0x0, sum = 3
1575 09:30:56.692774 11, 0x0, sum = 4
1576 09:30:56.693368 best_step = 9
1577 09:30:56.693867
1578 09:30:56.694328 ==
1579 09:30:56.695272 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 09:30:56.702700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1581 09:30:56.703298 ==
1582 09:30:56.703802 RX Vref Scan: 1
1583 09:30:56.704321
1584 09:30:56.705264 Set Vref Range= 32 -> 127
1585 09:30:56.705750
1586 09:30:56.709080 RX Vref 32 -> 127, step: 1
1587 09:30:56.709666
1588 09:30:56.710160 RX Delay -111 -> 252, step: 8
1589 09:30:56.712081
1590 09:30:56.712640 Set Vref, RX VrefLevel [Byte0]: 32
1591 09:30:56.715628 [Byte1]: 32
1592 09:30:56.719926
1593 09:30:56.720561 Set Vref, RX VrefLevel [Byte0]: 33
1594 09:30:56.723354 [Byte1]: 33
1595 09:30:56.727727
1596 09:30:56.728361 Set Vref, RX VrefLevel [Byte0]: 34
1597 09:30:56.730911 [Byte1]: 34
1598 09:30:56.735477
1599 09:30:56.736059 Set Vref, RX VrefLevel [Byte0]: 35
1600 09:30:56.738168 [Byte1]: 35
1601 09:30:56.742551
1602 09:30:56.743036 Set Vref, RX VrefLevel [Byte0]: 36
1603 09:30:56.746192 [Byte1]: 36
1604 09:30:56.750465
1605 09:30:56.751051 Set Vref, RX VrefLevel [Byte0]: 37
1606 09:30:56.753427 [Byte1]: 37
1607 09:30:56.757776
1608 09:30:56.758242 Set Vref, RX VrefLevel [Byte0]: 38
1609 09:30:56.761365 [Byte1]: 38
1610 09:30:56.765498
1611 09:30:56.765963 Set Vref, RX VrefLevel [Byte0]: 39
1612 09:30:56.768742 [Byte1]: 39
1613 09:30:56.773236
1614 09:30:56.773815 Set Vref, RX VrefLevel [Byte0]: 40
1615 09:30:56.776551 [Byte1]: 40
1616 09:30:56.781242
1617 09:30:56.781813 Set Vref, RX VrefLevel [Byte0]: 41
1618 09:30:56.784822 [Byte1]: 41
1619 09:30:56.788581
1620 09:30:56.789154 Set Vref, RX VrefLevel [Byte0]: 42
1621 09:30:56.792116 [Byte1]: 42
1622 09:30:56.796419
1623 09:30:56.796983 Set Vref, RX VrefLevel [Byte0]: 43
1624 09:30:56.799800 [Byte1]: 43
1625 09:30:56.803769
1626 09:30:56.804408 Set Vref, RX VrefLevel [Byte0]: 44
1627 09:30:56.807369 [Byte1]: 44
1628 09:30:56.811815
1629 09:30:56.812430 Set Vref, RX VrefLevel [Byte0]: 45
1630 09:30:56.815106 [Byte1]: 45
1631 09:30:56.818972
1632 09:30:56.819443 Set Vref, RX VrefLevel [Byte0]: 46
1633 09:30:56.822788 [Byte1]: 46
1634 09:30:56.827158
1635 09:30:56.827728 Set Vref, RX VrefLevel [Byte0]: 47
1636 09:30:56.830108 [Byte1]: 47
1637 09:30:56.834448
1638 09:30:56.835019 Set Vref, RX VrefLevel [Byte0]: 48
1639 09:30:56.837937 [Byte1]: 48
1640 09:30:56.842313
1641 09:30:56.842883 Set Vref, RX VrefLevel [Byte0]: 49
1642 09:30:56.845154 [Byte1]: 49
1643 09:30:56.849834
1644 09:30:56.850404 Set Vref, RX VrefLevel [Byte0]: 50
1645 09:30:56.852804 [Byte1]: 50
1646 09:30:56.857291
1647 09:30:56.857870 Set Vref, RX VrefLevel [Byte0]: 51
1648 09:30:56.860682 [Byte1]: 51
1649 09:30:56.864891
1650 09:30:56.865458 Set Vref, RX VrefLevel [Byte0]: 52
1651 09:30:56.868147 [Byte1]: 52
1652 09:30:56.872726
1653 09:30:56.873308 Set Vref, RX VrefLevel [Byte0]: 53
1654 09:30:56.875753 [Byte1]: 53
1655 09:30:56.880371
1656 09:30:56.880943 Set Vref, RX VrefLevel [Byte0]: 54
1657 09:30:56.883662 [Byte1]: 54
1658 09:30:56.887905
1659 09:30:56.888536 Set Vref, RX VrefLevel [Byte0]: 55
1660 09:30:56.891497 [Byte1]: 55
1661 09:30:56.895937
1662 09:30:56.896551 Set Vref, RX VrefLevel [Byte0]: 56
1663 09:30:56.899070 [Byte1]: 56
1664 09:30:56.903287
1665 09:30:56.903865 Set Vref, RX VrefLevel [Byte0]: 57
1666 09:30:56.906536 [Byte1]: 57
1667 09:30:56.911131
1668 09:30:56.911710 Set Vref, RX VrefLevel [Byte0]: 58
1669 09:30:56.914280 [Byte1]: 58
1670 09:30:56.918666
1671 09:30:56.919284 Set Vref, RX VrefLevel [Byte0]: 59
1672 09:30:56.922302 [Byte1]: 59
1673 09:30:56.926200
1674 09:30:56.926773 Set Vref, RX VrefLevel [Byte0]: 60
1675 09:30:56.929885 [Byte1]: 60
1676 09:30:56.934142
1677 09:30:56.934716 Set Vref, RX VrefLevel [Byte0]: 61
1678 09:30:56.937047 [Byte1]: 61
1679 09:30:56.941557
1680 09:30:56.942127 Set Vref, RX VrefLevel [Byte0]: 62
1681 09:30:56.944603 [Byte1]: 62
1682 09:30:56.949142
1683 09:30:56.949725 Set Vref, RX VrefLevel [Byte0]: 63
1684 09:30:56.952646 [Byte1]: 63
1685 09:30:56.956952
1686 09:30:56.957568 Set Vref, RX VrefLevel [Byte0]: 64
1687 09:30:56.960087 [Byte1]: 64
1688 09:30:56.964412
1689 09:30:56.964996 Set Vref, RX VrefLevel [Byte0]: 65
1690 09:30:56.967559 [Byte1]: 65
1691 09:30:56.972118
1692 09:30:56.972766 Set Vref, RX VrefLevel [Byte0]: 66
1693 09:30:56.975486 [Byte1]: 66
1694 09:30:56.979764
1695 09:30:56.980406 Set Vref, RX VrefLevel [Byte0]: 67
1696 09:30:56.983108 [Byte1]: 67
1697 09:30:56.987518
1698 09:30:56.988100 Set Vref, RX VrefLevel [Byte0]: 68
1699 09:30:56.990656 [Byte1]: 68
1700 09:30:56.995063
1701 09:30:56.995648 Set Vref, RX VrefLevel [Byte0]: 69
1702 09:30:56.998211 [Byte1]: 69
1703 09:30:57.002574
1704 09:30:57.003167 Set Vref, RX VrefLevel [Byte0]: 70
1705 09:30:57.006182 [Byte1]: 70
1706 09:30:57.010106
1707 09:30:57.010591 Set Vref, RX VrefLevel [Byte0]: 71
1708 09:30:57.013815 [Byte1]: 71
1709 09:30:57.018215
1710 09:30:57.018805 Set Vref, RX VrefLevel [Byte0]: 72
1711 09:30:57.021717 [Byte1]: 72
1712 09:30:57.025571
1713 09:30:57.026157 Set Vref, RX VrefLevel [Byte0]: 73
1714 09:30:57.029166 [Byte1]: 73
1715 09:30:57.033082
1716 09:30:57.033662 Set Vref, RX VrefLevel [Byte0]: 74
1717 09:30:57.036633 [Byte1]: 74
1718 09:30:57.040751
1719 09:30:57.041238 Set Vref, RX VrefLevel [Byte0]: 75
1720 09:30:57.044348 [Byte1]: 75
1721 09:30:57.048627
1722 09:30:57.049218 Final RX Vref Byte 0 = 59 to rank0
1723 09:30:57.052038 Final RX Vref Byte 1 = 59 to rank0
1724 09:30:57.055131 Final RX Vref Byte 0 = 59 to rank1
1725 09:30:57.058294 Final RX Vref Byte 1 = 59 to rank1==
1726 09:30:57.061825 Dram Type= 6, Freq= 0, CH_1, rank 0
1727 09:30:57.069132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1728 09:30:57.069728 ==
1729 09:30:57.070230 DQS Delay:
1730 09:30:57.070700 DQS0 = 0, DQS1 = 0
1731 09:30:57.071775 DQM Delay:
1732 09:30:57.072306 DQM0 = 81, DQM1 = 74
1733 09:30:57.075249 DQ Delay:
1734 09:30:57.078687 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1735 09:30:57.079342 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1736 09:30:57.082042 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1737 09:30:57.085418 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1738 09:30:57.088350
1739 09:30:57.088834
1740 09:30:57.095614 [DQSOSCAuto] RK0, (LSB)MR18= 0x5757, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1741 09:30:57.099207 CH1 RK0: MR19=606, MR18=5757
1742 09:30:57.102858 CH1_RK0: MR19=0x606, MR18=0x5757, DQSOSC=388, MR23=63, INC=98, DEC=65
1743 09:30:57.103463
1744 09:30:57.105961 ----->DramcWriteLeveling(PI) begin...
1745 09:30:57.109208 ==
1746 09:30:57.112891 Dram Type= 6, Freq= 0, CH_1, rank 1
1747 09:30:57.116135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1748 09:30:57.116773 ==
1749 09:30:57.119230 Write leveling (Byte 0): 26 => 26
1750 09:30:57.123059 Write leveling (Byte 1): 26 => 26
1751 09:30:57.126331 DramcWriteLeveling(PI) end<-----
1752 09:30:57.126926
1753 09:30:57.127422 ==
1754 09:30:57.129880 Dram Type= 6, Freq= 0, CH_1, rank 1
1755 09:30:57.132731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1756 09:30:57.133220 ==
1757 09:30:57.136115 [Gating] SW mode calibration
1758 09:30:57.142755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1759 09:30:57.146589 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1760 09:30:57.152930 0 6 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
1761 09:30:57.156950 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 09:30:57.159690 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 09:30:57.165820 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 09:30:57.169474 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 09:30:57.172774 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 09:30:57.179377 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 09:30:57.182733 0 6 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1768 09:30:57.186051 0 7 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1769 09:30:57.192772 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 09:30:57.196311 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 09:30:57.199255 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 09:30:57.206247 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 09:30:57.209232 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 09:30:57.212838 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 09:30:57.219337 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1776 09:30:57.222672 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1777 09:30:57.225513 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 09:30:57.232658 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 09:30:57.235730 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 09:30:57.239174 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 09:30:57.245899 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 09:30:57.249098 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 09:30:57.252675 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 09:30:57.255727 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 09:30:57.262509 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 09:30:57.265595 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 09:30:57.268847 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 09:30:57.275811 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 09:30:57.279252 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 09:30:57.282244 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 09:30:57.289284 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1792 09:30:57.292344 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1793 09:30:57.295561 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1794 09:30:57.298825 Total UI for P1: 0, mck2ui 16
1795 09:30:57.302597 best dqsien dly found for B0: ( 0, 9, 30)
1796 09:30:57.305775 Total UI for P1: 0, mck2ui 16
1797 09:30:57.308815 best dqsien dly found for B1: ( 0, 9, 30)
1798 09:30:57.312304 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1799 09:30:57.315716 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1800 09:30:57.316220
1801 09:30:57.322233 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1802 09:30:57.325441 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1803 09:30:57.328777 [Gating] SW calibration Done
1804 09:30:57.329251 ==
1805 09:30:57.332325 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 09:30:57.335645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 09:30:57.336121 ==
1808 09:30:57.336551 RX Vref Scan: 0
1809 09:30:57.336908
1810 09:30:57.339029 RX Vref 0 -> 0, step: 1
1811 09:30:57.339508
1812 09:30:57.341991 RX Delay -130 -> 252, step: 16
1813 09:30:57.345211 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1814 09:30:57.348927 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1815 09:30:57.355436 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1816 09:30:57.358625 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1817 09:30:57.362131 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1818 09:30:57.365539 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1819 09:30:57.369111 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1820 09:30:57.372425 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1821 09:30:57.379075 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1822 09:30:57.382459 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1823 09:30:57.385587 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1824 09:30:57.391917 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1825 09:30:57.395567 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1826 09:30:57.398993 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1827 09:30:57.402325 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1828 09:30:57.405416 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1829 09:30:57.405894 ==
1830 09:30:57.408772 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 09:30:57.416210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1832 09:30:57.416810 ==
1833 09:30:57.417188 DQS Delay:
1834 09:30:57.417539 DQS0 = 0, DQS1 = 0
1835 09:30:57.418796 DQM Delay:
1836 09:30:57.419266 DQM0 = 86, DQM1 = 74
1837 09:30:57.422548 DQ Delay:
1838 09:30:57.425481 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1839 09:30:57.425958 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1840 09:30:57.428838 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1841 09:30:57.435577 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1842 09:30:57.436146
1843 09:30:57.436583
1844 09:30:57.436932 ==
1845 09:30:57.438898 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 09:30:57.442266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1847 09:30:57.442840 ==
1848 09:30:57.443215
1849 09:30:57.443562
1850 09:30:57.445509 TX Vref Scan disable
1851 09:30:57.446083 == TX Byte 0 ==
1852 09:30:57.452238 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1853 09:30:57.455678 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1854 09:30:57.456316 == TX Byte 1 ==
1855 09:30:57.462167 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1856 09:30:57.465380 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1857 09:30:57.466031 ==
1858 09:30:57.468619 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 09:30:57.472257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1860 09:30:57.472732 ==
1861 09:30:57.485584 TX Vref=22, minBit 0, minWin=27, winSum=448
1862 09:30:57.488927 TX Vref=24, minBit 0, minWin=27, winSum=449
1863 09:30:57.492075 TX Vref=26, minBit 8, minWin=27, winSum=455
1864 09:30:57.495851 TX Vref=28, minBit 9, minWin=27, winSum=453
1865 09:30:57.498704 TX Vref=30, minBit 9, minWin=27, winSum=456
1866 09:30:57.502227 TX Vref=32, minBit 0, minWin=28, winSum=454
1867 09:30:57.509056 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1868 09:30:57.509488
1869 09:30:57.512393 Final TX Range 1 Vref 32
1870 09:30:57.512842
1871 09:30:57.513326 ==
1872 09:30:57.515757 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 09:30:57.518843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1874 09:30:57.519273 ==
1875 09:30:57.519612
1876 09:30:57.522308
1877 09:30:57.522731 TX Vref Scan disable
1878 09:30:57.525484 == TX Byte 0 ==
1879 09:30:57.528738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1880 09:30:57.532236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1881 09:30:57.535208 == TX Byte 1 ==
1882 09:30:57.538643 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1883 09:30:57.542080 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1884 09:30:57.545471
1885 09:30:57.545895 [DATLAT]
1886 09:30:57.546253 Freq=800, CH1 RK1
1887 09:30:57.546684
1888 09:30:57.548833 DATLAT Default: 0x9
1889 09:30:57.549429 0, 0xFFFF, sum = 0
1890 09:30:57.552206 1, 0xFFFF, sum = 0
1891 09:30:57.552656 2, 0xFFFF, sum = 0
1892 09:30:57.555452 3, 0xFFFF, sum = 0
1893 09:30:57.555884 4, 0xFFFF, sum = 0
1894 09:30:57.558919 5, 0xFFFF, sum = 0
1895 09:30:57.559354 6, 0xFFFF, sum = 0
1896 09:30:57.562128 7, 0xFFFF, sum = 0
1897 09:30:57.562567 8, 0x0, sum = 1
1898 09:30:57.565352 9, 0x0, sum = 2
1899 09:30:57.565788 10, 0x0, sum = 3
1900 09:30:57.568956 11, 0x0, sum = 4
1901 09:30:57.569423 best_step = 9
1902 09:30:57.569764
1903 09:30:57.570081 ==
1904 09:30:57.572061 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 09:30:57.578980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1906 09:30:57.579415 ==
1907 09:30:57.579763 RX Vref Scan: 0
1908 09:30:57.580082
1909 09:30:57.582296 RX Vref 0 -> 0, step: 1
1910 09:30:57.582728
1911 09:30:57.585405 RX Delay -111 -> 252, step: 8
1912 09:30:57.588758 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1913 09:30:57.592301 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1914 09:30:57.595371 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1915 09:30:57.602210 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1916 09:30:57.605788 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1917 09:30:57.608729 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1918 09:30:57.612161 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1919 09:30:57.615379 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1920 09:30:57.622278 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1921 09:30:57.625695 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1922 09:30:57.628808 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1923 09:30:57.631961 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1924 09:30:57.639048 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1925 09:30:57.641889 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1926 09:30:57.645606 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1927 09:30:57.648948 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1928 09:30:57.649427 ==
1929 09:30:57.652097 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 09:30:57.655613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1931 09:30:57.658829 ==
1932 09:30:57.659413 DQS Delay:
1933 09:30:57.659794 DQS0 = 0, DQS1 = 0
1934 09:30:57.661861 DQM Delay:
1935 09:30:57.662343 DQM0 = 84, DQM1 = 75
1936 09:30:57.665565 DQ Delay:
1937 09:30:57.668466 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =80
1938 09:30:57.668944 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1939 09:30:57.672348 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1940 09:30:57.675374 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1941 09:30:57.679080
1942 09:30:57.679658
1943 09:30:57.685340 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1944 09:30:57.688902 CH1 RK1: MR19=606, MR18=3636
1945 09:30:57.695304 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1946 09:30:57.698823 [RxdqsGatingPostProcess] freq 800
1947 09:30:57.702008 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1948 09:30:57.705462 Pre-setting of DQS Precalculation
1949 09:30:57.708431 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1950 09:30:57.718960 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1951 09:30:57.725669 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1952 09:30:57.726242
1953 09:30:57.726618
1954 09:30:57.728833 [Calibration Summary] 1600 Mbps
1955 09:30:57.729403 CH 0, Rank 0
1956 09:30:57.732121 SW Impedance : PASS
1957 09:30:57.732647 DUTY Scan : NO K
1958 09:30:57.735349 ZQ Calibration : PASS
1959 09:30:57.738933 Jitter Meter : NO K
1960 09:30:57.739515 CBT Training : PASS
1961 09:30:57.741879 Write leveling : PASS
1962 09:30:57.745325 RX DQS gating : PASS
1963 09:30:57.745895 RX DQ/DQS(RDDQC) : PASS
1964 09:30:57.748659 TX DQ/DQS : PASS
1965 09:30:57.752104 RX DATLAT : PASS
1966 09:30:57.752716 RX DQ/DQS(Engine): PASS
1967 09:30:57.755403 TX OE : NO K
1968 09:30:57.755977 All Pass.
1969 09:30:57.756420
1970 09:30:57.758875 CH 0, Rank 1
1971 09:30:57.759446 SW Impedance : PASS
1972 09:30:57.761735 DUTY Scan : NO K
1973 09:30:57.765056 ZQ Calibration : PASS
1974 09:30:57.765557 Jitter Meter : NO K
1975 09:30:57.768563 CBT Training : PASS
1976 09:30:57.769051 Write leveling : PASS
1977 09:30:57.772279 RX DQS gating : PASS
1978 09:30:57.775632 RX DQ/DQS(RDDQC) : PASS
1979 09:30:57.776267 TX DQ/DQS : PASS
1980 09:30:57.778464 RX DATLAT : PASS
1981 09:30:57.782176 RX DQ/DQS(Engine): PASS
1982 09:30:57.782769 TX OE : NO K
1983 09:30:57.785528 All Pass.
1984 09:30:57.786116
1985 09:30:57.786613 CH 1, Rank 0
1986 09:30:57.788755 SW Impedance : PASS
1987 09:30:57.789246 DUTY Scan : NO K
1988 09:30:57.792063 ZQ Calibration : PASS
1989 09:30:57.795296 Jitter Meter : NO K
1990 09:30:57.795882 CBT Training : PASS
1991 09:30:57.798765 Write leveling : PASS
1992 09:30:57.802131 RX DQS gating : PASS
1993 09:30:57.802619 RX DQ/DQS(RDDQC) : PASS
1994 09:30:57.805244 TX DQ/DQS : PASS
1995 09:30:57.805733 RX DATLAT : PASS
1996 09:30:57.808846 RX DQ/DQS(Engine): PASS
1997 09:30:57.812083 TX OE : NO K
1998 09:30:57.812759 All Pass.
1999 09:30:57.813253
2000 09:30:57.813733 CH 1, Rank 1
2001 09:30:57.815519 SW Impedance : PASS
2002 09:30:57.818683 DUTY Scan : NO K
2003 09:30:57.819271 ZQ Calibration : PASS
2004 09:30:57.822038 Jitter Meter : NO K
2005 09:30:57.825124 CBT Training : PASS
2006 09:30:57.825615 Write leveling : PASS
2007 09:30:57.828856 RX DQS gating : PASS
2008 09:30:57.832284 RX DQ/DQS(RDDQC) : PASS
2009 09:30:57.832878 TX DQ/DQS : PASS
2010 09:30:57.835596 RX DATLAT : PASS
2011 09:30:57.838552 RX DQ/DQS(Engine): PASS
2012 09:30:57.839040 TX OE : NO K
2013 09:30:57.841785 All Pass.
2014 09:30:57.842268
2015 09:30:57.842753 DramC Write-DBI off
2016 09:30:57.845492 PER_BANK_REFRESH: Hybrid Mode
2017 09:30:57.846081 TX_TRACKING: ON
2018 09:30:57.848820 [GetDramInforAfterCalByMRR] Vendor 6.
2019 09:30:57.852244 [GetDramInforAfterCalByMRR] Revision 606.
2020 09:30:57.859091 [GetDramInforAfterCalByMRR] Revision 2 0.
2021 09:30:57.859680 MR0 0x3939
2022 09:30:57.860212 MR8 0x1111
2023 09:30:57.862221 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2024 09:30:57.862780
2025 09:30:57.865149 MR0 0x3939
2026 09:30:57.865679 MR8 0x1111
2027 09:30:57.868714 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2028 09:30:57.869190
2029 09:30:57.878383 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2030 09:30:57.882032 [FAST_K] Save calibration result to emmc
2031 09:30:57.885212 [FAST_K] Save calibration result to emmc
2032 09:30:57.888973 dram_init: config_dvfs: 1
2033 09:30:57.892096 dramc_set_vcore_voltage set vcore to 662500
2034 09:30:57.895360 Read voltage for 1200, 2
2035 09:30:57.895947 Vio18 = 0
2036 09:30:57.896484 Vcore = 662500
2037 09:30:57.898560 Vdram = 0
2038 09:30:57.899155 Vddq = 0
2039 09:30:57.899649 Vmddr = 0
2040 09:30:57.905167 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2041 09:30:57.908422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2042 09:30:57.911997 MEM_TYPE=3, freq_sel=15
2043 09:30:57.915429 sv_algorithm_assistance_LP4_1600
2044 09:30:57.918394 ============ PULL DRAM RESETB DOWN ============
2045 09:30:57.921658 ========== PULL DRAM RESETB DOWN end =========
2046 09:30:57.928623 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2047 09:30:57.932000 ===================================
2048 09:30:57.932622 LPDDR4 DRAM CONFIGURATION
2049 09:30:57.935477 ===================================
2050 09:30:57.939033 EX_ROW_EN[0] = 0x0
2051 09:30:57.941832 EX_ROW_EN[1] = 0x0
2052 09:30:57.942322 LP4Y_EN = 0x0
2053 09:30:57.945106 WORK_FSP = 0x0
2054 09:30:57.945695 WL = 0x4
2055 09:30:57.948465 RL = 0x4
2056 09:30:57.949050 BL = 0x2
2057 09:30:57.951831 RPST = 0x0
2058 09:30:57.952363 RD_PRE = 0x0
2059 09:30:57.955259 WR_PRE = 0x1
2060 09:30:57.955849 WR_PST = 0x0
2061 09:30:57.958928 DBI_WR = 0x0
2062 09:30:57.959512 DBI_RD = 0x0
2063 09:30:57.961683 OTF = 0x1
2064 09:30:57.965203 ===================================
2065 09:30:57.968389 ===================================
2066 09:30:57.968865 ANA top config
2067 09:30:57.972287 ===================================
2068 09:30:57.975574 DLL_ASYNC_EN = 0
2069 09:30:57.978510 ALL_SLAVE_EN = 0
2070 09:30:57.979111 NEW_RANK_MODE = 1
2071 09:30:57.981854 DLL_IDLE_MODE = 1
2072 09:30:57.985121 LP45_APHY_COMB_EN = 1
2073 09:30:57.988635 TX_ODT_DIS = 1
2074 09:30:57.992010 NEW_8X_MODE = 1
2075 09:30:57.992648 ===================================
2076 09:30:57.995192 ===================================
2077 09:30:57.998787 data_rate = 2400
2078 09:30:58.001850 CKR = 1
2079 09:30:58.005579 DQ_P2S_RATIO = 8
2080 09:30:58.008675 ===================================
2081 09:30:58.011821 CA_P2S_RATIO = 8
2082 09:30:58.015092 DQ_CA_OPEN = 0
2083 09:30:58.018367 DQ_SEMI_OPEN = 0
2084 09:30:58.018952 CA_SEMI_OPEN = 0
2085 09:30:58.021529 CA_FULL_RATE = 0
2086 09:30:58.025117 DQ_CKDIV4_EN = 0
2087 09:30:58.028390 CA_CKDIV4_EN = 0
2088 09:30:58.031860 CA_PREDIV_EN = 0
2089 09:30:58.034982 PH8_DLY = 17
2090 09:30:58.035452 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2091 09:30:58.038574 DQ_AAMCK_DIV = 4
2092 09:30:58.041682 CA_AAMCK_DIV = 4
2093 09:30:58.044964 CA_ADMCK_DIV = 4
2094 09:30:58.048683 DQ_TRACK_CA_EN = 0
2095 09:30:58.051672 CA_PICK = 1200
2096 09:30:58.054987 CA_MCKIO = 1200
2097 09:30:58.055555 MCKIO_SEMI = 0
2098 09:30:58.058773 PLL_FREQ = 2366
2099 09:30:58.061635 DQ_UI_PI_RATIO = 32
2100 09:30:58.064943 CA_UI_PI_RATIO = 0
2101 09:30:58.067944 ===================================
2102 09:30:58.071562 ===================================
2103 09:30:58.075179 memory_type:LPDDR4
2104 09:30:58.075766 GP_NUM : 10
2105 09:30:58.078346 SRAM_EN : 1
2106 09:30:58.078941 MD32_EN : 0
2107 09:30:58.081540 ===================================
2108 09:30:58.084910 [ANA_INIT] >>>>>>>>>>>>>>
2109 09:30:58.088785 <<<<<< [CONFIGURE PHASE]: ANA_TX
2110 09:30:58.091704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2111 09:30:58.094679 ===================================
2112 09:30:58.098325 data_rate = 2400,PCW = 0X5b00
2113 09:30:58.101620 ===================================
2114 09:30:58.105102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2115 09:30:58.111316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2116 09:30:58.114797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2117 09:30:58.121723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2118 09:30:58.125109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2119 09:30:58.128259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2120 09:30:58.128851 [ANA_INIT] flow start
2121 09:30:58.131464 [ANA_INIT] PLL >>>>>>>>
2122 09:30:58.135047 [ANA_INIT] PLL <<<<<<<<
2123 09:30:58.135646 [ANA_INIT] MIDPI >>>>>>>>
2124 09:30:58.138014 [ANA_INIT] MIDPI <<<<<<<<
2125 09:30:58.141762 [ANA_INIT] DLL >>>>>>>>
2126 09:30:58.142249 [ANA_INIT] DLL <<<<<<<<
2127 09:30:58.144759 [ANA_INIT] flow end
2128 09:30:58.148226 ============ LP4 DIFF to SE enter ============
2129 09:30:58.151501 ============ LP4 DIFF to SE exit ============
2130 09:30:58.154966 [ANA_INIT] <<<<<<<<<<<<<
2131 09:30:58.158322 [Flow] Enable top DCM control >>>>>
2132 09:30:58.161647 [Flow] Enable top DCM control <<<<<
2133 09:30:58.164674 Enable DLL master slave shuffle
2134 09:30:58.171850 ==============================================================
2135 09:30:58.172503 Gating Mode config
2136 09:30:58.178063 ==============================================================
2137 09:30:58.178641 Config description:
2138 09:30:58.188404 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2139 09:30:58.195054 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2140 09:30:58.201466 SELPH_MODE 0: By rank 1: By Phase
2141 09:30:58.205333 ==============================================================
2142 09:30:58.208316 GAT_TRACK_EN = 1
2143 09:30:58.211559 RX_GATING_MODE = 2
2144 09:30:58.215091 RX_GATING_TRACK_MODE = 2
2145 09:30:58.218595 SELPH_MODE = 1
2146 09:30:58.221834 PICG_EARLY_EN = 1
2147 09:30:58.225153 VALID_LAT_VALUE = 1
2148 09:30:58.228080 ==============================================================
2149 09:30:58.235015 Enter into Gating configuration >>>>
2150 09:30:58.235609 Exit from Gating configuration <<<<
2151 09:30:58.238027 Enter into DVFS_PRE_config >>>>>
2152 09:30:58.251617 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2153 09:30:58.254800 Exit from DVFS_PRE_config <<<<<
2154 09:30:58.257960 Enter into PICG configuration >>>>
2155 09:30:58.261535 Exit from PICG configuration <<<<
2156 09:30:58.262038 [RX_INPUT] configuration >>>>>
2157 09:30:58.265021 [RX_INPUT] configuration <<<<<
2158 09:30:58.271610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2159 09:30:58.275117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2160 09:30:58.281649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2161 09:30:58.288416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2162 09:30:58.294919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2163 09:30:58.301566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2164 09:30:58.304829 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2165 09:30:58.308560 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2166 09:30:58.311653 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2167 09:30:58.318198 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2168 09:30:58.321726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2169 09:30:58.324645 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2170 09:30:58.328075 ===================================
2171 09:30:58.331424 LPDDR4 DRAM CONFIGURATION
2172 09:30:58.335156 ===================================
2173 09:30:58.338414 EX_ROW_EN[0] = 0x0
2174 09:30:58.338986 EX_ROW_EN[1] = 0x0
2175 09:30:58.341557 LP4Y_EN = 0x0
2176 09:30:58.342051 WORK_FSP = 0x0
2177 09:30:58.345069 WL = 0x4
2178 09:30:58.345653 RL = 0x4
2179 09:30:58.348492 BL = 0x2
2180 09:30:58.349081 RPST = 0x0
2181 09:30:58.351629 RD_PRE = 0x0
2182 09:30:58.352239 WR_PRE = 0x1
2183 09:30:58.355277 WR_PST = 0x0
2184 09:30:58.355861 DBI_WR = 0x0
2185 09:30:58.358549 DBI_RD = 0x0
2186 09:30:58.359132 OTF = 0x1
2187 09:30:58.361580 ===================================
2188 09:30:58.364643 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2189 09:30:58.371580 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2190 09:30:58.374844 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2191 09:30:58.378314 ===================================
2192 09:30:58.381398 LPDDR4 DRAM CONFIGURATION
2193 09:30:58.384922 ===================================
2194 09:30:58.385412 EX_ROW_EN[0] = 0x10
2195 09:30:58.388014 EX_ROW_EN[1] = 0x0
2196 09:30:58.388545 LP4Y_EN = 0x0
2197 09:30:58.391805 WORK_FSP = 0x0
2198 09:30:58.395147 WL = 0x4
2199 09:30:58.395739 RL = 0x4
2200 09:30:58.398249 BL = 0x2
2201 09:30:58.398837 RPST = 0x0
2202 09:30:58.401969 RD_PRE = 0x0
2203 09:30:58.402556 WR_PRE = 0x1
2204 09:30:58.405428 WR_PST = 0x0
2205 09:30:58.406012 DBI_WR = 0x0
2206 09:30:58.408303 DBI_RD = 0x0
2207 09:30:58.408791 OTF = 0x1
2208 09:30:58.411574 ===================================
2209 09:30:58.418784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2210 09:30:58.419375 ==
2211 09:30:58.421597 Dram Type= 6, Freq= 0, CH_0, rank 0
2212 09:30:58.425120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2213 09:30:58.425711 ==
2214 09:30:58.428375 [Duty_Offset_Calibration]
2215 09:30:58.428860 B0:0 B1:2 CA:1
2216 09:30:58.431645
2217 09:30:58.435017 [DutyScan_Calibration_Flow] k_type=0
2218 09:30:58.442930
2219 09:30:58.443521 ==CLK 0==
2220 09:30:58.446378 Final CLK duty delay cell = 0
2221 09:30:58.449519 [0] MAX Duty = 5093%(X100), DQS PI = 12
2222 09:30:58.452830 [0] MIN Duty = 4938%(X100), DQS PI = 52
2223 09:30:58.456650 [0] AVG Duty = 5015%(X100)
2224 09:30:58.457237
2225 09:30:58.459698 CH0 CLK Duty spec in!! Max-Min= 155%
2226 09:30:58.462527 [DutyScan_Calibration_Flow] ====Done====
2227 09:30:58.463010
2228 09:30:58.465873 [DutyScan_Calibration_Flow] k_type=1
2229 09:30:58.482320
2230 09:30:58.482906 ==DQS 0 ==
2231 09:30:58.485561 Final DQS duty delay cell = 0
2232 09:30:58.488701 [0] MAX Duty = 5125%(X100), DQS PI = 30
2233 09:30:58.491969 [0] MIN Duty = 5031%(X100), DQS PI = 4
2234 09:30:58.492674 [0] AVG Duty = 5078%(X100)
2235 09:30:58.495510
2236 09:30:58.495969 ==DQS 1 ==
2237 09:30:58.498897 Final DQS duty delay cell = 0
2238 09:30:58.502229 [0] MAX Duty = 5031%(X100), DQS PI = 50
2239 09:30:58.505839 [0] MIN Duty = 4906%(X100), DQS PI = 16
2240 09:30:58.506414 [0] AVG Duty = 4968%(X100)
2241 09:30:58.509100
2242 09:30:58.512249 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2243 09:30:58.512722
2244 09:30:58.515452 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2245 09:30:58.519306 [DutyScan_Calibration_Flow] ====Done====
2246 09:30:58.519878
2247 09:30:58.521940 [DutyScan_Calibration_Flow] k_type=3
2248 09:30:58.539280
2249 09:30:58.539875 ==DQM 0 ==
2250 09:30:58.543155 Final DQM duty delay cell = 0
2251 09:30:58.546144 [0] MAX Duty = 5156%(X100), DQS PI = 22
2252 09:30:58.549423 [0] MIN Duty = 4969%(X100), DQS PI = 54
2253 09:30:58.549994 [0] AVG Duty = 5062%(X100)
2254 09:30:58.552663
2255 09:30:58.553233 ==DQM 1 ==
2256 09:30:58.556040 Final DQM duty delay cell = 4
2257 09:30:58.559459 [4] MAX Duty = 5187%(X100), DQS PI = 54
2258 09:30:58.562712 [4] MIN Duty = 5000%(X100), DQS PI = 18
2259 09:30:58.565831 [4] AVG Duty = 5093%(X100)
2260 09:30:58.566356
2261 09:30:58.568997 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2262 09:30:58.569470
2263 09:30:58.572330 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2264 09:30:58.576017 [DutyScan_Calibration_Flow] ====Done====
2265 09:30:58.576628
2266 09:30:58.579138 [DutyScan_Calibration_Flow] k_type=2
2267 09:30:58.594231
2268 09:30:58.594797 ==DQ 0 ==
2269 09:30:58.597623 Final DQ duty delay cell = -4
2270 09:30:58.601069 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2271 09:30:58.604299 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2272 09:30:58.607588 [-4] AVG Duty = 4937%(X100)
2273 09:30:58.608163
2274 09:30:58.608745 ==DQ 1 ==
2275 09:30:58.610890 Final DQ duty delay cell = -4
2276 09:30:58.614349 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2277 09:30:58.617772 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2278 09:30:58.620840 [-4] AVG Duty = 4969%(X100)
2279 09:30:58.621410
2280 09:30:58.624600 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2281 09:30:58.625073
2282 09:30:58.627416 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2283 09:30:58.631292 [DutyScan_Calibration_Flow] ====Done====
2284 09:30:58.631865 ==
2285 09:30:58.634403 Dram Type= 6, Freq= 0, CH_1, rank 0
2286 09:30:58.637618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2287 09:30:58.638193 ==
2288 09:30:58.640907 [Duty_Offset_Calibration]
2289 09:30:58.641480 B0:0 B1:4 CA:-5
2290 09:30:58.641863
2291 09:30:58.644274 [DutyScan_Calibration_Flow] k_type=0
2292 09:30:58.654962
2293 09:30:58.655530 ==CLK 0==
2294 09:30:58.658274 Final CLK duty delay cell = 0
2295 09:30:58.661603 [0] MAX Duty = 5094%(X100), DQS PI = 24
2296 09:30:58.665060 [0] MIN Duty = 4875%(X100), DQS PI = 46
2297 09:30:58.667832 [0] AVG Duty = 4984%(X100)
2298 09:30:58.668356
2299 09:30:58.671061 CH1 CLK Duty spec in!! Max-Min= 219%
2300 09:30:58.674723 [DutyScan_Calibration_Flow] ====Done====
2301 09:30:58.675298
2302 09:30:58.677972 [DutyScan_Calibration_Flow] k_type=1
2303 09:30:58.693201
2304 09:30:58.693768 ==DQS 0 ==
2305 09:30:58.696940 Final DQS duty delay cell = 0
2306 09:30:58.700096 [0] MAX Duty = 5125%(X100), DQS PI = 16
2307 09:30:58.703240 [0] MIN Duty = 4875%(X100), DQS PI = 40
2308 09:30:58.706726 [0] AVG Duty = 5000%(X100)
2309 09:30:58.707303
2310 09:30:58.707683 ==DQS 1 ==
2311 09:30:58.710133 Final DQS duty delay cell = -4
2312 09:30:58.713087 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2313 09:30:58.716716 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2314 09:30:58.719867 [-4] AVG Duty = 4953%(X100)
2315 09:30:58.720478
2316 09:30:58.723331 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2317 09:30:58.723804
2318 09:30:58.726601 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2319 09:30:58.730448 [DutyScan_Calibration_Flow] ====Done====
2320 09:30:58.731022
2321 09:30:58.732949 [DutyScan_Calibration_Flow] k_type=3
2322 09:30:58.748477
2323 09:30:58.749053 ==DQM 0 ==
2324 09:30:58.752001 Final DQM duty delay cell = -4
2325 09:30:58.755199 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2326 09:30:58.758642 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2327 09:30:58.761673 [-4] AVG Duty = 4969%(X100)
2328 09:30:58.762141
2329 09:30:58.762512 ==DQM 1 ==
2330 09:30:58.764866 Final DQM duty delay cell = -4
2331 09:30:58.768087 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2332 09:30:58.771647 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2333 09:30:58.775221 [-4] AVG Duty = 4984%(X100)
2334 09:30:58.775787
2335 09:30:58.778152 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2336 09:30:58.778622
2337 09:30:58.781808 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2338 09:30:58.784910 [DutyScan_Calibration_Flow] ====Done====
2339 09:30:58.785381
2340 09:30:58.788300 [DutyScan_Calibration_Flow] k_type=2
2341 09:30:58.805518
2342 09:30:58.806087 ==DQ 0 ==
2343 09:30:58.808646 Final DQ duty delay cell = 0
2344 09:30:58.812086 [0] MAX Duty = 5062%(X100), DQS PI = 0
2345 09:30:58.815573 [0] MIN Duty = 4969%(X100), DQS PI = 42
2346 09:30:58.816149 [0] AVG Duty = 5015%(X100)
2347 09:30:58.818709
2348 09:30:58.819309 ==DQ 1 ==
2349 09:30:58.822102 Final DQ duty delay cell = 0
2350 09:30:58.825613 [0] MAX Duty = 5031%(X100), DQS PI = 8
2351 09:30:58.828911 [0] MIN Duty = 4875%(X100), DQS PI = 18
2352 09:30:58.829487 [0] AVG Duty = 4953%(X100)
2353 09:30:58.829865
2354 09:30:58.832346 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2355 09:30:58.832917
2356 09:30:58.835844 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2357 09:30:58.842063 [DutyScan_Calibration_Flow] ====Done====
2358 09:30:58.845796 nWR fixed to 30
2359 09:30:58.846387 [ModeRegInit_LP4] CH0 RK0
2360 09:30:58.848564 [ModeRegInit_LP4] CH0 RK1
2361 09:30:58.851799 [ModeRegInit_LP4] CH1 RK0
2362 09:30:58.852304 [ModeRegInit_LP4] CH1 RK1
2363 09:30:58.855312 match AC timing 6
2364 09:30:58.858611 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2365 09:30:58.862177 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2366 09:30:58.868828 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2367 09:30:58.872287 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2368 09:30:58.878716 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2369 09:30:58.879281 ==
2370 09:30:58.881842 Dram Type= 6, Freq= 0, CH_0, rank 0
2371 09:30:58.885209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2372 09:30:58.885684 ==
2373 09:30:58.892356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2374 09:30:58.895158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2375 09:30:58.905207 [CA 0] Center 39 (9~70) winsize 62
2376 09:30:58.908254 [CA 1] Center 39 (8~70) winsize 63
2377 09:30:58.911668 [CA 2] Center 36 (5~67) winsize 63
2378 09:30:58.915053 [CA 3] Center 35 (4~66) winsize 63
2379 09:30:58.918545 [CA 4] Center 34 (3~65) winsize 63
2380 09:30:58.921853 [CA 5] Center 33 (3~64) winsize 62
2381 09:30:58.922321
2382 09:30:58.924914 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2383 09:30:58.925384
2384 09:30:58.928680 [CATrainingPosCal] consider 1 rank data
2385 09:30:58.931570 u2DelayCellTimex100 = 270/100 ps
2386 09:30:58.935230 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2387 09:30:58.938878 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2388 09:30:58.945331 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2389 09:30:58.948758 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2390 09:30:58.951999 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2391 09:30:58.955261 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2392 09:30:58.955831
2393 09:30:58.958672 CA PerBit enable=1, Macro0, CA PI delay=33
2394 09:30:58.959236
2395 09:30:58.961616 [CBTSetCACLKResult] CA Dly = 33
2396 09:30:58.962133 CS Dly: 7 (0~38)
2397 09:30:58.962501 ==
2398 09:30:58.965161 Dram Type= 6, Freq= 0, CH_0, rank 1
2399 09:30:58.971788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2400 09:30:58.972294 ==
2401 09:30:58.975448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2402 09:30:58.982001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2403 09:30:58.991220 [CA 0] Center 39 (8~70) winsize 63
2404 09:30:58.994088 [CA 1] Center 39 (8~70) winsize 63
2405 09:30:58.997074 [CA 2] Center 35 (5~66) winsize 62
2406 09:30:59.000566 [CA 3] Center 35 (4~66) winsize 63
2407 09:30:59.003900 [CA 4] Center 33 (3~64) winsize 62
2408 09:30:59.007105 [CA 5] Center 33 (3~64) winsize 62
2409 09:30:59.007666
2410 09:30:59.010361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2411 09:30:59.010832
2412 09:30:59.014069 [CATrainingPosCal] consider 2 rank data
2413 09:30:59.016990 u2DelayCellTimex100 = 270/100 ps
2414 09:30:59.020321 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2415 09:30:59.023800 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2416 09:30:59.030558 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2417 09:30:59.033877 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2418 09:30:59.037468 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2419 09:30:59.040640 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2420 09:30:59.041209
2421 09:30:59.043840 CA PerBit enable=1, Macro0, CA PI delay=33
2422 09:30:59.044341
2423 09:30:59.047145 [CBTSetCACLKResult] CA Dly = 33
2424 09:30:59.047712 CS Dly: 7 (0~39)
2425 09:30:59.048130
2426 09:30:59.050455 ----->DramcWriteLeveling(PI) begin...
2427 09:30:59.054051 ==
2428 09:30:59.056850 Dram Type= 6, Freq= 0, CH_0, rank 0
2429 09:30:59.060551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2430 09:30:59.061124 ==
2431 09:30:59.063969 Write leveling (Byte 0): 27 => 27
2432 09:30:59.066827 Write leveling (Byte 1): 27 => 27
2433 09:30:59.070458 DramcWriteLeveling(PI) end<-----
2434 09:30:59.070925
2435 09:30:59.071289 ==
2436 09:30:59.073845 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 09:30:59.076964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2438 09:30:59.077532 ==
2439 09:30:59.080551 [Gating] SW mode calibration
2440 09:30:59.087201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2441 09:30:59.090861 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2442 09:30:59.097175 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 09:30:59.100332 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2444 09:30:59.103790 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2445 09:30:59.110339 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 09:30:59.113597 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 09:30:59.117093 0 11 20 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (1 0)
2448 09:30:59.123460 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2449 09:30:59.126781 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 09:30:59.130483 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 09:30:59.136927 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 09:30:59.140634 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 09:30:59.143561 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 09:30:59.150763 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 09:30:59.153514 0 12 20 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
2456 09:30:59.156669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 09:30:59.163601 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 09:30:59.166981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 09:30:59.169932 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 09:30:59.176752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 09:30:59.180230 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 09:30:59.183345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2463 09:30:59.190142 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2464 09:30:59.193341 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 09:30:59.196640 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 09:30:59.203103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 09:30:59.206478 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 09:30:59.209894 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 09:30:59.216664 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 09:30:59.219921 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 09:30:59.223189 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 09:30:59.226754 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 09:30:59.233207 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 09:30:59.236524 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 09:30:59.239725 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 09:30:59.246445 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 09:30:59.249815 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 09:30:59.252967 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2479 09:30:59.259872 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2480 09:30:59.263095 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2481 09:30:59.266490 Total UI for P1: 0, mck2ui 16
2482 09:30:59.269810 best dqsien dly found for B0: ( 0, 15, 18)
2483 09:30:59.273328 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2484 09:30:59.276724 Total UI for P1: 0, mck2ui 16
2485 09:30:59.280155 best dqsien dly found for B1: ( 0, 15, 20)
2486 09:30:59.283190 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2487 09:30:59.286739 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2488 09:30:59.287171
2489 09:30:59.290086 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2490 09:30:59.296610 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2491 09:30:59.297080 [Gating] SW calibration Done
2492 09:30:59.297463 ==
2493 09:30:59.299945 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 09:30:59.307088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2495 09:30:59.307564 ==
2496 09:30:59.307942 RX Vref Scan: 0
2497 09:30:59.308472
2498 09:30:59.309919 RX Vref 0 -> 0, step: 1
2499 09:30:59.310341
2500 09:30:59.313158 RX Delay -40 -> 252, step: 8
2501 09:30:59.316501 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2502 09:30:59.320257 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2503 09:30:59.323157 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2504 09:30:59.329914 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2505 09:30:59.333308 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2506 09:30:59.336737 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2507 09:30:59.340054 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2508 09:30:59.343426 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2509 09:30:59.346975 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2510 09:30:59.353700 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2511 09:30:59.356915 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2512 09:30:59.360377 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2513 09:30:59.363571 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2514 09:30:59.366869 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2515 09:30:59.373733 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2516 09:30:59.376807 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2517 09:30:59.377236 ==
2518 09:30:59.380398 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 09:30:59.383693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2520 09:30:59.384295 ==
2521 09:30:59.386643 DQS Delay:
2522 09:30:59.387079 DQS0 = 0, DQS1 = 0
2523 09:30:59.387413 DQM Delay:
2524 09:30:59.390377 DQM0 = 115, DQM1 = 106
2525 09:30:59.390905 DQ Delay:
2526 09:30:59.393636 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2527 09:30:59.397097 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2528 09:30:59.403954 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2529 09:30:59.407116 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2530 09:30:59.407647
2531 09:30:59.407984
2532 09:30:59.408353 ==
2533 09:30:59.410588 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 09:30:59.413335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2535 09:30:59.413887 ==
2536 09:30:59.414235
2537 09:30:59.414553
2538 09:30:59.416862 TX Vref Scan disable
2539 09:30:59.417303 == TX Byte 0 ==
2540 09:30:59.423437 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2541 09:30:59.426897 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2542 09:30:59.427428 == TX Byte 1 ==
2543 09:30:59.433883 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2544 09:30:59.436603 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2545 09:30:59.437026 ==
2546 09:30:59.440117 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 09:30:59.443337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2548 09:30:59.443765 ==
2549 09:30:59.456135 TX Vref=22, minBit 8, minWin=25, winSum=422
2550 09:30:59.459688 TX Vref=24, minBit 1, minWin=26, winSum=427
2551 09:30:59.463091 TX Vref=26, minBit 8, minWin=26, winSum=432
2552 09:30:59.466074 TX Vref=28, minBit 9, minWin=26, winSum=437
2553 09:30:59.469416 TX Vref=30, minBit 10, minWin=26, winSum=437
2554 09:30:59.476006 TX Vref=32, minBit 10, minWin=26, winSum=433
2555 09:30:59.479367 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
2556 09:30:59.479941
2557 09:30:59.482660 Final TX Range 1 Vref 28
2558 09:30:59.483127
2559 09:30:59.483562 ==
2560 09:30:59.486069 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 09:30:59.489156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2562 09:30:59.492425 ==
2563 09:30:59.492935
2564 09:30:59.493307
2565 09:30:59.493651 TX Vref Scan disable
2566 09:30:59.496115 == TX Byte 0 ==
2567 09:30:59.499756 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2568 09:30:59.506051 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2569 09:30:59.506628 == TX Byte 1 ==
2570 09:30:59.508949 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2571 09:30:59.515727 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2572 09:30:59.516341
2573 09:30:59.516722 [DATLAT]
2574 09:30:59.517108 Freq=1200, CH0 RK0
2575 09:30:59.517675
2576 09:30:59.519238 DATLAT Default: 0xd
2577 09:30:59.519705 0, 0xFFFF, sum = 0
2578 09:30:59.522586 1, 0xFFFF, sum = 0
2579 09:30:59.525739 2, 0xFFFF, sum = 0
2580 09:30:59.526213 3, 0xFFFF, sum = 0
2581 09:30:59.529088 4, 0xFFFF, sum = 0
2582 09:30:59.529671 5, 0xFFFF, sum = 0
2583 09:30:59.532857 6, 0xFFFF, sum = 0
2584 09:30:59.533440 7, 0xFFFF, sum = 0
2585 09:30:59.535616 8, 0xFFFF, sum = 0
2586 09:30:59.536088 9, 0xFFFF, sum = 0
2587 09:30:59.539612 10, 0xFFFF, sum = 0
2588 09:30:59.540235 11, 0x0, sum = 1
2589 09:30:59.542638 12, 0x0, sum = 2
2590 09:30:59.543223 13, 0x0, sum = 3
2591 09:30:59.545805 14, 0x0, sum = 4
2592 09:30:59.546282 best_step = 12
2593 09:30:59.546655
2594 09:30:59.546999 ==
2595 09:30:59.549476 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 09:30:59.552611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2597 09:30:59.553184 ==
2598 09:30:59.556067 RX Vref Scan: 1
2599 09:30:59.556674
2600 09:30:59.559252 Set Vref Range= 32 -> 127
2601 09:30:59.559818
2602 09:30:59.560245 RX Vref 32 -> 127, step: 1
2603 09:30:59.560615
2604 09:30:59.562284 RX Delay -21 -> 252, step: 4
2605 09:30:59.562747
2606 09:30:59.565742 Set Vref, RX VrefLevel [Byte0]: 32
2607 09:30:59.569023 [Byte1]: 32
2608 09:30:59.572605
2609 09:30:59.573113 Set Vref, RX VrefLevel [Byte0]: 33
2610 09:30:59.576021 [Byte1]: 33
2611 09:30:59.580636
2612 09:30:59.581250 Set Vref, RX VrefLevel [Byte0]: 34
2613 09:30:59.583974 [Byte1]: 34
2614 09:30:59.588463
2615 09:30:59.589024 Set Vref, RX VrefLevel [Byte0]: 35
2616 09:30:59.592095 [Byte1]: 35
2617 09:30:59.596764
2618 09:30:59.597352 Set Vref, RX VrefLevel [Byte0]: 36
2619 09:30:59.599962 [Byte1]: 36
2620 09:30:59.604607
2621 09:30:59.605170 Set Vref, RX VrefLevel [Byte0]: 37
2622 09:30:59.607732 [Byte1]: 37
2623 09:30:59.612450
2624 09:30:59.613083 Set Vref, RX VrefLevel [Byte0]: 38
2625 09:30:59.615376 [Byte1]: 38
2626 09:30:59.620440
2627 09:30:59.621005 Set Vref, RX VrefLevel [Byte0]: 39
2628 09:30:59.623717 [Byte1]: 39
2629 09:30:59.628546
2630 09:30:59.629114 Set Vref, RX VrefLevel [Byte0]: 40
2631 09:30:59.631493 [Byte1]: 40
2632 09:30:59.636326
2633 09:30:59.636887 Set Vref, RX VrefLevel [Byte0]: 41
2634 09:30:59.639501 [Byte1]: 41
2635 09:30:59.644241
2636 09:30:59.644806 Set Vref, RX VrefLevel [Byte0]: 42
2637 09:30:59.647387 [Byte1]: 42
2638 09:30:59.652239
2639 09:30:59.653011 Set Vref, RX VrefLevel [Byte0]: 43
2640 09:30:59.654902 [Byte1]: 43
2641 09:30:59.659560
2642 09:30:59.660028 Set Vref, RX VrefLevel [Byte0]: 44
2643 09:30:59.662944 [Byte1]: 44
2644 09:30:59.668101
2645 09:30:59.668729 Set Vref, RX VrefLevel [Byte0]: 45
2646 09:30:59.670928 [Byte1]: 45
2647 09:30:59.676023
2648 09:30:59.676652 Set Vref, RX VrefLevel [Byte0]: 46
2649 09:30:59.679031 [Byte1]: 46
2650 09:30:59.683885
2651 09:30:59.684579 Set Vref, RX VrefLevel [Byte0]: 47
2652 09:30:59.686896 [Byte1]: 47
2653 09:30:59.692045
2654 09:30:59.692691 Set Vref, RX VrefLevel [Byte0]: 48
2655 09:30:59.694917 [Byte1]: 48
2656 09:30:59.699607
2657 09:30:59.700222 Set Vref, RX VrefLevel [Byte0]: 49
2658 09:30:59.702905 [Byte1]: 49
2659 09:30:59.707482
2660 09:30:59.707950 Set Vref, RX VrefLevel [Byte0]: 50
2661 09:30:59.710699 [Byte1]: 50
2662 09:30:59.715270
2663 09:30:59.715732 Set Vref, RX VrefLevel [Byte0]: 51
2664 09:30:59.718923 [Byte1]: 51
2665 09:30:59.723252
2666 09:30:59.723712 Set Vref, RX VrefLevel [Byte0]: 52
2667 09:30:59.726262 [Byte1]: 52
2668 09:30:59.731207
2669 09:30:59.731789 Set Vref, RX VrefLevel [Byte0]: 53
2670 09:30:59.734576 [Byte1]: 53
2671 09:30:59.739672
2672 09:30:59.740275 Set Vref, RX VrefLevel [Byte0]: 54
2673 09:30:59.742649 [Byte1]: 54
2674 09:30:59.747296
2675 09:30:59.747862 Set Vref, RX VrefLevel [Byte0]: 55
2676 09:30:59.750462 [Byte1]: 55
2677 09:30:59.755307
2678 09:30:59.755875 Set Vref, RX VrefLevel [Byte0]: 56
2679 09:30:59.758740 [Byte1]: 56
2680 09:30:59.762900
2681 09:30:59.763466 Set Vref, RX VrefLevel [Byte0]: 57
2682 09:30:59.766297 [Byte1]: 57
2683 09:30:59.770875
2684 09:30:59.771342 Set Vref, RX VrefLevel [Byte0]: 58
2685 09:30:59.773937 [Byte1]: 58
2686 09:30:59.778956
2687 09:30:59.779524 Set Vref, RX VrefLevel [Byte0]: 59
2688 09:30:59.782089 [Byte1]: 59
2689 09:30:59.786635
2690 09:30:59.787100 Set Vref, RX VrefLevel [Byte0]: 60
2691 09:30:59.789646 [Byte1]: 60
2692 09:30:59.794496
2693 09:30:59.794995 Set Vref, RX VrefLevel [Byte0]: 61
2694 09:30:59.798139 [Byte1]: 61
2695 09:30:59.802394
2696 09:30:59.802912 Set Vref, RX VrefLevel [Byte0]: 62
2697 09:30:59.805842 [Byte1]: 62
2698 09:30:59.810431
2699 09:30:59.811002 Set Vref, RX VrefLevel [Byte0]: 63
2700 09:30:59.814140 [Byte1]: 63
2701 09:30:59.818211
2702 09:30:59.818680 Set Vref, RX VrefLevel [Byte0]: 64
2703 09:30:59.822021 [Byte1]: 64
2704 09:30:59.826248
2705 09:30:59.826834 Set Vref, RX VrefLevel [Byte0]: 65
2706 09:30:59.829596 [Byte1]: 65
2707 09:30:59.834122
2708 09:30:59.834689 Set Vref, RX VrefLevel [Byte0]: 66
2709 09:30:59.837431 [Byte1]: 66
2710 09:30:59.841958
2711 09:30:59.842525 Final RX Vref Byte 0 = 51 to rank0
2712 09:30:59.845604 Final RX Vref Byte 1 = 48 to rank0
2713 09:30:59.848870 Final RX Vref Byte 0 = 51 to rank1
2714 09:30:59.851990 Final RX Vref Byte 1 = 48 to rank1==
2715 09:30:59.855723 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 09:30:59.858996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2717 09:30:59.862480 ==
2718 09:30:59.863049 DQS Delay:
2719 09:30:59.863420 DQS0 = 0, DQS1 = 0
2720 09:30:59.866126 DQM Delay:
2721 09:30:59.866694 DQM0 = 114, DQM1 = 105
2722 09:30:59.869136 DQ Delay:
2723 09:30:59.872919 DQ0 =112, DQ1 =114, DQ2 =114, DQ3 =110
2724 09:30:59.875774 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2725 09:30:59.879364 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2726 09:30:59.882988 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2727 09:30:59.883566
2728 09:30:59.883939
2729 09:30:59.889072 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2730 09:30:59.892588 CH0 RK0: MR19=404, MR18=C0C
2731 09:30:59.899150 CH0_RK0: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2732 09:30:59.899736
2733 09:30:59.902174 ----->DramcWriteLeveling(PI) begin...
2734 09:30:59.902650 ==
2735 09:30:59.905932 Dram Type= 6, Freq= 0, CH_0, rank 1
2736 09:30:59.909438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2737 09:30:59.910058 ==
2738 09:30:59.912353 Write leveling (Byte 0): 28 => 28
2739 09:30:59.916049 Write leveling (Byte 1): 26 => 26
2740 09:30:59.919225 DramcWriteLeveling(PI) end<-----
2741 09:30:59.919813
2742 09:30:59.920224 ==
2743 09:30:59.922311 Dram Type= 6, Freq= 0, CH_0, rank 1
2744 09:30:59.925555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2745 09:30:59.926048 ==
2746 09:30:59.928918 [Gating] SW mode calibration
2747 09:30:59.935402 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2748 09:30:59.942345 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2749 09:30:59.945567 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2750 09:30:59.952158 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 09:30:59.956011 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 09:30:59.959283 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 09:30:59.966218 0 11 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2754 09:30:59.968934 0 11 20 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (1 0)
2755 09:30:59.972297 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 09:30:59.975735 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 09:30:59.982461 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 09:30:59.985941 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 09:30:59.989215 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 09:30:59.995873 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 09:30:59.999335 0 12 16 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
2762 09:31:00.002721 0 12 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2763 09:31:00.009227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 09:31:00.012600 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 09:31:00.015649 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 09:31:00.022558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 09:31:00.025986 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 09:31:00.029081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 09:31:00.036051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2770 09:31:00.039287 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2771 09:31:00.042753 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 09:31:00.049197 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 09:31:00.052766 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 09:31:00.056275 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 09:31:00.059490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 09:31:00.065729 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 09:31:00.069389 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 09:31:00.072620 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 09:31:00.079421 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 09:31:00.082579 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 09:31:00.086248 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 09:31:00.092536 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 09:31:00.095850 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 09:31:00.099577 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 09:31:00.105954 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2786 09:31:00.109012 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2787 09:31:00.112758 Total UI for P1: 0, mck2ui 16
2788 09:31:00.116135 best dqsien dly found for B0: ( 0, 15, 16)
2789 09:31:00.118955 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2790 09:31:00.122731 Total UI for P1: 0, mck2ui 16
2791 09:31:00.125877 best dqsien dly found for B1: ( 0, 15, 18)
2792 09:31:00.129597 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2793 09:31:00.132750 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2794 09:31:00.133326
2795 09:31:00.139479 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2796 09:31:00.142523 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2797 09:31:00.143095 [Gating] SW calibration Done
2798 09:31:00.145506 ==
2799 09:31:00.149091 Dram Type= 6, Freq= 0, CH_0, rank 1
2800 09:31:00.152804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2801 09:31:00.153380 ==
2802 09:31:00.153755 RX Vref Scan: 0
2803 09:31:00.154100
2804 09:31:00.155686 RX Vref 0 -> 0, step: 1
2805 09:31:00.156151
2806 09:31:00.159681 RX Delay -40 -> 252, step: 8
2807 09:31:00.162825 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2808 09:31:00.166431 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2809 09:31:00.169361 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2810 09:31:00.175672 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2811 09:31:00.178905 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2812 09:31:00.182586 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2813 09:31:00.185814 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2814 09:31:00.189136 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2815 09:31:00.195869 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2816 09:31:00.199324 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2817 09:31:00.202627 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2818 09:31:00.205956 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2819 09:31:00.208862 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2820 09:31:00.216448 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2821 09:31:00.219291 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2822 09:31:00.222339 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2823 09:31:00.222806 ==
2824 09:31:00.225917 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 09:31:00.228865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2826 09:31:00.229339 ==
2827 09:31:00.232662 DQS Delay:
2828 09:31:00.233230 DQS0 = 0, DQS1 = 0
2829 09:31:00.235408 DQM Delay:
2830 09:31:00.235873 DQM0 = 115, DQM1 = 107
2831 09:31:00.236295 DQ Delay:
2832 09:31:00.242424 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2833 09:31:00.245724 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2834 09:31:00.249094 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2835 09:31:00.252652 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2836 09:31:00.253224
2837 09:31:00.253595
2838 09:31:00.253937 ==
2839 09:31:00.255826 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 09:31:00.259074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2841 09:31:00.259648 ==
2842 09:31:00.260020
2843 09:31:00.260431
2844 09:31:00.262626 TX Vref Scan disable
2845 09:31:00.263092 == TX Byte 0 ==
2846 09:31:00.269372 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2847 09:31:00.272696 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2848 09:31:00.273166 == TX Byte 1 ==
2849 09:31:00.279477 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2850 09:31:00.282457 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2851 09:31:00.283033 ==
2852 09:31:00.286444 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 09:31:00.288922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2854 09:31:00.289393 ==
2855 09:31:00.302164 TX Vref=22, minBit 10, minWin=24, winSum=415
2856 09:31:00.305179 TX Vref=24, minBit 11, minWin=25, winSum=423
2857 09:31:00.308664 TX Vref=26, minBit 1, minWin=26, winSum=429
2858 09:31:00.312281 TX Vref=28, minBit 9, minWin=26, winSum=432
2859 09:31:00.315201 TX Vref=30, minBit 9, minWin=26, winSum=434
2860 09:31:00.322367 TX Vref=32, minBit 1, minWin=27, winSum=439
2861 09:31:00.325825 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 32
2862 09:31:00.326405
2863 09:31:00.328585 Final TX Range 1 Vref 32
2864 09:31:00.329053
2865 09:31:00.329421 ==
2866 09:31:00.332007 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 09:31:00.335334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2868 09:31:00.335913 ==
2869 09:31:00.338957
2870 09:31:00.339550
2871 09:31:00.339924 TX Vref Scan disable
2872 09:31:00.342182 == TX Byte 0 ==
2873 09:31:00.345296 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2874 09:31:00.349052 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2875 09:31:00.352337 == TX Byte 1 ==
2876 09:31:00.355570 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2877 09:31:00.358826 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2878 09:31:00.361893
2879 09:31:00.362460 [DATLAT]
2880 09:31:00.362834 Freq=1200, CH0 RK1
2881 09:31:00.363183
2882 09:31:00.365114 DATLAT Default: 0xc
2883 09:31:00.365579 0, 0xFFFF, sum = 0
2884 09:31:00.368832 1, 0xFFFF, sum = 0
2885 09:31:00.369411 2, 0xFFFF, sum = 0
2886 09:31:00.371962 3, 0xFFFF, sum = 0
2887 09:31:00.375535 4, 0xFFFF, sum = 0
2888 09:31:00.376130 5, 0xFFFF, sum = 0
2889 09:31:00.378287 6, 0xFFFF, sum = 0
2890 09:31:00.378761 7, 0xFFFF, sum = 0
2891 09:31:00.382099 8, 0xFFFF, sum = 0
2892 09:31:00.382689 9, 0xFFFF, sum = 0
2893 09:31:00.384894 10, 0xFFFF, sum = 0
2894 09:31:00.385368 11, 0x0, sum = 1
2895 09:31:00.388503 12, 0x0, sum = 2
2896 09:31:00.388974 13, 0x0, sum = 3
2897 09:31:00.389350 14, 0x0, sum = 4
2898 09:31:00.391723 best_step = 12
2899 09:31:00.392244
2900 09:31:00.392633 ==
2901 09:31:00.394903 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 09:31:00.398500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2903 09:31:00.399093 ==
2904 09:31:00.401983 RX Vref Scan: 0
2905 09:31:00.402553
2906 09:31:00.405443 RX Vref 0 -> 0, step: 1
2907 09:31:00.406013
2908 09:31:00.406387 RX Delay -21 -> 252, step: 4
2909 09:31:00.412344 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2910 09:31:00.415978 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2911 09:31:00.418984 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2912 09:31:00.422464 iDelay=199, Bit 3, Center 106 (35 ~ 178) 144
2913 09:31:00.425586 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2914 09:31:00.432322 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2915 09:31:00.435767 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2916 09:31:00.438875 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2917 09:31:00.442616 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2918 09:31:00.445665 iDelay=199, Bit 9, Center 88 (23 ~ 154) 132
2919 09:31:00.452578 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2920 09:31:00.455953 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2921 09:31:00.459342 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2922 09:31:00.462488 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2923 09:31:00.465766 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2924 09:31:00.472397 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2925 09:31:00.472975 ==
2926 09:31:00.475725 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 09:31:00.478947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2928 09:31:00.479414 ==
2929 09:31:00.479783 DQS Delay:
2930 09:31:00.482501 DQS0 = 0, DQS1 = 0
2931 09:31:00.483074 DQM Delay:
2932 09:31:00.485564 DQM0 = 114, DQM1 = 105
2933 09:31:00.486030 DQ Delay:
2934 09:31:00.489156 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =106
2935 09:31:00.492128 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2936 09:31:00.495515 DQ8 =94, DQ9 =88, DQ10 =110, DQ11 =96
2937 09:31:00.499420 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2938 09:31:00.499995
2939 09:31:00.500428
2940 09:31:00.508943 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2941 09:31:00.512366 CH0 RK1: MR19=404, MR18=E0E
2942 09:31:00.515617 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2943 09:31:00.519297 [RxdqsGatingPostProcess] freq 1200
2944 09:31:00.525731 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2945 09:31:00.528660 Pre-setting of DQS Precalculation
2946 09:31:00.532335 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2947 09:31:00.532898 ==
2948 09:31:00.535305 Dram Type= 6, Freq= 0, CH_1, rank 0
2949 09:31:00.542157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2950 09:31:00.542635 ==
2951 09:31:00.545253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2952 09:31:00.552035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2953 09:31:00.561082 [CA 0] Center 37 (7~68) winsize 62
2954 09:31:00.563949 [CA 1] Center 37 (7~68) winsize 62
2955 09:31:00.567715 [CA 2] Center 34 (4~65) winsize 62
2956 09:31:00.570598 [CA 3] Center 33 (3~64) winsize 62
2957 09:31:00.573890 [CA 4] Center 32 (2~63) winsize 62
2958 09:31:00.577573 [CA 5] Center 32 (1~63) winsize 63
2959 09:31:00.578134
2960 09:31:00.580901 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2961 09:31:00.581471
2962 09:31:00.584359 [CATrainingPosCal] consider 1 rank data
2963 09:31:00.587755 u2DelayCellTimex100 = 270/100 ps
2964 09:31:00.590651 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2965 09:31:00.593770 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2966 09:31:00.600893 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2967 09:31:00.604091 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2968 09:31:00.607373 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2969 09:31:00.611254 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2970 09:31:00.611887
2971 09:31:00.613728 CA PerBit enable=1, Macro0, CA PI delay=32
2972 09:31:00.614197
2973 09:31:00.617347 [CBTSetCACLKResult] CA Dly = 32
2974 09:31:00.617984 CS Dly: 6 (0~37)
2975 09:31:00.618364 ==
2976 09:31:00.620390 Dram Type= 6, Freq= 0, CH_1, rank 1
2977 09:31:00.627697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2978 09:31:00.628362 ==
2979 09:31:00.630652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2980 09:31:00.637555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2981 09:31:00.645981 [CA 0] Center 37 (7~68) winsize 62
2982 09:31:00.649223 [CA 1] Center 37 (6~68) winsize 63
2983 09:31:00.652854 [CA 2] Center 33 (3~64) winsize 62
2984 09:31:00.656231 [CA 3] Center 33 (3~64) winsize 62
2985 09:31:00.659480 [CA 4] Center 32 (2~63) winsize 62
2986 09:31:00.662599 [CA 5] Center 31 (1~62) winsize 62
2987 09:31:00.663279
2988 09:31:00.665921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2989 09:31:00.666391
2990 09:31:00.668929 [CATrainingPosCal] consider 2 rank data
2991 09:31:00.672528 u2DelayCellTimex100 = 270/100 ps
2992 09:31:00.676237 CA0 delay=37 (7~68),Diff = 6 PI (28 cell)
2993 09:31:00.682890 CA1 delay=37 (7~68),Diff = 6 PI (28 cell)
2994 09:31:00.685894 CA2 delay=34 (4~64),Diff = 3 PI (14 cell)
2995 09:31:00.689093 CA3 delay=33 (3~64),Diff = 2 PI (9 cell)
2996 09:31:00.692557 CA4 delay=32 (2~63),Diff = 1 PI (4 cell)
2997 09:31:00.695728 CA5 delay=31 (1~62),Diff = 0 PI (0 cell)
2998 09:31:00.696327
2999 09:31:00.699163 CA PerBit enable=1, Macro0, CA PI delay=31
3000 09:31:00.699737
3001 09:31:00.702971 [CBTSetCACLKResult] CA Dly = 31
3002 09:31:00.703542 CS Dly: 6 (0~38)
3003 09:31:00.705772
3004 09:31:00.709105 ----->DramcWriteLeveling(PI) begin...
3005 09:31:00.709688 ==
3006 09:31:00.712647 Dram Type= 6, Freq= 0, CH_1, rank 0
3007 09:31:00.715856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3008 09:31:00.716495 ==
3009 09:31:00.719293 Write leveling (Byte 0): 22 => 22
3010 09:31:00.722456 Write leveling (Byte 1): 22 => 22
3011 09:31:00.725429 DramcWriteLeveling(PI) end<-----
3012 09:31:00.725899
3013 09:31:00.726265 ==
3014 09:31:00.728952 Dram Type= 6, Freq= 0, CH_1, rank 0
3015 09:31:00.732551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3016 09:31:00.733127 ==
3017 09:31:00.735766 [Gating] SW mode calibration
3018 09:31:00.742184 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3019 09:31:00.748705 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3020 09:31:00.752033 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3021 09:31:00.755763 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3022 09:31:00.762116 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 09:31:00.765449 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3024 09:31:00.768578 0 11 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (1 0)
3025 09:31:00.775536 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3026 09:31:00.778593 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 09:31:00.781865 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 09:31:00.788958 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 09:31:00.792107 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 09:31:00.795877 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 09:31:00.799033 0 12 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3032 09:31:00.805605 0 12 16 | B1->B0 | 2f2f 4343 | 1 1 | (0 0) (0 0)
3033 09:31:00.808750 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 09:31:00.812435 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 09:31:00.819091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 09:31:00.822160 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 09:31:00.825682 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 09:31:00.832171 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 09:31:00.835620 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3040 09:31:00.839054 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3041 09:31:00.845226 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3042 09:31:00.849119 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 09:31:00.851929 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 09:31:00.859002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 09:31:00.861825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 09:31:00.865378 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 09:31:00.871989 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 09:31:00.875561 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 09:31:00.878654 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 09:31:00.881992 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 09:31:00.888545 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 09:31:00.892238 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 09:31:00.895394 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 09:31:00.902233 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 09:31:00.905373 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 09:31:00.908779 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3057 09:31:00.915443 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3058 09:31:00.918845 Total UI for P1: 0, mck2ui 16
3059 09:31:00.922155 best dqsien dly found for B0: ( 0, 15, 16)
3060 09:31:00.925383 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3061 09:31:00.928717 Total UI for P1: 0, mck2ui 16
3062 09:31:00.931963 best dqsien dly found for B1: ( 0, 15, 18)
3063 09:31:00.935566 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3064 09:31:00.938913 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3065 09:31:00.939483
3066 09:31:00.942001 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3067 09:31:00.945387 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3068 09:31:00.948696 [Gating] SW calibration Done
3069 09:31:00.949167 ==
3070 09:31:00.952337 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 09:31:00.955588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3072 09:31:00.958793 ==
3073 09:31:00.959358 RX Vref Scan: 0
3074 09:31:00.959732
3075 09:31:00.962266 RX Vref 0 -> 0, step: 1
3076 09:31:00.962761
3077 09:31:00.965188 RX Delay -40 -> 252, step: 8
3078 09:31:00.968780 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3079 09:31:00.972017 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3080 09:31:00.975378 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3081 09:31:00.978633 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3082 09:31:00.985410 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3083 09:31:00.988741 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3084 09:31:00.992114 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3085 09:31:00.995476 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3086 09:31:00.999273 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3087 09:31:01.002347 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3088 09:31:01.009347 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3089 09:31:01.012099 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3090 09:31:01.015331 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3091 09:31:01.018793 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3092 09:31:01.022412 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3093 09:31:01.029160 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3094 09:31:01.029724 ==
3095 09:31:01.032498 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 09:31:01.035957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3097 09:31:01.036576 ==
3098 09:31:01.036958 DQS Delay:
3099 09:31:01.039231 DQS0 = 0, DQS1 = 0
3100 09:31:01.039799 DQM Delay:
3101 09:31:01.042286 DQM0 = 116, DQM1 = 108
3102 09:31:01.042859 DQ Delay:
3103 09:31:01.046003 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3104 09:31:01.048927 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3105 09:31:01.052471 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3106 09:31:01.055810 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3107 09:31:01.056421
3108 09:31:01.056837
3109 09:31:01.057178 ==
3110 09:31:01.059449 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 09:31:01.065840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3112 09:31:01.066417 ==
3113 09:31:01.066897
3114 09:31:01.067439
3115 09:31:01.067797 TX Vref Scan disable
3116 09:31:01.069288 == TX Byte 0 ==
3117 09:31:01.072952 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3118 09:31:01.075948 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3119 09:31:01.079776 == TX Byte 1 ==
3120 09:31:01.082843 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3121 09:31:01.086388 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3122 09:31:01.089408 ==
3123 09:31:01.092660 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 09:31:01.096043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3125 09:31:01.096566 ==
3126 09:31:01.107403 TX Vref=22, minBit 11, minWin=25, winSum=420
3127 09:31:01.110506 TX Vref=24, minBit 11, minWin=25, winSum=423
3128 09:31:01.114090 TX Vref=26, minBit 0, minWin=26, winSum=427
3129 09:31:01.116824 TX Vref=28, minBit 8, minWin=26, winSum=431
3130 09:31:01.120364 TX Vref=30, minBit 9, minWin=25, winSum=431
3131 09:31:01.127224 TX Vref=32, minBit 9, minWin=26, winSum=431
3132 09:31:01.130478 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 28
3133 09:31:01.130946
3134 09:31:01.133941 Final TX Range 1 Vref 28
3135 09:31:01.134511
3136 09:31:01.134900 ==
3137 09:31:01.137121 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 09:31:01.140445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3139 09:31:01.141014 ==
3140 09:31:01.143884
3141 09:31:01.144508
3142 09:31:01.144886 TX Vref Scan disable
3143 09:31:01.147026 == TX Byte 0 ==
3144 09:31:01.150505 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3145 09:31:01.154075 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3146 09:31:01.157110 == TX Byte 1 ==
3147 09:31:01.160884 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3148 09:31:01.163775 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3149 09:31:01.167431
3150 09:31:01.167990 [DATLAT]
3151 09:31:01.168430 Freq=1200, CH1 RK0
3152 09:31:01.168791
3153 09:31:01.170251 DATLAT Default: 0xd
3154 09:31:01.170716 0, 0xFFFF, sum = 0
3155 09:31:01.173613 1, 0xFFFF, sum = 0
3156 09:31:01.174085 2, 0xFFFF, sum = 0
3157 09:31:01.176914 3, 0xFFFF, sum = 0
3158 09:31:01.177392 4, 0xFFFF, sum = 0
3159 09:31:01.180295 5, 0xFFFF, sum = 0
3160 09:31:01.183489 6, 0xFFFF, sum = 0
3161 09:31:01.183965 7, 0xFFFF, sum = 0
3162 09:31:01.186904 8, 0xFFFF, sum = 0
3163 09:31:01.187476 9, 0xFFFF, sum = 0
3164 09:31:01.190467 10, 0xFFFF, sum = 0
3165 09:31:01.191046 11, 0x0, sum = 1
3166 09:31:01.193383 12, 0x0, sum = 2
3167 09:31:01.193865 13, 0x0, sum = 3
3168 09:31:01.194247 14, 0x0, sum = 4
3169 09:31:01.197229 best_step = 12
3170 09:31:01.197704
3171 09:31:01.198080 ==
3172 09:31:01.200416 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 09:31:01.203730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3174 09:31:01.204371 ==
3175 09:31:01.207210 RX Vref Scan: 1
3176 09:31:01.207788
3177 09:31:01.210073 Set Vref Range= 32 -> 127
3178 09:31:01.210547
3179 09:31:01.210925 RX Vref 32 -> 127, step: 1
3180 09:31:01.211281
3181 09:31:01.213453 RX Delay -29 -> 252, step: 4
3182 09:31:01.213929
3183 09:31:01.216895 Set Vref, RX VrefLevel [Byte0]: 32
3184 09:31:01.220355 [Byte1]: 32
3185 09:31:01.223727
3186 09:31:01.224359 Set Vref, RX VrefLevel [Byte0]: 33
3187 09:31:01.227070 [Byte1]: 33
3188 09:31:01.231860
3189 09:31:01.232496 Set Vref, RX VrefLevel [Byte0]: 34
3190 09:31:01.235087 [Byte1]: 34
3191 09:31:01.240058
3192 09:31:01.240698 Set Vref, RX VrefLevel [Byte0]: 35
3193 09:31:01.243282 [Byte1]: 35
3194 09:31:01.247441
3195 09:31:01.248010 Set Vref, RX VrefLevel [Byte0]: 36
3196 09:31:01.250867 [Byte1]: 36
3197 09:31:01.255581
3198 09:31:01.256152 Set Vref, RX VrefLevel [Byte0]: 37
3199 09:31:01.258874 [Byte1]: 37
3200 09:31:01.263634
3201 09:31:01.264244 Set Vref, RX VrefLevel [Byte0]: 38
3202 09:31:01.266576 [Byte1]: 38
3203 09:31:01.271565
3204 09:31:01.272135 Set Vref, RX VrefLevel [Byte0]: 39
3205 09:31:01.274926 [Byte1]: 39
3206 09:31:01.279860
3207 09:31:01.280479 Set Vref, RX VrefLevel [Byte0]: 40
3208 09:31:01.282494 [Byte1]: 40
3209 09:31:01.287814
3210 09:31:01.288422 Set Vref, RX VrefLevel [Byte0]: 41
3211 09:31:01.290823 [Byte1]: 41
3212 09:31:01.295498
3213 09:31:01.296065 Set Vref, RX VrefLevel [Byte0]: 42
3214 09:31:01.298815 [Byte1]: 42
3215 09:31:01.303822
3216 09:31:01.304444 Set Vref, RX VrefLevel [Byte0]: 43
3217 09:31:01.306871 [Byte1]: 43
3218 09:31:01.311249
3219 09:31:01.311816 Set Vref, RX VrefLevel [Byte0]: 44
3220 09:31:01.314532 [Byte1]: 44
3221 09:31:01.319054
3222 09:31:01.319636 Set Vref, RX VrefLevel [Byte0]: 45
3223 09:31:01.322589 [Byte1]: 45
3224 09:31:01.327441
3225 09:31:01.328006 Set Vref, RX VrefLevel [Byte0]: 46
3226 09:31:01.330195 [Byte1]: 46
3227 09:31:01.335400
3228 09:31:01.335964 Set Vref, RX VrefLevel [Byte0]: 47
3229 09:31:01.338524 [Byte1]: 47
3230 09:31:01.343289
3231 09:31:01.343851 Set Vref, RX VrefLevel [Byte0]: 48
3232 09:31:01.346496 [Byte1]: 48
3233 09:31:01.350936
3234 09:31:01.351407 Set Vref, RX VrefLevel [Byte0]: 49
3235 09:31:01.354378 [Byte1]: 49
3236 09:31:01.359220
3237 09:31:01.359784 Set Vref, RX VrefLevel [Byte0]: 50
3238 09:31:01.362476 [Byte1]: 50
3239 09:31:01.367125
3240 09:31:01.367708 Set Vref, RX VrefLevel [Byte0]: 51
3241 09:31:01.370129 [Byte1]: 51
3242 09:31:01.375147
3243 09:31:01.375772 Set Vref, RX VrefLevel [Byte0]: 52
3244 09:31:01.378283 [Byte1]: 52
3245 09:31:01.382918
3246 09:31:01.383482 Set Vref, RX VrefLevel [Byte0]: 53
3247 09:31:01.386339 [Byte1]: 53
3248 09:31:01.391027
3249 09:31:01.391593 Set Vref, RX VrefLevel [Byte0]: 54
3250 09:31:01.394238 [Byte1]: 54
3251 09:31:01.398547
3252 09:31:01.399021 Set Vref, RX VrefLevel [Byte0]: 55
3253 09:31:01.402018 [Byte1]: 55
3254 09:31:01.406779
3255 09:31:01.407346 Set Vref, RX VrefLevel [Byte0]: 56
3256 09:31:01.410078 [Byte1]: 56
3257 09:31:01.414659
3258 09:31:01.415232 Set Vref, RX VrefLevel [Byte0]: 57
3259 09:31:01.417825 [Byte1]: 57
3260 09:31:01.422954
3261 09:31:01.423659 Set Vref, RX VrefLevel [Byte0]: 58
3262 09:31:01.425807 [Byte1]: 58
3263 09:31:01.430318
3264 09:31:01.430791 Set Vref, RX VrefLevel [Byte0]: 59
3265 09:31:01.434140 [Byte1]: 59
3266 09:31:01.438649
3267 09:31:01.439218 Set Vref, RX VrefLevel [Byte0]: 60
3268 09:31:01.441870 [Byte1]: 60
3269 09:31:01.446435
3270 09:31:01.447040 Set Vref, RX VrefLevel [Byte0]: 61
3271 09:31:01.449906 [Byte1]: 61
3272 09:31:01.454583
3273 09:31:01.455149 Set Vref, RX VrefLevel [Byte0]: 62
3274 09:31:01.457566 [Byte1]: 62
3275 09:31:01.462474
3276 09:31:01.463042 Set Vref, RX VrefLevel [Byte0]: 63
3277 09:31:01.465669 [Byte1]: 63
3278 09:31:01.470481
3279 09:31:01.471050 Set Vref, RX VrefLevel [Byte0]: 64
3280 09:31:01.473610 [Byte1]: 64
3281 09:31:01.478325
3282 09:31:01.478896 Set Vref, RX VrefLevel [Byte0]: 65
3283 09:31:01.481488 [Byte1]: 65
3284 09:31:01.485966
3285 09:31:01.486435 Final RX Vref Byte 0 = 52 to rank0
3286 09:31:01.489621 Final RX Vref Byte 1 = 50 to rank0
3287 09:31:01.493048 Final RX Vref Byte 0 = 52 to rank1
3288 09:31:01.496097 Final RX Vref Byte 1 = 50 to rank1==
3289 09:31:01.499949 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 09:31:01.505972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3291 09:31:01.506537 ==
3292 09:31:01.506920 DQS Delay:
3293 09:31:01.507272 DQS0 = 0, DQS1 = 0
3294 09:31:01.510062 DQM Delay:
3295 09:31:01.510631 DQM0 = 115, DQM1 = 105
3296 09:31:01.513056 DQ Delay:
3297 09:31:01.516103 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3298 09:31:01.519770 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3299 09:31:01.522744 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3300 09:31:01.526569 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =114
3301 09:31:01.527136
3302 09:31:01.527515
3303 09:31:01.532829 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3304 09:31:01.536406 CH1 RK0: MR19=404, MR18=1A1A
3305 09:31:01.542874 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3306 09:31:01.543450
3307 09:31:01.546138 ----->DramcWriteLeveling(PI) begin...
3308 09:31:01.546721 ==
3309 09:31:01.549339 Dram Type= 6, Freq= 0, CH_1, rank 1
3310 09:31:01.552830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3311 09:31:01.556444 ==
3312 09:31:01.557016 Write leveling (Byte 0): 20 => 20
3313 09:31:01.559517 Write leveling (Byte 1): 20 => 20
3314 09:31:01.562797 DramcWriteLeveling(PI) end<-----
3315 09:31:01.563355
3316 09:31:01.563735 ==
3317 09:31:01.566314 Dram Type= 6, Freq= 0, CH_1, rank 1
3318 09:31:01.572669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3319 09:31:01.573242 ==
3320 09:31:01.573678 [Gating] SW mode calibration
3321 09:31:01.583023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3322 09:31:01.586045 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3323 09:31:01.589352 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3324 09:31:01.596285 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3325 09:31:01.599689 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3326 09:31:01.603100 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
3327 09:31:01.609615 0 11 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
3328 09:31:01.613068 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 09:31:01.616305 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3330 09:31:01.622908 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3331 09:31:01.625989 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 09:31:01.630037 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 09:31:01.636326 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3334 09:31:01.639405 0 12 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3335 09:31:01.642930 0 12 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
3336 09:31:01.649331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 09:31:01.652732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 09:31:01.656257 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 09:31:01.662911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 09:31:01.666308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 09:31:01.669565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 09:31:01.673176 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3343 09:31:01.679224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3344 09:31:01.682879 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3345 09:31:01.686064 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 09:31:01.692527 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 09:31:01.695867 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 09:31:01.699212 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 09:31:01.706042 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 09:31:01.709345 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 09:31:01.712995 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 09:31:01.719538 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 09:31:01.722885 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 09:31:01.725898 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 09:31:01.732574 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 09:31:01.735848 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 09:31:01.739534 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 09:31:01.745995 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 09:31:01.749598 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3360 09:31:01.752697 Total UI for P1: 0, mck2ui 16
3361 09:31:01.756100 best dqsien dly found for B0: ( 0, 15, 14)
3362 09:31:01.759490 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3363 09:31:01.762615 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3364 09:31:01.766020 Total UI for P1: 0, mck2ui 16
3365 09:31:01.769368 best dqsien dly found for B1: ( 0, 15, 18)
3366 09:31:01.772816 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3367 09:31:01.779466 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3368 09:31:01.779893
3369 09:31:01.782710 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3370 09:31:01.785946 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3371 09:31:01.789265 [Gating] SW calibration Done
3372 09:31:01.789693 ==
3373 09:31:01.792501 Dram Type= 6, Freq= 0, CH_1, rank 1
3374 09:31:01.795782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3375 09:31:01.796237 ==
3376 09:31:01.799263 RX Vref Scan: 0
3377 09:31:01.799688
3378 09:31:01.800024 RX Vref 0 -> 0, step: 1
3379 09:31:01.800404
3380 09:31:01.802365 RX Delay -40 -> 252, step: 8
3381 09:31:01.805622 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3382 09:31:01.812352 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3383 09:31:01.815504 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3384 09:31:01.819431 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3385 09:31:01.822198 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3386 09:31:01.825670 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3387 09:31:01.832544 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3388 09:31:01.835409 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3389 09:31:01.839084 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3390 09:31:01.842567 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3391 09:31:01.845579 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3392 09:31:01.852292 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3393 09:31:01.855778 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3394 09:31:01.858801 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3395 09:31:01.862510 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3396 09:31:01.865862 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3397 09:31:01.866432 ==
3398 09:31:01.868809 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 09:31:01.875465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3400 09:31:01.876027 ==
3401 09:31:01.876469 DQS Delay:
3402 09:31:01.879120 DQS0 = 0, DQS1 = 0
3403 09:31:01.879838 DQM Delay:
3404 09:31:01.882136 DQM0 = 116, DQM1 = 104
3405 09:31:01.882698 DQ Delay:
3406 09:31:01.885334 DQ0 =119, DQ1 =111, DQ2 =111, DQ3 =111
3407 09:31:01.888791 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3408 09:31:01.892616 DQ8 =91, DQ9 =87, DQ10 =107, DQ11 =95
3409 09:31:01.895761 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3410 09:31:01.896378
3411 09:31:01.896755
3412 09:31:01.897100 ==
3413 09:31:01.898983 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 09:31:01.902503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3415 09:31:01.905888 ==
3416 09:31:01.906454
3417 09:31:01.906825
3418 09:31:01.907171 TX Vref Scan disable
3419 09:31:01.908710 == TX Byte 0 ==
3420 09:31:01.912448 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3421 09:31:01.915935 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3422 09:31:01.919285 == TX Byte 1 ==
3423 09:31:01.922629 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3424 09:31:01.925744 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3425 09:31:01.926311 ==
3426 09:31:01.928928 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 09:31:01.935684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3428 09:31:01.936304 ==
3429 09:31:01.946352 TX Vref=22, minBit 9, minWin=25, winSum=422
3430 09:31:01.949343 TX Vref=24, minBit 11, minWin=25, winSum=425
3431 09:31:01.952637 TX Vref=26, minBit 9, minWin=25, winSum=425
3432 09:31:01.956386 TX Vref=28, minBit 4, minWin=26, winSum=432
3433 09:31:01.959841 TX Vref=30, minBit 9, minWin=26, winSum=435
3434 09:31:01.962954 TX Vref=32, minBit 9, minWin=26, winSum=436
3435 09:31:01.969461 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3436 09:31:01.970019
3437 09:31:01.973113 Final TX Range 1 Vref 32
3438 09:31:01.973682
3439 09:31:01.974052 ==
3440 09:31:01.976313 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 09:31:01.979275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3442 09:31:01.979752 ==
3443 09:31:01.980121
3444 09:31:01.982847
3445 09:31:01.983409 TX Vref Scan disable
3446 09:31:01.985780 == TX Byte 0 ==
3447 09:31:01.989261 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3448 09:31:01.992844 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3449 09:31:01.996168 == TX Byte 1 ==
3450 09:31:01.999793 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3451 09:31:02.002821 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3452 09:31:02.003389
3453 09:31:02.006421 [DATLAT]
3454 09:31:02.006990 Freq=1200, CH1 RK1
3455 09:31:02.007367
3456 09:31:02.009494 DATLAT Default: 0xc
3457 09:31:02.010065 0, 0xFFFF, sum = 0
3458 09:31:02.012919 1, 0xFFFF, sum = 0
3459 09:31:02.013492 2, 0xFFFF, sum = 0
3460 09:31:02.016330 3, 0xFFFF, sum = 0
3461 09:31:02.016901 4, 0xFFFF, sum = 0
3462 09:31:02.019510 5, 0xFFFF, sum = 0
3463 09:31:02.019986 6, 0xFFFF, sum = 0
3464 09:31:02.022751 7, 0xFFFF, sum = 0
3465 09:31:02.023225 8, 0xFFFF, sum = 0
3466 09:31:02.026079 9, 0xFFFF, sum = 0
3467 09:31:02.029598 10, 0xFFFF, sum = 0
3468 09:31:02.030176 11, 0x0, sum = 1
3469 09:31:02.030560 12, 0x0, sum = 2
3470 09:31:02.033440 13, 0x0, sum = 3
3471 09:31:02.034015 14, 0x0, sum = 4
3472 09:31:02.036258 best_step = 12
3473 09:31:02.036820
3474 09:31:02.037195 ==
3475 09:31:02.039579 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 09:31:02.042877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3477 09:31:02.043349 ==
3478 09:31:02.046512 RX Vref Scan: 0
3479 09:31:02.047077
3480 09:31:02.047454 RX Vref 0 -> 0, step: 1
3481 09:31:02.047805
3482 09:31:02.049292 RX Delay -29 -> 252, step: 4
3483 09:31:02.056573 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3484 09:31:02.059530 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3485 09:31:02.063165 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3486 09:31:02.066158 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3487 09:31:02.069715 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3488 09:31:02.076597 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3489 09:31:02.079776 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3490 09:31:02.083438 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3491 09:31:02.086551 iDelay=195, Bit 8, Center 86 (19 ~ 154) 136
3492 09:31:02.089685 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3493 09:31:02.093046 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3494 09:31:02.099984 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3495 09:31:02.103214 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3496 09:31:02.106852 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3497 09:31:02.110235 iDelay=195, Bit 14, Center 112 (43 ~ 182) 140
3498 09:31:02.116842 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3499 09:31:02.117410 ==
3500 09:31:02.120218 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 09:31:02.123078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3502 09:31:02.123548 ==
3503 09:31:02.123920 DQS Delay:
3504 09:31:02.126564 DQS0 = 0, DQS1 = 0
3505 09:31:02.127032 DQM Delay:
3506 09:31:02.130383 DQM0 = 113, DQM1 = 103
3507 09:31:02.130952 DQ Delay:
3508 09:31:02.133184 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =110
3509 09:31:02.136633 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =112
3510 09:31:02.140373 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3511 09:31:02.143310 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3512 09:31:02.143888
3513 09:31:02.144315
3514 09:31:02.153207 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3515 09:31:02.156905 CH1 RK1: MR19=404, MR18=F0F
3516 09:31:02.159775 CH1_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
3517 09:31:02.163260 [RxdqsGatingPostProcess] freq 1200
3518 09:31:02.169714 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3519 09:31:02.173626 Pre-setting of DQS Precalculation
3520 09:31:02.176529 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3521 09:31:02.186763 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3522 09:31:02.192892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3523 09:31:02.193363
3524 09:31:02.193731
3525 09:31:02.196313 [Calibration Summary] 2400 Mbps
3526 09:31:02.196785 CH 0, Rank 0
3527 09:31:02.200111 SW Impedance : PASS
3528 09:31:02.200746 DUTY Scan : NO K
3529 09:31:02.203102 ZQ Calibration : PASS
3530 09:31:02.206557 Jitter Meter : NO K
3531 09:31:02.207129 CBT Training : PASS
3532 09:31:02.209903 Write leveling : PASS
3533 09:31:02.210480 RX DQS gating : PASS
3534 09:31:02.212981 RX DQ/DQS(RDDQC) : PASS
3535 09:31:02.216423 TX DQ/DQS : PASS
3536 09:31:02.216994 RX DATLAT : PASS
3537 09:31:02.219946 RX DQ/DQS(Engine): PASS
3538 09:31:02.223170 TX OE : NO K
3539 09:31:02.223645 All Pass.
3540 09:31:02.224017
3541 09:31:02.224401 CH 0, Rank 1
3542 09:31:02.226677 SW Impedance : PASS
3543 09:31:02.229899 DUTY Scan : NO K
3544 09:31:02.230469 ZQ Calibration : PASS
3545 09:31:02.233714 Jitter Meter : NO K
3546 09:31:02.236896 CBT Training : PASS
3547 09:31:02.237461 Write leveling : PASS
3548 09:31:02.240341 RX DQS gating : PASS
3549 09:31:02.243614 RX DQ/DQS(RDDQC) : PASS
3550 09:31:02.244251 TX DQ/DQS : PASS
3551 09:31:02.246969 RX DATLAT : PASS
3552 09:31:02.247540 RX DQ/DQS(Engine): PASS
3553 09:31:02.249754 TX OE : NO K
3554 09:31:02.250226 All Pass.
3555 09:31:02.250600
3556 09:31:02.253163 CH 1, Rank 0
3557 09:31:02.253732 SW Impedance : PASS
3558 09:31:02.256905 DUTY Scan : NO K
3559 09:31:02.260078 ZQ Calibration : PASS
3560 09:31:02.260695 Jitter Meter : NO K
3561 09:31:02.263433 CBT Training : PASS
3562 09:31:02.266888 Write leveling : PASS
3563 09:31:02.267459 RX DQS gating : PASS
3564 09:31:02.269724 RX DQ/DQS(RDDQC) : PASS
3565 09:31:02.273223 TX DQ/DQS : PASS
3566 09:31:02.273729 RX DATLAT : PASS
3567 09:31:02.276777 RX DQ/DQS(Engine): PASS
3568 09:31:02.280060 TX OE : NO K
3569 09:31:02.280694 All Pass.
3570 09:31:02.281075
3571 09:31:02.281427 CH 1, Rank 1
3572 09:31:02.283387 SW Impedance : PASS
3573 09:31:02.286332 DUTY Scan : NO K
3574 09:31:02.286834 ZQ Calibration : PASS
3575 09:31:02.289694 Jitter Meter : NO K
3576 09:31:02.293129 CBT Training : PASS
3577 09:31:02.293609 Write leveling : PASS
3578 09:31:02.296478 RX DQS gating : PASS
3579 09:31:02.296958 RX DQ/DQS(RDDQC) : PASS
3580 09:31:02.300116 TX DQ/DQS : PASS
3581 09:31:02.303258 RX DATLAT : PASS
3582 09:31:02.303850 RX DQ/DQS(Engine): PASS
3583 09:31:02.306776 TX OE : NO K
3584 09:31:02.307368 All Pass.
3585 09:31:02.307853
3586 09:31:02.309556 DramC Write-DBI off
3587 09:31:02.313259 PER_BANK_REFRESH: Hybrid Mode
3588 09:31:02.313845 TX_TRACKING: ON
3589 09:31:02.323115 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3590 09:31:02.326822 [FAST_K] Save calibration result to emmc
3591 09:31:02.329765 dramc_set_vcore_voltage set vcore to 650000
3592 09:31:02.332769 Read voltage for 600, 5
3593 09:31:02.333239 Vio18 = 0
3594 09:31:02.333611 Vcore = 650000
3595 09:31:02.336570 Vdram = 0
3596 09:31:02.337154 Vddq = 0
3597 09:31:02.337534 Vmddr = 0
3598 09:31:02.343226 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3599 09:31:02.346841 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3600 09:31:02.349538 MEM_TYPE=3, freq_sel=19
3601 09:31:02.352958 sv_algorithm_assistance_LP4_1600
3602 09:31:02.356393 ============ PULL DRAM RESETB DOWN ============
3603 09:31:02.360016 ========== PULL DRAM RESETB DOWN end =========
3604 09:31:02.366653 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3605 09:31:02.369537 ===================================
3606 09:31:02.373198 LPDDR4 DRAM CONFIGURATION
3607 09:31:02.376742 ===================================
3608 09:31:02.377315 EX_ROW_EN[0] = 0x0
3609 09:31:02.379951 EX_ROW_EN[1] = 0x0
3610 09:31:02.380573 LP4Y_EN = 0x0
3611 09:31:02.383161 WORK_FSP = 0x0
3612 09:31:02.383734 WL = 0x2
3613 09:31:02.386910 RL = 0x2
3614 09:31:02.387685 BL = 0x2
3615 09:31:02.389486 RPST = 0x0
3616 09:31:02.390204 RD_PRE = 0x0
3617 09:31:02.394263 WR_PRE = 0x1
3618 09:31:02.394854 WR_PST = 0x0
3619 09:31:02.396585 DBI_WR = 0x0
3620 09:31:02.397055 DBI_RD = 0x0
3621 09:31:02.400256 OTF = 0x1
3622 09:31:02.403179 ===================================
3623 09:31:02.406810 ===================================
3624 09:31:02.407384 ANA top config
3625 09:31:02.409544 ===================================
3626 09:31:02.413034 DLL_ASYNC_EN = 0
3627 09:31:02.416351 ALL_SLAVE_EN = 1
3628 09:31:02.419572 NEW_RANK_MODE = 1
3629 09:31:02.420148 DLL_IDLE_MODE = 1
3630 09:31:02.422878 LP45_APHY_COMB_EN = 1
3631 09:31:02.426322 TX_ODT_DIS = 1
3632 09:31:02.429799 NEW_8X_MODE = 1
3633 09:31:02.433096 ===================================
3634 09:31:02.436664 ===================================
3635 09:31:02.439693 data_rate = 1200
3636 09:31:02.440307 CKR = 1
3637 09:31:02.443271 DQ_P2S_RATIO = 8
3638 09:31:02.445957 ===================================
3639 09:31:02.449474 CA_P2S_RATIO = 8
3640 09:31:02.452698 DQ_CA_OPEN = 0
3641 09:31:02.456091 DQ_SEMI_OPEN = 0
3642 09:31:02.459493 CA_SEMI_OPEN = 0
3643 09:31:02.460073 CA_FULL_RATE = 0
3644 09:31:02.462655 DQ_CKDIV4_EN = 1
3645 09:31:02.466417 CA_CKDIV4_EN = 1
3646 09:31:02.469477 CA_PREDIV_EN = 0
3647 09:31:02.473145 PH8_DLY = 0
3648 09:31:02.476070 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3649 09:31:02.476579 DQ_AAMCK_DIV = 4
3650 09:31:02.479386 CA_AAMCK_DIV = 4
3651 09:31:02.482756 CA_ADMCK_DIV = 4
3652 09:31:02.485855 DQ_TRACK_CA_EN = 0
3653 09:31:02.488948 CA_PICK = 600
3654 09:31:02.492569 CA_MCKIO = 600
3655 09:31:02.496484 MCKIO_SEMI = 0
3656 09:31:02.497054 PLL_FREQ = 2288
3657 09:31:02.499527 DQ_UI_PI_RATIO = 32
3658 09:31:02.502701 CA_UI_PI_RATIO = 0
3659 09:31:02.505971 ===================================
3660 09:31:02.509338 ===================================
3661 09:31:02.512683 memory_type:LPDDR4
3662 09:31:02.513156 GP_NUM : 10
3663 09:31:02.515903 SRAM_EN : 1
3664 09:31:02.518881 MD32_EN : 0
3665 09:31:02.522540 ===================================
3666 09:31:02.523006 [ANA_INIT] >>>>>>>>>>>>>>
3667 09:31:02.525861 <<<<<< [CONFIGURE PHASE]: ANA_TX
3668 09:31:02.529287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3669 09:31:02.532367 ===================================
3670 09:31:02.535888 data_rate = 1200,PCW = 0X5800
3671 09:31:02.539283 ===================================
3672 09:31:02.542489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3673 09:31:02.548905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3674 09:31:02.552494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3675 09:31:02.559662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3676 09:31:02.562064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3677 09:31:02.565805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3678 09:31:02.566380 [ANA_INIT] flow start
3679 09:31:02.568828 [ANA_INIT] PLL >>>>>>>>
3680 09:31:02.572158 [ANA_INIT] PLL <<<<<<<<
3681 09:31:02.575497 [ANA_INIT] MIDPI >>>>>>>>
3682 09:31:02.575967 [ANA_INIT] MIDPI <<<<<<<<
3683 09:31:02.578929 [ANA_INIT] DLL >>>>>>>>
3684 09:31:02.579475 [ANA_INIT] flow end
3685 09:31:02.585737 ============ LP4 DIFF to SE enter ============
3686 09:31:02.589217 ============ LP4 DIFF to SE exit ============
3687 09:31:02.592451 [ANA_INIT] <<<<<<<<<<<<<
3688 09:31:02.595873 [Flow] Enable top DCM control >>>>>
3689 09:31:02.598818 [Flow] Enable top DCM control <<<<<
3690 09:31:02.602491 Enable DLL master slave shuffle
3691 09:31:02.605217 ==============================================================
3692 09:31:02.608936 Gating Mode config
3693 09:31:02.615298 ==============================================================
3694 09:31:02.615872 Config description:
3695 09:31:02.624921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3696 09:31:02.632014 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3697 09:31:02.635421 SELPH_MODE 0: By rank 1: By Phase
3698 09:31:02.641994 ==============================================================
3699 09:31:02.645792 GAT_TRACK_EN = 1
3700 09:31:02.648321 RX_GATING_MODE = 2
3701 09:31:02.651994 RX_GATING_TRACK_MODE = 2
3702 09:31:02.655265 SELPH_MODE = 1
3703 09:31:02.658744 PICG_EARLY_EN = 1
3704 09:31:02.662128 VALID_LAT_VALUE = 1
3705 09:31:02.665140 ==============================================================
3706 09:31:02.668604 Enter into Gating configuration >>>>
3707 09:31:02.671843 Exit from Gating configuration <<<<
3708 09:31:02.674819 Enter into DVFS_PRE_config >>>>>
3709 09:31:02.688076 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3710 09:31:02.688929 Exit from DVFS_PRE_config <<<<<
3711 09:31:02.691267 Enter into PICG configuration >>>>
3712 09:31:02.694527 Exit from PICG configuration <<<<
3713 09:31:02.698278 [RX_INPUT] configuration >>>>>
3714 09:31:02.701144 [RX_INPUT] configuration <<<<<
3715 09:31:02.708148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3716 09:31:02.711449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3717 09:31:02.718089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3718 09:31:02.725024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3719 09:31:02.731124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3720 09:31:02.738027 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3721 09:31:02.740959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3722 09:31:02.744244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3723 09:31:02.748013 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3724 09:31:02.754249 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3725 09:31:02.757570 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3726 09:31:02.760587 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 09:31:02.764378 ===================================
3728 09:31:02.767506 LPDDR4 DRAM CONFIGURATION
3729 09:31:02.770450 ===================================
3730 09:31:02.774061 EX_ROW_EN[0] = 0x0
3731 09:31:02.774545 EX_ROW_EN[1] = 0x0
3732 09:31:02.777173 LP4Y_EN = 0x0
3733 09:31:02.777731 WORK_FSP = 0x0
3734 09:31:02.780722 WL = 0x2
3735 09:31:02.781284 RL = 0x2
3736 09:31:02.784015 BL = 0x2
3737 09:31:02.784639 RPST = 0x0
3738 09:31:02.786955 RD_PRE = 0x0
3739 09:31:02.787432 WR_PRE = 0x1
3740 09:31:02.790515 WR_PST = 0x0
3741 09:31:02.790988 DBI_WR = 0x0
3742 09:31:02.793778 DBI_RD = 0x0
3743 09:31:02.794244 OTF = 0x1
3744 09:31:02.796897 ===================================
3745 09:31:02.803970 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3746 09:31:02.807388 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3747 09:31:02.810580 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 09:31:02.813699 ===================================
3749 09:31:02.816879 LPDDR4 DRAM CONFIGURATION
3750 09:31:02.820589 ===================================
3751 09:31:02.823928 EX_ROW_EN[0] = 0x10
3752 09:31:02.824435 EX_ROW_EN[1] = 0x0
3753 09:31:02.827152 LP4Y_EN = 0x0
3754 09:31:02.827721 WORK_FSP = 0x0
3755 09:31:02.830512 WL = 0x2
3756 09:31:02.831084 RL = 0x2
3757 09:31:02.833555 BL = 0x2
3758 09:31:02.834022 RPST = 0x0
3759 09:31:02.837592 RD_PRE = 0x0
3760 09:31:02.838163 WR_PRE = 0x1
3761 09:31:02.840607 WR_PST = 0x0
3762 09:31:02.841180 DBI_WR = 0x0
3763 09:31:02.844084 DBI_RD = 0x0
3764 09:31:02.844694 OTF = 0x1
3765 09:31:02.847097 ===================================
3766 09:31:02.853601 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3767 09:31:02.858161 nWR fixed to 30
3768 09:31:02.861863 [ModeRegInit_LP4] CH0 RK0
3769 09:31:02.862447 [ModeRegInit_LP4] CH0 RK1
3770 09:31:02.864909 [ModeRegInit_LP4] CH1 RK0
3771 09:31:02.868334 [ModeRegInit_LP4] CH1 RK1
3772 09:31:02.868910 match AC timing 16
3773 09:31:02.875089 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3774 09:31:02.878560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3775 09:31:02.881233 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3776 09:31:02.888095 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3777 09:31:02.891188 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3778 09:31:02.891679 ==
3779 09:31:02.894720 Dram Type= 6, Freq= 0, CH_0, rank 0
3780 09:31:02.897982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3781 09:31:02.898456 ==
3782 09:31:02.904594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3783 09:31:02.910980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3784 09:31:02.914515 [CA 0] Center 36 (6~66) winsize 61
3785 09:31:02.918078 [CA 1] Center 35 (5~66) winsize 62
3786 09:31:02.920982 [CA 2] Center 34 (4~65) winsize 62
3787 09:31:02.924278 [CA 3] Center 34 (4~65) winsize 62
3788 09:31:02.927784 [CA 4] Center 33 (3~64) winsize 62
3789 09:31:02.930997 [CA 5] Center 33 (3~64) winsize 62
3790 09:31:02.931564
3791 09:31:02.934260 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3792 09:31:02.934732
3793 09:31:02.937742 [CATrainingPosCal] consider 1 rank data
3794 09:31:02.941144 u2DelayCellTimex100 = 270/100 ps
3795 09:31:02.944292 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3796 09:31:02.947501 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3797 09:31:02.951306 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3798 09:31:02.954223 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3799 09:31:02.957996 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3800 09:31:02.964556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3801 09:31:02.965129
3802 09:31:02.967657 CA PerBit enable=1, Macro0, CA PI delay=33
3803 09:31:02.968289
3804 09:31:02.970626 [CBTSetCACLKResult] CA Dly = 33
3805 09:31:02.971096 CS Dly: 5 (0~36)
3806 09:31:02.971467 ==
3807 09:31:02.974288 Dram Type= 6, Freq= 0, CH_0, rank 1
3808 09:31:02.977448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3809 09:31:02.981134 ==
3810 09:31:02.984114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3811 09:31:02.990667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3812 09:31:02.994157 [CA 0] Center 35 (5~66) winsize 62
3813 09:31:02.997447 [CA 1] Center 35 (5~66) winsize 62
3814 09:31:03.000408 [CA 2] Center 34 (4~65) winsize 62
3815 09:31:03.003830 [CA 3] Center 34 (4~65) winsize 62
3816 09:31:03.007426 [CA 4] Center 33 (3~64) winsize 62
3817 09:31:03.010872 [CA 5] Center 33 (3~64) winsize 62
3818 09:31:03.011445
3819 09:31:03.014154 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3820 09:31:03.014727
3821 09:31:03.017055 [CATrainingPosCal] consider 2 rank data
3822 09:31:03.020389 u2DelayCellTimex100 = 270/100 ps
3823 09:31:03.023837 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3824 09:31:03.027584 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3825 09:31:03.030347 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3826 09:31:03.033968 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3827 09:31:03.040571 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3828 09:31:03.044110 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3829 09:31:03.044724
3830 09:31:03.047192 CA PerBit enable=1, Macro0, CA PI delay=33
3831 09:31:03.047765
3832 09:31:03.050299 [CBTSetCACLKResult] CA Dly = 33
3833 09:31:03.050771 CS Dly: 5 (0~36)
3834 09:31:03.051142
3835 09:31:03.053716 ----->DramcWriteLeveling(PI) begin...
3836 09:31:03.054192 ==
3837 09:31:03.057112 Dram Type= 6, Freq= 0, CH_0, rank 0
3838 09:31:03.063871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3839 09:31:03.064383 ==
3840 09:31:03.066903 Write leveling (Byte 0): 28 => 28
3841 09:31:03.070336 Write leveling (Byte 1): 28 => 28
3842 09:31:03.070809 DramcWriteLeveling(PI) end<-----
3843 09:31:03.071182
3844 09:31:03.074028 ==
3845 09:31:03.076854 Dram Type= 6, Freq= 0, CH_0, rank 0
3846 09:31:03.080577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3847 09:31:03.081050 ==
3848 09:31:03.083931 [Gating] SW mode calibration
3849 09:31:03.089949 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3850 09:31:03.093474 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3851 09:31:03.100542 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3852 09:31:03.103777 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3853 09:31:03.107280 0 5 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
3854 09:31:03.113592 0 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3855 09:31:03.116713 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 09:31:03.120399 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 09:31:03.126895 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 09:31:03.130000 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3859 09:31:03.133201 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 09:31:03.140287 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 09:31:03.143672 0 6 8 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
3862 09:31:03.146884 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3863 09:31:03.153196 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 09:31:03.156340 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 09:31:03.159832 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 09:31:03.166593 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 09:31:03.169830 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 09:31:03.172781 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 09:31:03.179826 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 09:31:03.183185 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3871 09:31:03.186506 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 09:31:03.192803 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 09:31:03.196253 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 09:31:03.199838 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 09:31:03.206332 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 09:31:03.209688 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 09:31:03.212906 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 09:31:03.216036 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 09:31:03.223058 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 09:31:03.226475 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 09:31:03.229196 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 09:31:03.236365 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 09:31:03.239892 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 09:31:03.243010 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 09:31:03.249395 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3886 09:31:03.252940 Total UI for P1: 0, mck2ui 16
3887 09:31:03.255980 best dqsien dly found for B0: ( 0, 9, 6)
3888 09:31:03.259604 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3889 09:31:03.262827 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3890 09:31:03.266053 Total UI for P1: 0, mck2ui 16
3891 09:31:03.269227 best dqsien dly found for B1: ( 0, 9, 10)
3892 09:31:03.272426 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3893 09:31:03.275760 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3894 09:31:03.276302
3895 09:31:03.282731 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3896 09:31:03.285927 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3897 09:31:03.289287 [Gating] SW calibration Done
3898 09:31:03.289759 ==
3899 09:31:03.292532 Dram Type= 6, Freq= 0, CH_0, rank 0
3900 09:31:03.295809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3901 09:31:03.296321 ==
3902 09:31:03.296702 RX Vref Scan: 0
3903 09:31:03.297047
3904 09:31:03.299351 RX Vref 0 -> 0, step: 1
3905 09:31:03.299927
3906 09:31:03.302828 RX Delay -230 -> 252, step: 16
3907 09:31:03.305956 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3908 09:31:03.312644 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3909 09:31:03.315689 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3910 09:31:03.318943 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3911 09:31:03.322050 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3912 09:31:03.325900 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3913 09:31:03.332326 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3914 09:31:03.335553 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3915 09:31:03.339093 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3916 09:31:03.342349 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3917 09:31:03.348825 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3918 09:31:03.352405 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3919 09:31:03.355501 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3920 09:31:03.358955 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3921 09:31:03.365441 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3922 09:31:03.368652 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3923 09:31:03.369228 ==
3924 09:31:03.372010 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 09:31:03.374948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3926 09:31:03.375533 ==
3927 09:31:03.378510 DQS Delay:
3928 09:31:03.379096 DQS0 = 0, DQS1 = 0
3929 09:31:03.379471 DQM Delay:
3930 09:31:03.382006 DQM0 = 40, DQM1 = 33
3931 09:31:03.382597 DQ Delay:
3932 09:31:03.384912 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
3933 09:31:03.388287 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3934 09:31:03.391592 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3935 09:31:03.394639 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3936 09:31:03.395108
3937 09:31:03.395476
3938 09:31:03.395814 ==
3939 09:31:03.398281 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 09:31:03.405100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3941 09:31:03.405673 ==
3942 09:31:03.406053
3943 09:31:03.406399
3944 09:31:03.406731 TX Vref Scan disable
3945 09:31:03.408254 == TX Byte 0 ==
3946 09:31:03.411950 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3947 09:31:03.418648 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3948 09:31:03.419213 == TX Byte 1 ==
3949 09:31:03.421898 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3950 09:31:03.428459 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3951 09:31:03.429085 ==
3952 09:31:03.431563 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 09:31:03.434604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3954 09:31:03.435253 ==
3955 09:31:03.435639
3956 09:31:03.435987
3957 09:31:03.438709 TX Vref Scan disable
3958 09:31:03.441476 == TX Byte 0 ==
3959 09:31:03.444594 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3960 09:31:03.448585 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3961 09:31:03.451530 == TX Byte 1 ==
3962 09:31:03.454818 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3963 09:31:03.458219 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3964 09:31:03.458803
3965 09:31:03.459181 [DATLAT]
3966 09:31:03.461598 Freq=600, CH0 RK0
3967 09:31:03.462129
3968 09:31:03.462508 DATLAT Default: 0x9
3969 09:31:03.464913 0, 0xFFFF, sum = 0
3970 09:31:03.468151 1, 0xFFFF, sum = 0
3971 09:31:03.468789 2, 0xFFFF, sum = 0
3972 09:31:03.471207 3, 0xFFFF, sum = 0
3973 09:31:03.471722 4, 0xFFFF, sum = 0
3974 09:31:03.474221 5, 0xFFFF, sum = 0
3975 09:31:03.474718 6, 0xFFFF, sum = 0
3976 09:31:03.478034 7, 0x0, sum = 1
3977 09:31:03.478642 8, 0x0, sum = 2
3978 09:31:03.479151 9, 0x0, sum = 3
3979 09:31:03.481030 10, 0x0, sum = 4
3980 09:31:03.481530 best_step = 8
3981 09:31:03.482021
3982 09:31:03.484285 ==
3983 09:31:03.484778 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 09:31:03.491185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3985 09:31:03.491770 ==
3986 09:31:03.492377 RX Vref Scan: 1
3987 09:31:03.492856
3988 09:31:03.494178 RX Vref 0 -> 0, step: 1
3989 09:31:03.494665
3990 09:31:03.497973 RX Delay -195 -> 252, step: 8
3991 09:31:03.498572
3992 09:31:03.500962 Set Vref, RX VrefLevel [Byte0]: 51
3993 09:31:03.504348 [Byte1]: 48
3994 09:31:03.504949
3995 09:31:03.507609 Final RX Vref Byte 0 = 51 to rank0
3996 09:31:03.511357 Final RX Vref Byte 1 = 48 to rank0
3997 09:31:03.514455 Final RX Vref Byte 0 = 51 to rank1
3998 09:31:03.517630 Final RX Vref Byte 1 = 48 to rank1==
3999 09:31:03.520835 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 09:31:03.524257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4001 09:31:03.524859 ==
4002 09:31:03.527616 DQS Delay:
4003 09:31:03.528253 DQS0 = 0, DQS1 = 0
4004 09:31:03.531395 DQM Delay:
4005 09:31:03.531991 DQM0 = 41, DQM1 = 30
4006 09:31:03.532541 DQ Delay:
4007 09:31:03.534167 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4008 09:31:03.537602 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4009 09:31:03.540951 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
4010 09:31:03.544292 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4011 09:31:03.544889
4012 09:31:03.547629
4013 09:31:03.553959 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4014 09:31:03.557294 CH0 RK0: MR19=808, MR18=5B5B
4015 09:31:03.564225 CH0_RK0: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4016 09:31:03.564840
4017 09:31:03.567022 ----->DramcWriteLeveling(PI) begin...
4018 09:31:03.567569 ==
4019 09:31:03.570455 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 09:31:03.573647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4021 09:31:03.574146 ==
4022 09:31:03.577150 Write leveling (Byte 0): 32 => 32
4023 09:31:03.580749 Write leveling (Byte 1): 28 => 28
4024 09:31:03.584374 DramcWriteLeveling(PI) end<-----
4025 09:31:03.584972
4026 09:31:03.585471 ==
4027 09:31:03.586840 Dram Type= 6, Freq= 0, CH_0, rank 1
4028 09:31:03.591188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4029 09:31:03.591792 ==
4030 09:31:03.593762 [Gating] SW mode calibration
4031 09:31:03.600582 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4032 09:31:03.607078 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4033 09:31:03.610029 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 09:31:03.613567 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 09:31:03.620055 0 5 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
4036 09:31:03.623193 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 09:31:03.626813 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 09:31:03.633020 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 09:31:03.636493 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 09:31:03.640507 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 09:31:03.646419 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 09:31:03.649991 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 09:31:03.653153 0 6 8 | B1->B0 | 2e2e 3333 | 0 0 | (1 1) (0 0)
4044 09:31:03.660341 0 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4045 09:31:03.663395 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 09:31:03.666553 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 09:31:03.673074 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 09:31:03.676613 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 09:31:03.679735 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 09:31:03.686292 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 09:31:03.689624 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4052 09:31:03.693143 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:31:03.699636 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:31:03.702871 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:31:03.706469 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:31:03.712675 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:31:03.716126 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:31:03.719341 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:31:03.726083 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:31:03.728951 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:31:03.732728 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 09:31:03.739295 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 09:31:03.742527 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 09:31:03.746138 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 09:31:03.752853 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 09:31:03.755688 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 09:31:03.759282 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4068 09:31:03.765963 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 09:31:03.766554 Total UI for P1: 0, mck2ui 16
4070 09:31:03.772338 best dqsien dly found for B0: ( 0, 9, 10)
4071 09:31:03.772933 Total UI for P1: 0, mck2ui 16
4072 09:31:03.775966 best dqsien dly found for B1: ( 0, 9, 8)
4073 09:31:03.782139 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4074 09:31:03.786103 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4075 09:31:03.786685
4076 09:31:03.788996 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4077 09:31:03.792307 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4078 09:31:03.795680 [Gating] SW calibration Done
4079 09:31:03.796152 ==
4080 09:31:03.799023 Dram Type= 6, Freq= 0, CH_0, rank 1
4081 09:31:03.802088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4082 09:31:03.802571 ==
4083 09:31:03.805604 RX Vref Scan: 0
4084 09:31:03.806201
4085 09:31:03.806579 RX Vref 0 -> 0, step: 1
4086 09:31:03.806929
4087 09:31:03.809412 RX Delay -230 -> 252, step: 16
4088 09:31:03.812012 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4089 09:31:03.818881 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4090 09:31:03.821969 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4091 09:31:03.825275 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4092 09:31:03.829110 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4093 09:31:03.835479 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4094 09:31:03.838804 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4095 09:31:03.842031 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4096 09:31:03.845589 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4097 09:31:03.848440 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4098 09:31:03.855162 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4099 09:31:03.858677 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4100 09:31:03.862174 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4101 09:31:03.865143 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4102 09:31:03.871960 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4103 09:31:03.874855 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4104 09:31:03.875349 ==
4105 09:31:03.878359 Dram Type= 6, Freq= 0, CH_0, rank 1
4106 09:31:03.881596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4107 09:31:03.882066 ==
4108 09:31:03.885824 DQS Delay:
4109 09:31:03.886391 DQS0 = 0, DQS1 = 0
4110 09:31:03.886768 DQM Delay:
4111 09:31:03.888412 DQM0 = 40, DQM1 = 32
4112 09:31:03.888884 DQ Delay:
4113 09:31:03.891682 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4114 09:31:03.894894 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4115 09:31:03.899269 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4116 09:31:03.901766 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4117 09:31:03.902347
4118 09:31:03.902723
4119 09:31:03.903068 ==
4120 09:31:03.905002 Dram Type= 6, Freq= 0, CH_0, rank 1
4121 09:31:03.911337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4122 09:31:03.911956 ==
4123 09:31:03.912403
4124 09:31:03.912764
4125 09:31:03.913102 TX Vref Scan disable
4126 09:31:03.915080 == TX Byte 0 ==
4127 09:31:03.918300 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4128 09:31:03.925191 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4129 09:31:03.925670 == TX Byte 1 ==
4130 09:31:03.928706 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4131 09:31:03.935297 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4132 09:31:03.935882 ==
4133 09:31:03.938250 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 09:31:03.941697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4135 09:31:03.942174 ==
4136 09:31:03.942550
4137 09:31:03.942895
4138 09:31:03.945122 TX Vref Scan disable
4139 09:31:03.948165 == TX Byte 0 ==
4140 09:31:03.951493 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4141 09:31:03.954901 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4142 09:31:03.958369 == TX Byte 1 ==
4143 09:31:03.961534 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4144 09:31:03.965429 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4145 09:31:03.965970
4146 09:31:03.966313 [DATLAT]
4147 09:31:03.968227 Freq=600, CH0 RK1
4148 09:31:03.968670
4149 09:31:03.971697 DATLAT Default: 0x8
4150 09:31:03.972286 0, 0xFFFF, sum = 0
4151 09:31:03.975087 1, 0xFFFF, sum = 0
4152 09:31:03.975635 2, 0xFFFF, sum = 0
4153 09:31:03.978114 3, 0xFFFF, sum = 0
4154 09:31:03.978551 4, 0xFFFF, sum = 0
4155 09:31:03.981524 5, 0xFFFF, sum = 0
4156 09:31:03.981958 6, 0xFFFF, sum = 0
4157 09:31:03.985009 7, 0x0, sum = 1
4158 09:31:03.985559 8, 0x0, sum = 2
4159 09:31:03.988163 9, 0x0, sum = 3
4160 09:31:03.988649 10, 0x0, sum = 4
4161 09:31:03.989001 best_step = 8
4162 09:31:03.989320
4163 09:31:03.991331 ==
4164 09:31:03.991765 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 09:31:03.997992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4166 09:31:03.998425 ==
4167 09:31:03.998767 RX Vref Scan: 0
4168 09:31:03.999084
4169 09:31:04.001317 RX Vref 0 -> 0, step: 1
4170 09:31:04.001748
4171 09:31:04.004660 RX Delay -195 -> 252, step: 8
4172 09:31:04.008427 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4173 09:31:04.014737 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4174 09:31:04.018534 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4175 09:31:04.021018 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4176 09:31:04.024671 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4177 09:31:04.031595 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4178 09:31:04.034928 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4179 09:31:04.037741 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4180 09:31:04.041134 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4181 09:31:04.044382 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4182 09:31:04.051162 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4183 09:31:04.054328 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4184 09:31:04.058040 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4185 09:31:04.061382 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4186 09:31:04.067905 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4187 09:31:04.071034 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4188 09:31:04.071577 ==
4189 09:31:04.074425 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 09:31:04.077623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4191 09:31:04.078065 ==
4192 09:31:04.080722 DQS Delay:
4193 09:31:04.081148 DQS0 = 0, DQS1 = 0
4194 09:31:04.084646 DQM Delay:
4195 09:31:04.085186 DQM0 = 41, DQM1 = 32
4196 09:31:04.085530 DQ Delay:
4197 09:31:04.087714 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4198 09:31:04.090897 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4199 09:31:04.094009 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4200 09:31:04.097656 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4201 09:31:04.098193
4202 09:31:04.098541
4203 09:31:04.107840 [DQSOSCAuto] RK1, (LSB)MR18= 0x7171, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4204 09:31:04.110776 CH0 RK1: MR19=808, MR18=7171
4205 09:31:04.117248 CH0_RK1: MR19=0x808, MR18=0x7171, DQSOSC=388, MR23=63, INC=174, DEC=116
4206 09:31:04.117795 [RxdqsGatingPostProcess] freq 600
4207 09:31:04.124078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4208 09:31:04.127476 Pre-setting of DQS Precalculation
4209 09:31:04.130902 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4210 09:31:04.133949 ==
4211 09:31:04.134490 Dram Type= 6, Freq= 0, CH_1, rank 0
4212 09:31:04.140654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4213 09:31:04.141184 ==
4214 09:31:04.143671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4215 09:31:04.150529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4216 09:31:04.154011 [CA 0] Center 35 (5~66) winsize 62
4217 09:31:04.157768 [CA 1] Center 35 (4~66) winsize 63
4218 09:31:04.161060 [CA 2] Center 33 (3~64) winsize 62
4219 09:31:04.164350 [CA 3] Center 33 (3~64) winsize 62
4220 09:31:04.167599 [CA 4] Center 33 (2~64) winsize 63
4221 09:31:04.171010 [CA 5] Center 33 (2~64) winsize 63
4222 09:31:04.171593
4223 09:31:04.174022 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4224 09:31:04.174491
4225 09:31:04.177492 [CATrainingPosCal] consider 1 rank data
4226 09:31:04.180708 u2DelayCellTimex100 = 270/100 ps
4227 09:31:04.184221 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4228 09:31:04.187330 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4229 09:31:04.194082 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4230 09:31:04.197340 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4231 09:31:04.200726 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4232 09:31:04.204023 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4233 09:31:04.204540
4234 09:31:04.207985 CA PerBit enable=1, Macro0, CA PI delay=33
4235 09:31:04.208631
4236 09:31:04.210958 [CBTSetCACLKResult] CA Dly = 33
4237 09:31:04.211533 CS Dly: 5 (0~36)
4238 09:31:04.214073 ==
4239 09:31:04.214547 Dram Type= 6, Freq= 0, CH_1, rank 1
4240 09:31:04.220977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4241 09:31:04.221557 ==
4242 09:31:04.224135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4243 09:31:04.230754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4244 09:31:04.234646 [CA 0] Center 35 (5~66) winsize 62
4245 09:31:04.237525 [CA 1] Center 34 (4~65) winsize 62
4246 09:31:04.240900 [CA 2] Center 33 (3~64) winsize 62
4247 09:31:04.244504 [CA 3] Center 33 (3~64) winsize 62
4248 09:31:04.247737 [CA 4] Center 32 (2~63) winsize 62
4249 09:31:04.250943 [CA 5] Center 32 (2~63) winsize 62
4250 09:31:04.251532
4251 09:31:04.253968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4252 09:31:04.254453
4253 09:31:04.257892 [CATrainingPosCal] consider 2 rank data
4254 09:31:04.261037 u2DelayCellTimex100 = 270/100 ps
4255 09:31:04.264640 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4256 09:31:04.270858 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4257 09:31:04.273749 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4258 09:31:04.277206 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4259 09:31:04.280812 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4260 09:31:04.284170 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4261 09:31:04.284799
4262 09:31:04.287352 CA PerBit enable=1, Macro0, CA PI delay=32
4263 09:31:04.287826
4264 09:31:04.291004 [CBTSetCACLKResult] CA Dly = 32
4265 09:31:04.291581 CS Dly: 5 (0~36)
4266 09:31:04.294008
4267 09:31:04.297179 ----->DramcWriteLeveling(PI) begin...
4268 09:31:04.297680 ==
4269 09:31:04.300488 Dram Type= 6, Freq= 0, CH_1, rank 0
4270 09:31:04.303795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4271 09:31:04.304321 ==
4272 09:31:04.307527 Write leveling (Byte 0): 27 => 27
4273 09:31:04.310560 Write leveling (Byte 1): 27 => 27
4274 09:31:04.313953 DramcWriteLeveling(PI) end<-----
4275 09:31:04.314717
4276 09:31:04.315113 ==
4277 09:31:04.317521 Dram Type= 6, Freq= 0, CH_1, rank 0
4278 09:31:04.320632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4279 09:31:04.321115 ==
4280 09:31:04.323617 [Gating] SW mode calibration
4281 09:31:04.330303 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4282 09:31:04.336806 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4283 09:31:04.340437 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4284 09:31:04.344000 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4285 09:31:04.350473 0 5 8 | B1->B0 | 3030 2a2a | 0 0 | (1 1) (1 1)
4286 09:31:04.353212 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 09:31:04.356624 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 09:31:04.363051 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 09:31:04.366592 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 09:31:04.369970 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 09:31:04.376743 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 09:31:04.379877 0 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4293 09:31:04.383137 0 6 8 | B1->B0 | 3939 3c3c | 0 1 | (0 0) (0 0)
4294 09:31:04.389805 0 6 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4295 09:31:04.392901 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 09:31:04.396315 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 09:31:04.403058 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 09:31:04.406184 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 09:31:04.409600 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 09:31:04.415930 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4301 09:31:04.419538 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4302 09:31:04.422958 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 09:31:04.429348 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 09:31:04.432928 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 09:31:04.435929 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 09:31:04.442763 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 09:31:04.446056 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 09:31:04.449176 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 09:31:04.456070 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 09:31:04.459738 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 09:31:04.462253 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 09:31:04.469577 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 09:31:04.472376 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 09:31:04.476132 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 09:31:04.479110 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 09:31:04.485493 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 09:31:04.489050 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4318 09:31:04.492267 Total UI for P1: 0, mck2ui 16
4319 09:31:04.495276 best dqsien dly found for B0: ( 0, 9, 6)
4320 09:31:04.498757 Total UI for P1: 0, mck2ui 16
4321 09:31:04.502179 best dqsien dly found for B1: ( 0, 9, 6)
4322 09:31:04.505940 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4323 09:31:04.508548 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4324 09:31:04.509021
4325 09:31:04.512299 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4326 09:31:04.515257 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4327 09:31:04.519103 [Gating] SW calibration Done
4328 09:31:04.519671 ==
4329 09:31:04.522245 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 09:31:04.528505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 09:31:04.529083 ==
4332 09:31:04.529468 RX Vref Scan: 0
4333 09:31:04.529819
4334 09:31:04.531958 RX Vref 0 -> 0, step: 1
4335 09:31:04.532577
4336 09:31:04.535261 RX Delay -230 -> 252, step: 16
4337 09:31:04.538637 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4338 09:31:04.541772 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4339 09:31:04.545679 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4340 09:31:04.552228 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4341 09:31:04.554968 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4342 09:31:04.558212 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4343 09:31:04.561998 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4344 09:31:04.568699 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4345 09:31:04.571594 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4346 09:31:04.575458 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4347 09:31:04.578111 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4348 09:31:04.584933 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4349 09:31:04.588842 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4350 09:31:04.591554 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4351 09:31:04.594982 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4352 09:31:04.601472 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4353 09:31:04.601944 ==
4354 09:31:04.604967 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 09:31:04.608003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4356 09:31:04.608510 ==
4357 09:31:04.608887 DQS Delay:
4358 09:31:04.611369 DQS0 = 0, DQS1 = 0
4359 09:31:04.611835 DQM Delay:
4360 09:31:04.614417 DQM0 = 42, DQM1 = 35
4361 09:31:04.614883 DQ Delay:
4362 09:31:04.617985 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4363 09:31:04.621264 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4364 09:31:04.624292 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4365 09:31:04.627320 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4366 09:31:04.627786
4367 09:31:04.628155
4368 09:31:04.628565 ==
4369 09:31:04.631178 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 09:31:04.634572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4371 09:31:04.634997 ==
4372 09:31:04.635336
4373 09:31:04.637723
4374 09:31:04.638201 TX Vref Scan disable
4375 09:31:04.640867 == TX Byte 0 ==
4376 09:31:04.644402 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4377 09:31:04.647371 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4378 09:31:04.650702 == TX Byte 1 ==
4379 09:31:04.653981 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4380 09:31:04.657106 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4381 09:31:04.660509 ==
4382 09:31:04.661030 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 09:31:04.667473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4384 09:31:04.667999 ==
4385 09:31:04.668382
4386 09:31:04.668697
4387 09:31:04.670360 TX Vref Scan disable
4388 09:31:04.670781 == TX Byte 0 ==
4389 09:31:04.676966 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4390 09:31:04.680457 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4391 09:31:04.680994 == TX Byte 1 ==
4392 09:31:04.687264 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4393 09:31:04.690592 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4394 09:31:04.691164
4395 09:31:04.691533 [DATLAT]
4396 09:31:04.693788 Freq=600, CH1 RK0
4397 09:31:04.694253
4398 09:31:04.694620 DATLAT Default: 0x9
4399 09:31:04.696979 0, 0xFFFF, sum = 0
4400 09:31:04.697459 1, 0xFFFF, sum = 0
4401 09:31:04.700056 2, 0xFFFF, sum = 0
4402 09:31:04.700706 3, 0xFFFF, sum = 0
4403 09:31:04.703894 4, 0xFFFF, sum = 0
4404 09:31:04.706881 5, 0xFFFF, sum = 0
4405 09:31:04.707452 6, 0xFFFF, sum = 0
4406 09:31:04.707828 7, 0x0, sum = 1
4407 09:31:04.710209 8, 0x0, sum = 2
4408 09:31:04.710779 9, 0x0, sum = 3
4409 09:31:04.713773 10, 0x0, sum = 4
4410 09:31:04.714345 best_step = 8
4411 09:31:04.714718
4412 09:31:04.715085 ==
4413 09:31:04.716766 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 09:31:04.723440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4415 09:31:04.724011 ==
4416 09:31:04.724480 RX Vref Scan: 1
4417 09:31:04.724841
4418 09:31:04.726730 RX Vref 0 -> 0, step: 1
4419 09:31:04.727194
4420 09:31:04.730636 RX Delay -195 -> 252, step: 8
4421 09:31:04.731200
4422 09:31:04.733773 Set Vref, RX VrefLevel [Byte0]: 52
4423 09:31:04.736908 [Byte1]: 50
4424 09:31:04.737475
4425 09:31:04.740115 Final RX Vref Byte 0 = 52 to rank0
4426 09:31:04.743695 Final RX Vref Byte 1 = 50 to rank0
4427 09:31:04.746884 Final RX Vref Byte 0 = 52 to rank1
4428 09:31:04.749969 Final RX Vref Byte 1 = 50 to rank1==
4429 09:31:04.753383 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 09:31:04.756795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4431 09:31:04.757375 ==
4432 09:31:04.759449 DQS Delay:
4433 09:31:04.759910 DQS0 = 0, DQS1 = 0
4434 09:31:04.763015 DQM Delay:
4435 09:31:04.763703 DQM0 = 37, DQM1 = 31
4436 09:31:04.764086 DQ Delay:
4437 09:31:04.766246 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4438 09:31:04.769885 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4439 09:31:04.773046 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4440 09:31:04.776583 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4441 09:31:04.777050
4442 09:31:04.777421
4443 09:31:04.786131 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4444 09:31:04.789464 CH1 RK0: MR19=808, MR18=7E7E
4445 09:31:04.796318 CH1_RK0: MR19=0x808, MR18=0x7E7E, DQSOSC=386, MR23=63, INC=176, DEC=117
4446 09:31:04.796890
4447 09:31:04.799301 ----->DramcWriteLeveling(PI) begin...
4448 09:31:04.799772 ==
4449 09:31:04.802597 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 09:31:04.806076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4451 09:31:04.806660 ==
4452 09:31:04.809382 Write leveling (Byte 0): 28 => 28
4453 09:31:04.812740 Write leveling (Byte 1): 28 => 28
4454 09:31:04.815748 DramcWriteLeveling(PI) end<-----
4455 09:31:04.816260
4456 09:31:04.816831 ==
4457 09:31:04.819384 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 09:31:04.822692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4459 09:31:04.823262 ==
4460 09:31:04.826242 [Gating] SW mode calibration
4461 09:31:04.832937 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4462 09:31:04.838949 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4463 09:31:04.842869 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4464 09:31:04.845858 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4465 09:31:04.852411 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4466 09:31:04.855539 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 09:31:04.859192 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 09:31:04.865423 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 09:31:04.868925 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 09:31:04.872446 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 09:31:04.878988 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 09:31:04.882866 0 6 4 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
4473 09:31:04.885339 0 6 8 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4474 09:31:04.892545 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:31:04.895991 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 09:31:04.899044 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 09:31:04.905645 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 09:31:04.908791 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 09:31:04.912249 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4480 09:31:04.918900 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4481 09:31:04.922927 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:31:04.925825 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:31:04.928968 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:31:04.935312 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:31:04.938544 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:31:04.941753 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:31:04.948483 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:31:04.951794 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:31:04.955234 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:31:04.961672 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:31:04.964745 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:31:04.968296 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:31:04.974546 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:31:04.977766 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:31:04.981072 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:31:04.987793 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 09:31:04.991082 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 09:31:04.994476 Total UI for P1: 0, mck2ui 16
4499 09:31:04.997757 best dqsien dly found for B0: ( 0, 9, 6)
4500 09:31:05.001067 Total UI for P1: 0, mck2ui 16
4501 09:31:05.004560 best dqsien dly found for B1: ( 0, 9, 6)
4502 09:31:05.007802 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4503 09:31:05.011216 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4504 09:31:05.011376
4505 09:31:05.014425 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4506 09:31:05.017931 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4507 09:31:05.020955 [Gating] SW calibration Done
4508 09:31:05.021115 ==
4509 09:31:05.024194 Dram Type= 6, Freq= 0, CH_1, rank 1
4510 09:31:05.027688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4511 09:31:05.030853 ==
4512 09:31:05.031015 RX Vref Scan: 0
4513 09:31:05.031142
4514 09:31:05.034720 RX Vref 0 -> 0, step: 1
4515 09:31:05.034880
4516 09:31:05.037479 RX Delay -230 -> 252, step: 16
4517 09:31:05.040878 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4518 09:31:05.044525 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4519 09:31:05.047366 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4520 09:31:05.054023 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4521 09:31:05.057422 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4522 09:31:05.060800 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4523 09:31:05.063949 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4524 09:31:05.067325 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4525 09:31:05.074055 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4526 09:31:05.077216 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4527 09:31:05.080377 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 09:31:05.083937 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4529 09:31:05.090248 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4530 09:31:05.093774 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4531 09:31:05.096955 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4532 09:31:05.100846 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4533 09:31:05.103835 ==
4534 09:31:05.103999 Dram Type= 6, Freq= 0, CH_1, rank 1
4535 09:31:05.110516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4536 09:31:05.110681 ==
4537 09:31:05.110810 DQS Delay:
4538 09:31:05.113736 DQS0 = 0, DQS1 = 0
4539 09:31:05.113898 DQM Delay:
4540 09:31:05.117237 DQM0 = 42, DQM1 = 33
4541 09:31:05.117399 DQ Delay:
4542 09:31:05.120504 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4543 09:31:05.123769 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4544 09:31:05.127112 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4545 09:31:05.130620 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4546 09:31:05.130872
4547 09:31:05.131014
4548 09:31:05.131144 ==
4549 09:31:05.134148 Dram Type= 6, Freq= 0, CH_1, rank 1
4550 09:31:05.137174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4551 09:31:05.137414 ==
4552 09:31:05.137559
4553 09:31:05.137688
4554 09:31:05.140437 TX Vref Scan disable
4555 09:31:05.143564 == TX Byte 0 ==
4556 09:31:05.147078 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4557 09:31:05.151060 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4558 09:31:05.153893 == TX Byte 1 ==
4559 09:31:05.157168 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4560 09:31:05.160893 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4561 09:31:05.161348 ==
4562 09:31:05.163712 Dram Type= 6, Freq= 0, CH_1, rank 1
4563 09:31:05.166953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4564 09:31:05.170899 ==
4565 09:31:05.171482
4566 09:31:05.171854
4567 09:31:05.172240 TX Vref Scan disable
4568 09:31:05.174489 == TX Byte 0 ==
4569 09:31:05.177898 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4570 09:31:05.184334 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4571 09:31:05.184902 == TX Byte 1 ==
4572 09:31:05.187992 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4573 09:31:05.194410 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4574 09:31:05.194981
4575 09:31:05.195359 [DATLAT]
4576 09:31:05.195705 Freq=600, CH1 RK1
4577 09:31:05.196042
4578 09:31:05.197919 DATLAT Default: 0x8
4579 09:31:05.198498 0, 0xFFFF, sum = 0
4580 09:31:05.200857 1, 0xFFFF, sum = 0
4581 09:31:05.201343 2, 0xFFFF, sum = 0
4582 09:31:05.204562 3, 0xFFFF, sum = 0
4583 09:31:05.207737 4, 0xFFFF, sum = 0
4584 09:31:05.208359 5, 0xFFFF, sum = 0
4585 09:31:05.211125 6, 0xFFFF, sum = 0
4586 09:31:05.211701 7, 0x0, sum = 1
4587 09:31:05.212081 8, 0x0, sum = 2
4588 09:31:05.214569 9, 0x0, sum = 3
4589 09:31:05.215143 10, 0x0, sum = 4
4590 09:31:05.217977 best_step = 8
4591 09:31:05.218726
4592 09:31:05.219152 ==
4593 09:31:05.221092 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 09:31:05.224400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4595 09:31:05.224975 ==
4596 09:31:05.228113 RX Vref Scan: 0
4597 09:31:05.228734
4598 09:31:05.229109 RX Vref 0 -> 0, step: 1
4599 09:31:05.229459
4600 09:31:05.230704 RX Delay -195 -> 252, step: 8
4601 09:31:05.238340 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4602 09:31:05.241688 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4603 09:31:05.244579 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4604 09:31:05.247949 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4605 09:31:05.254364 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4606 09:31:05.257946 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4607 09:31:05.261180 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4608 09:31:05.264523 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4609 09:31:05.271218 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4610 09:31:05.274592 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4611 09:31:05.277758 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4612 09:31:05.280714 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4613 09:31:05.287768 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4614 09:31:05.290891 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4615 09:31:05.294140 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4616 09:31:05.297580 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4617 09:31:05.298070 ==
4618 09:31:05.300667 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 09:31:05.307442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4620 09:31:05.308017 ==
4621 09:31:05.308456 DQS Delay:
4622 09:31:05.311153 DQS0 = 0, DQS1 = 0
4623 09:31:05.311722 DQM Delay:
4624 09:31:05.312098 DQM0 = 37, DQM1 = 28
4625 09:31:05.314270 DQ Delay:
4626 09:31:05.317543 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4627 09:31:05.320709 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4628 09:31:05.323962 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4629 09:31:05.327210 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4630 09:31:05.327687
4631 09:31:05.328058
4632 09:31:05.333953 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4633 09:31:05.337384 CH1 RK1: MR19=808, MR18=5454
4634 09:31:05.344089 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4635 09:31:05.347129 [RxdqsGatingPostProcess] freq 600
4636 09:31:05.350644 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4637 09:31:05.353706 Pre-setting of DQS Precalculation
4638 09:31:05.360598 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4639 09:31:05.367465 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4640 09:31:05.373899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4641 09:31:05.374471
4642 09:31:05.374847
4643 09:31:05.376845 [Calibration Summary] 1200 Mbps
4644 09:31:05.377314 CH 0, Rank 0
4645 09:31:05.380145 SW Impedance : PASS
4646 09:31:05.383544 DUTY Scan : NO K
4647 09:31:05.384112 ZQ Calibration : PASS
4648 09:31:05.386924 Jitter Meter : NO K
4649 09:31:05.390295 CBT Training : PASS
4650 09:31:05.390866 Write leveling : PASS
4651 09:31:05.393358 RX DQS gating : PASS
4652 09:31:05.396868 RX DQ/DQS(RDDQC) : PASS
4653 09:31:05.397338 TX DQ/DQS : PASS
4654 09:31:05.400473 RX DATLAT : PASS
4655 09:31:05.403233 RX DQ/DQS(Engine): PASS
4656 09:31:05.403720 TX OE : NO K
4657 09:31:05.406955 All Pass.
4658 09:31:05.407421
4659 09:31:05.407787 CH 0, Rank 1
4660 09:31:05.410284 SW Impedance : PASS
4661 09:31:05.410867 DUTY Scan : NO K
4662 09:31:05.413289 ZQ Calibration : PASS
4663 09:31:05.416598 Jitter Meter : NO K
4664 09:31:05.417072 CBT Training : PASS
4665 09:31:05.420319 Write leveling : PASS
4666 09:31:05.420888 RX DQS gating : PASS
4667 09:31:05.423592 RX DQ/DQS(RDDQC) : PASS
4668 09:31:05.427499 TX DQ/DQS : PASS
4669 09:31:05.428078 RX DATLAT : PASS
4670 09:31:05.429878 RX DQ/DQS(Engine): PASS
4671 09:31:05.433299 TX OE : NO K
4672 09:31:05.433771 All Pass.
4673 09:31:05.434142
4674 09:31:05.434487 CH 1, Rank 0
4675 09:31:05.436663 SW Impedance : PASS
4676 09:31:05.440035 DUTY Scan : NO K
4677 09:31:05.440560 ZQ Calibration : PASS
4678 09:31:05.443373 Jitter Meter : NO K
4679 09:31:05.446640 CBT Training : PASS
4680 09:31:05.447218 Write leveling : PASS
4681 09:31:05.449571 RX DQS gating : PASS
4682 09:31:05.453320 RX DQ/DQS(RDDQC) : PASS
4683 09:31:05.453892 TX DQ/DQS : PASS
4684 09:31:05.456538 RX DATLAT : PASS
4685 09:31:05.459956 RX DQ/DQS(Engine): PASS
4686 09:31:05.460563 TX OE : NO K
4687 09:31:05.463394 All Pass.
4688 09:31:05.463963
4689 09:31:05.464399 CH 1, Rank 1
4690 09:31:05.466017 SW Impedance : PASS
4691 09:31:05.466490 DUTY Scan : NO K
4692 09:31:05.469797 ZQ Calibration : PASS
4693 09:31:05.472800 Jitter Meter : NO K
4694 09:31:05.473274 CBT Training : PASS
4695 09:31:05.476294 Write leveling : PASS
4696 09:31:05.479543 RX DQS gating : PASS
4697 09:31:05.480100 RX DQ/DQS(RDDQC) : PASS
4698 09:31:05.483006 TX DQ/DQS : PASS
4699 09:31:05.483581 RX DATLAT : PASS
4700 09:31:05.486848 RX DQ/DQS(Engine): PASS
4701 09:31:05.489740 TX OE : NO K
4702 09:31:05.490318 All Pass.
4703 09:31:05.490692
4704 09:31:05.492902 DramC Write-DBI off
4705 09:31:05.493375 PER_BANK_REFRESH: Hybrid Mode
4706 09:31:05.496122 TX_TRACKING: ON
4707 09:31:05.506004 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4708 09:31:05.509832 [FAST_K] Save calibration result to emmc
4709 09:31:05.512896 dramc_set_vcore_voltage set vcore to 662500
4710 09:31:05.513374 Read voltage for 933, 3
4711 09:31:05.516107 Vio18 = 0
4712 09:31:05.516606 Vcore = 662500
4713 09:31:05.516979 Vdram = 0
4714 09:31:05.519318 Vddq = 0
4715 09:31:05.519907 Vmddr = 0
4716 09:31:05.522809 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4717 09:31:05.529311 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4718 09:31:05.532684 MEM_TYPE=3, freq_sel=17
4719 09:31:05.535853 sv_algorithm_assistance_LP4_1600
4720 09:31:05.539413 ============ PULL DRAM RESETB DOWN ============
4721 09:31:05.542726 ========== PULL DRAM RESETB DOWN end =========
4722 09:31:05.549176 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4723 09:31:05.552424 ===================================
4724 09:31:05.552897 LPDDR4 DRAM CONFIGURATION
4725 09:31:05.556043 ===================================
4726 09:31:05.559122 EX_ROW_EN[0] = 0x0
4727 09:31:05.559549 EX_ROW_EN[1] = 0x0
4728 09:31:05.562479 LP4Y_EN = 0x0
4729 09:31:05.562910 WORK_FSP = 0x0
4730 09:31:05.565836 WL = 0x3
4731 09:31:05.566267 RL = 0x3
4732 09:31:05.569147 BL = 0x2
4733 09:31:05.572450 RPST = 0x0
4734 09:31:05.572875 RD_PRE = 0x0
4735 09:31:05.575649 WR_PRE = 0x1
4736 09:31:05.576075 WR_PST = 0x0
4737 09:31:05.578979 DBI_WR = 0x0
4738 09:31:05.579402 DBI_RD = 0x0
4739 09:31:05.582478 OTF = 0x1
4740 09:31:05.585941 ===================================
4741 09:31:05.588813 ===================================
4742 09:31:05.589241 ANA top config
4743 09:31:05.592488 ===================================
4744 09:31:05.595734 DLL_ASYNC_EN = 0
4745 09:31:05.598892 ALL_SLAVE_EN = 1
4746 09:31:05.599318 NEW_RANK_MODE = 1
4747 09:31:05.602077 DLL_IDLE_MODE = 1
4748 09:31:05.605389 LP45_APHY_COMB_EN = 1
4749 09:31:05.608675 TX_ODT_DIS = 1
4750 09:31:05.612145 NEW_8X_MODE = 1
4751 09:31:05.615580 ===================================
4752 09:31:05.618501 ===================================
4753 09:31:05.618931 data_rate = 1866
4754 09:31:05.622146 CKR = 1
4755 09:31:05.625177 DQ_P2S_RATIO = 8
4756 09:31:05.628766 ===================================
4757 09:31:05.631850 CA_P2S_RATIO = 8
4758 09:31:05.635185 DQ_CA_OPEN = 0
4759 09:31:05.638556 DQ_SEMI_OPEN = 0
4760 09:31:05.639027 CA_SEMI_OPEN = 0
4761 09:31:05.642186 CA_FULL_RATE = 0
4762 09:31:05.645051 DQ_CKDIV4_EN = 1
4763 09:31:05.648492 CA_CKDIV4_EN = 1
4764 09:31:05.651685 CA_PREDIV_EN = 0
4765 09:31:05.655207 PH8_DLY = 0
4766 09:31:05.655638 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4767 09:31:05.658601 DQ_AAMCK_DIV = 4
4768 09:31:05.661579 CA_AAMCK_DIV = 4
4769 09:31:05.664907 CA_ADMCK_DIV = 4
4770 09:31:05.668652 DQ_TRACK_CA_EN = 0
4771 09:31:05.671428 CA_PICK = 933
4772 09:31:05.674664 CA_MCKIO = 933
4773 09:31:05.675088 MCKIO_SEMI = 0
4774 09:31:05.678376 PLL_FREQ = 3732
4775 09:31:05.681404 DQ_UI_PI_RATIO = 32
4776 09:31:05.685323 CA_UI_PI_RATIO = 0
4777 09:31:05.688401 ===================================
4778 09:31:05.691744 ===================================
4779 09:31:05.695096 memory_type:LPDDR4
4780 09:31:05.695782 GP_NUM : 10
4781 09:31:05.697916 SRAM_EN : 1
4782 09:31:05.701317 MD32_EN : 0
4783 09:31:05.704679 ===================================
4784 09:31:05.705187 [ANA_INIT] >>>>>>>>>>>>>>
4785 09:31:05.708232 <<<<<< [CONFIGURE PHASE]: ANA_TX
4786 09:31:05.711514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4787 09:31:05.714951 ===================================
4788 09:31:05.718426 data_rate = 1866,PCW = 0X8f00
4789 09:31:05.721398 ===================================
4790 09:31:05.724151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4791 09:31:05.730998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4792 09:31:05.734516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4793 09:31:05.740840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4794 09:31:05.744327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4795 09:31:05.747662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4796 09:31:05.748294 [ANA_INIT] flow start
4797 09:31:05.750990 [ANA_INIT] PLL >>>>>>>>
4798 09:31:05.754161 [ANA_INIT] PLL <<<<<<<<
4799 09:31:05.757970 [ANA_INIT] MIDPI >>>>>>>>
4800 09:31:05.758557 [ANA_INIT] MIDPI <<<<<<<<
4801 09:31:05.760656 [ANA_INIT] DLL >>>>>>>>
4802 09:31:05.764317 [ANA_INIT] flow end
4803 09:31:05.767750 ============ LP4 DIFF to SE enter ============
4804 09:31:05.770998 ============ LP4 DIFF to SE exit ============
4805 09:31:05.774348 [ANA_INIT] <<<<<<<<<<<<<
4806 09:31:05.777563 [Flow] Enable top DCM control >>>>>
4807 09:31:05.780502 [Flow] Enable top DCM control <<<<<
4808 09:31:05.783970 Enable DLL master slave shuffle
4809 09:31:05.787442 ==============================================================
4810 09:31:05.790645 Gating Mode config
4811 09:31:05.797376 ==============================================================
4812 09:31:05.797972 Config description:
4813 09:31:05.807090 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4814 09:31:05.814084 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4815 09:31:05.817113 SELPH_MODE 0: By rank 1: By Phase
4816 09:31:05.823748 ==============================================================
4817 09:31:05.826620 GAT_TRACK_EN = 1
4818 09:31:05.830068 RX_GATING_MODE = 2
4819 09:31:05.833543 RX_GATING_TRACK_MODE = 2
4820 09:31:05.836794 SELPH_MODE = 1
4821 09:31:05.839983 PICG_EARLY_EN = 1
4822 09:31:05.843798 VALID_LAT_VALUE = 1
4823 09:31:05.846942 ==============================================================
4824 09:31:05.850168 Enter into Gating configuration >>>>
4825 09:31:05.853088 Exit from Gating configuration <<<<
4826 09:31:05.856685 Enter into DVFS_PRE_config >>>>>
4827 09:31:05.870001 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4828 09:31:05.870606 Exit from DVFS_PRE_config <<<<<
4829 09:31:05.873027 Enter into PICG configuration >>>>
4830 09:31:05.876967 Exit from PICG configuration <<<<
4831 09:31:05.880067 [RX_INPUT] configuration >>>>>
4832 09:31:05.883217 [RX_INPUT] configuration <<<<<
4833 09:31:05.889787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4834 09:31:05.892844 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4835 09:31:05.899436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4836 09:31:05.906267 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4837 09:31:05.912427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4838 09:31:05.919489 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4839 09:31:05.922565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4840 09:31:05.925780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4841 09:31:05.932809 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4842 09:31:05.936013 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4843 09:31:05.939422 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4844 09:31:05.942764 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 09:31:05.946243 ===================================
4846 09:31:05.949249 LPDDR4 DRAM CONFIGURATION
4847 09:31:05.952670 ===================================
4848 09:31:05.956033 EX_ROW_EN[0] = 0x0
4849 09:31:05.956672 EX_ROW_EN[1] = 0x0
4850 09:31:05.959405 LP4Y_EN = 0x0
4851 09:31:05.960057 WORK_FSP = 0x0
4852 09:31:05.962497 WL = 0x3
4853 09:31:05.963078 RL = 0x3
4854 09:31:05.965972 BL = 0x2
4855 09:31:05.966546 RPST = 0x0
4856 09:31:05.968984 RD_PRE = 0x0
4857 09:31:05.969457 WR_PRE = 0x1
4858 09:31:05.972373 WR_PST = 0x0
4859 09:31:05.972844 DBI_WR = 0x0
4860 09:31:05.976006 DBI_RD = 0x0
4861 09:31:05.976661 OTF = 0x1
4862 09:31:05.979015 ===================================
4863 09:31:05.985692 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4864 09:31:05.988931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4865 09:31:05.992442 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4866 09:31:05.995576 ===================================
4867 09:31:05.999178 LPDDR4 DRAM CONFIGURATION
4868 09:31:06.002695 ===================================
4869 09:31:06.005800 EX_ROW_EN[0] = 0x10
4870 09:31:06.006418 EX_ROW_EN[1] = 0x0
4871 09:31:06.008857 LP4Y_EN = 0x0
4872 09:31:06.009501 WORK_FSP = 0x0
4873 09:31:06.012734 WL = 0x3
4874 09:31:06.013307 RL = 0x3
4875 09:31:06.015698 BL = 0x2
4876 09:31:06.016166 RPST = 0x0
4877 09:31:06.019304 RD_PRE = 0x0
4878 09:31:06.019880 WR_PRE = 0x1
4879 09:31:06.022360 WR_PST = 0x0
4880 09:31:06.023114 DBI_WR = 0x0
4881 09:31:06.025399 DBI_RD = 0x0
4882 09:31:06.025872 OTF = 0x1
4883 09:31:06.028903 ===================================
4884 09:31:06.035877 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4885 09:31:06.040648 nWR fixed to 30
4886 09:31:06.043269 [ModeRegInit_LP4] CH0 RK0
4887 09:31:06.043738 [ModeRegInit_LP4] CH0 RK1
4888 09:31:06.046791 [ModeRegInit_LP4] CH1 RK0
4889 09:31:06.050207 [ModeRegInit_LP4] CH1 RK1
4890 09:31:06.050785 match AC timing 8
4891 09:31:06.056940 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4892 09:31:06.060005 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4893 09:31:06.063229 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4894 09:31:06.070217 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4895 09:31:06.073273 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4896 09:31:06.073845 ==
4897 09:31:06.076475 Dram Type= 6, Freq= 0, CH_0, rank 0
4898 09:31:06.080226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4899 09:31:06.080817 ==
4900 09:31:06.086474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4901 09:31:06.092996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4902 09:31:06.096332 [CA 0] Center 38 (8~69) winsize 62
4903 09:31:06.099847 [CA 1] Center 38 (8~69) winsize 62
4904 09:31:06.103258 [CA 2] Center 36 (5~67) winsize 63
4905 09:31:06.106596 [CA 3] Center 36 (5~67) winsize 63
4906 09:31:06.109383 [CA 4] Center 34 (4~65) winsize 62
4907 09:31:06.113327 [CA 5] Center 34 (4~65) winsize 62
4908 09:31:06.113975
4909 09:31:06.116297 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4910 09:31:06.116779
4911 09:31:06.119963 [CATrainingPosCal] consider 1 rank data
4912 09:31:06.123184 u2DelayCellTimex100 = 270/100 ps
4913 09:31:06.126190 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4914 09:31:06.129540 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4915 09:31:06.132802 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4916 09:31:06.136432 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4917 09:31:06.142557 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4918 09:31:06.146307 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4919 09:31:06.146885
4920 09:31:06.149506 CA PerBit enable=1, Macro0, CA PI delay=34
4921 09:31:06.150089
4922 09:31:06.152705 [CBTSetCACLKResult] CA Dly = 34
4923 09:31:06.153291 CS Dly: 7 (0~38)
4924 09:31:06.153668 ==
4925 09:31:06.155885 Dram Type= 6, Freq= 0, CH_0, rank 1
4926 09:31:06.159393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4927 09:31:06.162746 ==
4928 09:31:06.166053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4929 09:31:06.172830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4930 09:31:06.175984 [CA 0] Center 38 (8~69) winsize 62
4931 09:31:06.179776 [CA 1] Center 38 (7~69) winsize 63
4932 09:31:06.182463 [CA 2] Center 36 (6~67) winsize 62
4933 09:31:06.186037 [CA 3] Center 35 (5~66) winsize 62
4934 09:31:06.189256 [CA 4] Center 34 (3~65) winsize 63
4935 09:31:06.192915 [CA 5] Center 34 (4~65) winsize 62
4936 09:31:06.193493
4937 09:31:06.195783 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4938 09:31:06.196301
4939 09:31:06.199388 [CATrainingPosCal] consider 2 rank data
4940 09:31:06.202630 u2DelayCellTimex100 = 270/100 ps
4941 09:31:06.205586 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4942 09:31:06.208863 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4943 09:31:06.212064 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4944 09:31:06.218905 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4945 09:31:06.222216 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4946 09:31:06.225379 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4947 09:31:06.225852
4948 09:31:06.228766 CA PerBit enable=1, Macro0, CA PI delay=34
4949 09:31:06.229239
4950 09:31:06.231910 [CBTSetCACLKResult] CA Dly = 34
4951 09:31:06.232458 CS Dly: 7 (0~39)
4952 09:31:06.232843
4953 09:31:06.235686 ----->DramcWriteLeveling(PI) begin...
4954 09:31:06.236331 ==
4955 09:31:06.238691 Dram Type= 6, Freq= 0, CH_0, rank 0
4956 09:31:06.246028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4957 09:31:06.246626 ==
4958 09:31:06.248745 Write leveling (Byte 0): 27 => 27
4959 09:31:06.252349 Write leveling (Byte 1): 26 => 26
4960 09:31:06.252938 DramcWriteLeveling(PI) end<-----
4961 09:31:06.256017
4962 09:31:06.256656 ==
4963 09:31:06.258704 Dram Type= 6, Freq= 0, CH_0, rank 0
4964 09:31:06.262309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4965 09:31:06.262895 ==
4966 09:31:06.265830 [Gating] SW mode calibration
4967 09:31:06.272330 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4968 09:31:06.275596 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4969 09:31:06.281911 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 09:31:06.285872 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4971 09:31:06.288651 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4972 09:31:06.295443 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4973 09:31:06.298883 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4974 09:31:06.302231 0 10 20 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
4975 09:31:06.308532 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4976 09:31:06.312005 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 09:31:06.315402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 09:31:06.321694 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4979 09:31:06.324940 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4980 09:31:06.328304 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 09:31:06.335251 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 09:31:06.338658 0 11 20 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
4983 09:31:06.341725 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4984 09:31:06.348241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 09:31:06.351702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 09:31:06.354918 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4987 09:31:06.361708 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 09:31:06.365182 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 09:31:06.368577 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 09:31:06.375109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4991 09:31:06.377989 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 09:31:06.382088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 09:31:06.388289 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 09:31:06.391538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 09:31:06.394701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 09:31:06.401378 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 09:31:06.404836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 09:31:06.408276 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 09:31:06.414816 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 09:31:06.418575 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 09:31:06.420983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 09:31:06.427990 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 09:31:06.431096 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 09:31:06.434471 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 09:31:06.440902 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5006 09:31:06.444509 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5007 09:31:06.447694 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5008 09:31:06.451344 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5009 09:31:06.454453 Total UI for P1: 0, mck2ui 16
5010 09:31:06.457613 best dqsien dly found for B0: ( 0, 14, 20)
5011 09:31:06.461115 Total UI for P1: 0, mck2ui 16
5012 09:31:06.464525 best dqsien dly found for B1: ( 0, 14, 22)
5013 09:31:06.467517 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5014 09:31:06.474016 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5015 09:31:06.474593
5016 09:31:06.477264 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5017 09:31:06.481017 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5018 09:31:06.484045 [Gating] SW calibration Done
5019 09:31:06.484555 ==
5020 09:31:06.487239 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 09:31:06.491061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5022 09:31:06.491643 ==
5023 09:31:06.494268 RX Vref Scan: 0
5024 09:31:06.494840
5025 09:31:06.495218 RX Vref 0 -> 0, step: 1
5026 09:31:06.495566
5027 09:31:06.497251 RX Delay -80 -> 252, step: 8
5028 09:31:06.500427 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5029 09:31:06.504329 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5030 09:31:06.510447 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5031 09:31:06.514061 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5032 09:31:06.517445 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5033 09:31:06.520708 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5034 09:31:06.523989 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5035 09:31:06.527601 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5036 09:31:06.534273 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5037 09:31:06.537399 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5038 09:31:06.540690 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5039 09:31:06.543520 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5040 09:31:06.547113 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5041 09:31:06.553442 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5042 09:31:06.556830 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5043 09:31:06.560467 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5044 09:31:06.561041 ==
5045 09:31:06.563735 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 09:31:06.566931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5047 09:31:06.567517 ==
5048 09:31:06.570175 DQS Delay:
5049 09:31:06.570744 DQS0 = 0, DQS1 = 0
5050 09:31:06.573620 DQM Delay:
5051 09:31:06.574091 DQM0 = 95, DQM1 = 84
5052 09:31:06.574464 DQ Delay:
5053 09:31:06.576777 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5054 09:31:06.580422 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5055 09:31:06.583562 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
5056 09:31:06.586567 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5057 09:31:06.587038
5058 09:31:06.587461
5059 09:31:06.590424 ==
5060 09:31:06.593776 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 09:31:06.596876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5062 09:31:06.597587 ==
5063 09:31:06.598127
5064 09:31:06.598634
5065 09:31:06.600099 TX Vref Scan disable
5066 09:31:06.600692 == TX Byte 0 ==
5067 09:31:06.603705 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5068 09:31:06.610385 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5069 09:31:06.610856 == TX Byte 1 ==
5070 09:31:06.613618 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5071 09:31:06.620514 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5072 09:31:06.621090 ==
5073 09:31:06.624158 Dram Type= 6, Freq= 0, CH_0, rank 0
5074 09:31:06.626888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5075 09:31:06.627360 ==
5076 09:31:06.627801
5077 09:31:06.628151
5078 09:31:06.630303 TX Vref Scan disable
5079 09:31:06.633246 == TX Byte 0 ==
5080 09:31:06.636974 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5081 09:31:06.640457 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5082 09:31:06.643597 == TX Byte 1 ==
5083 09:31:06.646984 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5084 09:31:06.649860 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5085 09:31:06.650332
5086 09:31:06.650702 [DATLAT]
5087 09:31:06.653575 Freq=933, CH0 RK0
5088 09:31:06.654047
5089 09:31:06.656457 DATLAT Default: 0xd
5090 09:31:06.656932 0, 0xFFFF, sum = 0
5091 09:31:06.660082 1, 0xFFFF, sum = 0
5092 09:31:06.660599 2, 0xFFFF, sum = 0
5093 09:31:06.663214 3, 0xFFFF, sum = 0
5094 09:31:06.663690 4, 0xFFFF, sum = 0
5095 09:31:06.666716 5, 0xFFFF, sum = 0
5096 09:31:06.667326 6, 0xFFFF, sum = 0
5097 09:31:06.669896 7, 0xFFFF, sum = 0
5098 09:31:06.670374 8, 0xFFFF, sum = 0
5099 09:31:06.673774 9, 0xFFFF, sum = 0
5100 09:31:06.674358 10, 0x0, sum = 1
5101 09:31:06.676582 11, 0x0, sum = 2
5102 09:31:06.677062 12, 0x0, sum = 3
5103 09:31:06.679965 13, 0x0, sum = 4
5104 09:31:06.680607 best_step = 11
5105 09:31:06.680988
5106 09:31:06.681336 ==
5107 09:31:06.683392 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 09:31:06.686888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5109 09:31:06.690149 ==
5110 09:31:06.690722 RX Vref Scan: 1
5111 09:31:06.691100
5112 09:31:06.693168 RX Vref 0 -> 0, step: 1
5113 09:31:06.693635
5114 09:31:06.696425 RX Delay -69 -> 252, step: 4
5115 09:31:06.696895
5116 09:31:06.699827 Set Vref, RX VrefLevel [Byte0]: 51
5117 09:31:06.700326 [Byte1]: 48
5118 09:31:06.704903
5119 09:31:06.705470 Final RX Vref Byte 0 = 51 to rank0
5120 09:31:06.708766 Final RX Vref Byte 1 = 48 to rank0
5121 09:31:06.711526 Final RX Vref Byte 0 = 51 to rank1
5122 09:31:06.715303 Final RX Vref Byte 1 = 48 to rank1==
5123 09:31:06.718393 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 09:31:06.724913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5125 09:31:06.725477 ==
5126 09:31:06.725852 DQS Delay:
5127 09:31:06.726197 DQS0 = 0, DQS1 = 0
5128 09:31:06.728162 DQM Delay:
5129 09:31:06.728677 DQM0 = 96, DQM1 = 87
5130 09:31:06.731377 DQ Delay:
5131 09:31:06.735224 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5132 09:31:06.738255 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =102
5133 09:31:06.741775 DQ8 =76, DQ9 =70, DQ10 =88, DQ11 =78
5134 09:31:06.745160 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5135 09:31:06.745718
5136 09:31:06.746096
5137 09:31:06.751579 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5138 09:31:06.754895 CH0 RK0: MR19=505, MR18=1E1E
5139 09:31:06.761645 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5140 09:31:06.762279
5141 09:31:06.764679 ----->DramcWriteLeveling(PI) begin...
5142 09:31:06.765164 ==
5143 09:31:06.768135 Dram Type= 6, Freq= 0, CH_0, rank 1
5144 09:31:06.771400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5145 09:31:06.771883 ==
5146 09:31:06.774628 Write leveling (Byte 0): 26 => 26
5147 09:31:06.777853 Write leveling (Byte 1): 26 => 26
5148 09:31:06.781270 DramcWriteLeveling(PI) end<-----
5149 09:31:06.781911
5150 09:31:06.782316 ==
5151 09:31:06.784465 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 09:31:06.787669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5153 09:31:06.788146 ==
5154 09:31:06.791183 [Gating] SW mode calibration
5155 09:31:06.797734 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5156 09:31:06.804816 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5157 09:31:06.808255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 09:31:06.814213 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 09:31:06.818145 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 09:31:06.820770 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 09:31:06.827455 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 09:31:06.831132 0 10 20 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
5163 09:31:06.834087 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5164 09:31:06.841106 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 09:31:06.844326 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 09:31:06.848298 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 09:31:06.851288 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 09:31:06.857517 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 09:31:06.861083 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5170 09:31:06.864255 0 11 20 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (1 1)
5171 09:31:06.871090 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 09:31:06.874373 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 09:31:06.877989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 09:31:06.884139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 09:31:06.887550 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 09:31:06.890928 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 09:31:06.897291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 09:31:06.900709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5179 09:31:06.904408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5180 09:31:06.910701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:31:06.914362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:31:06.917254 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:31:06.923798 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:31:06.927014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:31:06.930567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:31:06.936978 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:31:06.940515 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 09:31:06.943389 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:31:06.950084 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 09:31:06.953388 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:31:06.957317 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:31:06.963797 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 09:31:06.967077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 09:31:06.970436 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5195 09:31:06.976695 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5196 09:31:06.979954 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 09:31:06.983555 Total UI for P1: 0, mck2ui 16
5198 09:31:06.987497 best dqsien dly found for B0: ( 0, 14, 22)
5199 09:31:06.990049 Total UI for P1: 0, mck2ui 16
5200 09:31:06.993560 best dqsien dly found for B1: ( 0, 14, 22)
5201 09:31:06.996966 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5202 09:31:06.999774 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5203 09:31:07.000306
5204 09:31:07.003034 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5205 09:31:07.006713 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5206 09:31:07.010009 [Gating] SW calibration Done
5207 09:31:07.010585 ==
5208 09:31:07.013271 Dram Type= 6, Freq= 0, CH_0, rank 1
5209 09:31:07.019931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5210 09:31:07.020585 ==
5211 09:31:07.020972 RX Vref Scan: 0
5212 09:31:07.021324
5213 09:31:07.023072 RX Vref 0 -> 0, step: 1
5214 09:31:07.023653
5215 09:31:07.026701 RX Delay -80 -> 252, step: 8
5216 09:31:07.029521 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5217 09:31:07.032872 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5218 09:31:07.036417 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5219 09:31:07.039877 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5220 09:31:07.046510 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5221 09:31:07.050042 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5222 09:31:07.053019 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5223 09:31:07.055956 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5224 09:31:07.059920 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5225 09:31:07.062987 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5226 09:31:07.069513 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5227 09:31:07.072845 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5228 09:31:07.076731 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5229 09:31:07.079717 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5230 09:31:07.082872 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5231 09:31:07.089265 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5232 09:31:07.089836 ==
5233 09:31:07.092905 Dram Type= 6, Freq= 0, CH_0, rank 1
5234 09:31:07.096154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5235 09:31:07.096773 ==
5236 09:31:07.097154 DQS Delay:
5237 09:31:07.099321 DQS0 = 0, DQS1 = 0
5238 09:31:07.099891 DQM Delay:
5239 09:31:07.102365 DQM0 = 95, DQM1 = 85
5240 09:31:07.102837 DQ Delay:
5241 09:31:07.106006 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5242 09:31:07.109188 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5243 09:31:07.112434 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5244 09:31:07.115706 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5245 09:31:07.116194
5246 09:31:07.116568
5247 09:31:07.116911 ==
5248 09:31:07.118884 Dram Type= 6, Freq= 0, CH_0, rank 1
5249 09:31:07.122801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5250 09:31:07.125594 ==
5251 09:31:07.126296
5252 09:31:07.126686
5253 09:31:07.127035 TX Vref Scan disable
5254 09:31:07.128888 == TX Byte 0 ==
5255 09:31:07.132003 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5256 09:31:07.135552 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5257 09:31:07.138857 == TX Byte 1 ==
5258 09:31:07.142221 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5259 09:31:07.145336 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5260 09:31:07.148861 ==
5261 09:31:07.152134 Dram Type= 6, Freq= 0, CH_0, rank 1
5262 09:31:07.155169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5263 09:31:07.155825 ==
5264 09:31:07.156446
5265 09:31:07.156819
5266 09:31:07.158372 TX Vref Scan disable
5267 09:31:07.158845 == TX Byte 0 ==
5268 09:31:07.165227 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5269 09:31:07.168749 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5270 09:31:07.169339 == TX Byte 1 ==
5271 09:31:07.175088 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5272 09:31:07.178211 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5273 09:31:07.178687
5274 09:31:07.179143 [DATLAT]
5275 09:31:07.181788 Freq=933, CH0 RK1
5276 09:31:07.182346
5277 09:31:07.182887 DATLAT Default: 0xb
5278 09:31:07.184807 0, 0xFFFF, sum = 0
5279 09:31:07.185359 1, 0xFFFF, sum = 0
5280 09:31:07.188279 2, 0xFFFF, sum = 0
5281 09:31:07.188774 3, 0xFFFF, sum = 0
5282 09:31:07.191862 4, 0xFFFF, sum = 0
5283 09:31:07.192482 5, 0xFFFF, sum = 0
5284 09:31:07.194976 6, 0xFFFF, sum = 0
5285 09:31:07.198487 7, 0xFFFF, sum = 0
5286 09:31:07.199047 8, 0xFFFF, sum = 0
5287 09:31:07.201493 9, 0xFFFF, sum = 0
5288 09:31:07.201967 10, 0x0, sum = 1
5289 09:31:07.202347 11, 0x0, sum = 2
5290 09:31:07.205116 12, 0x0, sum = 3
5291 09:31:07.205694 13, 0x0, sum = 4
5292 09:31:07.208366 best_step = 11
5293 09:31:07.208932
5294 09:31:07.209308 ==
5295 09:31:07.211552 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 09:31:07.214667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5297 09:31:07.215140 ==
5298 09:31:07.218402 RX Vref Scan: 0
5299 09:31:07.218968
5300 09:31:07.219343 RX Vref 0 -> 0, step: 1
5301 09:31:07.219691
5302 09:31:07.221380 RX Delay -77 -> 252, step: 4
5303 09:31:07.229180 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5304 09:31:07.232436 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5305 09:31:07.235734 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5306 09:31:07.239037 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5307 09:31:07.242897 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5308 09:31:07.245562 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5309 09:31:07.252371 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5310 09:31:07.255741 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5311 09:31:07.258993 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5312 09:31:07.262627 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5313 09:31:07.265448 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5314 09:31:07.272585 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5315 09:31:07.275475 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5316 09:31:07.278587 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5317 09:31:07.282218 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5318 09:31:07.285155 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5319 09:31:07.285671 ==
5320 09:31:07.288422 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 09:31:07.295348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5322 09:31:07.295910 ==
5323 09:31:07.296327 DQS Delay:
5324 09:31:07.298505 DQS0 = 0, DQS1 = 0
5325 09:31:07.299075 DQM Delay:
5326 09:31:07.299451 DQM0 = 97, DQM1 = 85
5327 09:31:07.301998 DQ Delay:
5328 09:31:07.305337 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5329 09:31:07.308582 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5330 09:31:07.311761 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5331 09:31:07.315017 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5332 09:31:07.315489
5333 09:31:07.315863
5334 09:31:07.322055 [DQSOSCAuto] RK1, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5335 09:31:07.325098 CH0 RK1: MR19=505, MR18=3131
5336 09:31:07.332064 CH0_RK1: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5337 09:31:07.334563 [RxdqsGatingPostProcess] freq 933
5338 09:31:07.341296 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5339 09:31:07.341859 Pre-setting of DQS Precalculation
5340 09:31:07.347921 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5341 09:31:07.348430 ==
5342 09:31:07.351291 Dram Type= 6, Freq= 0, CH_1, rank 0
5343 09:31:07.354928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5344 09:31:07.355502 ==
5345 09:31:07.361442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5346 09:31:07.368016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5347 09:31:07.371394 [CA 0] Center 37 (7~68) winsize 62
5348 09:31:07.374446 [CA 1] Center 37 (6~68) winsize 63
5349 09:31:07.377958 [CA 2] Center 34 (4~65) winsize 62
5350 09:31:07.381330 [CA 3] Center 34 (4~65) winsize 62
5351 09:31:07.384636 [CA 4] Center 33 (2~64) winsize 63
5352 09:31:07.387929 [CA 5] Center 33 (2~64) winsize 63
5353 09:31:07.388548
5354 09:31:07.390901 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5355 09:31:07.391372
5356 09:31:07.394166 [CATrainingPosCal] consider 1 rank data
5357 09:31:07.400126 u2DelayCellTimex100 = 270/100 ps
5358 09:31:07.401283 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5359 09:31:07.403989 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5360 09:31:07.407662 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5361 09:31:07.410848 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5362 09:31:07.414073 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5363 09:31:07.417335 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5364 09:31:07.420964
5365 09:31:07.423984 CA PerBit enable=1, Macro0, CA PI delay=33
5366 09:31:07.424462
5367 09:31:07.427251 [CBTSetCACLKResult] CA Dly = 33
5368 09:31:07.427673 CS Dly: 5 (0~36)
5369 09:31:07.428057 ==
5370 09:31:07.430802 Dram Type= 6, Freq= 0, CH_1, rank 1
5371 09:31:07.433949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5372 09:31:07.437813 ==
5373 09:31:07.440799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5374 09:31:07.447471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5375 09:31:07.451102 [CA 0] Center 37 (7~68) winsize 62
5376 09:31:07.454166 [CA 1] Center 37 (6~68) winsize 63
5377 09:31:07.457456 [CA 2] Center 34 (4~65) winsize 62
5378 09:31:07.460563 [CA 3] Center 34 (4~64) winsize 61
5379 09:31:07.463948 [CA 4] Center 33 (2~64) winsize 63
5380 09:31:07.467422 [CA 5] Center 32 (2~63) winsize 62
5381 09:31:07.467893
5382 09:31:07.470619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5383 09:31:07.471188
5384 09:31:07.473783 [CATrainingPosCal] consider 2 rank data
5385 09:31:07.477111 u2DelayCellTimex100 = 270/100 ps
5386 09:31:07.480300 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5387 09:31:07.483924 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5388 09:31:07.487590 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5389 09:31:07.490356 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5390 09:31:07.497143 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5391 09:31:07.500055 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5392 09:31:07.500577
5393 09:31:07.503642 CA PerBit enable=1, Macro0, CA PI delay=32
5394 09:31:07.504108
5395 09:31:07.507011 [CBTSetCACLKResult] CA Dly = 32
5396 09:31:07.507577 CS Dly: 5 (0~37)
5397 09:31:07.507951
5398 09:31:07.510044 ----->DramcWriteLeveling(PI) begin...
5399 09:31:07.510518 ==
5400 09:31:07.513489 Dram Type= 6, Freq= 0, CH_1, rank 0
5401 09:31:07.520205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5402 09:31:07.520677 ==
5403 09:31:07.523783 Write leveling (Byte 0): 25 => 25
5404 09:31:07.526871 Write leveling (Byte 1): 25 => 25
5405 09:31:07.527447 DramcWriteLeveling(PI) end<-----
5406 09:31:07.529964
5407 09:31:07.530426 ==
5408 09:31:07.533226 Dram Type= 6, Freq= 0, CH_1, rank 0
5409 09:31:07.536906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5410 09:31:07.537478 ==
5411 09:31:07.540013 [Gating] SW mode calibration
5412 09:31:07.546721 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5413 09:31:07.549779 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5414 09:31:07.556866 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 09:31:07.559949 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 09:31:07.563533 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 09:31:07.570180 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 09:31:07.573116 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5419 09:31:07.576560 0 10 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
5420 09:31:07.583042 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 09:31:07.586306 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 09:31:07.589524 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 09:31:07.596832 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 09:31:07.599763 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 09:31:07.603323 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 09:31:07.609718 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5427 09:31:07.612810 0 11 20 | B1->B0 | 2424 4343 | 0 1 | (0 0) (0 0)
5428 09:31:07.615983 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5429 09:31:07.623042 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 09:31:07.626301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 09:31:07.629379 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 09:31:07.636035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 09:31:07.639762 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 09:31:07.643053 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5435 09:31:07.649378 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 09:31:07.652767 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 09:31:07.656871 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 09:31:07.662965 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 09:31:07.666543 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 09:31:07.670053 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 09:31:07.676329 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 09:31:07.679586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 09:31:07.682960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 09:31:07.685914 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 09:31:07.692747 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 09:31:07.696270 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 09:31:07.699436 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 09:31:07.706158 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 09:31:07.709588 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 09:31:07.712383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 09:31:07.719331 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5452 09:31:07.722713 Total UI for P1: 0, mck2ui 16
5453 09:31:07.725600 best dqsien dly found for B0: ( 0, 14, 18)
5454 09:31:07.729173 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5455 09:31:07.732599 Total UI for P1: 0, mck2ui 16
5456 09:31:07.735972 best dqsien dly found for B1: ( 0, 14, 20)
5457 09:31:07.739323 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5458 09:31:07.742658 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5459 09:31:07.743247
5460 09:31:07.745513 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5461 09:31:07.749098 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5462 09:31:07.752824 [Gating] SW calibration Done
5463 09:31:07.753394 ==
5464 09:31:07.755795 Dram Type= 6, Freq= 0, CH_1, rank 0
5465 09:31:07.762568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5466 09:31:07.763142 ==
5467 09:31:07.763521 RX Vref Scan: 0
5468 09:31:07.763871
5469 09:31:07.765383 RX Vref 0 -> 0, step: 1
5470 09:31:07.765902
5471 09:31:07.768686 RX Delay -80 -> 252, step: 8
5472 09:31:07.772601 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5473 09:31:07.775565 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5474 09:31:07.779114 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5475 09:31:07.782292 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5476 09:31:07.788605 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5477 09:31:07.792219 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5478 09:31:07.795279 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5479 09:31:07.798923 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5480 09:31:07.802096 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5481 09:31:07.809012 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5482 09:31:07.811807 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5483 09:31:07.815827 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5484 09:31:07.818796 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5485 09:31:07.822357 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5486 09:31:07.825426 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5487 09:31:07.831923 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5488 09:31:07.832530 ==
5489 09:31:07.835395 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 09:31:07.838835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5491 09:31:07.839416 ==
5492 09:31:07.839796 DQS Delay:
5493 09:31:07.842445 DQS0 = 0, DQS1 = 0
5494 09:31:07.843043 DQM Delay:
5495 09:31:07.845191 DQM0 = 94, DQM1 = 88
5496 09:31:07.845661 DQ Delay:
5497 09:31:07.848702 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5498 09:31:07.852043 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5499 09:31:07.855183 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5500 09:31:07.858531 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5501 09:31:07.859004
5502 09:31:07.859376
5503 09:31:07.859718 ==
5504 09:31:07.862226 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 09:31:07.865385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 09:31:07.865862 ==
5507 09:31:07.868610
5508 09:31:07.869174
5509 09:31:07.869547 TX Vref Scan disable
5510 09:31:07.872169 == TX Byte 0 ==
5511 09:31:07.875622 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5512 09:31:07.878747 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5513 09:31:07.881761 == TX Byte 1 ==
5514 09:31:07.885127 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5515 09:31:07.888507 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5516 09:31:07.888980 ==
5517 09:31:07.891852 Dram Type= 6, Freq= 0, CH_1, rank 0
5518 09:31:07.898332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5519 09:31:07.898892 ==
5520 09:31:07.899268
5521 09:31:07.899614
5522 09:31:07.899952 TX Vref Scan disable
5523 09:31:07.902261 == TX Byte 0 ==
5524 09:31:07.906308 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5525 09:31:07.909261 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5526 09:31:07.912864 == TX Byte 1 ==
5527 09:31:07.916026 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5528 09:31:07.922387 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5529 09:31:07.922956
5530 09:31:07.923330 [DATLAT]
5531 09:31:07.923677 Freq=933, CH1 RK0
5532 09:31:07.924015
5533 09:31:07.926032 DATLAT Default: 0xd
5534 09:31:07.926627 0, 0xFFFF, sum = 0
5535 09:31:07.929048 1, 0xFFFF, sum = 0
5536 09:31:07.929527 2, 0xFFFF, sum = 0
5537 09:31:07.932568 3, 0xFFFF, sum = 0
5538 09:31:07.935661 4, 0xFFFF, sum = 0
5539 09:31:07.936274 5, 0xFFFF, sum = 0
5540 09:31:07.939176 6, 0xFFFF, sum = 0
5541 09:31:07.939775 7, 0xFFFF, sum = 0
5542 09:31:07.942426 8, 0xFFFF, sum = 0
5543 09:31:07.942905 9, 0xFFFF, sum = 0
5544 09:31:07.945443 10, 0x0, sum = 1
5545 09:31:07.945920 11, 0x0, sum = 2
5546 09:31:07.948659 12, 0x0, sum = 3
5547 09:31:07.949140 13, 0x0, sum = 4
5548 09:31:07.949521 best_step = 11
5549 09:31:07.949871
5550 09:31:07.952246 ==
5551 09:31:07.955580 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 09:31:07.958929 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5553 09:31:07.959501 ==
5554 09:31:07.959877 RX Vref Scan: 1
5555 09:31:07.960279
5556 09:31:07.962371 RX Vref 0 -> 0, step: 1
5557 09:31:07.962949
5558 09:31:07.965575 RX Delay -61 -> 252, step: 4
5559 09:31:07.966048
5560 09:31:07.969031 Set Vref, RX VrefLevel [Byte0]: 52
5561 09:31:07.972413 [Byte1]: 50
5562 09:31:07.972982
5563 09:31:07.975487 Final RX Vref Byte 0 = 52 to rank0
5564 09:31:07.978797 Final RX Vref Byte 1 = 50 to rank0
5565 09:31:07.981802 Final RX Vref Byte 0 = 52 to rank1
5566 09:31:07.985251 Final RX Vref Byte 1 = 50 to rank1==
5567 09:31:07.988625 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 09:31:07.991708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5569 09:31:07.995416 ==
5570 09:31:07.996004 DQS Delay:
5571 09:31:07.996445 DQS0 = 0, DQS1 = 0
5572 09:31:07.998621 DQM Delay:
5573 09:31:07.999189 DQM0 = 94, DQM1 = 88
5574 09:31:08.001748 DQ Delay:
5575 09:31:08.002218 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5576 09:31:08.005266 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =94
5577 09:31:08.008699 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5578 09:31:08.011863 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5579 09:31:08.015238
5580 09:31:08.015706
5581 09:31:08.021757 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5582 09:31:08.025224 CH1 RK0: MR19=505, MR18=3131
5583 09:31:08.031679 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5584 09:31:08.032155
5585 09:31:08.035173 ----->DramcWriteLeveling(PI) begin...
5586 09:31:08.035647 ==
5587 09:31:08.038647 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 09:31:08.041812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5589 09:31:08.042285 ==
5590 09:31:08.045516 Write leveling (Byte 0): 24 => 24
5591 09:31:08.048453 Write leveling (Byte 1): 24 => 24
5592 09:31:08.051697 DramcWriteLeveling(PI) end<-----
5593 09:31:08.052163
5594 09:31:08.052580 ==
5595 09:31:08.055161 Dram Type= 6, Freq= 0, CH_1, rank 1
5596 09:31:08.058617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5597 09:31:08.059192 ==
5598 09:31:08.061529 [Gating] SW mode calibration
5599 09:31:08.068047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5600 09:31:08.075219 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5601 09:31:08.078720 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 09:31:08.081484 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 09:31:08.087941 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 09:31:08.091381 0 10 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5605 09:31:08.095192 0 10 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
5606 09:31:08.101353 0 10 20 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
5607 09:31:08.104768 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 09:31:08.108084 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 09:31:08.115055 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 09:31:08.117864 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 09:31:08.121216 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 09:31:08.128048 0 11 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
5613 09:31:08.131676 0 11 16 | B1->B0 | 2726 3a3a | 1 1 | (0 0) (0 0)
5614 09:31:08.134837 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5615 09:31:08.142048 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 09:31:08.144681 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 09:31:08.148011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 09:31:08.154873 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 09:31:08.158327 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 09:31:08.161697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 09:31:08.168634 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5622 09:31:08.171689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5623 09:31:08.174735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 09:31:08.181033 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 09:31:08.184813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 09:31:08.187867 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 09:31:08.194711 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 09:31:08.197927 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 09:31:08.200910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 09:31:08.207788 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 09:31:08.211242 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 09:31:08.214608 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 09:31:08.217883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 09:31:08.224647 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:31:08.228236 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:31:08.231172 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:31:08.238174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5638 09:31:08.240866 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5639 09:31:08.244626 Total UI for P1: 0, mck2ui 16
5640 09:31:08.247565 best dqsien dly found for B0: ( 0, 14, 16)
5641 09:31:08.251015 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 09:31:08.254304 Total UI for P1: 0, mck2ui 16
5643 09:31:08.257748 best dqsien dly found for B1: ( 0, 14, 18)
5644 09:31:08.260740 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5645 09:31:08.267708 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5646 09:31:08.268336
5647 09:31:08.271029 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5648 09:31:08.274365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5649 09:31:08.277214 [Gating] SW calibration Done
5650 09:31:08.277691 ==
5651 09:31:08.281009 Dram Type= 6, Freq= 0, CH_1, rank 1
5652 09:31:08.284301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5653 09:31:08.284873 ==
5654 09:31:08.285260 RX Vref Scan: 0
5655 09:31:08.287674
5656 09:31:08.288313 RX Vref 0 -> 0, step: 1
5657 09:31:08.288707
5658 09:31:08.290658 RX Delay -80 -> 252, step: 8
5659 09:31:08.294553 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5660 09:31:08.297450 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5661 09:31:08.304086 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5662 09:31:08.307632 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5663 09:31:08.310502 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5664 09:31:08.314141 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5665 09:31:08.317374 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5666 09:31:08.323796 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5667 09:31:08.327213 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5668 09:31:08.330792 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5669 09:31:08.334002 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5670 09:31:08.336902 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5671 09:31:08.343815 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5672 09:31:08.347093 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5673 09:31:08.350467 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5674 09:31:08.353877 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5675 09:31:08.354456 ==
5676 09:31:08.356795 Dram Type= 6, Freq= 0, CH_1, rank 1
5677 09:31:08.360437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5678 09:31:08.363859 ==
5679 09:31:08.364471 DQS Delay:
5680 09:31:08.364856 DQS0 = 0, DQS1 = 0
5681 09:31:08.366633 DQM Delay:
5682 09:31:08.367108 DQM0 = 97, DQM1 = 87
5683 09:31:08.369987 DQ Delay:
5684 09:31:08.370461 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5685 09:31:08.373371 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5686 09:31:08.376861 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5687 09:31:08.383497 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5688 09:31:08.384070
5689 09:31:08.384491
5690 09:31:08.384846 ==
5691 09:31:08.386563 Dram Type= 6, Freq= 0, CH_1, rank 1
5692 09:31:08.390179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5693 09:31:08.390765 ==
5694 09:31:08.391145
5695 09:31:08.391489
5696 09:31:08.393683 TX Vref Scan disable
5697 09:31:08.394258 == TX Byte 0 ==
5698 09:31:08.400071 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5699 09:31:08.403280 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5700 09:31:08.403779 == TX Byte 1 ==
5701 09:31:08.410243 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5702 09:31:08.413353 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5703 09:31:08.413939 ==
5704 09:31:08.416743 Dram Type= 6, Freq= 0, CH_1, rank 1
5705 09:31:08.419687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5706 09:31:08.420233 ==
5707 09:31:08.420731
5708 09:31:08.421190
5709 09:31:08.423367 TX Vref Scan disable
5710 09:31:08.426733 == TX Byte 0 ==
5711 09:31:08.429635 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5712 09:31:08.432937 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5713 09:31:08.436119 == TX Byte 1 ==
5714 09:31:08.439916 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5715 09:31:08.442778 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5716 09:31:08.443263
5717 09:31:08.446193 [DATLAT]
5718 09:31:08.446672 Freq=933, CH1 RK1
5719 09:31:08.447158
5720 09:31:08.449773 DATLAT Default: 0xb
5721 09:31:08.450340 0, 0xFFFF, sum = 0
5722 09:31:08.452883 1, 0xFFFF, sum = 0
5723 09:31:08.453358 2, 0xFFFF, sum = 0
5724 09:31:08.456355 3, 0xFFFF, sum = 0
5725 09:31:08.456926 4, 0xFFFF, sum = 0
5726 09:31:08.459749 5, 0xFFFF, sum = 0
5727 09:31:08.460379 6, 0xFFFF, sum = 0
5728 09:31:08.462935 7, 0xFFFF, sum = 0
5729 09:31:08.463517 8, 0xFFFF, sum = 0
5730 09:31:08.465974 9, 0xFFFF, sum = 0
5731 09:31:08.466451 10, 0x0, sum = 1
5732 09:31:08.469168 11, 0x0, sum = 2
5733 09:31:08.469642 12, 0x0, sum = 3
5734 09:31:08.472738 13, 0x0, sum = 4
5735 09:31:08.473321 best_step = 11
5736 09:31:08.473696
5737 09:31:08.474043 ==
5738 09:31:08.476513 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 09:31:08.482742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5740 09:31:08.483320 ==
5741 09:31:08.483696 RX Vref Scan: 0
5742 09:31:08.484047
5743 09:31:08.486232 RX Vref 0 -> 0, step: 1
5744 09:31:08.486788
5745 09:31:08.489021 RX Delay -69 -> 252, step: 4
5746 09:31:08.492660 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5747 09:31:08.499141 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5748 09:31:08.502450 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5749 09:31:08.505759 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5750 09:31:08.509162 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5751 09:31:08.512725 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5752 09:31:08.515818 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5753 09:31:08.521986 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5754 09:31:08.525743 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5755 09:31:08.529067 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5756 09:31:08.532100 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5757 09:31:08.535438 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5758 09:31:08.542098 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5759 09:31:08.545585 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5760 09:31:08.548567 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5761 09:31:08.552068 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5762 09:31:08.552686 ==
5763 09:31:08.555167 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 09:31:08.559155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5765 09:31:08.559731 ==
5766 09:31:08.561846 DQS Delay:
5767 09:31:08.562315 DQS0 = 0, DQS1 = 0
5768 09:31:08.565515 DQM Delay:
5769 09:31:08.566087 DQM0 = 96, DQM1 = 87
5770 09:31:08.566472 DQ Delay:
5771 09:31:08.568956 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94
5772 09:31:08.572344 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5773 09:31:08.575421 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5774 09:31:08.578871 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5775 09:31:08.579444
5776 09:31:08.581744
5777 09:31:08.589058 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5778 09:31:08.592241 CH1 RK1: MR19=505, MR18=2424
5779 09:31:08.598849 CH1_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5780 09:31:08.599420 [RxdqsGatingPostProcess] freq 933
5781 09:31:08.605081 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5782 09:31:08.608809 Pre-setting of DQS Precalculation
5783 09:31:08.615470 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5784 09:31:08.621554 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5785 09:31:08.628448 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5786 09:31:08.629020
5787 09:31:08.629396
5788 09:31:08.631378 [Calibration Summary] 1866 Mbps
5789 09:31:08.631896 CH 0, Rank 0
5790 09:31:08.634734 SW Impedance : PASS
5791 09:31:08.637870 DUTY Scan : NO K
5792 09:31:08.638427 ZQ Calibration : PASS
5793 09:31:08.641432 Jitter Meter : NO K
5794 09:31:08.644813 CBT Training : PASS
5795 09:31:08.645289 Write leveling : PASS
5796 09:31:08.648147 RX DQS gating : PASS
5797 09:31:08.651244 RX DQ/DQS(RDDQC) : PASS
5798 09:31:08.651869 TX DQ/DQS : PASS
5799 09:31:08.655024 RX DATLAT : PASS
5800 09:31:08.655594 RX DQ/DQS(Engine): PASS
5801 09:31:08.658328 TX OE : NO K
5802 09:31:08.658907 All Pass.
5803 09:31:08.659286
5804 09:31:08.661295 CH 0, Rank 1
5805 09:31:08.661722 SW Impedance : PASS
5806 09:31:08.665103 DUTY Scan : NO K
5807 09:31:08.668478 ZQ Calibration : PASS
5808 09:31:08.669046 Jitter Meter : NO K
5809 09:31:08.671666 CBT Training : PASS
5810 09:31:08.674945 Write leveling : PASS
5811 09:31:08.675521 RX DQS gating : PASS
5812 09:31:08.678106 RX DQ/DQS(RDDQC) : PASS
5813 09:31:08.681335 TX DQ/DQS : PASS
5814 09:31:08.681921 RX DATLAT : PASS
5815 09:31:08.684853 RX DQ/DQS(Engine): PASS
5816 09:31:08.687710 TX OE : NO K
5817 09:31:08.688202 All Pass.
5818 09:31:08.688579
5819 09:31:08.688920 CH 1, Rank 0
5820 09:31:08.691280 SW Impedance : PASS
5821 09:31:08.694342 DUTY Scan : NO K
5822 09:31:08.694809 ZQ Calibration : PASS
5823 09:31:08.698246 Jitter Meter : NO K
5824 09:31:08.701186 CBT Training : PASS
5825 09:31:08.701762 Write leveling : PASS
5826 09:31:08.704499 RX DQS gating : PASS
5827 09:31:08.704963 RX DQ/DQS(RDDQC) : PASS
5828 09:31:08.707585 TX DQ/DQS : PASS
5829 09:31:08.711291 RX DATLAT : PASS
5830 09:31:08.711862 RX DQ/DQS(Engine): PASS
5831 09:31:08.714587 TX OE : NO K
5832 09:31:08.715159 All Pass.
5833 09:31:08.715532
5834 09:31:08.717653 CH 1, Rank 1
5835 09:31:08.718119 SW Impedance : PASS
5836 09:31:08.721050 DUTY Scan : NO K
5837 09:31:08.724351 ZQ Calibration : PASS
5838 09:31:08.724819 Jitter Meter : NO K
5839 09:31:08.727962 CBT Training : PASS
5840 09:31:08.730866 Write leveling : PASS
5841 09:31:08.731437 RX DQS gating : PASS
5842 09:31:08.734573 RX DQ/DQS(RDDQC) : PASS
5843 09:31:08.737539 TX DQ/DQS : PASS
5844 09:31:08.738140 RX DATLAT : PASS
5845 09:31:08.740631 RX DQ/DQS(Engine): PASS
5846 09:31:08.744250 TX OE : NO K
5847 09:31:08.744844 All Pass.
5848 09:31:08.745221
5849 09:31:08.747468 DramC Write-DBI off
5850 09:31:08.748033 PER_BANK_REFRESH: Hybrid Mode
5851 09:31:08.750635 TX_TRACKING: ON
5852 09:31:08.757687 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5853 09:31:08.764000 [FAST_K] Save calibration result to emmc
5854 09:31:08.767536 dramc_set_vcore_voltage set vcore to 650000
5855 09:31:08.768105 Read voltage for 400, 6
5856 09:31:08.770599 Vio18 = 0
5857 09:31:08.771063 Vcore = 650000
5858 09:31:08.771433 Vdram = 0
5859 09:31:08.774199 Vddq = 0
5860 09:31:08.774768 Vmddr = 0
5861 09:31:08.777432 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5862 09:31:08.784144 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5863 09:31:08.787252 MEM_TYPE=3, freq_sel=20
5864 09:31:08.790706 sv_algorithm_assistance_LP4_800
5865 09:31:08.793721 ============ PULL DRAM RESETB DOWN ============
5866 09:31:08.797171 ========== PULL DRAM RESETB DOWN end =========
5867 09:31:08.803908 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5868 09:31:08.804533 ===================================
5869 09:31:08.807336 LPDDR4 DRAM CONFIGURATION
5870 09:31:08.810421 ===================================
5871 09:31:08.813745 EX_ROW_EN[0] = 0x0
5872 09:31:08.814326 EX_ROW_EN[1] = 0x0
5873 09:31:08.817130 LP4Y_EN = 0x0
5874 09:31:08.817700 WORK_FSP = 0x0
5875 09:31:08.820339 WL = 0x2
5876 09:31:08.820971 RL = 0x2
5877 09:31:08.823506 BL = 0x2
5878 09:31:08.827003 RPST = 0x0
5879 09:31:08.827571 RD_PRE = 0x0
5880 09:31:08.830175 WR_PRE = 0x1
5881 09:31:08.830748 WR_PST = 0x0
5882 09:31:08.833195 DBI_WR = 0x0
5883 09:31:08.833668 DBI_RD = 0x0
5884 09:31:08.836691 OTF = 0x1
5885 09:31:08.839833 ===================================
5886 09:31:08.843539 ===================================
5887 09:31:08.844110 ANA top config
5888 09:31:08.846793 ===================================
5889 09:31:08.850002 DLL_ASYNC_EN = 0
5890 09:31:08.853400 ALL_SLAVE_EN = 1
5891 09:31:08.853979 NEW_RANK_MODE = 1
5892 09:31:08.856453 DLL_IDLE_MODE = 1
5893 09:31:08.859896 LP45_APHY_COMB_EN = 1
5894 09:31:08.863209 TX_ODT_DIS = 1
5895 09:31:08.866389 NEW_8X_MODE = 1
5896 09:31:08.869711 ===================================
5897 09:31:08.872949 ===================================
5898 09:31:08.873616 data_rate = 800
5899 09:31:08.876342 CKR = 1
5900 09:31:08.879593 DQ_P2S_RATIO = 4
5901 09:31:08.882798 ===================================
5902 09:31:08.886281 CA_P2S_RATIO = 4
5903 09:31:08.889863 DQ_CA_OPEN = 0
5904 09:31:08.893003 DQ_SEMI_OPEN = 1
5905 09:31:08.893572 CA_SEMI_OPEN = 1
5906 09:31:08.896431 CA_FULL_RATE = 0
5907 09:31:08.899539 DQ_CKDIV4_EN = 0
5908 09:31:08.902868 CA_CKDIV4_EN = 1
5909 09:31:08.906386 CA_PREDIV_EN = 0
5910 09:31:08.909490 PH8_DLY = 0
5911 09:31:08.910010 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5912 09:31:08.912843 DQ_AAMCK_DIV = 0
5913 09:31:08.916094 CA_AAMCK_DIV = 0
5914 09:31:08.919819 CA_ADMCK_DIV = 4
5915 09:31:08.922871 DQ_TRACK_CA_EN = 0
5916 09:31:08.926272 CA_PICK = 800
5917 09:31:08.929600 CA_MCKIO = 400
5918 09:31:08.930173 MCKIO_SEMI = 400
5919 09:31:08.932560 PLL_FREQ = 3016
5920 09:31:08.935719 DQ_UI_PI_RATIO = 32
5921 09:31:08.939291 CA_UI_PI_RATIO = 32
5922 09:31:08.942378 ===================================
5923 09:31:08.945894 ===================================
5924 09:31:08.949275 memory_type:LPDDR4
5925 09:31:08.949845 GP_NUM : 10
5926 09:31:08.952686 SRAM_EN : 1
5927 09:31:08.955575 MD32_EN : 0
5928 09:31:08.959109 ===================================
5929 09:31:08.959684 [ANA_INIT] >>>>>>>>>>>>>>
5930 09:31:08.962257 <<<<<< [CONFIGURE PHASE]: ANA_TX
5931 09:31:08.965589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5932 09:31:08.969380 ===================================
5933 09:31:08.972389 data_rate = 800,PCW = 0X7400
5934 09:31:08.975788 ===================================
5935 09:31:08.978785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5936 09:31:08.985465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5937 09:31:08.995339 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5938 09:31:09.002730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5939 09:31:09.005263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5940 09:31:09.008905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5941 09:31:09.009479 [ANA_INIT] flow start
5942 09:31:09.012087 [ANA_INIT] PLL >>>>>>>>
5943 09:31:09.015324 [ANA_INIT] PLL <<<<<<<<
5944 09:31:09.015793 [ANA_INIT] MIDPI >>>>>>>>
5945 09:31:09.018361 [ANA_INIT] MIDPI <<<<<<<<
5946 09:31:09.022062 [ANA_INIT] DLL >>>>>>>>
5947 09:31:09.022632 [ANA_INIT] flow end
5948 09:31:09.028623 ============ LP4 DIFF to SE enter ============
5949 09:31:09.031692 ============ LP4 DIFF to SE exit ============
5950 09:31:09.032166 [ANA_INIT] <<<<<<<<<<<<<
5951 09:31:09.035563 [Flow] Enable top DCM control >>>>>
5952 09:31:09.038573 [Flow] Enable top DCM control <<<<<
5953 09:31:09.041769 Enable DLL master slave shuffle
5954 09:31:09.048570 ==============================================================
5955 09:31:09.051625 Gating Mode config
5956 09:31:09.054934 ==============================================================
5957 09:31:09.058375 Config description:
5958 09:31:09.068450 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5959 09:31:09.075022 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5960 09:31:09.078196 SELPH_MODE 0: By rank 1: By Phase
5961 09:31:09.084808 ==============================================================
5962 09:31:09.087903 GAT_TRACK_EN = 0
5963 09:31:09.091898 RX_GATING_MODE = 2
5964 09:31:09.094614 RX_GATING_TRACK_MODE = 2
5965 09:31:09.097780 SELPH_MODE = 1
5966 09:31:09.098254 PICG_EARLY_EN = 1
5967 09:31:09.101333 VALID_LAT_VALUE = 1
5968 09:31:09.108295 ==============================================================
5969 09:31:09.111409 Enter into Gating configuration >>>>
5970 09:31:09.115066 Exit from Gating configuration <<<<
5971 09:31:09.117924 Enter into DVFS_PRE_config >>>>>
5972 09:31:09.128069 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5973 09:31:09.131138 Exit from DVFS_PRE_config <<<<<
5974 09:31:09.134727 Enter into PICG configuration >>>>
5975 09:31:09.137973 Exit from PICG configuration <<<<
5976 09:31:09.141067 [RX_INPUT] configuration >>>>>
5977 09:31:09.144227 [RX_INPUT] configuration <<<<<
5978 09:31:09.147924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5979 09:31:09.154637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5980 09:31:09.161321 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5981 09:31:09.167802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5982 09:31:09.174859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5983 09:31:09.177453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5984 09:31:09.184377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5985 09:31:09.187406 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5986 09:31:09.190607 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5987 09:31:09.193935 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5988 09:31:09.200604 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5989 09:31:09.204118 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5990 09:31:09.207102 ===================================
5991 09:31:09.210770 LPDDR4 DRAM CONFIGURATION
5992 09:31:09.213958 ===================================
5993 09:31:09.214624 EX_ROW_EN[0] = 0x0
5994 09:31:09.217167 EX_ROW_EN[1] = 0x0
5995 09:31:09.217637 LP4Y_EN = 0x0
5996 09:31:09.220809 WORK_FSP = 0x0
5997 09:31:09.221377 WL = 0x2
5998 09:31:09.223865 RL = 0x2
5999 09:31:09.227179 BL = 0x2
6000 09:31:09.227750 RPST = 0x0
6001 09:31:09.230549 RD_PRE = 0x0
6002 09:31:09.231117 WR_PRE = 0x1
6003 09:31:09.233650 WR_PST = 0x0
6004 09:31:09.234120 DBI_WR = 0x0
6005 09:31:09.237452 DBI_RD = 0x0
6006 09:31:09.237921 OTF = 0x1
6007 09:31:09.240477 ===================================
6008 09:31:09.243506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6009 09:31:09.249960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6010 09:31:09.253875 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6011 09:31:09.256920 ===================================
6012 09:31:09.260213 LPDDR4 DRAM CONFIGURATION
6013 09:31:09.263229 ===================================
6014 09:31:09.263702 EX_ROW_EN[0] = 0x10
6015 09:31:09.266619 EX_ROW_EN[1] = 0x0
6016 09:31:09.267200 LP4Y_EN = 0x0
6017 09:31:09.270472 WORK_FSP = 0x0
6018 09:31:09.271109 WL = 0x2
6019 09:31:09.273602 RL = 0x2
6020 09:31:09.274184 BL = 0x2
6021 09:31:09.276729 RPST = 0x0
6022 09:31:09.280278 RD_PRE = 0x0
6023 09:31:09.280753 WR_PRE = 0x1
6024 09:31:09.283506 WR_PST = 0x0
6025 09:31:09.283985 DBI_WR = 0x0
6026 09:31:09.286907 DBI_RD = 0x0
6027 09:31:09.287375 OTF = 0x1
6028 09:31:09.290224 ===================================
6029 09:31:09.296338 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6030 09:31:09.300444 nWR fixed to 30
6031 09:31:09.303909 [ModeRegInit_LP4] CH0 RK0
6032 09:31:09.304539 [ModeRegInit_LP4] CH0 RK1
6033 09:31:09.306911 [ModeRegInit_LP4] CH1 RK0
6034 09:31:09.310609 [ModeRegInit_LP4] CH1 RK1
6035 09:31:09.311198 match AC timing 18
6036 09:31:09.316887 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6037 09:31:09.320330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6038 09:31:09.323340 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6039 09:31:09.329978 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6040 09:31:09.333326 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6041 09:31:09.333909 ==
6042 09:31:09.336838 Dram Type= 6, Freq= 0, CH_0, rank 0
6043 09:31:09.340027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6044 09:31:09.340547 ==
6045 09:31:09.346685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6046 09:31:09.353259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6047 09:31:09.356819 [CA 0] Center 36 (8~64) winsize 57
6048 09:31:09.360329 [CA 1] Center 36 (8~64) winsize 57
6049 09:31:09.363091 [CA 2] Center 36 (8~64) winsize 57
6050 09:31:09.366902 [CA 3] Center 36 (8~64) winsize 57
6051 09:31:09.367477 [CA 4] Center 36 (8~64) winsize 57
6052 09:31:09.369945 [CA 5] Center 36 (8~64) winsize 57
6053 09:31:09.370519
6054 09:31:09.376463 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6055 09:31:09.377037
6056 09:31:09.380046 [CATrainingPosCal] consider 1 rank data
6057 09:31:09.383251 u2DelayCellTimex100 = 270/100 ps
6058 09:31:09.386568 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 09:31:09.389839 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6060 09:31:09.393266 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 09:31:09.396911 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 09:31:09.399813 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 09:31:09.403177 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 09:31:09.403747
6065 09:31:09.406427 CA PerBit enable=1, Macro0, CA PI delay=36
6066 09:31:09.406896
6067 09:31:09.410106 [CBTSetCACLKResult] CA Dly = 36
6068 09:31:09.413103 CS Dly: 1 (0~32)
6069 09:31:09.413572 ==
6070 09:31:09.416387 Dram Type= 6, Freq= 0, CH_0, rank 1
6071 09:31:09.419602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6072 09:31:09.420211 ==
6073 09:31:09.426456 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6074 09:31:09.429645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6075 09:31:09.433014 [CA 0] Center 36 (8~64) winsize 57
6076 09:31:09.436145 [CA 1] Center 36 (8~64) winsize 57
6077 09:31:09.439461 [CA 2] Center 36 (8~64) winsize 57
6078 09:31:09.443221 [CA 3] Center 36 (8~64) winsize 57
6079 09:31:09.446652 [CA 4] Center 36 (8~64) winsize 57
6080 09:31:09.449432 [CA 5] Center 36 (8~64) winsize 57
6081 09:31:09.449907
6082 09:31:09.452849 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6083 09:31:09.453319
6084 09:31:09.456227 [CATrainingPosCal] consider 2 rank data
6085 09:31:09.459756 u2DelayCellTimex100 = 270/100 ps
6086 09:31:09.462960 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6087 09:31:09.466242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6088 09:31:09.472794 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 09:31:09.476003 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 09:31:09.479474 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 09:31:09.482581 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 09:31:09.483148
6093 09:31:09.486476 CA PerBit enable=1, Macro0, CA PI delay=36
6094 09:31:09.487049
6095 09:31:09.489326 [CBTSetCACLKResult] CA Dly = 36
6096 09:31:09.489797 CS Dly: 1 (0~32)
6097 09:31:09.490170
6098 09:31:09.492945 ----->DramcWriteLeveling(PI) begin...
6099 09:31:09.495893 ==
6100 09:31:09.499296 Dram Type= 6, Freq= 0, CH_0, rank 0
6101 09:31:09.502760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6102 09:31:09.503334 ==
6103 09:31:09.505739 Write leveling (Byte 0): 32 => 0
6104 09:31:09.509527 Write leveling (Byte 1): 32 => 0
6105 09:31:09.512376 DramcWriteLeveling(PI) end<-----
6106 09:31:09.512852
6107 09:31:09.513225 ==
6108 09:31:09.516014 Dram Type= 6, Freq= 0, CH_0, rank 0
6109 09:31:09.519358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6110 09:31:09.519951 ==
6111 09:31:09.522765 [Gating] SW mode calibration
6112 09:31:09.529340 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6113 09:31:09.532209 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6114 09:31:09.538946 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6115 09:31:09.542406 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6116 09:31:09.545650 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6117 09:31:09.552159 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6118 09:31:09.555746 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6119 09:31:09.558958 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6120 09:31:09.566043 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6121 09:31:09.568937 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6122 09:31:09.572609 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6123 09:31:09.575533 Total UI for P1: 0, mck2ui 16
6124 09:31:09.578884 best dqsien dly found for B0: ( 0, 10, 16)
6125 09:31:09.581932 Total UI for P1: 0, mck2ui 16
6126 09:31:09.585760 best dqsien dly found for B1: ( 0, 10, 24)
6127 09:31:09.588808 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6128 09:31:09.595388 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6129 09:31:09.595949
6130 09:31:09.598623 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6131 09:31:09.601689 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6132 09:31:09.605457 [Gating] SW calibration Done
6133 09:31:09.606032 ==
6134 09:31:09.608622 Dram Type= 6, Freq= 0, CH_0, rank 0
6135 09:31:09.612097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6136 09:31:09.612709 ==
6137 09:31:09.615682 RX Vref Scan: 0
6138 09:31:09.616288
6139 09:31:09.616733 RX Vref 0 -> 0, step: 1
6140 09:31:09.617096
6141 09:31:09.618734 RX Delay -410 -> 252, step: 16
6142 09:31:09.621805 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6143 09:31:09.628436 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6144 09:31:09.631997 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6145 09:31:09.635191 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6146 09:31:09.638247 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6147 09:31:09.645037 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6148 09:31:09.648445 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6149 09:31:09.651384 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6150 09:31:09.655136 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6151 09:31:09.661457 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6152 09:31:09.664874 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6153 09:31:09.668136 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6154 09:31:09.675103 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6155 09:31:09.678155 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6156 09:31:09.681690 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6157 09:31:09.684778 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6158 09:31:09.685355 ==
6159 09:31:09.688396 Dram Type= 6, Freq= 0, CH_0, rank 0
6160 09:31:09.695018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6161 09:31:09.695607 ==
6162 09:31:09.695989 DQS Delay:
6163 09:31:09.698419 DQS0 = 51, DQS1 = 59
6164 09:31:09.698988 DQM Delay:
6165 09:31:09.701318 DQM0 = 12, DQM1 = 13
6166 09:31:09.701786 DQ Delay:
6167 09:31:09.705209 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6168 09:31:09.708418 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6169 09:31:09.708999 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6170 09:31:09.714867 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6171 09:31:09.715439
6172 09:31:09.715816
6173 09:31:09.716161 ==
6174 09:31:09.717898 Dram Type= 6, Freq= 0, CH_0, rank 0
6175 09:31:09.721131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 09:31:09.721703 ==
6177 09:31:09.722077
6178 09:31:09.722417
6179 09:31:09.725089 TX Vref Scan disable
6180 09:31:09.725657 == TX Byte 0 ==
6181 09:31:09.731210 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6182 09:31:09.734146 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6183 09:31:09.734622 == TX Byte 1 ==
6184 09:31:09.741002 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6185 09:31:09.744370 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6186 09:31:09.744841 ==
6187 09:31:09.747595 Dram Type= 6, Freq= 0, CH_0, rank 0
6188 09:31:09.751013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6189 09:31:09.751675 ==
6190 09:31:09.752064
6191 09:31:09.752497
6192 09:31:09.754645 TX Vref Scan disable
6193 09:31:09.755220 == TX Byte 0 ==
6194 09:31:09.760692 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6195 09:31:09.764038 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6196 09:31:09.764571 == TX Byte 1 ==
6197 09:31:09.770824 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6198 09:31:09.774265 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6199 09:31:09.774848
6200 09:31:09.775224 [DATLAT]
6201 09:31:09.777687 Freq=400, CH0 RK0
6202 09:31:09.778162
6203 09:31:09.778536 DATLAT Default: 0xf
6204 09:31:09.781065 0, 0xFFFF, sum = 0
6205 09:31:09.781681 1, 0xFFFF, sum = 0
6206 09:31:09.784347 2, 0xFFFF, sum = 0
6207 09:31:09.787583 3, 0xFFFF, sum = 0
6208 09:31:09.788161 4, 0xFFFF, sum = 0
6209 09:31:09.790776 5, 0xFFFF, sum = 0
6210 09:31:09.791255 6, 0xFFFF, sum = 0
6211 09:31:09.793910 7, 0xFFFF, sum = 0
6212 09:31:09.794391 8, 0xFFFF, sum = 0
6213 09:31:09.797400 9, 0xFFFF, sum = 0
6214 09:31:09.797975 10, 0xFFFF, sum = 0
6215 09:31:09.800629 11, 0xFFFF, sum = 0
6216 09:31:09.801209 12, 0x0, sum = 1
6217 09:31:09.803837 13, 0x0, sum = 2
6218 09:31:09.804365 14, 0x0, sum = 3
6219 09:31:09.807263 15, 0x0, sum = 4
6220 09:31:09.807845 best_step = 13
6221 09:31:09.808255
6222 09:31:09.808608 ==
6223 09:31:09.810867 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 09:31:09.813949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6225 09:31:09.814526 ==
6226 09:31:09.817257 RX Vref Scan: 1
6227 09:31:09.817726
6228 09:31:09.820600 RX Vref 0 -> 0, step: 1
6229 09:31:09.821172
6230 09:31:09.821554 RX Delay -359 -> 252, step: 8
6231 09:31:09.824223
6232 09:31:09.824798 Set Vref, RX VrefLevel [Byte0]: 51
6233 09:31:09.827038 [Byte1]: 48
6234 09:31:09.832740
6235 09:31:09.833206 Final RX Vref Byte 0 = 51 to rank0
6236 09:31:09.836035 Final RX Vref Byte 1 = 48 to rank0
6237 09:31:09.839587 Final RX Vref Byte 0 = 51 to rank1
6238 09:31:09.842476 Final RX Vref Byte 1 = 48 to rank1==
6239 09:31:09.845996 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 09:31:09.852749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6241 09:31:09.853306 ==
6242 09:31:09.853683 DQS Delay:
6243 09:31:09.856053 DQS0 = 52, DQS1 = 68
6244 09:31:09.856559 DQM Delay:
6245 09:31:09.856933 DQM0 = 8, DQM1 = 16
6246 09:31:09.859326 DQ Delay:
6247 09:31:09.862552 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6248 09:31:09.863024 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6249 09:31:09.865824 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6250 09:31:09.869421 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6251 09:31:09.869892
6252 09:31:09.870264
6253 09:31:09.879098 [DQSOSCAuto] RK0, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6254 09:31:09.882768 CH0 RK0: MR19=C0C, MR18=A6A6
6255 09:31:09.889149 CH0_RK0: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6256 09:31:09.889727 ==
6257 09:31:09.892480 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 09:31:09.895929 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6259 09:31:09.896546 ==
6260 09:31:09.898780 [Gating] SW mode calibration
6261 09:31:09.905617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6262 09:31:09.912571 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6263 09:31:09.915715 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 09:31:09.919073 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 09:31:09.922682 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 09:31:09.929586 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6267 09:31:09.932357 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 09:31:09.935617 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 09:31:09.942124 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 09:31:09.945436 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6271 09:31:09.948562 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 09:31:09.951926 Total UI for P1: 0, mck2ui 16
6273 09:31:09.955426 best dqsien dly found for B0: ( 0, 10, 16)
6274 09:31:09.958631 Total UI for P1: 0, mck2ui 16
6275 09:31:09.961932 best dqsien dly found for B1: ( 0, 10, 16)
6276 09:31:09.965211 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6277 09:31:09.971855 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6278 09:31:09.972460
6279 09:31:09.975252 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6280 09:31:09.978764 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6281 09:31:09.981929 [Gating] SW calibration Done
6282 09:31:09.982502 ==
6283 09:31:09.985182 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 09:31:09.988850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6285 09:31:09.989433 ==
6286 09:31:09.992122 RX Vref Scan: 0
6287 09:31:09.992738
6288 09:31:09.993114 RX Vref 0 -> 0, step: 1
6289 09:31:09.993465
6290 09:31:09.995488 RX Delay -410 -> 252, step: 16
6291 09:31:09.998508 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6292 09:31:10.005381 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6293 09:31:10.008552 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6294 09:31:10.012110 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6295 09:31:10.015415 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6296 09:31:10.021853 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6297 09:31:10.025136 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6298 09:31:10.028896 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6299 09:31:10.031421 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6300 09:31:10.038874 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6301 09:31:10.041300 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6302 09:31:10.044908 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6303 09:31:10.048408 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6304 09:31:10.055243 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6305 09:31:10.058428 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6306 09:31:10.061610 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6307 09:31:10.062234 ==
6308 09:31:10.064654 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 09:31:10.071617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6310 09:31:10.072245 ==
6311 09:31:10.072639 DQS Delay:
6312 09:31:10.074576 DQS0 = 43, DQS1 = 59
6313 09:31:10.075042 DQM Delay:
6314 09:31:10.075409 DQM0 = 6, DQM1 = 15
6315 09:31:10.078192 DQ Delay:
6316 09:31:10.081386 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6317 09:31:10.081953 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6318 09:31:10.084611 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6319 09:31:10.088319 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6320 09:31:10.088905
6321 09:31:10.091283
6322 09:31:10.091754 ==
6323 09:31:10.095065 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 09:31:10.097984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6325 09:31:10.098457 ==
6326 09:31:10.098832
6327 09:31:10.099181
6328 09:31:10.101652 TX Vref Scan disable
6329 09:31:10.102221 == TX Byte 0 ==
6330 09:31:10.104921 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6331 09:31:10.111962 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6332 09:31:10.112585 == TX Byte 1 ==
6333 09:31:10.114680 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6334 09:31:10.121278 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6335 09:31:10.121847 ==
6336 09:31:10.124898 Dram Type= 6, Freq= 0, CH_0, rank 1
6337 09:31:10.128441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6338 09:31:10.129008 ==
6339 09:31:10.129385
6340 09:31:10.129733
6341 09:31:10.131375 TX Vref Scan disable
6342 09:31:10.131843 == TX Byte 0 ==
6343 09:31:10.134703 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6344 09:31:10.141195 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6345 09:31:10.141766 == TX Byte 1 ==
6346 09:31:10.144900 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6347 09:31:10.151278 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6348 09:31:10.151851
6349 09:31:10.152353 [DATLAT]
6350 09:31:10.152732 Freq=400, CH0 RK1
6351 09:31:10.153078
6352 09:31:10.154254 DATLAT Default: 0xd
6353 09:31:10.157599 0, 0xFFFF, sum = 0
6354 09:31:10.158113 1, 0xFFFF, sum = 0
6355 09:31:10.160931 2, 0xFFFF, sum = 0
6356 09:31:10.161409 3, 0xFFFF, sum = 0
6357 09:31:10.164131 4, 0xFFFF, sum = 0
6358 09:31:10.164640 5, 0xFFFF, sum = 0
6359 09:31:10.167672 6, 0xFFFF, sum = 0
6360 09:31:10.168145 7, 0xFFFF, sum = 0
6361 09:31:10.170852 8, 0xFFFF, sum = 0
6362 09:31:10.171326 9, 0xFFFF, sum = 0
6363 09:31:10.173959 10, 0xFFFF, sum = 0
6364 09:31:10.174551 11, 0xFFFF, sum = 0
6365 09:31:10.177544 12, 0x0, sum = 1
6366 09:31:10.178014 13, 0x0, sum = 2
6367 09:31:10.180683 14, 0x0, sum = 3
6368 09:31:10.181154 15, 0x0, sum = 4
6369 09:31:10.184019 best_step = 13
6370 09:31:10.184526
6371 09:31:10.184900 ==
6372 09:31:10.187359 Dram Type= 6, Freq= 0, CH_0, rank 1
6373 09:31:10.190899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6374 09:31:10.191371 ==
6375 09:31:10.191739 RX Vref Scan: 0
6376 09:31:10.194365
6377 09:31:10.194924 RX Vref 0 -> 0, step: 1
6378 09:31:10.195298
6379 09:31:10.197503 RX Delay -359 -> 252, step: 8
6380 09:31:10.205193 iDelay=225, Bit 0, Center -44 (-295 ~ 208) 504
6381 09:31:10.208568 iDelay=225, Bit 1, Center -40 (-295 ~ 216) 512
6382 09:31:10.211923 iDelay=225, Bit 2, Center -44 (-295 ~ 208) 504
6383 09:31:10.215003 iDelay=225, Bit 3, Center -48 (-295 ~ 200) 496
6384 09:31:10.221854 iDelay=225, Bit 4, Center -36 (-287 ~ 216) 504
6385 09:31:10.225013 iDelay=225, Bit 5, Center -52 (-303 ~ 200) 504
6386 09:31:10.228419 iDelay=225, Bit 6, Center -36 (-287 ~ 216) 504
6387 09:31:10.231378 iDelay=225, Bit 7, Center -28 (-279 ~ 224) 504
6388 09:31:10.237804 iDelay=225, Bit 8, Center -60 (-303 ~ 184) 488
6389 09:31:10.241840 iDelay=225, Bit 9, Center -60 (-303 ~ 184) 488
6390 09:31:10.244746 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6391 09:31:10.251855 iDelay=225, Bit 11, Center -60 (-303 ~ 184) 488
6392 09:31:10.254515 iDelay=225, Bit 12, Center -44 (-287 ~ 200) 488
6393 09:31:10.258392 iDelay=225, Bit 13, Center -48 (-295 ~ 200) 496
6394 09:31:10.261103 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6395 09:31:10.268132 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6396 09:31:10.268763 ==
6397 09:31:10.270870 Dram Type= 6, Freq= 0, CH_0, rank 1
6398 09:31:10.274410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6399 09:31:10.274893 ==
6400 09:31:10.275274 DQS Delay:
6401 09:31:10.277974 DQS0 = 52, DQS1 = 60
6402 09:31:10.278559 DQM Delay:
6403 09:31:10.281316 DQM0 = 11, DQM1 = 10
6404 09:31:10.281889 DQ Delay:
6405 09:31:10.284407 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6406 09:31:10.287568 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6407 09:31:10.290978 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6408 09:31:10.294540 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6409 09:31:10.295117
6410 09:31:10.295491
6411 09:31:10.300806 [DQSOSCAuto] RK1, (LSB)MR18= 0xcaca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6412 09:31:10.304400 CH0 RK1: MR19=C0C, MR18=CACA
6413 09:31:10.311137 CH0_RK1: MR19=0xC0C, MR18=0xCACA, DQSOSC=384, MR23=63, INC=400, DEC=267
6414 09:31:10.314316 [RxdqsGatingPostProcess] freq 400
6415 09:31:10.321182 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6416 09:31:10.324815 Pre-setting of DQS Precalculation
6417 09:31:10.327810 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6418 09:31:10.328411 ==
6419 09:31:10.330787 Dram Type= 6, Freq= 0, CH_1, rank 0
6420 09:31:10.333997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6421 09:31:10.334464 ==
6422 09:31:10.340946 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6423 09:31:10.347656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6424 09:31:10.351494 [CA 0] Center 36 (8~64) winsize 57
6425 09:31:10.354306 [CA 1] Center 36 (8~64) winsize 57
6426 09:31:10.357670 [CA 2] Center 36 (8~64) winsize 57
6427 09:31:10.360871 [CA 3] Center 36 (8~64) winsize 57
6428 09:31:10.361444 [CA 4] Center 36 (8~64) winsize 57
6429 09:31:10.364400 [CA 5] Center 36 (8~64) winsize 57
6430 09:31:10.364974
6431 09:31:10.371256 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6432 09:31:10.371830
6433 09:31:10.374291 [CATrainingPosCal] consider 1 rank data
6434 09:31:10.377572 u2DelayCellTimex100 = 270/100 ps
6435 09:31:10.380887 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6436 09:31:10.384467 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6437 09:31:10.387394 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 09:31:10.391215 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 09:31:10.393870 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 09:31:10.397238 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 09:31:10.397801
6442 09:31:10.400522 CA PerBit enable=1, Macro0, CA PI delay=36
6443 09:31:10.400990
6444 09:31:10.404018 [CBTSetCACLKResult] CA Dly = 36
6445 09:31:10.406944 CS Dly: 1 (0~32)
6446 09:31:10.407469 ==
6447 09:31:10.410772 Dram Type= 6, Freq= 0, CH_1, rank 1
6448 09:31:10.413966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6449 09:31:10.414544 ==
6450 09:31:10.420614 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6451 09:31:10.427215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6452 09:31:10.430741 [CA 0] Center 36 (8~64) winsize 57
6453 09:31:10.431302 [CA 1] Center 36 (8~64) winsize 57
6454 09:31:10.433805 [CA 2] Center 36 (8~64) winsize 57
6455 09:31:10.437390 [CA 3] Center 36 (8~64) winsize 57
6456 09:31:10.440510 [CA 4] Center 32 (8~56) winsize 49
6457 09:31:10.444056 [CA 5] Center 36 (8~64) winsize 57
6458 09:31:10.444690
6459 09:31:10.447204 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6460 09:31:10.447770
6461 09:31:10.450316 [CATrainingPosCal] consider 2 rank data
6462 09:31:10.453522 u2DelayCellTimex100 = 270/100 ps
6463 09:31:10.457128 CA0 delay=36 (8~64),Diff = 4 PI (57 cell)
6464 09:31:10.463891 CA1 delay=36 (8~64),Diff = 4 PI (57 cell)
6465 09:31:10.467116 CA2 delay=36 (8~64),Diff = 4 PI (57 cell)
6466 09:31:10.470770 CA3 delay=36 (8~64),Diff = 4 PI (57 cell)
6467 09:31:10.473784 CA4 delay=32 (8~56),Diff = 0 PI (0 cell)
6468 09:31:10.477135 CA5 delay=36 (8~64),Diff = 4 PI (57 cell)
6469 09:31:10.477703
6470 09:31:10.480325 CA PerBit enable=1, Macro0, CA PI delay=32
6471 09:31:10.480905
6472 09:31:10.484003 [CBTSetCACLKResult] CA Dly = 32
6473 09:31:10.486953 CS Dly: 1 (0~32)
6474 09:31:10.487520
6475 09:31:10.490065 ----->DramcWriteLeveling(PI) begin...
6476 09:31:10.490537 ==
6477 09:31:10.493464 Dram Type= 6, Freq= 0, CH_1, rank 0
6478 09:31:10.496684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6479 09:31:10.497207 ==
6480 09:31:10.499989 Write leveling (Byte 0): 32 => 0
6481 09:31:10.503714 Write leveling (Byte 1): 32 => 0
6482 09:31:10.506964 DramcWriteLeveling(PI) end<-----
6483 09:31:10.507531
6484 09:31:10.507905 ==
6485 09:31:10.510224 Dram Type= 6, Freq= 0, CH_1, rank 0
6486 09:31:10.513189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6487 09:31:10.513663 ==
6488 09:31:10.517011 [Gating] SW mode calibration
6489 09:31:10.523524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6490 09:31:10.530061 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6491 09:31:10.533127 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 09:31:10.536673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6493 09:31:10.543208 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 09:31:10.546646 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6495 09:31:10.549874 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 09:31:10.556650 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 09:31:10.559967 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 09:31:10.563377 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6499 09:31:10.569816 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 09:31:10.570396 Total UI for P1: 0, mck2ui 16
6501 09:31:10.573074 best dqsien dly found for B0: ( 0, 10, 16)
6502 09:31:10.576295 Total UI for P1: 0, mck2ui 16
6503 09:31:10.579858 best dqsien dly found for B1: ( 0, 10, 16)
6504 09:31:10.586419 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6505 09:31:10.589744 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6506 09:31:10.590310
6507 09:31:10.593310 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6508 09:31:10.597123 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6509 09:31:10.599831 [Gating] SW calibration Done
6510 09:31:10.600441 ==
6511 09:31:10.603330 Dram Type= 6, Freq= 0, CH_1, rank 0
6512 09:31:10.606913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6513 09:31:10.607504 ==
6514 09:31:10.609803 RX Vref Scan: 0
6515 09:31:10.610270
6516 09:31:10.610641 RX Vref 0 -> 0, step: 1
6517 09:31:10.610988
6518 09:31:10.612930 RX Delay -410 -> 252, step: 16
6519 09:31:10.619762 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6520 09:31:10.623366 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6521 09:31:10.626384 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6522 09:31:10.629681 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6523 09:31:10.636025 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6524 09:31:10.639307 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6525 09:31:10.643158 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6526 09:31:10.646191 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6527 09:31:10.652983 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6528 09:31:10.656314 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6529 09:31:10.659643 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6530 09:31:10.662982 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6531 09:31:10.669251 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6532 09:31:10.673047 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6533 09:31:10.676283 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6534 09:31:10.679648 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6535 09:31:10.680259 ==
6536 09:31:10.683200 Dram Type= 6, Freq= 0, CH_1, rank 0
6537 09:31:10.689533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6538 09:31:10.690109 ==
6539 09:31:10.690487 DQS Delay:
6540 09:31:10.692507 DQS0 = 43, DQS1 = 59
6541 09:31:10.692979 DQM Delay:
6542 09:31:10.696153 DQM0 = 6, DQM1 = 15
6543 09:31:10.696767 DQ Delay:
6544 09:31:10.699832 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6545 09:31:10.702956 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6546 09:31:10.703526 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6547 09:31:10.706290 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6548 09:31:10.709276
6549 09:31:10.709745
6550 09:31:10.710121 ==
6551 09:31:10.712746 Dram Type= 6, Freq= 0, CH_1, rank 0
6552 09:31:10.716135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 09:31:10.716750 ==
6554 09:31:10.717129
6555 09:31:10.717474
6556 09:31:10.719109 TX Vref Scan disable
6557 09:31:10.719668 == TX Byte 0 ==
6558 09:31:10.722475 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6559 09:31:10.729604 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6560 09:31:10.730211 == TX Byte 1 ==
6561 09:31:10.732550 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6562 09:31:10.739381 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6563 09:31:10.739960 ==
6564 09:31:10.742720 Dram Type= 6, Freq= 0, CH_1, rank 0
6565 09:31:10.746251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6566 09:31:10.746832 ==
6567 09:31:10.747209
6568 09:31:10.747555
6569 09:31:10.749222 TX Vref Scan disable
6570 09:31:10.749696 == TX Byte 0 ==
6571 09:31:10.755748 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6572 09:31:10.759564 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6573 09:31:10.760167 == TX Byte 1 ==
6574 09:31:10.765583 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6575 09:31:10.769398 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6576 09:31:10.769981
6577 09:31:10.770363 [DATLAT]
6578 09:31:10.772387 Freq=400, CH1 RK0
6579 09:31:10.772861
6580 09:31:10.773232 DATLAT Default: 0xf
6581 09:31:10.775757 0, 0xFFFF, sum = 0
6582 09:31:10.776418 1, 0xFFFF, sum = 0
6583 09:31:10.779300 2, 0xFFFF, sum = 0
6584 09:31:10.779876 3, 0xFFFF, sum = 0
6585 09:31:10.782337 4, 0xFFFF, sum = 0
6586 09:31:10.782917 5, 0xFFFF, sum = 0
6587 09:31:10.785939 6, 0xFFFF, sum = 0
6588 09:31:10.786418 7, 0xFFFF, sum = 0
6589 09:31:10.789071 8, 0xFFFF, sum = 0
6590 09:31:10.792170 9, 0xFFFF, sum = 0
6591 09:31:10.792793 10, 0xFFFF, sum = 0
6592 09:31:10.795656 11, 0xFFFF, sum = 0
6593 09:31:10.796279 12, 0x0, sum = 1
6594 09:31:10.799183 13, 0x0, sum = 2
6595 09:31:10.799753 14, 0x0, sum = 3
6596 09:31:10.802052 15, 0x0, sum = 4
6597 09:31:10.802528 best_step = 13
6598 09:31:10.802902
6599 09:31:10.803248 ==
6600 09:31:10.805485 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 09:31:10.808917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6602 09:31:10.809495 ==
6603 09:31:10.812356 RX Vref Scan: 1
6604 09:31:10.812918
6605 09:31:10.815197 RX Vref 0 -> 0, step: 1
6606 09:31:10.815666
6607 09:31:10.816040 RX Delay -359 -> 252, step: 8
6608 09:31:10.816500
6609 09:31:10.818535 Set Vref, RX VrefLevel [Byte0]: 52
6610 09:31:10.821818 [Byte1]: 50
6611 09:31:10.827467
6612 09:31:10.828030 Final RX Vref Byte 0 = 52 to rank0
6613 09:31:10.830802 Final RX Vref Byte 1 = 50 to rank0
6614 09:31:10.834335 Final RX Vref Byte 0 = 52 to rank1
6615 09:31:10.837384 Final RX Vref Byte 1 = 50 to rank1==
6616 09:31:10.841119 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 09:31:10.847542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6618 09:31:10.848121 ==
6619 09:31:10.848582 DQS Delay:
6620 09:31:10.850763 DQS0 = 48, DQS1 = 64
6621 09:31:10.851339 DQM Delay:
6622 09:31:10.851718 DQM0 = 8, DQM1 = 16
6623 09:31:10.853978 DQ Delay:
6624 09:31:10.854479 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6625 09:31:10.857558 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6626 09:31:10.860648 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6627 09:31:10.864123 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6628 09:31:10.864769
6629 09:31:10.865150
6630 09:31:10.874300 [DQSOSCAuto] RK0, (LSB)MR18= 0xdfdf, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6631 09:31:10.877430 CH1 RK0: MR19=C0C, MR18=DFDF
6632 09:31:10.884578 CH1_RK0: MR19=0xC0C, MR18=0xDFDF, DQSOSC=382, MR23=63, INC=404, DEC=269
6633 09:31:10.885158 ==
6634 09:31:10.887206 Dram Type= 6, Freq= 0, CH_1, rank 1
6635 09:31:10.890309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6636 09:31:10.890808 ==
6637 09:31:10.894208 [Gating] SW mode calibration
6638 09:31:10.900639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6639 09:31:10.903713 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6640 09:31:10.910319 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6641 09:31:10.914088 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6642 09:31:10.916897 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 09:31:10.924046 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6644 09:31:10.926900 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 09:31:10.930850 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 09:31:10.936907 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 09:31:10.940800 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6648 09:31:10.943538 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 09:31:10.947049 Total UI for P1: 0, mck2ui 16
6650 09:31:10.950126 best dqsien dly found for B0: ( 0, 10, 16)
6651 09:31:10.953404 Total UI for P1: 0, mck2ui 16
6652 09:31:10.956910 best dqsien dly found for B1: ( 0, 10, 16)
6653 09:31:10.960375 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6654 09:31:10.963326 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6655 09:31:10.963973
6656 09:31:10.970082 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6657 09:31:10.973344 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6658 09:31:10.976884 [Gating] SW calibration Done
6659 09:31:10.977364 ==
6660 09:31:10.980066 Dram Type= 6, Freq= 0, CH_1, rank 1
6661 09:31:10.983559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6662 09:31:10.984146 ==
6663 09:31:10.984594 RX Vref Scan: 0
6664 09:31:10.986286
6665 09:31:10.986775 RX Vref 0 -> 0, step: 1
6666 09:31:10.987156
6667 09:31:10.989798 RX Delay -410 -> 252, step: 16
6668 09:31:10.992933 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6669 09:31:10.999992 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6670 09:31:11.003219 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6671 09:31:11.006754 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6672 09:31:11.009911 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6673 09:31:11.016697 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6674 09:31:11.020248 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6675 09:31:11.023740 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6676 09:31:11.026619 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6677 09:31:11.033397 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6678 09:31:11.036264 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6679 09:31:11.039964 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6680 09:31:11.043283 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6681 09:31:11.049530 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6682 09:31:11.052852 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6683 09:31:11.056250 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6684 09:31:11.056730 ==
6685 09:31:11.059468 Dram Type= 6, Freq= 0, CH_1, rank 1
6686 09:31:11.066212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6687 09:31:11.066780 ==
6688 09:31:11.067166 DQS Delay:
6689 09:31:11.069987 DQS0 = 35, DQS1 = 59
6690 09:31:11.070573 DQM Delay:
6691 09:31:11.070955 DQM0 = 2, DQM1 = 17
6692 09:31:11.072867 DQ Delay:
6693 09:31:11.076126 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6694 09:31:11.076758 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6695 09:31:11.079833 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6696 09:31:11.083060 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6697 09:31:11.083634
6698 09:31:11.084009
6699 09:31:11.084404 ==
6700 09:31:11.086491 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 09:31:11.092649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6702 09:31:11.093221 ==
6703 09:31:11.093601
6704 09:31:11.093948
6705 09:31:11.095805 TX Vref Scan disable
6706 09:31:11.096312 == TX Byte 0 ==
6707 09:31:11.099792 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6708 09:31:11.105838 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6709 09:31:11.106422 == TX Byte 1 ==
6710 09:31:11.109190 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6711 09:31:11.112732 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6712 09:31:11.116271 ==
6713 09:31:11.119790 Dram Type= 6, Freq= 0, CH_1, rank 1
6714 09:31:11.122854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6715 09:31:11.123438 ==
6716 09:31:11.123815
6717 09:31:11.124158
6718 09:31:11.125727 TX Vref Scan disable
6719 09:31:11.126201 == TX Byte 0 ==
6720 09:31:11.129164 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6721 09:31:11.135634 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6722 09:31:11.136280 == TX Byte 1 ==
6723 09:31:11.139027 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6724 09:31:11.145702 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6725 09:31:11.146290
6726 09:31:11.146667 [DATLAT]
6727 09:31:11.147016 Freq=400, CH1 RK1
6728 09:31:11.147351
6729 09:31:11.148874 DATLAT Default: 0xd
6730 09:31:11.149350 0, 0xFFFF, sum = 0
6731 09:31:11.152463 1, 0xFFFF, sum = 0
6732 09:31:11.155456 2, 0xFFFF, sum = 0
6733 09:31:11.155940 3, 0xFFFF, sum = 0
6734 09:31:11.158966 4, 0xFFFF, sum = 0
6735 09:31:11.159553 5, 0xFFFF, sum = 0
6736 09:31:11.162300 6, 0xFFFF, sum = 0
6737 09:31:11.162892 7, 0xFFFF, sum = 0
6738 09:31:11.165207 8, 0xFFFF, sum = 0
6739 09:31:11.165691 9, 0xFFFF, sum = 0
6740 09:31:11.168510 10, 0xFFFF, sum = 0
6741 09:31:11.168994 11, 0xFFFF, sum = 0
6742 09:31:11.172447 12, 0x0, sum = 1
6743 09:31:11.173040 13, 0x0, sum = 2
6744 09:31:11.175393 14, 0x0, sum = 3
6745 09:31:11.175873 15, 0x0, sum = 4
6746 09:31:11.179085 best_step = 13
6747 09:31:11.179664
6748 09:31:11.180040 ==
6749 09:31:11.181878 Dram Type= 6, Freq= 0, CH_1, rank 1
6750 09:31:11.185327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6751 09:31:11.185917 ==
6752 09:31:11.186301 RX Vref Scan: 0
6753 09:31:11.188331
6754 09:31:11.188804 RX Vref 0 -> 0, step: 1
6755 09:31:11.189180
6756 09:31:11.191661 RX Delay -359 -> 252, step: 8
6757 09:31:11.199354 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6758 09:31:11.202760 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6759 09:31:11.206073 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6760 09:31:11.209172 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6761 09:31:11.216260 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6762 09:31:11.219546 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6763 09:31:11.222754 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6764 09:31:11.226084 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6765 09:31:11.232570 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6766 09:31:11.236123 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6767 09:31:11.239353 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6768 09:31:11.245618 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6769 09:31:11.249442 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6770 09:31:11.252880 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6771 09:31:11.255829 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6772 09:31:11.262638 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6773 09:31:11.263224 ==
6774 09:31:11.265660 Dram Type= 6, Freq= 0, CH_1, rank 1
6775 09:31:11.268848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6776 09:31:11.269326 ==
6777 09:31:11.269706 DQS Delay:
6778 09:31:11.272323 DQS0 = 48, DQS1 = 64
6779 09:31:11.272801 DQM Delay:
6780 09:31:11.275634 DQM0 = 9, DQM1 = 15
6781 09:31:11.276238 DQ Delay:
6782 09:31:11.279417 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6783 09:31:11.282583 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6784 09:31:11.285493 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6785 09:31:11.288912 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6786 09:31:11.289388
6787 09:31:11.289763
6788 09:31:11.295944 [DQSOSCAuto] RK1, (LSB)MR18= 0xabab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6789 09:31:11.299036 CH1 RK1: MR19=C0C, MR18=ABAB
6790 09:31:11.305659 CH1_RK1: MR19=0xC0C, MR18=0xABAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6791 09:31:11.309148 [RxdqsGatingPostProcess] freq 400
6792 09:31:11.315708 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6793 09:31:11.316347 Pre-setting of DQS Precalculation
6794 09:31:11.321929 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6795 09:31:11.328749 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6796 09:31:11.335575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6797 09:31:11.336368
6798 09:31:11.336794
6799 09:31:11.338913 [Calibration Summary] 800 Mbps
6800 09:31:11.342239 CH 0, Rank 0
6801 09:31:11.342815 SW Impedance : PASS
6802 09:31:11.345535 DUTY Scan : NO K
6803 09:31:11.348924 ZQ Calibration : PASS
6804 09:31:11.349683 Jitter Meter : NO K
6805 09:31:11.352236 CBT Training : PASS
6806 09:31:11.352714 Write leveling : PASS
6807 09:31:11.355503 RX DQS gating : PASS
6808 09:31:11.358989 RX DQ/DQS(RDDQC) : PASS
6809 09:31:11.359574 TX DQ/DQS : PASS
6810 09:31:11.362223 RX DATLAT : PASS
6811 09:31:11.365421 RX DQ/DQS(Engine): PASS
6812 09:31:11.365899 TX OE : NO K
6813 09:31:11.368577 All Pass.
6814 09:31:11.369046
6815 09:31:11.369418 CH 0, Rank 1
6816 09:31:11.371787 SW Impedance : PASS
6817 09:31:11.372300 DUTY Scan : NO K
6818 09:31:11.375127 ZQ Calibration : PASS
6819 09:31:11.378906 Jitter Meter : NO K
6820 09:31:11.379521 CBT Training : PASS
6821 09:31:11.381893 Write leveling : NO K
6822 09:31:11.385020 RX DQS gating : PASS
6823 09:31:11.385558 RX DQ/DQS(RDDQC) : PASS
6824 09:31:11.388450 TX DQ/DQS : PASS
6825 09:31:11.391949 RX DATLAT : PASS
6826 09:31:11.392592 RX DQ/DQS(Engine): PASS
6827 09:31:11.395353 TX OE : NO K
6828 09:31:11.395856 All Pass.
6829 09:31:11.396432
6830 09:31:11.398787 CH 1, Rank 0
6831 09:31:11.399376 SW Impedance : PASS
6832 09:31:11.402228 DUTY Scan : NO K
6833 09:31:11.402813 ZQ Calibration : PASS
6834 09:31:11.404999 Jitter Meter : NO K
6835 09:31:11.408393 CBT Training : PASS
6836 09:31:11.409204 Write leveling : PASS
6837 09:31:11.411801 RX DQS gating : PASS
6838 09:31:11.415159 RX DQ/DQS(RDDQC) : PASS
6839 09:31:11.415625 TX DQ/DQS : PASS
6840 09:31:11.418299 RX DATLAT : PASS
6841 09:31:11.421589 RX DQ/DQS(Engine): PASS
6842 09:31:11.422094 TX OE : NO K
6843 09:31:11.424747 All Pass.
6844 09:31:11.425211
6845 09:31:11.425624 CH 1, Rank 1
6846 09:31:11.428626 SW Impedance : PASS
6847 09:31:11.429092 DUTY Scan : NO K
6848 09:31:11.431524 ZQ Calibration : PASS
6849 09:31:11.434666 Jitter Meter : NO K
6850 09:31:11.435112 CBT Training : PASS
6851 09:31:11.438208 Write leveling : NO K
6852 09:31:11.441280 RX DQS gating : PASS
6853 09:31:11.441731 RX DQ/DQS(RDDQC) : PASS
6854 09:31:11.444521 TX DQ/DQS : PASS
6855 09:31:11.447915 RX DATLAT : PASS
6856 09:31:11.448496 RX DQ/DQS(Engine): PASS
6857 09:31:11.451585 TX OE : NO K
6858 09:31:11.452036 All Pass.
6859 09:31:11.452676
6860 09:31:11.454521 DramC Write-DBI off
6861 09:31:11.458452 PER_BANK_REFRESH: Hybrid Mode
6862 09:31:11.458874 TX_TRACKING: ON
6863 09:31:11.467683 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6864 09:31:11.471266 [FAST_K] Save calibration result to emmc
6865 09:31:11.474733 dramc_set_vcore_voltage set vcore to 725000
6866 09:31:11.477780 Read voltage for 1600, 0
6867 09:31:11.478203 Vio18 = 0
6868 09:31:11.478541 Vcore = 725000
6869 09:31:11.481119 Vdram = 0
6870 09:31:11.481572 Vddq = 0
6871 09:31:11.481904 Vmddr = 0
6872 09:31:11.487766 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6873 09:31:11.490854 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6874 09:31:11.494371 MEM_TYPE=3, freq_sel=13
6875 09:31:11.497692 sv_algorithm_assistance_LP4_3733
6876 09:31:11.501343 ============ PULL DRAM RESETB DOWN ============
6877 09:31:11.504203 ========== PULL DRAM RESETB DOWN end =========
6878 09:31:11.511146 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6879 09:31:11.514215 ===================================
6880 09:31:11.514667 LPDDR4 DRAM CONFIGURATION
6881 09:31:11.517483 ===================================
6882 09:31:11.520635 EX_ROW_EN[0] = 0x0
6883 09:31:11.524499 EX_ROW_EN[1] = 0x0
6884 09:31:11.524951 LP4Y_EN = 0x0
6885 09:31:11.527571 WORK_FSP = 0x1
6886 09:31:11.528033 WL = 0x5
6887 09:31:11.530991 RL = 0x5
6888 09:31:11.531354 BL = 0x2
6889 09:31:11.534415 RPST = 0x0
6890 09:31:11.534856 RD_PRE = 0x0
6891 09:31:11.537635 WR_PRE = 0x1
6892 09:31:11.538120 WR_PST = 0x1
6893 09:31:11.541064 DBI_WR = 0x0
6894 09:31:11.541551 DBI_RD = 0x0
6895 09:31:11.544050 OTF = 0x1
6896 09:31:11.547332 ===================================
6897 09:31:11.550760 ===================================
6898 09:31:11.551185 ANA top config
6899 09:31:11.554265 ===================================
6900 09:31:11.557646 DLL_ASYNC_EN = 0
6901 09:31:11.560739 ALL_SLAVE_EN = 0
6902 09:31:11.563999 NEW_RANK_MODE = 1
6903 09:31:11.564516 DLL_IDLE_MODE = 1
6904 09:31:11.567364 LP45_APHY_COMB_EN = 1
6905 09:31:11.570720 TX_ODT_DIS = 0
6906 09:31:11.574063 NEW_8X_MODE = 1
6907 09:31:11.577603 ===================================
6908 09:31:11.580558 ===================================
6909 09:31:11.584329 data_rate = 3200
6910 09:31:11.584868 CKR = 1
6911 09:31:11.587548 DQ_P2S_RATIO = 8
6912 09:31:11.590723 ===================================
6913 09:31:11.593961 CA_P2S_RATIO = 8
6914 09:31:11.597121 DQ_CA_OPEN = 0
6915 09:31:11.600619 DQ_SEMI_OPEN = 0
6916 09:31:11.603927 CA_SEMI_OPEN = 0
6917 09:31:11.604510 CA_FULL_RATE = 0
6918 09:31:11.607187 DQ_CKDIV4_EN = 0
6919 09:31:11.610360 CA_CKDIV4_EN = 0
6920 09:31:11.613707 CA_PREDIV_EN = 0
6921 09:31:11.617373 PH8_DLY = 12
6922 09:31:11.620508 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6923 09:31:11.620992 DQ_AAMCK_DIV = 4
6924 09:31:11.624079 CA_AAMCK_DIV = 4
6925 09:31:11.627173 CA_ADMCK_DIV = 4
6926 09:31:11.631041 DQ_TRACK_CA_EN = 0
6927 09:31:11.633758 CA_PICK = 1600
6928 09:31:11.636898 CA_MCKIO = 1600
6929 09:31:11.640297 MCKIO_SEMI = 0
6930 09:31:11.640770 PLL_FREQ = 3068
6931 09:31:11.644137 DQ_UI_PI_RATIO = 32
6932 09:31:11.647094 CA_UI_PI_RATIO = 0
6933 09:31:11.650529 ===================================
6934 09:31:11.653646 ===================================
6935 09:31:11.656903 memory_type:LPDDR4
6936 09:31:11.660573 GP_NUM : 10
6937 09:31:11.661149 SRAM_EN : 1
6938 09:31:11.663846 MD32_EN : 0
6939 09:31:11.666856 ===================================
6940 09:31:11.667349 [ANA_INIT] >>>>>>>>>>>>>>
6941 09:31:11.670060 <<<<<< [CONFIGURE PHASE]: ANA_TX
6942 09:31:11.674047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6943 09:31:11.677149 ===================================
6944 09:31:11.680712 data_rate = 3200,PCW = 0X7600
6945 09:31:11.683738 ===================================
6946 09:31:11.687244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6947 09:31:11.693312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6948 09:31:11.700038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6949 09:31:11.703730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6950 09:31:11.706890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6951 09:31:11.710056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6952 09:31:11.713366 [ANA_INIT] flow start
6953 09:31:11.713964 [ANA_INIT] PLL >>>>>>>>
6954 09:31:11.716829 [ANA_INIT] PLL <<<<<<<<
6955 09:31:11.720264 [ANA_INIT] MIDPI >>>>>>>>
6956 09:31:11.720750 [ANA_INIT] MIDPI <<<<<<<<
6957 09:31:11.723381 [ANA_INIT] DLL >>>>>>>>
6958 09:31:11.726859 [ANA_INIT] DLL <<<<<<<<
6959 09:31:11.727458 [ANA_INIT] flow end
6960 09:31:11.733996 ============ LP4 DIFF to SE enter ============
6961 09:31:11.736644 ============ LP4 DIFF to SE exit ============
6962 09:31:11.737141 [ANA_INIT] <<<<<<<<<<<<<
6963 09:31:11.739793 [Flow] Enable top DCM control >>>>>
6964 09:31:11.743346 [Flow] Enable top DCM control <<<<<
6965 09:31:11.746667 Enable DLL master slave shuffle
6966 09:31:11.753173 ==============================================================
6967 09:31:11.756480 Gating Mode config
6968 09:31:11.759753 ==============================================================
6969 09:31:11.763612 Config description:
6970 09:31:11.773292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6971 09:31:11.779774 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6972 09:31:11.783390 SELPH_MODE 0: By rank 1: By Phase
6973 09:31:11.789474 ==============================================================
6974 09:31:11.793295 GAT_TRACK_EN = 1
6975 09:31:11.796267 RX_GATING_MODE = 2
6976 09:31:11.799804 RX_GATING_TRACK_MODE = 2
6977 09:31:11.800456 SELPH_MODE = 1
6978 09:31:11.803276 PICG_EARLY_EN = 1
6979 09:31:11.806694 VALID_LAT_VALUE = 1
6980 09:31:11.813240 ==============================================================
6981 09:31:11.816579 Enter into Gating configuration >>>>
6982 09:31:11.819714 Exit from Gating configuration <<<<
6983 09:31:11.823061 Enter into DVFS_PRE_config >>>>>
6984 09:31:11.833134 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6985 09:31:11.836126 Exit from DVFS_PRE_config <<<<<
6986 09:31:11.839427 Enter into PICG configuration >>>>
6987 09:31:11.842585 Exit from PICG configuration <<<<
6988 09:31:11.846267 [RX_INPUT] configuration >>>>>
6989 09:31:11.849553 [RX_INPUT] configuration <<<<<
6990 09:31:11.852934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6991 09:31:11.859405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6992 09:31:11.866085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6993 09:31:11.872740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6994 09:31:11.879435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6995 09:31:11.882446 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6996 09:31:11.889368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6997 09:31:11.892659 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6998 09:31:11.895696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6999 09:31:11.899215 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7000 09:31:11.905635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7001 09:31:11.909135 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7002 09:31:11.912408 ===================================
7003 09:31:11.915689 LPDDR4 DRAM CONFIGURATION
7004 09:31:11.919138 ===================================
7005 09:31:11.919742 EX_ROW_EN[0] = 0x0
7006 09:31:11.922403 EX_ROW_EN[1] = 0x0
7007 09:31:11.922994 LP4Y_EN = 0x0
7008 09:31:11.925428 WORK_FSP = 0x1
7009 09:31:11.926046 WL = 0x5
7010 09:31:11.928909 RL = 0x5
7011 09:31:11.929500 BL = 0x2
7012 09:31:11.932293 RPST = 0x0
7013 09:31:11.932880 RD_PRE = 0x0
7014 09:31:11.935254 WR_PRE = 0x1
7015 09:31:11.938431 WR_PST = 0x1
7016 09:31:11.938918 DBI_WR = 0x0
7017 09:31:11.941706 DBI_RD = 0x0
7018 09:31:11.942195 OTF = 0x1
7019 09:31:11.944963 ===================================
7020 09:31:11.948489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7021 09:31:11.955647 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7022 09:31:11.958703 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7023 09:31:11.961713 ===================================
7024 09:31:11.964897 LPDDR4 DRAM CONFIGURATION
7025 09:31:11.968224 ===================================
7026 09:31:11.968715 EX_ROW_EN[0] = 0x10
7027 09:31:11.971481 EX_ROW_EN[1] = 0x0
7028 09:31:11.971964 LP4Y_EN = 0x0
7029 09:31:11.975390 WORK_FSP = 0x1
7030 09:31:11.975986 WL = 0x5
7031 09:31:11.978124 RL = 0x5
7032 09:31:11.978611 BL = 0x2
7033 09:31:11.981514 RPST = 0x0
7034 09:31:11.982001 RD_PRE = 0x0
7035 09:31:11.985032 WR_PRE = 0x1
7036 09:31:11.988208 WR_PST = 0x1
7037 09:31:11.988804 DBI_WR = 0x0
7038 09:31:11.991763 DBI_RD = 0x0
7039 09:31:11.992412 OTF = 0x1
7040 09:31:11.994668 ===================================
7041 09:31:12.001526 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7042 09:31:12.002150 ==
7043 09:31:12.005043 Dram Type= 6, Freq= 0, CH_0, rank 0
7044 09:31:12.008027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7045 09:31:12.008660 ==
7046 09:31:12.011551 [Duty_Offset_Calibration]
7047 09:31:12.012056 B0:0 B1:2 CA:1
7048 09:31:12.014787
7049 09:31:12.018080 [DutyScan_Calibration_Flow] k_type=0
7050 09:31:12.026379
7051 09:31:12.026947 ==CLK 0==
7052 09:31:12.029669 Final CLK duty delay cell = 0
7053 09:31:12.033026 [0] MAX Duty = 5156%(X100), DQS PI = 22
7054 09:31:12.036439 [0] MIN Duty = 4907%(X100), DQS PI = 52
7055 09:31:12.037017 [0] AVG Duty = 5031%(X100)
7056 09:31:12.039412
7057 09:31:12.042760 CH0 CLK Duty spec in!! Max-Min= 249%
7058 09:31:12.046086 [DutyScan_Calibration_Flow] ====Done====
7059 09:31:12.046665
7060 09:31:12.049259 [DutyScan_Calibration_Flow] k_type=1
7061 09:31:12.065632
7062 09:31:12.066205 ==DQS 0 ==
7063 09:31:12.068700 Final DQS duty delay cell = -4
7064 09:31:12.072253 [-4] MAX Duty = 4969%(X100), DQS PI = 4
7065 09:31:12.075821 [-4] MIN Duty = 4875%(X100), DQS PI = 0
7066 09:31:12.078938 [-4] AVG Duty = 4922%(X100)
7067 09:31:12.079512
7068 09:31:12.079884 ==DQS 1 ==
7069 09:31:12.082391 Final DQS duty delay cell = 0
7070 09:31:12.085853 [0] MAX Duty = 5031%(X100), DQS PI = 2
7071 09:31:12.089144 [0] MIN Duty = 4876%(X100), DQS PI = 16
7072 09:31:12.091984 [0] AVG Duty = 4953%(X100)
7073 09:31:12.092625
7074 09:31:12.095594 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7075 09:31:12.096169
7076 09:31:12.098741 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7077 09:31:12.102022 [DutyScan_Calibration_Flow] ====Done====
7078 09:31:12.102599
7079 09:31:12.105045 [DutyScan_Calibration_Flow] k_type=3
7080 09:31:12.122776
7081 09:31:12.123347 ==DQM 0 ==
7082 09:31:12.125677 Final DQM duty delay cell = 0
7083 09:31:12.129076 [0] MAX Duty = 5187%(X100), DQS PI = 22
7084 09:31:12.132719 [0] MIN Duty = 4907%(X100), DQS PI = 42
7085 09:31:12.135628 [0] AVG Duty = 5047%(X100)
7086 09:31:12.136101
7087 09:31:12.136529 ==DQM 1 ==
7088 09:31:12.138943 Final DQM duty delay cell = 0
7089 09:31:12.142530 [0] MAX Duty = 5031%(X100), DQS PI = 52
7090 09:31:12.145834 [0] MIN Duty = 4782%(X100), DQS PI = 14
7091 09:31:12.149600 [0] AVG Duty = 4906%(X100)
7092 09:31:12.150179
7093 09:31:12.152293 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7094 09:31:12.152766
7095 09:31:12.155787 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7096 09:31:12.159139 [DutyScan_Calibration_Flow] ====Done====
7097 09:31:12.159714
7098 09:31:12.162590 [DutyScan_Calibration_Flow] k_type=2
7099 09:31:12.179356
7100 09:31:12.179929 ==DQ 0 ==
7101 09:31:12.182285 Final DQ duty delay cell = 0
7102 09:31:12.186027 [0] MAX Duty = 5218%(X100), DQS PI = 18
7103 09:31:12.188916 [0] MIN Duty = 4938%(X100), DQS PI = 56
7104 09:31:12.192509 [0] AVG Duty = 5078%(X100)
7105 09:31:12.193082
7106 09:31:12.193461 ==DQ 1 ==
7107 09:31:12.195541 Final DQ duty delay cell = -4
7108 09:31:12.198983 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7109 09:31:12.202187 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7110 09:31:12.205168 [-4] AVG Duty = 4953%(X100)
7111 09:31:12.205642
7112 09:31:12.208833 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7113 09:31:12.209412
7114 09:31:12.212436 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7115 09:31:12.215924 [DutyScan_Calibration_Flow] ====Done====
7116 09:31:12.216550 ==
7117 09:31:12.218789 Dram Type= 6, Freq= 0, CH_1, rank 0
7118 09:31:12.222384 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7119 09:31:12.222862 ==
7120 09:31:12.225501 [Duty_Offset_Calibration]
7121 09:31:12.226083 B0:0 B1:4 CA:-5
7122 09:31:12.226465
7123 09:31:12.228718 [DutyScan_Calibration_Flow] k_type=0
7124 09:31:12.239618
7125 09:31:12.240254 ==CLK 0==
7126 09:31:12.242767 Final CLK duty delay cell = 0
7127 09:31:12.246152 [0] MAX Duty = 5156%(X100), DQS PI = 20
7128 09:31:12.249730 [0] MIN Duty = 4906%(X100), DQS PI = 52
7129 09:31:12.252840 [0] AVG Duty = 5031%(X100)
7130 09:31:12.253374
7131 09:31:12.256220 CH1 CLK Duty spec in!! Max-Min= 250%
7132 09:31:12.259451 [DutyScan_Calibration_Flow] ====Done====
7133 09:31:12.259921
7134 09:31:12.262786 [DutyScan_Calibration_Flow] k_type=1
7135 09:31:12.278618
7136 09:31:12.279200 ==DQS 0 ==
7137 09:31:12.281968 Final DQS duty delay cell = 0
7138 09:31:12.285238 [0] MAX Duty = 5156%(X100), DQS PI = 18
7139 09:31:12.288678 [0] MIN Duty = 4844%(X100), DQS PI = 44
7140 09:31:12.289261 [0] AVG Duty = 5000%(X100)
7141 09:31:12.292049
7142 09:31:12.292678 ==DQS 1 ==
7143 09:31:12.295196 Final DQS duty delay cell = -4
7144 09:31:12.298407 [-4] MAX Duty = 4969%(X100), DQS PI = 2
7145 09:31:12.301743 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7146 09:31:12.305257 [-4] AVG Duty = 4906%(X100)
7147 09:31:12.305848
7148 09:31:12.308703 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7149 09:31:12.309276
7150 09:31:12.312073 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7151 09:31:12.315704 [DutyScan_Calibration_Flow] ====Done====
7152 09:31:12.316322
7153 09:31:12.318413 [DutyScan_Calibration_Flow] k_type=3
7154 09:31:12.334298
7155 09:31:12.334872 ==DQM 0 ==
7156 09:31:12.337273 Final DQM duty delay cell = -4
7157 09:31:12.340870 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7158 09:31:12.343966 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7159 09:31:12.347390 [-4] AVG Duty = 4953%(X100)
7160 09:31:12.347971
7161 09:31:12.348409 ==DQM 1 ==
7162 09:31:12.350963 Final DQM duty delay cell = -4
7163 09:31:12.354044 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7164 09:31:12.357342 [-4] MIN Duty = 4875%(X100), DQS PI = 42
7165 09:31:12.360517 [-4] AVG Duty = 4984%(X100)
7166 09:31:12.360984
7167 09:31:12.364028 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7168 09:31:12.364661
7169 09:31:12.367527 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7170 09:31:12.370403 [DutyScan_Calibration_Flow] ====Done====
7171 09:31:12.370983
7172 09:31:12.373986 [DutyScan_Calibration_Flow] k_type=2
7173 09:31:12.391856
7174 09:31:12.392493 ==DQ 0 ==
7175 09:31:12.395333 Final DQ duty delay cell = 0
7176 09:31:12.398858 [0] MAX Duty = 5093%(X100), DQS PI = 20
7177 09:31:12.403737 [0] MIN Duty = 4969%(X100), DQS PI = 46
7178 09:31:12.404242 [0] AVG Duty = 5031%(X100)
7179 09:31:12.405084
7180 09:31:12.405482 ==DQ 1 ==
7181 09:31:12.408420 Final DQ duty delay cell = 0
7182 09:31:12.411635 [0] MAX Duty = 5031%(X100), DQS PI = 2
7183 09:31:12.415277 [0] MIN Duty = 4876%(X100), DQS PI = 28
7184 09:31:12.415858 [0] AVG Duty = 4953%(X100)
7185 09:31:12.416276
7186 09:31:12.418206 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7187 09:31:12.421777
7188 09:31:12.424783 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7189 09:31:12.428347 [DutyScan_Calibration_Flow] ====Done====
7190 09:31:12.431463 nWR fixed to 30
7191 09:31:12.431937 [ModeRegInit_LP4] CH0 RK0
7192 09:31:12.435232 [ModeRegInit_LP4] CH0 RK1
7193 09:31:12.438228 [ModeRegInit_LP4] CH1 RK0
7194 09:31:12.441565 [ModeRegInit_LP4] CH1 RK1
7195 09:31:12.442139 match AC timing 4
7196 09:31:12.444521 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7197 09:31:12.451132 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7198 09:31:12.454438 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7199 09:31:12.461446 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7200 09:31:12.464721 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7201 09:31:12.465305 [MiockJmeterHQA]
7202 09:31:12.465684
7203 09:31:12.468070 [DramcMiockJmeter] u1RxGatingPI = 0
7204 09:31:12.471434 0 : 4254, 4029
7205 09:31:12.472020 4 : 4255, 4029
7206 09:31:12.474747 8 : 4252, 4027
7207 09:31:12.475326 12 : 4252, 4026
7208 09:31:12.475705 16 : 4253, 4027
7209 09:31:12.477706 20 : 4252, 4026
7210 09:31:12.478186 24 : 4252, 4027
7211 09:31:12.480889 28 : 4365, 4140
7212 09:31:12.481366 32 : 4252, 4027
7213 09:31:12.484561 36 : 4254, 4029
7214 09:31:12.485177 40 : 4253, 4027
7215 09:31:12.487851 44 : 4363, 4138
7216 09:31:12.488533 48 : 4252, 4027
7217 09:31:12.488925 52 : 4363, 4138
7218 09:31:12.490923 56 : 4249, 4027
7219 09:31:12.491396 60 : 4252, 4027
7220 09:31:12.494482 64 : 4250, 4027
7221 09:31:12.494960 68 : 4252, 4029
7222 09:31:12.497393 72 : 4360, 4138
7223 09:31:12.497871 76 : 4249, 4027
7224 09:31:12.498248 80 : 4361, 4137
7225 09:31:12.501177 84 : 4250, 4027
7226 09:31:12.501765 88 : 4249, 4027
7227 09:31:12.504689 92 : 4250, 4027
7228 09:31:12.505274 96 : 4360, 4138
7229 09:31:12.507898 100 : 4249, 2265
7230 09:31:12.508533 104 : 4250, 0
7231 09:31:12.511218 108 : 4252, 0
7232 09:31:12.511868 112 : 4250, 0
7233 09:31:12.512292 116 : 4250, 0
7234 09:31:12.514362 120 : 4252, 0
7235 09:31:12.514947 124 : 4250, 0
7236 09:31:12.515329 128 : 4360, 0
7237 09:31:12.517649 132 : 4361, 0
7238 09:31:12.518248 136 : 4249, 0
7239 09:31:12.521327 140 : 4250, 0
7240 09:31:12.521912 144 : 4250, 0
7241 09:31:12.522292 148 : 4252, 0
7242 09:31:12.524374 152 : 4250, 0
7243 09:31:12.524964 156 : 4250, 0
7244 09:31:12.527588 160 : 4252, 0
7245 09:31:12.528209 164 : 4360, 0
7246 09:31:12.528624 168 : 4250, 0
7247 09:31:12.530544 172 : 4250, 0
7248 09:31:12.531019 176 : 4249, 0
7249 09:31:12.534147 180 : 4361, 0
7250 09:31:12.534737 184 : 4361, 0
7251 09:31:12.535119 188 : 4250, 0
7252 09:31:12.537713 192 : 4250, 0
7253 09:31:12.538303 196 : 4250, 0
7254 09:31:12.540788 200 : 4252, 0
7255 09:31:12.541266 204 : 4250, 0
7256 09:31:12.541644 208 : 4250, 0
7257 09:31:12.543998 212 : 4252, 0
7258 09:31:12.544741 216 : 4250, 0
7259 09:31:12.547124 220 : 4360, 503
7260 09:31:12.547620 224 : 4249, 3996
7261 09:31:12.548002 228 : 4249, 4027
7262 09:31:12.550463 232 : 4252, 4029
7263 09:31:12.551047 236 : 4250, 4027
7264 09:31:12.554106 240 : 4360, 4138
7265 09:31:12.554693 244 : 4250, 4026
7266 09:31:12.557092 248 : 4360, 4138
7267 09:31:12.557570 252 : 4250, 4026
7268 09:31:12.560386 256 : 4250, 4027
7269 09:31:12.560865 260 : 4253, 4027
7270 09:31:12.563684 264 : 4252, 4029
7271 09:31:12.564162 268 : 4250, 4026
7272 09:31:12.567433 272 : 4252, 4027
7273 09:31:12.568018 276 : 4249, 4027
7274 09:31:12.570856 280 : 4252, 4029
7275 09:31:12.571439 284 : 4250, 4026
7276 09:31:12.571820 288 : 4361, 4137
7277 09:31:12.573959 292 : 4360, 4138
7278 09:31:12.574548 296 : 4249, 4027
7279 09:31:12.577086 300 : 4363, 4140
7280 09:31:12.577588 304 : 4250, 4026
7281 09:31:12.580624 308 : 4250, 4027
7282 09:31:12.581213 312 : 4252, 4027
7283 09:31:12.584048 316 : 4252, 4029
7284 09:31:12.584681 320 : 4250, 4026
7285 09:31:12.587092 324 : 4250, 4027
7286 09:31:12.587674 328 : 4249, 4027
7287 09:31:12.590254 332 : 4252, 4029
7288 09:31:12.590734 336 : 4250, 3982
7289 09:31:12.593677 340 : 4361, 1939
7290 09:31:12.594266
7291 09:31:12.594644 MIOCK jitter meter ch=0
7292 09:31:12.594996
7293 09:31:12.596929 1T = (340-104) = 236 dly cells
7294 09:31:12.603671 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7295 09:31:12.604342 ==
7296 09:31:12.606851 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 09:31:12.610173 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7298 09:31:12.610755 ==
7299 09:31:12.616876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7300 09:31:12.620568 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7301 09:31:12.623479 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7302 09:31:12.630591 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7303 09:31:12.639207 [CA 0] Center 41 (11~72) winsize 62
7304 09:31:12.642088 [CA 1] Center 41 (11~72) winsize 62
7305 09:31:12.645647 [CA 2] Center 37 (7~68) winsize 62
7306 09:31:12.649032 [CA 3] Center 37 (7~67) winsize 61
7307 09:31:12.651786 [CA 4] Center 35 (5~66) winsize 62
7308 09:31:12.655409 [CA 5] Center 35 (5~65) winsize 61
7309 09:31:12.655978
7310 09:31:12.658541 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7311 09:31:12.659014
7312 09:31:12.662616 [CATrainingPosCal] consider 1 rank data
7313 09:31:12.665419 u2DelayCellTimex100 = 275/100 ps
7314 09:31:12.668732 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7315 09:31:12.675390 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7316 09:31:12.678752 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7317 09:31:12.682225 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7318 09:31:12.685141 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7319 09:31:12.688544 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7320 09:31:12.689015
7321 09:31:12.691856 CA PerBit enable=1, Macro0, CA PI delay=35
7322 09:31:12.692500
7323 09:31:12.694983 [CBTSetCACLKResult] CA Dly = 35
7324 09:31:12.698390 CS Dly: 11 (0~42)
7325 09:31:12.702035 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7326 09:31:12.705054 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7327 09:31:12.705530 ==
7328 09:31:12.708437 Dram Type= 6, Freq= 0, CH_0, rank 1
7329 09:31:12.711955 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7330 09:31:12.715159 ==
7331 09:31:12.718421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7332 09:31:12.721645 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7333 09:31:12.728341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7334 09:31:12.735087 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7335 09:31:12.741586 [CA 0] Center 42 (12~73) winsize 62
7336 09:31:12.744818 [CA 1] Center 42 (12~73) winsize 62
7337 09:31:12.748621 [CA 2] Center 38 (9~68) winsize 60
7338 09:31:12.751358 [CA 3] Center 37 (8~67) winsize 60
7339 09:31:12.754799 [CA 4] Center 36 (6~66) winsize 61
7340 09:31:12.757732 [CA 5] Center 36 (6~66) winsize 61
7341 09:31:12.758211
7342 09:31:12.761585 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7343 09:31:12.762160
7344 09:31:12.764390 [CATrainingPosCal] consider 2 rank data
7345 09:31:12.767799 u2DelayCellTimex100 = 275/100 ps
7346 09:31:12.771328 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7347 09:31:12.777912 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7348 09:31:12.781129 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7349 09:31:12.784516 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7350 09:31:12.788043 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7351 09:31:12.790988 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7352 09:31:12.791464
7353 09:31:12.794505 CA PerBit enable=1, Macro0, CA PI delay=35
7354 09:31:12.795026
7355 09:31:12.797513 [CBTSetCACLKResult] CA Dly = 35
7356 09:31:12.801354 CS Dly: 11 (0~42)
7357 09:31:12.804507 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7358 09:31:12.807875 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7359 09:31:12.808482
7360 09:31:12.810683 ----->DramcWriteLeveling(PI) begin...
7361 09:31:12.811158 ==
7362 09:31:12.814177 Dram Type= 6, Freq= 0, CH_0, rank 0
7363 09:31:12.820436 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7364 09:31:12.820907 ==
7365 09:31:12.823742 Write leveling (Byte 0): 30 => 30
7366 09:31:12.827177 Write leveling (Byte 1): 25 => 25
7367 09:31:12.827647 DramcWriteLeveling(PI) end<-----
7368 09:31:12.828018
7369 09:31:12.830529 ==
7370 09:31:12.834099 Dram Type= 6, Freq= 0, CH_0, rank 0
7371 09:31:12.837122 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7372 09:31:12.837600 ==
7373 09:31:12.840449 [Gating] SW mode calibration
7374 09:31:12.847197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7375 09:31:12.850668 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7376 09:31:12.857041 0 12 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7377 09:31:12.860110 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7378 09:31:12.863767 0 12 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
7379 09:31:12.870377 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7380 09:31:12.873391 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7381 09:31:12.876900 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 09:31:12.883501 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 09:31:12.886815 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7384 09:31:12.890168 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7385 09:31:12.897117 0 13 4 | B1->B0 | 3131 2525 | 0 0 | (0 1) (1 0)
7386 09:31:12.900275 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7387 09:31:12.903366 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7388 09:31:12.910433 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7389 09:31:12.913379 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 09:31:12.916631 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 09:31:12.923653 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 09:31:12.926728 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7393 09:31:12.930059 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
7394 09:31:12.936735 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7395 09:31:12.939961 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7396 09:31:12.943716 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 09:31:12.949585 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 09:31:12.953283 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 09:31:12.956583 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7400 09:31:12.963223 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7401 09:31:12.966475 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7402 09:31:12.969952 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 09:31:12.976567 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 09:31:12.979417 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 09:31:12.982949 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 09:31:12.989808 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 09:31:12.992696 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 09:31:12.996331 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 09:31:13.003305 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 09:31:13.006470 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 09:31:13.009388 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 09:31:13.016343 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 09:31:13.019515 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 09:31:13.022901 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 09:31:13.026273 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7416 09:31:13.033142 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7417 09:31:13.036355 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7418 09:31:13.039252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7419 09:31:13.042883 Total UI for P1: 0, mck2ui 16
7420 09:31:13.045683 best dqsien dly found for B0: ( 1, 1, 0)
7421 09:31:13.052573 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7422 09:31:13.055926 Total UI for P1: 0, mck2ui 16
7423 09:31:13.059396 best dqsien dly found for B1: ( 1, 1, 4)
7424 09:31:13.062282 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7425 09:31:13.065836 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7426 09:31:13.066308
7427 09:31:13.068898 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7428 09:31:13.072396 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7429 09:31:13.075752 [Gating] SW calibration Done
7430 09:31:13.076395 ==
7431 09:31:13.079214 Dram Type= 6, Freq= 0, CH_0, rank 0
7432 09:31:13.082537 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7433 09:31:13.083110 ==
7434 09:31:13.085663 RX Vref Scan: 0
7435 09:31:13.086132
7436 09:31:13.086500 RX Vref 0 -> 0, step: 1
7437 09:31:13.086848
7438 09:31:13.089032 RX Delay 0 -> 252, step: 8
7439 09:31:13.092059 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7440 09:31:13.098700 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7441 09:31:13.102224 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7442 09:31:13.105553 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7443 09:31:13.108947 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7444 09:31:13.112011 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7445 09:31:13.118955 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7446 09:31:13.122117 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7447 09:31:13.125884 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7448 09:31:13.129124 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7449 09:31:13.132366 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7450 09:31:13.138641 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7451 09:31:13.141828 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7452 09:31:13.145526 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7453 09:31:13.148729 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7454 09:31:13.151923 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7455 09:31:13.155194 ==
7456 09:31:13.158489 Dram Type= 6, Freq= 0, CH_0, rank 0
7457 09:31:13.162064 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7458 09:31:13.162541 ==
7459 09:31:13.162917 DQS Delay:
7460 09:31:13.165341 DQS0 = 0, DQS1 = 0
7461 09:31:13.165911 DQM Delay:
7462 09:31:13.168823 DQM0 = 129, DQM1 = 124
7463 09:31:13.169391 DQ Delay:
7464 09:31:13.172075 DQ0 =123, DQ1 =131, DQ2 =127, DQ3 =127
7465 09:31:13.175645 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
7466 09:31:13.178601 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7467 09:31:13.181948 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7468 09:31:13.182421
7469 09:31:13.182794
7470 09:31:13.183143 ==
7471 09:31:13.184836 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 09:31:13.192029 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7473 09:31:13.192718 ==
7474 09:31:13.193218
7475 09:31:13.193578
7476 09:31:13.194986 TX Vref Scan disable
7477 09:31:13.195459 == TX Byte 0 ==
7478 09:31:13.198134 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7479 09:31:13.204718 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7480 09:31:13.205197 == TX Byte 1 ==
7481 09:31:13.208399 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7482 09:31:13.215244 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7483 09:31:13.215821 ==
7484 09:31:13.218032 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 09:31:13.221208 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7486 09:31:13.221688 ==
7487 09:31:13.236001
7488 09:31:13.239433 TX Vref early break, caculate TX vref
7489 09:31:13.242294 TX Vref=16, minBit 8, minWin=21, winSum=362
7490 09:31:13.245987 TX Vref=18, minBit 15, minWin=22, winSum=371
7491 09:31:13.249055 TX Vref=20, minBit 0, minWin=23, winSum=380
7492 09:31:13.252445 TX Vref=22, minBit 8, minWin=23, winSum=388
7493 09:31:13.255792 TX Vref=24, minBit 1, minWin=24, winSum=400
7494 09:31:13.262713 TX Vref=26, minBit 0, minWin=25, winSum=407
7495 09:31:13.265781 TX Vref=28, minBit 0, minWin=24, winSum=408
7496 09:31:13.269342 TX Vref=30, minBit 0, minWin=24, winSum=404
7497 09:31:13.272089 TX Vref=32, minBit 7, minWin=23, winSum=394
7498 09:31:13.275955 TX Vref=34, minBit 6, minWin=23, winSum=387
7499 09:31:13.279189 TX Vref=36, minBit 1, minWin=22, winSum=378
7500 09:31:13.285619 [TxChooseVref] Worse bit 0, Min win 25, Win sum 407, Final Vref 26
7501 09:31:13.286188
7502 09:31:13.288780 Final TX Range 0 Vref 26
7503 09:31:13.289256
7504 09:31:13.289628 ==
7505 09:31:13.292152 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 09:31:13.295859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7507 09:31:13.296486 ==
7508 09:31:13.296867
7509 09:31:13.298644
7510 09:31:13.299115 TX Vref Scan disable
7511 09:31:13.305267 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7512 09:31:13.305836 == TX Byte 0 ==
7513 09:31:13.309089 u2DelayCellOfst[0]=14 cells (4 PI)
7514 09:31:13.312164 u2DelayCellOfst[1]=21 cells (6 PI)
7515 09:31:13.315350 u2DelayCellOfst[2]=14 cells (4 PI)
7516 09:31:13.318839 u2DelayCellOfst[3]=14 cells (4 PI)
7517 09:31:13.321849 u2DelayCellOfst[4]=7 cells (2 PI)
7518 09:31:13.325277 u2DelayCellOfst[5]=0 cells (0 PI)
7519 09:31:13.328635 u2DelayCellOfst[6]=21 cells (6 PI)
7520 09:31:13.331796 u2DelayCellOfst[7]=17 cells (5 PI)
7521 09:31:13.335311 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7522 09:31:13.338492 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7523 09:31:13.341762 == TX Byte 1 ==
7524 09:31:13.345064 u2DelayCellOfst[8]=3 cells (1 PI)
7525 09:31:13.348624 u2DelayCellOfst[9]=0 cells (0 PI)
7526 09:31:13.351537 u2DelayCellOfst[10]=10 cells (3 PI)
7527 09:31:13.355115 u2DelayCellOfst[11]=3 cells (1 PI)
7528 09:31:13.358451 u2DelayCellOfst[12]=14 cells (4 PI)
7529 09:31:13.359025 u2DelayCellOfst[13]=14 cells (4 PI)
7530 09:31:13.361692 u2DelayCellOfst[14]=17 cells (5 PI)
7531 09:31:13.364970 u2DelayCellOfst[15]=14 cells (4 PI)
7532 09:31:13.371654 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7533 09:31:13.375208 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7534 09:31:13.375791 DramC Write-DBI on
7535 09:31:13.377992 ==
7536 09:31:13.381310 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 09:31:13.384978 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7538 09:31:13.385455 ==
7539 09:31:13.385830
7540 09:31:13.386186
7541 09:31:13.388112 TX Vref Scan disable
7542 09:31:13.388638 == TX Byte 0 ==
7543 09:31:13.394457 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7544 09:31:13.394933 == TX Byte 1 ==
7545 09:31:13.397705 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7546 09:31:13.401393 DramC Write-DBI off
7547 09:31:13.401968
7548 09:31:13.402350 [DATLAT]
7549 09:31:13.404690 Freq=1600, CH0 RK0
7550 09:31:13.405168
7551 09:31:13.405539 DATLAT Default: 0xf
7552 09:31:13.408116 0, 0xFFFF, sum = 0
7553 09:31:13.408737 1, 0xFFFF, sum = 0
7554 09:31:13.410955 2, 0xFFFF, sum = 0
7555 09:31:13.411433 3, 0xFFFF, sum = 0
7556 09:31:13.414581 4, 0xFFFF, sum = 0
7557 09:31:13.415162 5, 0xFFFF, sum = 0
7558 09:31:13.417913 6, 0xFFFF, sum = 0
7559 09:31:13.421032 7, 0xFFFF, sum = 0
7560 09:31:13.421525 8, 0xFFFF, sum = 0
7561 09:31:13.425044 9, 0xFFFF, sum = 0
7562 09:31:13.425645 10, 0xFFFF, sum = 0
7563 09:31:13.427738 11, 0xFFFF, sum = 0
7564 09:31:13.428252 12, 0xBFF, sum = 0
7565 09:31:13.431135 13, 0x0, sum = 1
7566 09:31:13.431727 14, 0x0, sum = 2
7567 09:31:13.434542 15, 0x0, sum = 3
7568 09:31:13.435022 16, 0x0, sum = 4
7569 09:31:13.435616 best_step = 14
7570 09:31:13.437802
7571 09:31:13.438378 ==
7572 09:31:13.440836 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 09:31:13.444341 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7574 09:31:13.444908 ==
7575 09:31:13.445289 RX Vref Scan: 1
7576 09:31:13.445641
7577 09:31:13.447721 Set Vref Range= 24 -> 127
7578 09:31:13.448230
7579 09:31:13.451266 RX Vref 24 -> 127, step: 1
7580 09:31:13.451788
7581 09:31:13.454263 RX Delay 11 -> 252, step: 4
7582 09:31:13.454735
7583 09:31:13.457999 Set Vref, RX VrefLevel [Byte0]: 24
7584 09:31:13.460845 [Byte1]: 24
7585 09:31:13.461319
7586 09:31:13.464633 Set Vref, RX VrefLevel [Byte0]: 25
7587 09:31:13.467863 [Byte1]: 25
7588 09:31:13.468477
7589 09:31:13.471376 Set Vref, RX VrefLevel [Byte0]: 26
7590 09:31:13.474653 [Byte1]: 26
7591 09:31:13.477836
7592 09:31:13.481345 Set Vref, RX VrefLevel [Byte0]: 27
7593 09:31:13.482075 [Byte1]: 27
7594 09:31:13.485448
7595 09:31:13.486015 Set Vref, RX VrefLevel [Byte0]: 28
7596 09:31:13.489055 [Byte1]: 28
7597 09:31:13.493312
7598 09:31:13.493881 Set Vref, RX VrefLevel [Byte0]: 29
7599 09:31:13.496724 [Byte1]: 29
7600 09:31:13.500852
7601 09:31:13.501557 Set Vref, RX VrefLevel [Byte0]: 30
7602 09:31:13.504008 [Byte1]: 30
7603 09:31:13.508149
7604 09:31:13.508686 Set Vref, RX VrefLevel [Byte0]: 31
7605 09:31:13.511507 [Byte1]: 31
7606 09:31:13.516255
7607 09:31:13.516833 Set Vref, RX VrefLevel [Byte0]: 32
7608 09:31:13.519351 [Byte1]: 32
7609 09:31:13.524088
7610 09:31:13.524716 Set Vref, RX VrefLevel [Byte0]: 33
7611 09:31:13.526985 [Byte1]: 33
7612 09:31:13.531514
7613 09:31:13.532083 Set Vref, RX VrefLevel [Byte0]: 34
7614 09:31:13.534507 [Byte1]: 34
7615 09:31:13.538541
7616 09:31:13.539013 Set Vref, RX VrefLevel [Byte0]: 35
7617 09:31:13.541916 [Byte1]: 35
7618 09:31:13.546354
7619 09:31:13.546918 Set Vref, RX VrefLevel [Byte0]: 36
7620 09:31:13.549538 [Byte1]: 36
7621 09:31:13.553983
7622 09:31:13.554499 Set Vref, RX VrefLevel [Byte0]: 37
7623 09:31:13.557282 [Byte1]: 37
7624 09:31:13.561486
7625 09:31:13.561952 Set Vref, RX VrefLevel [Byte0]: 38
7626 09:31:13.564814 [Byte1]: 38
7627 09:31:13.569122
7628 09:31:13.569696 Set Vref, RX VrefLevel [Byte0]: 39
7629 09:31:13.572859 [Byte1]: 39
7630 09:31:13.576855
7631 09:31:13.580240 Set Vref, RX VrefLevel [Byte0]: 40
7632 09:31:13.583120 [Byte1]: 40
7633 09:31:13.583593
7634 09:31:13.586758 Set Vref, RX VrefLevel [Byte0]: 41
7635 09:31:13.590252 [Byte1]: 41
7636 09:31:13.590820
7637 09:31:13.593087 Set Vref, RX VrefLevel [Byte0]: 42
7638 09:31:13.597133 [Byte1]: 42
7639 09:31:13.597700
7640 09:31:13.599872 Set Vref, RX VrefLevel [Byte0]: 43
7641 09:31:13.603208 [Byte1]: 43
7642 09:31:13.607273
7643 09:31:13.607744 Set Vref, RX VrefLevel [Byte0]: 44
7644 09:31:13.610569 [Byte1]: 44
7645 09:31:13.614895
7646 09:31:13.615458 Set Vref, RX VrefLevel [Byte0]: 45
7647 09:31:13.618019 [Byte1]: 45
7648 09:31:13.622379
7649 09:31:13.622864 Set Vref, RX VrefLevel [Byte0]: 46
7650 09:31:13.625984 [Byte1]: 46
7651 09:31:13.630156
7652 09:31:13.630723 Set Vref, RX VrefLevel [Byte0]: 47
7653 09:31:13.633429 [Byte1]: 47
7654 09:31:13.637945
7655 09:31:13.638511 Set Vref, RX VrefLevel [Byte0]: 48
7656 09:31:13.641166 [Byte1]: 48
7657 09:31:13.645161
7658 09:31:13.645630 Set Vref, RX VrefLevel [Byte0]: 49
7659 09:31:13.648490 [Byte1]: 49
7660 09:31:13.652830
7661 09:31:13.653302 Set Vref, RX VrefLevel [Byte0]: 50
7662 09:31:13.656447 [Byte1]: 50
7663 09:31:13.660450
7664 09:31:13.660957 Set Vref, RX VrefLevel [Byte0]: 51
7665 09:31:13.663793 [Byte1]: 51
7666 09:31:13.668401
7667 09:31:13.668870 Set Vref, RX VrefLevel [Byte0]: 52
7668 09:31:13.671353 [Byte1]: 52
7669 09:31:13.675877
7670 09:31:13.676498 Set Vref, RX VrefLevel [Byte0]: 53
7671 09:31:13.679247 [Byte1]: 53
7672 09:31:13.683768
7673 09:31:13.684386 Set Vref, RX VrefLevel [Byte0]: 54
7674 09:31:13.686428 [Byte1]: 54
7675 09:31:13.690813
7676 09:31:13.691384 Set Vref, RX VrefLevel [Byte0]: 55
7677 09:31:13.694871 [Byte1]: 55
7678 09:31:13.698898
7679 09:31:13.699481 Set Vref, RX VrefLevel [Byte0]: 56
7680 09:31:13.701797 [Byte1]: 56
7681 09:31:13.706360
7682 09:31:13.706988 Set Vref, RX VrefLevel [Byte0]: 57
7683 09:31:13.709320 [Byte1]: 57
7684 09:31:13.714293
7685 09:31:13.714864 Set Vref, RX VrefLevel [Byte0]: 58
7686 09:31:13.717130 [Byte1]: 58
7687 09:31:13.721870
7688 09:31:13.722496 Set Vref, RX VrefLevel [Byte0]: 59
7689 09:31:13.725250 [Byte1]: 59
7690 09:31:13.729452
7691 09:31:13.730021 Set Vref, RX VrefLevel [Byte0]: 60
7692 09:31:13.732503 [Byte1]: 60
7693 09:31:13.736925
7694 09:31:13.737536 Set Vref, RX VrefLevel [Byte0]: 61
7695 09:31:13.740156 [Byte1]: 61
7696 09:31:13.744559
7697 09:31:13.745133 Set Vref, RX VrefLevel [Byte0]: 62
7698 09:31:13.747516 [Byte1]: 62
7699 09:31:13.751613
7700 09:31:13.752316 Set Vref, RX VrefLevel [Byte0]: 63
7701 09:31:13.755339 [Byte1]: 63
7702 09:31:13.759376
7703 09:31:13.759972 Set Vref, RX VrefLevel [Byte0]: 64
7704 09:31:13.762628 [Byte1]: 64
7705 09:31:13.767224
7706 09:31:13.767693 Set Vref, RX VrefLevel [Byte0]: 65
7707 09:31:13.770816 [Byte1]: 65
7708 09:31:13.775384
7709 09:31:13.775957 Set Vref, RX VrefLevel [Byte0]: 66
7710 09:31:13.778019 [Byte1]: 66
7711 09:31:13.782644
7712 09:31:13.783328 Set Vref, RX VrefLevel [Byte0]: 67
7713 09:31:13.786183 [Byte1]: 67
7714 09:31:13.790137
7715 09:31:13.790712 Set Vref, RX VrefLevel [Byte0]: 68
7716 09:31:13.793057 [Byte1]: 68
7717 09:31:13.797627
7718 09:31:13.798220 Set Vref, RX VrefLevel [Byte0]: 69
7719 09:31:13.800891 [Byte1]: 69
7720 09:31:13.805204
7721 09:31:13.805671 Set Vref, RX VrefLevel [Byte0]: 70
7722 09:31:13.808843 [Byte1]: 70
7723 09:31:13.812782
7724 09:31:13.813358 Final RX Vref Byte 0 = 53 to rank0
7725 09:31:13.815916 Final RX Vref Byte 1 = 54 to rank0
7726 09:31:13.819581 Final RX Vref Byte 0 = 53 to rank1
7727 09:31:13.822843 Final RX Vref Byte 1 = 54 to rank1==
7728 09:31:13.825975 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 09:31:13.832586 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7730 09:31:13.833156 ==
7731 09:31:13.833532 DQS Delay:
7732 09:31:13.833881 DQS0 = 0, DQS1 = 0
7733 09:31:13.835919 DQM Delay:
7734 09:31:13.836464 DQM0 = 126, DQM1 = 120
7735 09:31:13.839494 DQ Delay:
7736 09:31:13.842762 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7737 09:31:13.846082 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7738 09:31:13.849414 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7739 09:31:13.852667 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7740 09:31:13.853140
7741 09:31:13.853511
7742 09:31:13.853859
7743 09:31:13.855950 [DramC_TX_OE_Calibration] TA2
7744 09:31:13.859311 Original DQ_B0 (3 6) =30, OEN = 27
7745 09:31:13.862751 Original DQ_B1 (3 6) =30, OEN = 27
7746 09:31:13.865902 24, 0x0, End_B0=24 End_B1=24
7747 09:31:13.866379 25, 0x0, End_B0=25 End_B1=25
7748 09:31:13.869051 26, 0x0, End_B0=26 End_B1=26
7749 09:31:13.872779 27, 0x0, End_B0=27 End_B1=27
7750 09:31:13.876049 28, 0x0, End_B0=28 End_B1=28
7751 09:31:13.879693 29, 0x0, End_B0=29 End_B1=29
7752 09:31:13.880324 30, 0x0, End_B0=30 End_B1=30
7753 09:31:13.882570 31, 0x4141, End_B0=30 End_B1=30
7754 09:31:13.885799 Byte0 end_step=30 best_step=27
7755 09:31:13.889522 Byte1 end_step=30 best_step=27
7756 09:31:13.892881 Byte0 TX OE(2T, 0.5T) = (3, 3)
7757 09:31:13.893488 Byte1 TX OE(2T, 0.5T) = (3, 3)
7758 09:31:13.896129
7759 09:31:13.896745
7760 09:31:13.902533 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7761 09:31:13.905772 CH0 RK0: MR19=303, MR18=1919
7762 09:31:13.912454 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7763 09:31:13.913050
7764 09:31:13.915800 ----->DramcWriteLeveling(PI) begin...
7765 09:31:13.916427 ==
7766 09:31:13.919294 Dram Type= 6, Freq= 0, CH_0, rank 1
7767 09:31:13.922716 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7768 09:31:13.923307 ==
7769 09:31:13.925608 Write leveling (Byte 0): 29 => 29
7770 09:31:13.928864 Write leveling (Byte 1): 25 => 25
7771 09:31:13.932809 DramcWriteLeveling(PI) end<-----
7772 09:31:13.933378
7773 09:31:13.933751 ==
7774 09:31:13.935957 Dram Type= 6, Freq= 0, CH_0, rank 1
7775 09:31:13.939331 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7776 09:31:13.939908 ==
7777 09:31:13.942537 [Gating] SW mode calibration
7778 09:31:13.949038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7779 09:31:13.955784 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7780 09:31:13.959313 0 12 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7781 09:31:13.962060 0 12 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7782 09:31:13.968692 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7783 09:31:13.972417 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7784 09:31:13.975579 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7785 09:31:13.981885 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7786 09:31:13.985481 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7787 09:31:13.988583 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7788 09:31:13.995258 0 13 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
7789 09:31:13.998538 0 13 4 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7790 09:31:14.002078 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7791 09:31:14.008558 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7792 09:31:14.011928 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7793 09:31:14.015215 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 09:31:14.021723 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7795 09:31:14.025341 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7796 09:31:14.029049 0 14 0 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7797 09:31:14.034867 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7798 09:31:14.038565 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7799 09:31:14.041534 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7800 09:31:14.048507 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 09:31:14.051340 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 09:31:14.054743 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7803 09:31:14.061992 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7804 09:31:14.064638 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7805 09:31:14.067927 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7806 09:31:14.074750 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 09:31:14.078280 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 09:31:14.081440 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 09:31:14.088123 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 09:31:14.091414 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 09:31:14.094881 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 09:31:14.101802 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 09:31:14.104849 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 09:31:14.108071 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 09:31:14.114596 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 09:31:14.118088 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 09:31:14.121431 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 09:31:14.128069 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 09:31:14.131449 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7820 09:31:14.134760 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7821 09:31:14.137910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7822 09:31:14.141125 Total UI for P1: 0, mck2ui 16
7823 09:31:14.144398 best dqsien dly found for B0: ( 1, 0, 30)
7824 09:31:14.151374 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7825 09:31:14.154452 Total UI for P1: 0, mck2ui 16
7826 09:31:14.157698 best dqsien dly found for B1: ( 1, 1, 4)
7827 09:31:14.161581 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7828 09:31:14.164804 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7829 09:31:14.165378
7830 09:31:14.167905 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7831 09:31:14.171101 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7832 09:31:14.174528 [Gating] SW calibration Done
7833 09:31:14.175088 ==
7834 09:31:14.177995 Dram Type= 6, Freq= 0, CH_0, rank 1
7835 09:31:14.180921 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7836 09:31:14.181395 ==
7837 09:31:14.184120 RX Vref Scan: 0
7838 09:31:14.184635
7839 09:31:14.185010 RX Vref 0 -> 0, step: 1
7840 09:31:14.185363
7841 09:31:14.187603 RX Delay 0 -> 252, step: 8
7842 09:31:14.191466 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7843 09:31:14.197854 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7844 09:31:14.200973 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7845 09:31:14.204624 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7846 09:31:14.208045 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7847 09:31:14.210958 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7848 09:31:14.217550 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7849 09:31:14.221026 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7850 09:31:14.224334 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7851 09:31:14.227891 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7852 09:31:14.230960 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7853 09:31:14.237417 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7854 09:31:14.240993 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7855 09:31:14.243797 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7856 09:31:14.247322 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7857 09:31:14.253912 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7858 09:31:14.254473 ==
7859 09:31:14.257123 Dram Type= 6, Freq= 0, CH_0, rank 1
7860 09:31:14.260914 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7861 09:31:14.261498 ==
7862 09:31:14.261880 DQS Delay:
7863 09:31:14.263634 DQS0 = 0, DQS1 = 0
7864 09:31:14.264100 DQM Delay:
7865 09:31:14.267529 DQM0 = 130, DQM1 = 123
7866 09:31:14.268378 DQ Delay:
7867 09:31:14.270567 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7868 09:31:14.273811 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7869 09:31:14.277051 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7870 09:31:14.280211 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7871 09:31:14.280690
7872 09:31:14.283456
7873 09:31:14.283920 ==
7874 09:31:14.286611 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 09:31:14.290286 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 09:31:14.290867 ==
7877 09:31:14.291246
7878 09:31:14.291593
7879 09:31:14.293518 TX Vref Scan disable
7880 09:31:14.294048 == TX Byte 0 ==
7881 09:31:14.300359 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7882 09:31:14.303526 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7883 09:31:14.304103 == TX Byte 1 ==
7884 09:31:14.310338 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7885 09:31:14.313595 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7886 09:31:14.314175 ==
7887 09:31:14.316934 Dram Type= 6, Freq= 0, CH_0, rank 1
7888 09:31:14.319664 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7889 09:31:14.320138 ==
7890 09:31:14.334862
7891 09:31:14.338093 TX Vref early break, caculate TX vref
7892 09:31:14.341279 TX Vref=16, minBit 1, minWin=22, winSum=371
7893 09:31:14.344803 TX Vref=18, minBit 1, minWin=22, winSum=375
7894 09:31:14.347783 TX Vref=20, minBit 1, minWin=22, winSum=385
7895 09:31:14.350946 TX Vref=22, minBit 7, minWin=23, winSum=391
7896 09:31:14.354477 TX Vref=24, minBit 8, minWin=23, winSum=396
7897 09:31:14.360971 TX Vref=26, minBit 1, minWin=24, winSum=401
7898 09:31:14.364460 TX Vref=28, minBit 1, minWin=24, winSum=405
7899 09:31:14.367904 TX Vref=30, minBit 0, minWin=24, winSum=403
7900 09:31:14.371293 TX Vref=32, minBit 1, minWin=23, winSum=395
7901 09:31:14.374616 TX Vref=34, minBit 1, minWin=23, winSum=384
7902 09:31:14.377935 TX Vref=36, minBit 8, minWin=22, winSum=375
7903 09:31:14.384654 [TxChooseVref] Worse bit 1, Min win 24, Win sum 405, Final Vref 28
7904 09:31:14.385215
7905 09:31:14.387717 Final TX Range 0 Vref 28
7906 09:31:14.388231
7907 09:31:14.388619 ==
7908 09:31:14.391223 Dram Type= 6, Freq= 0, CH_0, rank 1
7909 09:31:14.394196 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7910 09:31:14.394700 ==
7911 09:31:14.395080
7912 09:31:14.395427
7913 09:31:14.397570 TX Vref Scan disable
7914 09:31:14.404918 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7915 09:31:14.405500 == TX Byte 0 ==
7916 09:31:14.408100 u2DelayCellOfst[0]=10 cells (3 PI)
7917 09:31:14.410745 u2DelayCellOfst[1]=17 cells (5 PI)
7918 09:31:14.414738 u2DelayCellOfst[2]=10 cells (3 PI)
7919 09:31:14.417597 u2DelayCellOfst[3]=14 cells (4 PI)
7920 09:31:14.421222 u2DelayCellOfst[4]=7 cells (2 PI)
7921 09:31:14.424377 u2DelayCellOfst[5]=0 cells (0 PI)
7922 09:31:14.428112 u2DelayCellOfst[6]=17 cells (5 PI)
7923 09:31:14.431122 u2DelayCellOfst[7]=17 cells (5 PI)
7924 09:31:14.434393 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7925 09:31:14.437622 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7926 09:31:14.440838 == TX Byte 1 ==
7927 09:31:14.444153 u2DelayCellOfst[8]=3 cells (1 PI)
7928 09:31:14.444823 u2DelayCellOfst[9]=0 cells (0 PI)
7929 09:31:14.447986 u2DelayCellOfst[10]=10 cells (3 PI)
7930 09:31:14.450699 u2DelayCellOfst[11]=7 cells (2 PI)
7931 09:31:14.454217 u2DelayCellOfst[12]=17 cells (5 PI)
7932 09:31:14.457625 u2DelayCellOfst[13]=17 cells (5 PI)
7933 09:31:14.460741 u2DelayCellOfst[14]=21 cells (6 PI)
7934 09:31:14.464145 u2DelayCellOfst[15]=17 cells (5 PI)
7935 09:31:14.470829 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7936 09:31:14.474025 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7937 09:31:14.474548 DramC Write-DBI on
7938 09:31:14.474924 ==
7939 09:31:14.477313 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 09:31:14.483978 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7941 09:31:14.484582 ==
7942 09:31:14.485047
7943 09:31:14.485402
7944 09:31:14.485734 TX Vref Scan disable
7945 09:31:14.488139 == TX Byte 0 ==
7946 09:31:14.491370 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7947 09:31:14.494595 == TX Byte 1 ==
7948 09:31:14.497895 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7949 09:31:14.501770 DramC Write-DBI off
7950 09:31:14.502240
7951 09:31:14.502615 [DATLAT]
7952 09:31:14.502966 Freq=1600, CH0 RK1
7953 09:31:14.503380
7954 09:31:14.504656 DATLAT Default: 0xe
7955 09:31:14.505154 0, 0xFFFF, sum = 0
7956 09:31:14.508061 1, 0xFFFF, sum = 0
7957 09:31:14.508567 2, 0xFFFF, sum = 0
7958 09:31:14.511207 3, 0xFFFF, sum = 0
7959 09:31:14.511682 4, 0xFFFF, sum = 0
7960 09:31:14.515115 5, 0xFFFF, sum = 0
7961 09:31:14.517878 6, 0xFFFF, sum = 0
7962 09:31:14.518365 7, 0xFFFF, sum = 0
7963 09:31:14.521372 8, 0xFFFF, sum = 0
7964 09:31:14.521995 9, 0xFFFF, sum = 0
7965 09:31:14.524910 10, 0xFFFF, sum = 0
7966 09:31:14.525494 11, 0xFFFF, sum = 0
7967 09:31:14.528062 12, 0x8FFF, sum = 0
7968 09:31:14.528678 13, 0x0, sum = 1
7969 09:31:14.531543 14, 0x0, sum = 2
7970 09:31:14.532122 15, 0x0, sum = 3
7971 09:31:14.534708 16, 0x0, sum = 4
7972 09:31:14.535291 best_step = 14
7973 09:31:14.535666
7974 09:31:14.536010 ==
7975 09:31:14.538081 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 09:31:14.540981 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7977 09:31:14.544644 ==
7978 09:31:14.545212 RX Vref Scan: 0
7979 09:31:14.545586
7980 09:31:14.547973 RX Vref 0 -> 0, step: 1
7981 09:31:14.548667
7982 09:31:14.549055 RX Delay 11 -> 252, step: 4
7983 09:31:14.555128 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7984 09:31:14.558603 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7985 09:31:14.561971 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7986 09:31:14.564940 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7987 09:31:14.571659 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7988 09:31:14.574801 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7989 09:31:14.578348 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7990 09:31:14.581432 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7991 09:31:14.584622 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7992 09:31:14.591333 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7993 09:31:14.594658 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7994 09:31:14.597899 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7995 09:31:14.601375 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7996 09:31:14.604763 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7997 09:31:14.611010 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7998 09:31:14.614620 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7999 09:31:14.615239 ==
8000 09:31:14.618188 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 09:31:14.621103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8002 09:31:14.621675 ==
8003 09:31:14.624234 DQS Delay:
8004 09:31:14.624730 DQS0 = 0, DQS1 = 0
8005 09:31:14.625105 DQM Delay:
8006 09:31:14.627519 DQM0 = 128, DQM1 = 120
8007 09:31:14.627992 DQ Delay:
8008 09:31:14.631217 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =122
8009 09:31:14.634385 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8010 09:31:14.640850 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8011 09:31:14.644698 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8012 09:31:14.645274
8013 09:31:14.645652
8014 09:31:14.645998
8015 09:31:14.647785 [DramC_TX_OE_Calibration] TA2
8016 09:31:14.650963 Original DQ_B0 (3 6) =30, OEN = 27
8017 09:31:14.651537 Original DQ_B1 (3 6) =30, OEN = 27
8018 09:31:14.654256 24, 0x0, End_B0=24 End_B1=24
8019 09:31:14.657308 25, 0x0, End_B0=25 End_B1=25
8020 09:31:14.661015 26, 0x0, End_B0=26 End_B1=26
8021 09:31:14.663888 27, 0x0, End_B0=27 End_B1=27
8022 09:31:14.664411 28, 0x0, End_B0=28 End_B1=28
8023 09:31:14.667725 29, 0x0, End_B0=29 End_B1=29
8024 09:31:14.670747 30, 0x0, End_B0=30 End_B1=30
8025 09:31:14.674010 31, 0x5151, End_B0=30 End_B1=30
8026 09:31:14.677658 Byte0 end_step=30 best_step=27
8027 09:31:14.680719 Byte1 end_step=30 best_step=27
8028 09:31:14.681293 Byte0 TX OE(2T, 0.5T) = (3, 3)
8029 09:31:14.684012 Byte1 TX OE(2T, 0.5T) = (3, 3)
8030 09:31:14.684529
8031 09:31:14.684904
8032 09:31:14.694288 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8033 09:31:14.697119 CH0 RK1: MR19=303, MR18=2323
8034 09:31:14.700750 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8035 09:31:14.704089 [RxdqsGatingPostProcess] freq 1600
8036 09:31:14.710757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8037 09:31:14.713743 Pre-setting of DQS Precalculation
8038 09:31:14.717240 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8039 09:31:14.717714 ==
8040 09:31:14.720632 Dram Type= 6, Freq= 0, CH_1, rank 0
8041 09:31:14.727109 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8042 09:31:14.727682 ==
8043 09:31:14.730682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8044 09:31:14.737084 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8045 09:31:14.740485 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8046 09:31:14.747102 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8047 09:31:14.754092 [CA 0] Center 41 (11~71) winsize 61
8048 09:31:14.757437 [CA 1] Center 41 (11~72) winsize 62
8049 09:31:14.760715 [CA 2] Center 37 (8~67) winsize 60
8050 09:31:14.763932 [CA 3] Center 36 (6~66) winsize 61
8051 09:31:14.767562 [CA 4] Center 34 (4~64) winsize 61
8052 09:31:14.770813 [CA 5] Center 34 (4~64) winsize 61
8053 09:31:14.771503
8054 09:31:14.774030 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8055 09:31:14.774613
8056 09:31:14.777368 [CATrainingPosCal] consider 1 rank data
8057 09:31:14.780679 u2DelayCellTimex100 = 275/100 ps
8058 09:31:14.783635 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8059 09:31:14.790582 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8060 09:31:14.793870 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8061 09:31:14.797219 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8062 09:31:14.800297 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8063 09:31:14.803905 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8064 09:31:14.804589
8065 09:31:14.807152 CA PerBit enable=1, Macro0, CA PI delay=34
8066 09:31:14.807742
8067 09:31:14.810166 [CBTSetCACLKResult] CA Dly = 34
8068 09:31:14.813967 CS Dly: 8 (0~39)
8069 09:31:14.817316 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8070 09:31:14.820446 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8071 09:31:14.821023 ==
8072 09:31:14.823805 Dram Type= 6, Freq= 0, CH_1, rank 1
8073 09:31:14.827043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8074 09:31:14.830322 ==
8075 09:31:14.833410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8076 09:31:14.836639 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8077 09:31:14.843434 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8078 09:31:14.849972 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8079 09:31:14.856444 [CA 0] Center 41 (11~71) winsize 61
8080 09:31:14.859821 [CA 1] Center 41 (11~71) winsize 61
8081 09:31:14.863179 [CA 2] Center 36 (7~66) winsize 60
8082 09:31:14.866245 [CA 3] Center 36 (7~65) winsize 59
8083 09:31:14.870237 [CA 4] Center 34 (4~64) winsize 61
8084 09:31:14.872799 [CA 5] Center 34 (4~64) winsize 61
8085 09:31:14.873269
8086 09:31:14.876552 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8087 09:31:14.877133
8088 09:31:14.879973 [CATrainingPosCal] consider 2 rank data
8089 09:31:14.883395 u2DelayCellTimex100 = 275/100 ps
8090 09:31:14.886193 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8091 09:31:14.893017 CA1 delay=41 (11~71),Diff = 7 PI (24 cell)
8092 09:31:14.896555 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8093 09:31:14.899568 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8094 09:31:14.903285 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8095 09:31:14.906543 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8096 09:31:14.907124
8097 09:31:14.909662 CA PerBit enable=1, Macro0, CA PI delay=34
8098 09:31:14.910133
8099 09:31:14.912957 [CBTSetCACLKResult] CA Dly = 34
8100 09:31:14.916276 CS Dly: 9 (0~41)
8101 09:31:14.919614 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8102 09:31:14.922830 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8103 09:31:14.923406
8104 09:31:14.925991 ----->DramcWriteLeveling(PI) begin...
8105 09:31:14.926575 ==
8106 09:31:14.929481 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 09:31:14.936104 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 09:31:14.936729 ==
8109 09:31:14.939299 Write leveling (Byte 0): 23 => 23
8110 09:31:14.942401 Write leveling (Byte 1): 21 => 21
8111 09:31:14.942984 DramcWriteLeveling(PI) end<-----
8112 09:31:14.943364
8113 09:31:14.945651 ==
8114 09:31:14.948886 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 09:31:14.952427 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 09:31:14.953006 ==
8117 09:31:14.955827 [Gating] SW mode calibration
8118 09:31:14.962253 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8119 09:31:14.965948 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8120 09:31:14.972009 0 12 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8121 09:31:14.975113 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 09:31:14.979137 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 09:31:14.985702 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 09:31:14.988609 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 09:31:14.991702 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 09:31:14.998637 0 12 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8127 09:31:15.002005 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8128 09:31:15.005276 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8129 09:31:15.012305 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8130 09:31:15.015225 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 09:31:15.018584 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 09:31:15.025134 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 09:31:15.028651 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 09:31:15.031589 0 13 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8135 09:31:15.038585 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8136 09:31:15.041728 0 14 0 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
8137 09:31:15.044863 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 09:31:15.051596 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 09:31:15.054907 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 09:31:15.057996 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 09:31:15.064748 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 09:31:15.067792 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 09:31:15.071660 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8144 09:31:15.077934 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8145 09:31:15.081423 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8146 09:31:15.084544 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 09:31:15.091236 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 09:31:15.094490 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 09:31:15.097762 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 09:31:15.104515 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 09:31:15.108011 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 09:31:15.111428 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 09:31:15.117656 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 09:31:15.121286 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 09:31:15.124734 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 09:31:15.131231 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 09:31:15.134472 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 09:31:15.137458 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8159 09:31:15.144527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8160 09:31:15.147643 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8161 09:31:15.151026 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8162 09:31:15.154464 Total UI for P1: 0, mck2ui 16
8163 09:31:15.157436 best dqsien dly found for B0: ( 1, 0, 28)
8164 09:31:15.161377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8165 09:31:15.164309 Total UI for P1: 0, mck2ui 16
8166 09:31:15.167426 best dqsien dly found for B1: ( 1, 1, 0)
8167 09:31:15.170957 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8168 09:31:15.174354 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8169 09:31:15.177804
8170 09:31:15.180818 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8171 09:31:15.184305 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8172 09:31:15.187580 [Gating] SW calibration Done
8173 09:31:15.188285 ==
8174 09:31:15.190780 Dram Type= 6, Freq= 0, CH_1, rank 0
8175 09:31:15.193936 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8176 09:31:15.194593 ==
8177 09:31:15.194977 RX Vref Scan: 0
8178 09:31:15.195342
8179 09:31:15.197204 RX Vref 0 -> 0, step: 1
8180 09:31:15.197757
8181 09:31:15.200506 RX Delay 0 -> 252, step: 8
8182 09:31:15.203936 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8183 09:31:15.207441 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8184 09:31:15.213548 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8185 09:31:15.217225 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8186 09:31:15.220767 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8187 09:31:15.224031 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8188 09:31:15.227294 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8189 09:31:15.233739 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8190 09:31:15.237125 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8191 09:31:15.240276 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8192 09:31:15.243351 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8193 09:31:15.246923 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8194 09:31:15.253622 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8195 09:31:15.256840 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8196 09:31:15.260492 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8197 09:31:15.263587 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8198 09:31:15.264164 ==
8199 09:31:15.267003 Dram Type= 6, Freq= 0, CH_1, rank 0
8200 09:31:15.273348 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8201 09:31:15.274114 ==
8202 09:31:15.274507 DQS Delay:
8203 09:31:15.276908 DQS0 = 0, DQS1 = 0
8204 09:31:15.277376 DQM Delay:
8205 09:31:15.277747 DQM0 = 130, DQM1 = 125
8206 09:31:15.280370 DQ Delay:
8207 09:31:15.283483 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8208 09:31:15.286670 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8209 09:31:15.290458 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8210 09:31:15.293359 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8211 09:31:15.293934
8212 09:31:15.294307
8213 09:31:15.294648 ==
8214 09:31:15.296426 Dram Type= 6, Freq= 0, CH_1, rank 0
8215 09:31:15.299774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8216 09:31:15.303441 ==
8217 09:31:15.304027
8218 09:31:15.304454
8219 09:31:15.304803 TX Vref Scan disable
8220 09:31:15.306568 == TX Byte 0 ==
8221 09:31:15.309764 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8222 09:31:15.313093 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8223 09:31:15.316672 == TX Byte 1 ==
8224 09:31:15.319873 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8225 09:31:15.323185 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8226 09:31:15.326623 ==
8227 09:31:15.329767 Dram Type= 6, Freq= 0, CH_1, rank 0
8228 09:31:15.333224 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8229 09:31:15.333806 ==
8230 09:31:15.344970
8231 09:31:15.348477 TX Vref early break, caculate TX vref
8232 09:31:15.351395 TX Vref=16, minBit 3, minWin=21, winSum=367
8233 09:31:15.354742 TX Vref=18, minBit 3, minWin=22, winSum=378
8234 09:31:15.358113 TX Vref=20, minBit 2, minWin=23, winSum=388
8235 09:31:15.361266 TX Vref=22, minBit 0, minWin=24, winSum=396
8236 09:31:15.364554 TX Vref=24, minBit 0, minWin=24, winSum=402
8237 09:31:15.371573 TX Vref=26, minBit 0, minWin=24, winSum=410
8238 09:31:15.374401 TX Vref=28, minBit 0, minWin=24, winSum=413
8239 09:31:15.378111 TX Vref=30, minBit 0, minWin=25, winSum=409
8240 09:31:15.381488 TX Vref=32, minBit 3, minWin=24, winSum=400
8241 09:31:15.384707 TX Vref=34, minBit 1, minWin=23, winSum=390
8242 09:31:15.391088 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 30
8243 09:31:15.391654
8244 09:31:15.394297 Final TX Range 0 Vref 30
8245 09:31:15.394769
8246 09:31:15.395140 ==
8247 09:31:15.397578 Dram Type= 6, Freq= 0, CH_1, rank 0
8248 09:31:15.401043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8249 09:31:15.401571 ==
8250 09:31:15.401961
8251 09:31:15.402305
8252 09:31:15.404364 TX Vref Scan disable
8253 09:31:15.411175 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8254 09:31:15.411758 == TX Byte 0 ==
8255 09:31:15.415075 u2DelayCellOfst[0]=14 cells (4 PI)
8256 09:31:15.417592 u2DelayCellOfst[1]=10 cells (3 PI)
8257 09:31:15.420847 u2DelayCellOfst[2]=0 cells (0 PI)
8258 09:31:15.424289 u2DelayCellOfst[3]=7 cells (2 PI)
8259 09:31:15.427221 u2DelayCellOfst[4]=7 cells (2 PI)
8260 09:31:15.430936 u2DelayCellOfst[5]=14 cells (4 PI)
8261 09:31:15.434336 u2DelayCellOfst[6]=17 cells (5 PI)
8262 09:31:15.437731 u2DelayCellOfst[7]=7 cells (2 PI)
8263 09:31:15.440672 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8264 09:31:15.443864 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8265 09:31:15.447598 == TX Byte 1 ==
8266 09:31:15.448231 u2DelayCellOfst[8]=0 cells (0 PI)
8267 09:31:15.450815 u2DelayCellOfst[9]=7 cells (2 PI)
8268 09:31:15.454213 u2DelayCellOfst[10]=10 cells (3 PI)
8269 09:31:15.457514 u2DelayCellOfst[11]=3 cells (1 PI)
8270 09:31:15.460543 u2DelayCellOfst[12]=17 cells (5 PI)
8271 09:31:15.463408 u2DelayCellOfst[13]=21 cells (6 PI)
8272 09:31:15.466822 u2DelayCellOfst[14]=21 cells (6 PI)
8273 09:31:15.470580 u2DelayCellOfst[15]=17 cells (5 PI)
8274 09:31:15.473766 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8275 09:31:15.480411 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8276 09:31:15.480989 DramC Write-DBI on
8277 09:31:15.481367 ==
8278 09:31:15.483354 Dram Type= 6, Freq= 0, CH_1, rank 0
8279 09:31:15.490201 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8280 09:31:15.490783 ==
8281 09:31:15.491160
8282 09:31:15.491505
8283 09:31:15.491839 TX Vref Scan disable
8284 09:31:15.494001 == TX Byte 0 ==
8285 09:31:15.497275 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8286 09:31:15.500838 == TX Byte 1 ==
8287 09:31:15.504045 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8288 09:31:15.507347 DramC Write-DBI off
8289 09:31:15.507923
8290 09:31:15.508328 [DATLAT]
8291 09:31:15.508680 Freq=1600, CH1 RK0
8292 09:31:15.509016
8293 09:31:15.510831 DATLAT Default: 0xf
8294 09:31:15.511408 0, 0xFFFF, sum = 0
8295 09:31:15.514064 1, 0xFFFF, sum = 0
8296 09:31:15.517056 2, 0xFFFF, sum = 0
8297 09:31:15.517632 3, 0xFFFF, sum = 0
8298 09:31:15.520291 4, 0xFFFF, sum = 0
8299 09:31:15.520770 5, 0xFFFF, sum = 0
8300 09:31:15.524119 6, 0xFFFF, sum = 0
8301 09:31:15.524751 7, 0xFFFF, sum = 0
8302 09:31:15.527609 8, 0xFFFF, sum = 0
8303 09:31:15.528220 9, 0xFFFF, sum = 0
8304 09:31:15.530644 10, 0xFFFF, sum = 0
8305 09:31:15.531222 11, 0xFFFF, sum = 0
8306 09:31:15.534216 12, 0x8F7F, sum = 0
8307 09:31:15.534795 13, 0x0, sum = 1
8308 09:31:15.536971 14, 0x0, sum = 2
8309 09:31:15.537452 15, 0x0, sum = 3
8310 09:31:15.540362 16, 0x0, sum = 4
8311 09:31:15.540946 best_step = 14
8312 09:31:15.541325
8313 09:31:15.541676 ==
8314 09:31:15.543457 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 09:31:15.546910 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8316 09:31:15.550405 ==
8317 09:31:15.551109 RX Vref Scan: 1
8318 09:31:15.551494
8319 09:31:15.553795 Set Vref Range= 24 -> 127
8320 09:31:15.554372
8321 09:31:15.556891 RX Vref 24 -> 127, step: 1
8322 09:31:15.557364
8323 09:31:15.557737 RX Delay 3 -> 252, step: 4
8324 09:31:15.558082
8325 09:31:15.559914 Set Vref, RX VrefLevel [Byte0]: 24
8326 09:31:15.564038 [Byte1]: 24
8327 09:31:15.567507
8328 09:31:15.568075 Set Vref, RX VrefLevel [Byte0]: 25
8329 09:31:15.570739 [Byte1]: 25
8330 09:31:15.574838
8331 09:31:15.575482 Set Vref, RX VrefLevel [Byte0]: 26
8332 09:31:15.577951 [Byte1]: 26
8333 09:31:15.582461
8334 09:31:15.583039 Set Vref, RX VrefLevel [Byte0]: 27
8335 09:31:15.585807 [Byte1]: 27
8336 09:31:15.590278
8337 09:31:15.590853 Set Vref, RX VrefLevel [Byte0]: 28
8338 09:31:15.593546 [Byte1]: 28
8339 09:31:15.598082
8340 09:31:15.598656 Set Vref, RX VrefLevel [Byte0]: 29
8341 09:31:15.600925 [Byte1]: 29
8342 09:31:15.606127
8343 09:31:15.606701 Set Vref, RX VrefLevel [Byte0]: 30
8344 09:31:15.608788 [Byte1]: 30
8345 09:31:15.613171
8346 09:31:15.613748 Set Vref, RX VrefLevel [Byte0]: 31
8347 09:31:15.616535 [Byte1]: 31
8348 09:31:15.620736
8349 09:31:15.621309 Set Vref, RX VrefLevel [Byte0]: 32
8350 09:31:15.624550 [Byte1]: 32
8351 09:31:15.628541
8352 09:31:15.629064 Set Vref, RX VrefLevel [Byte0]: 33
8353 09:31:15.631898 [Byte1]: 33
8354 09:31:15.636159
8355 09:31:15.636772 Set Vref, RX VrefLevel [Byte0]: 34
8356 09:31:15.639430 [Byte1]: 34
8357 09:31:15.643610
8358 09:31:15.644078 Set Vref, RX VrefLevel [Byte0]: 35
8359 09:31:15.646927 [Byte1]: 35
8360 09:31:15.651605
8361 09:31:15.652070 Set Vref, RX VrefLevel [Byte0]: 36
8362 09:31:15.654900 [Byte1]: 36
8363 09:31:15.658904
8364 09:31:15.662688 Set Vref, RX VrefLevel [Byte0]: 37
8365 09:31:15.663154 [Byte1]: 37
8366 09:31:15.666658
8367 09:31:15.667123 Set Vref, RX VrefLevel [Byte0]: 38
8368 09:31:15.669787 [Byte1]: 38
8369 09:31:15.674044
8370 09:31:15.674511 Set Vref, RX VrefLevel [Byte0]: 39
8371 09:31:15.677480 [Byte1]: 39
8372 09:31:15.682102
8373 09:31:15.682567 Set Vref, RX VrefLevel [Byte0]: 40
8374 09:31:15.684997 [Byte1]: 40
8375 09:31:15.690000
8376 09:31:15.690703 Set Vref, RX VrefLevel [Byte0]: 41
8377 09:31:15.692859 [Byte1]: 41
8378 09:31:15.697176
8379 09:31:15.697639 Set Vref, RX VrefLevel [Byte0]: 42
8380 09:31:15.700508 [Byte1]: 42
8381 09:31:15.704737
8382 09:31:15.705204 Set Vref, RX VrefLevel [Byte0]: 43
8383 09:31:15.708295 [Byte1]: 43
8384 09:31:15.712492
8385 09:31:15.713059 Set Vref, RX VrefLevel [Byte0]: 44
8386 09:31:15.715640 [Byte1]: 44
8387 09:31:15.720153
8388 09:31:15.720641 Set Vref, RX VrefLevel [Byte0]: 45
8389 09:31:15.723744 [Byte1]: 45
8390 09:31:15.727914
8391 09:31:15.728542 Set Vref, RX VrefLevel [Byte0]: 46
8392 09:31:15.731631 [Byte1]: 46
8393 09:31:15.735769
8394 09:31:15.736388 Set Vref, RX VrefLevel [Byte0]: 47
8395 09:31:15.738679 [Byte1]: 47
8396 09:31:15.743555
8397 09:31:15.744127 Set Vref, RX VrefLevel [Byte0]: 48
8398 09:31:15.746553 [Byte1]: 48
8399 09:31:15.751353
8400 09:31:15.751923 Set Vref, RX VrefLevel [Byte0]: 49
8401 09:31:15.754363 [Byte1]: 49
8402 09:31:15.758765
8403 09:31:15.759329 Set Vref, RX VrefLevel [Byte0]: 50
8404 09:31:15.761686 [Byte1]: 50
8405 09:31:15.766350
8406 09:31:15.766918 Set Vref, RX VrefLevel [Byte0]: 51
8407 09:31:15.769782 [Byte1]: 51
8408 09:31:15.773952
8409 09:31:15.774523 Set Vref, RX VrefLevel [Byte0]: 52
8410 09:31:15.777184 [Byte1]: 52
8411 09:31:15.781652
8412 09:31:15.782250 Set Vref, RX VrefLevel [Byte0]: 53
8413 09:31:15.784917 [Byte1]: 53
8414 09:31:15.788869
8415 09:31:15.789333 Set Vref, RX VrefLevel [Byte0]: 54
8416 09:31:15.793083 [Byte1]: 54
8417 09:31:15.796608
8418 09:31:15.797097 Set Vref, RX VrefLevel [Byte0]: 55
8419 09:31:15.799889 [Byte1]: 55
8420 09:31:15.804640
8421 09:31:15.805102 Set Vref, RX VrefLevel [Byte0]: 56
8422 09:31:15.807804 [Byte1]: 56
8423 09:31:15.812411
8424 09:31:15.812978 Set Vref, RX VrefLevel [Byte0]: 57
8425 09:31:15.815741 [Byte1]: 57
8426 09:31:15.819845
8427 09:31:15.820471 Set Vref, RX VrefLevel [Byte0]: 58
8428 09:31:15.823096 [Byte1]: 58
8429 09:31:15.828025
8430 09:31:15.828648 Set Vref, RX VrefLevel [Byte0]: 59
8431 09:31:15.830723 [Byte1]: 59
8432 09:31:15.835095
8433 09:31:15.835661 Set Vref, RX VrefLevel [Byte0]: 60
8434 09:31:15.838580 [Byte1]: 60
8435 09:31:15.842865
8436 09:31:15.843433 Set Vref, RX VrefLevel [Byte0]: 61
8437 09:31:15.846019 [Byte1]: 61
8438 09:31:15.850704
8439 09:31:15.851288 Set Vref, RX VrefLevel [Byte0]: 62
8440 09:31:15.854164 [Byte1]: 62
8441 09:31:15.858393
8442 09:31:15.858964 Set Vref, RX VrefLevel [Byte0]: 63
8443 09:31:15.861286 [Byte1]: 63
8444 09:31:15.865719
8445 09:31:15.866186 Set Vref, RX VrefLevel [Byte0]: 64
8446 09:31:15.868880 [Byte1]: 64
8447 09:31:15.873385
8448 09:31:15.873962 Set Vref, RX VrefLevel [Byte0]: 65
8449 09:31:15.876483 [Byte1]: 65
8450 09:31:15.881149
8451 09:31:15.881726 Set Vref, RX VrefLevel [Byte0]: 66
8452 09:31:15.884569 [Byte1]: 66
8453 09:31:15.888806
8454 09:31:15.889380 Set Vref, RX VrefLevel [Byte0]: 67
8455 09:31:15.891855 [Byte1]: 67
8456 09:31:15.896554
8457 09:31:15.897184 Set Vref, RX VrefLevel [Byte0]: 68
8458 09:31:15.899576 [Byte1]: 68
8459 09:31:15.904075
8460 09:31:15.904696 Set Vref, RX VrefLevel [Byte0]: 69
8461 09:31:15.907315 [Byte1]: 69
8462 09:31:15.911449
8463 09:31:15.911915 Set Vref, RX VrefLevel [Byte0]: 70
8464 09:31:15.914999 [Byte1]: 70
8465 09:31:15.919382
8466 09:31:15.919958 Set Vref, RX VrefLevel [Byte0]: 71
8467 09:31:15.922392 [Byte1]: 71
8468 09:31:15.927204
8469 09:31:15.927783 Set Vref, RX VrefLevel [Byte0]: 72
8470 09:31:15.930169 [Byte1]: 72
8471 09:31:15.934702
8472 09:31:15.935341 Set Vref, RX VrefLevel [Byte0]: 73
8473 09:31:15.937859 [Byte1]: 73
8474 09:31:15.942343
8475 09:31:15.942916 Set Vref, RX VrefLevel [Byte0]: 74
8476 09:31:15.945387 [Byte1]: 74
8477 09:31:15.949888
8478 09:31:15.950460 Set Vref, RX VrefLevel [Byte0]: 75
8479 09:31:15.953765 [Byte1]: 75
8480 09:31:15.957759
8481 09:31:15.958339 Set Vref, RX VrefLevel [Byte0]: 76
8482 09:31:15.960964 [Byte1]: 76
8483 09:31:15.965497
8484 09:31:15.965966 Final RX Vref Byte 0 = 60 to rank0
8485 09:31:15.968400 Final RX Vref Byte 1 = 57 to rank0
8486 09:31:15.972476 Final RX Vref Byte 0 = 60 to rank1
8487 09:31:15.975378 Final RX Vref Byte 1 = 57 to rank1==
8488 09:31:15.978287 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 09:31:15.985507 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8490 09:31:15.986089 ==
8491 09:31:15.986468 DQS Delay:
8492 09:31:15.986839 DQS0 = 0, DQS1 = 0
8493 09:31:15.988313 DQM Delay:
8494 09:31:15.988879 DQM0 = 128, DQM1 = 123
8495 09:31:15.991737 DQ Delay:
8496 09:31:15.995232 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8497 09:31:15.998707 DQ4 =128, DQ5 =140, DQ6 =136, DQ7 =126
8498 09:31:16.001536 DQ8 =106, DQ9 =112, DQ10 =126, DQ11 =110
8499 09:31:16.005022 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =132
8500 09:31:16.005606
8501 09:31:16.005982
8502 09:31:16.006327
8503 09:31:16.008238 [DramC_TX_OE_Calibration] TA2
8504 09:31:16.011395 Original DQ_B0 (3 6) =30, OEN = 27
8505 09:31:16.014898 Original DQ_B1 (3 6) =30, OEN = 27
8506 09:31:16.018288 24, 0x0, End_B0=24 End_B1=24
8507 09:31:16.018875 25, 0x0, End_B0=25 End_B1=25
8508 09:31:16.021404 26, 0x0, End_B0=26 End_B1=26
8509 09:31:16.025076 27, 0x0, End_B0=27 End_B1=27
8510 09:31:16.028119 28, 0x0, End_B0=28 End_B1=28
8511 09:31:16.028645 29, 0x0, End_B0=29 End_B1=29
8512 09:31:16.031759 30, 0x0, End_B0=30 End_B1=30
8513 09:31:16.035123 31, 0x5151, End_B0=30 End_B1=30
8514 09:31:16.038426 Byte0 end_step=30 best_step=27
8515 09:31:16.041575 Byte1 end_step=30 best_step=27
8516 09:31:16.045127 Byte0 TX OE(2T, 0.5T) = (3, 3)
8517 09:31:16.045601 Byte1 TX OE(2T, 0.5T) = (3, 3)
8518 09:31:16.048340
8519 09:31:16.048809
8520 09:31:16.055141 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8521 09:31:16.058073 CH1 RK0: MR19=303, MR18=2A2A
8522 09:31:16.064466 CH1_RK0: MR19=0x303, MR18=0x2A2A, DQSOSC=388, MR23=63, INC=24, DEC=16
8523 09:31:16.065025
8524 09:31:16.067760 ----->DramcWriteLeveling(PI) begin...
8525 09:31:16.068285 ==
8526 09:31:16.071619 Dram Type= 6, Freq= 0, CH_1, rank 1
8527 09:31:16.074583 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8528 09:31:16.075161 ==
8529 09:31:16.078048 Write leveling (Byte 0): 22 => 22
8530 09:31:16.081610 Write leveling (Byte 1): 19 => 19
8531 09:31:16.084827 DramcWriteLeveling(PI) end<-----
8532 09:31:16.085403
8533 09:31:16.085855 ==
8534 09:31:16.087620 Dram Type= 6, Freq= 0, CH_1, rank 1
8535 09:31:16.090841 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8536 09:31:16.091315 ==
8537 09:31:16.094747 [Gating] SW mode calibration
8538 09:31:16.101400 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8539 09:31:16.107834 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8540 09:31:16.111257 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8541 09:31:16.117716 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8542 09:31:16.121005 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8543 09:31:16.124339 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8544 09:31:16.130953 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8545 09:31:16.134624 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8546 09:31:16.137418 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8547 09:31:16.144119 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8548 09:31:16.147802 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8549 09:31:16.150846 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8550 09:31:16.157146 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8551 09:31:16.160696 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8552 09:31:16.163868 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8553 09:31:16.167069 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8554 09:31:16.174178 0 13 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8555 09:31:16.177208 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8556 09:31:16.180650 0 14 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8557 09:31:16.187598 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 09:31:16.190628 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8559 09:31:16.193962 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8560 09:31:16.200082 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 09:31:16.203702 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8562 09:31:16.206848 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8563 09:31:16.213638 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8564 09:31:16.216848 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8565 09:31:16.220098 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 09:31:16.226967 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 09:31:16.230538 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 09:31:16.233494 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 09:31:16.240335 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 09:31:16.243619 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 09:31:16.246671 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 09:31:16.253371 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 09:31:16.256954 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 09:31:16.260351 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 09:31:16.266539 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 09:31:16.270077 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 09:31:16.273595 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 09:31:16.279756 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8579 09:31:16.282920 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8580 09:31:16.286836 Total UI for P1: 0, mck2ui 16
8581 09:31:16.289555 best dqsien dly found for B0: ( 1, 0, 24)
8582 09:31:16.292944 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8583 09:31:16.299863 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8584 09:31:16.300504 Total UI for P1: 0, mck2ui 16
8585 09:31:16.306381 best dqsien dly found for B1: ( 1, 0, 30)
8586 09:31:16.309821 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8587 09:31:16.313025 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8588 09:31:16.313603
8589 09:31:16.316359 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8590 09:31:16.319342 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8591 09:31:16.322990 [Gating] SW calibration Done
8592 09:31:16.323580 ==
8593 09:31:16.326348 Dram Type= 6, Freq= 0, CH_1, rank 1
8594 09:31:16.329947 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8595 09:31:16.330535 ==
8596 09:31:16.333087 RX Vref Scan: 0
8597 09:31:16.333661
8598 09:31:16.334031 RX Vref 0 -> 0, step: 1
8599 09:31:16.334377
8600 09:31:16.336264 RX Delay 0 -> 252, step: 8
8601 09:31:16.339737 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8602 09:31:16.346179 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8603 09:31:16.349975 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8604 09:31:16.352779 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8605 09:31:16.356274 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8606 09:31:16.359317 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8607 09:31:16.366034 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8608 09:31:16.369134 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8609 09:31:16.372739 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8610 09:31:16.376082 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8611 09:31:16.379767 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8612 09:31:16.386369 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8613 09:31:16.389049 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8614 09:31:16.392242 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8615 09:31:16.395749 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8616 09:31:16.398895 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8617 09:31:16.402031 ==
8618 09:31:16.405818 Dram Type= 6, Freq= 0, CH_1, rank 1
8619 09:31:16.409105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8620 09:31:16.409688 ==
8621 09:31:16.410060 DQS Delay:
8622 09:31:16.412556 DQS0 = 0, DQS1 = 0
8623 09:31:16.413136 DQM Delay:
8624 09:31:16.416045 DQM0 = 130, DQM1 = 124
8625 09:31:16.416676 DQ Delay:
8626 09:31:16.419148 DQ0 =131, DQ1 =123, DQ2 =115, DQ3 =131
8627 09:31:16.422593 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8628 09:31:16.425744 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8629 09:31:16.429023 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8630 09:31:16.429601
8631 09:31:16.430018
8632 09:31:16.430571 ==
8633 09:31:16.431868 Dram Type= 6, Freq= 0, CH_1, rank 1
8634 09:31:16.438900 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8635 09:31:16.439482 ==
8636 09:31:16.439860
8637 09:31:16.440225
8638 09:31:16.440562 TX Vref Scan disable
8639 09:31:16.442383 == TX Byte 0 ==
8640 09:31:16.446222 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8641 09:31:16.452785 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8642 09:31:16.453364 == TX Byte 1 ==
8643 09:31:16.456328 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8644 09:31:16.462630 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8645 09:31:16.463212 ==
8646 09:31:16.465627 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 09:31:16.468842 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 09:31:16.469316 ==
8649 09:31:16.482547
8650 09:31:16.485642 TX Vref early break, caculate TX vref
8651 09:31:16.488895 TX Vref=16, minBit 0, minWin=22, winSum=380
8652 09:31:16.492585 TX Vref=18, minBit 5, minWin=22, winSum=386
8653 09:31:16.495731 TX Vref=20, minBit 1, minWin=23, winSum=399
8654 09:31:16.498738 TX Vref=22, minBit 0, minWin=24, winSum=406
8655 09:31:16.501939 TX Vref=24, minBit 0, minWin=24, winSum=411
8656 09:31:16.508863 TX Vref=26, minBit 0, minWin=25, winSum=420
8657 09:31:16.512393 TX Vref=28, minBit 0, minWin=24, winSum=418
8658 09:31:16.515533 TX Vref=30, minBit 0, minWin=25, winSum=418
8659 09:31:16.519017 TX Vref=32, minBit 0, minWin=24, winSum=411
8660 09:31:16.522639 TX Vref=34, minBit 0, minWin=22, winSum=401
8661 09:31:16.525534 TX Vref=36, minBit 0, minWin=23, winSum=390
8662 09:31:16.532158 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8663 09:31:16.532750
8664 09:31:16.535389 Final TX Range 0 Vref 26
8665 09:31:16.535967
8666 09:31:16.536412 ==
8667 09:31:16.538703 Dram Type= 6, Freq= 0, CH_1, rank 1
8668 09:31:16.541881 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8669 09:31:16.542483 ==
8670 09:31:16.542879
8671 09:31:16.545088
8672 09:31:16.545558 TX Vref Scan disable
8673 09:31:16.552231 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8674 09:31:16.552881 == TX Byte 0 ==
8675 09:31:16.555454 u2DelayCellOfst[0]=17 cells (5 PI)
8676 09:31:16.558620 u2DelayCellOfst[1]=10 cells (3 PI)
8677 09:31:16.562000 u2DelayCellOfst[2]=0 cells (0 PI)
8678 09:31:16.565170 u2DelayCellOfst[3]=10 cells (3 PI)
8679 09:31:16.568115 u2DelayCellOfst[4]=10 cells (3 PI)
8680 09:31:16.571757 u2DelayCellOfst[5]=17 cells (5 PI)
8681 09:31:16.575139 u2DelayCellOfst[6]=17 cells (5 PI)
8682 09:31:16.578179 u2DelayCellOfst[7]=7 cells (2 PI)
8683 09:31:16.581426 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8684 09:31:16.585169 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8685 09:31:16.588663 == TX Byte 1 ==
8686 09:31:16.591852 u2DelayCellOfst[8]=0 cells (0 PI)
8687 09:31:16.595249 u2DelayCellOfst[9]=3 cells (1 PI)
8688 09:31:16.597992 u2DelayCellOfst[10]=10 cells (3 PI)
8689 09:31:16.598528 u2DelayCellOfst[11]=3 cells (1 PI)
8690 09:31:16.601437 u2DelayCellOfst[12]=14 cells (4 PI)
8691 09:31:16.604806 u2DelayCellOfst[13]=17 cells (5 PI)
8692 09:31:16.608086 u2DelayCellOfst[14]=17 cells (5 PI)
8693 09:31:16.611742 u2DelayCellOfst[15]=17 cells (5 PI)
8694 09:31:16.618518 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8695 09:31:16.621654 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8696 09:31:16.622235 DramC Write-DBI on
8697 09:31:16.622612 ==
8698 09:31:16.624981 Dram Type= 6, Freq= 0, CH_1, rank 1
8699 09:31:16.631820 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8700 09:31:16.632444 ==
8701 09:31:16.632825
8702 09:31:16.633173
8703 09:31:16.633503 TX Vref Scan disable
8704 09:31:16.635634 == TX Byte 0 ==
8705 09:31:16.638980 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8706 09:31:16.642414 == TX Byte 1 ==
8707 09:31:16.645326 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8708 09:31:16.648826 DramC Write-DBI off
8709 09:31:16.649293
8710 09:31:16.649663 [DATLAT]
8711 09:31:16.650008 Freq=1600, CH1 RK1
8712 09:31:16.650344
8713 09:31:16.652259 DATLAT Default: 0xe
8714 09:31:16.652772 0, 0xFFFF, sum = 0
8715 09:31:16.655697 1, 0xFFFF, sum = 0
8716 09:31:16.658819 2, 0xFFFF, sum = 0
8717 09:31:16.659582 3, 0xFFFF, sum = 0
8718 09:31:16.662286 4, 0xFFFF, sum = 0
8719 09:31:16.662874 5, 0xFFFF, sum = 0
8720 09:31:16.665258 6, 0xFFFF, sum = 0
8721 09:31:16.665738 7, 0xFFFF, sum = 0
8722 09:31:16.668960 8, 0xFFFF, sum = 0
8723 09:31:16.669437 9, 0xFFFF, sum = 0
8724 09:31:16.672244 10, 0xFFFF, sum = 0
8725 09:31:16.672757 11, 0xFFFF, sum = 0
8726 09:31:16.675708 12, 0xF5F, sum = 0
8727 09:31:16.676343 13, 0x0, sum = 1
8728 09:31:16.678914 14, 0x0, sum = 2
8729 09:31:16.679498 15, 0x0, sum = 3
8730 09:31:16.682126 16, 0x0, sum = 4
8731 09:31:16.682600 best_step = 14
8732 09:31:16.682974
8733 09:31:16.683318 ==
8734 09:31:16.685642 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 09:31:16.688870 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8736 09:31:16.689349 ==
8737 09:31:16.692562 RX Vref Scan: 0
8738 09:31:16.693137
8739 09:31:16.695441 RX Vref 0 -> 0, step: 1
8740 09:31:16.696023
8741 09:31:16.696466 RX Delay 3 -> 252, step: 4
8742 09:31:16.702475 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8743 09:31:16.705754 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8744 09:31:16.709017 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8745 09:31:16.712688 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8746 09:31:16.718976 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8747 09:31:16.722511 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8748 09:31:16.725491 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8749 09:31:16.729649 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8750 09:31:16.732245 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8751 09:31:16.739167 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8752 09:31:16.742308 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8753 09:31:16.745750 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8754 09:31:16.748744 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8755 09:31:16.752000 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8756 09:31:16.758683 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8757 09:31:16.762093 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8758 09:31:16.762683 ==
8759 09:31:16.765563 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 09:31:16.768460 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8761 09:31:16.768970 ==
8762 09:31:16.771802 DQS Delay:
8763 09:31:16.772632 DQS0 = 0, DQS1 = 0
8764 09:31:16.773100 DQM Delay:
8765 09:31:16.775377 DQM0 = 127, DQM1 = 122
8766 09:31:16.775849 DQ Delay:
8767 09:31:16.778470 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8768 09:31:16.781452 DQ4 =126, DQ5 =138, DQ6 =138, DQ7 =126
8769 09:31:16.788330 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8770 09:31:16.791395 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =130
8771 09:31:16.791869
8772 09:31:16.792294
8773 09:31:16.792651
8774 09:31:16.795282 [DramC_TX_OE_Calibration] TA2
8775 09:31:16.798475 Original DQ_B0 (3 6) =30, OEN = 27
8776 09:31:16.801521 Original DQ_B1 (3 6) =30, OEN = 27
8777 09:31:16.801994 24, 0x0, End_B0=24 End_B1=24
8778 09:31:16.804669 25, 0x0, End_B0=25 End_B1=25
8779 09:31:16.808208 26, 0x0, End_B0=26 End_B1=26
8780 09:31:16.811583 27, 0x0, End_B0=27 End_B1=27
8781 09:31:16.812240 28, 0x0, End_B0=28 End_B1=28
8782 09:31:16.814344 29, 0x0, End_B0=29 End_B1=29
8783 09:31:16.817815 30, 0x0, End_B0=30 End_B1=30
8784 09:31:16.821394 31, 0x4141, End_B0=30 End_B1=30
8785 09:31:16.824593 Byte0 end_step=30 best_step=27
8786 09:31:16.827915 Byte1 end_step=30 best_step=27
8787 09:31:16.828560 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 09:31:16.831094 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 09:31:16.831725
8790 09:31:16.832120
8791 09:31:16.841458 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8792 09:31:16.844515 CH1 RK1: MR19=303, MR18=1B1B
8793 09:31:16.847773 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8794 09:31:16.851024 [RxdqsGatingPostProcess] freq 1600
8795 09:31:16.857995 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8796 09:31:16.861061 Pre-setting of DQS Precalculation
8797 09:31:16.864616 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8798 09:31:16.874670 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8799 09:31:16.881342 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8800 09:31:16.881925
8801 09:31:16.882363
8802 09:31:16.884129 [Calibration Summary] 3200 Mbps
8803 09:31:16.884642 CH 0, Rank 0
8804 09:31:16.887847 SW Impedance : PASS
8805 09:31:16.888472 DUTY Scan : NO K
8806 09:31:16.890946 ZQ Calibration : PASS
8807 09:31:16.894655 Jitter Meter : NO K
8808 09:31:16.895230 CBT Training : PASS
8809 09:31:16.897636 Write leveling : PASS
8810 09:31:16.900718 RX DQS gating : PASS
8811 09:31:16.901190 RX DQ/DQS(RDDQC) : PASS
8812 09:31:16.903922 TX DQ/DQS : PASS
8813 09:31:16.907612 RX DATLAT : PASS
8814 09:31:16.908221 RX DQ/DQS(Engine): PASS
8815 09:31:16.910632 TX OE : PASS
8816 09:31:16.911106 All Pass.
8817 09:31:16.911480
8818 09:31:16.913864 CH 0, Rank 1
8819 09:31:16.914333 SW Impedance : PASS
8820 09:31:16.917392 DUTY Scan : NO K
8821 09:31:16.920732 ZQ Calibration : PASS
8822 09:31:16.921358 Jitter Meter : NO K
8823 09:31:16.923748 CBT Training : PASS
8824 09:31:16.926990 Write leveling : PASS
8825 09:31:16.927572 RX DQS gating : PASS
8826 09:31:16.930197 RX DQ/DQS(RDDQC) : PASS
8827 09:31:16.934001 TX DQ/DQS : PASS
8828 09:31:16.934577 RX DATLAT : PASS
8829 09:31:16.937168 RX DQ/DQS(Engine): PASS
8830 09:31:16.940842 TX OE : PASS
8831 09:31:16.941430 All Pass.
8832 09:31:16.941808
8833 09:31:16.942155 CH 1, Rank 0
8834 09:31:16.943953 SW Impedance : PASS
8835 09:31:16.944472 DUTY Scan : NO K
8836 09:31:16.947351 ZQ Calibration : PASS
8837 09:31:16.950300 Jitter Meter : NO K
8838 09:31:16.950769 CBT Training : PASS
8839 09:31:16.953527 Write leveling : PASS
8840 09:31:16.957236 RX DQS gating : PASS
8841 09:31:16.957819 RX DQ/DQS(RDDQC) : PASS
8842 09:31:16.960015 TX DQ/DQS : PASS
8843 09:31:16.963466 RX DATLAT : PASS
8844 09:31:16.963932 RX DQ/DQS(Engine): PASS
8845 09:31:16.966842 TX OE : PASS
8846 09:31:16.967312 All Pass.
8847 09:31:16.967680
8848 09:31:16.970135 CH 1, Rank 1
8849 09:31:16.970606 SW Impedance : PASS
8850 09:31:16.973956 DUTY Scan : NO K
8851 09:31:16.976666 ZQ Calibration : PASS
8852 09:31:16.977137 Jitter Meter : NO K
8853 09:31:16.980088 CBT Training : PASS
8854 09:31:16.983474 Write leveling : PASS
8855 09:31:16.984048 RX DQS gating : PASS
8856 09:31:16.986778 RX DQ/DQS(RDDQC) : PASS
8857 09:31:16.989782 TX DQ/DQS : PASS
8858 09:31:16.990258 RX DATLAT : PASS
8859 09:31:16.993535 RX DQ/DQS(Engine): PASS
8860 09:31:16.996449 TX OE : PASS
8861 09:31:16.996922 All Pass.
8862 09:31:16.997294
8863 09:31:16.997639 DramC Write-DBI on
8864 09:31:16.999519 PER_BANK_REFRESH: Hybrid Mode
8865 09:31:17.002860 TX_TRACKING: ON
8866 09:31:17.010019 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8867 09:31:17.019874 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8868 09:31:17.025929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8869 09:31:17.029408 [FAST_K] Save calibration result to emmc
8870 09:31:17.032714 sync common calibartion params.
8871 09:31:17.035662 sync cbt_mode0:0, 1:0
8872 09:31:17.036135 dram_init: ddr_geometry: 0
8873 09:31:17.038950 dram_init: ddr_geometry: 0
8874 09:31:17.042304 dram_init: ddr_geometry: 0
8875 09:31:17.045568 0:dram_rank_size:80000000
8876 09:31:17.046046 1:dram_rank_size:80000000
8877 09:31:17.052688 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8878 09:31:17.055855 DFS_SHUFFLE_HW_MODE: ON
8879 09:31:17.059327 dramc_set_vcore_voltage set vcore to 725000
8880 09:31:17.059896 Read voltage for 1600, 0
8881 09:31:17.062605 Vio18 = 0
8882 09:31:17.063177 Vcore = 725000
8883 09:31:17.063550 Vdram = 0
8884 09:31:17.065655 Vddq = 0
8885 09:31:17.066226 Vmddr = 0
8886 09:31:17.069093 switch to 3200 Mbps bootup
8887 09:31:17.069607 [DramcRunTimeConfig]
8888 09:31:17.069987 PHYPLL
8889 09:31:17.072631 DPM_CONTROL_AFTERK: ON
8890 09:31:17.076115 PER_BANK_REFRESH: ON
8891 09:31:17.076746 REFRESH_OVERHEAD_REDUCTION: ON
8892 09:31:17.078811 CMD_PICG_NEW_MODE: OFF
8893 09:31:17.082247 XRTWTW_NEW_MODE: ON
8894 09:31:17.082829 XRTRTR_NEW_MODE: ON
8895 09:31:17.085524 TX_TRACKING: ON
8896 09:31:17.086104 RDSEL_TRACKING: OFF
8897 09:31:17.089394 DQS Precalculation for DVFS: ON
8898 09:31:17.091932 RX_TRACKING: OFF
8899 09:31:17.092444 HW_GATING DBG: ON
8900 09:31:17.095607 ZQCS_ENABLE_LP4: ON
8901 09:31:17.096216 RX_PICG_NEW_MODE: ON
8902 09:31:17.098792 TX_PICG_NEW_MODE: ON
8903 09:31:17.099307 ENABLE_RX_DCM_DPHY: ON
8904 09:31:17.102100 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8905 09:31:17.105599 DUMMY_READ_FOR_TRACKING: OFF
8906 09:31:17.108890 !!! SPM_CONTROL_AFTERK: OFF
8907 09:31:17.111778 !!! SPM could not control APHY
8908 09:31:17.112330 IMPEDANCE_TRACKING: ON
8909 09:31:17.115430 TEMP_SENSOR: ON
8910 09:31:17.116009 HW_SAVE_FOR_SR: OFF
8911 09:31:17.118489 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8912 09:31:17.122350 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8913 09:31:17.125285 Read ODT Tracking: ON
8914 09:31:17.128622 Refresh Rate DeBounce: ON
8915 09:31:17.129201 DFS_NO_QUEUE_FLUSH: ON
8916 09:31:17.132039 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8917 09:31:17.135008 ENABLE_DFS_RUNTIME_MRW: OFF
8918 09:31:17.138955 DDR_RESERVE_NEW_MODE: ON
8919 09:31:17.139531 MR_CBT_SWITCH_FREQ: ON
8920 09:31:17.142044 =========================
8921 09:31:17.160106 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8922 09:31:17.163561 dram_init: ddr_geometry: 0
8923 09:31:17.181340 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8924 09:31:17.184793 dram_init: dram init end (result: 0)
8925 09:31:17.191371 DRAM-K: Full calibration passed in 23418 msecs
8926 09:31:17.194940 MRC: failed to locate region type 0.
8927 09:31:17.195516 DRAM rank0 size:0x80000000,
8928 09:31:17.198026 DRAM rank1 size=0x80000000
8929 09:31:17.208062 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8930 09:31:17.214843 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8931 09:31:17.220821 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8932 09:31:17.227775 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8933 09:31:17.231272 DRAM rank0 size:0x80000000,
8934 09:31:17.234475 DRAM rank1 size=0x80000000
8935 09:31:17.235048 CBMEM:
8936 09:31:17.237529 IMD: root @ 0xfffff000 254 entries.
8937 09:31:17.241140 IMD: root @ 0xffffec00 62 entries.
8938 09:31:17.244654 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8939 09:31:17.247641 WARNING: RO_VPD is uninitialized or empty.
8940 09:31:17.253996 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8941 09:31:17.260982 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8942 09:31:17.273721 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8943 09:31:17.285387 BS: romstage times (exec / console): total (unknown) / 22962 ms
8944 09:31:17.285961
8945 09:31:17.286334
8946 09:31:17.295464 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8947 09:31:17.299047 ARM64: Exception handlers installed.
8948 09:31:17.302358 ARM64: Testing exception
8949 09:31:17.305563 ARM64: Done test exception
8950 09:31:17.306140 Enumerating buses...
8951 09:31:17.308583 Show all devs... Before device enumeration.
8952 09:31:17.312261 Root Device: enabled 1
8953 09:31:17.315266 CPU_CLUSTER: 0: enabled 1
8954 09:31:17.315839 CPU: 00: enabled 1
8955 09:31:17.318679 Compare with tree...
8956 09:31:17.319259 Root Device: enabled 1
8957 09:31:17.321889 CPU_CLUSTER: 0: enabled 1
8958 09:31:17.325069 CPU: 00: enabled 1
8959 09:31:17.325539 Root Device scanning...
8960 09:31:17.328579 scan_static_bus for Root Device
8961 09:31:17.331989 CPU_CLUSTER: 0 enabled
8962 09:31:17.334909 scan_static_bus for Root Device done
8963 09:31:17.338679 scan_bus: bus Root Device finished in 8 msecs
8964 09:31:17.339253 done
8965 09:31:17.345398 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8966 09:31:17.348061 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8967 09:31:17.354982 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8968 09:31:17.358297 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8969 09:31:17.361627 Allocating resources...
8970 09:31:17.364963 Reading resources...
8971 09:31:17.368330 Root Device read_resources bus 0 link: 0
8972 09:31:17.368908 DRAM rank0 size:0x80000000,
8973 09:31:17.371241 DRAM rank1 size=0x80000000
8974 09:31:17.375028 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8975 09:31:17.378158 CPU: 00 missing read_resources
8976 09:31:17.381314 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8977 09:31:17.388057 Root Device read_resources bus 0 link: 0 done
8978 09:31:17.388687 Done reading resources.
8979 09:31:17.394885 Show resources in subtree (Root Device)...After reading.
8980 09:31:17.398345 Root Device child on link 0 CPU_CLUSTER: 0
8981 09:31:17.401346 CPU_CLUSTER: 0 child on link 0 CPU: 00
8982 09:31:17.411717 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8983 09:31:17.412395 CPU: 00
8984 09:31:17.414646 Root Device assign_resources, bus 0 link: 0
8985 09:31:17.417903 CPU_CLUSTER: 0 missing set_resources
8986 09:31:17.421564 Root Device assign_resources, bus 0 link: 0 done
8987 09:31:17.424746 Done setting resources.
8988 09:31:17.431491 Show resources in subtree (Root Device)...After assigning values.
8989 09:31:17.434723 Root Device child on link 0 CPU_CLUSTER: 0
8990 09:31:17.438163 CPU_CLUSTER: 0 child on link 0 CPU: 00
8991 09:31:17.447899 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8992 09:31:17.448518 CPU: 00
8993 09:31:17.451206 Done allocating resources.
8994 09:31:17.454131 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8995 09:31:17.457843 Enabling resources...
8996 09:31:17.458422 done.
8997 09:31:17.464552 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8998 09:31:17.465129 Initializing devices...
8999 09:31:17.467507 Root Device init
9000 09:31:17.468084 init hardware done!
9001 09:31:17.470465 0x00000018: ctrlr->caps
9002 09:31:17.474361 52.000 MHz: ctrlr->f_max
9003 09:31:17.474950 0.400 MHz: ctrlr->f_min
9004 09:31:17.477571 0x40ff8080: ctrlr->voltages
9005 09:31:17.478164 sclk: 390625
9006 09:31:17.480690 Bus Width = 1
9007 09:31:17.481159 sclk: 390625
9008 09:31:17.483832 Bus Width = 1
9009 09:31:17.484344 Early init status = 3
9010 09:31:17.490766 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9011 09:31:17.494190 in-header: 03 fc 00 00 01 00 00 00
9012 09:31:17.497324 in-data: 00
9013 09:31:17.500461 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9014 09:31:17.506077 in-header: 03 fd 00 00 00 00 00 00
9015 09:31:17.509006 in-data:
9016 09:31:17.512737 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9017 09:31:17.516921 in-header: 03 fc 00 00 01 00 00 00
9018 09:31:17.520231 in-data: 00
9019 09:31:17.523678 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9020 09:31:17.529119 in-header: 03 fd 00 00 00 00 00 00
9021 09:31:17.533039 in-data:
9022 09:31:17.536348 [SSUSB] Setting up USB HOST controller...
9023 09:31:17.539362 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9024 09:31:17.542855 [SSUSB] phy power-on done.
9025 09:31:17.545999 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9026 09:31:17.552726 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9027 09:31:17.555606 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9028 09:31:17.563080 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9029 09:31:17.569124 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9030 09:31:17.575786 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9031 09:31:17.582521 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9032 09:31:17.589143 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9033 09:31:17.592350 SPM: binary array size = 0x9dc
9034 09:31:17.595819 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9035 09:31:17.602425 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9036 09:31:17.608962 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9037 09:31:17.612294 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9038 09:31:17.618750 configure_display: Starting display init
9039 09:31:17.652601 anx7625_power_on_init: Init interface.
9040 09:31:17.656086 anx7625_disable_pd_protocol: Disabled PD feature.
9041 09:31:17.659051 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9042 09:31:17.687351 anx7625_start_dp_work: Secure OCM version=00
9043 09:31:17.690253 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9044 09:31:17.705128 sp_tx_get_edid_block: EDID Block = 1
9045 09:31:17.807780 Extracted contents:
9046 09:31:17.811134 header: 00 ff ff ff ff ff ff 00
9047 09:31:17.814690 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9048 09:31:17.817566 version: 01 04
9049 09:31:17.820905 basic params: 95 1f 11 78 0a
9050 09:31:17.824818 chroma info: 76 90 94 55 54 90 27 21 50 54
9051 09:31:17.827878 established: 00 00 00
9052 09:31:17.834288 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9053 09:31:17.837396 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9054 09:31:17.843977 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9055 09:31:17.850572 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9056 09:31:17.857385 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9057 09:31:17.860380 extensions: 00
9058 09:31:17.860853 checksum: fb
9059 09:31:17.861226
9060 09:31:17.863882 Manufacturer: IVO Model 57d Serial Number 0
9061 09:31:17.867169 Made week 0 of 2020
9062 09:31:17.867749 EDID version: 1.4
9063 09:31:17.870589 Digital display
9064 09:31:17.873566 6 bits per primary color channel
9065 09:31:17.874050 DisplayPort interface
9066 09:31:17.876918 Maximum image size: 31 cm x 17 cm
9067 09:31:17.880130 Gamma: 220%
9068 09:31:17.880652 Check DPMS levels
9069 09:31:17.883500 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9070 09:31:17.890209 First detailed timing is preferred timing
9071 09:31:17.890685 Established timings supported:
9072 09:31:17.893494 Standard timings supported:
9073 09:31:17.897229 Detailed timings
9074 09:31:17.900066 Hex of detail: 383680a07038204018303c0035ae10000019
9075 09:31:17.906926 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9076 09:31:17.910024 0780 0798 07c8 0820 hborder 0
9077 09:31:17.913378 0438 043b 0447 0458 vborder 0
9078 09:31:17.916672 -hsync -vsync
9079 09:31:17.917143 Did detailed timing
9080 09:31:17.923651 Hex of detail: 000000000000000000000000000000000000
9081 09:31:17.926359 Manufacturer-specified data, tag 0
9082 09:31:17.930345 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9083 09:31:17.933255 ASCII string: InfoVision
9084 09:31:17.936553 Hex of detail: 000000fe00523134304e574635205248200a
9085 09:31:17.940070 ASCII string: R140NWF5 RH
9086 09:31:17.940676 Checksum
9087 09:31:17.943549 Checksum: 0xfb (valid)
9088 09:31:17.946452 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9089 09:31:17.949705 DSI data_rate: 832800000 bps
9090 09:31:17.956211 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9091 09:31:17.959829 anx7625_parse_edid: pixelclock(138800).
9092 09:31:17.963039 hactive(1920), hsync(48), hfp(24), hbp(88)
9093 09:31:17.966257 vactive(1080), vsync(12), vfp(3), vbp(17)
9094 09:31:17.969836 anx7625_dsi_config: config dsi.
9095 09:31:17.976008 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9096 09:31:17.989594 anx7625_dsi_config: success to config DSI
9097 09:31:17.992819 anx7625_dp_start: MIPI phy setup OK.
9098 09:31:17.996428 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9099 09:31:17.999526 mtk_ddp_mode_set invalid vrefresh 60
9100 09:31:18.002944 main_disp_path_setup
9101 09:31:18.003472 ovl_layer_smi_id_en
9102 09:31:18.005987 ovl_layer_smi_id_en
9103 09:31:18.006457 ccorr_config
9104 09:31:18.006826 aal_config
9105 09:31:18.009670 gamma_config
9106 09:31:18.010377 postmask_config
9107 09:31:18.012724 dither_config
9108 09:31:18.016237 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9109 09:31:18.023127 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9110 09:31:18.026366 Root Device init finished in 555 msecs
9111 09:31:18.029669 CPU_CLUSTER: 0 init
9112 09:31:18.036428 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9113 09:31:18.039460 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9114 09:31:18.042838 APU_MBOX 0x190000b0 = 0x10001
9115 09:31:18.046203 APU_MBOX 0x190001b0 = 0x10001
9116 09:31:18.049146 APU_MBOX 0x190005b0 = 0x10001
9117 09:31:18.052586 APU_MBOX 0x190006b0 = 0x10001
9118 09:31:18.056152 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9119 09:31:18.068370 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9120 09:31:18.080896 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9121 09:31:18.087677 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9122 09:31:18.099503 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9123 09:31:18.108601 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9124 09:31:18.111856 CPU_CLUSTER: 0 init finished in 81 msecs
9125 09:31:18.114942 Devices initialized
9126 09:31:18.118558 Show all devs... After init.
9127 09:31:18.119129 Root Device: enabled 1
9128 09:31:18.121690 CPU_CLUSTER: 0: enabled 1
9129 09:31:18.124891 CPU: 00: enabled 1
9130 09:31:18.128706 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9131 09:31:18.131630 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9132 09:31:18.135362 ELOG: NV offset 0x57f000 size 0x1000
9133 09:31:18.141749 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9134 09:31:18.148328 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9135 09:31:18.151351 ELOG: Event(17) added with size 13 at 2023-10-20 09:31:18 UTC
9136 09:31:18.158037 out: cmd=0x121: 03 db 21 01 00 00 00 00
9137 09:31:18.161261 in-header: 03 f5 00 00 2c 00 00 00
9138 09:31:18.174477 in-data: 6e 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9139 09:31:18.177960 ELOG: Event(A1) added with size 10 at 2023-10-20 09:31:18 UTC
9140 09:31:18.184394 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9141 09:31:18.191418 ELOG: Event(A0) added with size 9 at 2023-10-20 09:31:18 UTC
9142 09:31:18.194184 elog_add_boot_reason: Logged dev mode boot
9143 09:31:18.200923 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9144 09:31:18.201706 Finalize devices...
9145 09:31:18.203948 Devices finalized
9146 09:31:18.207645 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9147 09:31:18.210936 Writing coreboot table at 0xffe64000
9148 09:31:18.217747 0. 000000000010a000-0000000000113fff: RAMSTAGE
9149 09:31:18.221367 1. 0000000040000000-00000000400fffff: RAM
9150 09:31:18.224333 2. 0000000040100000-000000004032afff: RAMSTAGE
9151 09:31:18.227091 3. 000000004032b000-00000000545fffff: RAM
9152 09:31:18.230775 4. 0000000054600000-000000005465ffff: BL31
9153 09:31:18.234396 5. 0000000054660000-00000000ffe63fff: RAM
9154 09:31:18.240924 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9155 09:31:18.244110 7. 0000000100000000-000000013fffffff: RAM
9156 09:31:18.247416 Passing 5 GPIOs to payload:
9157 09:31:18.250277 NAME | PORT | POLARITY | VALUE
9158 09:31:18.257007 EC in RW | 0x000000aa | low | undefined
9159 09:31:18.260705 EC interrupt | 0x00000005 | low | undefined
9160 09:31:18.267373 TPM interrupt | 0x000000ab | high | undefined
9161 09:31:18.270621 SD card detect | 0x00000011 | high | undefined
9162 09:31:18.273676 speaker enable | 0x00000093 | high | undefined
9163 09:31:18.280357 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9164 09:31:18.283758 in-header: 03 f8 00 00 02 00 00 00
9165 09:31:18.284626 in-data: 03 00
9166 09:31:18.286941 ADC[4]: Raw value=669327 ID=5
9167 09:31:18.290014 ADC[3]: Raw value=212917 ID=1
9168 09:31:18.290494 RAM Code: 0x51
9169 09:31:18.293227 ADC[6]: Raw value=74778 ID=0
9170 09:31:18.296488 ADC[5]: Raw value=211812 ID=1
9171 09:31:18.296965 SKU Code: 0x1
9172 09:31:18.303290 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 163b
9173 09:31:18.303768 coreboot table: 964 bytes.
9174 09:31:18.306490 IMD ROOT 0. 0xfffff000 0x00001000
9175 09:31:18.310309 IMD SMALL 1. 0xffffe000 0x00001000
9176 09:31:18.313063 RO MCACHE 2. 0xffffc000 0x00001104
9177 09:31:18.316424 CONSOLE 3. 0xfff7c000 0x00080000
9178 09:31:18.320020 FMAP 4. 0xfff7b000 0x00000452
9179 09:31:18.323171 TIME STAMP 5. 0xfff7a000 0x00000910
9180 09:31:18.326721 VBOOT WORK 6. 0xfff66000 0x00014000
9181 09:31:18.330142 RAMOOPS 7. 0xffe66000 0x00100000
9182 09:31:18.333149 COREBOOT 8. 0xffe64000 0x00002000
9183 09:31:18.336549 IMD small region:
9184 09:31:18.339766 IMD ROOT 0. 0xffffec00 0x00000400
9185 09:31:18.343480 VPD 1. 0xffffeb80 0x0000006c
9186 09:31:18.346278 MMC STATUS 2. 0xffffeb60 0x00000004
9187 09:31:18.353030 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9188 09:31:18.353553 Probing TPM: done!
9189 09:31:18.360314 Connected to device vid:did:rid of 1ae0:0028:00
9190 09:31:18.366732 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9191 09:31:18.369718 Initialized TPM device CR50 revision 0
9192 09:31:18.373150 Checking cr50 for pending updates
9193 09:31:18.378972 Reading cr50 TPM mode
9194 09:31:18.387381 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9195 09:31:18.393954 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9196 09:31:18.434085 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9197 09:31:18.437284 Checking segment from ROM address 0x40100000
9198 09:31:18.441149 Checking segment from ROM address 0x4010001c
9199 09:31:18.447405 Loading segment from ROM address 0x40100000
9200 09:31:18.447982 code (compression=0)
9201 09:31:18.457456 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9202 09:31:18.464311 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9203 09:31:18.464891 it's not compressed!
9204 09:31:18.471040 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9205 09:31:18.474102 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9206 09:31:18.494534 Loading segment from ROM address 0x4010001c
9207 09:31:18.495113 Entry Point 0x80000000
9208 09:31:18.497727 Loaded segments
9209 09:31:18.500937 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9210 09:31:18.507918 Jumping to boot code at 0x80000000(0xffe64000)
9211 09:31:18.514716 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9212 09:31:18.520986 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9213 09:31:18.528897 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9214 09:31:18.532335 Checking segment from ROM address 0x40100000
9215 09:31:18.535905 Checking segment from ROM address 0x4010001c
9216 09:31:18.542409 Loading segment from ROM address 0x40100000
9217 09:31:18.542982 code (compression=1)
9218 09:31:18.548784 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9219 09:31:18.559150 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9220 09:31:18.559729 using LZMA
9221 09:31:18.567314 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9222 09:31:18.573699 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9223 09:31:18.577367 Loading segment from ROM address 0x4010001c
9224 09:31:18.577858 Entry Point 0x54601000
9225 09:31:18.580382 Loaded segments
9226 09:31:18.584135 NOTICE: MT8192 bl31_setup
9227 09:31:18.591015 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9228 09:31:18.594096 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9229 09:31:18.597542 WARNING: region 0:
9230 09:31:18.600400 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9231 09:31:18.600877 WARNING: region 1:
9232 09:31:18.607115 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9233 09:31:18.610809 WARNING: region 2:
9234 09:31:18.614101 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9235 09:31:18.617211 WARNING: region 3:
9236 09:31:18.620507 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9237 09:31:18.624163 WARNING: region 4:
9238 09:31:18.630679 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9239 09:31:18.631289 WARNING: region 5:
9240 09:31:18.633979 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 09:31:18.637335 WARNING: region 6:
9242 09:31:18.640616 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9243 09:31:18.643931 WARNING: region 7:
9244 09:31:18.647189 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9245 09:31:18.653655 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9246 09:31:18.657031 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9247 09:31:18.660729 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9248 09:31:18.666864 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9249 09:31:18.670316 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9250 09:31:18.677213 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9251 09:31:18.680467 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9252 09:31:18.683943 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9253 09:31:18.690246 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9254 09:31:18.693464 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9255 09:31:18.696866 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9256 09:31:18.703679 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9257 09:31:18.707020 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9258 09:31:18.710325 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9259 09:31:18.716872 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9260 09:31:18.720421 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9261 09:31:18.726914 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9262 09:31:18.730179 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9263 09:31:18.733498 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9264 09:31:18.740620 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9265 09:31:18.743502 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9266 09:31:18.750404 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9267 09:31:18.753622 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9268 09:31:18.757141 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9269 09:31:18.763627 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9270 09:31:18.766620 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9271 09:31:18.773183 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9272 09:31:18.776809 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9273 09:31:18.779822 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9274 09:31:18.786528 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9275 09:31:18.790129 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9276 09:31:18.796889 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9277 09:31:18.800006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9278 09:31:18.803194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9279 09:31:18.806540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9280 09:31:18.810123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9281 09:31:18.816590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9282 09:31:18.820115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9283 09:31:18.823500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9284 09:31:18.826817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9285 09:31:18.833381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9286 09:31:18.836732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9287 09:31:18.840505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9288 09:31:18.843765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9289 09:31:18.850065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9290 09:31:18.853588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9291 09:31:18.857034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9292 09:31:18.863625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9293 09:31:18.866852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9294 09:31:18.870586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9295 09:31:18.877139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9296 09:31:18.880209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9297 09:31:18.886851 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9298 09:31:18.889915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9299 09:31:18.893229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9300 09:31:18.900163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9301 09:31:18.903572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9302 09:31:18.910282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9303 09:31:18.913516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9304 09:31:18.919952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9305 09:31:18.923457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9306 09:31:18.926845 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9307 09:31:18.933799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9308 09:31:18.936799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9309 09:31:18.943720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9310 09:31:18.947157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9311 09:31:18.953393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9312 09:31:18.956871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9313 09:31:18.963592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9314 09:31:18.966881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9315 09:31:18.970337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9316 09:31:18.976894 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9317 09:31:18.980212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9318 09:31:18.986934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9319 09:31:18.990269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9320 09:31:18.993393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9321 09:31:19.000457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9322 09:31:19.003760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9323 09:31:19.010166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9324 09:31:19.013727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9325 09:31:19.020686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9326 09:31:19.023884 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9327 09:31:19.026889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9328 09:31:19.033609 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9329 09:31:19.037422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9330 09:31:19.043834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9331 09:31:19.047040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9332 09:31:19.053601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9333 09:31:19.057153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9334 09:31:19.060399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9335 09:31:19.067355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9336 09:31:19.070774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9337 09:31:19.076761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9338 09:31:19.080302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9339 09:31:19.087189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9340 09:31:19.090702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9341 09:31:19.094149 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9342 09:31:19.100816 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9343 09:31:19.104099 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9344 09:31:19.107436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9345 09:31:19.110455 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9346 09:31:19.117131 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9347 09:31:19.120443 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9348 09:31:19.127262 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9349 09:31:19.130458 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9350 09:31:19.133530 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9351 09:31:19.140571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9352 09:31:19.143676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9353 09:31:19.150519 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9354 09:31:19.153394 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9355 09:31:19.157121 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9356 09:31:19.163702 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9357 09:31:19.166887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9358 09:31:19.173512 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9359 09:31:19.176811 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9360 09:31:19.180127 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9361 09:31:19.183592 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9362 09:31:19.190298 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9363 09:31:19.193737 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9364 09:31:19.196751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9365 09:31:19.203237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9366 09:31:19.207176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9367 09:31:19.210627 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9368 09:31:19.213654 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9369 09:31:19.220545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9370 09:31:19.223485 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9371 09:31:19.229938 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9372 09:31:19.233393 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9373 09:31:19.237014 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9374 09:31:19.243855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9375 09:31:19.246806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9376 09:31:19.253623 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9377 09:31:19.256851 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9378 09:31:19.260110 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9379 09:31:19.267164 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9380 09:31:19.270436 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9381 09:31:19.273877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9382 09:31:19.279992 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9383 09:31:19.283423 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9384 09:31:19.290070 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9385 09:31:19.293829 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9386 09:31:19.296642 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9387 09:31:19.303938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9388 09:31:19.307139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9389 09:31:19.313739 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9390 09:31:19.317184 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9391 09:31:19.320328 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9392 09:31:19.326764 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9393 09:31:19.330016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9394 09:31:19.336712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9395 09:31:19.340559 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9396 09:31:19.343560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9397 09:31:19.350255 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9398 09:31:19.353506 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9399 09:31:19.357204 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9400 09:31:19.363860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9401 09:31:19.366969 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9402 09:31:19.373819 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9403 09:31:19.377109 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9404 09:31:19.380093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9405 09:31:19.387033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9406 09:31:19.389986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9407 09:31:19.393294 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9408 09:31:19.400391 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9409 09:31:19.403539 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9410 09:31:19.410013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9411 09:31:19.413511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9412 09:31:19.416605 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9413 09:31:19.423472 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9414 09:31:19.427013 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9415 09:31:19.433109 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9416 09:31:19.436892 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9417 09:31:19.439883 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9418 09:31:19.446793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9419 09:31:19.449868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9420 09:31:19.456527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9421 09:31:19.460095 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9422 09:31:19.463246 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9423 09:31:19.470081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9424 09:31:19.473182 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9425 09:31:19.476466 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9426 09:31:19.482948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9427 09:31:19.486586 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9428 09:31:19.492895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9429 09:31:19.496238 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9430 09:31:19.502897 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9431 09:31:19.506453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9432 09:31:19.509940 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9433 09:31:19.516027 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9434 09:31:19.519558 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9435 09:31:19.526373 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9436 09:31:19.529394 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9437 09:31:19.532900 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9438 09:31:19.539591 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9439 09:31:19.542981 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9440 09:31:19.549259 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9441 09:31:19.552824 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9442 09:31:19.559596 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9443 09:31:19.562716 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9444 09:31:19.565576 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9445 09:31:19.572973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9446 09:31:19.575942 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9447 09:31:19.582180 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9448 09:31:19.585730 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9449 09:31:19.592123 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9450 09:31:19.595679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9451 09:31:19.599043 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9452 09:31:19.605391 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9453 09:31:19.608732 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9454 09:31:19.615388 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9455 09:31:19.618438 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9456 09:31:19.622201 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9457 09:31:19.628740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9458 09:31:19.631702 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9459 09:31:19.638590 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9460 09:31:19.642257 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9461 09:31:19.648878 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9462 09:31:19.652318 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9463 09:31:19.654879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9464 09:31:19.661969 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9465 09:31:19.665097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9466 09:31:19.671856 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9467 09:31:19.675251 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9468 09:31:19.678253 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9469 09:31:19.684801 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9470 09:31:19.687836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9471 09:31:19.695137 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9472 09:31:19.697721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9473 09:31:19.704488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9474 09:31:19.707974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9475 09:31:19.711195 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9476 09:31:19.714963 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9477 09:31:19.720890 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9478 09:31:19.724257 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9479 09:31:19.728057 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9480 09:31:19.734587 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9481 09:31:19.737781 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9482 09:31:19.741230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9483 09:31:19.747674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9484 09:31:19.751034 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9485 09:31:19.754225 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9486 09:31:19.760885 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9487 09:31:19.764148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9488 09:31:19.767524 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9489 09:31:19.774346 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9490 09:31:19.777503 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9491 09:31:19.783788 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9492 09:31:19.787255 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9493 09:31:19.790700 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9494 09:31:19.796837 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9495 09:31:19.800328 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9496 09:31:19.807235 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9497 09:31:19.810286 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9498 09:31:19.813674 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9499 09:31:19.820169 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9500 09:31:19.823395 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9501 09:31:19.826733 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9502 09:31:19.833686 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9503 09:31:19.837047 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9504 09:31:19.840653 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9505 09:31:19.846694 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9506 09:31:19.850411 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9507 09:31:19.856696 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9508 09:31:19.859880 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9509 09:31:19.863209 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9510 09:31:19.870013 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9511 09:31:19.873076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9512 09:31:19.880242 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9513 09:31:19.882983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9514 09:31:19.886263 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9515 09:31:19.889879 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9516 09:31:19.892772 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9517 09:31:19.899584 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9518 09:31:19.903151 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9519 09:31:19.906324 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9520 09:31:19.909348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9521 09:31:19.916248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9522 09:31:19.919559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9523 09:31:19.922790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9524 09:31:19.926061 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9525 09:31:19.932659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9526 09:31:19.936059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9527 09:31:19.939227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9528 09:31:19.945984 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9529 09:31:19.949104 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9530 09:31:19.955907 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9531 09:31:19.959364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9532 09:31:19.965944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9533 09:31:19.969236 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9534 09:31:19.972761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9535 09:31:19.979082 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9536 09:31:19.982584 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9537 09:31:19.988767 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9538 09:31:19.992455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9539 09:31:19.995815 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9540 09:31:20.002329 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9541 09:31:20.005469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9542 09:31:20.012463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9543 09:31:20.015512 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9544 09:31:20.018700 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9545 09:31:20.025371 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9546 09:31:20.028705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9547 09:31:20.035601 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9548 09:31:20.038712 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9549 09:31:20.045344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9550 09:31:20.048781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9551 09:31:20.051981 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9552 09:31:20.058337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9553 09:31:20.061784 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9554 09:31:20.068322 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9555 09:31:20.072052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9556 09:31:20.075036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9557 09:31:20.081304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9558 09:31:20.084758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9559 09:31:20.091279 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9560 09:31:20.094694 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9561 09:31:20.098376 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9562 09:31:20.104997 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9563 09:31:20.108241 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9564 09:31:20.114982 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9565 09:31:20.118116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9566 09:31:20.121338 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9567 09:31:20.128139 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9568 09:31:20.131177 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9569 09:31:20.137697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9570 09:31:20.141145 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9571 09:31:20.148054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9572 09:31:20.151406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9573 09:31:20.154486 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9574 09:31:20.161016 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9575 09:31:20.164680 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9576 09:31:20.171323 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9577 09:31:20.174518 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9578 09:31:20.177803 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9579 09:31:20.184329 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9580 09:31:20.187469 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9581 09:31:20.194009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9582 09:31:20.197272 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9583 09:31:20.200768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9584 09:31:20.207332 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9585 09:31:20.211157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9586 09:31:20.217232 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9587 09:31:20.220952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9588 09:31:20.227487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9589 09:31:20.230877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9590 09:31:20.233858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9591 09:31:20.240846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9592 09:31:20.244059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9593 09:31:20.250423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9594 09:31:20.253944 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9595 09:31:20.260499 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9596 09:31:20.263935 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9597 09:31:20.266986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9598 09:31:20.273502 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9599 09:31:20.277202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9600 09:31:20.283924 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9601 09:31:20.286720 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9602 09:31:20.290217 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9603 09:31:20.296642 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9604 09:31:20.299911 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9605 09:31:20.306786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9606 09:31:20.309738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9607 09:31:20.317006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9608 09:31:20.320047 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9609 09:31:20.326718 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9610 09:31:20.330119 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9611 09:31:20.333425 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9612 09:31:20.340160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9613 09:31:20.343131 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9614 09:31:20.349753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9615 09:31:20.353111 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9616 09:31:20.359777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9617 09:31:20.363145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9618 09:31:20.369751 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9619 09:31:20.373023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9620 09:31:20.376382 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9621 09:31:20.382933 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9622 09:31:20.386051 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9623 09:31:20.392975 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9624 09:31:20.396273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9625 09:31:20.399398 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9626 09:31:20.406116 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9627 09:31:20.409326 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9628 09:31:20.416029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9629 09:31:20.419452 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9630 09:31:20.425846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9631 09:31:20.429331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9632 09:31:20.436259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9633 09:31:20.439502 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9634 09:31:20.442829 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9635 09:31:20.449390 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9636 09:31:20.452552 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9637 09:31:20.459442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9638 09:31:20.462331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9639 09:31:20.469049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9640 09:31:20.472447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9641 09:31:20.479272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9642 09:31:20.482273 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9643 09:31:20.485926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9644 09:31:20.492215 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9645 09:31:20.495775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9646 09:31:20.502373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9647 09:31:20.505173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9648 09:31:20.508564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9649 09:31:20.514989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9650 09:31:20.518722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9651 09:31:20.525391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9652 09:31:20.528530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9653 09:31:20.535630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9654 09:31:20.538840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9655 09:31:20.545172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9656 09:31:20.548265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9657 09:31:20.554801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9658 09:31:20.558493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9659 09:31:20.564836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9660 09:31:20.568145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9661 09:31:20.575124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9662 09:31:20.578285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9663 09:31:20.585172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9664 09:31:20.587995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9665 09:31:20.594842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9666 09:31:20.598148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9667 09:31:20.604690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9668 09:31:20.607893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9669 09:31:20.614788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9670 09:31:20.617861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9671 09:31:20.624817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9672 09:31:20.628004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9673 09:31:20.634948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9674 09:31:20.637809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9675 09:31:20.644759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9676 09:31:20.647940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9677 09:31:20.654610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9678 09:31:20.657677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9679 09:31:20.661135 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9680 09:31:20.664597 INFO: [APUAPC] vio 0
9681 09:31:20.671053 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9682 09:31:20.674294 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9683 09:31:20.677896 INFO: [APUAPC] D0_APC_0: 0x400510
9684 09:31:20.680981 INFO: [APUAPC] D0_APC_1: 0x0
9685 09:31:20.684333 INFO: [APUAPC] D0_APC_2: 0x1540
9686 09:31:20.687504 INFO: [APUAPC] D0_APC_3: 0x0
9687 09:31:20.690499 INFO: [APUAPC] D1_APC_0: 0xffffffff
9688 09:31:20.693942 INFO: [APUAPC] D1_APC_1: 0xffffffff
9689 09:31:20.697232 INFO: [APUAPC] D1_APC_2: 0x3fffff
9690 09:31:20.700611 INFO: [APUAPC] D1_APC_3: 0x0
9691 09:31:20.703799 INFO: [APUAPC] D2_APC_0: 0xffffffff
9692 09:31:20.707171 INFO: [APUAPC] D2_APC_1: 0xffffffff
9693 09:31:20.710335 INFO: [APUAPC] D2_APC_2: 0x3fffff
9694 09:31:20.714056 INFO: [APUAPC] D2_APC_3: 0x0
9695 09:31:20.716861 INFO: [APUAPC] D3_APC_0: 0xffffffff
9696 09:31:20.720394 INFO: [APUAPC] D3_APC_1: 0xffffffff
9697 09:31:20.723865 INFO: [APUAPC] D3_APC_2: 0x3fffff
9698 09:31:20.726800 INFO: [APUAPC] D3_APC_3: 0x0
9699 09:31:20.730545 INFO: [APUAPC] D4_APC_0: 0xffffffff
9700 09:31:20.733377 INFO: [APUAPC] D4_APC_1: 0xffffffff
9701 09:31:20.736668 INFO: [APUAPC] D4_APC_2: 0x3fffff
9702 09:31:20.737093 INFO: [APUAPC] D4_APC_3: 0x0
9703 09:31:20.740120 INFO: [APUAPC] D5_APC_0: 0xffffffff
9704 09:31:20.746620 INFO: [APUAPC] D5_APC_1: 0xffffffff
9705 09:31:20.750141 INFO: [APUAPC] D5_APC_2: 0x3fffff
9706 09:31:20.750601 INFO: [APUAPC] D5_APC_3: 0x0
9707 09:31:20.753414 INFO: [APUAPC] D6_APC_0: 0xffffffff
9708 09:31:20.756870 INFO: [APUAPC] D6_APC_1: 0xffffffff
9709 09:31:20.760046 INFO: [APUAPC] D6_APC_2: 0x3fffff
9710 09:31:20.763383 INFO: [APUAPC] D6_APC_3: 0x0
9711 09:31:20.766697 INFO: [APUAPC] D7_APC_0: 0xffffffff
9712 09:31:20.769937 INFO: [APUAPC] D7_APC_1: 0xffffffff
9713 09:31:20.773113 INFO: [APUAPC] D7_APC_2: 0x3fffff
9714 09:31:20.776691 INFO: [APUAPC] D7_APC_3: 0x0
9715 09:31:20.780052 INFO: [APUAPC] D8_APC_0: 0xffffffff
9716 09:31:20.783242 INFO: [APUAPC] D8_APC_1: 0xffffffff
9717 09:31:20.786655 INFO: [APUAPC] D8_APC_2: 0x3fffff
9718 09:31:20.789775 INFO: [APUAPC] D8_APC_3: 0x0
9719 09:31:20.793197 INFO: [APUAPC] D9_APC_0: 0xffffffff
9720 09:31:20.796473 INFO: [APUAPC] D9_APC_1: 0xffffffff
9721 09:31:20.799569 INFO: [APUAPC] D9_APC_2: 0x3fffff
9722 09:31:20.803088 INFO: [APUAPC] D9_APC_3: 0x0
9723 09:31:20.806346 INFO: [APUAPC] D10_APC_0: 0xffffffff
9724 09:31:20.809825 INFO: [APUAPC] D10_APC_1: 0xffffffff
9725 09:31:20.812953 INFO: [APUAPC] D10_APC_2: 0x3fffff
9726 09:31:20.816372 INFO: [APUAPC] D10_APC_3: 0x0
9727 09:31:20.819808 INFO: [APUAPC] D11_APC_0: 0xffffffff
9728 09:31:20.822877 INFO: [APUAPC] D11_APC_1: 0xffffffff
9729 09:31:20.826357 INFO: [APUAPC] D11_APC_2: 0x3fffff
9730 09:31:20.829521 INFO: [APUAPC] D11_APC_3: 0x0
9731 09:31:20.833096 INFO: [APUAPC] D12_APC_0: 0xffffffff
9732 09:31:20.836308 INFO: [APUAPC] D12_APC_1: 0xffffffff
9733 09:31:20.839863 INFO: [APUAPC] D12_APC_2: 0x3fffff
9734 09:31:20.843257 INFO: [APUAPC] D12_APC_3: 0x0
9735 09:31:20.846433 INFO: [APUAPC] D13_APC_0: 0xffffffff
9736 09:31:20.849600 INFO: [APUAPC] D13_APC_1: 0xffffffff
9737 09:31:20.853192 INFO: [APUAPC] D13_APC_2: 0x3fffff
9738 09:31:20.856223 INFO: [APUAPC] D13_APC_3: 0x0
9739 09:31:20.859397 INFO: [APUAPC] D14_APC_0: 0xffffffff
9740 09:31:20.862942 INFO: [APUAPC] D14_APC_1: 0xffffffff
9741 09:31:20.866362 INFO: [APUAPC] D14_APC_2: 0x3fffff
9742 09:31:20.869339 INFO: [APUAPC] D14_APC_3: 0x0
9743 09:31:20.873043 INFO: [APUAPC] D15_APC_0: 0xffffffff
9744 09:31:20.876393 INFO: [APUAPC] D15_APC_1: 0xffffffff
9745 09:31:20.879590 INFO: [APUAPC] D15_APC_2: 0x3fffff
9746 09:31:20.882744 INFO: [APUAPC] D15_APC_3: 0x0
9747 09:31:20.886272 INFO: [APUAPC] APC_CON: 0x4
9748 09:31:20.889365 INFO: [NOCDAPC] D0_APC_0: 0x0
9749 09:31:20.892675 INFO: [NOCDAPC] D0_APC_1: 0x0
9750 09:31:20.896242 INFO: [NOCDAPC] D1_APC_0: 0x0
9751 09:31:20.899230 INFO: [NOCDAPC] D1_APC_1: 0xfff
9752 09:31:20.899703 INFO: [NOCDAPC] D2_APC_0: 0x0
9753 09:31:20.902847 INFO: [NOCDAPC] D2_APC_1: 0xfff
9754 09:31:20.906441 INFO: [NOCDAPC] D3_APC_0: 0x0
9755 09:31:20.909575 INFO: [NOCDAPC] D3_APC_1: 0xfff
9756 09:31:20.912613 INFO: [NOCDAPC] D4_APC_0: 0x0
9757 09:31:20.916024 INFO: [NOCDAPC] D4_APC_1: 0xfff
9758 09:31:20.919309 INFO: [NOCDAPC] D5_APC_0: 0x0
9759 09:31:20.922739 INFO: [NOCDAPC] D5_APC_1: 0xfff
9760 09:31:20.926019 INFO: [NOCDAPC] D6_APC_0: 0x0
9761 09:31:20.929216 INFO: [NOCDAPC] D6_APC_1: 0xfff
9762 09:31:20.933010 INFO: [NOCDAPC] D7_APC_0: 0x0
9763 09:31:20.936345 INFO: [NOCDAPC] D7_APC_1: 0xfff
9764 09:31:20.936848 INFO: [NOCDAPC] D8_APC_0: 0x0
9765 09:31:20.939322 INFO: [NOCDAPC] D8_APC_1: 0xfff
9766 09:31:20.942463 INFO: [NOCDAPC] D9_APC_0: 0x0
9767 09:31:20.946210 INFO: [NOCDAPC] D9_APC_1: 0xfff
9768 09:31:20.949150 INFO: [NOCDAPC] D10_APC_0: 0x0
9769 09:31:20.952476 INFO: [NOCDAPC] D10_APC_1: 0xfff
9770 09:31:20.955807 INFO: [NOCDAPC] D11_APC_0: 0x0
9771 09:31:20.959039 INFO: [NOCDAPC] D11_APC_1: 0xfff
9772 09:31:20.962280 INFO: [NOCDAPC] D12_APC_0: 0x0
9773 09:31:20.965953 INFO: [NOCDAPC] D12_APC_1: 0xfff
9774 09:31:20.969321 INFO: [NOCDAPC] D13_APC_0: 0x0
9775 09:31:20.972521 INFO: [NOCDAPC] D13_APC_1: 0xfff
9776 09:31:20.975847 INFO: [NOCDAPC] D14_APC_0: 0x0
9777 09:31:20.979051 INFO: [NOCDAPC] D14_APC_1: 0xfff
9778 09:31:20.979488 INFO: [NOCDAPC] D15_APC_0: 0x0
9779 09:31:20.982510 INFO: [NOCDAPC] D15_APC_1: 0xfff
9780 09:31:20.985535 INFO: [NOCDAPC] APC_CON: 0x4
9781 09:31:20.988892 INFO: [APUAPC] set_apusys_apc done
9782 09:31:20.992319 INFO: [DEVAPC] devapc_init done
9783 09:31:20.995618 INFO: GICv3 without legacy support detected.
9784 09:31:21.002173 INFO: ARM GICv3 driver initialized in EL3
9785 09:31:21.005553 INFO: Maximum SPI INTID supported: 639
9786 09:31:21.008550 INFO: BL31: Initializing runtime services
9787 09:31:21.015270 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9788 09:31:21.018954 INFO: SPM: enable CPC mode
9789 09:31:21.021775 INFO: mcdi ready for mcusys-off-idle and system suspend
9790 09:31:21.028473 INFO: BL31: Preparing for EL3 exit to normal world
9791 09:31:21.031694 INFO: Entry point address = 0x80000000
9792 09:31:21.032167 INFO: SPSR = 0x8
9793 09:31:21.038537
9794 09:31:21.038910
9795 09:31:21.039228
9796 09:31:21.041817 Starting depthcharge on Spherion...
9797 09:31:21.042177
9798 09:31:21.042483 Wipe memory regions:
9799 09:31:21.042779
9800 09:31:21.045359 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9801 09:31:21.046068 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9802 09:31:21.046525 Setting prompt string to ['asurada:']
9803 09:31:21.046928 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9804 09:31:21.047636 [0x00000040000000, 0x00000054600000)
9805 09:31:21.167809
9806 09:31:21.168581 [0x00000054660000, 0x00000080000000)
9807 09:31:21.427887
9808 09:31:21.428479 [0x000000821a7280, 0x000000ffe64000)
9809 09:31:22.172965
9810 09:31:22.173540 [0x00000100000000, 0x00000140000000)
9811 09:31:22.554667
9812 09:31:22.559202 Initializing XHCI USB controller at 0x11200000.
9813 09:31:23.595196
9814 09:31:23.599104 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9815 09:31:23.599533
9816 09:31:23.599894
9817 09:31:23.600283
9818 09:31:23.601128 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9820 09:31:23.702419 asurada: tftpboot 192.168.201.1 11826813/tftp-deploy-pt1lsnrn/kernel/image.itb 11826813/tftp-deploy-pt1lsnrn/kernel/cmdline
9821 09:31:23.703103 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9822 09:31:23.703571 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9823 09:31:23.707926 tftpboot 192.168.201.1 11826813/tftp-deploy-pt1lsnrn/kernel/image.itp-deploy-pt1lsnrn/kernel/cmdline
9824 09:31:23.708589
9825 09:31:23.708974 Waiting for link
9826 09:31:23.868598
9827 09:31:23.869169 R8152: Initializing
9828 09:31:23.869546
9829 09:31:23.872076 Version 9 (ocp_data = 6010)
9830 09:31:23.872714
9831 09:31:23.875199 R8152: Done initializing
9832 09:31:23.875768
9833 09:31:23.876141 Adding net device
9834 09:31:25.882715
9835 09:31:25.883282 done.
9836 09:31:25.883655
9837 09:31:25.883998 MAC: 00:e0:4c:68:03:bd
9838 09:31:25.884374
9839 09:31:25.886148 Sending DHCP discover... done.
9840 09:31:25.886609
9841 09:31:37.449451 Waiting for reply... R8152: Bulk read error 0xffffffbf
9842 09:31:37.450153
9843 09:31:37.452878 Receive failed.
9844 09:31:37.453419
9845 09:31:37.453853 done.
9846 09:31:37.454227
9847 09:31:37.456113 Sending DHCP request... done.
9848 09:31:37.456668
9849 09:31:37.459308 Waiting for reply... done.
9850 09:31:37.459796
9851 09:31:37.462549 My ip is 192.168.201.16
9852 09:31:37.463071
9853 09:31:37.465880 The DHCP server ip is 192.168.201.1
9854 09:31:37.466374
9855 09:31:37.469265 TFTP server IP predefined by user: 192.168.201.1
9856 09:31:37.469759
9857 09:31:37.475609 Bootfile predefined by user: 11826813/tftp-deploy-pt1lsnrn/kernel/image.itb
9858 09:31:37.476079
9859 09:31:37.478901 Sending tftp read request... done.
9860 09:31:37.479277
9861 09:31:37.486274 Waiting for the transfer...
9862 09:31:37.486707
9863 09:31:37.789788 00000000 ################################################################
9864 09:31:37.789946
9865 09:31:38.086923 00080000 ################################################################
9866 09:31:38.087059
9867 09:31:38.384488 00100000 ################################################################
9868 09:31:38.384625
9869 09:31:38.678690 00180000 ################################################################
9870 09:31:38.678839
9871 09:31:38.932744 00200000 ################################################################
9872 09:31:38.932876
9873 09:31:39.227665 00280000 ################################################################
9874 09:31:39.227829
9875 09:31:39.526368 00300000 ################################################################
9876 09:31:39.526507
9877 09:31:39.819592 00380000 ################################################################
9878 09:31:39.819743
9879 09:31:40.118565 00400000 ################################################################
9880 09:31:40.118724
9881 09:31:40.416039 00480000 ################################################################
9882 09:31:40.416248
9883 09:31:40.714122 00500000 ################################################################
9884 09:31:40.714260
9885 09:31:41.007171 00580000 ################################################################
9886 09:31:41.007314
9887 09:31:41.262454 00600000 ################################################################
9888 09:31:41.262586
9889 09:31:41.529020 00680000 ################################################################
9890 09:31:41.529149
9891 09:31:41.820814 00700000 ################################################################
9892 09:31:41.820954
9893 09:31:42.093744 00780000 ################################################################
9894 09:31:42.093876
9895 09:31:42.380946 00800000 ################################################################
9896 09:31:42.381083
9897 09:31:42.669836 00880000 ################################################################
9898 09:31:42.669976
9899 09:31:42.931965 00900000 ################################################################
9900 09:31:42.932129
9901 09:31:43.227657 00980000 ################################################################
9902 09:31:43.227790
9903 09:31:43.517989 00a00000 ################################################################
9904 09:31:43.518125
9905 09:31:43.812744 00a80000 ################################################################
9906 09:31:43.812882
9907 09:31:44.080847 00b00000 ################################################################
9908 09:31:44.080979
9909 09:31:44.379315 00b80000 ################################################################
9910 09:31:44.379449
9911 09:31:44.677978 00c00000 ################################################################
9912 09:31:44.678112
9913 09:31:44.976981 00c80000 ################################################################
9914 09:31:44.977119
9915 09:31:45.276404 00d00000 ################################################################
9916 09:31:45.276539
9917 09:31:45.564140 00d80000 ################################################################
9918 09:31:45.564283
9919 09:31:45.845414 00e00000 ################################################################
9920 09:31:45.845548
9921 09:31:46.123456 00e80000 ################################################################
9922 09:31:46.123598
9923 09:31:46.388459 00f00000 ################################################################
9924 09:31:46.388595
9925 09:31:46.641112 00f80000 ################################################################
9926 09:31:46.641240
9927 09:31:46.914114 01000000 ################################################################
9928 09:31:46.914276
9929 09:31:47.198721 01080000 ################################################################
9930 09:31:47.198859
9931 09:31:47.491365 01100000 ################################################################
9932 09:31:47.491500
9933 09:31:47.784229 01180000 ################################################################
9934 09:31:47.784370
9935 09:31:48.060777 01200000 ################################################################
9936 09:31:48.060949
9937 09:31:48.341291 01280000 ################################################################
9938 09:31:48.341432
9939 09:31:48.640574 01300000 ################################################################
9940 09:31:48.640714
9941 09:31:48.939945 01380000 ################################################################
9942 09:31:48.940108
9943 09:31:49.240419 01400000 ################################################################
9944 09:31:49.240554
9945 09:31:49.535953 01480000 ################################################################
9946 09:31:49.536112
9947 09:31:49.832187 01500000 ################################################################
9948 09:31:49.832330
9949 09:31:50.124611 01580000 ################################################################
9950 09:31:50.124770
9951 09:31:50.422751 01600000 ################################################################
9952 09:31:50.422905
9953 09:31:50.719044 01680000 ################################################################
9954 09:31:50.719182
9955 09:31:51.018287 01700000 ################################################################
9956 09:31:51.018424
9957 09:31:51.307203 01780000 ################################################################
9958 09:31:51.307344
9959 09:31:51.590942 01800000 ################################################################
9960 09:31:51.591091
9961 09:31:51.889529 01880000 ################################################################
9962 09:31:51.889667
9963 09:31:52.183749 01900000 ################################################################
9964 09:31:52.183884
9965 09:31:52.482578 01980000 ################################################################
9966 09:31:52.482715
9967 09:31:52.778233 01a00000 ################################################################
9968 09:31:52.778387
9969 09:31:53.075907 01a80000 ################################################################
9970 09:31:53.076045
9971 09:31:53.374403 01b00000 ################################################################
9972 09:31:53.374543
9973 09:31:53.403064 01b80000 ###### done.
9974 09:31:53.403151
9975 09:31:53.406218 The bootfile was 28884194 bytes long.
9976 09:31:53.406309
9977 09:31:53.409664 Sending tftp read request... done.
9978 09:31:53.409852
9979 09:31:53.409956 Waiting for the transfer...
9980 09:31:53.410046
9981 09:31:53.412895 00000000 # done.
9982 09:31:53.413006
9983 09:31:53.419752 Command line loaded dynamically from TFTP file: 11826813/tftp-deploy-pt1lsnrn/kernel/cmdline
9984 09:31:53.419867
9985 09:31:53.443921 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9986 09:31:53.444596
9987 09:31:53.445096 Loading FIT.
9988 09:31:53.445557
9989 09:31:53.447386 Image ramdisk-1 has 17790622 bytes.
9990 09:31:53.447801
9991 09:31:53.449744 Image fdt-1 has 47278 bytes.
9992 09:31:53.449830
9993 09:31:53.452850 Image kernel-1 has 11044258 bytes.
9994 09:31:53.453017
9995 09:31:53.463179 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9996 09:31:53.463356
9997 09:31:53.479898 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9998 09:31:53.480119
9999 09:31:53.485754 Choosing best match conf-1 for compat google,spherion-rev3.
10000 09:31:53.485979
10001 09:31:53.493230 Connected to device vid:did:rid of 1ae0:0028:00
10002 09:31:53.500530
10003 09:31:53.503556 tpm_get_response: command 0x17b, return code 0x0
10004 09:31:53.503771
10005 09:31:53.507225 ec_init: CrosEC protocol v3 supported (256, 248)
10006 09:31:53.511474
10007 09:31:53.514453 tpm_cleanup: add release locality here.
10008 09:31:53.514864
10009 09:31:53.515179 Shutting down all USB controllers.
10010 09:31:53.518224
10011 09:31:53.518609 Removing current net device
10012 09:31:53.518931
10013 09:31:53.524791 Exiting depthcharge with code 4 at timestamp: 60711924
10014 09:31:53.525259
10015 09:31:53.527736 LZMA decompressing kernel-1 to 0x821a6718
10016 09:31:53.528244
10017 09:31:53.531277 LZMA decompressing kernel-1 to 0x40000000
10018 09:31:54.920588
10019 09:31:54.921196 jumping to kernel
10020 09:31:54.923382 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10021 09:31:54.924011 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10022 09:31:54.924549 Setting prompt string to ['Linux version [0-9]']
10023 09:31:54.924949 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 09:31:54.925354 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10025 09:31:54.970904
10026 09:31:54.973485 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10027 09:31:54.977600 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10028 09:31:54.978200 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10029 09:31:54.978606 Setting prompt string to []
10030 09:31:54.979034 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10031 09:31:54.979444 Using line separator: #'\n'#
10032 09:31:54.979789 No login prompt set.
10033 09:31:54.980145 Parsing kernel messages
10034 09:31:54.980522 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10035 09:31:54.981093 [login-action] Waiting for messages, (timeout 00:03:52)
10036 09:31:54.997014 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10037 09:31:55.000285 [ 0.000000] random: crng init done
10038 09:31:55.006592 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10039 09:31:55.010260 [ 0.000000] efi: UEFI not found.
10040 09:31:55.017113 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10041 09:31:55.023461 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10042 09:31:55.033477 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10043 09:31:55.043145 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10044 09:31:55.049492 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10045 09:31:55.056562 [ 0.000000] printk: bootconsole [mtk8250] enabled
10046 09:31:55.063221 [ 0.000000] NUMA: No NUMA configuration found
10047 09:31:55.069886 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10048 09:31:55.072792 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10049 09:31:55.076266 [ 0.000000] Zone ranges:
10050 09:31:55.082855 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10051 09:31:55.086322 [ 0.000000] DMA32 empty
10052 09:31:55.093094 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10053 09:31:55.096562 [ 0.000000] Movable zone start for each node
10054 09:31:55.099187 [ 0.000000] Early memory node ranges
10055 09:31:55.106035 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10056 09:31:55.112471 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10057 09:31:55.119353 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10058 09:31:55.125856 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10059 09:31:55.129091 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10060 09:31:55.139011 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10061 09:31:55.168763 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10062 09:31:55.175861 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10063 09:31:55.182384 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10064 09:31:55.185284 [ 0.000000] psci: probing for conduit method from DT.
10065 09:31:55.192096 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10066 09:31:55.195433 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10067 09:31:55.202118 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10068 09:31:55.205167 [ 0.000000] psci: SMC Calling Convention v1.2
10069 09:31:55.212271 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10070 09:31:55.215911 [ 0.000000] Detected VIPT I-cache on CPU0
10071 09:31:55.221612 [ 0.000000] CPU features: detected: GIC system register CPU interface
10072 09:31:55.228583 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10073 09:31:55.235299 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10074 09:31:55.241435 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10075 09:31:55.251554 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10076 09:31:55.258795 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10077 09:31:55.261780 [ 0.000000] alternatives: applying boot alternatives
10078 09:31:55.268285 [ 0.000000] Fallback order for Node 0: 0
10079 09:31:55.275252 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10080 09:31:55.278561 [ 0.000000] Policy zone: Normal
10081 09:31:55.301212 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10082 09:31:55.311362 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10083 09:31:55.321274 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10084 09:31:55.328083 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10085 09:31:55.334629 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10086 09:31:55.340865 <6>[ 0.000000] software IO TLB: area num 8.
10087 09:31:55.396115 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10088 09:31:55.476141 <6>[ 0.000000] Memory: 3837708K/4191232K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 320756K reserved, 32768K cma-reserved)
10089 09:31:55.483207 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10090 09:31:55.489412 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10091 09:31:55.492811 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10092 09:31:55.499574 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10093 09:31:55.505776 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10094 09:31:55.509044 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10095 09:31:55.519100 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10096 09:31:55.525668 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10097 09:31:55.532656 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10098 09:31:55.539000 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10099 09:31:55.542369 <6>[ 0.000000] GICv3: 608 SPIs implemented
10100 09:31:55.545766 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10101 09:31:55.552000 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10102 09:31:55.555529 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10103 09:31:55.561655 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10104 09:31:55.575436 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10105 09:31:55.588484 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10106 09:31:55.595006 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10107 09:31:55.603079 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10108 09:31:55.616345 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10109 09:31:55.622754 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10110 09:31:55.629390 <6>[ 0.009179] Console: colour dummy device 80x25
10111 09:31:55.639215 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10112 09:31:55.646003 <6>[ 0.024343] pid_max: default: 32768 minimum: 301
10113 09:31:55.648986 <6>[ 0.029213] LSM: Security Framework initializing
10114 09:31:55.655744 <6>[ 0.034123] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10115 09:31:55.665703 <6>[ 0.041730] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10116 09:31:55.672035 <6>[ 0.051004] cblist_init_generic: Setting adjustable number of callback queues.
10117 09:31:55.679179 <6>[ 0.058494] cblist_init_generic: Setting shift to 3 and lim to 1.
10118 09:31:55.688843 <6>[ 0.064833] cblist_init_generic: Setting adjustable number of callback queues.
10119 09:31:55.692291 <6>[ 0.072259] cblist_init_generic: Setting shift to 3 and lim to 1.
10120 09:31:55.699019 <6>[ 0.078697] rcu: Hierarchical SRCU implementation.
10121 09:31:55.705273 <6>[ 0.083713] rcu: Max phase no-delay instances is 1000.
10122 09:31:55.712121 <6>[ 0.090734] EFI services will not be available.
10123 09:31:55.715532 <6>[ 0.095685] smp: Bringing up secondary CPUs ...
10124 09:31:55.722777 <6>[ 0.100730] Detected VIPT I-cache on CPU1
10125 09:31:55.729656 <6>[ 0.100798] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10126 09:31:55.736571 <6>[ 0.100828] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10127 09:31:55.739503 <6>[ 0.101153] Detected VIPT I-cache on CPU2
10128 09:31:55.749468 <6>[ 0.101200] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10129 09:31:55.755818 <6>[ 0.101216] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10130 09:31:55.759469 <6>[ 0.101466] Detected VIPT I-cache on CPU3
10131 09:31:55.766147 <6>[ 0.101512] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10132 09:31:55.772263 <6>[ 0.101525] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10133 09:31:55.775684 <6>[ 0.101829] CPU features: detected: Spectre-v4
10134 09:31:55.782618 <6>[ 0.101835] CPU features: detected: Spectre-BHB
10135 09:31:55.785427 <6>[ 0.101840] Detected PIPT I-cache on CPU4
10136 09:31:55.792590 <6>[ 0.101897] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10137 09:31:55.798982 <6>[ 0.101913] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10138 09:31:55.805547 <6>[ 0.102206] Detected PIPT I-cache on CPU5
10139 09:31:55.812283 <6>[ 0.102268] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10140 09:31:55.818893 <6>[ 0.102285] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10141 09:31:55.821973 <6>[ 0.102566] Detected PIPT I-cache on CPU6
10142 09:31:55.828686 <6>[ 0.102627] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10143 09:31:55.835490 <6>[ 0.102644] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10144 09:31:55.842315 <6>[ 0.102943] Detected PIPT I-cache on CPU7
10145 09:31:55.848292 <6>[ 0.103008] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10146 09:31:55.855289 <6>[ 0.103024] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10147 09:31:55.858587 <6>[ 0.103073] smp: Brought up 1 node, 8 CPUs
10148 09:31:55.864919 <6>[ 0.244358] SMP: Total of 8 processors activated.
10149 09:31:55.868364 <6>[ 0.249278] CPU features: detected: 32-bit EL0 Support
10150 09:31:55.877905 <6>[ 0.254641] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10151 09:31:55.884683 <6>[ 0.263442] CPU features: detected: Common not Private translations
10152 09:31:55.891243 <6>[ 0.269918] CPU features: detected: CRC32 instructions
10153 09:31:55.894876 <6>[ 0.275302] CPU features: detected: RCpc load-acquire (LDAPR)
10154 09:31:55.901395 <6>[ 0.281262] CPU features: detected: LSE atomic instructions
10155 09:31:55.907985 <6>[ 0.287043] CPU features: detected: Privileged Access Never
10156 09:31:55.915105 <6>[ 0.292823] CPU features: detected: RAS Extension Support
10157 09:31:55.921203 <6>[ 0.298432] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10158 09:31:55.924453 <6>[ 0.305696] CPU: All CPU(s) started at EL2
10159 09:31:55.930889 <6>[ 0.310012] alternatives: applying system-wide alternatives
10160 09:31:55.939580 <6>[ 0.319922] devtmpfs: initialized
10161 09:31:55.954639 <6>[ 0.328350] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10162 09:31:55.961589 <6>[ 0.338312] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10163 09:31:55.968415 <6>[ 0.346531] pinctrl core: initialized pinctrl subsystem
10164 09:31:55.971601 <6>[ 0.353171] DMI not present or invalid.
10165 09:31:55.977971 <6>[ 0.357572] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10166 09:31:55.987868 <6>[ 0.364434] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10167 09:31:55.994306 <6>[ 0.371885] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10168 09:31:56.004321 <6>[ 0.379975] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10169 09:31:56.007980 <6>[ 0.388129] audit: initializing netlink subsys (disabled)
10170 09:31:56.017642 <5>[ 0.393823] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10171 09:31:56.024226 <6>[ 0.394513] thermal_sys: Registered thermal governor 'step_wise'
10172 09:31:56.030896 <6>[ 0.401789] thermal_sys: Registered thermal governor 'power_allocator'
10173 09:31:56.033955 <6>[ 0.408043] cpuidle: using governor menu
10174 09:31:56.040505 <6>[ 0.419003] NET: Registered PF_QIPCRTR protocol family
10175 09:31:56.047266 <6>[ 0.424496] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10176 09:31:56.053685 <6>[ 0.431602] ASID allocator initialised with 32768 entries
10177 09:31:56.056697 <6>[ 0.438145] Serial: AMBA PL011 UART driver
10178 09:31:56.067031 <4>[ 0.446905] Trying to register duplicate clock ID: 134
10179 09:31:56.121483 <6>[ 0.504842] KASLR enabled
10180 09:31:56.135842 <6>[ 0.512593] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10181 09:31:56.142521 <6>[ 0.519608] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10182 09:31:56.149015 <6>[ 0.526096] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10183 09:31:56.155685 <6>[ 0.533099] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10184 09:31:56.162944 <6>[ 0.539587] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10185 09:31:56.169035 <6>[ 0.546589] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10186 09:31:56.175766 <6>[ 0.553077] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10187 09:31:56.182178 <6>[ 0.560080] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10188 09:31:56.185388 <6>[ 0.567587] ACPI: Interpreter disabled.
10189 09:31:56.193648 <6>[ 0.573995] iommu: Default domain type: Translated
10190 09:31:56.200525 <6>[ 0.579106] iommu: DMA domain TLB invalidation policy: strict mode
10191 09:31:56.203883 <5>[ 0.585761] SCSI subsystem initialized
10192 09:31:56.210246 <6>[ 0.589926] usbcore: registered new interface driver usbfs
10193 09:31:56.217166 <6>[ 0.595656] usbcore: registered new interface driver hub
10194 09:31:56.220010 <6>[ 0.601207] usbcore: registered new device driver usb
10195 09:31:56.227370 <6>[ 0.607308] pps_core: LinuxPPS API ver. 1 registered
10196 09:31:56.237428 <6>[ 0.612500] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10197 09:31:56.240234 <6>[ 0.621844] PTP clock support registered
10198 09:31:56.243844 <6>[ 0.626087] EDAC MC: Ver: 3.0.0
10199 09:31:56.251105 <6>[ 0.631236] FPGA manager framework
10200 09:31:56.254385 <6>[ 0.634913] Advanced Linux Sound Architecture Driver Initialized.
10201 09:31:56.258262 <6>[ 0.641620] vgaarb: loaded
10202 09:31:56.265264 <6>[ 0.644784] clocksource: Switched to clocksource arch_sys_counter
10203 09:31:56.271546 <5>[ 0.651220] VFS: Disk quotas dquot_6.6.0
10204 09:31:56.278266 <6>[ 0.655403] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10205 09:31:56.281282 <6>[ 0.662593] pnp: PnP ACPI: disabled
10206 09:31:56.289398 <6>[ 0.669274] NET: Registered PF_INET protocol family
10207 09:31:56.296030 <6>[ 0.674645] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10208 09:31:56.307965 <6>[ 0.684659] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10209 09:31:56.317715 <6>[ 0.693447] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10210 09:31:56.324380 <6>[ 0.701409] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10211 09:31:56.330759 <6>[ 0.709815] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10212 09:31:56.341633 <6>[ 0.718466] TCP: Hash tables configured (established 32768 bind 32768)
10213 09:31:56.348375 <6>[ 0.725261] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10214 09:31:56.355120 <6>[ 0.732275] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10215 09:31:56.361583 <6>[ 0.739790] NET: Registered PF_UNIX/PF_LOCAL protocol family
10216 09:31:56.368132 <6>[ 0.745911] RPC: Registered named UNIX socket transport module.
10217 09:31:56.371563 <6>[ 0.752067] RPC: Registered udp transport module.
10218 09:31:56.377971 <6>[ 0.756999] RPC: Registered tcp transport module.
10219 09:31:56.384856 <6>[ 0.761930] RPC: Registered tcp NFSv4.1 backchannel transport module.
10220 09:31:56.388358 <6>[ 0.768599] PCI: CLS 0 bytes, default 64
10221 09:31:56.391326 <6>[ 0.772956] Unpacking initramfs...
10222 09:31:56.401654 <6>[ 0.777049] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10223 09:31:56.407772 <6>[ 0.785671] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10224 09:31:56.414759 <6>[ 0.794475] kvm [1]: IPA Size Limit: 40 bits
10225 09:31:56.417678 <6>[ 0.799003] kvm [1]: GICv3: no GICV resource entry
10226 09:31:56.424450 <6>[ 0.804022] kvm [1]: disabling GICv2 emulation
10227 09:31:56.431113 <6>[ 0.808707] kvm [1]: GIC system register CPU interface enabled
10228 09:31:56.434163 <6>[ 0.814867] kvm [1]: vgic interrupt IRQ18
10229 09:31:56.440650 <6>[ 0.819227] kvm [1]: VHE mode initialized successfully
10230 09:31:56.444256 <5>[ 0.825648] Initialise system trusted keyrings
10231 09:31:56.450579 <6>[ 0.830452] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10232 09:31:56.460372 <6>[ 0.840450] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10233 09:31:56.466688 <5>[ 0.846833] NFS: Registering the id_resolver key type
10234 09:31:56.469938 <5>[ 0.852134] Key type id_resolver registered
10235 09:31:56.476742 <5>[ 0.856551] Key type id_legacy registered
10236 09:31:56.483727 <6>[ 0.860832] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10237 09:31:56.490534 <6>[ 0.867752] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10238 09:31:56.496960 <6>[ 0.875482] 9p: Installing v9fs 9p2000 file system support
10239 09:31:56.533172 <5>[ 0.913100] Key type asymmetric registered
10240 09:31:56.536314 <5>[ 0.917433] Asymmetric key parser 'x509' registered
10241 09:31:56.546537 <6>[ 0.922578] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10242 09:31:56.549529 <6>[ 0.930191] io scheduler mq-deadline registered
10243 09:31:56.552571 <6>[ 0.934953] io scheduler kyber registered
10244 09:31:56.571882 <6>[ 0.951998] EINJ: ACPI disabled.
10245 09:31:56.603854 <4>[ 0.977207] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10246 09:31:56.613517 <4>[ 0.987828] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10247 09:31:56.628495 <6>[ 1.008629] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10248 09:31:56.636593 <6>[ 1.016646] printk: console [ttyS0] disabled
10249 09:31:56.664777 <6>[ 1.041290] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10250 09:31:56.670938 <6>[ 1.050757] printk: console [ttyS0] enabled
10251 09:31:56.674508 <6>[ 1.050757] printk: console [ttyS0] enabled
10252 09:31:56.681079 <6>[ 1.059661] printk: bootconsole [mtk8250] disabled
10253 09:31:56.684655 <6>[ 1.059661] printk: bootconsole [mtk8250] disabled
10254 09:31:56.691210 <6>[ 1.070944] SuperH (H)SCI(F) driver initialized
10255 09:31:56.694302 <6>[ 1.076230] msm_serial: driver initialized
10256 09:31:56.708536 <6>[ 1.085224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10257 09:31:56.718163 <6>[ 1.093783] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10258 09:31:56.725017 <6>[ 1.102325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10259 09:31:56.734932 <6>[ 1.110955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10260 09:31:56.744853 <6>[ 1.119664] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10261 09:31:56.751578 <6>[ 1.128379] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10262 09:31:56.761616 <6>[ 1.136921] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10263 09:31:56.768207 <6>[ 1.145728] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10264 09:31:56.777619 <6>[ 1.154273] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10265 09:31:56.789657 <6>[ 1.170156] loop: module loaded
10266 09:31:56.796808 <6>[ 1.176139] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10267 09:31:56.819590 <4>[ 1.199666] mtk-pmic-keys: Failed to locate of_node [id: -1]
10268 09:31:56.826474 <6>[ 1.206819] megasas: 07.719.03.00-rc1
10269 09:31:56.836490 <6>[ 1.216673] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10270 09:31:56.844240 <6>[ 1.224171] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10271 09:31:56.860849 <6>[ 1.240712] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10272 09:31:56.917122 <6>[ 1.290415] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10273 09:31:57.123750 <6>[ 1.503714] Freeing initrd memory: 17368K
10274 09:31:57.133858 <6>[ 1.514073] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10275 09:31:57.145055 <6>[ 1.525138] tun: Universal TUN/TAP device driver, 1.6
10276 09:31:57.148494 <6>[ 1.531207] thunder_xcv, ver 1.0
10277 09:31:57.151486 <6>[ 1.534712] thunder_bgx, ver 1.0
10278 09:31:57.155315 <6>[ 1.538205] nicpf, ver 1.0
10279 09:31:57.165617 <6>[ 1.542237] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10280 09:31:57.168653 <6>[ 1.549714] hns3: Copyright (c) 2017 Huawei Corporation.
10281 09:31:57.175212 <6>[ 1.555302] hclge is initializing
10282 09:31:57.178774 <6>[ 1.558885] e1000: Intel(R) PRO/1000 Network Driver
10283 09:31:57.185608 <6>[ 1.564014] e1000: Copyright (c) 1999-2006 Intel Corporation.
10284 09:31:57.188916 <6>[ 1.570032] e1000e: Intel(R) PRO/1000 Network Driver
10285 09:31:57.195677 <6>[ 1.575248] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10286 09:31:57.202067 <6>[ 1.581436] igb: Intel(R) Gigabit Ethernet Network Driver
10287 09:31:57.209127 <6>[ 1.587086] igb: Copyright (c) 2007-2014 Intel Corporation.
10288 09:31:57.215412 <6>[ 1.592923] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10289 09:31:57.221850 <6>[ 1.599441] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10290 09:31:57.225000 <6>[ 1.605905] sky2: driver version 1.30
10291 09:31:57.231688 <6>[ 1.610909] VFIO - User Level meta-driver version: 0.3
10292 09:31:57.239192 <6>[ 1.619183] usbcore: registered new interface driver usb-storage
10293 09:31:57.245547 <6>[ 1.625628] usbcore: registered new device driver onboard-usb-hub
10294 09:31:57.255081 <6>[ 1.634759] mt6397-rtc mt6359-rtc: registered as rtc0
10295 09:31:57.264514 <6>[ 1.640225] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:31:57 UTC (1697794317)
10296 09:31:57.267532 <6>[ 1.649793] i2c_dev: i2c /dev entries driver
10297 09:31:57.284898 <6>[ 1.661595] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10298 09:31:57.304566 <6>[ 1.684572] cpu cpu0: EM: created perf domain
10299 09:31:57.307763 <6>[ 1.689477] cpu cpu4: EM: created perf domain
10300 09:31:57.318008 <6>[ 1.695002] sdhci: Secure Digital Host Controller Interface driver
10301 09:31:57.321253 <6>[ 1.701434] sdhci: Copyright(c) Pierre Ossman
10302 09:31:57.328033 <6>[ 1.706342] Synopsys Designware Multimedia Card Interface Driver
10303 09:31:57.334532 <6>[ 1.712937] sdhci-pltfm: SDHCI platform and OF driver helper
10304 09:31:57.337773 <6>[ 1.713102] mmc0: CQHCI version 5.10
10305 09:31:57.344481 <6>[ 1.722862] ledtrig-cpu: registered to indicate activity on CPUs
10306 09:31:57.350930 <6>[ 1.729734] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10307 09:31:57.357696 <6>[ 1.736757] usbcore: registered new interface driver usbhid
10308 09:31:57.361163 <6>[ 1.742580] usbhid: USB HID core driver
10309 09:31:57.367670 <6>[ 1.746773] spi_master spi0: will run message pump with realtime priority
10310 09:31:57.410787 <6>[ 1.784347] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10311 09:31:57.425850 <6>[ 1.799540] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10312 09:31:57.434119 <6>[ 1.814230] cros-ec-spi spi0.0: Chrome EC device registered
10313 09:31:57.440937 <6>[ 1.820346] mmc0: Command Queue Engine enabled
10314 09:31:57.447441 <6>[ 1.825117] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10315 09:31:57.450713 <6>[ 1.832840] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10316 09:31:57.464331 <6>[ 1.844274] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10317 09:31:57.475178 <6>[ 1.847931] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10318 09:31:57.480683 <6>[ 1.851651] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10319 09:31:57.483693 <6>[ 1.860381] NET: Registered PF_PACKET protocol family
10320 09:31:57.490584 <6>[ 1.865492] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10321 09:31:57.493826 <6>[ 1.870118] 9pnet: Installing 9P2000 support
10322 09:31:57.500383 <6>[ 1.875958] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10323 09:31:57.507181 <5>[ 1.879806] Key type dns_resolver registered
10324 09:31:57.510444 <6>[ 1.891240] registered taskstats version 1
10325 09:31:57.513657 <5>[ 1.895615] Loading compiled-in X.509 certificates
10326 09:31:57.544102 <4>[ 1.917448] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10327 09:31:57.553650 <4>[ 1.928346] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10328 09:31:57.560348 <3>[ 1.938900] debugfs: File 'uA_load' in directory '/' already present!
10329 09:31:57.567142 <3>[ 1.945624] debugfs: File 'min_uV' in directory '/' already present!
10330 09:31:57.573613 <3>[ 1.952294] debugfs: File 'max_uV' in directory '/' already present!
10331 09:31:57.580508 <3>[ 1.958921] debugfs: File 'constraint_flags' in directory '/' already present!
10332 09:31:57.591246 <3>[ 1.968322] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10333 09:31:57.599887 <6>[ 1.980172] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10334 09:31:57.606895 <6>[ 1.986931] xhci-mtk 11200000.usb: xHCI Host Controller
10335 09:31:57.614057 <6>[ 1.992440] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10336 09:31:57.623792 <6>[ 2.000276] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10337 09:31:57.630236 <6>[ 2.009694] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10338 09:31:57.636690 <6>[ 2.015734] xhci-mtk 11200000.usb: xHCI Host Controller
10339 09:31:57.643380 <6>[ 2.021210] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10340 09:31:57.649913 <6>[ 2.028858] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10341 09:31:57.657006 <6>[ 2.036525] hub 1-0:1.0: USB hub found
10342 09:31:57.660134 <6>[ 2.040533] hub 1-0:1.0: 1 port detected
10343 09:31:57.666645 <6>[ 2.044805] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10344 09:31:57.673187 <6>[ 2.053359] hub 2-0:1.0: USB hub found
10345 09:31:57.676342 <6>[ 2.057363] hub 2-0:1.0: 1 port detected
10346 09:31:57.685112 <6>[ 2.064969] mtk-msdc 11f70000.mmc: Got CD GPIO
10347 09:31:57.694640 <6>[ 2.071207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10348 09:31:57.701372 <6>[ 2.079230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10349 09:31:57.711257 <4>[ 2.087186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10350 09:31:57.721085 <6>[ 2.096711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10351 09:31:57.727680 <6>[ 2.104807] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10352 09:31:57.734481 <6>[ 2.112941] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10353 09:31:57.744150 <6>[ 2.120881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10354 09:31:57.750952 <6>[ 2.128709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10355 09:31:57.760738 <6>[ 2.136528] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10356 09:31:57.770659 <6>[ 2.147008] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10357 09:31:57.777239 <6>[ 2.155384] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10358 09:31:57.788060 <6>[ 2.163726] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10359 09:31:57.793948 <6>[ 2.172064] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10360 09:31:57.803695 <6>[ 2.180402] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10361 09:31:57.810540 <6>[ 2.188740] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10362 09:31:57.820433 <6>[ 2.197077] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10363 09:31:57.826853 <6>[ 2.205415] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10364 09:31:57.836722 <6>[ 2.213752] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10365 09:31:57.847017 <6>[ 2.222090] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10366 09:31:57.853080 <6>[ 2.230428] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10367 09:31:57.863417 <6>[ 2.238765] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10368 09:31:57.869606 <6>[ 2.247103] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10369 09:31:57.879715 <6>[ 2.255451] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10370 09:31:57.886620 <6>[ 2.263789] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10371 09:31:57.893015 <6>[ 2.272528] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10372 09:31:57.899707 <6>[ 2.279652] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10373 09:31:57.906057 <6>[ 2.286414] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10374 09:31:57.915998 <6>[ 2.293156] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10375 09:31:57.922482 <6>[ 2.300062] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10376 09:31:57.929166 <6>[ 2.306933] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10377 09:31:57.938994 <6>[ 2.316065] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10378 09:31:57.949678 <6>[ 2.325190] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10379 09:31:57.958901 <6>[ 2.334483] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10380 09:31:57.968790 <6>[ 2.343950] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10381 09:31:57.979018 <6>[ 2.353416] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10382 09:31:57.985559 <6>[ 2.362536] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10383 09:31:57.995320 <6>[ 2.372002] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10384 09:31:58.005518 <6>[ 2.381122] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10385 09:31:58.015483 <6>[ 2.390416] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10386 09:31:58.024823 <6>[ 2.400576] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10387 09:31:58.034886 <6>[ 2.411972] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10388 09:31:58.041437 <6>[ 2.421567] Trying to probe devices needed for running init ...
10389 09:31:58.092081 <6>[ 2.469053] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10390 09:31:58.246589 <6>[ 2.626858] hub 1-1:1.0: USB hub found
10391 09:31:58.249589 <6>[ 2.631406] hub 1-1:1.0: 4 ports detected
10392 09:31:58.372340 <6>[ 2.749212] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10393 09:31:58.398672 <6>[ 2.779015] hub 2-1:1.0: USB hub found
10394 09:31:58.401900 <6>[ 2.783516] hub 2-1:1.0: 3 ports detected
10395 09:31:58.572310 <6>[ 2.949061] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10396 09:31:58.704951 <6>[ 3.085169] hub 1-1.4:1.0: USB hub found
10397 09:31:58.707841 <6>[ 3.089871] hub 1-1.4:1.0: 2 ports detected
10398 09:31:58.784436 <6>[ 3.161309] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10399 09:31:59.004027 <6>[ 3.381095] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10400 09:31:59.195893 <6>[ 3.573068] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10401 09:32:10.317166 <6>[ 14.702089] ALSA device list:
10402 09:32:10.323331 <6>[ 14.705380] No soundcards found.
10403 09:32:10.331673 <6>[ 14.713157] Freeing unused kernel memory: 8384K
10404 09:32:10.334743 <6>[ 14.718144] Run /init as init process
10405 09:32:10.345937 Loading, please wait...
10406 09:32:10.366581 Starting version 247.3-7+deb11u2
10407 09:32:10.537079 <6>[ 14.915724] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10408 09:32:10.545921 <6>[ 14.927395] remoteproc remoteproc0: scp is available
10409 09:32:10.555927 <3>[ 14.928682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10410 09:32:10.558903 <6>[ 14.932931] remoteproc remoteproc0: powering up scp
10411 09:32:10.568853 <3>[ 14.942050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10412 09:32:10.575482 <6>[ 14.946021] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10413 09:32:10.585488 <3>[ 14.954037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10414 09:32:10.588904 <6>[ 14.964617] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10415 09:32:10.599013 <3>[ 14.970689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10416 09:32:10.605142 <6>[ 14.972951] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10417 09:32:10.615062 <6>[ 14.972976] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10418 09:32:10.621780 <6>[ 14.972986] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10419 09:32:10.631750 <6>[ 14.987180] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10420 09:32:10.638801 <3>[ 14.991886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 09:32:10.644948 <3>[ 14.991891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 09:32:10.655392 <4>[ 14.995980] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10423 09:32:10.661652 <4>[ 14.996080] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10424 09:32:10.664896 <6>[ 15.003929] mc: Linux media interface: v0.10
10425 09:32:10.672264 <6>[ 15.008170] usbcore: registered new interface driver r8152
10426 09:32:10.678693 <3>[ 15.009273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 09:32:10.688661 <3>[ 15.009280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10428 09:32:10.695404 <3>[ 15.011644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 09:32:10.704866 <4>[ 15.025301] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10430 09:32:10.708154 <4>[ 15.025301] Fallback method does not support PEC.
10431 09:32:10.718620 <3>[ 15.033254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10432 09:32:10.724802 <3>[ 15.060213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10433 09:32:10.735100 <3>[ 15.066182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 09:32:10.741286 <6>[ 15.077217] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10435 09:32:10.751395 <3>[ 15.082315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10436 09:32:10.757964 <3>[ 15.082371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 09:32:10.768887 <6>[ 15.097457] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10438 09:32:10.775515 <6>[ 15.102100] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10439 09:32:10.782293 <6>[ 15.102106] pci_bus 0000:00: root bus resource [bus 00-ff]
10440 09:32:10.788909 <6>[ 15.102114] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10441 09:32:10.798907 <6>[ 15.102120] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10442 09:32:10.804915 <6>[ 15.102157] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10443 09:32:10.811909 <6>[ 15.102182] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10444 09:32:10.814930 <6>[ 15.102278] pci 0000:00:00.0: supports D1 D2
10445 09:32:10.821424 <6>[ 15.102282] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10446 09:32:10.831686 <6>[ 15.103946] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10447 09:32:10.838484 <3>[ 15.104032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10448 09:32:10.848382 <3>[ 15.104035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10449 09:32:10.854776 <3>[ 15.104040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10450 09:32:10.864873 <3>[ 15.104043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10451 09:32:10.871169 <6>[ 15.104054] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10452 09:32:10.877540 <3>[ 15.104063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10453 09:32:10.884709 <6>[ 15.104084] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10454 09:32:10.891038 <6>[ 15.112952] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10455 09:32:10.900717 <6>[ 15.113002] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10456 09:32:10.907274 <6>[ 15.113018] remoteproc remoteproc0: remote processor scp is now up
10457 09:32:10.917584 <6>[ 15.113941] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10458 09:32:10.927094 <6>[ 15.117014] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10459 09:32:10.933585 <4>[ 15.120237] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10460 09:32:10.943800 <4>[ 15.120247] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10461 09:32:10.950428 <6>[ 15.121249] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10462 09:32:10.956793 <6>[ 15.122709] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10463 09:32:10.966531 <6>[ 15.123834] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10464 09:32:10.972891 <6>[ 15.145194] videodev: Linux video capture interface: v2.00
10465 09:32:10.979728 <3>[ 15.152928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10466 09:32:10.989873 <6>[ 15.154897] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10467 09:32:10.992903 <6>[ 15.155602] Bluetooth: Core ver 2.22
10468 09:32:10.999729 <6>[ 15.155669] NET: Registered PF_BLUETOOTH protocol family
10469 09:32:11.006502 <6>[ 15.155671] Bluetooth: HCI device and connection manager initialized
10470 09:32:11.009307 <6>[ 15.155690] Bluetooth: HCI socket layer initialized
10471 09:32:11.016134 <6>[ 15.155690] usbcore: registered new interface driver cdc_ether
10472 09:32:11.023015 <6>[ 15.155693] Bluetooth: L2CAP socket layer initialized
10473 09:32:11.026000 <6>[ 15.155701] Bluetooth: SCO socket layer initialized
10474 09:32:11.032765 <6>[ 15.162382] usbcore: registered new interface driver r8153_ecm
10475 09:32:11.035982 <6>[ 15.167574] pci 0000:01:00.0: supports D1 D2
10476 09:32:11.042817 <6>[ 15.176951] r8152 2-1.3:1.0 eth0: v1.12.13
10477 09:32:11.049259 <6>[ 15.184443] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10478 09:32:11.052933 <6>[ 15.199337] usbcore: registered new interface driver btusb
10479 09:32:11.059181 <6>[ 15.199601] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10480 09:32:11.068798 <4>[ 15.210267] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10481 09:32:11.075534 <6>[ 15.220863] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10482 09:32:11.082169 <3>[ 15.226023] Bluetooth: hci0: Failed to load firmware file (-2)
10483 09:32:11.091967 <6>[ 15.234046] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10484 09:32:11.098422 <6>[ 15.234051] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10485 09:32:11.105641 <6>[ 15.234129] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10486 09:32:11.112221 <3>[ 15.242156] Bluetooth: hci0: Failed to set up firmware (-2)
10487 09:32:11.118217 <6>[ 15.242650] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10488 09:32:11.125068 <6>[ 15.250210] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10489 09:32:11.135044 <6>[ 15.250222] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10490 09:32:11.145042 <4>[ 15.256566] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10491 09:32:11.158076 <6>[ 15.257574] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10492 09:32:11.165098 <6>[ 15.257666] usbcore: registered new interface driver uvcvideo
10493 09:32:11.171331 <6>[ 15.264566] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10494 09:32:11.178464 <6>[ 15.558221] pci 0000:00:00.0: PCI bridge to [bus 01]
10495 09:32:11.184902 <6>[ 15.563441] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10496 09:32:11.191522 <6>[ 15.571570] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10497 09:32:11.197929 <6>[ 15.578375] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10498 09:32:11.204524 <6>[ 15.584696] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10499 09:32:11.224968 <5>[ 15.603147] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10500 09:32:11.237526 <5>[ 15.619094] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10501 09:32:11.247588 <4>[ 15.626027] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10502 09:32:11.254019 <6>[ 15.634949] cfg80211: failed to load regulatory.db
10503 09:32:11.313684 <6>[ 15.692160] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10504 09:32:11.320422 <6>[ 15.699736] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10505 09:32:11.344887 <6>[ 15.726567] mt7921e 0000:01:00.0: ASIC revision: 79610010
10506 09:32:11.449412 <4>[ 15.824542] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10507 09:32:11.463316 Begin: Loading essential drivers ... done.
10508 09:32:11.466730 Begin: Running /scripts/init-premount ... done.
10509 09:32:11.472879 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10510 09:32:11.482997 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10511 09:32:11.486713 Device /sys/class/net/enx00e04c6803bd found
10512 09:32:11.487297 done.
10513 09:32:11.574165 <4>[ 15.949118] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10514 09:32:11.580714 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10515 09:32:11.696935 <4>[ 16.072311] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10516 09:32:11.812837 <4>[ 16.188352] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10517 09:32:11.933277 <4>[ 16.308458] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10518 09:32:12.052961 <4>[ 16.428425] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10519 09:32:12.173479 <4>[ 16.548541] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10520 09:32:12.293349 <4>[ 16.668427] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10521 09:32:12.413117 <4>[ 16.788515] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10522 09:32:12.428054 <6>[ 16.810079] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10523 09:32:12.532946 <4>[ 16.908405] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10524 09:32:12.644247 <3>[ 17.026432] mt7921e 0000:01:00.0: hardware init failed
10525 09:32:12.758038 IP-Config: no response after 2 secs - giving up
10526 09:32:12.798226 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10527 09:32:12.804909 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10528 09:32:12.811390 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10529 09:32:12.818173 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10530 09:32:12.824730 host : mt8192-asurada-spherion-r0-cbg-4
10531 09:32:12.831317 domain : lava-rack
10532 09:32:12.834546 rootserver: 192.168.201.1 rootpath:
10533 09:32:12.834979 filename :
10534 09:32:12.900537 done.
10535 09:32:12.903971 Begin: Running /scripts/nfs-bottom ... done.
10536 09:32:12.921151 Begin: Running /scripts/init-bottom ... done.
10537 09:32:14.101798 <6>[ 18.483555] NET: Registered PF_INET6 protocol family
10538 09:32:14.108868 <6>[ 18.490884] Segment Routing with IPv6
10539 09:32:14.112110 <6>[ 18.494840] In-situ OAM (IOAM) with IPv6
10540 09:32:14.219170 <30>[ 18.581576] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10541 09:32:14.222779 <30>[ 18.605953] systemd[1]: Detected architecture arm64.
10542 09:32:14.244851
10543 09:32:14.248362 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10544 09:32:14.248949
10545 09:32:14.265472 <30>[ 18.647910] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10546 09:32:15.175062 <30>[ 19.553945] systemd[1]: Queued start job for default target Graphical Interface.
10547 09:32:15.217588 <30>[ 19.599640] systemd[1]: Created slice system-getty.slice.
10548 09:32:15.224124 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10549 09:32:15.240848 <30>[ 19.622664] systemd[1]: Created slice system-modprobe.slice.
10550 09:32:15.247167 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10551 09:32:15.264280 <30>[ 19.646520] systemd[1]: Created slice system-serial\x2dgetty.slice.
10552 09:32:15.274580 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10553 09:32:15.288255 <30>[ 19.670175] systemd[1]: Created slice User and Session Slice.
10554 09:32:15.294428 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10555 09:32:15.315061 <30>[ 19.693906] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10556 09:32:15.325077 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10557 09:32:15.342483 <30>[ 19.721725] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10558 09:32:15.349662 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10559 09:32:15.373493 <30>[ 19.749235] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10560 09:32:15.380280 <30>[ 19.761385] systemd[1]: Reached target Local Encrypted Volumes.
10561 09:32:15.386970 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10562 09:32:15.403922 <30>[ 19.785530] systemd[1]: Reached target Paths.
10563 09:32:15.407210 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10564 09:32:15.422899 <30>[ 19.805063] systemd[1]: Reached target Remote File Systems.
10565 09:32:15.429309 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10566 09:32:15.446984 <30>[ 19.829429] systemd[1]: Reached target Slices.
10567 09:32:15.453768 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10568 09:32:15.467163 <30>[ 19.849069] systemd[1]: Reached target Swap.
10569 09:32:15.470006 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10570 09:32:15.490546 <30>[ 19.869564] systemd[1]: Listening on initctl Compatibility Named Pipe.
10571 09:32:15.496893 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10572 09:32:15.503963 <30>[ 19.885759] systemd[1]: Listening on Journal Audit Socket.
10573 09:32:15.510313 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10574 09:32:15.528440 <30>[ 19.910455] systemd[1]: Listening on Journal Socket (/dev/log).
10575 09:32:15.534859 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10576 09:32:15.551355 <30>[ 19.933621] systemd[1]: Listening on Journal Socket.
10577 09:32:15.557869 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10578 09:32:15.576014 <30>[ 19.954635] systemd[1]: Listening on Network Service Netlink Socket.
10579 09:32:15.581887 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10580 09:32:15.597967 <30>[ 19.980264] systemd[1]: Listening on udev Control Socket.
10581 09:32:15.604482 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10582 09:32:15.619447 <30>[ 20.001508] systemd[1]: Listening on udev Kernel Socket.
10583 09:32:15.625942 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10584 09:32:15.679244 <30>[ 20.061312] systemd[1]: Mounting Huge Pages File System...
10585 09:32:15.685654 Mounting [0;1;39mHuge Pages File System[0m...
10586 09:32:15.702921 <30>[ 20.085498] systemd[1]: Mounting POSIX Message Queue File System...
10587 09:32:15.709866 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10588 09:32:15.730871 <30>[ 20.113422] systemd[1]: Mounting Kernel Debug File System...
10589 09:32:15.737647 Mounting [0;1;39mKernel Debug File System[0m...
10590 09:32:15.754388 <30>[ 20.133561] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10591 09:32:15.775129 <30>[ 20.154243] systemd[1]: Starting Create list of static device nodes for the current kernel...
10592 09:32:15.781844 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10593 09:32:15.801722 <30>[ 20.184055] systemd[1]: Starting Load Kernel Module configfs...
10594 09:32:15.808095 Starting [0;1;39mLoad Kernel Module configfs[0m...
10595 09:32:15.827521 <30>[ 20.209990] systemd[1]: Starting Load Kernel Module drm...
10596 09:32:15.834149 Starting [0;1;39mLoad Kernel Module drm[0m...
10597 09:32:15.849864 <30>[ 20.232317] systemd[1]: Starting Load Kernel Module fuse...
10598 09:32:15.856521 Starting [0;1;39mLoad Kernel Module fuse[0m...
10599 09:32:15.889488 <6>[ 20.271929] fuse: init (API version 7.37)
10600 09:32:15.899309 <30>[ 20.272719] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10601 09:32:15.935258 <30>[ 20.317793] systemd[1]: Starting Journal Service...
10602 09:32:15.941918 Starting [0;1;39mJournal Service[0m...
10603 09:32:15.965005 <30>[ 20.347326] systemd[1]: Starting Load Kernel Modules...
10604 09:32:15.971364 Starting [0;1;39mLoad Kernel Modules[0m...
10605 09:32:15.995610 <30>[ 20.374925] systemd[1]: Starting Remount Root and Kernel File Systems...
10606 09:32:16.002190 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10607 09:32:16.019243 <30>[ 20.402164] systemd[1]: Starting Coldplug All udev Devices...
10608 09:32:16.025912 Starting [0;1;39mColdplug All udev Devices[0m...
10609 09:32:16.041963 <30>[ 20.424537] systemd[1]: Mounted Huge Pages File System.
10610 09:32:16.048453 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10611 09:32:16.058877 <3>[ 20.438306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10612 09:32:16.065399 <30>[ 20.447869] systemd[1]: Mounted POSIX Message Queue File System.
10613 09:32:16.071975 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10614 09:32:16.087045 <30>[ 20.469426] systemd[1]: Mounted Kernel Debug File System.
10615 09:32:16.097179 <3>[ 20.473107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10616 09:32:16.103578 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10617 09:32:16.123270 <30>[ 20.502104] systemd[1]: Finished Create list of static device nodes for the current kernel.
10618 09:32:16.136665 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 20.515396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 09:32:16.139704 for the current kernel[0m.
10620 09:32:16.155954 <30>[ 20.537990] systemd[1]: modprobe@configfs.service: Succeeded.
10621 09:32:16.162554 <30>[ 20.544749] systemd[1]: Finished Load Kernel Module configfs.
10622 09:32:16.172900 <3>[ 20.549147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 09:32:16.179429 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10624 09:32:16.195933 <30>[ 20.577884] systemd[1]: modprobe@drm.service: Succeeded.
10625 09:32:16.206323 <3>[ 20.582123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10626 09:32:16.209067 <30>[ 20.584193] systemd[1]: Finished Load Kernel Module drm.
10627 09:32:16.215906 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10628 09:32:16.232499 <30>[ 20.614377] systemd[1]: modprobe@fuse.service: Succeeded.
10629 09:32:16.242239 <3>[ 20.614688] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10630 09:32:16.248739 <30>[ 20.620764] systemd[1]: Finished Load Kernel Module fuse.
10631 09:32:16.252101 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10632 09:32:16.268460 <30>[ 20.650977] systemd[1]: Finished Load Kernel Modules.
10633 09:32:16.278609 <3>[ 20.652569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 09:32:16.285132 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10635 09:32:16.299931 <30>[ 20.682095] systemd[1]: Finished Remount Root and Kernel File Systems.
10636 09:32:16.310260 <3>[ 20.688921] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 09:32:16.316790 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10638 09:32:16.340585 <3>[ 20.719518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 09:32:16.365467 <30>[ 20.747715] systemd[1]: Mounting FUSE Control File System...
10640 09:32:16.375339 <3>[ 20.753259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10641 09:32:16.381879 Mounting [0;1;39mFUSE Control File System[0m...
10642 09:32:16.397875 <30>[ 20.779821] systemd[1]: Mounting Kernel Configuration File System...
10643 09:32:16.404547 Mounting [0;1;39mKernel Configuration File System[0m...
10644 09:32:16.427993 <30>[ 20.806995] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10645 09:32:16.438055 <30>[ 20.816021] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10646 09:32:16.475593 <30>[ 20.858072] systemd[1]: Starting Load/Save Random Seed...
10647 09:32:16.482417 Starting [0;1;39mLoad/Save Random Seed[0m...
10648 09:32:16.501474 <4>[ 20.873785] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10649 09:32:16.511323 <3>[ 20.889464] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10650 09:32:16.514670 <30>[ 20.894667] systemd[1]: Starting Apply Kernel Variables...
10651 09:32:16.520905 Starting [0;1;39mApply Kernel Variables[0m...
10652 09:32:16.541033 <30>[ 20.923462] systemd[1]: Starting Create System Users...
10653 09:32:16.547728 Starting [0;1;39mCreate System Users[0m...
10654 09:32:16.566494 <30>[ 20.948749] systemd[1]: Started Journal Service.
10655 09:32:16.573421 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10656 09:32:16.596091 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10657 09:32:16.610377 See 'systemctl status systemd-udev-trigger.service' for details.
10658 09:32:16.627230 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10659 09:32:16.642930 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10660 09:32:16.660169 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10661 09:32:16.676790 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10662 09:32:16.696748 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10663 09:32:16.755926 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10664 09:32:16.773758 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10665 09:32:16.808811 <46>[ 21.188081] systemd-journald[299]: Received client request to flush runtime journal.
10666 09:32:16.841769 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10667 09:32:16.859254 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10668 09:32:16.874872 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10669 09:32:16.926730 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10670 09:32:18.221177 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10671 09:32:18.267384 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10672 09:32:18.286346 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10673 09:32:18.312576 Starting [0;1;39mNetwork Service[0m...
10674 09:32:18.620485 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10675 09:32:18.641088 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10676 09:32:18.686937 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10677 09:32:18.971053 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10678 09:32:18.989352 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10679 09:32:19.023096 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10680 09:32:19.044587 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10681 09:32:19.058807 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10682 09:32:19.075178 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10683 09:32:19.123135 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10684 09:32:19.175262 Starting [0;1;39mNetwork Name Resolution[0m...
10685 09:32:19.205361 Starting [0;1;39mNetwork Time Synchronization[0m...
10686 09:32:19.224341 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10687 09:32:19.309058 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10688 09:32:19.642490 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10689 09:32:19.658845 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10690 09:32:19.677551 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10691 09:32:19.690212 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10692 09:32:19.706435 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10693 09:32:19.756944 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10694 09:32:19.782380 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10695 09:32:19.800883 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10696 09:32:19.824775 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10697 09:32:19.838405 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10698 09:32:19.863982 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10699 09:32:19.878650 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10700 09:32:19.898518 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10701 09:32:19.947094 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10702 09:32:20.062354 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10703 09:32:20.151044 Starting [0;1;39mUser Login Management[0m...
10704 09:32:20.167511 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10705 09:32:20.183125 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10706 09:32:20.201464 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10707 09:32:20.250971 Starting [0;1;39mPermit User Sessions[0m...
10708 09:32:20.352587 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10709 09:32:20.372131 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10710 09:32:20.419592 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10711 09:32:20.449146 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10712 09:32:20.455196 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10713 09:32:20.473230 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10714 09:32:20.492659 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10715 09:32:20.511191 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10716 09:32:20.567214 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10717 09:32:20.621806 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10718 09:32:20.672921
10719 09:32:20.673427
10720 09:32:20.676310 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10721 09:32:20.676785
10722 09:32:20.679786 debian-bullseye-arm64 login: root (automatic login)
10723 09:32:20.680397
10724 09:32:20.680935
10725 09:32:21.040965 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
10726 09:32:21.041480
10727 09:32:21.047399 The programs included with the Debian GNU/Linux system are free software;
10728 09:32:21.054302 the exact distribution terms for each program are described in the
10729 09:32:21.057327 individual files in /usr/share/doc/*/copyright.
10730 09:32:21.057943
10731 09:32:21.064283 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10732 09:32:21.067272 permitted by applicable law.
10733 09:32:21.957820 Matched prompt #10: / #
10735 09:32:21.959098 Setting prompt string to ['/ #']
10736 09:32:21.959601 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10738 09:32:21.960751 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10739 09:32:21.961255 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10740 09:32:21.961651 Setting prompt string to ['/ #']
10741 09:32:21.962141 Forcing a shell prompt, looking for ['/ #']
10743 09:32:22.013309 / #
10744 09:32:22.013993 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10745 09:32:22.014464 Waiting using forced prompt support (timeout 00:02:30)
10746 09:32:22.019809
10747 09:32:22.020848 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10748 09:32:22.021415 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10750 09:32:22.122616 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f'
10751 09:32:22.128475 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826813/extract-nfsrootfs-komjjw6f'
10753 09:32:22.229565 / # export NFS_SERVER_IP='192.168.201.1'
10754 09:32:22.236315 export NFS_SERVER_IP='192.168.201.1'
10755 09:32:22.237268 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10756 09:32:22.237881 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10757 09:32:22.238401 end: 2 depthcharge-action (duration 00:01:35) [common]
10758 09:32:22.238915 start: 3 lava-test-retry (timeout 00:07:45) [common]
10759 09:32:22.239414 start: 3.1 lava-test-shell (timeout 00:07:45) [common]
10760 09:32:22.239903 Using namespace: common
10762 09:32:22.341310 / # #
10763 09:32:22.342001 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10764 09:32:22.348028 #
10765 09:32:22.348995 Using /lava-11826813
10767 09:32:22.450431 / # export SHELL=/bin/bash
10768 09:32:22.456903 export SHELL=/bin/bash
10770 09:32:22.558723 / # . /lava-11826813/environment
10771 09:32:22.565255 . /lava-11826813/environment
10773 09:32:22.672738 / # /lava-11826813/bin/lava-test-runner /lava-11826813/0
10774 09:32:22.673402 Test shell timeout: 10s (minimum of the action and connection timeout)
10775 09:32:22.679433 /lava-11826813/bin/lava-test-runner /lava-11826813/0
10776 09:32:22.981368 + export TESTRUN_ID=0_timesync-off
10777 09:32:22.984495 + TESTRUN_ID=0_timesync-off
10778 09:32:22.988120 + cd /lava-11826813/0/tests/0_timesync-off
10779 09:32:22.990900 ++ cat uuid
10780 09:32:22.997177 + UUID=11826813_1.6.2.3.1
10781 09:32:22.997656 + set +x
10782 09:32:23.004005 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11826813_1.6.2.3.1>
10783 09:32:23.004816 Received signal: <STARTRUN> 0_timesync-off 11826813_1.6.2.3.1
10784 09:32:23.005240 Starting test lava.0_timesync-off (11826813_1.6.2.3.1)
10785 09:32:23.005711 Skipping test definition patterns.
10786 09:32:23.007145 + systemctl stop systemd-timesyncd
10787 09:32:23.071501 + set +x
10788 09:32:23.074879 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11826813_1.6.2.3.1>
10789 09:32:23.075685 Received signal: <ENDRUN> 0_timesync-off 11826813_1.6.2.3.1
10790 09:32:23.076154 Ending use of test pattern.
10791 09:32:23.076573 Ending test lava.0_timesync-off (11826813_1.6.2.3.1), duration 0.07
10793 09:32:23.151431 + export TESTRUN_ID=1_kselftest-rtc
10794 09:32:23.154482 + TESTRUN_ID=1_kselftest-rtc
10795 09:32:23.157659 + cd /lava-11826813/0/tests/1_kselftest-rtc
10796 09:32:23.161072 ++ cat uuid
10797 09:32:23.165485 + UUID=11826813_1.6.2.3.5
10798 09:32:23.165920 + set +x
10799 09:32:23.172256 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 11826813_1.6.2.3.5>
10800 09:32:23.173000 Received signal: <STARTRUN> 1_kselftest-rtc 11826813_1.6.2.3.5
10801 09:32:23.173396 Starting test lava.1_kselftest-rtc (11826813_1.6.2.3.5)
10802 09:32:23.173831 Skipping test definition patterns.
10803 09:32:23.175719 + cd ./automated/linux/kselftest/
10804 09:32:23.198458 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10805 09:32:23.238500 INFO: install_deps skipped
10806 09:32:23.350506 --2023-10-20 09:32:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10807 09:32:23.372539 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10808 09:32:23.507938 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10809 09:32:23.641840 HTTP request sent, awaiting response... 200 OK
10810 09:32:23.644932 Length: 2964156 (2.8M) [application/octet-stream]
10811 09:32:23.648377 Saving to: 'kselftest.tar.xz'
10812 09:32:23.648950
10813 09:32:23.649328
10814 09:32:23.910431 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10815 09:32:24.177385 kselftest.tar.xz 1%[ ] 49.22K 188KB/s
10816 09:32:24.715849 kselftest.tar.xz 7%[> ] 213.25K 408KB/s
10817 09:32:25.014002 kselftest.tar.xz 29%[====> ] 842.51K 803KB/s
10818 09:32:25.235642 kselftest.tar.xz 95%[==================> ] 2.71M 2.02MB/s
10819 09:32:25.420082 kselftest.tar.xz 98%[==================> ] 2.78M 1.78MB/s
10820 09:32:25.426320 kselftest.tar.xz 100%[===================>] 2.83M 1.62MB/s in 1.7s
10821 09:32:25.426802
10822 09:32:25.684722 2023-10-20 09:32:25 (1.62 MB/s) - 'kselftest.tar.xz' saved [2964156/2964156]
10823 09:32:25.685130
10824 09:32:31.610579 skiplist:
10825 09:32:31.614102 ========================================
10826 09:32:31.617226 ========================================
10827 09:32:31.668479 rtc:rtctest
10828 09:32:31.689786 ============== Tests to run ===============
10829 09:32:31.690221 rtc:rtctest
10830 09:32:31.696290 ===========End Tests to run ===============
10831 09:32:31.699795 shardfile-rtc pass
10832 09:32:31.805761 <12>[ 36.190099] kselftest: Running tests in rtc
10833 09:32:31.815516 TAP version 13
10834 09:32:31.827976 1..1
10835 09:32:31.858618 # selftests: rtc: rtctest
10836 09:32:32.313977 # TAP version 13
10837 09:32:32.314605 # 1..8
10838 09:32:32.317218 # # Starting 8 tests from 2 test cases.
10839 09:32:32.320562 # # RUN rtc.date_read ...
10840 09:32:32.326989 # # rtctest.c:49:date_read:Current RTC date/time is 20/10/2023 09:32:32.
10841 09:32:32.330372 # # OK rtc.date_read
10842 09:32:32.333623 # ok 1 rtc.date_read
10843 09:32:32.336870 # # RUN rtc.date_read_loop ...
10844 09:32:32.347044 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
10845 09:32:42.008380 <6>[ 46.396583] vpu: disabling
10846 09:32:42.011416 <6>[ 46.399686] vproc2: disabling
10847 09:32:42.014464 <6>[ 46.403011] vproc1: disabling
10848 09:32:42.017797 <6>[ 46.406536] vaud18: disabling
10849 09:32:42.024928 <6>[ 46.410076] vsram_others: disabling
10850 09:32:42.027858 <6>[ 46.414044] va09: disabling
10851 09:32:42.031178 <6>[ 46.417212] vsram_md: disabling
10852 09:32:42.034850 <6>[ 46.420775] Vgpu: disabling
10853 09:33:02.798685 # # rtctest.c:115:date_read_loop:Performed 2667 RTC time reads.
10854 09:33:02.802162 # # OK rtc.date_read_loop
10855 09:33:02.805307 # ok 2 rtc.date_read_loop
10856 09:33:02.808879 # # RUN rtc.uie_read ...
10857 09:33:05.778684 # # OK rtc.uie_read
10858 09:33:05.781291 # ok 3 rtc.uie_read
10859 09:33:05.785059 # # RUN rtc.uie_select ...
10860 09:33:08.778136 # # OK rtc.uie_select
10861 09:33:08.780795 # ok 4 rtc.uie_select
10862 09:33:08.784326 # # RUN rtc.alarm_alm_set ...
10863 09:33:08.791075 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 09:33:12.
10864 09:33:08.794369 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
10865 09:33:08.800681 # # alarm_alm_set: Test terminated by assertion
10866 09:33:08.804237 # # FAIL rtc.alarm_alm_set
10867 09:33:08.807582 # not ok 5 rtc.alarm_alm_set
10868 09:33:08.810715 # # RUN rtc.alarm_wkalm_set ...
10869 09:33:08.817227 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 20/10/2023 09:33:12.
10870 09:33:11.780744 # # OK rtc.alarm_wkalm_set
10871 09:33:11.781320 # ok 6 rtc.alarm_wkalm_set
10872 09:33:11.787296 # # RUN rtc.alarm_alm_set_minute ...
10873 09:33:11.791409 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 09:34:00.
10874 09:33:11.797575 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
10875 09:33:11.803782 # # alarm_alm_set_minute: Test terminated by assertion
10876 09:33:11.807181 # # FAIL rtc.alarm_alm_set_minute
10877 09:33:11.810140 # not ok 7 rtc.alarm_alm_set_minute
10878 09:33:11.813578 # # RUN rtc.alarm_wkalm_set_minute ...
10879 09:33:11.820322 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 20/10/2023 09:34:00.
10880 09:33:59.774765 # # OK rtc.alarm_wkalm_set_minute
10881 09:33:59.778315 # ok 8 rtc.alarm_wkalm_set_minute
10882 09:33:59.781460 # # FAILED: 6 / 8 tests passed.
10883 09:33:59.784682 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
10884 09:33:59.787762 not ok 1 selftests: rtc: rtctest # exit=1
10885 09:34:00.418052 rtc_rtctest_rtc_date_read pass
10886 09:34:00.421023 rtc_rtctest_rtc_date_read_loop pass
10887 09:34:00.424511 rtc_rtctest_rtc_uie_read pass
10888 09:34:00.427842 rtc_rtctest_rtc_uie_select pass
10889 09:34:00.431221 rtc_rtctest_rtc_alarm_alm_set fail
10890 09:34:00.434733 rtc_rtctest_rtc_alarm_wkalm_set pass
10891 09:34:00.437534 rtc_rtctest_rtc_alarm_alm_set_minute fail
10892 09:34:00.441019 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
10893 09:34:00.444077 rtc_rtctest fail
10894 09:34:00.450824 + ../../utils/send-to-lava.sh ./output/result.txt
10895 09:34:00.532217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
10896 09:34:00.533028 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
10898 09:34:00.593819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
10899 09:34:00.594517 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
10901 09:34:00.646361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
10902 09:34:00.647054 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
10904 09:34:00.696907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
10905 09:34:00.697818 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
10907 09:34:00.746293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
10908 09:34:00.746568 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
10910 09:34:00.802589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
10911 09:34:00.803337 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
10913 09:34:00.862957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
10914 09:34:00.863668 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
10916 09:34:00.921402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
10917 09:34:00.922107 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
10919 09:34:00.981224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
10920 09:34:00.981927 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
10922 09:34:01.028052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
10923 09:34:01.028543 + set +x
10924 09:34:01.029154 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
10926 09:34:01.034800 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 11826813_1.6.2.3.5>
10927 09:34:01.035235 <LAVA_TEST_RUNNER EXIT>
10928 09:34:01.035831 Received signal: <ENDRUN> 1_kselftest-rtc 11826813_1.6.2.3.5
10929 09:34:01.036239 Ending use of test pattern.
10930 09:34:01.036576 Ending test lava.1_kselftest-rtc (11826813_1.6.2.3.5), duration 97.86
10932 09:34:01.037674 ok: lava_test_shell seems to have completed
10933 09:34:01.038361 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
10934 09:34:01.038819 end: 3.1 lava-test-shell (duration 00:01:39) [common]
10935 09:34:01.039242 end: 3 lava-test-retry (duration 00:01:39) [common]
10936 09:34:01.039693 start: 4 finalize (timeout 00:06:07) [common]
10937 09:34:01.040156 start: 4.1 power-off (timeout 00:00:30) [common]
10938 09:34:01.040946 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10939 09:34:01.161884 >> Command sent successfully.
10940 09:34:01.165725 Returned 0 in 0 seconds
10941 09:34:01.266702 end: 4.1 power-off (duration 00:00:00) [common]
10943 09:34:01.268526 start: 4.2 read-feedback (timeout 00:06:06) [common]
10944 09:34:01.269971 Listened to connection for namespace 'common' for up to 1s
10945 09:34:01.270865 Listened to connection for namespace 'common' for up to 1s
10946 09:34:02.270488 Finalising connection for namespace 'common'
10947 09:34:02.271179 Disconnecting from shell: Finalise
10948 09:34:02.271604 / #
10949 09:34:02.372639 end: 4.2 read-feedback (duration 00:00:01) [common]
10950 09:34:02.373368 end: 4 finalize (duration 00:00:01) [common]
10951 09:34:02.373961 Cleaning after the job
10952 09:34:02.374564 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/ramdisk
10953 09:34:02.388906 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/kernel
10954 09:34:02.423098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/dtb
10955 09:34:02.423399 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/nfsrootfs
10956 09:34:02.517019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826813/tftp-deploy-pt1lsnrn/modules
10957 09:34:02.524418 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826813
10958 09:34:03.158611 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826813
10959 09:34:03.158800 Job finished correctly