Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 38
- Errors: 0
- Boot result: PASS
1 09:30:15.434861 lava-dispatcher, installed at version: 2023.08
2 09:30:15.435052 start: 0 validate
3 09:30:15.435178 Start time: 2023-10-20 09:30:15.435170+00:00 (UTC)
4 09:30:15.435290 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:30:15.435422 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:30:15.695634 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:30:15.696367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:30:15.701549 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:30:15.702265 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:30:15.971922 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:30:15.972669 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:30:16.241168 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:30:16.241416 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:30:16.509595 validate duration: 1.07
16 09:30:16.509918 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:30:16.510014 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:30:16.510102 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:30:16.510218 Not decompressing ramdisk as can be used compressed.
20 09:30:16.510300 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 09:30:16.510368 saving as /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/ramdisk/initrd.cpio.gz
22 09:30:16.510433 total size: 4665398 (4 MB)
23 09:30:16.511453 progress 0 % (0 MB)
24 09:30:16.513025 progress 5 % (0 MB)
25 09:30:16.514296 progress 10 % (0 MB)
26 09:30:16.515508 progress 15 % (0 MB)
27 09:30:16.516737 progress 20 % (0 MB)
28 09:30:16.518073 progress 25 % (1 MB)
29 09:30:16.519255 progress 30 % (1 MB)
30 09:30:16.520518 progress 35 % (1 MB)
31 09:30:16.521834 progress 40 % (1 MB)
32 09:30:16.523240 progress 45 % (2 MB)
33 09:30:16.524460 progress 50 % (2 MB)
34 09:30:16.525695 progress 55 % (2 MB)
35 09:30:16.526905 progress 60 % (2 MB)
36 09:30:16.528091 progress 65 % (2 MB)
37 09:30:16.529324 progress 70 % (3 MB)
38 09:30:16.530530 progress 75 % (3 MB)
39 09:30:16.531711 progress 80 % (3 MB)
40 09:30:16.533155 progress 85 % (3 MB)
41 09:30:16.534404 progress 90 % (4 MB)
42 09:30:16.535673 progress 95 % (4 MB)
43 09:30:16.536869 progress 100 % (4 MB)
44 09:30:16.537072 4 MB downloaded in 0.03 s (167.02 MB/s)
45 09:30:16.537228 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:30:16.537463 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:30:16.537548 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:30:16.537631 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:30:16.537760 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:30:16.537827 saving as /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/kernel/Image
52 09:30:16.537889 total size: 49236480 (46 MB)
53 09:30:16.537949 No compression specified
54 09:30:16.538999 progress 0 % (0 MB)
55 09:30:16.551304 progress 5 % (2 MB)
56 09:30:16.563442 progress 10 % (4 MB)
57 09:30:16.575896 progress 15 % (7 MB)
58 09:30:16.588133 progress 20 % (9 MB)
59 09:30:16.600483 progress 25 % (11 MB)
60 09:30:16.612983 progress 30 % (14 MB)
61 09:30:16.625450 progress 35 % (16 MB)
62 09:30:16.638047 progress 40 % (18 MB)
63 09:30:16.650408 progress 45 % (21 MB)
64 09:30:16.662732 progress 50 % (23 MB)
65 09:30:16.675152 progress 55 % (25 MB)
66 09:30:16.687485 progress 60 % (28 MB)
67 09:30:16.699750 progress 65 % (30 MB)
68 09:30:16.712256 progress 70 % (32 MB)
69 09:30:16.724763 progress 75 % (35 MB)
70 09:30:16.737430 progress 80 % (37 MB)
71 09:30:16.749827 progress 85 % (39 MB)
72 09:30:16.762133 progress 90 % (42 MB)
73 09:30:16.774442 progress 95 % (44 MB)
74 09:30:16.786685 progress 100 % (46 MB)
75 09:30:16.786893 46 MB downloaded in 0.25 s (188.58 MB/s)
76 09:30:16.787044 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:30:16.787275 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:30:16.787363 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:30:16.787450 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:30:16.787583 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:30:16.787657 saving as /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/dtb/mt8192-asurada-spherion-r0.dtb
83 09:30:16.787718 total size: 47278 (0 MB)
84 09:30:16.787779 No compression specified
85 09:30:16.788882 progress 69 % (0 MB)
86 09:30:16.789188 progress 100 % (0 MB)
87 09:30:16.789342 0 MB downloaded in 0.00 s (27.81 MB/s)
88 09:30:16.789465 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:30:16.789687 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:30:16.789773 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:30:16.789855 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:30:16.789965 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 09:30:16.790033 saving as /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/nfsrootfs/full.rootfs.tar
95 09:30:16.790097 total size: 89451516 (85 MB)
96 09:30:16.790159 Using unxz to decompress xz
97 09:30:16.793645 progress 0 % (0 MB)
98 09:30:17.003078 progress 5 % (4 MB)
99 09:30:17.217226 progress 10 % (8 MB)
100 09:30:17.468063 progress 15 % (12 MB)
101 09:30:17.661185 progress 20 % (17 MB)
102 09:30:17.755212 progress 25 % (21 MB)
103 09:30:17.997523 progress 30 % (25 MB)
104 09:30:18.276331 progress 35 % (29 MB)
105 09:30:18.537027 progress 40 % (34 MB)
106 09:30:18.799404 progress 45 % (38 MB)
107 09:30:19.046434 progress 50 % (42 MB)
108 09:30:19.307087 progress 55 % (46 MB)
109 09:30:19.558873 progress 60 % (51 MB)
110 09:30:19.826248 progress 65 % (55 MB)
111 09:30:20.118880 progress 70 % (59 MB)
112 09:30:20.419695 progress 75 % (64 MB)
113 09:30:20.719947 progress 80 % (68 MB)
114 09:30:20.973837 progress 85 % (72 MB)
115 09:30:21.290222 progress 90 % (76 MB)
116 09:30:21.571747 progress 95 % (81 MB)
117 09:30:21.840068 progress 100 % (85 MB)
118 09:30:21.846335 85 MB downloaded in 5.06 s (16.87 MB/s)
119 09:30:21.846576 end: 1.4.1 http-download (duration 00:00:05) [common]
121 09:30:21.846832 end: 1.4 download-retry (duration 00:00:05) [common]
122 09:30:21.846924 start: 1.5 download-retry (timeout 00:09:55) [common]
123 09:30:21.847011 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 09:30:21.847161 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:30:21.847232 saving as /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/modules/modules.tar
126 09:30:21.847294 total size: 8614716 (8 MB)
127 09:30:21.847359 Using unxz to decompress xz
128 09:30:21.850979 progress 0 % (0 MB)
129 09:30:21.872412 progress 5 % (0 MB)
130 09:30:21.896156 progress 10 % (0 MB)
131 09:30:21.919738 progress 15 % (1 MB)
132 09:30:21.943365 progress 20 % (1 MB)
133 09:30:21.967513 progress 25 % (2 MB)
134 09:30:21.993581 progress 30 % (2 MB)
135 09:30:22.020218 progress 35 % (2 MB)
136 09:30:22.044148 progress 40 % (3 MB)
137 09:30:22.068342 progress 45 % (3 MB)
138 09:30:22.093531 progress 50 % (4 MB)
139 09:30:22.118213 progress 55 % (4 MB)
140 09:30:22.144728 progress 60 % (4 MB)
141 09:30:22.170181 progress 65 % (5 MB)
142 09:30:22.196892 progress 70 % (5 MB)
143 09:30:22.220393 progress 75 % (6 MB)
144 09:30:22.247133 progress 80 % (6 MB)
145 09:30:22.273712 progress 85 % (7 MB)
146 09:30:22.298819 progress 90 % (7 MB)
147 09:30:22.328683 progress 95 % (7 MB)
148 09:30:22.356759 progress 100 % (8 MB)
149 09:30:22.363123 8 MB downloaded in 0.52 s (15.93 MB/s)
150 09:30:22.363372 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:30:22.363630 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:30:22.363723 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 09:30:22.363824 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 09:30:23.932622 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8
156 09:30:23.932833 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:30:23.932940 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 09:30:23.933140 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02
159 09:30:23.933266 makedir: /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin
160 09:30:23.933366 makedir: /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/tests
161 09:30:23.933462 makedir: /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/results
162 09:30:23.933567 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-add-keys
163 09:30:23.933708 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-add-sources
164 09:30:23.933831 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-background-process-start
165 09:30:23.933970 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-background-process-stop
166 09:30:23.934106 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-common-functions
167 09:30:23.934223 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-echo-ipv4
168 09:30:23.934342 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-install-packages
169 09:30:23.934459 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-installed-packages
170 09:30:23.934577 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-os-build
171 09:30:23.934697 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-probe-channel
172 09:30:23.934815 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-probe-ip
173 09:30:23.934934 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-target-ip
174 09:30:23.935052 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-target-mac
175 09:30:23.935170 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-target-storage
176 09:30:23.935291 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-case
177 09:30:23.935412 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-event
178 09:30:23.935531 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-feedback
179 09:30:23.935648 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-raise
180 09:30:23.935765 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-reference
181 09:30:23.935882 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-runner
182 09:30:23.935999 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-set
183 09:30:23.936116 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-test-shell
184 09:30:23.936235 Updating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-install-packages (oe)
185 09:30:23.936383 Updating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/bin/lava-installed-packages (oe)
186 09:30:23.936500 Creating /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/environment
187 09:30:23.936625 LAVA metadata
188 09:30:23.936710 - LAVA_JOB_ID=11826809
189 09:30:23.936774 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:30:23.936874 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 09:30:23.936983 skipped lava-vland-overlay
192 09:30:23.937057 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:30:23.937136 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 09:30:23.937198 skipped lava-multinode-overlay
195 09:30:23.937270 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:30:23.937347 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 09:30:23.937421 Loading test definitions
198 09:30:23.937508 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 09:30:23.937581 Using /lava-11826809 at stage 0
200 09:30:23.937868 uuid=11826809_1.6.2.3.1 testdef=None
201 09:30:23.937957 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:30:23.938044 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 09:30:23.938515 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:30:23.938736 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 09:30:23.939317 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:30:23.939543 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 09:30:23.940112 runner path: /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/0/tests/0_lc-compliance test_uuid 11826809_1.6.2.3.1
210 09:30:23.940263 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:30:23.940466 Creating lava-test-runner.conf files
213 09:30:23.940530 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826809/lava-overlay-mdux2c02/lava-11826809/0 for stage 0
214 09:30:23.940617 - 0_lc-compliance
215 09:30:23.940714 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 09:30:23.940800 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 09:30:23.946616 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 09:30:23.946720 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 09:30:23.946806 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 09:30:23.946890 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 09:30:23.946975 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 09:30:24.060947 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 09:30:24.061339 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 09:30:24.061452 extracting modules file /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8
225 09:30:24.263244 extracting modules file /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826809/extract-overlay-ramdisk-1vmixr4c/ramdisk
226 09:30:24.469904 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 09:30:24.470080 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 09:30:24.470171 [common] Applying overlay to NFS
229 09:30:24.470243 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826809/compress-overlay-p4ofrb49/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8
230 09:30:24.476513 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 09:30:24.476630 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 09:30:24.476722 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 09:30:24.476811 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 09:30:24.476893 Building ramdisk /var/lib/lava/dispatcher/tmp/11826809/extract-overlay-ramdisk-1vmixr4c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826809/extract-overlay-ramdisk-1vmixr4c/ramdisk
235 09:30:24.756409 >> 119368 blocks
236 09:30:26.697215 rename /var/lib/lava/dispatcher/tmp/11826809/extract-overlay-ramdisk-1vmixr4c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/ramdisk/ramdisk.cpio.gz
237 09:30:26.697643 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 09:30:26.697763 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 09:30:26.697869 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 09:30:26.697979 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/kernel/Image'
241 09:30:39.120969 Returned 0 in 12 seconds
242 09:30:39.221606 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/kernel/image.itb
243 09:30:39.532785 output: FIT description: Kernel Image image with one or more FDT blobs
244 09:30:39.533144 output: Created: Fri Oct 20 10:30:39 2023
245 09:30:39.533218 output: Image 0 (kernel-1)
246 09:30:39.533286 output: Description:
247 09:30:39.533351 output: Created: Fri Oct 20 10:30:39 2023
248 09:30:39.533414 output: Type: Kernel Image
249 09:30:39.533476 output: Compression: lzma compressed
250 09:30:39.533537 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
251 09:30:39.533595 output: Architecture: AArch64
252 09:30:39.533652 output: OS: Linux
253 09:30:39.533707 output: Load Address: 0x00000000
254 09:30:39.533763 output: Entry Point: 0x00000000
255 09:30:39.533820 output: Hash algo: crc32
256 09:30:39.533879 output: Hash value: 05d3904e
257 09:30:39.533939 output: Image 1 (fdt-1)
258 09:30:39.533994 output: Description: mt8192-asurada-spherion-r0
259 09:30:39.534047 output: Created: Fri Oct 20 10:30:39 2023
260 09:30:39.534101 output: Type: Flat Device Tree
261 09:30:39.534154 output: Compression: uncompressed
262 09:30:39.534208 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 09:30:39.534261 output: Architecture: AArch64
264 09:30:39.534314 output: Hash algo: crc32
265 09:30:39.534367 output: Hash value: cc4352de
266 09:30:39.534420 output: Image 2 (ramdisk-1)
267 09:30:39.534473 output: Description: unavailable
268 09:30:39.534526 output: Created: Fri Oct 20 10:30:39 2023
269 09:30:39.534579 output: Type: RAMDisk Image
270 09:30:39.534632 output: Compression: Unknown Compression
271 09:30:39.534685 output: Data Size: 17794327 Bytes = 17377.27 KiB = 16.97 MiB
272 09:30:39.534738 output: Architecture: AArch64
273 09:30:39.534791 output: OS: Linux
274 09:30:39.534843 output: Load Address: unavailable
275 09:30:39.534896 output: Entry Point: unavailable
276 09:30:39.534949 output: Hash algo: crc32
277 09:30:39.535001 output: Hash value: 905c16eb
278 09:30:39.535054 output: Default Configuration: 'conf-1'
279 09:30:39.535107 output: Configuration 0 (conf-1)
280 09:30:39.535159 output: Description: mt8192-asurada-spherion-r0
281 09:30:39.535212 output: Kernel: kernel-1
282 09:30:39.535265 output: Init Ramdisk: ramdisk-1
283 09:30:39.535319 output: FDT: fdt-1
284 09:30:39.535372 output: Loadables: kernel-1
285 09:30:39.535425 output:
286 09:30:39.535622 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 09:30:39.535724 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 09:30:39.535821 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 09:30:39.535910 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 09:30:39.535985 No LXC device requested
291 09:30:39.536062 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 09:30:39.536148 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 09:30:39.536225 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 09:30:39.536293 Checking files for TFTP limit of 4294967296 bytes.
295 09:30:39.536777 end: 1 tftp-deploy (duration 00:00:23) [common]
296 09:30:39.536882 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 09:30:39.536985 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 09:30:39.537115 substitutions:
299 09:30:39.537183 - {DTB}: 11826809/tftp-deploy-_vzq_rat/dtb/mt8192-asurada-spherion-r0.dtb
300 09:30:39.537248 - {INITRD}: 11826809/tftp-deploy-_vzq_rat/ramdisk/ramdisk.cpio.gz
301 09:30:39.537307 - {KERNEL}: 11826809/tftp-deploy-_vzq_rat/kernel/Image
302 09:30:39.537365 - {LAVA_MAC}: None
303 09:30:39.537420 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8
304 09:30:39.537477 - {NFS_SERVER_IP}: 192.168.201.1
305 09:30:39.537539 - {PRESEED_CONFIG}: None
306 09:30:39.537595 - {PRESEED_LOCAL}: None
307 09:30:39.537648 - {RAMDISK}: 11826809/tftp-deploy-_vzq_rat/ramdisk/ramdisk.cpio.gz
308 09:30:39.537703 - {ROOT_PART}: None
309 09:30:39.537756 - {ROOT}: None
310 09:30:39.537811 - {SERVER_IP}: 192.168.201.1
311 09:30:39.537864 - {TEE}: None
312 09:30:39.537919 Parsed boot commands:
313 09:30:39.537973 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 09:30:39.538152 Parsed boot commands: tftpboot 192.168.201.1 11826809/tftp-deploy-_vzq_rat/kernel/image.itb 11826809/tftp-deploy-_vzq_rat/kernel/cmdline
315 09:30:39.538240 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 09:30:39.538329 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 09:30:39.538423 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 09:30:39.538514 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 09:30:39.538586 Not connected, no need to disconnect.
320 09:30:39.538660 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 09:30:39.538742 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 09:30:39.538814 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 09:30:39.542131 Setting prompt string to ['lava-test: # ']
324 09:30:39.542460 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 09:30:39.542567 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 09:30:39.542666 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 09:30:39.542796 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 09:30:39.542989 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 09:30:44.676277 >> Command sent successfully.
330 09:30:44.678719 Returned 0 in 5 seconds
331 09:30:44.779106 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 09:30:44.779451 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 09:30:44.779592 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 09:30:44.779687 Setting prompt string to 'Starting depthcharge on Spherion...'
336 09:30:44.779759 Changing prompt to 'Starting depthcharge on Spherion...'
337 09:30:44.779830 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 09:30:44.780093 [Enter `^Ec?' for help]
339 09:30:44.953498
340 09:30:44.953638
341 09:30:44.953711 F0: 102B 0000
342 09:30:44.953777
343 09:30:44.953840 F3: 1001 0000 [0200]
344 09:30:44.953900
345 09:30:44.956837 F3: 1001 0000
346 09:30:44.956925
347 09:30:44.957005 F7: 102D 0000
348 09:30:44.957069
349 09:30:44.957130 F1: 0000 0000
350 09:30:44.960704
351 09:30:44.960789 V0: 0000 0000 [0001]
352 09:30:44.960858
353 09:30:44.960920 00: 0007 8000
354 09:30:44.961032
355 09:30:44.964292 01: 0000 0000
356 09:30:44.964378
357 09:30:44.964448 BP: 0C00 0209 [0000]
358 09:30:44.964511
359 09:30:44.968071 G0: 1182 0000
360 09:30:44.968156
361 09:30:44.968223 EC: 0000 0021 [4000]
362 09:30:44.968285
363 09:30:44.971841 S7: 0000 0000 [0000]
364 09:30:44.971968
365 09:30:44.972041 CC: 0000 0000 [0001]
366 09:30:44.972105
367 09:30:44.975185 T0: 0000 0040 [010F]
368 09:30:44.975273
369 09:30:44.975378 Jump to BL
370 09:30:44.975484
371 09:30:45.000220
372 09:30:45.000309
373 09:30:45.000376
374 09:30:45.007519 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 09:30:45.010981 ARM64: Exception handlers installed.
376 09:30:45.014793 ARM64: Testing exception
377 09:30:45.018450 ARM64: Done test exception
378 09:30:45.025579 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 09:30:45.036230 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 09:30:45.042647 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 09:30:45.053047 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 09:30:45.059242 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 09:30:45.066131 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 09:30:45.076817 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 09:30:45.083554 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 09:30:45.103017 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 09:30:45.106432 WDT: Last reset was cold boot
388 09:30:45.109810 SPI1(PAD0) initialized at 2873684 Hz
389 09:30:45.112824 SPI5(PAD0) initialized at 992727 Hz
390 09:30:45.116391 VBOOT: Loading verstage.
391 09:30:45.123324 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 09:30:45.126262 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 09:30:45.129759 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 09:30:45.133244 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 09:30:45.140323 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 09:30:45.146873 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 09:30:45.157818 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 09:30:45.157913
399 09:30:45.157980
400 09:30:45.168034 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 09:30:45.171624 ARM64: Exception handlers installed.
402 09:30:45.175117 ARM64: Testing exception
403 09:30:45.175205 ARM64: Done test exception
404 09:30:45.181175 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 09:30:45.185037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 09:30:45.199061 Probing TPM: . done!
407 09:30:45.199223 TPM ready after 0 ms
408 09:30:45.205820 Connected to device vid:did:rid of 1ae0:0028:00
409 09:30:45.212675 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 09:30:45.216424 Initialized TPM device CR50 revision 0
411 09:30:45.282975 tlcl_send_startup: Startup return code is 0
412 09:30:45.283125 TPM: setup succeeded
413 09:30:45.294686 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 09:30:45.303528 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 09:30:45.313383 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 09:30:45.322713 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 09:30:45.326397 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 09:30:45.332916 in-header: 03 07 00 00 08 00 00 00
419 09:30:45.336298 in-data: aa e4 47 04 13 02 00 00
420 09:30:45.339849 Chrome EC: UHEPI supported
421 09:30:45.347428 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 09:30:45.351014 in-header: 03 ad 00 00 08 00 00 00
423 09:30:45.354445 in-data: 00 20 20 08 00 00 00 00
424 09:30:45.354531 Phase 1
425 09:30:45.358330 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 09:30:45.365350 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 09:30:45.369430 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 09:30:45.373203 Recovery requested (1009000e)
429 09:30:45.382306 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 09:30:45.387961 tlcl_extend: response is 0
431 09:30:45.397273 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 09:30:45.402810 tlcl_extend: response is 0
433 09:30:45.409792 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 09:30:45.429955 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 09:30:45.436920 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 09:30:45.437091
437 09:30:45.437197
438 09:30:45.446973 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 09:30:45.450298 ARM64: Exception handlers installed.
440 09:30:45.450409 ARM64: Testing exception
441 09:30:45.454013 ARM64: Done test exception
442 09:30:45.475516 pmic_efuse_setting: Set efuses in 11 msecs
443 09:30:45.478811 pmwrap_interface_init: Select PMIF_VLD_RDY
444 09:30:45.485699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 09:30:45.489544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 09:30:45.493036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 09:30:45.499742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 09:30:45.502903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 09:30:45.507003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 09:30:45.514350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 09:30:45.517625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 09:30:45.521627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 09:30:45.529048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 09:30:45.532588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 09:30:45.536200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 09:30:45.539834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 09:30:45.546535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 09:30:45.553495 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 09:30:45.557559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 09:30:45.564518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 09:30:45.572053 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 09:30:45.575665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 09:30:45.582166 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 09:30:45.585379 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 09:30:45.592252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 09:30:45.599201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 09:30:45.602702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 09:30:45.609557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 09:30:45.615878 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 09:30:45.619260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 09:30:45.625892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 09:30:45.629315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 09:30:45.632588 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 09:30:45.639169 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 09:30:45.642726 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 09:30:45.649516 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 09:30:45.653027 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 09:30:45.659449 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 09:30:45.662943 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 09:30:45.669432 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 09:30:45.673066 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 09:30:45.679456 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 09:30:45.682989 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 09:30:45.686122 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 09:30:45.693236 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 09:30:45.697032 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 09:30:45.700375 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 09:30:45.703499 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 09:30:45.710557 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 09:30:45.713499 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 09:30:45.716828 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 09:30:45.723623 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 09:30:45.726783 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 09:30:45.730432 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 09:30:45.737148 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 09:30:45.746872 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 09:30:45.750597 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 09:30:45.760322 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 09:30:45.766746 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 09:30:45.773796 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 09:30:45.777253 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 09:30:45.780346 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 09:30:45.787689 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x32
504 09:30:45.794315 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 09:30:45.797902 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 09:30:45.804233 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 09:30:45.812727 [RTC]rtc_get_frequency_meter,154: input=15, output=773
508 09:30:45.821962 [RTC]rtc_get_frequency_meter,154: input=23, output=956
509 09:30:45.831413 [RTC]rtc_get_frequency_meter,154: input=19, output=866
510 09:30:45.840849 [RTC]rtc_get_frequency_meter,154: input=17, output=818
511 09:30:45.851704 [RTC]rtc_get_frequency_meter,154: input=16, output=795
512 09:30:45.855013 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 09:30:45.858482 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 09:30:45.862258 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 09:30:45.870179 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 09:30:45.870384 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 09:30:45.874003 ADC[4]: Raw value=903245 ID=7
518 09:30:45.877248 ADC[3]: Raw value=213179 ID=1
519 09:30:45.877340 RAM Code: 0x71
520 09:30:45.884834 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 09:30:45.888744 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 09:30:45.895922 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 09:30:45.903570 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 09:30:45.907373 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 09:30:45.910740 in-header: 03 07 00 00 08 00 00 00
526 09:30:45.913737 in-data: aa e4 47 04 13 02 00 00
527 09:30:45.917373 Chrome EC: UHEPI supported
528 09:30:45.923740 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 09:30:45.927271 in-header: 03 ed 00 00 08 00 00 00
530 09:30:45.930584 in-data: 80 20 60 08 00 00 00 00
531 09:30:45.934055 MRC: failed to locate region type 0.
532 09:30:45.940475 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 09:30:45.940580 DRAM-K: Running full calibration
534 09:30:45.947250 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 09:30:45.950672 header.status = 0x0
536 09:30:45.953924 header.version = 0x6 (expected: 0x6)
537 09:30:45.957492 header.size = 0xd00 (expected: 0xd00)
538 09:30:45.957582 header.flags = 0x0
539 09:30:45.964138 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 09:30:45.983469 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
541 09:30:45.990311 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 09:30:45.993761 dram_init: ddr_geometry: 2
543 09:30:45.993837 [EMI] MDL number = 2
544 09:30:45.997403 [EMI] Get MDL freq = 0
545 09:30:45.997483 dram_init: ddr_type: 0
546 09:30:46.000369 is_discrete_lpddr4: 1
547 09:30:46.003927 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 09:30:46.004018
549 09:30:46.004095
550 09:30:46.006884 [Bian_co] ETT version 0.0.0.1
551 09:30:46.010205 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 09:30:46.010295
553 09:30:46.013739 dramc_set_vcore_voltage set vcore to 650000
554 09:30:46.017271 Read voltage for 800, 4
555 09:30:46.017345 Vio18 = 0
556 09:30:46.020381 Vcore = 650000
557 09:30:46.020452 Vdram = 0
558 09:30:46.020519 Vddq = 0
559 09:30:46.023777 Vmddr = 0
560 09:30:46.023856 dram_init: config_dvfs: 1
561 09:30:46.030426 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 09:30:46.033770 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 09:30:46.040720 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
564 09:30:46.043715 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
565 09:30:46.047449 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 09:30:46.050677 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 09:30:46.053679 MEM_TYPE=3, freq_sel=18
568 09:30:46.057341 sv_algorithm_assistance_LP4_1600
569 09:30:46.060517 ============ PULL DRAM RESETB DOWN ============
570 09:30:46.064071 ========== PULL DRAM RESETB DOWN end =========
571 09:30:46.067276 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 09:30:46.070592 ===================================
573 09:30:46.073921 LPDDR4 DRAM CONFIGURATION
574 09:30:46.077409 ===================================
575 09:30:46.080349 EX_ROW_EN[0] = 0x0
576 09:30:46.080452 EX_ROW_EN[1] = 0x0
577 09:30:46.083808 LP4Y_EN = 0x0
578 09:30:46.083911 WORK_FSP = 0x0
579 09:30:46.087319 WL = 0x2
580 09:30:46.087421 RL = 0x2
581 09:30:46.090848 BL = 0x2
582 09:30:46.090948 RPST = 0x0
583 09:30:46.094116 RD_PRE = 0x0
584 09:30:46.094220 WR_PRE = 0x1
585 09:30:46.097139 WR_PST = 0x0
586 09:30:46.097235 DBI_WR = 0x0
587 09:30:46.100330 DBI_RD = 0x0
588 09:30:46.103657 OTF = 0x1
589 09:30:46.107308 ===================================
590 09:30:46.110321 ===================================
591 09:30:46.110426 ANA top config
592 09:30:46.113746 ===================================
593 09:30:46.117172 DLL_ASYNC_EN = 0
594 09:30:46.117281 ALL_SLAVE_EN = 1
595 09:30:46.120668 NEW_RANK_MODE = 1
596 09:30:46.123689 DLL_IDLE_MODE = 1
597 09:30:46.127238 LP45_APHY_COMB_EN = 1
598 09:30:46.130314 TX_ODT_DIS = 1
599 09:30:46.130421 NEW_8X_MODE = 1
600 09:30:46.133775 ===================================
601 09:30:46.137157 ===================================
602 09:30:46.140577 data_rate = 1600
603 09:30:46.144039 CKR = 1
604 09:30:46.147412 DQ_P2S_RATIO = 8
605 09:30:46.150348 ===================================
606 09:30:46.153793 CA_P2S_RATIO = 8
607 09:30:46.153896 DQ_CA_OPEN = 0
608 09:30:46.157097 DQ_SEMI_OPEN = 0
609 09:30:46.160643 CA_SEMI_OPEN = 0
610 09:30:46.164013 CA_FULL_RATE = 0
611 09:30:46.167504 DQ_CKDIV4_EN = 1
612 09:30:46.170710 CA_CKDIV4_EN = 1
613 09:30:46.170813 CA_PREDIV_EN = 0
614 09:30:46.173705 PH8_DLY = 0
615 09:30:46.177381 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 09:30:46.180449 DQ_AAMCK_DIV = 4
617 09:30:46.183891 CA_AAMCK_DIV = 4
618 09:30:46.187472 CA_ADMCK_DIV = 4
619 09:30:46.187603 DQ_TRACK_CA_EN = 0
620 09:30:46.190934 CA_PICK = 800
621 09:30:46.193937 CA_MCKIO = 800
622 09:30:46.197235 MCKIO_SEMI = 0
623 09:30:46.200604 PLL_FREQ = 3068
624 09:30:46.203974 DQ_UI_PI_RATIO = 32
625 09:30:46.207314 CA_UI_PI_RATIO = 0
626 09:30:46.210331 ===================================
627 09:30:46.214017 ===================================
628 09:30:46.214118 memory_type:LPDDR4
629 09:30:46.217264 GP_NUM : 10
630 09:30:46.220643 SRAM_EN : 1
631 09:30:46.220749 MD32_EN : 0
632 09:30:46.223858 ===================================
633 09:30:46.227865 [ANA_INIT] >>>>>>>>>>>>>>
634 09:30:46.231344 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 09:30:46.234914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 09:30:46.235020 ===================================
637 09:30:46.238918 data_rate = 1600,PCW = 0X7600
638 09:30:46.242337 ===================================
639 09:30:46.246137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 09:30:46.249882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 09:30:46.257038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 09:30:46.260911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 09:30:46.264177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 09:30:46.267488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 09:30:46.270992 [ANA_INIT] flow start
646 09:30:46.271077 [ANA_INIT] PLL >>>>>>>>
647 09:30:46.274699 [ANA_INIT] PLL <<<<<<<<
648 09:30:46.277832 [ANA_INIT] MIDPI >>>>>>>>
649 09:30:46.280900 [ANA_INIT] MIDPI <<<<<<<<
650 09:30:46.281012 [ANA_INIT] DLL >>>>>>>>
651 09:30:46.284656 [ANA_INIT] flow end
652 09:30:46.288211 ============ LP4 DIFF to SE enter ============
653 09:30:46.292109 ============ LP4 DIFF to SE exit ============
654 09:30:46.295611 [ANA_INIT] <<<<<<<<<<<<<
655 09:30:46.299282 [Flow] Enable top DCM control >>>>>
656 09:30:46.299389 [Flow] Enable top DCM control <<<<<
657 09:30:46.303242 Enable DLL master slave shuffle
658 09:30:46.310739 ==============================================================
659 09:30:46.310852 Gating Mode config
660 09:30:46.317763 ==============================================================
661 09:30:46.317852 Config description:
662 09:30:46.328717 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 09:30:46.336732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 09:30:46.340273 SELPH_MODE 0: By rank 1: By Phase
665 09:30:46.344151 ==============================================================
666 09:30:46.347827 GAT_TRACK_EN = 1
667 09:30:46.351428 RX_GATING_MODE = 2
668 09:30:46.354878 RX_GATING_TRACK_MODE = 2
669 09:30:46.359005 SELPH_MODE = 1
670 09:30:46.359090 PICG_EARLY_EN = 1
671 09:30:46.362470 VALID_LAT_VALUE = 1
672 09:30:46.369844 ==============================================================
673 09:30:46.373611 Enter into Gating configuration >>>>
674 09:30:46.376995 Exit from Gating configuration <<<<
675 09:30:46.377114 Enter into DVFS_PRE_config >>>>>
676 09:30:46.388487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 09:30:46.392286 Exit from DVFS_PRE_config <<<<<
678 09:30:46.395531 Enter into PICG configuration >>>>
679 09:30:46.399828 Exit from PICG configuration <<<<
680 09:30:46.403350 [RX_INPUT] configuration >>>>>
681 09:30:46.403446 [RX_INPUT] configuration <<<<<
682 09:30:46.410864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 09:30:46.414720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 09:30:46.422117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 09:30:46.426016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 09:30:46.433274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 09:30:46.440768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 09:30:46.444915 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 09:30:46.448146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 09:30:46.452287 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 09:30:46.455832 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 09:30:46.460019 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 09:30:46.463515 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 09:30:46.467054 ===================================
695 09:30:46.470941 LPDDR4 DRAM CONFIGURATION
696 09:30:46.474345 ===================================
697 09:30:46.474456 EX_ROW_EN[0] = 0x0
698 09:30:46.478364 EX_ROW_EN[1] = 0x0
699 09:30:46.478488 LP4Y_EN = 0x0
700 09:30:46.482358 WORK_FSP = 0x0
701 09:30:46.482443 WL = 0x2
702 09:30:46.485797 RL = 0x2
703 09:30:46.485881 BL = 0x2
704 09:30:46.489663 RPST = 0x0
705 09:30:46.489748 RD_PRE = 0x0
706 09:30:46.493298 WR_PRE = 0x1
707 09:30:46.493385 WR_PST = 0x0
708 09:30:46.493453 DBI_WR = 0x0
709 09:30:46.497045 DBI_RD = 0x0
710 09:30:46.497165 OTF = 0x1
711 09:30:46.500719 ===================================
712 09:30:46.504290 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 09:30:46.508376 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 09:30:46.515291 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 09:30:46.519266 ===================================
716 09:30:46.519351 LPDDR4 DRAM CONFIGURATION
717 09:30:46.523224 ===================================
718 09:30:46.526676 EX_ROW_EN[0] = 0x10
719 09:30:46.526760 EX_ROW_EN[1] = 0x0
720 09:30:46.530461 LP4Y_EN = 0x0
721 09:30:46.530545 WORK_FSP = 0x0
722 09:30:46.534283 WL = 0x2
723 09:30:46.534366 RL = 0x2
724 09:30:46.537744 BL = 0x2
725 09:30:46.537828 RPST = 0x0
726 09:30:46.537894 RD_PRE = 0x0
727 09:30:46.541724 WR_PRE = 0x1
728 09:30:46.541811 WR_PST = 0x0
729 09:30:46.545304 DBI_WR = 0x0
730 09:30:46.545387 DBI_RD = 0x0
731 09:30:46.549184 OTF = 0x1
732 09:30:46.552699 ===================================
733 09:30:46.556423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 09:30:46.561547 nWR fixed to 40
735 09:30:46.561631 [ModeRegInit_LP4] CH0 RK0
736 09:30:46.565578 [ModeRegInit_LP4] CH0 RK1
737 09:30:46.569111 [ModeRegInit_LP4] CH1 RK0
738 09:30:46.569195 [ModeRegInit_LP4] CH1 RK1
739 09:30:46.572960 match AC timing 13
740 09:30:46.576460 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 09:30:46.580771 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 09:30:46.584316 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 09:30:46.591565 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 09:30:46.594924 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 09:30:46.595008 [EMI DOE] emi_dcm 0
746 09:30:46.601343 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 09:30:46.601427 ==
748 09:30:46.605055 Dram Type= 6, Freq= 0, CH_0, rank 0
749 09:30:46.608288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 09:30:46.608372 ==
751 09:30:46.615257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 09:30:46.618261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 09:30:46.629035 [CA 0] Center 38 (7~69) winsize 63
754 09:30:46.632054 [CA 1] Center 38 (7~69) winsize 63
755 09:30:46.635431 [CA 2] Center 35 (5~66) winsize 62
756 09:30:46.639164 [CA 3] Center 35 (5~66) winsize 62
757 09:30:46.642203 [CA 4] Center 34 (4~65) winsize 62
758 09:30:46.645708 [CA 5] Center 33 (3~64) winsize 62
759 09:30:46.645791
760 09:30:46.648707 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 09:30:46.648791
762 09:30:46.652090 [CATrainingPosCal] consider 1 rank data
763 09:30:46.655692 u2DelayCellTimex100 = 270/100 ps
764 09:30:46.659033 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
765 09:30:46.662369 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
766 09:30:46.665861 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 09:30:46.672491 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 09:30:46.676065 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
769 09:30:46.679473 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 09:30:46.679556
771 09:30:46.682803 CA PerBit enable=1, Macro0, CA PI delay=33
772 09:30:46.682889
773 09:30:46.685798 [CBTSetCACLKResult] CA Dly = 33
774 09:30:46.685871 CS Dly: 5 (0~36)
775 09:30:46.685933 ==
776 09:30:46.689441 Dram Type= 6, Freq= 0, CH_0, rank 1
777 09:30:46.696181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 09:30:46.696266 ==
779 09:30:46.699250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 09:30:46.705948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 09:30:46.715622 [CA 0] Center 38 (7~69) winsize 63
782 09:30:46.718630 [CA 1] Center 38 (7~69) winsize 63
783 09:30:46.722206 [CA 2] Center 36 (6~67) winsize 62
784 09:30:46.725463 [CA 3] Center 35 (5~66) winsize 62
785 09:30:46.728450 [CA 4] Center 35 (4~66) winsize 63
786 09:30:46.732040 [CA 5] Center 34 (4~65) winsize 62
787 09:30:46.732123
788 09:30:46.735112 [CmdBusTrainingLP45] Vref(ca) range 1: 32
789 09:30:46.735195
790 09:30:46.738442 [CATrainingPosCal] consider 2 rank data
791 09:30:46.741581 u2DelayCellTimex100 = 270/100 ps
792 09:30:46.745200 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 09:30:46.751667 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
794 09:30:46.755194 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
795 09:30:46.758694 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 09:30:46.762054 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
797 09:30:46.764916 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
798 09:30:46.765032
799 09:30:46.768385 CA PerBit enable=1, Macro0, CA PI delay=34
800 09:30:46.768469
801 09:30:46.771609 [CBTSetCACLKResult] CA Dly = 34
802 09:30:46.771692 CS Dly: 6 (0~38)
803 09:30:46.771757
804 09:30:46.778577 ----->DramcWriteLeveling(PI) begin...
805 09:30:46.778662 ==
806 09:30:46.781603 Dram Type= 6, Freq= 0, CH_0, rank 0
807 09:30:46.784873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 09:30:46.785016 ==
809 09:30:46.788289 Write leveling (Byte 0): 32 => 32
810 09:30:46.791807 Write leveling (Byte 1): 31 => 31
811 09:30:46.795212 DramcWriteLeveling(PI) end<-----
812 09:30:46.795294
813 09:30:46.795359 ==
814 09:30:46.798001 Dram Type= 6, Freq= 0, CH_0, rank 0
815 09:30:46.801555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 09:30:46.801637 ==
817 09:30:46.805104 [Gating] SW mode calibration
818 09:30:46.812189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 09:30:46.815806 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 09:30:46.819800 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
821 09:30:46.826452 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 09:30:46.830017 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
823 09:30:46.833361 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:30:46.840429 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:30:46.843893 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:30:46.847277 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:30:46.850780 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 09:30:46.857114 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 09:30:46.860525 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 09:30:46.864025 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 09:30:46.870789 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 09:30:46.874256 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 09:30:46.877296 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 09:30:46.884299 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 09:30:46.887382 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 09:30:46.891209 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 09:30:46.894133 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
838 09:30:46.901129 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
839 09:30:46.904139 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
840 09:30:46.907529 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 09:30:46.914004 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 09:30:46.917412 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 09:30:46.920810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 09:30:46.927490 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 09:30:46.930791 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
846 09:30:46.934021 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 09:30:46.941046 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
848 09:30:46.944265 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 09:30:46.947498 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 09:30:46.954082 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 09:30:46.958034 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 09:30:46.960890 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 09:30:46.967895 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
854 09:30:46.970864 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
855 09:30:46.974182 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
856 09:30:46.977787 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:30:46.984247 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:30:46.987769 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:30:46.991216 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:30:46.998023 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:30:47.001217 0 11 4 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
862 09:30:47.004417 0 11 8 | B1->B0 | 2f2e 4646 | 1 0 | (0 0) (0 0)
863 09:30:47.010944 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
864 09:30:47.014426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 09:30:47.017941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 09:30:47.024601 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 09:30:47.027968 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 09:30:47.031200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 09:30:47.037804 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
870 09:30:47.041347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 09:30:47.044764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
872 09:30:47.051430 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 09:30:47.054514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 09:30:47.057820 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 09:30:47.061226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 09:30:47.067954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 09:30:47.071379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 09:30:47.074401 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 09:30:47.081208 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 09:30:47.084765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 09:30:47.088218 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 09:30:47.094792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 09:30:47.098085 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 09:30:47.101160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 09:30:47.108222 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
886 09:30:47.108308 Total UI for P1: 0, mck2ui 16
887 09:30:47.114685 best dqsien dly found for B0: ( 0, 14, 2)
888 09:30:47.118246 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 09:30:47.121248 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 09:30:47.124613 Total UI for P1: 0, mck2ui 16
891 09:30:47.127995 best dqsien dly found for B1: ( 0, 14, 6)
892 09:30:47.131728 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
893 09:30:47.134852 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
894 09:30:47.134938
895 09:30:47.138329 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
896 09:30:47.141300 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
897 09:30:47.144850 [Gating] SW calibration Done
898 09:30:47.144955 ==
899 09:30:47.147949 Dram Type= 6, Freq= 0, CH_0, rank 0
900 09:30:47.154960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 09:30:47.155046 ==
902 09:30:47.155128 RX Vref Scan: 0
903 09:30:47.155203
904 09:30:47.158364 RX Vref 0 -> 0, step: 1
905 09:30:47.158464
906 09:30:47.161267 RX Delay -130 -> 252, step: 16
907 09:30:47.164716 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
908 09:30:47.167916 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
909 09:30:47.171672 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
910 09:30:47.174594 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
911 09:30:47.181374 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
912 09:30:47.184808 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
913 09:30:47.188324 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
914 09:30:47.191843 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 09:30:47.194849 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
916 09:30:47.201507 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 09:30:47.204907 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
918 09:30:47.208394 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
919 09:30:47.211391 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
920 09:30:47.214874 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
921 09:30:47.221889 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
922 09:30:47.224799 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
923 09:30:47.224915 ==
924 09:30:47.228190 Dram Type= 6, Freq= 0, CH_0, rank 0
925 09:30:47.231673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 09:30:47.231762 ==
927 09:30:47.235130 DQS Delay:
928 09:30:47.235220 DQS0 = 0, DQS1 = 0
929 09:30:47.235307 DQM Delay:
930 09:30:47.238307 DQM0 = 92, DQM1 = 79
931 09:30:47.238394 DQ Delay:
932 09:30:47.241929 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
933 09:30:47.245333 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
934 09:30:47.248236 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
935 09:30:47.251809 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
936 09:30:47.251924
937 09:30:47.252009
938 09:30:47.252098 ==
939 09:30:47.254943 Dram Type= 6, Freq= 0, CH_0, rank 0
940 09:30:47.261522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 09:30:47.261607 ==
942 09:30:47.261673
943 09:30:47.261733
944 09:30:47.261791 TX Vref Scan disable
945 09:30:47.265251 == TX Byte 0 ==
946 09:30:47.268483 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
947 09:30:47.271735 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
948 09:30:47.275326 == TX Byte 1 ==
949 09:30:47.278350 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
950 09:30:47.281797 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
951 09:30:47.285018 ==
952 09:30:47.288664 Dram Type= 6, Freq= 0, CH_0, rank 0
953 09:30:47.291597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 09:30:47.291681 ==
955 09:30:47.304461 TX Vref=22, minBit 13, minWin=26, winSum=442
956 09:30:47.307770 TX Vref=24, minBit 6, minWin=27, winSum=441
957 09:30:47.310859 TX Vref=26, minBit 8, minWin=27, winSum=447
958 09:30:47.314412 TX Vref=28, minBit 10, minWin=27, winSum=452
959 09:30:47.317768 TX Vref=30, minBit 9, minWin=27, winSum=451
960 09:30:47.324251 TX Vref=32, minBit 12, minWin=27, winSum=451
961 09:30:47.327845 [TxChooseVref] Worse bit 10, Min win 27, Win sum 452, Final Vref 28
962 09:30:47.327943
963 09:30:47.331200 Final TX Range 1 Vref 28
964 09:30:47.331284
965 09:30:47.331349 ==
966 09:30:47.334172 Dram Type= 6, Freq= 0, CH_0, rank 0
967 09:30:47.337572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 09:30:47.337669 ==
969 09:30:47.340770
970 09:30:47.340852
971 09:30:47.340917 TX Vref Scan disable
972 09:30:47.344459 == TX Byte 0 ==
973 09:30:47.347581 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 09:30:47.350907 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 09:30:47.354413 == TX Byte 1 ==
976 09:30:47.357921 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 09:30:47.361298 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 09:30:47.364323
979 09:30:47.364437 [DATLAT]
980 09:30:47.364523 Freq=800, CH0 RK0
981 09:30:47.364598
982 09:30:47.367520 DATLAT Default: 0xa
983 09:30:47.367588 0, 0xFFFF, sum = 0
984 09:30:47.371265 1, 0xFFFF, sum = 0
985 09:30:47.371342 2, 0xFFFF, sum = 0
986 09:30:47.374379 3, 0xFFFF, sum = 0
987 09:30:47.374484 4, 0xFFFF, sum = 0
988 09:30:47.377985 5, 0xFFFF, sum = 0
989 09:30:47.378062 6, 0xFFFF, sum = 0
990 09:30:47.381179 7, 0xFFFF, sum = 0
991 09:30:47.381264 8, 0xFFFF, sum = 0
992 09:30:47.384808 9, 0x0, sum = 1
993 09:30:47.384895 10, 0x0, sum = 2
994 09:30:47.388174 11, 0x0, sum = 3
995 09:30:47.388262 12, 0x0, sum = 4
996 09:30:47.391103 best_step = 10
997 09:30:47.391187
998 09:30:47.391252 ==
999 09:30:47.394499 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 09:30:47.398078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 09:30:47.398156 ==
1002 09:30:47.401142 RX Vref Scan: 1
1003 09:30:47.401215
1004 09:30:47.401283 Set Vref Range= 32 -> 127
1005 09:30:47.401344
1006 09:30:47.404722 RX Vref 32 -> 127, step: 1
1007 09:30:47.404803
1008 09:30:47.408100 RX Delay -95 -> 252, step: 8
1009 09:30:47.408172
1010 09:30:47.411517 Set Vref, RX VrefLevel [Byte0]: 32
1011 09:30:47.414879 [Byte1]: 32
1012 09:30:47.414957
1013 09:30:47.417956 Set Vref, RX VrefLevel [Byte0]: 33
1014 09:30:47.421433 [Byte1]: 33
1015 09:30:47.424715
1016 09:30:47.424818 Set Vref, RX VrefLevel [Byte0]: 34
1017 09:30:47.428464 [Byte1]: 34
1018 09:30:47.432412
1019 09:30:47.432496 Set Vref, RX VrefLevel [Byte0]: 35
1020 09:30:47.435771 [Byte1]: 35
1021 09:30:47.439791
1022 09:30:47.439862 Set Vref, RX VrefLevel [Byte0]: 36
1023 09:30:47.443091 [Byte1]: 36
1024 09:30:47.447491
1025 09:30:47.447639 Set Vref, RX VrefLevel [Byte0]: 37
1026 09:30:47.450615 [Byte1]: 37
1027 09:30:47.455790
1028 09:30:47.455893 Set Vref, RX VrefLevel [Byte0]: 38
1029 09:30:47.458811 [Byte1]: 38
1030 09:30:47.462447
1031 09:30:47.462520 Set Vref, RX VrefLevel [Byte0]: 39
1032 09:30:47.466057 [Byte1]: 39
1033 09:30:47.470277
1034 09:30:47.470375 Set Vref, RX VrefLevel [Byte0]: 40
1035 09:30:47.473340 [Byte1]: 40
1036 09:30:47.478077
1037 09:30:47.478158 Set Vref, RX VrefLevel [Byte0]: 41
1038 09:30:47.481514 [Byte1]: 41
1039 09:30:47.485497
1040 09:30:47.485582 Set Vref, RX VrefLevel [Byte0]: 42
1041 09:30:47.489292 [Byte1]: 42
1042 09:30:47.493053
1043 09:30:47.493140 Set Vref, RX VrefLevel [Byte0]: 43
1044 09:30:47.496677 [Byte1]: 43
1045 09:30:47.500764
1046 09:30:47.500850 Set Vref, RX VrefLevel [Byte0]: 44
1047 09:30:47.504296 [Byte1]: 44
1048 09:30:47.508737
1049 09:30:47.508821 Set Vref, RX VrefLevel [Byte0]: 45
1050 09:30:47.511856 [Byte1]: 45
1051 09:30:47.515652
1052 09:30:47.515737 Set Vref, RX VrefLevel [Byte0]: 46
1053 09:30:47.519148 [Byte1]: 46
1054 09:30:47.523330
1055 09:30:47.523407 Set Vref, RX VrefLevel [Byte0]: 47
1056 09:30:47.526653 [Byte1]: 47
1057 09:30:47.530811
1058 09:30:47.530881 Set Vref, RX VrefLevel [Byte0]: 48
1059 09:30:47.534426 [Byte1]: 48
1060 09:30:47.538903
1061 09:30:47.538976 Set Vref, RX VrefLevel [Byte0]: 49
1062 09:30:47.541804 [Byte1]: 49
1063 09:30:47.546294
1064 09:30:47.546375 Set Vref, RX VrefLevel [Byte0]: 50
1065 09:30:47.549408 [Byte1]: 50
1066 09:30:47.553718
1067 09:30:47.553808 Set Vref, RX VrefLevel [Byte0]: 51
1068 09:30:47.557229 [Byte1]: 51
1069 09:30:47.561283
1070 09:30:47.561353 Set Vref, RX VrefLevel [Byte0]: 52
1071 09:30:47.564636 [Byte1]: 52
1072 09:30:47.569045
1073 09:30:47.569115 Set Vref, RX VrefLevel [Byte0]: 53
1074 09:30:47.572279 [Byte1]: 53
1075 09:30:47.576657
1076 09:30:47.576738 Set Vref, RX VrefLevel [Byte0]: 54
1077 09:30:47.579882 [Byte1]: 54
1078 09:30:47.584078
1079 09:30:47.584152 Set Vref, RX VrefLevel [Byte0]: 55
1080 09:30:47.587511 [Byte1]: 55
1081 09:30:47.591689
1082 09:30:47.591763 Set Vref, RX VrefLevel [Byte0]: 56
1083 09:30:47.595062 [Byte1]: 56
1084 09:30:47.599427
1085 09:30:47.599502 Set Vref, RX VrefLevel [Byte0]: 57
1086 09:30:47.602723 [Byte1]: 57
1087 09:30:47.607375
1088 09:30:47.607458 Set Vref, RX VrefLevel [Byte0]: 58
1089 09:30:47.610372 [Byte1]: 58
1090 09:30:47.614419
1091 09:30:47.614501 Set Vref, RX VrefLevel [Byte0]: 59
1092 09:30:47.617818 [Byte1]: 59
1093 09:30:47.622271
1094 09:30:47.622352 Set Vref, RX VrefLevel [Byte0]: 60
1095 09:30:47.625633 [Byte1]: 60
1096 09:30:47.629999
1097 09:30:47.630080 Set Vref, RX VrefLevel [Byte0]: 61
1098 09:30:47.633017 [Byte1]: 61
1099 09:30:47.637626
1100 09:30:47.637707 Set Vref, RX VrefLevel [Byte0]: 62
1101 09:30:47.640656 [Byte1]: 62
1102 09:30:47.644871
1103 09:30:47.645005 Set Vref, RX VrefLevel [Byte0]: 63
1104 09:30:47.648321 [Byte1]: 63
1105 09:30:47.652668
1106 09:30:47.652779 Set Vref, RX VrefLevel [Byte0]: 64
1107 09:30:47.655942 [Byte1]: 64
1108 09:30:47.660127
1109 09:30:47.660225 Set Vref, RX VrefLevel [Byte0]: 65
1110 09:30:47.663531 [Byte1]: 65
1111 09:30:47.667621
1112 09:30:47.667718 Set Vref, RX VrefLevel [Byte0]: 66
1113 09:30:47.671132 [Byte1]: 66
1114 09:30:47.675309
1115 09:30:47.675463 Set Vref, RX VrefLevel [Byte0]: 67
1116 09:30:47.678914 [Byte1]: 67
1117 09:30:47.683201
1118 09:30:47.683298 Set Vref, RX VrefLevel [Byte0]: 68
1119 09:30:47.686327 [Byte1]: 68
1120 09:30:47.690402
1121 09:30:47.690513 Set Vref, RX VrefLevel [Byte0]: 69
1122 09:30:47.694120 [Byte1]: 69
1123 09:30:47.698326
1124 09:30:47.698403 Set Vref, RX VrefLevel [Byte0]: 70
1125 09:30:47.701588 [Byte1]: 70
1126 09:30:47.705860
1127 09:30:47.705944 Set Vref, RX VrefLevel [Byte0]: 71
1128 09:30:47.708876 [Byte1]: 71
1129 09:30:47.713370
1130 09:30:47.713453 Set Vref, RX VrefLevel [Byte0]: 72
1131 09:30:47.716726 [Byte1]: 72
1132 09:30:47.721100
1133 09:30:47.721190 Set Vref, RX VrefLevel [Byte0]: 73
1134 09:30:47.724472 [Byte1]: 73
1135 09:30:47.728795
1136 09:30:47.728896 Set Vref, RX VrefLevel [Byte0]: 74
1137 09:30:47.731835 [Byte1]: 74
1138 09:30:47.736325
1139 09:30:47.736427 Set Vref, RX VrefLevel [Byte0]: 75
1140 09:30:47.739309 [Byte1]: 75
1141 09:30:47.743781
1142 09:30:47.743874 Set Vref, RX VrefLevel [Byte0]: 76
1143 09:30:47.747290 [Byte1]: 76
1144 09:30:47.751458
1145 09:30:47.751563 Set Vref, RX VrefLevel [Byte0]: 77
1146 09:30:47.754949 [Byte1]: 77
1147 09:30:47.758743
1148 09:30:47.758856 Final RX Vref Byte 0 = 60 to rank0
1149 09:30:47.762223 Final RX Vref Byte 1 = 56 to rank0
1150 09:30:47.765848 Final RX Vref Byte 0 = 60 to rank1
1151 09:30:47.768799 Final RX Vref Byte 1 = 56 to rank1==
1152 09:30:47.772259 Dram Type= 6, Freq= 0, CH_0, rank 0
1153 09:30:47.775674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 09:30:47.779049 ==
1155 09:30:47.779162 DQS Delay:
1156 09:30:47.779258 DQS0 = 0, DQS1 = 0
1157 09:30:47.782501 DQM Delay:
1158 09:30:47.782599 DQM0 = 93, DQM1 = 81
1159 09:30:47.785760 DQ Delay:
1160 09:30:47.789234 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1161 09:30:47.789328 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1162 09:30:47.792670 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1163 09:30:47.795915 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1164 09:30:47.795987
1165 09:30:47.799110
1166 09:30:47.805870 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1167 09:30:47.809387 CH0 RK0: MR19=606, MR18=3C37
1168 09:30:47.816056 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1169 09:30:47.816154
1170 09:30:47.819604 ----->DramcWriteLeveling(PI) begin...
1171 09:30:47.819689 ==
1172 09:30:47.822540 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 09:30:47.825954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 09:30:47.826030 ==
1175 09:30:47.829267 Write leveling (Byte 0): 32 => 32
1176 09:30:47.832785 Write leveling (Byte 1): 30 => 30
1177 09:30:47.835682 DramcWriteLeveling(PI) end<-----
1178 09:30:47.835793
1179 09:30:47.835890 ==
1180 09:30:47.839096 Dram Type= 6, Freq= 0, CH_0, rank 1
1181 09:30:47.842600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1182 09:30:47.842707 ==
1183 09:30:47.846113 [Gating] SW mode calibration
1184 09:30:47.852429 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1185 09:30:47.859366 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1186 09:30:47.862557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1187 09:30:47.865998 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1188 09:30:47.872544 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1189 09:30:47.876088 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:30:47.879219 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:30:47.923675 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:30:47.923839 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:30:47.924140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:30:47.924220 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:30:47.924345 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:30:47.924426 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 09:30:47.924565 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:30:47.924660 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:30:47.924734 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:30:47.924800 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 09:30:47.935959 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 09:30:47.936528 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1203 09:30:47.939659 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1204 09:30:47.943034 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 09:30:47.946093 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 09:30:47.949550 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 09:30:47.956183 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 09:30:47.959424 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 09:30:47.963046 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 09:30:47.969648 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 09:30:47.973050 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1212 09:30:47.976277 0 9 8 | B1->B0 | 2d2d 3333 | 1 0 | (0 0) (0 0)
1213 09:30:47.980010 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 09:30:47.986179 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 09:30:47.989534 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 09:30:47.992823 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 09:30:47.999976 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 09:30:48.003300 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 09:30:48.006371 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
1220 09:30:48.013258 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1221 09:30:48.016487 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:30:48.019587 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:30:48.026214 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:30:48.029710 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:30:48.032841 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:30:48.039722 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:30:48.042901 0 11 4 | B1->B0 | 2525 2f2f | 1 1 | (0 0) (0 0)
1228 09:30:48.046497 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1229 09:30:48.052772 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 09:30:48.056467 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 09:30:48.060529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 09:30:48.064200 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 09:30:48.067668 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 09:30:48.074910 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 09:30:48.078518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 09:30:48.081596 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 09:30:48.089046 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 09:30:48.092356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 09:30:48.095907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 09:30:48.098920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 09:30:48.102398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 09:30:48.109288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 09:30:48.112467 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 09:30:48.115725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 09:30:48.122626 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 09:30:48.126171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 09:30:48.129555 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 09:30:48.136232 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 09:30:48.139596 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 09:30:48.142926 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 09:30:48.149510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1252 09:30:48.149609 Total UI for P1: 0, mck2ui 16
1253 09:30:48.155919 best dqsien dly found for B1: ( 0, 14, 2)
1254 09:30:48.159394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1255 09:30:48.162871 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 09:30:48.166243 Total UI for P1: 0, mck2ui 16
1257 09:30:48.169714 best dqsien dly found for B0: ( 0, 14, 6)
1258 09:30:48.172710 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1259 09:30:48.175987 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1260 09:30:48.176128
1261 09:30:48.179522 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1262 09:30:48.186070 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1263 09:30:48.186184 [Gating] SW calibration Done
1264 09:30:48.186252 ==
1265 09:30:48.189532 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 09:30:48.196150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 09:30:48.196242 ==
1268 09:30:48.196307 RX Vref Scan: 0
1269 09:30:48.196368
1270 09:30:48.199488 RX Vref 0 -> 0, step: 1
1271 09:30:48.199578
1272 09:30:48.202908 RX Delay -130 -> 252, step: 16
1273 09:30:48.206438 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1274 09:30:48.209521 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1275 09:30:48.212767 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1276 09:30:48.219614 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1277 09:30:48.222949 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1278 09:30:48.226269 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1279 09:30:48.229587 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1280 09:30:48.232799 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1281 09:30:48.236226 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1282 09:30:48.242676 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1283 09:30:48.246416 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1284 09:30:48.249318 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1285 09:30:48.252869 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1286 09:30:48.256207 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1287 09:30:48.262825 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1288 09:30:48.266442 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1289 09:30:48.266537 ==
1290 09:30:48.269843 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 09:30:48.273196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 09:30:48.273287 ==
1293 09:30:48.276547 DQS Delay:
1294 09:30:48.276641 DQS0 = 0, DQS1 = 0
1295 09:30:48.276714 DQM Delay:
1296 09:30:48.279907 DQM0 = 88, DQM1 = 79
1297 09:30:48.280008 DQ Delay:
1298 09:30:48.282962 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1299 09:30:48.286487 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1300 09:30:48.289984 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1301 09:30:48.293076 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =93
1302 09:30:48.293176
1303 09:30:48.293268
1304 09:30:48.293360 ==
1305 09:30:48.296605 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 09:30:48.303160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 09:30:48.303295 ==
1308 09:30:48.303397
1309 09:30:48.303490
1310 09:30:48.303584 TX Vref Scan disable
1311 09:30:48.306652 == TX Byte 0 ==
1312 09:30:48.309711 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1313 09:30:48.313125 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1314 09:30:48.316598 == TX Byte 1 ==
1315 09:30:48.319644 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1316 09:30:48.323283 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1317 09:30:48.326707 ==
1318 09:30:48.329999 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 09:30:48.333195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 09:30:48.333289 ==
1321 09:30:48.345693 TX Vref=22, minBit 8, minWin=27, winSum=448
1322 09:30:48.349029 TX Vref=24, minBit 8, minWin=27, winSum=445
1323 09:30:48.352697 TX Vref=26, minBit 8, minWin=27, winSum=453
1324 09:30:48.355752 TX Vref=28, minBit 8, minWin=27, winSum=451
1325 09:30:48.359226 TX Vref=30, minBit 8, minWin=28, winSum=457
1326 09:30:48.362681 TX Vref=32, minBit 8, minWin=27, winSum=458
1327 09:30:48.369056 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30
1328 09:30:48.369159
1329 09:30:48.372630 Final TX Range 1 Vref 30
1330 09:30:48.372721
1331 09:30:48.372786 ==
1332 09:30:48.376005 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 09:30:48.379571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 09:30:48.379681 ==
1335 09:30:48.379748
1336 09:30:48.379824
1337 09:30:48.382816 TX Vref Scan disable
1338 09:30:48.385857 == TX Byte 0 ==
1339 09:30:48.389352 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1340 09:30:48.392890 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1341 09:30:48.395871 == TX Byte 1 ==
1342 09:30:48.399218 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1343 09:30:48.402686 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1344 09:30:48.402778
1345 09:30:48.406137 [DATLAT]
1346 09:30:48.406223 Freq=800, CH0 RK1
1347 09:30:48.406287
1348 09:30:48.409276 DATLAT Default: 0xa
1349 09:30:48.409361 0, 0xFFFF, sum = 0
1350 09:30:48.412787 1, 0xFFFF, sum = 0
1351 09:30:48.412872 2, 0xFFFF, sum = 0
1352 09:30:48.416196 3, 0xFFFF, sum = 0
1353 09:30:48.416289 4, 0xFFFF, sum = 0
1354 09:30:48.419373 5, 0xFFFF, sum = 0
1355 09:30:48.419459 6, 0xFFFF, sum = 0
1356 09:30:48.422897 7, 0xFFFF, sum = 0
1357 09:30:48.422982 8, 0xFFFF, sum = 0
1358 09:30:48.426266 9, 0x0, sum = 1
1359 09:30:48.426352 10, 0x0, sum = 2
1360 09:30:48.429454 11, 0x0, sum = 3
1361 09:30:48.429538 12, 0x0, sum = 4
1362 09:30:48.432983 best_step = 10
1363 09:30:48.433068
1364 09:30:48.433132 ==
1365 09:30:48.436142 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 09:30:48.439509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 09:30:48.439595 ==
1368 09:30:48.442612 RX Vref Scan: 0
1369 09:30:48.442695
1370 09:30:48.442759 RX Vref 0 -> 0, step: 1
1371 09:30:48.442819
1372 09:30:48.446332 RX Delay -95 -> 252, step: 8
1373 09:30:48.453104 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1374 09:30:48.456481 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1375 09:30:48.459529 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1376 09:30:48.463037 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1377 09:30:48.466006 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1378 09:30:48.469467 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1379 09:30:48.476550 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1380 09:30:48.479764 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1381 09:30:48.482769 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1382 09:30:48.486295 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1383 09:30:48.489581 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1384 09:30:48.496145 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1385 09:30:48.499616 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1386 09:30:48.502869 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1387 09:30:48.506404 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1388 09:30:48.509761 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1389 09:30:48.512882 ==
1390 09:30:48.516380 Dram Type= 6, Freq= 0, CH_0, rank 1
1391 09:30:48.519872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 09:30:48.519959 ==
1393 09:30:48.520023 DQS Delay:
1394 09:30:48.522851 DQS0 = 0, DQS1 = 0
1395 09:30:48.522932 DQM Delay:
1396 09:30:48.526568 DQM0 = 91, DQM1 = 81
1397 09:30:48.526678 DQ Delay:
1398 09:30:48.529950 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1399 09:30:48.532874 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1400 09:30:48.536483 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1401 09:30:48.539802 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1402 09:30:48.539890
1403 09:30:48.539955
1404 09:30:48.546571 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1405 09:30:48.549753 CH0 RK1: MR19=606, MR18=4721
1406 09:30:48.556144 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1407 09:30:48.559839 [RxdqsGatingPostProcess] freq 800
1408 09:30:48.566566 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1409 09:30:48.566674 Pre-setting of DQS Precalculation
1410 09:30:48.572880 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1411 09:30:48.573015 ==
1412 09:30:48.576335 Dram Type= 6, Freq= 0, CH_1, rank 0
1413 09:30:48.579831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 09:30:48.579929 ==
1415 09:30:48.586230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 09:30:48.593206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 09:30:48.601071 [CA 0] Center 36 (6~67) winsize 62
1418 09:30:48.604188 [CA 1] Center 36 (6~67) winsize 62
1419 09:30:48.607641 [CA 2] Center 35 (5~65) winsize 61
1420 09:30:48.610757 [CA 3] Center 34 (3~65) winsize 63
1421 09:30:48.614487 [CA 4] Center 34 (3~65) winsize 63
1422 09:30:48.617688 [CA 5] Center 34 (3~65) winsize 63
1423 09:30:48.617779
1424 09:30:48.620769 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1425 09:30:48.620859
1426 09:30:48.624267 [CATrainingPosCal] consider 1 rank data
1427 09:30:48.627356 u2DelayCellTimex100 = 270/100 ps
1428 09:30:48.630955 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 09:30:48.634457 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 09:30:48.640869 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 09:30:48.644194 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1432 09:30:48.647473 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
1433 09:30:48.651260 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1434 09:30:48.651357
1435 09:30:48.654236 CA PerBit enable=1, Macro0, CA PI delay=34
1436 09:30:48.654326
1437 09:30:48.657438 [CBTSetCACLKResult] CA Dly = 34
1438 09:30:48.657526 CS Dly: 5 (0~36)
1439 09:30:48.657612 ==
1440 09:30:48.661143 Dram Type= 6, Freq= 0, CH_1, rank 1
1441 09:30:48.667691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 09:30:48.667794 ==
1443 09:30:48.671066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 09:30:48.677544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 09:30:48.686937 [CA 0] Center 36 (6~67) winsize 62
1446 09:30:48.690209 [CA 1] Center 37 (6~68) winsize 63
1447 09:30:48.694269 [CA 2] Center 35 (4~66) winsize 63
1448 09:30:48.696913 [CA 3] Center 34 (4~65) winsize 62
1449 09:30:48.700481 [CA 4] Center 34 (4~65) winsize 62
1450 09:30:48.703994 [CA 5] Center 34 (4~65) winsize 62
1451 09:30:48.704084
1452 09:30:48.706960 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1453 09:30:48.707047
1454 09:30:48.710494 [CATrainingPosCal] consider 2 rank data
1455 09:30:48.713777 u2DelayCellTimex100 = 270/100 ps
1456 09:30:48.717172 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 09:30:48.720502 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 09:30:48.724010 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1459 09:30:48.727414 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 09:30:48.734882 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 09:30:48.734992 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 09:30:48.738401
1463 09:30:48.742027 CA PerBit enable=1, Macro0, CA PI delay=34
1464 09:30:48.742119
1465 09:30:48.742205 [CBTSetCACLKResult] CA Dly = 34
1466 09:30:48.745610 CS Dly: 6 (0~38)
1467 09:30:48.745698
1468 09:30:48.749788 ----->DramcWriteLeveling(PI) begin...
1469 09:30:48.749880 ==
1470 09:30:48.753543 Dram Type= 6, Freq= 0, CH_1, rank 0
1471 09:30:48.756862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 09:30:48.757004 ==
1473 09:30:48.760909 Write leveling (Byte 0): 29 => 29
1474 09:30:48.764005 Write leveling (Byte 1): 30 => 30
1475 09:30:48.764172 DramcWriteLeveling(PI) end<-----
1476 09:30:48.764260
1477 09:30:48.767399 ==
1478 09:30:48.770524 Dram Type= 6, Freq= 0, CH_1, rank 0
1479 09:30:48.774118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1480 09:30:48.774212 ==
1481 09:30:48.777418 [Gating] SW mode calibration
1482 09:30:48.784069 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1483 09:30:48.787526 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1484 09:30:48.793949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1485 09:30:48.797403 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:30:48.800703 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:30:48.807387 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:30:48.810848 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:30:48.813891 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:30:48.820907 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:30:48.824059 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:30:48.827703 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:30:48.834204 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:30:48.837287 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:30:48.840767 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:30:48.844282 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:30:48.850719 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:30:48.854197 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:30:48.857489 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:30:48.864019 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1501 09:30:48.867430 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1502 09:30:48.870697 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 09:30:48.877242 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 09:30:48.881002 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 09:30:48.884135 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 09:30:48.890844 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 09:30:48.894344 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 09:30:48.897657 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 09:30:48.904138 0 9 4 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
1510 09:30:48.907478 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1511 09:30:48.910963 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 09:30:48.914531 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 09:30:48.920920 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 09:30:48.924523 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 09:30:48.927495 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 09:30:48.934576 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1517 09:30:48.937565 0 10 4 | B1->B0 | 2b2b 2929 | 0 0 | (0 1) (1 1)
1518 09:30:48.941048 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1519 09:30:48.947652 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:30:48.951168 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:30:48.954108 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:30:48.961034 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:30:48.964027 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:30:48.967423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:30:48.974187 0 11 4 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (0 0)
1526 09:30:48.977341 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1527 09:30:48.980618 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 09:30:48.987672 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 09:30:48.991282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 09:30:48.994164 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 09:30:49.000709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 09:30:49.004171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1533 09:30:49.007459 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1534 09:30:49.013867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 09:30:49.017247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 09:30:49.020836 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 09:30:49.027507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 09:30:49.030778 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 09:30:49.034179 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 09:30:49.037503 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 09:30:49.044047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 09:30:49.047496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 09:30:49.051089 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 09:30:49.057394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 09:30:49.061040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 09:30:49.064059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 09:30:49.070905 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 09:30:49.074101 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1549 09:30:49.077266 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1550 09:30:49.084054 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 09:30:49.084171 Total UI for P1: 0, mck2ui 16
1552 09:30:49.090944 best dqsien dly found for B0: ( 0, 14, 2)
1553 09:30:49.091051 Total UI for P1: 0, mck2ui 16
1554 09:30:49.094021 best dqsien dly found for B1: ( 0, 14, 4)
1555 09:30:49.100821 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1556 09:30:49.104283 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1557 09:30:49.104378
1558 09:30:49.107902 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1559 09:30:49.110829 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1560 09:30:49.114503 [Gating] SW calibration Done
1561 09:30:49.114601 ==
1562 09:30:49.117498 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 09:30:49.120920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 09:30:49.121060 ==
1565 09:30:49.121144 RX Vref Scan: 0
1566 09:30:49.121221
1567 09:30:49.124389 RX Vref 0 -> 0, step: 1
1568 09:30:49.124473
1569 09:30:49.127435 RX Delay -130 -> 252, step: 16
1570 09:30:49.130935 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1571 09:30:49.134391 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1572 09:30:49.140777 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1573 09:30:49.144253 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1574 09:30:49.147907 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1575 09:30:49.150864 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1576 09:30:49.154511 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1577 09:30:49.160904 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1578 09:30:49.164440 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1579 09:30:49.167512 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1580 09:30:49.171048 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1581 09:30:49.174409 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1582 09:30:49.181029 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1583 09:30:49.184146 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1584 09:30:49.187663 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1585 09:30:49.191231 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1586 09:30:49.191328 ==
1587 09:30:49.194433 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 09:30:49.201291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 09:30:49.201396 ==
1590 09:30:49.201483 DQS Delay:
1591 09:30:49.201563 DQS0 = 0, DQS1 = 0
1592 09:30:49.204643 DQM Delay:
1593 09:30:49.204731 DQM0 = 89, DQM1 = 80
1594 09:30:49.207772 DQ Delay:
1595 09:30:49.211571 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1596 09:30:49.214396 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1597 09:30:49.214489 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1598 09:30:49.221310 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1599 09:30:49.221409
1600 09:30:49.221496
1601 09:30:49.221575 ==
1602 09:30:49.224739 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 09:30:49.228234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 09:30:49.228323 ==
1605 09:30:49.228409
1606 09:30:49.228489
1607 09:30:49.231148 TX Vref Scan disable
1608 09:30:49.231236 == TX Byte 0 ==
1609 09:30:49.238171 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 09:30:49.241431 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 09:30:49.241527 == TX Byte 1 ==
1612 09:30:49.247986 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1613 09:30:49.251073 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1614 09:30:49.251164 ==
1615 09:30:49.254583 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 09:30:49.258154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 09:30:49.258248 ==
1618 09:30:49.271233 TX Vref=22, minBit 8, minWin=27, winSum=450
1619 09:30:49.274833 TX Vref=24, minBit 8, minWin=27, winSum=449
1620 09:30:49.278075 TX Vref=26, minBit 15, minWin=27, winSum=454
1621 09:30:49.281455 TX Vref=28, minBit 15, minWin=27, winSum=457
1622 09:30:49.284666 TX Vref=30, minBit 15, minWin=27, winSum=455
1623 09:30:49.291516 TX Vref=32, minBit 12, minWin=27, winSum=453
1624 09:30:49.294948 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 28
1625 09:30:49.295050
1626 09:30:49.298233 Final TX Range 1 Vref 28
1627 09:30:49.298324
1628 09:30:49.298409 ==
1629 09:30:49.301606 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 09:30:49.305245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 09:30:49.305344 ==
1632 09:30:49.308756
1633 09:30:49.308836
1634 09:30:49.308975 TX Vref Scan disable
1635 09:30:49.312705 == TX Byte 0 ==
1636 09:30:49.315600 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1637 09:30:49.319252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1638 09:30:49.322638 == TX Byte 1 ==
1639 09:30:49.326172 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 09:30:49.329047 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 09:30:49.329139
1642 09:30:49.332653 [DATLAT]
1643 09:30:49.332740 Freq=800, CH1 RK0
1644 09:30:49.332843
1645 09:30:49.336175 DATLAT Default: 0xa
1646 09:30:49.336262 0, 0xFFFF, sum = 0
1647 09:30:49.339480 1, 0xFFFF, sum = 0
1648 09:30:49.339568 2, 0xFFFF, sum = 0
1649 09:30:49.342423 3, 0xFFFF, sum = 0
1650 09:30:49.342510 4, 0xFFFF, sum = 0
1651 09:30:49.346189 5, 0xFFFF, sum = 0
1652 09:30:49.346279 6, 0xFFFF, sum = 0
1653 09:30:49.349146 7, 0xFFFF, sum = 0
1654 09:30:49.349234 8, 0xFFFF, sum = 0
1655 09:30:49.352699 9, 0x0, sum = 1
1656 09:30:49.352788 10, 0x0, sum = 2
1657 09:30:49.356234 11, 0x0, sum = 3
1658 09:30:49.356323 12, 0x0, sum = 4
1659 09:30:49.359269 best_step = 10
1660 09:30:49.359358
1661 09:30:49.359443 ==
1662 09:30:49.362866 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 09:30:49.365743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 09:30:49.365831 ==
1665 09:30:49.365917 RX Vref Scan: 1
1666 09:30:49.365996
1667 09:30:49.369234 Set Vref Range= 32 -> 127
1668 09:30:49.369319
1669 09:30:49.372892 RX Vref 32 -> 127, step: 1
1670 09:30:49.373018
1671 09:30:49.375805 RX Delay -95 -> 252, step: 8
1672 09:30:49.375893
1673 09:30:49.379309 Set Vref, RX VrefLevel [Byte0]: 32
1674 09:30:49.382786 [Byte1]: 32
1675 09:30:49.382876
1676 09:30:49.385830 Set Vref, RX VrefLevel [Byte0]: 33
1677 09:30:49.389444 [Byte1]: 33
1678 09:30:49.389534
1679 09:30:49.392782 Set Vref, RX VrefLevel [Byte0]: 34
1680 09:30:49.396032 [Byte1]: 34
1681 09:30:49.399777
1682 09:30:49.399873 Set Vref, RX VrefLevel [Byte0]: 35
1683 09:30:49.403142 [Byte1]: 35
1684 09:30:49.407359
1685 09:30:49.407450 Set Vref, RX VrefLevel [Byte0]: 36
1686 09:30:49.410492 [Byte1]: 36
1687 09:30:49.414576
1688 09:30:49.414666 Set Vref, RX VrefLevel [Byte0]: 37
1689 09:30:49.418142 [Byte1]: 37
1690 09:30:49.422670
1691 09:30:49.422765 Set Vref, RX VrefLevel [Byte0]: 38
1692 09:30:49.425768 [Byte1]: 38
1693 09:30:49.430247
1694 09:30:49.430342 Set Vref, RX VrefLevel [Byte0]: 39
1695 09:30:49.433252 [Byte1]: 39
1696 09:30:49.437593
1697 09:30:49.437685 Set Vref, RX VrefLevel [Byte0]: 40
1698 09:30:49.441067 [Byte1]: 40
1699 09:30:49.445100
1700 09:30:49.445191 Set Vref, RX VrefLevel [Byte0]: 41
1701 09:30:49.448289 [Byte1]: 41
1702 09:30:49.452601
1703 09:30:49.452696 Set Vref, RX VrefLevel [Byte0]: 42
1704 09:30:49.456101 [Byte1]: 42
1705 09:30:49.460189
1706 09:30:49.460296 Set Vref, RX VrefLevel [Byte0]: 43
1707 09:30:49.463656 [Byte1]: 43
1708 09:30:49.468206
1709 09:30:49.468299 Set Vref, RX VrefLevel [Byte0]: 44
1710 09:30:49.471232 [Byte1]: 44
1711 09:30:49.475763
1712 09:30:49.475855 Set Vref, RX VrefLevel [Byte0]: 45
1713 09:30:49.478761 [Byte1]: 45
1714 09:30:49.483350
1715 09:30:49.483445 Set Vref, RX VrefLevel [Byte0]: 46
1716 09:30:49.486328 [Byte1]: 46
1717 09:30:49.490847
1718 09:30:49.490948 Set Vref, RX VrefLevel [Byte0]: 47
1719 09:30:49.494190 [Byte1]: 47
1720 09:30:49.498570
1721 09:30:49.498665 Set Vref, RX VrefLevel [Byte0]: 48
1722 09:30:49.501564 [Byte1]: 48
1723 09:30:49.506057
1724 09:30:49.506149 Set Vref, RX VrefLevel [Byte0]: 49
1725 09:30:49.509055 [Byte1]: 49
1726 09:30:49.513394
1727 09:30:49.513486 Set Vref, RX VrefLevel [Byte0]: 50
1728 09:30:49.516902 [Byte1]: 50
1729 09:30:49.521197
1730 09:30:49.521290 Set Vref, RX VrefLevel [Byte0]: 51
1731 09:30:49.524417 [Byte1]: 51
1732 09:30:49.528655
1733 09:30:49.528744 Set Vref, RX VrefLevel [Byte0]: 52
1734 09:30:49.532129 [Byte1]: 52
1735 09:30:49.536778
1736 09:30:49.536895 Set Vref, RX VrefLevel [Byte0]: 53
1737 09:30:49.539606 [Byte1]: 53
1738 09:30:49.544040
1739 09:30:49.544130 Set Vref, RX VrefLevel [Byte0]: 54
1740 09:30:49.547037 [Byte1]: 54
1741 09:30:49.551397
1742 09:30:49.551487 Set Vref, RX VrefLevel [Byte0]: 55
1743 09:30:49.554858 [Byte1]: 55
1744 09:30:49.558965
1745 09:30:49.559057 Set Vref, RX VrefLevel [Byte0]: 56
1746 09:30:49.562472 [Byte1]: 56
1747 09:30:49.566470
1748 09:30:49.566583 Set Vref, RX VrefLevel [Byte0]: 57
1749 09:30:49.570110 [Byte1]: 57
1750 09:30:49.574583
1751 09:30:49.574675 Set Vref, RX VrefLevel [Byte0]: 58
1752 09:30:49.577523 [Byte1]: 58
1753 09:30:49.582022
1754 09:30:49.582126 Set Vref, RX VrefLevel [Byte0]: 59
1755 09:30:49.585038 [Byte1]: 59
1756 09:30:49.589481
1757 09:30:49.589573 Set Vref, RX VrefLevel [Byte0]: 60
1758 09:30:49.593005 [Byte1]: 60
1759 09:30:49.597086
1760 09:30:49.597176 Set Vref, RX VrefLevel [Byte0]: 61
1761 09:30:49.600392 [Byte1]: 61
1762 09:30:49.604746
1763 09:30:49.604840 Set Vref, RX VrefLevel [Byte0]: 62
1764 09:30:49.608206 [Byte1]: 62
1765 09:30:49.612270
1766 09:30:49.612365 Set Vref, RX VrefLevel [Byte0]: 63
1767 09:30:49.615721 [Byte1]: 63
1768 09:30:49.619832
1769 09:30:49.619926 Set Vref, RX VrefLevel [Byte0]: 64
1770 09:30:49.623278 [Byte1]: 64
1771 09:30:49.627473
1772 09:30:49.627567 Set Vref, RX VrefLevel [Byte0]: 65
1773 09:30:49.631163 [Byte1]: 65
1774 09:30:49.635101
1775 09:30:49.635196 Set Vref, RX VrefLevel [Byte0]: 66
1776 09:30:49.638335 [Byte1]: 66
1777 09:30:49.642612
1778 09:30:49.642706 Set Vref, RX VrefLevel [Byte0]: 67
1779 09:30:49.646260 [Byte1]: 67
1780 09:30:49.650188
1781 09:30:49.650280 Set Vref, RX VrefLevel [Byte0]: 68
1782 09:30:49.653726 [Byte1]: 68
1783 09:30:49.657982
1784 09:30:49.658078 Set Vref, RX VrefLevel [Byte0]: 69
1785 09:30:49.661059 [Byte1]: 69
1786 09:30:49.665337
1787 09:30:49.665429 Set Vref, RX VrefLevel [Byte0]: 70
1788 09:30:49.668883 [Byte1]: 70
1789 09:30:49.673047
1790 09:30:49.673139 Set Vref, RX VrefLevel [Byte0]: 71
1791 09:30:49.676523 [Byte1]: 71
1792 09:30:49.680488
1793 09:30:49.680593 Set Vref, RX VrefLevel [Byte0]: 72
1794 09:30:49.683915 [Byte1]: 72
1795 09:30:49.688525
1796 09:30:49.688623 Set Vref, RX VrefLevel [Byte0]: 73
1797 09:30:49.691465 [Byte1]: 73
1798 09:30:49.695989
1799 09:30:49.696083 Set Vref, RX VrefLevel [Byte0]: 74
1800 09:30:49.699438 [Byte1]: 74
1801 09:30:49.703316
1802 09:30:49.703399 Set Vref, RX VrefLevel [Byte0]: 75
1803 09:30:49.706908 [Byte1]: 75
1804 09:30:49.711116
1805 09:30:49.711209 Set Vref, RX VrefLevel [Byte0]: 76
1806 09:30:49.714765 [Byte1]: 76
1807 09:30:49.718729
1808 09:30:49.718821 Set Vref, RX VrefLevel [Byte0]: 77
1809 09:30:49.721886 [Byte1]: 77
1810 09:30:49.726010
1811 09:30:49.726106 Final RX Vref Byte 0 = 48 to rank0
1812 09:30:49.729695 Final RX Vref Byte 1 = 63 to rank0
1813 09:30:49.732862 Final RX Vref Byte 0 = 48 to rank1
1814 09:30:49.736401 Final RX Vref Byte 1 = 63 to rank1==
1815 09:30:49.739704 Dram Type= 6, Freq= 0, CH_1, rank 0
1816 09:30:49.742879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 09:30:49.746465 ==
1818 09:30:49.746563 DQS Delay:
1819 09:30:49.746650 DQS0 = 0, DQS1 = 0
1820 09:30:49.749935 DQM Delay:
1821 09:30:49.750028 DQM0 = 91, DQM1 = 82
1822 09:30:49.752856 DQ Delay:
1823 09:30:49.752981 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1824 09:30:49.756414 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1825 09:30:49.759849 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1826 09:30:49.763082 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =84
1827 09:30:49.766603
1828 09:30:49.766697
1829 09:30:49.773195 [DQSOSCAuto] RK0, (LSB)MR18= 0x3351, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1830 09:30:49.776643 CH1 RK0: MR19=606, MR18=3351
1831 09:30:49.783178 CH1_RK0: MR19=0x606, MR18=0x3351, DQSOSC=389, MR23=63, INC=97, DEC=65
1832 09:30:49.783302
1833 09:30:49.786634 ----->DramcWriteLeveling(PI) begin...
1834 09:30:49.786727 ==
1835 09:30:49.789743 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 09:30:49.793213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 09:30:49.793304 ==
1838 09:30:49.796690 Write leveling (Byte 0): 27 => 27
1839 09:30:49.799818 Write leveling (Byte 1): 33 => 33
1840 09:30:49.803321 DramcWriteLeveling(PI) end<-----
1841 09:30:49.803412
1842 09:30:49.803499 ==
1843 09:30:49.806839 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 09:30:49.809909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 09:30:49.810000 ==
1846 09:30:49.813538 [Gating] SW mode calibration
1847 09:30:49.820122 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1848 09:30:49.826710 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1849 09:30:49.830026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1850 09:30:49.833268 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1851 09:30:49.839868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:30:49.843670 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:30:49.846785 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:30:49.849979 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:30:49.856897 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:30:49.860257 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:30:49.863313 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:30:49.870099 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:30:49.873627 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:30:49.876759 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:30:49.883717 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 09:30:49.886737 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:30:49.890348 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:30:49.896739 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:30:49.900299 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1866 09:30:49.903739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1867 09:30:49.910180 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:30:49.913784 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:30:49.916843 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 09:30:49.923663 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 09:30:49.926831 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 09:30:49.930132 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 09:30:49.933942 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 09:30:49.940377 0 9 4 | B1->B0 | 2323 2322 | 1 1 | (1 1) (0 0)
1875 09:30:49.943587 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1876 09:30:49.946869 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 09:30:49.953457 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 09:30:49.956987 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 09:30:49.960379 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 09:30:49.967173 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 09:30:49.970547 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 09:30:49.973519 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 0)
1883 09:30:49.980570 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:30:49.983539 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:30:49.987173 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:30:49.993615 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:30:49.997169 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:30:50.000248 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 09:30:50.007112 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 09:30:50.010606 0 11 4 | B1->B0 | 3636 3636 | 1 0 | (0 0) (0 0)
1891 09:30:50.014123 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 09:30:50.017206 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 09:30:50.024000 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 09:30:50.027029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 09:30:50.030488 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 09:30:50.037058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 09:30:50.040705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 09:30:50.044126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1899 09:30:50.050993 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1900 09:30:50.054161 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 09:30:50.057225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 09:30:50.063917 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 09:30:50.067214 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 09:30:50.070511 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 09:30:50.077570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 09:30:50.080982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 09:30:50.084150 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 09:30:50.087636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 09:30:50.094074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 09:30:50.097599 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 09:30:50.100584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 09:30:50.107609 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 09:30:50.110607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 09:30:50.114026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1915 09:30:50.120396 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 09:30:50.123674 Total UI for P1: 0, mck2ui 16
1917 09:30:50.127206 best dqsien dly found for B0: ( 0, 14, 4)
1918 09:30:50.127294 Total UI for P1: 0, mck2ui 16
1919 09:30:50.133798 best dqsien dly found for B1: ( 0, 14, 4)
1920 09:30:50.137270 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1921 09:30:50.140547 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1922 09:30:50.140635
1923 09:30:50.144076 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1924 09:30:50.147482 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1925 09:30:50.150702 [Gating] SW calibration Done
1926 09:30:50.150788 ==
1927 09:30:50.154130 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 09:30:50.157316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 09:30:50.157404 ==
1930 09:30:50.160434 RX Vref Scan: 0
1931 09:30:50.160518
1932 09:30:50.160584 RX Vref 0 -> 0, step: 1
1933 09:30:50.160642
1934 09:30:50.163819 RX Delay -130 -> 252, step: 16
1935 09:30:50.167296 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1936 09:30:50.174260 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1937 09:30:50.177529 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1938 09:30:50.180707 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1939 09:30:50.183925 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1940 09:30:50.187463 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1941 09:30:50.193839 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1942 09:30:50.197285 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1943 09:30:50.200827 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1944 09:30:50.203929 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1945 09:30:50.207303 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1946 09:30:50.213892 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1947 09:30:50.217448 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1948 09:30:50.220873 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1949 09:30:50.223892 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1950 09:30:50.227455 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1951 09:30:50.231003 ==
1952 09:30:50.231093 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 09:30:50.237451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 09:30:50.237546 ==
1955 09:30:50.237613 DQS Delay:
1956 09:30:50.240939 DQS0 = 0, DQS1 = 0
1957 09:30:50.241025 DQM Delay:
1958 09:30:50.244025 DQM0 = 88, DQM1 = 84
1959 09:30:50.244110 DQ Delay:
1960 09:30:50.247186 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1961 09:30:50.251060 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1962 09:30:50.254449 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =69
1963 09:30:50.257449 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1964 09:30:50.257540
1965 09:30:50.257607
1966 09:30:50.257667 ==
1967 09:30:50.260860 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 09:30:50.264104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 09:30:50.264194 ==
1970 09:30:50.264261
1971 09:30:50.264321
1972 09:30:50.267662 TX Vref Scan disable
1973 09:30:50.267749 == TX Byte 0 ==
1974 09:30:50.274103 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 09:30:50.277600 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 09:30:50.277698 == TX Byte 1 ==
1977 09:30:50.284129 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1978 09:30:50.287679 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1979 09:30:50.287774 ==
1980 09:30:50.290747 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 09:30:50.294360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 09:30:50.294451 ==
1983 09:30:50.308815 TX Vref=22, minBit 8, minWin=27, winSum=451
1984 09:30:50.312290 TX Vref=24, minBit 8, minWin=27, winSum=453
1985 09:30:50.315250 TX Vref=26, minBit 8, minWin=27, winSum=455
1986 09:30:50.318599 TX Vref=28, minBit 13, minWin=27, winSum=456
1987 09:30:50.322194 TX Vref=30, minBit 13, minWin=27, winSum=459
1988 09:30:50.328706 TX Vref=32, minBit 8, minWin=28, winSum=457
1989 09:30:50.332263 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 32
1990 09:30:50.332361
1991 09:30:50.335760 Final TX Range 1 Vref 32
1992 09:30:50.335848
1993 09:30:50.335914 ==
1994 09:30:50.338811 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 09:30:50.342480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 09:30:50.342571 ==
1997 09:30:50.342638
1998 09:30:50.345417
1999 09:30:50.345501 TX Vref Scan disable
2000 09:30:50.349129 == TX Byte 0 ==
2001 09:30:50.351945 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2002 09:30:50.359271 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2003 09:30:50.359384 == TX Byte 1 ==
2004 09:30:50.362088 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2005 09:30:50.368857 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2006 09:30:50.368988
2007 09:30:50.369056 [DATLAT]
2008 09:30:50.369118 Freq=800, CH1 RK1
2009 09:30:50.369177
2010 09:30:50.372081 DATLAT Default: 0xa
2011 09:30:50.372168 0, 0xFFFF, sum = 0
2012 09:30:50.375401 1, 0xFFFF, sum = 0
2013 09:30:50.375493 2, 0xFFFF, sum = 0
2014 09:30:50.378703 3, 0xFFFF, sum = 0
2015 09:30:50.378804 4, 0xFFFF, sum = 0
2016 09:30:50.381916 5, 0xFFFF, sum = 0
2017 09:30:50.385541 6, 0xFFFF, sum = 0
2018 09:30:50.385637 7, 0xFFFF, sum = 0
2019 09:30:50.389032 8, 0xFFFF, sum = 0
2020 09:30:50.389120 9, 0x0, sum = 1
2021 09:30:50.391846 10, 0x0, sum = 2
2022 09:30:50.391931 11, 0x0, sum = 3
2023 09:30:50.391997 12, 0x0, sum = 4
2024 09:30:50.395472 best_step = 10
2025 09:30:50.395557
2026 09:30:50.395622 ==
2027 09:30:50.398790 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 09:30:50.402420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 09:30:50.402507 ==
2030 09:30:50.405537 RX Vref Scan: 0
2031 09:30:50.405620
2032 09:30:50.405685 RX Vref 0 -> 0, step: 1
2033 09:30:50.405744
2034 09:30:50.408996 RX Delay -95 -> 252, step: 8
2035 09:30:50.415407 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2036 09:30:50.419023 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2037 09:30:50.422387 iDelay=209, Bit 2, Center 76 (-23 ~ 176) 200
2038 09:30:50.425389 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2039 09:30:50.428893 iDelay=209, Bit 4, Center 88 (-15 ~ 192) 208
2040 09:30:50.435376 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2041 09:30:50.438937 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2042 09:30:50.442063 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2043 09:30:50.445471 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2044 09:30:50.448872 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2045 09:30:50.455889 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2046 09:30:50.458759 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2047 09:30:50.462089 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2048 09:30:50.465778 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2049 09:30:50.468872 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2050 09:30:50.475655 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2051 09:30:50.475759 ==
2052 09:30:50.479076 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 09:30:50.482156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 09:30:50.482248 ==
2055 09:30:50.482313 DQS Delay:
2056 09:30:50.485825 DQS0 = 0, DQS1 = 0
2057 09:30:50.485938 DQM Delay:
2058 09:30:50.489090 DQM0 = 89, DQM1 = 83
2059 09:30:50.489187 DQ Delay:
2060 09:30:50.492205 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =88
2061 09:30:50.495556 DQ4 =88, DQ5 =100, DQ6 =96, DQ7 =88
2062 09:30:50.499058 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2063 09:30:50.502291 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2064 09:30:50.502380
2065 09:30:50.502447
2066 09:30:50.508814 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2067 09:30:50.512416 CH1 RK1: MR19=606, MR18=3D13
2068 09:30:50.518915 CH1_RK1: MR19=0x606, MR18=0x3D13, DQSOSC=394, MR23=63, INC=95, DEC=63
2069 09:30:50.522590 [RxdqsGatingPostProcess] freq 800
2070 09:30:50.528915 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2071 09:30:50.529051 Pre-setting of DQS Precalculation
2072 09:30:50.536053 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2073 09:30:50.542468 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2074 09:30:50.549453 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2075 09:30:50.549563
2076 09:30:50.549628
2077 09:30:50.552460 [Calibration Summary] 1600 Mbps
2078 09:30:50.555961 CH 0, Rank 0
2079 09:30:50.556047 SW Impedance : PASS
2080 09:30:50.559389 DUTY Scan : NO K
2081 09:30:50.562731 ZQ Calibration : PASS
2082 09:30:50.562844 Jitter Meter : NO K
2083 09:30:50.565702 CBT Training : PASS
2084 09:30:50.565786 Write leveling : PASS
2085 09:30:50.569094 RX DQS gating : PASS
2086 09:30:50.572441 RX DQ/DQS(RDDQC) : PASS
2087 09:30:50.572527 TX DQ/DQS : PASS
2088 09:30:50.576072 RX DATLAT : PASS
2089 09:30:50.579352 RX DQ/DQS(Engine): PASS
2090 09:30:50.579472 TX OE : NO K
2091 09:30:50.582401 All Pass.
2092 09:30:50.582490
2093 09:30:50.582556 CH 0, Rank 1
2094 09:30:50.586092 SW Impedance : PASS
2095 09:30:50.586178 DUTY Scan : NO K
2096 09:30:50.589183 ZQ Calibration : PASS
2097 09:30:50.592923 Jitter Meter : NO K
2098 09:30:50.593080 CBT Training : PASS
2099 09:30:50.596174 Write leveling : PASS
2100 09:30:50.596256 RX DQS gating : PASS
2101 09:30:50.599449 RX DQ/DQS(RDDQC) : PASS
2102 09:30:50.602647 TX DQ/DQS : PASS
2103 09:30:50.602732 RX DATLAT : PASS
2104 09:30:50.605799 RX DQ/DQS(Engine): PASS
2105 09:30:50.609493 TX OE : NO K
2106 09:30:50.609584 All Pass.
2107 09:30:50.609649
2108 09:30:50.609731 CH 1, Rank 0
2109 09:30:50.613024 SW Impedance : PASS
2110 09:30:50.615872 DUTY Scan : NO K
2111 09:30:50.615956 ZQ Calibration : PASS
2112 09:30:50.619403 Jitter Meter : NO K
2113 09:30:50.622957 CBT Training : PASS
2114 09:30:50.623043 Write leveling : PASS
2115 09:30:50.626360 RX DQS gating : PASS
2116 09:30:50.629426 RX DQ/DQS(RDDQC) : PASS
2117 09:30:50.629537 TX DQ/DQS : PASS
2118 09:30:50.632847 RX DATLAT : PASS
2119 09:30:50.632984 RX DQ/DQS(Engine): PASS
2120 09:30:50.636349 TX OE : NO K
2121 09:30:50.636434 All Pass.
2122 09:30:50.636497
2123 09:30:50.639350 CH 1, Rank 1
2124 09:30:50.639432 SW Impedance : PASS
2125 09:30:50.642860 DUTY Scan : NO K
2126 09:30:50.646025 ZQ Calibration : PASS
2127 09:30:50.646111 Jitter Meter : NO K
2128 09:30:50.649427 CBT Training : PASS
2129 09:30:50.652499 Write leveling : PASS
2130 09:30:50.652583 RX DQS gating : PASS
2131 09:30:50.655920 RX DQ/DQS(RDDQC) : PASS
2132 09:30:50.659389 TX DQ/DQS : PASS
2133 09:30:50.659476 RX DATLAT : PASS
2134 09:30:50.662943 RX DQ/DQS(Engine): PASS
2135 09:30:50.665810 TX OE : NO K
2136 09:30:50.665896 All Pass.
2137 09:30:50.665961
2138 09:30:50.669542 DramC Write-DBI off
2139 09:30:50.669627 PER_BANK_REFRESH: Hybrid Mode
2140 09:30:50.673072 TX_TRACKING: ON
2141 09:30:50.675922 [GetDramInforAfterCalByMRR] Vendor 6.
2142 09:30:50.679463 [GetDramInforAfterCalByMRR] Revision 606.
2143 09:30:50.682602 [GetDramInforAfterCalByMRR] Revision 2 0.
2144 09:30:50.682699 MR0 0x3b3b
2145 09:30:50.685994 MR8 0x5151
2146 09:30:50.689359 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2147 09:30:50.689461
2148 09:30:50.689526 MR0 0x3b3b
2149 09:30:50.689586 MR8 0x5151
2150 09:30:50.692548 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 09:30:50.696150
2152 09:30:50.703022 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2153 09:30:50.706431 [FAST_K] Save calibration result to emmc
2154 09:30:50.709498 [FAST_K] Save calibration result to emmc
2155 09:30:50.713051 dram_init: config_dvfs: 1
2156 09:30:50.716329 dramc_set_vcore_voltage set vcore to 662500
2157 09:30:50.719428 Read voltage for 1200, 2
2158 09:30:50.719518 Vio18 = 0
2159 09:30:50.722799 Vcore = 662500
2160 09:30:50.722884 Vdram = 0
2161 09:30:50.722950 Vddq = 0
2162 09:30:50.723010 Vmddr = 0
2163 09:30:50.729613 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2164 09:30:50.733131 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2165 09:30:50.736187 MEM_TYPE=3, freq_sel=15
2166 09:30:50.739618 sv_algorithm_assistance_LP4_1600
2167 09:30:50.743009 ============ PULL DRAM RESETB DOWN ============
2168 09:30:50.750074 ========== PULL DRAM RESETB DOWN end =========
2169 09:30:50.752970 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2170 09:30:50.756551 ===================================
2171 09:30:50.759910 LPDDR4 DRAM CONFIGURATION
2172 09:30:50.762988 ===================================
2173 09:30:50.763078 EX_ROW_EN[0] = 0x0
2174 09:30:50.766378 EX_ROW_EN[1] = 0x0
2175 09:30:50.766464 LP4Y_EN = 0x0
2176 09:30:50.769680 WORK_FSP = 0x0
2177 09:30:50.769766 WL = 0x4
2178 09:30:50.772960 RL = 0x4
2179 09:30:50.773060 BL = 0x2
2180 09:30:50.776608 RPST = 0x0
2181 09:30:50.776695 RD_PRE = 0x0
2182 09:30:50.779751 WR_PRE = 0x1
2183 09:30:50.779864 WR_PST = 0x0
2184 09:30:50.783078 DBI_WR = 0x0
2185 09:30:50.783165 DBI_RD = 0x0
2186 09:30:50.786406 OTF = 0x1
2187 09:30:50.789860 ===================================
2188 09:30:50.793149 ===================================
2189 09:30:50.793265 ANA top config
2190 09:30:50.796467 ===================================
2191 09:30:50.799651 DLL_ASYNC_EN = 0
2192 09:30:50.803243 ALL_SLAVE_EN = 0
2193 09:30:50.806352 NEW_RANK_MODE = 1
2194 09:30:50.806445 DLL_IDLE_MODE = 1
2195 09:30:50.809981 LP45_APHY_COMB_EN = 1
2196 09:30:50.813300 TX_ODT_DIS = 1
2197 09:30:50.816473 NEW_8X_MODE = 1
2198 09:30:50.819683 ===================================
2199 09:30:50.823247 ===================================
2200 09:30:50.826694 data_rate = 2400
2201 09:30:50.826786 CKR = 1
2202 09:30:50.829684 DQ_P2S_RATIO = 8
2203 09:30:50.833215 ===================================
2204 09:30:50.836571 CA_P2S_RATIO = 8
2205 09:30:50.840121 DQ_CA_OPEN = 0
2206 09:30:50.843186 DQ_SEMI_OPEN = 0
2207 09:30:50.843277 CA_SEMI_OPEN = 0
2208 09:30:50.846602 CA_FULL_RATE = 0
2209 09:30:50.850071 DQ_CKDIV4_EN = 0
2210 09:30:50.853155 CA_CKDIV4_EN = 0
2211 09:30:50.856529 CA_PREDIV_EN = 0
2212 09:30:50.860079 PH8_DLY = 17
2213 09:30:50.860234 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2214 09:30:50.863227 DQ_AAMCK_DIV = 4
2215 09:30:50.866740 CA_AAMCK_DIV = 4
2216 09:30:50.870090 CA_ADMCK_DIV = 4
2217 09:30:50.873395 DQ_TRACK_CA_EN = 0
2218 09:30:50.876681 CA_PICK = 1200
2219 09:30:50.880165 CA_MCKIO = 1200
2220 09:30:50.880266 MCKIO_SEMI = 0
2221 09:30:50.883301 PLL_FREQ = 2366
2222 09:30:50.886378 DQ_UI_PI_RATIO = 32
2223 09:30:50.890280 CA_UI_PI_RATIO = 0
2224 09:30:50.893615 ===================================
2225 09:30:50.896664 ===================================
2226 09:30:50.900071 memory_type:LPDDR4
2227 09:30:50.900164 GP_NUM : 10
2228 09:30:50.903299 SRAM_EN : 1
2229 09:30:50.903387 MD32_EN : 0
2230 09:30:50.906838 ===================================
2231 09:30:50.910196 [ANA_INIT] >>>>>>>>>>>>>>
2232 09:30:50.913451 <<<<<< [CONFIGURE PHASE]: ANA_TX
2233 09:30:50.916790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2234 09:30:50.920118 ===================================
2235 09:30:50.923611 data_rate = 2400,PCW = 0X5b00
2236 09:30:50.926924 ===================================
2237 09:30:50.930299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2238 09:30:50.936888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2239 09:30:50.940163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2240 09:30:50.946852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2241 09:30:50.949883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2242 09:30:50.953406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2243 09:30:50.953496 [ANA_INIT] flow start
2244 09:30:50.956415 [ANA_INIT] PLL >>>>>>>>
2245 09:30:50.959976 [ANA_INIT] PLL <<<<<<<<
2246 09:30:50.960064 [ANA_INIT] MIDPI >>>>>>>>
2247 09:30:50.963523 [ANA_INIT] MIDPI <<<<<<<<
2248 09:30:50.967024 [ANA_INIT] DLL >>>>>>>>
2249 09:30:50.967146 [ANA_INIT] DLL <<<<<<<<
2250 09:30:50.970120 [ANA_INIT] flow end
2251 09:30:50.973412 ============ LP4 DIFF to SE enter ============
2252 09:30:50.979772 ============ LP4 DIFF to SE exit ============
2253 09:30:50.979876 [ANA_INIT] <<<<<<<<<<<<<
2254 09:30:50.983362 [Flow] Enable top DCM control >>>>>
2255 09:30:50.986950 [Flow] Enable top DCM control <<<<<
2256 09:30:50.990062 Enable DLL master slave shuffle
2257 09:30:50.996458 ==============================================================
2258 09:30:50.996558 Gating Mode config
2259 09:30:51.003213 ==============================================================
2260 09:30:51.006599 Config description:
2261 09:30:51.013203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2262 09:30:51.019990 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2263 09:30:51.026724 SELPH_MODE 0: By rank 1: By Phase
2264 09:30:51.029699 ==============================================================
2265 09:30:51.033558 GAT_TRACK_EN = 1
2266 09:30:51.036431 RX_GATING_MODE = 2
2267 09:30:51.039747 RX_GATING_TRACK_MODE = 2
2268 09:30:51.043200 SELPH_MODE = 1
2269 09:30:51.046651 PICG_EARLY_EN = 1
2270 09:30:51.050186 VALID_LAT_VALUE = 1
2271 09:30:51.056623 ==============================================================
2272 09:30:51.060058 Enter into Gating configuration >>>>
2273 09:30:51.063445 Exit from Gating configuration <<<<
2274 09:30:51.063554 Enter into DVFS_PRE_config >>>>>
2275 09:30:51.076534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2276 09:30:51.079888 Exit from DVFS_PRE_config <<<<<
2277 09:30:51.083406 Enter into PICG configuration >>>>
2278 09:30:51.086794 Exit from PICG configuration <<<<
2279 09:30:51.086887 [RX_INPUT] configuration >>>>>
2280 09:30:51.089886 [RX_INPUT] configuration <<<<<
2281 09:30:51.096462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2282 09:30:51.099863 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2283 09:30:51.106811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2284 09:30:51.113407 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2285 09:30:51.120037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2286 09:30:51.126745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2287 09:30:51.130014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2288 09:30:51.133734 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2289 09:30:51.136860 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2290 09:30:51.143195 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2291 09:30:51.146564 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2292 09:30:51.149810 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2293 09:30:51.153318 ===================================
2294 09:30:51.156792 LPDDR4 DRAM CONFIGURATION
2295 09:30:51.160303 ===================================
2296 09:30:51.163757 EX_ROW_EN[0] = 0x0
2297 09:30:51.163843 EX_ROW_EN[1] = 0x0
2298 09:30:51.166653 LP4Y_EN = 0x0
2299 09:30:51.166737 WORK_FSP = 0x0
2300 09:30:51.170193 WL = 0x4
2301 09:30:51.170276 RL = 0x4
2302 09:30:51.173634 BL = 0x2
2303 09:30:51.173718 RPST = 0x0
2304 09:30:51.176873 RD_PRE = 0x0
2305 09:30:51.177012 WR_PRE = 0x1
2306 09:30:51.180103 WR_PST = 0x0
2307 09:30:51.180205 DBI_WR = 0x0
2308 09:30:51.183628 DBI_RD = 0x0
2309 09:30:51.183714 OTF = 0x1
2310 09:30:51.187013 ===================================
2311 09:30:51.190410 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2312 09:30:51.197053 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2313 09:30:51.200435 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2314 09:30:51.203427 ===================================
2315 09:30:51.207031 LPDDR4 DRAM CONFIGURATION
2316 09:30:51.210431 ===================================
2317 09:30:51.210535 EX_ROW_EN[0] = 0x10
2318 09:30:51.213428 EX_ROW_EN[1] = 0x0
2319 09:30:51.213512 LP4Y_EN = 0x0
2320 09:30:51.216675 WORK_FSP = 0x0
2321 09:30:51.220329 WL = 0x4
2322 09:30:51.220415 RL = 0x4
2323 09:30:51.223656 BL = 0x2
2324 09:30:51.223742 RPST = 0x0
2325 09:30:51.227007 RD_PRE = 0x0
2326 09:30:51.227091 WR_PRE = 0x1
2327 09:30:51.230066 WR_PST = 0x0
2328 09:30:51.230155 DBI_WR = 0x0
2329 09:30:51.233666 DBI_RD = 0x0
2330 09:30:51.233754 OTF = 0x1
2331 09:30:51.236805 ===================================
2332 09:30:51.243475 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2333 09:30:51.243581 ==
2334 09:30:51.246753 Dram Type= 6, Freq= 0, CH_0, rank 0
2335 09:30:51.249995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2336 09:30:51.250083 ==
2337 09:30:51.253297 [Duty_Offset_Calibration]
2338 09:30:51.256870 B0:2 B1:0 CA:1
2339 09:30:51.256995
2340 09:30:51.259969 [DutyScan_Calibration_Flow] k_type=0
2341 09:30:51.267440
2342 09:30:51.267546 ==CLK 0==
2343 09:30:51.270987 Final CLK duty delay cell = -4
2344 09:30:51.274024 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2345 09:30:51.277540 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2346 09:30:51.280539 [-4] AVG Duty = 4953%(X100)
2347 09:30:51.280631
2348 09:30:51.284156 CH0 CLK Duty spec in!! Max-Min= 156%
2349 09:30:51.287136 [DutyScan_Calibration_Flow] ====Done====
2350 09:30:51.287226
2351 09:30:51.290520 [DutyScan_Calibration_Flow] k_type=1
2352 09:30:51.306486
2353 09:30:51.306633 ==DQS 0 ==
2354 09:30:51.309525 Final DQS duty delay cell = 0
2355 09:30:51.312914 [0] MAX Duty = 5187%(X100), DQS PI = 30
2356 09:30:51.316415 [0] MIN Duty = 4938%(X100), DQS PI = 0
2357 09:30:51.316501 [0] AVG Duty = 5062%(X100)
2358 09:30:51.319447
2359 09:30:51.319531 ==DQS 1 ==
2360 09:30:51.322892 Final DQS duty delay cell = -4
2361 09:30:51.326353 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2362 09:30:51.329805 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2363 09:30:51.332829 [-4] AVG Duty = 5031%(X100)
2364 09:30:51.332917
2365 09:30:51.336466 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2366 09:30:51.336551
2367 09:30:51.339907 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2368 09:30:51.343107 [DutyScan_Calibration_Flow] ====Done====
2369 09:30:51.343196
2370 09:30:51.346196 [DutyScan_Calibration_Flow] k_type=3
2371 09:30:51.362984
2372 09:30:51.363135 ==DQM 0 ==
2373 09:30:51.366303 Final DQM duty delay cell = 0
2374 09:30:51.369848 [0] MAX Duty = 5062%(X100), DQS PI = 24
2375 09:30:51.372840 [0] MIN Duty = 4844%(X100), DQS PI = 0
2376 09:30:51.372956 [0] AVG Duty = 4953%(X100)
2377 09:30:51.376290
2378 09:30:51.376373 ==DQM 1 ==
2379 09:30:51.379648 Final DQM duty delay cell = 0
2380 09:30:51.383311 [0] MAX Duty = 5187%(X100), DQS PI = 48
2381 09:30:51.386157 [0] MIN Duty = 5000%(X100), DQS PI = 22
2382 09:30:51.386245 [0] AVG Duty = 5093%(X100)
2383 09:30:51.389792
2384 09:30:51.393113 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2385 09:30:51.393198
2386 09:30:51.396556 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2387 09:30:51.400021 [DutyScan_Calibration_Flow] ====Done====
2388 09:30:51.400105
2389 09:30:51.402746 [DutyScan_Calibration_Flow] k_type=2
2390 09:30:51.419386
2391 09:30:51.419530 ==DQ 0 ==
2392 09:30:51.422933 Final DQ duty delay cell = -4
2393 09:30:51.426357 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2394 09:30:51.429468 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2395 09:30:51.432822 [-4] AVG Duty = 4969%(X100)
2396 09:30:51.432955
2397 09:30:51.433035 ==DQ 1 ==
2398 09:30:51.436171 Final DQ duty delay cell = 4
2399 09:30:51.439612 [4] MAX Duty = 5093%(X100), DQS PI = 6
2400 09:30:51.442786 [4] MIN Duty = 5031%(X100), DQS PI = 0
2401 09:30:51.442871 [4] AVG Duty = 5062%(X100)
2402 09:30:51.442935
2403 09:30:51.446598 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2404 09:30:51.449703
2405 09:30:51.452798 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2406 09:30:51.456267 [DutyScan_Calibration_Flow] ====Done====
2407 09:30:51.456373 ==
2408 09:30:51.459716 Dram Type= 6, Freq= 0, CH_1, rank 0
2409 09:30:51.462991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2410 09:30:51.463078 ==
2411 09:30:51.466279 [Duty_Offset_Calibration]
2412 09:30:51.466361 B0:0 B1:-1 CA:2
2413 09:30:51.466473
2414 09:30:51.469420 [DutyScan_Calibration_Flow] k_type=0
2415 09:30:51.479406
2416 09:30:51.479529 ==CLK 0==
2417 09:30:51.482815 Final CLK duty delay cell = 0
2418 09:30:51.486422 [0] MAX Duty = 5156%(X100), DQS PI = 16
2419 09:30:51.489466 [0] MIN Duty = 4938%(X100), DQS PI = 44
2420 09:30:51.489562 [0] AVG Duty = 5047%(X100)
2421 09:30:51.492879
2422 09:30:51.493035 CH1 CLK Duty spec in!! Max-Min= 218%
2423 09:30:51.500022 [DutyScan_Calibration_Flow] ====Done====
2424 09:30:51.500128
2425 09:30:51.503080 [DutyScan_Calibration_Flow] k_type=1
2426 09:30:51.519164
2427 09:30:51.519309 ==DQS 0 ==
2428 09:30:51.522607 Final DQS duty delay cell = 0
2429 09:30:51.525622 [0] MAX Duty = 5093%(X100), DQS PI = 22
2430 09:30:51.529069 [0] MIN Duty = 4969%(X100), DQS PI = 0
2431 09:30:51.529155 [0] AVG Duty = 5031%(X100)
2432 09:30:51.532247
2433 09:30:51.532330 ==DQS 1 ==
2434 09:30:51.535564 Final DQS duty delay cell = 0
2435 09:30:51.538964 [0] MAX Duty = 5156%(X100), DQS PI = 0
2436 09:30:51.542452 [0] MIN Duty = 4844%(X100), DQS PI = 36
2437 09:30:51.542541 [0] AVG Duty = 5000%(X100)
2438 09:30:51.542606
2439 09:30:51.549077 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2440 09:30:51.549175
2441 09:30:51.552203 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2442 09:30:51.555788 [DutyScan_Calibration_Flow] ====Done====
2443 09:30:51.555877
2444 09:30:51.558777 [DutyScan_Calibration_Flow] k_type=3
2445 09:30:51.575765
2446 09:30:51.575916 ==DQM 0 ==
2447 09:30:51.578732 Final DQM duty delay cell = 4
2448 09:30:51.582179 [4] MAX Duty = 5093%(X100), DQS PI = 20
2449 09:30:51.585424 [4] MIN Duty = 4938%(X100), DQS PI = 48
2450 09:30:51.588570 [4] AVG Duty = 5015%(X100)
2451 09:30:51.588659
2452 09:30:51.588725 ==DQM 1 ==
2453 09:30:51.592125 Final DQM duty delay cell = -4
2454 09:30:51.595553 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2455 09:30:51.599146 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2456 09:30:51.602120 [-4] AVG Duty = 4875%(X100)
2457 09:30:51.602210
2458 09:30:51.605373 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2459 09:30:51.605463
2460 09:30:51.608709 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2461 09:30:51.612153 [DutyScan_Calibration_Flow] ====Done====
2462 09:30:51.612245
2463 09:30:51.615523 [DutyScan_Calibration_Flow] k_type=2
2464 09:30:51.632552
2465 09:30:51.632699 ==DQ 0 ==
2466 09:30:51.636024 Final DQ duty delay cell = 0
2467 09:30:51.639497 [0] MAX Duty = 5062%(X100), DQS PI = 20
2468 09:30:51.642806 [0] MIN Duty = 4938%(X100), DQS PI = 0
2469 09:30:51.642896 [0] AVG Duty = 5000%(X100)
2470 09:30:51.642962
2471 09:30:51.645800 ==DQ 1 ==
2472 09:30:51.649326 Final DQ duty delay cell = 0
2473 09:30:51.652810 [0] MAX Duty = 5031%(X100), DQS PI = 2
2474 09:30:51.655911 [0] MIN Duty = 4813%(X100), DQS PI = 34
2475 09:30:51.656003 [0] AVG Duty = 4922%(X100)
2476 09:30:51.656070
2477 09:30:51.658903 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2478 09:30:51.658990
2479 09:30:51.662582 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2480 09:30:51.669160 [DutyScan_Calibration_Flow] ====Done====
2481 09:30:51.672325 nWR fixed to 30
2482 09:30:51.672421 [ModeRegInit_LP4] CH0 RK0
2483 09:30:51.675574 [ModeRegInit_LP4] CH0 RK1
2484 09:30:51.679030 [ModeRegInit_LP4] CH1 RK0
2485 09:30:51.679122 [ModeRegInit_LP4] CH1 RK1
2486 09:30:51.682305 match AC timing 7
2487 09:30:51.686386 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2488 09:30:51.688899 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2489 09:30:51.696175 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2490 09:30:51.699302 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2491 09:30:51.705808 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2492 09:30:51.705913 ==
2493 09:30:51.708897 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 09:30:51.712655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 09:30:51.712749 ==
2496 09:30:51.719114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 09:30:51.722649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 09:30:51.732225 [CA 0] Center 38 (8~69) winsize 62
2499 09:30:51.735602 [CA 1] Center 38 (7~69) winsize 63
2500 09:30:51.739045 [CA 2] Center 35 (5~66) winsize 62
2501 09:30:51.742030 [CA 3] Center 35 (4~66) winsize 63
2502 09:30:51.745389 [CA 4] Center 34 (4~65) winsize 62
2503 09:30:51.748856 [CA 5] Center 33 (3~63) winsize 61
2504 09:30:51.748952
2505 09:30:51.752340 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2506 09:30:51.752427
2507 09:30:51.755455 [CATrainingPosCal] consider 1 rank data
2508 09:30:51.759163 u2DelayCellTimex100 = 270/100 ps
2509 09:30:51.762340 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2510 09:30:51.765672 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2511 09:30:51.769268 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 09:30:51.775652 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2513 09:30:51.778798 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2514 09:30:51.782301 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2515 09:30:51.782401
2516 09:30:51.785543 CA PerBit enable=1, Macro0, CA PI delay=33
2517 09:30:51.785633
2518 09:30:51.789197 [CBTSetCACLKResult] CA Dly = 33
2519 09:30:51.789290 CS Dly: 6 (0~37)
2520 09:30:51.789357 ==
2521 09:30:51.792813 Dram Type= 6, Freq= 0, CH_0, rank 1
2522 09:30:51.799177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 09:30:51.799283 ==
2524 09:30:51.802229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2525 09:30:51.808707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2526 09:30:51.817823 [CA 0] Center 39 (8~70) winsize 63
2527 09:30:51.821342 [CA 1] Center 38 (8~69) winsize 62
2528 09:30:51.824307 [CA 2] Center 35 (5~66) winsize 62
2529 09:30:51.827879 [CA 3] Center 35 (5~66) winsize 62
2530 09:30:51.831016 [CA 4] Center 34 (4~65) winsize 62
2531 09:30:51.834409 [CA 5] Center 34 (4~64) winsize 61
2532 09:30:51.834497
2533 09:30:51.837951 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2534 09:30:51.838038
2535 09:30:51.841039 [CATrainingPosCal] consider 2 rank data
2536 09:30:51.844870 u2DelayCellTimex100 = 270/100 ps
2537 09:30:51.847883 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2538 09:30:51.851307 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2539 09:30:51.854883 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 09:30:51.861569 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 09:30:51.865048 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2542 09:30:51.868080 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2543 09:30:51.868170
2544 09:30:51.871509 CA PerBit enable=1, Macro0, CA PI delay=33
2545 09:30:51.871596
2546 09:30:51.875151 [CBTSetCACLKResult] CA Dly = 33
2547 09:30:51.875238 CS Dly: 7 (0~39)
2548 09:30:51.875305
2549 09:30:51.878066 ----->DramcWriteLeveling(PI) begin...
2550 09:30:51.878153 ==
2551 09:30:51.881434 Dram Type= 6, Freq= 0, CH_0, rank 0
2552 09:30:51.888527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 09:30:51.888644 ==
2554 09:30:51.891638 Write leveling (Byte 0): 33 => 33
2555 09:30:51.891726 Write leveling (Byte 1): 30 => 30
2556 09:30:51.895058 DramcWriteLeveling(PI) end<-----
2557 09:30:51.895160
2558 09:30:51.898194 ==
2559 09:30:51.898282 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 09:30:51.904811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 09:30:51.904934 ==
2562 09:30:51.908461 [Gating] SW mode calibration
2563 09:30:51.914876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2564 09:30:51.918220 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2565 09:30:51.924826 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2566 09:30:51.928189 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2567 09:30:51.931638 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 09:30:51.938192 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 09:30:51.941611 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 09:30:51.945121 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 09:30:51.951509 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2572 09:30:51.954895 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2573 09:30:51.958428 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2574 09:30:51.961887 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 09:30:51.968261 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 09:30:51.971983 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 09:30:51.974876 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 09:30:51.981864 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 09:30:51.985078 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2580 09:30:51.988465 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2581 09:30:51.994927 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2582 09:30:51.998685 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 09:30:52.001706 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 09:30:52.008815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 09:30:52.011836 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 09:30:52.015226 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 09:30:52.021625 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 09:30:52.025469 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2589 09:30:52.028392 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2590 09:30:52.034963 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 09:30:52.038425 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 09:30:52.041900 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 09:30:52.044910 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 09:30:52.051929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 09:30:52.055617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 09:30:52.058363 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 09:30:52.065524 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 09:30:52.068368 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 09:30:52.071945 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 09:30:52.078510 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 09:30:52.081862 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 09:30:52.085487 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 09:30:52.092127 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2604 09:30:52.095572 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2605 09:30:52.098705 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2606 09:30:52.102045 Total UI for P1: 0, mck2ui 16
2607 09:30:52.105395 best dqsien dly found for B0: ( 1, 3, 26)
2608 09:30:52.108806 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 09:30:52.112249 Total UI for P1: 0, mck2ui 16
2610 09:30:52.115607 best dqsien dly found for B1: ( 1, 3, 30)
2611 09:30:52.118810 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2612 09:30:52.121990 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2613 09:30:52.125582
2614 09:30:52.129010 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2615 09:30:52.132445 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2616 09:30:52.135701 [Gating] SW calibration Done
2617 09:30:52.135794 ==
2618 09:30:52.139214 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 09:30:52.142234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 09:30:52.142324 ==
2621 09:30:52.142412 RX Vref Scan: 0
2622 09:30:52.142492
2623 09:30:52.145685 RX Vref 0 -> 0, step: 1
2624 09:30:52.145772
2625 09:30:52.149139 RX Delay -40 -> 252, step: 8
2626 09:30:52.152127 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2627 09:30:52.155726 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2628 09:30:52.162559 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2629 09:30:52.165509 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2630 09:30:52.169119 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2631 09:30:52.172459 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2632 09:30:52.175501 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2633 09:30:52.179020 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2634 09:30:52.186022 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2635 09:30:52.189319 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2636 09:30:52.192817 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2637 09:30:52.195824 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2638 09:30:52.199200 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2639 09:30:52.206019 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2640 09:30:52.209174 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2641 09:30:52.212398 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2642 09:30:52.212491 ==
2643 09:30:52.215678 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 09:30:52.219351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 09:30:52.219448 ==
2646 09:30:52.222594 DQS Delay:
2647 09:30:52.222688 DQS0 = 0, DQS1 = 0
2648 09:30:52.225720 DQM Delay:
2649 09:30:52.225828 DQM0 = 123, DQM1 = 110
2650 09:30:52.229306 DQ Delay:
2651 09:30:52.232842 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2652 09:30:52.236246 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2653 09:30:52.239140 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2654 09:30:52.242772 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2655 09:30:52.242861
2656 09:30:52.242926
2657 09:30:52.242989 ==
2658 09:30:52.246196 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 09:30:52.249328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 09:30:52.249415 ==
2661 09:30:52.249482
2662 09:30:52.249542
2663 09:30:52.252781 TX Vref Scan disable
2664 09:30:52.255786 == TX Byte 0 ==
2665 09:30:52.259183 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2666 09:30:52.262684 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2667 09:30:52.265999 == TX Byte 1 ==
2668 09:30:52.269475 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2669 09:30:52.273123 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2670 09:30:52.273215 ==
2671 09:30:52.276041 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 09:30:52.279710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 09:30:52.279799 ==
2674 09:30:52.292419 TX Vref=22, minBit 0, minWin=24, winSum=407
2675 09:30:52.295696 TX Vref=24, minBit 0, minWin=25, winSum=419
2676 09:30:52.299277 TX Vref=26, minBit 1, minWin=25, winSum=422
2677 09:30:52.302231 TX Vref=28, minBit 2, minWin=25, winSum=420
2678 09:30:52.305870 TX Vref=30, minBit 1, minWin=25, winSum=427
2679 09:30:52.309153 TX Vref=32, minBit 1, minWin=25, winSum=422
2680 09:30:52.315730 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 30
2681 09:30:52.315839
2682 09:30:52.319300 Final TX Range 1 Vref 30
2683 09:30:52.319388
2684 09:30:52.319454 ==
2685 09:30:52.322467 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 09:30:52.326045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 09:30:52.326138 ==
2688 09:30:52.326206
2689 09:30:52.329057
2690 09:30:52.329141 TX Vref Scan disable
2691 09:30:52.332482 == TX Byte 0 ==
2692 09:30:52.335633 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2693 09:30:52.339229 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2694 09:30:52.342285 == TX Byte 1 ==
2695 09:30:52.345845 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2696 09:30:52.348894 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2697 09:30:52.348992
2698 09:30:52.352403 [DATLAT]
2699 09:30:52.352487 Freq=1200, CH0 RK0
2700 09:30:52.352552
2701 09:30:52.355977 DATLAT Default: 0xd
2702 09:30:52.356062 0, 0xFFFF, sum = 0
2703 09:30:52.358993 1, 0xFFFF, sum = 0
2704 09:30:52.359078 2, 0xFFFF, sum = 0
2705 09:30:52.362424 3, 0xFFFF, sum = 0
2706 09:30:52.362512 4, 0xFFFF, sum = 0
2707 09:30:52.365965 5, 0xFFFF, sum = 0
2708 09:30:52.366053 6, 0xFFFF, sum = 0
2709 09:30:52.369363 7, 0xFFFF, sum = 0
2710 09:30:52.369456 8, 0xFFFF, sum = 0
2711 09:30:52.372843 9, 0xFFFF, sum = 0
2712 09:30:52.372952 10, 0xFFFF, sum = 0
2713 09:30:52.375821 11, 0xFFFF, sum = 0
2714 09:30:52.375921 12, 0x0, sum = 1
2715 09:30:52.379298 13, 0x0, sum = 2
2716 09:30:52.379385 14, 0x0, sum = 3
2717 09:30:52.382696 15, 0x0, sum = 4
2718 09:30:52.382784 best_step = 13
2719 09:30:52.382849
2720 09:30:52.382907 ==
2721 09:30:52.385766 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 09:30:52.392622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 09:30:52.392729 ==
2724 09:30:52.392794 RX Vref Scan: 1
2725 09:30:52.392853
2726 09:30:52.396281 Set Vref Range= 32 -> 127
2727 09:30:52.396368
2728 09:30:52.399189 RX Vref 32 -> 127, step: 1
2729 09:30:52.399274
2730 09:30:52.402714 RX Delay -13 -> 252, step: 4
2731 09:30:52.402801
2732 09:30:52.402865 Set Vref, RX VrefLevel [Byte0]: 32
2733 09:30:52.406159 [Byte1]: 32
2734 09:30:52.410787
2735 09:30:52.410882 Set Vref, RX VrefLevel [Byte0]: 33
2736 09:30:52.414140 [Byte1]: 33
2737 09:30:52.418429
2738 09:30:52.418524 Set Vref, RX VrefLevel [Byte0]: 34
2739 09:30:52.421996 [Byte1]: 34
2740 09:30:52.426218
2741 09:30:52.426312 Set Vref, RX VrefLevel [Byte0]: 35
2742 09:30:52.430003 [Byte1]: 35
2743 09:30:52.434172
2744 09:30:52.434282 Set Vref, RX VrefLevel [Byte0]: 36
2745 09:30:52.437429 [Byte1]: 36
2746 09:30:52.441986
2747 09:30:52.442074 Set Vref, RX VrefLevel [Byte0]: 37
2748 09:30:52.445580 [Byte1]: 37
2749 09:30:52.449992
2750 09:30:52.450101 Set Vref, RX VrefLevel [Byte0]: 38
2751 09:30:52.453471 [Byte1]: 38
2752 09:30:52.458027
2753 09:30:52.458121 Set Vref, RX VrefLevel [Byte0]: 39
2754 09:30:52.461081 [Byte1]: 39
2755 09:30:52.466039
2756 09:30:52.466131 Set Vref, RX VrefLevel [Byte0]: 40
2757 09:30:52.469062 [Byte1]: 40
2758 09:30:52.473912
2759 09:30:52.474005 Set Vref, RX VrefLevel [Byte0]: 41
2760 09:30:52.476815 [Byte1]: 41
2761 09:30:52.481788
2762 09:30:52.481884 Set Vref, RX VrefLevel [Byte0]: 42
2763 09:30:52.484685 [Byte1]: 42
2764 09:30:52.490029
2765 09:30:52.490126 Set Vref, RX VrefLevel [Byte0]: 43
2766 09:30:52.493141 [Byte1]: 43
2767 09:30:52.497261
2768 09:30:52.497353 Set Vref, RX VrefLevel [Byte0]: 44
2769 09:30:52.500626 [Byte1]: 44
2770 09:30:52.505585
2771 09:30:52.505678 Set Vref, RX VrefLevel [Byte0]: 45
2772 09:30:52.508520 [Byte1]: 45
2773 09:30:52.513023
2774 09:30:52.513116 Set Vref, RX VrefLevel [Byte0]: 46
2775 09:30:52.516608 [Byte1]: 46
2776 09:30:52.520871
2777 09:30:52.520963 Set Vref, RX VrefLevel [Byte0]: 47
2778 09:30:52.524223 [Byte1]: 47
2779 09:30:52.529084
2780 09:30:52.529185 Set Vref, RX VrefLevel [Byte0]: 48
2781 09:30:52.532297 [Byte1]: 48
2782 09:30:52.537136
2783 09:30:52.537229 Set Vref, RX VrefLevel [Byte0]: 49
2784 09:30:52.540011 [Byte1]: 49
2785 09:30:52.544657
2786 09:30:52.544750 Set Vref, RX VrefLevel [Byte0]: 50
2787 09:30:52.548061 [Byte1]: 50
2788 09:30:52.552405
2789 09:30:52.552497 Set Vref, RX VrefLevel [Byte0]: 51
2790 09:30:52.555840 [Byte1]: 51
2791 09:30:52.560809
2792 09:30:52.560902 Set Vref, RX VrefLevel [Byte0]: 52
2793 09:30:52.563781 [Byte1]: 52
2794 09:30:52.568347
2795 09:30:52.568436 Set Vref, RX VrefLevel [Byte0]: 53
2796 09:30:52.571934 [Byte1]: 53
2797 09:30:52.576287
2798 09:30:52.576374 Set Vref, RX VrefLevel [Byte0]: 54
2799 09:30:52.579757 [Byte1]: 54
2800 09:30:52.584209
2801 09:30:52.584304 Set Vref, RX VrefLevel [Byte0]: 55
2802 09:30:52.587762 [Byte1]: 55
2803 09:30:52.592290
2804 09:30:52.592379 Set Vref, RX VrefLevel [Byte0]: 56
2805 09:30:52.598893 [Byte1]: 56
2806 09:30:52.598988
2807 09:30:52.601886 Set Vref, RX VrefLevel [Byte0]: 57
2808 09:30:52.605037 [Byte1]: 57
2809 09:30:52.605122
2810 09:30:52.608421 Set Vref, RX VrefLevel [Byte0]: 58
2811 09:30:52.611917 [Byte1]: 58
2812 09:30:52.615882
2813 09:30:52.615971 Set Vref, RX VrefLevel [Byte0]: 59
2814 09:30:52.619259 [Byte1]: 59
2815 09:30:52.623767
2816 09:30:52.623854 Set Vref, RX VrefLevel [Byte0]: 60
2817 09:30:52.627071 [Byte1]: 60
2818 09:30:52.631355
2819 09:30:52.631445 Set Vref, RX VrefLevel [Byte0]: 61
2820 09:30:52.635123 [Byte1]: 61
2821 09:30:52.639260
2822 09:30:52.639350 Set Vref, RX VrefLevel [Byte0]: 62
2823 09:30:52.642840 [Byte1]: 62
2824 09:30:52.647226
2825 09:30:52.647318 Set Vref, RX VrefLevel [Byte0]: 63
2826 09:30:52.650579 [Byte1]: 63
2827 09:30:52.655009
2828 09:30:52.655101 Set Vref, RX VrefLevel [Byte0]: 64
2829 09:30:52.658547 [Byte1]: 64
2830 09:30:52.662945
2831 09:30:52.663037 Set Vref, RX VrefLevel [Byte0]: 65
2832 09:30:52.666137 [Byte1]: 65
2833 09:30:52.671169
2834 09:30:52.671261 Set Vref, RX VrefLevel [Byte0]: 66
2835 09:30:52.674261 [Byte1]: 66
2836 09:30:52.678809
2837 09:30:52.678897 Set Vref, RX VrefLevel [Byte0]: 67
2838 09:30:52.682121 [Byte1]: 67
2839 09:30:52.686760
2840 09:30:52.686860 Set Vref, RX VrefLevel [Byte0]: 68
2841 09:30:52.690258 [Byte1]: 68
2842 09:30:52.694792
2843 09:30:52.694882 Set Vref, RX VrefLevel [Byte0]: 69
2844 09:30:52.697729 [Byte1]: 69
2845 09:30:52.702746
2846 09:30:52.702836 Final RX Vref Byte 0 = 58 to rank0
2847 09:30:52.705662 Final RX Vref Byte 1 = 49 to rank0
2848 09:30:52.708888 Final RX Vref Byte 0 = 58 to rank1
2849 09:30:52.712336 Final RX Vref Byte 1 = 49 to rank1==
2850 09:30:52.715637 Dram Type= 6, Freq= 0, CH_0, rank 0
2851 09:30:52.722300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 09:30:52.722406 ==
2853 09:30:52.722474 DQS Delay:
2854 09:30:52.722535 DQS0 = 0, DQS1 = 0
2855 09:30:52.725874 DQM Delay:
2856 09:30:52.725957 DQM0 = 122, DQM1 = 109
2857 09:30:52.728969 DQ Delay:
2858 09:30:52.732404 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2859 09:30:52.735786 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2860 09:30:52.739306 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2861 09:30:52.742361 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =116
2862 09:30:52.742448
2863 09:30:52.742525
2864 09:30:52.749289 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2865 09:30:52.752290 CH0 RK0: MR19=404, MR18=B08
2866 09:30:52.759011 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2867 09:30:52.759117
2868 09:30:52.762432 ----->DramcWriteLeveling(PI) begin...
2869 09:30:52.762551 ==
2870 09:30:52.765791 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 09:30:52.769208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 09:30:52.769298 ==
2873 09:30:52.772665 Write leveling (Byte 0): 34 => 34
2874 09:30:52.775752 Write leveling (Byte 1): 30 => 30
2875 09:30:52.779277 DramcWriteLeveling(PI) end<-----
2876 09:30:52.779365
2877 09:30:52.779431 ==
2878 09:30:52.782649 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 09:30:52.786098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 09:30:52.788998 ==
2881 09:30:52.789088 [Gating] SW mode calibration
2882 09:30:52.799491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2883 09:30:52.802439 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2884 09:30:52.805971 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2885 09:30:52.812448 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 09:30:52.815868 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 09:30:52.819303 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 09:30:52.826324 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 09:30:52.829372 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 09:30:52.832770 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 09:30:52.839402 0 15 28 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (1 0)
2892 09:30:52.843053 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 09:30:52.846008 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 09:30:52.849590 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 09:30:52.856179 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 09:30:52.859387 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 09:30:52.862617 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 09:30:52.869230 1 0 24 | B1->B0 | 2424 2626 | 1 1 | (0 0) (0 0)
2899 09:30:52.872467 1 0 28 | B1->B0 | 3d3d 3f3f | 0 1 | (0 0) (0 0)
2900 09:30:52.876102 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 09:30:52.882647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 09:30:52.886015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 09:30:52.889475 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 09:30:52.895929 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 09:30:52.899340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 09:30:52.902423 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 09:30:52.909435 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2908 09:30:52.912439 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 09:30:52.915864 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 09:30:52.922722 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 09:30:52.925804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 09:30:52.929351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 09:30:52.936020 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 09:30:52.939466 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 09:30:52.942562 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 09:30:52.949510 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 09:30:52.953100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:30:52.955894 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:30:52.959258 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:30:52.965901 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:30:52.969578 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:30:52.972912 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:30:52.979409 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 09:30:52.982662 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 09:30:52.986309 Total UI for P1: 0, mck2ui 16
2926 09:30:52.989379 best dqsien dly found for B0: ( 1, 3, 28)
2927 09:30:52.992736 Total UI for P1: 0, mck2ui 16
2928 09:30:52.996165 best dqsien dly found for B1: ( 1, 3, 30)
2929 09:30:52.999734 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2930 09:30:53.003077 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2931 09:30:53.003167
2932 09:30:53.006237 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2933 09:30:53.009760 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2934 09:30:53.012677 [Gating] SW calibration Done
2935 09:30:53.012764 ==
2936 09:30:53.016260 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 09:30:53.019820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 09:30:53.022825 ==
2939 09:30:53.022915 RX Vref Scan: 0
2940 09:30:53.022981
2941 09:30:53.026400 RX Vref 0 -> 0, step: 1
2942 09:30:53.026486
2943 09:30:53.026552 RX Delay -40 -> 252, step: 8
2944 09:30:53.032855 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2945 09:30:53.036370 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2946 09:30:53.039680 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2947 09:30:53.043078 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2948 09:30:53.046459 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2949 09:30:53.052908 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2950 09:30:53.056486 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2951 09:30:53.059861 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2952 09:30:53.062938 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2953 09:30:53.066592 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2954 09:30:53.073238 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2955 09:30:53.076368 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2956 09:30:53.079781 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2957 09:30:53.083084 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2958 09:30:53.086663 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2959 09:30:53.093051 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2960 09:30:53.093166 ==
2961 09:30:53.096475 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 09:30:53.099807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 09:30:53.099899 ==
2964 09:30:53.099966 DQS Delay:
2965 09:30:53.102907 DQS0 = 0, DQS1 = 0
2966 09:30:53.102993 DQM Delay:
2967 09:30:53.106562 DQM0 = 120, DQM1 = 108
2968 09:30:53.106648 DQ Delay:
2969 09:30:53.109538 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2970 09:30:53.112951 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2971 09:30:53.116541 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2972 09:30:53.119867 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2973 09:30:53.119955
2974 09:30:53.120020
2975 09:30:53.120079 ==
2976 09:30:53.122889 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 09:30:53.129625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 09:30:53.129727 ==
2979 09:30:53.129796
2980 09:30:53.129857
2981 09:30:53.129916 TX Vref Scan disable
2982 09:30:53.133613 == TX Byte 0 ==
2983 09:30:53.136705 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2984 09:30:53.140112 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2985 09:30:53.143669 == TX Byte 1 ==
2986 09:30:53.146674 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2987 09:30:53.150153 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2988 09:30:53.153487 ==
2989 09:30:53.157066 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 09:30:53.159932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 09:30:53.160022 ==
2992 09:30:53.171535 TX Vref=22, minBit 0, minWin=24, winSum=413
2993 09:30:53.174774 TX Vref=24, minBit 7, minWin=24, winSum=416
2994 09:30:53.178023 TX Vref=26, minBit 0, minWin=25, winSum=420
2995 09:30:53.181621 TX Vref=28, minBit 1, minWin=24, winSum=423
2996 09:30:53.184951 TX Vref=30, minBit 1, minWin=25, winSum=421
2997 09:30:53.188148 TX Vref=32, minBit 2, minWin=25, winSum=424
2998 09:30:53.194985 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 32
2999 09:30:53.195102
3000 09:30:53.198099 Final TX Range 1 Vref 32
3001 09:30:53.198188
3002 09:30:53.198254 ==
3003 09:30:53.201514 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 09:30:53.204829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 09:30:53.204969 ==
3006 09:30:53.205038
3007 09:30:53.208302
3008 09:30:53.208388 TX Vref Scan disable
3009 09:30:53.211758 == TX Byte 0 ==
3010 09:30:53.214856 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3011 09:30:53.218400 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3012 09:30:53.222075 == TX Byte 1 ==
3013 09:30:53.224925 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3014 09:30:53.228535 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3015 09:30:53.228623
3016 09:30:53.231933 [DATLAT]
3017 09:30:53.232017 Freq=1200, CH0 RK1
3018 09:30:53.232083
3019 09:30:53.234925 DATLAT Default: 0xd
3020 09:30:53.235010 0, 0xFFFF, sum = 0
3021 09:30:53.238297 1, 0xFFFF, sum = 0
3022 09:30:53.238385 2, 0xFFFF, sum = 0
3023 09:30:53.241921 3, 0xFFFF, sum = 0
3024 09:30:53.242010 4, 0xFFFF, sum = 0
3025 09:30:53.244884 5, 0xFFFF, sum = 0
3026 09:30:53.245019 6, 0xFFFF, sum = 0
3027 09:30:53.248586 7, 0xFFFF, sum = 0
3028 09:30:53.248674 8, 0xFFFF, sum = 0
3029 09:30:53.251649 9, 0xFFFF, sum = 0
3030 09:30:53.254975 10, 0xFFFF, sum = 0
3031 09:30:53.255063 11, 0xFFFF, sum = 0
3032 09:30:53.258455 12, 0x0, sum = 1
3033 09:30:53.258542 13, 0x0, sum = 2
3034 09:30:53.258608 14, 0x0, sum = 3
3035 09:30:53.262015 15, 0x0, sum = 4
3036 09:30:53.262103 best_step = 13
3037 09:30:53.262174
3038 09:30:53.262240 ==
3039 09:30:53.265216 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 09:30:53.271982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 09:30:53.272089 ==
3042 09:30:53.272159 RX Vref Scan: 0
3043 09:30:53.272220
3044 09:30:53.275028 RX Vref 0 -> 0, step: 1
3045 09:30:53.275112
3046 09:30:53.278292 RX Delay -21 -> 252, step: 4
3047 09:30:53.281925 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3048 09:30:53.285276 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3049 09:30:53.292114 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3050 09:30:53.295614 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3051 09:30:53.298671 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3052 09:30:53.301850 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3053 09:30:53.305487 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3054 09:30:53.311814 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3055 09:30:53.315448 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3056 09:30:53.318410 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3057 09:30:53.321968 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3058 09:30:53.325484 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3059 09:30:53.331982 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3060 09:30:53.334972 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3061 09:30:53.338712 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3062 09:30:53.342240 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3063 09:30:53.342329 ==
3064 09:30:53.345230 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 09:30:53.348725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 09:30:53.352150 ==
3067 09:30:53.352241 DQS Delay:
3068 09:30:53.352306 DQS0 = 0, DQS1 = 0
3069 09:30:53.355636 DQM Delay:
3070 09:30:53.355722 DQM0 = 119, DQM1 = 108
3071 09:30:53.358657 DQ Delay:
3072 09:30:53.362090 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3073 09:30:53.365493 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3074 09:30:53.368754 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3075 09:30:53.372398 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3076 09:30:53.372488
3077 09:30:53.372554
3078 09:30:53.378980 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3079 09:30:53.382302 CH0 RK1: MR19=403, MR18=12F9
3080 09:30:53.388852 CH0_RK1: MR19=0x403, MR18=0x12F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3081 09:30:53.392577 [RxdqsGatingPostProcess] freq 1200
3082 09:30:53.395899 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3083 09:30:53.399059 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 09:30:53.402123 best DQS1 dly(2T, 0.5T) = (0, 11)
3085 09:30:53.405838 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 09:30:53.408837 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3087 09:30:53.412424 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 09:30:53.415497 best DQS1 dly(2T, 0.5T) = (0, 11)
3089 09:30:53.419062 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 09:30:53.422503 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3091 09:30:53.426003 Pre-setting of DQS Precalculation
3092 09:30:53.428882 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3093 09:30:53.429003 ==
3094 09:30:53.432438 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 09:30:53.439013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 09:30:53.439112 ==
3097 09:30:53.442241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 09:30:53.449176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3099 09:30:53.458041 [CA 0] Center 37 (7~68) winsize 62
3100 09:30:53.460986 [CA 1] Center 37 (7~68) winsize 62
3101 09:30:53.464682 [CA 2] Center 35 (5~65) winsize 61
3102 09:30:53.468203 [CA 3] Center 34 (4~65) winsize 62
3103 09:30:53.471090 [CA 4] Center 34 (3~65) winsize 63
3104 09:30:53.474576 [CA 5] Center 33 (3~64) winsize 62
3105 09:30:53.474678
3106 09:30:53.478164 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3107 09:30:53.478249
3108 09:30:53.481362 [CATrainingPosCal] consider 1 rank data
3109 09:30:53.484795 u2DelayCellTimex100 = 270/100 ps
3110 09:30:53.487636 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 09:30:53.491139 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3112 09:30:53.498130 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 09:30:53.501389 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 09:30:53.504616 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3115 09:30:53.507835 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 09:30:53.507931
3117 09:30:53.511531 CA PerBit enable=1, Macro0, CA PI delay=33
3118 09:30:53.511617
3119 09:30:53.514837 [CBTSetCACLKResult] CA Dly = 33
3120 09:30:53.514922 CS Dly: 5 (0~36)
3121 09:30:53.514988 ==
3122 09:30:53.518014 Dram Type= 6, Freq= 0, CH_1, rank 1
3123 09:30:53.524582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 09:30:53.524686 ==
3125 09:30:53.528156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 09:30:53.534642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 09:30:53.543535 [CA 0] Center 38 (8~68) winsize 61
3128 09:30:53.546926 [CA 1] Center 38 (7~69) winsize 63
3129 09:30:53.550265 [CA 2] Center 35 (5~66) winsize 62
3130 09:30:53.553866 [CA 3] Center 35 (5~65) winsize 61
3131 09:30:53.557127 [CA 4] Center 35 (5~65) winsize 61
3132 09:30:53.560666 [CA 5] Center 34 (4~64) winsize 61
3133 09:30:53.560757
3134 09:30:53.563680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3135 09:30:53.563767
3136 09:30:53.567038 [CATrainingPosCal] consider 2 rank data
3137 09:30:53.570411 u2DelayCellTimex100 = 270/100 ps
3138 09:30:53.573859 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3139 09:30:53.576896 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3140 09:30:53.580410 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3141 09:30:53.587008 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3142 09:30:53.590354 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3143 09:30:53.593772 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3144 09:30:53.593865
3145 09:30:53.597180 CA PerBit enable=1, Macro0, CA PI delay=34
3146 09:30:53.597267
3147 09:30:53.600633 [CBTSetCACLKResult] CA Dly = 34
3148 09:30:53.600722 CS Dly: 6 (0~39)
3149 09:30:53.600823
3150 09:30:53.603781 ----->DramcWriteLeveling(PI) begin...
3151 09:30:53.603870 ==
3152 09:30:53.606972 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 09:30:53.614022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 09:30:53.614133 ==
3155 09:30:53.617329 Write leveling (Byte 0): 26 => 26
3156 09:30:53.620574 Write leveling (Byte 1): 28 => 28
3157 09:30:53.620665 DramcWriteLeveling(PI) end<-----
3158 09:30:53.620751
3159 09:30:53.624194 ==
3160 09:30:53.627349 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 09:30:53.630695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 09:30:53.630786 ==
3163 09:30:53.634151 [Gating] SW mode calibration
3164 09:30:53.640728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3165 09:30:53.644368 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3166 09:30:53.650596 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 09:30:53.653975 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 09:30:53.657556 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 09:30:53.664075 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 09:30:53.667561 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 09:30:53.670577 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3172 09:30:53.677265 0 15 24 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (1 0)
3173 09:30:53.680661 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3174 09:30:53.684346 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 09:30:53.687799 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 09:30:53.694443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 09:30:53.697937 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 09:30:53.700838 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 09:30:53.707401 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 09:30:53.711206 1 0 24 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3181 09:30:53.714031 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 09:30:53.721122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 09:30:53.724543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 09:30:53.727899 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 09:30:53.734156 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 09:30:53.737607 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 09:30:53.741215 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3188 09:30:53.744562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3189 09:30:53.751105 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3190 09:30:53.754507 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 09:30:53.757714 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 09:30:53.764202 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 09:30:53.767716 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 09:30:53.771249 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 09:30:53.777697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 09:30:53.781149 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 09:30:53.784223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 09:30:53.790701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 09:30:53.794191 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:30:53.797854 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:30:53.804314 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:30:53.807640 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:30:53.810917 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3204 09:30:53.817598 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 09:30:53.820955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 09:30:53.824191 Total UI for P1: 0, mck2ui 16
3207 09:30:53.827919 best dqsien dly found for B0: ( 1, 3, 22)
3208 09:30:53.831031 Total UI for P1: 0, mck2ui 16
3209 09:30:53.834340 best dqsien dly found for B1: ( 1, 3, 24)
3210 09:30:53.837710 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3211 09:30:53.840835 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3212 09:30:53.840925
3213 09:30:53.844272 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3214 09:30:53.847785 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3215 09:30:53.851319 [Gating] SW calibration Done
3216 09:30:53.851407 ==
3217 09:30:53.854396 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 09:30:53.857818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 09:30:53.857911 ==
3220 09:30:53.860971 RX Vref Scan: 0
3221 09:30:53.861057
3222 09:30:53.864279 RX Vref 0 -> 0, step: 1
3223 09:30:53.864367
3224 09:30:53.864433 RX Delay -40 -> 252, step: 8
3225 09:30:53.870793 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3226 09:30:53.874345 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3227 09:30:53.877767 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3228 09:30:53.880926 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3229 09:30:53.884378 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3230 09:30:53.891356 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3231 09:30:53.894339 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3232 09:30:53.897432 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3233 09:30:53.900954 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3234 09:30:53.904421 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3235 09:30:53.907880 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3236 09:30:53.914291 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3237 09:30:53.917933 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3238 09:30:53.921256 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3239 09:30:53.924619 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3240 09:30:53.931022 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3241 09:30:53.931127 ==
3242 09:30:53.934587 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 09:30:53.937802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 09:30:53.937891 ==
3245 09:30:53.937955 DQS Delay:
3246 09:30:53.940915 DQS0 = 0, DQS1 = 0
3247 09:30:53.941070 DQM Delay:
3248 09:30:53.944285 DQM0 = 119, DQM1 = 113
3249 09:30:53.944368 DQ Delay:
3250 09:30:53.947826 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3251 09:30:53.951334 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3252 09:30:53.954406 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3253 09:30:53.957813 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3254 09:30:53.957901
3255 09:30:53.957966
3256 09:30:53.958024 ==
3257 09:30:53.961194 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 09:30:53.967869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 09:30:53.967970 ==
3260 09:30:53.968037
3261 09:30:53.968098
3262 09:30:53.968155 TX Vref Scan disable
3263 09:30:53.971494 == TX Byte 0 ==
3264 09:30:53.974427 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3265 09:30:53.977986 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3266 09:30:53.981482 == TX Byte 1 ==
3267 09:30:53.984849 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 09:30:53.988193 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 09:30:53.991210 ==
3270 09:30:53.994665 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 09:30:53.998115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 09:30:53.998204 ==
3273 09:30:54.008997 TX Vref=22, minBit 1, minWin=24, winSum=405
3274 09:30:54.012517 TX Vref=24, minBit 1, minWin=25, winSum=409
3275 09:30:54.015602 TX Vref=26, minBit 1, minWin=25, winSum=415
3276 09:30:54.018998 TX Vref=28, minBit 10, minWin=25, winSum=424
3277 09:30:54.022227 TX Vref=30, minBit 11, minWin=25, winSum=423
3278 09:30:54.025694 TX Vref=32, minBit 9, minWin=25, winSum=423
3279 09:30:54.032374 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 28
3280 09:30:54.032482
3281 09:30:54.035600 Final TX Range 1 Vref 28
3282 09:30:54.035688
3283 09:30:54.035772 ==
3284 09:30:54.039048 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 09:30:54.042644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 09:30:54.042752 ==
3287 09:30:54.042852
3288 09:30:54.045746
3289 09:30:54.045831 TX Vref Scan disable
3290 09:30:54.049274 == TX Byte 0 ==
3291 09:30:54.052493 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3292 09:30:54.056008 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3293 09:30:54.059018 == TX Byte 1 ==
3294 09:30:54.062790 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3295 09:30:54.066211 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3296 09:30:54.066304
3297 09:30:54.069243 [DATLAT]
3298 09:30:54.069342 Freq=1200, CH1 RK0
3299 09:30:54.069426
3300 09:30:54.072666 DATLAT Default: 0xd
3301 09:30:54.072766 0, 0xFFFF, sum = 0
3302 09:30:54.075808 1, 0xFFFF, sum = 0
3303 09:30:54.075894 2, 0xFFFF, sum = 0
3304 09:30:54.079257 3, 0xFFFF, sum = 0
3305 09:30:54.079342 4, 0xFFFF, sum = 0
3306 09:30:54.082747 5, 0xFFFF, sum = 0
3307 09:30:54.082835 6, 0xFFFF, sum = 0
3308 09:30:54.086258 7, 0xFFFF, sum = 0
3309 09:30:54.086363 8, 0xFFFF, sum = 0
3310 09:30:54.089658 9, 0xFFFF, sum = 0
3311 09:30:54.089748 10, 0xFFFF, sum = 0
3312 09:30:54.092559 11, 0xFFFF, sum = 0
3313 09:30:54.092643 12, 0x0, sum = 1
3314 09:30:54.096024 13, 0x0, sum = 2
3315 09:30:54.096109 14, 0x0, sum = 3
3316 09:30:54.099357 15, 0x0, sum = 4
3317 09:30:54.099443 best_step = 13
3318 09:30:54.099507
3319 09:30:54.099567 ==
3320 09:30:54.102900 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 09:30:54.109385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 09:30:54.109483 ==
3323 09:30:54.109548 RX Vref Scan: 1
3324 09:30:54.109608
3325 09:30:54.112734 Set Vref Range= 32 -> 127
3326 09:30:54.112818
3327 09:30:54.116253 RX Vref 32 -> 127, step: 1
3328 09:30:54.116338
3329 09:30:54.119475 RX Delay -13 -> 252, step: 4
3330 09:30:54.119559
3331 09:30:54.123031 Set Vref, RX VrefLevel [Byte0]: 32
3332 09:30:54.123119 [Byte1]: 32
3333 09:30:54.127386
3334 09:30:54.127476 Set Vref, RX VrefLevel [Byte0]: 33
3335 09:30:54.130701 [Byte1]: 33
3336 09:30:54.135484
3337 09:30:54.135574 Set Vref, RX VrefLevel [Byte0]: 34
3338 09:30:54.138458 [Byte1]: 34
3339 09:30:54.143423
3340 09:30:54.143517 Set Vref, RX VrefLevel [Byte0]: 35
3341 09:30:54.146585 [Byte1]: 35
3342 09:30:54.151272
3343 09:30:54.151366 Set Vref, RX VrefLevel [Byte0]: 36
3344 09:30:54.154454 [Byte1]: 36
3345 09:30:54.159205
3346 09:30:54.159300 Set Vref, RX VrefLevel [Byte0]: 37
3347 09:30:54.162306 [Byte1]: 37
3348 09:30:54.167034
3349 09:30:54.167129 Set Vref, RX VrefLevel [Byte0]: 38
3350 09:30:54.170088 [Byte1]: 38
3351 09:30:54.175007
3352 09:30:54.175100 Set Vref, RX VrefLevel [Byte0]: 39
3353 09:30:54.178379 [Byte1]: 39
3354 09:30:54.182871
3355 09:30:54.182962 Set Vref, RX VrefLevel [Byte0]: 40
3356 09:30:54.185942 [Byte1]: 40
3357 09:30:54.190483
3358 09:30:54.190579 Set Vref, RX VrefLevel [Byte0]: 41
3359 09:30:54.193778 [Byte1]: 41
3360 09:30:54.198558
3361 09:30:54.198649 Set Vref, RX VrefLevel [Byte0]: 42
3362 09:30:54.202013 [Byte1]: 42
3363 09:30:54.206495
3364 09:30:54.206586 Set Vref, RX VrefLevel [Byte0]: 43
3365 09:30:54.209556 [Byte1]: 43
3366 09:30:54.214548
3367 09:30:54.214641 Set Vref, RX VrefLevel [Byte0]: 44
3368 09:30:54.217433 [Byte1]: 44
3369 09:30:54.221972
3370 09:30:54.222064 Set Vref, RX VrefLevel [Byte0]: 45
3371 09:30:54.225414 [Byte1]: 45
3372 09:30:54.229911
3373 09:30:54.230004 Set Vref, RX VrefLevel [Byte0]: 46
3374 09:30:54.233238 [Byte1]: 46
3375 09:30:54.238187
3376 09:30:54.238289 Set Vref, RX VrefLevel [Byte0]: 47
3377 09:30:54.241343 [Byte1]: 47
3378 09:30:54.245540
3379 09:30:54.245630 Set Vref, RX VrefLevel [Byte0]: 48
3380 09:30:54.248985 [Byte1]: 48
3381 09:30:54.253600
3382 09:30:54.253692 Set Vref, RX VrefLevel [Byte0]: 49
3383 09:30:54.256817 [Byte1]: 49
3384 09:30:54.261683
3385 09:30:54.261779 Set Vref, RX VrefLevel [Byte0]: 50
3386 09:30:54.264943 [Byte1]: 50
3387 09:30:54.269407
3388 09:30:54.269500 Set Vref, RX VrefLevel [Byte0]: 51
3389 09:30:54.272630 [Byte1]: 51
3390 09:30:54.277177
3391 09:30:54.277269 Set Vref, RX VrefLevel [Byte0]: 52
3392 09:30:54.283940 [Byte1]: 52
3393 09:30:54.284036
3394 09:30:54.287322 Set Vref, RX VrefLevel [Byte0]: 53
3395 09:30:54.290252 [Byte1]: 53
3396 09:30:54.290340
3397 09:30:54.293678 Set Vref, RX VrefLevel [Byte0]: 54
3398 09:30:54.296957 [Byte1]: 54
3399 09:30:54.300751
3400 09:30:54.300838 Set Vref, RX VrefLevel [Byte0]: 55
3401 09:30:54.304221 [Byte1]: 55
3402 09:30:54.308794
3403 09:30:54.308882 Set Vref, RX VrefLevel [Byte0]: 56
3404 09:30:54.312275 [Byte1]: 56
3405 09:30:54.316665
3406 09:30:54.316758 Set Vref, RX VrefLevel [Byte0]: 57
3407 09:30:54.319771 [Byte1]: 57
3408 09:30:54.324883
3409 09:30:54.324980 Set Vref, RX VrefLevel [Byte0]: 58
3410 09:30:54.327714 [Byte1]: 58
3411 09:30:54.332374
3412 09:30:54.332460 Set Vref, RX VrefLevel [Byte0]: 59
3413 09:30:54.335987 [Byte1]: 59
3414 09:30:54.340208
3415 09:30:54.340301 Set Vref, RX VrefLevel [Byte0]: 60
3416 09:30:54.343719 [Byte1]: 60
3417 09:30:54.348212
3418 09:30:54.348316 Set Vref, RX VrefLevel [Byte0]: 61
3419 09:30:54.351441 [Byte1]: 61
3420 09:30:54.356064
3421 09:30:54.356159 Set Vref, RX VrefLevel [Byte0]: 62
3422 09:30:54.359174 [Byte1]: 62
3423 09:30:54.363874
3424 09:30:54.363968 Set Vref, RX VrefLevel [Byte0]: 63
3425 09:30:54.367444 [Byte1]: 63
3426 09:30:54.371742
3427 09:30:54.371835 Set Vref, RX VrefLevel [Byte0]: 64
3428 09:30:54.375463 [Byte1]: 64
3429 09:30:54.379853
3430 09:30:54.379946 Set Vref, RX VrefLevel [Byte0]: 65
3431 09:30:54.383288 [Byte1]: 65
3432 09:30:54.387818
3433 09:30:54.387918 Set Vref, RX VrefLevel [Byte0]: 66
3434 09:30:54.390915 [Byte1]: 66
3435 09:30:54.395463
3436 09:30:54.395581 Set Vref, RX VrefLevel [Byte0]: 67
3437 09:30:54.398962 [Byte1]: 67
3438 09:30:54.403275
3439 09:30:54.403365 Final RX Vref Byte 0 = 53 to rank0
3440 09:30:54.406704 Final RX Vref Byte 1 = 53 to rank0
3441 09:30:54.410177 Final RX Vref Byte 0 = 53 to rank1
3442 09:30:54.413690 Final RX Vref Byte 1 = 53 to rank1==
3443 09:30:54.416801 Dram Type= 6, Freq= 0, CH_1, rank 0
3444 09:30:54.423326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 09:30:54.423423 ==
3446 09:30:54.423491 DQS Delay:
3447 09:30:54.423551 DQS0 = 0, DQS1 = 0
3448 09:30:54.427072 DQM Delay:
3449 09:30:54.427156 DQM0 = 119, DQM1 = 112
3450 09:30:54.430341 DQ Delay:
3451 09:30:54.433418 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3452 09:30:54.436893 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3453 09:30:54.440448 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3454 09:30:54.443712 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3455 09:30:54.443801
3456 09:30:54.443867
3457 09:30:54.450411 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3458 09:30:54.453747 CH1 RK0: MR19=404, MR18=417
3459 09:30:54.460212 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3460 09:30:54.460334
3461 09:30:54.463398 ----->DramcWriteLeveling(PI) begin...
3462 09:30:54.463535 ==
3463 09:30:54.466728 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 09:30:54.470429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 09:30:54.470518 ==
3466 09:30:54.473560 Write leveling (Byte 0): 25 => 25
3467 09:30:54.477168 Write leveling (Byte 1): 28 => 28
3468 09:30:54.480444 DramcWriteLeveling(PI) end<-----
3469 09:30:54.480532
3470 09:30:54.480597 ==
3471 09:30:54.483588 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 09:30:54.487045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 09:30:54.490383 ==
3474 09:30:54.490478 [Gating] SW mode calibration
3475 09:30:54.500373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3476 09:30:54.503452 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3477 09:30:54.506961 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 09:30:54.513967 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 09:30:54.516859 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 09:30:54.520474 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 09:30:54.527017 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 09:30:54.530554 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3483 09:30:54.534083 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
3484 09:30:54.540543 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 1)
3485 09:30:54.543610 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 09:30:54.547008 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 09:30:54.550923 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 09:30:54.557253 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 09:30:54.560615 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 09:30:54.563753 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3491 09:30:54.570260 1 0 24 | B1->B0 | 3c3c 2828 | 0 0 | (0 0) (1 1)
3492 09:30:54.573728 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3493 09:30:54.577430 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 09:30:54.584090 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 09:30:54.587225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 09:30:54.590933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 09:30:54.597256 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 09:30:54.600714 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3499 09:30:54.603915 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3500 09:30:54.610833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3501 09:30:54.614085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 09:30:54.617105 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 09:30:54.624101 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 09:30:54.627490 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 09:30:54.630574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 09:30:54.637520 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 09:30:54.640568 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 09:30:54.643551 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 09:30:54.650610 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 09:30:54.653710 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 09:30:54.657184 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 09:30:54.660235 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 09:30:54.667259 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 09:30:54.670489 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:30:54.673735 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3516 09:30:54.680413 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3517 09:30:54.683642 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 09:30:54.686845 Total UI for P1: 0, mck2ui 16
3519 09:30:54.690197 best dqsien dly found for B0: ( 1, 3, 26)
3520 09:30:54.693921 Total UI for P1: 0, mck2ui 16
3521 09:30:54.697098 best dqsien dly found for B1: ( 1, 3, 26)
3522 09:30:54.700366 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3523 09:30:54.703576 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3524 09:30:54.703660
3525 09:30:54.706971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3526 09:30:54.710537 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3527 09:30:54.713919 [Gating] SW calibration Done
3528 09:30:54.714002 ==
3529 09:30:54.716784 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 09:30:54.720226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 09:30:54.723651 ==
3532 09:30:54.723734 RX Vref Scan: 0
3533 09:30:54.723799
3534 09:30:54.727214 RX Vref 0 -> 0, step: 1
3535 09:30:54.727297
3536 09:30:54.730114 RX Delay -40 -> 252, step: 8
3537 09:30:54.733825 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3538 09:30:54.737279 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3539 09:30:54.740387 iDelay=200, Bit 2, Center 103 (40 ~ 167) 128
3540 09:30:54.743492 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3541 09:30:54.750422 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3542 09:30:54.753779 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3543 09:30:54.757140 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3544 09:30:54.760507 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3545 09:30:54.763601 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3546 09:30:54.767117 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3547 09:30:54.773716 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3548 09:30:54.777049 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3549 09:30:54.780454 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3550 09:30:54.783667 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3551 09:30:54.790278 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3552 09:30:54.793326 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3553 09:30:54.793407 ==
3554 09:30:54.797134 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 09:30:54.800339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 09:30:54.800420 ==
3557 09:30:54.800483 DQS Delay:
3558 09:30:54.803540 DQS0 = 0, DQS1 = 0
3559 09:30:54.803621 DQM Delay:
3560 09:30:54.806927 DQM0 = 119, DQM1 = 112
3561 09:30:54.807008 DQ Delay:
3562 09:30:54.810060 DQ0 =123, DQ1 =115, DQ2 =103, DQ3 =123
3563 09:30:54.813528 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3564 09:30:54.817046 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3565 09:30:54.819901 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3566 09:30:54.823237
3567 09:30:54.823317
3568 09:30:54.823380 ==
3569 09:30:54.826701 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 09:30:54.830254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 09:30:54.830336 ==
3572 09:30:54.830400
3573 09:30:54.830458
3574 09:30:54.833415 TX Vref Scan disable
3575 09:30:54.833495 == TX Byte 0 ==
3576 09:30:54.839971 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 09:30:54.843476 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 09:30:54.843556 == TX Byte 1 ==
3579 09:30:54.850029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3580 09:30:54.853577 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3581 09:30:54.853657 ==
3582 09:30:54.856588 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 09:30:54.860147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 09:30:54.860228 ==
3585 09:30:54.872250 TX Vref=22, minBit 3, minWin=25, winSum=417
3586 09:30:54.875826 TX Vref=24, minBit 11, minWin=25, winSum=424
3587 09:30:54.879187 TX Vref=26, minBit 9, minWin=25, winSum=420
3588 09:30:54.882468 TX Vref=28, minBit 1, minWin=26, winSum=429
3589 09:30:54.885732 TX Vref=30, minBit 8, minWin=26, winSum=431
3590 09:30:54.892261 TX Vref=32, minBit 9, minWin=25, winSum=424
3591 09:30:54.895904 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3592 09:30:54.895990
3593 09:30:54.899171 Final TX Range 1 Vref 30
3594 09:30:54.899256
3595 09:30:54.899339 ==
3596 09:30:54.902468 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 09:30:54.905769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 09:30:54.905854 ==
3599 09:30:54.909066
3600 09:30:54.909150
3601 09:30:54.909233 TX Vref Scan disable
3602 09:30:54.912066 == TX Byte 0 ==
3603 09:30:54.915365 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3604 09:30:54.922272 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3605 09:30:54.922378 == TX Byte 1 ==
3606 09:30:54.925545 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3607 09:30:54.928910 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3608 09:30:54.932518
3609 09:30:54.932603 [DATLAT]
3610 09:30:54.932686 Freq=1200, CH1 RK1
3611 09:30:54.932764
3612 09:30:54.935471 DATLAT Default: 0xd
3613 09:30:54.935554 0, 0xFFFF, sum = 0
3614 09:30:54.938943 1, 0xFFFF, sum = 0
3615 09:30:54.939028 2, 0xFFFF, sum = 0
3616 09:30:54.942068 3, 0xFFFF, sum = 0
3617 09:30:54.942152 4, 0xFFFF, sum = 0
3618 09:30:54.945499 5, 0xFFFF, sum = 0
3619 09:30:54.948625 6, 0xFFFF, sum = 0
3620 09:30:54.948709 7, 0xFFFF, sum = 0
3621 09:30:54.952085 8, 0xFFFF, sum = 0
3622 09:30:54.952170 9, 0xFFFF, sum = 0
3623 09:30:54.955227 10, 0xFFFF, sum = 0
3624 09:30:54.955311 11, 0xFFFF, sum = 0
3625 09:30:54.958660 12, 0x0, sum = 1
3626 09:30:54.958745 13, 0x0, sum = 2
3627 09:30:54.962202 14, 0x0, sum = 3
3628 09:30:54.962287 15, 0x0, sum = 4
3629 09:30:54.962370 best_step = 13
3630 09:30:54.965442
3631 09:30:54.965525 ==
3632 09:30:54.968918 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 09:30:54.972456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 09:30:54.972540 ==
3635 09:30:54.972623 RX Vref Scan: 0
3636 09:30:54.972700
3637 09:30:54.975452 RX Vref 0 -> 0, step: 1
3638 09:30:54.975536
3639 09:30:54.978918 RX Delay -13 -> 252, step: 4
3640 09:30:54.981925 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3641 09:30:54.988610 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3642 09:30:54.992014 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3643 09:30:54.995455 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3644 09:30:54.998718 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3645 09:30:55.002124 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3646 09:30:55.009158 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3647 09:30:55.012216 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3648 09:30:55.015317 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3649 09:30:55.018628 iDelay=191, Bit 9, Center 100 (35 ~ 166) 132
3650 09:30:55.022307 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3651 09:30:55.025631 iDelay=191, Bit 11, Center 108 (43 ~ 174) 132
3652 09:30:55.031892 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3653 09:30:55.035446 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3654 09:30:55.039055 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3655 09:30:55.042022 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3656 09:30:55.042111 ==
3657 09:30:55.045459 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 09:30:55.051913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 09:30:55.052002 ==
3660 09:30:55.052086 DQS Delay:
3661 09:30:55.055421 DQS0 = 0, DQS1 = 0
3662 09:30:55.055504 DQM Delay:
3663 09:30:55.058553 DQM0 = 119, DQM1 = 113
3664 09:30:55.058638 DQ Delay:
3665 09:30:55.061813 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3666 09:30:55.065346 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3667 09:30:55.068701 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =108
3668 09:30:55.072152 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3669 09:30:55.072237
3670 09:30:55.072320
3671 09:30:55.081778 [DQSOSCAuto] RK1, (LSB)MR18= 0xbee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3672 09:30:55.081863 CH1 RK1: MR19=403, MR18=BEE
3673 09:30:55.088727 CH1_RK1: MR19=0x403, MR18=0xBEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3674 09:30:55.091683 [RxdqsGatingPostProcess] freq 1200
3675 09:30:55.098528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3676 09:30:55.101700 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 09:30:55.105062 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 09:30:55.108521 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 09:30:55.112020 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 09:30:55.115318 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 09:30:55.115399 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 09:30:55.118457 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 09:30:55.121576 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 09:30:55.124825 Pre-setting of DQS Precalculation
3685 09:30:55.131714 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3686 09:30:55.138090 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3687 09:30:55.144825 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3688 09:30:55.144907
3689 09:30:55.145004
3690 09:30:55.148265 [Calibration Summary] 2400 Mbps
3691 09:30:55.151583 CH 0, Rank 0
3692 09:30:55.151663 SW Impedance : PASS
3693 09:30:55.155173 DUTY Scan : NO K
3694 09:30:55.155254 ZQ Calibration : PASS
3695 09:30:55.158064 Jitter Meter : NO K
3696 09:30:55.161513 CBT Training : PASS
3697 09:30:55.161596 Write leveling : PASS
3698 09:30:55.164920 RX DQS gating : PASS
3699 09:30:55.168366 RX DQ/DQS(RDDQC) : PASS
3700 09:30:55.168446 TX DQ/DQS : PASS
3701 09:30:55.171467 RX DATLAT : PASS
3702 09:30:55.174747 RX DQ/DQS(Engine): PASS
3703 09:30:55.174828 TX OE : NO K
3704 09:30:55.178172 All Pass.
3705 09:30:55.178253
3706 09:30:55.178316 CH 0, Rank 1
3707 09:30:55.181321 SW Impedance : PASS
3708 09:30:55.181402 DUTY Scan : NO K
3709 09:30:55.184790 ZQ Calibration : PASS
3710 09:30:55.188250 Jitter Meter : NO K
3711 09:30:55.188331 CBT Training : PASS
3712 09:30:55.191272 Write leveling : PASS
3713 09:30:55.194893 RX DQS gating : PASS
3714 09:30:55.195009 RX DQ/DQS(RDDQC) : PASS
3715 09:30:55.198143 TX DQ/DQS : PASS
3716 09:30:55.198230 RX DATLAT : PASS
3717 09:30:55.201282 RX DQ/DQS(Engine): PASS
3718 09:30:55.205078 TX OE : NO K
3719 09:30:55.205161 All Pass.
3720 09:30:55.205226
3721 09:30:55.205286 CH 1, Rank 0
3722 09:30:55.207985 SW Impedance : PASS
3723 09:30:55.211400 DUTY Scan : NO K
3724 09:30:55.211484 ZQ Calibration : PASS
3725 09:30:55.214587 Jitter Meter : NO K
3726 09:30:55.217845 CBT Training : PASS
3727 09:30:55.217936 Write leveling : PASS
3728 09:30:55.221184 RX DQS gating : PASS
3729 09:30:55.224697 RX DQ/DQS(RDDQC) : PASS
3730 09:30:55.224779 TX DQ/DQS : PASS
3731 09:30:55.228105 RX DATLAT : PASS
3732 09:30:55.231293 RX DQ/DQS(Engine): PASS
3733 09:30:55.231376 TX OE : NO K
3734 09:30:55.234490 All Pass.
3735 09:30:55.234573
3736 09:30:55.234638 CH 1, Rank 1
3737 09:30:55.237960 SW Impedance : PASS
3738 09:30:55.238042 DUTY Scan : NO K
3739 09:30:55.241277 ZQ Calibration : PASS
3740 09:30:55.241359 Jitter Meter : NO K
3741 09:30:55.244877 CBT Training : PASS
3742 09:30:55.247936 Write leveling : PASS
3743 09:30:55.248030 RX DQS gating : PASS
3744 09:30:55.251461 RX DQ/DQS(RDDQC) : PASS
3745 09:30:55.254992 TX DQ/DQS : PASS
3746 09:30:55.255076 RX DATLAT : PASS
3747 09:30:55.257904 RX DQ/DQS(Engine): PASS
3748 09:30:55.261416 TX OE : NO K
3749 09:30:55.261502 All Pass.
3750 09:30:55.261586
3751 09:30:55.264863 DramC Write-DBI off
3752 09:30:55.264993 PER_BANK_REFRESH: Hybrid Mode
3753 09:30:55.267902 TX_TRACKING: ON
3754 09:30:55.274466 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3755 09:30:55.281243 [FAST_K] Save calibration result to emmc
3756 09:30:55.284696 dramc_set_vcore_voltage set vcore to 650000
3757 09:30:55.284780 Read voltage for 600, 5
3758 09:30:55.287737 Vio18 = 0
3759 09:30:55.287860 Vcore = 650000
3760 09:30:55.287930 Vdram = 0
3761 09:30:55.291298 Vddq = 0
3762 09:30:55.291381 Vmddr = 0
3763 09:30:55.294764 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3764 09:30:55.301191 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3765 09:30:55.304151 MEM_TYPE=3, freq_sel=19
3766 09:30:55.307642 sv_algorithm_assistance_LP4_1600
3767 09:30:55.310791 ============ PULL DRAM RESETB DOWN ============
3768 09:30:55.314137 ========== PULL DRAM RESETB DOWN end =========
3769 09:30:55.321263 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3770 09:30:55.324481 ===================================
3771 09:30:55.324566 LPDDR4 DRAM CONFIGURATION
3772 09:30:55.327626 ===================================
3773 09:30:55.330917 EX_ROW_EN[0] = 0x0
3774 09:30:55.331003 EX_ROW_EN[1] = 0x0
3775 09:30:55.334216 LP4Y_EN = 0x0
3776 09:30:55.334303 WORK_FSP = 0x0
3777 09:30:55.337455 WL = 0x2
3778 09:30:55.341082 RL = 0x2
3779 09:30:55.341167 BL = 0x2
3780 09:30:55.344297 RPST = 0x0
3781 09:30:55.344381 RD_PRE = 0x0
3782 09:30:55.347647 WR_PRE = 0x1
3783 09:30:55.347730 WR_PST = 0x0
3784 09:30:55.351112 DBI_WR = 0x0
3785 09:30:55.351194 DBI_RD = 0x0
3786 09:30:55.354142 OTF = 0x1
3787 09:30:55.357672 ===================================
3788 09:30:55.360613 ===================================
3789 09:30:55.360697 ANA top config
3790 09:30:55.364304 ===================================
3791 09:30:55.367170 DLL_ASYNC_EN = 0
3792 09:30:55.370759 ALL_SLAVE_EN = 1
3793 09:30:55.370844 NEW_RANK_MODE = 1
3794 09:30:55.373674 DLL_IDLE_MODE = 1
3795 09:30:55.377142 LP45_APHY_COMB_EN = 1
3796 09:30:55.380748 TX_ODT_DIS = 1
3797 09:30:55.384033 NEW_8X_MODE = 1
3798 09:30:55.387035 ===================================
3799 09:30:55.390572 ===================================
3800 09:30:55.390659 data_rate = 1200
3801 09:30:55.393940 CKR = 1
3802 09:30:55.396933 DQ_P2S_RATIO = 8
3803 09:30:55.400447 ===================================
3804 09:30:55.403925 CA_P2S_RATIO = 8
3805 09:30:55.406937 DQ_CA_OPEN = 0
3806 09:30:55.410342 DQ_SEMI_OPEN = 0
3807 09:30:55.410426 CA_SEMI_OPEN = 0
3808 09:30:55.413972 CA_FULL_RATE = 0
3809 09:30:55.417027 DQ_CKDIV4_EN = 1
3810 09:30:55.420367 CA_CKDIV4_EN = 1
3811 09:30:55.423944 CA_PREDIV_EN = 0
3812 09:30:55.427107 PH8_DLY = 0
3813 09:30:55.427192 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3814 09:30:55.430502 DQ_AAMCK_DIV = 4
3815 09:30:55.433570 CA_AAMCK_DIV = 4
3816 09:30:55.436923 CA_ADMCK_DIV = 4
3817 09:30:55.440024 DQ_TRACK_CA_EN = 0
3818 09:30:55.443567 CA_PICK = 600
3819 09:30:55.443663 CA_MCKIO = 600
3820 09:30:55.446905 MCKIO_SEMI = 0
3821 09:30:55.450485 PLL_FREQ = 2288
3822 09:30:55.453458 DQ_UI_PI_RATIO = 32
3823 09:30:55.456819 CA_UI_PI_RATIO = 0
3824 09:30:55.459977 ===================================
3825 09:30:55.463414 ===================================
3826 09:30:55.466946 memory_type:LPDDR4
3827 09:30:55.467044 GP_NUM : 10
3828 09:30:55.469977 SRAM_EN : 1
3829 09:30:55.470067 MD32_EN : 0
3830 09:30:55.473547 ===================================
3831 09:30:55.476457 [ANA_INIT] >>>>>>>>>>>>>>
3832 09:30:55.479990 <<<<<< [CONFIGURE PHASE]: ANA_TX
3833 09:30:55.483034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3834 09:30:55.486501 ===================================
3835 09:30:55.489897 data_rate = 1200,PCW = 0X5800
3836 09:30:55.493331 ===================================
3837 09:30:55.496388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3838 09:30:55.502976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 09:30:55.506438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 09:30:55.513089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3841 09:30:55.516393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3842 09:30:55.519874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3843 09:30:55.519974 [ANA_INIT] flow start
3844 09:30:55.522780 [ANA_INIT] PLL >>>>>>>>
3845 09:30:55.526081 [ANA_INIT] PLL <<<<<<<<
3846 09:30:55.526164 [ANA_INIT] MIDPI >>>>>>>>
3847 09:30:55.529620 [ANA_INIT] MIDPI <<<<<<<<
3848 09:30:55.532791 [ANA_INIT] DLL >>>>>>>>
3849 09:30:55.532874 [ANA_INIT] flow end
3850 09:30:55.539293 ============ LP4 DIFF to SE enter ============
3851 09:30:55.542623 ============ LP4 DIFF to SE exit ============
3852 09:30:55.545856 [ANA_INIT] <<<<<<<<<<<<<
3853 09:30:55.549504 [Flow] Enable top DCM control >>>>>
3854 09:30:55.552705 [Flow] Enable top DCM control <<<<<
3855 09:30:55.555847 Enable DLL master slave shuffle
3856 09:30:55.559064 ==============================================================
3857 09:30:55.562676 Gating Mode config
3858 09:30:55.565675 ==============================================================
3859 09:30:55.569295 Config description:
3860 09:30:55.579138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3861 09:30:55.585711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3862 09:30:55.589174 SELPH_MODE 0: By rank 1: By Phase
3863 09:30:55.595715 ==============================================================
3864 09:30:55.599208 GAT_TRACK_EN = 1
3865 09:30:55.602254 RX_GATING_MODE = 2
3866 09:30:55.605688 RX_GATING_TRACK_MODE = 2
3867 09:30:55.609211 SELPH_MODE = 1
3868 09:30:55.612706 PICG_EARLY_EN = 1
3869 09:30:55.612794 VALID_LAT_VALUE = 1
3870 09:30:55.618981 ==============================================================
3871 09:30:55.622350 Enter into Gating configuration >>>>
3872 09:30:55.625766 Exit from Gating configuration <<<<
3873 09:30:55.628828 Enter into DVFS_PRE_config >>>>>
3874 09:30:55.638792 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3875 09:30:55.642218 Exit from DVFS_PRE_config <<<<<
3876 09:30:55.646008 Enter into PICG configuration >>>>
3877 09:30:55.649110 Exit from PICG configuration <<<<
3878 09:30:55.652154 [RX_INPUT] configuration >>>>>
3879 09:30:55.655646 [RX_INPUT] configuration <<<<<
3880 09:30:55.658854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3881 09:30:55.665453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3882 09:30:55.672276 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 09:30:55.678837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 09:30:55.685437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 09:30:55.692014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 09:30:55.695238 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3887 09:30:55.698589 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3888 09:30:55.702107 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3889 09:30:55.705144 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3890 09:30:55.711643 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3891 09:30:55.715196 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 09:30:55.718591 ===================================
3893 09:30:55.721681 LPDDR4 DRAM CONFIGURATION
3894 09:30:55.725052 ===================================
3895 09:30:55.725134 EX_ROW_EN[0] = 0x0
3896 09:30:55.728559 EX_ROW_EN[1] = 0x0
3897 09:30:55.728641 LP4Y_EN = 0x0
3898 09:30:55.731976 WORK_FSP = 0x0
3899 09:30:55.732058 WL = 0x2
3900 09:30:55.734989 RL = 0x2
3901 09:30:55.738447 BL = 0x2
3902 09:30:55.738528 RPST = 0x0
3903 09:30:55.742006 RD_PRE = 0x0
3904 09:30:55.742087 WR_PRE = 0x1
3905 09:30:55.745169 WR_PST = 0x0
3906 09:30:55.745251 DBI_WR = 0x0
3907 09:30:55.748293 DBI_RD = 0x0
3908 09:30:55.748374 OTF = 0x1
3909 09:30:55.751661 ===================================
3910 09:30:55.754971 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3911 09:30:55.761771 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3912 09:30:55.765024 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 09:30:55.768184 ===================================
3914 09:30:55.771750 LPDDR4 DRAM CONFIGURATION
3915 09:30:55.775088 ===================================
3916 09:30:55.775170 EX_ROW_EN[0] = 0x10
3917 09:30:55.778208 EX_ROW_EN[1] = 0x0
3918 09:30:55.778290 LP4Y_EN = 0x0
3919 09:30:55.781820 WORK_FSP = 0x0
3920 09:30:55.781902 WL = 0x2
3921 09:30:55.784862 RL = 0x2
3922 09:30:55.784981 BL = 0x2
3923 09:30:55.788491 RPST = 0x0
3924 09:30:55.788573 RD_PRE = 0x0
3925 09:30:55.791999 WR_PRE = 0x1
3926 09:30:55.792096 WR_PST = 0x0
3927 09:30:55.795027 DBI_WR = 0x0
3928 09:30:55.798408 DBI_RD = 0x0
3929 09:30:55.798488 OTF = 0x1
3930 09:30:55.801977 ===================================
3931 09:30:55.808269 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3932 09:30:55.811866 nWR fixed to 30
3933 09:30:55.814980 [ModeRegInit_LP4] CH0 RK0
3934 09:30:55.815062 [ModeRegInit_LP4] CH0 RK1
3935 09:30:55.818184 [ModeRegInit_LP4] CH1 RK0
3936 09:30:55.821727 [ModeRegInit_LP4] CH1 RK1
3937 09:30:55.821807 match AC timing 17
3938 09:30:55.828221 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3939 09:30:55.831810 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3940 09:30:55.835312 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3941 09:30:55.841969 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3942 09:30:55.844920 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3943 09:30:55.845028 ==
3944 09:30:55.848458 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 09:30:55.851545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 09:30:55.851626 ==
3947 09:30:55.858261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 09:30:55.864783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3949 09:30:55.868449 [CA 0] Center 36 (5~67) winsize 63
3950 09:30:55.871650 [CA 1] Center 36 (6~67) winsize 62
3951 09:30:55.875157 [CA 2] Center 34 (4~65) winsize 62
3952 09:30:55.878335 [CA 3] Center 34 (3~65) winsize 63
3953 09:30:55.881643 [CA 4] Center 33 (3~64) winsize 62
3954 09:30:55.884822 [CA 5] Center 33 (3~64) winsize 62
3955 09:30:55.884904
3956 09:30:55.888099 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3957 09:30:55.888181
3958 09:30:55.891694 [CATrainingPosCal] consider 1 rank data
3959 09:30:55.894682 u2DelayCellTimex100 = 270/100 ps
3960 09:30:55.898219 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3961 09:30:55.901616 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3962 09:30:55.904957 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 09:30:55.908461 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3964 09:30:55.911501 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 09:30:55.915020 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 09:30:55.918036
3967 09:30:55.921401 CA PerBit enable=1, Macro0, CA PI delay=33
3968 09:30:55.921483
3969 09:30:55.924413 [CBTSetCACLKResult] CA Dly = 33
3970 09:30:55.924495 CS Dly: 4 (0~35)
3971 09:30:55.924558 ==
3972 09:30:55.927858 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 09:30:55.931414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 09:30:55.931498 ==
3975 09:30:55.937974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 09:30:55.944484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3977 09:30:55.947877 [CA 0] Center 36 (6~67) winsize 62
3978 09:30:55.951234 [CA 1] Center 36 (6~67) winsize 62
3979 09:30:55.954622 [CA 2] Center 34 (4~65) winsize 62
3980 09:30:55.958105 [CA 3] Center 34 (4~65) winsize 62
3981 09:30:55.961041 [CA 4] Center 34 (3~65) winsize 63
3982 09:30:55.964485 [CA 5] Center 33 (3~64) winsize 62
3983 09:30:55.964569
3984 09:30:55.968155 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3985 09:30:55.968238
3986 09:30:55.971385 [CATrainingPosCal] consider 2 rank data
3987 09:30:55.974541 u2DelayCellTimex100 = 270/100 ps
3988 09:30:55.977700 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3989 09:30:55.981365 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3990 09:30:55.984473 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 09:30:55.987878 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 09:30:55.991361 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3993 09:30:55.997654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 09:30:55.997738
3995 09:30:56.001207 CA PerBit enable=1, Macro0, CA PI delay=33
3996 09:30:56.001288
3997 09:30:56.004228 [CBTSetCACLKResult] CA Dly = 33
3998 09:30:56.004310 CS Dly: 5 (0~37)
3999 09:30:56.004373
4000 09:30:56.007978 ----->DramcWriteLeveling(PI) begin...
4001 09:30:56.008061 ==
4002 09:30:56.011101 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 09:30:56.018132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 09:30:56.018215 ==
4005 09:30:56.021217 Write leveling (Byte 0): 33 => 33
4006 09:30:56.021304 Write leveling (Byte 1): 31 => 31
4007 09:30:56.024438 DramcWriteLeveling(PI) end<-----
4008 09:30:56.024518
4009 09:30:56.024581 ==
4010 09:30:56.027563 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 09:30:56.033996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 09:30:56.034079 ==
4013 09:30:56.037675 [Gating] SW mode calibration
4014 09:30:56.044176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4015 09:30:56.047720 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4016 09:30:56.054202 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 09:30:56.057440 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 09:30:56.060976 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 09:30:56.067468 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (1 0) (0 0)
4020 09:30:56.070725 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4021 09:30:56.073819 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 09:30:56.080533 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 09:30:56.083809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 09:30:56.087353 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 09:30:56.093916 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 09:30:56.097126 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4027 09:30:56.100789 0 10 12 | B1->B0 | 2727 3838 | 0 1 | (1 1) (0 0)
4028 09:30:56.107254 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4029 09:30:56.110665 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 09:30:56.113548 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 09:30:56.120480 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 09:30:56.124067 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 09:30:56.126984 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 09:30:56.130364 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 09:30:56.137035 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4036 09:30:56.140487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4037 09:30:56.143579 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 09:30:56.150493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 09:30:56.154658 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 09:30:56.157086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 09:30:56.163950 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 09:30:56.167000 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 09:30:56.170431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 09:30:56.177252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 09:30:56.180610 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 09:30:56.183673 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:30:56.190099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:30:56.193497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:30:56.196903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:30:56.203557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:30:56.207011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4052 09:30:56.210422 Total UI for P1: 0, mck2ui 16
4053 09:30:56.213550 best dqsien dly found for B0: ( 0, 13, 10)
4054 09:30:56.216832 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4055 09:30:56.223472 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 09:30:56.223563 Total UI for P1: 0, mck2ui 16
4057 09:30:56.227012 best dqsien dly found for B1: ( 0, 13, 14)
4058 09:30:56.233414 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4059 09:30:56.236866 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4060 09:30:56.236954
4061 09:30:56.240359 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4062 09:30:56.243481 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4063 09:30:56.247066 [Gating] SW calibration Done
4064 09:30:56.247149 ==
4065 09:30:56.250541 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 09:30:56.253584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 09:30:56.253667 ==
4068 09:30:56.257069 RX Vref Scan: 0
4069 09:30:56.257153
4070 09:30:56.257217 RX Vref 0 -> 0, step: 1
4071 09:30:56.257276
4072 09:30:56.260669 RX Delay -230 -> 252, step: 16
4073 09:30:56.263492 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4074 09:30:56.270451 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4075 09:30:56.273401 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4076 09:30:56.276909 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4077 09:30:56.280346 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4078 09:30:56.286684 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4079 09:30:56.290354 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4080 09:30:56.293282 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4081 09:30:56.296683 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4082 09:30:56.299937 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4083 09:30:56.306413 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4084 09:30:56.309895 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4085 09:30:56.313142 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4086 09:30:56.316486 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4087 09:30:56.323037 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4088 09:30:56.326522 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4089 09:30:56.326611 ==
4090 09:30:56.330119 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 09:30:56.332924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 09:30:56.333045 ==
4093 09:30:56.336584 DQS Delay:
4094 09:30:56.336668 DQS0 = 0, DQS1 = 0
4095 09:30:56.336732 DQM Delay:
4096 09:30:56.339897 DQM0 = 52, DQM1 = 40
4097 09:30:56.339980 DQ Delay:
4098 09:30:56.342992 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4099 09:30:56.346471 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4100 09:30:56.350083 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4101 09:30:56.353002 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4102 09:30:56.353085
4103 09:30:56.353149
4104 09:30:56.353208 ==
4105 09:30:56.356418 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 09:30:56.363459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 09:30:56.363545 ==
4108 09:30:56.363610
4109 09:30:56.363669
4110 09:30:56.363726 TX Vref Scan disable
4111 09:30:56.366982 == TX Byte 0 ==
4112 09:30:56.369813 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4113 09:30:56.373356 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4114 09:30:56.376845 == TX Byte 1 ==
4115 09:30:56.380012 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4116 09:30:56.386790 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4117 09:30:56.386878 ==
4118 09:30:56.390210 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 09:30:56.393162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 09:30:56.393246 ==
4121 09:30:56.393311
4122 09:30:56.393370
4123 09:30:56.396479 TX Vref Scan disable
4124 09:30:56.400123 == TX Byte 0 ==
4125 09:30:56.403315 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4126 09:30:56.407159 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4127 09:30:56.407242 == TX Byte 1 ==
4128 09:30:56.413217 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4129 09:30:56.416831 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4130 09:30:56.416915
4131 09:30:56.417021 [DATLAT]
4132 09:30:56.419941 Freq=600, CH0 RK0
4133 09:30:56.420024
4134 09:30:56.420089 DATLAT Default: 0x9
4135 09:30:56.423487 0, 0xFFFF, sum = 0
4136 09:30:56.423572 1, 0xFFFF, sum = 0
4137 09:30:56.426461 2, 0xFFFF, sum = 0
4138 09:30:56.429967 3, 0xFFFF, sum = 0
4139 09:30:56.430052 4, 0xFFFF, sum = 0
4140 09:30:56.433422 5, 0xFFFF, sum = 0
4141 09:30:56.433507 6, 0xFFFF, sum = 0
4142 09:30:56.436853 7, 0xFFFF, sum = 0
4143 09:30:56.436976 8, 0x0, sum = 1
4144 09:30:56.437044 9, 0x0, sum = 2
4145 09:30:56.439993 10, 0x0, sum = 3
4146 09:30:56.440077 11, 0x0, sum = 4
4147 09:30:56.443535 best_step = 9
4148 09:30:56.443616
4149 09:30:56.443681 ==
4150 09:30:56.446458 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 09:30:56.449552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 09:30:56.449636 ==
4153 09:30:56.452910 RX Vref Scan: 1
4154 09:30:56.453065
4155 09:30:56.453165 RX Vref 0 -> 0, step: 1
4156 09:30:56.453233
4157 09:30:56.456585 RX Delay -179 -> 252, step: 8
4158 09:30:56.456668
4159 09:30:56.459600 Set Vref, RX VrefLevel [Byte0]: 58
4160 09:30:56.463159 [Byte1]: 49
4161 09:30:56.467328
4162 09:30:56.467410 Final RX Vref Byte 0 = 58 to rank0
4163 09:30:56.470781 Final RX Vref Byte 1 = 49 to rank0
4164 09:30:56.473698 Final RX Vref Byte 0 = 58 to rank1
4165 09:30:56.477229 Final RX Vref Byte 1 = 49 to rank1==
4166 09:30:56.480669 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 09:30:56.487206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 09:30:56.487294 ==
4169 09:30:56.487360 DQS Delay:
4170 09:30:56.487420 DQS0 = 0, DQS1 = 0
4171 09:30:56.490465 DQM Delay:
4172 09:30:56.490553 DQM0 = 50, DQM1 = 37
4173 09:30:56.493780 DQ Delay:
4174 09:30:56.496697 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4175 09:30:56.500312 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4176 09:30:56.503863 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4177 09:30:56.507038 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4178 09:30:56.507123
4179 09:30:56.507188
4180 09:30:56.513672 [DQSOSCAuto] RK0, (LSB)MR18= 0x615c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4181 09:30:56.516920 CH0 RK0: MR19=808, MR18=615C
4182 09:30:56.523653 CH0_RK0: MR19=0x808, MR18=0x615C, DQSOSC=391, MR23=63, INC=171, DEC=114
4183 09:30:56.523747
4184 09:30:56.527142 ----->DramcWriteLeveling(PI) begin...
4185 09:30:56.527226 ==
4186 09:30:56.530226 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 09:30:56.533828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 09:30:56.533914 ==
4189 09:30:56.536832 Write leveling (Byte 0): 34 => 34
4190 09:30:56.540417 Write leveling (Byte 1): 29 => 29
4191 09:30:56.543448 DramcWriteLeveling(PI) end<-----
4192 09:30:56.543532
4193 09:30:56.543597 ==
4194 09:30:56.546934 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 09:30:56.550561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 09:30:56.550646 ==
4197 09:30:56.553467 [Gating] SW mode calibration
4198 09:30:56.559834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4199 09:30:56.566776 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4200 09:30:56.570030 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 09:30:56.576869 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 09:30:56.580264 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 09:30:56.583219 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
4204 09:30:56.586518 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4205 09:30:56.593256 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 09:30:56.596457 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 09:30:56.599867 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 09:30:56.606423 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 09:30:56.610314 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 09:30:56.613183 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 09:30:56.619907 0 10 12 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
4212 09:30:56.623254 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 09:30:56.626702 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 09:30:56.633306 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 09:30:56.636751 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 09:30:56.640003 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 09:30:56.646471 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 09:30:56.650285 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 09:30:56.653276 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 09:30:56.659863 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4221 09:30:56.663656 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 09:30:56.666834 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 09:30:56.673081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 09:30:56.676541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 09:30:56.679997 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 09:30:56.686490 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 09:30:56.690031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 09:30:56.693475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 09:30:56.696433 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 09:30:56.703047 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 09:30:56.706604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 09:30:56.710033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:30:56.716424 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:30:56.719962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:30:56.722876 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4236 09:30:56.726563 Total UI for P1: 0, mck2ui 16
4237 09:30:56.729905 best dqsien dly found for B1: ( 0, 13, 10)
4238 09:30:56.736507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 09:30:56.736600 Total UI for P1: 0, mck2ui 16
4240 09:30:56.743086 best dqsien dly found for B0: ( 0, 13, 12)
4241 09:30:56.746343 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4242 09:30:56.749786 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4243 09:30:56.749870
4244 09:30:56.753153 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4245 09:30:56.756146 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4246 09:30:56.759577 [Gating] SW calibration Done
4247 09:30:56.759659 ==
4248 09:30:56.763149 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 09:30:56.766409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 09:30:56.766505 ==
4251 09:30:56.769811 RX Vref Scan: 0
4252 09:30:56.769899
4253 09:30:56.769964 RX Vref 0 -> 0, step: 1
4254 09:30:56.770025
4255 09:30:56.772824 RX Delay -230 -> 252, step: 16
4256 09:30:56.779553 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4257 09:30:56.782864 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4258 09:30:56.786243 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4259 09:30:56.789771 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4260 09:30:56.792740 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4261 09:30:56.799298 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4262 09:30:56.802693 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4263 09:30:56.806112 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4264 09:30:56.809594 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4265 09:30:56.816033 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4266 09:30:56.819180 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4267 09:30:56.822532 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4268 09:30:56.826204 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4269 09:30:56.832725 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4270 09:30:56.836074 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4271 09:30:56.839179 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4272 09:30:56.839262 ==
4273 09:30:56.843013 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 09:30:56.846187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 09:30:56.846275 ==
4276 09:30:56.849275 DQS Delay:
4277 09:30:56.849361 DQS0 = 0, DQS1 = 0
4278 09:30:56.852961 DQM Delay:
4279 09:30:56.853067 DQM0 = 49, DQM1 = 41
4280 09:30:56.853131 DQ Delay:
4281 09:30:56.856198 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4282 09:30:56.859249 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4283 09:30:56.862623 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4284 09:30:56.866079 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4285 09:30:56.866186
4286 09:30:56.866293
4287 09:30:56.869368 ==
4288 09:30:56.869443 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 09:30:56.875910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 09:30:56.875995 ==
4291 09:30:56.876059
4292 09:30:56.876125
4293 09:30:56.879563 TX Vref Scan disable
4294 09:30:56.879672 == TX Byte 0 ==
4295 09:30:56.882522 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4296 09:30:56.889214 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4297 09:30:56.889327 == TX Byte 1 ==
4298 09:30:56.892638 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4299 09:30:56.899065 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4300 09:30:56.899168 ==
4301 09:30:56.902530 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 09:30:56.906213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 09:30:56.906292 ==
4304 09:30:56.906366
4305 09:30:56.906426
4306 09:30:56.909345 TX Vref Scan disable
4307 09:30:56.912803 == TX Byte 0 ==
4308 09:30:56.915660 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4309 09:30:56.919183 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4310 09:30:56.922859 == TX Byte 1 ==
4311 09:30:56.925818 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4312 09:30:56.929320 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4313 09:30:56.929406
4314 09:30:56.932600 [DATLAT]
4315 09:30:56.932713 Freq=600, CH0 RK1
4316 09:30:56.932804
4317 09:30:56.935580 DATLAT Default: 0x9
4318 09:30:56.935664 0, 0xFFFF, sum = 0
4319 09:30:56.939077 1, 0xFFFF, sum = 0
4320 09:30:56.939163 2, 0xFFFF, sum = 0
4321 09:30:56.942502 3, 0xFFFF, sum = 0
4322 09:30:56.942589 4, 0xFFFF, sum = 0
4323 09:30:56.945724 5, 0xFFFF, sum = 0
4324 09:30:56.945799 6, 0xFFFF, sum = 0
4325 09:30:56.949104 7, 0xFFFF, sum = 0
4326 09:30:56.949189 8, 0x0, sum = 1
4327 09:30:56.952718 9, 0x0, sum = 2
4328 09:30:56.952811 10, 0x0, sum = 3
4329 09:30:56.955539 11, 0x0, sum = 4
4330 09:30:56.955653 best_step = 9
4331 09:30:56.955719
4332 09:30:56.955778 ==
4333 09:30:56.959035 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 09:30:56.962347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 09:30:56.965545 ==
4336 09:30:56.965629 RX Vref Scan: 0
4337 09:30:56.965698
4338 09:30:56.968701 RX Vref 0 -> 0, step: 1
4339 09:30:56.968772
4340 09:30:56.972022 RX Delay -179 -> 252, step: 8
4341 09:30:56.975664 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4342 09:30:56.978950 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4343 09:30:56.985319 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4344 09:30:56.988734 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4345 09:30:56.992245 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4346 09:30:56.995172 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4347 09:30:56.998689 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4348 09:30:57.005306 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4349 09:30:57.008739 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4350 09:30:57.012105 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4351 09:30:57.015539 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4352 09:30:57.021665 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4353 09:30:57.025281 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4354 09:30:57.028685 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4355 09:30:57.031619 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4356 09:30:57.035143 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4357 09:30:57.038446 ==
4358 09:30:57.041563 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 09:30:57.045026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 09:30:57.045113 ==
4361 09:30:57.045178 DQS Delay:
4362 09:30:57.048423 DQS0 = 0, DQS1 = 0
4363 09:30:57.048525 DQM Delay:
4364 09:30:57.051829 DQM0 = 48, DQM1 = 41
4365 09:30:57.051905 DQ Delay:
4366 09:30:57.054616 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4367 09:30:57.057938 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4368 09:30:57.061353 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4369 09:30:57.065022 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4370 09:30:57.065114
4371 09:30:57.065178
4372 09:30:57.071172 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4373 09:30:57.074752 CH0 RK1: MR19=808, MR18=6A37
4374 09:30:57.081300 CH0_RK1: MR19=0x808, MR18=0x6A37, DQSOSC=389, MR23=63, INC=173, DEC=115
4375 09:30:57.084691 [RxdqsGatingPostProcess] freq 600
4376 09:30:57.091233 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4377 09:30:57.094847 Pre-setting of DQS Precalculation
4378 09:30:57.097676 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4379 09:30:57.097802 ==
4380 09:30:57.101470 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 09:30:57.104356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 09:30:57.104432 ==
4383 09:30:57.111362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 09:30:57.117987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4385 09:30:57.121031 [CA 0] Center 35 (5~66) winsize 62
4386 09:30:57.124096 [CA 1] Center 35 (5~66) winsize 62
4387 09:30:57.127560 [CA 2] Center 34 (4~65) winsize 62
4388 09:30:57.130619 [CA 3] Center 34 (3~65) winsize 63
4389 09:30:57.134114 [CA 4] Center 34 (3~65) winsize 63
4390 09:30:57.137875 [CA 5] Center 33 (3~64) winsize 62
4391 09:30:57.137957
4392 09:30:57.140829 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4393 09:30:57.140910
4394 09:30:57.144136 [CATrainingPosCal] consider 1 rank data
4395 09:30:57.147768 u2DelayCellTimex100 = 270/100 ps
4396 09:30:57.150697 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 09:30:57.154087 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 09:30:57.157544 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 09:30:57.160918 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4400 09:30:57.167368 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4401 09:30:57.170456 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 09:30:57.170544
4403 09:30:57.173809 CA PerBit enable=1, Macro0, CA PI delay=33
4404 09:30:57.173901
4405 09:30:57.177427 [CBTSetCACLKResult] CA Dly = 33
4406 09:30:57.177513 CS Dly: 4 (0~35)
4407 09:30:57.177579 ==
4408 09:30:57.180567 Dram Type= 6, Freq= 0, CH_1, rank 1
4409 09:30:57.183762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 09:30:57.187292 ==
4411 09:30:57.190660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 09:30:57.197370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4413 09:30:57.200696 [CA 0] Center 35 (5~66) winsize 62
4414 09:30:57.203833 [CA 1] Center 35 (5~66) winsize 62
4415 09:30:57.207335 [CA 2] Center 34 (4~65) winsize 62
4416 09:30:57.210676 [CA 3] Center 34 (4~65) winsize 62
4417 09:30:57.214242 [CA 4] Center 34 (4~65) winsize 62
4418 09:30:57.217271 [CA 5] Center 34 (3~65) winsize 63
4419 09:30:57.217358
4420 09:30:57.220541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4421 09:30:57.220629
4422 09:30:57.223874 [CATrainingPosCal] consider 2 rank data
4423 09:30:57.227417 u2DelayCellTimex100 = 270/100 ps
4424 09:30:57.230474 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 09:30:57.233872 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 09:30:57.236980 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4427 09:30:57.243893 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 09:30:57.247273 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 09:30:57.250323 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 09:30:57.250410
4431 09:30:57.253786 CA PerBit enable=1, Macro0, CA PI delay=33
4432 09:30:57.253873
4433 09:30:57.257110 [CBTSetCACLKResult] CA Dly = 33
4434 09:30:57.257196 CS Dly: 4 (0~36)
4435 09:30:57.257280
4436 09:30:57.260169 ----->DramcWriteLeveling(PI) begin...
4437 09:30:57.260270 ==
4438 09:30:57.263822 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 09:30:57.270308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 09:30:57.270397 ==
4441 09:30:57.273670 Write leveling (Byte 0): 29 => 29
4442 09:30:57.277059 Write leveling (Byte 1): 32 => 32
4443 09:30:57.277146 DramcWriteLeveling(PI) end<-----
4444 09:30:57.277230
4445 09:30:57.280419 ==
4446 09:30:57.283648 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 09:30:57.287209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 09:30:57.287327 ==
4449 09:30:57.290467 [Gating] SW mode calibration
4450 09:30:57.296894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4451 09:30:57.300366 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4452 09:30:57.306807 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 09:30:57.310198 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 09:30:57.313875 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
4455 09:30:57.320471 0 9 12 | B1->B0 | 2a2a 2d2d | 0 1 | (1 0) (1 0)
4456 09:30:57.323379 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 09:30:57.326802 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 09:30:57.333586 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 09:30:57.337152 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 09:30:57.340298 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 09:30:57.346834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 09:30:57.350241 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4463 09:30:57.353613 0 10 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4464 09:30:57.360034 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 09:30:57.363342 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 09:30:57.366636 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 09:30:57.373178 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 09:30:57.376756 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 09:30:57.380336 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 09:30:57.383692 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:30:57.389932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 09:30:57.393211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 09:30:57.396658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 09:30:57.403210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 09:30:57.406666 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 09:30:57.409673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 09:30:57.416818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:30:57.419725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:30:57.423238 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:30:57.429966 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:30:57.433132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:30:57.436142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:30:57.443229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:30:57.446218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:30:57.449739 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:30:57.456147 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:30:57.459632 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4488 09:30:57.462995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 09:30:57.466399 Total UI for P1: 0, mck2ui 16
4490 09:30:57.469341 best dqsien dly found for B0: ( 0, 13, 14)
4491 09:30:57.472828 Total UI for P1: 0, mck2ui 16
4492 09:30:57.476380 best dqsien dly found for B1: ( 0, 13, 12)
4493 09:30:57.479407 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4494 09:30:57.483001 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4495 09:30:57.483084
4496 09:30:57.489239 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4497 09:30:57.493105 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4498 09:30:57.495929 [Gating] SW calibration Done
4499 09:30:57.496028 ==
4500 09:30:57.499584 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 09:30:57.502767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 09:30:57.502885 ==
4503 09:30:57.502967 RX Vref Scan: 0
4504 09:30:57.503027
4505 09:30:57.505996 RX Vref 0 -> 0, step: 1
4506 09:30:57.506082
4507 09:30:57.509299 RX Delay -230 -> 252, step: 16
4508 09:30:57.513033 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4509 09:30:57.516172 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4510 09:30:57.522636 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4511 09:30:57.526184 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4512 09:30:57.529731 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4513 09:30:57.532858 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4514 09:30:57.539657 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4515 09:30:57.542680 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4516 09:30:57.546173 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4517 09:30:57.549762 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4518 09:30:57.552738 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4519 09:30:57.559456 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4520 09:30:57.562564 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4521 09:30:57.565927 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4522 09:30:57.569140 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4523 09:30:57.576279 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4524 09:30:57.576363 ==
4525 09:30:57.579714 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 09:30:57.582712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 09:30:57.582796 ==
4528 09:30:57.582861 DQS Delay:
4529 09:30:57.586116 DQS0 = 0, DQS1 = 0
4530 09:30:57.586200 DQM Delay:
4531 09:30:57.589122 DQM0 = 45, DQM1 = 43
4532 09:30:57.589206 DQ Delay:
4533 09:30:57.592811 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4534 09:30:57.595972 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4535 09:30:57.599226 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4536 09:30:57.602608 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4537 09:30:57.602700
4538 09:30:57.602765
4539 09:30:57.602825 ==
4540 09:30:57.605785 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 09:30:57.609139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 09:30:57.609228 ==
4543 09:30:57.609294
4544 09:30:57.612437
4545 09:30:57.612519 TX Vref Scan disable
4546 09:30:57.616049 == TX Byte 0 ==
4547 09:30:57.619210 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4548 09:30:57.622704 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4549 09:30:57.625783 == TX Byte 1 ==
4550 09:30:57.629264 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4551 09:30:57.632680 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4552 09:30:57.632764 ==
4553 09:30:57.636003 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 09:30:57.642782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 09:30:57.642865 ==
4556 09:30:57.642929
4557 09:30:57.642989
4558 09:30:57.643046 TX Vref Scan disable
4559 09:30:57.647443 == TX Byte 0 ==
4560 09:30:57.650376 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4561 09:30:57.656921 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4562 09:30:57.657042 == TX Byte 1 ==
4563 09:30:57.660350 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4564 09:30:57.667233 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4565 09:30:57.667317
4566 09:30:57.667382 [DATLAT]
4567 09:30:57.667443 Freq=600, CH1 RK0
4568 09:30:57.667502
4569 09:30:57.670595 DATLAT Default: 0x9
4570 09:30:57.670677 0, 0xFFFF, sum = 0
4571 09:30:57.673984 1, 0xFFFF, sum = 0
4572 09:30:57.674067 2, 0xFFFF, sum = 0
4573 09:30:57.676892 3, 0xFFFF, sum = 0
4574 09:30:57.677028 4, 0xFFFF, sum = 0
4575 09:30:57.680495 5, 0xFFFF, sum = 0
4576 09:30:57.683460 6, 0xFFFF, sum = 0
4577 09:30:57.683545 7, 0xFFFF, sum = 0
4578 09:30:57.683612 8, 0x0, sum = 1
4579 09:30:57.686844 9, 0x0, sum = 2
4580 09:30:57.686928 10, 0x0, sum = 3
4581 09:30:57.690330 11, 0x0, sum = 4
4582 09:30:57.690451 best_step = 9
4583 09:30:57.690517
4584 09:30:57.690578 ==
4585 09:30:57.693746 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 09:30:57.700535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 09:30:57.700674 ==
4588 09:30:57.700745 RX Vref Scan: 1
4589 09:30:57.700806
4590 09:30:57.703883 RX Vref 0 -> 0, step: 1
4591 09:30:57.703962
4592 09:30:57.707063 RX Delay -179 -> 252, step: 8
4593 09:30:57.707157
4594 09:30:57.710174 Set Vref, RX VrefLevel [Byte0]: 53
4595 09:30:57.713538 [Byte1]: 53
4596 09:30:57.713633
4597 09:30:57.716736 Final RX Vref Byte 0 = 53 to rank0
4598 09:30:57.720437 Final RX Vref Byte 1 = 53 to rank0
4599 09:30:57.723439 Final RX Vref Byte 0 = 53 to rank1
4600 09:30:57.727003 Final RX Vref Byte 1 = 53 to rank1==
4601 09:30:57.730412 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 09:30:57.733480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 09:30:57.733583 ==
4604 09:30:57.736850 DQS Delay:
4605 09:30:57.736979 DQS0 = 0, DQS1 = 0
4606 09:30:57.737063 DQM Delay:
4607 09:30:57.740313 DQM0 = 46, DQM1 = 38
4608 09:30:57.740402 DQ Delay:
4609 09:30:57.743600 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4610 09:30:57.747029 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4611 09:30:57.750127 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =32
4612 09:30:57.753469 DQ12 =52, DQ13 =44, DQ14 =44, DQ15 =44
4613 09:30:57.753587
4614 09:30:57.753655
4615 09:30:57.763445 [DQSOSCAuto] RK0, (LSB)MR18= 0x5179, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4616 09:30:57.763625 CH1 RK0: MR19=808, MR18=5179
4617 09:30:57.770186 CH1_RK0: MR19=0x808, MR18=0x5179, DQSOSC=387, MR23=63, INC=175, DEC=116
4618 09:30:57.770410
4619 09:30:57.773647 ----->DramcWriteLeveling(PI) begin...
4620 09:30:57.776851 ==
4621 09:30:57.777000 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 09:30:57.783681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 09:30:57.783870 ==
4624 09:30:57.786685 Write leveling (Byte 0): 30 => 30
4625 09:30:57.790221 Write leveling (Byte 1): 30 => 30
4626 09:30:57.793370 DramcWriteLeveling(PI) end<-----
4627 09:30:57.793518
4628 09:30:57.793617 ==
4629 09:30:57.796732 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 09:30:57.800062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 09:30:57.800142 ==
4632 09:30:57.803487 [Gating] SW mode calibration
4633 09:30:57.809973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4634 09:30:57.813643 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4635 09:30:57.819984 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 09:30:57.823216 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 09:30:57.826314 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4638 09:30:57.833309 0 9 12 | B1->B0 | 2626 2f2f | 0 1 | (0 1) (1 0)
4639 09:30:57.836680 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4640 09:30:57.839707 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 09:30:57.846585 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 09:30:57.850071 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 09:30:57.853070 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 09:30:57.860083 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 09:30:57.863059 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4646 09:30:57.866518 0 10 12 | B1->B0 | 4646 3535 | 0 0 | (0 0) (0 0)
4647 09:30:57.873025 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 09:30:57.876374 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 09:30:57.879737 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 09:30:57.886301 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 09:30:57.889932 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 09:30:57.893007 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 09:30:57.900053 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 09:30:57.902870 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4655 09:30:57.906348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 09:30:57.913239 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 09:30:57.916299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 09:30:57.919886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 09:30:57.926406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 09:30:57.929495 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 09:30:57.933319 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 09:30:57.936104 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 09:30:57.942913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 09:30:57.946479 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 09:30:57.949578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 09:30:57.956229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 09:30:57.959377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:30:57.963133 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:30:57.969515 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:30:57.972608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4671 09:30:57.976348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 09:30:57.979381 Total UI for P1: 0, mck2ui 16
4673 09:30:57.982956 best dqsien dly found for B0: ( 0, 13, 12)
4674 09:30:57.986250 Total UI for P1: 0, mck2ui 16
4675 09:30:57.989138 best dqsien dly found for B1: ( 0, 13, 12)
4676 09:30:57.992610 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4677 09:30:57.996204 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4678 09:30:57.999152
4679 09:30:58.002720 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4680 09:30:58.006195 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4681 09:30:58.009400 [Gating] SW calibration Done
4682 09:30:58.009485 ==
4683 09:30:58.012978 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 09:30:58.015884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 09:30:58.015969 ==
4686 09:30:58.016053 RX Vref Scan: 0
4687 09:30:58.019407
4688 09:30:58.019491 RX Vref 0 -> 0, step: 1
4689 09:30:58.019574
4690 09:30:58.022528 RX Delay -230 -> 252, step: 16
4691 09:30:58.025827 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4692 09:30:58.032815 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4693 09:30:58.035913 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4694 09:30:58.039234 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4695 09:30:58.042364 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4696 09:30:58.045988 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4697 09:30:58.052483 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4698 09:30:58.056192 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4699 09:30:58.059415 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4700 09:30:58.062374 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4701 09:30:58.068900 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4702 09:30:58.072542 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4703 09:30:58.076035 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4704 09:30:58.078941 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4705 09:30:58.085847 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4706 09:30:58.088871 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4707 09:30:58.089008 ==
4708 09:30:58.092225 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 09:30:58.095687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 09:30:58.095786 ==
4711 09:30:58.095882 DQS Delay:
4712 09:30:58.098840 DQS0 = 0, DQS1 = 0
4713 09:30:58.098923 DQM Delay:
4714 09:30:58.102397 DQM0 = 49, DQM1 = 45
4715 09:30:58.102510 DQ Delay:
4716 09:30:58.105940 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4717 09:30:58.108775 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4718 09:30:58.112188 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4719 09:30:58.115524 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4720 09:30:58.115607
4721 09:30:58.115702
4722 09:30:58.115763 ==
4723 09:30:58.118607 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 09:30:58.125190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 09:30:58.125275 ==
4726 09:30:58.125341
4727 09:30:58.125400
4728 09:30:58.125457 TX Vref Scan disable
4729 09:30:58.128904 == TX Byte 0 ==
4730 09:30:58.132011 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4731 09:30:58.138643 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4732 09:30:58.138727 == TX Byte 1 ==
4733 09:30:58.142022 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 09:30:58.148722 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 09:30:58.148807 ==
4736 09:30:58.151760 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 09:30:58.155437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 09:30:58.155521 ==
4739 09:30:58.155587
4740 09:30:58.155648
4741 09:30:58.158600 TX Vref Scan disable
4742 09:30:58.162069 == TX Byte 0 ==
4743 09:30:58.165431 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4744 09:30:58.168450 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4745 09:30:58.171952 == TX Byte 1 ==
4746 09:30:58.175352 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4747 09:30:58.178407 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4748 09:30:58.178490
4749 09:30:58.178556 [DATLAT]
4750 09:30:58.181749 Freq=600, CH1 RK1
4751 09:30:58.181832
4752 09:30:58.185101 DATLAT Default: 0x9
4753 09:30:58.185184 0, 0xFFFF, sum = 0
4754 09:30:58.188557 1, 0xFFFF, sum = 0
4755 09:30:58.188642 2, 0xFFFF, sum = 0
4756 09:30:58.192008 3, 0xFFFF, sum = 0
4757 09:30:58.192092 4, 0xFFFF, sum = 0
4758 09:30:58.195327 5, 0xFFFF, sum = 0
4759 09:30:58.195413 6, 0xFFFF, sum = 0
4760 09:30:58.198731 7, 0xFFFF, sum = 0
4761 09:30:58.198816 8, 0x0, sum = 1
4762 09:30:58.201727 9, 0x0, sum = 2
4763 09:30:58.201821 10, 0x0, sum = 3
4764 09:30:58.201891 11, 0x0, sum = 4
4765 09:30:58.205081 best_step = 9
4766 09:30:58.205163
4767 09:30:58.205229 ==
4768 09:30:58.208209 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 09:30:58.211648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 09:30:58.211732 ==
4771 09:30:58.215059 RX Vref Scan: 0
4772 09:30:58.215142
4773 09:30:58.215207 RX Vref 0 -> 0, step: 1
4774 09:30:58.218342
4775 09:30:58.218426 RX Delay -179 -> 252, step: 8
4776 09:30:58.225977 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4777 09:30:58.228916 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4778 09:30:58.232448 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4779 09:30:58.235939 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4780 09:30:58.239279 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4781 09:30:58.245635 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4782 09:30:58.249108 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4783 09:30:58.252310 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4784 09:30:58.255576 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4785 09:30:58.262238 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4786 09:30:58.265656 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4787 09:30:58.268995 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4788 09:30:58.272265 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4789 09:30:58.275559 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4790 09:30:58.282233 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4791 09:30:58.285772 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4792 09:30:58.285855 ==
4793 09:30:58.289212 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 09:30:58.292161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 09:30:58.292245 ==
4796 09:30:58.295615 DQS Delay:
4797 09:30:58.295699 DQS0 = 0, DQS1 = 0
4798 09:30:58.295764 DQM Delay:
4799 09:30:58.299019 DQM0 = 46, DQM1 = 40
4800 09:30:58.299102 DQ Delay:
4801 09:30:58.302400 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4802 09:30:58.305412 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4803 09:30:58.308992 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =36
4804 09:30:58.312398 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =52
4805 09:30:58.312481
4806 09:30:58.312545
4807 09:30:58.322145 [DQSOSCAuto] RK1, (LSB)MR18= 0x551c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4808 09:30:58.325213 CH1 RK1: MR19=808, MR18=551C
4809 09:30:58.332404 CH1_RK1: MR19=0x808, MR18=0x551C, DQSOSC=393, MR23=63, INC=169, DEC=113
4810 09:30:58.332488 [RxdqsGatingPostProcess] freq 600
4811 09:30:58.338645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4812 09:30:58.342186 Pre-setting of DQS Precalculation
4813 09:30:58.345219 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4814 09:30:58.355444 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4815 09:30:58.361747 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4816 09:30:58.361836
4817 09:30:58.361901
4818 09:30:58.365546 [Calibration Summary] 1200 Mbps
4819 09:30:58.365642 CH 0, Rank 0
4820 09:30:58.368780 SW Impedance : PASS
4821 09:30:58.368889 DUTY Scan : NO K
4822 09:30:58.371981 ZQ Calibration : PASS
4823 09:30:58.375442 Jitter Meter : NO K
4824 09:30:58.375524 CBT Training : PASS
4825 09:30:58.378553 Write leveling : PASS
4826 09:30:58.381797 RX DQS gating : PASS
4827 09:30:58.381880 RX DQ/DQS(RDDQC) : PASS
4828 09:30:58.385521 TX DQ/DQS : PASS
4829 09:30:58.388477 RX DATLAT : PASS
4830 09:30:58.388559 RX DQ/DQS(Engine): PASS
4831 09:30:58.391944 TX OE : NO K
4832 09:30:58.392031 All Pass.
4833 09:30:58.392095
4834 09:30:58.394987 CH 0, Rank 1
4835 09:30:58.395069 SW Impedance : PASS
4836 09:30:58.398443 DUTY Scan : NO K
4837 09:30:58.398525 ZQ Calibration : PASS
4838 09:30:58.401977 Jitter Meter : NO K
4839 09:30:58.405221 CBT Training : PASS
4840 09:30:58.405302 Write leveling : PASS
4841 09:30:58.408147 RX DQS gating : PASS
4842 09:30:58.411674 RX DQ/DQS(RDDQC) : PASS
4843 09:30:58.411755 TX DQ/DQS : PASS
4844 09:30:58.415176 RX DATLAT : PASS
4845 09:30:58.418247 RX DQ/DQS(Engine): PASS
4846 09:30:58.418329 TX OE : NO K
4847 09:30:58.421704 All Pass.
4848 09:30:58.421786
4849 09:30:58.421855 CH 1, Rank 0
4850 09:30:58.425097 SW Impedance : PASS
4851 09:30:58.425179 DUTY Scan : NO K
4852 09:30:58.428415 ZQ Calibration : PASS
4853 09:30:58.431447 Jitter Meter : NO K
4854 09:30:58.431529 CBT Training : PASS
4855 09:30:58.434895 Write leveling : PASS
4856 09:30:58.437891 RX DQS gating : PASS
4857 09:30:58.438006 RX DQ/DQS(RDDQC) : PASS
4858 09:30:58.441666 TX DQ/DQS : PASS
4859 09:30:58.444855 RX DATLAT : PASS
4860 09:30:58.444964 RX DQ/DQS(Engine): PASS
4861 09:30:58.448504 TX OE : NO K
4862 09:30:58.448586 All Pass.
4863 09:30:58.448651
4864 09:30:58.451775 CH 1, Rank 1
4865 09:30:58.451860 SW Impedance : PASS
4866 09:30:58.454669 DUTY Scan : NO K
4867 09:30:58.458285 ZQ Calibration : PASS
4868 09:30:58.458367 Jitter Meter : NO K
4869 09:30:58.461643 CBT Training : PASS
4870 09:30:58.461725 Write leveling : PASS
4871 09:30:58.464552 RX DQS gating : PASS
4872 09:30:58.468199 RX DQ/DQS(RDDQC) : PASS
4873 09:30:58.468281 TX DQ/DQS : PASS
4874 09:30:58.471450 RX DATLAT : PASS
4875 09:30:58.474623 RX DQ/DQS(Engine): PASS
4876 09:30:58.474705 TX OE : NO K
4877 09:30:58.477773 All Pass.
4878 09:30:58.477856
4879 09:30:58.477921 DramC Write-DBI off
4880 09:30:58.481005 PER_BANK_REFRESH: Hybrid Mode
4881 09:30:58.484744 TX_TRACKING: ON
4882 09:30:58.491189 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4883 09:30:58.494592 [FAST_K] Save calibration result to emmc
4884 09:30:58.498130 dramc_set_vcore_voltage set vcore to 662500
4885 09:30:58.501253 Read voltage for 933, 3
4886 09:30:58.501336 Vio18 = 0
4887 09:30:58.504680 Vcore = 662500
4888 09:30:58.504762 Vdram = 0
4889 09:30:58.504826 Vddq = 0
4890 09:30:58.507966 Vmddr = 0
4891 09:30:58.511038 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4892 09:30:58.517721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4893 09:30:58.517805 MEM_TYPE=3, freq_sel=17
4894 09:30:58.521262 sv_algorithm_assistance_LP4_1600
4895 09:30:58.527800 ============ PULL DRAM RESETB DOWN ============
4896 09:30:58.531059 ========== PULL DRAM RESETB DOWN end =========
4897 09:30:58.534578 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4898 09:30:58.537675 ===================================
4899 09:30:58.541200 LPDDR4 DRAM CONFIGURATION
4900 09:30:58.544555 ===================================
4901 09:30:58.544638 EX_ROW_EN[0] = 0x0
4902 09:30:58.547741 EX_ROW_EN[1] = 0x0
4903 09:30:58.551169 LP4Y_EN = 0x0
4904 09:30:58.551252 WORK_FSP = 0x0
4905 09:30:58.554141 WL = 0x3
4906 09:30:58.554223 RL = 0x3
4907 09:30:58.557404 BL = 0x2
4908 09:30:58.557486 RPST = 0x0
4909 09:30:58.560838 RD_PRE = 0x0
4910 09:30:58.560920 WR_PRE = 0x1
4911 09:30:58.564392 WR_PST = 0x0
4912 09:30:58.564474 DBI_WR = 0x0
4913 09:30:58.567346 DBI_RD = 0x0
4914 09:30:58.567428 OTF = 0x1
4915 09:30:58.570925 ===================================
4916 09:30:58.574253 ===================================
4917 09:30:58.577419 ANA top config
4918 09:30:58.581078 ===================================
4919 09:30:58.581160 DLL_ASYNC_EN = 0
4920 09:30:58.584151 ALL_SLAVE_EN = 1
4921 09:30:58.587554 NEW_RANK_MODE = 1
4922 09:30:58.591065 DLL_IDLE_MODE = 1
4923 09:30:58.594046 LP45_APHY_COMB_EN = 1
4924 09:30:58.594130 TX_ODT_DIS = 1
4925 09:30:58.597344 NEW_8X_MODE = 1
4926 09:30:58.600762 ===================================
4927 09:30:58.604059 ===================================
4928 09:30:58.607578 data_rate = 1866
4929 09:30:58.611070 CKR = 1
4930 09:30:58.614283 DQ_P2S_RATIO = 8
4931 09:30:58.617348 ===================================
4932 09:30:58.617431 CA_P2S_RATIO = 8
4933 09:30:58.620903 DQ_CA_OPEN = 0
4934 09:30:58.623975 DQ_SEMI_OPEN = 0
4935 09:30:58.627467 CA_SEMI_OPEN = 0
4936 09:30:58.630429 CA_FULL_RATE = 0
4937 09:30:58.634157 DQ_CKDIV4_EN = 1
4938 09:30:58.634238 CA_CKDIV4_EN = 1
4939 09:30:58.637270 CA_PREDIV_EN = 0
4940 09:30:58.640389 PH8_DLY = 0
4941 09:30:58.643960 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4942 09:30:58.647219 DQ_AAMCK_DIV = 4
4943 09:30:58.650286 CA_AAMCK_DIV = 4
4944 09:30:58.650372 CA_ADMCK_DIV = 4
4945 09:30:58.653646 DQ_TRACK_CA_EN = 0
4946 09:30:58.657166 CA_PICK = 933
4947 09:30:58.660500 CA_MCKIO = 933
4948 09:30:58.663774 MCKIO_SEMI = 0
4949 09:30:58.666942 PLL_FREQ = 3732
4950 09:30:58.670422 DQ_UI_PI_RATIO = 32
4951 09:30:58.670505 CA_UI_PI_RATIO = 0
4952 09:30:58.676865 ===================================
4953 09:30:58.676954 ===================================
4954 09:30:58.680288 memory_type:LPDDR4
4955 09:30:58.683512 GP_NUM : 10
4956 09:30:58.683594 SRAM_EN : 1
4957 09:30:58.686775 MD32_EN : 0
4958 09:30:58.690348 ===================================
4959 09:30:58.693141 [ANA_INIT] >>>>>>>>>>>>>>
4960 09:30:58.696610 <<<<<< [CONFIGURE PHASE]: ANA_TX
4961 09:30:58.700260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4962 09:30:58.703356 ===================================
4963 09:30:58.706542 data_rate = 1866,PCW = 0X8f00
4964 09:30:58.710065 ===================================
4965 09:30:58.713195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4966 09:30:58.716466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 09:30:58.722899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 09:30:58.726452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4969 09:30:58.730086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4970 09:30:58.733002 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4971 09:30:58.736506 [ANA_INIT] flow start
4972 09:30:58.739329 [ANA_INIT] PLL >>>>>>>>
4973 09:30:58.739410 [ANA_INIT] PLL <<<<<<<<
4974 09:30:58.742867 [ANA_INIT] MIDPI >>>>>>>>
4975 09:30:58.746325 [ANA_INIT] MIDPI <<<<<<<<
4976 09:30:58.749337 [ANA_INIT] DLL >>>>>>>>
4977 09:30:58.749418 [ANA_INIT] flow end
4978 09:30:58.752890 ============ LP4 DIFF to SE enter ============
4979 09:30:58.759709 ============ LP4 DIFF to SE exit ============
4980 09:30:58.759794 [ANA_INIT] <<<<<<<<<<<<<
4981 09:30:58.762608 [Flow] Enable top DCM control >>>>>
4982 09:30:58.766302 [Flow] Enable top DCM control <<<<<
4983 09:30:58.769385 Enable DLL master slave shuffle
4984 09:30:58.776343 ==============================================================
4985 09:30:58.776428 Gating Mode config
4986 09:30:58.782701 ==============================================================
4987 09:30:58.785679 Config description:
4988 09:30:58.795889 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4989 09:30:58.802799 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4990 09:30:58.805962 SELPH_MODE 0: By rank 1: By Phase
4991 09:30:58.812268 ==============================================================
4992 09:30:58.815880 GAT_TRACK_EN = 1
4993 09:30:58.815964 RX_GATING_MODE = 2
4994 09:30:58.819237 RX_GATING_TRACK_MODE = 2
4995 09:30:58.822056 SELPH_MODE = 1
4996 09:30:58.825438 PICG_EARLY_EN = 1
4997 09:30:58.828966 VALID_LAT_VALUE = 1
4998 09:30:58.835451 ==============================================================
4999 09:30:58.838981 Enter into Gating configuration >>>>
5000 09:30:58.841917 Exit from Gating configuration <<<<
5001 09:30:58.845437 Enter into DVFS_PRE_config >>>>>
5002 09:30:58.855292 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5003 09:30:58.858812 Exit from DVFS_PRE_config <<<<<
5004 09:30:58.862108 Enter into PICG configuration >>>>
5005 09:30:58.865254 Exit from PICG configuration <<<<
5006 09:30:58.868510 [RX_INPUT] configuration >>>>>
5007 09:30:58.871965 [RX_INPUT] configuration <<<<<
5008 09:30:58.875246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5009 09:30:58.881816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5010 09:30:58.888796 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 09:30:58.891756 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 09:30:58.898560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 09:30:58.905336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 09:30:58.908468 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5015 09:30:58.915201 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5016 09:30:58.918386 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5017 09:30:58.921922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5018 09:30:58.925234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5019 09:30:58.931666 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 09:30:58.935234 ===================================
5021 09:30:58.935317 LPDDR4 DRAM CONFIGURATION
5022 09:30:58.938371 ===================================
5023 09:30:58.941799 EX_ROW_EN[0] = 0x0
5024 09:30:58.945219 EX_ROW_EN[1] = 0x0
5025 09:30:58.945301 LP4Y_EN = 0x0
5026 09:30:58.948557 WORK_FSP = 0x0
5027 09:30:58.948638 WL = 0x3
5028 09:30:58.952196 RL = 0x3
5029 09:30:58.952277 BL = 0x2
5030 09:30:58.955232 RPST = 0x0
5031 09:30:58.955312 RD_PRE = 0x0
5032 09:30:58.958298 WR_PRE = 0x1
5033 09:30:58.958378 WR_PST = 0x0
5034 09:30:58.961655 DBI_WR = 0x0
5035 09:30:58.961751 DBI_RD = 0x0
5036 09:30:58.965214 OTF = 0x1
5037 09:30:58.968762 ===================================
5038 09:30:58.971652 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5039 09:30:58.975072 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5040 09:30:58.981879 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 09:30:58.984825 ===================================
5042 09:30:58.984909 LPDDR4 DRAM CONFIGURATION
5043 09:30:58.988327 ===================================
5044 09:30:58.991795 EX_ROW_EN[0] = 0x10
5045 09:30:58.991877 EX_ROW_EN[1] = 0x0
5046 09:30:58.994952 LP4Y_EN = 0x0
5047 09:30:58.995035 WORK_FSP = 0x0
5048 09:30:58.998224 WL = 0x3
5049 09:30:59.002052 RL = 0x3
5050 09:30:59.002134 BL = 0x2
5051 09:30:59.004873 RPST = 0x0
5052 09:30:59.004992 RD_PRE = 0x0
5053 09:30:59.008470 WR_PRE = 0x1
5054 09:30:59.008556 WR_PST = 0x0
5055 09:30:59.011482 DBI_WR = 0x0
5056 09:30:59.011563 DBI_RD = 0x0
5057 09:30:59.015227 OTF = 0x1
5058 09:30:59.018556 ===================================
5059 09:30:59.021715 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5060 09:30:59.027312 nWR fixed to 30
5061 09:30:59.030867 [ModeRegInit_LP4] CH0 RK0
5062 09:30:59.030949 [ModeRegInit_LP4] CH0 RK1
5063 09:30:59.033755 [ModeRegInit_LP4] CH1 RK0
5064 09:30:59.037200 [ModeRegInit_LP4] CH1 RK1
5065 09:30:59.037281 match AC timing 9
5066 09:30:59.043902 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5067 09:30:59.047193 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5068 09:30:59.050551 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5069 09:30:59.056881 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5070 09:30:59.060518 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5071 09:30:59.060601 ==
5072 09:30:59.063906 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 09:30:59.066979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 09:30:59.067061 ==
5075 09:30:59.073471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 09:30:59.080217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5077 09:30:59.083586 [CA 0] Center 38 (7~69) winsize 63
5078 09:30:59.087042 [CA 1] Center 38 (7~69) winsize 63
5079 09:30:59.090039 [CA 2] Center 35 (5~66) winsize 62
5080 09:30:59.093574 [CA 3] Center 34 (4~65) winsize 62
5081 09:30:59.096952 [CA 4] Center 34 (4~65) winsize 62
5082 09:30:59.100141 [CA 5] Center 33 (3~64) winsize 62
5083 09:30:59.100225
5084 09:30:59.103386 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5085 09:30:59.103469
5086 09:30:59.106645 [CATrainingPosCal] consider 1 rank data
5087 09:30:59.110090 u2DelayCellTimex100 = 270/100 ps
5088 09:30:59.113690 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5089 09:30:59.116760 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5090 09:30:59.120373 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5091 09:30:59.123391 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5092 09:30:59.127055 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5093 09:30:59.130179 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 09:30:59.133294
5095 09:30:59.136724 CA PerBit enable=1, Macro0, CA PI delay=33
5096 09:30:59.136806
5097 09:30:59.140258 [CBTSetCACLKResult] CA Dly = 33
5098 09:30:59.140340 CS Dly: 6 (0~37)
5099 09:30:59.140404 ==
5100 09:30:59.143916 Dram Type= 6, Freq= 0, CH_0, rank 1
5101 09:30:59.146982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 09:30:59.147065 ==
5103 09:30:59.153384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 09:30:59.160421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5105 09:30:59.163371 [CA 0] Center 38 (7~69) winsize 63
5106 09:30:59.166849 [CA 1] Center 38 (8~69) winsize 62
5107 09:30:59.170435 [CA 2] Center 36 (6~66) winsize 61
5108 09:30:59.173240 [CA 3] Center 35 (5~66) winsize 62
5109 09:30:59.176923 [CA 4] Center 34 (4~65) winsize 62
5110 09:30:59.180359 [CA 5] Center 34 (4~65) winsize 62
5111 09:30:59.180443
5112 09:30:59.183372 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5113 09:30:59.183454
5114 09:30:59.186695 [CATrainingPosCal] consider 2 rank data
5115 09:30:59.190134 u2DelayCellTimex100 = 270/100 ps
5116 09:30:59.193260 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5117 09:30:59.196787 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5118 09:30:59.200364 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5119 09:30:59.203419 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5120 09:30:59.206541 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5121 09:30:59.213216 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5122 09:30:59.213299
5123 09:30:59.216732 CA PerBit enable=1, Macro0, CA PI delay=34
5124 09:30:59.216814
5125 09:30:59.219792 [CBTSetCACLKResult] CA Dly = 34
5126 09:30:59.219875 CS Dly: 7 (0~39)
5127 09:30:59.219939
5128 09:30:59.223392 ----->DramcWriteLeveling(PI) begin...
5129 09:30:59.223478 ==
5130 09:30:59.226458 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 09:30:59.229749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 09:30:59.233242 ==
5133 09:30:59.233324 Write leveling (Byte 0): 30 => 30
5134 09:30:59.236661 Write leveling (Byte 1): 29 => 29
5135 09:30:59.239970 DramcWriteLeveling(PI) end<-----
5136 09:30:59.240051
5137 09:30:59.240115 ==
5138 09:30:59.243395 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 09:30:59.249948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 09:30:59.250030 ==
5141 09:30:59.252916 [Gating] SW mode calibration
5142 09:30:59.259645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5143 09:30:59.262982 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5144 09:30:59.270156 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5145 09:30:59.273145 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 09:30:59.276892 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 09:30:59.283346 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 09:30:59.286317 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 09:30:59.289628 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 09:30:59.293031 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5151 09:30:59.299581 0 14 28 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
5152 09:30:59.302748 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5153 09:30:59.306293 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 09:30:59.312798 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 09:30:59.316184 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 09:30:59.319623 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 09:30:59.326244 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 09:30:59.329451 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5159 09:30:59.332603 0 15 28 | B1->B0 | 3030 4545 | 0 0 | (0 0) (1 1)
5160 09:30:59.339644 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5161 09:30:59.342843 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 09:30:59.346162 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 09:30:59.352595 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 09:30:59.356110 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 09:30:59.359523 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:30:59.365972 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5167 09:30:59.369341 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5168 09:30:59.372832 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5169 09:30:59.379263 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5170 09:30:59.382471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 09:30:59.386028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 09:30:59.392787 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 09:30:59.396391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:30:59.399208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:30:59.405737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:30:59.409234 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:30:59.412595 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:30:59.416255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:30:59.422654 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:30:59.425751 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:30:59.432755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:30:59.435662 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5183 09:30:59.439222 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5184 09:30:59.442272 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5185 09:30:59.445835 Total UI for P1: 0, mck2ui 16
5186 09:30:59.449092 best dqsien dly found for B0: ( 1, 2, 26)
5187 09:30:59.455866 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 09:30:59.458969 Total UI for P1: 0, mck2ui 16
5189 09:30:59.462385 best dqsien dly found for B1: ( 1, 3, 0)
5190 09:30:59.465798 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5191 09:30:59.469064 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5192 09:30:59.469146
5193 09:30:59.472406 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5194 09:30:59.475492 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5195 09:30:59.479038 [Gating] SW calibration Done
5196 09:30:59.479121 ==
5197 09:30:59.482096 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 09:30:59.485505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 09:30:59.485589 ==
5200 09:30:59.488922 RX Vref Scan: 0
5201 09:30:59.489045
5202 09:30:59.489109 RX Vref 0 -> 0, step: 1
5203 09:30:59.489169
5204 09:30:59.492249 RX Delay -80 -> 252, step: 8
5205 09:30:59.499020 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5206 09:30:59.502171 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5207 09:30:59.505786 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5208 09:30:59.508822 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5209 09:30:59.512459 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5210 09:30:59.515391 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5211 09:30:59.522387 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5212 09:30:59.525369 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5213 09:30:59.529116 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5214 09:30:59.531974 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5215 09:30:59.535548 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5216 09:30:59.538773 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5217 09:30:59.545405 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5218 09:30:59.548554 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5219 09:30:59.552558 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5220 09:30:59.555453 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5221 09:30:59.555537 ==
5222 09:30:59.558792 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 09:30:59.562349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 09:30:59.562433 ==
5225 09:30:59.565375 DQS Delay:
5226 09:30:59.565458 DQS0 = 0, DQS1 = 0
5227 09:30:59.568957 DQM Delay:
5228 09:30:59.569054 DQM0 = 106, DQM1 = 90
5229 09:30:59.569118 DQ Delay:
5230 09:30:59.571997 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5231 09:30:59.575295 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5232 09:30:59.578816 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5233 09:30:59.585562 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5234 09:30:59.585647
5235 09:30:59.585713
5236 09:30:59.585772 ==
5237 09:30:59.588620 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 09:30:59.591941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 09:30:59.592025 ==
5240 09:30:59.592090
5241 09:30:59.592150
5242 09:30:59.595463 TX Vref Scan disable
5243 09:30:59.595546 == TX Byte 0 ==
5244 09:30:59.602201 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5245 09:30:59.605228 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5246 09:30:59.605313 == TX Byte 1 ==
5247 09:30:59.611832 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5248 09:30:59.615332 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5249 09:30:59.615417 ==
5250 09:30:59.618889 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 09:30:59.621843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 09:30:59.621926 ==
5253 09:30:59.621991
5254 09:30:59.622050
5255 09:30:59.625413 TX Vref Scan disable
5256 09:30:59.628473 == TX Byte 0 ==
5257 09:30:59.631963 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5258 09:30:59.635328 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5259 09:30:59.638293 == TX Byte 1 ==
5260 09:30:59.641512 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5261 09:30:59.645199 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5262 09:30:59.645287
5263 09:30:59.648478 [DATLAT]
5264 09:30:59.648560 Freq=933, CH0 RK0
5265 09:30:59.648626
5266 09:30:59.651593 DATLAT Default: 0xd
5267 09:30:59.651676 0, 0xFFFF, sum = 0
5268 09:30:59.655019 1, 0xFFFF, sum = 0
5269 09:30:59.655104 2, 0xFFFF, sum = 0
5270 09:30:59.658493 3, 0xFFFF, sum = 0
5271 09:30:59.658576 4, 0xFFFF, sum = 0
5272 09:30:59.661545 5, 0xFFFF, sum = 0
5273 09:30:59.661630 6, 0xFFFF, sum = 0
5274 09:30:59.665043 7, 0xFFFF, sum = 0
5275 09:30:59.665128 8, 0xFFFF, sum = 0
5276 09:30:59.668447 9, 0xFFFF, sum = 0
5277 09:30:59.668531 10, 0x0, sum = 1
5278 09:30:59.671420 11, 0x0, sum = 2
5279 09:30:59.671504 12, 0x0, sum = 3
5280 09:30:59.674800 13, 0x0, sum = 4
5281 09:30:59.674884 best_step = 11
5282 09:30:59.674950
5283 09:30:59.675009 ==
5284 09:30:59.678184 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 09:30:59.685097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 09:30:59.685182 ==
5287 09:30:59.685248 RX Vref Scan: 1
5288 09:30:59.685308
5289 09:30:59.688386 RX Vref 0 -> 0, step: 1
5290 09:30:59.688469
5291 09:30:59.691448 RX Delay -53 -> 252, step: 4
5292 09:30:59.691531
5293 09:30:59.694992 Set Vref, RX VrefLevel [Byte0]: 58
5294 09:30:59.697912 [Byte1]: 49
5295 09:30:59.697997
5296 09:30:59.701531 Final RX Vref Byte 0 = 58 to rank0
5297 09:30:59.704902 Final RX Vref Byte 1 = 49 to rank0
5298 09:30:59.707826 Final RX Vref Byte 0 = 58 to rank1
5299 09:30:59.711351 Final RX Vref Byte 1 = 49 to rank1==
5300 09:30:59.714666 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 09:30:59.718151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 09:30:59.718239 ==
5303 09:30:59.721626 DQS Delay:
5304 09:30:59.721708 DQS0 = 0, DQS1 = 0
5305 09:30:59.721773 DQM Delay:
5306 09:30:59.724542 DQM0 = 108, DQM1 = 91
5307 09:30:59.724625 DQ Delay:
5308 09:30:59.728029 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5309 09:30:59.731177 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =114
5310 09:30:59.734599 DQ8 =88, DQ9 =76, DQ10 =90, DQ11 =90
5311 09:30:59.741223 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =98
5312 09:30:59.741306
5313 09:30:59.741370
5314 09:30:59.748255 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5315 09:30:59.751048 CH0 RK0: MR19=505, MR18=211D
5316 09:30:59.757972 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5317 09:30:59.758056
5318 09:30:59.761134 ----->DramcWriteLeveling(PI) begin...
5319 09:30:59.761217 ==
5320 09:30:59.764879 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 09:30:59.767984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 09:30:59.768071 ==
5323 09:30:59.771278 Write leveling (Byte 0): 31 => 31
5324 09:30:59.774780 Write leveling (Byte 1): 30 => 30
5325 09:30:59.778324 DramcWriteLeveling(PI) end<-----
5326 09:30:59.778406
5327 09:30:59.778472 ==
5328 09:30:59.781244 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 09:30:59.784637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 09:30:59.784718 ==
5331 09:30:59.788061 [Gating] SW mode calibration
5332 09:30:59.795000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5333 09:30:59.801281 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5334 09:30:59.804811 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 09:30:59.807765 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 09:30:59.814595 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 09:30:59.818145 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 09:30:59.821148 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 09:30:59.827687 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 09:30:59.831177 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5341 09:30:59.834314 0 14 28 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (1 0)
5342 09:30:59.841099 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 09:30:59.844599 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 09:30:59.847602 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 09:30:59.854304 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 09:30:59.857715 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 09:30:59.861000 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 09:30:59.867806 0 15 24 | B1->B0 | 2525 2828 | 0 0 | (0 0) (1 1)
5349 09:30:59.871260 0 15 28 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
5350 09:30:59.874525 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 09:30:59.880960 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 09:30:59.884340 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 09:30:59.887864 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 09:30:59.891241 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 09:30:59.897913 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 09:30:59.900802 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 09:30:59.904262 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5358 09:30:59.911047 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 09:30:59.914230 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 09:30:59.917624 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 09:30:59.924283 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 09:30:59.927385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 09:30:59.930942 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 09:30:59.937664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 09:30:59.940601 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 09:30:59.944311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 09:30:59.950944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 09:30:59.954254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 09:30:59.957504 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 09:30:59.964274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 09:30:59.967558 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:30:59.970700 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:30:59.977147 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5374 09:30:59.977229 Total UI for P1: 0, mck2ui 16
5375 09:30:59.983891 best dqsien dly found for B0: ( 1, 2, 26)
5376 09:30:59.987106 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 09:30:59.990955 Total UI for P1: 0, mck2ui 16
5378 09:30:59.993806 best dqsien dly found for B1: ( 1, 2, 28)
5379 09:30:59.997413 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5380 09:31:00.000446 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5381 09:31:00.000525
5382 09:31:00.003966 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5383 09:31:00.007639 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5384 09:31:00.010779 [Gating] SW calibration Done
5385 09:31:00.010858 ==
5386 09:31:00.013883 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 09:31:00.017279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 09:31:00.017359 ==
5389 09:31:00.020663 RX Vref Scan: 0
5390 09:31:00.020741
5391 09:31:00.024092 RX Vref 0 -> 0, step: 1
5392 09:31:00.024171
5393 09:31:00.024233 RX Delay -80 -> 252, step: 8
5394 09:31:00.030650 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5395 09:31:00.034106 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5396 09:31:00.037372 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5397 09:31:00.040627 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5398 09:31:00.044201 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5399 09:31:00.050705 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5400 09:31:00.053813 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5401 09:31:00.057424 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5402 09:31:00.060361 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5403 09:31:00.063721 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5404 09:31:00.067231 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5405 09:31:00.073583 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5406 09:31:00.077216 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5407 09:31:00.080569 iDelay=208, Bit 13, Center 99 (16 ~ 183) 168
5408 09:31:00.083702 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5409 09:31:00.087287 iDelay=208, Bit 15, Center 99 (16 ~ 183) 168
5410 09:31:00.090556 ==
5411 09:31:00.093972 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 09:31:00.097129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 09:31:00.097241 ==
5414 09:31:00.097342 DQS Delay:
5415 09:31:00.100388 DQS0 = 0, DQS1 = 0
5416 09:31:00.100467 DQM Delay:
5417 09:31:00.103966 DQM0 = 105, DQM1 = 91
5418 09:31:00.104045 DQ Delay:
5419 09:31:00.107047 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5420 09:31:00.110413 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5421 09:31:00.113887 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5422 09:31:00.117028 DQ12 =91, DQ13 =99, DQ14 =103, DQ15 =99
5423 09:31:00.117109
5424 09:31:00.117171
5425 09:31:00.117229 ==
5426 09:31:00.120491 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 09:31:00.123942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 09:31:00.124095 ==
5429 09:31:00.127175
5430 09:31:00.127324
5431 09:31:00.127394 TX Vref Scan disable
5432 09:31:00.130671 == TX Byte 0 ==
5433 09:31:00.133484 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5434 09:31:00.137009 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5435 09:31:00.140661 == TX Byte 1 ==
5436 09:31:00.143993 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5437 09:31:00.147504 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5438 09:31:00.147657 ==
5439 09:31:00.150991 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 09:31:00.157398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 09:31:00.157561 ==
5442 09:31:00.157641
5443 09:31:00.157707
5444 09:31:00.157768 TX Vref Scan disable
5445 09:31:00.161491 == TX Byte 0 ==
5446 09:31:00.164634 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5447 09:31:00.171516 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5448 09:31:00.171696 == TX Byte 1 ==
5449 09:31:00.174826 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5450 09:31:00.181449 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5451 09:31:00.181666
5452 09:31:00.181776 [DATLAT]
5453 09:31:00.181870 Freq=933, CH0 RK1
5454 09:31:00.181961
5455 09:31:00.184667 DATLAT Default: 0xb
5456 09:31:00.184886 0, 0xFFFF, sum = 0
5457 09:31:00.187872 1, 0xFFFF, sum = 0
5458 09:31:00.188102 2, 0xFFFF, sum = 0
5459 09:31:00.191535 3, 0xFFFF, sum = 0
5460 09:31:00.194696 4, 0xFFFF, sum = 0
5461 09:31:00.194977 5, 0xFFFF, sum = 0
5462 09:31:00.197842 6, 0xFFFF, sum = 0
5463 09:31:00.198112 7, 0xFFFF, sum = 0
5464 09:31:00.201571 8, 0xFFFF, sum = 0
5465 09:31:00.201882 9, 0xFFFF, sum = 0
5466 09:31:00.204769 10, 0x0, sum = 1
5467 09:31:00.205123 11, 0x0, sum = 2
5468 09:31:00.205319 12, 0x0, sum = 3
5469 09:31:00.208305 13, 0x0, sum = 4
5470 09:31:00.208672 best_step = 11
5471 09:31:00.208908
5472 09:31:00.209145 ==
5473 09:31:00.211808 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 09:31:00.218558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 09:31:00.219040 ==
5476 09:31:00.219355 RX Vref Scan: 0
5477 09:31:00.219632
5478 09:31:00.221706 RX Vref 0 -> 0, step: 1
5479 09:31:00.222085
5480 09:31:00.224622 RX Delay -53 -> 252, step: 4
5481 09:31:00.227929 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5482 09:31:00.235009 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5483 09:31:00.238055 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5484 09:31:00.241533 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5485 09:31:00.245138 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5486 09:31:00.247974 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5487 09:31:00.254499 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5488 09:31:00.257917 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5489 09:31:00.261472 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5490 09:31:00.264478 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5491 09:31:00.267906 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5492 09:31:00.271037 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5493 09:31:00.277836 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5494 09:31:00.281175 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5495 09:31:00.284179 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5496 09:31:00.287461 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5497 09:31:00.287562 ==
5498 09:31:00.290914 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 09:31:00.297436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 09:31:00.297561 ==
5501 09:31:00.297628 DQS Delay:
5502 09:31:00.297688 DQS0 = 0, DQS1 = 0
5503 09:31:00.300656 DQM Delay:
5504 09:31:00.300747 DQM0 = 104, DQM1 = 91
5505 09:31:00.304247 DQ Delay:
5506 09:31:00.307478 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5507 09:31:00.310765 DQ4 =104, DQ5 =98, DQ6 =110, DQ7 =112
5508 09:31:00.314229 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5509 09:31:00.317273 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5510 09:31:00.317356
5511 09:31:00.317422
5512 09:31:00.324380 [DQSOSCAuto] RK1, (LSB)MR18= 0x2709, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5513 09:31:00.327284 CH0 RK1: MR19=505, MR18=2709
5514 09:31:00.334140 CH0_RK1: MR19=0x505, MR18=0x2709, DQSOSC=409, MR23=63, INC=64, DEC=43
5515 09:31:00.337655 [RxdqsGatingPostProcess] freq 933
5516 09:31:00.340716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5517 09:31:00.344216 best DQS0 dly(2T, 0.5T) = (0, 10)
5518 09:31:00.347291 best DQS1 dly(2T, 0.5T) = (0, 11)
5519 09:31:00.350866 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5520 09:31:00.354455 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5521 09:31:00.357135 best DQS0 dly(2T, 0.5T) = (0, 10)
5522 09:31:00.360608 best DQS1 dly(2T, 0.5T) = (0, 10)
5523 09:31:00.363728 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5524 09:31:00.367275 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5525 09:31:00.370804 Pre-setting of DQS Precalculation
5526 09:31:00.373761 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5527 09:31:00.377348 ==
5528 09:31:00.380358 Dram Type= 6, Freq= 0, CH_1, rank 0
5529 09:31:00.384145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 09:31:00.384228 ==
5531 09:31:00.387275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 09:31:00.394064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5533 09:31:00.397337 [CA 0] Center 38 (8~68) winsize 61
5534 09:31:00.400728 [CA 1] Center 37 (7~68) winsize 62
5535 09:31:00.404073 [CA 2] Center 35 (5~65) winsize 61
5536 09:31:00.407245 [CA 3] Center 35 (5~65) winsize 61
5537 09:31:00.410568 [CA 4] Center 35 (5~65) winsize 61
5538 09:31:00.414044 [CA 5] Center 34 (5~64) winsize 60
5539 09:31:00.414191
5540 09:31:00.417094 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5541 09:31:00.417240
5542 09:31:00.420425 [CATrainingPosCal] consider 1 rank data
5543 09:31:00.423912 u2DelayCellTimex100 = 270/100 ps
5544 09:31:00.427205 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5545 09:31:00.430477 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5546 09:31:00.437161 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5547 09:31:00.440799 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5548 09:31:00.444138 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5549 09:31:00.447606 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5550 09:31:00.447686
5551 09:31:00.450593 CA PerBit enable=1, Macro0, CA PI delay=34
5552 09:31:00.450674
5553 09:31:00.453917 [CBTSetCACLKResult] CA Dly = 34
5554 09:31:00.454000 CS Dly: 6 (0~37)
5555 09:31:00.454063 ==
5556 09:31:00.456839 Dram Type= 6, Freq= 0, CH_1, rank 1
5557 09:31:00.464011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 09:31:00.464093 ==
5559 09:31:00.466998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 09:31:00.473497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5561 09:31:00.477222 [CA 0] Center 38 (7~69) winsize 63
5562 09:31:00.480728 [CA 1] Center 38 (7~69) winsize 63
5563 09:31:00.483825 [CA 2] Center 36 (6~66) winsize 61
5564 09:31:00.487313 [CA 3] Center 35 (6~65) winsize 60
5565 09:31:00.490336 [CA 4] Center 35 (5~65) winsize 61
5566 09:31:00.493949 [CA 5] Center 34 (4~64) winsize 61
5567 09:31:00.494045
5568 09:31:00.497333 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5569 09:31:00.497416
5570 09:31:00.500592 [CATrainingPosCal] consider 2 rank data
5571 09:31:00.504055 u2DelayCellTimex100 = 270/100 ps
5572 09:31:00.506976 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5573 09:31:00.513610 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5574 09:31:00.516845 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5575 09:31:00.520507 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5576 09:31:00.523434 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5577 09:31:00.527039 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5578 09:31:00.527121
5579 09:31:00.530406 CA PerBit enable=1, Macro0, CA PI delay=34
5580 09:31:00.530488
5581 09:31:00.533513 [CBTSetCACLKResult] CA Dly = 34
5582 09:31:00.533596 CS Dly: 7 (0~39)
5583 09:31:00.537131
5584 09:31:00.540424 ----->DramcWriteLeveling(PI) begin...
5585 09:31:00.540512 ==
5586 09:31:00.543982 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 09:31:00.546953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 09:31:00.547038 ==
5589 09:31:00.550451 Write leveling (Byte 0): 27 => 27
5590 09:31:00.553494 Write leveling (Byte 1): 28 => 28
5591 09:31:00.557117 DramcWriteLeveling(PI) end<-----
5592 09:31:00.557200
5593 09:31:00.557264 ==
5594 09:31:00.560445 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 09:31:00.563376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 09:31:00.563460 ==
5597 09:31:00.566812 [Gating] SW mode calibration
5598 09:31:00.573489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5599 09:31:00.579914 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5600 09:31:00.583482 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 09:31:00.586879 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 09:31:00.593666 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 09:31:00.596777 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 09:31:00.599950 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 09:31:00.607155 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 09:31:00.610009 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5607 09:31:00.613600 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5608 09:31:00.616891 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 09:31:00.624142 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 09:31:00.627376 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 09:31:00.630872 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 09:31:00.637531 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 09:31:00.640614 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 09:31:00.643711 0 15 24 | B1->B0 | 2a29 2e2e | 1 0 | (1 1) (0 0)
5615 09:31:00.650701 0 15 28 | B1->B0 | 3d3d 4242 | 0 0 | (1 1) (0 0)
5616 09:31:00.653996 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 09:31:00.656986 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 09:31:00.664191 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 09:31:00.667527 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 09:31:00.670660 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 09:31:00.677444 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 09:31:00.680404 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5623 09:31:00.683704 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 09:31:00.690328 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 09:31:00.693220 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 09:31:00.696830 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 09:31:00.703893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 09:31:00.706847 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 09:31:00.710196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 09:31:00.716820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 09:31:00.719842 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 09:31:00.723385 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 09:31:00.726684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 09:31:00.733914 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 09:31:00.737136 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 09:31:00.740070 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 09:31:00.746598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:31:00.750736 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5639 09:31:00.753839 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 09:31:00.756848 Total UI for P1: 0, mck2ui 16
5641 09:31:00.760661 best dqsien dly found for B0: ( 1, 2, 24)
5642 09:31:00.763505 Total UI for P1: 0, mck2ui 16
5643 09:31:00.766938 best dqsien dly found for B1: ( 1, 2, 26)
5644 09:31:00.770455 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5645 09:31:00.773292 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5646 09:31:00.777193
5647 09:31:00.780068 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5648 09:31:00.783871 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5649 09:31:00.787104 [Gating] SW calibration Done
5650 09:31:00.787629 ==
5651 09:31:00.790658 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 09:31:00.793809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 09:31:00.794239 ==
5654 09:31:00.794578 RX Vref Scan: 0
5655 09:31:00.794891
5656 09:31:00.796981 RX Vref 0 -> 0, step: 1
5657 09:31:00.797544
5658 09:31:00.800323 RX Delay -80 -> 252, step: 8
5659 09:31:00.803762 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5660 09:31:00.807295 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5661 09:31:00.810278 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5662 09:31:00.816901 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5663 09:31:00.820236 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5664 09:31:00.823443 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5665 09:31:00.827277 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5666 09:31:00.830239 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5667 09:31:00.833541 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5668 09:31:00.840203 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5669 09:31:00.843611 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5670 09:31:00.846976 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5671 09:31:00.850341 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5672 09:31:00.853787 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5673 09:31:00.857035 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5674 09:31:00.863407 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5675 09:31:00.863833 ==
5676 09:31:00.867201 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 09:31:00.870003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 09:31:00.870436 ==
5679 09:31:00.870776 DQS Delay:
5680 09:31:00.873580 DQS0 = 0, DQS1 = 0
5681 09:31:00.874004 DQM Delay:
5682 09:31:00.876721 DQM0 = 102, DQM1 = 95
5683 09:31:00.877180 DQ Delay:
5684 09:31:00.879925 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5685 09:31:00.883547 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5686 09:31:00.886777 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5687 09:31:00.890381 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5688 09:31:00.890900
5689 09:31:00.891239
5690 09:31:00.891549 ==
5691 09:31:00.893267 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 09:31:00.897031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 09:31:00.899852 ==
5694 09:31:00.900280
5695 09:31:00.900609
5696 09:31:00.900917 TX Vref Scan disable
5697 09:31:00.903576 == TX Byte 0 ==
5698 09:31:00.907099 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5699 09:31:00.909942 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5700 09:31:00.913034 == TX Byte 1 ==
5701 09:31:00.916871 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5702 09:31:00.919761 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5703 09:31:00.923127 ==
5704 09:31:00.926363 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 09:31:00.929881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 09:31:00.930407 ==
5707 09:31:00.930750
5708 09:31:00.931062
5709 09:31:00.932995 TX Vref Scan disable
5710 09:31:00.933460 == TX Byte 0 ==
5711 09:31:00.939589 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 09:31:00.943224 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 09:31:00.943649 == TX Byte 1 ==
5714 09:31:00.949419 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5715 09:31:00.953342 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5716 09:31:00.953880
5717 09:31:00.954221 [DATLAT]
5718 09:31:00.956407 Freq=933, CH1 RK0
5719 09:31:00.956832
5720 09:31:00.957186 DATLAT Default: 0xd
5721 09:31:00.959743 0, 0xFFFF, sum = 0
5722 09:31:00.960214 1, 0xFFFF, sum = 0
5723 09:31:00.963242 2, 0xFFFF, sum = 0
5724 09:31:00.963673 3, 0xFFFF, sum = 0
5725 09:31:00.966597 4, 0xFFFF, sum = 0
5726 09:31:00.967099 5, 0xFFFF, sum = 0
5727 09:31:00.969900 6, 0xFFFF, sum = 0
5728 09:31:00.970427 7, 0xFFFF, sum = 0
5729 09:31:00.973464 8, 0xFFFF, sum = 0
5730 09:31:00.973996 9, 0xFFFF, sum = 0
5731 09:31:00.976292 10, 0x0, sum = 1
5732 09:31:00.976724 11, 0x0, sum = 2
5733 09:31:00.980084 12, 0x0, sum = 3
5734 09:31:00.980612 13, 0x0, sum = 4
5735 09:31:00.983008 best_step = 11
5736 09:31:00.983433
5737 09:31:00.983769 ==
5738 09:31:00.986235 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 09:31:00.989469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 09:31:00.989996 ==
5741 09:31:00.992825 RX Vref Scan: 1
5742 09:31:00.993290
5743 09:31:00.993630 RX Vref 0 -> 0, step: 1
5744 09:31:00.993948
5745 09:31:00.996575 RX Delay -53 -> 252, step: 4
5746 09:31:00.997165
5747 09:31:00.999441 Set Vref, RX VrefLevel [Byte0]: 53
5748 09:31:01.002723 [Byte1]: 53
5749 09:31:01.007342
5750 09:31:01.007867 Final RX Vref Byte 0 = 53 to rank0
5751 09:31:01.010361 Final RX Vref Byte 1 = 53 to rank0
5752 09:31:01.013463 Final RX Vref Byte 0 = 53 to rank1
5753 09:31:01.017141 Final RX Vref Byte 1 = 53 to rank1==
5754 09:31:01.020195 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 09:31:01.027184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 09:31:01.027711 ==
5757 09:31:01.028050 DQS Delay:
5758 09:31:01.028362 DQS0 = 0, DQS1 = 0
5759 09:31:01.030253 DQM Delay:
5760 09:31:01.030772 DQM0 = 104, DQM1 = 97
5761 09:31:01.033610 DQ Delay:
5762 09:31:01.036794 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5763 09:31:01.040086 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5764 09:31:01.043517 DQ8 =86, DQ9 =84, DQ10 =102, DQ11 =92
5765 09:31:01.046633 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5766 09:31:01.047063
5767 09:31:01.047463
5768 09:31:01.053708 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5769 09:31:01.056748 CH1 RK0: MR19=505, MR18=1D35
5770 09:31:01.063241 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5771 09:31:01.063671
5772 09:31:01.066861 ----->DramcWriteLeveling(PI) begin...
5773 09:31:01.067294 ==
5774 09:31:01.069984 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 09:31:01.073541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 09:31:01.073968 ==
5777 09:31:01.076683 Write leveling (Byte 0): 29 => 29
5778 09:31:01.079980 Write leveling (Byte 1): 29 => 29
5779 09:31:01.083608 DramcWriteLeveling(PI) end<-----
5780 09:31:01.084126
5781 09:31:01.084465 ==
5782 09:31:01.086602 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 09:31:01.093362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 09:31:01.093888 ==
5785 09:31:01.094228 [Gating] SW mode calibration
5786 09:31:01.103380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 09:31:01.106996 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 09:31:01.113380 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 09:31:01.116214 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 09:31:01.119767 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 09:31:01.123182 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 09:31:01.129871 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 09:31:01.132840 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 09:31:01.136578 0 14 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 0)
5795 09:31:01.142979 0 14 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5796 09:31:01.146650 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 09:31:01.149759 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 09:31:01.156210 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 09:31:01.159781 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 09:31:01.162996 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 09:31:01.169319 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 09:31:01.172825 0 15 24 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
5803 09:31:01.176032 0 15 28 | B1->B0 | 4141 3f3e | 0 1 | (0 0) (0 0)
5804 09:31:01.182791 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 09:31:01.185947 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 09:31:01.189622 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 09:31:01.196212 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 09:31:01.199533 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 09:31:01.202958 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 09:31:01.209814 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5811 09:31:01.212731 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5812 09:31:01.216416 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 09:31:01.222593 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 09:31:01.225666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 09:31:01.229316 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 09:31:01.235658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 09:31:01.239100 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 09:31:01.243037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 09:31:01.246197 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 09:31:01.252792 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 09:31:01.256575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 09:31:01.259624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 09:31:01.266196 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 09:31:01.269450 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 09:31:01.272770 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 09:31:01.279468 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 09:31:01.282676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5828 09:31:01.285825 Total UI for P1: 0, mck2ui 16
5829 09:31:01.289305 best dqsien dly found for B1: ( 1, 2, 26)
5830 09:31:01.292471 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 09:31:01.296050 Total UI for P1: 0, mck2ui 16
5832 09:31:01.298951 best dqsien dly found for B0: ( 1, 2, 28)
5833 09:31:01.302119 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5834 09:31:01.305893 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5835 09:31:01.306416
5836 09:31:01.312833 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5837 09:31:01.315932 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5838 09:31:01.318803 [Gating] SW calibration Done
5839 09:31:01.319232 ==
5840 09:31:01.322639 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 09:31:01.325577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 09:31:01.326006 ==
5843 09:31:01.326341 RX Vref Scan: 0
5844 09:31:01.326655
5845 09:31:01.328762 RX Vref 0 -> 0, step: 1
5846 09:31:01.329226
5847 09:31:01.332712 RX Delay -80 -> 252, step: 8
5848 09:31:01.335782 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5849 09:31:01.339066 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5850 09:31:01.342581 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5851 09:31:01.349054 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5852 09:31:01.352416 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5853 09:31:01.355664 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5854 09:31:01.358762 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5855 09:31:01.362479 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5856 09:31:01.365442 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5857 09:31:01.372611 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5858 09:31:01.375746 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5859 09:31:01.379366 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5860 09:31:01.382139 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5861 09:31:01.385394 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5862 09:31:01.389001 iDelay=200, Bit 14, Center 99 (0 ~ 199) 200
5863 09:31:01.395451 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5864 09:31:01.395961 ==
5865 09:31:01.398788 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 09:31:01.401890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 09:31:01.402317 ==
5868 09:31:01.402655 DQS Delay:
5869 09:31:01.405395 DQS0 = 0, DQS1 = 0
5870 09:31:01.405816 DQM Delay:
5871 09:31:01.409282 DQM0 = 100, DQM1 = 96
5872 09:31:01.409797 DQ Delay:
5873 09:31:01.412351 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5874 09:31:01.415386 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =99
5875 09:31:01.419014 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5876 09:31:01.421850 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5877 09:31:01.422391
5878 09:31:01.422733
5879 09:31:01.423046 ==
5880 09:31:01.425290 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 09:31:01.431934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 09:31:01.432460 ==
5883 09:31:01.432800
5884 09:31:01.433148
5885 09:31:01.433452 TX Vref Scan disable
5886 09:31:01.435539 == TX Byte 0 ==
5887 09:31:01.438828 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5888 09:31:01.441849 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5889 09:31:01.445409 == TX Byte 1 ==
5890 09:31:01.448568 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 09:31:01.452094 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 09:31:01.455100 ==
5893 09:31:01.458764 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 09:31:01.462244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 09:31:01.462940 ==
5896 09:31:01.463557
5897 09:31:01.464168
5898 09:31:01.465310 TX Vref Scan disable
5899 09:31:01.465811 == TX Byte 0 ==
5900 09:31:01.472073 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5901 09:31:01.475577 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5902 09:31:01.476101 == TX Byte 1 ==
5903 09:31:01.481747 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5904 09:31:01.485186 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5905 09:31:01.485613
5906 09:31:01.486103 [DATLAT]
5907 09:31:01.488899 Freq=933, CH1 RK1
5908 09:31:01.489363
5909 09:31:01.489718 DATLAT Default: 0xb
5910 09:31:01.491709 0, 0xFFFF, sum = 0
5911 09:31:01.492279 1, 0xFFFF, sum = 0
5912 09:31:01.495231 2, 0xFFFF, sum = 0
5913 09:31:01.495666 3, 0xFFFF, sum = 0
5914 09:31:01.498580 4, 0xFFFF, sum = 0
5915 09:31:01.499027 5, 0xFFFF, sum = 0
5916 09:31:01.501799 6, 0xFFFF, sum = 0
5917 09:31:01.502370 7, 0xFFFF, sum = 0
5918 09:31:01.505358 8, 0xFFFF, sum = 0
5919 09:31:01.508818 9, 0xFFFF, sum = 0
5920 09:31:01.509456 10, 0x0, sum = 1
5921 09:31:01.509805 11, 0x0, sum = 2
5922 09:31:01.511764 12, 0x0, sum = 3
5923 09:31:01.512193 13, 0x0, sum = 4
5924 09:31:01.515145 best_step = 11
5925 09:31:01.515660
5926 09:31:01.515997 ==
5927 09:31:01.518388 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 09:31:01.522062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 09:31:01.522585 ==
5930 09:31:01.524887 RX Vref Scan: 0
5931 09:31:01.525342
5932 09:31:01.525675 RX Vref 0 -> 0, step: 1
5933 09:31:01.525988
5934 09:31:01.528104 RX Delay -53 -> 252, step: 4
5935 09:31:01.535873 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5936 09:31:01.539252 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5937 09:31:01.542378 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5938 09:31:01.545904 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5939 09:31:01.549096 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5940 09:31:01.555741 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5941 09:31:01.559166 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5942 09:31:01.562215 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5943 09:31:01.565853 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5944 09:31:01.569544 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5945 09:31:01.572767 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5946 09:31:01.579370 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5947 09:31:01.582139 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5948 09:31:01.585544 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5949 09:31:01.589024 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5950 09:31:01.595539 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5951 09:31:01.596053 ==
5952 09:31:01.598599 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 09:31:01.601904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 09:31:01.602367 ==
5955 09:31:01.602749 DQS Delay:
5956 09:31:01.605299 DQS0 = 0, DQS1 = 0
5957 09:31:01.605719 DQM Delay:
5958 09:31:01.608512 DQM0 = 104, DQM1 = 97
5959 09:31:01.608972 DQ Delay:
5960 09:31:01.611737 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5961 09:31:01.614940 DQ4 =106, DQ5 =116, DQ6 =110, DQ7 =102
5962 09:31:01.618599 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5963 09:31:01.621565 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5964 09:31:01.621991
5965 09:31:01.622319
5966 09:31:01.631775 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5967 09:31:01.632310 CH1 RK1: MR19=504, MR18=20FC
5968 09:31:01.638550 CH1_RK1: MR19=0x504, MR18=0x20FC, DQSOSC=411, MR23=63, INC=64, DEC=42
5969 09:31:01.641790 [RxdqsGatingPostProcess] freq 933
5970 09:31:01.648581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 09:31:01.651969 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 09:31:01.654906 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 09:31:01.658652 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 09:31:01.661787 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 09:31:01.665243 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 09:31:01.668781 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 09:31:01.671930 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 09:31:01.672458 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 09:31:01.675375 Pre-setting of DQS Precalculation
5980 09:31:01.681703 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 09:31:01.688700 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 09:31:01.695181 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 09:31:01.695706
5984 09:31:01.696040
5985 09:31:01.698643 [Calibration Summary] 1866 Mbps
5986 09:31:01.701682 CH 0, Rank 0
5987 09:31:01.702108 SW Impedance : PASS
5988 09:31:01.704863 DUTY Scan : NO K
5989 09:31:01.705338 ZQ Calibration : PASS
5990 09:31:01.708086 Jitter Meter : NO K
5991 09:31:01.711588 CBT Training : PASS
5992 09:31:01.712008 Write leveling : PASS
5993 09:31:01.715246 RX DQS gating : PASS
5994 09:31:01.718154 RX DQ/DQS(RDDQC) : PASS
5995 09:31:01.718579 TX DQ/DQS : PASS
5996 09:31:01.721455 RX DATLAT : PASS
5997 09:31:01.724921 RX DQ/DQS(Engine): PASS
5998 09:31:01.725508 TX OE : NO K
5999 09:31:01.728297 All Pass.
6000 09:31:01.728817
6001 09:31:01.729221 CH 0, Rank 1
6002 09:31:01.731708 SW Impedance : PASS
6003 09:31:01.732234 DUTY Scan : NO K
6004 09:31:01.735037 ZQ Calibration : PASS
6005 09:31:01.738398 Jitter Meter : NO K
6006 09:31:01.738913 CBT Training : PASS
6007 09:31:01.741665 Write leveling : PASS
6008 09:31:01.745038 RX DQS gating : PASS
6009 09:31:01.745697 RX DQ/DQS(RDDQC) : PASS
6010 09:31:01.748370 TX DQ/DQS : PASS
6011 09:31:01.751929 RX DATLAT : PASS
6012 09:31:01.752468 RX DQ/DQS(Engine): PASS
6013 09:31:01.754836 TX OE : NO K
6014 09:31:01.755349 All Pass.
6015 09:31:01.755687
6016 09:31:01.758554 CH 1, Rank 0
6017 09:31:01.759075 SW Impedance : PASS
6018 09:31:01.761397 DUTY Scan : NO K
6019 09:31:01.761817 ZQ Calibration : PASS
6020 09:31:01.764956 Jitter Meter : NO K
6021 09:31:01.768785 CBT Training : PASS
6022 09:31:01.769342 Write leveling : PASS
6023 09:31:01.771872 RX DQS gating : PASS
6024 09:31:01.775454 RX DQ/DQS(RDDQC) : PASS
6025 09:31:01.775976 TX DQ/DQS : PASS
6026 09:31:01.777964 RX DATLAT : PASS
6027 09:31:01.781749 RX DQ/DQS(Engine): PASS
6028 09:31:01.782269 TX OE : NO K
6029 09:31:01.784975 All Pass.
6030 09:31:01.785496
6031 09:31:01.785834 CH 1, Rank 1
6032 09:31:01.788669 SW Impedance : PASS
6033 09:31:01.789237 DUTY Scan : NO K
6034 09:31:01.791500 ZQ Calibration : PASS
6035 09:31:01.794594 Jitter Meter : NO K
6036 09:31:01.795015 CBT Training : PASS
6037 09:31:01.798281 Write leveling : PASS
6038 09:31:01.798802 RX DQS gating : PASS
6039 09:31:01.801697 RX DQ/DQS(RDDQC) : PASS
6040 09:31:01.804769 TX DQ/DQS : PASS
6041 09:31:01.805242 RX DATLAT : PASS
6042 09:31:01.808579 RX DQ/DQS(Engine): PASS
6043 09:31:01.811400 TX OE : NO K
6044 09:31:01.811822 All Pass.
6045 09:31:01.812152
6046 09:31:01.814784 DramC Write-DBI off
6047 09:31:01.815205 PER_BANK_REFRESH: Hybrid Mode
6048 09:31:01.818158 TX_TRACKING: ON
6049 09:31:01.828350 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 09:31:01.831652 [FAST_K] Save calibration result to emmc
6051 09:31:01.834549 dramc_set_vcore_voltage set vcore to 650000
6052 09:31:01.834973 Read voltage for 400, 6
6053 09:31:01.838502 Vio18 = 0
6054 09:31:01.839030 Vcore = 650000
6055 09:31:01.839369 Vdram = 0
6056 09:31:01.841580 Vddq = 0
6057 09:31:01.842016 Vmddr = 0
6058 09:31:01.845320 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 09:31:01.851356 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 09:31:01.854945 MEM_TYPE=3, freq_sel=20
6061 09:31:01.858003 sv_algorithm_assistance_LP4_800
6062 09:31:01.861369 ============ PULL DRAM RESETB DOWN ============
6063 09:31:01.865045 ========== PULL DRAM RESETB DOWN end =========
6064 09:31:01.871821 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 09:31:01.872341 ===================================
6066 09:31:01.874930 LPDDR4 DRAM CONFIGURATION
6067 09:31:01.878459 ===================================
6068 09:31:01.881557 EX_ROW_EN[0] = 0x0
6069 09:31:01.882077 EX_ROW_EN[1] = 0x0
6070 09:31:01.885155 LP4Y_EN = 0x0
6071 09:31:01.885675 WORK_FSP = 0x0
6072 09:31:01.887909 WL = 0x2
6073 09:31:01.888328 RL = 0x2
6074 09:31:01.891428 BL = 0x2
6075 09:31:01.891946 RPST = 0x0
6076 09:31:01.894697 RD_PRE = 0x0
6077 09:31:01.897827 WR_PRE = 0x1
6078 09:31:01.898247 WR_PST = 0x0
6079 09:31:01.901469 DBI_WR = 0x0
6080 09:31:01.901890 DBI_RD = 0x0
6081 09:31:01.904522 OTF = 0x1
6082 09:31:01.908149 ===================================
6083 09:31:01.911556 ===================================
6084 09:31:01.912082 ANA top config
6085 09:31:01.914875 ===================================
6086 09:31:01.917763 DLL_ASYNC_EN = 0
6087 09:31:01.918185 ALL_SLAVE_EN = 1
6088 09:31:01.921174 NEW_RANK_MODE = 1
6089 09:31:01.924515 DLL_IDLE_MODE = 1
6090 09:31:01.927524 LP45_APHY_COMB_EN = 1
6091 09:31:01.931402 TX_ODT_DIS = 1
6092 09:31:01.931921 NEW_8X_MODE = 1
6093 09:31:01.934164 ===================================
6094 09:31:01.937782 ===================================
6095 09:31:01.941336 data_rate = 800
6096 09:31:01.944659 CKR = 1
6097 09:31:01.947607 DQ_P2S_RATIO = 4
6098 09:31:01.950861 ===================================
6099 09:31:01.954628 CA_P2S_RATIO = 4
6100 09:31:01.957969 DQ_CA_OPEN = 0
6101 09:31:01.958394 DQ_SEMI_OPEN = 1
6102 09:31:01.960911 CA_SEMI_OPEN = 1
6103 09:31:01.964478 CA_FULL_RATE = 0
6104 09:31:01.967466 DQ_CKDIV4_EN = 0
6105 09:31:01.971527 CA_CKDIV4_EN = 1
6106 09:31:01.974527 CA_PREDIV_EN = 0
6107 09:31:01.975051 PH8_DLY = 0
6108 09:31:01.977639 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 09:31:01.981316 DQ_AAMCK_DIV = 0
6110 09:31:01.983908 CA_AAMCK_DIV = 0
6111 09:31:01.987617 CA_ADMCK_DIV = 4
6112 09:31:01.991153 DQ_TRACK_CA_EN = 0
6113 09:31:01.991671 CA_PICK = 800
6114 09:31:01.993946 CA_MCKIO = 400
6115 09:31:01.997855 MCKIO_SEMI = 400
6116 09:31:02.000773 PLL_FREQ = 3016
6117 09:31:02.004172 DQ_UI_PI_RATIO = 32
6118 09:31:02.007351 CA_UI_PI_RATIO = 32
6119 09:31:02.010758 ===================================
6120 09:31:02.013659 ===================================
6121 09:31:02.017211 memory_type:LPDDR4
6122 09:31:02.017626 GP_NUM : 10
6123 09:31:02.020705 SRAM_EN : 1
6124 09:31:02.021263 MD32_EN : 0
6125 09:31:02.024126 ===================================
6126 09:31:02.027322 [ANA_INIT] >>>>>>>>>>>>>>
6127 09:31:02.030708 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 09:31:02.033870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 09:31:02.036910 ===================================
6130 09:31:02.040369 data_rate = 800,PCW = 0X7400
6131 09:31:02.043813 ===================================
6132 09:31:02.046872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 09:31:02.053707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 09:31:02.063865 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 09:31:02.067041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 09:31:02.070511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 09:31:02.073803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 09:31:02.076780 [ANA_INIT] flow start
6139 09:31:02.080404 [ANA_INIT] PLL >>>>>>>>
6140 09:31:02.080919 [ANA_INIT] PLL <<<<<<<<
6141 09:31:02.083456 [ANA_INIT] MIDPI >>>>>>>>
6142 09:31:02.086900 [ANA_INIT] MIDPI <<<<<<<<
6143 09:31:02.090016 [ANA_INIT] DLL >>>>>>>>
6144 09:31:02.090533 [ANA_INIT] flow end
6145 09:31:02.093419 ============ LP4 DIFF to SE enter ============
6146 09:31:02.100289 ============ LP4 DIFF to SE exit ============
6147 09:31:02.100810 [ANA_INIT] <<<<<<<<<<<<<
6148 09:31:02.103127 [Flow] Enable top DCM control >>>>>
6149 09:31:02.106779 [Flow] Enable top DCM control <<<<<
6150 09:31:02.109729 Enable DLL master slave shuffle
6151 09:31:02.116761 ==============================================================
6152 09:31:02.117357 Gating Mode config
6153 09:31:02.123311 ==============================================================
6154 09:31:02.126289 Config description:
6155 09:31:02.136775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 09:31:02.143058 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 09:31:02.146615 SELPH_MODE 0: By rank 1: By Phase
6158 09:31:02.153390 ==============================================================
6159 09:31:02.156454 GAT_TRACK_EN = 0
6160 09:31:02.157025 RX_GATING_MODE = 2
6161 09:31:02.159795 RX_GATING_TRACK_MODE = 2
6162 09:31:02.162939 SELPH_MODE = 1
6163 09:31:02.166172 PICG_EARLY_EN = 1
6164 09:31:02.169775 VALID_LAT_VALUE = 1
6165 09:31:02.176368 ==============================================================
6166 09:31:02.179736 Enter into Gating configuration >>>>
6167 09:31:02.183170 Exit from Gating configuration <<<<
6168 09:31:02.186450 Enter into DVFS_PRE_config >>>>>
6169 09:31:02.196565 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 09:31:02.200134 Exit from DVFS_PRE_config <<<<<
6171 09:31:02.202925 Enter into PICG configuration >>>>
6172 09:31:02.206434 Exit from PICG configuration <<<<
6173 09:31:02.209469 [RX_INPUT] configuration >>>>>
6174 09:31:02.213094 [RX_INPUT] configuration <<<<<
6175 09:31:02.216476 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 09:31:02.223183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 09:31:02.229913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 09:31:02.232844 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 09:31:02.239692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 09:31:02.246695 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 09:31:02.249666 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 09:31:02.252793 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 09:31:02.259592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 09:31:02.262667 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 09:31:02.266066 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 09:31:02.273291 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 09:31:02.276113 ===================================
6188 09:31:02.276645 LPDDR4 DRAM CONFIGURATION
6189 09:31:02.279551 ===================================
6190 09:31:02.282531 EX_ROW_EN[0] = 0x0
6191 09:31:02.285939 EX_ROW_EN[1] = 0x0
6192 09:31:02.286457 LP4Y_EN = 0x0
6193 09:31:02.289674 WORK_FSP = 0x0
6194 09:31:02.290193 WL = 0x2
6195 09:31:02.292670 RL = 0x2
6196 09:31:02.293127 BL = 0x2
6197 09:31:02.296093 RPST = 0x0
6198 09:31:02.296534 RD_PRE = 0x0
6199 09:31:02.299136 WR_PRE = 0x1
6200 09:31:02.299553 WR_PST = 0x0
6201 09:31:02.302290 DBI_WR = 0x0
6202 09:31:02.302712 DBI_RD = 0x0
6203 09:31:02.305748 OTF = 0x1
6204 09:31:02.309303 ===================================
6205 09:31:02.312386 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 09:31:02.316113 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 09:31:02.322950 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 09:31:02.325735 ===================================
6209 09:31:02.326161 LPDDR4 DRAM CONFIGURATION
6210 09:31:02.328907 ===================================
6211 09:31:02.332849 EX_ROW_EN[0] = 0x10
6212 09:31:02.333418 EX_ROW_EN[1] = 0x0
6213 09:31:02.335640 LP4Y_EN = 0x0
6214 09:31:02.339143 WORK_FSP = 0x0
6215 09:31:02.339571 WL = 0x2
6216 09:31:02.342214 RL = 0x2
6217 09:31:02.342634 BL = 0x2
6218 09:31:02.345947 RPST = 0x0
6219 09:31:02.346466 RD_PRE = 0x0
6220 09:31:02.349285 WR_PRE = 0x1
6221 09:31:02.349810 WR_PST = 0x0
6222 09:31:02.352355 DBI_WR = 0x0
6223 09:31:02.352774 DBI_RD = 0x0
6224 09:31:02.355831 OTF = 0x1
6225 09:31:02.359451 ===================================
6226 09:31:02.365809 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 09:31:02.368837 nWR fixed to 30
6228 09:31:02.369329 [ModeRegInit_LP4] CH0 RK0
6229 09:31:02.372421 [ModeRegInit_LP4] CH0 RK1
6230 09:31:02.375599 [ModeRegInit_LP4] CH1 RK0
6231 09:31:02.376025 [ModeRegInit_LP4] CH1 RK1
6232 09:31:02.378697 match AC timing 19
6233 09:31:02.382317 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 09:31:02.385810 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 09:31:02.392617 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 09:31:02.395685 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 09:31:02.402202 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 09:31:02.402752 ==
6239 09:31:02.405437 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 09:31:02.409424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 09:31:02.409952 ==
6242 09:31:02.415479 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 09:31:02.419260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6244 09:31:02.422352 [CA 0] Center 36 (8~64) winsize 57
6245 09:31:02.425634 [CA 1] Center 36 (8~64) winsize 57
6246 09:31:02.429047 [CA 2] Center 36 (8~64) winsize 57
6247 09:31:02.432200 [CA 3] Center 36 (8~64) winsize 57
6248 09:31:02.435862 [CA 4] Center 36 (8~64) winsize 57
6249 09:31:02.438964 [CA 5] Center 36 (8~64) winsize 57
6250 09:31:02.439487
6251 09:31:02.442373 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6252 09:31:02.442794
6253 09:31:02.445400 [CATrainingPosCal] consider 1 rank data
6254 09:31:02.449273 u2DelayCellTimex100 = 270/100 ps
6255 09:31:02.451941 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 09:31:02.455344 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 09:31:02.458766 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 09:31:02.465523 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 09:31:02.468698 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 09:31:02.472519 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 09:31:02.473077
6262 09:31:02.475122 CA PerBit enable=1, Macro0, CA PI delay=36
6263 09:31:02.475543
6264 09:31:02.478396 [CBTSetCACLKResult] CA Dly = 36
6265 09:31:02.478818 CS Dly: 1 (0~32)
6266 09:31:02.479151 ==
6267 09:31:02.481878 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 09:31:02.488582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 09:31:02.489196 ==
6270 09:31:02.492097 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 09:31:02.498221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6272 09:31:02.501644 [CA 0] Center 36 (8~64) winsize 57
6273 09:31:02.505252 [CA 1] Center 36 (8~64) winsize 57
6274 09:31:02.508811 [CA 2] Center 36 (8~64) winsize 57
6275 09:31:02.511962 [CA 3] Center 36 (8~64) winsize 57
6276 09:31:02.515633 [CA 4] Center 36 (8~64) winsize 57
6277 09:31:02.518713 [CA 5] Center 36 (8~64) winsize 57
6278 09:31:02.519232
6279 09:31:02.522297 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6280 09:31:02.522820
6281 09:31:02.525155 [CATrainingPosCal] consider 2 rank data
6282 09:31:02.528228 u2DelayCellTimex100 = 270/100 ps
6283 09:31:02.531678 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 09:31:02.535379 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 09:31:02.538739 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 09:31:02.541650 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 09:31:02.545163 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 09:31:02.548453 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 09:31:02.552280
6290 09:31:02.555115 CA PerBit enable=1, Macro0, CA PI delay=36
6291 09:31:02.555637
6292 09:31:02.558870 [CBTSetCACLKResult] CA Dly = 36
6293 09:31:02.559394 CS Dly: 1 (0~32)
6294 09:31:02.559726
6295 09:31:02.561445 ----->DramcWriteLeveling(PI) begin...
6296 09:31:02.561941 ==
6297 09:31:02.565139 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 09:31:02.568193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 09:31:02.572211 ==
6300 09:31:02.572732 Write leveling (Byte 0): 40 => 8
6301 09:31:02.575144 Write leveling (Byte 1): 32 => 0
6302 09:31:02.578067 DramcWriteLeveling(PI) end<-----
6303 09:31:02.578487
6304 09:31:02.578816 ==
6305 09:31:02.581410 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 09:31:02.596976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 09:31:02.597435 ==
6308 09:31:02.597874 [Gating] SW mode calibration
6309 09:31:02.598587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 09:31:02.601553 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 09:31:02.604652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 09:31:02.611683 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 09:31:02.615002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 09:31:02.618127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 09:31:02.624919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 09:31:02.628572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 09:31:02.631736 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 09:31:02.638323 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 09:31:02.641361 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 09:31:02.645259 Total UI for P1: 0, mck2ui 16
6321 09:31:02.648399 best dqsien dly found for B0: ( 0, 14, 24)
6322 09:31:02.651878 Total UI for P1: 0, mck2ui 16
6323 09:31:02.654580 best dqsien dly found for B1: ( 0, 14, 24)
6324 09:31:02.658114 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 09:31:02.661618 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 09:31:02.662045
6327 09:31:02.664758 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 09:31:02.668436 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 09:31:02.671218 [Gating] SW calibration Done
6330 09:31:02.671635 ==
6331 09:31:02.674686 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 09:31:02.677835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 09:31:02.681414 ==
6334 09:31:02.681935 RX Vref Scan: 0
6335 09:31:02.682417
6336 09:31:02.684447 RX Vref 0 -> 0, step: 1
6337 09:31:02.684960
6338 09:31:02.687734 RX Delay -410 -> 252, step: 16
6339 09:31:02.691160 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6340 09:31:02.694594 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6341 09:31:02.697785 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6342 09:31:02.704325 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6343 09:31:02.707674 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6344 09:31:02.711100 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6345 09:31:02.714243 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6346 09:31:02.720805 iDelay=230, Bit 7, Center 5 (-218 ~ 229) 448
6347 09:31:02.723895 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6348 09:31:02.727661 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6349 09:31:02.730648 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6350 09:31:02.737511 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6351 09:31:02.740787 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6352 09:31:02.744464 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6353 09:31:02.747594 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6354 09:31:02.754404 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6355 09:31:02.754872 ==
6356 09:31:02.757406 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 09:31:02.761213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 09:31:02.761738 ==
6359 09:31:02.762072 DQS Delay:
6360 09:31:02.764463 DQS0 = 27, DQS1 = 43
6361 09:31:02.764875 DQM Delay:
6362 09:31:02.767841 DQM0 = 14, DQM1 = 12
6363 09:31:02.768361 DQ Delay:
6364 09:31:02.771221 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =0
6365 09:31:02.774477 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6366 09:31:02.777837 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6367 09:31:02.781379 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6368 09:31:02.781897
6369 09:31:02.782230
6370 09:31:02.782541 ==
6371 09:31:02.784072 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 09:31:02.787765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 09:31:02.788183 ==
6374 09:31:02.788510
6375 09:31:02.788810
6376 09:31:02.791127 TX Vref Scan disable
6377 09:31:02.794069 == TX Byte 0 ==
6378 09:31:02.797764 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 09:31:02.800961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 09:31:02.804606 == TX Byte 1 ==
6381 09:31:02.807769 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 09:31:02.810561 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 09:31:02.810977 ==
6384 09:31:02.814427 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 09:31:02.817399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 09:31:02.817813 ==
6387 09:31:02.821075
6388 09:31:02.821571
6389 09:31:02.821901 TX Vref Scan disable
6390 09:31:02.824343 == TX Byte 0 ==
6391 09:31:02.827451 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 09:31:02.830854 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 09:31:02.834242 == TX Byte 1 ==
6394 09:31:02.837354 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 09:31:02.840877 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 09:31:02.841437
6397 09:31:02.841770 [DATLAT]
6398 09:31:02.844166 Freq=400, CH0 RK0
6399 09:31:02.844676
6400 09:31:02.847758 DATLAT Default: 0xf
6401 09:31:02.848262 0, 0xFFFF, sum = 0
6402 09:31:02.850763 1, 0xFFFF, sum = 0
6403 09:31:02.851276 2, 0xFFFF, sum = 0
6404 09:31:02.854192 3, 0xFFFF, sum = 0
6405 09:31:02.854704 4, 0xFFFF, sum = 0
6406 09:31:02.857532 5, 0xFFFF, sum = 0
6407 09:31:02.858043 6, 0xFFFF, sum = 0
6408 09:31:02.860680 7, 0xFFFF, sum = 0
6409 09:31:02.861244 8, 0xFFFF, sum = 0
6410 09:31:02.864164 9, 0xFFFF, sum = 0
6411 09:31:02.864698 10, 0xFFFF, sum = 0
6412 09:31:02.867343 11, 0xFFFF, sum = 0
6413 09:31:02.867858 12, 0xFFFF, sum = 0
6414 09:31:02.870882 13, 0x0, sum = 1
6415 09:31:02.871492 14, 0x0, sum = 2
6416 09:31:02.874050 15, 0x0, sum = 3
6417 09:31:02.874471 16, 0x0, sum = 4
6418 09:31:02.877027 best_step = 14
6419 09:31:02.877435
6420 09:31:02.877756 ==
6421 09:31:02.880986 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 09:31:02.883840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 09:31:02.884347 ==
6424 09:31:02.887219 RX Vref Scan: 1
6425 09:31:02.887631
6426 09:31:02.887954 RX Vref 0 -> 0, step: 1
6427 09:31:02.888256
6428 09:31:02.890686 RX Delay -327 -> 252, step: 8
6429 09:31:02.891195
6430 09:31:02.893866 Set Vref, RX VrefLevel [Byte0]: 58
6431 09:31:02.897077 [Byte1]: 49
6432 09:31:02.901588
6433 09:31:02.902096 Final RX Vref Byte 0 = 58 to rank0
6434 09:31:02.905205 Final RX Vref Byte 1 = 49 to rank0
6435 09:31:02.907985 Final RX Vref Byte 0 = 58 to rank1
6436 09:31:02.912081 Final RX Vref Byte 1 = 49 to rank1==
6437 09:31:02.914543 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 09:31:02.921255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 09:31:02.921674 ==
6440 09:31:02.921996 DQS Delay:
6441 09:31:02.924485 DQS0 = 28, DQS1 = 48
6442 09:31:02.925093 DQM Delay:
6443 09:31:02.925633 DQM0 = 11, DQM1 = 15
6444 09:31:02.927886 DQ Delay:
6445 09:31:02.931188 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6446 09:31:02.931754 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6447 09:31:02.934550 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6448 09:31:02.937978 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6449 09:31:02.938449
6450 09:31:02.941024
6451 09:31:02.947572 [DQSOSCAuto] RK0, (LSB)MR18= 0xb4ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6452 09:31:02.951074 CH0 RK0: MR19=C0C, MR18=B4AC
6453 09:31:02.957687 CH0_RK0: MR19=0xC0C, MR18=0xB4AC, DQSOSC=387, MR23=63, INC=394, DEC=262
6454 09:31:02.957844 ==
6455 09:31:02.960777 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 09:31:02.964304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 09:31:02.964441 ==
6458 09:31:02.967393 [Gating] SW mode calibration
6459 09:31:02.974022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 09:31:02.980509 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 09:31:02.984061 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 09:31:02.987507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 09:31:02.994182 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 09:31:02.997199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 09:31:03.000777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 09:31:03.007666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 09:31:03.010770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 09:31:03.014046 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 09:31:03.017502 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 09:31:03.020847 Total UI for P1: 0, mck2ui 16
6471 09:31:03.024067 best dqsien dly found for B0: ( 0, 14, 24)
6472 09:31:03.027342 Total UI for P1: 0, mck2ui 16
6473 09:31:03.030718 best dqsien dly found for B1: ( 0, 14, 24)
6474 09:31:03.034484 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 09:31:03.041093 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 09:31:03.041540
6477 09:31:03.044322 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 09:31:03.047369 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 09:31:03.050904 [Gating] SW calibration Done
6480 09:31:03.051328 ==
6481 09:31:03.054067 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 09:31:03.057524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 09:31:03.057950 ==
6484 09:31:03.060487 RX Vref Scan: 0
6485 09:31:03.060911
6486 09:31:03.061291 RX Vref 0 -> 0, step: 1
6487 09:31:03.061609
6488 09:31:03.064077 RX Delay -410 -> 252, step: 16
6489 09:31:03.067183 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6490 09:31:03.074056 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6491 09:31:03.076985 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6492 09:31:03.080538 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6493 09:31:03.083828 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6494 09:31:03.090199 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6495 09:31:03.093783 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6496 09:31:03.096795 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6497 09:31:03.100368 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6498 09:31:03.106960 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6499 09:31:03.110374 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6500 09:31:03.113631 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6501 09:31:03.117123 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6502 09:31:03.123718 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6503 09:31:03.127120 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6504 09:31:03.130368 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6505 09:31:03.130614 ==
6506 09:31:03.133314 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 09:31:03.139972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 09:31:03.140270 ==
6509 09:31:03.140461 DQS Delay:
6510 09:31:03.143382 DQS0 = 27, DQS1 = 43
6511 09:31:03.143622 DQM Delay:
6512 09:31:03.143811 DQM0 = 9, DQM1 = 14
6513 09:31:03.146696 DQ Delay:
6514 09:31:03.150054 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6515 09:31:03.150354 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6516 09:31:03.153608 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6517 09:31:03.156717 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6518 09:31:03.157185
6519 09:31:03.157514
6520 09:31:03.160234 ==
6521 09:31:03.163873 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 09:31:03.166880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 09:31:03.167302 ==
6524 09:31:03.167634
6525 09:31:03.167942
6526 09:31:03.170070 TX Vref Scan disable
6527 09:31:03.170495 == TX Byte 0 ==
6528 09:31:03.173798 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6529 09:31:03.180360 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6530 09:31:03.180896 == TX Byte 1 ==
6531 09:31:03.183221 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6532 09:31:03.190079 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6533 09:31:03.190508 ==
6534 09:31:03.193514 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 09:31:03.196677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 09:31:03.197136 ==
6537 09:31:03.197475
6538 09:31:03.197788
6539 09:31:03.199796 TX Vref Scan disable
6540 09:31:03.200220 == TX Byte 0 ==
6541 09:31:03.203270 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6542 09:31:03.209887 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6543 09:31:03.210322 == TX Byte 1 ==
6544 09:31:03.213254 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6545 09:31:03.219998 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6546 09:31:03.220425
6547 09:31:03.220761 [DATLAT]
6548 09:31:03.221135 Freq=400, CH0 RK1
6549 09:31:03.221447
6550 09:31:03.223231 DATLAT Default: 0xe
6551 09:31:03.226389 0, 0xFFFF, sum = 0
6552 09:31:03.226825 1, 0xFFFF, sum = 0
6553 09:31:03.229852 2, 0xFFFF, sum = 0
6554 09:31:03.230162 3, 0xFFFF, sum = 0
6555 09:31:03.233113 4, 0xFFFF, sum = 0
6556 09:31:03.233348 5, 0xFFFF, sum = 0
6557 09:31:03.236298 6, 0xFFFF, sum = 0
6558 09:31:03.236533 7, 0xFFFF, sum = 0
6559 09:31:03.239495 8, 0xFFFF, sum = 0
6560 09:31:03.239699 9, 0xFFFF, sum = 0
6561 09:31:03.243028 10, 0xFFFF, sum = 0
6562 09:31:03.243189 11, 0xFFFF, sum = 0
6563 09:31:03.246220 12, 0xFFFF, sum = 0
6564 09:31:03.246378 13, 0x0, sum = 1
6565 09:31:03.249070 14, 0x0, sum = 2
6566 09:31:03.249205 15, 0x0, sum = 3
6567 09:31:03.252639 16, 0x0, sum = 4
6568 09:31:03.252762 best_step = 14
6569 09:31:03.252853
6570 09:31:03.252949 ==
6571 09:31:03.255954 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 09:31:03.262555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 09:31:03.262729 ==
6574 09:31:03.262815 RX Vref Scan: 0
6575 09:31:03.262890
6576 09:31:03.266317 RX Vref 0 -> 0, step: 1
6577 09:31:03.266479
6578 09:31:03.269269 RX Delay -327 -> 252, step: 8
6579 09:31:03.276116 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6580 09:31:03.279612 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6581 09:31:03.282666 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6582 09:31:03.286041 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6583 09:31:03.292525 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6584 09:31:03.295995 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6585 09:31:03.299007 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6586 09:31:03.302481 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6587 09:31:03.306055 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6588 09:31:03.312820 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6589 09:31:03.315771 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6590 09:31:03.319642 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6591 09:31:03.326426 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6592 09:31:03.329407 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6593 09:31:03.332897 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6594 09:31:03.336334 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6595 09:31:03.336651 ==
6596 09:31:03.339164 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 09:31:03.346157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 09:31:03.346628 ==
6599 09:31:03.346928 DQS Delay:
6600 09:31:03.349499 DQS0 = 28, DQS1 = 44
6601 09:31:03.349863 DQM Delay:
6602 09:31:03.353166 DQM0 = 10, DQM1 = 15
6603 09:31:03.353678 DQ Delay:
6604 09:31:03.355958 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6605 09:31:03.359176 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6606 09:31:03.359603 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6607 09:31:03.362432 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6608 09:31:03.366055
6609 09:31:03.366573
6610 09:31:03.373049 [DQSOSCAuto] RK1, (LSB)MR18= 0xb66a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6611 09:31:03.376720 CH0 RK1: MR19=C0C, MR18=B66A
6612 09:31:03.383296 CH0_RK1: MR19=0xC0C, MR18=0xB66A, DQSOSC=387, MR23=63, INC=394, DEC=262
6613 09:31:03.386327 [RxdqsGatingPostProcess] freq 400
6614 09:31:03.389887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 09:31:03.393050 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 09:31:03.396078 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 09:31:03.399321 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 09:31:03.402345 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 09:31:03.405775 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 09:31:03.409291 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 09:31:03.412988 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 09:31:03.416019 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 09:31:03.419529 Pre-setting of DQS Precalculation
6624 09:31:03.422336 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 09:31:03.422772 ==
6626 09:31:03.425877 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 09:31:03.432630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 09:31:03.433207 ==
6629 09:31:03.435989 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 09:31:03.442784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6631 09:31:03.445891 [CA 0] Center 36 (8~64) winsize 57
6632 09:31:03.449111 [CA 1] Center 36 (8~64) winsize 57
6633 09:31:03.452765 [CA 2] Center 36 (8~64) winsize 57
6634 09:31:03.455619 [CA 3] Center 36 (8~64) winsize 57
6635 09:31:03.458822 [CA 4] Center 36 (8~64) winsize 57
6636 09:31:03.462668 [CA 5] Center 36 (8~64) winsize 57
6637 09:31:03.463209
6638 09:31:03.465724 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6639 09:31:03.466160
6640 09:31:03.468841 [CATrainingPosCal] consider 1 rank data
6641 09:31:03.472508 u2DelayCellTimex100 = 270/100 ps
6642 09:31:03.476185 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 09:31:03.479172 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 09:31:03.482778 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 09:31:03.485712 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 09:31:03.489310 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 09:31:03.492499 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 09:31:03.493042
6649 09:31:03.499151 CA PerBit enable=1, Macro0, CA PI delay=36
6650 09:31:03.499587
6651 09:31:03.500015 [CBTSetCACLKResult] CA Dly = 36
6652 09:31:03.502588 CS Dly: 1 (0~32)
6653 09:31:03.503020 ==
6654 09:31:03.505414 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 09:31:03.509051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 09:31:03.509491 ==
6657 09:31:03.515674 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 09:31:03.522382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6659 09:31:03.525409 [CA 0] Center 36 (8~64) winsize 57
6660 09:31:03.529016 [CA 1] Center 36 (8~64) winsize 57
6661 09:31:03.532609 [CA 2] Center 36 (8~64) winsize 57
6662 09:31:03.533087 [CA 3] Center 36 (8~64) winsize 57
6663 09:31:03.535676 [CA 4] Center 36 (8~64) winsize 57
6664 09:31:03.538811 [CA 5] Center 36 (8~64) winsize 57
6665 09:31:03.539248
6666 09:31:03.545295 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6667 09:31:03.545734
6668 09:31:03.548836 [CATrainingPosCal] consider 2 rank data
6669 09:31:03.552075 u2DelayCellTimex100 = 270/100 ps
6670 09:31:03.555670 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 09:31:03.558958 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 09:31:03.562389 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 09:31:03.565482 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 09:31:03.568759 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 09:31:03.572091 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 09:31:03.572526
6677 09:31:03.575595 CA PerBit enable=1, Macro0, CA PI delay=36
6678 09:31:03.576131
6679 09:31:03.578952 [CBTSetCACLKResult] CA Dly = 36
6680 09:31:03.581812 CS Dly: 1 (0~32)
6681 09:31:03.582247
6682 09:31:03.585439 ----->DramcWriteLeveling(PI) begin...
6683 09:31:03.585880 ==
6684 09:31:03.588528 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 09:31:03.591984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 09:31:03.592420 ==
6687 09:31:03.595931 Write leveling (Byte 0): 40 => 8
6688 09:31:03.598642 Write leveling (Byte 1): 32 => 0
6689 09:31:03.601763 DramcWriteLeveling(PI) end<-----
6690 09:31:03.602196
6691 09:31:03.602624 ==
6692 09:31:03.605380 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 09:31:03.608726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 09:31:03.609303 ==
6695 09:31:03.612230 [Gating] SW mode calibration
6696 09:31:03.618909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 09:31:03.625788 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 09:31:03.628838 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 09:31:03.632158 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 09:31:03.638571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 09:31:03.642222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 09:31:03.645432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 09:31:03.652020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 09:31:03.655293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 09:31:03.659018 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 09:31:03.665576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 09:31:03.666136 Total UI for P1: 0, mck2ui 16
6708 09:31:03.672099 best dqsien dly found for B0: ( 0, 14, 24)
6709 09:31:03.672535 Total UI for P1: 0, mck2ui 16
6710 09:31:03.675496 best dqsien dly found for B1: ( 0, 14, 24)
6711 09:31:03.682083 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 09:31:03.685430 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 09:31:03.686005
6714 09:31:03.688386 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 09:31:03.691996 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 09:31:03.695331 [Gating] SW calibration Done
6717 09:31:03.695887 ==
6718 09:31:03.698063 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 09:31:03.701678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 09:31:03.702315 ==
6721 09:31:03.704813 RX Vref Scan: 0
6722 09:31:03.705365
6723 09:31:03.705699 RX Vref 0 -> 0, step: 1
6724 09:31:03.706066
6725 09:31:03.708620 RX Delay -410 -> 252, step: 16
6726 09:31:03.714724 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6727 09:31:03.718433 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6728 09:31:03.721303 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6729 09:31:03.725011 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6730 09:31:03.731196 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6731 09:31:03.734962 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6732 09:31:03.738297 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6733 09:31:03.741511 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6734 09:31:03.748380 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6735 09:31:03.752012 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6736 09:31:03.755129 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6737 09:31:03.758379 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6738 09:31:03.764919 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6739 09:31:03.768632 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6740 09:31:03.771344 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6741 09:31:03.774640 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6742 09:31:03.775058 ==
6743 09:31:03.778319 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 09:31:03.785122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 09:31:03.785637 ==
6746 09:31:03.785971 DQS Delay:
6747 09:31:03.788032 DQS0 = 27, DQS1 = 43
6748 09:31:03.788502 DQM Delay:
6749 09:31:03.791325 DQM0 = 7, DQM1 = 16
6750 09:31:03.791851 DQ Delay:
6751 09:31:03.794648 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6752 09:31:03.797999 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6753 09:31:03.798522 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6754 09:31:03.804776 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6755 09:31:03.805280
6756 09:31:03.805611
6757 09:31:03.805933 ==
6758 09:31:03.807460 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 09:31:03.811225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 09:31:03.811669 ==
6761 09:31:03.812066
6762 09:31:03.812567
6763 09:31:03.814381 TX Vref Scan disable
6764 09:31:03.814802 == TX Byte 0 ==
6765 09:31:03.818123 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 09:31:03.824867 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 09:31:03.825446 == TX Byte 1 ==
6768 09:31:03.827917 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6769 09:31:03.834628 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6770 09:31:03.835157 ==
6771 09:31:03.837782 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 09:31:03.841178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 09:31:03.841697 ==
6774 09:31:03.842035
6775 09:31:03.842346
6776 09:31:03.844261 TX Vref Scan disable
6777 09:31:03.844683 == TX Byte 0 ==
6778 09:31:03.851071 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 09:31:03.854687 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 09:31:03.855111 == TX Byte 1 ==
6781 09:31:03.861205 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6782 09:31:03.864826 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6783 09:31:03.865404
6784 09:31:03.865744 [DATLAT]
6785 09:31:03.867804 Freq=400, CH1 RK0
6786 09:31:03.868225
6787 09:31:03.868560 DATLAT Default: 0xf
6788 09:31:03.870959 0, 0xFFFF, sum = 0
6789 09:31:03.871387 1, 0xFFFF, sum = 0
6790 09:31:03.874860 2, 0xFFFF, sum = 0
6791 09:31:03.875394 3, 0xFFFF, sum = 0
6792 09:31:03.877636 4, 0xFFFF, sum = 0
6793 09:31:03.878062 5, 0xFFFF, sum = 0
6794 09:31:03.881420 6, 0xFFFF, sum = 0
6795 09:31:03.881959 7, 0xFFFF, sum = 0
6796 09:31:03.884486 8, 0xFFFF, sum = 0
6797 09:31:03.884917 9, 0xFFFF, sum = 0
6798 09:31:03.887642 10, 0xFFFF, sum = 0
6799 09:31:03.890978 11, 0xFFFF, sum = 0
6800 09:31:03.891526 12, 0xFFFF, sum = 0
6801 09:31:03.894382 13, 0x0, sum = 1
6802 09:31:03.894912 14, 0x0, sum = 2
6803 09:31:03.895253 15, 0x0, sum = 3
6804 09:31:03.897548 16, 0x0, sum = 4
6805 09:31:03.897978 best_step = 14
6806 09:31:03.898307
6807 09:31:03.898615 ==
6808 09:31:03.900964 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 09:31:03.907430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 09:31:03.907943 ==
6811 09:31:03.908276 RX Vref Scan: 1
6812 09:31:03.908583
6813 09:31:03.910975 RX Vref 0 -> 0, step: 1
6814 09:31:03.911308
6815 09:31:03.914309 RX Delay -327 -> 252, step: 8
6816 09:31:03.914838
6817 09:31:03.917582 Set Vref, RX VrefLevel [Byte0]: 53
6818 09:31:03.920634 [Byte1]: 53
6819 09:31:03.924505
6820 09:31:03.925090 Final RX Vref Byte 0 = 53 to rank0
6821 09:31:03.928091 Final RX Vref Byte 1 = 53 to rank0
6822 09:31:03.931064 Final RX Vref Byte 0 = 53 to rank1
6823 09:31:03.934352 Final RX Vref Byte 1 = 53 to rank1==
6824 09:31:03.937623 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 09:31:03.944446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 09:31:03.945153 ==
6827 09:31:03.945579 DQS Delay:
6828 09:31:03.947577 DQS0 = 32, DQS1 = 40
6829 09:31:03.948110 DQM Delay:
6830 09:31:03.948450 DQM0 = 12, DQM1 = 12
6831 09:31:03.951200 DQ Delay:
6832 09:31:03.954237 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6833 09:31:03.954769 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6834 09:31:03.957730 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6835 09:31:03.960798 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6836 09:31:03.961370
6837 09:31:03.961713
6838 09:31:03.971001 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6839 09:31:03.973703 CH1 RK0: MR19=C0C, MR18=94CF
6840 09:31:03.980594 CH1_RK0: MR19=0xC0C, MR18=0x94CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6841 09:31:03.981157 ==
6842 09:31:03.984130 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 09:31:03.987643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 09:31:03.988167 ==
6845 09:31:03.990513 [Gating] SW mode calibration
6846 09:31:03.997272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 09:31:04.000846 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 09:31:04.007258 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 09:31:04.010540 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 09:31:04.014206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 09:31:04.020827 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 09:31:04.023990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 09:31:04.027661 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 09:31:04.034117 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 09:31:04.037643 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 09:31:04.040716 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 09:31:04.043773 Total UI for P1: 0, mck2ui 16
6858 09:31:04.047308 best dqsien dly found for B0: ( 0, 14, 24)
6859 09:31:04.050657 Total UI for P1: 0, mck2ui 16
6860 09:31:04.053899 best dqsien dly found for B1: ( 0, 14, 24)
6861 09:31:04.057362 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 09:31:04.060628 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 09:31:04.061178
6864 09:31:04.066957 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 09:31:04.070847 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 09:31:04.073602 [Gating] SW calibration Done
6867 09:31:04.074031 ==
6868 09:31:04.077143 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 09:31:04.080485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 09:31:04.081047 ==
6871 09:31:04.081395 RX Vref Scan: 0
6872 09:31:04.081709
6873 09:31:04.084091 RX Vref 0 -> 0, step: 1
6874 09:31:04.084610
6875 09:31:04.086976 RX Delay -410 -> 252, step: 16
6876 09:31:04.090787 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6877 09:31:04.097478 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6878 09:31:04.100208 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6879 09:31:04.103714 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6880 09:31:04.107006 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6881 09:31:04.113823 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6882 09:31:04.116979 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6883 09:31:04.120424 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6884 09:31:04.123561 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6885 09:31:04.130463 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6886 09:31:04.133805 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6887 09:31:04.136695 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6888 09:31:04.140468 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6889 09:31:04.147226 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6890 09:31:04.150018 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6891 09:31:04.153625 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6892 09:31:04.154143 ==
6893 09:31:04.157178 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 09:31:04.160314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 09:31:04.163916 ==
6896 09:31:04.164430 DQS Delay:
6897 09:31:04.164763 DQS0 = 35, DQS1 = 43
6898 09:31:04.166965 DQM Delay:
6899 09:31:04.167484 DQM0 = 16, DQM1 = 18
6900 09:31:04.170195 DQ Delay:
6901 09:31:04.173244 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6902 09:31:04.173664 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6903 09:31:04.177277 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6904 09:31:04.180013 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6905 09:31:04.180528
6906 09:31:04.183558
6907 09:31:04.184077 ==
6908 09:31:04.187277 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 09:31:04.190106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 09:31:04.190529 ==
6911 09:31:04.190861
6912 09:31:04.191169
6913 09:31:04.193184 TX Vref Scan disable
6914 09:31:04.193606 == TX Byte 0 ==
6915 09:31:04.196812 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6916 09:31:04.203785 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6917 09:31:04.204309 == TX Byte 1 ==
6918 09:31:04.206600 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 09:31:04.210062 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 09:31:04.213694 ==
6921 09:31:04.217199 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 09:31:04.220294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 09:31:04.220832 ==
6924 09:31:04.221251
6925 09:31:04.221568
6926 09:31:04.223691 TX Vref Scan disable
6927 09:31:04.224223 == TX Byte 0 ==
6928 09:31:04.226550 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6929 09:31:04.233446 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6930 09:31:04.233904 == TX Byte 1 ==
6931 09:31:04.236622 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6932 09:31:04.243270 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6933 09:31:04.243804
6934 09:31:04.244145 [DATLAT]
6935 09:31:04.244458 Freq=400, CH1 RK1
6936 09:31:04.244758
6937 09:31:04.246861 DATLAT Default: 0xe
6938 09:31:04.247278 0, 0xFFFF, sum = 0
6939 09:31:04.249848 1, 0xFFFF, sum = 0
6940 09:31:04.250272 2, 0xFFFF, sum = 0
6941 09:31:04.253404 3, 0xFFFF, sum = 0
6942 09:31:04.256720 4, 0xFFFF, sum = 0
6943 09:31:04.257295 5, 0xFFFF, sum = 0
6944 09:31:04.259963 6, 0xFFFF, sum = 0
6945 09:31:04.260489 7, 0xFFFF, sum = 0
6946 09:31:04.263208 8, 0xFFFF, sum = 0
6947 09:31:04.263737 9, 0xFFFF, sum = 0
6948 09:31:04.266574 10, 0xFFFF, sum = 0
6949 09:31:04.267003 11, 0xFFFF, sum = 0
6950 09:31:04.269663 12, 0xFFFF, sum = 0
6951 09:31:04.270091 13, 0x0, sum = 1
6952 09:31:04.273201 14, 0x0, sum = 2
6953 09:31:04.273625 15, 0x0, sum = 3
6954 09:31:04.276666 16, 0x0, sum = 4
6955 09:31:04.277232 best_step = 14
6956 09:31:04.277573
6957 09:31:04.277883 ==
6958 09:31:04.280051 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 09:31:04.283650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 09:31:04.284178 ==
6961 09:31:04.286765 RX Vref Scan: 0
6962 09:31:04.287185
6963 09:31:04.289782 RX Vref 0 -> 0, step: 1
6964 09:31:04.290203
6965 09:31:04.290535 RX Delay -327 -> 252, step: 8
6966 09:31:04.299322 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6967 09:31:04.302410 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6968 09:31:04.305649 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6969 09:31:04.308399 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6970 09:31:04.315312 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6971 09:31:04.318246 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6972 09:31:04.321896 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6973 09:31:04.325379 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6974 09:31:04.331749 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6975 09:31:04.335193 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6976 09:31:04.338437 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6977 09:31:04.341621 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6978 09:31:04.348424 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6979 09:31:04.351772 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6980 09:31:04.354930 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6981 09:31:04.361741 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6982 09:31:04.362267 ==
6983 09:31:04.365260 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 09:31:04.368630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 09:31:04.369185 ==
6986 09:31:04.369529 DQS Delay:
6987 09:31:04.372270 DQS0 = 32, DQS1 = 36
6988 09:31:04.372796 DQM Delay:
6989 09:31:04.375362 DQM0 = 13, DQM1 = 11
6990 09:31:04.375876 DQ Delay:
6991 09:31:04.379060 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6992 09:31:04.381957 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6993 09:31:04.385274 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6994 09:31:04.388718 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6995 09:31:04.389292
6996 09:31:04.389633
6997 09:31:04.394793 [DQSOSCAuto] RK1, (LSB)MR18= 0xb059, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6998 09:31:04.398598 CH1 RK1: MR19=C0C, MR18=B059
6999 09:31:04.405508 CH1_RK1: MR19=0xC0C, MR18=0xB059, DQSOSC=387, MR23=63, INC=394, DEC=262
7000 09:31:04.408481 [RxdqsGatingPostProcess] freq 400
7001 09:31:04.415098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 09:31:04.415616 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 09:31:04.418067 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 09:31:04.421645 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 09:31:04.424989 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 09:31:04.428566 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 09:31:04.431331 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 09:31:04.434629 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 09:31:04.438447 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 09:31:04.441244 Pre-setting of DQS Precalculation
7011 09:31:04.447877 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 09:31:04.454596 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 09:31:04.461327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 09:31:04.461854
7015 09:31:04.462199
7016 09:31:04.464910 [Calibration Summary] 800 Mbps
7017 09:31:04.465462 CH 0, Rank 0
7018 09:31:04.468160 SW Impedance : PASS
7019 09:31:04.471683 DUTY Scan : NO K
7020 09:31:04.472203 ZQ Calibration : PASS
7021 09:31:04.474912 Jitter Meter : NO K
7022 09:31:04.475433 CBT Training : PASS
7023 09:31:04.477748 Write leveling : PASS
7024 09:31:04.481381 RX DQS gating : PASS
7025 09:31:04.481898 RX DQ/DQS(RDDQC) : PASS
7026 09:31:04.484613 TX DQ/DQS : PASS
7027 09:31:04.487983 RX DATLAT : PASS
7028 09:31:04.488502 RX DQ/DQS(Engine): PASS
7029 09:31:04.491256 TX OE : NO K
7030 09:31:04.491781 All Pass.
7031 09:31:04.492138
7032 09:31:04.494483 CH 0, Rank 1
7033 09:31:04.494898 SW Impedance : PASS
7034 09:31:04.497796 DUTY Scan : NO K
7035 09:31:04.501317 ZQ Calibration : PASS
7036 09:31:04.501733 Jitter Meter : NO K
7037 09:31:04.504387 CBT Training : PASS
7038 09:31:04.507951 Write leveling : NO K
7039 09:31:04.508367 RX DQS gating : PASS
7040 09:31:04.511392 RX DQ/DQS(RDDQC) : PASS
7041 09:31:04.514626 TX DQ/DQS : PASS
7042 09:31:04.515050 RX DATLAT : PASS
7043 09:31:04.517674 RX DQ/DQS(Engine): PASS
7044 09:31:04.518087 TX OE : NO K
7045 09:31:04.521509 All Pass.
7046 09:31:04.522039
7047 09:31:04.522372 CH 1, Rank 0
7048 09:31:04.524643 SW Impedance : PASS
7049 09:31:04.525093 DUTY Scan : NO K
7050 09:31:04.528135 ZQ Calibration : PASS
7051 09:31:04.531735 Jitter Meter : NO K
7052 09:31:04.532253 CBT Training : PASS
7053 09:31:04.534500 Write leveling : PASS
7054 09:31:04.538190 RX DQS gating : PASS
7055 09:31:04.538703 RX DQ/DQS(RDDQC) : PASS
7056 09:31:04.541025 TX DQ/DQS : PASS
7057 09:31:04.544210 RX DATLAT : PASS
7058 09:31:04.544625 RX DQ/DQS(Engine): PASS
7059 09:31:04.547786 TX OE : NO K
7060 09:31:04.548269 All Pass.
7061 09:31:04.548604
7062 09:31:04.550860 CH 1, Rank 1
7063 09:31:04.551279 SW Impedance : PASS
7064 09:31:04.554295 DUTY Scan : NO K
7065 09:31:04.557580 ZQ Calibration : PASS
7066 09:31:04.557999 Jitter Meter : NO K
7067 09:31:04.560967 CBT Training : PASS
7068 09:31:04.564236 Write leveling : NO K
7069 09:31:04.564656 RX DQS gating : PASS
7070 09:31:04.567732 RX DQ/DQS(RDDQC) : PASS
7071 09:31:04.568152 TX DQ/DQS : PASS
7072 09:31:04.571066 RX DATLAT : PASS
7073 09:31:04.574392 RX DQ/DQS(Engine): PASS
7074 09:31:04.574808 TX OE : NO K
7075 09:31:04.577829 All Pass.
7076 09:31:04.578244
7077 09:31:04.578569 DramC Write-DBI off
7078 09:31:04.581288 PER_BANK_REFRESH: Hybrid Mode
7079 09:31:04.584670 TX_TRACKING: ON
7080 09:31:04.591403 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 09:31:04.594245 [FAST_K] Save calibration result to emmc
7082 09:31:04.597890 dramc_set_vcore_voltage set vcore to 725000
7083 09:31:04.600994 Read voltage for 1600, 0
7084 09:31:04.601416 Vio18 = 0
7085 09:31:04.604978 Vcore = 725000
7086 09:31:04.605503 Vdram = 0
7087 09:31:04.605836 Vddq = 0
7088 09:31:04.607794 Vmddr = 0
7089 09:31:04.610870 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 09:31:04.617683 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 09:31:04.618106 MEM_TYPE=3, freq_sel=13
7092 09:31:04.620897 sv_algorithm_assistance_LP4_3733
7093 09:31:04.627736 ============ PULL DRAM RESETB DOWN ============
7094 09:31:04.631220 ========== PULL DRAM RESETB DOWN end =========
7095 09:31:04.634586 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 09:31:04.637602 ===================================
7097 09:31:04.641218 LPDDR4 DRAM CONFIGURATION
7098 09:31:04.644397 ===================================
7099 09:31:04.647978 EX_ROW_EN[0] = 0x0
7100 09:31:04.648497 EX_ROW_EN[1] = 0x0
7101 09:31:04.651096 LP4Y_EN = 0x0
7102 09:31:04.651611 WORK_FSP = 0x1
7103 09:31:04.654436 WL = 0x5
7104 09:31:04.654853 RL = 0x5
7105 09:31:04.657582 BL = 0x2
7106 09:31:04.658000 RPST = 0x0
7107 09:31:04.660737 RD_PRE = 0x0
7108 09:31:04.661306 WR_PRE = 0x1
7109 09:31:04.664384 WR_PST = 0x1
7110 09:31:04.664803 DBI_WR = 0x0
7111 09:31:04.667294 DBI_RD = 0x0
7112 09:31:04.667710 OTF = 0x1
7113 09:31:04.670563 ===================================
7114 09:31:04.674159 ===================================
7115 09:31:04.677832 ANA top config
7116 09:31:04.680758 ===================================
7117 09:31:04.681313 DLL_ASYNC_EN = 0
7118 09:31:04.684547 ALL_SLAVE_EN = 0
7119 09:31:04.687900 NEW_RANK_MODE = 1
7120 09:31:04.690950 DLL_IDLE_MODE = 1
7121 09:31:04.694339 LP45_APHY_COMB_EN = 1
7122 09:31:04.694859 TX_ODT_DIS = 0
7123 09:31:04.697690 NEW_8X_MODE = 1
7124 09:31:04.700842 ===================================
7125 09:31:04.703911 ===================================
7126 09:31:04.707500 data_rate = 3200
7127 09:31:04.710946 CKR = 1
7128 09:31:04.713913 DQ_P2S_RATIO = 8
7129 09:31:04.717404 ===================================
7130 09:31:04.720690 CA_P2S_RATIO = 8
7131 09:31:04.721244 DQ_CA_OPEN = 0
7132 09:31:04.724387 DQ_SEMI_OPEN = 0
7133 09:31:04.727519 CA_SEMI_OPEN = 0
7134 09:31:04.731155 CA_FULL_RATE = 0
7135 09:31:04.733687 DQ_CKDIV4_EN = 0
7136 09:31:04.734105 CA_CKDIV4_EN = 0
7137 09:31:04.737593 CA_PREDIV_EN = 0
7138 09:31:04.740416 PH8_DLY = 12
7139 09:31:04.743819 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 09:31:04.747647 DQ_AAMCK_DIV = 4
7141 09:31:04.750477 CA_AAMCK_DIV = 4
7142 09:31:04.750898 CA_ADMCK_DIV = 4
7143 09:31:04.754283 DQ_TRACK_CA_EN = 0
7144 09:31:04.757553 CA_PICK = 1600
7145 09:31:04.760338 CA_MCKIO = 1600
7146 09:31:04.763542 MCKIO_SEMI = 0
7147 09:31:04.767329 PLL_FREQ = 3068
7148 09:31:04.770422 DQ_UI_PI_RATIO = 32
7149 09:31:04.773588 CA_UI_PI_RATIO = 0
7150 09:31:04.777319 ===================================
7151 09:31:04.780562 ===================================
7152 09:31:04.781010 memory_type:LPDDR4
7153 09:31:04.783813 GP_NUM : 10
7154 09:31:04.784231 SRAM_EN : 1
7155 09:31:04.787117 MD32_EN : 0
7156 09:31:04.790342 ===================================
7157 09:31:04.794186 [ANA_INIT] >>>>>>>>>>>>>>
7158 09:31:04.797040 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 09:31:04.800259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 09:31:04.804165 ===================================
7161 09:31:04.804688 data_rate = 3200,PCW = 0X7600
7162 09:31:04.807247 ===================================
7163 09:31:04.810524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 09:31:04.816763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 09:31:04.823876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 09:31:04.827530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 09:31:04.830603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 09:31:04.833963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 09:31:04.836999 [ANA_INIT] flow start
7170 09:31:04.840584 [ANA_INIT] PLL >>>>>>>>
7171 09:31:04.841134 [ANA_INIT] PLL <<<<<<<<
7172 09:31:04.844016 [ANA_INIT] MIDPI >>>>>>>>
7173 09:31:04.847199 [ANA_INIT] MIDPI <<<<<<<<
7174 09:31:04.847724 [ANA_INIT] DLL >>>>>>>>
7175 09:31:04.850351 [ANA_INIT] DLL <<<<<<<<
7176 09:31:04.853638 [ANA_INIT] flow end
7177 09:31:04.857052 ============ LP4 DIFF to SE enter ============
7178 09:31:04.860753 ============ LP4 DIFF to SE exit ============
7179 09:31:04.863470 [ANA_INIT] <<<<<<<<<<<<<
7180 09:31:04.867308 [Flow] Enable top DCM control >>>>>
7181 09:31:04.870144 [Flow] Enable top DCM control <<<<<
7182 09:31:04.873818 Enable DLL master slave shuffle
7183 09:31:04.876833 ==============================================================
7184 09:31:04.879784 Gating Mode config
7185 09:31:04.883773 ==============================================================
7186 09:31:04.887047 Config description:
7187 09:31:04.897135 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 09:31:04.904065 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 09:31:04.907209 SELPH_MODE 0: By rank 1: By Phase
7190 09:31:04.913889 ==============================================================
7191 09:31:04.916977 GAT_TRACK_EN = 1
7192 09:31:04.919886 RX_GATING_MODE = 2
7193 09:31:04.923864 RX_GATING_TRACK_MODE = 2
7194 09:31:04.927005 SELPH_MODE = 1
7195 09:31:04.930629 PICG_EARLY_EN = 1
7196 09:31:04.933621 VALID_LAT_VALUE = 1
7197 09:31:04.936859 ==============================================================
7198 09:31:04.940596 Enter into Gating configuration >>>>
7199 09:31:04.943227 Exit from Gating configuration <<<<
7200 09:31:04.946518 Enter into DVFS_PRE_config >>>>>
7201 09:31:04.956907 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 09:31:04.960295 Exit from DVFS_PRE_config <<<<<
7203 09:31:04.963608 Enter into PICG configuration >>>>
7204 09:31:04.966711 Exit from PICG configuration <<<<
7205 09:31:04.970078 [RX_INPUT] configuration >>>>>
7206 09:31:04.973075 [RX_INPUT] configuration <<<<<
7207 09:31:04.979866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 09:31:04.983209 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 09:31:04.989712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 09:31:04.996560 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 09:31:05.002749 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 09:31:05.009583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 09:31:05.012769 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 09:31:05.016540 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 09:31:05.019709 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 09:31:05.026341 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 09:31:05.029745 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 09:31:05.033159 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 09:31:05.036221 ===================================
7220 09:31:05.039797 LPDDR4 DRAM CONFIGURATION
7221 09:31:05.042622 ===================================
7222 09:31:05.043044 EX_ROW_EN[0] = 0x0
7223 09:31:05.046021 EX_ROW_EN[1] = 0x0
7224 09:31:05.049391 LP4Y_EN = 0x0
7225 09:31:05.049916 WORK_FSP = 0x1
7226 09:31:05.052325 WL = 0x5
7227 09:31:05.052740 RL = 0x5
7228 09:31:05.056007 BL = 0x2
7229 09:31:05.056529 RPST = 0x0
7230 09:31:05.059541 RD_PRE = 0x0
7231 09:31:05.060070 WR_PRE = 0x1
7232 09:31:05.062620 WR_PST = 0x1
7233 09:31:05.063141 DBI_WR = 0x0
7234 09:31:05.066095 DBI_RD = 0x0
7235 09:31:05.066619 OTF = 0x1
7236 09:31:05.069296 ===================================
7237 09:31:05.072471 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 09:31:05.079427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 09:31:05.082503 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 09:31:05.085743 ===================================
7241 09:31:05.089113 LPDDR4 DRAM CONFIGURATION
7242 09:31:05.092858 ===================================
7243 09:31:05.093415 EX_ROW_EN[0] = 0x10
7244 09:31:05.095876 EX_ROW_EN[1] = 0x0
7245 09:31:05.099048 LP4Y_EN = 0x0
7246 09:31:05.099468 WORK_FSP = 0x1
7247 09:31:05.102663 WL = 0x5
7248 09:31:05.103081 RL = 0x5
7249 09:31:05.105769 BL = 0x2
7250 09:31:05.106185 RPST = 0x0
7251 09:31:05.109021 RD_PRE = 0x0
7252 09:31:05.109432 WR_PRE = 0x1
7253 09:31:05.112315 WR_PST = 0x1
7254 09:31:05.112730 DBI_WR = 0x0
7255 09:31:05.115865 DBI_RD = 0x0
7256 09:31:05.116381 OTF = 0x1
7257 09:31:05.118963 ===================================
7258 09:31:05.125728 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 09:31:05.126247 ==
7260 09:31:05.129070 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 09:31:05.132842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 09:31:05.133436 ==
7263 09:31:05.136033 [Duty_Offset_Calibration]
7264 09:31:05.139618 B0:2 B1:0 CA:1
7265 09:31:05.140143
7266 09:31:05.142358 [DutyScan_Calibration_Flow] k_type=0
7267 09:31:05.150191
7268 09:31:05.150721 ==CLK 0==
7269 09:31:05.153604 Final CLK duty delay cell = -4
7270 09:31:05.156467 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7271 09:31:05.160107 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7272 09:31:05.163630 [-4] AVG Duty = 4922%(X100)
7273 09:31:05.164050
7274 09:31:05.166893 CH0 CLK Duty spec in!! Max-Min= 218%
7275 09:31:05.169890 [DutyScan_Calibration_Flow] ====Done====
7276 09:31:05.170416
7277 09:31:05.173526 [DutyScan_Calibration_Flow] k_type=1
7278 09:31:05.189416
7279 09:31:05.189945 ==DQS 0 ==
7280 09:31:05.192747 Final DQS duty delay cell = 0
7281 09:31:05.196516 [0] MAX Duty = 5249%(X100), DQS PI = 32
7282 09:31:05.199536 [0] MIN Duty = 4969%(X100), DQS PI = 0
7283 09:31:05.200065 [0] AVG Duty = 5109%(X100)
7284 09:31:05.203266
7285 09:31:05.203803 ==DQS 1 ==
7286 09:31:05.205850 Final DQS duty delay cell = -4
7287 09:31:05.209427 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7288 09:31:05.212643 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7289 09:31:05.216495 [-4] AVG Duty = 5000%(X100)
7290 09:31:05.217065
7291 09:31:05.219478 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7292 09:31:05.219927
7293 09:31:05.222801 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7294 09:31:05.226393 [DutyScan_Calibration_Flow] ====Done====
7295 09:31:05.226926
7296 09:31:05.229394 [DutyScan_Calibration_Flow] k_type=3
7297 09:31:05.247251
7298 09:31:05.247778 ==DQM 0 ==
7299 09:31:05.250053 Final DQM duty delay cell = 0
7300 09:31:05.253783 [0] MAX Duty = 5093%(X100), DQS PI = 26
7301 09:31:05.257335 [0] MIN Duty = 4813%(X100), DQS PI = 50
7302 09:31:05.259952 [0] AVG Duty = 4953%(X100)
7303 09:31:05.260374
7304 09:31:05.260704 ==DQM 1 ==
7305 09:31:05.263637 Final DQM duty delay cell = 0
7306 09:31:05.266655 [0] MAX Duty = 5249%(X100), DQS PI = 28
7307 09:31:05.269778 [0] MIN Duty = 5000%(X100), DQS PI = 20
7308 09:31:05.273376 [0] AVG Duty = 5124%(X100)
7309 09:31:05.273796
7310 09:31:05.277179 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7311 09:31:05.277706
7312 09:31:05.280291 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7313 09:31:05.283922 [DutyScan_Calibration_Flow] ====Done====
7314 09:31:05.284459
7315 09:31:05.286972 [DutyScan_Calibration_Flow] k_type=2
7316 09:31:05.304207
7317 09:31:05.304737 ==DQ 0 ==
7318 09:31:05.307716 Final DQ duty delay cell = 0
7319 09:31:05.310574 [0] MAX Duty = 5124%(X100), DQS PI = 32
7320 09:31:05.314293 [0] MIN Duty = 5000%(X100), DQS PI = 16
7321 09:31:05.314846 [0] AVG Duty = 5062%(X100)
7322 09:31:05.317694
7323 09:31:05.318224 ==DQ 1 ==
7324 09:31:05.320780 Final DQ duty delay cell = 0
7325 09:31:05.323978 [0] MAX Duty = 4969%(X100), DQS PI = 50
7326 09:31:05.327284 [0] MIN Duty = 4875%(X100), DQS PI = 10
7327 09:31:05.327802 [0] AVG Duty = 4922%(X100)
7328 09:31:05.328143
7329 09:31:05.330594 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7330 09:31:05.333770
7331 09:31:05.337452 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7332 09:31:05.340656 [DutyScan_Calibration_Flow] ====Done====
7333 09:31:05.341095 ==
7334 09:31:05.343974 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 09:31:05.347273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 09:31:05.347688 ==
7337 09:31:05.350605 [Duty_Offset_Calibration]
7338 09:31:05.351107 B0:0 B1:-1 CA:2
7339 09:31:05.351431
7340 09:31:05.354056 [DutyScan_Calibration_Flow] k_type=0
7341 09:31:05.364712
7342 09:31:05.365303 ==CLK 0==
7343 09:31:05.368237 Final CLK duty delay cell = 0
7344 09:31:05.371347 [0] MAX Duty = 5156%(X100), DQS PI = 10
7345 09:31:05.374439 [0] MIN Duty = 4906%(X100), DQS PI = 46
7346 09:31:05.374947 [0] AVG Duty = 5031%(X100)
7347 09:31:05.377992
7348 09:31:05.381087 CH1 CLK Duty spec in!! Max-Min= 250%
7349 09:31:05.384696 [DutyScan_Calibration_Flow] ====Done====
7350 09:31:05.385241
7351 09:31:05.387636 [DutyScan_Calibration_Flow] k_type=1
7352 09:31:05.404090
7353 09:31:05.404591 ==DQS 0 ==
7354 09:31:05.407794 Final DQS duty delay cell = 0
7355 09:31:05.410533 [0] MAX Duty = 5124%(X100), DQS PI = 26
7356 09:31:05.414117 [0] MIN Duty = 4969%(X100), DQS PI = 2
7357 09:31:05.414529 [0] AVG Duty = 5046%(X100)
7358 09:31:05.417086
7359 09:31:05.417493 ==DQS 1 ==
7360 09:31:05.420758 Final DQS duty delay cell = 0
7361 09:31:05.424533 [0] MAX Duty = 5187%(X100), DQS PI = 0
7362 09:31:05.427532 [0] MIN Duty = 4844%(X100), DQS PI = 34
7363 09:31:05.428039 [0] AVG Duty = 5015%(X100)
7364 09:31:05.430520
7365 09:31:05.434354 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7366 09:31:05.434761
7367 09:31:05.437212 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7368 09:31:05.440835 [DutyScan_Calibration_Flow] ====Done====
7369 09:31:05.441430
7370 09:31:05.443616 [DutyScan_Calibration_Flow] k_type=3
7371 09:31:05.462023
7372 09:31:05.462530 ==DQM 0 ==
7373 09:31:05.465097 Final DQM duty delay cell = 4
7374 09:31:05.468671 [4] MAX Duty = 5125%(X100), DQS PI = 6
7375 09:31:05.471752 [4] MIN Duty = 5000%(X100), DQS PI = 32
7376 09:31:05.472172 [4] AVG Duty = 5062%(X100)
7377 09:31:05.475162
7378 09:31:05.475668 ==DQM 1 ==
7379 09:31:05.478749 Final DQM duty delay cell = 0
7380 09:31:05.481647 [0] MAX Duty = 5281%(X100), DQS PI = 58
7381 09:31:05.485095 [0] MIN Duty = 4876%(X100), DQS PI = 34
7382 09:31:05.488630 [0] AVG Duty = 5078%(X100)
7383 09:31:05.489178
7384 09:31:05.491749 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7385 09:31:05.492258
7386 09:31:05.494711 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7387 09:31:05.498390 [DutyScan_Calibration_Flow] ====Done====
7388 09:31:05.498797
7389 09:31:05.501544 [DutyScan_Calibration_Flow] k_type=2
7390 09:31:05.518822
7391 09:31:05.519327 ==DQ 0 ==
7392 09:31:05.522064 Final DQ duty delay cell = 0
7393 09:31:05.525250 [0] MAX Duty = 5093%(X100), DQS PI = 20
7394 09:31:05.528762 [0] MIN Duty = 4969%(X100), DQS PI = 46
7395 09:31:05.529334 [0] AVG Duty = 5031%(X100)
7396 09:31:05.529666
7397 09:31:05.532036 ==DQ 1 ==
7398 09:31:05.535642 Final DQ duty delay cell = 0
7399 09:31:05.538794 [0] MAX Duty = 5062%(X100), DQS PI = 0
7400 09:31:05.541964 [0] MIN Duty = 4813%(X100), DQS PI = 34
7401 09:31:05.542393 [0] AVG Duty = 4937%(X100)
7402 09:31:05.542715
7403 09:31:05.545184 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7404 09:31:05.545595
7405 09:31:05.549036 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7406 09:31:05.555153 [DutyScan_Calibration_Flow] ====Done====
7407 09:31:05.558596 nWR fixed to 30
7408 09:31:05.559103 [ModeRegInit_LP4] CH0 RK0
7409 09:31:05.561738 [ModeRegInit_LP4] CH0 RK1
7410 09:31:05.565217 [ModeRegInit_LP4] CH1 RK0
7411 09:31:05.565627 [ModeRegInit_LP4] CH1 RK1
7412 09:31:05.568631 match AC timing 5
7413 09:31:05.572024 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 09:31:05.575189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 09:31:05.581759 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 09:31:05.584823 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 09:31:05.591490 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 09:31:05.591901 [MiockJmeterHQA]
7419 09:31:05.592222
7420 09:31:05.595056 [DramcMiockJmeter] u1RxGatingPI = 0
7421 09:31:05.598329 0 : 4255, 4026
7422 09:31:05.598745 4 : 4252, 4027
7423 09:31:05.599096 8 : 4363, 4137
7424 09:31:05.601655 12 : 4363, 4137
7425 09:31:05.602069 16 : 4253, 4027
7426 09:31:05.605286 20 : 4363, 4138
7427 09:31:05.605702 24 : 4253, 4026
7428 09:31:05.608189 28 : 4253, 4026
7429 09:31:05.608603 32 : 4252, 4027
7430 09:31:05.608965 36 : 4255, 4029
7431 09:31:05.611642 40 : 4253, 4026
7432 09:31:05.612058 44 : 4253, 4027
7433 09:31:05.615131 48 : 4365, 4140
7434 09:31:05.615643 52 : 4252, 4027
7435 09:31:05.618524 56 : 4255, 4030
7436 09:31:05.618954 60 : 4253, 4026
7437 09:31:05.621483 64 : 4363, 4138
7438 09:31:05.622031 68 : 4249, 4027
7439 09:31:05.622379 72 : 4361, 4137
7440 09:31:05.625005 76 : 4253, 4027
7441 09:31:05.625458 80 : 4250, 4026
7442 09:31:05.628000 84 : 4250, 4027
7443 09:31:05.628416 88 : 4252, 3274
7444 09:31:05.631351 92 : 4250, 0
7445 09:31:05.631770 96 : 4363, 0
7446 09:31:05.632103 100 : 4250, 0
7447 09:31:05.634786 104 : 4363, 0
7448 09:31:05.635206 108 : 4360, 0
7449 09:31:05.637897 112 : 4247, 0
7450 09:31:05.638314 116 : 4253, 0
7451 09:31:05.638645 120 : 4360, 0
7452 09:31:05.641285 124 : 4361, 0
7453 09:31:05.641880 128 : 4250, 0
7454 09:31:05.642226 132 : 4250, 0
7455 09:31:05.644867 136 : 4250, 0
7456 09:31:05.645320 140 : 4250, 0
7457 09:31:05.648195 144 : 4360, 0
7458 09:31:05.648610 148 : 4250, 0
7459 09:31:05.649001 152 : 4250, 0
7460 09:31:05.651612 156 : 4361, 0
7461 09:31:05.652040 160 : 4360, 0
7462 09:31:05.654993 164 : 4250, 0
7463 09:31:05.655409 168 : 4250, 0
7464 09:31:05.655740 172 : 4361, 0
7465 09:31:05.658189 176 : 4360, 0
7466 09:31:05.658620 180 : 4250, 0
7467 09:31:05.661354 184 : 4250, 0
7468 09:31:05.661771 188 : 4250, 0
7469 09:31:05.662097 192 : 4250, 0
7470 09:31:05.664604 196 : 4250, 0
7471 09:31:05.665079 200 : 4250, 0
7472 09:31:05.668094 204 : 4250, 2097
7473 09:31:05.668546 208 : 4250, 4026
7474 09:31:05.668877 212 : 4250, 4027
7475 09:31:05.671861 216 : 4360, 4137
7476 09:31:05.672368 220 : 4250, 4027
7477 09:31:05.674773 224 : 4250, 4026
7478 09:31:05.675184 228 : 4361, 4137
7479 09:31:05.678655 232 : 4363, 4140
7480 09:31:05.679171 236 : 4251, 4027
7481 09:31:05.681325 240 : 4363, 4139
7482 09:31:05.681738 244 : 4360, 4137
7483 09:31:05.685223 248 : 4252, 4029
7484 09:31:05.685781 252 : 4253, 4029
7485 09:31:05.687962 256 : 4252, 4029
7486 09:31:05.688374 260 : 4250, 4026
7487 09:31:05.692068 264 : 4250, 4027
7488 09:31:05.692583 268 : 4250, 4027
7489 09:31:05.692914 272 : 4253, 4029
7490 09:31:05.694671 276 : 4250, 4026
7491 09:31:05.695099 280 : 4361, 4137
7492 09:31:05.697813 284 : 4360, 4138
7493 09:31:05.698227 288 : 4250, 4027
7494 09:31:05.701293 292 : 4363, 4140
7495 09:31:05.701774 296 : 4360, 4137
7496 09:31:05.704656 300 : 4252, 4029
7497 09:31:05.705158 304 : 4250, 4027
7498 09:31:05.708177 308 : 4252, 4029
7499 09:31:05.708588 312 : 4250, 3922
7500 09:31:05.711159 316 : 4252, 2025
7501 09:31:05.711589
7502 09:31:05.711992 MIOCK jitter meter ch=0
7503 09:31:05.712318
7504 09:31:05.716674 1T = (316-92) = 224 dly cells
7505 09:31:05.721371 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7506 09:31:05.721817 ==
7507 09:31:05.724496 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 09:31:05.728069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 09:31:05.728487 ==
7510 09:31:05.734211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 09:31:05.737870 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 09:31:05.741476 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 09:31:05.747884 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 09:31:05.757324 [CA 0] Center 42 (12~72) winsize 61
7515 09:31:05.760773 [CA 1] Center 42 (12~72) winsize 61
7516 09:31:05.764100 [CA 2] Center 37 (7~67) winsize 61
7517 09:31:05.767329 [CA 3] Center 37 (7~67) winsize 61
7518 09:31:05.770376 [CA 4] Center 35 (5~66) winsize 62
7519 09:31:05.774008 [CA 5] Center 35 (5~65) winsize 61
7520 09:31:05.774632
7521 09:31:05.777359 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 09:31:05.777977
7523 09:31:05.780083 [CATrainingPosCal] consider 1 rank data
7524 09:31:05.783630 u2DelayCellTimex100 = 290/100 ps
7525 09:31:05.787184 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7526 09:31:05.793776 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7527 09:31:05.797122 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7528 09:31:05.800560 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7529 09:31:05.803616 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7530 09:31:05.807201 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7531 09:31:05.807700
7532 09:31:05.810250 CA PerBit enable=1, Macro0, CA PI delay=35
7533 09:31:05.810665
7534 09:31:05.813951 [CBTSetCACLKResult] CA Dly = 35
7535 09:31:05.816976 CS Dly: 10 (0~41)
7536 09:31:05.820691 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 09:31:05.824012 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 09:31:05.824435 ==
7539 09:31:05.827517 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 09:31:05.830969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 09:31:05.831483 ==
7542 09:31:05.837325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 09:31:05.841012 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 09:31:05.847336 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 09:31:05.850289 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 09:31:05.861179 [CA 0] Center 43 (13~74) winsize 62
7547 09:31:05.864018 [CA 1] Center 43 (13~73) winsize 61
7548 09:31:05.867146 [CA 2] Center 38 (9~68) winsize 60
7549 09:31:05.870434 [CA 3] Center 38 (9~68) winsize 60
7550 09:31:05.873801 [CA 4] Center 37 (7~67) winsize 61
7551 09:31:05.877027 [CA 5] Center 36 (7~66) winsize 60
7552 09:31:05.877564
7553 09:31:05.880523 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 09:31:05.880978
7555 09:31:05.884107 [CATrainingPosCal] consider 2 rank data
7556 09:31:05.887435 u2DelayCellTimex100 = 290/100 ps
7557 09:31:05.890469 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
7558 09:31:05.897651 CA1 delay=42 (13~72),Diff = 6 PI (20 cell)
7559 09:31:05.900781 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7560 09:31:05.904404 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7561 09:31:05.907242 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 09:31:05.910168 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7563 09:31:05.910778
7564 09:31:05.913985 CA PerBit enable=1, Macro0, CA PI delay=36
7565 09:31:05.914439
7566 09:31:05.917244 [CBTSetCACLKResult] CA Dly = 36
7567 09:31:05.920291 CS Dly: 11 (0~43)
7568 09:31:05.923770 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 09:31:05.927455 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 09:31:05.927878
7571 09:31:05.930679 ----->DramcWriteLeveling(PI) begin...
7572 09:31:05.931211 ==
7573 09:31:05.933565 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 09:31:05.937553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 09:31:05.940669 ==
7576 09:31:05.941230 Write leveling (Byte 0): 37 => 37
7577 09:31:05.944121 Write leveling (Byte 1): 31 => 31
7578 09:31:05.947369 DramcWriteLeveling(PI) end<-----
7579 09:31:05.947900
7580 09:31:05.948243 ==
7581 09:31:05.950412 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 09:31:05.957188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 09:31:05.957610 ==
7584 09:31:05.957949 [Gating] SW mode calibration
7585 09:31:05.967205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 09:31:05.970112 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 09:31:05.976694 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 09:31:05.980553 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 09:31:05.983309 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7590 09:31:05.986933 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7591 09:31:05.993817 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7592 09:31:05.997043 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7593 09:31:06.000158 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 09:31:06.007147 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 09:31:06.010082 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 09:31:06.013785 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 09:31:06.020108 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7598 09:31:06.023491 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7599 09:31:06.026529 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7600 09:31:06.033426 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7601 09:31:06.036772 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7602 09:31:06.040249 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 09:31:06.046933 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 09:31:06.049861 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7605 09:31:06.053508 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7606 09:31:06.060129 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7607 09:31:06.063437 1 6 16 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
7608 09:31:06.067029 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 09:31:06.073585 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 09:31:06.076274 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 09:31:06.079952 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 09:31:06.086382 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 09:31:06.089792 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 09:31:06.092914 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 09:31:06.099539 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 09:31:06.103277 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7617 09:31:06.106441 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 09:31:06.113004 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 09:31:06.116478 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 09:31:06.119631 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 09:31:06.126156 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 09:31:06.129328 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 09:31:06.132461 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 09:31:06.139723 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 09:31:06.142550 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 09:31:06.146445 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 09:31:06.152648 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 09:31:06.155973 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 09:31:06.159948 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 09:31:06.162759 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 09:31:06.169891 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7632 09:31:06.173102 Total UI for P1: 0, mck2ui 16
7633 09:31:06.175902 best dqsien dly found for B0: ( 1, 9, 10)
7634 09:31:06.179714 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 09:31:06.183052 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 09:31:06.185993 Total UI for P1: 0, mck2ui 16
7637 09:31:06.189096 best dqsien dly found for B1: ( 1, 9, 20)
7638 09:31:06.192770 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7639 09:31:06.195698 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7640 09:31:06.199246
7641 09:31:06.202756 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7642 09:31:06.206101 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7643 09:31:06.209233 [Gating] SW calibration Done
7644 09:31:06.209838 ==
7645 09:31:06.212312 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 09:31:06.215903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 09:31:06.216333 ==
7648 09:31:06.216668 RX Vref Scan: 0
7649 09:31:06.217027
7650 09:31:06.219016 RX Vref 0 -> 0, step: 1
7651 09:31:06.219440
7652 09:31:06.222766 RX Delay 0 -> 252, step: 8
7653 09:31:06.225999 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7654 09:31:06.229235 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7655 09:31:06.235818 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7656 09:31:06.239011 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7657 09:31:06.242506 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7658 09:31:06.245622 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7659 09:31:06.249336 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7660 09:31:06.252282 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7661 09:31:06.259091 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7662 09:31:06.262331 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7663 09:31:06.265563 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7664 09:31:06.268872 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7665 09:31:06.275425 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7666 09:31:06.278750 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7667 09:31:06.282241 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7668 09:31:06.285433 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7669 09:31:06.285517 ==
7670 09:31:06.288902 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 09:31:06.291979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 09:31:06.294997 ==
7673 09:31:06.295073 DQS Delay:
7674 09:31:06.295138 DQS0 = 0, DQS1 = 0
7675 09:31:06.298698 DQM Delay:
7676 09:31:06.298775 DQM0 = 138, DQM1 = 127
7677 09:31:06.301578 DQ Delay:
7678 09:31:06.305153 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7679 09:31:06.308256 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7680 09:31:06.311655 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7681 09:31:06.315107 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7682 09:31:06.315181
7683 09:31:06.315242
7684 09:31:06.315301 ==
7685 09:31:06.318227 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 09:31:06.321933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 09:31:06.322008 ==
7688 09:31:06.322070
7689 09:31:06.325051
7690 09:31:06.325186 TX Vref Scan disable
7691 09:31:06.328201 == TX Byte 0 ==
7692 09:31:06.331808 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7693 09:31:06.335260 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7694 09:31:06.338302 == TX Byte 1 ==
7695 09:31:06.341859 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7696 09:31:06.345134 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7697 09:31:06.345241 ==
7698 09:31:06.348360 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 09:31:06.354969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 09:31:06.355078 ==
7701 09:31:06.368016
7702 09:31:06.371223 TX Vref early break, caculate TX vref
7703 09:31:06.374778 TX Vref=16, minBit 12, minWin=22, winSum=379
7704 09:31:06.378227 TX Vref=18, minBit 6, minWin=23, winSum=384
7705 09:31:06.381300 TX Vref=20, minBit 6, minWin=23, winSum=396
7706 09:31:06.384388 TX Vref=22, minBit 0, minWin=25, winSum=405
7707 09:31:06.388070 TX Vref=24, minBit 0, minWin=25, winSum=413
7708 09:31:06.394803 TX Vref=26, minBit 2, minWin=25, winSum=426
7709 09:31:06.397868 TX Vref=28, minBit 1, minWin=25, winSum=428
7710 09:31:06.401347 TX Vref=30, minBit 1, minWin=25, winSum=422
7711 09:31:06.404408 TX Vref=32, minBit 0, minWin=25, winSum=415
7712 09:31:06.407884 TX Vref=34, minBit 7, minWin=24, winSum=406
7713 09:31:06.411347 TX Vref=36, minBit 2, minWin=24, winSum=393
7714 09:31:06.418002 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 28
7715 09:31:06.418109
7716 09:31:06.421521 Final TX Range 0 Vref 28
7717 09:31:06.421602
7718 09:31:06.421669 ==
7719 09:31:06.424674 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 09:31:06.427767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 09:31:06.427870 ==
7722 09:31:06.427964
7723 09:31:06.428053
7724 09:31:06.431260 TX Vref Scan disable
7725 09:31:06.437870 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7726 09:31:06.437992 == TX Byte 0 ==
7727 09:31:06.441359 u2DelayCellOfst[0]=10 cells (3 PI)
7728 09:31:06.444623 u2DelayCellOfst[1]=16 cells (5 PI)
7729 09:31:06.447647 u2DelayCellOfst[2]=10 cells (3 PI)
7730 09:31:06.451083 u2DelayCellOfst[3]=10 cells (3 PI)
7731 09:31:06.454573 u2DelayCellOfst[4]=6 cells (2 PI)
7732 09:31:06.457752 u2DelayCellOfst[5]=0 cells (0 PI)
7733 09:31:06.460812 u2DelayCellOfst[6]=16 cells (5 PI)
7734 09:31:06.464356 u2DelayCellOfst[7]=13 cells (4 PI)
7735 09:31:06.467906 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7736 09:31:06.470989 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7737 09:31:06.474066 == TX Byte 1 ==
7738 09:31:06.477997 u2DelayCellOfst[8]=3 cells (1 PI)
7739 09:31:06.478100 u2DelayCellOfst[9]=0 cells (0 PI)
7740 09:31:06.480994 u2DelayCellOfst[10]=6 cells (2 PI)
7741 09:31:06.483993 u2DelayCellOfst[11]=3 cells (1 PI)
7742 09:31:06.487589 u2DelayCellOfst[12]=13 cells (4 PI)
7743 09:31:06.490646 u2DelayCellOfst[13]=13 cells (4 PI)
7744 09:31:06.494215 u2DelayCellOfst[14]=13 cells (4 PI)
7745 09:31:06.497601 u2DelayCellOfst[15]=10 cells (3 PI)
7746 09:31:06.501069 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7747 09:31:06.507574 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7748 09:31:06.507697 DramC Write-DBI on
7749 09:31:06.507847 ==
7750 09:31:06.510699 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 09:31:06.517690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 09:31:06.517822 ==
7753 09:31:06.517951
7754 09:31:06.518046
7755 09:31:06.518133 TX Vref Scan disable
7756 09:31:06.521561 == TX Byte 0 ==
7757 09:31:06.525408 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7758 09:31:06.527939 == TX Byte 1 ==
7759 09:31:06.531586 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7760 09:31:06.531672 DramC Write-DBI off
7761 09:31:06.534844
7762 09:31:06.534927 [DATLAT]
7763 09:31:06.534993 Freq=1600, CH0 RK0
7764 09:31:06.535083
7765 09:31:06.538325 DATLAT Default: 0xf
7766 09:31:06.538403 0, 0xFFFF, sum = 0
7767 09:31:06.541326 1, 0xFFFF, sum = 0
7768 09:31:06.541430 2, 0xFFFF, sum = 0
7769 09:31:06.544867 3, 0xFFFF, sum = 0
7770 09:31:06.547956 4, 0xFFFF, sum = 0
7771 09:31:06.548064 5, 0xFFFF, sum = 0
7772 09:31:06.551166 6, 0xFFFF, sum = 0
7773 09:31:06.551260 7, 0xFFFF, sum = 0
7774 09:31:06.554460 8, 0xFFFF, sum = 0
7775 09:31:06.554571 9, 0xFFFF, sum = 0
7776 09:31:06.558113 10, 0xFFFF, sum = 0
7777 09:31:06.558217 11, 0xFFFF, sum = 0
7778 09:31:06.561193 12, 0xFFFF, sum = 0
7779 09:31:06.561299 13, 0xFFFF, sum = 0
7780 09:31:06.564814 14, 0x0, sum = 1
7781 09:31:06.564919 15, 0x0, sum = 2
7782 09:31:06.567850 16, 0x0, sum = 3
7783 09:31:06.567931 17, 0x0, sum = 4
7784 09:31:06.571060 best_step = 15
7785 09:31:06.571186
7786 09:31:06.571280 ==
7787 09:31:06.574323 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 09:31:06.577840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 09:31:06.577916 ==
7790 09:31:06.577994 RX Vref Scan: 1
7791 09:31:06.581290
7792 09:31:06.581364 Set Vref Range= 24 -> 127
7793 09:31:06.581444
7794 09:31:06.584301 RX Vref 24 -> 127, step: 1
7795 09:31:06.584373
7796 09:31:06.587724 RX Delay 19 -> 252, step: 4
7797 09:31:06.587804
7798 09:31:06.591523 Set Vref, RX VrefLevel [Byte0]: 24
7799 09:31:06.594408 [Byte1]: 24
7800 09:31:06.594483
7801 09:31:06.597961 Set Vref, RX VrefLevel [Byte0]: 25
7802 09:31:06.601371 [Byte1]: 25
7803 09:31:06.601478
7804 09:31:06.604336 Set Vref, RX VrefLevel [Byte0]: 26
7805 09:31:06.607826 [Byte1]: 26
7806 09:31:06.611765
7807 09:31:06.611844 Set Vref, RX VrefLevel [Byte0]: 27
7808 09:31:06.614855 [Byte1]: 27
7809 09:31:06.619335
7810 09:31:06.619449 Set Vref, RX VrefLevel [Byte0]: 28
7811 09:31:06.622448 [Byte1]: 28
7812 09:31:06.626762
7813 09:31:06.626865 Set Vref, RX VrefLevel [Byte0]: 29
7814 09:31:06.630318 [Byte1]: 29
7815 09:31:06.634385
7816 09:31:06.637469 Set Vref, RX VrefLevel [Byte0]: 30
7817 09:31:06.640554 [Byte1]: 30
7818 09:31:06.640631
7819 09:31:06.644088 Set Vref, RX VrefLevel [Byte0]: 31
7820 09:31:06.647397 [Byte1]: 31
7821 09:31:06.647473
7822 09:31:06.650855 Set Vref, RX VrefLevel [Byte0]: 32
7823 09:31:06.654388 [Byte1]: 32
7824 09:31:06.654460
7825 09:31:06.657291 Set Vref, RX VrefLevel [Byte0]: 33
7826 09:31:06.660775 [Byte1]: 33
7827 09:31:06.664755
7828 09:31:06.664854 Set Vref, RX VrefLevel [Byte0]: 34
7829 09:31:06.667827 [Byte1]: 34
7830 09:31:06.672371
7831 09:31:06.672445 Set Vref, RX VrefLevel [Byte0]: 35
7832 09:31:06.675547 [Byte1]: 35
7833 09:31:06.680150
7834 09:31:06.680277 Set Vref, RX VrefLevel [Byte0]: 36
7835 09:31:06.683137 [Byte1]: 36
7836 09:31:06.687435
7837 09:31:06.687548 Set Vref, RX VrefLevel [Byte0]: 37
7838 09:31:06.690869 [Byte1]: 37
7839 09:31:06.694788
7840 09:31:06.694895 Set Vref, RX VrefLevel [Byte0]: 38
7841 09:31:06.698365 [Byte1]: 38
7842 09:31:06.702385
7843 09:31:06.702502 Set Vref, RX VrefLevel [Byte0]: 39
7844 09:31:06.705800 [Byte1]: 39
7845 09:31:06.710271
7846 09:31:06.710387 Set Vref, RX VrefLevel [Byte0]: 40
7847 09:31:06.713329 [Byte1]: 40
7848 09:31:06.717860
7849 09:31:06.717987 Set Vref, RX VrefLevel [Byte0]: 41
7850 09:31:06.720812 [Byte1]: 41
7851 09:31:06.725170
7852 09:31:06.725297 Set Vref, RX VrefLevel [Byte0]: 42
7853 09:31:06.728577 [Byte1]: 42
7854 09:31:06.732838
7855 09:31:06.732948 Set Vref, RX VrefLevel [Byte0]: 43
7856 09:31:06.736425 [Byte1]: 43
7857 09:31:06.740534
7858 09:31:06.740612 Set Vref, RX VrefLevel [Byte0]: 44
7859 09:31:06.743545 [Byte1]: 44
7860 09:31:06.747988
7861 09:31:06.748065 Set Vref, RX VrefLevel [Byte0]: 45
7862 09:31:06.751489 [Byte1]: 45
7863 09:31:06.755913
7864 09:31:06.756004 Set Vref, RX VrefLevel [Byte0]: 46
7865 09:31:06.758856 [Byte1]: 46
7866 09:31:06.763222
7867 09:31:06.763308 Set Vref, RX VrefLevel [Byte0]: 47
7868 09:31:06.766313 [Byte1]: 47
7869 09:31:06.770372
7870 09:31:06.770483 Set Vref, RX VrefLevel [Byte0]: 48
7871 09:31:06.773917 [Byte1]: 48
7872 09:31:06.778113
7873 09:31:06.778215 Set Vref, RX VrefLevel [Byte0]: 49
7874 09:31:06.781665 [Byte1]: 49
7875 09:31:06.785799
7876 09:31:06.785913 Set Vref, RX VrefLevel [Byte0]: 50
7877 09:31:06.789404 [Byte1]: 50
7878 09:31:06.793440
7879 09:31:06.793518 Set Vref, RX VrefLevel [Byte0]: 51
7880 09:31:06.796554 [Byte1]: 51
7881 09:31:06.800760
7882 09:31:06.800863 Set Vref, RX VrefLevel [Byte0]: 52
7883 09:31:06.804325 [Byte1]: 52
7884 09:31:06.808781
7885 09:31:06.808882 Set Vref, RX VrefLevel [Byte0]: 53
7886 09:31:06.811654 [Byte1]: 53
7887 09:31:06.816117
7888 09:31:06.816291 Set Vref, RX VrefLevel [Byte0]: 54
7889 09:31:06.819602 [Byte1]: 54
7890 09:31:06.823960
7891 09:31:06.824054 Set Vref, RX VrefLevel [Byte0]: 55
7892 09:31:06.827269 [Byte1]: 55
7893 09:31:06.831232
7894 09:31:06.831323 Set Vref, RX VrefLevel [Byte0]: 56
7895 09:31:06.834590 [Byte1]: 56
7896 09:31:06.838761
7897 09:31:06.838844 Set Vref, RX VrefLevel [Byte0]: 57
7898 09:31:06.842402 [Byte1]: 57
7899 09:31:06.846458
7900 09:31:06.846541 Set Vref, RX VrefLevel [Byte0]: 58
7901 09:31:06.849697 [Byte1]: 58
7902 09:31:06.853717
7903 09:31:06.853800 Set Vref, RX VrefLevel [Byte0]: 59
7904 09:31:06.857258 [Byte1]: 59
7905 09:31:06.861790
7906 09:31:06.861874 Set Vref, RX VrefLevel [Byte0]: 60
7907 09:31:06.864813 [Byte1]: 60
7908 09:31:06.868854
7909 09:31:06.868946 Set Vref, RX VrefLevel [Byte0]: 61
7910 09:31:06.872489 [Byte1]: 61
7911 09:31:06.876515
7912 09:31:06.876616 Set Vref, RX VrefLevel [Byte0]: 62
7913 09:31:06.879797 [Byte1]: 62
7914 09:31:06.884145
7915 09:31:06.884228 Set Vref, RX VrefLevel [Byte0]: 63
7916 09:31:06.887777 [Byte1]: 63
7917 09:31:06.891894
7918 09:31:06.891993 Set Vref, RX VrefLevel [Byte0]: 64
7919 09:31:06.895233 [Byte1]: 64
7920 09:31:06.899278
7921 09:31:06.899361 Set Vref, RX VrefLevel [Byte0]: 65
7922 09:31:06.902782 [Byte1]: 65
7923 09:31:06.906882
7924 09:31:06.906965 Set Vref, RX VrefLevel [Byte0]: 66
7925 09:31:06.910113 [Byte1]: 66
7926 09:31:06.914710
7927 09:31:06.914794 Set Vref, RX VrefLevel [Byte0]: 67
7928 09:31:06.917664 [Byte1]: 67
7929 09:31:06.922337
7930 09:31:06.922420 Set Vref, RX VrefLevel [Byte0]: 68
7931 09:31:06.925297 [Byte1]: 68
7932 09:31:06.929902
7933 09:31:06.930024 Set Vref, RX VrefLevel [Byte0]: 69
7934 09:31:06.932851 [Byte1]: 69
7935 09:31:06.937204
7936 09:31:06.937347 Set Vref, RX VrefLevel [Byte0]: 70
7937 09:31:06.940749 [Byte1]: 70
7938 09:31:06.944984
7939 09:31:06.945094 Set Vref, RX VrefLevel [Byte0]: 71
7940 09:31:06.948083 [Byte1]: 71
7941 09:31:06.952633
7942 09:31:06.952731 Set Vref, RX VrefLevel [Byte0]: 72
7943 09:31:06.955678 [Byte1]: 72
7944 09:31:06.960094
7945 09:31:06.960188 Set Vref, RX VrefLevel [Byte0]: 73
7946 09:31:06.963510 [Byte1]: 73
7947 09:31:06.967556
7948 09:31:06.967668 Set Vref, RX VrefLevel [Byte0]: 74
7949 09:31:06.970724 [Byte1]: 74
7950 09:31:06.974977
7951 09:31:06.975054 Set Vref, RX VrefLevel [Byte0]: 75
7952 09:31:06.978169 [Byte1]: 75
7953 09:31:06.982931
7954 09:31:06.983005 Set Vref, RX VrefLevel [Byte0]: 76
7955 09:31:06.986056 [Byte1]: 76
7956 09:31:06.990193
7957 09:31:06.990267 Set Vref, RX VrefLevel [Byte0]: 77
7958 09:31:06.993361 [Byte1]: 77
7959 09:31:06.997949
7960 09:31:06.998023 Set Vref, RX VrefLevel [Byte0]: 78
7961 09:31:07.001341 [Byte1]: 78
7962 09:31:07.005222
7963 09:31:07.005307 Final RX Vref Byte 0 = 57 to rank0
7964 09:31:07.008803 Final RX Vref Byte 1 = 60 to rank0
7965 09:31:07.011954 Final RX Vref Byte 0 = 57 to rank1
7966 09:31:07.015673 Final RX Vref Byte 1 = 60 to rank1==
7967 09:31:07.018601 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 09:31:07.025313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 09:31:07.025396 ==
7970 09:31:07.025464 DQS Delay:
7971 09:31:07.025525 DQS0 = 0, DQS1 = 0
7972 09:31:07.028780 DQM Delay:
7973 09:31:07.028899 DQM0 = 135, DQM1 = 124
7974 09:31:07.031765 DQ Delay:
7975 09:31:07.035310 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7976 09:31:07.038939 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7977 09:31:07.041904 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7978 09:31:07.045398 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7979 09:31:07.045476
7980 09:31:07.045541
7981 09:31:07.045602
7982 09:31:07.048545 [DramC_TX_OE_Calibration] TA2
7983 09:31:07.052133 Original DQ_B0 (3 6) =30, OEN = 27
7984 09:31:07.055226 Original DQ_B1 (3 6) =30, OEN = 27
7985 09:31:07.058525 24, 0x0, End_B0=24 End_B1=24
7986 09:31:07.058612 25, 0x0, End_B0=25 End_B1=25
7987 09:31:07.061977 26, 0x0, End_B0=26 End_B1=26
7988 09:31:07.065090 27, 0x0, End_B0=27 End_B1=27
7989 09:31:07.068745 28, 0x0, End_B0=28 End_B1=28
7990 09:31:07.068830 29, 0x0, End_B0=29 End_B1=29
7991 09:31:07.071956 30, 0x0, End_B0=30 End_B1=30
7992 09:31:07.074959 31, 0x4141, End_B0=30 End_B1=30
7993 09:31:07.078505 Byte0 end_step=30 best_step=27
7994 09:31:07.081664 Byte1 end_step=30 best_step=27
7995 09:31:07.084967 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 09:31:07.088797 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 09:31:07.088869
7998 09:31:07.088951
7999 09:31:07.095060 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8000 09:31:07.098599 CH0 RK0: MR19=303, MR18=1E1C
8001 09:31:07.105136 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8002 09:31:07.105241
8003 09:31:07.108734 ----->DramcWriteLeveling(PI) begin...
8004 09:31:07.108841 ==
8005 09:31:07.111713 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 09:31:07.114868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 09:31:07.114950 ==
8008 09:31:07.118484 Write leveling (Byte 0): 37 => 37
8009 09:31:07.121563 Write leveling (Byte 1): 29 => 29
8010 09:31:07.124696 DramcWriteLeveling(PI) end<-----
8011 09:31:07.124783
8012 09:31:07.124877 ==
8013 09:31:07.128319 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 09:31:07.131787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 09:31:07.131892 ==
8016 09:31:07.134723 [Gating] SW mode calibration
8017 09:31:07.141646 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 09:31:07.148155 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 09:31:07.151755 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 09:31:07.154859 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 09:31:07.161730 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 09:31:07.164889 1 4 12 | B1->B0 | 2626 3131 | 0 1 | (0 0) (0 0)
8023 09:31:07.168037 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8024 09:31:07.174670 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 09:31:07.178139 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 09:31:07.181444 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 09:31:07.188186 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 09:31:07.191375 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 09:31:07.194873 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 09:31:07.201281 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (0 1) (0 0)
8031 09:31:07.204839 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8032 09:31:07.208259 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 09:31:07.215154 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 09:31:07.218255 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 09:31:07.221303 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 09:31:07.228270 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 09:31:07.231244 1 6 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8038 09:31:07.234863 1 6 12 | B1->B0 | 3232 4544 | 1 1 | (0 0) (0 0)
8039 09:31:07.241552 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 09:31:07.244570 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 09:31:07.247961 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 09:31:07.254859 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 09:31:07.258360 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 09:31:07.261408 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 09:31:07.264422 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 09:31:07.271207 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 09:31:07.274518 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8048 09:31:07.278093 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 09:31:07.284555 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 09:31:07.288128 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 09:31:07.291151 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 09:31:07.297777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 09:31:07.300912 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 09:31:07.304442 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 09:31:07.310913 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 09:31:07.314121 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 09:31:07.317584 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 09:31:07.324141 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 09:31:07.327666 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 09:31:07.330985 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 09:31:07.337450 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 09:31:07.341028 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8063 09:31:07.343913 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 09:31:07.347305 Total UI for P1: 0, mck2ui 16
8065 09:31:07.350738 best dqsien dly found for B0: ( 1, 9, 10)
8066 09:31:07.357449 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 09:31:07.357546 Total UI for P1: 0, mck2ui 16
8068 09:31:07.364089 best dqsien dly found for B1: ( 1, 9, 14)
8069 09:31:07.367148 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8070 09:31:07.370735 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8071 09:31:07.370803
8072 09:31:07.374310 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8073 09:31:07.377122 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8074 09:31:07.380812 [Gating] SW calibration Done
8075 09:31:07.380896 ==
8076 09:31:07.383747 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 09:31:07.387260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 09:31:07.387333 ==
8079 09:31:07.390834 RX Vref Scan: 0
8080 09:31:07.390903
8081 09:31:07.390962 RX Vref 0 -> 0, step: 1
8082 09:31:07.391018
8083 09:31:07.394306 RX Delay 0 -> 252, step: 8
8084 09:31:07.397473 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8085 09:31:07.404014 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8086 09:31:07.407433 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8087 09:31:07.410996 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8088 09:31:07.414095 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8089 09:31:07.417500 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8090 09:31:07.424273 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8091 09:31:07.427394 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8092 09:31:07.430488 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8093 09:31:07.433900 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8094 09:31:07.437303 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8095 09:31:07.443859 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8096 09:31:07.447263 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8097 09:31:07.450668 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8098 09:31:07.454175 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8099 09:31:07.457545 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8100 09:31:07.457657 ==
8101 09:31:07.460745 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 09:31:07.467352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 09:31:07.467454 ==
8104 09:31:07.467562 DQS Delay:
8105 09:31:07.470875 DQS0 = 0, DQS1 = 0
8106 09:31:07.470976 DQM Delay:
8107 09:31:07.473983 DQM0 = 136, DQM1 = 125
8108 09:31:07.474083 DQ Delay:
8109 09:31:07.477110 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8110 09:31:07.480531 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8111 09:31:07.483907 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8112 09:31:07.487096 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8113 09:31:07.487201
8114 09:31:07.487293
8115 09:31:07.487395 ==
8116 09:31:07.490731 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 09:31:07.497408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 09:31:07.497491 ==
8119 09:31:07.497555
8120 09:31:07.497616
8121 09:31:07.497674 TX Vref Scan disable
8122 09:31:07.500506 == TX Byte 0 ==
8123 09:31:07.504137 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8124 09:31:07.507255 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8125 09:31:07.510899 == TX Byte 1 ==
8126 09:31:07.514073 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8127 09:31:07.520360 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8128 09:31:07.520443 ==
8129 09:31:07.523770 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 09:31:07.527138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 09:31:07.527256 ==
8132 09:31:07.540167
8133 09:31:07.543708 TX Vref early break, caculate TX vref
8134 09:31:07.546878 TX Vref=16, minBit 0, minWin=23, winSum=389
8135 09:31:07.550397 TX Vref=18, minBit 0, minWin=23, winSum=392
8136 09:31:07.553781 TX Vref=20, minBit 8, minWin=24, winSum=406
8137 09:31:07.557329 TX Vref=22, minBit 2, minWin=25, winSum=413
8138 09:31:07.560255 TX Vref=24, minBit 0, minWin=25, winSum=424
8139 09:31:07.566793 TX Vref=26, minBit 8, minWin=25, winSum=428
8140 09:31:07.570443 TX Vref=28, minBit 0, minWin=26, winSum=431
8141 09:31:07.573514 TX Vref=30, minBit 8, minWin=25, winSum=427
8142 09:31:07.577145 TX Vref=32, minBit 0, minWin=25, winSum=415
8143 09:31:07.580292 TX Vref=34, minBit 2, minWin=24, winSum=407
8144 09:31:07.586852 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8145 09:31:07.586954
8146 09:31:07.590135 Final TX Range 0 Vref 28
8147 09:31:07.590207
8148 09:31:07.590268 ==
8149 09:31:07.593628 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 09:31:07.597110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 09:31:07.597205 ==
8152 09:31:07.597296
8153 09:31:07.597382
8154 09:31:07.600242 TX Vref Scan disable
8155 09:31:07.607066 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8156 09:31:07.607187 == TX Byte 0 ==
8157 09:31:07.610170 u2DelayCellOfst[0]=13 cells (4 PI)
8158 09:31:07.613292 u2DelayCellOfst[1]=20 cells (6 PI)
8159 09:31:07.616864 u2DelayCellOfst[2]=13 cells (4 PI)
8160 09:31:07.619892 u2DelayCellOfst[3]=13 cells (4 PI)
8161 09:31:07.623557 u2DelayCellOfst[4]=10 cells (3 PI)
8162 09:31:07.626565 u2DelayCellOfst[5]=0 cells (0 PI)
8163 09:31:07.629950 u2DelayCellOfst[6]=20 cells (6 PI)
8164 09:31:07.633567 u2DelayCellOfst[7]=20 cells (6 PI)
8165 09:31:07.636806 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8166 09:31:07.639744 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8167 09:31:07.643168 == TX Byte 1 ==
8168 09:31:07.643278 u2DelayCellOfst[8]=0 cells (0 PI)
8169 09:31:07.646695 u2DelayCellOfst[9]=0 cells (0 PI)
8170 09:31:07.650114 u2DelayCellOfst[10]=3 cells (1 PI)
8171 09:31:07.653404 u2DelayCellOfst[11]=0 cells (0 PI)
8172 09:31:07.656733 u2DelayCellOfst[12]=13 cells (4 PI)
8173 09:31:07.659769 u2DelayCellOfst[13]=10 cells (3 PI)
8174 09:31:07.663282 u2DelayCellOfst[14]=10 cells (3 PI)
8175 09:31:07.666683 u2DelayCellOfst[15]=6 cells (2 PI)
8176 09:31:07.670198 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8177 09:31:07.676467 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8178 09:31:07.676579 DramC Write-DBI on
8179 09:31:07.676645 ==
8180 09:31:07.680083 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 09:31:07.683101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 09:31:07.683188 ==
8183 09:31:07.686261
8184 09:31:07.686358
8185 09:31:07.686437 TX Vref Scan disable
8186 09:31:07.689775 == TX Byte 0 ==
8187 09:31:07.693263 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8188 09:31:07.696369 == TX Byte 1 ==
8189 09:31:07.700006 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8190 09:31:07.700091 DramC Write-DBI off
8191 09:31:07.703072
8192 09:31:07.703182 [DATLAT]
8193 09:31:07.703278 Freq=1600, CH0 RK1
8194 09:31:07.703381
8195 09:31:07.706798 DATLAT Default: 0xf
8196 09:31:07.706903 0, 0xFFFF, sum = 0
8197 09:31:07.709953 1, 0xFFFF, sum = 0
8198 09:31:07.710031 2, 0xFFFF, sum = 0
8199 09:31:07.713109 3, 0xFFFF, sum = 0
8200 09:31:07.716360 4, 0xFFFF, sum = 0
8201 09:31:07.716433 5, 0xFFFF, sum = 0
8202 09:31:07.719996 6, 0xFFFF, sum = 0
8203 09:31:07.720082 7, 0xFFFF, sum = 0
8204 09:31:07.723068 8, 0xFFFF, sum = 0
8205 09:31:07.723154 9, 0xFFFF, sum = 0
8206 09:31:07.726260 10, 0xFFFF, sum = 0
8207 09:31:07.726347 11, 0xFFFF, sum = 0
8208 09:31:07.729802 12, 0xFFFF, sum = 0
8209 09:31:07.729890 13, 0xFFFF, sum = 0
8210 09:31:07.732805 14, 0x0, sum = 1
8211 09:31:07.732892 15, 0x0, sum = 2
8212 09:31:07.736274 16, 0x0, sum = 3
8213 09:31:07.736361 17, 0x0, sum = 4
8214 09:31:07.739952 best_step = 15
8215 09:31:07.740037
8216 09:31:07.740104 ==
8217 09:31:07.742902 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 09:31:07.746088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 09:31:07.746174 ==
8220 09:31:07.749283 RX Vref Scan: 0
8221 09:31:07.749366
8222 09:31:07.749436 RX Vref 0 -> 0, step: 1
8223 09:31:07.749528
8224 09:31:07.752769 RX Delay 11 -> 252, step: 4
8225 09:31:07.756501 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8226 09:31:07.762972 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8227 09:31:07.766107 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8228 09:31:07.769483 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8229 09:31:07.772962 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8230 09:31:07.775988 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8231 09:31:07.782723 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8232 09:31:07.785915 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8233 09:31:07.789576 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8234 09:31:07.792685 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8235 09:31:07.796071 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8236 09:31:07.802815 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8237 09:31:07.806312 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8238 09:31:07.809357 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8239 09:31:07.813034 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8240 09:31:07.816119 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8241 09:31:07.819294 ==
8242 09:31:07.819372 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 09:31:07.826063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 09:31:07.826188 ==
8245 09:31:07.826265 DQS Delay:
8246 09:31:07.829341 DQS0 = 0, DQS1 = 0
8247 09:31:07.829425 DQM Delay:
8248 09:31:07.832923 DQM0 = 132, DQM1 = 123
8249 09:31:07.833017 DQ Delay:
8250 09:31:07.836305 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8251 09:31:07.839158 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8252 09:31:07.842784 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8253 09:31:07.846061 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8254 09:31:07.846145
8255 09:31:07.846211
8256 09:31:07.846272
8257 09:31:07.849204 [DramC_TX_OE_Calibration] TA2
8258 09:31:07.852620 Original DQ_B0 (3 6) =30, OEN = 27
8259 09:31:07.856250 Original DQ_B1 (3 6) =30, OEN = 27
8260 09:31:07.859284 24, 0x0, End_B0=24 End_B1=24
8261 09:31:07.862746 25, 0x0, End_B0=25 End_B1=25
8262 09:31:07.862822 26, 0x0, End_B0=26 End_B1=26
8263 09:31:07.866082 27, 0x0, End_B0=27 End_B1=27
8264 09:31:07.869445 28, 0x0, End_B0=28 End_B1=28
8265 09:31:07.872773 29, 0x0, End_B0=29 End_B1=29
8266 09:31:07.872899 30, 0x0, End_B0=30 End_B1=30
8267 09:31:07.876322 31, 0x4141, End_B0=30 End_B1=30
8268 09:31:07.879164 Byte0 end_step=30 best_step=27
8269 09:31:07.882697 Byte1 end_step=30 best_step=27
8270 09:31:07.885763 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 09:31:07.888803 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 09:31:07.888908
8273 09:31:07.888994
8274 09:31:07.895573 [DQSOSCAuto] RK1, (LSB)MR18= 0x200e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8275 09:31:07.898920 CH0 RK1: MR19=303, MR18=200E
8276 09:31:07.905609 CH0_RK1: MR19=0x303, MR18=0x200E, DQSOSC=393, MR23=63, INC=23, DEC=15
8277 09:31:07.909116 [RxdqsGatingPostProcess] freq 1600
8278 09:31:07.912782 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 09:31:07.915910 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 09:31:07.919024 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 09:31:07.922683 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 09:31:07.925807 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 09:31:07.929031 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 09:31:07.932634 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 09:31:07.935898 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 09:31:07.938879 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 09:31:07.942334 Pre-setting of DQS Precalculation
8288 09:31:07.945431 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 09:31:07.945509 ==
8290 09:31:07.948840 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 09:31:07.955425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 09:31:07.955500 ==
8293 09:31:07.958847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 09:31:07.962499 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 09:31:07.969274 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 09:31:07.975242 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 09:31:07.982688 [CA 0] Center 41 (12~71) winsize 60
8298 09:31:07.986311 [CA 1] Center 42 (12~72) winsize 61
8299 09:31:07.989459 [CA 2] Center 38 (9~68) winsize 60
8300 09:31:07.992615 [CA 3] Center 37 (8~67) winsize 60
8301 09:31:07.995813 [CA 4] Center 37 (7~67) winsize 61
8302 09:31:07.999404 [CA 5] Center 37 (7~67) winsize 61
8303 09:31:07.999478
8304 09:31:08.002451 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8305 09:31:08.002524
8306 09:31:08.006144 [CATrainingPosCal] consider 1 rank data
8307 09:31:08.009293 u2DelayCellTimex100 = 290/100 ps
8308 09:31:08.012749 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8309 09:31:08.019251 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8310 09:31:08.022778 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8311 09:31:08.025947 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8312 09:31:08.029490 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8313 09:31:08.032607 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8314 09:31:08.032692
8315 09:31:08.035773 CA PerBit enable=1, Macro0, CA PI delay=37
8316 09:31:08.035857
8317 09:31:08.039006 [CBTSetCACLKResult] CA Dly = 37
8318 09:31:08.042525 CS Dly: 8 (0~39)
8319 09:31:08.046035 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 09:31:08.049311 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 09:31:08.049395 ==
8322 09:31:08.052526 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 09:31:08.056107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 09:31:08.056193 ==
8325 09:31:08.062538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 09:31:08.065955 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 09:31:08.072306 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 09:31:08.075761 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 09:31:08.085961 [CA 0] Center 42 (13~72) winsize 60
8330 09:31:08.089462 [CA 1] Center 42 (13~72) winsize 60
8331 09:31:08.092522 [CA 2] Center 39 (10~68) winsize 59
8332 09:31:08.096145 [CA 3] Center 37 (8~67) winsize 60
8333 09:31:08.099311 [CA 4] Center 38 (9~68) winsize 60
8334 09:31:08.102793 [CA 5] Center 37 (8~67) winsize 60
8335 09:31:08.102874
8336 09:31:08.105923 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8337 09:31:08.106005
8338 09:31:08.109289 [CATrainingPosCal] consider 2 rank data
8339 09:31:08.112472 u2DelayCellTimex100 = 290/100 ps
8340 09:31:08.115709 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8341 09:31:08.122319 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8342 09:31:08.125826 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8343 09:31:08.128988 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8344 09:31:08.132535 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 09:31:08.135611 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8346 09:31:08.135691
8347 09:31:08.139149 CA PerBit enable=1, Macro0, CA PI delay=37
8348 09:31:08.139244
8349 09:31:08.142276 [CBTSetCACLKResult] CA Dly = 37
8350 09:31:08.145975 CS Dly: 9 (0~41)
8351 09:31:08.148799 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 09:31:08.152322 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 09:31:08.152402
8354 09:31:08.155531 ----->DramcWriteLeveling(PI) begin...
8355 09:31:08.155613 ==
8356 09:31:08.159238 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 09:31:08.162202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 09:31:08.165884 ==
8359 09:31:08.165964 Write leveling (Byte 0): 24 => 24
8360 09:31:08.168840 Write leveling (Byte 1): 28 => 28
8361 09:31:08.172311 DramcWriteLeveling(PI) end<-----
8362 09:31:08.172391
8363 09:31:08.172455 ==
8364 09:31:08.175797 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 09:31:08.182329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 09:31:08.182421 ==
8367 09:31:08.185715 [Gating] SW mode calibration
8368 09:31:08.192469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 09:31:08.195627 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 09:31:08.202267 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 09:31:08.206167 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 09:31:08.209330 1 4 8 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (1 1)
8373 09:31:08.212776 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8374 09:31:08.219245 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 09:31:08.222606 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 09:31:08.226181 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 09:31:08.232309 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 09:31:08.235955 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 09:31:08.239013 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 09:31:08.245660 1 5 8 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (0 1)
8381 09:31:08.249277 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8382 09:31:08.252172 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 09:31:08.259347 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 09:31:08.262904 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 09:31:08.265695 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 09:31:08.272109 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 09:31:08.275548 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8388 09:31:08.279066 1 6 8 | B1->B0 | 3737 3f3f | 0 1 | (0 0) (0 0)
8389 09:31:08.286022 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 09:31:08.288904 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 09:31:08.292207 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 09:31:08.298893 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 09:31:08.302486 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 09:31:08.305510 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 09:31:08.312588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8396 09:31:08.315480 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8397 09:31:08.318755 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 09:31:08.325179 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 09:31:08.328476 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 09:31:08.331639 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 09:31:08.338695 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 09:31:08.341811 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 09:31:08.344896 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 09:31:08.351652 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 09:31:08.355156 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 09:31:08.357887 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 09:31:08.364859 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 09:31:08.368062 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 09:31:08.371615 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 09:31:08.375132 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 09:31:08.381838 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 09:31:08.385150 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8413 09:31:08.388325 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8414 09:31:08.391513 Total UI for P1: 0, mck2ui 16
8415 09:31:08.395101 best dqsien dly found for B0: ( 1, 9, 6)
8416 09:31:08.401835 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 09:31:08.405043 Total UI for P1: 0, mck2ui 16
8418 09:31:08.408448 best dqsien dly found for B1: ( 1, 9, 8)
8419 09:31:08.411694 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8420 09:31:08.415396 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8421 09:31:08.415801
8422 09:31:08.418466 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8423 09:31:08.421769 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8424 09:31:08.425327 [Gating] SW calibration Done
8425 09:31:08.425792 ==
8426 09:31:08.428338 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 09:31:08.431828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 09:31:08.432396 ==
8429 09:31:08.435496 RX Vref Scan: 0
8430 09:31:08.436068
8431 09:31:08.436459 RX Vref 0 -> 0, step: 1
8432 09:31:08.438271
8433 09:31:08.438740 RX Delay 0 -> 252, step: 8
8434 09:31:08.442062 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8435 09:31:08.448279 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8436 09:31:08.451819 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8437 09:31:08.454691 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8438 09:31:08.458391 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8439 09:31:08.461318 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8440 09:31:08.468339 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8441 09:31:08.471826 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8442 09:31:08.474750 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8443 09:31:08.478140 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8444 09:31:08.481710 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8445 09:31:08.488123 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8446 09:31:08.491375 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8447 09:31:08.494604 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8448 09:31:08.498282 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8449 09:31:08.501386 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8450 09:31:08.504654 ==
8451 09:31:08.505166 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 09:31:08.511467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 09:31:08.512033 ==
8454 09:31:08.512409 DQS Delay:
8455 09:31:08.514839 DQS0 = 0, DQS1 = 0
8456 09:31:08.515302 DQM Delay:
8457 09:31:08.518226 DQM0 = 137, DQM1 = 129
8458 09:31:08.518818 DQ Delay:
8459 09:31:08.521497 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8460 09:31:08.525007 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8461 09:31:08.527673 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8462 09:31:08.531304 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8463 09:31:08.531809
8464 09:31:08.532186
8465 09:31:08.532526 ==
8466 09:31:08.534318 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 09:31:08.540868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 09:31:08.541475 ==
8469 09:31:08.541845
8470 09:31:08.542199
8471 09:31:08.542542 TX Vref Scan disable
8472 09:31:08.544897 == TX Byte 0 ==
8473 09:31:08.548258 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8474 09:31:08.554718 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8475 09:31:08.555145 == TX Byte 1 ==
8476 09:31:08.557928 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8477 09:31:08.564676 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8478 09:31:08.565284 ==
8479 09:31:08.568074 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 09:31:08.571609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 09:31:08.572177 ==
8482 09:31:08.583530
8483 09:31:08.586971 TX Vref early break, caculate TX vref
8484 09:31:08.590405 TX Vref=16, minBit 10, minWin=21, winSum=366
8485 09:31:08.593566 TX Vref=18, minBit 10, minWin=22, winSum=382
8486 09:31:08.596813 TX Vref=20, minBit 10, minWin=23, winSum=392
8487 09:31:08.600624 TX Vref=22, minBit 10, minWin=23, winSum=397
8488 09:31:08.606870 TX Vref=24, minBit 10, minWin=23, winSum=405
8489 09:31:08.609966 TX Vref=26, minBit 10, minWin=24, winSum=418
8490 09:31:08.613523 TX Vref=28, minBit 10, minWin=25, winSum=418
8491 09:31:08.616699 TX Vref=30, minBit 0, minWin=25, winSum=414
8492 09:31:08.620094 TX Vref=32, minBit 10, minWin=24, winSum=409
8493 09:31:08.623589 TX Vref=34, minBit 9, minWin=23, winSum=395
8494 09:31:08.630017 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 28
8495 09:31:08.630774
8496 09:31:08.633738 Final TX Range 0 Vref 28
8497 09:31:08.634305
8498 09:31:08.634673 ==
8499 09:31:08.636685 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 09:31:08.640055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 09:31:08.640688 ==
8502 09:31:08.641144
8503 09:31:08.643373
8504 09:31:08.643931 TX Vref Scan disable
8505 09:31:08.649800 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8506 09:31:08.650348 == TX Byte 0 ==
8507 09:31:08.653559 u2DelayCellOfst[0]=16 cells (5 PI)
8508 09:31:08.657311 u2DelayCellOfst[1]=10 cells (3 PI)
8509 09:31:08.660457 u2DelayCellOfst[2]=0 cells (0 PI)
8510 09:31:08.663306 u2DelayCellOfst[3]=3 cells (1 PI)
8511 09:31:08.666840 u2DelayCellOfst[4]=6 cells (2 PI)
8512 09:31:08.669767 u2DelayCellOfst[5]=16 cells (5 PI)
8513 09:31:08.673163 u2DelayCellOfst[6]=16 cells (5 PI)
8514 09:31:08.676614 u2DelayCellOfst[7]=6 cells (2 PI)
8515 09:31:08.679733 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8516 09:31:08.683279 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8517 09:31:08.686200 == TX Byte 1 ==
8518 09:31:08.689693 u2DelayCellOfst[8]=0 cells (0 PI)
8519 09:31:08.690160 u2DelayCellOfst[9]=6 cells (2 PI)
8520 09:31:08.693177 u2DelayCellOfst[10]=10 cells (3 PI)
8521 09:31:08.696241 u2DelayCellOfst[11]=3 cells (1 PI)
8522 09:31:08.699835 u2DelayCellOfst[12]=16 cells (5 PI)
8523 09:31:08.703376 u2DelayCellOfst[13]=20 cells (6 PI)
8524 09:31:08.706495 u2DelayCellOfst[14]=20 cells (6 PI)
8525 09:31:08.709606 u2DelayCellOfst[15]=16 cells (5 PI)
8526 09:31:08.716166 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8527 09:31:08.719751 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8528 09:31:08.720175 DramC Write-DBI on
8529 09:31:08.720509 ==
8530 09:31:08.723131 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 09:31:08.729621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 09:31:08.730168 ==
8533 09:31:08.730512
8534 09:31:08.730844
8535 09:31:08.731138 TX Vref Scan disable
8536 09:31:08.733461 == TX Byte 0 ==
8537 09:31:08.737194 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8538 09:31:08.740707 == TX Byte 1 ==
8539 09:31:08.743495 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8540 09:31:08.747186 DramC Write-DBI off
8541 09:31:08.747716
8542 09:31:08.748054 [DATLAT]
8543 09:31:08.748366 Freq=1600, CH1 RK0
8544 09:31:08.748668
8545 09:31:08.750196 DATLAT Default: 0xf
8546 09:31:08.750618 0, 0xFFFF, sum = 0
8547 09:31:08.753290 1, 0xFFFF, sum = 0
8548 09:31:08.753716 2, 0xFFFF, sum = 0
8549 09:31:08.757075 3, 0xFFFF, sum = 0
8550 09:31:08.760274 4, 0xFFFF, sum = 0
8551 09:31:08.760803 5, 0xFFFF, sum = 0
8552 09:31:08.763959 6, 0xFFFF, sum = 0
8553 09:31:08.764485 7, 0xFFFF, sum = 0
8554 09:31:08.766639 8, 0xFFFF, sum = 0
8555 09:31:08.767072 9, 0xFFFF, sum = 0
8556 09:31:08.770174 10, 0xFFFF, sum = 0
8557 09:31:08.770611 11, 0xFFFF, sum = 0
8558 09:31:08.773514 12, 0xFFFF, sum = 0
8559 09:31:08.774064 13, 0xFFFF, sum = 0
8560 09:31:08.776770 14, 0x0, sum = 1
8561 09:31:08.777225 15, 0x0, sum = 2
8562 09:31:08.780541 16, 0x0, sum = 3
8563 09:31:08.781124 17, 0x0, sum = 4
8564 09:31:08.783387 best_step = 15
8565 09:31:08.783972
8566 09:31:08.784448 ==
8567 09:31:08.787163 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 09:31:08.789942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 09:31:08.790559 ==
8570 09:31:08.791062 RX Vref Scan: 1
8571 09:31:08.793359
8572 09:31:08.793937 Set Vref Range= 24 -> 127
8573 09:31:08.794413
8574 09:31:08.796580 RX Vref 24 -> 127, step: 1
8575 09:31:08.797108
8576 09:31:08.800353 RX Delay 19 -> 252, step: 4
8577 09:31:08.800963
8578 09:31:08.803225 Set Vref, RX VrefLevel [Byte0]: 24
8579 09:31:08.806565 [Byte1]: 24
8580 09:31:08.807040
8581 09:31:08.809949 Set Vref, RX VrefLevel [Byte0]: 25
8582 09:31:08.813411 [Byte1]: 25
8583 09:31:08.813893
8584 09:31:08.816589 Set Vref, RX VrefLevel [Byte0]: 26
8585 09:31:08.820297 [Byte1]: 26
8586 09:31:08.824104
8587 09:31:08.824678 Set Vref, RX VrefLevel [Byte0]: 27
8588 09:31:08.826856 [Byte1]: 27
8589 09:31:08.831415
8590 09:31:08.831887 Set Vref, RX VrefLevel [Byte0]: 28
8591 09:31:08.834835 [Byte1]: 28
8592 09:31:08.838868
8593 09:31:08.839437 Set Vref, RX VrefLevel [Byte0]: 29
8594 09:31:08.842141 [Byte1]: 29
8595 09:31:08.846815
8596 09:31:08.847388 Set Vref, RX VrefLevel [Byte0]: 30
8597 09:31:08.849676 [Byte1]: 30
8598 09:31:08.854280
8599 09:31:08.854868 Set Vref, RX VrefLevel [Byte0]: 31
8600 09:31:08.857270 [Byte1]: 31
8601 09:31:08.861763
8602 09:31:08.862333 Set Vref, RX VrefLevel [Byte0]: 32
8603 09:31:08.865009 [Byte1]: 32
8604 09:31:08.869569
8605 09:31:08.870144 Set Vref, RX VrefLevel [Byte0]: 33
8606 09:31:08.872453 [Byte1]: 33
8607 09:31:08.877033
8608 09:31:08.877602 Set Vref, RX VrefLevel [Byte0]: 34
8609 09:31:08.879987 [Byte1]: 34
8610 09:31:08.884327
8611 09:31:08.884895 Set Vref, RX VrefLevel [Byte0]: 35
8612 09:31:08.887816 [Byte1]: 35
8613 09:31:08.892247
8614 09:31:08.892820 Set Vref, RX VrefLevel [Byte0]: 36
8615 09:31:08.895152 [Byte1]: 36
8616 09:31:08.899471
8617 09:31:08.900045 Set Vref, RX VrefLevel [Byte0]: 37
8618 09:31:08.902925 [Byte1]: 37
8619 09:31:08.907272
8620 09:31:08.907746 Set Vref, RX VrefLevel [Byte0]: 38
8621 09:31:08.910143 [Byte1]: 38
8622 09:31:08.914641
8623 09:31:08.915215 Set Vref, RX VrefLevel [Byte0]: 39
8624 09:31:08.918027 [Byte1]: 39
8625 09:31:08.922360
8626 09:31:08.922947 Set Vref, RX VrefLevel [Byte0]: 40
8627 09:31:08.925676 [Byte1]: 40
8628 09:31:08.929801
8629 09:31:08.930353 Set Vref, RX VrefLevel [Byte0]: 41
8630 09:31:08.933516 [Byte1]: 41
8631 09:31:08.937584
8632 09:31:08.938111 Set Vref, RX VrefLevel [Byte0]: 42
8633 09:31:08.940913 [Byte1]: 42
8634 09:31:08.945348
8635 09:31:08.945880 Set Vref, RX VrefLevel [Byte0]: 43
8636 09:31:08.948112 [Byte1]: 43
8637 09:31:08.952631
8638 09:31:08.953207 Set Vref, RX VrefLevel [Byte0]: 44
8639 09:31:08.955764 [Byte1]: 44
8640 09:31:08.960235
8641 09:31:08.960769 Set Vref, RX VrefLevel [Byte0]: 45
8642 09:31:08.963390 [Byte1]: 45
8643 09:31:08.967716
8644 09:31:08.968145 Set Vref, RX VrefLevel [Byte0]: 46
8645 09:31:08.971096 [Byte1]: 46
8646 09:31:08.975022
8647 09:31:08.975555 Set Vref, RX VrefLevel [Byte0]: 47
8648 09:31:08.978585 [Byte1]: 47
8649 09:31:08.982792
8650 09:31:08.983313 Set Vref, RX VrefLevel [Byte0]: 48
8651 09:31:08.986466 [Byte1]: 48
8652 09:31:08.990537
8653 09:31:08.991218 Set Vref, RX VrefLevel [Byte0]: 49
8654 09:31:08.993647 [Byte1]: 49
8655 09:31:08.997692
8656 09:31:08.998153 Set Vref, RX VrefLevel [Byte0]: 50
8657 09:31:09.001552 [Byte1]: 50
8658 09:31:09.005594
8659 09:31:09.006238 Set Vref, RX VrefLevel [Byte0]: 51
8660 09:31:09.008902 [Byte1]: 51
8661 09:31:09.012818
8662 09:31:09.013410 Set Vref, RX VrefLevel [Byte0]: 52
8663 09:31:09.016246 [Byte1]: 52
8664 09:31:09.020888
8665 09:31:09.021564 Set Vref, RX VrefLevel [Byte0]: 53
8666 09:31:09.023778 [Byte1]: 53
8667 09:31:09.028155
8668 09:31:09.028656 Set Vref, RX VrefLevel [Byte0]: 54
8669 09:31:09.031208 [Byte1]: 54
8670 09:31:09.035841
8671 09:31:09.036310 Set Vref, RX VrefLevel [Byte0]: 55
8672 09:31:09.038834 [Byte1]: 55
8673 09:31:09.043710
8674 09:31:09.044230 Set Vref, RX VrefLevel [Byte0]: 56
8675 09:31:09.046600 [Byte1]: 56
8676 09:31:09.051409
8677 09:31:09.051949 Set Vref, RX VrefLevel [Byte0]: 57
8678 09:31:09.054011 [Byte1]: 57
8679 09:31:09.058602
8680 09:31:09.059165 Set Vref, RX VrefLevel [Byte0]: 58
8681 09:31:09.061875 [Byte1]: 58
8682 09:31:09.066264
8683 09:31:09.066822 Set Vref, RX VrefLevel [Byte0]: 59
8684 09:31:09.069666 [Byte1]: 59
8685 09:31:09.073757
8686 09:31:09.074326 Set Vref, RX VrefLevel [Byte0]: 60
8687 09:31:09.077136 [Byte1]: 60
8688 09:31:09.081635
8689 09:31:09.082197 Set Vref, RX VrefLevel [Byte0]: 61
8690 09:31:09.084804 [Byte1]: 61
8691 09:31:09.089239
8692 09:31:09.089870 Set Vref, RX VrefLevel [Byte0]: 62
8693 09:31:09.092134 [Byte1]: 62
8694 09:31:09.096474
8695 09:31:09.097088 Set Vref, RX VrefLevel [Byte0]: 63
8696 09:31:09.099564 [Byte1]: 63
8697 09:31:09.104415
8698 09:31:09.105088 Set Vref, RX VrefLevel [Byte0]: 64
8699 09:31:09.107025 [Byte1]: 64
8700 09:31:09.111931
8701 09:31:09.112502 Set Vref, RX VrefLevel [Byte0]: 65
8702 09:31:09.114583 [Byte1]: 65
8703 09:31:09.119391
8704 09:31:09.120010 Set Vref, RX VrefLevel [Byte0]: 66
8705 09:31:09.122417 [Byte1]: 66
8706 09:31:09.126528
8707 09:31:09.126988 Set Vref, RX VrefLevel [Byte0]: 67
8708 09:31:09.129960 [Byte1]: 67
8709 09:31:09.134301
8710 09:31:09.134894 Set Vref, RX VrefLevel [Byte0]: 68
8711 09:31:09.137650 [Byte1]: 68
8712 09:31:09.141626
8713 09:31:09.142063 Set Vref, RX VrefLevel [Byte0]: 69
8714 09:31:09.148564 [Byte1]: 69
8715 09:31:09.149140
8716 09:31:09.151377 Set Vref, RX VrefLevel [Byte0]: 70
8717 09:31:09.155262 [Byte1]: 70
8718 09:31:09.155811
8719 09:31:09.157974 Set Vref, RX VrefLevel [Byte0]: 71
8720 09:31:09.161383 [Byte1]: 71
8721 09:31:09.161846
8722 09:31:09.164779 Set Vref, RX VrefLevel [Byte0]: 72
8723 09:31:09.167969 [Byte1]: 72
8724 09:31:09.172061
8725 09:31:09.172592 Set Vref, RX VrefLevel [Byte0]: 73
8726 09:31:09.175727 [Byte1]: 73
8727 09:31:09.179807
8728 09:31:09.180279 Final RX Vref Byte 0 = 57 to rank0
8729 09:31:09.182831 Final RX Vref Byte 1 = 61 to rank0
8730 09:31:09.186647 Final RX Vref Byte 0 = 57 to rank1
8731 09:31:09.189861 Final RX Vref Byte 1 = 61 to rank1==
8732 09:31:09.193329 Dram Type= 6, Freq= 0, CH_1, rank 0
8733 09:31:09.199889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 09:31:09.200483 ==
8735 09:31:09.200861 DQS Delay:
8736 09:31:09.201336 DQS0 = 0, DQS1 = 0
8737 09:31:09.203163 DQM Delay:
8738 09:31:09.203626 DQM0 = 134, DQM1 = 129
8739 09:31:09.206184 DQ Delay:
8740 09:31:09.209621 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8741 09:31:09.213027 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8742 09:31:09.216691 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8743 09:31:09.219318 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8744 09:31:09.219747
8745 09:31:09.220087
8746 09:31:09.220403
8747 09:31:09.223186 [DramC_TX_OE_Calibration] TA2
8748 09:31:09.226401 Original DQ_B0 (3 6) =30, OEN = 27
8749 09:31:09.229403 Original DQ_B1 (3 6) =30, OEN = 27
8750 09:31:09.232871 24, 0x0, End_B0=24 End_B1=24
8751 09:31:09.233343 25, 0x0, End_B0=25 End_B1=25
8752 09:31:09.236375 26, 0x0, End_B0=26 End_B1=26
8753 09:31:09.239964 27, 0x0, End_B0=27 End_B1=27
8754 09:31:09.243330 28, 0x0, End_B0=28 End_B1=28
8755 09:31:09.243866 29, 0x0, End_B0=29 End_B1=29
8756 09:31:09.246456 30, 0x0, End_B0=30 End_B1=30
8757 09:31:09.249586 31, 0x4141, End_B0=30 End_B1=30
8758 09:31:09.252850 Byte0 end_step=30 best_step=27
8759 09:31:09.256421 Byte1 end_step=30 best_step=27
8760 09:31:09.259527 Byte0 TX OE(2T, 0.5T) = (3, 3)
8761 09:31:09.259953 Byte1 TX OE(2T, 0.5T) = (3, 3)
8762 09:31:09.262812
8763 09:31:09.263371
8764 09:31:09.269308 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8765 09:31:09.272619 CH1 RK0: MR19=303, MR18=1624
8766 09:31:09.279336 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8767 09:31:09.279847
8768 09:31:09.282974 ----->DramcWriteLeveling(PI) begin...
8769 09:31:09.283425 ==
8770 09:31:09.285784 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 09:31:09.289765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 09:31:09.290330 ==
8773 09:31:09.292861 Write leveling (Byte 0): 23 => 23
8774 09:31:09.296398 Write leveling (Byte 1): 28 => 28
8775 09:31:09.299550 DramcWriteLeveling(PI) end<-----
8776 09:31:09.300159
8777 09:31:09.300533 ==
8778 09:31:09.302811 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 09:31:09.306371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 09:31:09.306940 ==
8781 09:31:09.309272 [Gating] SW mode calibration
8782 09:31:09.316621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8783 09:31:09.323148 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8784 09:31:09.325788 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 09:31:09.329522 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 09:31:09.336438 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8787 09:31:09.339416 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8788 09:31:09.342399 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 09:31:09.349312 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 09:31:09.352632 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 09:31:09.356138 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 09:31:09.362776 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 09:31:09.366150 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 09:31:09.369393 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8795 09:31:09.376099 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8796 09:31:09.378694 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 09:31:09.382664 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 09:31:09.389103 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 09:31:09.392727 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 09:31:09.395570 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 09:31:09.402480 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 09:31:09.405592 1 6 8 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8803 09:31:09.408981 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 09:31:09.415652 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 09:31:09.418800 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 09:31:09.421932 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 09:31:09.429002 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 09:31:09.432247 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 09:31:09.435229 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 09:31:09.441464 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8811 09:31:09.445212 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 09:31:09.448494 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 09:31:09.454799 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 09:31:09.458371 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 09:31:09.461554 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 09:31:09.468458 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 09:31:09.471724 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 09:31:09.475010 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 09:31:09.481541 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 09:31:09.485167 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 09:31:09.488396 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 09:31:09.492080 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 09:31:09.497937 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 09:31:09.501822 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 09:31:09.504967 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 09:31:09.511671 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8827 09:31:09.514736 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8828 09:31:09.518296 Total UI for P1: 0, mck2ui 16
8829 09:31:09.521908 best dqsien dly found for B1: ( 1, 9, 8)
8830 09:31:09.524772 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 09:31:09.528283 Total UI for P1: 0, mck2ui 16
8832 09:31:09.531851 best dqsien dly found for B0: ( 1, 9, 10)
8833 09:31:09.534963 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8834 09:31:09.538046 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8835 09:31:09.538461
8836 09:31:09.544372 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8837 09:31:09.547853 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8838 09:31:09.551678 [Gating] SW calibration Done
8839 09:31:09.552339 ==
8840 09:31:09.554835 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 09:31:09.558358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 09:31:09.558887 ==
8843 09:31:09.559224 RX Vref Scan: 0
8844 09:31:09.559533
8845 09:31:09.561212 RX Vref 0 -> 0, step: 1
8846 09:31:09.561627
8847 09:31:09.564458 RX Delay 0 -> 252, step: 8
8848 09:31:09.567942 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8849 09:31:09.571697 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8850 09:31:09.577697 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8851 09:31:09.580862 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8852 09:31:09.584590 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8853 09:31:09.587826 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8854 09:31:09.591131 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8855 09:31:09.597794 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8856 09:31:09.600919 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8857 09:31:09.604516 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8858 09:31:09.607230 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8859 09:31:09.610595 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8860 09:31:09.617395 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8861 09:31:09.620417 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8862 09:31:09.624218 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8863 09:31:09.627331 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8864 09:31:09.627845 ==
8865 09:31:09.630821 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 09:31:09.637116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 09:31:09.637546 ==
8868 09:31:09.637884 DQS Delay:
8869 09:31:09.640611 DQS0 = 0, DQS1 = 0
8870 09:31:09.641066 DQM Delay:
8871 09:31:09.643730 DQM0 = 136, DQM1 = 132
8872 09:31:09.644299 DQ Delay:
8873 09:31:09.646952 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8874 09:31:09.650430 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8875 09:31:09.653505 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8876 09:31:09.656826 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8877 09:31:09.657270
8878 09:31:09.657605
8879 09:31:09.657910 ==
8880 09:31:09.660325 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 09:31:09.667201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 09:31:09.667737 ==
8883 09:31:09.668073
8884 09:31:09.668380
8885 09:31:09.668675 TX Vref Scan disable
8886 09:31:09.670740 == TX Byte 0 ==
8887 09:31:09.673373 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8888 09:31:09.679938 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8889 09:31:09.680473 == TX Byte 1 ==
8890 09:31:09.683333 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8891 09:31:09.689770 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8892 09:31:09.690281 ==
8893 09:31:09.693200 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 09:31:09.696441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 09:31:09.696865 ==
8896 09:31:09.710350
8897 09:31:09.713280 TX Vref early break, caculate TX vref
8898 09:31:09.716901 TX Vref=16, minBit 9, minWin=22, winSum=382
8899 09:31:09.720310 TX Vref=18, minBit 9, minWin=22, winSum=387
8900 09:31:09.723307 TX Vref=20, minBit 11, minWin=23, winSum=397
8901 09:31:09.726808 TX Vref=22, minBit 9, minWin=24, winSum=407
8902 09:31:09.730809 TX Vref=24, minBit 9, minWin=24, winSum=414
8903 09:31:09.737029 TX Vref=26, minBit 10, minWin=24, winSum=418
8904 09:31:09.740451 TX Vref=28, minBit 9, minWin=25, winSum=417
8905 09:31:09.743395 TX Vref=30, minBit 5, minWin=25, winSum=412
8906 09:31:09.746945 TX Vref=32, minBit 9, minWin=24, winSum=407
8907 09:31:09.750375 TX Vref=34, minBit 9, minWin=24, winSum=401
8908 09:31:09.753273 TX Vref=36, minBit 8, minWin=23, winSum=393
8909 09:31:09.759988 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8910 09:31:09.760513
8911 09:31:09.763610 Final TX Range 0 Vref 28
8912 09:31:09.764196
8913 09:31:09.764531 ==
8914 09:31:09.766790 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 09:31:09.770179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 09:31:09.770602 ==
8917 09:31:09.770955
8918 09:31:09.773546
8919 09:31:09.774064 TX Vref Scan disable
8920 09:31:09.779946 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8921 09:31:09.780369 == TX Byte 0 ==
8922 09:31:09.783090 u2DelayCellOfst[0]=16 cells (5 PI)
8923 09:31:09.786694 u2DelayCellOfst[1]=10 cells (3 PI)
8924 09:31:09.789964 u2DelayCellOfst[2]=0 cells (0 PI)
8925 09:31:09.793019 u2DelayCellOfst[3]=6 cells (2 PI)
8926 09:31:09.796727 u2DelayCellOfst[4]=6 cells (2 PI)
8927 09:31:09.800067 u2DelayCellOfst[5]=16 cells (5 PI)
8928 09:31:09.803575 u2DelayCellOfst[6]=16 cells (5 PI)
8929 09:31:09.806862 u2DelayCellOfst[7]=3 cells (1 PI)
8930 09:31:09.809790 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8931 09:31:09.813275 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8932 09:31:09.816568 == TX Byte 1 ==
8933 09:31:09.820088 u2DelayCellOfst[8]=0 cells (0 PI)
8934 09:31:09.822857 u2DelayCellOfst[9]=3 cells (1 PI)
8935 09:31:09.823278 u2DelayCellOfst[10]=10 cells (3 PI)
8936 09:31:09.826119 u2DelayCellOfst[11]=6 cells (2 PI)
8937 09:31:09.829656 u2DelayCellOfst[12]=13 cells (4 PI)
8938 09:31:09.833151 u2DelayCellOfst[13]=16 cells (5 PI)
8939 09:31:09.836061 u2DelayCellOfst[14]=20 cells (6 PI)
8940 09:31:09.839992 u2DelayCellOfst[15]=16 cells (5 PI)
8941 09:31:09.846604 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8942 09:31:09.849686 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8943 09:31:09.850110 DramC Write-DBI on
8944 09:31:09.850443 ==
8945 09:31:09.853236 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 09:31:09.859527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 09:31:09.860084 ==
8948 09:31:09.860431
8949 09:31:09.860741
8950 09:31:09.861113 TX Vref Scan disable
8951 09:31:09.863801 == TX Byte 0 ==
8952 09:31:09.866659 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8953 09:31:09.870109 == TX Byte 1 ==
8954 09:31:09.873386 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8955 09:31:09.877037 DramC Write-DBI off
8956 09:31:09.877574
8957 09:31:09.877913 [DATLAT]
8958 09:31:09.878252 Freq=1600, CH1 RK1
8959 09:31:09.878562
8960 09:31:09.880023 DATLAT Default: 0xf
8961 09:31:09.880460 0, 0xFFFF, sum = 0
8962 09:31:09.883765 1, 0xFFFF, sum = 0
8963 09:31:09.886850 2, 0xFFFF, sum = 0
8964 09:31:09.887408 3, 0xFFFF, sum = 0
8965 09:31:09.890455 4, 0xFFFF, sum = 0
8966 09:31:09.891009 5, 0xFFFF, sum = 0
8967 09:31:09.893341 6, 0xFFFF, sum = 0
8968 09:31:09.893769 7, 0xFFFF, sum = 0
8969 09:31:09.896975 8, 0xFFFF, sum = 0
8970 09:31:09.897505 9, 0xFFFF, sum = 0
8971 09:31:09.900275 10, 0xFFFF, sum = 0
8972 09:31:09.900702 11, 0xFFFF, sum = 0
8973 09:31:09.903802 12, 0xFFFF, sum = 0
8974 09:31:09.904349 13, 0xFFFF, sum = 0
8975 09:31:09.907434 14, 0x0, sum = 1
8976 09:31:09.907964 15, 0x0, sum = 2
8977 09:31:09.910448 16, 0x0, sum = 3
8978 09:31:09.910981 17, 0x0, sum = 4
8979 09:31:09.913847 best_step = 15
8980 09:31:09.914377
8981 09:31:09.914716 ==
8982 09:31:09.916735 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 09:31:09.920670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 09:31:09.921259 ==
8985 09:31:09.921607 RX Vref Scan: 0
8986 09:31:09.923570
8987 09:31:09.923991 RX Vref 0 -> 0, step: 1
8988 09:31:09.924325
8989 09:31:09.927041 RX Delay 19 -> 252, step: 4
8990 09:31:09.930054 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8991 09:31:09.936619 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8992 09:31:09.940110 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8993 09:31:09.943302 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8994 09:31:09.947046 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8995 09:31:09.949920 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8996 09:31:09.953457 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8997 09:31:09.960188 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8998 09:31:09.963609 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8999 09:31:09.967028 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9000 09:31:09.969770 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9001 09:31:09.973179 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9002 09:31:09.979996 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9003 09:31:09.983713 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9004 09:31:09.986934 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9005 09:31:09.989768 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9006 09:31:09.990188 ==
9007 09:31:09.993750 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 09:31:10.000100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 09:31:10.000662 ==
9010 09:31:10.001098 DQS Delay:
9011 09:31:10.003673 DQS0 = 0, DQS1 = 0
9012 09:31:10.004133 DQM Delay:
9013 09:31:10.004499 DQM0 = 134, DQM1 = 130
9014 09:31:10.006390 DQ Delay:
9015 09:31:10.009730 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9016 09:31:10.013423 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
9017 09:31:10.016400 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =124
9018 09:31:10.019414 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9019 09:31:10.020012
9020 09:31:10.020477
9021 09:31:10.020922
9022 09:31:10.023227 [DramC_TX_OE_Calibration] TA2
9023 09:31:10.026254 Original DQ_B0 (3 6) =30, OEN = 27
9024 09:31:10.029897 Original DQ_B1 (3 6) =30, OEN = 27
9025 09:31:10.033363 24, 0x0, End_B0=24 End_B1=24
9026 09:31:10.033789 25, 0x0, End_B0=25 End_B1=25
9027 09:31:10.036240 26, 0x0, End_B0=26 End_B1=26
9028 09:31:10.039874 27, 0x0, End_B0=27 End_B1=27
9029 09:31:10.043124 28, 0x0, End_B0=28 End_B1=28
9030 09:31:10.046212 29, 0x0, End_B0=29 End_B1=29
9031 09:31:10.046640 30, 0x0, End_B0=30 End_B1=30
9032 09:31:10.049753 31, 0x4141, End_B0=30 End_B1=30
9033 09:31:10.052992 Byte0 end_step=30 best_step=27
9034 09:31:10.056275 Byte1 end_step=30 best_step=27
9035 09:31:10.059563 Byte0 TX OE(2T, 0.5T) = (3, 3)
9036 09:31:10.062656 Byte1 TX OE(2T, 0.5T) = (3, 3)
9037 09:31:10.063091
9038 09:31:10.063435
9039 09:31:10.069334 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9040 09:31:10.072824 CH1 RK1: MR19=303, MR18=1D08
9041 09:31:10.079167 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9042 09:31:10.082452 [RxdqsGatingPostProcess] freq 1600
9043 09:31:10.085874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9044 09:31:10.089376 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 09:31:10.092525 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 09:31:10.095955 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 09:31:10.099122 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 09:31:10.102652 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 09:31:10.105711 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 09:31:10.109766 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 09:31:10.112653 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 09:31:10.116141 Pre-setting of DQS Precalculation
9053 09:31:10.119318 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9054 09:31:10.125922 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9055 09:31:10.135815 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9056 09:31:10.136392
9057 09:31:10.136854
9058 09:31:10.137454 [Calibration Summary] 3200 Mbps
9059 09:31:10.139289 CH 0, Rank 0
9060 09:31:10.142622 SW Impedance : PASS
9061 09:31:10.143045 DUTY Scan : NO K
9062 09:31:10.146019 ZQ Calibration : PASS
9063 09:31:10.146435 Jitter Meter : NO K
9064 09:31:10.149188 CBT Training : PASS
9065 09:31:10.152249 Write leveling : PASS
9066 09:31:10.152696 RX DQS gating : PASS
9067 09:31:10.155780 RX DQ/DQS(RDDQC) : PASS
9068 09:31:10.159415 TX DQ/DQS : PASS
9069 09:31:10.159838 RX DATLAT : PASS
9070 09:31:10.162493 RX DQ/DQS(Engine): PASS
9071 09:31:10.165550 TX OE : PASS
9072 09:31:10.165966 All Pass.
9073 09:31:10.166297
9074 09:31:10.166604 CH 0, Rank 1
9075 09:31:10.168925 SW Impedance : PASS
9076 09:31:10.172535 DUTY Scan : NO K
9077 09:31:10.172987 ZQ Calibration : PASS
9078 09:31:10.175497 Jitter Meter : NO K
9079 09:31:10.178974 CBT Training : PASS
9080 09:31:10.179391 Write leveling : PASS
9081 09:31:10.182445 RX DQS gating : PASS
9082 09:31:10.185692 RX DQ/DQS(RDDQC) : PASS
9083 09:31:10.186136 TX DQ/DQS : PASS
9084 09:31:10.189029 RX DATLAT : PASS
9085 09:31:10.189446 RX DQ/DQS(Engine): PASS
9086 09:31:10.192066 TX OE : PASS
9087 09:31:10.192484 All Pass.
9088 09:31:10.192814
9089 09:31:10.195715 CH 1, Rank 0
9090 09:31:10.196129 SW Impedance : PASS
9091 09:31:10.198861 DUTY Scan : NO K
9092 09:31:10.202420 ZQ Calibration : PASS
9093 09:31:10.202836 Jitter Meter : NO K
9094 09:31:10.205296 CBT Training : PASS
9095 09:31:10.208749 Write leveling : PASS
9096 09:31:10.209196 RX DQS gating : PASS
9097 09:31:10.212320 RX DQ/DQS(RDDQC) : PASS
9098 09:31:10.215310 TX DQ/DQS : PASS
9099 09:31:10.215728 RX DATLAT : PASS
9100 09:31:10.218700 RX DQ/DQS(Engine): PASS
9101 09:31:10.222233 TX OE : PASS
9102 09:31:10.222649 All Pass.
9103 09:31:10.222979
9104 09:31:10.223283 CH 1, Rank 1
9105 09:31:10.225295 SW Impedance : PASS
9106 09:31:10.228844 DUTY Scan : NO K
9107 09:31:10.229279 ZQ Calibration : PASS
9108 09:31:10.232024 Jitter Meter : NO K
9109 09:31:10.235622 CBT Training : PASS
9110 09:31:10.235766 Write leveling : PASS
9111 09:31:10.238357 RX DQS gating : PASS
9112 09:31:10.241859 RX DQ/DQS(RDDQC) : PASS
9113 09:31:10.241941 TX DQ/DQS : PASS
9114 09:31:10.244786 RX DATLAT : PASS
9115 09:31:10.244867 RX DQ/DQS(Engine): PASS
9116 09:31:10.248174 TX OE : PASS
9117 09:31:10.248256 All Pass.
9118 09:31:10.248320
9119 09:31:10.251698 DramC Write-DBI on
9120 09:31:10.254790 PER_BANK_REFRESH: Hybrid Mode
9121 09:31:10.254872 TX_TRACKING: ON
9122 09:31:10.265061 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9123 09:31:10.271493 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9124 09:31:10.278211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9125 09:31:10.285052 [FAST_K] Save calibration result to emmc
9126 09:31:10.285135 sync common calibartion params.
9127 09:31:10.288085 sync cbt_mode0:1, 1:1
9128 09:31:10.291607 dram_init: ddr_geometry: 2
9129 09:31:10.291688 dram_init: ddr_geometry: 2
9130 09:31:10.294918 dram_init: ddr_geometry: 2
9131 09:31:10.298472 0:dram_rank_size:100000000
9132 09:31:10.301627 1:dram_rank_size:100000000
9133 09:31:10.304721 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9134 09:31:10.308426 DFS_SHUFFLE_HW_MODE: ON
9135 09:31:10.311402 dramc_set_vcore_voltage set vcore to 725000
9136 09:31:10.314779 Read voltage for 1600, 0
9137 09:31:10.314861 Vio18 = 0
9138 09:31:10.318341 Vcore = 725000
9139 09:31:10.318423 Vdram = 0
9140 09:31:10.318488 Vddq = 0
9141 09:31:10.318547 Vmddr = 0
9142 09:31:10.321695 switch to 3200 Mbps bootup
9143 09:31:10.324851 [DramcRunTimeConfig]
9144 09:31:10.324940 PHYPLL
9145 09:31:10.325006 DPM_CONTROL_AFTERK: ON
9146 09:31:10.328005 PER_BANK_REFRESH: ON
9147 09:31:10.331727 REFRESH_OVERHEAD_REDUCTION: ON
9148 09:31:10.331810 CMD_PICG_NEW_MODE: OFF
9149 09:31:10.334607 XRTWTW_NEW_MODE: ON
9150 09:31:10.338119 XRTRTR_NEW_MODE: ON
9151 09:31:10.338201 TX_TRACKING: ON
9152 09:31:10.341682 RDSEL_TRACKING: OFF
9153 09:31:10.341763 DQS Precalculation for DVFS: ON
9154 09:31:10.344632 RX_TRACKING: OFF
9155 09:31:10.344713 HW_GATING DBG: ON
9156 09:31:10.348210 ZQCS_ENABLE_LP4: ON
9157 09:31:10.348291 RX_PICG_NEW_MODE: ON
9158 09:31:10.351576 TX_PICG_NEW_MODE: ON
9159 09:31:10.355171 ENABLE_RX_DCM_DPHY: ON
9160 09:31:10.358212 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9161 09:31:10.358293 DUMMY_READ_FOR_TRACKING: OFF
9162 09:31:10.361382 !!! SPM_CONTROL_AFTERK: OFF
9163 09:31:10.364887 !!! SPM could not control APHY
9164 09:31:10.368325 IMPEDANCE_TRACKING: ON
9165 09:31:10.368406 TEMP_SENSOR: ON
9166 09:31:10.371354 HW_SAVE_FOR_SR: OFF
9167 09:31:10.371436 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9168 09:31:10.378266 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9169 09:31:10.378348 Read ODT Tracking: ON
9170 09:31:10.381270 Refresh Rate DeBounce: ON
9171 09:31:10.384640 DFS_NO_QUEUE_FLUSH: ON
9172 09:31:10.384721 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9173 09:31:10.388084 ENABLE_DFS_RUNTIME_MRW: OFF
9174 09:31:10.391495 DDR_RESERVE_NEW_MODE: ON
9175 09:31:10.394714 MR_CBT_SWITCH_FREQ: ON
9176 09:31:10.394796 =========================
9177 09:31:10.414414 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9178 09:31:10.417631 dram_init: ddr_geometry: 2
9179 09:31:10.436015 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9180 09:31:10.439084 dram_init: dram init end (result: 0)
9181 09:31:10.445664 DRAM-K: Full calibration passed in 24491 msecs
9182 09:31:10.448913 MRC: failed to locate region type 0.
9183 09:31:10.449018 DRAM rank0 size:0x100000000,
9184 09:31:10.452400 DRAM rank1 size=0x100000000
9185 09:31:10.462377 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9186 09:31:10.468556 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9187 09:31:10.475499 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9188 09:31:10.481983 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9189 09:31:10.485398 DRAM rank0 size:0x100000000,
9190 09:31:10.488864 DRAM rank1 size=0x100000000
9191 09:31:10.488983 CBMEM:
9192 09:31:10.491757 IMD: root @ 0xfffff000 254 entries.
9193 09:31:10.495548 IMD: root @ 0xffffec00 62 entries.
9194 09:31:10.498488 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9195 09:31:10.505410 WARNING: RO_VPD is uninitialized or empty.
9196 09:31:10.508501 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9197 09:31:10.515625 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9198 09:31:10.528351 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9199 09:31:10.539961 BS: romstage times (exec / console): total (unknown) / 23992 ms
9200 09:31:10.540048
9201 09:31:10.540117
9202 09:31:10.549881 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9203 09:31:10.553409 ARM64: Exception handlers installed.
9204 09:31:10.556847 ARM64: Testing exception
9205 09:31:10.559808 ARM64: Done test exception
9206 09:31:10.559885 Enumerating buses...
9207 09:31:10.563318 Show all devs... Before device enumeration.
9208 09:31:10.566916 Root Device: enabled 1
9209 09:31:10.569997 CPU_CLUSTER: 0: enabled 1
9210 09:31:10.570073 CPU: 00: enabled 1
9211 09:31:10.573049 Compare with tree...
9212 09:31:10.573128 Root Device: enabled 1
9213 09:31:10.576603 CPU_CLUSTER: 0: enabled 1
9214 09:31:10.580138 CPU: 00: enabled 1
9215 09:31:10.580212 Root Device scanning...
9216 09:31:10.583193 scan_static_bus for Root Device
9217 09:31:10.586649 CPU_CLUSTER: 0 enabled
9218 09:31:10.590143 scan_static_bus for Root Device done
9219 09:31:10.593183 scan_bus: bus Root Device finished in 8 msecs
9220 09:31:10.593257 done
9221 09:31:10.599844 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9222 09:31:10.602946 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9223 09:31:10.609901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9224 09:31:10.613435 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9225 09:31:10.616335 Allocating resources...
9226 09:31:10.619915 Reading resources...
9227 09:31:10.622861 Root Device read_resources bus 0 link: 0
9228 09:31:10.622942 DRAM rank0 size:0x100000000,
9229 09:31:10.626238 DRAM rank1 size=0x100000000
9230 09:31:10.629830 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9231 09:31:10.632850 CPU: 00 missing read_resources
9232 09:31:10.636364 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9233 09:31:10.642909 Root Device read_resources bus 0 link: 0 done
9234 09:31:10.642992 Done reading resources.
9235 09:31:10.649828 Show resources in subtree (Root Device)...After reading.
9236 09:31:10.653193 Root Device child on link 0 CPU_CLUSTER: 0
9237 09:31:10.656222 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 09:31:10.666299 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 09:31:10.666381 CPU: 00
9240 09:31:10.669569 Root Device assign_resources, bus 0 link: 0
9241 09:31:10.672734 CPU_CLUSTER: 0 missing set_resources
9242 09:31:10.676495 Root Device assign_resources, bus 0 link: 0 done
9243 09:31:10.679847 Done setting resources.
9244 09:31:10.686308 Show resources in subtree (Root Device)...After assigning values.
9245 09:31:10.689298 Root Device child on link 0 CPU_CLUSTER: 0
9246 09:31:10.692876 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 09:31:10.702695 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 09:31:10.702778 CPU: 00
9249 09:31:10.706103 Done allocating resources.
9250 09:31:10.709578 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9251 09:31:10.712577 Enabling resources...
9252 09:31:10.712658 done.
9253 09:31:10.719371 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9254 09:31:10.719454 Initializing devices...
9255 09:31:10.722848 Root Device init
9256 09:31:10.722928 init hardware done!
9257 09:31:10.725910 0x00000018: ctrlr->caps
9258 09:31:10.729380 52.000 MHz: ctrlr->f_max
9259 09:31:10.729489 0.400 MHz: ctrlr->f_min
9260 09:31:10.732478 0x40ff8080: ctrlr->voltages
9261 09:31:10.732562 sclk: 390625
9262 09:31:10.735918 Bus Width = 1
9263 09:31:10.736012 sclk: 390625
9264 09:31:10.739413 Bus Width = 1
9265 09:31:10.739495 Early init status = 3
9266 09:31:10.746078 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9267 09:31:10.749228 in-header: 03 fc 00 00 01 00 00 00
9268 09:31:10.749313 in-data: 00
9269 09:31:10.755810 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9270 09:31:10.759373 in-header: 03 fd 00 00 00 00 00 00
9271 09:31:10.762430 in-data:
9272 09:31:10.765428 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9273 09:31:10.768834 in-header: 03 fc 00 00 01 00 00 00
9274 09:31:10.772403 in-data: 00
9275 09:31:10.775647 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9276 09:31:10.780820 in-header: 03 fd 00 00 00 00 00 00
9277 09:31:10.783649 in-data:
9278 09:31:10.787220 [SSUSB] Setting up USB HOST controller...
9279 09:31:10.790752 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9280 09:31:10.793597 [SSUSB] phy power-on done.
9281 09:31:10.797158 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9282 09:31:10.803544 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9283 09:31:10.806902 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9284 09:31:10.813666 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9285 09:31:10.820722 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9286 09:31:10.827296 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9287 09:31:10.833806 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9288 09:31:10.840468 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9289 09:31:10.843875 SPM: binary array size = 0x9dc
9290 09:31:10.846935 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9291 09:31:10.853599 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9292 09:31:10.860335 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9293 09:31:10.863931 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9294 09:31:10.867039 configure_display: Starting display init
9295 09:31:10.903801 anx7625_power_on_init: Init interface.
9296 09:31:10.907214 anx7625_disable_pd_protocol: Disabled PD feature.
9297 09:31:10.910264 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9298 09:31:10.938076 anx7625_start_dp_work: Secure OCM version=00
9299 09:31:10.941556 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9300 09:31:10.956219 sp_tx_get_edid_block: EDID Block = 1
9301 09:31:11.059159 Extracted contents:
9302 09:31:11.062228 header: 00 ff ff ff ff ff ff 00
9303 09:31:11.065701 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9304 09:31:11.068848 version: 01 04
9305 09:31:11.072432 basic params: 95 1f 11 78 0a
9306 09:31:11.075935 chroma info: 76 90 94 55 54 90 27 21 50 54
9307 09:31:11.078879 established: 00 00 00
9308 09:31:11.082414 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9309 09:31:11.088772 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9310 09:31:11.095251 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9311 09:31:11.102309 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9312 09:31:11.108810 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9313 09:31:11.112370 extensions: 00
9314 09:31:11.112453 checksum: fb
9315 09:31:11.112519
9316 09:31:11.115819 Manufacturer: IVO Model 57d Serial Number 0
9317 09:31:11.118812 Made week 0 of 2020
9318 09:31:11.118922 EDID version: 1.4
9319 09:31:11.122244 Digital display
9320 09:31:11.125599 6 bits per primary color channel
9321 09:31:11.125683 DisplayPort interface
9322 09:31:11.128666 Maximum image size: 31 cm x 17 cm
9323 09:31:11.131824 Gamma: 220%
9324 09:31:11.131907 Check DPMS levels
9325 09:31:11.135466 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9326 09:31:11.138600 First detailed timing is preferred timing
9327 09:31:11.142080 Established timings supported:
9328 09:31:11.145582 Standard timings supported:
9329 09:31:11.145665 Detailed timings
9330 09:31:11.151955 Hex of detail: 383680a07038204018303c0035ae10000019
9331 09:31:11.155486 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9332 09:31:11.162102 0780 0798 07c8 0820 hborder 0
9333 09:31:11.165500 0438 043b 0447 0458 vborder 0
9334 09:31:11.165582 -hsync -vsync
9335 09:31:11.168648 Did detailed timing
9336 09:31:11.171759 Hex of detail: 000000000000000000000000000000000000
9337 09:31:11.175364 Manufacturer-specified data, tag 0
9338 09:31:11.181941 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9339 09:31:11.182022 ASCII string: InfoVision
9340 09:31:11.188477 Hex of detail: 000000fe00523134304e574635205248200a
9341 09:31:11.191865 ASCII string: R140NWF5 RH
9342 09:31:11.191945 Checksum
9343 09:31:11.192009 Checksum: 0xfb (valid)
9344 09:31:11.198515 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9345 09:31:11.201602 DSI data_rate: 832800000 bps
9346 09:31:11.205015 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9347 09:31:11.211781 anx7625_parse_edid: pixelclock(138800).
9348 09:31:11.214806 hactive(1920), hsync(48), hfp(24), hbp(88)
9349 09:31:11.218334 vactive(1080), vsync(12), vfp(3), vbp(17)
9350 09:31:11.221410 anx7625_dsi_config: config dsi.
9351 09:31:11.228294 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9352 09:31:11.240845 anx7625_dsi_config: success to config DSI
9353 09:31:11.244430 anx7625_dp_start: MIPI phy setup OK.
9354 09:31:11.247470 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9355 09:31:11.250893 mtk_ddp_mode_set invalid vrefresh 60
9356 09:31:11.254403 main_disp_path_setup
9357 09:31:11.254501 ovl_layer_smi_id_en
9358 09:31:11.257331 ovl_layer_smi_id_en
9359 09:31:11.257429 ccorr_config
9360 09:31:11.257517 aal_config
9361 09:31:11.260882 gamma_config
9362 09:31:11.261021 postmask_config
9363 09:31:11.264310 dither_config
9364 09:31:11.267388 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9365 09:31:11.274183 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9366 09:31:11.277279 Root Device init finished in 552 msecs
9367 09:31:11.277380 CPU_CLUSTER: 0 init
9368 09:31:11.287700 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9369 09:31:11.290847 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9370 09:31:11.294283 APU_MBOX 0x190000b0 = 0x10001
9371 09:31:11.297280 APU_MBOX 0x190001b0 = 0x10001
9372 09:31:11.300894 APU_MBOX 0x190005b0 = 0x10001
9373 09:31:11.304250 APU_MBOX 0x190006b0 = 0x10001
9374 09:31:11.307434 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9375 09:31:11.319840 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9376 09:31:11.332101 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9377 09:31:11.338581 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9378 09:31:11.350311 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9379 09:31:11.359798 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9380 09:31:11.362663 CPU_CLUSTER: 0 init finished in 81 msecs
9381 09:31:11.366302 Devices initialized
9382 09:31:11.369828 Show all devs... After init.
9383 09:31:11.369932 Root Device: enabled 1
9384 09:31:11.372816 CPU_CLUSTER: 0: enabled 1
9385 09:31:11.376397 CPU: 00: enabled 1
9386 09:31:11.379595 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9387 09:31:11.383276 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9388 09:31:11.386373 ELOG: NV offset 0x57f000 size 0x1000
9389 09:31:11.392745 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9390 09:31:11.399309 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9391 09:31:11.402508 ELOG: Event(17) added with size 13 at 2023-10-20 09:30:50 UTC
9392 09:31:11.409394 out: cmd=0x121: 03 db 21 01 00 00 00 00
9393 09:31:11.412480 in-header: 03 40 00 00 2c 00 00 00
9394 09:31:11.422350 in-data: 1f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9395 09:31:11.429346 ELOG: Event(A1) added with size 10 at 2023-10-20 09:30:50 UTC
9396 09:31:11.435826 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9397 09:31:11.442658 ELOG: Event(A0) added with size 9 at 2023-10-20 09:30:50 UTC
9398 09:31:11.445833 elog_add_boot_reason: Logged dev mode boot
9399 09:31:11.449313 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9400 09:31:11.452422 Finalize devices...
9401 09:31:11.455514 Devices finalized
9402 09:31:11.458833 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9403 09:31:11.462523 Writing coreboot table at 0xffe64000
9404 09:31:11.465502 0. 000000000010a000-0000000000113fff: RAMSTAGE
9405 09:31:11.468872 1. 0000000040000000-00000000400fffff: RAM
9406 09:31:11.475461 2. 0000000040100000-000000004032afff: RAMSTAGE
9407 09:31:11.479097 3. 000000004032b000-00000000545fffff: RAM
9408 09:31:11.482120 4. 0000000054600000-000000005465ffff: BL31
9409 09:31:11.485792 5. 0000000054660000-00000000ffe63fff: RAM
9410 09:31:11.491829 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9411 09:31:11.495269 7. 0000000100000000-000000023fffffff: RAM
9412 09:31:11.498343 Passing 5 GPIOs to payload:
9413 09:31:11.501861 NAME | PORT | POLARITY | VALUE
9414 09:31:11.505502 EC in RW | 0x000000aa | low | undefined
9415 09:31:11.511823 EC interrupt | 0x00000005 | low | undefined
9416 09:31:11.515403 TPM interrupt | 0x000000ab | high | undefined
9417 09:31:11.521824 SD card detect | 0x00000011 | high | undefined
9418 09:31:11.525276 speaker enable | 0x00000093 | high | undefined
9419 09:31:11.528625 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9420 09:31:11.531522 in-header: 03 f9 00 00 02 00 00 00
9421 09:31:11.535063 in-data: 02 00
9422 09:31:11.535171 ADC[4]: Raw value=901032 ID=7
9423 09:31:11.538429 ADC[3]: Raw value=212810 ID=1
9424 09:31:11.541884 RAM Code: 0x71
9425 09:31:11.544812 ADC[6]: Raw value=74502 ID=0
9426 09:31:11.544922 ADC[5]: Raw value=212072 ID=1
9427 09:31:11.548285 SKU Code: 0x1
9428 09:31:11.551964 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7bf8
9429 09:31:11.555108 coreboot table: 964 bytes.
9430 09:31:11.558236 IMD ROOT 0. 0xfffff000 0x00001000
9431 09:31:11.561737 IMD SMALL 1. 0xffffe000 0x00001000
9432 09:31:11.565317 RO MCACHE 2. 0xffffc000 0x00001104
9433 09:31:11.568352 CONSOLE 3. 0xfff7c000 0x00080000
9434 09:31:11.571715 FMAP 4. 0xfff7b000 0x00000452
9435 09:31:11.575140 TIME STAMP 5. 0xfff7a000 0x00000910
9436 09:31:11.578139 VBOOT WORK 6. 0xfff66000 0x00014000
9437 09:31:11.581698 RAMOOPS 7. 0xffe66000 0x00100000
9438 09:31:11.585290 COREBOOT 8. 0xffe64000 0x00002000
9439 09:31:11.585365 IMD small region:
9440 09:31:11.591903 IMD ROOT 0. 0xffffec00 0x00000400
9441 09:31:11.594885 VPD 1. 0xffffeb80 0x0000006c
9442 09:31:11.598392 MMC STATUS 2. 0xffffeb60 0x00000004
9443 09:31:11.601335 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9444 09:31:11.605003 Probing TPM: done!
9445 09:31:11.608290 Connected to device vid:did:rid of 1ae0:0028:00
9446 09:31:11.618268 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9447 09:31:11.621836 Initialized TPM device CR50 revision 0
9448 09:31:11.625400 Checking cr50 for pending updates
9449 09:31:11.629205 Reading cr50 TPM mode
9450 09:31:11.637836 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9451 09:31:11.644624 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9452 09:31:11.684859 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9453 09:31:11.688074 Checking segment from ROM address 0x40100000
9454 09:31:11.691180 Checking segment from ROM address 0x4010001c
9455 09:31:11.698396 Loading segment from ROM address 0x40100000
9456 09:31:11.698500 code (compression=0)
9457 09:31:11.704796 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9458 09:31:11.714986 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9459 09:31:11.715091 it's not compressed!
9460 09:31:11.721447 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9461 09:31:11.724906 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9462 09:31:11.745269 Loading segment from ROM address 0x4010001c
9463 09:31:11.745380 Entry Point 0x80000000
9464 09:31:11.748727 Loaded segments
9465 09:31:11.751703 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9466 09:31:11.758297 Jumping to boot code at 0x80000000(0xffe64000)
9467 09:31:11.765528 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9468 09:31:11.771571 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9469 09:31:11.779634 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9470 09:31:11.782949 Checking segment from ROM address 0x40100000
9471 09:31:11.785957 Checking segment from ROM address 0x4010001c
9472 09:31:11.792642 Loading segment from ROM address 0x40100000
9473 09:31:11.792747 code (compression=1)
9474 09:31:11.799425 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9475 09:31:11.809071 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9476 09:31:11.809174 using LZMA
9477 09:31:11.817796 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9478 09:31:11.824286 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9479 09:31:11.827891 Loading segment from ROM address 0x4010001c
9480 09:31:11.827990 Entry Point 0x54601000
9481 09:31:11.831318 Loaded segments
9482 09:31:11.834264 NOTICE: MT8192 bl31_setup
9483 09:31:11.841395 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9484 09:31:11.844740 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9485 09:31:11.848259 WARNING: region 0:
9486 09:31:11.851493 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 09:31:11.851601 WARNING: region 1:
9488 09:31:11.858253 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9489 09:31:11.861384 WARNING: region 2:
9490 09:31:11.864850 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9491 09:31:11.868473 WARNING: region 3:
9492 09:31:11.871682 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 09:31:11.875099 WARNING: region 4:
9494 09:31:11.878236 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 09:31:11.881791 WARNING: region 5:
9496 09:31:11.884778 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 09:31:11.888176 WARNING: region 6:
9498 09:31:11.891326 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 09:31:11.894883 WARNING: region 7:
9500 09:31:11.898461 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 09:31:11.904603 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9502 09:31:11.908195 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9503 09:31:11.911630 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9504 09:31:11.918108 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9505 09:31:11.921663 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9506 09:31:11.924759 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9507 09:31:11.931357 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9508 09:31:11.934995 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9509 09:31:11.941438 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9510 09:31:11.944919 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9511 09:31:11.948339 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9512 09:31:11.954820 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9513 09:31:11.958220 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9514 09:31:11.961795 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9515 09:31:11.968378 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9516 09:31:11.971408 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9517 09:31:11.974917 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9518 09:31:11.981360 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9519 09:31:11.984817 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9520 09:31:11.991907 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9521 09:31:11.994900 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9522 09:31:11.998544 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9523 09:31:12.005244 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9524 09:31:12.008270 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9525 09:31:12.014783 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9526 09:31:12.018201 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9527 09:31:12.021838 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9528 09:31:12.028368 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9529 09:31:12.031838 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9530 09:31:12.034873 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9531 09:31:12.041696 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9532 09:31:12.045257 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9533 09:31:12.048151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9534 09:31:12.055129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9535 09:31:12.058612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9536 09:31:12.062401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9537 09:31:12.065307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9538 09:31:12.071812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9539 09:31:12.075355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9540 09:31:12.078355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9541 09:31:12.081828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9542 09:31:12.088257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9543 09:31:12.091813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9544 09:31:12.095297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9545 09:31:12.098332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9546 09:31:12.105042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9547 09:31:12.108571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9548 09:31:12.112080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9549 09:31:12.118638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9550 09:31:12.122118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9551 09:31:12.125210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9552 09:31:12.132233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9553 09:31:12.135335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9554 09:31:12.142164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9555 09:31:12.145350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9556 09:31:12.148784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9557 09:31:12.155697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9558 09:31:12.159038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9559 09:31:12.165439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9560 09:31:12.168848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9561 09:31:12.175902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9562 09:31:12.179017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9563 09:31:12.182603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9564 09:31:12.189192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9565 09:31:12.192565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9566 09:31:12.199189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9567 09:31:12.202188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9568 09:31:12.208848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9569 09:31:12.212264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9570 09:31:12.215816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9571 09:31:12.222375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9572 09:31:12.225692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9573 09:31:12.232434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9574 09:31:12.235452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9575 09:31:12.242300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9576 09:31:12.245679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9577 09:31:12.248798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9578 09:31:12.255782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9579 09:31:12.258747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9580 09:31:12.265651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9581 09:31:12.268954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9582 09:31:12.275856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9583 09:31:12.278936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9584 09:31:12.282551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9585 09:31:12.289065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9586 09:31:12.292705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9587 09:31:12.299382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9588 09:31:12.302839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9589 09:31:12.309451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9590 09:31:12.312404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9591 09:31:12.316032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9592 09:31:12.322655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9593 09:31:12.325655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9594 09:31:12.332666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9595 09:31:12.335834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9596 09:31:12.342519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9597 09:31:12.346065 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9598 09:31:12.349391 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9599 09:31:12.352424 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9600 09:31:12.359290 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9601 09:31:12.362369 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9602 09:31:12.365849 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9603 09:31:12.372499 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9604 09:31:12.376023 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9605 09:31:12.382594 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9606 09:31:12.386139 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9607 09:31:12.389235 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9608 09:31:12.395909 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9609 09:31:12.399297 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9610 09:31:12.405870 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9611 09:31:12.409267 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9612 09:31:12.413335 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9613 09:31:12.419524 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9614 09:31:12.422569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9615 09:31:12.429319 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9616 09:31:12.432698 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9617 09:31:12.436227 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9618 09:31:12.439321 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9619 09:31:12.446121 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9620 09:31:12.449233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9621 09:31:12.453031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9622 09:31:12.456127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9623 09:31:12.463008 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9624 09:31:12.466125 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9625 09:31:12.469374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9626 09:31:12.475926 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9627 09:31:12.479408 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9628 09:31:12.482840 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9629 09:31:12.489458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9630 09:31:12.493052 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9631 09:31:12.499386 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9632 09:31:12.502887 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9633 09:31:12.506350 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9634 09:31:12.512592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9635 09:31:12.516315 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9636 09:31:12.522504 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9637 09:31:12.526144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9638 09:31:12.529228 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9639 09:31:12.535884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9640 09:31:12.539349 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9641 09:31:12.542863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9642 09:31:12.549292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9643 09:31:12.552844 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9644 09:31:12.559328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9645 09:31:12.562781 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9646 09:31:12.565862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9647 09:31:12.572708 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9648 09:31:12.575808 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9649 09:31:12.582815 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9650 09:31:12.585854 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9651 09:31:12.589245 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9652 09:31:12.595893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9653 09:31:12.599420 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9654 09:31:12.602663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9655 09:31:12.609250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9656 09:31:12.612791 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9657 09:31:12.619264 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9658 09:31:12.622821 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9659 09:31:12.626368 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9660 09:31:12.632612 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9661 09:31:12.636160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9662 09:31:12.639668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9663 09:31:12.646209 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9664 09:31:12.649566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9665 09:31:12.656266 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9666 09:31:12.659852 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9667 09:31:12.662740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9668 09:31:12.669376 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9669 09:31:12.672858 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9670 09:31:12.679389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9671 09:31:12.682846 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9672 09:31:12.686171 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9673 09:31:12.692618 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9674 09:31:12.696139 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9675 09:31:12.702784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9676 09:31:12.705851 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9677 09:31:12.709454 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9678 09:31:12.715835 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9679 09:31:12.719264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9680 09:31:12.722759 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9681 09:31:12.729557 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9682 09:31:12.732610 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9683 09:31:12.739263 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9684 09:31:12.742315 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9685 09:31:12.745735 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9686 09:31:12.752723 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9687 09:31:12.756137 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9688 09:31:12.762220 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9689 09:31:12.765647 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9690 09:31:12.769176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9691 09:31:12.775600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9692 09:31:12.779009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9693 09:31:12.785916 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9694 09:31:12.788779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9695 09:31:12.795772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9696 09:31:12.798886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9697 09:31:12.802379 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9698 09:31:12.808810 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9699 09:31:12.812475 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9700 09:31:12.819057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9701 09:31:12.822102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9702 09:31:12.825438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9703 09:31:12.832202 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9704 09:31:12.835261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9705 09:31:12.842293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9706 09:31:12.845390 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9707 09:31:12.852097 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9708 09:31:12.855222 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9709 09:31:12.858889 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9710 09:31:12.865345 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9711 09:31:12.868389 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9712 09:31:12.875360 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9713 09:31:12.878269 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9714 09:31:12.885292 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9715 09:31:12.888392 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9716 09:31:12.891807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9717 09:31:12.898576 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9718 09:31:12.901660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9719 09:31:12.908279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9720 09:31:12.911452 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9721 09:31:12.915076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9722 09:31:12.921560 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9723 09:31:12.925082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9724 09:31:12.931518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9725 09:31:12.935090 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9726 09:31:12.938186 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9727 09:31:12.944651 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9728 09:31:12.948388 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9729 09:31:12.954806 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9730 09:31:12.958252 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9731 09:31:12.961283 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9732 09:31:12.964740 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9733 09:31:12.971589 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9734 09:31:12.974588 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9735 09:31:12.978143 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9736 09:31:12.984482 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9737 09:31:12.987991 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9738 09:31:12.991609 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9739 09:31:12.997912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9740 09:31:13.001309 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9741 09:31:13.004817 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9742 09:31:13.011394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9743 09:31:13.014497 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9744 09:31:13.020984 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9745 09:31:13.024566 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9746 09:31:13.027514 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9747 09:31:13.034045 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9748 09:31:13.037515 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9749 09:31:13.041282 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9750 09:31:13.047570 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9751 09:31:13.050635 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9752 09:31:13.057636 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9753 09:31:13.060886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9754 09:31:13.063987 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9755 09:31:13.070515 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9756 09:31:13.074214 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9757 09:31:13.077230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9758 09:31:13.084215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9759 09:31:13.087225 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9760 09:31:13.090734 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9761 09:31:13.097334 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9762 09:31:13.100769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9763 09:31:13.107528 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9764 09:31:13.110420 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9765 09:31:13.114029 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9766 09:31:13.120745 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9767 09:31:13.123729 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9768 09:31:13.127314 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9769 09:31:13.133809 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9770 09:31:13.137260 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9771 09:31:13.140351 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9772 09:31:13.143927 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9773 09:31:13.150563 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9774 09:31:13.153568 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9775 09:31:13.157164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9776 09:31:13.160273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9777 09:31:13.167029 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9778 09:31:13.170130 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9779 09:31:13.173441 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9780 09:31:13.176912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9781 09:31:13.183474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9782 09:31:13.186865 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9783 09:31:13.190332 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9784 09:31:13.196857 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9785 09:31:13.200352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9786 09:31:13.206715 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9787 09:31:13.210084 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9788 09:31:13.213378 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9789 09:31:13.219929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9790 09:31:13.223510 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9791 09:31:13.230193 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9792 09:31:13.233672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9793 09:31:13.236692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9794 09:31:13.243286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9795 09:31:13.246886 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9796 09:31:13.253141 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9797 09:31:13.256632 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9798 09:31:13.259693 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9799 09:31:13.266624 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9800 09:31:13.269810 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9801 09:31:13.276311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9802 09:31:13.279770 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9803 09:31:13.286283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9804 09:31:13.289821 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9805 09:31:13.293266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9806 09:31:13.299625 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9807 09:31:13.303085 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9808 09:31:13.309684 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9809 09:31:13.313121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9810 09:31:13.316509 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9811 09:31:13.322636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9812 09:31:13.326283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9813 09:31:13.332984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9814 09:31:13.336037 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9815 09:31:13.339392 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9816 09:31:13.346219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9817 09:31:13.349310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9818 09:31:13.356048 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9819 09:31:13.359103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9820 09:31:13.365924 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9821 09:31:13.368887 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9822 09:31:13.372479 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9823 09:31:13.378909 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9824 09:31:13.382293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9825 09:31:13.388897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9826 09:31:13.392584 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9827 09:31:13.395562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9828 09:31:13.402628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9829 09:31:13.405602 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9830 09:31:13.412232 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9831 09:31:13.415498 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9832 09:31:13.418976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9833 09:31:13.425474 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9834 09:31:13.428948 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9835 09:31:13.435679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9836 09:31:13.438777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9837 09:31:13.445404 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9838 09:31:13.448775 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9839 09:31:13.452356 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9840 09:31:13.459006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9841 09:31:13.461984 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9842 09:31:13.468634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9843 09:31:13.471771 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9844 09:31:13.475304 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9845 09:31:13.482096 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9846 09:31:13.485138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9847 09:31:13.492021 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9848 09:31:13.495308 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9849 09:31:13.498462 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9850 09:31:13.505298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9851 09:31:13.508308 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9852 09:31:13.515269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9853 09:31:13.518637 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9854 09:31:13.522116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9855 09:31:13.528582 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9856 09:31:13.531662 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9857 09:31:13.538357 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9858 09:31:13.541915 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9859 09:31:13.548326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9860 09:31:13.551904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9861 09:31:13.558465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9862 09:31:13.561633 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9863 09:31:13.565168 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9864 09:31:13.571911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9865 09:31:13.574856 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9866 09:31:13.581589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9867 09:31:13.584756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9868 09:31:13.591886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9869 09:31:13.594831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9870 09:31:13.598220 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9871 09:31:13.604635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9872 09:31:13.608057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9873 09:31:13.614482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9874 09:31:13.617959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9875 09:31:13.624660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9876 09:31:13.628135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9877 09:31:13.634550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9878 09:31:13.637609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9879 09:31:13.641127 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9880 09:31:13.647738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9881 09:31:13.650691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9882 09:31:13.657756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9883 09:31:13.660797 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9884 09:31:13.667350 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9885 09:31:13.670930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9886 09:31:13.674026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9887 09:31:13.680697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9888 09:31:13.683766 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9889 09:31:13.690298 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9890 09:31:13.693662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9891 09:31:13.700307 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9892 09:31:13.703792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9893 09:31:13.710297 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9894 09:31:13.713664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9895 09:31:13.717080 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9896 09:31:13.723640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9897 09:31:13.727092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9898 09:31:13.733861 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9899 09:31:13.736829 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9900 09:31:13.743534 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9901 09:31:13.747083 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9902 09:31:13.750427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9903 09:31:13.756874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9904 09:31:13.759972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9905 09:31:13.766860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9906 09:31:13.770463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9907 09:31:13.777089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9908 09:31:13.780163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9909 09:31:13.786834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9910 09:31:13.790316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9911 09:31:13.796755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9912 09:31:13.800313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9913 09:31:13.806748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9914 09:31:13.810115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9915 09:31:13.813126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9916 09:31:13.819992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9917 09:31:13.823448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9918 09:31:13.829932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9919 09:31:13.833262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9920 09:31:13.839635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9921 09:31:13.843285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9922 09:31:13.850109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9923 09:31:13.853033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9924 09:31:13.859969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9925 09:31:13.863529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9926 09:31:13.869827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9927 09:31:13.873428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9928 09:31:13.880053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9929 09:31:13.883026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9930 09:31:13.889638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9931 09:31:13.893330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9932 09:31:13.900015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9933 09:31:13.903532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9934 09:31:13.910160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9935 09:31:13.913177 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9936 09:31:13.916557 INFO: [APUAPC] vio 0
9937 09:31:13.920077 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9938 09:31:13.926414 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9939 09:31:13.929913 INFO: [APUAPC] D0_APC_0: 0x400510
9940 09:31:13.929995 INFO: [APUAPC] D0_APC_1: 0x0
9941 09:31:13.932889 INFO: [APUAPC] D0_APC_2: 0x1540
9942 09:31:13.936400 INFO: [APUAPC] D0_APC_3: 0x0
9943 09:31:13.939850 INFO: [APUAPC] D1_APC_0: 0xffffffff
9944 09:31:13.942807 INFO: [APUAPC] D1_APC_1: 0xffffffff
9945 09:31:13.946397 INFO: [APUAPC] D1_APC_2: 0x3fffff
9946 09:31:13.949458 INFO: [APUAPC] D1_APC_3: 0x0
9947 09:31:13.953071 INFO: [APUAPC] D2_APC_0: 0xffffffff
9948 09:31:13.956181 INFO: [APUAPC] D2_APC_1: 0xffffffff
9949 09:31:13.959674 INFO: [APUAPC] D2_APC_2: 0x3fffff
9950 09:31:13.962660 INFO: [APUAPC] D2_APC_3: 0x0
9951 09:31:13.966251 INFO: [APUAPC] D3_APC_0: 0xffffffff
9952 09:31:13.969302 INFO: [APUAPC] D3_APC_1: 0xffffffff
9953 09:31:13.972604 INFO: [APUAPC] D3_APC_2: 0x3fffff
9954 09:31:13.976373 INFO: [APUAPC] D3_APC_3: 0x0
9955 09:31:13.979389 INFO: [APUAPC] D4_APC_0: 0xffffffff
9956 09:31:13.982850 INFO: [APUAPC] D4_APC_1: 0xffffffff
9957 09:31:13.985857 INFO: [APUAPC] D4_APC_2: 0x3fffff
9958 09:31:13.989422 INFO: [APUAPC] D4_APC_3: 0x0
9959 09:31:13.992590 INFO: [APUAPC] D5_APC_0: 0xffffffff
9960 09:31:13.996152 INFO: [APUAPC] D5_APC_1: 0xffffffff
9961 09:31:13.999129 INFO: [APUAPC] D5_APC_2: 0x3fffff
9962 09:31:14.002550 INFO: [APUAPC] D5_APC_3: 0x0
9963 09:31:14.006075 INFO: [APUAPC] D6_APC_0: 0xffffffff
9964 09:31:14.009194 INFO: [APUAPC] D6_APC_1: 0xffffffff
9965 09:31:14.012719 INFO: [APUAPC] D6_APC_2: 0x3fffff
9966 09:31:14.016180 INFO: [APUAPC] D6_APC_3: 0x0
9967 09:31:14.019306 INFO: [APUAPC] D7_APC_0: 0xffffffff
9968 09:31:14.022828 INFO: [APUAPC] D7_APC_1: 0xffffffff
9969 09:31:14.026165 INFO: [APUAPC] D7_APC_2: 0x3fffff
9970 09:31:14.029147 INFO: [APUAPC] D7_APC_3: 0x0
9971 09:31:14.032458 INFO: [APUAPC] D8_APC_0: 0xffffffff
9972 09:31:14.035852 INFO: [APUAPC] D8_APC_1: 0xffffffff
9973 09:31:14.039378 INFO: [APUAPC] D8_APC_2: 0x3fffff
9974 09:31:14.042247 INFO: [APUAPC] D8_APC_3: 0x0
9975 09:31:14.045796 INFO: [APUAPC] D9_APC_0: 0xffffffff
9976 09:31:14.049289 INFO: [APUAPC] D9_APC_1: 0xffffffff
9977 09:31:14.052434 INFO: [APUAPC] D9_APC_2: 0x3fffff
9978 09:31:14.055945 INFO: [APUAPC] D9_APC_3: 0x0
9979 09:31:14.059127 INFO: [APUAPC] D10_APC_0: 0xffffffff
9980 09:31:14.062295 INFO: [APUAPC] D10_APC_1: 0xffffffff
9981 09:31:14.065706 INFO: [APUAPC] D10_APC_2: 0x3fffff
9982 09:31:14.069186 INFO: [APUAPC] D10_APC_3: 0x0
9983 09:31:14.072660 INFO: [APUAPC] D11_APC_0: 0xffffffff
9984 09:31:14.075570 INFO: [APUAPC] D11_APC_1: 0xffffffff
9985 09:31:14.079144 INFO: [APUAPC] D11_APC_2: 0x3fffff
9986 09:31:14.082381 INFO: [APUAPC] D11_APC_3: 0x0
9987 09:31:14.085928 INFO: [APUAPC] D12_APC_0: 0xffffffff
9988 09:31:14.088919 INFO: [APUAPC] D12_APC_1: 0xffffffff
9989 09:31:14.092618 INFO: [APUAPC] D12_APC_2: 0x3fffff
9990 09:31:14.095596 INFO: [APUAPC] D12_APC_3: 0x0
9991 09:31:14.099172 INFO: [APUAPC] D13_APC_0: 0xffffffff
9992 09:31:14.102240 INFO: [APUAPC] D13_APC_1: 0xffffffff
9993 09:31:14.105689 INFO: [APUAPC] D13_APC_2: 0x3fffff
9994 09:31:14.108816 INFO: [APUAPC] D13_APC_3: 0x0
9995 09:31:14.112160 INFO: [APUAPC] D14_APC_0: 0xffffffff
9996 09:31:14.115735 INFO: [APUAPC] D14_APC_1: 0xffffffff
9997 09:31:14.118773 INFO: [APUAPC] D14_APC_2: 0x3fffff
9998 09:31:14.122369 INFO: [APUAPC] D14_APC_3: 0x0
9999 09:31:14.125872 INFO: [APUAPC] D15_APC_0: 0xffffffff
10000 09:31:14.128777 INFO: [APUAPC] D15_APC_1: 0xffffffff
10001 09:31:14.132275 INFO: [APUAPC] D15_APC_2: 0x3fffff
10002 09:31:14.135766 INFO: [APUAPC] D15_APC_3: 0x0
10003 09:31:14.135871 INFO: [APUAPC] APC_CON: 0x4
10004 09:31:14.139135 INFO: [NOCDAPC] D0_APC_0: 0x0
10005 09:31:14.142322 INFO: [NOCDAPC] D0_APC_1: 0x0
10006 09:31:14.145643 INFO: [NOCDAPC] D1_APC_0: 0x0
10007 09:31:14.148619 INFO: [NOCDAPC] D1_APC_1: 0xfff
10008 09:31:14.152010 INFO: [NOCDAPC] D2_APC_0: 0x0
10009 09:31:14.155580 INFO: [NOCDAPC] D2_APC_1: 0xfff
10010 09:31:14.158735 INFO: [NOCDAPC] D3_APC_0: 0x0
10011 09:31:14.162363 INFO: [NOCDAPC] D3_APC_1: 0xfff
10012 09:31:14.165450 INFO: [NOCDAPC] D4_APC_0: 0x0
10013 09:31:14.165559 INFO: [NOCDAPC] D4_APC_1: 0xfff
10014 09:31:14.169013 INFO: [NOCDAPC] D5_APC_0: 0x0
10015 09:31:14.172438 INFO: [NOCDAPC] D5_APC_1: 0xfff
10016 09:31:14.175477 INFO: [NOCDAPC] D6_APC_0: 0x0
10017 09:31:14.178864 INFO: [NOCDAPC] D6_APC_1: 0xfff
10018 09:31:14.182270 INFO: [NOCDAPC] D7_APC_0: 0x0
10019 09:31:14.185386 INFO: [NOCDAPC] D7_APC_1: 0xfff
10020 09:31:14.188848 INFO: [NOCDAPC] D8_APC_0: 0x0
10021 09:31:14.191997 INFO: [NOCDAPC] D8_APC_1: 0xfff
10022 09:31:14.195572 INFO: [NOCDAPC] D9_APC_0: 0x0
10023 09:31:14.195679 INFO: [NOCDAPC] D9_APC_1: 0xfff
10024 09:31:14.198659 INFO: [NOCDAPC] D10_APC_0: 0x0
10025 09:31:14.202328 INFO: [NOCDAPC] D10_APC_1: 0xfff
10026 09:31:14.205424 INFO: [NOCDAPC] D11_APC_0: 0x0
10027 09:31:14.208893 INFO: [NOCDAPC] D11_APC_1: 0xfff
10028 09:31:14.211972 INFO: [NOCDAPC] D12_APC_0: 0x0
10029 09:31:14.215435 INFO: [NOCDAPC] D12_APC_1: 0xfff
10030 09:31:14.218778 INFO: [NOCDAPC] D13_APC_0: 0x0
10031 09:31:14.222165 INFO: [NOCDAPC] D13_APC_1: 0xfff
10032 09:31:14.225606 INFO: [NOCDAPC] D14_APC_0: 0x0
10033 09:31:14.228507 INFO: [NOCDAPC] D14_APC_1: 0xfff
10034 09:31:14.232179 INFO: [NOCDAPC] D15_APC_0: 0x0
10035 09:31:14.235018 INFO: [NOCDAPC] D15_APC_1: 0xfff
10036 09:31:14.238809 INFO: [NOCDAPC] APC_CON: 0x4
10037 09:31:14.242058 INFO: [APUAPC] set_apusys_apc done
10038 09:31:14.245064 INFO: [DEVAPC] devapc_init done
10039 09:31:14.248490 INFO: GICv3 without legacy support detected.
10040 09:31:14.251974 INFO: ARM GICv3 driver initialized in EL3
10041 09:31:14.254970 INFO: Maximum SPI INTID supported: 639
10042 09:31:14.258420 INFO: BL31: Initializing runtime services
10043 09:31:14.264916 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10044 09:31:14.268500 INFO: SPM: enable CPC mode
10045 09:31:14.271652 INFO: mcdi ready for mcusys-off-idle and system suspend
10046 09:31:14.278027 INFO: BL31: Preparing for EL3 exit to normal world
10047 09:31:14.281534 INFO: Entry point address = 0x80000000
10048 09:31:14.284914 INFO: SPSR = 0x8
10049 09:31:14.289485
10050 09:31:14.289567
10051 09:31:14.289632
10052 09:31:14.292592 Starting depthcharge on Spherion...
10053 09:31:14.292674
10054 09:31:14.292738 Wipe memory regions:
10055 09:31:14.292798
10056 09:31:14.293424 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10057 09:31:14.293523 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10058 09:31:14.293606 Setting prompt string to ['asurada:']
10059 09:31:14.293684 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10060 09:31:14.295591 [0x00000040000000, 0x00000054600000)
10061 09:31:14.417940
10062 09:31:14.418084 [0x00000054660000, 0x00000080000000)
10063 09:31:14.678944
10064 09:31:14.679089 [0x000000821a7280, 0x000000ffe64000)
10065 09:31:15.423772
10066 09:31:15.423926 [0x00000100000000, 0x00000240000000)
10067 09:31:17.313349
10068 09:31:17.316944 Initializing XHCI USB controller at 0x11200000.
10069 09:31:18.355348
10070 09:31:18.358782 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10071 09:31:18.358865
10072 09:31:18.358929
10073 09:31:18.358989
10074 09:31:18.359264 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 09:31:18.459580 asurada: tftpboot 192.168.201.1 11826809/tftp-deploy-_vzq_rat/kernel/image.itb 11826809/tftp-deploy-_vzq_rat/kernel/cmdline
10077 09:31:18.459716 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 09:31:18.459804 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10079 09:31:18.463698 tftpboot 192.168.201.1 11826809/tftp-deploy-_vzq_rat/kernel/image.itp-deploy-_vzq_rat/kernel/cmdline
10080 09:31:18.463784
10081 09:31:18.463849 Waiting for link
10082 09:31:18.624612
10083 09:31:18.624761 R8152: Initializing
10084 09:31:18.624835
10085 09:31:18.627605 Version 9 (ocp_data = 6010)
10086 09:31:18.627686
10087 09:31:18.631080 R8152: Done initializing
10088 09:31:18.631163
10089 09:31:18.631234 Adding net device
10090 09:31:20.503613
10091 09:31:20.503768 done.
10092 09:31:20.503838
10093 09:31:20.503903 MAC: 00:e0:4c:72:2d:d6
10094 09:31:20.503968
10095 09:31:20.506663 Sending DHCP discover... done.
10096 09:31:20.506746
10097 09:31:28.817798 Waiting for reply... done.
10098 09:31:28.818410
10099 09:31:28.818857 Sending DHCP request... done.
10100 09:31:28.819785
10101 09:31:28.820242 Waiting for reply... done.
10102 09:31:28.820668
10103 09:31:28.822929 My ip is 192.168.201.21
10104 09:31:28.823228
10105 09:31:28.826558 The DHCP server ip is 192.168.201.1
10106 09:31:28.826874
10107 09:31:28.829708 TFTP server IP predefined by user: 192.168.201.1
10108 09:31:28.830010
10109 09:31:28.836522 Bootfile predefined by user: 11826809/tftp-deploy-_vzq_rat/kernel/image.itb
10110 09:31:28.836838
10111 09:31:28.839966 Sending tftp read request... done.
10112 09:31:28.840264
10113 09:31:28.842862 Waiting for the transfer...
10114 09:31:28.846245
10115 09:31:29.189700 00000000 ################################################################
10116 09:31:29.189833
10117 09:31:29.443711 00080000 ################################################################
10118 09:31:29.443846
10119 09:31:29.717600 00100000 ################################################################
10120 09:31:29.717751
10121 09:31:30.061787 00180000 ################################################################
10122 09:31:30.061920
10123 09:31:30.355332 00200000 ################################################################
10124 09:31:30.355493
10125 09:31:30.617283 00280000 ################################################################
10126 09:31:30.617429
10127 09:31:30.867232 00300000 ################################################################
10128 09:31:30.867392
10129 09:31:31.187921 00380000 ################################################################
10130 09:31:31.188069
10131 09:31:31.523985 00400000 ################################################################
10132 09:31:31.524139
10133 09:31:31.773902 00480000 ################################################################
10134 09:31:31.774033
10135 09:31:32.068791 00500000 ################################################################
10136 09:31:32.068988
10137 09:31:32.359455 00580000 ################################################################
10138 09:31:32.359588
10139 09:31:32.609698 00600000 ################################################################
10140 09:31:32.609888
10141 09:31:32.892163 00680000 ################################################################
10142 09:31:32.892303
10143 09:31:33.187561 00700000 ################################################################
10144 09:31:33.187695
10145 09:31:33.471157 00780000 ################################################################
10146 09:31:33.471295
10147 09:31:33.722927 00800000 ################################################################
10148 09:31:33.723071
10149 09:31:33.989281 00880000 ################################################################
10150 09:31:33.989423
10151 09:31:34.272658 00900000 ################################################################
10152 09:31:34.272800
10153 09:31:34.563942 00980000 ################################################################
10154 09:31:34.564113
10155 09:31:34.876582 00a00000 ################################################################
10156 09:31:34.876726
10157 09:31:35.182370 00a80000 ################################################################
10158 09:31:35.182516
10159 09:31:35.462910 00b00000 ################################################################
10160 09:31:35.463048
10161 09:31:35.757967 00b80000 ################################################################
10162 09:31:35.758109
10163 09:31:36.053565 00c00000 ################################################################
10164 09:31:36.053711
10165 09:31:36.350129 00c80000 ################################################################
10166 09:31:36.350269
10167 09:31:36.643169 00d00000 ################################################################
10168 09:31:36.643332
10169 09:31:36.936468 00d80000 ################################################################
10170 09:31:36.936615
10171 09:31:37.231590 00e00000 ################################################################
10172 09:31:37.231727
10173 09:31:37.526794 00e80000 ################################################################
10174 09:31:37.526936
10175 09:31:37.782932 00f00000 ################################################################
10176 09:31:37.783072
10177 09:31:38.034494 00f80000 ################################################################
10178 09:31:38.034622
10179 09:31:38.283603 01000000 ################################################################
10180 09:31:38.283737
10181 09:31:38.609036 01080000 ################################################################
10182 09:31:38.609187
10183 09:31:38.921287 01100000 ################################################################
10184 09:31:38.921449
10185 09:31:39.198769 01180000 ################################################################
10186 09:31:39.198937
10187 09:31:39.470012 01200000 ################################################################
10188 09:31:39.470155
10189 09:31:39.738569 01280000 ################################################################
10190 09:31:39.738717
10191 09:31:40.033963 01300000 ################################################################
10192 09:31:40.034101
10193 09:31:40.329056 01380000 ################################################################
10194 09:31:40.329201
10195 09:31:40.592286 01400000 ################################################################
10196 09:31:40.592433
10197 09:31:40.881120 01480000 ################################################################
10198 09:31:40.881265
10199 09:31:41.173296 01500000 ################################################################
10200 09:31:41.173450
10201 09:31:41.473826 01580000 ################################################################
10202 09:31:41.474155
10203 09:31:41.755252 01600000 ################################################################
10204 09:31:41.755404
10205 09:31:42.012331 01680000 ################################################################
10206 09:31:42.012466
10207 09:31:42.293884 01700000 ################################################################
10208 09:31:42.294022
10209 09:31:42.585222 01780000 ################################################################
10210 09:31:42.585366
10211 09:31:42.875320 01800000 ################################################################
10212 09:31:42.875465
10213 09:31:43.169709 01880000 ################################################################
10214 09:31:43.169877
10215 09:31:43.508125 01900000 ################################################################
10216 09:31:43.508310
10217 09:31:43.804649 01980000 ################################################################
10218 09:31:43.804801
10219 09:31:44.075320 01a00000 ################################################################
10220 09:31:44.075455
10221 09:31:44.345718 01a80000 ################################################################
10222 09:31:44.345845
10223 09:31:44.619226 01b00000 ################################################################
10224 09:31:44.619360
10225 09:31:44.643615 01b80000 ####### done.
10226 09:31:44.643701
10227 09:31:44.647074 The bootfile was 28887898 bytes long.
10228 09:31:44.647157
10229 09:31:44.650176 Sending tftp read request... done.
10230 09:31:44.650260
10231 09:31:44.653796 Waiting for the transfer...
10232 09:31:44.653884
10233 09:31:44.653954 00000000 # done.
10234 09:31:44.654021
10235 09:31:44.663714 Command line loaded dynamically from TFTP file: 11826809/tftp-deploy-_vzq_rat/kernel/cmdline
10236 09:31:44.663799
10237 09:31:44.683734 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10238 09:31:44.683826
10239 09:31:44.687000 Loading FIT.
10240 09:31:44.687072
10241 09:31:44.690410 Image ramdisk-1 has 17794327 bytes.
10242 09:31:44.690492
10243 09:31:44.690594 Image fdt-1 has 47278 bytes.
10244 09:31:44.690655
10245 09:31:44.693870 Image kernel-1 has 11044258 bytes.
10246 09:31:44.693952
10247 09:31:44.703712 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10248 09:31:44.703802
10249 09:31:44.720085 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10250 09:31:44.720213
10251 09:31:44.726768 Choosing best match conf-1 for compat google,spherion-rev2.
10252 09:31:44.730445
10253 09:31:44.735036 Connected to device vid:did:rid of 1ae0:0028:00
10254 09:31:44.742005
10255 09:31:44.745103 tpm_get_response: command 0x17b, return code 0x0
10256 09:31:44.745307
10257 09:31:44.748737 ec_init: CrosEC protocol v3 supported (256, 248)
10258 09:31:44.753811
10259 09:31:44.757410 tpm_cleanup: add release locality here.
10260 09:31:44.757653
10261 09:31:44.757845 Shutting down all USB controllers.
10262 09:31:44.760979
10263 09:31:44.761189 Removing current net device
10264 09:31:44.761368
10265 09:31:44.767465 Exiting depthcharge with code 4 at timestamp: 59763611
10266 09:31:44.767744
10267 09:31:44.770957 LZMA decompressing kernel-1 to 0x821a6718
10268 09:31:44.771044
10269 09:31:44.773746 LZMA decompressing kernel-1 to 0x40000000
10270 09:31:46.165093
10271 09:31:46.165660 jumping to kernel
10272 09:31:46.167426 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10273 09:31:46.167973 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10274 09:31:46.168432 Setting prompt string to ['Linux version [0-9]']
10275 09:31:46.168809 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10276 09:31:46.169248 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10277 09:31:46.247169
10278 09:31:46.250596 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10279 09:31:46.253746 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10280 09:31:46.254245 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10281 09:31:46.254642 Setting prompt string to []
10282 09:31:46.255056 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10283 09:31:46.255483 Using line separator: #'\n'#
10284 09:31:46.255819 No login prompt set.
10285 09:31:46.256166 Parsing kernel messages
10286 09:31:46.256475 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10287 09:31:46.257063 [login-action] Waiting for messages, (timeout 00:03:53)
10288 09:31:46.273579 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10289 09:31:46.277128 [ 0.000000] random: crng init done
10290 09:31:46.283327 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10291 09:31:46.286925 [ 0.000000] efi: UEFI not found.
10292 09:31:46.293223 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10293 09:31:46.299512 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10294 09:31:46.309528 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10295 09:31:46.319917 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10296 09:31:46.326739 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10297 09:31:46.333269 [ 0.000000] printk: bootconsole [mtk8250] enabled
10298 09:31:46.340014 [ 0.000000] NUMA: No NUMA configuration found
10299 09:31:46.346257 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10300 09:31:46.349824 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10301 09:31:46.352916 [ 0.000000] Zone ranges:
10302 09:31:46.359354 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10303 09:31:46.362637 [ 0.000000] DMA32 empty
10304 09:31:46.369415 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10305 09:31:46.373007 [ 0.000000] Movable zone start for each node
10306 09:31:46.376366 [ 0.000000] Early memory node ranges
10307 09:31:46.382608 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10308 09:31:46.389477 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10309 09:31:46.396315 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10310 09:31:46.402405 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10311 09:31:46.405779 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10312 09:31:46.415394 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10313 09:31:46.470896 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10314 09:31:46.477669 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10315 09:31:46.484273 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10316 09:31:46.487589 [ 0.000000] psci: probing for conduit method from DT.
10317 09:31:46.494399 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10318 09:31:46.497867 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10319 09:31:46.504351 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10320 09:31:46.507731 [ 0.000000] psci: SMC Calling Convention v1.2
10321 09:31:46.514226 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10322 09:31:46.517791 [ 0.000000] Detected VIPT I-cache on CPU0
10323 09:31:46.524405 [ 0.000000] CPU features: detected: GIC system register CPU interface
10324 09:31:46.530847 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10325 09:31:46.537729 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10326 09:31:46.544138 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10327 09:31:46.550621 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10328 09:31:46.557454 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10329 09:31:46.564414 [ 0.000000] alternatives: applying boot alternatives
10330 09:31:46.567869 [ 0.000000] Fallback order for Node 0: 0
10331 09:31:46.574225 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10332 09:31:46.577477 [ 0.000000] Policy zone: Normal
10333 09:31:46.601086 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10334 09:31:46.610840 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10335 09:31:46.623943 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10336 09:31:46.634140 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10337 09:31:46.641003 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10338 09:31:46.644218 <6>[ 0.000000] software IO TLB: area num 8.
10339 09:31:46.700849 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10340 09:31:46.849582 <6>[ 0.000000] Memory: 7952116K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400652K reserved, 32768K cma-reserved)
10341 09:31:46.856670 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10342 09:31:46.863473 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10343 09:31:46.866223 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10344 09:31:46.872871 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10345 09:31:46.879940 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10346 09:31:46.883250 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10347 09:31:46.893289 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10348 09:31:46.900122 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10349 09:31:46.906355 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10350 09:31:46.913215 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10351 09:31:46.916471 <6>[ 0.000000] GICv3: 608 SPIs implemented
10352 09:31:46.920049 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10353 09:31:46.926669 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10354 09:31:46.929925 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10355 09:31:46.936808 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10356 09:31:46.949751 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10357 09:31:46.959907 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10358 09:31:46.969571 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10359 09:31:46.976648 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10360 09:31:46.990271 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10361 09:31:46.996519 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10362 09:31:47.003112 <6>[ 0.009234] Console: colour dummy device 80x25
10363 09:31:47.013013 <6>[ 0.013988] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10364 09:31:47.019681 <6>[ 0.024430] pid_max: default: 32768 minimum: 301
10365 09:31:47.023070 <6>[ 0.029301] LSM: Security Framework initializing
10366 09:31:47.029962 <6>[ 0.034238] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10367 09:31:47.039733 <6>[ 0.042052] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10368 09:31:47.046149 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10369 09:31:47.052706 <6>[ 0.058910] cblist_init_generic: Setting shift to 3 and lim to 1.
10370 09:31:47.062714 <6>[ 0.065246] cblist_init_generic: Setting adjustable number of callback queues.
10371 09:31:47.069736 <6>[ 0.072673] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 09:31:47.073235 <6>[ 0.079071] rcu: Hierarchical SRCU implementation.
10373 09:31:47.079588 <6>[ 0.084087] rcu: Max phase no-delay instances is 1000.
10374 09:31:47.086276 <6>[ 0.091113] EFI services will not be available.
10375 09:31:47.089098 <6>[ 0.096067] smp: Bringing up secondary CPUs ...
10376 09:31:47.097296 <6>[ 0.101115] Detected VIPT I-cache on CPU1
10377 09:31:47.103948 <6>[ 0.101186] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10378 09:31:47.110673 <6>[ 0.101217] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10379 09:31:47.114218 <6>[ 0.101553] Detected VIPT I-cache on CPU2
10380 09:31:47.120319 <6>[ 0.101604] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10381 09:31:47.130625 <6>[ 0.101621] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10382 09:31:47.134014 <6>[ 0.101881] Detected VIPT I-cache on CPU3
10383 09:31:47.140788 <6>[ 0.101928] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10384 09:31:47.147067 <6>[ 0.101943] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10385 09:31:47.150677 <6>[ 0.102246] CPU features: detected: Spectre-v4
10386 09:31:47.157284 <6>[ 0.102252] CPU features: detected: Spectre-BHB
10387 09:31:47.160538 <6>[ 0.102257] Detected PIPT I-cache on CPU4
10388 09:31:47.167248 <6>[ 0.102315] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10389 09:31:47.173708 <6>[ 0.102331] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10390 09:31:47.180462 <6>[ 0.102623] Detected PIPT I-cache on CPU5
10391 09:31:47.186822 <6>[ 0.102686] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10392 09:31:47.193452 <6>[ 0.102703] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10393 09:31:47.196665 <6>[ 0.102984] Detected PIPT I-cache on CPU6
10394 09:31:47.203433 <6>[ 0.103047] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10395 09:31:47.210382 <6>[ 0.103063] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10396 09:31:47.216773 <6>[ 0.103357] Detected PIPT I-cache on CPU7
10397 09:31:47.223365 <6>[ 0.103421] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10398 09:31:47.230117 <6>[ 0.103437] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10399 09:31:47.233070 <6>[ 0.103485] smp: Brought up 1 node, 8 CPUs
10400 09:31:47.239956 <6>[ 0.244839] SMP: Total of 8 processors activated.
10401 09:31:47.243407 <6>[ 0.249760] CPU features: detected: 32-bit EL0 Support
10402 09:31:47.253388 <6>[ 0.255156] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10403 09:31:47.259601 <6>[ 0.263957] CPU features: detected: Common not Private translations
10404 09:31:47.266351 <6>[ 0.270432] CPU features: detected: CRC32 instructions
10405 09:31:47.269633 <6>[ 0.275816] CPU features: detected: RCpc load-acquire (LDAPR)
10406 09:31:47.276186 <6>[ 0.281813] CPU features: detected: LSE atomic instructions
10407 09:31:47.283028 <6>[ 0.287595] CPU features: detected: Privileged Access Never
10408 09:31:47.289412 <6>[ 0.293374] CPU features: detected: RAS Extension Support
10409 09:31:47.296041 <6>[ 0.298983] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10410 09:31:47.299688 <6>[ 0.306204] CPU: All CPU(s) started at EL2
10411 09:31:47.306241 <6>[ 0.310521] alternatives: applying system-wide alternatives
10412 09:31:47.315018 <6>[ 0.321273] devtmpfs: initialized
10413 09:31:47.327434 <6>[ 0.330274] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10414 09:31:47.337433 <6>[ 0.340236] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10415 09:31:47.343921 <6>[ 0.348248] pinctrl core: initialized pinctrl subsystem
10416 09:31:47.347279 <6>[ 0.354905] DMI not present or invalid.
10417 09:31:47.354035 <6>[ 0.359316] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10418 09:31:47.363753 <6>[ 0.366175] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10419 09:31:47.370813 <6>[ 0.373757] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10420 09:31:47.380384 <6>[ 0.381976] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10421 09:31:47.383810 <6>[ 0.390219] audit: initializing netlink subsys (disabled)
10422 09:31:47.393814 <5>[ 0.395908] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10423 09:31:47.400704 <6>[ 0.396614] thermal_sys: Registered thermal governor 'step_wise'
10424 09:31:47.407048 <6>[ 0.403871] thermal_sys: Registered thermal governor 'power_allocator'
10425 09:31:47.410349 <6>[ 0.410128] cpuidle: using governor menu
10426 09:31:47.417256 <6>[ 0.421086] NET: Registered PF_QIPCRTR protocol family
10427 09:31:47.423873 <6>[ 0.426579] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10428 09:31:47.426914 <6>[ 0.433683] ASID allocator initialised with 32768 entries
10429 09:31:47.434060 <6>[ 0.440243] Serial: AMBA PL011 UART driver
10430 09:31:47.442788 <4>[ 0.449055] Trying to register duplicate clock ID: 134
10431 09:31:47.499736 <6>[ 0.508983] KASLR enabled
10432 09:31:47.514194 <6>[ 0.516736] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10433 09:31:47.520712 <6>[ 0.523750] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10434 09:31:47.527494 <6>[ 0.530240] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10435 09:31:47.534040 <6>[ 0.537247] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10436 09:31:47.540648 <6>[ 0.543738] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10437 09:31:47.547136 <6>[ 0.550743] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10438 09:31:47.554067 <6>[ 0.557228] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10439 09:31:47.560294 <6>[ 0.564229] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10440 09:31:47.563783 <6>[ 0.571750] ACPI: Interpreter disabled.
10441 09:31:47.572138 <6>[ 0.578180] iommu: Default domain type: Translated
10442 09:31:47.578749 <6>[ 0.583291] iommu: DMA domain TLB invalidation policy: strict mode
10443 09:31:47.582185 <5>[ 0.589950] SCSI subsystem initialized
10444 09:31:47.588471 <6>[ 0.594121] usbcore: registered new interface driver usbfs
10445 09:31:47.594939 <6>[ 0.599854] usbcore: registered new interface driver hub
10446 09:31:47.598438 <6>[ 0.605405] usbcore: registered new device driver usb
10447 09:31:47.605381 <6>[ 0.611513] pps_core: LinuxPPS API ver. 1 registered
10448 09:31:47.615216 <6>[ 0.616705] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10449 09:31:47.618699 <6>[ 0.626052] PTP clock support registered
10450 09:31:47.622132 <6>[ 0.630297] EDAC MC: Ver: 3.0.0
10451 09:31:47.629397 <6>[ 0.635467] FPGA manager framework
10452 09:31:47.636234 <6>[ 0.639146] Advanced Linux Sound Architecture Driver Initialized.
10453 09:31:47.639188 <6>[ 0.645928] vgaarb: loaded
10454 09:31:47.646017 <6>[ 0.649096] clocksource: Switched to clocksource arch_sys_counter
10455 09:31:47.649490 <5>[ 0.655535] VFS: Disk quotas dquot_6.6.0
10456 09:31:47.656036 <6>[ 0.659718] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10457 09:31:47.659337 <6>[ 0.666912] pnp: PnP ACPI: disabled
10458 09:31:47.667556 <6>[ 0.673621] NET: Registered PF_INET protocol family
10459 09:31:47.677446 <6>[ 0.679220] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10460 09:31:47.688634 <6>[ 0.691540] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10461 09:31:47.698641 <6>[ 0.700356] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10462 09:31:47.705518 <6>[ 0.708326] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10463 09:31:47.711980 <6>[ 0.717024] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10464 09:31:47.723815 <6>[ 0.726742] TCP: Hash tables configured (established 65536 bind 65536)
10465 09:31:47.730639 <6>[ 0.733600] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10466 09:31:47.736966 <6>[ 0.740796] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10467 09:31:47.743778 <6>[ 0.748498] NET: Registered PF_UNIX/PF_LOCAL protocol family
10468 09:31:47.750205 <6>[ 0.754648] RPC: Registered named UNIX socket transport module.
10469 09:31:47.753370 <6>[ 0.760803] RPC: Registered udp transport module.
10470 09:31:47.760437 <6>[ 0.765734] RPC: Registered tcp transport module.
10471 09:31:47.766750 <6>[ 0.770667] RPC: Registered tcp NFSv4.1 backchannel transport module.
10472 09:31:47.770179 <6>[ 0.777329] PCI: CLS 0 bytes, default 64
10473 09:31:47.773683 <6>[ 0.781647] Unpacking initramfs...
10474 09:31:47.790635 <6>[ 0.793560] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10475 09:31:47.800810 <6>[ 0.802227] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10476 09:31:47.804284 <6>[ 0.811071] kvm [1]: IPA Size Limit: 40 bits
10477 09:31:47.810461 <6>[ 0.815598] kvm [1]: GICv3: no GICV resource entry
10478 09:31:47.813900 <6>[ 0.820617] kvm [1]: disabling GICv2 emulation
10479 09:31:47.820523 <6>[ 0.825307] kvm [1]: GIC system register CPU interface enabled
10480 09:31:47.823958 <6>[ 0.831473] kvm [1]: vgic interrupt IRQ18
10481 09:31:47.830369 <6>[ 0.835826] kvm [1]: VHE mode initialized successfully
10482 09:31:47.837100 <5>[ 0.842325] Initialise system trusted keyrings
10483 09:31:47.843554 <6>[ 0.847127] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10484 09:31:47.851056 <6>[ 0.857080] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10485 09:31:47.857587 <5>[ 0.863485] NFS: Registering the id_resolver key type
10486 09:31:47.860971 <5>[ 0.868802] Key type id_resolver registered
10487 09:31:47.867654 <5>[ 0.873221] Key type id_legacy registered
10488 09:31:47.874619 <6>[ 0.877502] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10489 09:31:47.881028 <6>[ 0.884425] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10490 09:31:47.887524 <6>[ 0.892128] 9p: Installing v9fs 9p2000 file system support
10491 09:31:47.924598 <5>[ 0.930882] Key type asymmetric registered
10492 09:31:47.928041 <5>[ 0.935213] Asymmetric key parser 'x509' registered
10493 09:31:47.938212 <6>[ 0.940353] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10494 09:31:47.941019 <6>[ 0.947970] io scheduler mq-deadline registered
10495 09:31:47.944619 <6>[ 0.952742] io scheduler kyber registered
10496 09:31:47.963737 <6>[ 0.969928] EINJ: ACPI disabled.
10497 09:31:47.996621 <4>[ 0.996050] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10498 09:31:48.006526 <4>[ 1.006695] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10499 09:31:48.021416 <6>[ 1.027784] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10500 09:31:48.029854 <6>[ 1.035923] printk: console [ttyS0] disabled
10501 09:31:48.057887 <6>[ 1.060571] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10502 09:31:48.064820 <6>[ 1.070040] printk: console [ttyS0] enabled
10503 09:31:48.068124 <6>[ 1.070040] printk: console [ttyS0] enabled
10504 09:31:48.074519 <6>[ 1.078934] printk: bootconsole [mtk8250] disabled
10505 09:31:48.077883 <6>[ 1.078934] printk: bootconsole [mtk8250] disabled
10506 09:31:48.084401 <6>[ 1.090190] SuperH (H)SCI(F) driver initialized
10507 09:31:48.087837 <6>[ 1.095469] msm_serial: driver initialized
10508 09:31:48.101809 <6>[ 1.104557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10509 09:31:48.111707 <6>[ 1.113110] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10510 09:31:48.118176 <6>[ 1.121653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10511 09:31:48.128327 <6>[ 1.130283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10512 09:31:48.135401 <6>[ 1.138991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10513 09:31:48.145066 <6>[ 1.147710] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10514 09:31:48.154840 <6>[ 1.156252] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10515 09:31:48.161435 <6>[ 1.165065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10516 09:31:48.171223 <6>[ 1.173609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10517 09:31:48.183264 <6>[ 1.189239] loop: module loaded
10518 09:31:48.189936 <6>[ 1.195299] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10519 09:31:48.212338 <4>[ 1.218617] mtk-pmic-keys: Failed to locate of_node [id: -1]
10520 09:31:48.219301 <6>[ 1.225425] megasas: 07.719.03.00-rc1
10521 09:31:48.228869 <6>[ 1.234910] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10522 09:31:48.238650 <6>[ 1.244479] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10523 09:31:48.254923 <6>[ 1.260980] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10524 09:31:48.311589 <6>[ 1.311010] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10525 09:31:48.513693 <6>[ 1.520155] Freeing initrd memory: 17372K
10526 09:31:48.523959 <6>[ 1.530388] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10527 09:31:48.535019 <6>[ 1.541331] tun: Universal TUN/TAP device driver, 1.6
10528 09:31:48.538527 <6>[ 1.547382] thunder_xcv, ver 1.0
10529 09:31:48.542017 <6>[ 1.550885] thunder_bgx, ver 1.0
10530 09:31:48.544925 <6>[ 1.554378] nicpf, ver 1.0
10531 09:31:48.555433 <6>[ 1.558396] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10532 09:31:48.559005 <6>[ 1.565872] hns3: Copyright (c) 2017 Huawei Corporation.
10533 09:31:48.562413 <6>[ 1.571458] hclge is initializing
10534 09:31:48.568609 <6>[ 1.575039] e1000: Intel(R) PRO/1000 Network Driver
10535 09:31:48.575734 <6>[ 1.580168] e1000: Copyright (c) 1999-2006 Intel Corporation.
10536 09:31:48.578606 <6>[ 1.586182] e1000e: Intel(R) PRO/1000 Network Driver
10537 09:31:48.585499 <6>[ 1.591397] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10538 09:31:48.592206 <6>[ 1.597582] igb: Intel(R) Gigabit Ethernet Network Driver
10539 09:31:48.598747 <6>[ 1.603232] igb: Copyright (c) 2007-2014 Intel Corporation.
10540 09:31:48.605174 <6>[ 1.609068] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10541 09:31:48.611562 <6>[ 1.615587] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10542 09:31:48.615009 <6>[ 1.622049] sky2: driver version 1.30
10543 09:31:48.621821 <6>[ 1.627045] VFIO - User Level meta-driver version: 0.3
10544 09:31:48.629303 <6>[ 1.635284] usbcore: registered new interface driver usb-storage
10545 09:31:48.635537 <6>[ 1.641724] usbcore: registered new device driver onboard-usb-hub
10546 09:31:48.644449 <6>[ 1.650814] mt6397-rtc mt6359-rtc: registered as rtc0
10547 09:31:48.654332 <6>[ 1.656279] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:31:27 UTC (1697794287)
10548 09:31:48.657917 <6>[ 1.665844] i2c_dev: i2c /dev entries driver
10549 09:31:48.674868 <6>[ 1.677674] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10550 09:31:48.694561 <6>[ 1.700662] cpu cpu0: EM: created perf domain
10551 09:31:48.697721 <6>[ 1.705591] cpu cpu4: EM: created perf domain
10552 09:31:48.705056 <6>[ 1.711178] sdhci: Secure Digital Host Controller Interface driver
10553 09:31:48.711492 <6>[ 1.717610] sdhci: Copyright(c) Pierre Ossman
10554 09:31:48.718356 <6>[ 1.722574] Synopsys Designware Multimedia Card Interface Driver
10555 09:31:48.725207 <6>[ 1.729215] sdhci-pltfm: SDHCI platform and OF driver helper
10556 09:31:48.728275 <6>[ 1.729314] mmc0: CQHCI version 5.10
10557 09:31:48.734993 <6>[ 1.739396] ledtrig-cpu: registered to indicate activity on CPUs
10558 09:31:48.741731 <6>[ 1.746478] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10559 09:31:48.748209 <6>[ 1.753536] usbcore: registered new interface driver usbhid
10560 09:31:48.751846 <6>[ 1.759362] usbhid: USB HID core driver
10561 09:31:48.758858 <6>[ 1.763555] spi_master spi0: will run message pump with realtime priority
10562 09:31:48.801744 <6>[ 1.801496] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10563 09:31:48.821279 <6>[ 1.817559] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10564 09:31:48.824884 <6>[ 1.831189] mmc0: Command Queue Engine enabled
10565 09:31:48.831376 <6>[ 1.835962] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10566 09:31:48.838425 <6>[ 1.842893] cros-ec-spi spi0.0: Chrome EC device registered
10567 09:31:48.841560 <6>[ 1.843237] mmcblk0: mmc0:0001 DA4128 116 GiB
10568 09:31:48.854736 <6>[ 1.860659] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10569 09:31:48.862314 <6>[ 1.868388] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10570 09:31:48.872335 <6>[ 1.871991] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10571 09:31:48.875714 <6>[ 1.874416] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10572 09:31:48.882348 <6>[ 1.884143] NET: Registered PF_PACKET protocol family
10573 09:31:48.888983 <6>[ 1.888793] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10574 09:31:48.891968 <6>[ 1.893556] 9pnet: Installing 9P2000 support
10575 09:31:48.898870 <5>[ 1.904539] Key type dns_resolver registered
10576 09:31:48.901995 <6>[ 1.909506] registered taskstats version 1
10577 09:31:48.908668 <5>[ 1.913876] Loading compiled-in X.509 certificates
10578 09:31:48.936543 <4>[ 1.935926] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 09:31:48.946313 <4>[ 1.946689] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 09:31:48.953298 <3>[ 1.957292] debugfs: File 'uA_load' in directory '/' already present!
10581 09:31:48.959859 <3>[ 1.964044] debugfs: File 'min_uV' in directory '/' already present!
10582 09:31:48.966807 <3>[ 1.970657] debugfs: File 'max_uV' in directory '/' already present!
10583 09:31:48.973327 <3>[ 1.977268] debugfs: File 'constraint_flags' in directory '/' already present!
10584 09:31:48.984005 <3>[ 1.986703] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10585 09:31:48.992684 <6>[ 1.999276] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10586 09:31:49.000105 <6>[ 2.006175] xhci-mtk 11200000.usb: xHCI Host Controller
10587 09:31:49.007011 <6>[ 2.011691] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10588 09:31:49.016970 <6>[ 2.019558] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10589 09:31:49.023514 <6>[ 2.028972] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10590 09:31:49.030320 <6>[ 2.035036] xhci-mtk 11200000.usb: xHCI Host Controller
10591 09:31:49.036592 <6>[ 2.040510] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10592 09:31:49.043392 <6>[ 2.048154] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10593 09:31:49.049889 <6>[ 2.055807] hub 1-0:1.0: USB hub found
10594 09:31:49.053665 <6>[ 2.059817] hub 1-0:1.0: 1 port detected
10595 09:31:49.060272 <6>[ 2.064086] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10596 09:31:49.067085 <6>[ 2.072598] hub 2-0:1.0: USB hub found
10597 09:31:49.069958 <6>[ 2.076602] hub 2-0:1.0: 1 port detected
10598 09:31:49.078754 <6>[ 2.084990] mtk-msdc 11f70000.mmc: Got CD GPIO
10599 09:31:49.089351 <6>[ 2.092073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10600 09:31:49.095715 <6>[ 2.100094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10601 09:31:49.106054 <4>[ 2.108015] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10602 09:31:49.112649 <6>[ 2.117538] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10603 09:31:49.123195 <6>[ 2.125614] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10604 09:31:49.129671 <6>[ 2.133687] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10605 09:31:49.139426 <6>[ 2.141616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10606 09:31:49.146094 <6>[ 2.149433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10607 09:31:49.156313 <6>[ 2.157249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10608 09:31:49.163109 <6>[ 2.167396] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10609 09:31:49.172792 <6>[ 2.175775] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10610 09:31:49.183416 <6>[ 2.184115] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10611 09:31:49.189649 <6>[ 2.192454] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10612 09:31:49.199660 <6>[ 2.200792] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10613 09:31:49.206177 <6>[ 2.209132] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10614 09:31:49.213052 <6>[ 2.217471] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10615 09:31:49.223041 <6>[ 2.225809] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10616 09:31:49.232760 <6>[ 2.234148] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10617 09:31:49.239363 <6>[ 2.242487] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10618 09:31:49.249590 <6>[ 2.250839] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10619 09:31:49.256365 <6>[ 2.259177] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10620 09:31:49.263257 <6>[ 2.267527] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10621 09:31:49.272870 <6>[ 2.275867] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10622 09:31:49.279890 <6>[ 2.284206] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10623 09:31:49.286817 <6>[ 2.292990] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10624 09:31:49.294085 <6>[ 2.300211] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10625 09:31:49.300467 <6>[ 2.306984] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10626 09:31:49.310441 <6>[ 2.313742] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10627 09:31:49.317107 <6>[ 2.320691] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10628 09:31:49.323479 <6>[ 2.327541] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10629 09:31:49.333548 <6>[ 2.336674] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10630 09:31:49.343943 <6>[ 2.345794] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10631 09:31:49.353572 <6>[ 2.355095] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10632 09:31:49.363480 <6>[ 2.364565] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10633 09:31:49.370161 <6>[ 2.374033] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10634 09:31:49.380025 <6>[ 2.383152] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10635 09:31:49.389906 <6>[ 2.392620] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10636 09:31:49.400094 <6>[ 2.401740] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10637 09:31:49.409873 <6>[ 2.411035] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10638 09:31:49.419709 <6>[ 2.421195] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10639 09:31:49.429860 <6>[ 2.433184] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10640 09:31:49.436219 <6>[ 2.442867] Trying to probe devices needed for running init ...
10641 09:31:49.457921 <6>[ 2.461617] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10642 09:31:49.485981 <6>[ 2.492847] hub 2-1:1.0: USB hub found
10643 09:31:49.489634 <6>[ 2.497429] hub 2-1:1.0: 3 ports detected
10644 09:31:49.609932 <6>[ 2.613358] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10645 09:31:49.765366 <6>[ 2.771480] hub 1-1:1.0: USB hub found
10646 09:31:49.768663 <6>[ 2.776019] hub 1-1:1.0: 4 ports detected
10647 09:31:49.842559 <6>[ 2.845692] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10648 09:31:50.090170 <6>[ 3.093250] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10649 09:31:50.223163 <6>[ 3.229416] hub 1-1.4:1.0: USB hub found
10650 09:31:50.226407 <6>[ 3.234096] hub 1-1.4:1.0: 2 ports detected
10651 09:31:50.522308 <6>[ 3.525396] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10652 09:31:50.714160 <6>[ 3.717397] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10653 09:32:01.723088 <6>[ 14.734395] ALSA device list:
10654 09:32:01.729577 <6>[ 14.737690] No soundcards found.
10655 09:32:01.737698 <6>[ 14.745654] Freeing unused kernel memory: 8384K
10656 09:32:01.741019 <6>[ 14.750637] Run /init as init process
10657 09:32:01.752291 Loading, please wait...
10658 09:32:01.773533 Starting version 247.3-7+deb11u2
10659 09:32:01.974343 <6>[ 14.978972] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10660 09:32:01.983996 <6>[ 14.991733] remoteproc remoteproc0: scp is available
10661 09:32:01.990773 <6>[ 14.997895] remoteproc remoteproc0: powering up scp
10662 09:32:01.997543 <6>[ 15.003195] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10663 09:32:02.003993 <6>[ 15.011650] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10664 09:32:02.015051 <6>[ 15.019268] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10665 09:32:02.021590 <3>[ 15.024522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 09:32:02.031715 <6>[ 15.028371] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10667 09:32:02.038339 <3>[ 15.036154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 09:32:02.047959 <6>[ 15.043772] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10669 09:32:02.054812 <3>[ 15.051983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 09:32:02.061073 <6>[ 15.053517] mc: Linux media interface: v0.10
10671 09:32:02.064366 <6>[ 15.067781] usbcore: registered new interface driver r8152
10672 09:32:02.074406 <3>[ 15.073451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 09:32:02.081307 <6>[ 15.078516] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10674 09:32:02.090965 <3>[ 15.094641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 09:32:02.094449 <6>[ 15.098318] videodev: Linux video capture interface: v2.00
10676 09:32:02.105461 <4>[ 15.098861] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10677 09:32:02.108280 <4>[ 15.098861] Fallback method does not support PEC.
10678 09:32:02.118358 <3>[ 15.102725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 09:32:02.125345 <3>[ 15.102730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 09:32:02.135156 <3>[ 15.102734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 09:32:02.141572 <3>[ 15.114079] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10682 09:32:02.151964 <3>[ 15.131832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 09:32:02.158167 <6>[ 15.144096] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10684 09:32:02.164722 <6>[ 15.146456] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10685 09:32:02.171376 <6>[ 15.146474] remoteproc remoteproc0: remote processor scp is now up
10686 09:32:02.181567 <4>[ 15.147847] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10687 09:32:02.188316 <3>[ 15.149818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 09:32:02.194589 <3>[ 15.149888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 09:32:02.204433 <3>[ 15.149904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 09:32:02.211266 <3>[ 15.150450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 09:32:02.221290 <3>[ 15.150485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 09:32:02.227625 <3>[ 15.150491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 09:32:02.237545 <3>[ 15.150503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 09:32:02.244618 <3>[ 15.150508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 09:32:02.250937 <6>[ 15.150722] usbcore: registered new interface driver cdc_ether
10696 09:32:02.257601 <3>[ 15.151222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 09:32:02.267883 <6>[ 15.194506] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10698 09:32:02.274344 <4>[ 15.201216] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10699 09:32:02.284007 <6>[ 15.211872] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10700 09:32:02.291089 <6>[ 15.214324] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10701 09:32:02.294213 <6>[ 15.214349] pci_bus 0000:00: root bus resource [bus 00-ff]
10702 09:32:02.303873 <6>[ 15.214357] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10703 09:32:02.313810 <6>[ 15.214363] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10704 09:32:02.317243 <6>[ 15.214409] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10705 09:32:02.327245 <6>[ 15.214442] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10706 09:32:02.330514 <6>[ 15.214552] pci 0000:00:00.0: supports D1 D2
10707 09:32:02.337443 <6>[ 15.214558] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10708 09:32:02.344251 <6>[ 15.216623] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10709 09:32:02.350904 <6>[ 15.216788] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10710 09:32:02.360755 <6>[ 15.216824] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10711 09:32:02.367783 <6>[ 15.216853] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10712 09:32:02.374425 <6>[ 15.216873] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10713 09:32:02.377852 <6>[ 15.217004] pci 0000:01:00.0: supports D1 D2
10714 09:32:02.384648 <6>[ 15.217008] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10715 09:32:02.394055 <6>[ 15.221333] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10716 09:32:02.400703 <6>[ 15.233460] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10717 09:32:02.410685 <6>[ 15.250290] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10718 09:32:02.417483 <6>[ 15.257680] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10719 09:32:02.427318 <6>[ 15.264154] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10720 09:32:02.437472 <4>[ 15.268365] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10721 09:32:02.443826 <4>[ 15.268374] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10722 09:32:02.453615 <6>[ 15.271829] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10723 09:32:02.460441 <6>[ 15.324814] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10724 09:32:02.467009 <6>[ 15.325157] r8152 2-1.3:1.0 eth0: v1.12.13
10725 09:32:02.473418 <6>[ 15.325376] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10726 09:32:02.479927 <6>[ 15.343964] usbcore: registered new interface driver r8153_ecm
10727 09:32:02.490267 <3>[ 15.347487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 09:32:02.496738 <6>[ 15.350396] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10729 09:32:02.500026 <6>[ 15.365438] Bluetooth: Core ver 2.22
10730 09:32:02.506754 <6>[ 15.367918] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10731 09:32:02.513231 <6>[ 15.372389] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10732 09:32:02.522790 <6>[ 15.373680] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10733 09:32:02.533280 <6>[ 15.375019] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10734 09:32:02.539779 <6>[ 15.375125] usbcore: registered new interface driver uvcvideo
10735 09:32:02.546192 <6>[ 15.379917] NET: Registered PF_BLUETOOTH protocol family
10736 09:32:02.549738 <6>[ 15.387330] pci 0000:00:00.0: PCI bridge to [bus 01]
10737 09:32:02.556084 <6>[ 15.391837] Bluetooth: HCI device and connection manager initialized
10738 09:32:02.562799 <6>[ 15.391854] Bluetooth: HCI socket layer initialized
10739 09:32:02.569877 <6>[ 15.398702] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10740 09:32:02.576297 <6>[ 15.405825] Bluetooth: L2CAP socket layer initialized
10741 09:32:02.582607 <6>[ 15.406295] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10742 09:32:02.589174 <6>[ 15.412815] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10743 09:32:02.592510 <6>[ 15.422777] Bluetooth: SCO socket layer initialized
10744 09:32:02.599059 <6>[ 15.431329] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10745 09:32:02.606053 <6>[ 15.509901] usbcore: registered new interface driver btusb
10746 09:32:02.615725 <4>[ 15.511105] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10747 09:32:02.622314 <3>[ 15.511111] Bluetooth: hci0: Failed to load firmware file (-2)
10748 09:32:02.628960 <3>[ 15.511113] Bluetooth: hci0: Failed to set up firmware (-2)
10749 09:32:02.638777 <4>[ 15.511116] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10750 09:32:02.645360 <6>[ 15.513592] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10751 09:32:02.675285 <5>[ 15.679725] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10752 09:32:02.693169 <5>[ 15.697452] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10753 09:32:02.699406 <4>[ 15.704582] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10754 09:32:02.706327 <6>[ 15.713494] cfg80211: failed to load regulatory.db
10755 09:32:02.765773 <6>[ 15.770534] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10756 09:32:02.772829 <6>[ 15.778092] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10757 09:32:02.797162 <6>[ 15.804931] mt7921e 0000:01:00.0: ASIC revision: 79610010
10758 09:32:02.900590 <4>[ 15.901915] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 09:32:02.903800 Begin: Loading essential drivers ... done.
10760 09:32:02.907024 Begin: Running /scripts/init-premount ... done.
10761 09:32:02.913777 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10762 09:32:02.923731 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10763 09:32:02.926965 Device /sys/class/net/enx00e04c722dd6 found
10764 09:32:02.927048 done.
10765 09:32:02.968732 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10766 09:32:03.023699 <4>[ 16.025265] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 09:32:03.143606 <4>[ 16.145057] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 09:32:03.263469 <4>[ 16.265042] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 09:32:03.383923 <4>[ 16.385058] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 09:32:03.503531 <4>[ 16.504985] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 09:32:03.623814 <4>[ 16.625174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 09:32:03.743433 <4>[ 16.745019] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 09:32:03.863440 <4>[ 16.865050] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 09:32:03.983485 <4>[ 16.984780] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 09:32:03.997833 <6>[ 17.005907] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10776 09:32:04.094517 <3>[ 17.102942] mt7921e 0000:01:00.0: hardware init failed
10777 09:32:04.148225 IP-Config: no response after 2 secs - giving up
10778 09:32:04.180409 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10779 09:32:04.183645 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10780 09:32:04.190100 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10781 09:32:04.200357 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10782 09:32:04.206722 host : mt8192-asurada-spherion-r0-cbg-1
10783 09:32:04.213429 domain : lava-rack
10784 09:32:04.216437 rootserver: 192.168.201.1 rootpath:
10785 09:32:04.216526 filename :
10786 09:32:04.254217 done.
10787 09:32:04.262088 Begin: Running /scripts/nfs-bottom ... done.
10788 09:32:04.282000 Begin: Running /scripts/init-bottom ... done.
10789 09:32:05.462268 <6>[ 18.470782] NET: Registered PF_INET6 protocol family
10790 09:32:05.469802 <6>[ 18.478150] Segment Routing with IPv6
10791 09:32:05.472785 <6>[ 18.482184] In-situ OAM (IOAM) with IPv6
10792 09:32:05.595890 <30>[ 18.584493] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10793 09:32:05.599188 <30>[ 18.608844] systemd[1]: Detected architecture arm64.
10794 09:32:05.619913
10795 09:32:05.623368 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10796 09:32:05.623452
10797 09:32:05.639588 <30>[ 18.647834] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10798 09:32:06.455785 <30>[ 19.461245] systemd[1]: Queued start job for default target Graphical Interface.
10799 09:32:06.479377 <30>[ 19.487799] systemd[1]: Created slice system-getty.slice.
10800 09:32:06.485953 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10801 09:32:06.502319 <30>[ 19.510844] systemd[1]: Created slice system-modprobe.slice.
10802 09:32:06.509328 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10803 09:32:06.527236 <30>[ 19.535353] systemd[1]: Created slice system-serial\x2dgetty.slice.
10804 09:32:06.537194 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10805 09:32:06.550144 <30>[ 19.558462] systemd[1]: Created slice User and Session Slice.
10806 09:32:06.556720 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10807 09:32:06.577229 <30>[ 19.582232] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10808 09:32:06.587102 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10809 09:32:06.605344 <30>[ 19.610172] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10810 09:32:06.611693 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10811 09:32:06.635807 <30>[ 19.637556] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10812 09:32:06.642498 <30>[ 19.649701] systemd[1]: Reached target Local Encrypted Volumes.
10813 09:32:06.648989 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10814 09:32:06.665928 <30>[ 19.673948] systemd[1]: Reached target Paths.
10815 09:32:06.669290 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10816 09:32:06.684965 <30>[ 19.693389] systemd[1]: Reached target Remote File Systems.
10817 09:32:06.691468 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10818 09:32:06.709407 <30>[ 19.717745] systemd[1]: Reached target Slices.
10819 09:32:06.715797 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10820 09:32:06.729135 <30>[ 19.737390] systemd[1]: Reached target Swap.
10821 09:32:06.732240 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10822 09:32:06.753143 <30>[ 19.757900] systemd[1]: Listening on initctl Compatibility Named Pipe.
10823 09:32:06.759578 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10824 09:32:06.766112 <30>[ 19.773972] systemd[1]: Listening on Journal Audit Socket.
10825 09:32:06.772956 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10826 09:32:06.790413 <30>[ 19.798668] systemd[1]: Listening on Journal Socket (/dev/log).
10827 09:32:06.796830 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10828 09:32:06.813516 <30>[ 19.821943] systemd[1]: Listening on Journal Socket.
10829 09:32:06.820373 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10830 09:32:06.838069 <30>[ 19.842881] systemd[1]: Listening on Network Service Netlink Socket.
10831 09:32:06.844488 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10832 09:32:06.860121 <30>[ 19.868281] systemd[1]: Listening on udev Control Socket.
10833 09:32:06.866626 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10834 09:32:06.881474 <30>[ 19.889823] systemd[1]: Listening on udev Kernel Socket.
10835 09:32:06.888374 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10836 09:32:06.929109 <30>[ 19.937438] systemd[1]: Mounting Huge Pages File System...
10837 09:32:06.935681 Mounting [0;1;39mHuge Pages File System[0m...
10838 09:32:06.952103 <30>[ 19.960973] systemd[1]: Mounting POSIX Message Queue File System...
10839 09:32:06.959393 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10840 09:32:06.984606 <30>[ 19.993183] systemd[1]: Mounting Kernel Debug File System...
10841 09:32:06.991555 Mounting [0;1;39mKernel Debug File System[0m...
10842 09:32:07.008029 <30>[ 20.013660] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10843 09:32:07.023029 <30>[ 20.028343] systemd[1]: Starting Create list of static device nodes for the current kernel...
10844 09:32:07.029827 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10845 09:32:07.086062 <30>[ 20.094254] systemd[1]: Starting Load Kernel Module configfs...
10846 09:32:07.092396 Starting [0;1;39mLoad Kernel Module configfs[0m...
10847 09:32:07.112074 <30>[ 20.120256] systemd[1]: Starting Load Kernel Module drm...
10848 09:32:07.118610 Starting [0;1;39mLoad Kernel Module drm[0m...
10849 09:32:07.137878 <30>[ 20.146251] systemd[1]: Starting Load Kernel Module fuse...
10850 09:32:07.144359 Starting [0;1;39mLoad Kernel Module fuse[0m...
10851 09:32:07.177138 <6>[ 20.185753] fuse: init (API version 7.37)
10852 09:32:07.187021 <30>[ 20.186115] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10853 09:32:07.225800 <30>[ 20.233958] systemd[1]: Starting Journal Service...
10854 09:32:07.232395 Starting [0;1;39mJournal Service[0m...
10855 09:32:07.253351 <30>[ 20.261687] systemd[1]: Starting Load Kernel Modules...
10856 09:32:07.260098 Starting [0;1;39mLoad Kernel Modules[0m...
10857 09:32:07.279521 <30>[ 20.284807] systemd[1]: Starting Remount Root and Kernel File Systems...
10858 09:32:07.286263 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10859 09:32:07.306775 <30>[ 20.315233] systemd[1]: Starting Coldplug All udev Devices...
10860 09:32:07.313350 Starting [0;1;39mColdplug All udev Devices[0m...
10861 09:32:07.333768 <30>[ 20.342101] systemd[1]: Mounted Huge Pages File System.
10862 09:32:07.340132 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10863 09:32:07.357558 <30>[ 20.365956] systemd[1]: Mounted POSIX Message Queue File System.
10864 09:32:07.364350 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10865 09:32:07.381979 <30>[ 20.389793] systemd[1]: Mounted Kernel Debug File System.
10866 09:32:07.395263 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 20.398725] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 09:32:07.398351 g File System[0m.
10868 09:32:07.418380 <30>[ 20.423309] systemd[1]: Finished Create list of static device nodes for the current kernel.
10869 09:32:07.425724 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10870 09:32:07.435374 <3>[ 20.439739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 09:32:07.442009 <30>[ 20.450562] systemd[1]: modprobe@configfs.service: Succeeded.
10872 09:32:07.449149 <30>[ 20.457418] systemd[1]: Finished Load Kernel Module configfs.
10873 09:32:07.455756 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10874 09:32:07.474086 <30>[ 20.482220] systemd[1]: modprobe@drm.service: Succeeded.
10875 09:32:07.483784 <3>[ 20.486320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 09:32:07.487274 <30>[ 20.488450] systemd[1]: Finished Load Kernel Module drm.
10877 09:32:07.493902 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10878 09:32:07.512770 <3>[ 20.517596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 09:32:07.519348 <30>[ 20.518184] systemd[1]: modprobe@fuse.service: Succeeded.
10880 09:32:07.525245 <30>[ 20.533026] systemd[1]: Finished Load Kernel Module fuse.
10881 09:32:07.532682 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10882 09:32:07.542698 <3>[ 20.547427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 09:32:07.549773 <30>[ 20.558183] systemd[1]: Finished Load Kernel Modules.
10884 09:32:07.555940 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10885 09:32:07.571946 <3>[ 20.577271] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 09:32:07.582387 <30>[ 20.587741] systemd[1]: Finished Remount Root and Kernel File Systems.
10887 09:32:07.588789 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10888 09:32:07.602360 <3>[ 20.607659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 09:32:07.632434 <3>[ 20.638086] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 09:32:07.643196 <30>[ 20.651706] systemd[1]: Mounting FUSE Control File System...
10891 09:32:07.649496 Mounting [0;1;39mFUSE Control File System[0m...
10892 09:32:07.662069 <3>[ 20.667519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 09:32:07.671813 <30>[ 20.680411] systemd[1]: Mounting Kernel Configuration File System...
10894 09:32:07.678762 Mounting [0;1;39mKernel Configuration File System[0m...
10895 09:32:07.694117 <3>[ 20.699340] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 09:32:07.707245 <30>[ 20.712668] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10897 09:32:07.717723 <30>[ 20.722071] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10898 09:32:07.765058 <30>[ 20.774094] systemd[1]: Starting Load/Save Random Seed...
10899 09:32:07.772043 Starting [0;1;39mLoad/Save Random Seed[0m...
10900 09:32:07.787435 <30>[ 20.796023] systemd[1]: Starting Apply Kernel Variables...
10901 09:32:07.793607 Starting [0;1;39mApply Kernel Variables[0m...
10902 09:32:07.821998 <4>[ 20.820571] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10903 09:32:07.828823 <30>[ 20.822033] systemd[1]: Starting Create System Users...
10904 09:32:07.835354 <3>[ 20.836550] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10905 09:32:07.841809 Starting [0;1;39mCreate System Users[0m...
10906 09:32:07.859734 <30>[ 20.868720] systemd[1]: Started Journal Service.
10907 09:32:07.866413 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10908 09:32:07.890509 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10909 09:32:07.904365 See 'systemctl status systemd-udev-trigger.service' for details.
10910 09:32:07.921189 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10911 09:32:07.941281 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10912 09:32:07.958274 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10913 09:32:07.978746 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10914 09:32:07.993712 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10915 09:32:08.033950 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10916 09:32:08.051760 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10917 09:32:08.085359 <46>[ 21.091060] systemd-journald[302]: Received client request to flush runtime journal.
10918 09:32:08.114067 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10919 09:32:08.125094 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10920 09:32:08.140555 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10921 09:32:08.197616 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10922 09:32:09.476621 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10923 09:32:09.517897 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10924 09:32:09.550857 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10925 09:32:09.631153 Starting [0;1;39mNetwork Service[0m...
10926 09:32:09.736291 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10927 09:32:09.917287 Starting [0;1;39mNetwork Time Synchronization[0m...
10928 09:32:09.937427 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10929 09:32:10.044233 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10930 09:32:10.306221 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10931 09:32:10.320782 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10932 09:32:10.339945 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10933 09:32:10.388170 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10934 09:32:10.401720 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10935 09:32:10.426385 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10936 09:32:10.502229 Starting [0;1;39mNetwork Name Resolution[0m...
10937 09:32:10.521206 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10938 09:32:10.541544 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10939 09:32:10.564944 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10940 09:32:10.581690 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10941 09:32:10.597232 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10942 09:32:10.615682 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10943 09:32:10.628668 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10944 09:32:10.644489 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10945 09:32:11.315617 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10946 09:32:11.650411 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10947 09:32:11.673838 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10948 09:32:11.702543 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10949 09:32:11.722759 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10950 09:32:11.753039 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10951 09:32:11.764844 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10952 09:32:11.784003 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10953 09:32:11.846500 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10954 09:32:11.988255 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10955 09:32:12.129442 Starting [0;1;39mUser Login Management[0m...
10956 09:32:12.252390 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10957 09:32:12.268578 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10958 09:32:12.287246 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10959 09:32:12.346521 Starting [0;1;39mPermit User Sessions[0m...
10960 09:32:12.405183 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10961 09:32:12.433283 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10962 09:32:12.465377 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10963 09:32:12.517750 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10964 09:32:12.533159 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10965 09:32:12.551865 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10966 09:32:12.560185 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10967 09:32:12.577502 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10968 09:32:12.639998 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10969 09:32:12.718218 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10970 09:32:12.788177
10971 09:32:12.788331
10972 09:32:12.791392 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10973 09:32:12.791473
10974 09:32:12.794944 debian-bullseye-arm64 login: root (automatic login)
10975 09:32:12.795025
10976 09:32:12.795089
10977 09:32:13.120498 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
10978 09:32:13.121199
10979 09:32:13.127120 The programs included with the Debian GNU/Linux system are free software;
10980 09:32:13.134116 the exact distribution terms for each program are described in the
10981 09:32:13.137125 individual files in /usr/share/doc/*/copyright.
10982 09:32:13.137527
10983 09:32:13.143900 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10984 09:32:13.147233 permitted by applicable law.
10985 09:32:13.245914 Matched prompt #10: / #
10987 09:32:13.247298 Setting prompt string to ['/ #']
10988 09:32:13.247885 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10990 09:32:13.249123 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10991 09:32:13.249620 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10992 09:32:13.250005 Setting prompt string to ['/ #']
10993 09:32:13.250346 Forcing a shell prompt, looking for ['/ #']
10995 09:32:13.301160 / #
10996 09:32:13.301832 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10997 09:32:13.302343 Waiting using forced prompt support (timeout 00:02:30)
10998 09:32:13.307693
10999 09:32:13.308623 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11000 09:32:13.309242 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11002 09:32:13.410626 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8'
11003 09:32:13.417442 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11826809/extract-nfsrootfs-dmrp86a8'
11005 09:32:13.519194 / # export NFS_SERVER_IP='192.168.201.1'
11006 09:32:13.525509 export NFS_SERVER_IP='192.168.201.1'
11007 09:32:13.526363 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11008 09:32:13.526904 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11009 09:32:13.527390 end: 2 depthcharge-action (duration 00:01:34) [common]
11010 09:32:13.527878 start: 3 lava-test-retry (timeout 00:30:00) [common]
11011 09:32:13.528347 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11012 09:32:13.528752 Using namespace: common
11014 09:32:13.630049 / # #
11015 09:32:13.630695 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11016 09:32:13.636124 #
11017 09:32:13.637149 Using /lava-11826809
11019 09:32:13.737679 / # export SHELL=/bin/sh
11020 09:32:13.744524 export SHELL=/bin/sh
11022 09:32:13.846152 / # . /lava-11826809/environment
11023 09:32:13.852736 . /lava-11826809/environment
11025 09:32:13.960142 / # /lava-11826809/bin/lava-test-runner /lava-11826809/0
11026 09:32:13.960770 Test shell timeout: 10s (minimum of the action and connection timeout)
11027 09:32:13.966708 /lava-11826809/bin/lava-test-runner /lava-11826809/0
11028 09:32:14.217912 + export TESTRUN_ID=0_lc-compliance
11029 09:32:14.224850 + cd /lava-11826809/0/tests/0_lc-compliance
11030 09:32:14.225367 + cat uuid
11031 09:32:14.234295 + UUID=11826809_1.6.2.3.1
11032 09:32:14.234760 + set +x
11033 09:32:14.241016 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 11826809_1.6.2.3.1>
11034 09:32:14.241754 Received signal: <STARTRUN> 0_lc-compliance 11826809_1.6.2.3.1
11035 09:32:14.242162 Starting test lava.0_lc-compliance (11826809_1.6.2.3.1)
11036 09:32:14.242602 Skipping test definition patterns.
11037 09:32:14.244589 + /usr/bin/lc-compliance-parser.sh
11038 09:32:15.477525 [0:00:28.366385770] [412] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11039 09:32:15.480554 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11040 09:32:15.493954 [0:00:28.383745847] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11041 09:32:15.553633 [0:00:28.442986155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 09:32:15.572167 [==========] Running 120 tests from 1 test suite.
11043 09:32:15.614651 [0:00:28.504123847] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11044 09:32:15.654469 [----------] Global test environment set-up.
11045 09:32:15.671146 [0:00:28.560771616] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11046 09:32:15.735445 [----------] 120 tests from CaptureTests/SingleStream
11047 09:32:15.817148 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11048 09:32:15.876722 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11049 09:32:15.877028 Received signal: <TESTSET> START CaptureTests/SingleStream
11050 09:32:15.877106 Starting test_set CaptureTests/SingleStream
11051 09:32:15.879590 Camera needs 4 requests, can't test only 1
11052 09:32:15.945906 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11053 09:32:16.015496
11054 09:32:16.035611 [0:00:28.925337309] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11055 09:32:16.102656 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (60 ms)
11056 09:32:16.210033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11057 09:32:16.210772 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11059 09:32:16.227114 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11060 09:32:16.278751 Camera needs 4 requests, can't test only 2
11061 09:32:16.349610 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11062 09:32:16.423703
11063 09:32:16.503157 [0:00:29.392806770] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11064 09:32:16.506299 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (60 ms)
11065 09:32:16.603609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11066 09:32:16.604312 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11068 09:32:16.619560 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11069 09:32:16.673719 Camera needs 4 requests, can't test only 3
11070 09:32:16.755360 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11071 09:32:16.834424
11072 09:32:16.921043 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (57 ms)
11073 09:32:17.021696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11074 09:32:17.022034 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11076 09:32:17.038685 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11077 09:32:17.092781 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (365 ms)
11078 09:32:17.178942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11079 09:32:17.179298 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11081 09:32:17.193515 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11082 09:32:17.231018 [0:00:30.121185386] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11083 09:32:17.243679 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (466 ms)
11084 09:32:17.330695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11085 09:32:17.331049 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11087 09:32:17.348181 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11088 09:32:17.399764 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (730 ms)
11089 09:32:17.480577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11090 09:32:17.481051 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11092 09:32:17.497594 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11093 09:32:18.218630 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (995 ms)
11094 09:32:18.228339 [0:00:31.118032155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11095 09:32:18.324787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11096 09:32:18.325652 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11098 09:32:18.342165 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11099 09:32:19.615765 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1398 ms)
11100 09:32:19.625859 [0:00:32.515790540] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11101 09:32:19.712287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11102 09:32:19.712619 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11104 09:32:19.728010 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11105 09:32:21.713549 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2098 ms)
11106 09:32:21.723462 [0:00:34.613773694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11107 09:32:21.813826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11108 09:32:21.814608 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11110 09:32:21.829810 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11111 09:32:24.911422 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3198 ms)
11112 09:32:24.921333 [0:00:37.811751309] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11113 09:32:24.976486 [0:00:37.867125002] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11114 09:32:25.031427 [0:00:37.922249309] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 09:32:25.034998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11116 09:32:25.035694 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11118 09:32:25.045000 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11119 09:32:25.085881 [0:00:37.976685771] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11120 09:32:25.101625 Camera needs 4 requests, can't test only 1
11121 09:32:25.173844 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11122 09:32:25.250040
11123 09:32:25.336360 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11124 09:32:25.439144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11125 09:32:25.439969 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11127 09:32:25.452538 [0:00:38.343157540] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11128 09:32:25.459754 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11129 09:32:25.514286 Camera needs 4 requests, can't test only 2
11130 09:32:25.598899 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11131 09:32:25.677968
11132 09:32:25.765193 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11133 09:32:25.856632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11134 09:32:25.857487 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11136 09:32:25.875569 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11137 09:32:25.916236 [0:00:38.807180848] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11138 09:32:25.931399 Camera needs 4 requests, can't test only 3
11139 09:32:26.010082 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11140 09:32:26.080136
11141 09:32:26.160339 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
11142 09:32:26.240279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11143 09:32:26.241135 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11145 09:32:26.257063 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11146 09:32:26.310791 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (366 ms)
11147 09:32:26.402208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11148 09:32:26.402964 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11150 09:32:26.419840 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11151 09:32:26.477393 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (465 ms)
11152 09:32:26.567695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11153 09:32:26.568622 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11155 09:32:26.582157 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11156 09:32:26.611421 [0:00:39.502064309] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11157 09:32:26.636337 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (695 ms)
11158 09:32:26.734182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11159 09:32:26.735299 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11161 09:32:26.751179 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11162 09:32:27.596632 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (994 ms)
11163 09:32:27.610079 [0:00:40.497975309] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11164 09:32:27.675441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11165 09:32:27.675780 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11167 09:32:27.686573 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11168 09:32:28.931281 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1334 ms)
11169 09:32:28.944510 [0:00:41.831952233] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11170 09:32:29.036716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11171 09:32:29.037624 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11173 09:32:29.054901 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11174 09:32:31.061202 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2130 ms)
11175 09:32:31.074456 [0:00:43.961908156] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11176 09:32:31.145116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11177 09:32:31.145482 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11179 09:32:31.158175 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11180 09:32:33.143302 <6>[ 46.157337] vpu: disabling
11181 09:32:33.145686 <6>[ 46.160435] vproc2: disabling
11182 09:32:33.149469 <6>[ 46.164178] vproc1: disabling
11183 09:32:33.153694 <6>[ 46.168295] vaud18: disabling
11184 09:32:33.160672 <6>[ 46.172040] vsram_others: disabling
11185 09:32:33.164396 <6>[ 46.176227] va09: disabling
11186 09:32:33.167200 <6>[ 46.179634] vsram_md: disabling
11187 09:32:33.170692 <6>[ 46.183425] Vgpu: disabling
11188 09:32:34.257948 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3196 ms)
11189 09:32:34.270467 [0:00:47.158547694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11190 09:32:34.323402 [0:00:47.214878618] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11191 09:32:34.357581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11192 09:32:34.358275 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11194 09:32:34.376028 [0:00:47.267642618] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11195 09:32:34.379175 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11196 09:32:34.427506 [0:00:47.319281387] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11197 09:32:34.430771 Camera needs 4 requests, can't test only 1
11198 09:32:34.504758 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11199 09:32:34.575081
11200 09:32:34.661152 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11201 09:32:34.756125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11202 09:32:34.756890 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11204 09:32:34.773984 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11205 09:32:34.790490 [0:00:47.682510310] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 09:32:34.835308 Camera needs 4 requests, can't test only 2
11207 09:32:34.918005 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11208 09:32:35.002515
11209 09:32:35.092345 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11210 09:32:35.188958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11211 09:32:35.189732 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11213 09:32:35.207935 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11214 09:32:35.258237 [0:00:48.150141387] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11215 09:32:35.267062 Camera needs 4 requests, can't test only 3
11216 09:32:35.340104 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11217 09:32:35.411567
11218 09:32:35.490402 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (51 ms)
11219 09:32:35.555706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11220 09:32:35.556033 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11222 09:32:35.567861 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11223 09:32:35.605275 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (363 ms)
11224 09:32:35.669951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11225 09:32:35.670718 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11227 09:32:35.687828 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11228 09:32:35.746434 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (468 ms)
11229 09:32:35.843778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11230 09:32:35.844496 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11232 09:32:35.862375 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11233 09:32:35.978611 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (729 ms)
11234 09:32:35.991813 [0:00:48.881097079] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 09:32:36.084746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11236 09:32:36.085655 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11238 09:32:36.105290 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11239 09:32:36.978645 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (999 ms)
11240 09:32:36.991858 [0:00:49.879693925] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 09:32:37.072912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11242 09:32:37.073637 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11244 09:32:37.090988 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11245 09:32:38.374200 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1396 ms)
11246 09:32:38.386978 [0:00:51.275728002] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11247 09:32:38.465666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11248 09:32:38.466017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11250 09:32:38.481351 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11251 09:32:40.470354 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2097 ms)
11252 09:32:40.483453 [0:00:53.372047772] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 09:32:40.569854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11254 09:32:40.570564 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11256 09:32:40.588011 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11257 09:32:43.667038 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3197 ms)
11258 09:32:43.680309 [0:00:56.569717476] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11259 09:32:43.732414 [0:00:56.625313583] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 09:32:43.774522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11261 09:32:43.775252 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11263 09:32:43.791423 [0:00:56.684031261] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11264 09:32:43.794936 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11265 09:32:43.847143 [0:00:56.739776871] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 09:32:43.850716 Camera needs 4 requests, can't test only 1
11267 09:32:43.928610 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11268 09:32:44.011415
11269 09:32:44.096908 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11270 09:32:44.179356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11271 09:32:44.179650 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11273 09:32:44.193521 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11274 09:32:44.212159 [0:00:57.104957897] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 09:32:44.252409 Camera needs 4 requests, can't test only 2
11276 09:32:44.331595 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11277 09:32:44.409346
11278 09:32:44.501130 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (58 ms)
11279 09:32:44.606386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11280 09:32:44.607328 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11282 09:32:44.625011 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11283 09:32:44.675395 [0:00:57.567966241] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11284 09:32:44.678338 Camera needs 4 requests, can't test only 3
11285 09:32:44.756234 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11286 09:32:44.833881
11287 09:32:44.920963 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (57 ms)
11288 09:32:45.007651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11289 09:32:45.007978 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11291 09:32:45.021992 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11292 09:32:45.073541 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (366 ms)
11293 09:32:45.169286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11294 09:32:45.170079 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11296 09:32:45.185631 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11297 09:32:45.239011 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (463 ms)
11298 09:32:45.337815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11299 09:32:45.338510 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11301 09:32:45.356133 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11302 09:32:45.371736 [0:00:58.264102664] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 09:32:45.415325 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (694 ms)
11304 09:32:45.506125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11305 09:32:45.506832 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11307 09:32:45.523589 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11308 09:32:46.359965 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (998 ms)
11309 09:32:46.373297 [0:00:59.261710236] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 09:32:46.467984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11311 09:32:46.468833 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11313 09:32:46.485821 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11314 09:32:47.693606 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1333 ms)
11315 09:32:47.706595 [0:01:00.595768465] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 09:32:47.791626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11317 09:32:47.792372 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11319 09:32:47.808973 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11320 09:32:49.825125 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2131 ms)
11321 09:32:49.837312 [0:01:02.726364848] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 09:32:49.927574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11323 09:32:49.928345 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11325 09:32:49.944803 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11326 09:32:53.022046 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3197 ms)
11327 09:32:53.035295 [0:01:05.923788504] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11328 09:32:53.088446 [0:01:05.980825665] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11329 09:32:53.134279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11330 09:32:53.135092 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11332 09:32:53.147140 [0:01:06.038133405] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11333 09:32:53.153721 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11334 09:32:53.199861 [0:01:06.091988909] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11335 09:32:53.206876 Camera needs 4 requests, can't test only 1
11336 09:32:53.288904 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11337 09:32:53.369421
11338 09:32:53.457131 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11339 09:32:53.550217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11340 09:32:53.550933 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11342 09:32:53.570084 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11343 09:32:53.631261 Camera needs 4 requests, can't test only 2
11344 09:32:53.712827 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11345 09:32:53.791989
11346 09:32:53.885154 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11347 09:32:53.990367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11348 09:32:53.991364 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11350 09:32:54.007271 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11351 09:32:54.066813 Camera needs 4 requests, can't test only 3
11352 09:32:54.150748 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11353 09:32:54.223236
11354 09:32:54.287399 [0:01:07.179669450] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 09:32:54.307666 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11356 09:32:54.396889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11357 09:32:54.397182 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11359 09:32:54.411440 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11360 09:32:54.458923 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1087 ms)
11361 09:32:54.548066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11362 09:32:54.548363 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11364 09:32:54.562272 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11365 09:32:55.663928 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1385 ms)
11366 09:32:55.676841 [0:01:08.565533496] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 09:32:55.765169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11368 09:32:55.765922 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11370 09:32:55.782159 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11371 09:32:57.714439 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2050 ms)
11372 09:32:57.727492 [0:01:10.615655356] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 09:32:57.813906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11374 09:32:57.814727 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11376 09:32:57.832263 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11377 09:33:00.434176 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2720 ms)
11378 09:33:00.447303 [0:01:13.335718428] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 09:33:00.534515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11380 09:33:00.535351 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11382 09:33:00.551335 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11383 09:33:04.550574 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4117 ms)
11384 09:33:04.563740 [0:01:17.452892610] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11385 09:33:04.648285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11386 09:33:04.649064 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11388 09:33:04.665935 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11389 09:33:10.863306 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6313 ms)
11390 09:33:10.876376 [0:01:23.766013783] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11391 09:33:10.953757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11392 09:33:10.954583 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11394 09:33:10.970938 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11395 09:33:20.512060 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9650 ms)
11396 09:33:20.525020 [0:01:33.414272503] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11397 09:33:20.572220 [0:01:33.466109303] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11398 09:33:20.610271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11399 09:33:20.610948 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11401 09:33:20.628075 [0:01:33.521485180] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11402 09:33:20.634376 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11403 09:33:20.682005 [0:01:33.575578623] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11404 09:33:20.684982 Camera needs 4 requests, can't test only 1
11405 09:33:20.763929 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11406 09:33:20.846544
11407 09:33:20.938054 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (52 ms)
11408 09:33:21.033634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11409 09:33:21.034348 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11411 09:33:21.048395 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11412 09:33:21.098231 Camera needs 4 requests, can't test only 2
11413 09:33:21.183107 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11414 09:33:21.265298
11415 09:33:21.355539 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11416 09:33:21.445555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11417 09:33:21.445877 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11419 09:33:21.455619 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11420 09:33:21.509986 Camera needs 4 requests, can't test only 3
11421 09:33:21.592926 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11422 09:33:21.668840
11423 09:33:21.753471 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11424 09:33:21.767150 [0:01:34.661319186] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 09:33:21.849194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11426 09:33:21.850043 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11428 09:33:21.863413 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11429 09:33:21.923182 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1086 ms)
11430 09:33:22.005772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11431 09:33:22.006076 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11433 09:33:22.018106 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11434 09:33:23.146814 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1385 ms)
11435 09:33:23.156748 [0:01:36.046486278] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 09:33:23.211275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11437 09:33:23.211559 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11439 09:33:23.221438 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11440 09:33:25.194869 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2048 ms)
11441 09:33:25.204911 [0:01:38.094280152] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 09:33:25.285945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11443 09:33:25.286297 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11445 09:33:25.300630 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11446 09:33:27.975999 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2781 ms)
11447 09:33:27.985571 [0:01:40.875402055] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 09:33:28.079717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11449 09:33:28.080683 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11451 09:33:28.094483 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11452 09:33:32.091155 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4116 ms)
11453 09:33:32.100909 [0:01:44.991236969] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 09:33:32.183242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11455 09:33:32.183525 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11457 09:33:32.194160 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11458 09:33:38.402387 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6312 ms)
11459 09:33:38.411861 [0:01:51.302975896] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 09:33:38.485228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11461 09:33:38.485590 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11463 09:33:38.494716 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11464 09:33:48.016938 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9615 ms)
11465 09:33:48.026473 [0:02:00.919036435] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11466 09:33:48.075299 [0:02:00.971497539] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11467 09:33:48.094503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11468 09:33:48.094779 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11470 09:33:48.104275 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11471 09:33:48.129227 [0:02:01.025872368] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11472 09:33:48.145599 Camera needs 4 requests, can't test only 1
11473 09:33:48.182505 [0:02:01.078836262] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 09:33:48.215796 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11475 09:33:48.277959
11476 09:33:48.348170 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (54 ms)
11477 09:33:48.422119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11478 09:33:48.422398 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11480 09:33:48.431814 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11481 09:33:48.474827 Camera needs 4 requests, can't test only 2
11482 09:33:48.545610 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11483 09:33:48.604693
11484 09:33:48.678580 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (54 ms)
11485 09:33:48.749330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11486 09:33:48.749617 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11488 09:33:48.759520 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11489 09:33:48.806435 Camera needs 4 requests, can't test only 3
11490 09:33:48.875394 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11491 09:33:48.945731
11492 09:33:49.018284 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (52 ms)
11493 09:33:49.097145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11494 09:33:49.097434 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11496 09:33:49.108419 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11497 09:33:49.329721 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1153 ms)
11498 09:33:49.340168 [0:02:02.231434277] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 09:33:49.408923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11500 09:33:49.409208 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11502 09:33:49.418644 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11503 09:33:50.747196 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1417 ms)
11504 09:33:50.756820 [0:02:03.648105459] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 09:33:50.849558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11506 09:33:50.850426 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11508 09:33:50.864032 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11509 09:33:52.860251 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2112 ms)
11510 09:33:52.869865 [0:02:05.760859564] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11511 09:33:52.952343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11512 09:33:52.952667 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11514 09:33:52.964175 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11515 09:33:55.579233 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2718 ms)
11516 09:33:55.589052 [0:02:08.479679497] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 09:33:55.675871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11518 09:33:55.676592 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11520 09:33:55.689604 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11521 09:33:59.694461 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4116 ms)
11522 09:33:59.704407 [0:02:12.595252023] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11523 09:33:59.776129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11524 09:33:59.776478 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11526 09:33:59.788672 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11527 09:34:06.005104 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6310 ms)
11528 09:34:06.015286 [0:02:18.905812770] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11529 09:34:06.082417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11530 09:34:06.082754 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11532 09:34:06.093746 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11533 09:34:15.651171 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9646 ms)
11534 09:34:15.660688 [0:02:28.551087599] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11535 09:34:15.709548 [0:02:28.604354569] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11536 09:34:15.715903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11537 09:34:15.716169 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11539 09:34:15.726293 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11540 09:34:15.765332 [0:02:28.659880100] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11541 09:34:15.768171 Camera needs 4 requests, can't test only 1
11542 09:34:15.818402 [0:02:28.713427958] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 09:34:15.821727 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11544 09:34:15.881902
11545 09:34:15.949595 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11546 09:34:16.016151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11547 09:34:16.016449 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11549 09:34:16.026201 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11550 09:34:16.065344 Camera needs 4 requests, can't test only 2
11551 09:34:16.119704 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11552 09:34:16.176566
11553 09:34:16.243396 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (55 ms)
11554 09:34:16.316515 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11556 09:34:16.319302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11557 09:34:16.328219 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11558 09:34:16.370080 Camera needs 4 requests, can't test only 3
11559 09:34:16.418800 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11560 09:34:16.474942
11561 09:34:16.545522 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11562 09:34:16.612030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11563 09:34:16.612312 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11565 09:34:16.620067 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11566 09:34:16.898987 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1085 ms)
11567 09:34:16.908653 [0:02:29.798792733] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 09:34:16.968314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11569 09:34:16.968587 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11571 09:34:16.975674 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11572 09:34:18.297005 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1384 ms)
11573 09:34:18.297215 [0:02:31.183455378] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 09:34:18.412799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11575 09:34:18.413196 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11577 09:34:18.423414 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11578 09:34:20.331555 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2048 ms)
11579 09:34:20.341030 [0:02:33.231536727] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11580 09:34:20.405216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11581 09:34:20.405494 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11583 09:34:20.413720 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11584 09:34:23.112549 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2781 ms)
11585 09:34:23.122627 [0:02:36.012546280] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11586 09:34:23.178391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11587 09:34:23.178670 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11589 09:34:23.187316 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11590 09:34:27.228463 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4115 ms)
11591 09:34:27.237426 [0:02:40.127756729] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11592 09:34:27.319574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11593 09:34:27.320305 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11595 09:34:27.333271 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11596 09:34:33.538986 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6312 ms)
11597 09:34:33.548413 [0:02:46.439132087] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11598 09:34:33.613168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11599 09:34:33.613453 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11601 09:34:33.622173 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11602 09:34:43.151799 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9613 ms)
11603 09:34:43.161833 [0:02:56.052051068] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11604 09:34:43.254264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11605 09:34:43.255106 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11607 09:34:43.269423 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11608 09:34:43.443223 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (295 ms)
11609 09:34:43.453174 [0:02:56.347181844] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11610 09:34:43.513078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11611 09:34:43.513390 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11613 09:34:43.525558 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11614 09:34:43.739802 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (296 ms)
11615 09:34:43.752805 [0:02:56.643406113] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11616 09:34:43.822234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11617 09:34:43.822995 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11619 09:34:43.838109 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11620 09:34:44.036429 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (297 ms)
11621 09:34:44.049994 [0:02:56.940199113] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11622 09:34:44.128675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11623 09:34:44.129454 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11625 09:34:44.144135 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11626 09:34:44.498474 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (462 ms)
11627 09:34:44.508528 [0:02:57.402293234] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11628 09:34:44.576402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11629 09:34:44.576698 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11631 09:34:44.591017 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11632 09:34:44.995479 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (497 ms)
11633 09:34:45.008550 [0:02:57.899145314] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 09:34:45.076915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11635 09:34:45.077196 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11637 09:34:45.089353 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11638 09:34:45.723625 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (728 ms)
11639 09:34:45.736864 [0:02:58.627221430] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 09:34:45.820695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11641 09:34:45.821498 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11643 09:34:45.836425 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11644 09:34:46.717887 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (994 ms)
11645 09:34:46.730821 [0:02:59.621599776] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11646 09:34:46.810888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11647 09:34:46.811642 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11649 09:34:46.826907 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11650 09:34:48.112526 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1395 ms)
11651 09:34:48.125391 [0:03:01.016149312] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11652 09:34:48.225630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11653 09:34:48.226480 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11655 09:34:48.244758 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11656 09:34:50.207354 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2095 ms)
11657 09:34:50.219817 [0:03:03.110781589] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11658 09:34:50.304590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11659 09:34:50.305418 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11661 09:34:50.321705 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11662 09:34:53.402871 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3195 ms)
11663 09:34:53.415934 [0:03:06.307053693] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11664 09:34:53.498177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11665 09:34:53.498942 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11667 09:34:53.513594 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11668 09:34:53.701563 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (295 ms)
11669 09:34:53.711477 [0:03:06.602308840] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11670 09:34:53.790184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11671 09:34:53.790462 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11673 09:34:53.800853 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11674 09:34:53.998593 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (297 ms)
11675 09:34:54.007729 [0:03:06.898930984] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11676 09:34:54.085845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11677 09:34:54.086139 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11679 09:34:54.096919 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11680 09:34:54.294570 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (296 ms)
11681 09:34:54.304280 [0:03:07.195590818] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11682 09:34:54.385745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11683 09:34:54.386067 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11685 09:34:54.394915 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11686 09:34:54.657999 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (364 ms)
11687 09:34:54.667853 [0:03:07.559028236] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11688 09:34:54.755892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11689 09:34:54.756638 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11691 09:34:54.768590 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11692 09:34:55.121120 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (463 ms)
11693 09:34:55.131089 [0:03:08.022271764] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11694 09:34:55.202507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11695 09:34:55.202792 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11697 09:34:55.211434 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11698 09:34:55.816643 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (695 ms)
11699 09:34:55.826214 [0:03:08.717267660] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11700 09:34:55.908225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11701 09:34:55.908561 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11703 09:34:55.920026 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11704 09:34:56.810953 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (995 ms)
11705 09:34:56.820513 [0:03:09.711923339] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11706 09:34:56.889614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11707 09:34:56.889896 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11709 09:34:56.899281 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11710 09:34:58.142606 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1331 ms)
11711 09:34:58.152394 [0:03:11.043540950] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11712 09:34:58.223801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11713 09:34:58.224610 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11715 09:34:58.235723 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11716 09:35:00.270255 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2128 ms)
11717 09:35:00.280048 [0:03:13.171219715] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11718 09:35:00.367432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11719 09:35:00.367719 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11721 09:35:00.381334 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11722 09:35:03.465033 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3195 ms)
11723 09:35:03.474839 [0:03:16.366830544] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11724 09:35:03.537935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11725 09:35:03.538286 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11727 09:35:03.545959 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11728 09:35:03.760356 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (296 ms)
11729 09:35:03.770484 [0:03:16.662380540] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11730 09:35:03.828390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11731 09:35:03.828672 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11733 09:35:03.836545 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11734 09:35:04.057457 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (297 ms)
11735 09:35:04.067047 [0:03:16.959097324] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11736 09:35:04.122009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11737 09:35:04.122294 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11739 09:35:04.131292 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11740 09:35:04.353545 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (296 ms)
11741 09:35:04.363485 [0:03:17.255513547] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11742 09:35:04.422233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11743 09:35:04.422523 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11745 09:35:04.430431 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11746 09:35:04.717544 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (364 ms)
11747 09:35:04.727273 [0:03:17.618893280] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11748 09:35:04.794462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11749 09:35:04.794745 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11751 09:35:04.804037 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11752 09:35:05.182490 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (465 ms)
11753 09:35:05.192035 [0:03:18.084239008] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 09:35:05.250592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11755 09:35:05.250862 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11757 09:35:05.259530 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11758 09:35:05.911086 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (729 ms)
11759 09:35:05.920712 [0:03:18.812823392] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11760 09:35:05.980059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11761 09:35:05.980390 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11763 09:35:05.988291 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11764 09:35:06.807271 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (896 ms)
11765 09:35:06.816851 [0:03:19.709087068] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11766 09:35:06.878499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11767 09:35:06.878800 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11769 09:35:06.890867 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11770 09:35:08.201078 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1394 ms)
11771 09:35:08.211206 [0:03:21.103021036] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11772 09:35:08.270378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11773 09:35:08.270671 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11775 09:35:08.279435 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11776 09:35:10.295485 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2094 ms)
11777 09:35:10.305905 [0:03:23.197796694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11778 09:35:10.387348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11779 09:35:10.388163 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11781 09:35:10.400956 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11782 09:35:13.493501 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3198 ms)
11783 09:35:13.503076 [0:03:26.395829718] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11784 09:35:13.563983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11785 09:35:13.564279 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11787 09:35:13.572983 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11788 09:35:13.821895 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (328 ms)
11789 09:35:13.831754 [0:03:26.724451544] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11790 09:35:13.887261 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11792 09:35:13.890221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11793 09:35:13.898333 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11794 09:35:14.118957 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (297 ms)
11795 09:35:14.128426 [0:03:27.021276332] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11796 09:35:14.182724 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11798 09:35:14.185481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11799 09:35:14.193930 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11800 09:35:14.415765 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (297 ms)
11801 09:35:14.425597 [0:03:27.317995568] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11802 09:35:14.478235 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11804 09:35:14.480757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11805 09:35:14.489789 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11806 09:35:14.844100 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (428 ms)
11807 09:35:14.854115 [0:03:27.746426131] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11808 09:35:14.932043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11809 09:35:14.932812 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11811 09:35:14.946807 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11812 09:35:15.339886 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (496 ms)
11813 09:35:15.349880 [0:03:28.242227115] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11814 09:35:15.420298 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11816 09:35:15.423553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11817 09:35:15.434246 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11818 09:35:16.035291 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (695 ms)
11819 09:35:16.045054 [0:03:28.937287807] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11820 09:35:16.115466 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11822 09:35:16.118589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11823 09:35:16.128867 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11824 09:35:17.029727 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (995 ms)
11825 09:35:17.039711 [0:03:29.931951161] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11826 09:35:17.109514 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11828 09:35:17.112803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11829 09:35:17.122792 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11830 09:35:18.361258 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1331 ms)
11831 09:35:18.371414 [0:03:31.263778808] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11832 09:35:18.463068 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11834 09:35:18.466096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11835 09:35:18.480739 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11836 09:35:20.488660 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2127 ms)
11837 09:35:20.498453 [0:03:33.391483138] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11838 09:35:20.552634 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11840 09:35:20.555488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11841 09:35:20.564983 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11842 09:35:23.685111 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3197 ms)
11843 09:35:23.776268 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11845 09:35:23.778881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11846 09:35:23.792297 [----------] 120 tests from CaptureTests/SingleStream (188205 ms total)
11847 09:35:23.871588
11848 09:35:23.958617 [----------] Global test environment tear-down
11849 09:35:24.043988 [==========] 120 tests from 1 test suite ran. (188205 ms total)
11850 09:35:24.127210 <LAVA_SIGNAL_TESTSET STOP>
11851 09:35:24.127932 Received signal: <TESTSET> STOP
11852 09:35:24.128316 Closing test_set CaptureTests/SingleStream
11853 09:35:24.141262 + set +x
11854 09:35:24.144724 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 11826809_1.6.2.3.1>
11855 09:35:24.145623 Received signal: <ENDRUN> 0_lc-compliance 11826809_1.6.2.3.1
11856 09:35:24.146263 Ending use of test pattern.
11857 09:35:24.146786 Ending test lava.0_lc-compliance (11826809_1.6.2.3.1), duration 189.90
11859 09:35:24.149612 <LAVA_TEST_RUNNER EXIT>
11860 09:35:24.150463 ok: lava_test_shell seems to have completed
11861 09:35:24.167102 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11862 09:35:24.167582 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11863 09:35:24.167830 end: 3 lava-test-retry (duration 00:03:11) [common]
11864 09:35:24.168077 start: 4 finalize (timeout 00:10:00) [common]
11865 09:35:24.168315 start: 4.1 power-off (timeout 00:00:30) [common]
11866 09:35:24.168714 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11867 09:35:24.260128 >> Command sent successfully.
11868 09:35:24.262545 Returned 0 in 0 seconds
11869 09:35:24.363279 end: 4.1 power-off (duration 00:00:00) [common]
11871 09:35:24.364564 start: 4.2 read-feedback (timeout 00:10:00) [common]
11872 09:35:24.365643 Listened to connection for namespace 'common' for up to 1s
11873 09:35:25.366460 Finalising connection for namespace 'common'
11874 09:35:25.366930 Disconnecting from shell: Finalise
11875 09:35:25.367204 / #
11876 09:35:25.468060 end: 4.2 read-feedback (duration 00:00:01) [common]
11877 09:35:25.469013 end: 4 finalize (duration 00:00:01) [common]
11878 09:35:25.469708 Cleaning after the job
11879 09:35:25.470330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/ramdisk
11880 09:35:25.480758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/kernel
11881 09:35:25.505025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/dtb
11882 09:35:25.505331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/nfsrootfs
11883 09:35:25.552347 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826809/tftp-deploy-_vzq_rat/modules
11884 09:35:25.557905 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826809
11885 09:35:25.813547 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826809
11886 09:35:25.813729 Job finished correctly