Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 105
- Kernel Errors: 272
- Errors: 0
- Boot result: PASS
1 09:26:35.391626 lava-dispatcher, installed at version: 2023.08
2 09:26:35.391897 start: 0 validate
3 09:26:35.392037 Start time: 2023-10-20 09:26:35.392029+00:00 (UTC)
4 09:26:35.392160 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:26:35.392300 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:26:35.656548 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:26:35.656809 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:26:35.925527 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:26:35.926361 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:10.822654 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:10.823505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:27:11.349698 validate duration: 35.96
14 09:27:11.349971 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:27:11.350069 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:27:11.350155 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:27:11.350282 Not decompressing ramdisk as can be used compressed.
18 09:27:11.350367 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 09:27:11.350432 saving as /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/ramdisk/rootfs.cpio.gz
20 09:27:11.350497 total size: 84918747 (80 MB)
21 09:27:13.968848 progress 0 % (0 MB)
22 09:27:14.032985 progress 5 % (4 MB)
23 09:27:14.056349 progress 10 % (8 MB)
24 09:27:14.078431 progress 15 % (12 MB)
25 09:27:14.100802 progress 20 % (16 MB)
26 09:27:14.122403 progress 25 % (20 MB)
27 09:27:14.144241 progress 30 % (24 MB)
28 09:27:14.166572 progress 35 % (28 MB)
29 09:27:14.188721 progress 40 % (32 MB)
30 09:27:14.210812 progress 45 % (36 MB)
31 09:27:14.232510 progress 50 % (40 MB)
32 09:27:14.254614 progress 55 % (44 MB)
33 09:27:14.276753 progress 60 % (48 MB)
34 09:27:14.298827 progress 65 % (52 MB)
35 09:27:14.320842 progress 70 % (56 MB)
36 09:27:14.342547 progress 75 % (60 MB)
37 09:27:14.364827 progress 80 % (64 MB)
38 09:27:14.387001 progress 85 % (68 MB)
39 09:27:14.409063 progress 90 % (72 MB)
40 09:27:14.430900 progress 95 % (76 MB)
41 09:27:14.452641 progress 100 % (80 MB)
42 09:27:14.452887 80 MB downloaded in 3.10 s (26.10 MB/s)
43 09:27:14.453055 end: 1.1.1 http-download (duration 00:00:03) [common]
45 09:27:14.453299 end: 1.1 download-retry (duration 00:00:03) [common]
46 09:27:14.453388 start: 1.2 download-retry (timeout 00:09:57) [common]
47 09:27:14.453475 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 09:27:14.453621 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:27:14.453692 saving as /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/kernel/Image
50 09:27:14.453754 total size: 49236480 (46 MB)
51 09:27:14.453816 No compression specified
52 09:27:14.454996 progress 0 % (0 MB)
53 09:27:14.467897 progress 5 % (2 MB)
54 09:27:14.481029 progress 10 % (4 MB)
55 09:27:14.493936 progress 15 % (7 MB)
56 09:27:14.506623 progress 20 % (9 MB)
57 09:27:14.519370 progress 25 % (11 MB)
58 09:27:14.532164 progress 30 % (14 MB)
59 09:27:14.544905 progress 35 % (16 MB)
60 09:27:14.557995 progress 40 % (18 MB)
61 09:27:14.570795 progress 45 % (21 MB)
62 09:27:14.583984 progress 50 % (23 MB)
63 09:27:14.596880 progress 55 % (25 MB)
64 09:27:14.609783 progress 60 % (28 MB)
65 09:27:14.622465 progress 65 % (30 MB)
66 09:27:14.635120 progress 70 % (32 MB)
67 09:27:14.648068 progress 75 % (35 MB)
68 09:27:14.661416 progress 80 % (37 MB)
69 09:27:14.674694 progress 85 % (39 MB)
70 09:27:14.687970 progress 90 % (42 MB)
71 09:27:14.701962 progress 95 % (44 MB)
72 09:27:14.715121 progress 100 % (46 MB)
73 09:27:14.715413 46 MB downloaded in 0.26 s (179.46 MB/s)
74 09:27:14.715618 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:27:14.715924 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:27:14.716013 start: 1.3 download-retry (timeout 00:09:57) [common]
78 09:27:14.716107 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 09:27:14.716249 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:27:14.716320 saving as /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/dtb/mt8192-asurada-spherion-r0.dtb
81 09:27:14.716382 total size: 47278 (0 MB)
82 09:27:14.716445 No compression specified
83 09:27:14.717844 progress 69 % (0 MB)
84 09:27:14.718126 progress 100 % (0 MB)
85 09:27:14.718283 0 MB downloaded in 0.00 s (23.75 MB/s)
86 09:27:14.718406 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:27:14.718627 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:27:14.718713 start: 1.4 download-retry (timeout 00:09:57) [common]
90 09:27:14.718798 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 09:27:14.718913 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:27:14.718981 saving as /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/modules/modules.tar
93 09:27:14.719080 total size: 8614716 (8 MB)
94 09:27:14.719142 Using unxz to decompress xz
95 09:27:14.723327 progress 0 % (0 MB)
96 09:27:14.744304 progress 5 % (0 MB)
97 09:27:14.768049 progress 10 % (0 MB)
98 09:27:14.791688 progress 15 % (1 MB)
99 09:27:14.815041 progress 20 % (1 MB)
100 09:27:14.839077 progress 25 % (2 MB)
101 09:27:14.865189 progress 30 % (2 MB)
102 09:27:14.891437 progress 35 % (2 MB)
103 09:27:14.914628 progress 40 % (3 MB)
104 09:27:14.938615 progress 45 % (3 MB)
105 09:27:14.964360 progress 50 % (4 MB)
106 09:27:14.988765 progress 55 % (4 MB)
107 09:27:15.013379 progress 60 % (4 MB)
108 09:27:15.038834 progress 65 % (5 MB)
109 09:27:15.066005 progress 70 % (5 MB)
110 09:27:15.089697 progress 75 % (6 MB)
111 09:27:15.116507 progress 80 % (6 MB)
112 09:27:15.142006 progress 85 % (7 MB)
113 09:27:15.167068 progress 90 % (7 MB)
114 09:27:15.197115 progress 95 % (7 MB)
115 09:27:15.224989 progress 100 % (8 MB)
116 09:27:15.231258 8 MB downloaded in 0.51 s (16.04 MB/s)
117 09:27:15.231600 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:27:15.232058 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:27:15.232203 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 09:27:15.232353 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 09:27:15.232481 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:27:15.232622 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 09:27:15.232936 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q
125 09:27:15.233146 makedir: /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin
126 09:27:15.233311 makedir: /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/tests
127 09:27:15.233461 makedir: /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/results
128 09:27:15.233633 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-add-keys
129 09:27:15.233849 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-add-sources
130 09:27:15.234045 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-background-process-start
131 09:27:15.234237 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-background-process-stop
132 09:27:15.234427 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-common-functions
133 09:27:15.234616 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-echo-ipv4
134 09:27:15.234808 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-install-packages
135 09:27:15.235003 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-installed-packages
136 09:27:15.235196 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-os-build
137 09:27:15.235387 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-probe-channel
138 09:27:15.235577 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-probe-ip
139 09:27:15.235813 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-target-ip
140 09:27:15.236002 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-target-mac
141 09:27:15.236194 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-target-storage
142 09:27:15.236393 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-case
143 09:27:15.236585 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-event
144 09:27:15.236776 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-feedback
145 09:27:15.236967 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-raise
146 09:27:15.237158 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-reference
147 09:27:15.237350 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-runner
148 09:27:15.237543 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-set
149 09:27:15.237737 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-test-shell
150 09:27:15.237938 Updating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-install-packages (oe)
151 09:27:15.238162 Updating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/bin/lava-installed-packages (oe)
152 09:27:15.238348 Creating /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/environment
153 09:27:15.238499 LAVA metadata
154 09:27:15.238615 - LAVA_JOB_ID=11826806
155 09:27:15.238722 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:27:15.238878 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 09:27:15.238985 skipped lava-vland-overlay
158 09:27:15.239109 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:27:15.239243 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 09:27:15.239348 skipped lava-multinode-overlay
161 09:27:15.239479 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:27:15.239618 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 09:27:15.239765 Loading test definitions
164 09:27:15.239931 start: 1.5.2.3.1 git-repo-action (timeout 00:09:56) [common]
165 09:27:15.240057 Using /lava-11826806 at stage 0
166 09:27:15.240214 Fetching tests from https://github.com/kernelci/kernelci-core
167 09:27:15.240349 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/0/tests/0_sleep'
168 09:27:15.923162 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/0/tests/0_sleep
169 09:27:15.924542 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 09:27:15.924936 uuid=11826806_1.5.2.3.1 testdef=None
171 09:27:15.925080 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 09:27:15.925339 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
174 09:27:15.925913 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 09:27:15.926142 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
177 09:27:15.926858 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 09:27:15.927093 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
180 09:27:15.927805 runner path: /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/0/tests/0_sleep test_uuid 11826806_1.5.2.3.1
181 09:27:15.927891 sleep_params='mem freeze'
182 09:27:15.928037 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 09:27:15.928244 Creating lava-test-runner.conf files
185 09:27:15.928308 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826806/lava-overlay-zbonk78q/lava-11826806/0 for stage 0
186 09:27:15.928402 - 0_sleep
187 09:27:15.928508 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 09:27:15.928598 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
189 09:27:16.054160 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 09:27:16.054319 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
191 09:27:16.054412 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 09:27:16.054512 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 09:27:16.054601 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
194 09:27:18.534869 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 09:27:18.535274 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
196 09:27:18.535393 extracting modules file /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826806/extract-overlay-ramdisk-aopapax2/ramdisk
197 09:27:18.765667 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 09:27:18.765840 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
199 09:27:18.765945 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826806/compress-overlay-5ia5sbru/overlay-1.5.2.4.tar.gz to ramdisk
200 09:27:18.766020 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826806/compress-overlay-5ia5sbru/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826806/extract-overlay-ramdisk-aopapax2/ramdisk
201 09:27:18.860649 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 09:27:18.860816 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
203 09:27:18.860910 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 09:27:18.861002 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
205 09:27:18.861088 Building ramdisk /var/lib/lava/dispatcher/tmp/11826806/extract-overlay-ramdisk-aopapax2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826806/extract-overlay-ramdisk-aopapax2/ramdisk
206 09:27:20.446347 >> 563460 blocks
207 09:27:30.030528 rename /var/lib/lava/dispatcher/tmp/11826806/extract-overlay-ramdisk-aopapax2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/ramdisk/ramdisk.cpio.gz
208 09:27:30.030984 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 09:27:30.031103 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 09:27:30.031203 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 09:27:30.031314 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/kernel/Image'
212 09:27:42.192446 Returned 0 in 12 seconds
213 09:27:42.293122 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/kernel/image.itb
214 09:27:43.642565 output: FIT description: Kernel Image image with one or more FDT blobs
215 09:27:43.642948 output: Created: Fri Oct 20 10:27:43 2023
216 09:27:43.643024 output: Image 0 (kernel-1)
217 09:27:43.643092 output: Description:
218 09:27:43.643155 output: Created: Fri Oct 20 10:27:43 2023
219 09:27:43.643216 output: Type: Kernel Image
220 09:27:43.643278 output: Compression: lzma compressed
221 09:27:43.643336 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
222 09:27:43.643395 output: Architecture: AArch64
223 09:27:43.643452 output: OS: Linux
224 09:27:43.643508 output: Load Address: 0x00000000
225 09:27:43.643565 output: Entry Point: 0x00000000
226 09:27:43.643620 output: Hash algo: crc32
227 09:27:43.643675 output: Hash value: 05d3904e
228 09:27:43.643761 output: Image 1 (fdt-1)
229 09:27:43.643837 output: Description: mt8192-asurada-spherion-r0
230 09:27:43.643890 output: Created: Fri Oct 20 10:27:43 2023
231 09:27:43.643944 output: Type: Flat Device Tree
232 09:27:43.643997 output: Compression: uncompressed
233 09:27:43.644049 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 09:27:43.644102 output: Architecture: AArch64
235 09:27:43.644154 output: Hash algo: crc32
236 09:27:43.644206 output: Hash value: cc4352de
237 09:27:43.644258 output: Image 2 (ramdisk-1)
238 09:27:43.644310 output: Description: unavailable
239 09:27:43.644362 output: Created: Fri Oct 20 10:27:43 2023
240 09:27:43.644414 output: Type: RAMDisk Image
241 09:27:43.644466 output: Compression: Unknown Compression
242 09:27:43.644517 output: Data Size: 98319697 Bytes = 96015.33 KiB = 93.76 MiB
243 09:27:43.644569 output: Architecture: AArch64
244 09:27:43.644620 output: OS: Linux
245 09:27:43.644672 output: Load Address: unavailable
246 09:27:43.644725 output: Entry Point: unavailable
247 09:27:43.644776 output: Hash algo: crc32
248 09:27:43.644828 output: Hash value: d7a57a2d
249 09:27:43.644880 output: Default Configuration: 'conf-1'
250 09:27:43.644932 output: Configuration 0 (conf-1)
251 09:27:43.644984 output: Description: mt8192-asurada-spherion-r0
252 09:27:43.645036 output: Kernel: kernel-1
253 09:27:43.645088 output: Init Ramdisk: ramdisk-1
254 09:27:43.645139 output: FDT: fdt-1
255 09:27:43.645191 output: Loadables: kernel-1
256 09:27:43.645243 output:
257 09:27:43.645453 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 09:27:43.645565 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 09:27:43.645828 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 09:27:43.645966 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 09:27:43.646055 No LXC device requested
262 09:27:43.646139 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 09:27:43.646227 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 09:27:43.646305 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 09:27:43.646379 Checking files for TFTP limit of 4294967296 bytes.
266 09:27:43.646892 end: 1 tftp-deploy (duration 00:00:32) [common]
267 09:27:43.646995 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 09:27:43.647083 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 09:27:43.647210 substitutions:
270 09:27:43.647274 - {DTB}: 11826806/tftp-deploy-u1ub0oxe/dtb/mt8192-asurada-spherion-r0.dtb
271 09:27:43.647337 - {INITRD}: 11826806/tftp-deploy-u1ub0oxe/ramdisk/ramdisk.cpio.gz
272 09:27:43.647396 - {KERNEL}: 11826806/tftp-deploy-u1ub0oxe/kernel/Image
273 09:27:43.647452 - {LAVA_MAC}: None
274 09:27:43.647507 - {PRESEED_CONFIG}: None
275 09:27:43.647562 - {PRESEED_LOCAL}: None
276 09:27:43.647615 - {RAMDISK}: 11826806/tftp-deploy-u1ub0oxe/ramdisk/ramdisk.cpio.gz
277 09:27:43.647669 - {ROOT_PART}: None
278 09:27:43.647726 - {ROOT}: None
279 09:27:43.647819 - {SERVER_IP}: 192.168.201.1
280 09:27:43.647872 - {TEE}: None
281 09:27:43.647926 Parsed boot commands:
282 09:27:43.647978 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 09:27:43.648248 Parsed boot commands: tftpboot 192.168.201.1 11826806/tftp-deploy-u1ub0oxe/kernel/image.itb 11826806/tftp-deploy-u1ub0oxe/kernel/cmdline
284 09:27:43.648457 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 09:27:43.648599 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 09:27:43.648702 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 09:27:43.648797 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 09:27:43.648870 Not connected, no need to disconnect.
289 09:27:43.648945 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 09:27:43.649033 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 09:27:43.649102 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
292 09:27:43.653538 Setting prompt string to ['lava-test: # ']
293 09:27:43.653929 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 09:27:43.654043 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 09:27:43.654142 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 09:27:43.654295 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 09:27:43.654653 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
298 09:27:48.792132 >> Command sent successfully.
299 09:27:48.794494 Returned 0 in 5 seconds
300 09:27:48.894905 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 09:27:48.895242 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 09:27:48.895343 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 09:27:48.895431 Setting prompt string to 'Starting depthcharge on Spherion...'
305 09:27:48.895499 Changing prompt to 'Starting depthcharge on Spherion...'
306 09:27:48.895568 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 09:27:48.895856 [Enter `^Ec?' for help]
308 09:27:49.071452
309 09:27:49.071613
310 09:27:49.071691 F0: 102B 0000
311 09:27:49.071802
312 09:27:49.071868 F3: 1001 0000 [0200]
313 09:27:49.075303
314 09:27:49.075386 F3: 1001 0000
315 09:27:49.075451
316 09:27:49.075513 F7: 102D 0000
317 09:27:49.075571
318 09:27:49.078475 F1: 0000 0000
319 09:27:49.078558
320 09:27:49.078625 V0: 0000 0000 [0001]
321 09:27:49.078686
322 09:27:49.078745 00: 0007 8000
323 09:27:49.078806
324 09:27:49.082382 01: 0000 0000
325 09:27:49.082465
326 09:27:49.082543 BP: 0C00 0209 [0000]
327 09:27:49.082608
328 09:27:49.086062 G0: 1182 0000
329 09:27:49.086144
330 09:27:49.086213 EC: 0000 0021 [4000]
331 09:27:49.086296
332 09:27:49.089366 S7: 0000 0000 [0000]
333 09:27:49.089448
334 09:27:49.089512 CC: 0000 0000 [0001]
335 09:27:49.089572
336 09:27:49.092855 T0: 0000 0040 [010F]
337 09:27:49.092970
338 09:27:49.093038 Jump to BL
339 09:27:49.093099
340 09:27:49.118583
341 09:27:49.118678
342 09:27:49.118745
343 09:27:49.125760 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 09:27:49.130265 ARM64: Exception handlers installed.
345 09:27:49.132838 ARM64: Testing exception
346 09:27:49.136304 ARM64: Done test exception
347 09:27:49.143939 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 09:27:49.151199 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 09:27:49.158120 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 09:27:49.169882 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 09:27:49.177031 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 09:27:49.183472 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 09:27:49.194810 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 09:27:49.201285 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 09:27:49.221131 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 09:27:49.224639 WDT: Last reset was cold boot
357 09:27:49.228441 SPI1(PAD0) initialized at 2873684 Hz
358 09:27:49.231353 SPI5(PAD0) initialized at 992727 Hz
359 09:27:49.234194 VBOOT: Loading verstage.
360 09:27:49.240807 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 09:27:49.244354 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 09:27:49.247603 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 09:27:49.251382 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 09:27:49.258419 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 09:27:49.265489 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 09:27:49.275795 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 09:27:49.275884
368 09:27:49.275955
369 09:27:49.286326 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 09:27:49.289454 ARM64: Exception handlers installed.
371 09:27:49.292448 ARM64: Testing exception
372 09:27:49.292533 ARM64: Done test exception
373 09:27:49.299051 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 09:27:49.302553 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 09:27:49.317045 Probing TPM: . done!
376 09:27:49.317131 TPM ready after 0 ms
377 09:27:49.323819 Connected to device vid:did:rid of 1ae0:0028:00
378 09:27:49.333700 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 09:27:49.372505 Initialized TPM device CR50 revision 0
380 09:27:49.384153 tlcl_send_startup: Startup return code is 0
381 09:27:49.384306 TPM: setup succeeded
382 09:27:49.395911 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 09:27:49.403894 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 09:27:49.414373 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 09:27:49.423207 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 09:27:49.426569 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 09:27:49.429641 in-header: 03 07 00 00 08 00 00 00
388 09:27:49.433125 in-data: aa e4 47 04 13 02 00 00
389 09:27:49.436309 Chrome EC: UHEPI supported
390 09:27:49.442868 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 09:27:49.446329 in-header: 03 ad 00 00 08 00 00 00
392 09:27:49.449372 in-data: 00 20 20 08 00 00 00 00
393 09:27:49.449470 Phase 1
394 09:27:49.452558 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 09:27:49.459437 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 09:27:49.465836 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 09:27:49.469148 Recovery requested (1009000e)
398 09:27:49.476468 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 09:27:49.481941 tlcl_extend: response is 0
400 09:27:49.490081 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 09:27:49.495355 tlcl_extend: response is 0
402 09:27:49.501992 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 09:27:49.522548 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 09:27:49.529428 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 09:27:49.529528
406 09:27:49.529595
407 09:27:49.540076 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 09:27:49.543181 ARM64: Exception handlers installed.
409 09:27:49.543294 ARM64: Testing exception
410 09:27:49.546134 ARM64: Done test exception
411 09:27:49.567946 pmic_efuse_setting: Set efuses in 11 msecs
412 09:27:49.571118 pmwrap_interface_init: Select PMIF_VLD_RDY
413 09:27:49.578335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 09:27:49.581837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 09:27:49.588369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 09:27:49.592731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 09:27:49.594975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 09:27:49.602889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 09:27:49.605732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 09:27:49.612652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 09:27:49.615931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 09:27:49.618779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 09:27:49.625768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 09:27:49.628900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 09:27:49.632115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 09:27:49.639523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 09:27:49.646074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 09:27:49.652832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 09:27:49.656317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 09:27:49.662873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 09:27:49.669564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 09:27:49.672801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 09:27:49.679276 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 09:27:49.686525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 09:27:49.689807 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 09:27:49.697679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 09:27:49.700744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 09:27:49.706948 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 09:27:49.714128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 09:27:49.718012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 09:27:49.721103 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 09:27:49.727839 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 09:27:49.731208 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 09:27:49.737840 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 09:27:49.741524 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 09:27:49.747811 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 09:27:49.751437 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 09:27:49.757965 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 09:27:49.761159 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 09:27:49.767902 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 09:27:49.771614 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 09:27:49.775449 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 09:27:49.778800 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 09:27:49.785771 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 09:27:49.789242 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 09:27:49.792795 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 09:27:49.796126 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 09:27:49.802509 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 09:27:49.806154 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 09:27:49.809329 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 09:27:49.815949 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 09:27:49.820120 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 09:27:49.822756 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 09:27:49.829258 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 09:27:49.839326 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 09:27:49.842355 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 09:27:49.852532 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 09:27:49.859027 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 09:27:49.865638 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 09:27:49.869137 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 09:27:49.872375 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 09:27:49.880812 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x15
473 09:27:49.887057 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 09:27:49.891101 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
475 09:27:49.897214 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 09:27:49.904834 [RTC]rtc_get_frequency_meter,154: input=15, output=834
477 09:27:49.914593 [RTC]rtc_get_frequency_meter,154: input=7, output=709
478 09:27:49.924620 [RTC]rtc_get_frequency_meter,154: input=11, output=772
479 09:27:49.933720 [RTC]rtc_get_frequency_meter,154: input=13, output=803
480 09:27:49.943255 [RTC]rtc_get_frequency_meter,154: input=12, output=787
481 09:27:49.953075 [RTC]rtc_get_frequency_meter,154: input=12, output=787
482 09:27:49.962072 [RTC]rtc_get_frequency_meter,154: input=13, output=803
483 09:27:49.966113 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
484 09:27:49.972555 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
485 09:27:49.976474 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 09:27:49.979302 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 09:27:49.985773 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 09:27:49.989379 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 09:27:49.992501 ADC[4]: Raw value=905988 ID=7
490 09:27:49.992585 ADC[3]: Raw value=213282 ID=1
491 09:27:49.995968 RAM Code: 0x71
492 09:27:49.999610 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 09:27:50.006079 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 09:27:50.012382 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 09:27:50.019272 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 09:27:50.022618 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 09:27:50.025732 in-header: 03 07 00 00 08 00 00 00
498 09:27:50.028815 in-data: aa e4 47 04 13 02 00 00
499 09:27:50.032457 Chrome EC: UHEPI supported
500 09:27:50.039206 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 09:27:50.042268 in-header: 03 dd 00 00 08 00 00 00
502 09:27:50.045537 in-data: 90 20 60 08 00 00 00 00
503 09:27:50.048729 MRC: failed to locate region type 0.
504 09:27:50.055603 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 09:27:50.058731 DRAM-K: Running full calibration
506 09:27:50.065265 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 09:27:50.065350 header.status = 0x0
508 09:27:50.068713 header.version = 0x6 (expected: 0x6)
509 09:27:50.071834 header.size = 0xd00 (expected: 0xd00)
510 09:27:50.075116 header.flags = 0x0
511 09:27:50.081701 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 09:27:50.099200 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 09:27:50.105773 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 09:27:50.109008 dram_init: ddr_geometry: 2
515 09:27:50.112043 [EMI] MDL number = 2
516 09:27:50.112127 [EMI] Get MDL freq = 0
517 09:27:50.115197 dram_init: ddr_type: 0
518 09:27:50.115281 is_discrete_lpddr4: 1
519 09:27:50.119593 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 09:27:50.119677
521 09:27:50.122141
522 09:27:50.122224 [Bian_co] ETT version 0.0.0.1
523 09:27:50.129205 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 09:27:50.129296
525 09:27:50.131919 dramc_set_vcore_voltage set vcore to 650000
526 09:27:50.135311 Read voltage for 800, 4
527 09:27:50.135394 Vio18 = 0
528 09:27:50.135460 Vcore = 650000
529 09:27:50.138593 Vdram = 0
530 09:27:50.138676 Vddq = 0
531 09:27:50.138742 Vmddr = 0
532 09:27:50.142835 dram_init: config_dvfs: 1
533 09:27:50.145297 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 09:27:50.152107 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 09:27:50.155032 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
536 09:27:50.158532 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
537 09:27:50.162400 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
538 09:27:50.168231 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
539 09:27:50.168315 MEM_TYPE=3, freq_sel=18
540 09:27:50.171582 sv_algorithm_assistance_LP4_1600
541 09:27:50.175143 ============ PULL DRAM RESETB DOWN ============
542 09:27:50.181526 ========== PULL DRAM RESETB DOWN end =========
543 09:27:50.185055 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 09:27:50.188353 ===================================
545 09:27:50.191771 LPDDR4 DRAM CONFIGURATION
546 09:27:50.194855 ===================================
547 09:27:50.194939 EX_ROW_EN[0] = 0x0
548 09:27:50.198453 EX_ROW_EN[1] = 0x0
549 09:27:50.198536 LP4Y_EN = 0x0
550 09:27:50.201685 WORK_FSP = 0x0
551 09:27:50.201769 WL = 0x2
552 09:27:50.205061 RL = 0x2
553 09:27:50.208186 BL = 0x2
554 09:27:50.208269 RPST = 0x0
555 09:27:50.211509 RD_PRE = 0x0
556 09:27:50.211592 WR_PRE = 0x1
557 09:27:50.214788 WR_PST = 0x0
558 09:27:50.214872 DBI_WR = 0x0
559 09:27:50.217915 DBI_RD = 0x0
560 09:27:50.217999 OTF = 0x1
561 09:27:50.221378 ===================================
562 09:27:50.224897 ===================================
563 09:27:50.227945 ANA top config
564 09:27:50.231205 ===================================
565 09:27:50.231288 DLL_ASYNC_EN = 0
566 09:27:50.235086 ALL_SLAVE_EN = 1
567 09:27:50.238187 NEW_RANK_MODE = 1
568 09:27:50.241300 DLL_IDLE_MODE = 1
569 09:27:50.241384 LP45_APHY_COMB_EN = 1
570 09:27:50.244402 TX_ODT_DIS = 1
571 09:27:50.247661 NEW_8X_MODE = 1
572 09:27:50.251221 ===================================
573 09:27:50.254584 ===================================
574 09:27:50.257678 data_rate = 1600
575 09:27:50.260912 CKR = 1
576 09:27:50.264555 DQ_P2S_RATIO = 8
577 09:27:50.267947 ===================================
578 09:27:50.268030 CA_P2S_RATIO = 8
579 09:27:50.271245 DQ_CA_OPEN = 0
580 09:27:50.274492 DQ_SEMI_OPEN = 0
581 09:27:50.277718 CA_SEMI_OPEN = 0
582 09:27:50.280945 CA_FULL_RATE = 0
583 09:27:50.284350 DQ_CKDIV4_EN = 1
584 09:27:50.284434 CA_CKDIV4_EN = 1
585 09:27:50.287510 CA_PREDIV_EN = 0
586 09:27:50.290844 PH8_DLY = 0
587 09:27:50.294027 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 09:27:50.297576 DQ_AAMCK_DIV = 4
589 09:27:50.300945 CA_AAMCK_DIV = 4
590 09:27:50.301028 CA_ADMCK_DIV = 4
591 09:27:50.304400 DQ_TRACK_CA_EN = 0
592 09:27:50.307716 CA_PICK = 800
593 09:27:50.311657 CA_MCKIO = 800
594 09:27:50.314458 MCKIO_SEMI = 0
595 09:27:50.317495 PLL_FREQ = 3068
596 09:27:50.321145 DQ_UI_PI_RATIO = 32
597 09:27:50.321229 CA_UI_PI_RATIO = 0
598 09:27:50.324445 ===================================
599 09:27:50.327396 ===================================
600 09:27:50.330711 memory_type:LPDDR4
601 09:27:50.334048 GP_NUM : 10
602 09:27:50.334132 SRAM_EN : 1
603 09:27:50.337204 MD32_EN : 0
604 09:27:50.340948 ===================================
605 09:27:50.344020 [ANA_INIT] >>>>>>>>>>>>>>
606 09:27:50.347151 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 09:27:50.350543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 09:27:50.354154 ===================================
609 09:27:50.354239 data_rate = 1600,PCW = 0X7600
610 09:27:50.357369 ===================================
611 09:27:50.360487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 09:27:50.366713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 09:27:50.373928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 09:27:50.377336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 09:27:50.380549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 09:27:50.383654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 09:27:50.386854 [ANA_INIT] flow start
618 09:27:50.390663 [ANA_INIT] PLL >>>>>>>>
619 09:27:50.390747 [ANA_INIT] PLL <<<<<<<<
620 09:27:50.393705 [ANA_INIT] MIDPI >>>>>>>>
621 09:27:50.397330 [ANA_INIT] MIDPI <<<<<<<<
622 09:27:50.397414 [ANA_INIT] DLL >>>>>>>>
623 09:27:50.400165 [ANA_INIT] flow end
624 09:27:50.403625 ============ LP4 DIFF to SE enter ============
625 09:27:50.406998 ============ LP4 DIFF to SE exit ============
626 09:27:50.410094 [ANA_INIT] <<<<<<<<<<<<<
627 09:27:50.413952 [Flow] Enable top DCM control >>>>>
628 09:27:50.417218 [Flow] Enable top DCM control <<<<<
629 09:27:50.420036 Enable DLL master slave shuffle
630 09:27:50.427236 ==============================================================
631 09:27:50.427327 Gating Mode config
632 09:27:50.433253 ==============================================================
633 09:27:50.433339 Config description:
634 09:27:50.443149 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 09:27:50.450146 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 09:27:50.456706 SELPH_MODE 0: By rank 1: By Phase
637 09:27:50.459789 ==============================================================
638 09:27:50.463150 GAT_TRACK_EN = 1
639 09:27:50.466413 RX_GATING_MODE = 2
640 09:27:50.469631 RX_GATING_TRACK_MODE = 2
641 09:27:50.473071 SELPH_MODE = 1
642 09:27:50.476350 PICG_EARLY_EN = 1
643 09:27:50.479843 VALID_LAT_VALUE = 1
644 09:27:50.486675 ==============================================================
645 09:27:50.489941 Enter into Gating configuration >>>>
646 09:27:50.492913 Exit from Gating configuration <<<<
647 09:27:50.492998 Enter into DVFS_PRE_config >>>>>
648 09:27:50.506325 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 09:27:50.509472 Exit from DVFS_PRE_config <<<<<
650 09:27:50.512497 Enter into PICG configuration >>>>
651 09:27:50.516175 Exit from PICG configuration <<<<
652 09:27:50.519664 [RX_INPUT] configuration >>>>>
653 09:27:50.519788 [RX_INPUT] configuration <<<<<
654 09:27:50.525953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 09:27:50.530134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 09:27:50.536340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 09:27:50.543557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 09:27:50.550819 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 09:27:50.554549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 09:27:50.561420 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 09:27:50.565225 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 09:27:50.568429 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 09:27:50.571895 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 09:27:50.575599 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 09:27:50.579274 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 09:27:50.583034 ===================================
667 09:27:50.587017 LPDDR4 DRAM CONFIGURATION
668 09:27:50.590727 ===================================
669 09:27:50.593592 EX_ROW_EN[0] = 0x0
670 09:27:50.593708 EX_ROW_EN[1] = 0x0
671 09:27:50.596989 LP4Y_EN = 0x0
672 09:27:50.597072 WORK_FSP = 0x0
673 09:27:50.601379 WL = 0x2
674 09:27:50.601464 RL = 0x2
675 09:27:50.604246 BL = 0x2
676 09:27:50.604330 RPST = 0x0
677 09:27:50.608106 RD_PRE = 0x0
678 09:27:50.608193 WR_PRE = 0x1
679 09:27:50.608259 WR_PST = 0x0
680 09:27:50.611589 DBI_WR = 0x0
681 09:27:50.611672 DBI_RD = 0x0
682 09:27:50.615057 OTF = 0x1
683 09:27:50.618988 ===================================
684 09:27:50.622817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 09:27:50.626167 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 09:27:50.629967 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 09:27:50.633436 ===================================
688 09:27:50.637256 LPDDR4 DRAM CONFIGURATION
689 09:27:50.640537 ===================================
690 09:27:50.640623 EX_ROW_EN[0] = 0x10
691 09:27:50.644624 EX_ROW_EN[1] = 0x0
692 09:27:50.644708 LP4Y_EN = 0x0
693 09:27:50.648288 WORK_FSP = 0x0
694 09:27:50.648371 WL = 0x2
695 09:27:50.651590 RL = 0x2
696 09:27:50.651718 BL = 0x2
697 09:27:50.655031 RPST = 0x0
698 09:27:50.655113 RD_PRE = 0x0
699 09:27:50.659184 WR_PRE = 0x1
700 09:27:50.659267 WR_PST = 0x0
701 09:27:50.662965 DBI_WR = 0x0
702 09:27:50.663047 DBI_RD = 0x0
703 09:27:50.663113 OTF = 0x1
704 09:27:50.667123 ===================================
705 09:27:50.674066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 09:27:50.677069 nWR fixed to 40
707 09:27:50.681557 [ModeRegInit_LP4] CH0 RK0
708 09:27:50.681668 [ModeRegInit_LP4] CH0 RK1
709 09:27:50.684708 [ModeRegInit_LP4] CH1 RK0
710 09:27:50.684790 [ModeRegInit_LP4] CH1 RK1
711 09:27:50.688295 match AC timing 13
712 09:27:50.692145 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 09:27:50.695715 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 09:27:50.702412 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 09:27:50.705205 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 09:27:50.708885 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 09:27:50.712664 [EMI DOE] emi_dcm 0
718 09:27:50.715744 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 09:27:50.715828 ==
720 09:27:50.719394 Dram Type= 6, Freq= 0, CH_0, rank 0
721 09:27:50.725430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 09:27:50.725514 ==
723 09:27:50.729042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 09:27:50.735410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 09:27:50.745611 [CA 0] Center 37 (7~68) winsize 62
726 09:27:50.748403 [CA 1] Center 37 (6~68) winsize 63
727 09:27:50.751759 [CA 2] Center 34 (4~65) winsize 62
728 09:27:50.754952 [CA 3] Center 34 (4~65) winsize 62
729 09:27:50.758069 [CA 4] Center 33 (3~64) winsize 62
730 09:27:50.761397 [CA 5] Center 33 (3~64) winsize 62
731 09:27:50.761480
732 09:27:50.764762 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 09:27:50.764846
734 09:27:50.768608 [CATrainingPosCal] consider 1 rank data
735 09:27:50.771506 u2DelayCellTimex100 = 270/100 ps
736 09:27:50.775025 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 09:27:50.777976 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 09:27:50.784703 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 09:27:50.787745 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 09:27:50.791338 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 09:27:50.794602 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 09:27:50.794685
743 09:27:50.797709 CA PerBit enable=1, Macro0, CA PI delay=33
744 09:27:50.797792
745 09:27:50.800858 [CBTSetCACLKResult] CA Dly = 33
746 09:27:50.800941 CS Dly: 6 (0~37)
747 09:27:50.804280 ==
748 09:27:50.807485 Dram Type= 6, Freq= 0, CH_0, rank 1
749 09:27:50.810943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 09:27:50.811027 ==
751 09:27:50.814522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 09:27:50.820909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 09:27:50.830867 [CA 0] Center 37 (6~68) winsize 63
754 09:27:50.834067 [CA 1] Center 37 (7~68) winsize 62
755 09:27:50.838036 [CA 2] Center 34 (4~65) winsize 62
756 09:27:50.840799 [CA 3] Center 34 (4~65) winsize 62
757 09:27:50.844002 [CA 4] Center 33 (3~64) winsize 62
758 09:27:50.847332 [CA 5] Center 33 (2~64) winsize 63
759 09:27:50.847415
760 09:27:50.850941 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 09:27:50.851024
762 09:27:50.853964 [CATrainingPosCal] consider 2 rank data
763 09:27:50.857296 u2DelayCellTimex100 = 270/100 ps
764 09:27:50.861532 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 09:27:50.867241 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 09:27:50.870557 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 09:27:50.874366 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 09:27:50.878299 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 09:27:50.881447 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 09:27:50.881529
771 09:27:50.885126 CA PerBit enable=1, Macro0, CA PI delay=33
772 09:27:50.885208
773 09:27:50.889418 [CBTSetCACLKResult] CA Dly = 33
774 09:27:50.889501 CS Dly: 6 (0~38)
775 09:27:50.889567
776 09:27:50.892614 ----->DramcWriteLeveling(PI) begin...
777 09:27:50.892701 ==
778 09:27:50.896272 Dram Type= 6, Freq= 0, CH_0, rank 0
779 09:27:50.899716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 09:27:50.899808 ==
781 09:27:50.903920 Write leveling (Byte 0): 35 => 35
782 09:27:50.906677 Write leveling (Byte 1): 29 => 29
783 09:27:50.911138 DramcWriteLeveling(PI) end<-----
784 09:27:50.911220
785 09:27:50.911285 ==
786 09:27:50.913581 Dram Type= 6, Freq= 0, CH_0, rank 0
787 09:27:50.916827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 09:27:50.916910 ==
789 09:27:50.920257 [Gating] SW mode calibration
790 09:27:50.926808 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 09:27:50.933786 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 09:27:50.936852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 09:27:50.941174 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 09:27:50.947114 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 09:27:50.950114 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 09:27:50.953427 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:27:50.960129 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:27:50.963938 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:27:50.966914 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:27:50.973523 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:27:50.976896 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:27:50.980253 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:27:50.983203 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:27:50.990088 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:27:50.993929 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:27:50.996744 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:27:51.003445 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:27:51.006453 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:27:51.009959 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 09:27:51.016562 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 09:27:51.020211 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:27:51.023627 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 09:27:51.030209 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 09:27:51.033641 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 09:27:51.036760 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:27:51.043176 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 09:27:51.046407 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 09:27:51.049777 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
819 09:27:51.056315 0 9 12 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
820 09:27:51.059929 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 09:27:51.062544 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 09:27:51.069684 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 09:27:51.072766 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 09:27:51.076613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 09:27:51.082818 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 09:27:51.086093 0 10 8 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
827 09:27:51.089407 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
828 09:27:51.096001 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 09:27:51.100105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 09:27:51.102995 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 09:27:51.109344 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 09:27:51.113657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 09:27:51.116016 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 09:27:51.122772 0 11 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
835 09:27:51.125788 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
836 09:27:51.129337 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 09:27:51.136057 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 09:27:51.139095 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 09:27:51.142492 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 09:27:51.149413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 09:27:51.152753 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 09:27:51.155939 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
843 09:27:51.163227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:27:51.165989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:27:51.169601 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:27:51.175698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:27:51.179420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:27:51.183181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:27:51.189216 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:27:51.192252 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:27:51.195637 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 09:27:51.199093 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 09:27:51.205837 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 09:27:51.209027 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 09:27:51.212067 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 09:27:51.218667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 09:27:51.221746 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 09:27:51.225317 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 09:27:51.232341 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
860 09:27:51.235381 Total UI for P1: 0, mck2ui 16
861 09:27:51.238447 best dqsien dly found for B0: ( 0, 14, 8)
862 09:27:51.242118 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 09:27:51.245087 Total UI for P1: 0, mck2ui 16
864 09:27:51.248685 best dqsien dly found for B1: ( 0, 14, 10)
865 09:27:51.252007 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
866 09:27:51.255002 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 09:27:51.255100
868 09:27:51.258158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 09:27:51.265489 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 09:27:51.265622 [Gating] SW calibration Done
871 09:27:51.265691 ==
872 09:27:51.269193 Dram Type= 6, Freq= 0, CH_0, rank 0
873 09:27:51.272518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 09:27:51.272601 ==
875 09:27:51.275435 RX Vref Scan: 0
876 09:27:51.275518
877 09:27:51.279264 RX Vref 0 -> 0, step: 1
878 09:27:51.279347
879 09:27:51.279413 RX Delay -130 -> 252, step: 16
880 09:27:51.285861 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
881 09:27:51.289186 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
882 09:27:51.292643 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 09:27:51.295694 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 09:27:51.298918 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
885 09:27:51.305878 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
886 09:27:51.308824 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
887 09:27:51.312011 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
888 09:27:51.315233 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
889 09:27:51.319254 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
890 09:27:51.325222 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
891 09:27:51.328923 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
892 09:27:51.332375 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
893 09:27:51.335411 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
894 09:27:51.342058 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
895 09:27:51.345656 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
896 09:27:51.345739 ==
897 09:27:51.349532 Dram Type= 6, Freq= 0, CH_0, rank 0
898 09:27:51.352217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 09:27:51.352301 ==
900 09:27:51.356119 DQS Delay:
901 09:27:51.356202 DQS0 = 0, DQS1 = 0
902 09:27:51.356268 DQM Delay:
903 09:27:51.358618 DQM0 = 86, DQM1 = 71
904 09:27:51.358701 DQ Delay:
905 09:27:51.362078 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 09:27:51.365351 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
907 09:27:51.368609 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
908 09:27:51.372386 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
909 09:27:51.372470
910 09:27:51.372536
911 09:27:51.372598 ==
912 09:27:51.375167 Dram Type= 6, Freq= 0, CH_0, rank 0
913 09:27:51.382172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 09:27:51.382255 ==
915 09:27:51.382321
916 09:27:51.382381
917 09:27:51.382439 TX Vref Scan disable
918 09:27:51.385707 == TX Byte 0 ==
919 09:27:51.389330 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
920 09:27:51.393325 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
921 09:27:51.396866 == TX Byte 1 ==
922 09:27:51.400625 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
923 09:27:51.404050 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
924 09:27:51.404134 ==
925 09:27:51.407478 Dram Type= 6, Freq= 0, CH_0, rank 0
926 09:27:51.411287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 09:27:51.411372 ==
928 09:27:51.425531 TX Vref=22, minBit 4, minWin=27, winSum=438
929 09:27:51.429567 TX Vref=24, minBit 2, minWin=27, winSum=443
930 09:27:51.432729 TX Vref=26, minBit 3, minWin=27, winSum=443
931 09:27:51.436707 TX Vref=28, minBit 8, minWin=27, winSum=446
932 09:27:51.439935 TX Vref=30, minBit 8, minWin=27, winSum=446
933 09:27:51.443467 TX Vref=32, minBit 11, minWin=26, winSum=440
934 09:27:51.450967 [TxChooseVref] Worse bit 8, Min win 27, Win sum 446, Final Vref 28
935 09:27:51.451070
936 09:27:51.451167 Final TX Range 1 Vref 28
937 09:27:51.451259
938 09:27:51.451346 ==
939 09:27:51.454404 Dram Type= 6, Freq= 0, CH_0, rank 0
940 09:27:51.458272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 09:27:51.458356 ==
942 09:27:51.458450
943 09:27:51.461392
944 09:27:51.461473 TX Vref Scan disable
945 09:27:51.465418 == TX Byte 0 ==
946 09:27:51.469391 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
947 09:27:51.472500 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
948 09:27:51.476073 == TX Byte 1 ==
949 09:27:51.479553 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
950 09:27:51.483880 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
951 09:27:51.483963
952 09:27:51.484028 [DATLAT]
953 09:27:51.487035 Freq=800, CH0 RK0
954 09:27:51.487122
955 09:27:51.487187 DATLAT Default: 0xa
956 09:27:51.490323 0, 0xFFFF, sum = 0
957 09:27:51.490406 1, 0xFFFF, sum = 0
958 09:27:51.493381 2, 0xFFFF, sum = 0
959 09:27:51.493463 3, 0xFFFF, sum = 0
960 09:27:51.496808 4, 0xFFFF, sum = 0
961 09:27:51.496891 5, 0xFFFF, sum = 0
962 09:27:51.501033 6, 0xFFFF, sum = 0
963 09:27:51.501116 7, 0xFFFF, sum = 0
964 09:27:51.503704 8, 0xFFFF, sum = 0
965 09:27:51.503829 9, 0x0, sum = 1
966 09:27:51.508018 10, 0x0, sum = 2
967 09:27:51.508103 11, 0x0, sum = 3
968 09:27:51.510827 12, 0x0, sum = 4
969 09:27:51.510911 best_step = 10
970 09:27:51.510975
971 09:27:51.511069 ==
972 09:27:51.514780 Dram Type= 6, Freq= 0, CH_0, rank 0
973 09:27:51.518527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 09:27:51.518636 ==
975 09:27:51.521961 RX Vref Scan: 1
976 09:27:51.522043
977 09:27:51.522111 Set Vref Range= 32 -> 127
978 09:27:51.522173
979 09:27:51.525728 RX Vref 32 -> 127, step: 1
980 09:27:51.525837
981 09:27:51.528657 RX Delay -111 -> 252, step: 8
982 09:27:51.528740
983 09:27:51.532081 Set Vref, RX VrefLevel [Byte0]: 32
984 09:27:51.535596 [Byte1]: 32
985 09:27:51.535704
986 09:27:51.539067 Set Vref, RX VrefLevel [Byte0]: 33
987 09:27:51.542503 [Byte1]: 33
988 09:27:51.545205
989 09:27:51.545285 Set Vref, RX VrefLevel [Byte0]: 34
990 09:27:51.549009 [Byte1]: 34
991 09:27:51.553295
992 09:27:51.553387 Set Vref, RX VrefLevel [Byte0]: 35
993 09:27:51.556324 [Byte1]: 35
994 09:27:51.560674
995 09:27:51.560756 Set Vref, RX VrefLevel [Byte0]: 36
996 09:27:51.564912 [Byte1]: 36
997 09:27:51.569073
998 09:27:51.569156 Set Vref, RX VrefLevel [Byte0]: 37
999 09:27:51.571506 [Byte1]: 37
1000 09:27:51.575725
1001 09:27:51.575821 Set Vref, RX VrefLevel [Byte0]: 38
1002 09:27:51.579800 [Byte1]: 38
1003 09:27:51.583685
1004 09:27:51.583818 Set Vref, RX VrefLevel [Byte0]: 39
1005 09:27:51.587248 [Byte1]: 39
1006 09:27:51.591462
1007 09:27:51.591562 Set Vref, RX VrefLevel [Byte0]: 40
1008 09:27:51.594359 [Byte1]: 40
1009 09:27:51.598999
1010 09:27:51.599089 Set Vref, RX VrefLevel [Byte0]: 41
1011 09:27:51.602265 [Byte1]: 41
1012 09:27:51.606596
1013 09:27:51.606761 Set Vref, RX VrefLevel [Byte0]: 42
1014 09:27:51.609851 [Byte1]: 42
1015 09:27:51.614901
1016 09:27:51.615057 Set Vref, RX VrefLevel [Byte0]: 43
1017 09:27:51.618111 [Byte1]: 43
1018 09:27:51.622406
1019 09:27:51.622569 Set Vref, RX VrefLevel [Byte0]: 44
1020 09:27:51.625582 [Byte1]: 44
1021 09:27:51.629568
1022 09:27:51.629748 Set Vref, RX VrefLevel [Byte0]: 45
1023 09:27:51.633224 [Byte1]: 45
1024 09:27:51.637405
1025 09:27:51.637570 Set Vref, RX VrefLevel [Byte0]: 46
1026 09:27:51.640864 [Byte1]: 46
1027 09:27:51.645184
1028 09:27:51.645418 Set Vref, RX VrefLevel [Byte0]: 47
1029 09:27:51.648138 [Byte1]: 47
1030 09:27:51.652609
1031 09:27:51.652842 Set Vref, RX VrefLevel [Byte0]: 48
1032 09:27:51.655838 [Byte1]: 48
1033 09:27:51.660290
1034 09:27:51.663572 Set Vref, RX VrefLevel [Byte0]: 49
1035 09:27:51.666729 [Byte1]: 49
1036 09:27:51.666982
1037 09:27:51.670750 Set Vref, RX VrefLevel [Byte0]: 50
1038 09:27:51.673729 [Byte1]: 50
1039 09:27:51.674036
1040 09:27:51.676851 Set Vref, RX VrefLevel [Byte0]: 51
1041 09:27:51.680056 [Byte1]: 51
1042 09:27:51.683797
1043 09:27:51.684308 Set Vref, RX VrefLevel [Byte0]: 52
1044 09:27:51.687600 [Byte1]: 52
1045 09:27:51.691561
1046 09:27:51.692139 Set Vref, RX VrefLevel [Byte0]: 53
1047 09:27:51.694618 [Byte1]: 53
1048 09:27:51.699098
1049 09:27:51.699627 Set Vref, RX VrefLevel [Byte0]: 54
1050 09:27:51.702337 [Byte1]: 54
1051 09:27:51.706988
1052 09:27:51.707516 Set Vref, RX VrefLevel [Byte0]: 55
1053 09:27:51.709818 [Byte1]: 55
1054 09:27:51.714396
1055 09:27:51.714922 Set Vref, RX VrefLevel [Byte0]: 56
1056 09:27:51.717483 [Byte1]: 56
1057 09:27:51.722022
1058 09:27:51.722547 Set Vref, RX VrefLevel [Byte0]: 57
1059 09:27:51.725082 [Byte1]: 57
1060 09:27:51.729542
1061 09:27:51.729967 Set Vref, RX VrefLevel [Byte0]: 58
1062 09:27:51.732465 [Byte1]: 58
1063 09:27:51.737756
1064 09:27:51.738278 Set Vref, RX VrefLevel [Byte0]: 59
1065 09:27:51.740287 [Byte1]: 59
1066 09:27:51.745267
1067 09:27:51.745787 Set Vref, RX VrefLevel [Byte0]: 60
1068 09:27:51.747933 [Byte1]: 60
1069 09:27:51.752542
1070 09:27:51.753064 Set Vref, RX VrefLevel [Byte0]: 61
1071 09:27:51.755470 [Byte1]: 61
1072 09:27:51.760728
1073 09:27:51.761273 Set Vref, RX VrefLevel [Byte0]: 62
1074 09:27:51.763964 [Byte1]: 62
1075 09:27:51.767984
1076 09:27:51.768412 Set Vref, RX VrefLevel [Byte0]: 63
1077 09:27:51.772512 [Byte1]: 63
1078 09:27:51.776018
1079 09:27:51.776638 Set Vref, RX VrefLevel [Byte0]: 64
1080 09:27:51.779460 [Byte1]: 64
1081 09:27:51.782734
1082 09:27:51.783143 Set Vref, RX VrefLevel [Byte0]: 65
1083 09:27:51.786234 [Byte1]: 65
1084 09:27:51.790393
1085 09:27:51.790805 Set Vref, RX VrefLevel [Byte0]: 66
1086 09:27:51.794006 [Byte1]: 66
1087 09:27:51.798767
1088 09:27:51.799355 Set Vref, RX VrefLevel [Byte0]: 67
1089 09:27:51.801961 [Byte1]: 67
1090 09:27:51.805818
1091 09:27:51.806226 Set Vref, RX VrefLevel [Byte0]: 68
1092 09:27:51.809255 [Byte1]: 68
1093 09:27:51.813315
1094 09:27:51.813724 Set Vref, RX VrefLevel [Byte0]: 69
1095 09:27:51.817022 [Byte1]: 69
1096 09:27:51.821025
1097 09:27:51.824074 Set Vref, RX VrefLevel [Byte0]: 70
1098 09:27:51.827549 [Byte1]: 70
1099 09:27:51.827994
1100 09:27:51.831096 Set Vref, RX VrefLevel [Byte0]: 71
1101 09:27:51.833930 [Byte1]: 71
1102 09:27:51.834341
1103 09:27:51.837199 Set Vref, RX VrefLevel [Byte0]: 72
1104 09:27:51.840771 [Byte1]: 72
1105 09:27:51.841182
1106 09:27:51.844316 Set Vref, RX VrefLevel [Byte0]: 73
1107 09:27:51.847483 [Byte1]: 73
1108 09:27:51.851923
1109 09:27:51.852434 Set Vref, RX VrefLevel [Byte0]: 74
1110 09:27:51.854815 [Byte1]: 74
1111 09:27:51.859172
1112 09:27:51.859696 Set Vref, RX VrefLevel [Byte0]: 75
1113 09:27:51.863198 [Byte1]: 75
1114 09:27:51.867140
1115 09:27:51.867663 Set Vref, RX VrefLevel [Byte0]: 76
1116 09:27:51.870529 [Byte1]: 76
1117 09:27:51.874933
1118 09:27:51.875370 Set Vref, RX VrefLevel [Byte0]: 77
1119 09:27:51.878166 [Byte1]: 77
1120 09:27:51.882572
1121 09:27:51.885503 Set Vref, RX VrefLevel [Byte0]: 78
1122 09:27:51.885966 [Byte1]: 78
1123 09:27:51.890170
1124 09:27:51.890597 Set Vref, RX VrefLevel [Byte0]: 79
1125 09:27:51.893701 [Byte1]: 79
1126 09:27:51.897408
1127 09:27:51.897931 Set Vref, RX VrefLevel [Byte0]: 80
1128 09:27:51.900948 [Byte1]: 80
1129 09:27:51.905196
1130 09:27:51.905627 Set Vref, RX VrefLevel [Byte0]: 81
1131 09:27:51.908673 [Byte1]: 81
1132 09:27:51.913241
1133 09:27:51.913759 Set Vref, RX VrefLevel [Byte0]: 82
1134 09:27:51.916519 [Byte1]: 82
1135 09:27:51.920601
1136 09:27:51.921120 Final RX Vref Byte 0 = 62 to rank0
1137 09:27:51.923786 Final RX Vref Byte 1 = 60 to rank0
1138 09:27:51.927061 Final RX Vref Byte 0 = 62 to rank1
1139 09:27:51.930396 Final RX Vref Byte 1 = 60 to rank1==
1140 09:27:51.933709 Dram Type= 6, Freq= 0, CH_0, rank 0
1141 09:27:51.940635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 09:27:51.941136 ==
1143 09:27:51.941467 DQS Delay:
1144 09:27:51.941773 DQS0 = 0, DQS1 = 0
1145 09:27:51.944559 DQM Delay:
1146 09:27:51.944967 DQM0 = 87, DQM1 = 76
1147 09:27:51.947761 DQ Delay:
1148 09:27:51.951192 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1149 09:27:51.951718 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1150 09:27:51.954000 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =72
1151 09:27:51.957123 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1152 09:27:51.960534
1153 09:27:51.960976
1154 09:27:51.967384 [DQSOSCAuto] RK0, (LSB)MR18= 0x492b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
1155 09:27:51.970593 CH0 RK0: MR19=606, MR18=492B
1156 09:27:51.977479 CH0_RK0: MR19=0x606, MR18=0x492B, DQSOSC=391, MR23=63, INC=96, DEC=64
1157 09:27:51.977994
1158 09:27:51.980457 ----->DramcWriteLeveling(PI) begin...
1159 09:27:51.980875 ==
1160 09:27:51.984176 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 09:27:51.987274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1162 09:27:51.987836 ==
1163 09:27:51.990605 Write leveling (Byte 0): 32 => 32
1164 09:27:51.993848 Write leveling (Byte 1): 30 => 30
1165 09:27:52.037638 DramcWriteLeveling(PI) end<-----
1166 09:27:52.038340
1167 09:27:52.038834 ==
1168 09:27:52.039189 Dram Type= 6, Freq= 0, CH_0, rank 1
1169 09:27:52.039892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1170 09:27:52.040228 ==
1171 09:27:52.040529 [Gating] SW mode calibration
1172 09:27:52.040818 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1173 09:27:52.041109 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1174 09:27:52.041396 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1175 09:27:52.041676 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1176 09:27:52.041955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 09:27:52.042289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1178 09:27:52.065745 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:27:52.066665 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:27:52.067052 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:27:52.067370 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:27:52.067778 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:27:52.068113 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:27:52.071193 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:27:52.073919 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:27:52.077146 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:27:52.080018 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:27:52.086572 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:27:52.090282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:27:52.093266 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 09:27:52.099923 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1192 09:27:52.103195 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1193 09:27:52.106906 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:27:52.113011 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:27:52.116257 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:27:52.119946 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 09:27:52.123026 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:27:52.129932 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:27:52.133612 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:27:52.136416 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (1 1) (0 0)
1201 09:27:52.143222 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1202 09:27:52.146478 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 09:27:52.149835 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 09:27:52.156535 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 09:27:52.159544 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 09:27:52.163427 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 09:27:52.170748 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1208 09:27:52.174950 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 1) (0 1)
1209 09:27:52.178487 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 09:27:52.181815 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 09:27:52.185532 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 09:27:52.192470 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 09:27:52.196052 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 09:27:52.199961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 09:27:52.203375 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1216 09:27:52.207253 0 11 8 | B1->B0 | 3131 4040 | 1 0 | (0 0) (1 1)
1217 09:27:52.214288 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1218 09:27:52.218097 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 09:27:52.221255 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 09:27:52.224701 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 09:27:52.232061 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 09:27:52.235618 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 09:27:52.239700 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 09:27:52.242573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1225 09:27:52.246561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1226 09:27:52.253670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 09:27:52.257340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 09:27:52.261017 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 09:27:52.264709 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 09:27:52.268541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 09:27:52.275802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 09:27:52.279794 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 09:27:52.283098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 09:27:52.286849 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 09:27:52.290625 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 09:27:52.298011 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 09:27:52.301657 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 09:27:52.305402 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 09:27:52.309317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 09:27:52.312583 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1241 09:27:52.315989 Total UI for P1: 0, mck2ui 16
1242 09:27:52.320159 best dqsien dly found for B0: ( 0, 14, 6)
1243 09:27:52.324075 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1244 09:27:52.327524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 09:27:52.330976 Total UI for P1: 0, mck2ui 16
1246 09:27:52.334989 best dqsien dly found for B1: ( 0, 14, 10)
1247 09:27:52.338959 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1248 09:27:52.342410 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1249 09:27:52.342973
1250 09:27:52.346015 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1251 09:27:52.350083 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1252 09:27:52.353558 [Gating] SW calibration Done
1253 09:27:52.354102 ==
1254 09:27:52.356892 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 09:27:52.361001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 09:27:52.361439 ==
1257 09:27:52.364274 RX Vref Scan: 0
1258 09:27:52.364700
1259 09:27:52.365153 RX Vref 0 -> 0, step: 1
1260 09:27:52.365559
1261 09:27:52.368250 RX Delay -130 -> 252, step: 16
1262 09:27:52.371551 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1263 09:27:52.375610 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1264 09:27:52.378837 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1265 09:27:52.383147 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1266 09:27:52.386267 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1267 09:27:52.390094 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1268 09:27:52.397276 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1269 09:27:52.400601 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1270 09:27:52.404343 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1271 09:27:52.407685 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1272 09:27:52.411422 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1273 09:27:52.415442 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1274 09:27:52.418613 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1275 09:27:52.421905 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1276 09:27:52.429168 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1277 09:27:52.433386 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1278 09:27:52.433905 ==
1279 09:27:52.436488 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 09:27:52.439958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 09:27:52.440393 ==
1282 09:27:52.440729 DQS Delay:
1283 09:27:52.443878 DQS0 = 0, DQS1 = 0
1284 09:27:52.444409 DQM Delay:
1285 09:27:52.446698 DQM0 = 87, DQM1 = 77
1286 09:27:52.447170 DQ Delay:
1287 09:27:52.450969 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1288 09:27:52.454388 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1289 09:27:52.458099 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1290 09:27:52.461758 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1291 09:27:52.462301
1292 09:27:52.462642
1293 09:27:52.462954 ==
1294 09:27:52.465491 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 09:27:52.468962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 09:27:52.469504 ==
1297 09:27:52.469846
1298 09:27:52.470153
1299 09:27:52.470448 TX Vref Scan disable
1300 09:27:52.472324 == TX Byte 0 ==
1301 09:27:52.476319 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 09:27:52.479933 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 09:27:52.483815 == TX Byte 1 ==
1304 09:27:52.487605 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1305 09:27:52.490845 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1306 09:27:52.491139 ==
1307 09:27:52.494480 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 09:27:52.497855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 09:27:52.498078 ==
1310 09:27:52.511448 TX Vref=22, minBit 8, minWin=27, winSum=446
1311 09:27:52.514815 TX Vref=24, minBit 9, minWin=27, winSum=447
1312 09:27:52.518576 TX Vref=26, minBit 9, minWin=27, winSum=448
1313 09:27:52.521566 TX Vref=28, minBit 8, minWin=27, winSum=448
1314 09:27:52.524704 TX Vref=30, minBit 8, minWin=27, winSum=446
1315 09:27:52.531202 TX Vref=32, minBit 9, minWin=27, winSum=446
1316 09:27:52.534490 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1317 09:27:52.534711
1318 09:27:52.537914 Final TX Range 1 Vref 26
1319 09:27:52.538135
1320 09:27:52.538308 ==
1321 09:27:52.540954 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 09:27:52.544313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 09:27:52.544535 ==
1324 09:27:52.548442
1325 09:27:52.548751
1326 09:27:52.548931 TX Vref Scan disable
1327 09:27:52.552024 == TX Byte 0 ==
1328 09:27:52.555442 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1329 09:27:52.558737 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1330 09:27:52.561857 == TX Byte 1 ==
1331 09:27:52.565020 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1332 09:27:52.571587 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1333 09:27:52.572164
1334 09:27:52.572596 [DATLAT]
1335 09:27:52.572878 Freq=800, CH0 RK1
1336 09:27:52.573135
1337 09:27:52.574560 DATLAT Default: 0xa
1338 09:27:52.574904 0, 0xFFFF, sum = 0
1339 09:27:52.578308 1, 0xFFFF, sum = 0
1340 09:27:52.578769 2, 0xFFFF, sum = 0
1341 09:27:52.581489 3, 0xFFFF, sum = 0
1342 09:27:52.584868 4, 0xFFFF, sum = 0
1343 09:27:52.585321 5, 0xFFFF, sum = 0
1344 09:27:52.588389 6, 0xFFFF, sum = 0
1345 09:27:52.588845 7, 0xFFFF, sum = 0
1346 09:27:52.591621 8, 0xFFFF, sum = 0
1347 09:27:52.592136 9, 0x0, sum = 1
1348 09:27:52.594923 10, 0x0, sum = 2
1349 09:27:52.595373 11, 0x0, sum = 3
1350 09:27:52.595654 12, 0x0, sum = 4
1351 09:27:52.597799 best_step = 10
1352 09:27:52.598143
1353 09:27:52.598416 ==
1354 09:27:52.601136 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 09:27:52.604496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 09:27:52.604954 ==
1357 09:27:52.608002 RX Vref Scan: 0
1358 09:27:52.608349
1359 09:27:52.611321 RX Vref 0 -> 0, step: 1
1360 09:27:52.611832
1361 09:27:52.612152 RX Delay -111 -> 252, step: 8
1362 09:27:52.618486 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1363 09:27:52.621521 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1364 09:27:52.625335 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1365 09:27:52.628096 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1366 09:27:52.631621 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1367 09:27:52.638413 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1368 09:27:52.641738 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1369 09:27:52.644675 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1370 09:27:52.648089 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1371 09:27:52.651537 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1372 09:27:52.658234 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1373 09:27:52.661341 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1374 09:27:52.664831 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1375 09:27:52.668152 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1376 09:27:52.675003 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1377 09:27:52.678345 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1378 09:27:52.678793 ==
1379 09:27:52.681591 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 09:27:52.684685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 09:27:52.685140 ==
1382 09:27:52.688613 DQS Delay:
1383 09:27:52.689060 DQS0 = 0, DQS1 = 0
1384 09:27:52.689341 DQM Delay:
1385 09:27:52.692046 DQM0 = 86, DQM1 = 76
1386 09:27:52.692492 DQ Delay:
1387 09:27:52.694280 DQ0 =88, DQ1 =92, DQ2 =80, DQ3 =84
1388 09:27:52.697776 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1389 09:27:52.700771 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1390 09:27:52.704316 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1391 09:27:52.704767
1392 09:27:52.705046
1393 09:27:52.715094 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f06, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1394 09:27:52.715545 CH0 RK1: MR19=606, MR18=3F06
1395 09:27:52.721130 CH0_RK1: MR19=0x606, MR18=0x3F06, DQSOSC=393, MR23=63, INC=95, DEC=63
1396 09:27:52.724232 [RxdqsGatingPostProcess] freq 800
1397 09:27:52.731234 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1398 09:27:52.733850 Pre-setting of DQS Precalculation
1399 09:27:52.737642 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1400 09:27:52.738092 ==
1401 09:27:52.740970 Dram Type= 6, Freq= 0, CH_1, rank 0
1402 09:27:52.747719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 09:27:52.748227 ==
1404 09:27:52.750818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 09:27:52.757122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 09:27:52.766845 [CA 0] Center 36 (6~67) winsize 62
1407 09:27:52.770280 [CA 1] Center 36 (6~67) winsize 62
1408 09:27:52.773650 [CA 2] Center 34 (4~65) winsize 62
1409 09:27:52.776444 [CA 3] Center 34 (4~65) winsize 62
1410 09:27:52.779667 [CA 4] Center 34 (4~65) winsize 62
1411 09:27:52.783801 [CA 5] Center 34 (3~65) winsize 63
1412 09:27:52.784256
1413 09:27:52.786860 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1414 09:27:52.787323
1415 09:27:52.790130 [CATrainingPosCal] consider 1 rank data
1416 09:27:52.793492 u2DelayCellTimex100 = 270/100 ps
1417 09:27:52.796721 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 09:27:52.803153 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 09:27:52.806211 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 09:27:52.809863 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 09:27:52.813243 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 09:27:52.816906 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1423 09:27:52.817334
1424 09:27:52.820239 CA PerBit enable=1, Macro0, CA PI delay=34
1425 09:27:52.820766
1426 09:27:52.823560 [CBTSetCACLKResult] CA Dly = 34
1427 09:27:52.824130 CS Dly: 5 (0~36)
1428 09:27:52.826248 ==
1429 09:27:52.829557 Dram Type= 6, Freq= 0, CH_1, rank 1
1430 09:27:52.832987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 09:27:52.833510 ==
1432 09:27:52.836518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1433 09:27:52.842891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1434 09:27:52.852631 [CA 0] Center 36 (6~67) winsize 62
1435 09:27:52.856252 [CA 1] Center 37 (6~68) winsize 63
1436 09:27:52.859675 [CA 2] Center 34 (4~65) winsize 62
1437 09:27:52.862561 [CA 3] Center 34 (3~65) winsize 63
1438 09:27:52.866156 [CA 4] Center 34 (4~65) winsize 62
1439 09:27:52.869572 [CA 5] Center 34 (4~64) winsize 61
1440 09:27:52.870098
1441 09:27:52.872655 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1442 09:27:52.873144
1443 09:27:52.875965 [CATrainingPosCal] consider 2 rank data
1444 09:27:52.879710 u2DelayCellTimex100 = 270/100 ps
1445 09:27:52.882850 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1446 09:27:52.885979 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1447 09:27:52.892563 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 09:27:52.895651 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 09:27:52.899124 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1450 09:27:52.902315 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1451 09:27:52.902741
1452 09:27:52.905475 CA PerBit enable=1, Macro0, CA PI delay=34
1453 09:27:52.905902
1454 09:27:52.909204 [CBTSetCACLKResult] CA Dly = 34
1455 09:27:52.909732 CS Dly: 6 (0~38)
1456 09:27:52.912627
1457 09:27:52.915827 ----->DramcWriteLeveling(PI) begin...
1458 09:27:52.916263 ==
1459 09:27:52.918788 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 09:27:52.922248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 09:27:52.922667 ==
1462 09:27:52.925317 Write leveling (Byte 0): 26 => 26
1463 09:27:52.928839 Write leveling (Byte 1): 27 => 27
1464 09:27:52.932272 DramcWriteLeveling(PI) end<-----
1465 09:27:52.932697
1466 09:27:52.933133 ==
1467 09:27:52.935897 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 09:27:52.938798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 09:27:52.939220 ==
1470 09:27:52.942004 [Gating] SW mode calibration
1471 09:27:52.948750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1472 09:27:52.955287 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1473 09:27:52.958763 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1474 09:27:52.961637 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:27:52.968186 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:27:52.971685 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:27:52.975310 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:27:52.981796 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:27:52.984956 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:27:52.988706 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:27:52.992325 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 09:27:52.998358 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:27:53.001576 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:27:53.005000 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:27:53.011859 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:27:53.015046 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:27:53.018414 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 09:27:53.024767 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:27:53.028342 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1490 09:27:53.031463 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1491 09:27:53.038521 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1492 09:27:53.041556 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:27:53.044644 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:27:53.051891 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:27:53.054616 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:27:53.058165 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:27:53.064420 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:27:53.067620 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:27:53.071194 0 9 8 | B1->B0 | 3030 3333 | 0 1 | (0 0) (1 1)
1500 09:27:53.078127 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 09:27:53.081259 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 09:27:53.084662 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 09:27:53.090881 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 09:27:53.094251 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 09:27:53.097710 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 09:27:53.104256 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 0)
1507 09:27:53.107238 0 10 8 | B1->B0 | 2d2d 2929 | 1 0 | (1 0) (0 0)
1508 09:27:53.111356 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 09:27:53.117853 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 09:27:53.121326 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 09:27:53.124221 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 09:27:53.130799 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 09:27:53.134034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 09:27:53.137485 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1515 09:27:53.144852 0 11 8 | B1->B0 | 3c3c 3e3e | 1 0 | (0 0) (0 0)
1516 09:27:53.147464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 09:27:53.150551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 09:27:53.157871 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 09:27:53.161104 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 09:27:53.164533 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 09:27:53.171545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1522 09:27:53.174603 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1523 09:27:53.177418 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 09:27:53.180572 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 09:27:53.187335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 09:27:53.190891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 09:27:53.194198 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 09:27:53.200489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 09:27:53.204394 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 09:27:53.207321 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 09:27:53.214264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 09:27:53.217046 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 09:27:53.220305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 09:27:53.226884 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 09:27:53.230103 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 09:27:53.233805 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 09:27:53.240072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 09:27:53.243318 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1539 09:27:53.246982 Total UI for P1: 0, mck2ui 16
1540 09:27:53.250812 best dqsien dly found for B0: ( 0, 14, 2)
1541 09:27:53.253676 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1542 09:27:53.260192 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 09:27:53.260280 Total UI for P1: 0, mck2ui 16
1544 09:27:53.267085 best dqsien dly found for B1: ( 0, 14, 8)
1545 09:27:53.270220 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1546 09:27:53.273632 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1547 09:27:53.273723
1548 09:27:53.276885 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1549 09:27:53.280124 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1550 09:27:53.283348 [Gating] SW calibration Done
1551 09:27:53.283437 ==
1552 09:27:53.286394 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 09:27:53.289992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 09:27:53.290090 ==
1555 09:27:53.293353 RX Vref Scan: 0
1556 09:27:53.293449
1557 09:27:53.293526 RX Vref 0 -> 0, step: 1
1558 09:27:53.293597
1559 09:27:53.296872 RX Delay -130 -> 252, step: 16
1560 09:27:53.299787 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1561 09:27:53.306528 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1562 09:27:53.309771 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1563 09:27:53.312969 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1564 09:27:53.316591 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1565 09:27:53.322894 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1566 09:27:53.326275 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1567 09:27:53.329526 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1568 09:27:53.332929 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1569 09:27:53.336277 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1570 09:27:53.343634 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1571 09:27:53.346586 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1572 09:27:53.349735 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1573 09:27:53.353369 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1574 09:27:53.357052 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1575 09:27:53.363502 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1576 09:27:53.363799 ==
1577 09:27:53.367387 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 09:27:53.370195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 09:27:53.370544 ==
1580 09:27:53.370760 DQS Delay:
1581 09:27:53.373415 DQS0 = 0, DQS1 = 0
1582 09:27:53.373773 DQM Delay:
1583 09:27:53.377178 DQM0 = 89, DQM1 = 79
1584 09:27:53.377620 DQ Delay:
1585 09:27:53.380339 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1586 09:27:53.383840 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1587 09:27:53.386593 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1588 09:27:53.390054 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1589 09:27:53.390573
1590 09:27:53.390906
1591 09:27:53.391210 ==
1592 09:27:53.393650 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 09:27:53.396805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 09:27:53.397329 ==
1595 09:27:53.399775
1596 09:27:53.400236
1597 09:27:53.400567 TX Vref Scan disable
1598 09:27:53.403181 == TX Byte 0 ==
1599 09:27:53.406380 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1600 09:27:53.410249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1601 09:27:53.413173 == TX Byte 1 ==
1602 09:27:53.416557 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 09:27:53.420107 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 09:27:53.420631 ==
1605 09:27:53.423516 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 09:27:53.429606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 09:27:53.430345 ==
1608 09:27:53.441819 TX Vref=22, minBit 0, minWin=27, winSum=444
1609 09:27:53.445838 TX Vref=24, minBit 6, minWin=27, winSum=443
1610 09:27:53.448708 TX Vref=26, minBit 1, minWin=27, winSum=447
1611 09:27:53.451596 TX Vref=28, minBit 10, minWin=27, winSum=450
1612 09:27:53.455529 TX Vref=30, minBit 8, minWin=27, winSum=445
1613 09:27:53.461650 TX Vref=32, minBit 8, minWin=27, winSum=446
1614 09:27:53.464506 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 28
1615 09:27:53.464960
1616 09:27:53.468662 Final TX Range 1 Vref 28
1617 09:27:53.469071
1618 09:27:53.469469 ==
1619 09:27:53.470951 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 09:27:53.477637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 09:27:53.478135 ==
1622 09:27:53.478465
1623 09:27:53.478771
1624 09:27:53.479063 TX Vref Scan disable
1625 09:27:53.481830 == TX Byte 0 ==
1626 09:27:53.485200 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1627 09:27:53.488211 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1628 09:27:53.491882 == TX Byte 1 ==
1629 09:27:53.494765 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1630 09:27:53.501653 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1631 09:27:53.502167
1632 09:27:53.502496 [DATLAT]
1633 09:27:53.502803 Freq=800, CH1 RK0
1634 09:27:53.503097
1635 09:27:53.504705 DATLAT Default: 0xa
1636 09:27:53.505116 0, 0xFFFF, sum = 0
1637 09:27:53.508267 1, 0xFFFF, sum = 0
1638 09:27:53.508780 2, 0xFFFF, sum = 0
1639 09:27:53.511714 3, 0xFFFF, sum = 0
1640 09:27:53.515040 4, 0xFFFF, sum = 0
1641 09:27:53.515549 5, 0xFFFF, sum = 0
1642 09:27:53.518766 6, 0xFFFF, sum = 0
1643 09:27:53.519273 7, 0xFFFF, sum = 0
1644 09:27:53.521844 8, 0xFFFF, sum = 0
1645 09:27:53.522353 9, 0x0, sum = 1
1646 09:27:53.525291 10, 0x0, sum = 2
1647 09:27:53.525806 11, 0x0, sum = 3
1648 09:27:53.526143 12, 0x0, sum = 4
1649 09:27:53.528176 best_step = 10
1650 09:27:53.528683
1651 09:27:53.529014 ==
1652 09:27:53.531286 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 09:27:53.535026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 09:27:53.535533 ==
1655 09:27:53.538078 RX Vref Scan: 1
1656 09:27:53.538489
1657 09:27:53.541561 Set Vref Range= 32 -> 127
1658 09:27:53.542066
1659 09:27:53.542399 RX Vref 32 -> 127, step: 1
1660 09:27:53.542708
1661 09:27:53.545162 RX Delay -95 -> 252, step: 8
1662 09:27:53.545668
1663 09:27:53.548225 Set Vref, RX VrefLevel [Byte0]: 32
1664 09:27:53.551209 [Byte1]: 32
1665 09:27:53.551619
1666 09:27:53.555069 Set Vref, RX VrefLevel [Byte0]: 33
1667 09:27:53.557969 [Byte1]: 33
1668 09:27:53.562482
1669 09:27:53.563000 Set Vref, RX VrefLevel [Byte0]: 34
1670 09:27:53.565571 [Byte1]: 34
1671 09:27:53.569762
1672 09:27:53.570279 Set Vref, RX VrefLevel [Byte0]: 35
1673 09:27:53.573103 [Byte1]: 35
1674 09:27:53.577561
1675 09:27:53.578064 Set Vref, RX VrefLevel [Byte0]: 36
1676 09:27:53.581013 [Byte1]: 36
1677 09:27:53.584920
1678 09:27:53.585426 Set Vref, RX VrefLevel [Byte0]: 37
1679 09:27:53.587959 [Byte1]: 37
1680 09:27:53.592333
1681 09:27:53.592748 Set Vref, RX VrefLevel [Byte0]: 38
1682 09:27:53.595548 [Byte1]: 38
1683 09:27:53.600419
1684 09:27:53.600831 Set Vref, RX VrefLevel [Byte0]: 39
1685 09:27:53.604281 [Byte1]: 39
1686 09:27:53.607587
1687 09:27:53.608044 Set Vref, RX VrefLevel [Byte0]: 40
1688 09:27:53.610871 [Byte1]: 40
1689 09:27:53.615119
1690 09:27:53.615534 Set Vref, RX VrefLevel [Byte0]: 41
1691 09:27:53.618658 [Byte1]: 41
1692 09:27:53.623099
1693 09:27:53.623601 Set Vref, RX VrefLevel [Byte0]: 42
1694 09:27:53.626138 [Byte1]: 42
1695 09:27:53.630688
1696 09:27:53.631100 Set Vref, RX VrefLevel [Byte0]: 43
1697 09:27:53.633691 [Byte1]: 43
1698 09:27:53.637744
1699 09:27:53.638164 Set Vref, RX VrefLevel [Byte0]: 44
1700 09:27:53.641493 [Byte1]: 44
1701 09:27:53.646061
1702 09:27:53.646594 Set Vref, RX VrefLevel [Byte0]: 45
1703 09:27:53.648829 [Byte1]: 45
1704 09:27:53.653632
1705 09:27:53.654150 Set Vref, RX VrefLevel [Byte0]: 46
1706 09:27:53.656251 [Byte1]: 46
1707 09:27:53.660714
1708 09:27:53.661289 Set Vref, RX VrefLevel [Byte0]: 47
1709 09:27:53.664091 [Byte1]: 47
1710 09:27:53.668416
1711 09:27:53.668939 Set Vref, RX VrefLevel [Byte0]: 48
1712 09:27:53.672072 [Byte1]: 48
1713 09:27:53.676217
1714 09:27:53.676778 Set Vref, RX VrefLevel [Byte0]: 49
1715 09:27:53.679505 [Byte1]: 49
1716 09:27:53.683665
1717 09:27:53.684287 Set Vref, RX VrefLevel [Byte0]: 50
1718 09:27:53.686623 [Byte1]: 50
1719 09:27:53.691624
1720 09:27:53.692236 Set Vref, RX VrefLevel [Byte0]: 51
1721 09:27:53.694662 [Byte1]: 51
1722 09:27:53.698679
1723 09:27:53.699236 Set Vref, RX VrefLevel [Byte0]: 52
1724 09:27:53.702067 [Byte1]: 52
1725 09:27:53.706996
1726 09:27:53.707511 Set Vref, RX VrefLevel [Byte0]: 53
1727 09:27:53.709973 [Byte1]: 53
1728 09:27:53.714202
1729 09:27:53.714710 Set Vref, RX VrefLevel [Byte0]: 54
1730 09:27:53.717431 [Byte1]: 54
1731 09:27:53.721657
1732 09:27:53.722067 Set Vref, RX VrefLevel [Byte0]: 55
1733 09:27:53.724977 [Byte1]: 55
1734 09:27:53.730031
1735 09:27:53.730561 Set Vref, RX VrefLevel [Byte0]: 56
1736 09:27:53.732494 [Byte1]: 56
1737 09:27:53.736701
1738 09:27:53.737227 Set Vref, RX VrefLevel [Byte0]: 57
1739 09:27:53.740237 [Byte1]: 57
1740 09:27:53.744256
1741 09:27:53.744774 Set Vref, RX VrefLevel [Byte0]: 58
1742 09:27:53.747905 [Byte1]: 58
1743 09:27:53.752616
1744 09:27:53.753182 Set Vref, RX VrefLevel [Byte0]: 59
1745 09:27:53.758914 [Byte1]: 59
1746 09:27:53.759477
1747 09:27:53.761744 Set Vref, RX VrefLevel [Byte0]: 60
1748 09:27:53.765370 [Byte1]: 60
1749 09:27:53.765931
1750 09:27:53.768933 Set Vref, RX VrefLevel [Byte0]: 61
1751 09:27:53.771651 [Byte1]: 61
1752 09:27:53.772157
1753 09:27:53.775199 Set Vref, RX VrefLevel [Byte0]: 62
1754 09:27:53.778403 [Byte1]: 62
1755 09:27:53.782286
1756 09:27:53.782847 Set Vref, RX VrefLevel [Byte0]: 63
1757 09:27:53.785698 [Byte1]: 63
1758 09:27:53.789993
1759 09:27:53.790576 Set Vref, RX VrefLevel [Byte0]: 64
1760 09:27:53.793337 [Byte1]: 64
1761 09:27:53.797622
1762 09:27:53.798064 Set Vref, RX VrefLevel [Byte0]: 65
1763 09:27:53.800899 [Byte1]: 65
1764 09:27:53.804999
1765 09:27:53.805542 Set Vref, RX VrefLevel [Byte0]: 66
1766 09:27:53.808243 [Byte1]: 66
1767 09:27:53.813230
1768 09:27:53.813766 Set Vref, RX VrefLevel [Byte0]: 67
1769 09:27:53.816031 [Byte1]: 67
1770 09:27:53.821169
1771 09:27:53.821692 Set Vref, RX VrefLevel [Byte0]: 68
1772 09:27:53.824293 [Byte1]: 68
1773 09:27:53.828902
1774 09:27:53.829429 Set Vref, RX VrefLevel [Byte0]: 69
1775 09:27:53.831241 [Byte1]: 69
1776 09:27:53.835489
1777 09:27:53.836070 Set Vref, RX VrefLevel [Byte0]: 70
1778 09:27:53.839019 [Byte1]: 70
1779 09:27:53.843248
1780 09:27:53.843820 Set Vref, RX VrefLevel [Byte0]: 71
1781 09:27:53.846753 [Byte1]: 71
1782 09:27:53.850936
1783 09:27:53.851454 Set Vref, RX VrefLevel [Byte0]: 72
1784 09:27:53.854346 [Byte1]: 72
1785 09:27:53.858309
1786 09:27:53.858831 Set Vref, RX VrefLevel [Byte0]: 73
1787 09:27:53.861744 [Byte1]: 73
1788 09:27:53.865924
1789 09:27:53.866444 Set Vref, RX VrefLevel [Byte0]: 74
1790 09:27:53.869295 [Byte1]: 74
1791 09:27:53.873779
1792 09:27:53.874300 Set Vref, RX VrefLevel [Byte0]: 75
1793 09:27:53.877257 [Byte1]: 75
1794 09:27:53.881574
1795 09:27:53.882095 Set Vref, RX VrefLevel [Byte0]: 76
1796 09:27:53.884779 [Byte1]: 76
1797 09:27:53.889468
1798 09:27:53.889993 Set Vref, RX VrefLevel [Byte0]: 77
1799 09:27:53.892345 [Byte1]: 77
1800 09:27:53.896360
1801 09:27:53.896889 Set Vref, RX VrefLevel [Byte0]: 78
1802 09:27:53.899937 [Byte1]: 78
1803 09:27:53.904598
1804 09:27:53.905121 Final RX Vref Byte 0 = 51 to rank0
1805 09:27:53.907452 Final RX Vref Byte 1 = 67 to rank0
1806 09:27:53.911087 Final RX Vref Byte 0 = 51 to rank1
1807 09:27:53.913970 Final RX Vref Byte 1 = 67 to rank1==
1808 09:27:53.917529 Dram Type= 6, Freq= 0, CH_1, rank 0
1809 09:27:53.923717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 09:27:53.924291 ==
1811 09:27:53.924632 DQS Delay:
1812 09:27:53.925005 DQS0 = 0, DQS1 = 0
1813 09:27:53.927447 DQM Delay:
1814 09:27:53.928118 DQM0 = 86, DQM1 = 78
1815 09:27:53.930523 DQ Delay:
1816 09:27:53.934610 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1817 09:27:53.938305 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1818 09:27:53.940838 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1819 09:27:53.944267 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1820 09:27:53.944724
1821 09:27:53.945087
1822 09:27:53.950378 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1823 09:27:53.953942 CH1 RK0: MR19=606, MR18=3622
1824 09:27:53.960423 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1825 09:27:53.960947
1826 09:27:53.963418 ----->DramcWriteLeveling(PI) begin...
1827 09:27:53.963869 ==
1828 09:27:53.967400 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 09:27:53.970620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 09:27:53.971145 ==
1831 09:27:53.973858 Write leveling (Byte 0): 29 => 29
1832 09:27:53.976705 Write leveling (Byte 1): 29 => 29
1833 09:27:53.980514 DramcWriteLeveling(PI) end<-----
1834 09:27:53.981021
1835 09:27:53.981347 ==
1836 09:27:53.983454 Dram Type= 6, Freq= 0, CH_1, rank 1
1837 09:27:53.987263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 09:27:53.987810 ==
1839 09:27:53.990835 [Gating] SW mode calibration
1840 09:27:53.997086 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1841 09:27:54.003573 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1842 09:27:54.007093 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1843 09:27:54.010428 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1844 09:27:54.017354 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1845 09:27:54.020414 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:27:54.023786 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:27:54.030246 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:27:54.033036 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:27:54.036969 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:27:54.043543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:27:54.047122 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:27:54.050395 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:27:54.057036 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:27:54.059884 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:27:54.063146 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:27:54.070024 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:27:54.073649 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:27:54.076360 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:27:54.083217 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1860 09:27:54.086366 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 09:27:54.089782 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 09:27:54.096071 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:27:54.099858 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:27:54.102830 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:27:54.109708 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:27:54.112822 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:27:54.116119 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:27:54.122783 0 9 8 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 1)
1869 09:27:54.126193 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 09:27:54.129380 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 09:27:54.136261 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 09:27:54.138825 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 09:27:54.142367 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 09:27:54.149132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 09:27:54.152788 0 10 4 | B1->B0 | 3030 3434 | 1 0 | (0 1) (0 1)
1876 09:27:54.155761 0 10 8 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
1877 09:27:54.162003 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 09:27:54.165980 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 09:27:54.169029 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:27:54.175906 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 09:27:54.179254 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 09:27:54.182326 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 09:27:54.188601 0 11 4 | B1->B0 | 2928 2525 | 1 0 | (0 0) (0 0)
1884 09:27:54.192583 0 11 8 | B1->B0 | 3c3c 3535 | 0 0 | (0 0) (1 1)
1885 09:27:54.195388 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 09:27:54.202265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 09:27:54.205198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 09:27:54.209101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 09:27:54.215641 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 09:27:54.218961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 09:27:54.222520 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1892 09:27:54.225401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1893 09:27:54.232411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 09:27:54.235255 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:27:54.239109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 09:27:54.245797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 09:27:54.248532 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 09:27:54.252193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 09:27:54.258941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 09:27:54.262019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 09:27:54.265417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 09:27:54.271828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 09:27:54.274901 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 09:27:54.278566 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 09:27:54.285489 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 09:27:54.288244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 09:27:54.292024 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1908 09:27:54.298601 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1909 09:27:54.299015 Total UI for P1: 0, mck2ui 16
1910 09:27:54.305153 best dqsien dly found for B1: ( 0, 14, 4)
1911 09:27:54.308000 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 09:27:54.311664 Total UI for P1: 0, mck2ui 16
1913 09:27:54.314914 best dqsien dly found for B0: ( 0, 14, 8)
1914 09:27:54.318383 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1915 09:27:54.321315 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1916 09:27:54.321726
1917 09:27:54.325082 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1918 09:27:54.328190 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 09:27:54.331332 [Gating] SW calibration Done
1920 09:27:54.331884 ==
1921 09:27:54.334790 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 09:27:54.338210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 09:27:54.341168 ==
1924 09:27:54.341826 RX Vref Scan: 0
1925 09:27:54.342265
1926 09:27:54.344377 RX Vref 0 -> 0, step: 1
1927 09:27:54.344805
1928 09:27:54.347668 RX Delay -130 -> 252, step: 16
1929 09:27:54.351332 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1930 09:27:54.355092 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1931 09:27:54.358317 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1932 09:27:54.361390 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1933 09:27:54.368029 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1934 09:27:54.371892 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1935 09:27:54.374504 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1936 09:27:54.377981 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1937 09:27:54.381811 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1938 09:27:54.388298 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1939 09:27:54.391299 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1940 09:27:54.395328 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1941 09:27:54.398074 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1942 09:27:54.400926 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1943 09:27:54.408221 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1944 09:27:54.411364 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1945 09:27:54.411959 ==
1946 09:27:54.414867 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 09:27:54.417860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 09:27:54.418414 ==
1949 09:27:54.420894 DQS Delay:
1950 09:27:54.421351 DQS0 = 0, DQS1 = 0
1951 09:27:54.421714 DQM Delay:
1952 09:27:54.424658 DQM0 = 87, DQM1 = 78
1953 09:27:54.425207 DQ Delay:
1954 09:27:54.428439 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =77
1955 09:27:54.431453 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1956 09:27:54.434428 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1957 09:27:54.437813 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1958 09:27:54.438369
1959 09:27:54.438732
1960 09:27:54.439068 ==
1961 09:27:54.440562 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 09:27:54.447213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 09:27:54.447666 ==
1964 09:27:54.448071
1965 09:27:54.448408
1966 09:27:54.450702 TX Vref Scan disable
1967 09:27:54.451259 == TX Byte 0 ==
1968 09:27:54.453981 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1969 09:27:54.460434 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1970 09:27:54.460972 == TX Byte 1 ==
1971 09:27:54.463814 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 09:27:54.470981 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 09:27:54.471490 ==
1974 09:27:54.474203 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 09:27:54.477648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 09:27:54.478157 ==
1977 09:27:54.490712 TX Vref=22, minBit 8, minWin=27, winSum=446
1978 09:27:54.494350 TX Vref=24, minBit 10, minWin=27, winSum=446
1979 09:27:54.497033 TX Vref=26, minBit 13, minWin=27, winSum=453
1980 09:27:54.500746 TX Vref=28, minBit 13, minWin=27, winSum=453
1981 09:27:54.503948 TX Vref=30, minBit 13, minWin=27, winSum=450
1982 09:27:54.510674 TX Vref=32, minBit 8, minWin=27, winSum=449
1983 09:27:54.514087 [TxChooseVref] Worse bit 13, Min win 27, Win sum 453, Final Vref 26
1984 09:27:54.514660
1985 09:27:54.517613 Final TX Range 1 Vref 26
1986 09:27:54.518166
1987 09:27:54.518529 ==
1988 09:27:54.520679 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 09:27:54.523881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 09:27:54.527609 ==
1991 09:27:54.528200
1992 09:27:54.528568
1993 09:27:54.528907 TX Vref Scan disable
1994 09:27:54.531163 == TX Byte 0 ==
1995 09:27:54.534784 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1996 09:27:54.537575 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1997 09:27:54.540867 == TX Byte 1 ==
1998 09:27:54.544295 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1999 09:27:54.548232 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2000 09:27:54.550792
2001 09:27:54.551245 [DATLAT]
2002 09:27:54.551604 Freq=800, CH1 RK1
2003 09:27:54.551995
2004 09:27:54.554489 DATLAT Default: 0xa
2005 09:27:54.554948 0, 0xFFFF, sum = 0
2006 09:27:54.557583 1, 0xFFFF, sum = 0
2007 09:27:54.558135 2, 0xFFFF, sum = 0
2008 09:27:54.560761 3, 0xFFFF, sum = 0
2009 09:27:54.564147 4, 0xFFFF, sum = 0
2010 09:27:54.564613 5, 0xFFFF, sum = 0
2011 09:27:54.567419 6, 0xFFFF, sum = 0
2012 09:27:54.567969 7, 0xFFFF, sum = 0
2013 09:27:54.570975 8, 0xFFFF, sum = 0
2014 09:27:54.571583 9, 0x0, sum = 1
2015 09:27:54.573903 10, 0x0, sum = 2
2016 09:27:54.574417 11, 0x0, sum = 3
2017 09:27:54.574759 12, 0x0, sum = 4
2018 09:27:54.577052 best_step = 10
2019 09:27:54.577587
2020 09:27:54.577921 ==
2021 09:27:54.581096 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 09:27:54.583981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 09:27:54.584490 ==
2024 09:27:54.587136 RX Vref Scan: 0
2025 09:27:54.587643
2026 09:27:54.590711 RX Vref 0 -> 0, step: 1
2027 09:27:54.591309
2028 09:27:54.591680 RX Delay -95 -> 252, step: 8
2029 09:27:54.597353 iDelay=217, Bit 0, Center 92 (-15 ~ 200) 216
2030 09:27:54.600536 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2031 09:27:54.604357 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2032 09:27:54.607414 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2033 09:27:54.611064 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2034 09:27:54.617561 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2035 09:27:54.620648 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2036 09:27:54.624018 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2037 09:27:54.627886 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2038 09:27:54.630879 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2039 09:27:54.637306 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2040 09:27:54.640814 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2041 09:27:54.643627 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2042 09:27:54.647265 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2043 09:27:54.654021 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2044 09:27:54.657206 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
2045 09:27:54.657764 ==
2046 09:27:54.660470 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 09:27:54.664396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 09:27:54.664949 ==
2049 09:27:54.667329 DQS Delay:
2050 09:27:54.667937 DQS0 = 0, DQS1 = 0
2051 09:27:54.668311 DQM Delay:
2052 09:27:54.670278 DQM0 = 88, DQM1 = 77
2053 09:27:54.670732 DQ Delay:
2054 09:27:54.673485 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2055 09:27:54.677327 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2056 09:27:54.680139 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =72
2057 09:27:54.683441 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2058 09:27:54.684066
2059 09:27:54.684437
2060 09:27:54.693456 [DQSOSCAuto] RK1, (LSB)MR18= 0x1810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2061 09:27:54.696886 CH1 RK1: MR19=606, MR18=1810
2062 09:27:54.700357 CH1_RK1: MR19=0x606, MR18=0x1810, DQSOSC=403, MR23=63, INC=90, DEC=60
2063 09:27:54.703655 [RxdqsGatingPostProcess] freq 800
2064 09:27:54.710137 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 09:27:54.713440 Pre-setting of DQS Precalculation
2066 09:27:54.716744 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 09:27:54.726804 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 09:27:54.734657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 09:27:54.735230
2070 09:27:54.735717
2071 09:27:54.736558 [Calibration Summary] 1600 Mbps
2072 09:27:54.736955 CH 0, Rank 0
2073 09:27:54.740163 SW Impedance : PASS
2074 09:27:54.740732 DUTY Scan : NO K
2075 09:27:54.743492 ZQ Calibration : PASS
2076 09:27:54.746669 Jitter Meter : NO K
2077 09:27:54.747237 CBT Training : PASS
2078 09:27:54.749986 Write leveling : PASS
2079 09:27:54.752757 RX DQS gating : PASS
2080 09:27:54.753232 RX DQ/DQS(RDDQC) : PASS
2081 09:27:54.756952 TX DQ/DQS : PASS
2082 09:27:54.760116 RX DATLAT : PASS
2083 09:27:54.760602 RX DQ/DQS(Engine): PASS
2084 09:27:54.762892 TX OE : NO K
2085 09:27:54.763458 All Pass.
2086 09:27:54.764017
2087 09:27:54.766427 CH 0, Rank 1
2088 09:27:54.766994 SW Impedance : PASS
2089 09:27:54.770475 DUTY Scan : NO K
2090 09:27:54.771048 ZQ Calibration : PASS
2091 09:27:54.773245 Jitter Meter : NO K
2092 09:27:54.776390 CBT Training : PASS
2093 09:27:54.776858 Write leveling : PASS
2094 09:27:54.779795 RX DQS gating : PASS
2095 09:27:54.783474 RX DQ/DQS(RDDQC) : PASS
2096 09:27:54.784097 TX DQ/DQS : PASS
2097 09:27:54.786334 RX DATLAT : PASS
2098 09:27:54.789560 RX DQ/DQS(Engine): PASS
2099 09:27:54.790129 TX OE : NO K
2100 09:27:54.793221 All Pass.
2101 09:27:54.793781
2102 09:27:54.794260 CH 1, Rank 0
2103 09:27:54.796835 SW Impedance : PASS
2104 09:27:54.797308 DUTY Scan : NO K
2105 09:27:54.799492 ZQ Calibration : PASS
2106 09:27:54.802610 Jitter Meter : NO K
2107 09:27:54.803066 CBT Training : PASS
2108 09:27:54.806182 Write leveling : PASS
2109 09:27:54.809908 RX DQS gating : PASS
2110 09:27:54.810339 RX DQ/DQS(RDDQC) : PASS
2111 09:27:54.812469 TX DQ/DQS : PASS
2112 09:27:54.816058 RX DATLAT : PASS
2113 09:27:54.816602 RX DQ/DQS(Engine): PASS
2114 09:27:54.819359 TX OE : NO K
2115 09:27:54.819939 All Pass.
2116 09:27:54.820379
2117 09:27:54.822834 CH 1, Rank 1
2118 09:27:54.823358 SW Impedance : PASS
2119 09:27:54.826506 DUTY Scan : NO K
2120 09:27:54.827028 ZQ Calibration : PASS
2121 09:27:54.829522 Jitter Meter : NO K
2122 09:27:54.832649 CBT Training : PASS
2123 09:27:54.833176 Write leveling : PASS
2124 09:27:54.836006 RX DQS gating : PASS
2125 09:27:54.839240 RX DQ/DQS(RDDQC) : PASS
2126 09:27:54.839761 TX DQ/DQS : PASS
2127 09:27:54.842814 RX DATLAT : PASS
2128 09:27:54.846168 RX DQ/DQS(Engine): PASS
2129 09:27:54.846736 TX OE : NO K
2130 09:27:54.849395 All Pass.
2131 09:27:54.849811
2132 09:27:54.850135 DramC Write-DBI off
2133 09:27:54.852337 PER_BANK_REFRESH: Hybrid Mode
2134 09:27:54.852754 TX_TRACKING: ON
2135 09:27:54.859486 [GetDramInforAfterCalByMRR] Vendor 6.
2136 09:27:54.862798 [GetDramInforAfterCalByMRR] Revision 606.
2137 09:27:54.865643 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 09:27:54.866103 MR0 0x3b3b
2139 09:27:54.866472 MR8 0x5151
2140 09:27:54.869218 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 09:27:54.872429
2142 09:27:54.872885 MR0 0x3b3b
2143 09:27:54.873211 MR8 0x5151
2144 09:27:54.875558 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 09:27:54.876011
2146 09:27:54.885671 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 09:27:54.889060 [FAST_K] Save calibration result to emmc
2148 09:27:54.892223 [FAST_K] Save calibration result to emmc
2149 09:27:54.895453 dram_init: config_dvfs: 1
2150 09:27:54.899404 dramc_set_vcore_voltage set vcore to 662500
2151 09:27:54.902363 Read voltage for 1200, 2
2152 09:27:54.902818 Vio18 = 0
2153 09:27:54.903179 Vcore = 662500
2154 09:27:54.906109 Vdram = 0
2155 09:27:54.906657 Vddq = 0
2156 09:27:54.907018 Vmddr = 0
2157 09:27:54.912622 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 09:27:54.915840 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 09:27:54.919063 MEM_TYPE=3, freq_sel=15
2160 09:27:54.922126 sv_algorithm_assistance_LP4_1600
2161 09:27:54.925907 ============ PULL DRAM RESETB DOWN ============
2162 09:27:54.929097 ========== PULL DRAM RESETB DOWN end =========
2163 09:27:54.935562 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 09:27:54.939031 ===================================
2165 09:27:54.942651 LPDDR4 DRAM CONFIGURATION
2166 09:27:54.945577 ===================================
2167 09:27:54.946037 EX_ROW_EN[0] = 0x0
2168 09:27:54.949316 EX_ROW_EN[1] = 0x0
2169 09:27:54.949776 LP4Y_EN = 0x0
2170 09:27:54.952157 WORK_FSP = 0x0
2171 09:27:54.952658 WL = 0x4
2172 09:27:54.956868 RL = 0x4
2173 09:27:54.957327 BL = 0x2
2174 09:27:54.958446 RPST = 0x0
2175 09:27:54.958902 RD_PRE = 0x0
2176 09:27:54.962269 WR_PRE = 0x1
2177 09:27:54.962849 WR_PST = 0x0
2178 09:27:54.965543 DBI_WR = 0x0
2179 09:27:54.966098 DBI_RD = 0x0
2180 09:27:54.968625 OTF = 0x1
2181 09:27:54.971876 ===================================
2182 09:27:54.975704 ===================================
2183 09:27:54.976318 ANA top config
2184 09:27:54.979020 ===================================
2185 09:27:54.982291 DLL_ASYNC_EN = 0
2186 09:27:54.985228 ALL_SLAVE_EN = 0
2187 09:27:54.988317 NEW_RANK_MODE = 1
2188 09:27:54.988781 DLL_IDLE_MODE = 1
2189 09:27:54.991550 LP45_APHY_COMB_EN = 1
2190 09:27:54.995259 TX_ODT_DIS = 1
2191 09:27:54.998500 NEW_8X_MODE = 1
2192 09:27:55.001436 ===================================
2193 09:27:55.005119 ===================================
2194 09:27:55.007832 data_rate = 2400
2195 09:27:55.011420 CKR = 1
2196 09:27:55.011869 DQ_P2S_RATIO = 8
2197 09:27:55.015300 ===================================
2198 09:27:55.018047 CA_P2S_RATIO = 8
2199 09:27:55.021339 DQ_CA_OPEN = 0
2200 09:27:55.024687 DQ_SEMI_OPEN = 0
2201 09:27:55.028682 CA_SEMI_OPEN = 0
2202 09:27:55.032206 CA_FULL_RATE = 0
2203 09:27:55.032714 DQ_CKDIV4_EN = 0
2204 09:27:55.034716 CA_CKDIV4_EN = 0
2205 09:27:55.038563 CA_PREDIV_EN = 0
2206 09:27:55.041036 PH8_DLY = 17
2207 09:27:55.044438 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 09:27:55.048309 DQ_AAMCK_DIV = 4
2209 09:27:55.048725 CA_AAMCK_DIV = 4
2210 09:27:55.051269 CA_ADMCK_DIV = 4
2211 09:27:55.054583 DQ_TRACK_CA_EN = 0
2212 09:27:55.057916 CA_PICK = 1200
2213 09:27:55.061396 CA_MCKIO = 1200
2214 09:27:55.065235 MCKIO_SEMI = 0
2215 09:27:55.068079 PLL_FREQ = 2366
2216 09:27:55.068539 DQ_UI_PI_RATIO = 32
2217 09:27:55.071318 CA_UI_PI_RATIO = 0
2218 09:27:55.074590 ===================================
2219 09:27:55.078045 ===================================
2220 09:27:55.081316 memory_type:LPDDR4
2221 09:27:55.084300 GP_NUM : 10
2222 09:27:55.084757 SRAM_EN : 1
2223 09:27:55.087674 MD32_EN : 0
2224 09:27:55.091015 ===================================
2225 09:27:55.094573 [ANA_INIT] >>>>>>>>>>>>>>
2226 09:27:55.095123 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 09:27:55.100926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 09:27:55.104319 ===================================
2229 09:27:55.104781 data_rate = 2400,PCW = 0X5b00
2230 09:27:55.107802 ===================================
2231 09:27:55.110804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 09:27:55.117666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 09:27:55.124840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 09:27:55.127383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 09:27:55.131141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 09:27:55.134230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 09:27:55.137694 [ANA_INIT] flow start
2238 09:27:55.138244 [ANA_INIT] PLL >>>>>>>>
2239 09:27:55.141057 [ANA_INIT] PLL <<<<<<<<
2240 09:27:55.144407 [ANA_INIT] MIDPI >>>>>>>>
2241 09:27:55.147173 [ANA_INIT] MIDPI <<<<<<<<
2242 09:27:55.147630 [ANA_INIT] DLL >>>>>>>>
2243 09:27:55.150860 [ANA_INIT] DLL <<<<<<<<
2244 09:27:55.151318 [ANA_INIT] flow end
2245 09:27:55.157311 ============ LP4 DIFF to SE enter ============
2246 09:27:55.160579 ============ LP4 DIFF to SE exit ============
2247 09:27:55.164555 [ANA_INIT] <<<<<<<<<<<<<
2248 09:27:55.167186 [Flow] Enable top DCM control >>>>>
2249 09:27:55.171000 [Flow] Enable top DCM control <<<<<
2250 09:27:55.174832 Enable DLL master slave shuffle
2251 09:27:55.177785 ==============================================================
2252 09:27:55.180556 Gating Mode config
2253 09:27:55.184120 ==============================================================
2254 09:27:55.187206 Config description:
2255 09:27:55.197727 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 09:27:55.203663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 09:27:55.207127 SELPH_MODE 0: By rank 1: By Phase
2258 09:27:55.213679 ==============================================================
2259 09:27:55.216704 GAT_TRACK_EN = 1
2260 09:27:55.220062 RX_GATING_MODE = 2
2261 09:27:55.223762 RX_GATING_TRACK_MODE = 2
2262 09:27:55.226858 SELPH_MODE = 1
2263 09:27:55.230738 PICG_EARLY_EN = 1
2264 09:27:55.231479 VALID_LAT_VALUE = 1
2265 09:27:55.236771 ==============================================================
2266 09:27:55.240532 Enter into Gating configuration >>>>
2267 09:27:55.243592 Exit from Gating configuration <<<<
2268 09:27:55.247012 Enter into DVFS_PRE_config >>>>>
2269 09:27:55.256538 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 09:27:55.260083 Exit from DVFS_PRE_config <<<<<
2271 09:27:55.263713 Enter into PICG configuration >>>>
2272 09:27:55.266974 Exit from PICG configuration <<<<
2273 09:27:55.270198 [RX_INPUT] configuration >>>>>
2274 09:27:55.273565 [RX_INPUT] configuration <<<<<
2275 09:27:55.280428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 09:27:55.283845 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 09:27:55.290603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 09:27:55.296739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 09:27:55.303693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 09:27:55.310168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 09:27:55.313180 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 09:27:55.316587 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 09:27:55.319913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 09:27:55.326942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 09:27:55.329609 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 09:27:55.332876 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 09:27:55.335944 ===================================
2288 09:27:55.339941 LPDDR4 DRAM CONFIGURATION
2289 09:27:55.342825 ===================================
2290 09:27:55.343381 EX_ROW_EN[0] = 0x0
2291 09:27:55.346425 EX_ROW_EN[1] = 0x0
2292 09:27:55.349883 LP4Y_EN = 0x0
2293 09:27:55.350722 WORK_FSP = 0x0
2294 09:27:55.352509 WL = 0x4
2295 09:27:55.352968 RL = 0x4
2296 09:27:55.356271 BL = 0x2
2297 09:27:55.356835 RPST = 0x0
2298 09:27:55.359466 RD_PRE = 0x0
2299 09:27:55.360028 WR_PRE = 0x1
2300 09:27:55.362437 WR_PST = 0x0
2301 09:27:55.363136 DBI_WR = 0x0
2302 09:27:55.366011 DBI_RD = 0x0
2303 09:27:55.366421 OTF = 0x1
2304 09:27:55.369202 ===================================
2305 09:27:55.372626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 09:27:55.379504 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 09:27:55.382442 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 09:27:55.385864 ===================================
2309 09:27:55.389424 LPDDR4 DRAM CONFIGURATION
2310 09:27:55.392579 ===================================
2311 09:27:55.392989 EX_ROW_EN[0] = 0x10
2312 09:27:55.395693 EX_ROW_EN[1] = 0x0
2313 09:27:55.396146 LP4Y_EN = 0x0
2314 09:27:55.399214 WORK_FSP = 0x0
2315 09:27:55.399878 WL = 0x4
2316 09:27:55.402339 RL = 0x4
2317 09:27:55.405989 BL = 0x2
2318 09:27:55.406496 RPST = 0x0
2319 09:27:55.409434 RD_PRE = 0x0
2320 09:27:55.409979 WR_PRE = 0x1
2321 09:27:55.412581 WR_PST = 0x0
2322 09:27:55.412992 DBI_WR = 0x0
2323 09:27:55.415847 DBI_RD = 0x0
2324 09:27:55.416258 OTF = 0x1
2325 09:27:55.419176 ===================================
2326 09:27:55.425858 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 09:27:55.426363 ==
2328 09:27:55.429354 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 09:27:55.432551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 09:27:55.432970 ==
2331 09:27:55.435617 [Duty_Offset_Calibration]
2332 09:27:55.439277 B0:1 B1:-1 CA:0
2333 09:27:55.439685
2334 09:27:55.442074 [DutyScan_Calibration_Flow] k_type=0
2335 09:27:55.450856
2336 09:27:55.451365 ==CLK 0==
2337 09:27:55.454220 Final CLK duty delay cell = 0
2338 09:27:55.457252 [0] MAX Duty = 5125%(X100), DQS PI = 24
2339 09:27:55.460505 [0] MIN Duty = 4907%(X100), DQS PI = 8
2340 09:27:55.460919 [0] AVG Duty = 5016%(X100)
2341 09:27:55.463771
2342 09:27:55.467297 CH0 CLK Duty spec in!! Max-Min= 218%
2343 09:27:55.470315 [DutyScan_Calibration_Flow] ====Done====
2344 09:27:55.470832
2345 09:27:55.473862 [DutyScan_Calibration_Flow] k_type=1
2346 09:27:55.489184
2347 09:27:55.489713 ==DQS 0 ==
2348 09:27:55.492427 Final DQS duty delay cell = -4
2349 09:27:55.495553 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2350 09:27:55.498891 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2351 09:27:55.502427 [-4] AVG Duty = 4968%(X100)
2352 09:27:55.502948
2353 09:27:55.503283 ==DQS 1 ==
2354 09:27:55.505409 Final DQS duty delay cell = 0
2355 09:27:55.508860 [0] MAX Duty = 5124%(X100), DQS PI = 4
2356 09:27:55.512317 [0] MIN Duty = 5000%(X100), DQS PI = 24
2357 09:27:55.515415 [0] AVG Duty = 5062%(X100)
2358 09:27:55.515872
2359 09:27:55.518734 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2360 09:27:55.519146
2361 09:27:55.522203 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2362 09:27:55.525467 [DutyScan_Calibration_Flow] ====Done====
2363 09:27:55.525877
2364 09:27:55.528838 [DutyScan_Calibration_Flow] k_type=3
2365 09:27:55.546394
2366 09:27:55.546557 ==DQM 0 ==
2367 09:27:55.549436 Final DQM duty delay cell = 0
2368 09:27:55.553259 [0] MAX Duty = 5062%(X100), DQS PI = 18
2369 09:27:55.556339 [0] MIN Duty = 4875%(X100), DQS PI = 8
2370 09:27:55.559149 [0] AVG Duty = 4968%(X100)
2371 09:27:55.559263
2372 09:27:55.559352 ==DQM 1 ==
2373 09:27:55.562410 Final DQM duty delay cell = 4
2374 09:27:55.565923 [4] MAX Duty = 5187%(X100), DQS PI = 32
2375 09:27:55.569846 [4] MIN Duty = 5000%(X100), DQS PI = 22
2376 09:27:55.572549 [4] AVG Duty = 5093%(X100)
2377 09:27:55.572635
2378 09:27:55.575639 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2379 09:27:55.575729
2380 09:27:55.579134 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2381 09:27:55.582668 [DutyScan_Calibration_Flow] ====Done====
2382 09:27:55.582753
2383 09:27:55.585994 [DutyScan_Calibration_Flow] k_type=2
2384 09:27:55.601555
2385 09:27:55.601665 ==DQ 0 ==
2386 09:27:55.604238 Final DQ duty delay cell = -4
2387 09:27:55.607340 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2388 09:27:55.610887 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2389 09:27:55.614379 [-4] AVG Duty = 4969%(X100)
2390 09:27:55.614465
2391 09:27:55.614550 ==DQ 1 ==
2392 09:27:55.617303 Final DQ duty delay cell = -4
2393 09:27:55.620751 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2394 09:27:55.624426 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2395 09:27:55.627512 [-4] AVG Duty = 4938%(X100)
2396 09:27:55.627602
2397 09:27:55.630759 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2398 09:27:55.630844
2399 09:27:55.633932 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2400 09:27:55.637028 [DutyScan_Calibration_Flow] ====Done====
2401 09:27:55.637116 ==
2402 09:27:55.640615 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 09:27:55.644327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 09:27:55.644418 ==
2405 09:27:55.647187 [Duty_Offset_Calibration]
2406 09:27:55.650766 B0:-1 B1:1 CA:1
2407 09:27:55.650868
2408 09:27:55.653525 [DutyScan_Calibration_Flow] k_type=0
2409 09:27:55.662374
2410 09:27:55.662480 ==CLK 0==
2411 09:27:55.664756 Final CLK duty delay cell = 0
2412 09:27:55.668368 [0] MAX Duty = 5156%(X100), DQS PI = 20
2413 09:27:55.671790 [0] MIN Duty = 4969%(X100), DQS PI = 0
2414 09:27:55.671896 [0] AVG Duty = 5062%(X100)
2415 09:27:55.675241
2416 09:27:55.678094 CH1 CLK Duty spec in!! Max-Min= 187%
2417 09:27:55.681407 [DutyScan_Calibration_Flow] ====Done====
2418 09:27:55.681500
2419 09:27:55.684675 [DutyScan_Calibration_Flow] k_type=1
2420 09:27:55.700962
2421 09:27:55.701095 ==DQS 0 ==
2422 09:27:55.704208 Final DQS duty delay cell = 0
2423 09:27:55.707531 [0] MAX Duty = 5156%(X100), DQS PI = 48
2424 09:27:55.711001 [0] MIN Duty = 4938%(X100), DQS PI = 6
2425 09:27:55.711092 [0] AVG Duty = 5047%(X100)
2426 09:27:55.714199
2427 09:27:55.714290 ==DQS 1 ==
2428 09:27:55.717273 Final DQS duty delay cell = 0
2429 09:27:55.720644 [0] MAX Duty = 5094%(X100), DQS PI = 12
2430 09:27:55.723943 [0] MIN Duty = 4969%(X100), DQS PI = 58
2431 09:27:55.727470 [0] AVG Duty = 5031%(X100)
2432 09:27:55.727551
2433 09:27:55.730742 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2434 09:27:55.730824
2435 09:27:55.734157 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2436 09:27:55.737737 [DutyScan_Calibration_Flow] ====Done====
2437 09:27:55.737820
2438 09:27:55.740963 [DutyScan_Calibration_Flow] k_type=3
2439 09:27:55.756748
2440 09:27:55.756865 ==DQM 0 ==
2441 09:27:55.759819 Final DQM duty delay cell = -4
2442 09:27:55.763055 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2443 09:27:55.766365 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2444 09:27:55.769571 [-4] AVG Duty = 4969%(X100)
2445 09:27:55.769653
2446 09:27:55.769718 ==DQM 1 ==
2447 09:27:55.773225 Final DQM duty delay cell = 0
2448 09:27:55.776282 [0] MAX Duty = 5187%(X100), DQS PI = 6
2449 09:27:55.779744 [0] MIN Duty = 5000%(X100), DQS PI = 28
2450 09:27:55.783048 [0] AVG Duty = 5093%(X100)
2451 09:27:55.783129
2452 09:27:55.786071 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2453 09:27:55.786152
2454 09:27:55.789571 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2455 09:27:55.793011 [DutyScan_Calibration_Flow] ====Done====
2456 09:27:55.793092
2457 09:27:55.796300 [DutyScan_Calibration_Flow] k_type=2
2458 09:27:55.813557
2459 09:27:55.813644 ==DQ 0 ==
2460 09:27:55.817248 Final DQ duty delay cell = 0
2461 09:27:55.819591 [0] MAX Duty = 5187%(X100), DQS PI = 30
2462 09:27:55.822938 [0] MIN Duty = 4907%(X100), DQS PI = 6
2463 09:27:55.823023 [0] AVG Duty = 5047%(X100)
2464 09:27:55.827326
2465 09:27:55.827406 ==DQ 1 ==
2466 09:27:55.830145 Final DQ duty delay cell = 0
2467 09:27:55.833575 [0] MAX Duty = 5124%(X100), DQS PI = 10
2468 09:27:55.836460 [0] MIN Duty = 4969%(X100), DQS PI = 0
2469 09:27:55.836543 [0] AVG Duty = 5046%(X100)
2470 09:27:55.836608
2471 09:27:55.840270 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2472 09:27:55.842898
2473 09:27:55.846384 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2474 09:27:55.849949 [DutyScan_Calibration_Flow] ====Done====
2475 09:27:55.853196 nWR fixed to 30
2476 09:27:55.853279 [ModeRegInit_LP4] CH0 RK0
2477 09:27:55.856438 [ModeRegInit_LP4] CH0 RK1
2478 09:27:55.859518 [ModeRegInit_LP4] CH1 RK0
2479 09:27:55.863098 [ModeRegInit_LP4] CH1 RK1
2480 09:27:55.863180 match AC timing 7
2481 09:27:55.866260 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 09:27:55.872978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 09:27:55.876369 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 09:27:55.883040 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 09:27:55.886040 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 09:27:55.886121 ==
2487 09:27:55.889923 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 09:27:55.892755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 09:27:55.892837 ==
2490 09:27:55.899296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 09:27:55.905909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 09:27:55.913338 [CA 0] Center 39 (9~70) winsize 62
2493 09:27:55.916603 [CA 1] Center 39 (9~70) winsize 62
2494 09:27:55.919681 [CA 2] Center 35 (5~66) winsize 62
2495 09:27:55.923038 [CA 3] Center 35 (5~66) winsize 62
2496 09:27:55.926518 [CA 4] Center 33 (3~63) winsize 61
2497 09:27:55.929596 [CA 5] Center 33 (4~63) winsize 60
2498 09:27:55.929677
2499 09:27:55.932853 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 09:27:55.932935
2501 09:27:55.936235 [CATrainingPosCal] consider 1 rank data
2502 09:27:55.940035 u2DelayCellTimex100 = 270/100 ps
2503 09:27:55.943651 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 09:27:55.949652 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 09:27:55.953104 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 09:27:55.956326 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 09:27:55.960140 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
2508 09:27:55.962895 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2509 09:27:55.962977
2510 09:27:55.966922 CA PerBit enable=1, Macro0, CA PI delay=33
2511 09:27:55.967075
2512 09:27:55.969836 [CBTSetCACLKResult] CA Dly = 33
2513 09:27:55.969990 CS Dly: 8 (0~39)
2514 09:27:55.973075 ==
2515 09:27:55.976598 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 09:27:55.979787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 09:27:55.979944 ==
2518 09:27:55.983698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 09:27:55.989746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 09:27:55.998909 [CA 0] Center 39 (9~70) winsize 62
2521 09:27:56.002435 [CA 1] Center 39 (9~70) winsize 62
2522 09:27:56.005308 [CA 2] Center 35 (5~66) winsize 62
2523 09:27:56.008664 [CA 3] Center 34 (4~65) winsize 62
2524 09:27:56.012467 [CA 4] Center 33 (3~64) winsize 62
2525 09:27:56.015613 [CA 5] Center 33 (3~63) winsize 61
2526 09:27:56.015733
2527 09:27:56.018772 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 09:27:56.018857
2529 09:27:56.022126 [CATrainingPosCal] consider 2 rank data
2530 09:27:56.025209 u2DelayCellTimex100 = 270/100 ps
2531 09:27:56.028912 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2532 09:27:56.035637 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 09:27:56.038898 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 09:27:56.042060 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2535 09:27:56.045461 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
2536 09:27:56.048667 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2537 09:27:56.048756
2538 09:27:56.051962 CA PerBit enable=1, Macro0, CA PI delay=33
2539 09:27:56.052055
2540 09:27:56.055204 [CBTSetCACLKResult] CA Dly = 33
2541 09:27:56.055293 CS Dly: 9 (0~41)
2542 09:27:56.058958
2543 09:27:56.062165 ----->DramcWriteLeveling(PI) begin...
2544 09:27:56.062274 ==
2545 09:27:56.065147 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 09:27:56.068834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 09:27:56.068924 ==
2548 09:27:56.071644 Write leveling (Byte 0): 34 => 34
2549 09:27:56.075297 Write leveling (Byte 1): 29 => 29
2550 09:27:56.078287 DramcWriteLeveling(PI) end<-----
2551 09:27:56.078380
2552 09:27:56.078446 ==
2553 09:27:56.081783 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 09:27:56.085233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 09:27:56.085323 ==
2556 09:27:56.088755 [Gating] SW mode calibration
2557 09:27:56.094878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 09:27:56.101452 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 09:27:56.105156 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2560 09:27:56.108281 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2561 09:27:56.115021 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 09:27:56.118285 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 09:27:56.121483 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 09:27:56.128310 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 09:27:56.131535 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 09:27:56.134914 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2567 09:27:56.141836 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2568 09:27:56.144846 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 09:27:56.148395 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 09:27:56.151662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 09:27:56.158426 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 09:27:56.161663 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 09:27:56.165215 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 09:27:56.171528 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2575 09:27:56.175253 1 1 0 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
2576 09:27:56.178263 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2577 09:27:56.184665 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 09:27:56.188158 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 09:27:56.191134 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 09:27:56.198316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 09:27:56.201723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 09:27:56.205072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 09:27:56.211122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2584 09:27:56.214808 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2585 09:27:56.217916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 09:27:56.224269 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 09:27:56.228599 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 09:27:56.231184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 09:27:56.238054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 09:27:56.240891 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 09:27:56.244361 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 09:27:56.251644 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 09:27:56.254328 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 09:27:56.257757 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 09:27:56.264316 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 09:27:56.267636 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 09:27:56.271088 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2598 09:27:56.277625 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 09:27:56.281337 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2600 09:27:56.284136 Total UI for P1: 0, mck2ui 16
2601 09:27:56.287290 best dqsien dly found for B0: ( 1, 3, 26)
2602 09:27:56.290731 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 09:27:56.294336 Total UI for P1: 0, mck2ui 16
2604 09:27:56.297299 best dqsien dly found for B1: ( 1, 4, 0)
2605 09:27:56.300745 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2606 09:27:56.303814 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2607 09:27:56.303912
2608 09:27:56.307269 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2609 09:27:56.313862 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2610 09:27:56.313982 [Gating] SW calibration Done
2611 09:27:56.314051 ==
2612 09:27:56.316974 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 09:27:56.324214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 09:27:56.324333 ==
2615 09:27:56.324402 RX Vref Scan: 0
2616 09:27:56.324462
2617 09:27:56.326950 RX Vref 0 -> 0, step: 1
2618 09:27:56.327035
2619 09:27:56.330756 RX Delay -40 -> 252, step: 8
2620 09:27:56.333873 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2621 09:27:56.336961 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2622 09:27:56.340375 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2623 09:27:56.347047 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2624 09:27:56.350561 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2625 09:27:56.353618 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2626 09:27:56.356680 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2627 09:27:56.360197 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2628 09:27:56.367035 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2629 09:27:56.370195 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2630 09:27:56.373389 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2631 09:27:56.377008 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2632 09:27:56.380106 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2633 09:27:56.386734 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2634 09:27:56.389847 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2635 09:27:56.393583 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2636 09:27:56.393680 ==
2637 09:27:56.396777 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 09:27:56.400450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 09:27:56.400568 ==
2640 09:27:56.403056 DQS Delay:
2641 09:27:56.403142 DQS0 = 0, DQS1 = 0
2642 09:27:56.407019 DQM Delay:
2643 09:27:56.407114 DQM0 = 119, DQM1 = 107
2644 09:27:56.410145 DQ Delay:
2645 09:27:56.413443 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2646 09:27:56.416710 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2647 09:27:56.419775 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2648 09:27:56.422796 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2649 09:27:56.422918
2650 09:27:56.423013
2651 09:27:56.423101 ==
2652 09:27:56.426556 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 09:27:56.429676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 09:27:56.429769 ==
2655 09:27:56.429836
2656 09:27:56.429896
2657 09:27:56.432937 TX Vref Scan disable
2658 09:27:56.436750 == TX Byte 0 ==
2659 09:27:56.439898 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2660 09:27:56.443155 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2661 09:27:56.446675 == TX Byte 1 ==
2662 09:27:56.450212 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2663 09:27:56.453040 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2664 09:27:56.453168 ==
2665 09:27:56.456535 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 09:27:56.459813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 09:27:56.462764 ==
2668 09:27:56.473361 TX Vref=22, minBit 3, minWin=25, winSum=415
2669 09:27:56.476867 TX Vref=24, minBit 13, minWin=25, winSum=425
2670 09:27:56.480014 TX Vref=26, minBit 10, minWin=26, winSum=428
2671 09:27:56.483540 TX Vref=28, minBit 10, minWin=26, winSum=435
2672 09:27:56.486562 TX Vref=30, minBit 10, minWin=26, winSum=434
2673 09:27:56.493288 TX Vref=32, minBit 4, minWin=26, winSum=433
2674 09:27:56.496934 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2675 09:27:56.497034
2676 09:27:56.500029 Final TX Range 1 Vref 28
2677 09:27:56.500119
2678 09:27:56.500185 ==
2679 09:27:56.503643 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 09:27:56.509868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 09:27:56.509980 ==
2682 09:27:56.510049
2683 09:27:56.510109
2684 09:27:56.510166 TX Vref Scan disable
2685 09:27:56.513789 == TX Byte 0 ==
2686 09:27:56.517571 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2687 09:27:56.524001 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2688 09:27:56.524109 == TX Byte 1 ==
2689 09:27:56.527174 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2690 09:27:56.533820 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2691 09:27:56.533919
2692 09:27:56.533987 [DATLAT]
2693 09:27:56.534047 Freq=1200, CH0 RK0
2694 09:27:56.534106
2695 09:27:56.537084 DATLAT Default: 0xd
2696 09:27:56.537171 0, 0xFFFF, sum = 0
2697 09:27:56.540424 1, 0xFFFF, sum = 0
2698 09:27:56.543679 2, 0xFFFF, sum = 0
2699 09:27:56.543785 3, 0xFFFF, sum = 0
2700 09:27:56.547183 4, 0xFFFF, sum = 0
2701 09:27:56.547267 5, 0xFFFF, sum = 0
2702 09:27:56.549956 6, 0xFFFF, sum = 0
2703 09:27:56.550041 7, 0xFFFF, sum = 0
2704 09:27:56.553813 8, 0xFFFF, sum = 0
2705 09:27:56.553902 9, 0xFFFF, sum = 0
2706 09:27:56.556814 10, 0xFFFF, sum = 0
2707 09:27:56.556901 11, 0xFFFF, sum = 0
2708 09:27:56.560366 12, 0x0, sum = 1
2709 09:27:56.560452 13, 0x0, sum = 2
2710 09:27:56.563715 14, 0x0, sum = 3
2711 09:27:56.563827 15, 0x0, sum = 4
2712 09:27:56.567014 best_step = 13
2713 09:27:56.567150
2714 09:27:56.567243 ==
2715 09:27:56.569891 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 09:27:56.573566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 09:27:56.573654 ==
2718 09:27:56.573720 RX Vref Scan: 1
2719 09:27:56.573780
2720 09:27:56.576583 Set Vref Range= 32 -> 127
2721 09:27:56.576668
2722 09:27:56.580010 RX Vref 32 -> 127, step: 1
2723 09:27:56.580095
2724 09:27:56.583383 RX Delay -21 -> 252, step: 4
2725 09:27:56.583466
2726 09:27:56.587262 Set Vref, RX VrefLevel [Byte0]: 32
2727 09:27:56.590268 [Byte1]: 32
2728 09:27:56.590363
2729 09:27:56.593253 Set Vref, RX VrefLevel [Byte0]: 33
2730 09:27:56.596733 [Byte1]: 33
2731 09:27:56.600184
2732 09:27:56.600277 Set Vref, RX VrefLevel [Byte0]: 34
2733 09:27:56.603503 [Byte1]: 34
2734 09:27:56.608163
2735 09:27:56.608266 Set Vref, RX VrefLevel [Byte0]: 35
2736 09:27:56.611452 [Byte1]: 35
2737 09:27:56.616042
2738 09:27:56.616167 Set Vref, RX VrefLevel [Byte0]: 36
2739 09:27:56.619309 [Byte1]: 36
2740 09:27:56.623975
2741 09:27:56.624146 Set Vref, RX VrefLevel [Byte0]: 37
2742 09:27:56.627609 [Byte1]: 37
2743 09:27:56.631477
2744 09:27:56.635579 Set Vref, RX VrefLevel [Byte0]: 38
2745 09:27:56.638827 [Byte1]: 38
2746 09:27:56.638960
2747 09:27:56.641901 Set Vref, RX VrefLevel [Byte0]: 39
2748 09:27:56.644934 [Byte1]: 39
2749 09:27:56.645037
2750 09:27:56.648510 Set Vref, RX VrefLevel [Byte0]: 40
2751 09:27:56.651668 [Byte1]: 40
2752 09:27:56.655557
2753 09:27:56.655658 Set Vref, RX VrefLevel [Byte0]: 41
2754 09:27:56.659162 [Byte1]: 41
2755 09:27:56.663496
2756 09:27:56.663590 Set Vref, RX VrefLevel [Byte0]: 42
2757 09:27:56.667313 [Byte1]: 42
2758 09:27:56.671474
2759 09:27:56.671566 Set Vref, RX VrefLevel [Byte0]: 43
2760 09:27:56.674665 [Byte1]: 43
2761 09:27:56.679319
2762 09:27:56.679422 Set Vref, RX VrefLevel [Byte0]: 44
2763 09:27:56.683086 [Byte1]: 44
2764 09:27:56.687138
2765 09:27:56.687284 Set Vref, RX VrefLevel [Byte0]: 45
2766 09:27:56.691288 [Byte1]: 45
2767 09:27:56.695190
2768 09:27:56.695292 Set Vref, RX VrefLevel [Byte0]: 46
2769 09:27:56.698538 [Byte1]: 46
2770 09:27:56.703210
2771 09:27:56.703310 Set Vref, RX VrefLevel [Byte0]: 47
2772 09:27:56.706675 [Byte1]: 47
2773 09:27:56.711054
2774 09:27:56.711155 Set Vref, RX VrefLevel [Byte0]: 48
2775 09:27:56.714579 [Byte1]: 48
2776 09:27:56.718991
2777 09:27:56.719087 Set Vref, RX VrefLevel [Byte0]: 49
2778 09:27:56.722255 [Byte1]: 49
2779 09:27:56.726955
2780 09:27:56.727056 Set Vref, RX VrefLevel [Byte0]: 50
2781 09:27:56.730200 [Byte1]: 50
2782 09:27:56.735161
2783 09:27:56.735254 Set Vref, RX VrefLevel [Byte0]: 51
2784 09:27:56.738303 [Byte1]: 51
2785 09:27:56.742996
2786 09:27:56.743091 Set Vref, RX VrefLevel [Byte0]: 52
2787 09:27:56.746499 [Byte1]: 52
2788 09:27:56.750653
2789 09:27:56.750754 Set Vref, RX VrefLevel [Byte0]: 53
2790 09:27:56.753934 [Byte1]: 53
2791 09:27:56.758692
2792 09:27:56.758793 Set Vref, RX VrefLevel [Byte0]: 54
2793 09:27:56.761988 [Byte1]: 54
2794 09:27:56.766646
2795 09:27:56.766738 Set Vref, RX VrefLevel [Byte0]: 55
2796 09:27:56.770031 [Byte1]: 55
2797 09:27:56.774409
2798 09:27:56.774500 Set Vref, RX VrefLevel [Byte0]: 56
2799 09:27:56.778191 [Byte1]: 56
2800 09:27:56.782394
2801 09:27:56.782485 Set Vref, RX VrefLevel [Byte0]: 57
2802 09:27:56.785681 [Byte1]: 57
2803 09:27:56.790845
2804 09:27:56.790941 Set Vref, RX VrefLevel [Byte0]: 58
2805 09:27:56.793636 [Byte1]: 58
2806 09:27:56.798441
2807 09:27:56.798530 Set Vref, RX VrefLevel [Byte0]: 59
2808 09:27:56.801650 [Byte1]: 59
2809 09:27:56.806145
2810 09:27:56.806238 Set Vref, RX VrefLevel [Byte0]: 60
2811 09:27:56.809716 [Byte1]: 60
2812 09:27:56.814228
2813 09:27:56.814323 Set Vref, RX VrefLevel [Byte0]: 61
2814 09:27:56.817517 [Byte1]: 61
2815 09:27:56.822046
2816 09:27:56.822141 Set Vref, RX VrefLevel [Byte0]: 62
2817 09:27:56.825595 [Byte1]: 62
2818 09:27:56.829981
2819 09:27:56.833538 Set Vref, RX VrefLevel [Byte0]: 63
2820 09:27:56.833634 [Byte1]: 63
2821 09:27:56.838081
2822 09:27:56.838177 Set Vref, RX VrefLevel [Byte0]: 64
2823 09:27:56.841108 [Byte1]: 64
2824 09:27:56.846307
2825 09:27:56.846417 Set Vref, RX VrefLevel [Byte0]: 65
2826 09:27:56.848901 [Byte1]: 65
2827 09:27:56.853560
2828 09:27:56.853670 Set Vref, RX VrefLevel [Byte0]: 66
2829 09:27:56.856911 [Byte1]: 66
2830 09:27:56.861502
2831 09:27:56.861603 Set Vref, RX VrefLevel [Byte0]: 67
2832 09:27:56.865033 [Byte1]: 67
2833 09:27:56.869707
2834 09:27:56.869798 Set Vref, RX VrefLevel [Byte0]: 68
2835 09:27:56.873608 [Byte1]: 68
2836 09:27:56.877945
2837 09:27:56.878031 Set Vref, RX VrefLevel [Byte0]: 69
2838 09:27:56.880770 [Byte1]: 69
2839 09:27:56.885609
2840 09:27:56.885696 Set Vref, RX VrefLevel [Byte0]: 70
2841 09:27:56.888597 [Byte1]: 70
2842 09:27:56.893242
2843 09:27:56.893327 Set Vref, RX VrefLevel [Byte0]: 71
2844 09:27:56.896764 [Byte1]: 71
2845 09:27:56.901260
2846 09:27:56.901356 Set Vref, RX VrefLevel [Byte0]: 72
2847 09:27:56.904800 [Byte1]: 72
2848 09:27:56.909229
2849 09:27:56.909320 Set Vref, RX VrefLevel [Byte0]: 73
2850 09:27:56.912364 [Byte1]: 73
2851 09:27:56.917220
2852 09:27:56.917311 Set Vref, RX VrefLevel [Byte0]: 74
2853 09:27:56.920683 [Byte1]: 74
2854 09:27:56.924969
2855 09:27:56.925066 Set Vref, RX VrefLevel [Byte0]: 75
2856 09:27:56.931396 [Byte1]: 75
2857 09:27:56.931499
2858 09:27:56.934895 Set Vref, RX VrefLevel [Byte0]: 76
2859 09:27:56.938348 [Byte1]: 76
2860 09:27:56.938443
2861 09:27:56.941382 Set Vref, RX VrefLevel [Byte0]: 77
2862 09:27:56.944440 [Byte1]: 77
2863 09:27:56.948978
2864 09:27:56.949074 Set Vref, RX VrefLevel [Byte0]: 78
2865 09:27:56.952010 [Byte1]: 78
2866 09:27:56.956848
2867 09:27:56.956951 Final RX Vref Byte 0 = 59 to rank0
2868 09:27:56.960413 Final RX Vref Byte 1 = 59 to rank0
2869 09:27:56.963537 Final RX Vref Byte 0 = 59 to rank1
2870 09:27:56.966827 Final RX Vref Byte 1 = 59 to rank1==
2871 09:27:56.970864 Dram Type= 6, Freq= 0, CH_0, rank 0
2872 09:27:56.976894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 09:27:56.976997 ==
2874 09:27:56.977063 DQS Delay:
2875 09:27:56.977123 DQS0 = 0, DQS1 = 0
2876 09:27:56.980569 DQM Delay:
2877 09:27:56.980655 DQM0 = 119, DQM1 = 107
2878 09:27:56.983578 DQ Delay:
2879 09:27:56.987054 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =116
2880 09:27:56.990028 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2881 09:27:56.993663 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2882 09:27:56.996421 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2883 09:27:56.996515
2884 09:27:56.996581
2885 09:27:57.006872 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2886 09:27:57.007002 CH0 RK0: MR19=403, MR18=12FE
2887 09:27:57.014085 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2888 09:27:57.014197
2889 09:27:57.016714 ----->DramcWriteLeveling(PI) begin...
2890 09:27:57.016800 ==
2891 09:27:57.019891 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 09:27:57.026717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 09:27:57.026829 ==
2894 09:27:57.029839 Write leveling (Byte 0): 32 => 32
2895 09:27:57.029933 Write leveling (Byte 1): 31 => 31
2896 09:27:57.033378 DramcWriteLeveling(PI) end<-----
2897 09:27:57.033465
2898 09:27:57.036227 ==
2899 09:27:57.036316 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 09:27:57.042843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 09:27:57.042949 ==
2902 09:27:57.046173 [Gating] SW mode calibration
2903 09:27:57.053187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2904 09:27:57.056274 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2905 09:27:57.063067 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2906 09:27:57.067037 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2907 09:27:57.069484 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 09:27:57.076192 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 09:27:57.079708 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 09:27:57.082941 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 09:27:57.089732 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2912 09:27:57.093136 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
2913 09:27:57.096501 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2914 09:27:57.102589 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 09:27:57.106578 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 09:27:57.109575 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 09:27:57.112854 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 09:27:57.119430 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 09:27:57.122790 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 09:27:57.126114 1 0 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
2921 09:27:57.132913 1 1 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
2922 09:27:57.136375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 09:27:57.139127 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 09:27:57.145801 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 09:27:57.149440 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 09:27:57.152724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 09:27:57.159295 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 09:27:57.162778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2929 09:27:57.165680 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2930 09:27:57.172353 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 09:27:57.176216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 09:27:57.179199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 09:27:57.185356 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 09:27:57.189191 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 09:27:57.191995 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 09:27:57.198779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 09:27:57.202166 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 09:27:57.205377 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 09:27:57.212537 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 09:27:57.215673 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 09:27:57.218959 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 09:27:57.225206 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 09:27:57.228564 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2944 09:27:57.231858 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2945 09:27:57.238553 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2946 09:27:57.238664 Total UI for P1: 0, mck2ui 16
2947 09:27:57.245181 best dqsien dly found for B0: ( 1, 3, 26)
2948 09:27:57.248275 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 09:27:57.252378 Total UI for P1: 0, mck2ui 16
2950 09:27:57.255230 best dqsien dly found for B1: ( 1, 3, 30)
2951 09:27:57.258476 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2952 09:27:57.261699 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2953 09:27:57.261790
2954 09:27:57.264865 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2955 09:27:57.268252 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2956 09:27:57.271520 [Gating] SW calibration Done
2957 09:27:57.271611 ==
2958 09:27:57.275425 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 09:27:57.278120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 09:27:57.281714 ==
2961 09:27:57.281811 RX Vref Scan: 0
2962 09:27:57.281877
2963 09:27:57.285260 RX Vref 0 -> 0, step: 1
2964 09:27:57.285348
2965 09:27:57.288411 RX Delay -40 -> 252, step: 8
2966 09:27:57.292011 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2967 09:27:57.295093 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2968 09:27:57.298199 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2969 09:27:57.301873 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2970 09:27:57.308556 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2971 09:27:57.311651 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2972 09:27:57.314727 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2973 09:27:57.318253 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2974 09:27:57.321340 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2975 09:27:57.325075 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2976 09:27:57.331900 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2977 09:27:57.334723 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2978 09:27:57.337758 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2979 09:27:57.341019 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2980 09:27:57.347720 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2981 09:27:57.351173 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2982 09:27:57.351307 ==
2983 09:27:57.354132 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 09:27:57.357608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 09:27:57.357697 ==
2986 09:27:57.360929 DQS Delay:
2987 09:27:57.361014 DQS0 = 0, DQS1 = 0
2988 09:27:57.361078 DQM Delay:
2989 09:27:57.364287 DQM0 = 117, DQM1 = 108
2990 09:27:57.364389 DQ Delay:
2991 09:27:57.367984 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2992 09:27:57.371053 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2993 09:27:57.374134 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2994 09:27:57.381012 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2995 09:27:57.381115
2996 09:27:57.381184
2997 09:27:57.381243 ==
2998 09:27:57.384194 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 09:27:57.387657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 09:27:57.387787 ==
3001 09:27:57.387854
3002 09:27:57.387915
3003 09:27:57.390515 TX Vref Scan disable
3004 09:27:57.390597 == TX Byte 0 ==
3005 09:27:57.397684 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3006 09:27:57.400663 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3007 09:27:57.400753 == TX Byte 1 ==
3008 09:27:57.407509 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3009 09:27:57.410669 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3010 09:27:57.410760 ==
3011 09:27:57.414250 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 09:27:57.417102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 09:27:57.417190 ==
3014 09:27:57.430261 TX Vref=22, minBit 5, minWin=25, winSum=425
3015 09:27:57.433778 TX Vref=24, minBit 0, minWin=26, winSum=424
3016 09:27:57.436757 TX Vref=26, minBit 8, minWin=25, winSum=429
3017 09:27:57.440260 TX Vref=28, minBit 1, minWin=26, winSum=434
3018 09:27:57.443633 TX Vref=30, minBit 1, minWin=26, winSum=434
3019 09:27:57.446949 TX Vref=32, minBit 2, minWin=26, winSum=433
3020 09:27:57.453670 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
3021 09:27:57.453796
3022 09:27:57.457093 Final TX Range 1 Vref 28
3023 09:27:57.457183
3024 09:27:57.457248 ==
3025 09:27:57.460472 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 09:27:57.463360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 09:27:57.463449 ==
3028 09:27:57.467002
3029 09:27:57.467075
3030 09:27:57.467138 TX Vref Scan disable
3031 09:27:57.469839 == TX Byte 0 ==
3032 09:27:57.473177 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3033 09:27:57.480309 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3034 09:27:57.480428 == TX Byte 1 ==
3035 09:27:57.483462 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3036 09:27:57.489610 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3037 09:27:57.489731
3038 09:27:57.489816 [DATLAT]
3039 09:27:57.489910 Freq=1200, CH0 RK1
3040 09:27:57.489987
3041 09:27:57.493291 DATLAT Default: 0xd
3042 09:27:57.496281 0, 0xFFFF, sum = 0
3043 09:27:57.496382 1, 0xFFFF, sum = 0
3044 09:27:57.499637 2, 0xFFFF, sum = 0
3045 09:27:57.499734 3, 0xFFFF, sum = 0
3046 09:27:57.503245 4, 0xFFFF, sum = 0
3047 09:27:57.503336 5, 0xFFFF, sum = 0
3048 09:27:57.506413 6, 0xFFFF, sum = 0
3049 09:27:57.506502 7, 0xFFFF, sum = 0
3050 09:27:57.509636 8, 0xFFFF, sum = 0
3051 09:27:57.509722 9, 0xFFFF, sum = 0
3052 09:27:57.512695 10, 0xFFFF, sum = 0
3053 09:27:57.512782 11, 0xFFFF, sum = 0
3054 09:27:57.516170 12, 0x0, sum = 1
3055 09:27:57.516257 13, 0x0, sum = 2
3056 09:27:57.519918 14, 0x0, sum = 3
3057 09:27:57.520007 15, 0x0, sum = 4
3058 09:27:57.522725 best_step = 13
3059 09:27:57.522819
3060 09:27:57.522892 ==
3061 09:27:57.526194 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 09:27:57.529137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 09:27:57.529228 ==
3064 09:27:57.533016 RX Vref Scan: 0
3065 09:27:57.533102
3066 09:27:57.533169 RX Vref 0 -> 0, step: 1
3067 09:27:57.533230
3068 09:27:57.536164 RX Delay -21 -> 252, step: 4
3069 09:27:57.543123 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3070 09:27:57.545831 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3071 09:27:57.549148 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3072 09:27:57.552350 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3073 09:27:57.555834 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3074 09:27:57.562303 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3075 09:27:57.565690 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3076 09:27:57.569193 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3077 09:27:57.572321 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3078 09:27:57.575580 iDelay=199, Bit 9, Center 96 (31 ~ 162) 132
3079 09:27:57.582499 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3080 09:27:57.586034 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3081 09:27:57.589438 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3082 09:27:57.592403 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3083 09:27:57.595691 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3084 09:27:57.602525 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3085 09:27:57.602641 ==
3086 09:27:57.605448 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 09:27:57.608813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 09:27:57.608900 ==
3089 09:27:57.608966 DQS Delay:
3090 09:27:57.612481 DQS0 = 0, DQS1 = 0
3091 09:27:57.612566 DQM Delay:
3092 09:27:57.616041 DQM0 = 116, DQM1 = 109
3093 09:27:57.616140 DQ Delay:
3094 09:27:57.618709 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3095 09:27:57.621955 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3096 09:27:57.625617 DQ8 =98, DQ9 =96, DQ10 =112, DQ11 =104
3097 09:27:57.628766 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =116
3098 09:27:57.628855
3099 09:27:57.628919
3100 09:27:57.638652 [DQSOSCAuto] RK1, (LSB)MR18= 0x11eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3101 09:27:57.642139 CH0 RK1: MR19=403, MR18=11EB
3102 09:27:57.648963 CH0_RK1: MR19=0x403, MR18=0x11EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3103 09:27:57.649060 [RxdqsGatingPostProcess] freq 1200
3104 09:27:57.655185 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 09:27:57.658709 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 09:27:57.662060 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 09:27:57.665293 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 09:27:57.668818 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 09:27:57.671868 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 09:27:57.675136 best DQS1 dly(2T, 0.5T) = (0, 11)
3111 09:27:57.678795 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 09:27:57.681946 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3113 09:27:57.684959 Pre-setting of DQS Precalculation
3114 09:27:57.688467 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 09:27:57.688560 ==
3116 09:27:57.691669 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 09:27:57.694855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 09:27:57.698548 ==
3119 09:27:57.701692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 09:27:57.708990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3121 09:27:57.716306 [CA 0] Center 37 (7~68) winsize 62
3122 09:27:57.719475 [CA 1] Center 37 (7~68) winsize 62
3123 09:27:57.723075 [CA 2] Center 34 (4~64) winsize 61
3124 09:27:57.726465 [CA 3] Center 33 (3~64) winsize 62
3125 09:27:57.729686 [CA 4] Center 34 (4~64) winsize 61
3126 09:27:57.732905 [CA 5] Center 33 (3~64) winsize 62
3127 09:27:57.733002
3128 09:27:57.736061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 09:27:57.736145
3130 09:27:57.739556 [CATrainingPosCal] consider 1 rank data
3131 09:27:57.742818 u2DelayCellTimex100 = 270/100 ps
3132 09:27:57.746118 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 09:27:57.752819 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 09:27:57.756104 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 09:27:57.759314 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3136 09:27:57.762756 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 09:27:57.766556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3138 09:27:57.766671
3139 09:27:57.769649 CA PerBit enable=1, Macro0, CA PI delay=33
3140 09:27:57.769740
3141 09:27:57.772600 [CBTSetCACLKResult] CA Dly = 33
3142 09:27:57.772689 CS Dly: 5 (0~36)
3143 09:27:57.776066 ==
3144 09:27:57.779453 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 09:27:57.782907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 09:27:57.783009 ==
3147 09:27:57.786084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 09:27:57.792364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3149 09:27:57.801958 [CA 0] Center 37 (7~68) winsize 62
3150 09:27:57.805198 [CA 1] Center 38 (8~68) winsize 61
3151 09:27:57.808615 [CA 2] Center 34 (3~65) winsize 63
3152 09:27:57.811594 [CA 3] Center 33 (3~64) winsize 62
3153 09:27:57.814875 [CA 4] Center 34 (3~65) winsize 63
3154 09:27:57.818236 [CA 5] Center 33 (3~64) winsize 62
3155 09:27:57.818342
3156 09:27:57.821679 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3157 09:27:57.821766
3158 09:27:57.825251 [CATrainingPosCal] consider 2 rank data
3159 09:27:57.828767 u2DelayCellTimex100 = 270/100 ps
3160 09:27:57.831845 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 09:27:57.838555 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3162 09:27:57.841424 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 09:27:57.844872 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3164 09:27:57.848354 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 09:27:57.851892 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3166 09:27:57.851989
3167 09:27:57.855174 CA PerBit enable=1, Macro0, CA PI delay=33
3168 09:27:57.855281
3169 09:27:57.858423 [CBTSetCACLKResult] CA Dly = 33
3170 09:27:57.862064 CS Dly: 7 (0~40)
3171 09:27:57.862166
3172 09:27:57.865094 ----->DramcWriteLeveling(PI) begin...
3173 09:27:57.865189 ==
3174 09:27:57.868141 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 09:27:57.871515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 09:27:57.871614 ==
3177 09:27:57.874847 Write leveling (Byte 0): 26 => 26
3178 09:27:57.877899 Write leveling (Byte 1): 28 => 28
3179 09:27:57.881639 DramcWriteLeveling(PI) end<-----
3180 09:27:57.881733
3181 09:27:57.881799 ==
3182 09:27:57.884853 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 09:27:57.888334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 09:27:57.888443 ==
3185 09:27:57.891332 [Gating] SW mode calibration
3186 09:27:57.897882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 09:27:57.904488 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 09:27:57.907838 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3189 09:27:57.910985 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 09:27:57.918177 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 09:27:57.921094 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 09:27:57.924467 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 09:27:57.930945 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 09:27:57.934275 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
3195 09:27:57.937741 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3196 09:27:57.944085 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 09:27:57.947597 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 09:27:57.951271 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 09:27:57.957641 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 09:27:57.960963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 09:27:57.964237 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 09:27:57.971084 1 0 24 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
3203 09:27:57.974185 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3204 09:27:57.977472 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 09:27:57.983784 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 09:27:57.987396 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 09:27:57.990817 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 09:27:57.997424 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 09:27:58.000348 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 09:27:58.003990 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3211 09:27:58.010753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3212 09:27:58.013498 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:27:58.017014 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 09:27:58.023608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 09:27:58.026934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 09:27:58.030122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 09:27:58.036709 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 09:27:58.039993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 09:27:58.043257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 09:27:58.049930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 09:27:58.053261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 09:27:58.056521 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 09:27:58.059964 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 09:27:58.066687 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 09:27:58.069880 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 09:27:58.073509 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 09:27:58.080011 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 09:27:58.083506 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 09:27:58.086877 Total UI for P1: 0, mck2ui 16
3230 09:27:58.090258 best dqsien dly found for B0: ( 1, 3, 26)
3231 09:27:58.093974 Total UI for P1: 0, mck2ui 16
3232 09:27:58.096933 best dqsien dly found for B1: ( 1, 3, 26)
3233 09:27:58.099924 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3234 09:27:58.103168 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3235 09:27:58.103263
3236 09:27:58.106363 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3237 09:27:58.109906 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3238 09:27:58.113618 [Gating] SW calibration Done
3239 09:27:58.113712 ==
3240 09:27:58.116672 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 09:27:58.123570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 09:27:58.123687 ==
3243 09:27:58.123801 RX Vref Scan: 0
3244 09:27:58.123866
3245 09:27:58.126542 RX Vref 0 -> 0, step: 1
3246 09:27:58.126627
3247 09:27:58.129822 RX Delay -40 -> 252, step: 8
3248 09:27:58.133063 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3249 09:27:58.136377 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3250 09:27:58.140047 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3251 09:27:58.143381 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3252 09:27:58.149676 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3253 09:27:58.152930 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 09:27:58.156551 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3255 09:27:58.159656 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3256 09:27:58.162909 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3257 09:27:58.169405 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3258 09:27:58.173037 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3259 09:27:58.176230 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3260 09:27:58.179662 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3261 09:27:58.182653 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3262 09:27:58.189618 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3263 09:27:58.192954 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3264 09:27:58.193125 ==
3265 09:27:58.195975 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 09:27:58.199412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 09:27:58.199507 ==
3268 09:27:58.202561 DQS Delay:
3269 09:27:58.202648 DQS0 = 0, DQS1 = 0
3270 09:27:58.202714 DQM Delay:
3271 09:27:58.206158 DQM0 = 117, DQM1 = 109
3272 09:27:58.206256 DQ Delay:
3273 09:27:58.209339 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3274 09:27:58.212458 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3275 09:27:58.216081 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3276 09:27:58.222516 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3277 09:27:58.222627
3278 09:27:58.222734
3279 09:27:58.222795 ==
3280 09:27:58.225857 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 09:27:58.229082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 09:27:58.229177 ==
3283 09:27:58.229244
3284 09:27:58.229345
3285 09:27:58.232607 TX Vref Scan disable
3286 09:27:58.232692 == TX Byte 0 ==
3287 09:27:58.238988 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3288 09:27:58.242415 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3289 09:27:58.242530 == TX Byte 1 ==
3290 09:27:58.249170 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3291 09:27:58.253018 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3292 09:27:58.253137 ==
3293 09:27:58.255860 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 09:27:58.258734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 09:27:58.258836 ==
3296 09:27:58.272047 TX Vref=22, minBit 8, minWin=25, winSum=415
3297 09:27:58.275317 TX Vref=24, minBit 9, minWin=25, winSum=424
3298 09:27:58.278491 TX Vref=26, minBit 8, minWin=25, winSum=423
3299 09:27:58.282387 TX Vref=28, minBit 8, minWin=26, winSum=434
3300 09:27:58.285021 TX Vref=30, minBit 9, minWin=26, winSum=431
3301 09:27:58.288420 TX Vref=32, minBit 9, minWin=25, winSum=426
3302 09:27:58.295104 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3303 09:27:58.295217
3304 09:27:58.298199 Final TX Range 1 Vref 28
3305 09:27:58.298287
3306 09:27:58.298352 ==
3307 09:27:58.301614 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 09:27:58.304965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 09:27:58.305062 ==
3310 09:27:58.305130
3311 09:27:58.308794
3312 09:27:58.308881 TX Vref Scan disable
3313 09:27:58.312132 == TX Byte 0 ==
3314 09:27:58.315202 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 09:27:58.318620 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 09:27:58.321753 == TX Byte 1 ==
3317 09:27:58.324969 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3318 09:27:58.327938 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3319 09:27:58.331595
3320 09:27:58.331713 [DATLAT]
3321 09:27:58.331826 Freq=1200, CH1 RK0
3322 09:27:58.331888
3323 09:27:58.334584 DATLAT Default: 0xd
3324 09:27:58.334667 0, 0xFFFF, sum = 0
3325 09:27:58.338346 1, 0xFFFF, sum = 0
3326 09:27:58.338433 2, 0xFFFF, sum = 0
3327 09:27:58.341331 3, 0xFFFF, sum = 0
3328 09:27:58.344884 4, 0xFFFF, sum = 0
3329 09:27:58.344976 5, 0xFFFF, sum = 0
3330 09:27:58.347897 6, 0xFFFF, sum = 0
3331 09:27:58.348001 7, 0xFFFF, sum = 0
3332 09:27:58.351668 8, 0xFFFF, sum = 0
3333 09:27:58.351783 9, 0xFFFF, sum = 0
3334 09:27:58.355104 10, 0xFFFF, sum = 0
3335 09:27:58.355197 11, 0xFFFF, sum = 0
3336 09:27:58.358008 12, 0x0, sum = 1
3337 09:27:58.358095 13, 0x0, sum = 2
3338 09:27:58.360980 14, 0x0, sum = 3
3339 09:27:58.361068 15, 0x0, sum = 4
3340 09:27:58.365282 best_step = 13
3341 09:27:58.365373
3342 09:27:58.365445 ==
3343 09:27:58.368073 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 09:27:58.371312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 09:27:58.371423 ==
3346 09:27:58.371518 RX Vref Scan: 1
3347 09:27:58.371607
3348 09:27:58.374433 Set Vref Range= 32 -> 127
3349 09:27:58.374516
3350 09:27:58.377855 RX Vref 32 -> 127, step: 1
3351 09:27:58.377939
3352 09:27:58.381125 RX Delay -21 -> 252, step: 4
3353 09:27:58.381210
3354 09:27:58.384689 Set Vref, RX VrefLevel [Byte0]: 32
3355 09:27:58.387646 [Byte1]: 32
3356 09:27:58.387779
3357 09:27:58.391211 Set Vref, RX VrefLevel [Byte0]: 33
3358 09:27:58.394476 [Byte1]: 33
3359 09:27:58.397753
3360 09:27:58.397891 Set Vref, RX VrefLevel [Byte0]: 34
3361 09:27:58.401050 [Byte1]: 34
3362 09:27:58.405726
3363 09:27:58.405866 Set Vref, RX VrefLevel [Byte0]: 35
3364 09:27:58.409252 [Byte1]: 35
3365 09:27:58.413694
3366 09:27:58.413834 Set Vref, RX VrefLevel [Byte0]: 36
3367 09:27:58.416710 [Byte1]: 36
3368 09:27:58.421624
3369 09:27:58.421726 Set Vref, RX VrefLevel [Byte0]: 37
3370 09:27:58.424750 [Byte1]: 37
3371 09:27:58.429507
3372 09:27:58.429622 Set Vref, RX VrefLevel [Byte0]: 38
3373 09:27:58.432706 [Byte1]: 38
3374 09:27:58.437209
3375 09:27:58.437309 Set Vref, RX VrefLevel [Byte0]: 39
3376 09:27:58.440610 [Byte1]: 39
3377 09:27:58.445419
3378 09:27:58.445573 Set Vref, RX VrefLevel [Byte0]: 40
3379 09:27:58.448576 [Byte1]: 40
3380 09:27:58.453556
3381 09:27:58.453705 Set Vref, RX VrefLevel [Byte0]: 41
3382 09:27:58.456634 [Byte1]: 41
3383 09:27:58.461117
3384 09:27:58.461270 Set Vref, RX VrefLevel [Byte0]: 42
3385 09:27:58.464441 [Byte1]: 42
3386 09:27:58.469488
3387 09:27:58.469634 Set Vref, RX VrefLevel [Byte0]: 43
3388 09:27:58.472534 [Byte1]: 43
3389 09:27:58.477350
3390 09:27:58.477496 Set Vref, RX VrefLevel [Byte0]: 44
3391 09:27:58.480441 [Byte1]: 44
3392 09:27:58.485242
3393 09:27:58.485382 Set Vref, RX VrefLevel [Byte0]: 45
3394 09:27:58.488081 [Byte1]: 45
3395 09:27:58.492975
3396 09:27:58.493096 Set Vref, RX VrefLevel [Byte0]: 46
3397 09:27:58.496278 [Byte1]: 46
3398 09:27:58.500879
3399 09:27:58.501014 Set Vref, RX VrefLevel [Byte0]: 47
3400 09:27:58.504806 [Byte1]: 47
3401 09:27:58.509128
3402 09:27:58.509233 Set Vref, RX VrefLevel [Byte0]: 48
3403 09:27:58.511992 [Byte1]: 48
3404 09:27:58.516918
3405 09:27:58.517016 Set Vref, RX VrefLevel [Byte0]: 49
3406 09:27:58.520160 [Byte1]: 49
3407 09:27:58.525155
3408 09:27:58.525252 Set Vref, RX VrefLevel [Byte0]: 50
3409 09:27:58.527965 [Byte1]: 50
3410 09:27:58.533094
3411 09:27:58.533187 Set Vref, RX VrefLevel [Byte0]: 51
3412 09:27:58.535698 [Byte1]: 51
3413 09:27:58.540818
3414 09:27:58.540931 Set Vref, RX VrefLevel [Byte0]: 52
3415 09:27:58.543607 [Byte1]: 52
3416 09:27:58.548187
3417 09:27:58.548305 Set Vref, RX VrefLevel [Byte0]: 53
3418 09:27:58.552016 [Byte1]: 53
3419 09:27:58.556473
3420 09:27:58.556601 Set Vref, RX VrefLevel [Byte0]: 54
3421 09:27:58.559415 [Byte1]: 54
3422 09:27:58.564255
3423 09:27:58.564370 Set Vref, RX VrefLevel [Byte0]: 55
3424 09:27:58.567193 [Byte1]: 55
3425 09:27:58.571983
3426 09:27:58.572100 Set Vref, RX VrefLevel [Byte0]: 56
3427 09:27:58.575528 [Byte1]: 56
3428 09:27:58.580072
3429 09:27:58.580187 Set Vref, RX VrefLevel [Byte0]: 57
3430 09:27:58.583243 [Byte1]: 57
3431 09:27:58.587714
3432 09:27:58.587876 Set Vref, RX VrefLevel [Byte0]: 58
3433 09:27:58.591425 [Byte1]: 58
3434 09:27:58.596382
3435 09:27:58.596496 Set Vref, RX VrefLevel [Byte0]: 59
3436 09:27:58.599194 [Byte1]: 59
3437 09:27:58.604008
3438 09:27:58.604129 Set Vref, RX VrefLevel [Byte0]: 60
3439 09:27:58.607170 [Byte1]: 60
3440 09:27:58.611597
3441 09:27:58.611737 Set Vref, RX VrefLevel [Byte0]: 61
3442 09:27:58.615045 [Byte1]: 61
3443 09:27:58.619644
3444 09:27:58.619760 Set Vref, RX VrefLevel [Byte0]: 62
3445 09:27:58.622646 [Byte1]: 62
3446 09:27:58.627684
3447 09:27:58.627797 Set Vref, RX VrefLevel [Byte0]: 63
3448 09:27:58.630709 [Byte1]: 63
3449 09:27:58.635582
3450 09:27:58.635693 Set Vref, RX VrefLevel [Byte0]: 64
3451 09:27:58.638784 [Byte1]: 64
3452 09:27:58.643163
3453 09:27:58.643257 Set Vref, RX VrefLevel [Byte0]: 65
3454 09:27:58.649980 [Byte1]: 65
3455 09:27:58.650086
3456 09:27:58.653479 Set Vref, RX VrefLevel [Byte0]: 66
3457 09:27:58.656553 [Byte1]: 66
3458 09:27:58.656644
3459 09:27:58.660074 Final RX Vref Byte 0 = 52 to rank0
3460 09:27:58.663165 Final RX Vref Byte 1 = 54 to rank0
3461 09:27:58.666305 Final RX Vref Byte 0 = 52 to rank1
3462 09:27:58.669657 Final RX Vref Byte 1 = 54 to rank1==
3463 09:27:58.673286 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 09:27:58.676616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 09:27:58.676764 ==
3466 09:27:58.679685 DQS Delay:
3467 09:27:58.679805 DQS0 = 0, DQS1 = 0
3468 09:27:58.682975 DQM Delay:
3469 09:27:58.683073 DQM0 = 116, DQM1 = 110
3470 09:27:58.686118 DQ Delay:
3471 09:27:58.689483 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3472 09:27:58.693027 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3473 09:27:58.696597 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3474 09:27:58.699815 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3475 09:27:58.699943
3476 09:27:58.700042
3477 09:27:58.706025 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3478 09:27:58.709419 CH1 RK0: MR19=403, MR18=7FB
3479 09:27:58.715766 CH1_RK0: MR19=0x403, MR18=0x7FB, DQSOSC=407, MR23=63, INC=39, DEC=26
3480 09:27:58.715920
3481 09:27:58.719362 ----->DramcWriteLeveling(PI) begin...
3482 09:27:58.719473 ==
3483 09:27:58.722486 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 09:27:58.725698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 09:27:58.725798 ==
3486 09:27:58.729175 Write leveling (Byte 0): 24 => 24
3487 09:27:58.732601 Write leveling (Byte 1): 28 => 28
3488 09:27:58.736225 DramcWriteLeveling(PI) end<-----
3489 09:27:58.736337
3490 09:27:58.736434 ==
3491 09:27:58.739428 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 09:27:58.745953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 09:27:58.746220 ==
3494 09:27:58.746329 [Gating] SW mode calibration
3495 09:27:58.755712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3496 09:27:58.759157 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3497 09:27:58.762087 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
3498 09:27:58.768852 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 09:27:58.772092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 09:27:58.775662 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 09:27:58.782153 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 09:27:58.785360 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 09:27:58.788708 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
3504 09:27:58.795611 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
3505 09:27:58.798505 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 09:27:58.802211 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 09:27:58.809680 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 09:27:58.812058 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 09:27:58.814825 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 09:27:58.821959 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 09:27:58.825117 1 0 24 | B1->B0 | 3939 2827 | 0 1 | (0 0) (1 1)
3512 09:27:58.827975 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 09:27:58.834708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 09:27:58.837885 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 09:27:58.841806 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 09:27:58.847914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 09:27:58.851102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 09:27:58.854351 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 09:27:58.861601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 09:27:58.864296 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3521 09:27:58.867980 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:27:58.874603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 09:27:58.877617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 09:27:58.880803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 09:27:58.887413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 09:27:58.890793 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 09:27:58.894125 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 09:27:58.901352 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 09:27:58.903954 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 09:27:58.907322 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 09:27:58.914164 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 09:27:58.917634 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 09:27:58.920405 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 09:27:58.927101 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 09:27:58.930568 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3536 09:27:58.933591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3537 09:27:58.940136 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 09:27:58.943931 Total UI for P1: 0, mck2ui 16
3539 09:27:58.946867 best dqsien dly found for B0: ( 1, 3, 26)
3540 09:27:58.949950 Total UI for P1: 0, mck2ui 16
3541 09:27:58.953587 best dqsien dly found for B1: ( 1, 3, 26)
3542 09:27:58.957329 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3543 09:27:58.960176 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3544 09:27:58.960278
3545 09:27:58.963232 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3546 09:27:58.966687 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3547 09:27:58.969561 [Gating] SW calibration Done
3548 09:27:58.969693 ==
3549 09:27:58.973049 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 09:27:58.976428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 09:27:58.976556 ==
3552 09:27:58.979825 RX Vref Scan: 0
3553 09:27:58.979952
3554 09:27:58.982680 RX Vref 0 -> 0, step: 1
3555 09:27:58.982828
3556 09:27:58.982930 RX Delay -40 -> 252, step: 8
3557 09:27:58.989384 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3558 09:27:58.992927 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3559 09:27:58.996408 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3560 09:27:58.999443 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3561 09:27:59.005836 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3562 09:27:59.009188 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3563 09:27:59.012459 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3564 09:27:59.015677 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3565 09:27:59.019048 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3566 09:27:59.022445 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3567 09:27:59.029691 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3568 09:27:59.032047 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3569 09:27:59.035497 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3570 09:27:59.039309 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3571 09:27:59.045293 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3572 09:27:59.048946 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3573 09:27:59.049056 ==
3574 09:27:59.052594 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 09:27:59.055523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 09:27:59.055663 ==
3577 09:27:59.058454 DQS Delay:
3578 09:27:59.058546 DQS0 = 0, DQS1 = 0
3579 09:27:59.058614 DQM Delay:
3580 09:27:59.061918 DQM0 = 117, DQM1 = 110
3581 09:27:59.062009 DQ Delay:
3582 09:27:59.065539 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3583 09:27:59.069052 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3584 09:27:59.075441 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3585 09:27:59.078413 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3586 09:27:59.078511
3587 09:27:59.078577
3588 09:27:59.078638 ==
3589 09:27:59.082171 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 09:27:59.085283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 09:27:59.085381 ==
3592 09:27:59.085447
3593 09:27:59.085507
3594 09:27:59.088724 TX Vref Scan disable
3595 09:27:59.088810 == TX Byte 0 ==
3596 09:27:59.095200 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3597 09:27:59.098263 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3598 09:27:59.101746 == TX Byte 1 ==
3599 09:27:59.105388 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 09:27:59.108276 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 09:27:59.108375 ==
3602 09:27:59.111577 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 09:27:59.114967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 09:27:59.115066 ==
3605 09:27:59.128720 TX Vref=22, minBit 8, minWin=25, winSum=425
3606 09:27:59.131473 TX Vref=24, minBit 8, minWin=26, winSum=432
3607 09:27:59.134778 TX Vref=26, minBit 8, minWin=26, winSum=432
3608 09:27:59.138122 TX Vref=28, minBit 8, minWin=26, winSum=434
3609 09:27:59.141728 TX Vref=30, minBit 8, minWin=26, winSum=435
3610 09:27:59.148222 TX Vref=32, minBit 9, minWin=25, winSum=430
3611 09:27:59.151602 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3612 09:27:59.151712
3613 09:27:59.154621 Final TX Range 1 Vref 30
3614 09:27:59.154714
3615 09:27:59.154780 ==
3616 09:27:59.158457 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 09:27:59.161247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 09:27:59.164821 ==
3619 09:27:59.164926
3620 09:27:59.164993
3621 09:27:59.165055 TX Vref Scan disable
3622 09:27:59.167702 == TX Byte 0 ==
3623 09:27:59.171123 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3624 09:27:59.177852 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3625 09:27:59.177972 == TX Byte 1 ==
3626 09:27:59.181176 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 09:27:59.187990 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 09:27:59.188114
3629 09:27:59.188184 [DATLAT]
3630 09:27:59.188246 Freq=1200, CH1 RK1
3631 09:27:59.188306
3632 09:27:59.191321 DATLAT Default: 0xd
3633 09:27:59.191407 0, 0xFFFF, sum = 0
3634 09:27:59.194360 1, 0xFFFF, sum = 0
3635 09:27:59.197900 2, 0xFFFF, sum = 0
3636 09:27:59.197995 3, 0xFFFF, sum = 0
3637 09:27:59.201325 4, 0xFFFF, sum = 0
3638 09:27:59.201416 5, 0xFFFF, sum = 0
3639 09:27:59.204174 6, 0xFFFF, sum = 0
3640 09:27:59.204263 7, 0xFFFF, sum = 0
3641 09:27:59.207562 8, 0xFFFF, sum = 0
3642 09:27:59.207692 9, 0xFFFF, sum = 0
3643 09:27:59.210820 10, 0xFFFF, sum = 0
3644 09:27:59.210929 11, 0xFFFF, sum = 0
3645 09:27:59.213955 12, 0x0, sum = 1
3646 09:27:59.214061 13, 0x0, sum = 2
3647 09:27:59.217703 14, 0x0, sum = 3
3648 09:27:59.217800 15, 0x0, sum = 4
3649 09:27:59.220624 best_step = 13
3650 09:27:59.220711
3651 09:27:59.220776 ==
3652 09:27:59.224223 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 09:27:59.227574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 09:27:59.227667 ==
3655 09:27:59.227761 RX Vref Scan: 0
3656 09:27:59.230831
3657 09:27:59.230916 RX Vref 0 -> 0, step: 1
3658 09:27:59.230981
3659 09:27:59.233826 RX Delay -21 -> 252, step: 4
3660 09:27:59.240620 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3661 09:27:59.243685 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3662 09:27:59.247227 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3663 09:27:59.250781 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3664 09:27:59.254130 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3665 09:27:59.260908 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3666 09:27:59.263562 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3667 09:27:59.267091 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3668 09:27:59.270534 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3669 09:27:59.274041 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3670 09:27:59.280480 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3671 09:27:59.283697 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3672 09:27:59.286811 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3673 09:27:59.290328 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3674 09:27:59.293416 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3675 09:27:59.300313 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3676 09:27:59.300435 ==
3677 09:27:59.303616 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 09:27:59.306550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 09:27:59.306647 ==
3680 09:27:59.306714 DQS Delay:
3681 09:27:59.310073 DQS0 = 0, DQS1 = 0
3682 09:27:59.310163 DQM Delay:
3683 09:27:59.313981 DQM0 = 117, DQM1 = 110
3684 09:27:59.314073 DQ Delay:
3685 09:27:59.316792 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3686 09:27:59.319786 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3687 09:27:59.323581 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3688 09:27:59.327102 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3689 09:27:59.327206
3690 09:27:59.329813
3691 09:27:59.336541 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3692 09:27:59.339670 CH1 RK1: MR19=303, MR18=F5F0
3693 09:27:59.346371 CH1_RK1: MR19=0x303, MR18=0xF5F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3694 09:27:59.349554 [RxdqsGatingPostProcess] freq 1200
3695 09:27:59.352979 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 09:27:59.356613 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 09:27:59.359403 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 09:27:59.363224 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 09:27:59.366461 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 09:27:59.369264 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 09:27:59.372685 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 09:27:59.376472 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 09:27:59.379614 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 09:27:59.382593 Pre-setting of DQS Precalculation
3705 09:27:59.386215 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 09:27:59.396096 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 09:27:59.402245 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 09:27:59.402398
3709 09:27:59.402470
3710 09:27:59.405411 [Calibration Summary] 2400 Mbps
3711 09:27:59.405542 CH 0, Rank 0
3712 09:27:59.409132 SW Impedance : PASS
3713 09:27:59.409232 DUTY Scan : NO K
3714 09:27:59.412157 ZQ Calibration : PASS
3715 09:27:59.415421 Jitter Meter : NO K
3716 09:27:59.415516 CBT Training : PASS
3717 09:27:59.418648 Write leveling : PASS
3718 09:27:59.421963 RX DQS gating : PASS
3719 09:27:59.422097 RX DQ/DQS(RDDQC) : PASS
3720 09:27:59.425051 TX DQ/DQS : PASS
3721 09:27:59.428463 RX DATLAT : PASS
3722 09:27:59.428586 RX DQ/DQS(Engine): PASS
3723 09:27:59.431802 TX OE : NO K
3724 09:27:59.431923 All Pass.
3725 09:27:59.432004
3726 09:27:59.435163 CH 0, Rank 1
3727 09:27:59.435255 SW Impedance : PASS
3728 09:27:59.438169 DUTY Scan : NO K
3729 09:27:59.442099 ZQ Calibration : PASS
3730 09:27:59.442220 Jitter Meter : NO K
3731 09:27:59.445169 CBT Training : PASS
3732 09:27:59.448586 Write leveling : PASS
3733 09:27:59.448701 RX DQS gating : PASS
3734 09:27:59.451838 RX DQ/DQS(RDDQC) : PASS
3735 09:27:59.454889 TX DQ/DQS : PASS
3736 09:27:59.455062 RX DATLAT : PASS
3737 09:27:59.458365 RX DQ/DQS(Engine): PASS
3738 09:27:59.458467 TX OE : NO K
3739 09:27:59.462246 All Pass.
3740 09:27:59.462351
3741 09:27:59.462432 CH 1, Rank 0
3742 09:27:59.464963 SW Impedance : PASS
3743 09:27:59.465048 DUTY Scan : NO K
3744 09:27:59.468508 ZQ Calibration : PASS
3745 09:27:59.471597 Jitter Meter : NO K
3746 09:27:59.471711 CBT Training : PASS
3747 09:27:59.474738 Write leveling : PASS
3748 09:27:59.478501 RX DQS gating : PASS
3749 09:27:59.478630 RX DQ/DQS(RDDQC) : PASS
3750 09:27:59.481475 TX DQ/DQS : PASS
3751 09:27:59.484691 RX DATLAT : PASS
3752 09:27:59.484822 RX DQ/DQS(Engine): PASS
3753 09:27:59.487954 TX OE : NO K
3754 09:27:59.488074 All Pass.
3755 09:27:59.488173
3756 09:27:59.491330 CH 1, Rank 1
3757 09:27:59.491445 SW Impedance : PASS
3758 09:27:59.494978 DUTY Scan : NO K
3759 09:27:59.498255 ZQ Calibration : PASS
3760 09:27:59.498370 Jitter Meter : NO K
3761 09:27:59.501146 CBT Training : PASS
3762 09:27:59.504372 Write leveling : PASS
3763 09:27:59.504489 RX DQS gating : PASS
3764 09:27:59.507560 RX DQ/DQS(RDDQC) : PASS
3765 09:27:59.510851 TX DQ/DQS : PASS
3766 09:27:59.510973 RX DATLAT : PASS
3767 09:27:59.514683 RX DQ/DQS(Engine): PASS
3768 09:27:59.517722 TX OE : NO K
3769 09:27:59.517853 All Pass.
3770 09:27:59.517946
3771 09:27:59.518045 DramC Write-DBI off
3772 09:27:59.520679 PER_BANK_REFRESH: Hybrid Mode
3773 09:27:59.524249 TX_TRACKING: ON
3774 09:27:59.530699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 09:27:59.534036 [FAST_K] Save calibration result to emmc
3776 09:27:59.541045 dramc_set_vcore_voltage set vcore to 650000
3777 09:27:59.541190 Read voltage for 600, 5
3778 09:27:59.544242 Vio18 = 0
3779 09:27:59.544375 Vcore = 650000
3780 09:27:59.544469 Vdram = 0
3781 09:27:59.547496 Vddq = 0
3782 09:27:59.547601 Vmddr = 0
3783 09:27:59.551071 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 09:27:59.557268 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 09:27:59.560449 MEM_TYPE=3, freq_sel=19
3786 09:27:59.563693 sv_algorithm_assistance_LP4_1600
3787 09:27:59.567521 ============ PULL DRAM RESETB DOWN ============
3788 09:27:59.570455 ========== PULL DRAM RESETB DOWN end =========
3789 09:27:59.577161 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 09:27:59.577269 ===================================
3791 09:27:59.580544 LPDDR4 DRAM CONFIGURATION
3792 09:27:59.584005 ===================================
3793 09:27:59.587145 EX_ROW_EN[0] = 0x0
3794 09:27:59.587237 EX_ROW_EN[1] = 0x0
3795 09:27:59.590718 LP4Y_EN = 0x0
3796 09:27:59.590808 WORK_FSP = 0x0
3797 09:27:59.593838 WL = 0x2
3798 09:27:59.593926 RL = 0x2
3799 09:27:59.597061 BL = 0x2
3800 09:27:59.597148 RPST = 0x0
3801 09:27:59.600456 RD_PRE = 0x0
3802 09:27:59.604293 WR_PRE = 0x1
3803 09:27:59.604386 WR_PST = 0x0
3804 09:27:59.607231 DBI_WR = 0x0
3805 09:27:59.607318 DBI_RD = 0x0
3806 09:27:59.610263 OTF = 0x1
3807 09:27:59.613499 ===================================
3808 09:27:59.616911 ===================================
3809 09:27:59.617038 ANA top config
3810 09:27:59.620125 ===================================
3811 09:27:59.623563 DLL_ASYNC_EN = 0
3812 09:27:59.626885 ALL_SLAVE_EN = 1
3813 09:27:59.626975 NEW_RANK_MODE = 1
3814 09:27:59.630372 DLL_IDLE_MODE = 1
3815 09:27:59.633604 LP45_APHY_COMB_EN = 1
3816 09:27:59.636789 TX_ODT_DIS = 1
3817 09:27:59.636883 NEW_8X_MODE = 1
3818 09:27:59.639913 ===================================
3819 09:27:59.643191 ===================================
3820 09:27:59.646649 data_rate = 1200
3821 09:27:59.649792 CKR = 1
3822 09:27:59.653412 DQ_P2S_RATIO = 8
3823 09:27:59.656549 ===================================
3824 09:27:59.659587 CA_P2S_RATIO = 8
3825 09:27:59.662906 DQ_CA_OPEN = 0
3826 09:27:59.666404 DQ_SEMI_OPEN = 0
3827 09:27:59.666539 CA_SEMI_OPEN = 0
3828 09:27:59.669571 CA_FULL_RATE = 0
3829 09:27:59.672902 DQ_CKDIV4_EN = 1
3830 09:27:59.676733 CA_CKDIV4_EN = 1
3831 09:27:59.679865 CA_PREDIV_EN = 0
3832 09:27:59.683094 PH8_DLY = 0
3833 09:27:59.683187 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 09:27:59.686129 DQ_AAMCK_DIV = 4
3835 09:27:59.689719 CA_AAMCK_DIV = 4
3836 09:27:59.693147 CA_ADMCK_DIV = 4
3837 09:27:59.696274 DQ_TRACK_CA_EN = 0
3838 09:27:59.699302 CA_PICK = 600
3839 09:27:59.699392 CA_MCKIO = 600
3840 09:27:59.703242 MCKIO_SEMI = 0
3841 09:27:59.706320 PLL_FREQ = 2288
3842 09:27:59.709940 DQ_UI_PI_RATIO = 32
3843 09:27:59.713150 CA_UI_PI_RATIO = 0
3844 09:27:59.716215 ===================================
3845 09:27:59.719691 ===================================
3846 09:27:59.722457 memory_type:LPDDR4
3847 09:27:59.722579 GP_NUM : 10
3848 09:27:59.726201 SRAM_EN : 1
3849 09:27:59.726291 MD32_EN : 0
3850 09:27:59.729319 ===================================
3851 09:27:59.732555 [ANA_INIT] >>>>>>>>>>>>>>
3852 09:27:59.735604 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 09:27:59.739146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 09:27:59.742282 ===================================
3855 09:27:59.747280 data_rate = 1200,PCW = 0X5800
3856 09:27:59.749690 ===================================
3857 09:27:59.752421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 09:27:59.759121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 09:27:59.762126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 09:27:59.768770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 09:27:59.772173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 09:27:59.775608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 09:27:59.775737 [ANA_INIT] flow start
3864 09:27:59.779053 [ANA_INIT] PLL >>>>>>>>
3865 09:27:59.782070 [ANA_INIT] PLL <<<<<<<<
3866 09:27:59.785673 [ANA_INIT] MIDPI >>>>>>>>
3867 09:27:59.785774 [ANA_INIT] MIDPI <<<<<<<<
3868 09:27:59.788496 [ANA_INIT] DLL >>>>>>>>
3869 09:27:59.792010 [ANA_INIT] flow end
3870 09:27:59.794924 ============ LP4 DIFF to SE enter ============
3871 09:27:59.798234 ============ LP4 DIFF to SE exit ============
3872 09:27:59.801589 [ANA_INIT] <<<<<<<<<<<<<
3873 09:27:59.805554 [Flow] Enable top DCM control >>>>>
3874 09:27:59.808402 [Flow] Enable top DCM control <<<<<
3875 09:27:59.811701 Enable DLL master slave shuffle
3876 09:27:59.814952 ==============================================================
3877 09:27:59.818252 Gating Mode config
3878 09:27:59.824511 ==============================================================
3879 09:27:59.824622 Config description:
3880 09:27:59.834611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 09:27:59.841217 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 09:27:59.844862 SELPH_MODE 0: By rank 1: By Phase
3883 09:27:59.851043 ==============================================================
3884 09:27:59.854408 GAT_TRACK_EN = 1
3885 09:27:59.857644 RX_GATING_MODE = 2
3886 09:27:59.861073 RX_GATING_TRACK_MODE = 2
3887 09:27:59.864556 SELPH_MODE = 1
3888 09:27:59.867569 PICG_EARLY_EN = 1
3889 09:27:59.870770 VALID_LAT_VALUE = 1
3890 09:27:59.873890 ==============================================================
3891 09:27:59.877689 Enter into Gating configuration >>>>
3892 09:27:59.880604 Exit from Gating configuration <<<<
3893 09:27:59.884459 Enter into DVFS_PRE_config >>>>>
3894 09:27:59.897252 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 09:27:59.900725 Exit from DVFS_PRE_config <<<<<
3896 09:27:59.904290 Enter into PICG configuration >>>>
3897 09:27:59.907136 Exit from PICG configuration <<<<
3898 09:27:59.907234 [RX_INPUT] configuration >>>>>
3899 09:27:59.910305 [RX_INPUT] configuration <<<<<
3900 09:27:59.916973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 09:27:59.920732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 09:27:59.926879 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 09:27:59.933728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 09:27:59.939885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 09:27:59.946650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 09:27:59.949968 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 09:27:59.953199 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 09:27:59.959932 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 09:27:59.963638 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 09:27:59.966636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 09:27:59.970066 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 09:27:59.973475 ===================================
3913 09:27:59.976567 LPDDR4 DRAM CONFIGURATION
3914 09:27:59.979563 ===================================
3915 09:27:59.983176 EX_ROW_EN[0] = 0x0
3916 09:27:59.983258 EX_ROW_EN[1] = 0x0
3917 09:27:59.986358 LP4Y_EN = 0x0
3918 09:27:59.986439 WORK_FSP = 0x0
3919 09:27:59.989854 WL = 0x2
3920 09:27:59.989934 RL = 0x2
3921 09:27:59.994014 BL = 0x2
3922 09:27:59.994094 RPST = 0x0
3923 09:27:59.996611 RD_PRE = 0x0
3924 09:27:59.996701 WR_PRE = 0x1
3925 09:27:59.999517 WR_PST = 0x0
3926 09:28:00.003381 DBI_WR = 0x0
3927 09:28:00.003458 DBI_RD = 0x0
3928 09:28:00.006224 OTF = 0x1
3929 09:28:00.009806 ===================================
3930 09:28:00.012929 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 09:28:00.016339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 09:28:00.019446 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 09:28:00.023242 ===================================
3934 09:28:00.026189 LPDDR4 DRAM CONFIGURATION
3935 09:28:00.029323 ===================================
3936 09:28:00.032464 EX_ROW_EN[0] = 0x10
3937 09:28:00.032545 EX_ROW_EN[1] = 0x0
3938 09:28:00.035991 LP4Y_EN = 0x0
3939 09:28:00.036072 WORK_FSP = 0x0
3940 09:28:00.039392 WL = 0x2
3941 09:28:00.039473 RL = 0x2
3942 09:28:00.042525 BL = 0x2
3943 09:28:00.045904 RPST = 0x0
3944 09:28:00.045986 RD_PRE = 0x0
3945 09:28:00.049199 WR_PRE = 0x1
3946 09:28:00.049300 WR_PST = 0x0
3947 09:28:00.052523 DBI_WR = 0x0
3948 09:28:00.052606 DBI_RD = 0x0
3949 09:28:00.055681 OTF = 0x1
3950 09:28:00.058939 ===================================
3951 09:28:00.065582 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 09:28:00.068682 nWR fixed to 30
3953 09:28:00.068765 [ModeRegInit_LP4] CH0 RK0
3954 09:28:00.072280 [ModeRegInit_LP4] CH0 RK1
3955 09:28:00.075785 [ModeRegInit_LP4] CH1 RK0
3956 09:28:00.075868 [ModeRegInit_LP4] CH1 RK1
3957 09:28:00.078674 match AC timing 17
3958 09:28:00.081965 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 09:28:00.085498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 09:28:00.091870 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 09:28:00.095641 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 09:28:00.102224 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 09:28:00.102306 ==
3964 09:28:00.104901 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 09:28:00.108472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 09:28:00.108554 ==
3967 09:28:00.115123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 09:28:00.121479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3969 09:28:00.125049 [CA 0] Center 36 (6~66) winsize 61
3970 09:28:00.128079 [CA 1] Center 36 (6~66) winsize 61
3971 09:28:00.131345 [CA 2] Center 34 (4~65) winsize 62
3972 09:28:00.134790 [CA 3] Center 34 (4~65) winsize 62
3973 09:28:00.138051 [CA 4] Center 33 (3~64) winsize 62
3974 09:28:00.141556 [CA 5] Center 33 (3~64) winsize 62
3975 09:28:00.141636
3976 09:28:00.144281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3977 09:28:00.144361
3978 09:28:00.147861 [CATrainingPosCal] consider 1 rank data
3979 09:28:00.151108 u2DelayCellTimex100 = 270/100 ps
3980 09:28:00.154412 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3981 09:28:00.157602 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3982 09:28:00.160946 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 09:28:00.164118 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3984 09:28:00.167680 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 09:28:00.171218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 09:28:00.174049
3987 09:28:00.177630 CA PerBit enable=1, Macro0, CA PI delay=33
3988 09:28:00.177774
3989 09:28:00.180809 [CBTSetCACLKResult] CA Dly = 33
3990 09:28:00.180914 CS Dly: 5 (0~36)
3991 09:28:00.180981 ==
3992 09:28:00.184103 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 09:28:00.187149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 09:28:00.187241 ==
3995 09:28:00.193872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 09:28:00.200726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 09:28:00.203756 [CA 0] Center 35 (5~66) winsize 62
3998 09:28:00.207212 [CA 1] Center 36 (6~66) winsize 61
3999 09:28:00.210328 [CA 2] Center 34 (3~65) winsize 63
4000 09:28:00.213694 [CA 3] Center 33 (3~64) winsize 62
4001 09:28:00.216768 [CA 4] Center 33 (2~64) winsize 63
4002 09:28:00.220423 [CA 5] Center 33 (2~64) winsize 63
4003 09:28:00.220506
4004 09:28:00.223611 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 09:28:00.223692
4006 09:28:00.227059 [CATrainingPosCal] consider 2 rank data
4007 09:28:00.230180 u2DelayCellTimex100 = 270/100 ps
4008 09:28:00.233472 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4009 09:28:00.236745 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4010 09:28:00.240315 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4011 09:28:00.246859 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4012 09:28:00.250681 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 09:28:00.253342 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4014 09:28:00.253425
4015 09:28:00.256775 CA PerBit enable=1, Macro0, CA PI delay=33
4016 09:28:00.256856
4017 09:28:00.260041 [CBTSetCACLKResult] CA Dly = 33
4018 09:28:00.260122 CS Dly: 5 (0~36)
4019 09:28:00.260187
4020 09:28:00.263089 ----->DramcWriteLeveling(PI) begin...
4021 09:28:00.263172 ==
4022 09:28:00.266802 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 09:28:00.273207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 09:28:00.273289 ==
4025 09:28:00.277038 Write leveling (Byte 0): 31 => 31
4026 09:28:00.279851 Write leveling (Byte 1): 27 => 27
4027 09:28:00.283465 DramcWriteLeveling(PI) end<-----
4028 09:28:00.283547
4029 09:28:00.283612 ==
4030 09:28:00.286238 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 09:28:00.289725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 09:28:00.289807 ==
4033 09:28:00.292829 [Gating] SW mode calibration
4034 09:28:00.299457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 09:28:00.306039 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 09:28:00.309476 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 09:28:00.313064 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 09:28:00.319507 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 09:28:00.323221 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (0 1)
4040 09:28:00.325952 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (0 1) (1 1)
4041 09:28:00.329226 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 09:28:00.336042 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 09:28:00.339419 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 09:28:00.342641 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 09:28:00.349293 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 09:28:00.352434 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 09:28:00.355685 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4048 09:28:00.362477 0 10 16 | B1->B0 | 3434 4040 | 0 0 | (1 1) (0 0)
4049 09:28:00.365691 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 09:28:00.368857 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 09:28:00.375678 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 09:28:00.378833 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 09:28:00.382674 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 09:28:00.388588 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 09:28:00.392096 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4056 09:28:00.395599 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:28:00.401923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:28:00.405788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:28:00.409058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:28:00.415533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:28:00.418549 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 09:28:00.422283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 09:28:00.428378 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 09:28:00.432077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 09:28:00.434994 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 09:28:00.441602 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 09:28:00.444810 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 09:28:00.448620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 09:28:00.454980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 09:28:00.458079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 09:28:00.461616 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4072 09:28:00.468412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 09:28:00.471544 Total UI for P1: 0, mck2ui 16
4074 09:28:00.474569 best dqsien dly found for B0: ( 0, 13, 12)
4075 09:28:00.474650 Total UI for P1: 0, mck2ui 16
4076 09:28:00.481454 best dqsien dly found for B1: ( 0, 13, 14)
4077 09:28:00.484568 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4078 09:28:00.488272 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4079 09:28:00.488356
4080 09:28:00.491391 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 09:28:00.494702 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4082 09:28:00.497963 [Gating] SW calibration Done
4083 09:28:00.498043 ==
4084 09:28:00.501129 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 09:28:00.504202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 09:28:00.504297 ==
4087 09:28:00.508023 RX Vref Scan: 0
4088 09:28:00.508118
4089 09:28:00.510605 RX Vref 0 -> 0, step: 1
4090 09:28:00.510685
4091 09:28:00.510749 RX Delay -230 -> 252, step: 16
4092 09:28:00.517512 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4093 09:28:00.521440 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4094 09:28:00.523984 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4095 09:28:00.527445 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4096 09:28:00.534108 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4097 09:28:00.537528 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4098 09:28:00.540735 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4099 09:28:00.543697 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4100 09:28:00.550399 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4101 09:28:00.553841 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4102 09:28:00.557626 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4103 09:28:00.560399 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4104 09:28:00.566950 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4105 09:28:00.570252 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4106 09:28:00.573474 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4107 09:28:00.577009 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4108 09:28:00.577089 ==
4109 09:28:00.579984 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 09:28:00.586960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 09:28:00.587040 ==
4112 09:28:00.587104 DQS Delay:
4113 09:28:00.590131 DQS0 = 0, DQS1 = 0
4114 09:28:00.590211 DQM Delay:
4115 09:28:00.590275 DQM0 = 43, DQM1 = 33
4116 09:28:00.593786 DQ Delay:
4117 09:28:00.596582 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4118 09:28:00.599710 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4119 09:28:00.602907 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4120 09:28:00.606301 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4121 09:28:00.606382
4122 09:28:00.606445
4123 09:28:00.606504 ==
4124 09:28:00.609987 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 09:28:00.612795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 09:28:00.612875 ==
4127 09:28:00.612938
4128 09:28:00.612997
4129 09:28:00.616211 TX Vref Scan disable
4130 09:28:00.619681 == TX Byte 0 ==
4131 09:28:00.622966 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4132 09:28:00.626005 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4133 09:28:00.629232 == TX Byte 1 ==
4134 09:28:00.632655 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4135 09:28:00.635870 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4136 09:28:00.635950 ==
4137 09:28:00.639414 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 09:28:00.645760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 09:28:00.645842 ==
4140 09:28:00.645907
4141 09:28:00.645966
4142 09:28:00.646022 TX Vref Scan disable
4143 09:28:00.650045 == TX Byte 0 ==
4144 09:28:00.653367 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4145 09:28:00.660548 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4146 09:28:00.660629 == TX Byte 1 ==
4147 09:28:00.664470 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4148 09:28:00.670295 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4149 09:28:00.670377
4150 09:28:00.670441 [DATLAT]
4151 09:28:00.670500 Freq=600, CH0 RK0
4152 09:28:00.670559
4153 09:28:00.673512 DATLAT Default: 0x9
4154 09:28:00.673593 0, 0xFFFF, sum = 0
4155 09:28:00.676705 1, 0xFFFF, sum = 0
4156 09:28:00.680204 2, 0xFFFF, sum = 0
4157 09:28:00.680287 3, 0xFFFF, sum = 0
4158 09:28:00.683256 4, 0xFFFF, sum = 0
4159 09:28:00.683339 5, 0xFFFF, sum = 0
4160 09:28:00.686344 6, 0xFFFF, sum = 0
4161 09:28:00.686427 7, 0xFFFF, sum = 0
4162 09:28:00.689771 8, 0x0, sum = 1
4163 09:28:00.689856 9, 0x0, sum = 2
4164 09:28:00.689923 10, 0x0, sum = 3
4165 09:28:00.692928 11, 0x0, sum = 4
4166 09:28:00.693000 best_step = 9
4167 09:28:00.693061
4168 09:28:00.696299 ==
4169 09:28:00.696381 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 09:28:00.703223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 09:28:00.703305 ==
4172 09:28:00.703370 RX Vref Scan: 1
4173 09:28:00.703431
4174 09:28:00.706327 RX Vref 0 -> 0, step: 1
4175 09:28:00.706412
4176 09:28:00.710248 RX Delay -195 -> 252, step: 8
4177 09:28:00.710363
4178 09:28:00.712592 Set Vref, RX VrefLevel [Byte0]: 59
4179 09:28:00.716135 [Byte1]: 59
4180 09:28:00.716222
4181 09:28:00.719275 Final RX Vref Byte 0 = 59 to rank0
4182 09:28:00.722915 Final RX Vref Byte 1 = 59 to rank0
4183 09:28:00.726033 Final RX Vref Byte 0 = 59 to rank1
4184 09:28:00.729424 Final RX Vref Byte 1 = 59 to rank1==
4185 09:28:00.732694 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 09:28:00.735926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 09:28:00.739390 ==
4188 09:28:00.739471 DQS Delay:
4189 09:28:00.739536 DQS0 = 0, DQS1 = 0
4190 09:28:00.742583 DQM Delay:
4191 09:28:00.742691 DQM0 = 44, DQM1 = 32
4192 09:28:00.745849 DQ Delay:
4193 09:28:00.749211 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4194 09:28:00.749293 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4195 09:28:00.752143 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4196 09:28:00.758750 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4197 09:28:00.758832
4198 09:28:00.758898
4199 09:28:00.765727 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4200 09:28:00.768480 CH0 RK0: MR19=808, MR18=6C44
4201 09:28:00.775285 CH0_RK0: MR19=0x808, MR18=0x6C44, DQSOSC=389, MR23=63, INC=173, DEC=115
4202 09:28:00.775367
4203 09:28:00.778545 ----->DramcWriteLeveling(PI) begin...
4204 09:28:00.778628 ==
4205 09:28:00.781878 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 09:28:00.784790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 09:28:00.784909 ==
4208 09:28:00.788236 Write leveling (Byte 0): 31 => 31
4209 09:28:00.791500 Write leveling (Byte 1): 30 => 30
4210 09:28:00.795026 DramcWriteLeveling(PI) end<-----
4211 09:28:00.795108
4212 09:28:00.795172 ==
4213 09:28:00.798186 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 09:28:00.801381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 09:28:00.804685 ==
4216 09:28:00.804767 [Gating] SW mode calibration
4217 09:28:00.811387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 09:28:00.818377 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 09:28:00.821381 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 09:28:00.828416 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 09:28:00.831255 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 09:28:00.834648 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4223 09:28:00.841153 0 9 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
4224 09:28:00.844611 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 09:28:00.847584 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 09:28:00.854659 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 09:28:00.858038 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 09:28:00.860831 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 09:28:00.867554 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 09:28:00.870741 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4231 09:28:00.874085 0 10 16 | B1->B0 | 3939 4242 | 0 1 | (0 0) (0 0)
4232 09:28:00.880705 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 09:28:00.884055 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 09:28:00.887301 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 09:28:00.893664 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 09:28:00.897263 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 09:28:00.900290 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 09:28:00.906692 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4239 09:28:00.910132 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:28:00.913545 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:28:00.920208 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:28:00.923513 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 09:28:00.926633 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 09:28:00.933476 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 09:28:00.936526 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 09:28:00.940058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 09:28:00.946374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 09:28:00.949920 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 09:28:00.953226 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 09:28:00.959639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 09:28:00.963427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 09:28:00.966240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 09:28:00.972818 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 09:28:00.976550 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4255 09:28:00.979702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4256 09:28:00.983361 Total UI for P1: 0, mck2ui 16
4257 09:28:00.985955 best dqsien dly found for B0: ( 0, 13, 12)
4258 09:28:00.992585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 09:28:00.992666 Total UI for P1: 0, mck2ui 16
4260 09:28:00.999570 best dqsien dly found for B1: ( 0, 13, 14)
4261 09:28:01.003082 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 09:28:01.006139 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4263 09:28:01.006219
4264 09:28:01.009251 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 09:28:01.012534 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4266 09:28:01.015559 [Gating] SW calibration Done
4267 09:28:01.015639 ==
4268 09:28:01.019027 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 09:28:01.022145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 09:28:01.022226 ==
4271 09:28:01.025465 RX Vref Scan: 0
4272 09:28:01.025545
4273 09:28:01.028791 RX Vref 0 -> 0, step: 1
4274 09:28:01.028871
4275 09:28:01.028935 RX Delay -230 -> 252, step: 16
4276 09:28:01.035241 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4277 09:28:01.038816 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4278 09:28:01.042898 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4279 09:28:01.045770 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4280 09:28:01.052013 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4281 09:28:01.055294 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4282 09:28:01.058595 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4283 09:28:01.062124 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4284 09:28:01.068567 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4285 09:28:01.072398 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4286 09:28:01.075262 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4287 09:28:01.078634 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4288 09:28:01.081831 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4289 09:28:01.088478 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4290 09:28:01.092013 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4291 09:28:01.095100 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4292 09:28:01.095180 ==
4293 09:28:01.098383 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 09:28:01.105127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 09:28:01.105208 ==
4296 09:28:01.105272 DQS Delay:
4297 09:28:01.108583 DQS0 = 0, DQS1 = 0
4298 09:28:01.108663 DQM Delay:
4299 09:28:01.108727 DQM0 = 42, DQM1 = 36
4300 09:28:01.111244 DQ Delay:
4301 09:28:01.114748 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4302 09:28:01.118366 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4303 09:28:01.121516 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4304 09:28:01.124930 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4305 09:28:01.125009
4306 09:28:01.125072
4307 09:28:01.125130 ==
4308 09:28:01.128023 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 09:28:01.131302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 09:28:01.131382 ==
4311 09:28:01.131445
4312 09:28:01.131503
4313 09:28:01.134408 TX Vref Scan disable
4314 09:28:01.137897 == TX Byte 0 ==
4315 09:28:01.140933 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4316 09:28:01.144541 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4317 09:28:01.148209 == TX Byte 1 ==
4318 09:28:01.150980 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4319 09:28:01.154848 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4320 09:28:01.154928 ==
4321 09:28:01.158024 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 09:28:01.161374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 09:28:01.161454 ==
4324 09:28:01.164643
4325 09:28:01.164721
4326 09:28:01.164783 TX Vref Scan disable
4327 09:28:01.167978 == TX Byte 0 ==
4328 09:28:01.171604 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4329 09:28:01.177942 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4330 09:28:01.178023 == TX Byte 1 ==
4331 09:28:01.181326 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4332 09:28:01.187732 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4333 09:28:01.187813
4334 09:28:01.187876 [DATLAT]
4335 09:28:01.187935 Freq=600, CH0 RK1
4336 09:28:01.187991
4337 09:28:01.191884 DATLAT Default: 0x9
4338 09:28:01.194657 0, 0xFFFF, sum = 0
4339 09:28:01.194737 1, 0xFFFF, sum = 0
4340 09:28:01.198044 2, 0xFFFF, sum = 0
4341 09:28:01.198124 3, 0xFFFF, sum = 0
4342 09:28:01.201224 4, 0xFFFF, sum = 0
4343 09:28:01.201305 5, 0xFFFF, sum = 0
4344 09:28:01.204761 6, 0xFFFF, sum = 0
4345 09:28:01.204841 7, 0xFFFF, sum = 0
4346 09:28:01.207608 8, 0x0, sum = 1
4347 09:28:01.207688 9, 0x0, sum = 2
4348 09:28:01.207797 10, 0x0, sum = 3
4349 09:28:01.211070 11, 0x0, sum = 4
4350 09:28:01.211151 best_step = 9
4351 09:28:01.211214
4352 09:28:01.214323 ==
4353 09:28:01.214403 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 09:28:01.221077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 09:28:01.221156 ==
4356 09:28:01.221221 RX Vref Scan: 0
4357 09:28:01.221281
4358 09:28:01.224253 RX Vref 0 -> 0, step: 1
4359 09:28:01.224332
4360 09:28:01.227439 RX Delay -179 -> 252, step: 8
4361 09:28:01.234386 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4362 09:28:01.238343 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4363 09:28:01.240862 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4364 09:28:01.243905 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4365 09:28:01.247789 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4366 09:28:01.253710 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4367 09:28:01.257010 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4368 09:28:01.260416 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4369 09:28:01.263620 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4370 09:28:01.270450 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4371 09:28:01.273700 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4372 09:28:01.277085 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4373 09:28:01.280376 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4374 09:28:01.287244 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4375 09:28:01.290512 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4376 09:28:01.293968 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4377 09:28:01.294047 ==
4378 09:28:01.297265 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 09:28:01.300083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 09:28:01.300163 ==
4381 09:28:01.303852 DQS Delay:
4382 09:28:01.303931 DQS0 = 0, DQS1 = 0
4383 09:28:01.306900 DQM Delay:
4384 09:28:01.306979 DQM0 = 42, DQM1 = 35
4385 09:28:01.307076 DQ Delay:
4386 09:28:01.310156 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4387 09:28:01.313459 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4388 09:28:01.316867 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4389 09:28:01.320000 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4390 09:28:01.320079
4391 09:28:01.320142
4392 09:28:01.330287 [DQSOSCAuto] RK1, (LSB)MR18= 0x6316, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4393 09:28:01.333320 CH0 RK1: MR19=808, MR18=6316
4394 09:28:01.340405 CH0_RK1: MR19=0x808, MR18=0x6316, DQSOSC=391, MR23=63, INC=171, DEC=114
4395 09:28:01.340486 [RxdqsGatingPostProcess] freq 600
4396 09:28:01.346426 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 09:28:01.350034 Pre-setting of DQS Precalculation
4398 09:28:01.353211 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 09:28:01.356434 ==
4400 09:28:01.359924 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 09:28:01.363138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 09:28:01.363219 ==
4403 09:28:01.369472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 09:28:01.373246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4405 09:28:01.376883 [CA 0] Center 35 (5~66) winsize 62
4406 09:28:01.380101 [CA 1] Center 35 (5~66) winsize 62
4407 09:28:01.383601 [CA 2] Center 34 (4~65) winsize 62
4408 09:28:01.386717 [CA 3] Center 33 (3~64) winsize 62
4409 09:28:01.389880 [CA 4] Center 34 (4~65) winsize 62
4410 09:28:01.393232 [CA 5] Center 33 (3~64) winsize 62
4411 09:28:01.393312
4412 09:28:01.396785 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4413 09:28:01.396865
4414 09:28:01.403060 [CATrainingPosCal] consider 1 rank data
4415 09:28:01.403144 u2DelayCellTimex100 = 270/100 ps
4416 09:28:01.409669 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 09:28:01.413091 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4418 09:28:01.416343 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 09:28:01.419864 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 09:28:01.422940 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4421 09:28:01.426714 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 09:28:01.426793
4423 09:28:01.429182 CA PerBit enable=1, Macro0, CA PI delay=33
4424 09:28:01.429299
4425 09:28:01.432640 [CBTSetCACLKResult] CA Dly = 33
4426 09:28:01.436154 CS Dly: 5 (0~36)
4427 09:28:01.436233 ==
4428 09:28:01.439629 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 09:28:01.442458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 09:28:01.442538 ==
4431 09:28:01.449319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 09:28:01.455477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4433 09:28:01.458682 [CA 0] Center 35 (5~66) winsize 62
4434 09:28:01.462179 [CA 1] Center 36 (6~66) winsize 61
4435 09:28:01.465336 [CA 2] Center 34 (4~65) winsize 62
4436 09:28:01.468986 [CA 3] Center 34 (4~65) winsize 62
4437 09:28:01.472294 [CA 4] Center 34 (4~65) winsize 62
4438 09:28:01.475631 [CA 5] Center 34 (3~65) winsize 63
4439 09:28:01.475761
4440 09:28:01.479028 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4441 09:28:01.479106
4442 09:28:01.482032 [CATrainingPosCal] consider 2 rank data
4443 09:28:01.485215 u2DelayCellTimex100 = 270/100 ps
4444 09:28:01.488716 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 09:28:01.492014 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 09:28:01.495049 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 09:28:01.498744 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4448 09:28:01.502048 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 09:28:01.505108 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 09:28:01.505187
4451 09:28:01.512300 CA PerBit enable=1, Macro0, CA PI delay=33
4452 09:28:01.512379
4453 09:28:01.512442 [CBTSetCACLKResult] CA Dly = 33
4454 09:28:01.514975 CS Dly: 5 (0~37)
4455 09:28:01.515052
4456 09:28:01.518212 ----->DramcWriteLeveling(PI) begin...
4457 09:28:01.518292 ==
4458 09:28:01.521503 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 09:28:01.525005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 09:28:01.525084 ==
4461 09:28:01.528201 Write leveling (Byte 0): 28 => 28
4462 09:28:01.531337 Write leveling (Byte 1): 30 => 30
4463 09:28:01.534900 DramcWriteLeveling(PI) end<-----
4464 09:28:01.534978
4465 09:28:01.535041 ==
4466 09:28:01.537922 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 09:28:01.544660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 09:28:01.544740 ==
4469 09:28:01.544803 [Gating] SW mode calibration
4470 09:28:01.555366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 09:28:01.557860 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 09:28:01.561559 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 09:28:01.568133 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 09:28:01.571493 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 09:28:01.574897 0 9 12 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (1 0)
4476 09:28:01.581233 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 09:28:01.584712 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 09:28:01.588965 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 09:28:01.594390 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 09:28:01.597698 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 09:28:01.601301 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 09:28:01.607832 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 09:28:01.610786 0 10 12 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
4484 09:28:01.614476 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4485 09:28:01.620846 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 09:28:01.624228 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 09:28:01.627606 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 09:28:01.634223 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 09:28:01.637470 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 09:28:01.641030 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 09:28:01.647432 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4492 09:28:01.651020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:28:01.654058 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:28:01.660361 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:28:01.663590 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:28:01.666982 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 09:28:01.673642 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 09:28:01.677068 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 09:28:01.680097 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 09:28:01.686767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 09:28:01.690456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 09:28:01.693339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 09:28:01.700450 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 09:28:01.703534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 09:28:01.706874 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 09:28:01.713682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4507 09:28:01.716650 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4508 09:28:01.719837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 09:28:01.723310 Total UI for P1: 0, mck2ui 16
4510 09:28:01.726294 best dqsien dly found for B0: ( 0, 13, 10)
4511 09:28:01.730446 Total UI for P1: 0, mck2ui 16
4512 09:28:01.733228 best dqsien dly found for B1: ( 0, 13, 14)
4513 09:28:01.736405 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4514 09:28:01.739454 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4515 09:28:01.739534
4516 09:28:01.746548 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4517 09:28:01.749845 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4518 09:28:01.752595 [Gating] SW calibration Done
4519 09:28:01.752675 ==
4520 09:28:01.755832 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 09:28:01.759532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 09:28:01.759615 ==
4523 09:28:01.759680 RX Vref Scan: 0
4524 09:28:01.762523
4525 09:28:01.762605 RX Vref 0 -> 0, step: 1
4526 09:28:01.762670
4527 09:28:01.765934 RX Delay -230 -> 252, step: 16
4528 09:28:01.769173 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4529 09:28:01.775570 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4530 09:28:01.779120 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4531 09:28:01.782424 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4532 09:28:01.785496 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4533 09:28:01.792118 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4534 09:28:01.795577 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4535 09:28:01.799238 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4536 09:28:01.802032 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4537 09:28:01.805672 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4538 09:28:01.812294 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4539 09:28:01.815325 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4540 09:28:01.818614 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4541 09:28:01.822453 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4542 09:28:01.828469 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4543 09:28:01.831807 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4544 09:28:01.831890 ==
4545 09:28:01.834871 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 09:28:01.838570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 09:28:01.838652 ==
4548 09:28:01.841928 DQS Delay:
4549 09:28:01.842010 DQS0 = 0, DQS1 = 0
4550 09:28:01.844969 DQM Delay:
4551 09:28:01.845051 DQM0 = 46, DQM1 = 36
4552 09:28:01.845116 DQ Delay:
4553 09:28:01.848416 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4554 09:28:01.851527 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4555 09:28:01.854736 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4556 09:28:01.858022 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4557 09:28:01.858104
4558 09:28:01.858169
4559 09:28:01.861989 ==
4560 09:28:01.864672 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 09:28:01.868659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 09:28:01.868741 ==
4563 09:28:01.868806
4564 09:28:01.868866
4565 09:28:01.872423 TX Vref Scan disable
4566 09:28:01.872505 == TX Byte 0 ==
4567 09:28:01.878160 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 09:28:01.881115 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 09:28:01.881197 == TX Byte 1 ==
4570 09:28:01.887697 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 09:28:01.891144 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 09:28:01.891225 ==
4573 09:28:01.894419 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 09:28:01.897787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 09:28:01.897868 ==
4576 09:28:01.897937
4577 09:28:01.897998
4578 09:28:01.900965 TX Vref Scan disable
4579 09:28:01.904188 == TX Byte 0 ==
4580 09:28:01.907395 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4581 09:28:01.910923 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4582 09:28:01.914010 == TX Byte 1 ==
4583 09:28:01.918064 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4584 09:28:01.920941 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4585 09:28:01.921023
4586 09:28:01.924257 [DATLAT]
4587 09:28:01.924338 Freq=600, CH1 RK0
4588 09:28:01.924403
4589 09:28:01.927527 DATLAT Default: 0x9
4590 09:28:01.927609 0, 0xFFFF, sum = 0
4591 09:28:01.931051 1, 0xFFFF, sum = 0
4592 09:28:01.931134 2, 0xFFFF, sum = 0
4593 09:28:01.934365 3, 0xFFFF, sum = 0
4594 09:28:01.934449 4, 0xFFFF, sum = 0
4595 09:28:01.937280 5, 0xFFFF, sum = 0
4596 09:28:01.937363 6, 0xFFFF, sum = 0
4597 09:28:01.940400 7, 0xFFFF, sum = 0
4598 09:28:01.940484 8, 0x0, sum = 1
4599 09:28:01.944111 9, 0x0, sum = 2
4600 09:28:01.944195 10, 0x0, sum = 3
4601 09:28:01.947682 11, 0x0, sum = 4
4602 09:28:01.947774 best_step = 9
4603 09:28:01.947840
4604 09:28:01.947901 ==
4605 09:28:01.950557 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 09:28:01.956747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 09:28:01.956830 ==
4608 09:28:01.956895 RX Vref Scan: 1
4609 09:28:01.956955
4610 09:28:01.960228 RX Vref 0 -> 0, step: 1
4611 09:28:01.960310
4612 09:28:01.963537 RX Delay -195 -> 252, step: 8
4613 09:28:01.963618
4614 09:28:01.966929 Set Vref, RX VrefLevel [Byte0]: 52
4615 09:28:01.970178 [Byte1]: 54
4616 09:28:01.970259
4617 09:28:01.973776 Final RX Vref Byte 0 = 52 to rank0
4618 09:28:01.977381 Final RX Vref Byte 1 = 54 to rank0
4619 09:28:01.980266 Final RX Vref Byte 0 = 52 to rank1
4620 09:28:01.983178 Final RX Vref Byte 1 = 54 to rank1==
4621 09:28:01.986698 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 09:28:01.989909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 09:28:01.989991 ==
4624 09:28:01.993441 DQS Delay:
4625 09:28:01.993522 DQS0 = 0, DQS1 = 0
4626 09:28:01.996517 DQM Delay:
4627 09:28:01.996599 DQM0 = 46, DQM1 = 36
4628 09:28:01.996664 DQ Delay:
4629 09:28:02.000402 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4630 09:28:02.003118 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4631 09:28:02.006440 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4632 09:28:02.010170 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4633 09:28:02.010277
4634 09:28:02.013013
4635 09:28:02.019626 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f35, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4636 09:28:02.022884 CH1 RK0: MR19=808, MR18=4F35
4637 09:28:02.029477 CH1_RK0: MR19=0x808, MR18=0x4F35, DQSOSC=394, MR23=63, INC=168, DEC=112
4638 09:28:02.029559
4639 09:28:02.033488 ----->DramcWriteLeveling(PI) begin...
4640 09:28:02.033571 ==
4641 09:28:02.036292 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 09:28:02.039435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 09:28:02.039516 ==
4644 09:28:02.042968 Write leveling (Byte 0): 30 => 30
4645 09:28:02.046308 Write leveling (Byte 1): 33 => 33
4646 09:28:02.049263 DramcWriteLeveling(PI) end<-----
4647 09:28:02.049344
4648 09:28:02.049408 ==
4649 09:28:02.053105 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 09:28:02.056350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 09:28:02.056431 ==
4652 09:28:02.059185 [Gating] SW mode calibration
4653 09:28:02.065970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 09:28:02.072474 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 09:28:02.075795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 09:28:02.078969 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 09:28:02.085397 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 09:28:02.088760 0 9 12 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
4659 09:28:02.092224 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4660 09:28:02.098878 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 09:28:02.102109 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 09:28:02.105860 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 09:28:02.111993 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 09:28:02.115451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 09:28:02.118469 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 09:28:02.124951 0 10 12 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (0 0)
4667 09:28:02.128474 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4668 09:28:02.134724 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 09:28:02.138259 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 09:28:02.141390 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 09:28:02.147885 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 09:28:02.151754 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 09:28:02.154553 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 09:28:02.161066 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4675 09:28:02.164483 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:28:02.167713 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:28:02.174483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:28:02.177879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 09:28:02.181102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 09:28:02.187471 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 09:28:02.191165 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 09:28:02.194068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 09:28:02.200817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 09:28:02.204036 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 09:28:02.207211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 09:28:02.214234 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 09:28:02.217302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 09:28:02.220532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 09:28:02.226931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4690 09:28:02.230640 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4691 09:28:02.233528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4692 09:28:02.237435 Total UI for P1: 0, mck2ui 16
4693 09:28:02.240644 best dqsien dly found for B1: ( 0, 13, 10)
4694 09:28:02.246594 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 09:28:02.246678 Total UI for P1: 0, mck2ui 16
4696 09:28:02.250004 best dqsien dly found for B0: ( 0, 13, 14)
4697 09:28:02.257003 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4698 09:28:02.259871 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4699 09:28:02.259956
4700 09:28:02.263584 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4701 09:28:02.266541 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4702 09:28:02.270093 [Gating] SW calibration Done
4703 09:28:02.270174 ==
4704 09:28:02.273407 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 09:28:02.276816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 09:28:02.276897 ==
4707 09:28:02.279934 RX Vref Scan: 0
4708 09:28:02.280015
4709 09:28:02.280080 RX Vref 0 -> 0, step: 1
4710 09:28:02.280141
4711 09:28:02.283010 RX Delay -230 -> 252, step: 16
4712 09:28:02.290033 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4713 09:28:02.292920 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4714 09:28:02.296519 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4715 09:28:02.300216 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4716 09:28:02.302800 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4717 09:28:02.309463 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4718 09:28:02.313220 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4719 09:28:02.316406 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4720 09:28:02.319564 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4721 09:28:02.326148 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4722 09:28:02.330082 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4723 09:28:02.332977 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4724 09:28:02.335875 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4725 09:28:02.342647 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4726 09:28:02.346046 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4727 09:28:02.349446 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4728 09:28:02.349527 ==
4729 09:28:02.352594 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 09:28:02.355709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 09:28:02.359120 ==
4732 09:28:02.359201 DQS Delay:
4733 09:28:02.359265 DQS0 = 0, DQS1 = 0
4734 09:28:02.362226 DQM Delay:
4735 09:28:02.362324 DQM0 = 46, DQM1 = 38
4736 09:28:02.365544 DQ Delay:
4737 09:28:02.369707 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4738 09:28:02.369789 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4739 09:28:02.372480 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4740 09:28:02.375513 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4741 09:28:02.375593
4742 09:28:02.378704
4743 09:28:02.378784 ==
4744 09:28:02.381995 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 09:28:02.385635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 09:28:02.385716 ==
4747 09:28:02.385780
4748 09:28:02.385839
4749 09:28:02.389103 TX Vref Scan disable
4750 09:28:02.389183 == TX Byte 0 ==
4751 09:28:02.395582 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4752 09:28:02.398771 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4753 09:28:02.398851 == TX Byte 1 ==
4754 09:28:02.405629 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4755 09:28:02.408666 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4756 09:28:02.408747 ==
4757 09:28:02.411737 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 09:28:02.415234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 09:28:02.415328 ==
4760 09:28:02.415394
4761 09:28:02.418336
4762 09:28:02.418416 TX Vref Scan disable
4763 09:28:02.422045 == TX Byte 0 ==
4764 09:28:02.425176 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4765 09:28:02.431860 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4766 09:28:02.431940 == TX Byte 1 ==
4767 09:28:02.435286 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4768 09:28:02.441731 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4769 09:28:02.441812
4770 09:28:02.441877 [DATLAT]
4771 09:28:02.441937 Freq=600, CH1 RK1
4772 09:28:02.441996
4773 09:28:02.444833 DATLAT Default: 0x9
4774 09:28:02.444913 0, 0xFFFF, sum = 0
4775 09:28:02.448427 1, 0xFFFF, sum = 0
4776 09:28:02.451604 2, 0xFFFF, sum = 0
4777 09:28:02.451701 3, 0xFFFF, sum = 0
4778 09:28:02.454576 4, 0xFFFF, sum = 0
4779 09:28:02.454658 5, 0xFFFF, sum = 0
4780 09:28:02.457818 6, 0xFFFF, sum = 0
4781 09:28:02.457900 7, 0xFFFF, sum = 0
4782 09:28:02.461464 8, 0x0, sum = 1
4783 09:28:02.461548 9, 0x0, sum = 2
4784 09:28:02.464829 10, 0x0, sum = 3
4785 09:28:02.464911 11, 0x0, sum = 4
4786 09:28:02.464976 best_step = 9
4787 09:28:02.465036
4788 09:28:02.468030 ==
4789 09:28:02.468112 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 09:28:02.474276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 09:28:02.474357 ==
4792 09:28:02.474422 RX Vref Scan: 0
4793 09:28:02.474482
4794 09:28:02.477464 RX Vref 0 -> 0, step: 1
4795 09:28:02.477545
4796 09:28:02.480951 RX Delay -195 -> 252, step: 8
4797 09:28:02.487594 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4798 09:28:02.491016 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4799 09:28:02.494214 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4800 09:28:02.497354 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4801 09:28:02.503847 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4802 09:28:02.507460 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4803 09:28:02.510925 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4804 09:28:02.513880 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4805 09:28:02.517161 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4806 09:28:02.523713 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4807 09:28:02.526872 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4808 09:28:02.530406 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4809 09:28:02.533727 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4810 09:28:02.540915 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4811 09:28:02.543485 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4812 09:28:02.547281 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4813 09:28:02.547359 ==
4814 09:28:02.550468 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 09:28:02.553504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 09:28:02.557470 ==
4817 09:28:02.557544 DQS Delay:
4818 09:28:02.557606 DQS0 = 0, DQS1 = 0
4819 09:28:02.560541 DQM Delay:
4820 09:28:02.560622 DQM0 = 45, DQM1 = 36
4821 09:28:02.563431 DQ Delay:
4822 09:28:02.563512 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4823 09:28:02.567040 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4824 09:28:02.570156 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4825 09:28:02.573585 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4826 09:28:02.573666
4827 09:28:02.576585
4828 09:28:02.583298 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4829 09:28:02.587325 CH1 RK1: MR19=808, MR18=2C21
4830 09:28:02.593027 CH1_RK1: MR19=0x808, MR18=0x2C21, DQSOSC=401, MR23=63, INC=163, DEC=108
4831 09:28:02.596717 [RxdqsGatingPostProcess] freq 600
4832 09:28:02.599967 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4833 09:28:02.602994 Pre-setting of DQS Precalculation
4834 09:28:02.609419 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4835 09:28:02.616374 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4836 09:28:02.622827 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4837 09:28:02.622931
4838 09:28:02.623031
4839 09:28:02.626075 [Calibration Summary] 1200 Mbps
4840 09:28:02.626148 CH 0, Rank 0
4841 09:28:02.629392 SW Impedance : PASS
4842 09:28:02.632633 DUTY Scan : NO K
4843 09:28:02.632733 ZQ Calibration : PASS
4844 09:28:02.635993 Jitter Meter : NO K
4845 09:28:02.639384 CBT Training : PASS
4846 09:28:02.639487 Write leveling : PASS
4847 09:28:02.642638 RX DQS gating : PASS
4848 09:28:02.645634 RX DQ/DQS(RDDQC) : PASS
4849 09:28:02.645736 TX DQ/DQS : PASS
4850 09:28:02.648823 RX DATLAT : PASS
4851 09:28:02.652340 RX DQ/DQS(Engine): PASS
4852 09:28:02.652412 TX OE : NO K
4853 09:28:02.655653 All Pass.
4854 09:28:02.655731
4855 09:28:02.655811 CH 0, Rank 1
4856 09:28:02.659036 SW Impedance : PASS
4857 09:28:02.659134 DUTY Scan : NO K
4858 09:28:02.661812 ZQ Calibration : PASS
4859 09:28:02.665541 Jitter Meter : NO K
4860 09:28:02.665648 CBT Training : PASS
4861 09:28:02.668855 Write leveling : PASS
4862 09:28:02.672356 RX DQS gating : PASS
4863 09:28:02.672426 RX DQ/DQS(RDDQC) : PASS
4864 09:28:02.675712 TX DQ/DQS : PASS
4865 09:28:02.678433 RX DATLAT : PASS
4866 09:28:02.678528 RX DQ/DQS(Engine): PASS
4867 09:28:02.681733 TX OE : NO K
4868 09:28:02.681812 All Pass.
4869 09:28:02.681903
4870 09:28:02.685174 CH 1, Rank 0
4871 09:28:02.685243 SW Impedance : PASS
4872 09:28:02.688429 DUTY Scan : NO K
4873 09:28:02.691402 ZQ Calibration : PASS
4874 09:28:02.691472 Jitter Meter : NO K
4875 09:28:02.694839 CBT Training : PASS
4876 09:28:02.694914 Write leveling : PASS
4877 09:28:02.698327 RX DQS gating : PASS
4878 09:28:02.701707 RX DQ/DQS(RDDQC) : PASS
4879 09:28:02.701803 TX DQ/DQS : PASS
4880 09:28:02.704965 RX DATLAT : PASS
4881 09:28:02.708339 RX DQ/DQS(Engine): PASS
4882 09:28:02.708420 TX OE : NO K
4883 09:28:02.711682 All Pass.
4884 09:28:02.711772
4885 09:28:02.711837 CH 1, Rank 1
4886 09:28:02.714783 SW Impedance : PASS
4887 09:28:02.714863 DUTY Scan : NO K
4888 09:28:02.717888 ZQ Calibration : PASS
4889 09:28:02.721088 Jitter Meter : NO K
4890 09:28:02.721169 CBT Training : PASS
4891 09:28:02.724975 Write leveling : PASS
4892 09:28:02.727826 RX DQS gating : PASS
4893 09:28:02.727907 RX DQ/DQS(RDDQC) : PASS
4894 09:28:02.730975 TX DQ/DQS : PASS
4895 09:28:02.734376 RX DATLAT : PASS
4896 09:28:02.734457 RX DQ/DQS(Engine): PASS
4897 09:28:02.737828 TX OE : NO K
4898 09:28:02.737909 All Pass.
4899 09:28:02.738010
4900 09:28:02.741451 DramC Write-DBI off
4901 09:28:02.744442 PER_BANK_REFRESH: Hybrid Mode
4902 09:28:02.744522 TX_TRACKING: ON
4903 09:28:02.754183 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4904 09:28:02.757660 [FAST_K] Save calibration result to emmc
4905 09:28:02.761403 dramc_set_vcore_voltage set vcore to 662500
4906 09:28:02.764030 Read voltage for 933, 3
4907 09:28:02.764111 Vio18 = 0
4908 09:28:02.764175 Vcore = 662500
4909 09:28:02.767453 Vdram = 0
4910 09:28:02.767534 Vddq = 0
4911 09:28:02.767599 Vmddr = 0
4912 09:28:02.774434 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4913 09:28:02.777411 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4914 09:28:02.781029 MEM_TYPE=3, freq_sel=17
4915 09:28:02.783961 sv_algorithm_assistance_LP4_1600
4916 09:28:02.787435 ============ PULL DRAM RESETB DOWN ============
4917 09:28:02.790731 ========== PULL DRAM RESETB DOWN end =========
4918 09:28:02.797137 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4919 09:28:02.800391 ===================================
4920 09:28:02.804173 LPDDR4 DRAM CONFIGURATION
4921 09:28:02.807074 ===================================
4922 09:28:02.807157 EX_ROW_EN[0] = 0x0
4923 09:28:02.810272 EX_ROW_EN[1] = 0x0
4924 09:28:02.810354 LP4Y_EN = 0x0
4925 09:28:02.813702 WORK_FSP = 0x0
4926 09:28:02.813785 WL = 0x3
4927 09:28:02.816712 RL = 0x3
4928 09:28:02.816794 BL = 0x2
4929 09:28:02.820404 RPST = 0x0
4930 09:28:02.820486 RD_PRE = 0x0
4931 09:28:02.823996 WR_PRE = 0x1
4932 09:28:02.824078 WR_PST = 0x0
4933 09:28:02.826962 DBI_WR = 0x0
4934 09:28:02.830092 DBI_RD = 0x0
4935 09:28:02.830173 OTF = 0x1
4936 09:28:02.833178 ===================================
4937 09:28:02.836955 ===================================
4938 09:28:02.837037 ANA top config
4939 09:28:02.839962 ===================================
4940 09:28:02.843173 DLL_ASYNC_EN = 0
4941 09:28:02.846764 ALL_SLAVE_EN = 1
4942 09:28:02.849970 NEW_RANK_MODE = 1
4943 09:28:02.853137 DLL_IDLE_MODE = 1
4944 09:28:02.853218 LP45_APHY_COMB_EN = 1
4945 09:28:02.856800 TX_ODT_DIS = 1
4946 09:28:02.859718 NEW_8X_MODE = 1
4947 09:28:02.863048 ===================================
4948 09:28:02.866602 ===================================
4949 09:28:02.869798 data_rate = 1866
4950 09:28:02.873214 CKR = 1
4951 09:28:02.876651 DQ_P2S_RATIO = 8
4952 09:28:02.879471 ===================================
4953 09:28:02.879552 CA_P2S_RATIO = 8
4954 09:28:02.882951 DQ_CA_OPEN = 0
4955 09:28:02.886180 DQ_SEMI_OPEN = 0
4956 09:28:02.889602 CA_SEMI_OPEN = 0
4957 09:28:02.892563 CA_FULL_RATE = 0
4958 09:28:02.896440 DQ_CKDIV4_EN = 1
4959 09:28:02.896521 CA_CKDIV4_EN = 1
4960 09:28:02.899643 CA_PREDIV_EN = 0
4961 09:28:02.902417 PH8_DLY = 0
4962 09:28:02.905904 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4963 09:28:02.909447 DQ_AAMCK_DIV = 4
4964 09:28:02.912470 CA_AAMCK_DIV = 4
4965 09:28:02.912551 CA_ADMCK_DIV = 4
4966 09:28:02.915753 DQ_TRACK_CA_EN = 0
4967 09:28:02.919267 CA_PICK = 933
4968 09:28:02.922810 CA_MCKIO = 933
4969 09:28:02.926080 MCKIO_SEMI = 0
4970 09:28:02.930023 PLL_FREQ = 3732
4971 09:28:02.932920 DQ_UI_PI_RATIO = 32
4972 09:28:02.933001 CA_UI_PI_RATIO = 0
4973 09:28:02.935717 ===================================
4974 09:28:02.939003 ===================================
4975 09:28:02.942493 memory_type:LPDDR4
4976 09:28:02.946390 GP_NUM : 10
4977 09:28:02.946471 SRAM_EN : 1
4978 09:28:02.949070 MD32_EN : 0
4979 09:28:02.952727 ===================================
4980 09:28:02.955868 [ANA_INIT] >>>>>>>>>>>>>>
4981 09:28:02.959203 <<<<<< [CONFIGURE PHASE]: ANA_TX
4982 09:28:02.962568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4983 09:28:02.965867 ===================================
4984 09:28:02.965949 data_rate = 1866,PCW = 0X8f00
4985 09:28:02.969443 ===================================
4986 09:28:02.972470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4987 09:28:02.979333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 09:28:02.985695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 09:28:02.989341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4990 09:28:02.992107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4991 09:28:02.995880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4992 09:28:02.998742 [ANA_INIT] flow start
4993 09:28:02.998824 [ANA_INIT] PLL >>>>>>>>
4994 09:28:03.001876 [ANA_INIT] PLL <<<<<<<<
4995 09:28:03.005262 [ANA_INIT] MIDPI >>>>>>>>
4996 09:28:03.008971 [ANA_INIT] MIDPI <<<<<<<<
4997 09:28:03.009052 [ANA_INIT] DLL >>>>>>>>
4998 09:28:03.011881 [ANA_INIT] flow end
4999 09:28:03.015135 ============ LP4 DIFF to SE enter ============
5000 09:28:03.018486 ============ LP4 DIFF to SE exit ============
5001 09:28:03.021883 [ANA_INIT] <<<<<<<<<<<<<
5002 09:28:03.025385 [Flow] Enable top DCM control >>>>>
5003 09:28:03.028323 [Flow] Enable top DCM control <<<<<
5004 09:28:03.031661 Enable DLL master slave shuffle
5005 09:28:03.038689 ==============================================================
5006 09:28:03.038770 Gating Mode config
5007 09:28:03.044957 ==============================================================
5008 09:28:03.045039 Config description:
5009 09:28:03.054652 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5010 09:28:03.061575 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5011 09:28:03.068104 SELPH_MODE 0: By rank 1: By Phase
5012 09:28:03.074814 ==============================================================
5013 09:28:03.074896 GAT_TRACK_EN = 1
5014 09:28:03.078636 RX_GATING_MODE = 2
5015 09:28:03.081621 RX_GATING_TRACK_MODE = 2
5016 09:28:03.084502 SELPH_MODE = 1
5017 09:28:03.087704 PICG_EARLY_EN = 1
5018 09:28:03.091038 VALID_LAT_VALUE = 1
5019 09:28:03.097767 ==============================================================
5020 09:28:03.101042 Enter into Gating configuration >>>>
5021 09:28:03.104535 Exit from Gating configuration <<<<
5022 09:28:03.108301 Enter into DVFS_PRE_config >>>>>
5023 09:28:03.117627 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5024 09:28:03.120789 Exit from DVFS_PRE_config <<<<<
5025 09:28:03.124005 Enter into PICG configuration >>>>
5026 09:28:03.127323 Exit from PICG configuration <<<<
5027 09:28:03.130406 [RX_INPUT] configuration >>>>>
5028 09:28:03.133644 [RX_INPUT] configuration <<<<<
5029 09:28:03.137311 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5030 09:28:03.143988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5031 09:28:03.150276 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 09:28:03.156851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 09:28:03.160235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 09:28:03.166671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 09:28:03.169923 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5036 09:28:03.177113 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5037 09:28:03.179890 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5038 09:28:03.183837 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5039 09:28:03.186453 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5040 09:28:03.192932 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 09:28:03.196259 ===================================
5042 09:28:03.199888 LPDDR4 DRAM CONFIGURATION
5043 09:28:03.203260 ===================================
5044 09:28:03.203329 EX_ROW_EN[0] = 0x0
5045 09:28:03.206588 EX_ROW_EN[1] = 0x0
5046 09:28:03.206657 LP4Y_EN = 0x0
5047 09:28:03.209728 WORK_FSP = 0x0
5048 09:28:03.209811 WL = 0x3
5049 09:28:03.213163 RL = 0x3
5050 09:28:03.213245 BL = 0x2
5051 09:28:03.216208 RPST = 0x0
5052 09:28:03.216290 RD_PRE = 0x0
5053 09:28:03.219654 WR_PRE = 0x1
5054 09:28:03.219759 WR_PST = 0x0
5055 09:28:03.222711 DBI_WR = 0x0
5056 09:28:03.222793 DBI_RD = 0x0
5057 09:28:03.226834 OTF = 0x1
5058 09:28:03.229441 ===================================
5059 09:28:03.232961 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5060 09:28:03.236112 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5061 09:28:03.242749 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 09:28:03.245909 ===================================
5063 09:28:03.249250 LPDDR4 DRAM CONFIGURATION
5064 09:28:03.252689 ===================================
5065 09:28:03.252769 EX_ROW_EN[0] = 0x10
5066 09:28:03.256301 EX_ROW_EN[1] = 0x0
5067 09:28:03.256377 LP4Y_EN = 0x0
5068 09:28:03.259051 WORK_FSP = 0x0
5069 09:28:03.259121 WL = 0x3
5070 09:28:03.262324 RL = 0x3
5071 09:28:03.262405 BL = 0x2
5072 09:28:03.265799 RPST = 0x0
5073 09:28:03.265877 RD_PRE = 0x0
5074 09:28:03.269254 WR_PRE = 0x1
5075 09:28:03.269322 WR_PST = 0x0
5076 09:28:03.272732 DBI_WR = 0x0
5077 09:28:03.276175 DBI_RD = 0x0
5078 09:28:03.276256 OTF = 0x1
5079 09:28:03.279150 ===================================
5080 09:28:03.285671 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5081 09:28:03.289032 nWR fixed to 30
5082 09:28:03.292777 [ModeRegInit_LP4] CH0 RK0
5083 09:28:03.292859 [ModeRegInit_LP4] CH0 RK1
5084 09:28:03.296054 [ModeRegInit_LP4] CH1 RK0
5085 09:28:03.299127 [ModeRegInit_LP4] CH1 RK1
5086 09:28:03.299208 match AC timing 9
5087 09:28:03.305496 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5088 09:28:03.308676 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5089 09:28:03.312154 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5090 09:28:03.318532 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5091 09:28:03.321851 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5092 09:28:03.321932 ==
5093 09:28:03.325320 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 09:28:03.328310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 09:28:03.328392 ==
5096 09:28:03.335084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 09:28:03.341561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5098 09:28:03.345534 [CA 0] Center 37 (7~68) winsize 62
5099 09:28:03.348702 [CA 1] Center 37 (7~68) winsize 62
5100 09:28:03.351479 [CA 2] Center 34 (4~65) winsize 62
5101 09:28:03.354896 [CA 3] Center 34 (4~65) winsize 62
5102 09:28:03.358159 [CA 4] Center 34 (4~64) winsize 61
5103 09:28:03.361783 [CA 5] Center 33 (3~63) winsize 61
5104 09:28:03.361864
5105 09:28:03.364997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5106 09:28:03.365079
5107 09:28:03.368019 [CATrainingPosCal] consider 1 rank data
5108 09:28:03.371273 u2DelayCellTimex100 = 270/100 ps
5109 09:28:03.374604 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5110 09:28:03.377942 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5111 09:28:03.381235 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5112 09:28:03.387942 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5113 09:28:03.391195 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5114 09:28:03.394768 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5115 09:28:03.394849
5116 09:28:03.397739 CA PerBit enable=1, Macro0, CA PI delay=33
5117 09:28:03.397820
5118 09:28:03.401060 [CBTSetCACLKResult] CA Dly = 33
5119 09:28:03.401141 CS Dly: 7 (0~38)
5120 09:28:03.401207 ==
5121 09:28:03.404309 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 09:28:03.410736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 09:28:03.410818 ==
5124 09:28:03.414228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 09:28:03.420822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 09:28:03.424250 [CA 0] Center 37 (7~68) winsize 62
5127 09:28:03.427663 [CA 1] Center 37 (7~68) winsize 62
5128 09:28:03.431303 [CA 2] Center 34 (4~65) winsize 62
5129 09:28:03.433949 [CA 3] Center 34 (4~65) winsize 62
5130 09:28:03.437409 [CA 4] Center 33 (3~64) winsize 62
5131 09:28:03.440942 [CA 5] Center 33 (3~63) winsize 61
5132 09:28:03.441023
5133 09:28:03.444250 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 09:28:03.444332
5135 09:28:03.447374 [CATrainingPosCal] consider 2 rank data
5136 09:28:03.450451 u2DelayCellTimex100 = 270/100 ps
5137 09:28:03.453750 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5138 09:28:03.460624 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5139 09:28:03.463860 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5140 09:28:03.467294 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5141 09:28:03.470278 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5142 09:28:03.473517 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5143 09:28:03.473599
5144 09:28:03.477103 CA PerBit enable=1, Macro0, CA PI delay=33
5145 09:28:03.477185
5146 09:28:03.480510 [CBTSetCACLKResult] CA Dly = 33
5147 09:28:03.480591 CS Dly: 8 (0~40)
5148 09:28:03.483582
5149 09:28:03.487067 ----->DramcWriteLeveling(PI) begin...
5150 09:28:03.487150 ==
5151 09:28:03.490523 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 09:28:03.493501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 09:28:03.493583 ==
5154 09:28:03.496632 Write leveling (Byte 0): 33 => 33
5155 09:28:03.500495 Write leveling (Byte 1): 28 => 28
5156 09:28:03.504010 DramcWriteLeveling(PI) end<-----
5157 09:28:03.504092
5158 09:28:03.504156 ==
5159 09:28:03.506847 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 09:28:03.510396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 09:28:03.510478 ==
5162 09:28:03.513147 [Gating] SW mode calibration
5163 09:28:03.520000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 09:28:03.526577 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5165 09:28:03.529675 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5166 09:28:03.533180 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 09:28:03.539377 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 09:28:03.542954 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 09:28:03.546469 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 09:28:03.552904 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 09:28:03.556268 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 09:28:03.559194 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5173 09:28:03.566158 0 15 0 | B1->B0 | 3131 2626 | 0 0 | (0 0) (0 0)
5174 09:28:03.569230 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 09:28:03.572404 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 09:28:03.579217 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 09:28:03.582300 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 09:28:03.585419 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 09:28:03.592781 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 09:28:03.595528 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5181 09:28:03.599494 1 0 0 | B1->B0 | 3131 4242 | 0 0 | (0 0) (0 0)
5182 09:28:03.605325 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 09:28:03.608528 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 09:28:03.611999 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 09:28:03.618335 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 09:28:03.621777 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 09:28:03.625228 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 09:28:03.631844 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5189 09:28:03.635169 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5190 09:28:03.638066 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:28:03.644604 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:28:03.648092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 09:28:03.651587 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 09:28:03.658043 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 09:28:03.661318 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 09:28:03.664734 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 09:28:03.671009 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 09:28:03.674195 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 09:28:03.677587 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 09:28:03.684286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 09:28:03.687466 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 09:28:03.690658 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 09:28:03.697408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 09:28:03.700791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5205 09:28:03.703939 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5206 09:28:03.710534 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 09:28:03.714209 Total UI for P1: 0, mck2ui 16
5208 09:28:03.717354 best dqsien dly found for B0: ( 1, 2, 30)
5209 09:28:03.720641 Total UI for P1: 0, mck2ui 16
5210 09:28:03.723802 best dqsien dly found for B1: ( 1, 3, 0)
5211 09:28:03.727484 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5212 09:28:03.730457 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5213 09:28:03.730557
5214 09:28:03.733999 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5215 09:28:03.737382 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5216 09:28:03.740678 [Gating] SW calibration Done
5217 09:28:03.740770 ==
5218 09:28:03.744421 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 09:28:03.747399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 09:28:03.747476 ==
5221 09:28:03.750769 RX Vref Scan: 0
5222 09:28:03.750869
5223 09:28:03.750959 RX Vref 0 -> 0, step: 1
5224 09:28:03.753662
5225 09:28:03.753736 RX Delay -80 -> 252, step: 8
5226 09:28:03.760958 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5227 09:28:03.763548 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5228 09:28:03.767019 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5229 09:28:03.770436 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5230 09:28:03.773680 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5231 09:28:03.777093 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5232 09:28:03.783499 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5233 09:28:03.786614 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5234 09:28:03.790028 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5235 09:28:03.793444 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5236 09:28:03.796822 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5237 09:28:03.803331 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5238 09:28:03.806570 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5239 09:28:03.809742 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5240 09:28:03.813438 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5241 09:28:03.816194 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5242 09:28:03.816276 ==
5243 09:28:03.819926 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 09:28:03.827106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 09:28:03.827187 ==
5246 09:28:03.827251 DQS Delay:
5247 09:28:03.829203 DQS0 = 0, DQS1 = 0
5248 09:28:03.829284 DQM Delay:
5249 09:28:03.832530 DQM0 = 97, DQM1 = 86
5250 09:28:03.832610 DQ Delay:
5251 09:28:03.836094 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5252 09:28:03.839580 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5253 09:28:03.842589 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5254 09:28:03.846221 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5255 09:28:03.846302
5256 09:28:03.846366
5257 09:28:03.846425 ==
5258 09:28:03.849408 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 09:28:03.853040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 09:28:03.853131 ==
5261 09:28:03.853217
5262 09:28:03.853278
5263 09:28:03.856868 TX Vref Scan disable
5264 09:28:03.859192 == TX Byte 0 ==
5265 09:28:03.862542 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5266 09:28:03.865532 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5267 09:28:03.868941 == TX Byte 1 ==
5268 09:28:03.872186 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5269 09:28:03.875905 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5270 09:28:03.875988 ==
5271 09:28:03.878926 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 09:28:03.885629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 09:28:03.885711 ==
5274 09:28:03.885776
5275 09:28:03.885837
5276 09:28:03.885894 TX Vref Scan disable
5277 09:28:03.889700 == TX Byte 0 ==
5278 09:28:03.893451 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5279 09:28:03.899404 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5280 09:28:03.899487 == TX Byte 1 ==
5281 09:28:03.902863 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5282 09:28:03.909113 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5283 09:28:03.909195
5284 09:28:03.909260 [DATLAT]
5285 09:28:03.909321 Freq=933, CH0 RK0
5286 09:28:03.909380
5287 09:28:03.912754 DATLAT Default: 0xd
5288 09:28:03.915838 0, 0xFFFF, sum = 0
5289 09:28:03.915921 1, 0xFFFF, sum = 0
5290 09:28:03.919822 2, 0xFFFF, sum = 0
5291 09:28:03.919906 3, 0xFFFF, sum = 0
5292 09:28:03.923137 4, 0xFFFF, sum = 0
5293 09:28:03.923220 5, 0xFFFF, sum = 0
5294 09:28:03.925885 6, 0xFFFF, sum = 0
5295 09:28:03.925969 7, 0xFFFF, sum = 0
5296 09:28:03.929278 8, 0xFFFF, sum = 0
5297 09:28:03.929360 9, 0xFFFF, sum = 0
5298 09:28:03.932713 10, 0x0, sum = 1
5299 09:28:03.932833 11, 0x0, sum = 2
5300 09:28:03.935783 12, 0x0, sum = 3
5301 09:28:03.935867 13, 0x0, sum = 4
5302 09:28:03.935934 best_step = 11
5303 09:28:03.939174
5304 09:28:03.939255 ==
5305 09:28:03.942885 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 09:28:03.945627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 09:28:03.945708 ==
5308 09:28:03.945773 RX Vref Scan: 1
5309 09:28:03.945834
5310 09:28:03.949009 RX Vref 0 -> 0, step: 1
5311 09:28:03.949090
5312 09:28:03.952275 RX Delay -61 -> 252, step: 4
5313 09:28:03.952356
5314 09:28:03.955599 Set Vref, RX VrefLevel [Byte0]: 59
5315 09:28:03.958867 [Byte1]: 59
5316 09:28:03.962256
5317 09:28:03.962337 Final RX Vref Byte 0 = 59 to rank0
5318 09:28:03.965307 Final RX Vref Byte 1 = 59 to rank0
5319 09:28:03.968629 Final RX Vref Byte 0 = 59 to rank1
5320 09:28:03.972128 Final RX Vref Byte 1 = 59 to rank1==
5321 09:28:03.975904 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 09:28:03.981907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 09:28:03.981988 ==
5324 09:28:03.982053 DQS Delay:
5325 09:28:03.985906 DQS0 = 0, DQS1 = 0
5326 09:28:03.985987 DQM Delay:
5327 09:28:03.986051 DQM0 = 97, DQM1 = 88
5328 09:28:03.988385 DQ Delay:
5329 09:28:03.991660 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5330 09:28:03.995268 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5331 09:28:03.998429 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =86
5332 09:28:04.001784 DQ12 =90, DQ13 =90, DQ14 =100, DQ15 =94
5333 09:28:04.001865
5334 09:28:04.001929
5335 09:28:04.008657 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5336 09:28:04.011904 CH0 RK0: MR19=505, MR18=2C13
5337 09:28:04.018048 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5338 09:28:04.018130
5339 09:28:04.021365 ----->DramcWriteLeveling(PI) begin...
5340 09:28:04.021447 ==
5341 09:28:04.024813 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 09:28:04.027878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 09:28:04.027960 ==
5344 09:28:04.031669 Write leveling (Byte 0): 35 => 35
5345 09:28:04.034632 Write leveling (Byte 1): 31 => 31
5346 09:28:04.037770 DramcWriteLeveling(PI) end<-----
5347 09:28:04.037851
5348 09:28:04.037916 ==
5349 09:28:04.041729 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 09:28:04.045075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 09:28:04.048472 ==
5352 09:28:04.048553 [Gating] SW mode calibration
5353 09:28:04.057953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5354 09:28:04.061142 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5355 09:28:04.064109 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5356 09:28:04.071055 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5357 09:28:04.074180 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 09:28:04.077585 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 09:28:04.084239 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 09:28:04.087672 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 09:28:04.090746 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 09:28:04.097467 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 1)
5363 09:28:04.101151 0 15 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 1)
5364 09:28:04.104525 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 09:28:04.110418 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 09:28:04.114068 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 09:28:04.116976 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 09:28:04.123707 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 09:28:04.126825 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 09:28:04.130335 0 15 28 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5371 09:28:04.136686 1 0 0 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
5372 09:28:04.140519 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 09:28:04.143814 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 09:28:04.150113 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 09:28:04.154201 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 09:28:04.156911 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 09:28:04.163207 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 09:28:04.166367 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5379 09:28:04.170055 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5380 09:28:04.176910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 09:28:04.179839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 09:28:04.182833 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 09:28:04.189923 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 09:28:04.193220 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 09:28:04.196140 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 09:28:04.202584 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 09:28:04.206094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 09:28:04.209245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 09:28:04.216045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 09:28:04.219745 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 09:28:04.222904 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 09:28:04.229350 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 09:28:04.232398 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 09:28:04.236144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5395 09:28:04.242705 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5396 09:28:04.245627 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 09:28:04.249004 Total UI for P1: 0, mck2ui 16
5398 09:28:04.253041 best dqsien dly found for B0: ( 1, 2, 30)
5399 09:28:04.255789 Total UI for P1: 0, mck2ui 16
5400 09:28:04.258858 best dqsien dly found for B1: ( 1, 3, 0)
5401 09:28:04.262315 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5402 09:28:04.265555 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5403 09:28:04.265664
5404 09:28:04.268832 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5405 09:28:04.272289 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5406 09:28:04.275573 [Gating] SW calibration Done
5407 09:28:04.275680 ==
5408 09:28:04.278997 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 09:28:04.282439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 09:28:04.285542 ==
5411 09:28:04.285614 RX Vref Scan: 0
5412 09:28:04.285679
5413 09:28:04.288677 RX Vref 0 -> 0, step: 1
5414 09:28:04.288747
5415 09:28:04.291910 RX Delay -80 -> 252, step: 8
5416 09:28:04.295347 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5417 09:28:04.298589 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5418 09:28:04.301917 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5419 09:28:04.305405 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5420 09:28:04.308707 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5421 09:28:04.315178 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5422 09:28:04.318314 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5423 09:28:04.321564 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5424 09:28:04.324974 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5425 09:28:04.328659 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5426 09:28:04.335275 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5427 09:28:04.338636 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5428 09:28:04.341408 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5429 09:28:04.344599 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5430 09:28:04.348038 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5431 09:28:04.354675 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5432 09:28:04.354755 ==
5433 09:28:04.357967 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 09:28:04.361440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 09:28:04.361513 ==
5436 09:28:04.361574 DQS Delay:
5437 09:28:04.364822 DQS0 = 0, DQS1 = 0
5438 09:28:04.364938 DQM Delay:
5439 09:28:04.367927 DQM0 = 96, DQM1 = 89
5440 09:28:04.367999 DQ Delay:
5441 09:28:04.371324 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5442 09:28:04.374654 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5443 09:28:04.378022 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5444 09:28:04.381028 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5445 09:28:04.381100
5446 09:28:04.381161
5447 09:28:04.381218 ==
5448 09:28:04.384554 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 09:28:04.387914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 09:28:04.390839 ==
5451 09:28:04.390914
5452 09:28:04.390975
5453 09:28:04.391031 TX Vref Scan disable
5454 09:28:04.394156 == TX Byte 0 ==
5455 09:28:04.397277 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5456 09:28:04.400596 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5457 09:28:04.403884 == TX Byte 1 ==
5458 09:28:04.407467 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5459 09:28:04.410800 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5460 09:28:04.414144 ==
5461 09:28:04.417444 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 09:28:04.420542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 09:28:04.420625 ==
5464 09:28:04.420737
5465 09:28:04.420797
5466 09:28:04.423892 TX Vref Scan disable
5467 09:28:04.423991 == TX Byte 0 ==
5468 09:28:04.430555 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5469 09:28:04.433410 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5470 09:28:04.433489 == TX Byte 1 ==
5471 09:28:04.440626 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5472 09:28:04.443486 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5473 09:28:04.443573
5474 09:28:04.443663 [DATLAT]
5475 09:28:04.447260 Freq=933, CH0 RK1
5476 09:28:04.447331
5477 09:28:04.447391 DATLAT Default: 0xb
5478 09:28:04.450134 0, 0xFFFF, sum = 0
5479 09:28:04.450218 1, 0xFFFF, sum = 0
5480 09:28:04.453435 2, 0xFFFF, sum = 0
5481 09:28:04.453518 3, 0xFFFF, sum = 0
5482 09:28:04.456744 4, 0xFFFF, sum = 0
5483 09:28:04.460478 5, 0xFFFF, sum = 0
5484 09:28:04.460561 6, 0xFFFF, sum = 0
5485 09:28:04.463445 7, 0xFFFF, sum = 0
5486 09:28:04.463528 8, 0xFFFF, sum = 0
5487 09:28:04.466534 9, 0xFFFF, sum = 0
5488 09:28:04.466617 10, 0x0, sum = 1
5489 09:28:04.470004 11, 0x0, sum = 2
5490 09:28:04.470087 12, 0x0, sum = 3
5491 09:28:04.473352 13, 0x0, sum = 4
5492 09:28:04.473435 best_step = 11
5493 09:28:04.473500
5494 09:28:04.473560 ==
5495 09:28:04.476465 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 09:28:04.479874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 09:28:04.479956 ==
5498 09:28:04.483209 RX Vref Scan: 0
5499 09:28:04.483291
5500 09:28:04.486447 RX Vref 0 -> 0, step: 1
5501 09:28:04.486528
5502 09:28:04.486593 RX Delay -61 -> 252, step: 4
5503 09:28:04.494181 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5504 09:28:04.497907 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5505 09:28:04.501146 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5506 09:28:04.504769 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5507 09:28:04.507966 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5508 09:28:04.513881 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5509 09:28:04.517544 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5510 09:28:04.520447 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5511 09:28:04.523923 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5512 09:28:04.527078 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5513 09:28:04.533892 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5514 09:28:04.536957 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5515 09:28:04.540353 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5516 09:28:04.543940 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5517 09:28:04.547345 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5518 09:28:04.550276 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5519 09:28:04.553649 ==
5520 09:28:04.556955 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 09:28:04.560113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 09:28:04.560194 ==
5523 09:28:04.560259 DQS Delay:
5524 09:28:04.563437 DQS0 = 0, DQS1 = 0
5525 09:28:04.563517 DQM Delay:
5526 09:28:04.566832 DQM0 = 95, DQM1 = 88
5527 09:28:04.566913 DQ Delay:
5528 09:28:04.570474 DQ0 =94, DQ1 =96, DQ2 =90, DQ3 =94
5529 09:28:04.573319 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5530 09:28:04.576492 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5531 09:28:04.580590 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =94
5532 09:28:04.580671
5533 09:28:04.580735
5534 09:28:04.586681 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5535 09:28:04.590088 CH0 RK1: MR19=504, MR18=2BFB
5536 09:28:04.596317 CH0_RK1: MR19=0x504, MR18=0x2BFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5537 09:28:04.600019 [RxdqsGatingPostProcess] freq 933
5538 09:28:04.606753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 09:28:04.609481 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 09:28:04.609563 best DQS1 dly(2T, 0.5T) = (0, 11)
5541 09:28:04.613059 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 09:28:04.616856 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5543 09:28:04.619637 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 09:28:04.622775 best DQS1 dly(2T, 0.5T) = (0, 11)
5545 09:28:04.626299 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 09:28:04.629463 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5547 09:28:04.632941 Pre-setting of DQS Precalculation
5548 09:28:04.639645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 09:28:04.639748 ==
5550 09:28:04.643308 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 09:28:04.646383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 09:28:04.646464 ==
5553 09:28:04.652990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 09:28:04.656253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5555 09:28:04.660332 [CA 0] Center 36 (6~67) winsize 62
5556 09:28:04.663643 [CA 1] Center 36 (6~67) winsize 62
5557 09:28:04.667072 [CA 2] Center 34 (4~64) winsize 61
5558 09:28:04.670491 [CA 3] Center 33 (3~64) winsize 62
5559 09:28:04.673443 [CA 4] Center 34 (4~64) winsize 61
5560 09:28:04.676720 [CA 5] Center 33 (3~64) winsize 62
5561 09:28:04.676802
5562 09:28:04.680216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5563 09:28:04.680298
5564 09:28:04.683432 [CATrainingPosCal] consider 1 rank data
5565 09:28:04.686971 u2DelayCellTimex100 = 270/100 ps
5566 09:28:04.690097 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 09:28:04.696586 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 09:28:04.699907 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 09:28:04.703067 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 09:28:04.706669 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 09:28:04.709736 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 09:28:04.709817
5573 09:28:04.713302 CA PerBit enable=1, Macro0, CA PI delay=33
5574 09:28:04.713397
5575 09:28:04.716662 [CBTSetCACLKResult] CA Dly = 33
5576 09:28:04.719784 CS Dly: 6 (0~37)
5577 09:28:04.719865 ==
5578 09:28:04.723351 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 09:28:04.726730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 09:28:04.726812 ==
5581 09:28:04.732822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 09:28:04.736228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5583 09:28:04.740103 [CA 0] Center 36 (6~67) winsize 62
5584 09:28:04.743975 [CA 1] Center 37 (7~67) winsize 61
5585 09:28:04.746932 [CA 2] Center 34 (4~65) winsize 62
5586 09:28:04.750298 [CA 3] Center 33 (3~64) winsize 62
5587 09:28:04.753589 [CA 4] Center 34 (3~65) winsize 63
5588 09:28:04.756684 [CA 5] Center 33 (3~64) winsize 62
5589 09:28:04.756765
5590 09:28:04.760595 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5591 09:28:04.760675
5592 09:28:04.763209 [CATrainingPosCal] consider 2 rank data
5593 09:28:04.766997 u2DelayCellTimex100 = 270/100 ps
5594 09:28:04.769829 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 09:28:04.776825 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 09:28:04.779789 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 09:28:04.783053 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 09:28:04.786463 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5599 09:28:04.789661 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5600 09:28:04.789742
5601 09:28:04.792751 CA PerBit enable=1, Macro0, CA PI delay=33
5602 09:28:04.792849
5603 09:28:04.796269 [CBTSetCACLKResult] CA Dly = 33
5604 09:28:04.800412 CS Dly: 7 (0~39)
5605 09:28:04.800492
5606 09:28:04.803499 ----->DramcWriteLeveling(PI) begin...
5607 09:28:04.803581 ==
5608 09:28:04.806435 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 09:28:04.809433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 09:28:04.809515 ==
5611 09:28:04.813007 Write leveling (Byte 0): 26 => 26
5612 09:28:04.815959 Write leveling (Byte 1): 27 => 27
5613 09:28:04.819254 DramcWriteLeveling(PI) end<-----
5614 09:28:04.819335
5615 09:28:04.819399 ==
5616 09:28:04.822469 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 09:28:04.825718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 09:28:04.825847 ==
5619 09:28:04.829030 [Gating] SW mode calibration
5620 09:28:04.836108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 09:28:04.842229 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 09:28:04.845900 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5623 09:28:04.848969 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 09:28:04.855804 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 09:28:04.859057 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 09:28:04.865916 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 09:28:04.868814 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 09:28:04.872512 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
5629 09:28:04.875556 0 14 28 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
5630 09:28:04.882030 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5631 09:28:04.885666 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 09:28:04.888823 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 09:28:04.895592 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 09:28:04.899147 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 09:28:04.901695 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 09:28:04.908364 0 15 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5637 09:28:04.911840 0 15 28 | B1->B0 | 3434 3e3e | 1 1 | (0 0) (0 0)
5638 09:28:04.915131 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 09:28:04.921517 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 09:28:04.925066 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 09:28:04.928305 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 09:28:04.934765 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 09:28:04.938045 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5644 09:28:04.941448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 09:28:04.948066 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5646 09:28:04.951233 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:28:04.954725 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 09:28:04.961329 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 09:28:04.964666 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 09:28:04.967753 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 09:28:04.974549 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 09:28:04.977778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 09:28:04.981047 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 09:28:04.987434 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 09:28:04.991032 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 09:28:04.994295 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 09:28:05.001159 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 09:28:05.003956 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 09:28:05.007641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 09:28:05.014303 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 09:28:05.017222 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 09:28:05.020658 Total UI for P1: 0, mck2ui 16
5663 09:28:05.024033 best dqsien dly found for B0: ( 1, 2, 24)
5664 09:28:05.027155 Total UI for P1: 0, mck2ui 16
5665 09:28:05.030514 best dqsien dly found for B1: ( 1, 2, 24)
5666 09:28:05.033854 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5667 09:28:05.037300 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5668 09:28:05.037401
5669 09:28:05.040494 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5670 09:28:05.043492 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5671 09:28:05.047123 [Gating] SW calibration Done
5672 09:28:05.047222 ==
5673 09:28:05.050214 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 09:28:05.056600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 09:28:05.056696 ==
5676 09:28:05.056762 RX Vref Scan: 0
5677 09:28:05.056822
5678 09:28:05.060048 RX Vref 0 -> 0, step: 1
5679 09:28:05.060122
5680 09:28:05.063467 RX Delay -80 -> 252, step: 8
5681 09:28:05.066672 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5682 09:28:05.070216 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5683 09:28:05.073361 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5684 09:28:05.076235 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5685 09:28:05.082895 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5686 09:28:05.086258 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5687 09:28:05.089546 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5688 09:28:05.093145 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5689 09:28:05.096091 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5690 09:28:05.102890 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5691 09:28:05.106133 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5692 09:28:05.109540 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5693 09:28:05.113176 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5694 09:28:05.116025 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5695 09:28:05.122985 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5696 09:28:05.125899 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5697 09:28:05.125976 ==
5698 09:28:05.129555 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 09:28:05.132476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 09:28:05.132552 ==
5701 09:28:05.132615 DQS Delay:
5702 09:28:05.136164 DQS0 = 0, DQS1 = 0
5703 09:28:05.136237 DQM Delay:
5704 09:28:05.138923 DQM0 = 101, DQM1 = 90
5705 09:28:05.138993 DQ Delay:
5706 09:28:05.142441 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5707 09:28:05.145801 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5708 09:28:05.149339 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5709 09:28:05.152388 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5710 09:28:05.152461
5711 09:28:05.152524
5712 09:28:05.152583 ==
5713 09:28:05.155540 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 09:28:05.162831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 09:28:05.162921 ==
5716 09:28:05.163009
5717 09:28:05.163090
5718 09:28:05.163170 TX Vref Scan disable
5719 09:28:05.165957 == TX Byte 0 ==
5720 09:28:05.168804 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5721 09:28:05.175464 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5722 09:28:05.175568 == TX Byte 1 ==
5723 09:28:05.178646 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 09:28:05.185722 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 09:28:05.185830 ==
5726 09:28:05.188710 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 09:28:05.191959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 09:28:05.192048 ==
5729 09:28:05.192170
5730 09:28:05.192257
5731 09:28:05.195376 TX Vref Scan disable
5732 09:28:05.198439 == TX Byte 0 ==
5733 09:28:05.202101 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5734 09:28:05.205022 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5735 09:28:05.208429 == TX Byte 1 ==
5736 09:28:05.211608 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5737 09:28:05.215366 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5738 09:28:05.215468
5739 09:28:05.215563 [DATLAT]
5740 09:28:05.218512 Freq=933, CH1 RK0
5741 09:28:05.218599
5742 09:28:05.218660 DATLAT Default: 0xd
5743 09:28:05.221585 0, 0xFFFF, sum = 0
5744 09:28:05.225346 1, 0xFFFF, sum = 0
5745 09:28:05.225420 2, 0xFFFF, sum = 0
5746 09:28:05.228337 3, 0xFFFF, sum = 0
5747 09:28:05.228438 4, 0xFFFF, sum = 0
5748 09:28:05.231459 5, 0xFFFF, sum = 0
5749 09:28:05.231563 6, 0xFFFF, sum = 0
5750 09:28:05.235440 7, 0xFFFF, sum = 0
5751 09:28:05.235540 8, 0xFFFF, sum = 0
5752 09:28:05.238085 9, 0xFFFF, sum = 0
5753 09:28:05.238161 10, 0x0, sum = 1
5754 09:28:05.241748 11, 0x0, sum = 2
5755 09:28:05.241823 12, 0x0, sum = 3
5756 09:28:05.244510 13, 0x0, sum = 4
5757 09:28:05.244581 best_step = 11
5758 09:28:05.244642
5759 09:28:05.244703 ==
5760 09:28:05.248345 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 09:28:05.251287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 09:28:05.254630 ==
5763 09:28:05.254704 RX Vref Scan: 1
5764 09:28:05.254766
5765 09:28:05.258291 RX Vref 0 -> 0, step: 1
5766 09:28:05.258371
5767 09:28:05.258436 RX Delay -69 -> 252, step: 4
5768 09:28:05.261209
5769 09:28:05.261281 Set Vref, RX VrefLevel [Byte0]: 52
5770 09:28:05.264613 [Byte1]: 54
5771 09:28:05.269441
5772 09:28:05.269545 Final RX Vref Byte 0 = 52 to rank0
5773 09:28:05.272683 Final RX Vref Byte 1 = 54 to rank0
5774 09:28:05.276088 Final RX Vref Byte 0 = 52 to rank1
5775 09:28:05.279415 Final RX Vref Byte 1 = 54 to rank1==
5776 09:28:05.282711 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 09:28:05.289523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 09:28:05.289600 ==
5779 09:28:05.289668 DQS Delay:
5780 09:28:05.292594 DQS0 = 0, DQS1 = 0
5781 09:28:05.292668 DQM Delay:
5782 09:28:05.292729 DQM0 = 100, DQM1 = 93
5783 09:28:05.295843 DQ Delay:
5784 09:28:05.299223 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =96
5785 09:28:05.302663 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5786 09:28:05.305841 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5787 09:28:05.308926 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =102
5788 09:28:05.309024
5789 09:28:05.309112
5790 09:28:05.315716 [DQSOSCAuto] RK0, (LSB)MR18= 0x2010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 411 ps
5791 09:28:05.319040 CH1 RK0: MR19=505, MR18=2010
5792 09:28:05.325706 CH1_RK0: MR19=0x505, MR18=0x2010, DQSOSC=411, MR23=63, INC=64, DEC=42
5793 09:28:05.325817
5794 09:28:05.329230 ----->DramcWriteLeveling(PI) begin...
5795 09:28:05.329324 ==
5796 09:28:05.332856 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 09:28:05.335474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 09:28:05.338570 ==
5799 09:28:05.338645 Write leveling (Byte 0): 27 => 27
5800 09:28:05.341973 Write leveling (Byte 1): 28 => 28
5801 09:28:05.345212 DramcWriteLeveling(PI) end<-----
5802 09:28:05.345309
5803 09:28:05.345371 ==
5804 09:28:05.348710 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 09:28:05.355510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 09:28:05.355627 ==
5807 09:28:05.358425 [Gating] SW mode calibration
5808 09:28:05.365366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 09:28:05.368691 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 09:28:05.375140 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5811 09:28:05.378440 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 09:28:05.382113 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 09:28:05.388225 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 09:28:05.391677 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 09:28:05.395121 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 09:28:05.401686 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5817 09:28:05.404919 0 14 28 | B1->B0 | 2828 2828 | 0 0 | (1 0) (1 1)
5818 09:28:05.408111 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5819 09:28:05.414506 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 09:28:05.417888 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 09:28:05.421179 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 09:28:05.428217 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 09:28:05.431228 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 09:28:05.434454 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5825 09:28:05.441186 0 15 28 | B1->B0 | 4444 3a3a | 0 0 | (0 0) (0 0)
5826 09:28:05.444775 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 09:28:05.448397 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 09:28:05.454585 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 09:28:05.457668 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 09:28:05.460829 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 09:28:05.467516 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 09:28:05.471005 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 09:28:05.474133 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5834 09:28:05.477707 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:28:05.484010 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:28:05.487914 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 09:28:05.490864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 09:28:05.497886 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 09:28:05.500604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 09:28:05.503914 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 09:28:05.510615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 09:28:05.513905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 09:28:05.517219 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 09:28:05.523668 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 09:28:05.526848 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 09:28:05.530271 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 09:28:05.536716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 09:28:05.540543 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5849 09:28:05.543537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 09:28:05.550149 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 09:28:05.553529 Total UI for P1: 0, mck2ui 16
5852 09:28:05.557213 best dqsien dly found for B0: ( 1, 2, 28)
5853 09:28:05.559629 Total UI for P1: 0, mck2ui 16
5854 09:28:05.563216 best dqsien dly found for B1: ( 1, 2, 26)
5855 09:28:05.566453 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5856 09:28:05.569977 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5857 09:28:05.570057
5858 09:28:05.572920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5859 09:28:05.576332 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5860 09:28:05.579440 [Gating] SW calibration Done
5861 09:28:05.579512 ==
5862 09:28:05.582880 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 09:28:05.586584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 09:28:05.586661 ==
5865 09:28:05.590143 RX Vref Scan: 0
5866 09:28:05.590222
5867 09:28:05.592555 RX Vref 0 -> 0, step: 1
5868 09:28:05.592630
5869 09:28:05.592691 RX Delay -80 -> 252, step: 8
5870 09:28:05.599585 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5871 09:28:05.602763 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5872 09:28:05.605921 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5873 09:28:05.609991 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5874 09:28:05.613366 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5875 09:28:05.615818 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5876 09:28:05.622638 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5877 09:28:05.625718 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5878 09:28:05.629084 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5879 09:28:05.632433 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5880 09:28:05.635884 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5881 09:28:05.642585 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5882 09:28:05.645897 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5883 09:28:05.649240 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5884 09:28:05.652399 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5885 09:28:05.655903 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5886 09:28:05.655983 ==
5887 09:28:05.658860 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 09:28:05.665666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 09:28:05.665753 ==
5890 09:28:05.665822 DQS Delay:
5891 09:28:05.668716 DQS0 = 0, DQS1 = 0
5892 09:28:05.668789 DQM Delay:
5893 09:28:05.668853 DQM0 = 100, DQM1 = 90
5894 09:28:05.672272 DQ Delay:
5895 09:28:05.675582 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5896 09:28:05.678895 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5897 09:28:05.681915 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5898 09:28:05.685319 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5899 09:28:05.685433
5900 09:28:05.685515
5901 09:28:05.685615 ==
5902 09:28:05.688651 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 09:28:05.692083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 09:28:05.692159 ==
5905 09:28:05.692226
5906 09:28:05.692286
5907 09:28:05.695299 TX Vref Scan disable
5908 09:28:05.698495 == TX Byte 0 ==
5909 09:28:05.702146 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5910 09:28:05.705198 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5911 09:28:05.708473 == TX Byte 1 ==
5912 09:28:05.711686 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 09:28:05.715325 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 09:28:05.715429 ==
5915 09:28:05.718384 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 09:28:05.725156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 09:28:05.725239 ==
5918 09:28:05.725306
5919 09:28:05.725371
5920 09:28:05.725436 TX Vref Scan disable
5921 09:28:05.728917 == TX Byte 0 ==
5922 09:28:05.732079 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 09:28:05.738660 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 09:28:05.738746 == TX Byte 1 ==
5925 09:28:05.741907 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5926 09:28:05.748748 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5927 09:28:05.748836
5928 09:28:05.748900 [DATLAT]
5929 09:28:05.748964 Freq=933, CH1 RK1
5930 09:28:05.749022
5931 09:28:05.751881 DATLAT Default: 0xb
5932 09:28:05.755367 0, 0xFFFF, sum = 0
5933 09:28:05.755447 1, 0xFFFF, sum = 0
5934 09:28:05.758357 2, 0xFFFF, sum = 0
5935 09:28:05.758434 3, 0xFFFF, sum = 0
5936 09:28:05.762134 4, 0xFFFF, sum = 0
5937 09:28:05.762212 5, 0xFFFF, sum = 0
5938 09:28:05.765572 6, 0xFFFF, sum = 0
5939 09:28:05.765651 7, 0xFFFF, sum = 0
5940 09:28:05.768505 8, 0xFFFF, sum = 0
5941 09:28:05.768587 9, 0xFFFF, sum = 0
5942 09:28:05.772064 10, 0x0, sum = 1
5943 09:28:05.772142 11, 0x0, sum = 2
5944 09:28:05.775184 12, 0x0, sum = 3
5945 09:28:05.775257 13, 0x0, sum = 4
5946 09:28:05.775318 best_step = 11
5947 09:28:05.778392
5948 09:28:05.778471 ==
5949 09:28:05.781812 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 09:28:05.785392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 09:28:05.785474 ==
5952 09:28:05.785541 RX Vref Scan: 0
5953 09:28:05.785601
5954 09:28:05.788404 RX Vref 0 -> 0, step: 1
5955 09:28:05.788476
5956 09:28:05.791845 RX Delay -69 -> 252, step: 4
5957 09:28:05.798367 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5958 09:28:05.801332 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
5959 09:28:05.804542 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5960 09:28:05.808319 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
5961 09:28:05.811758 iDelay=207, Bit 4, Center 102 (11 ~ 194) 184
5962 09:28:05.814691 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5963 09:28:05.821831 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5964 09:28:05.824351 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5965 09:28:05.827646 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5966 09:28:05.830950 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5967 09:28:05.834792 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5968 09:28:05.841341 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5969 09:28:05.844345 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5970 09:28:05.847860 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5971 09:28:05.850992 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5972 09:28:05.854352 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5973 09:28:05.857606 ==
5974 09:28:05.861958 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 09:28:05.864440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 09:28:05.864538 ==
5977 09:28:05.864628 DQS Delay:
5978 09:28:05.867803 DQS0 = 0, DQS1 = 0
5979 09:28:05.867910 DQM Delay:
5980 09:28:05.870836 DQM0 = 101, DQM1 = 94
5981 09:28:05.870920 DQ Delay:
5982 09:28:05.873972 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =96
5983 09:28:05.877076 DQ4 =102, DQ5 =112, DQ6 =116, DQ7 =98
5984 09:28:05.880575 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5985 09:28:05.884261 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =102
5986 09:28:05.884347
5987 09:28:05.884434
5988 09:28:05.893930 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5989 09:28:05.894023 CH1 RK1: MR19=505, MR18=600
5990 09:28:05.901643 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
5991 09:28:05.903553 [RxdqsGatingPostProcess] freq 933
5992 09:28:05.910316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5993 09:28:05.913925 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 09:28:05.916820 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 09:28:05.920799 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 09:28:05.923452 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 09:28:05.926932 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 09:28:05.927018 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 09:28:05.930409 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 09:28:05.933355 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 09:28:05.936409 Pre-setting of DQS Precalculation
6002 09:28:05.943178 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6003 09:28:05.949842 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6004 09:28:05.956458 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6005 09:28:05.956585
6006 09:28:05.956681
6007 09:28:05.960050 [Calibration Summary] 1866 Mbps
6008 09:28:05.962786 CH 0, Rank 0
6009 09:28:05.962872 SW Impedance : PASS
6010 09:28:05.966089 DUTY Scan : NO K
6011 09:28:05.969973 ZQ Calibration : PASS
6012 09:28:05.970057 Jitter Meter : NO K
6013 09:28:05.973060 CBT Training : PASS
6014 09:28:05.977217 Write leveling : PASS
6015 09:28:05.977300 RX DQS gating : PASS
6016 09:28:05.979511 RX DQ/DQS(RDDQC) : PASS
6017 09:28:05.979592 TX DQ/DQS : PASS
6018 09:28:05.982636 RX DATLAT : PASS
6019 09:28:05.985997 RX DQ/DQS(Engine): PASS
6020 09:28:05.986079 TX OE : NO K
6021 09:28:05.989479 All Pass.
6022 09:28:05.989560
6023 09:28:05.989625 CH 0, Rank 1
6024 09:28:05.992365 SW Impedance : PASS
6025 09:28:05.992446 DUTY Scan : NO K
6026 09:28:05.995646 ZQ Calibration : PASS
6027 09:28:05.999317 Jitter Meter : NO K
6028 09:28:05.999413 CBT Training : PASS
6029 09:28:06.002771 Write leveling : PASS
6030 09:28:06.006025 RX DQS gating : PASS
6031 09:28:06.006116 RX DQ/DQS(RDDQC) : PASS
6032 09:28:06.009202 TX DQ/DQS : PASS
6033 09:28:06.012258 RX DATLAT : PASS
6034 09:28:06.012341 RX DQ/DQS(Engine): PASS
6035 09:28:06.015767 TX OE : NO K
6036 09:28:06.015850 All Pass.
6037 09:28:06.015916
6038 09:28:06.018963 CH 1, Rank 0
6039 09:28:06.019044 SW Impedance : PASS
6040 09:28:06.022793 DUTY Scan : NO K
6041 09:28:06.025669 ZQ Calibration : PASS
6042 09:28:06.025754 Jitter Meter : NO K
6043 09:28:06.028758 CBT Training : PASS
6044 09:28:06.032249 Write leveling : PASS
6045 09:28:06.032335 RX DQS gating : PASS
6046 09:28:06.035243 RX DQ/DQS(RDDQC) : PASS
6047 09:28:06.038571 TX DQ/DQS : PASS
6048 09:28:06.038674 RX DATLAT : PASS
6049 09:28:06.041978 RX DQ/DQS(Engine): PASS
6050 09:28:06.045309 TX OE : NO K
6051 09:28:06.045408 All Pass.
6052 09:28:06.045495
6053 09:28:06.045557 CH 1, Rank 1
6054 09:28:06.048690 SW Impedance : PASS
6055 09:28:06.051985 DUTY Scan : NO K
6056 09:28:06.052091 ZQ Calibration : PASS
6057 09:28:06.055118 Jitter Meter : NO K
6058 09:28:06.058644 CBT Training : PASS
6059 09:28:06.058724 Write leveling : PASS
6060 09:28:06.061840 RX DQS gating : PASS
6061 09:28:06.061939 RX DQ/DQS(RDDQC) : PASS
6062 09:28:06.065032 TX DQ/DQS : PASS
6063 09:28:06.068692 RX DATLAT : PASS
6064 09:28:06.068803 RX DQ/DQS(Engine): PASS
6065 09:28:06.071731 TX OE : NO K
6066 09:28:06.071852 All Pass.
6067 09:28:06.071945
6068 09:28:06.074951 DramC Write-DBI off
6069 09:28:06.078102 PER_BANK_REFRESH: Hybrid Mode
6070 09:28:06.078184 TX_TRACKING: ON
6071 09:28:06.088363 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6072 09:28:06.091243 [FAST_K] Save calibration result to emmc
6073 09:28:06.095003 dramc_set_vcore_voltage set vcore to 650000
6074 09:28:06.097836 Read voltage for 400, 6
6075 09:28:06.097918 Vio18 = 0
6076 09:28:06.101493 Vcore = 650000
6077 09:28:06.101574 Vdram = 0
6078 09:28:06.101639 Vddq = 0
6079 09:28:06.101700 Vmddr = 0
6080 09:28:06.107713 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6081 09:28:06.114464 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6082 09:28:06.114547 MEM_TYPE=3, freq_sel=20
6083 09:28:06.117869 sv_algorithm_assistance_LP4_800
6084 09:28:06.121131 ============ PULL DRAM RESETB DOWN ============
6085 09:28:06.127883 ========== PULL DRAM RESETB DOWN end =========
6086 09:28:06.131093 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6087 09:28:06.134285 ===================================
6088 09:28:06.137587 LPDDR4 DRAM CONFIGURATION
6089 09:28:06.140891 ===================================
6090 09:28:06.140974 EX_ROW_EN[0] = 0x0
6091 09:28:06.144263 EX_ROW_EN[1] = 0x0
6092 09:28:06.147186 LP4Y_EN = 0x0
6093 09:28:06.147267 WORK_FSP = 0x0
6094 09:28:06.150754 WL = 0x2
6095 09:28:06.150836 RL = 0x2
6096 09:28:06.154124 BL = 0x2
6097 09:28:06.154205 RPST = 0x0
6098 09:28:06.156960 RD_PRE = 0x0
6099 09:28:06.157042 WR_PRE = 0x1
6100 09:28:06.160550 WR_PST = 0x0
6101 09:28:06.160632 DBI_WR = 0x0
6102 09:28:06.163601 DBI_RD = 0x0
6103 09:28:06.163682 OTF = 0x1
6104 09:28:06.166811 ===================================
6105 09:28:06.170611 ===================================
6106 09:28:06.173587 ANA top config
6107 09:28:06.176989 ===================================
6108 09:28:06.180249 DLL_ASYNC_EN = 0
6109 09:28:06.180333 ALL_SLAVE_EN = 1
6110 09:28:06.183281 NEW_RANK_MODE = 1
6111 09:28:06.186859 DLL_IDLE_MODE = 1
6112 09:28:06.190029 LP45_APHY_COMB_EN = 1
6113 09:28:06.190110 TX_ODT_DIS = 1
6114 09:28:06.193893 NEW_8X_MODE = 1
6115 09:28:06.196794 ===================================
6116 09:28:06.200262 ===================================
6117 09:28:06.203600 data_rate = 800
6118 09:28:06.206713 CKR = 1
6119 09:28:06.210453 DQ_P2S_RATIO = 4
6120 09:28:06.213660 ===================================
6121 09:28:06.216362 CA_P2S_RATIO = 4
6122 09:28:06.216444 DQ_CA_OPEN = 0
6123 09:28:06.219836 DQ_SEMI_OPEN = 1
6124 09:28:06.223589 CA_SEMI_OPEN = 1
6125 09:28:06.226372 CA_FULL_RATE = 0
6126 09:28:06.230132 DQ_CKDIV4_EN = 0
6127 09:28:06.233249 CA_CKDIV4_EN = 1
6128 09:28:06.233330 CA_PREDIV_EN = 0
6129 09:28:06.236826 PH8_DLY = 0
6130 09:28:06.239776 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6131 09:28:06.243076 DQ_AAMCK_DIV = 0
6132 09:28:06.246093 CA_AAMCK_DIV = 0
6133 09:28:06.249842 CA_ADMCK_DIV = 4
6134 09:28:06.249950 DQ_TRACK_CA_EN = 0
6135 09:28:06.253097 CA_PICK = 800
6136 09:28:06.256053 CA_MCKIO = 400
6137 09:28:06.259332 MCKIO_SEMI = 400
6138 09:28:06.262484 PLL_FREQ = 3016
6139 09:28:06.266200 DQ_UI_PI_RATIO = 32
6140 09:28:06.269746 CA_UI_PI_RATIO = 32
6141 09:28:06.272769 ===================================
6142 09:28:06.276200 ===================================
6143 09:28:06.276282 memory_type:LPDDR4
6144 09:28:06.279478 GP_NUM : 10
6145 09:28:06.282728 SRAM_EN : 1
6146 09:28:06.282809 MD32_EN : 0
6147 09:28:06.285688 ===================================
6148 09:28:06.289565 [ANA_INIT] >>>>>>>>>>>>>>
6149 09:28:06.292586 <<<<<< [CONFIGURE PHASE]: ANA_TX
6150 09:28:06.295903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6151 09:28:06.299160 ===================================
6152 09:28:06.302948 data_rate = 800,PCW = 0X7400
6153 09:28:06.305498 ===================================
6154 09:28:06.309043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6155 09:28:06.312802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 09:28:06.325342 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 09:28:06.328919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6158 09:28:06.332434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6159 09:28:06.335304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6160 09:28:06.338706 [ANA_INIT] flow start
6161 09:28:06.341856 [ANA_INIT] PLL >>>>>>>>
6162 09:28:06.341938 [ANA_INIT] PLL <<<<<<<<
6163 09:28:06.345118 [ANA_INIT] MIDPI >>>>>>>>
6164 09:28:06.348638 [ANA_INIT] MIDPI <<<<<<<<
6165 09:28:06.351756 [ANA_INIT] DLL >>>>>>>>
6166 09:28:06.351851 [ANA_INIT] flow end
6167 09:28:06.355082 ============ LP4 DIFF to SE enter ============
6168 09:28:06.361519 ============ LP4 DIFF to SE exit ============
6169 09:28:06.361603 [ANA_INIT] <<<<<<<<<<<<<
6170 09:28:06.364989 [Flow] Enable top DCM control >>>>>
6171 09:28:06.368144 [Flow] Enable top DCM control <<<<<
6172 09:28:06.371352 Enable DLL master slave shuffle
6173 09:28:06.378515 ==============================================================
6174 09:28:06.378599 Gating Mode config
6175 09:28:06.384570 ==============================================================
6176 09:28:06.388181 Config description:
6177 09:28:06.397646 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6178 09:28:06.404430 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6179 09:28:06.408059 SELPH_MODE 0: By rank 1: By Phase
6180 09:28:06.414890 ==============================================================
6181 09:28:06.417627 GAT_TRACK_EN = 0
6182 09:28:06.421568 RX_GATING_MODE = 2
6183 09:28:06.421651 RX_GATING_TRACK_MODE = 2
6184 09:28:06.424211 SELPH_MODE = 1
6185 09:28:06.427709 PICG_EARLY_EN = 1
6186 09:28:06.430965 VALID_LAT_VALUE = 1
6187 09:28:06.437798 ==============================================================
6188 09:28:06.440621 Enter into Gating configuration >>>>
6189 09:28:06.443971 Exit from Gating configuration <<<<
6190 09:28:06.447110 Enter into DVFS_PRE_config >>>>>
6191 09:28:06.456971 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6192 09:28:06.460840 Exit from DVFS_PRE_config <<<<<
6193 09:28:06.463715 Enter into PICG configuration >>>>
6194 09:28:06.467582 Exit from PICG configuration <<<<
6195 09:28:06.470496 [RX_INPUT] configuration >>>>>
6196 09:28:06.473646 [RX_INPUT] configuration <<<<<
6197 09:28:06.477242 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6198 09:28:06.483460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6199 09:28:06.490256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 09:28:06.496533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 09:28:06.503124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 09:28:06.509843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 09:28:06.513291 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6204 09:28:06.516278 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6205 09:28:06.519868 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6206 09:28:06.526340 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6207 09:28:06.529744 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6208 09:28:06.533305 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 09:28:06.536093 ===================================
6210 09:28:06.539667 LPDDR4 DRAM CONFIGURATION
6211 09:28:06.543041 ===================================
6212 09:28:06.543122 EX_ROW_EN[0] = 0x0
6213 09:28:06.546107 EX_ROW_EN[1] = 0x0
6214 09:28:06.546188 LP4Y_EN = 0x0
6215 09:28:06.549500 WORK_FSP = 0x0
6216 09:28:06.552571 WL = 0x2
6217 09:28:06.552653 RL = 0x2
6218 09:28:06.555944 BL = 0x2
6219 09:28:06.556025 RPST = 0x0
6220 09:28:06.559110 RD_PRE = 0x0
6221 09:28:06.559191 WR_PRE = 0x1
6222 09:28:06.563003 WR_PST = 0x0
6223 09:28:06.563159 DBI_WR = 0x0
6224 09:28:06.566051 DBI_RD = 0x0
6225 09:28:06.566127 OTF = 0x1
6226 09:28:06.569190 ===================================
6227 09:28:06.572536 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6228 09:28:06.579255 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6229 09:28:06.582241 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 09:28:06.585657 ===================================
6231 09:28:06.589087 LPDDR4 DRAM CONFIGURATION
6232 09:28:06.592563 ===================================
6233 09:28:06.592633 EX_ROW_EN[0] = 0x10
6234 09:28:06.595472 EX_ROW_EN[1] = 0x0
6235 09:28:06.595566 LP4Y_EN = 0x0
6236 09:28:06.598935 WORK_FSP = 0x0
6237 09:28:06.602354 WL = 0x2
6238 09:28:06.602422 RL = 0x2
6239 09:28:06.605986 BL = 0x2
6240 09:28:06.606054 RPST = 0x0
6241 09:28:06.609248 RD_PRE = 0x0
6242 09:28:06.609317 WR_PRE = 0x1
6243 09:28:06.612249 WR_PST = 0x0
6244 09:28:06.612323 DBI_WR = 0x0
6245 09:28:06.615441 DBI_RD = 0x0
6246 09:28:06.615542 OTF = 0x1
6247 09:28:06.618859 ===================================
6248 09:28:06.625404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6249 09:28:06.629640 nWR fixed to 30
6250 09:28:06.632812 [ModeRegInit_LP4] CH0 RK0
6251 09:28:06.632882 [ModeRegInit_LP4] CH0 RK1
6252 09:28:06.635970 [ModeRegInit_LP4] CH1 RK0
6253 09:28:06.639168 [ModeRegInit_LP4] CH1 RK1
6254 09:28:06.639238 match AC timing 19
6255 09:28:06.645780 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6256 09:28:06.649536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6257 09:28:06.652725 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6258 09:28:06.658952 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6259 09:28:06.662445 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6260 09:28:06.662516 ==
6261 09:28:06.665994 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 09:28:06.669091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 09:28:06.669194 ==
6264 09:28:06.675759 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 09:28:06.682390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6266 09:28:06.685324 [CA 0] Center 36 (8~64) winsize 57
6267 09:28:06.688694 [CA 1] Center 36 (8~64) winsize 57
6268 09:28:06.691852 [CA 2] Center 36 (8~64) winsize 57
6269 09:28:06.694983 [CA 3] Center 36 (8~64) winsize 57
6270 09:28:06.698403 [CA 4] Center 36 (8~64) winsize 57
6271 09:28:06.701637 [CA 5] Center 36 (8~64) winsize 57
6272 09:28:06.701747
6273 09:28:06.704963 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6274 09:28:06.705063
6275 09:28:06.708156 [CATrainingPosCal] consider 1 rank data
6276 09:28:06.711455 u2DelayCellTimex100 = 270/100 ps
6277 09:28:06.715117 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 09:28:06.718263 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 09:28:06.721883 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 09:28:06.725180 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 09:28:06.727990 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 09:28:06.731611 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 09:28:06.731705
6284 09:28:06.738076 CA PerBit enable=1, Macro0, CA PI delay=36
6285 09:28:06.738150
6286 09:28:06.738212 [CBTSetCACLKResult] CA Dly = 36
6287 09:28:06.741212 CS Dly: 1 (0~32)
6288 09:28:06.741283 ==
6289 09:28:06.744657 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 09:28:06.747867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 09:28:06.747942 ==
6292 09:28:06.754473 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 09:28:06.761314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6294 09:28:06.764198 [CA 0] Center 36 (8~64) winsize 57
6295 09:28:06.767607 [CA 1] Center 36 (8~64) winsize 57
6296 09:28:06.771161 [CA 2] Center 36 (8~64) winsize 57
6297 09:28:06.774448 [CA 3] Center 36 (8~64) winsize 57
6298 09:28:06.777532 [CA 4] Center 36 (8~64) winsize 57
6299 09:28:06.777602 [CA 5] Center 36 (8~64) winsize 57
6300 09:28:06.780756
6301 09:28:06.784343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6302 09:28:06.784417
6303 09:28:06.788181 [CATrainingPosCal] consider 2 rank data
6304 09:28:06.791258 u2DelayCellTimex100 = 270/100 ps
6305 09:28:06.794601 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 09:28:06.797721 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 09:28:06.800975 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 09:28:06.804013 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 09:28:06.807541 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 09:28:06.810370 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 09:28:06.810444
6312 09:28:06.814388 CA PerBit enable=1, Macro0, CA PI delay=36
6313 09:28:06.814466
6314 09:28:06.817026 [CBTSetCACLKResult] CA Dly = 36
6315 09:28:06.820608 CS Dly: 1 (0~32)
6316 09:28:06.820692
6317 09:28:06.824187 ----->DramcWriteLeveling(PI) begin...
6318 09:28:06.824261 ==
6319 09:28:06.827425 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 09:28:06.831725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 09:28:06.831824 ==
6322 09:28:06.834107 Write leveling (Byte 0): 40 => 8
6323 09:28:06.837118 Write leveling (Byte 1): 32 => 0
6324 09:28:06.840568 DramcWriteLeveling(PI) end<-----
6325 09:28:06.840650
6326 09:28:06.840714 ==
6327 09:28:06.843659 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 09:28:06.847315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 09:28:06.847397 ==
6330 09:28:06.850453 [Gating] SW mode calibration
6331 09:28:06.857629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6332 09:28:06.863424 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6333 09:28:06.867180 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 09:28:06.873267 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 09:28:06.877063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 09:28:06.879998 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 09:28:06.886559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 09:28:06.889738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 09:28:06.893057 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 09:28:06.899852 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 09:28:06.903065 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 09:28:06.906218 Total UI for P1: 0, mck2ui 16
6343 09:28:06.910007 best dqsien dly found for B0: ( 0, 14, 24)
6344 09:28:06.913195 Total UI for P1: 0, mck2ui 16
6345 09:28:06.916312 best dqsien dly found for B1: ( 0, 14, 24)
6346 09:28:06.919581 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6347 09:28:06.923133 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6348 09:28:06.923214
6349 09:28:06.926130 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 09:28:06.929610 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 09:28:06.932947 [Gating] SW calibration Done
6352 09:28:06.933029 ==
6353 09:28:06.935904 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 09:28:06.942490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 09:28:06.942570 ==
6356 09:28:06.942635 RX Vref Scan: 0
6357 09:28:06.942695
6358 09:28:06.945707 RX Vref 0 -> 0, step: 1
6359 09:28:06.945787
6360 09:28:06.949159 RX Delay -410 -> 252, step: 16
6361 09:28:06.952237 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6362 09:28:06.955381 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6363 09:28:06.962211 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6364 09:28:06.965358 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6365 09:28:06.969008 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6366 09:28:06.972399 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6367 09:28:06.979431 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6368 09:28:06.982017 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6369 09:28:06.985454 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6370 09:28:06.989140 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6371 09:28:06.995583 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6372 09:28:06.998692 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6373 09:28:07.002142 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6374 09:28:07.005374 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6375 09:28:07.011974 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6376 09:28:07.015294 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6377 09:28:07.015366 ==
6378 09:28:07.018544 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 09:28:07.021727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 09:28:07.021800 ==
6381 09:28:07.024980 DQS Delay:
6382 09:28:07.025053 DQS0 = 43, DQS1 = 59
6383 09:28:07.028429 DQM Delay:
6384 09:28:07.028501 DQM0 = 10, DQM1 = 13
6385 09:28:07.028561 DQ Delay:
6386 09:28:07.031455 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6387 09:28:07.034731 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6388 09:28:07.038316 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6389 09:28:07.041638 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6390 09:28:07.041709
6391 09:28:07.041770
6392 09:28:07.041826 ==
6393 09:28:07.045004 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 09:28:07.051401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 09:28:07.051496 ==
6396 09:28:07.051562
6397 09:28:07.051620
6398 09:28:07.051679 TX Vref Scan disable
6399 09:28:07.054812 == TX Byte 0 ==
6400 09:28:07.058198 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 09:28:07.061010 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 09:28:07.064757 == TX Byte 1 ==
6403 09:28:07.067869 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 09:28:07.074599 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 09:28:07.074706 ==
6406 09:28:07.077535 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 09:28:07.081353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 09:28:07.081466 ==
6409 09:28:07.081562
6410 09:28:07.081657
6411 09:28:07.084381 TX Vref Scan disable
6412 09:28:07.084460 == TX Byte 0 ==
6413 09:28:07.087652 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 09:28:07.094137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 09:28:07.094218 == TX Byte 1 ==
6416 09:28:07.097405 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6417 09:28:07.103928 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6418 09:28:07.104011
6419 09:28:07.104076 [DATLAT]
6420 09:28:07.104136 Freq=400, CH0 RK0
6421 09:28:07.107439
6422 09:28:07.107523 DATLAT Default: 0xf
6423 09:28:07.110828 0, 0xFFFF, sum = 0
6424 09:28:07.110912 1, 0xFFFF, sum = 0
6425 09:28:07.113945 2, 0xFFFF, sum = 0
6426 09:28:07.114027 3, 0xFFFF, sum = 0
6427 09:28:07.117179 4, 0xFFFF, sum = 0
6428 09:28:07.117263 5, 0xFFFF, sum = 0
6429 09:28:07.120881 6, 0xFFFF, sum = 0
6430 09:28:07.120965 7, 0xFFFF, sum = 0
6431 09:28:07.123888 8, 0xFFFF, sum = 0
6432 09:28:07.123971 9, 0xFFFF, sum = 0
6433 09:28:07.127570 10, 0xFFFF, sum = 0
6434 09:28:07.127653 11, 0xFFFF, sum = 0
6435 09:28:07.130735 12, 0xFFFF, sum = 0
6436 09:28:07.130818 13, 0x0, sum = 1
6437 09:28:07.133782 14, 0x0, sum = 2
6438 09:28:07.133873 15, 0x0, sum = 3
6439 09:28:07.137383 16, 0x0, sum = 4
6440 09:28:07.137466 best_step = 14
6441 09:28:07.137530
6442 09:28:07.137590 ==
6443 09:28:07.140353 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 09:28:07.147046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 09:28:07.147129 ==
6446 09:28:07.147193 RX Vref Scan: 1
6447 09:28:07.147254
6448 09:28:07.150287 RX Vref 0 -> 0, step: 1
6449 09:28:07.150368
6450 09:28:07.153612 RX Delay -359 -> 252, step: 8
6451 09:28:07.153694
6452 09:28:07.157070 Set Vref, RX VrefLevel [Byte0]: 59
6453 09:28:07.160159 [Byte1]: 59
6454 09:28:07.163382
6455 09:28:07.163462 Final RX Vref Byte 0 = 59 to rank0
6456 09:28:07.166798 Final RX Vref Byte 1 = 59 to rank0
6457 09:28:07.170015 Final RX Vref Byte 0 = 59 to rank1
6458 09:28:07.173323 Final RX Vref Byte 1 = 59 to rank1==
6459 09:28:07.176737 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 09:28:07.183133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 09:28:07.183216 ==
6462 09:28:07.183282 DQS Delay:
6463 09:28:07.186479 DQS0 = 48, DQS1 = 60
6464 09:28:07.186560 DQM Delay:
6465 09:28:07.186624 DQM0 = 12, DQM1 = 12
6466 09:28:07.189759 DQ Delay:
6467 09:28:07.193049 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6468 09:28:07.196409 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6469 09:28:07.196491 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6470 09:28:07.200191 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6471 09:28:07.203058
6472 09:28:07.203190
6473 09:28:07.209557 [DQSOSCAuto] RK0, (LSB)MR18= 0xc487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6474 09:28:07.213004 CH0 RK0: MR19=C0C, MR18=C487
6475 09:28:07.219584 CH0_RK0: MR19=0xC0C, MR18=0xC487, DQSOSC=385, MR23=63, INC=398, DEC=265
6476 09:28:07.219715 ==
6477 09:28:07.222796 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 09:28:07.226030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 09:28:07.226113 ==
6480 09:28:07.229830 [Gating] SW mode calibration
6481 09:28:07.236627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6482 09:28:07.242656 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6483 09:28:07.245743 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 09:28:07.249034 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 09:28:07.255745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 09:28:07.258847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 09:28:07.262206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 09:28:07.269454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 09:28:07.271927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 09:28:07.275379 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 09:28:07.281975 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 09:28:07.285403 Total UI for P1: 0, mck2ui 16
6493 09:28:07.288634 best dqsien dly found for B0: ( 0, 14, 24)
6494 09:28:07.292173 Total UI for P1: 0, mck2ui 16
6495 09:28:07.295076 best dqsien dly found for B1: ( 0, 14, 24)
6496 09:28:07.299008 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6497 09:28:07.301875 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6498 09:28:07.301946
6499 09:28:07.305240 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 09:28:07.308372 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 09:28:07.312051 [Gating] SW calibration Done
6502 09:28:07.312131 ==
6503 09:28:07.315291 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 09:28:07.318309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 09:28:07.318382 ==
6506 09:28:07.321718 RX Vref Scan: 0
6507 09:28:07.321787
6508 09:28:07.325524 RX Vref 0 -> 0, step: 1
6509 09:28:07.325596
6510 09:28:07.325659 RX Delay -410 -> 252, step: 16
6511 09:28:07.332275 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6512 09:28:07.335255 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6513 09:28:07.338346 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6514 09:28:07.345260 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6515 09:28:07.348354 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6516 09:28:07.351436 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6517 09:28:07.355161 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6518 09:28:07.361620 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6519 09:28:07.364442 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6520 09:28:07.367862 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6521 09:28:07.371332 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6522 09:28:07.377665 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6523 09:28:07.381265 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6524 09:28:07.384353 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6525 09:28:07.387717 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6526 09:28:07.394422 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6527 09:28:07.394506 ==
6528 09:28:07.397572 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 09:28:07.401343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 09:28:07.401427 ==
6531 09:28:07.403869 DQS Delay:
6532 09:28:07.403952 DQS0 = 43, DQS1 = 59
6533 09:28:07.404020 DQM Delay:
6534 09:28:07.407488 DQM0 = 11, DQM1 = 16
6535 09:28:07.407570 DQ Delay:
6536 09:28:07.410692 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6537 09:28:07.413988 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6538 09:28:07.417677 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6539 09:28:07.420504 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6540 09:28:07.420587
6541 09:28:07.420652
6542 09:28:07.420713 ==
6543 09:28:07.423853 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 09:28:07.427415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 09:28:07.427497 ==
6546 09:28:07.430818
6547 09:28:07.430899
6548 09:28:07.430964 TX Vref Scan disable
6549 09:28:07.433842 == TX Byte 0 ==
6550 09:28:07.437140 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6551 09:28:07.440469 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6552 09:28:07.443595 == TX Byte 1 ==
6553 09:28:07.447035 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6554 09:28:07.450386 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6555 09:28:07.450467 ==
6556 09:28:07.453738 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 09:28:07.457026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 09:28:07.460228 ==
6559 09:28:07.460311
6560 09:28:07.460375
6561 09:28:07.460435 TX Vref Scan disable
6562 09:28:07.463511 == TX Byte 0 ==
6563 09:28:07.466877 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6564 09:28:07.470470 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6565 09:28:07.473412 == TX Byte 1 ==
6566 09:28:07.476818 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6567 09:28:07.479901 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6568 09:28:07.479984
6569 09:28:07.483280 [DATLAT]
6570 09:28:07.483373 Freq=400, CH0 RK1
6571 09:28:07.483444
6572 09:28:07.486501 DATLAT Default: 0xe
6573 09:28:07.486583 0, 0xFFFF, sum = 0
6574 09:28:07.490008 1, 0xFFFF, sum = 0
6575 09:28:07.490092 2, 0xFFFF, sum = 0
6576 09:28:07.493412 3, 0xFFFF, sum = 0
6577 09:28:07.493496 4, 0xFFFF, sum = 0
6578 09:28:07.496347 5, 0xFFFF, sum = 0
6579 09:28:07.496470 6, 0xFFFF, sum = 0
6580 09:28:07.499818 7, 0xFFFF, sum = 0
6581 09:28:07.499895 8, 0xFFFF, sum = 0
6582 09:28:07.503526 9, 0xFFFF, sum = 0
6583 09:28:07.503629 10, 0xFFFF, sum = 0
6584 09:28:07.506198 11, 0xFFFF, sum = 0
6585 09:28:07.509690 12, 0xFFFF, sum = 0
6586 09:28:07.509767 13, 0x0, sum = 1
6587 09:28:07.509834 14, 0x0, sum = 2
6588 09:28:07.513121 15, 0x0, sum = 3
6589 09:28:07.513195 16, 0x0, sum = 4
6590 09:28:07.516310 best_step = 14
6591 09:28:07.516404
6592 09:28:07.516492 ==
6593 09:28:07.519453 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 09:28:07.522846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 09:28:07.522929 ==
6596 09:28:07.526177 RX Vref Scan: 0
6597 09:28:07.526259
6598 09:28:07.526376 RX Vref 0 -> 0, step: 1
6599 09:28:07.526463
6600 09:28:07.529441 RX Delay -359 -> 252, step: 8
6601 09:28:07.538058 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6602 09:28:07.541606 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6603 09:28:07.544660 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6604 09:28:07.550924 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6605 09:28:07.554423 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6606 09:28:07.557589 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6607 09:28:07.561120 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6608 09:28:07.567293 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6609 09:28:07.571091 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6610 09:28:07.573979 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6611 09:28:07.577464 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6612 09:28:07.584200 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6613 09:28:07.587111 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6614 09:28:07.590542 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6615 09:28:07.594002 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6616 09:28:07.600819 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6617 09:28:07.600904 ==
6618 09:28:07.603442 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 09:28:07.607032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 09:28:07.607116 ==
6621 09:28:07.607181 DQS Delay:
6622 09:28:07.610500 DQS0 = 44, DQS1 = 60
6623 09:28:07.610587 DQM Delay:
6624 09:28:07.613807 DQM0 = 7, DQM1 = 14
6625 09:28:07.613882 DQ Delay:
6626 09:28:07.616714 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6627 09:28:07.621272 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6628 09:28:07.623523 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6629 09:28:07.626850 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6630 09:28:07.626951
6631 09:28:07.627040
6632 09:28:07.633691 [DQSOSCAuto] RK1, (LSB)MR18= 0xba46, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6633 09:28:07.637053 CH0 RK1: MR19=C0C, MR18=BA46
6634 09:28:07.643351 CH0_RK1: MR19=0xC0C, MR18=0xBA46, DQSOSC=386, MR23=63, INC=396, DEC=264
6635 09:28:07.646774 [RxdqsGatingPostProcess] freq 400
6636 09:28:07.653062 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6637 09:28:07.656433 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 09:28:07.659896 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 09:28:07.663123 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 09:28:07.666547 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 09:28:07.666623 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 09:28:07.669576 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 09:28:07.672943 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 09:28:07.676009 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 09:28:07.679688 Pre-setting of DQS Precalculation
6646 09:28:07.686006 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6647 09:28:07.686100 ==
6648 09:28:07.689589 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 09:28:07.692692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 09:28:07.692778 ==
6651 09:28:07.699390 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 09:28:07.705767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 09:28:07.709426 [CA 0] Center 36 (8~64) winsize 57
6654 09:28:07.713046 [CA 1] Center 36 (8~64) winsize 57
6655 09:28:07.713135 [CA 2] Center 36 (8~64) winsize 57
6656 09:28:07.716456 [CA 3] Center 36 (8~64) winsize 57
6657 09:28:07.719142 [CA 4] Center 36 (8~64) winsize 57
6658 09:28:07.722671 [CA 5] Center 36 (8~64) winsize 57
6659 09:28:07.722756
6660 09:28:07.725876 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 09:28:07.725961
6662 09:28:07.732485 [CATrainingPosCal] consider 1 rank data
6663 09:28:07.732574 u2DelayCellTimex100 = 270/100 ps
6664 09:28:07.738855 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 09:28:07.742674 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 09:28:07.745503 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 09:28:07.748957 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 09:28:07.752248 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 09:28:07.755574 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 09:28:07.755660
6671 09:28:07.758998 CA PerBit enable=1, Macro0, CA PI delay=36
6672 09:28:07.759071
6673 09:28:07.761914 [CBTSetCACLKResult] CA Dly = 36
6674 09:28:07.765405 CS Dly: 1 (0~32)
6675 09:28:07.765476 ==
6676 09:28:07.768354 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 09:28:07.771635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 09:28:07.771767 ==
6679 09:28:07.778285 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 09:28:07.784790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6681 09:28:07.788223 [CA 0] Center 36 (8~64) winsize 57
6682 09:28:07.788304 [CA 1] Center 36 (8~64) winsize 57
6683 09:28:07.791312 [CA 2] Center 36 (8~64) winsize 57
6684 09:28:07.794605 [CA 3] Center 36 (8~64) winsize 57
6685 09:28:07.797897 [CA 4] Center 36 (8~64) winsize 57
6686 09:28:07.801792 [CA 5] Center 36 (8~64) winsize 57
6687 09:28:07.801864
6688 09:28:07.804598 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6689 09:28:07.804672
6690 09:28:07.811680 [CATrainingPosCal] consider 2 rank data
6691 09:28:07.811794 u2DelayCellTimex100 = 270/100 ps
6692 09:28:07.814537 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 09:28:07.821138 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 09:28:07.824534 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 09:28:07.827582 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 09:28:07.830982 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 09:28:07.834919 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 09:28:07.835000
6699 09:28:07.837588 CA PerBit enable=1, Macro0, CA PI delay=36
6700 09:28:07.837662
6701 09:28:07.841034 [CBTSetCACLKResult] CA Dly = 36
6702 09:28:07.844597 CS Dly: 1 (0~32)
6703 09:28:07.844667
6704 09:28:07.847718 ----->DramcWriteLeveling(PI) begin...
6705 09:28:07.847830 ==
6706 09:28:07.850596 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 09:28:07.854384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 09:28:07.854473 ==
6709 09:28:07.857662 Write leveling (Byte 0): 40 => 8
6710 09:28:07.860772 Write leveling (Byte 1): 40 => 8
6711 09:28:07.864065 DramcWriteLeveling(PI) end<-----
6712 09:28:07.864138
6713 09:28:07.864198 ==
6714 09:28:07.867417 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 09:28:07.870492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 09:28:07.870567 ==
6717 09:28:07.873707 [Gating] SW mode calibration
6718 09:28:07.880357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6719 09:28:07.887159 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6720 09:28:07.889979 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 09:28:07.893828 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 09:28:07.900074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 09:28:07.903185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 09:28:07.906783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 09:28:07.913650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 09:28:07.916799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 09:28:07.919802 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 09:28:07.926684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 09:28:07.929646 Total UI for P1: 0, mck2ui 16
6730 09:28:07.932920 best dqsien dly found for B0: ( 0, 14, 24)
6731 09:28:07.936359 Total UI for P1: 0, mck2ui 16
6732 09:28:07.939859 best dqsien dly found for B1: ( 0, 14, 24)
6733 09:28:07.942813 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6734 09:28:07.946271 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6735 09:28:07.946355
6736 09:28:07.949518 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 09:28:07.952620 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 09:28:07.956116 [Gating] SW calibration Done
6739 09:28:07.956205 ==
6740 09:28:07.959332 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 09:28:07.962533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 09:28:07.966523 ==
6743 09:28:07.966606 RX Vref Scan: 0
6744 09:28:07.966667
6745 09:28:07.969453 RX Vref 0 -> 0, step: 1
6746 09:28:07.969522
6747 09:28:07.972782 RX Delay -410 -> 252, step: 16
6748 09:28:07.975890 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6749 09:28:07.979053 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6750 09:28:07.982894 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6751 09:28:07.989090 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6752 09:28:07.992613 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6753 09:28:07.995907 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6754 09:28:07.999745 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6755 09:28:08.006177 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6756 09:28:08.008931 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6757 09:28:08.012495 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6758 09:28:08.015650 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6759 09:28:08.022241 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6760 09:28:08.025443 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6761 09:28:08.029179 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6762 09:28:08.032585 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6763 09:28:08.039008 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6764 09:28:08.039158 ==
6765 09:28:08.042026 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 09:28:08.045767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 09:28:08.045857 ==
6768 09:28:08.045924 DQS Delay:
6769 09:28:08.048926 DQS0 = 43, DQS1 = 51
6770 09:28:08.049010 DQM Delay:
6771 09:28:08.052195 DQM0 = 12, DQM1 = 14
6772 09:28:08.052286 DQ Delay:
6773 09:28:08.055292 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6774 09:28:08.058478 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6775 09:28:08.061917 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6776 09:28:08.065616 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6777 09:28:08.065710
6778 09:28:08.065776
6779 09:28:08.065837 ==
6780 09:28:08.068482 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 09:28:08.072062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 09:28:08.072160 ==
6783 09:28:08.074897
6784 09:28:08.074981
6785 09:28:08.075045 TX Vref Scan disable
6786 09:28:08.078341 == TX Byte 0 ==
6787 09:28:08.081535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 09:28:08.084984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 09:28:08.088517 == TX Byte 1 ==
6790 09:28:08.091277 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 09:28:08.094794 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 09:28:08.094882 ==
6793 09:28:08.097955 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 09:28:08.104519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 09:28:08.104617 ==
6796 09:28:08.104685
6797 09:28:08.104745
6798 09:28:08.104801 TX Vref Scan disable
6799 09:28:08.107886 == TX Byte 0 ==
6800 09:28:08.111551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 09:28:08.114663 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 09:28:08.118170 == TX Byte 1 ==
6803 09:28:08.121489 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 09:28:08.124935 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 09:28:08.125029
6806 09:28:08.128083 [DATLAT]
6807 09:28:08.128167 Freq=400, CH1 RK0
6808 09:28:08.128232
6809 09:28:08.131412 DATLAT Default: 0xf
6810 09:28:08.131495 0, 0xFFFF, sum = 0
6811 09:28:08.134378 1, 0xFFFF, sum = 0
6812 09:28:08.134461 2, 0xFFFF, sum = 0
6813 09:28:08.137709 3, 0xFFFF, sum = 0
6814 09:28:08.137795 4, 0xFFFF, sum = 0
6815 09:28:08.141069 5, 0xFFFF, sum = 0
6816 09:28:08.141155 6, 0xFFFF, sum = 0
6817 09:28:08.144129 7, 0xFFFF, sum = 0
6818 09:28:08.144231 8, 0xFFFF, sum = 0
6819 09:28:08.147640 9, 0xFFFF, sum = 0
6820 09:28:08.150546 10, 0xFFFF, sum = 0
6821 09:28:08.150643 11, 0xFFFF, sum = 0
6822 09:28:08.153804 12, 0xFFFF, sum = 0
6823 09:28:08.153914 13, 0x0, sum = 1
6824 09:28:08.157372 14, 0x0, sum = 2
6825 09:28:08.157462 15, 0x0, sum = 3
6826 09:28:08.160717 16, 0x0, sum = 4
6827 09:28:08.160804 best_step = 14
6828 09:28:08.160870
6829 09:28:08.160931 ==
6830 09:28:08.163902 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 09:28:08.167396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 09:28:08.167526 ==
6833 09:28:08.170502 RX Vref Scan: 1
6834 09:28:08.170601
6835 09:28:08.173680 RX Vref 0 -> 0, step: 1
6836 09:28:08.173761
6837 09:28:08.173825 RX Delay -343 -> 252, step: 8
6838 09:28:08.176996
6839 09:28:08.177101 Set Vref, RX VrefLevel [Byte0]: 52
6840 09:28:08.180523 [Byte1]: 54
6841 09:28:08.185841
6842 09:28:08.185938 Final RX Vref Byte 0 = 52 to rank0
6843 09:28:08.189270 Final RX Vref Byte 1 = 54 to rank0
6844 09:28:08.193351 Final RX Vref Byte 0 = 52 to rank1
6845 09:28:08.196236 Final RX Vref Byte 1 = 54 to rank1==
6846 09:28:08.199117 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 09:28:08.205833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 09:28:08.205914 ==
6849 09:28:08.205980 DQS Delay:
6850 09:28:08.209406 DQS0 = 44, DQS1 = 56
6851 09:28:08.209475 DQM Delay:
6852 09:28:08.209538 DQM0 = 8, DQM1 = 11
6853 09:28:08.212250 DQ Delay:
6854 09:28:08.215471 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6855 09:28:08.215566 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6856 09:28:08.219020 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6857 09:28:08.222475 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6858 09:28:08.222552
6859 09:28:08.225462
6860 09:28:08.232107 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6861 09:28:08.235191 CH1 RK0: MR19=C0C, MR18=9D73
6862 09:28:08.241906 CH1_RK0: MR19=0xC0C, MR18=0x9D73, DQSOSC=390, MR23=63, INC=388, DEC=258
6863 09:28:08.241981 ==
6864 09:28:08.245669 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 09:28:08.248748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 09:28:08.248829 ==
6867 09:28:08.251592 [Gating] SW mode calibration
6868 09:28:08.258300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6869 09:28:08.265019 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6870 09:28:08.268273 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 09:28:08.271460 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 09:28:08.278067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 09:28:08.281904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 09:28:08.284855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 09:28:08.291402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 09:28:08.294561 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 09:28:08.297822 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 09:28:08.304642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 09:28:08.304751 Total UI for P1: 0, mck2ui 16
6880 09:28:08.311057 best dqsien dly found for B0: ( 0, 14, 24)
6881 09:28:08.311147 Total UI for P1: 0, mck2ui 16
6882 09:28:08.317917 best dqsien dly found for B1: ( 0, 14, 24)
6883 09:28:08.321071 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6884 09:28:08.324486 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6885 09:28:08.324566
6886 09:28:08.327681 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 09:28:08.331198 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 09:28:08.334841 [Gating] SW calibration Done
6889 09:28:08.334920 ==
6890 09:28:08.337779 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 09:28:08.341035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 09:28:08.341109 ==
6893 09:28:08.344348 RX Vref Scan: 0
6894 09:28:08.344417
6895 09:28:08.344476 RX Vref 0 -> 0, step: 1
6896 09:28:08.344533
6897 09:28:08.348111 RX Delay -410 -> 252, step: 16
6898 09:28:08.354253 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6899 09:28:08.357682 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6900 09:28:08.361480 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6901 09:28:08.364125 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6902 09:28:08.371125 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6903 09:28:08.374095 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6904 09:28:08.377446 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6905 09:28:08.380584 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6906 09:28:08.387713 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6907 09:28:08.390643 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6908 09:28:08.394013 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6909 09:28:08.397454 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6910 09:28:08.403659 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6911 09:28:08.406904 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6912 09:28:08.410179 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6913 09:28:08.417023 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6914 09:28:08.417127 ==
6915 09:28:08.420829 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 09:28:08.423909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 09:28:08.423992 ==
6918 09:28:08.424061 DQS Delay:
6919 09:28:08.426545 DQS0 = 43, DQS1 = 59
6920 09:28:08.426620 DQM Delay:
6921 09:28:08.429881 DQM0 = 12, DQM1 = 22
6922 09:28:08.429952 DQ Delay:
6923 09:28:08.433623 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6924 09:28:08.436525 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6925 09:28:08.440230 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6926 09:28:08.443085 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6927 09:28:08.443152
6928 09:28:08.443211
6929 09:28:08.443272 ==
6930 09:28:08.446434 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 09:28:08.449817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 09:28:08.449885 ==
6933 09:28:08.449945
6934 09:28:08.452977
6935 09:28:08.453082 TX Vref Scan disable
6936 09:28:08.456259 == TX Byte 0 ==
6937 09:28:08.460030 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6938 09:28:08.462778 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6939 09:28:08.466336 == TX Byte 1 ==
6940 09:28:08.469302 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6941 09:28:08.473195 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6942 09:28:08.473282 ==
6943 09:28:08.476308 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 09:28:08.479333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 09:28:08.482659 ==
6946 09:28:08.482742
6947 09:28:08.482807
6948 09:28:08.482867 TX Vref Scan disable
6949 09:28:08.486048 == TX Byte 0 ==
6950 09:28:08.489491 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6951 09:28:08.492634 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6952 09:28:08.495695 == TX Byte 1 ==
6953 09:28:08.499191 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6954 09:28:08.502363 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6955 09:28:08.502447
6956 09:28:08.502556 [DATLAT]
6957 09:28:08.506175 Freq=400, CH1 RK1
6958 09:28:08.506258
6959 09:28:08.509185 DATLAT Default: 0xe
6960 09:28:08.509267 0, 0xFFFF, sum = 0
6961 09:28:08.512590 1, 0xFFFF, sum = 0
6962 09:28:08.512674 2, 0xFFFF, sum = 0
6963 09:28:08.515645 3, 0xFFFF, sum = 0
6964 09:28:08.515734 4, 0xFFFF, sum = 0
6965 09:28:08.518977 5, 0xFFFF, sum = 0
6966 09:28:08.519061 6, 0xFFFF, sum = 0
6967 09:28:08.522131 7, 0xFFFF, sum = 0
6968 09:28:08.522214 8, 0xFFFF, sum = 0
6969 09:28:08.526516 9, 0xFFFF, sum = 0
6970 09:28:08.526599 10, 0xFFFF, sum = 0
6971 09:28:08.528877 11, 0xFFFF, sum = 0
6972 09:28:08.528960 12, 0xFFFF, sum = 0
6973 09:28:08.532150 13, 0x0, sum = 1
6974 09:28:08.532232 14, 0x0, sum = 2
6975 09:28:08.536054 15, 0x0, sum = 3
6976 09:28:08.536136 16, 0x0, sum = 4
6977 09:28:08.538943 best_step = 14
6978 09:28:08.539023
6979 09:28:08.539087 ==
6980 09:28:08.542962 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 09:28:08.545393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 09:28:08.545475 ==
6983 09:28:08.548671 RX Vref Scan: 0
6984 09:28:08.548753
6985 09:28:08.548818 RX Vref 0 -> 0, step: 1
6986 09:28:08.548877
6987 09:28:08.551963 RX Delay -359 -> 252, step: 8
6988 09:28:08.560093 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6989 09:28:08.563557 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6990 09:28:08.566968 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6991 09:28:08.573325 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6992 09:28:08.576716 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6993 09:28:08.580477 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6994 09:28:08.583281 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6995 09:28:08.590144 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6996 09:28:08.593358 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6997 09:28:08.596660 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6998 09:28:08.600051 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6999 09:28:08.606577 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7000 09:28:08.609908 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7001 09:28:08.613147 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7002 09:28:08.616424 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7003 09:28:08.622841 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7004 09:28:08.622936 ==
7005 09:28:08.626086 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 09:28:08.629934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 09:28:08.630030 ==
7008 09:28:08.630098 DQS Delay:
7009 09:28:08.633041 DQS0 = 44, DQS1 = 56
7010 09:28:08.633124 DQM Delay:
7011 09:28:08.636295 DQM0 = 8, DQM1 = 11
7012 09:28:08.636378 DQ Delay:
7013 09:28:08.639935 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7014 09:28:08.643358 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7015 09:28:08.645944 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7016 09:28:08.649558 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7017 09:28:08.649650
7018 09:28:08.649718
7019 09:28:08.656003 [DQSOSCAuto] RK1, (LSB)MR18= 0x7161, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7020 09:28:08.659425 CH1 RK1: MR19=C0C, MR18=7161
7021 09:28:08.665988 CH1_RK1: MR19=0xC0C, MR18=0x7161, DQSOSC=395, MR23=63, INC=378, DEC=252
7022 09:28:08.669045 [RxdqsGatingPostProcess] freq 400
7023 09:28:08.675767 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7024 09:28:08.678812 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 09:28:08.682876 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 09:28:08.686057 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 09:28:08.689292 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 09:28:08.689385 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 09:28:08.692526 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 09:28:08.695774 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 09:28:08.698921 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 09:28:08.702730 Pre-setting of DQS Precalculation
7033 09:28:08.709161 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7034 09:28:08.715338 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7035 09:28:08.722469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7036 09:28:08.722601
7037 09:28:08.722673
7038 09:28:08.725255 [Calibration Summary] 800 Mbps
7039 09:28:08.725341 CH 0, Rank 0
7040 09:28:08.728681 SW Impedance : PASS
7041 09:28:08.732331 DUTY Scan : NO K
7042 09:28:08.732420 ZQ Calibration : PASS
7043 09:28:08.735401 Jitter Meter : NO K
7044 09:28:08.738652 CBT Training : PASS
7045 09:28:08.738739 Write leveling : PASS
7046 09:28:08.742052 RX DQS gating : PASS
7047 09:28:08.745193 RX DQ/DQS(RDDQC) : PASS
7048 09:28:08.745281 TX DQ/DQS : PASS
7049 09:28:08.748737 RX DATLAT : PASS
7050 09:28:08.751971 RX DQ/DQS(Engine): PASS
7051 09:28:08.752065 TX OE : NO K
7052 09:28:08.754843 All Pass.
7053 09:28:08.754931
7054 09:28:08.754997 CH 0, Rank 1
7055 09:28:08.758598 SW Impedance : PASS
7056 09:28:08.758687 DUTY Scan : NO K
7057 09:28:08.762009 ZQ Calibration : PASS
7058 09:28:08.764823 Jitter Meter : NO K
7059 09:28:08.764909 CBT Training : PASS
7060 09:28:08.769150 Write leveling : NO K
7061 09:28:08.772028 RX DQS gating : PASS
7062 09:28:08.772127 RX DQ/DQS(RDDQC) : PASS
7063 09:28:08.775012 TX DQ/DQS : PASS
7064 09:28:08.775106 RX DATLAT : PASS
7065 09:28:08.778077 RX DQ/DQS(Engine): PASS
7066 09:28:08.781387 TX OE : NO K
7067 09:28:08.781473 All Pass.
7068 09:28:08.781541
7069 09:28:08.781602 CH 1, Rank 0
7070 09:28:08.784536 SW Impedance : PASS
7071 09:28:08.788458 DUTY Scan : NO K
7072 09:28:08.788549 ZQ Calibration : PASS
7073 09:28:08.791260 Jitter Meter : NO K
7074 09:28:08.794596 CBT Training : PASS
7075 09:28:08.794701 Write leveling : PASS
7076 09:28:08.798112 RX DQS gating : PASS
7077 09:28:08.801409 RX DQ/DQS(RDDQC) : PASS
7078 09:28:08.801496 TX DQ/DQS : PASS
7079 09:28:08.804421 RX DATLAT : PASS
7080 09:28:08.808007 RX DQ/DQS(Engine): PASS
7081 09:28:08.808088 TX OE : NO K
7082 09:28:08.811058 All Pass.
7083 09:28:08.811155
7084 09:28:08.811252 CH 1, Rank 1
7085 09:28:08.814683 SW Impedance : PASS
7086 09:28:08.814761 DUTY Scan : NO K
7087 09:28:08.818190 ZQ Calibration : PASS
7088 09:28:08.822017 Jitter Meter : NO K
7089 09:28:08.822099 CBT Training : PASS
7090 09:28:08.824567 Write leveling : NO K
7091 09:28:08.827996 RX DQS gating : PASS
7092 09:28:08.828081 RX DQ/DQS(RDDQC) : PASS
7093 09:28:08.831477 TX DQ/DQS : PASS
7094 09:28:08.831581 RX DATLAT : PASS
7095 09:28:08.834159 RX DQ/DQS(Engine): PASS
7096 09:28:08.837668 TX OE : NO K
7097 09:28:08.837761 All Pass.
7098 09:28:08.837829
7099 09:28:08.841023 DramC Write-DBI off
7100 09:28:08.841107 PER_BANK_REFRESH: Hybrid Mode
7101 09:28:08.844550 TX_TRACKING: ON
7102 09:28:08.854220 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7103 09:28:08.857766 [FAST_K] Save calibration result to emmc
7104 09:28:08.861187 dramc_set_vcore_voltage set vcore to 725000
7105 09:28:08.864412 Read voltage for 1600, 0
7106 09:28:08.864505 Vio18 = 0
7107 09:28:08.864572 Vcore = 725000
7108 09:28:08.867627 Vdram = 0
7109 09:28:08.867711 Vddq = 0
7110 09:28:08.867812 Vmddr = 0
7111 09:28:08.874141 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7112 09:28:08.877330 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7113 09:28:08.880779 MEM_TYPE=3, freq_sel=13
7114 09:28:08.884000 sv_algorithm_assistance_LP4_3733
7115 09:28:08.887296 ============ PULL DRAM RESETB DOWN ============
7116 09:28:08.890607 ========== PULL DRAM RESETB DOWN end =========
7117 09:28:08.897509 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7118 09:28:08.900884 ===================================
7119 09:28:08.900979 LPDDR4 DRAM CONFIGURATION
7120 09:28:08.903961 ===================================
7121 09:28:08.907152 EX_ROW_EN[0] = 0x0
7122 09:28:08.910431 EX_ROW_EN[1] = 0x0
7123 09:28:08.910530 LP4Y_EN = 0x0
7124 09:28:08.913664 WORK_FSP = 0x1
7125 09:28:08.913738 WL = 0x5
7126 09:28:08.917234 RL = 0x5
7127 09:28:08.917340 BL = 0x2
7128 09:28:08.920403 RPST = 0x0
7129 09:28:08.920485 RD_PRE = 0x0
7130 09:28:08.923511 WR_PRE = 0x1
7131 09:28:08.923579 WR_PST = 0x1
7132 09:28:08.926867 DBI_WR = 0x0
7133 09:28:08.926945 DBI_RD = 0x0
7134 09:28:08.929999 OTF = 0x1
7135 09:28:08.933288 ===================================
7136 09:28:08.936773 ===================================
7137 09:28:08.936844 ANA top config
7138 09:28:08.940069 ===================================
7139 09:28:08.943320 DLL_ASYNC_EN = 0
7140 09:28:08.947413 ALL_SLAVE_EN = 0
7141 09:28:08.950120 NEW_RANK_MODE = 1
7142 09:28:08.950193 DLL_IDLE_MODE = 1
7143 09:28:08.953538 LP45_APHY_COMB_EN = 1
7144 09:28:08.956445 TX_ODT_DIS = 0
7145 09:28:08.960026 NEW_8X_MODE = 1
7146 09:28:08.963985 ===================================
7147 09:28:08.966637 ===================================
7148 09:28:08.969909 data_rate = 3200
7149 09:28:08.973272 CKR = 1
7150 09:28:08.973365 DQ_P2S_RATIO = 8
7151 09:28:08.976500 ===================================
7152 09:28:08.979934 CA_P2S_RATIO = 8
7153 09:28:08.983256 DQ_CA_OPEN = 0
7154 09:28:08.986186 DQ_SEMI_OPEN = 0
7155 09:28:08.989500 CA_SEMI_OPEN = 0
7156 09:28:08.993079 CA_FULL_RATE = 0
7157 09:28:08.993162 DQ_CKDIV4_EN = 0
7158 09:28:08.996340 CA_CKDIV4_EN = 0
7159 09:28:08.999403 CA_PREDIV_EN = 0
7160 09:28:09.003124 PH8_DLY = 12
7161 09:28:09.006352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7162 09:28:09.009458 DQ_AAMCK_DIV = 4
7163 09:28:09.009537 CA_AAMCK_DIV = 4
7164 09:28:09.012714 CA_ADMCK_DIV = 4
7165 09:28:09.016285 DQ_TRACK_CA_EN = 0
7166 09:28:09.019256 CA_PICK = 1600
7167 09:28:09.022601 CA_MCKIO = 1600
7168 09:28:09.026353 MCKIO_SEMI = 0
7169 09:28:09.029413 PLL_FREQ = 3068
7170 09:28:09.029491 DQ_UI_PI_RATIO = 32
7171 09:28:09.032603 CA_UI_PI_RATIO = 0
7172 09:28:09.036026 ===================================
7173 09:28:09.039278 ===================================
7174 09:28:09.042469 memory_type:LPDDR4
7175 09:28:09.046174 GP_NUM : 10
7176 09:28:09.046244 SRAM_EN : 1
7177 09:28:09.049422 MD32_EN : 0
7178 09:28:09.052563 ===================================
7179 09:28:09.055945 [ANA_INIT] >>>>>>>>>>>>>>
7180 09:28:09.056031 <<<<<< [CONFIGURE PHASE]: ANA_TX
7181 09:28:09.059242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7182 09:28:09.062478 ===================================
7183 09:28:09.065795 data_rate = 3200,PCW = 0X7600
7184 09:28:09.068837 ===================================
7185 09:28:09.072234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7186 09:28:09.078719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 09:28:09.085243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 09:28:09.089251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7189 09:28:09.092728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7190 09:28:09.095315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7191 09:28:09.099037 [ANA_INIT] flow start
7192 09:28:09.099152 [ANA_INIT] PLL >>>>>>>>
7193 09:28:09.102078 [ANA_INIT] PLL <<<<<<<<
7194 09:28:09.105189 [ANA_INIT] MIDPI >>>>>>>>
7195 09:28:09.108553 [ANA_INIT] MIDPI <<<<<<<<
7196 09:28:09.108629 [ANA_INIT] DLL >>>>>>>>
7197 09:28:09.111996 [ANA_INIT] DLL <<<<<<<<
7198 09:28:09.114960 [ANA_INIT] flow end
7199 09:28:09.118373 ============ LP4 DIFF to SE enter ============
7200 09:28:09.121738 ============ LP4 DIFF to SE exit ============
7201 09:28:09.124837 [ANA_INIT] <<<<<<<<<<<<<
7202 09:28:09.128255 [Flow] Enable top DCM control >>>>>
7203 09:28:09.131418 [Flow] Enable top DCM control <<<<<
7204 09:28:09.134747 Enable DLL master slave shuffle
7205 09:28:09.138130 ==============================================================
7206 09:28:09.141799 Gating Mode config
7207 09:28:09.148560 ==============================================================
7208 09:28:09.148676 Config description:
7209 09:28:09.157704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7210 09:28:09.165017 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7211 09:28:09.170820 SELPH_MODE 0: By rank 1: By Phase
7212 09:28:09.174428 ==============================================================
7213 09:28:09.177694 GAT_TRACK_EN = 1
7214 09:28:09.181342 RX_GATING_MODE = 2
7215 09:28:09.184267 RX_GATING_TRACK_MODE = 2
7216 09:28:09.187493 SELPH_MODE = 1
7217 09:28:09.190854 PICG_EARLY_EN = 1
7218 09:28:09.194551 VALID_LAT_VALUE = 1
7219 09:28:09.197657 ==============================================================
7220 09:28:09.200872 Enter into Gating configuration >>>>
7221 09:28:09.204033 Exit from Gating configuration <<<<
7222 09:28:09.207091 Enter into DVFS_PRE_config >>>>>
7223 09:28:09.220466 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7224 09:28:09.223706 Exit from DVFS_PRE_config <<<<<
7225 09:28:09.227294 Enter into PICG configuration >>>>
7226 09:28:09.230668 Exit from PICG configuration <<<<
7227 09:28:09.230784 [RX_INPUT] configuration >>>>>
7228 09:28:09.233909 [RX_INPUT] configuration <<<<<
7229 09:28:09.240524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7230 09:28:09.243421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7231 09:28:09.250297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 09:28:09.256527 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 09:28:09.263655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 09:28:09.270091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 09:28:09.273230 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7236 09:28:09.276459 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7237 09:28:09.283347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7238 09:28:09.286754 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7239 09:28:09.289473 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7240 09:28:09.296146 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 09:28:09.299445 ===================================
7242 09:28:09.299554 LPDDR4 DRAM CONFIGURATION
7243 09:28:09.302942 ===================================
7244 09:28:09.306405 EX_ROW_EN[0] = 0x0
7245 09:28:09.306492 EX_ROW_EN[1] = 0x0
7246 09:28:09.309663 LP4Y_EN = 0x0
7247 09:28:09.309743 WORK_FSP = 0x1
7248 09:28:09.312829 WL = 0x5
7249 09:28:09.316059 RL = 0x5
7250 09:28:09.316147 BL = 0x2
7251 09:28:09.319445 RPST = 0x0
7252 09:28:09.319531 RD_PRE = 0x0
7253 09:28:09.322665 WR_PRE = 0x1
7254 09:28:09.322753 WR_PST = 0x1
7255 09:28:09.326022 DBI_WR = 0x0
7256 09:28:09.326108 DBI_RD = 0x0
7257 09:28:09.329233 OTF = 0x1
7258 09:28:09.332390 ===================================
7259 09:28:09.335892 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7260 09:28:09.339236 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7261 09:28:09.346038 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 09:28:09.349359 ===================================
7263 09:28:09.349455 LPDDR4 DRAM CONFIGURATION
7264 09:28:09.352359 ===================================
7265 09:28:09.355535 EX_ROW_EN[0] = 0x10
7266 09:28:09.355633 EX_ROW_EN[1] = 0x0
7267 09:28:09.358880 LP4Y_EN = 0x0
7268 09:28:09.362162 WORK_FSP = 0x1
7269 09:28:09.362262 WL = 0x5
7270 09:28:09.365659 RL = 0x5
7271 09:28:09.365744 BL = 0x2
7272 09:28:09.369127 RPST = 0x0
7273 09:28:09.369209 RD_PRE = 0x0
7274 09:28:09.372257 WR_PRE = 0x1
7275 09:28:09.372340 WR_PST = 0x1
7276 09:28:09.375306 DBI_WR = 0x0
7277 09:28:09.375389 DBI_RD = 0x0
7278 09:28:09.379069 OTF = 0x1
7279 09:28:09.381923 ===================================
7280 09:28:09.388431 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7281 09:28:09.388517 ==
7282 09:28:09.391744 Dram Type= 6, Freq= 0, CH_0, rank 0
7283 09:28:09.395269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 09:28:09.395354 ==
7285 09:28:09.398370 [Duty_Offset_Calibration]
7286 09:28:09.398511 B0:1 B1:-1 CA:0
7287 09:28:09.398634
7288 09:28:09.401865 [DutyScan_Calibration_Flow] k_type=0
7289 09:28:09.412235
7290 09:28:09.412461 ==CLK 0==
7291 09:28:09.416056 Final CLK duty delay cell = 0
7292 09:28:09.419134 [0] MAX Duty = 5125%(X100), DQS PI = 20
7293 09:28:09.422230 [0] MIN Duty = 4907%(X100), DQS PI = 6
7294 09:28:09.422325 [0] AVG Duty = 5016%(X100)
7295 09:28:09.425829
7296 09:28:09.428888 CH0 CLK Duty spec in!! Max-Min= 218%
7297 09:28:09.432437 [DutyScan_Calibration_Flow] ====Done====
7298 09:28:09.432542
7299 09:28:09.435332 [DutyScan_Calibration_Flow] k_type=1
7300 09:28:09.451435
7301 09:28:09.451594 ==DQS 0 ==
7302 09:28:09.454566 Final DQS duty delay cell = -4
7303 09:28:09.458301 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7304 09:28:09.461449 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7305 09:28:09.464595 [-4] AVG Duty = 4922%(X100)
7306 09:28:09.464687
7307 09:28:09.464752 ==DQS 1 ==
7308 09:28:09.467683 Final DQS duty delay cell = 0
7309 09:28:09.470994 [0] MAX Duty = 5187%(X100), DQS PI = 4
7310 09:28:09.474262 [0] MIN Duty = 5031%(X100), DQS PI = 18
7311 09:28:09.478007 [0] AVG Duty = 5109%(X100)
7312 09:28:09.478103
7313 09:28:09.481035 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7314 09:28:09.481119
7315 09:28:09.484174 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7316 09:28:09.488005 [DutyScan_Calibration_Flow] ====Done====
7317 09:28:09.488092
7318 09:28:09.490909 [DutyScan_Calibration_Flow] k_type=3
7319 09:28:09.509449
7320 09:28:09.509596 ==DQM 0 ==
7321 09:28:09.512119 Final DQM duty delay cell = 0
7322 09:28:09.515933 [0] MAX Duty = 5125%(X100), DQS PI = 22
7323 09:28:09.518973 [0] MIN Duty = 4876%(X100), DQS PI = 10
7324 09:28:09.522471 [0] AVG Duty = 5000%(X100)
7325 09:28:09.522555
7326 09:28:09.522619 ==DQM 1 ==
7327 09:28:09.525325 Final DQM duty delay cell = 0
7328 09:28:09.528584 [0] MAX Duty = 5000%(X100), DQS PI = 4
7329 09:28:09.532133 [0] MIN Duty = 4813%(X100), DQS PI = 18
7330 09:28:09.535294 [0] AVG Duty = 4906%(X100)
7331 09:28:09.535375
7332 09:28:09.538649 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7333 09:28:09.538731
7334 09:28:09.542025 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7335 09:28:09.545162 [DutyScan_Calibration_Flow] ====Done====
7336 09:28:09.545243
7337 09:28:09.548310 [DutyScan_Calibration_Flow] k_type=2
7338 09:28:09.565235
7339 09:28:09.565383 ==DQ 0 ==
7340 09:28:09.568421 Final DQ duty delay cell = -4
7341 09:28:09.571674 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7342 09:28:09.575090 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7343 09:28:09.578594 [-4] AVG Duty = 4953%(X100)
7344 09:28:09.578681
7345 09:28:09.578748 ==DQ 1 ==
7346 09:28:09.581823 Final DQ duty delay cell = 0
7347 09:28:09.584943 [0] MAX Duty = 5125%(X100), DQS PI = 4
7348 09:28:09.588090 [0] MIN Duty = 5000%(X100), DQS PI = 36
7349 09:28:09.592087 [0] AVG Duty = 5062%(X100)
7350 09:28:09.592170
7351 09:28:09.595290 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7352 09:28:09.595372
7353 09:28:09.598197 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7354 09:28:09.601990 [DutyScan_Calibration_Flow] ====Done====
7355 09:28:09.602073 ==
7356 09:28:09.604591 Dram Type= 6, Freq= 0, CH_1, rank 0
7357 09:28:09.608228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7358 09:28:09.608311 ==
7359 09:28:09.611403 [Duty_Offset_Calibration]
7360 09:28:09.611485 B0:-1 B1:1 CA:2
7361 09:28:09.614641
7362 09:28:09.617786 [DutyScan_Calibration_Flow] k_type=0
7363 09:28:09.625995
7364 09:28:09.626088 ==CLK 0==
7365 09:28:09.629176 Final CLK duty delay cell = 0
7366 09:28:09.632531 [0] MAX Duty = 5187%(X100), DQS PI = 24
7367 09:28:09.635667 [0] MIN Duty = 4969%(X100), DQS PI = 0
7368 09:28:09.635785 [0] AVG Duty = 5078%(X100)
7369 09:28:09.638925
7370 09:28:09.642296 CH1 CLK Duty spec in!! Max-Min= 218%
7371 09:28:09.645424 [DutyScan_Calibration_Flow] ====Done====
7372 09:28:09.645506
7373 09:28:09.649132 [DutyScan_Calibration_Flow] k_type=1
7374 09:28:09.665417
7375 09:28:09.665534 ==DQS 0 ==
7376 09:28:09.668911 Final DQS duty delay cell = 0
7377 09:28:09.672258 [0] MAX Duty = 5156%(X100), DQS PI = 20
7378 09:28:09.675230 [0] MIN Duty = 4907%(X100), DQS PI = 8
7379 09:28:09.678682 [0] AVG Duty = 5031%(X100)
7380 09:28:09.678766
7381 09:28:09.678831 ==DQS 1 ==
7382 09:28:09.681716 Final DQS duty delay cell = 0
7383 09:28:09.685150 [0] MAX Duty = 5093%(X100), DQS PI = 24
7384 09:28:09.688289 [0] MIN Duty = 4969%(X100), DQS PI = 54
7385 09:28:09.691538 [0] AVG Duty = 5031%(X100)
7386 09:28:09.691647
7387 09:28:09.695371 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7388 09:28:09.695453
7389 09:28:09.698393 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7390 09:28:09.701478 [DutyScan_Calibration_Flow] ====Done====
7391 09:28:09.701560
7392 09:28:09.704856 [DutyScan_Calibration_Flow] k_type=3
7393 09:28:09.722210
7394 09:28:09.722310 ==DQM 0 ==
7395 09:28:09.725938 Final DQM duty delay cell = 0
7396 09:28:09.728907 [0] MAX Duty = 5218%(X100), DQS PI = 34
7397 09:28:09.732429 [0] MIN Duty = 5031%(X100), DQS PI = 8
7398 09:28:09.732512 [0] AVG Duty = 5124%(X100)
7399 09:28:09.735821
7400 09:28:09.735903 ==DQM 1 ==
7401 09:28:09.738605 Final DQM duty delay cell = 0
7402 09:28:09.741977 [0] MAX Duty = 5156%(X100), DQS PI = 6
7403 09:28:09.745657 [0] MIN Duty = 4969%(X100), DQS PI = 32
7404 09:28:09.748438 [0] AVG Duty = 5062%(X100)
7405 09:28:09.748520
7406 09:28:09.751619 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7407 09:28:09.751760
7408 09:28:09.755479 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7409 09:28:09.758545 [DutyScan_Calibration_Flow] ====Done====
7410 09:28:09.758630
7411 09:28:09.761894 [DutyScan_Calibration_Flow] k_type=2
7412 09:28:09.779049
7413 09:28:09.779171 ==DQ 0 ==
7414 09:28:09.782374 Final DQ duty delay cell = 0
7415 09:28:09.785679 [0] MAX Duty = 5156%(X100), DQS PI = 30
7416 09:28:09.789312 [0] MIN Duty = 4906%(X100), DQS PI = 8
7417 09:28:09.789395 [0] AVG Duty = 5031%(X100)
7418 09:28:09.792507
7419 09:28:09.792590 ==DQ 1 ==
7420 09:28:09.795560 Final DQ duty delay cell = 0
7421 09:28:09.799154 [0] MAX Duty = 5156%(X100), DQS PI = 8
7422 09:28:09.802134 [0] MIN Duty = 4969%(X100), DQS PI = 56
7423 09:28:09.802219 [0] AVG Duty = 5062%(X100)
7424 09:28:09.802285
7425 09:28:09.808831 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7426 09:28:09.808915
7427 09:28:09.811985 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7428 09:28:09.815277 [DutyScan_Calibration_Flow] ====Done====
7429 09:28:09.818703 nWR fixed to 30
7430 09:28:09.818787 [ModeRegInit_LP4] CH0 RK0
7431 09:28:09.822021 [ModeRegInit_LP4] CH0 RK1
7432 09:28:09.825197 [ModeRegInit_LP4] CH1 RK0
7433 09:28:09.828951 [ModeRegInit_LP4] CH1 RK1
7434 09:28:09.829035 match AC timing 5
7435 09:28:09.835138 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7436 09:28:09.838199 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7437 09:28:09.841958 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7438 09:28:09.848653 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7439 09:28:09.851454 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7440 09:28:09.851541 [MiockJmeterHQA]
7441 09:28:09.851606
7442 09:28:09.854905 [DramcMiockJmeter] u1RxGatingPI = 0
7443 09:28:09.858549 0 : 4253, 4026
7444 09:28:09.858636 4 : 4253, 4026
7445 09:28:09.861742 8 : 4366, 4139
7446 09:28:09.861862 12 : 4363, 4138
7447 09:28:09.864640 16 : 4366, 4140
7448 09:28:09.864724 20 : 4253, 4026
7449 09:28:09.864790 24 : 4252, 4027
7450 09:28:09.868037 28 : 4253, 4026
7451 09:28:09.868151 32 : 4252, 4027
7452 09:28:09.871671 36 : 4252, 4027
7453 09:28:09.871796 40 : 4363, 4137
7454 09:28:09.874887 44 : 4253, 4027
7455 09:28:09.875016 48 : 4252, 4026
7456 09:28:09.877954 52 : 4252, 4027
7457 09:28:09.878040 56 : 4252, 4027
7458 09:28:09.878108 60 : 4252, 4026
7459 09:28:09.881528 64 : 4363, 4138
7460 09:28:09.881615 68 : 4363, 4137
7461 09:28:09.885132 72 : 4250, 4027
7462 09:28:09.885221 76 : 4250, 4027
7463 09:28:09.887674 80 : 4250, 4026
7464 09:28:09.887790 84 : 4250, 4027
7465 09:28:09.891460 88 : 4255, 4032
7466 09:28:09.891547 92 : 4361, 874
7467 09:28:09.891615 96 : 4250, 0
7468 09:28:09.894553 100 : 4250, 0
7469 09:28:09.894641 104 : 4360, 0
7470 09:28:09.894707 108 : 4360, 0
7471 09:28:09.897786 112 : 4250, 0
7472 09:28:09.897873 116 : 4250, 0
7473 09:28:09.901149 120 : 4250, 0
7474 09:28:09.901236 124 : 4252, 0
7475 09:28:09.901303 128 : 4250, 0
7476 09:28:09.904533 132 : 4250, 0
7477 09:28:09.904623 136 : 4249, 0
7478 09:28:09.907531 140 : 4361, 0
7479 09:28:09.907644 144 : 4250, 0
7480 09:28:09.907767 148 : 4360, 0
7481 09:28:09.910846 152 : 4250, 0
7482 09:28:09.910930 156 : 4250, 0
7483 09:28:09.914447 160 : 4250, 0
7484 09:28:09.914531 164 : 4250, 0
7485 09:28:09.914597 168 : 4250, 0
7486 09:28:09.917685 172 : 4250, 0
7487 09:28:09.917767 176 : 4249, 0
7488 09:28:09.920917 180 : 4250, 0
7489 09:28:09.921008 184 : 4250, 0
7490 09:28:09.921075 188 : 4249, 0
7491 09:28:09.924017 192 : 4361, 0
7492 09:28:09.924103 196 : 4361, 0
7493 09:28:09.924169 200 : 4361, 0
7494 09:28:09.927466 204 : 4250, 0
7495 09:28:09.927577 208 : 4360, 0
7496 09:28:09.930970 212 : 4250, 0
7497 09:28:09.931052 216 : 4250, 0
7498 09:28:09.931119 220 : 4250, 0
7499 09:28:09.934692 224 : 4250, 59
7500 09:28:09.934776 228 : 4250, 3017
7501 09:28:09.937535 232 : 4252, 4030
7502 09:28:09.937619 236 : 4249, 4027
7503 09:28:09.940515 240 : 4250, 4026
7504 09:28:09.940600 244 : 4360, 4138
7505 09:28:09.944168 248 : 4249, 4027
7506 09:28:09.944254 252 : 4250, 4026
7507 09:28:09.947631 256 : 4361, 4137
7508 09:28:09.947762 260 : 4250, 4027
7509 09:28:09.950881 264 : 4250, 4026
7510 09:28:09.950964 268 : 4360, 4137
7511 09:28:09.951030 272 : 4250, 4026
7512 09:28:09.954479 276 : 4250, 4027
7513 09:28:09.954567 280 : 4250, 4027
7514 09:28:09.957481 284 : 4249, 4027
7515 09:28:09.957569 288 : 4250, 4026
7516 09:28:09.960446 292 : 4250, 4027
7517 09:28:09.960532 296 : 4360, 4138
7518 09:28:09.964346 300 : 4249, 4027
7519 09:28:09.964434 304 : 4250, 4026
7520 09:28:09.967116 308 : 4361, 4137
7521 09:28:09.967201 312 : 4250, 4027
7522 09:28:09.970889 316 : 4250, 4027
7523 09:28:09.970976 320 : 4360, 4137
7524 09:28:09.973678 324 : 4250, 4026
7525 09:28:09.973765 328 : 4250, 4027
7526 09:28:09.973832 332 : 4250, 4027
7527 09:28:09.977021 336 : 4250, 3978
7528 09:28:09.977109 340 : 4250, 2385
7529 09:28:09.980273 344 : 4250, 178
7530 09:28:09.980360
7531 09:28:09.983625 MIOCK jitter meter ch=0
7532 09:28:09.983765
7533 09:28:09.983849 1T = (344-92) = 252 dly cells
7534 09:28:09.990329 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7535 09:28:09.990437 ==
7536 09:28:09.993824 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 09:28:09.996996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 09:28:10.000339 ==
7539 09:28:10.003647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 09:28:10.006784 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 09:28:10.013674 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 09:28:10.019988 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 09:28:10.027528 [CA 0] Center 43 (12~74) winsize 63
7544 09:28:10.031117 [CA 1] Center 42 (12~73) winsize 62
7545 09:28:10.033855 [CA 2] Center 38 (9~68) winsize 60
7546 09:28:10.037647 [CA 3] Center 38 (8~68) winsize 61
7547 09:28:10.040418 [CA 4] Center 36 (7~66) winsize 60
7548 09:28:10.044540 [CA 5] Center 35 (6~65) winsize 60
7549 09:28:10.044633
7550 09:28:10.047442 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 09:28:10.047525
7552 09:28:10.050505 [CATrainingPosCal] consider 1 rank data
7553 09:28:10.053654 u2DelayCellTimex100 = 258/100 ps
7554 09:28:10.060563 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7555 09:28:10.063646 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7556 09:28:10.066981 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7557 09:28:10.070471 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7558 09:28:10.073395 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7559 09:28:10.077205 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7560 09:28:10.077311
7561 09:28:10.080189 CA PerBit enable=1, Macro0, CA PI delay=35
7562 09:28:10.080275
7563 09:28:10.083912 [CBTSetCACLKResult] CA Dly = 35
7564 09:28:10.087236 CS Dly: 12 (0~43)
7565 09:28:10.090124 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 09:28:10.093690 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 09:28:10.093781 ==
7568 09:28:10.096858 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 09:28:10.103201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 09:28:10.103314 ==
7571 09:28:10.106433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 09:28:10.113389 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 09:28:10.116263 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 09:28:10.122975 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 09:28:10.130974 [CA 0] Center 42 (12~73) winsize 62
7576 09:28:10.134597 [CA 1] Center 43 (13~73) winsize 61
7577 09:28:10.137809 [CA 2] Center 37 (8~67) winsize 60
7578 09:28:10.140898 [CA 3] Center 37 (7~67) winsize 61
7579 09:28:10.144522 [CA 4] Center 35 (6~65) winsize 60
7580 09:28:10.147827 [CA 5] Center 35 (5~65) winsize 61
7581 09:28:10.147920
7582 09:28:10.150765 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 09:28:10.150849
7584 09:28:10.154220 [CATrainingPosCal] consider 2 rank data
7585 09:28:10.157560 u2DelayCellTimex100 = 258/100 ps
7586 09:28:10.163874 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7587 09:28:10.167327 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7588 09:28:10.171000 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7589 09:28:10.174001 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7590 09:28:10.177468 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7591 09:28:10.180554 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7592 09:28:10.180647
7593 09:28:10.183901 CA PerBit enable=1, Macro0, CA PI delay=35
7594 09:28:10.183988
7595 09:28:10.186925 [CBTSetCACLKResult] CA Dly = 35
7596 09:28:10.190259 CS Dly: 12 (0~43)
7597 09:28:10.193953 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 09:28:10.197198 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 09:28:10.197289
7600 09:28:10.200406 ----->DramcWriteLeveling(PI) begin...
7601 09:28:10.200492 ==
7602 09:28:10.203477 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 09:28:10.210351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 09:28:10.210468 ==
7605 09:28:10.213446 Write leveling (Byte 0): 36 => 36
7606 09:28:10.216852 Write leveling (Byte 1): 28 => 28
7607 09:28:10.216941 DramcWriteLeveling(PI) end<-----
7608 09:28:10.220447
7609 09:28:10.220537 ==
7610 09:28:10.223380 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 09:28:10.227302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 09:28:10.227391 ==
7613 09:28:10.230161 [Gating] SW mode calibration
7614 09:28:10.236624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 09:28:10.240131 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 09:28:10.246950 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 09:28:10.249993 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 09:28:10.253266 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 09:28:10.259970 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7620 09:28:10.263138 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7621 09:28:10.266856 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7622 09:28:10.272992 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7623 09:28:10.276253 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 09:28:10.279551 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 09:28:10.286242 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 09:28:10.289764 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7627 09:28:10.292850 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7628 09:28:10.299605 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7629 09:28:10.302660 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7630 09:28:10.306337 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7631 09:28:10.312917 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 09:28:10.316137 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 09:28:10.318772 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 09:28:10.325479 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7635 09:28:10.329044 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7636 09:28:10.331998 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7637 09:28:10.339193 1 6 20 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
7638 09:28:10.342331 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7639 09:28:10.345565 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 09:28:10.352156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 09:28:10.355871 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 09:28:10.358652 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 09:28:10.365201 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 09:28:10.369085 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 09:28:10.372215 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 09:28:10.378443 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 09:28:10.382141 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 09:28:10.385252 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 09:28:10.391736 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 09:28:10.394895 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 09:28:10.398428 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 09:28:10.405049 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 09:28:10.408404 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 09:28:10.411911 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 09:28:10.418155 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 09:28:10.421386 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 09:28:10.424986 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 09:28:10.431210 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 09:28:10.434494 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 09:28:10.438123 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 09:28:10.444590 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 09:28:10.444775 Total UI for P1: 0, mck2ui 16
7663 09:28:10.451488 best dqsien dly found for B0: ( 1, 9, 14)
7664 09:28:10.454633 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 09:28:10.458494 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 09:28:10.461453 Total UI for P1: 0, mck2ui 16
7667 09:28:10.464517 best dqsien dly found for B1: ( 1, 9, 22)
7668 09:28:10.467892 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7669 09:28:10.471018 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7670 09:28:10.471100
7671 09:28:10.477786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7672 09:28:10.480796 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7673 09:28:10.484077 [Gating] SW calibration Done
7674 09:28:10.484187 ==
7675 09:28:10.487558 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 09:28:10.490854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 09:28:10.490936 ==
7678 09:28:10.491001 RX Vref Scan: 0
7679 09:28:10.491062
7680 09:28:10.494051 RX Vref 0 -> 0, step: 1
7681 09:28:10.494131
7682 09:28:10.497542 RX Delay 0 -> 252, step: 8
7683 09:28:10.500730 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7684 09:28:10.503835 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7685 09:28:10.510791 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7686 09:28:10.513731 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7687 09:28:10.517158 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7688 09:28:10.520477 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7689 09:28:10.524255 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7690 09:28:10.530309 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7691 09:28:10.533696 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7692 09:28:10.537354 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7693 09:28:10.540218 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7694 09:28:10.543576 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7695 09:28:10.550108 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7696 09:28:10.553494 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7697 09:28:10.556638 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7698 09:28:10.559859 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7699 09:28:10.559941 ==
7700 09:28:10.563677 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 09:28:10.570315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 09:28:10.570400 ==
7703 09:28:10.570465 DQS Delay:
7704 09:28:10.573262 DQS0 = 0, DQS1 = 0
7705 09:28:10.573343 DQM Delay:
7706 09:28:10.576932 DQM0 = 133, DQM1 = 125
7707 09:28:10.577015 DQ Delay:
7708 09:28:10.579701 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131
7709 09:28:10.582933 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7710 09:28:10.586377 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7711 09:28:10.589603 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7712 09:28:10.589686
7713 09:28:10.589751
7714 09:28:10.589811 ==
7715 09:28:10.592847 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 09:28:10.600893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 09:28:10.600980 ==
7718 09:28:10.601045
7719 09:28:10.601107
7720 09:28:10.601179 TX Vref Scan disable
7721 09:28:10.603535 == TX Byte 0 ==
7722 09:28:10.606686 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7723 09:28:10.613012 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7724 09:28:10.613095 == TX Byte 1 ==
7725 09:28:10.616277 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7726 09:28:10.622986 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7727 09:28:10.623070 ==
7728 09:28:10.626281 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 09:28:10.629590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 09:28:10.629673 ==
7731 09:28:10.642715
7732 09:28:10.646110 TX Vref early break, caculate TX vref
7733 09:28:10.649651 TX Vref=16, minBit 6, minWin=22, winSum=372
7734 09:28:10.652327 TX Vref=18, minBit 1, minWin=23, winSum=382
7735 09:28:10.656102 TX Vref=20, minBit 14, minWin=23, winSum=393
7736 09:28:10.659279 TX Vref=22, minBit 1, minWin=24, winSum=403
7737 09:28:10.662575 TX Vref=24, minBit 0, minWin=24, winSum=407
7738 09:28:10.669352 TX Vref=26, minBit 0, minWin=25, winSum=416
7739 09:28:10.672188 TX Vref=28, minBit 4, minWin=24, winSum=419
7740 09:28:10.675382 TX Vref=30, minBit 0, minWin=24, winSum=412
7741 09:28:10.678626 TX Vref=32, minBit 0, minWin=24, winSum=403
7742 09:28:10.682056 TX Vref=34, minBit 4, minWin=23, winSum=387
7743 09:28:10.688914 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
7744 09:28:10.689037
7745 09:28:10.692347 Final TX Range 0 Vref 26
7746 09:28:10.692437
7747 09:28:10.692501 ==
7748 09:28:10.695270 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 09:28:10.698771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 09:28:10.698862 ==
7751 09:28:10.698928
7752 09:28:10.698988
7753 09:28:10.702185 TX Vref Scan disable
7754 09:28:10.708753 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7755 09:28:10.708870 == TX Byte 0 ==
7756 09:28:10.711671 u2DelayCellOfst[0]=18 cells (5 PI)
7757 09:28:10.715237 u2DelayCellOfst[1]=18 cells (5 PI)
7758 09:28:10.718582 u2DelayCellOfst[2]=15 cells (4 PI)
7759 09:28:10.721603 u2DelayCellOfst[3]=15 cells (4 PI)
7760 09:28:10.724916 u2DelayCellOfst[4]=11 cells (3 PI)
7761 09:28:10.728415 u2DelayCellOfst[5]=0 cells (0 PI)
7762 09:28:10.731484 u2DelayCellOfst[6]=18 cells (5 PI)
7763 09:28:10.735210 u2DelayCellOfst[7]=18 cells (5 PI)
7764 09:28:10.738444 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7765 09:28:10.741493 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7766 09:28:10.744808 == TX Byte 1 ==
7767 09:28:10.748145 u2DelayCellOfst[8]=0 cells (0 PI)
7768 09:28:10.751396 u2DelayCellOfst[9]=0 cells (0 PI)
7769 09:28:10.754498 u2DelayCellOfst[10]=3 cells (1 PI)
7770 09:28:10.757986 u2DelayCellOfst[11]=0 cells (0 PI)
7771 09:28:10.761375 u2DelayCellOfst[12]=11 cells (3 PI)
7772 09:28:10.761464 u2DelayCellOfst[13]=11 cells (3 PI)
7773 09:28:10.764748 u2DelayCellOfst[14]=15 cells (4 PI)
7774 09:28:10.767673 u2DelayCellOfst[15]=11 cells (3 PI)
7775 09:28:10.774353 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7776 09:28:10.777721 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7777 09:28:10.780861 DramC Write-DBI on
7778 09:28:10.780953 ==
7779 09:28:10.784361 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 09:28:10.787379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 09:28:10.787467 ==
7782 09:28:10.787533
7783 09:28:10.787593
7784 09:28:10.790831 TX Vref Scan disable
7785 09:28:10.790916 == TX Byte 0 ==
7786 09:28:10.797712 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7787 09:28:10.797825 == TX Byte 1 ==
7788 09:28:10.800737 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7789 09:28:10.804242 DramC Write-DBI off
7790 09:28:10.804341
7791 09:28:10.804406 [DATLAT]
7792 09:28:10.807337 Freq=1600, CH0 RK0
7793 09:28:10.807423
7794 09:28:10.807524 DATLAT Default: 0xf
7795 09:28:10.810590 0, 0xFFFF, sum = 0
7796 09:28:10.810678 1, 0xFFFF, sum = 0
7797 09:28:10.814454 2, 0xFFFF, sum = 0
7798 09:28:10.814541 3, 0xFFFF, sum = 0
7799 09:28:10.817424 4, 0xFFFF, sum = 0
7800 09:28:10.817511 5, 0xFFFF, sum = 0
7801 09:28:10.820846 6, 0xFFFF, sum = 0
7802 09:28:10.823949 7, 0xFFFF, sum = 0
7803 09:28:10.824035 8, 0xFFFF, sum = 0
7804 09:28:10.827564 9, 0xFFFF, sum = 0
7805 09:28:10.827649 10, 0xFFFF, sum = 0
7806 09:28:10.830853 11, 0xFFFF, sum = 0
7807 09:28:10.830938 12, 0xFFFF, sum = 0
7808 09:28:10.833822 13, 0xFFFF, sum = 0
7809 09:28:10.833905 14, 0x0, sum = 1
7810 09:28:10.837321 15, 0x0, sum = 2
7811 09:28:10.837404 16, 0x0, sum = 3
7812 09:28:10.840813 17, 0x0, sum = 4
7813 09:28:10.840896 best_step = 15
7814 09:28:10.840961
7815 09:28:10.841035 ==
7816 09:28:10.843999 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 09:28:10.847317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 09:28:10.850672 ==
7819 09:28:10.850754 RX Vref Scan: 1
7820 09:28:10.850834
7821 09:28:10.854462 Set Vref Range= 24 -> 127
7822 09:28:10.854544
7823 09:28:10.857134 RX Vref 24 -> 127, step: 1
7824 09:28:10.857218
7825 09:28:10.857283 RX Delay 11 -> 252, step: 4
7826 09:28:10.857371
7827 09:28:10.860636 Set Vref, RX VrefLevel [Byte0]: 24
7828 09:28:10.863593 [Byte1]: 24
7829 09:28:10.867324
7830 09:28:10.867418 Set Vref, RX VrefLevel [Byte0]: 25
7831 09:28:10.870871 [Byte1]: 25
7832 09:28:10.875605
7833 09:28:10.875703 Set Vref, RX VrefLevel [Byte0]: 26
7834 09:28:10.878714 [Byte1]: 26
7835 09:28:10.882803
7836 09:28:10.882897 Set Vref, RX VrefLevel [Byte0]: 27
7837 09:28:10.885991 [Byte1]: 27
7838 09:28:10.890542
7839 09:28:10.890640 Set Vref, RX VrefLevel [Byte0]: 28
7840 09:28:10.893708 [Byte1]: 28
7841 09:28:10.898051
7842 09:28:10.898135 Set Vref, RX VrefLevel [Byte0]: 29
7843 09:28:10.901558 [Byte1]: 29
7844 09:28:10.905529
7845 09:28:10.905611 Set Vref, RX VrefLevel [Byte0]: 30
7846 09:28:10.908721 [Byte1]: 30
7847 09:28:10.913265
7848 09:28:10.913346 Set Vref, RX VrefLevel [Byte0]: 31
7849 09:28:10.916416 [Byte1]: 31
7850 09:28:10.920854
7851 09:28:10.920937 Set Vref, RX VrefLevel [Byte0]: 32
7852 09:28:10.924217 [Byte1]: 32
7853 09:28:10.928500
7854 09:28:10.928581 Set Vref, RX VrefLevel [Byte0]: 33
7855 09:28:10.931972 [Byte1]: 33
7856 09:28:10.936200
7857 09:28:10.936290 Set Vref, RX VrefLevel [Byte0]: 34
7858 09:28:10.940218 [Byte1]: 34
7859 09:28:10.943507
7860 09:28:10.943589 Set Vref, RX VrefLevel [Byte0]: 35
7861 09:28:10.946735 [Byte1]: 35
7862 09:28:10.951043
7863 09:28:10.951124 Set Vref, RX VrefLevel [Byte0]: 36
7864 09:28:10.954492 [Byte1]: 36
7865 09:28:10.958880
7866 09:28:10.958961 Set Vref, RX VrefLevel [Byte0]: 37
7867 09:28:10.961971 [Byte1]: 37
7868 09:28:10.966539
7869 09:28:10.966620 Set Vref, RX VrefLevel [Byte0]: 38
7870 09:28:10.969916 [Byte1]: 38
7871 09:28:10.973907
7872 09:28:10.973987 Set Vref, RX VrefLevel [Byte0]: 39
7873 09:28:10.977383 [Byte1]: 39
7874 09:28:10.981861
7875 09:28:10.981942 Set Vref, RX VrefLevel [Byte0]: 40
7876 09:28:10.984934 [Byte1]: 40
7877 09:28:10.989650
7878 09:28:10.989730 Set Vref, RX VrefLevel [Byte0]: 41
7879 09:28:10.992506 [Byte1]: 41
7880 09:28:10.996961
7881 09:28:10.997041 Set Vref, RX VrefLevel [Byte0]: 42
7882 09:28:11.000642 [Byte1]: 42
7883 09:28:11.004611
7884 09:28:11.004692 Set Vref, RX VrefLevel [Byte0]: 43
7885 09:28:11.007747 [Byte1]: 43
7886 09:28:11.012185
7887 09:28:11.012265 Set Vref, RX VrefLevel [Byte0]: 44
7888 09:28:11.015482 [Byte1]: 44
7889 09:28:11.019893
7890 09:28:11.019974 Set Vref, RX VrefLevel [Byte0]: 45
7891 09:28:11.022917 [Byte1]: 45
7892 09:28:11.027222
7893 09:28:11.027302 Set Vref, RX VrefLevel [Byte0]: 46
7894 09:28:11.031300 [Byte1]: 46
7895 09:28:11.034750
7896 09:28:11.034832 Set Vref, RX VrefLevel [Byte0]: 47
7897 09:28:11.038075 [Byte1]: 47
7898 09:28:11.042525
7899 09:28:11.042609 Set Vref, RX VrefLevel [Byte0]: 48
7900 09:28:11.045559 [Byte1]: 48
7901 09:28:11.050299
7902 09:28:11.050380 Set Vref, RX VrefLevel [Byte0]: 49
7903 09:28:11.053554 [Byte1]: 49
7904 09:28:11.057967
7905 09:28:11.058049 Set Vref, RX VrefLevel [Byte0]: 50
7906 09:28:11.061050 [Byte1]: 50
7907 09:28:11.065789
7908 09:28:11.065872 Set Vref, RX VrefLevel [Byte0]: 51
7909 09:28:11.068784 [Byte1]: 51
7910 09:28:11.073053
7911 09:28:11.073170 Set Vref, RX VrefLevel [Byte0]: 52
7912 09:28:11.076739 [Byte1]: 52
7913 09:28:11.080820
7914 09:28:11.080917 Set Vref, RX VrefLevel [Byte0]: 53
7915 09:28:11.084189 [Byte1]: 53
7916 09:28:11.088182
7917 09:28:11.088269 Set Vref, RX VrefLevel [Byte0]: 54
7918 09:28:11.091660 [Byte1]: 54
7919 09:28:11.096023
7920 09:28:11.096104 Set Vref, RX VrefLevel [Byte0]: 55
7921 09:28:11.099387 [Byte1]: 55
7922 09:28:11.103280
7923 09:28:11.103361 Set Vref, RX VrefLevel [Byte0]: 56
7924 09:28:11.106692 [Byte1]: 56
7925 09:28:11.111011
7926 09:28:11.111092 Set Vref, RX VrefLevel [Byte0]: 57
7927 09:28:11.114628 [Byte1]: 57
7928 09:28:11.118604
7929 09:28:11.118686 Set Vref, RX VrefLevel [Byte0]: 58
7930 09:28:11.121938 [Byte1]: 58
7931 09:28:11.126255
7932 09:28:11.126336 Set Vref, RX VrefLevel [Byte0]: 59
7933 09:28:11.129459 [Byte1]: 59
7934 09:28:11.133811
7935 09:28:11.133895 Set Vref, RX VrefLevel [Byte0]: 60
7936 09:28:11.137191 [Byte1]: 60
7937 09:28:11.141703
7938 09:28:11.141786 Set Vref, RX VrefLevel [Byte0]: 61
7939 09:28:11.144516 [Byte1]: 61
7940 09:28:11.149584
7941 09:28:11.149666 Set Vref, RX VrefLevel [Byte0]: 62
7942 09:28:11.152150 [Byte1]: 62
7943 09:28:11.157436
7944 09:28:11.157527 Set Vref, RX VrefLevel [Byte0]: 63
7945 09:28:11.160253 [Byte1]: 63
7946 09:28:11.164295
7947 09:28:11.164377 Set Vref, RX VrefLevel [Byte0]: 64
7948 09:28:11.167370 [Byte1]: 64
7949 09:28:11.171897
7950 09:28:11.171983 Set Vref, RX VrefLevel [Byte0]: 65
7951 09:28:11.175460 [Byte1]: 65
7952 09:28:11.179490
7953 09:28:11.179575 Set Vref, RX VrefLevel [Byte0]: 66
7954 09:28:11.183035 [Byte1]: 66
7955 09:28:11.187190
7956 09:28:11.187275 Set Vref, RX VrefLevel [Byte0]: 67
7957 09:28:11.190810 [Byte1]: 67
7958 09:28:11.194767
7959 09:28:11.194853 Set Vref, RX VrefLevel [Byte0]: 68
7960 09:28:11.197963 [Byte1]: 68
7961 09:28:11.202404
7962 09:28:11.202487 Set Vref, RX VrefLevel [Byte0]: 69
7963 09:28:11.206262 [Byte1]: 69
7964 09:28:11.210127
7965 09:28:11.210210 Set Vref, RX VrefLevel [Byte0]: 70
7966 09:28:11.213597 [Byte1]: 70
7967 09:28:11.217755
7968 09:28:11.217838 Set Vref, RX VrefLevel [Byte0]: 71
7969 09:28:11.221351 [Byte1]: 71
7970 09:28:11.225162
7971 09:28:11.225247 Set Vref, RX VrefLevel [Byte0]: 72
7972 09:28:11.228421 [Byte1]: 72
7973 09:28:11.232760
7974 09:28:11.232844 Set Vref, RX VrefLevel [Byte0]: 73
7975 09:28:11.236289 [Byte1]: 73
7976 09:28:11.240383
7977 09:28:11.240466 Set Vref, RX VrefLevel [Byte0]: 74
7978 09:28:11.243637 [Byte1]: 74
7979 09:28:11.248393
7980 09:28:11.248476 Set Vref, RX VrefLevel [Byte0]: 75
7981 09:28:11.251431 [Byte1]: 75
7982 09:28:11.255514
7983 09:28:11.255599 Set Vref, RX VrefLevel [Byte0]: 76
7984 09:28:11.259155 [Byte1]: 76
7985 09:28:11.263164
7986 09:28:11.263247 Set Vref, RX VrefLevel [Byte0]: 77
7987 09:28:11.267355 [Byte1]: 77
7988 09:28:11.270878
7989 09:28:11.270961 Set Vref, RX VrefLevel [Byte0]: 78
7990 09:28:11.273950 [Byte1]: 78
7991 09:28:11.278633
7992 09:28:11.278730 Set Vref, RX VrefLevel [Byte0]: 79
7993 09:28:11.281809 [Byte1]: 79
7994 09:28:11.285994
7995 09:28:11.286080 Set Vref, RX VrefLevel [Byte0]: 80
7996 09:28:11.289262 [Byte1]: 80
7997 09:28:11.293610
7998 09:28:11.293694 Final RX Vref Byte 0 = 68 to rank0
7999 09:28:11.297041 Final RX Vref Byte 1 = 56 to rank0
8000 09:28:11.300505 Final RX Vref Byte 0 = 68 to rank1
8001 09:28:11.303932 Final RX Vref Byte 1 = 56 to rank1==
8002 09:28:11.306929 Dram Type= 6, Freq= 0, CH_0, rank 0
8003 09:28:11.313483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 09:28:11.313598 ==
8005 09:28:11.313680 DQS Delay:
8006 09:28:11.316875 DQS0 = 0, DQS1 = 0
8007 09:28:11.316958 DQM Delay:
8008 09:28:11.317095 DQM0 = 133, DQM1 = 123
8009 09:28:11.320464 DQ Delay:
8010 09:28:11.323549 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8011 09:28:11.326441 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8012 09:28:11.329891 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8013 09:28:11.333400 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8014 09:28:11.333488
8015 09:28:11.333553
8016 09:28:11.333613
8017 09:28:11.336767 [DramC_TX_OE_Calibration] TA2
8018 09:28:11.339753 Original DQ_B0 (3 6) =30, OEN = 27
8019 09:28:11.343128 Original DQ_B1 (3 6) =30, OEN = 27
8020 09:28:11.346334 24, 0x0, End_B0=24 End_B1=24
8021 09:28:11.349690 25, 0x0, End_B0=25 End_B1=25
8022 09:28:11.349775 26, 0x0, End_B0=26 End_B1=26
8023 09:28:11.352840 27, 0x0, End_B0=27 End_B1=27
8024 09:28:11.356396 28, 0x0, End_B0=28 End_B1=28
8025 09:28:11.359327 29, 0x0, End_B0=29 End_B1=29
8026 09:28:11.359436 30, 0x0, End_B0=30 End_B1=30
8027 09:28:11.362894 31, 0x4141, End_B0=30 End_B1=30
8028 09:28:11.366300 Byte0 end_step=30 best_step=27
8029 09:28:11.369114 Byte1 end_step=30 best_step=27
8030 09:28:11.372730 Byte0 TX OE(2T, 0.5T) = (3, 3)
8031 09:28:11.376017 Byte1 TX OE(2T, 0.5T) = (3, 3)
8032 09:28:11.376102
8033 09:28:11.376167
8034 09:28:11.382351 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8035 09:28:11.385931 CH0 RK0: MR19=303, MR18=2112
8036 09:28:11.392778 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8037 09:28:11.392885
8038 09:28:11.395645 ----->DramcWriteLeveling(PI) begin...
8039 09:28:11.395757 ==
8040 09:28:11.398559 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 09:28:11.402546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 09:28:11.405379 ==
8043 09:28:11.405468 Write leveling (Byte 0): 36 => 36
8044 09:28:11.408514 Write leveling (Byte 1): 27 => 27
8045 09:28:11.412075 DramcWriteLeveling(PI) end<-----
8046 09:28:11.412160
8047 09:28:11.412225 ==
8048 09:28:11.415388 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 09:28:11.421806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 09:28:11.421934 ==
8051 09:28:11.425105 [Gating] SW mode calibration
8052 09:28:11.431944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8053 09:28:11.435118 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8054 09:28:11.441486 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 09:28:11.444779 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 09:28:11.448418 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 09:28:11.455233 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8058 09:28:11.458372 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8059 09:28:11.461174 1 4 20 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
8060 09:28:11.467681 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 09:28:11.471039 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 09:28:11.474619 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 09:28:11.481058 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 09:28:11.484347 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 09:28:11.487644 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8066 09:28:11.494810 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8067 09:28:11.497805 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8068 09:28:11.500827 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8069 09:28:11.507834 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 09:28:11.510728 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 09:28:11.514229 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 09:28:11.520655 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 09:28:11.523901 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8074 09:28:11.527135 1 6 16 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8075 09:28:11.533893 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8076 09:28:11.537067 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 09:28:11.540493 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 09:28:11.547304 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 09:28:11.550579 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 09:28:11.553713 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 09:28:11.560578 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 09:28:11.563732 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8083 09:28:11.566810 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8084 09:28:11.573372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 09:28:11.576915 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 09:28:11.580374 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 09:28:11.586584 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 09:28:11.589995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 09:28:11.593492 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 09:28:11.599797 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 09:28:11.602810 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 09:28:11.606284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 09:28:11.612932 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 09:28:11.616014 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 09:28:11.619405 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 09:28:11.625996 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 09:28:11.629598 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 09:28:11.632969 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 09:28:11.635923 Total UI for P1: 0, mck2ui 16
8100 09:28:11.639390 best dqsien dly found for B0: ( 1, 9, 12)
8101 09:28:11.646416 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 09:28:11.646521 Total UI for P1: 0, mck2ui 16
8103 09:28:11.649497 best dqsien dly found for B1: ( 1, 9, 16)
8104 09:28:11.656271 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8105 09:28:11.659320 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8106 09:28:11.659416
8107 09:28:11.662648 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8108 09:28:11.665933 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8109 09:28:11.669091 [Gating] SW calibration Done
8110 09:28:11.669198 ==
8111 09:28:11.672667 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 09:28:11.675950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 09:28:11.676063 ==
8114 09:28:11.679389 RX Vref Scan: 0
8115 09:28:11.679478
8116 09:28:11.679556 RX Vref 0 -> 0, step: 1
8117 09:28:11.679648
8118 09:28:11.682534 RX Delay 0 -> 252, step: 8
8119 09:28:11.685765 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 09:28:11.693094 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8121 09:28:11.695959 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8122 09:28:11.699466 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8123 09:28:11.702149 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8124 09:28:11.705454 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8125 09:28:11.712306 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8126 09:28:11.715639 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8127 09:28:11.718752 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8128 09:28:11.722094 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8129 09:28:11.725344 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8130 09:28:11.732133 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8131 09:28:11.735201 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8132 09:28:11.738551 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8133 09:28:11.742170 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 09:28:11.748522 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 09:28:11.748641 ==
8136 09:28:11.751646 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 09:28:11.755078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 09:28:11.755185 ==
8139 09:28:11.755275 DQS Delay:
8140 09:28:11.758349 DQS0 = 0, DQS1 = 0
8141 09:28:11.758451 DQM Delay:
8142 09:28:11.761822 DQM0 = 133, DQM1 = 127
8143 09:28:11.761897 DQ Delay:
8144 09:28:11.765113 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8145 09:28:11.768521 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8146 09:28:11.772086 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8147 09:28:11.774962 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8148 09:28:11.775046
8149 09:28:11.775111
8150 09:28:11.778537 ==
8151 09:28:11.781449 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 09:28:11.784779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 09:28:11.784866 ==
8154 09:28:11.784932
8155 09:28:11.784993
8156 09:28:11.787889 TX Vref Scan disable
8157 09:28:11.787972 == TX Byte 0 ==
8158 09:28:11.794720 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8159 09:28:11.797756 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8160 09:28:11.797850 == TX Byte 1 ==
8161 09:28:11.804652 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8162 09:28:11.807906 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8163 09:28:11.808000 ==
8164 09:28:11.811227 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 09:28:11.814152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 09:28:11.814236 ==
8167 09:28:11.828886
8168 09:28:11.832787 TX Vref early break, caculate TX vref
8169 09:28:11.835289 TX Vref=16, minBit 2, minWin=22, winSum=377
8170 09:28:11.838456 TX Vref=18, minBit 0, minWin=23, winSum=387
8171 09:28:11.842009 TX Vref=20, minBit 0, minWin=23, winSum=391
8172 09:28:11.845059 TX Vref=22, minBit 1, minWin=23, winSum=396
8173 09:28:11.848503 TX Vref=24, minBit 1, minWin=24, winSum=408
8174 09:28:11.855756 TX Vref=26, minBit 4, minWin=24, winSum=409
8175 09:28:11.858644 TX Vref=28, minBit 0, minWin=25, winSum=413
8176 09:28:11.861874 TX Vref=30, minBit 0, minWin=24, winSum=405
8177 09:28:11.865365 TX Vref=32, minBit 2, minWin=23, winSum=394
8178 09:28:11.868162 TX Vref=34, minBit 1, minWin=23, winSum=390
8179 09:28:11.874865 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8180 09:28:11.874973
8181 09:28:11.878372 Final TX Range 0 Vref 28
8182 09:28:11.878473
8183 09:28:11.878541 ==
8184 09:28:11.881441 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 09:28:11.884785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 09:28:11.884863 ==
8187 09:28:11.884932
8188 09:28:11.884991
8189 09:28:11.888373 TX Vref Scan disable
8190 09:28:11.894701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8191 09:28:11.894788 == TX Byte 0 ==
8192 09:28:11.897983 u2DelayCellOfst[0]=11 cells (3 PI)
8193 09:28:11.901454 u2DelayCellOfst[1]=15 cells (4 PI)
8194 09:28:11.905340 u2DelayCellOfst[2]=11 cells (3 PI)
8195 09:28:11.908382 u2DelayCellOfst[3]=11 cells (3 PI)
8196 09:28:11.911629 u2DelayCellOfst[4]=7 cells (2 PI)
8197 09:28:11.914908 u2DelayCellOfst[5]=0 cells (0 PI)
8198 09:28:11.917910 u2DelayCellOfst[6]=15 cells (4 PI)
8199 09:28:11.921503 u2DelayCellOfst[7]=18 cells (5 PI)
8200 09:28:11.924385 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8201 09:28:11.927664 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8202 09:28:11.931452 == TX Byte 1 ==
8203 09:28:11.934438 u2DelayCellOfst[8]=0 cells (0 PI)
8204 09:28:11.937997 u2DelayCellOfst[9]=0 cells (0 PI)
8205 09:28:11.938103 u2DelayCellOfst[10]=7 cells (2 PI)
8206 09:28:11.941221 u2DelayCellOfst[11]=0 cells (0 PI)
8207 09:28:11.944610 u2DelayCellOfst[12]=11 cells (3 PI)
8208 09:28:11.947282 u2DelayCellOfst[13]=11 cells (3 PI)
8209 09:28:11.950721 u2DelayCellOfst[14]=18 cells (5 PI)
8210 09:28:11.954029 u2DelayCellOfst[15]=11 cells (3 PI)
8211 09:28:11.960856 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8212 09:28:11.964155 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8213 09:28:11.964253 DramC Write-DBI on
8214 09:28:11.964319 ==
8215 09:28:11.967146 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 09:28:11.974159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 09:28:11.974253 ==
8218 09:28:11.974319
8219 09:28:11.974377
8220 09:28:11.974434 TX Vref Scan disable
8221 09:28:11.977973 == TX Byte 0 ==
8222 09:28:11.981303 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8223 09:28:11.984933 == TX Byte 1 ==
8224 09:28:11.988675 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8225 09:28:11.991555 DramC Write-DBI off
8226 09:28:11.991661
8227 09:28:11.991776 [DATLAT]
8228 09:28:11.991856 Freq=1600, CH0 RK1
8229 09:28:11.991915
8230 09:28:11.994900 DATLAT Default: 0xf
8231 09:28:11.998366 0, 0xFFFF, sum = 0
8232 09:28:11.998469 1, 0xFFFF, sum = 0
8233 09:28:12.001207 2, 0xFFFF, sum = 0
8234 09:28:12.001282 3, 0xFFFF, sum = 0
8235 09:28:12.005055 4, 0xFFFF, sum = 0
8236 09:28:12.005130 5, 0xFFFF, sum = 0
8237 09:28:12.007815 6, 0xFFFF, sum = 0
8238 09:28:12.007888 7, 0xFFFF, sum = 0
8239 09:28:12.011572 8, 0xFFFF, sum = 0
8240 09:28:12.011644 9, 0xFFFF, sum = 0
8241 09:28:12.014613 10, 0xFFFF, sum = 0
8242 09:28:12.014688 11, 0xFFFF, sum = 0
8243 09:28:12.017922 12, 0xFFFF, sum = 0
8244 09:28:12.017993 13, 0xFFFF, sum = 0
8245 09:28:12.021264 14, 0x0, sum = 1
8246 09:28:12.021362 15, 0x0, sum = 2
8247 09:28:12.024708 16, 0x0, sum = 3
8248 09:28:12.024785 17, 0x0, sum = 4
8249 09:28:12.027672 best_step = 15
8250 09:28:12.027781
8251 09:28:12.027843 ==
8252 09:28:12.031028 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 09:28:12.034125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 09:28:12.034197 ==
8255 09:28:12.037448 RX Vref Scan: 0
8256 09:28:12.037523
8257 09:28:12.037589 RX Vref 0 -> 0, step: 1
8258 09:28:12.037647
8259 09:28:12.040864 RX Delay 11 -> 252, step: 4
8260 09:28:12.047510 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8261 09:28:12.050893 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8262 09:28:12.054159 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8263 09:28:12.057531 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8264 09:28:12.060874 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8265 09:28:12.067285 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8266 09:28:12.070511 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8267 09:28:12.073663 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8268 09:28:12.077246 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8269 09:28:12.080362 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8270 09:28:12.087831 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8271 09:28:12.091033 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8272 09:28:12.093869 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8273 09:28:12.097065 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8274 09:28:12.103649 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8275 09:28:12.107175 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8276 09:28:12.107273 ==
8277 09:28:12.109848 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 09:28:12.113382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 09:28:12.113473 ==
8280 09:28:12.116786 DQS Delay:
8281 09:28:12.116870 DQS0 = 0, DQS1 = 0
8282 09:28:12.116947 DQM Delay:
8283 09:28:12.120083 DQM0 = 130, DQM1 = 125
8284 09:28:12.120202 DQ Delay:
8285 09:28:12.123089 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126
8286 09:28:12.126515 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8287 09:28:12.129894 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8288 09:28:12.136534 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8289 09:28:12.136638
8290 09:28:12.136704
8291 09:28:12.136764
8292 09:28:12.140124 [DramC_TX_OE_Calibration] TA2
8293 09:28:12.140202 Original DQ_B0 (3 6) =30, OEN = 27
8294 09:28:12.143246 Original DQ_B1 (3 6) =30, OEN = 27
8295 09:28:12.146360 24, 0x0, End_B0=24 End_B1=24
8296 09:28:12.149554 25, 0x0, End_B0=25 End_B1=25
8297 09:28:12.153003 26, 0x0, End_B0=26 End_B1=26
8298 09:28:12.156548 27, 0x0, End_B0=27 End_B1=27
8299 09:28:12.156644 28, 0x0, End_B0=28 End_B1=28
8300 09:28:12.159647 29, 0x0, End_B0=29 End_B1=29
8301 09:28:12.162752 30, 0x0, End_B0=30 End_B1=30
8302 09:28:12.166265 31, 0x4141, End_B0=30 End_B1=30
8303 09:28:12.169591 Byte0 end_step=30 best_step=27
8304 09:28:12.169707 Byte1 end_step=30 best_step=27
8305 09:28:12.172887 Byte0 TX OE(2T, 0.5T) = (3, 3)
8306 09:28:12.175991 Byte1 TX OE(2T, 0.5T) = (3, 3)
8307 09:28:12.176079
8308 09:28:12.176145
8309 09:28:12.185942 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8310 09:28:12.189659 CH0 RK1: MR19=303, MR18=1F02
8311 09:28:12.192883 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8312 09:28:12.195942 [RxdqsGatingPostProcess] freq 1600
8313 09:28:12.202276 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8314 09:28:12.206083 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 09:28:12.209930 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 09:28:12.212360 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 09:28:12.216236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 09:28:12.219201 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 09:28:12.222608 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 09:28:12.222721 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 09:28:12.225437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 09:28:12.229167 Pre-setting of DQS Precalculation
8323 09:28:12.235858 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8324 09:28:12.235960 ==
8325 09:28:12.239210 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 09:28:12.242051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 09:28:12.242152 ==
8328 09:28:12.248590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 09:28:12.251930 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 09:28:12.255751 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 09:28:12.262227 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 09:28:12.271316 [CA 0] Center 41 (12~71) winsize 60
8333 09:28:12.274937 [CA 1] Center 42 (12~72) winsize 61
8334 09:28:12.278088 [CA 2] Center 37 (8~66) winsize 59
8335 09:28:12.281146 [CA 3] Center 36 (7~65) winsize 59
8336 09:28:12.284735 [CA 4] Center 37 (8~66) winsize 59
8337 09:28:12.288050 [CA 5] Center 36 (7~66) winsize 60
8338 09:28:12.288136
8339 09:28:12.291022 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8340 09:28:12.291097
8341 09:28:12.294343 [CATrainingPosCal] consider 1 rank data
8342 09:28:12.297967 u2DelayCellTimex100 = 258/100 ps
8343 09:28:12.301126 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8344 09:28:12.308105 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8345 09:28:12.311201 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 09:28:12.314251 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8347 09:28:12.317526 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8348 09:28:12.321333 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8349 09:28:12.321440
8350 09:28:12.324040 CA PerBit enable=1, Macro0, CA PI delay=36
8351 09:28:12.324118
8352 09:28:12.327446 [CBTSetCACLKResult] CA Dly = 36
8353 09:28:12.330686 CS Dly: 9 (0~40)
8354 09:28:12.334406 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 09:28:12.337431 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 09:28:12.337527 ==
8357 09:28:12.340782 Dram Type= 6, Freq= 0, CH_1, rank 1
8358 09:28:12.344564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 09:28:12.348011 ==
8360 09:28:12.351422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 09:28:12.354284 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 09:28:12.360603 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 09:28:12.367209 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 09:28:12.374517 [CA 0] Center 42 (13~72) winsize 60
8365 09:28:12.377679 [CA 1] Center 42 (12~72) winsize 61
8366 09:28:12.380899 [CA 2] Center 37 (8~67) winsize 60
8367 09:28:12.384605 [CA 3] Center 37 (8~66) winsize 59
8368 09:28:12.387558 [CA 4] Center 37 (8~67) winsize 60
8369 09:28:12.391026 [CA 5] Center 37 (8~66) winsize 59
8370 09:28:12.391263
8371 09:28:12.394527 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8372 09:28:12.394640
8373 09:28:12.398041 [CATrainingPosCal] consider 2 rank data
8374 09:28:12.400937 u2DelayCellTimex100 = 258/100 ps
8375 09:28:12.407641 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8376 09:28:12.410938 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8377 09:28:12.414115 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8378 09:28:12.417137 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8379 09:28:12.420541 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8380 09:28:12.424046 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8381 09:28:12.424175
8382 09:28:12.426999 CA PerBit enable=1, Macro0, CA PI delay=36
8383 09:28:12.427105
8384 09:28:12.430597 [CBTSetCACLKResult] CA Dly = 36
8385 09:28:12.433809 CS Dly: 11 (0~44)
8386 09:28:12.437213 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 09:28:12.440365 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 09:28:12.440445
8389 09:28:12.443688 ----->DramcWriteLeveling(PI) begin...
8390 09:28:12.443817 ==
8391 09:28:12.446980 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 09:28:12.453764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 09:28:12.453864 ==
8394 09:28:12.456786 Write leveling (Byte 0): 22 => 22
8395 09:28:12.460274 Write leveling (Byte 1): 28 => 28
8396 09:28:12.460361 DramcWriteLeveling(PI) end<-----
8397 09:28:12.463248
8398 09:28:12.463324 ==
8399 09:28:12.467095 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 09:28:12.470207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 09:28:12.470286 ==
8402 09:28:12.473652 [Gating] SW mode calibration
8403 09:28:12.479951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8404 09:28:12.486437 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8405 09:28:12.489773 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 09:28:12.493278 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 09:28:12.499828 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 09:28:12.502983 1 4 12 | B1->B0 | 2d2c 3333 | 1 1 | (0 0) (1 1)
8409 09:28:12.506006 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 09:28:12.512804 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 09:28:12.516075 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 09:28:12.519521 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 09:28:12.525932 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 09:28:12.529702 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8415 09:28:12.532826 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8416 09:28:12.535892 1 5 12 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
8417 09:28:12.542782 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 09:28:12.545871 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 09:28:12.549378 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 09:28:12.556052 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 09:28:12.559073 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 09:28:12.562785 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 09:28:12.568848 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8424 09:28:12.572141 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8425 09:28:12.575571 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 09:28:12.582301 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 09:28:12.585690 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 09:28:12.588483 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 09:28:12.595356 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 09:28:12.598951 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 09:28:12.601914 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 09:28:12.608522 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 09:28:12.612020 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8434 09:28:12.615598 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 09:28:12.621539 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 09:28:12.624907 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 09:28:12.628213 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 09:28:12.634796 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 09:28:12.638418 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 09:28:12.641866 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 09:28:12.647883 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 09:28:12.651382 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 09:28:12.654983 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 09:28:12.661340 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 09:28:12.664860 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 09:28:12.668040 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 09:28:12.674540 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8448 09:28:12.677859 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8449 09:28:12.681007 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 09:28:12.684557 Total UI for P1: 0, mck2ui 16
8451 09:28:12.687483 best dqsien dly found for B0: ( 1, 9, 10)
8452 09:28:12.690942 Total UI for P1: 0, mck2ui 16
8453 09:28:12.694264 best dqsien dly found for B1: ( 1, 9, 10)
8454 09:28:12.697340 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8455 09:28:12.700967 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8456 09:28:12.704332
8457 09:28:12.707397 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8458 09:28:12.710785 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8459 09:28:12.714062 [Gating] SW calibration Done
8460 09:28:12.714162 ==
8461 09:28:12.717756 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 09:28:12.721396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 09:28:12.721484 ==
8464 09:28:12.723803 RX Vref Scan: 0
8465 09:28:12.723886
8466 09:28:12.723951 RX Vref 0 -> 0, step: 1
8467 09:28:12.724013
8468 09:28:12.727540 RX Delay 0 -> 252, step: 8
8469 09:28:12.730982 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8470 09:28:12.734164 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8471 09:28:12.740450 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8472 09:28:12.743661 iDelay=208, Bit 3, Center 135 (88 ~ 183) 96
8473 09:28:12.747026 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8474 09:28:12.750419 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8475 09:28:12.753749 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8476 09:28:12.760267 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8477 09:28:12.763666 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8478 09:28:12.766934 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8479 09:28:12.770214 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8480 09:28:12.776473 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8481 09:28:12.779908 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8482 09:28:12.783611 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8483 09:28:12.786269 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8484 09:28:12.793285 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8485 09:28:12.793394 ==
8486 09:28:12.797027 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 09:28:12.799956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 09:28:12.800034 ==
8489 09:28:12.800100 DQS Delay:
8490 09:28:12.802805 DQS0 = 0, DQS1 = 0
8491 09:28:12.802878 DQM Delay:
8492 09:28:12.806236 DQM0 = 138, DQM1 = 130
8493 09:28:12.806310 DQ Delay:
8494 09:28:12.809338 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8495 09:28:12.812782 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8496 09:28:12.816060 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8497 09:28:12.819157 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8498 09:28:12.819235
8499 09:28:12.819326
8500 09:28:12.822598 ==
8501 09:28:12.826417 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 09:28:12.829151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 09:28:12.829277 ==
8504 09:28:12.829344
8505 09:28:12.829404
8506 09:28:12.832537 TX Vref Scan disable
8507 09:28:12.832621 == TX Byte 0 ==
8508 09:28:12.836155 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8509 09:28:12.842701 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8510 09:28:12.842812 == TX Byte 1 ==
8511 09:28:12.849084 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8512 09:28:12.852460 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8513 09:28:12.852559 ==
8514 09:28:12.855687 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 09:28:12.858840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 09:28:12.858929 ==
8517 09:28:12.872475
8518 09:28:12.876219 TX Vref early break, caculate TX vref
8519 09:28:12.879304 TX Vref=16, minBit 5, minWin=21, winSum=364
8520 09:28:12.882262 TX Vref=18, minBit 5, minWin=21, winSum=378
8521 09:28:12.885689 TX Vref=20, minBit 5, minWin=22, winSum=389
8522 09:28:12.889103 TX Vref=22, minBit 0, minWin=23, winSum=398
8523 09:28:12.892621 TX Vref=24, minBit 2, minWin=24, winSum=406
8524 09:28:12.899016 TX Vref=26, minBit 0, minWin=24, winSum=413
8525 09:28:12.902921 TX Vref=28, minBit 0, minWin=24, winSum=414
8526 09:28:12.905967 TX Vref=30, minBit 0, minWin=24, winSum=408
8527 09:28:12.908767 TX Vref=32, minBit 5, minWin=22, winSum=394
8528 09:28:12.912549 TX Vref=34, minBit 5, minWin=22, winSum=387
8529 09:28:12.918858 [TxChooseVref] Worse bit 0, Min win 24, Win sum 414, Final Vref 28
8530 09:28:12.918974
8531 09:28:12.921928 Final TX Range 0 Vref 28
8532 09:28:12.922026
8533 09:28:12.922103 ==
8534 09:28:12.925390 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 09:28:12.928997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 09:28:12.929112 ==
8537 09:28:12.929178
8538 09:28:12.929238
8539 09:28:12.931859 TX Vref Scan disable
8540 09:28:12.938685 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8541 09:28:12.938812 == TX Byte 0 ==
8542 09:28:12.942236 u2DelayCellOfst[0]=18 cells (5 PI)
8543 09:28:12.945302 u2DelayCellOfst[1]=15 cells (4 PI)
8544 09:28:12.948611 u2DelayCellOfst[2]=0 cells (0 PI)
8545 09:28:12.951939 u2DelayCellOfst[3]=7 cells (2 PI)
8546 09:28:12.955333 u2DelayCellOfst[4]=7 cells (2 PI)
8547 09:28:12.958701 u2DelayCellOfst[5]=22 cells (6 PI)
8548 09:28:12.961934 u2DelayCellOfst[6]=22 cells (6 PI)
8549 09:28:12.965058 u2DelayCellOfst[7]=7 cells (2 PI)
8550 09:28:12.968109 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8551 09:28:12.971424 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8552 09:28:12.974885 == TX Byte 1 ==
8553 09:28:12.978392 u2DelayCellOfst[8]=0 cells (0 PI)
8554 09:28:12.978499 u2DelayCellOfst[9]=3 cells (1 PI)
8555 09:28:12.981777 u2DelayCellOfst[10]=11 cells (3 PI)
8556 09:28:12.984736 u2DelayCellOfst[11]=3 cells (1 PI)
8557 09:28:12.988456 u2DelayCellOfst[12]=15 cells (4 PI)
8558 09:28:12.991493 u2DelayCellOfst[13]=15 cells (4 PI)
8559 09:28:12.995087 u2DelayCellOfst[14]=18 cells (5 PI)
8560 09:28:12.998016 u2DelayCellOfst[15]=18 cells (5 PI)
8561 09:28:13.001733 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8562 09:28:13.008131 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8563 09:28:13.008241 DramC Write-DBI on
8564 09:28:13.008307 ==
8565 09:28:13.011255 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 09:28:13.017671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 09:28:13.017765 ==
8568 09:28:13.017830
8569 09:28:13.017920
8570 09:28:13.018007 TX Vref Scan disable
8571 09:28:13.021837 == TX Byte 0 ==
8572 09:28:13.025542 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8573 09:28:13.028622 == TX Byte 1 ==
8574 09:28:13.032051 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8575 09:28:13.034961 DramC Write-DBI off
8576 09:28:13.035066
8577 09:28:13.035155 [DATLAT]
8578 09:28:13.035247 Freq=1600, CH1 RK0
8579 09:28:13.035333
8580 09:28:13.038405 DATLAT Default: 0xf
8581 09:28:13.041595 0, 0xFFFF, sum = 0
8582 09:28:13.041673 1, 0xFFFF, sum = 0
8583 09:28:13.044617 2, 0xFFFF, sum = 0
8584 09:28:13.044692 3, 0xFFFF, sum = 0
8585 09:28:13.048142 4, 0xFFFF, sum = 0
8586 09:28:13.048244 5, 0xFFFF, sum = 0
8587 09:28:13.051510 6, 0xFFFF, sum = 0
8588 09:28:13.051598 7, 0xFFFF, sum = 0
8589 09:28:13.054598 8, 0xFFFF, sum = 0
8590 09:28:13.054672 9, 0xFFFF, sum = 0
8591 09:28:13.058283 10, 0xFFFF, sum = 0
8592 09:28:13.058386 11, 0xFFFF, sum = 0
8593 09:28:13.061433 12, 0xFFFF, sum = 0
8594 09:28:13.061530 13, 0xFFFF, sum = 0
8595 09:28:13.064711 14, 0x0, sum = 1
8596 09:28:13.064788 15, 0x0, sum = 2
8597 09:28:13.068277 16, 0x0, sum = 3
8598 09:28:13.068377 17, 0x0, sum = 4
8599 09:28:13.071159 best_step = 15
8600 09:28:13.071232
8601 09:28:13.071292 ==
8602 09:28:13.074593 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 09:28:13.077615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 09:28:13.077694 ==
8605 09:28:13.081563 RX Vref Scan: 1
8606 09:28:13.081659
8607 09:28:13.081733 Set Vref Range= 24 -> 127
8608 09:28:13.081795
8609 09:28:13.084614 RX Vref 24 -> 127, step: 1
8610 09:28:13.084694
8611 09:28:13.087677 RX Delay 19 -> 252, step: 4
8612 09:28:13.087802
8613 09:28:13.091114 Set Vref, RX VrefLevel [Byte0]: 24
8614 09:28:13.094098 [Byte1]: 24
8615 09:28:13.094174
8616 09:28:13.097348 Set Vref, RX VrefLevel [Byte0]: 25
8617 09:28:13.100846 [Byte1]: 25
8618 09:28:13.104396
8619 09:28:13.104480 Set Vref, RX VrefLevel [Byte0]: 26
8620 09:28:13.108052 [Byte1]: 26
8621 09:28:13.112041
8622 09:28:13.112158 Set Vref, RX VrefLevel [Byte0]: 27
8623 09:28:13.115627 [Byte1]: 27
8624 09:28:13.120029
8625 09:28:13.120142 Set Vref, RX VrefLevel [Byte0]: 28
8626 09:28:13.122889 [Byte1]: 28
8627 09:28:13.127615
8628 09:28:13.127736 Set Vref, RX VrefLevel [Byte0]: 29
8629 09:28:13.130345 [Byte1]: 29
8630 09:28:13.135204
8631 09:28:13.135287 Set Vref, RX VrefLevel [Byte0]: 30
8632 09:28:13.138378 [Byte1]: 30
8633 09:28:13.142305
8634 09:28:13.142412 Set Vref, RX VrefLevel [Byte0]: 31
8635 09:28:13.145801 [Byte1]: 31
8636 09:28:13.149949
8637 09:28:13.150030 Set Vref, RX VrefLevel [Byte0]: 32
8638 09:28:13.153243 [Byte1]: 32
8639 09:28:13.157401
8640 09:28:13.157508 Set Vref, RX VrefLevel [Byte0]: 33
8641 09:28:13.160662 [Byte1]: 33
8642 09:28:13.165267
8643 09:28:13.165360 Set Vref, RX VrefLevel [Byte0]: 34
8644 09:28:13.168266 [Byte1]: 34
8645 09:28:13.172737
8646 09:28:13.172822 Set Vref, RX VrefLevel [Byte0]: 35
8647 09:28:13.176116 [Byte1]: 35
8648 09:28:13.180329
8649 09:28:13.180445 Set Vref, RX VrefLevel [Byte0]: 36
8650 09:28:13.183659 [Byte1]: 36
8651 09:28:13.187891
8652 09:28:13.187975 Set Vref, RX VrefLevel [Byte0]: 37
8653 09:28:13.191323 [Byte1]: 37
8654 09:28:13.195570
8655 09:28:13.195674 Set Vref, RX VrefLevel [Byte0]: 38
8656 09:28:13.198873 [Byte1]: 38
8657 09:28:13.203270
8658 09:28:13.203378 Set Vref, RX VrefLevel [Byte0]: 39
8659 09:28:13.206311 [Byte1]: 39
8660 09:28:13.210911
8661 09:28:13.211018 Set Vref, RX VrefLevel [Byte0]: 40
8662 09:28:13.213832 [Byte1]: 40
8663 09:28:13.217998
8664 09:28:13.218084 Set Vref, RX VrefLevel [Byte0]: 41
8665 09:28:13.221427 [Byte1]: 41
8666 09:28:13.225685
8667 09:28:13.225775 Set Vref, RX VrefLevel [Byte0]: 42
8668 09:28:13.228780 [Byte1]: 42
8669 09:28:13.233172
8670 09:28:13.233258 Set Vref, RX VrefLevel [Byte0]: 43
8671 09:28:13.236632 [Byte1]: 43
8672 09:28:13.240919
8673 09:28:13.241018 Set Vref, RX VrefLevel [Byte0]: 44
8674 09:28:13.244007 [Byte1]: 44
8675 09:28:13.248704
8676 09:28:13.248788 Set Vref, RX VrefLevel [Byte0]: 45
8677 09:28:13.251741 [Byte1]: 45
8678 09:28:13.255871
8679 09:28:13.255980 Set Vref, RX VrefLevel [Byte0]: 46
8680 09:28:13.259594 [Byte1]: 46
8681 09:28:13.263372
8682 09:28:13.263458 Set Vref, RX VrefLevel [Byte0]: 47
8683 09:28:13.267172 [Byte1]: 47
8684 09:28:13.271230
8685 09:28:13.271312 Set Vref, RX VrefLevel [Byte0]: 48
8686 09:28:13.274640 [Byte1]: 48
8687 09:28:13.278896
8688 09:28:13.278980 Set Vref, RX VrefLevel [Byte0]: 49
8689 09:28:13.282074 [Byte1]: 49
8690 09:28:13.286202
8691 09:28:13.286316 Set Vref, RX VrefLevel [Byte0]: 50
8692 09:28:13.289440 [Byte1]: 50
8693 09:28:13.293730
8694 09:28:13.293841 Set Vref, RX VrefLevel [Byte0]: 51
8695 09:28:13.297316 [Byte1]: 51
8696 09:28:13.301695
8697 09:28:13.301775 Set Vref, RX VrefLevel [Byte0]: 52
8698 09:28:13.305017 [Byte1]: 52
8699 09:28:13.309019
8700 09:28:13.309126 Set Vref, RX VrefLevel [Byte0]: 53
8701 09:28:13.312633 [Byte1]: 53
8702 09:28:13.316323
8703 09:28:13.316417 Set Vref, RX VrefLevel [Byte0]: 54
8704 09:28:13.319837 [Byte1]: 54
8705 09:28:13.324350
8706 09:28:13.324460 Set Vref, RX VrefLevel [Byte0]: 55
8707 09:28:13.327656 [Byte1]: 55
8708 09:28:13.331547
8709 09:28:13.331634 Set Vref, RX VrefLevel [Byte0]: 56
8710 09:28:13.335026 [Byte1]: 56
8711 09:28:13.339451
8712 09:28:13.339541 Set Vref, RX VrefLevel [Byte0]: 57
8713 09:28:13.342964 [Byte1]: 57
8714 09:28:13.347021
8715 09:28:13.347110 Set Vref, RX VrefLevel [Byte0]: 58
8716 09:28:13.349924 [Byte1]: 58
8717 09:28:13.354261
8718 09:28:13.354353 Set Vref, RX VrefLevel [Byte0]: 59
8719 09:28:13.358056 [Byte1]: 59
8720 09:28:13.361888
8721 09:28:13.361979 Set Vref, RX VrefLevel [Byte0]: 60
8722 09:28:13.365180 [Byte1]: 60
8723 09:28:13.369895
8724 09:28:13.373287 Set Vref, RX VrefLevel [Byte0]: 61
8725 09:28:13.373383 [Byte1]: 61
8726 09:28:13.377000
8727 09:28:13.377089 Set Vref, RX VrefLevel [Byte0]: 62
8728 09:28:13.380421 [Byte1]: 62
8729 09:28:13.384898
8730 09:28:13.385034 Set Vref, RX VrefLevel [Byte0]: 63
8731 09:28:13.387813 [Byte1]: 63
8732 09:28:13.392422
8733 09:28:13.392514 Set Vref, RX VrefLevel [Byte0]: 64
8734 09:28:13.395636 [Byte1]: 64
8735 09:28:13.399775
8736 09:28:13.399867 Set Vref, RX VrefLevel [Byte0]: 65
8737 09:28:13.403797 [Byte1]: 65
8738 09:28:13.407530
8739 09:28:13.407616 Set Vref, RX VrefLevel [Byte0]: 66
8740 09:28:13.411016 [Byte1]: 66
8741 09:28:13.415076
8742 09:28:13.415162 Set Vref, RX VrefLevel [Byte0]: 67
8743 09:28:13.418266 [Byte1]: 67
8744 09:28:13.422795
8745 09:28:13.422882 Set Vref, RX VrefLevel [Byte0]: 68
8746 09:28:13.426270 [Byte1]: 68
8747 09:28:13.430294
8748 09:28:13.430380 Set Vref, RX VrefLevel [Byte0]: 69
8749 09:28:13.433592 [Byte1]: 69
8750 09:28:13.437738
8751 09:28:13.437828 Set Vref, RX VrefLevel [Byte0]: 70
8752 09:28:13.440990 [Byte1]: 70
8753 09:28:13.445317
8754 09:28:13.445408 Set Vref, RX VrefLevel [Byte0]: 71
8755 09:28:13.448490 [Byte1]: 71
8756 09:28:13.453010
8757 09:28:13.453113 Set Vref, RX VrefLevel [Byte0]: 72
8758 09:28:13.456464 [Byte1]: 72
8759 09:28:13.460347
8760 09:28:13.460464 Final RX Vref Byte 0 = 53 to rank0
8761 09:28:13.463534 Final RX Vref Byte 1 = 60 to rank0
8762 09:28:13.466981 Final RX Vref Byte 0 = 53 to rank1
8763 09:28:13.470318 Final RX Vref Byte 1 = 60 to rank1==
8764 09:28:13.473774 Dram Type= 6, Freq= 0, CH_1, rank 0
8765 09:28:13.480319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 09:28:13.480484 ==
8767 09:28:13.480556 DQS Delay:
8768 09:28:13.483430 DQS0 = 0, DQS1 = 0
8769 09:28:13.483518 DQM Delay:
8770 09:28:13.483585 DQM0 = 134, DQM1 = 129
8771 09:28:13.487497 DQ Delay:
8772 09:28:13.491046 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8773 09:28:13.493264 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8774 09:28:13.496655 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8775 09:28:13.500051 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8776 09:28:13.500143
8777 09:28:13.500209
8778 09:28:13.500272
8779 09:28:13.503219 [DramC_TX_OE_Calibration] TA2
8780 09:28:13.506968 Original DQ_B0 (3 6) =30, OEN = 27
8781 09:28:13.510402 Original DQ_B1 (3 6) =30, OEN = 27
8782 09:28:13.513530 24, 0x0, End_B0=24 End_B1=24
8783 09:28:13.513648 25, 0x0, End_B0=25 End_B1=25
8784 09:28:13.516696 26, 0x0, End_B0=26 End_B1=26
8785 09:28:13.519924 27, 0x0, End_B0=27 End_B1=27
8786 09:28:13.523009 28, 0x0, End_B0=28 End_B1=28
8787 09:28:13.526592 29, 0x0, End_B0=29 End_B1=29
8788 09:28:13.526685 30, 0x0, End_B0=30 End_B1=30
8789 09:28:13.529549 31, 0x4141, End_B0=30 End_B1=30
8790 09:28:13.533303 Byte0 end_step=30 best_step=27
8791 09:28:13.536130 Byte1 end_step=30 best_step=27
8792 09:28:13.539569 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 09:28:13.543444 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 09:28:13.543536
8795 09:28:13.543603
8796 09:28:13.549489 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8797 09:28:13.552783 CH1 RK0: MR19=303, MR18=1B11
8798 09:28:13.559166 CH1_RK0: MR19=0x303, MR18=0x1B11, DQSOSC=396, MR23=63, INC=23, DEC=15
8799 09:28:13.559266
8800 09:28:13.562432 ----->DramcWriteLeveling(PI) begin...
8801 09:28:13.562524 ==
8802 09:28:13.566025 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 09:28:13.569196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 09:28:13.569284 ==
8805 09:28:13.572409 Write leveling (Byte 0): 24 => 24
8806 09:28:13.576055 Write leveling (Byte 1): 29 => 29
8807 09:28:13.579418 DramcWriteLeveling(PI) end<-----
8808 09:28:13.579507
8809 09:28:13.579574 ==
8810 09:28:13.582755 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 09:28:13.585707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 09:28:13.589123 ==
8813 09:28:13.589210 [Gating] SW mode calibration
8814 09:28:13.599274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8815 09:28:13.602400 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8816 09:28:13.605799 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 09:28:13.613080 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 09:28:13.616144 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8819 09:28:13.618826 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8820 09:28:13.625731 1 4 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8821 09:28:13.628840 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 09:28:13.631965 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 09:28:13.639356 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 09:28:13.641627 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 09:28:13.645190 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 09:28:13.652057 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8827 09:28:13.655534 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8828 09:28:13.658734 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 09:28:13.664893 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 09:28:13.668410 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 09:28:13.671551 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 09:28:13.678243 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 09:28:13.681670 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 09:28:13.684822 1 6 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
8835 09:28:13.691331 1 6 12 | B1->B0 | 4545 2525 | 0 0 | (0 0) (0 0)
8836 09:28:13.694592 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 09:28:13.697730 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 09:28:13.704703 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 09:28:13.707604 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 09:28:13.711038 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 09:28:13.717455 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 09:28:13.721133 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8843 09:28:13.724134 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8844 09:28:13.730718 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8845 09:28:13.734110 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 09:28:13.738344 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 09:28:13.743912 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 09:28:13.747377 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 09:28:13.750647 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 09:28:13.757144 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 09:28:13.760656 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 09:28:13.764357 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 09:28:13.770810 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 09:28:13.773762 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 09:28:13.777248 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 09:28:13.783645 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 09:28:13.787087 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 09:28:13.790742 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 09:28:13.797070 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8860 09:28:13.797173 Total UI for P1: 0, mck2ui 16
8861 09:28:13.804111 best dqsien dly found for B1: ( 1, 9, 8)
8862 09:28:13.806848 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8863 09:28:13.811035 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 09:28:13.813643 Total UI for P1: 0, mck2ui 16
8865 09:28:13.816831 best dqsien dly found for B0: ( 1, 9, 12)
8866 09:28:13.820042 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8867 09:28:13.823535 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8868 09:28:13.823614
8869 09:28:13.830073 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8870 09:28:13.833184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8871 09:28:13.836442 [Gating] SW calibration Done
8872 09:28:13.836520 ==
8873 09:28:13.840237 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 09:28:13.843047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 09:28:13.843123 ==
8876 09:28:13.843184 RX Vref Scan: 0
8877 09:28:13.843247
8878 09:28:13.846620 RX Vref 0 -> 0, step: 1
8879 09:28:13.846694
8880 09:28:13.849812 RX Delay 0 -> 252, step: 8
8881 09:28:13.853577 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8882 09:28:13.857062 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8883 09:28:13.860100 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8884 09:28:13.866635 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8885 09:28:13.869879 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8886 09:28:13.873066 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8887 09:28:13.876328 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8888 09:28:13.879526 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8889 09:28:13.886673 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8890 09:28:13.889831 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8891 09:28:13.893006 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8892 09:28:13.896114 iDelay=208, Bit 11, Center 115 (56 ~ 175) 120
8893 09:28:13.902678 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8894 09:28:13.906075 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8895 09:28:13.909707 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8896 09:28:13.912966 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8897 09:28:13.913064 ==
8898 09:28:13.916102 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 09:28:13.922955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 09:28:13.923073 ==
8901 09:28:13.923176 DQS Delay:
8902 09:28:13.923265 DQS0 = 0, DQS1 = 0
8903 09:28:13.925908 DQM Delay:
8904 09:28:13.925985 DQM0 = 136, DQM1 = 128
8905 09:28:13.929262 DQ Delay:
8906 09:28:13.932317 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8907 09:28:13.935848 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8908 09:28:13.939128 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =115
8909 09:28:13.942503 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8910 09:28:13.942609
8911 09:28:13.942710
8912 09:28:13.942797 ==
8913 09:28:13.945551 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 09:28:13.952352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 09:28:13.952469 ==
8916 09:28:13.952571
8917 09:28:13.952660
8918 09:28:13.952754 TX Vref Scan disable
8919 09:28:13.955442 == TX Byte 0 ==
8920 09:28:13.959137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8921 09:28:13.962485 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 09:28:13.965432 == TX Byte 1 ==
8923 09:28:13.969078 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8924 09:28:13.975388 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8925 09:28:13.975488 ==
8926 09:28:13.978378 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 09:28:13.981685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 09:28:13.981802 ==
8929 09:28:13.994596
8930 09:28:13.997866 TX Vref early break, caculate TX vref
8931 09:28:14.001046 TX Vref=16, minBit 1, minWin=22, winSum=380
8932 09:28:14.004227 TX Vref=18, minBit 0, minWin=23, winSum=388
8933 09:28:14.007895 TX Vref=20, minBit 8, minWin=23, winSum=398
8934 09:28:14.010936 TX Vref=22, minBit 0, minWin=23, winSum=402
8935 09:28:14.014154 TX Vref=24, minBit 1, minWin=24, winSum=412
8936 09:28:14.021029 TX Vref=26, minBit 5, minWin=25, winSum=420
8937 09:28:14.024352 TX Vref=28, minBit 0, minWin=25, winSum=416
8938 09:28:14.027414 TX Vref=30, minBit 9, minWin=24, winSum=413
8939 09:28:14.030928 TX Vref=32, minBit 0, minWin=23, winSum=399
8940 09:28:14.034177 TX Vref=34, minBit 1, minWin=23, winSum=391
8941 09:28:14.040658 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 26
8942 09:28:14.040768
8943 09:28:14.044194 Final TX Range 0 Vref 26
8944 09:28:14.044279
8945 09:28:14.044361 ==
8946 09:28:14.047640 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 09:28:14.050456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 09:28:14.050536 ==
8949 09:28:14.050619
8950 09:28:14.050702
8951 09:28:14.053778 TX Vref Scan disable
8952 09:28:14.060518 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8953 09:28:14.060614 == TX Byte 0 ==
8954 09:28:14.063689 u2DelayCellOfst[0]=18 cells (5 PI)
8955 09:28:14.067110 u2DelayCellOfst[1]=11 cells (3 PI)
8956 09:28:14.070838 u2DelayCellOfst[2]=0 cells (0 PI)
8957 09:28:14.073622 u2DelayCellOfst[3]=7 cells (2 PI)
8958 09:28:14.077410 u2DelayCellOfst[4]=7 cells (2 PI)
8959 09:28:14.080589 u2DelayCellOfst[5]=22 cells (6 PI)
8960 09:28:14.083338 u2DelayCellOfst[6]=18 cells (5 PI)
8961 09:28:14.086765 u2DelayCellOfst[7]=3 cells (1 PI)
8962 09:28:14.089933 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8963 09:28:14.093547 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8964 09:28:14.096843 == TX Byte 1 ==
8965 09:28:14.100352 u2DelayCellOfst[8]=0 cells (0 PI)
8966 09:28:14.103459 u2DelayCellOfst[9]=7 cells (2 PI)
8967 09:28:14.103544 u2DelayCellOfst[10]=15 cells (4 PI)
8968 09:28:14.106661 u2DelayCellOfst[11]=7 cells (2 PI)
8969 09:28:14.110088 u2DelayCellOfst[12]=15 cells (4 PI)
8970 09:28:14.112969 u2DelayCellOfst[13]=18 cells (5 PI)
8971 09:28:14.116474 u2DelayCellOfst[14]=18 cells (5 PI)
8972 09:28:14.119905 u2DelayCellOfst[15]=18 cells (5 PI)
8973 09:28:14.126465 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8974 09:28:14.129603 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8975 09:28:14.129695 DramC Write-DBI on
8976 09:28:14.129779 ==
8977 09:28:14.133284 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 09:28:14.139875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 09:28:14.140007 ==
8980 09:28:14.140096
8981 09:28:14.140174
8982 09:28:14.140254 TX Vref Scan disable
8983 09:28:14.144212 == TX Byte 0 ==
8984 09:28:14.146849 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8985 09:28:14.150147 == TX Byte 1 ==
8986 09:28:14.153763 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8987 09:28:14.157132 DramC Write-DBI off
8988 09:28:14.157223
8989 09:28:14.157307 [DATLAT]
8990 09:28:14.157385 Freq=1600, CH1 RK1
8991 09:28:14.157463
8992 09:28:14.160355 DATLAT Default: 0xf
8993 09:28:14.163523 0, 0xFFFF, sum = 0
8994 09:28:14.163611 1, 0xFFFF, sum = 0
8995 09:28:14.167191 2, 0xFFFF, sum = 0
8996 09:28:14.167271 3, 0xFFFF, sum = 0
8997 09:28:14.170071 4, 0xFFFF, sum = 0
8998 09:28:14.170149 5, 0xFFFF, sum = 0
8999 09:28:14.173476 6, 0xFFFF, sum = 0
9000 09:28:14.173579 7, 0xFFFF, sum = 0
9001 09:28:14.176703 8, 0xFFFF, sum = 0
9002 09:28:14.176781 9, 0xFFFF, sum = 0
9003 09:28:14.180125 10, 0xFFFF, sum = 0
9004 09:28:14.180216 11, 0xFFFF, sum = 0
9005 09:28:14.183223 12, 0xFFFF, sum = 0
9006 09:28:14.183334 13, 0xFFFF, sum = 0
9007 09:28:14.186960 14, 0x0, sum = 1
9008 09:28:14.187041 15, 0x0, sum = 2
9009 09:28:14.189956 16, 0x0, sum = 3
9010 09:28:14.190034 17, 0x0, sum = 4
9011 09:28:14.193569 best_step = 15
9012 09:28:14.193670
9013 09:28:14.193768 ==
9014 09:28:14.196665 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 09:28:14.199881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 09:28:14.199960 ==
9017 09:28:14.203355 RX Vref Scan: 0
9018 09:28:14.203464
9019 09:28:14.203578 RX Vref 0 -> 0, step: 1
9020 09:28:14.203700
9021 09:28:14.206464 RX Delay 11 -> 252, step: 4
9022 09:28:14.213216 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9023 09:28:14.216178 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9024 09:28:14.219676 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9025 09:28:14.223225 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9026 09:28:14.226978 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9027 09:28:14.233155 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9028 09:28:14.235982 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9029 09:28:14.239299 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9030 09:28:14.242765 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9031 09:28:14.245859 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9032 09:28:14.252753 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9033 09:28:14.255835 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9034 09:28:14.259615 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9035 09:28:14.262606 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9036 09:28:14.269024 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9037 09:28:14.272577 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9038 09:28:14.272670 ==
9039 09:28:14.275517 Dram Type= 6, Freq= 0, CH_1, rank 1
9040 09:28:14.279185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9041 09:28:14.279300 ==
9042 09:28:14.283027 DQS Delay:
9043 09:28:14.283150 DQS0 = 0, DQS1 = 0
9044 09:28:14.283236 DQM Delay:
9045 09:28:14.286044 DQM0 = 134, DQM1 = 126
9046 09:28:14.286156 DQ Delay:
9047 09:28:14.288954 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9048 09:28:14.291946 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =130
9049 09:28:14.295331 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9050 09:28:14.301973 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9051 09:28:14.302070
9052 09:28:14.302170
9053 09:28:14.302249
9054 09:28:14.305709 [DramC_TX_OE_Calibration] TA2
9055 09:28:14.308638 Original DQ_B0 (3 6) =30, OEN = 27
9056 09:28:14.308719 Original DQ_B1 (3 6) =30, OEN = 27
9057 09:28:14.311923 24, 0x0, End_B0=24 End_B1=24
9058 09:28:14.315337 25, 0x0, End_B0=25 End_B1=25
9059 09:28:14.318718 26, 0x0, End_B0=26 End_B1=26
9060 09:28:14.322228 27, 0x0, End_B0=27 End_B1=27
9061 09:28:14.322337 28, 0x0, End_B0=28 End_B1=28
9062 09:28:14.325069 29, 0x0, End_B0=29 End_B1=29
9063 09:28:14.328406 30, 0x0, End_B0=30 End_B1=30
9064 09:28:14.331612 31, 0x4141, End_B0=30 End_B1=30
9065 09:28:14.335548 Byte0 end_step=30 best_step=27
9066 09:28:14.338268 Byte1 end_step=30 best_step=27
9067 09:28:14.338374 Byte0 TX OE(2T, 0.5T) = (3, 3)
9068 09:28:14.341714 Byte1 TX OE(2T, 0.5T) = (3, 3)
9069 09:28:14.341792
9070 09:28:14.341874
9071 09:28:14.351393 [DQSOSCAuto] RK1, (LSB)MR18= 0xd08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9072 09:28:14.354934 CH1 RK1: MR19=303, MR18=D08
9073 09:28:14.358106 CH1_RK1: MR19=0x303, MR18=0xD08, DQSOSC=403, MR23=63, INC=22, DEC=15
9074 09:28:14.361310 [RxdqsGatingPostProcess] freq 1600
9075 09:28:14.367890 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9076 09:28:14.371214 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 09:28:14.374620 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 09:28:14.377864 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 09:28:14.381052 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 09:28:14.384382 best DQS0 dly(2T, 0.5T) = (1, 1)
9081 09:28:14.384491 best DQS1 dly(2T, 0.5T) = (1, 1)
9082 09:28:14.387634 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9083 09:28:14.391178 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9084 09:28:14.394355 Pre-setting of DQS Precalculation
9085 09:28:14.401007 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9086 09:28:14.407361 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9087 09:28:14.414223 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9088 09:28:14.414361
9089 09:28:14.414451
9090 09:28:14.417453 [Calibration Summary] 3200 Mbps
9091 09:28:14.420702 CH 0, Rank 0
9092 09:28:14.420785 SW Impedance : PASS
9093 09:28:14.424280 DUTY Scan : NO K
9094 09:28:14.424391 ZQ Calibration : PASS
9095 09:28:14.427388 Jitter Meter : NO K
9096 09:28:14.431024 CBT Training : PASS
9097 09:28:14.431133 Write leveling : PASS
9098 09:28:14.434260 RX DQS gating : PASS
9099 09:28:14.437390 RX DQ/DQS(RDDQC) : PASS
9100 09:28:14.437484 TX DQ/DQS : PASS
9101 09:28:14.440691 RX DATLAT : PASS
9102 09:28:14.444076 RX DQ/DQS(Engine): PASS
9103 09:28:14.444157 TX OE : PASS
9104 09:28:14.447483 All Pass.
9105 09:28:14.447558
9106 09:28:14.447624 CH 0, Rank 1
9107 09:28:14.450448 SW Impedance : PASS
9108 09:28:14.450546 DUTY Scan : NO K
9109 09:28:14.453907 ZQ Calibration : PASS
9110 09:28:14.457303 Jitter Meter : NO K
9111 09:28:14.457383 CBT Training : PASS
9112 09:28:14.460429 Write leveling : PASS
9113 09:28:14.464078 RX DQS gating : PASS
9114 09:28:14.464160 RX DQ/DQS(RDDQC) : PASS
9115 09:28:14.467285 TX DQ/DQS : PASS
9116 09:28:14.470640 RX DATLAT : PASS
9117 09:28:14.470745 RX DQ/DQS(Engine): PASS
9118 09:28:14.473570 TX OE : PASS
9119 09:28:14.473651 All Pass.
9120 09:28:14.473715
9121 09:28:14.476711 CH 1, Rank 0
9122 09:28:14.476822 SW Impedance : PASS
9123 09:28:14.479938 DUTY Scan : NO K
9124 09:28:14.483092 ZQ Calibration : PASS
9125 09:28:14.483210 Jitter Meter : NO K
9126 09:28:14.486776 CBT Training : PASS
9127 09:28:14.489922 Write leveling : PASS
9128 09:28:14.490001 RX DQS gating : PASS
9129 09:28:14.493509 RX DQ/DQS(RDDQC) : PASS
9130 09:28:14.496219 TX DQ/DQS : PASS
9131 09:28:14.496331 RX DATLAT : PASS
9132 09:28:14.499619 RX DQ/DQS(Engine): PASS
9133 09:28:14.502771 TX OE : PASS
9134 09:28:14.502891 All Pass.
9135 09:28:14.502985
9136 09:28:14.503077 CH 1, Rank 1
9137 09:28:14.506247 SW Impedance : PASS
9138 09:28:14.509723 DUTY Scan : NO K
9139 09:28:14.509831 ZQ Calibration : PASS
9140 09:28:14.513587 Jitter Meter : NO K
9141 09:28:14.513682 CBT Training : PASS
9142 09:28:14.516208 Write leveling : PASS
9143 09:28:14.519781 RX DQS gating : PASS
9144 09:28:14.519884 RX DQ/DQS(RDDQC) : PASS
9145 09:28:14.523169 TX DQ/DQS : PASS
9146 09:28:14.525955 RX DATLAT : PASS
9147 09:28:14.526053 RX DQ/DQS(Engine): PASS
9148 09:28:14.529486 TX OE : PASS
9149 09:28:14.529570 All Pass.
9150 09:28:14.529636
9151 09:28:14.532734 DramC Write-DBI on
9152 09:28:14.536458 PER_BANK_REFRESH: Hybrid Mode
9153 09:28:14.536571 TX_TRACKING: ON
9154 09:28:14.546027 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9155 09:28:14.552463 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9156 09:28:14.562295 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9157 09:28:14.565539 [FAST_K] Save calibration result to emmc
9158 09:28:14.565628 sync common calibartion params.
9159 09:28:14.569065 sync cbt_mode0:1, 1:1
9160 09:28:14.572713 dram_init: ddr_geometry: 2
9161 09:28:14.575463 dram_init: ddr_geometry: 2
9162 09:28:14.575541 dram_init: ddr_geometry: 2
9163 09:28:14.578734 0:dram_rank_size:100000000
9164 09:28:14.582387 1:dram_rank_size:100000000
9165 09:28:14.585368 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9166 09:28:14.588817 DFS_SHUFFLE_HW_MODE: ON
9167 09:28:14.592102 dramc_set_vcore_voltage set vcore to 725000
9168 09:28:14.595521 Read voltage for 1600, 0
9169 09:28:14.595602 Vio18 = 0
9170 09:28:14.599128 Vcore = 725000
9171 09:28:14.599202 Vdram = 0
9172 09:28:14.599263 Vddq = 0
9173 09:28:14.599322 Vmddr = 0
9174 09:28:14.602150 switch to 3200 Mbps bootup
9175 09:28:14.605266 [DramcRunTimeConfig]
9176 09:28:14.605359 PHYPLL
9177 09:28:14.609036 DPM_CONTROL_AFTERK: ON
9178 09:28:14.609118 PER_BANK_REFRESH: ON
9179 09:28:14.612205 REFRESH_OVERHEAD_REDUCTION: ON
9180 09:28:14.615039 CMD_PICG_NEW_MODE: OFF
9181 09:28:14.615141 XRTWTW_NEW_MODE: ON
9182 09:28:14.618607 XRTRTR_NEW_MODE: ON
9183 09:28:14.618692 TX_TRACKING: ON
9184 09:28:14.621976 RDSEL_TRACKING: OFF
9185 09:28:14.624996 DQS Precalculation for DVFS: ON
9186 09:28:14.625108 RX_TRACKING: OFF
9187 09:28:14.629393 HW_GATING DBG: ON
9188 09:28:14.629506 ZQCS_ENABLE_LP4: ON
9189 09:28:14.631617 RX_PICG_NEW_MODE: ON
9190 09:28:14.631754 TX_PICG_NEW_MODE: ON
9191 09:28:14.635137 ENABLE_RX_DCM_DPHY: ON
9192 09:28:14.638382 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9193 09:28:14.641492 DUMMY_READ_FOR_TRACKING: OFF
9194 09:28:14.641596 !!! SPM_CONTROL_AFTERK: OFF
9195 09:28:14.644798 !!! SPM could not control APHY
9196 09:28:14.648057 IMPEDANCE_TRACKING: ON
9197 09:28:14.648149 TEMP_SENSOR: ON
9198 09:28:14.651827 HW_SAVE_FOR_SR: OFF
9199 09:28:14.654835 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9200 09:28:14.657886 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9201 09:28:14.657970 Read ODT Tracking: ON
9202 09:28:14.661408 Refresh Rate DeBounce: ON
9203 09:28:14.664856 DFS_NO_QUEUE_FLUSH: ON
9204 09:28:14.667772 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9205 09:28:14.671931 ENABLE_DFS_RUNTIME_MRW: OFF
9206 09:28:14.672012 DDR_RESERVE_NEW_MODE: ON
9207 09:28:14.674505 MR_CBT_SWITCH_FREQ: ON
9208 09:28:14.677632 =========================
9209 09:28:14.695282 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9210 09:28:14.698329 dram_init: ddr_geometry: 2
9211 09:28:14.716742 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9212 09:28:14.719922 dram_init: dram init end (result: 0)
9213 09:28:14.726776 DRAM-K: Full calibration passed in 24656 msecs
9214 09:28:14.729940 MRC: failed to locate region type 0.
9215 09:28:14.730051 DRAM rank0 size:0x100000000,
9216 09:28:14.733489 DRAM rank1 size=0x100000000
9217 09:28:14.742973 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9218 09:28:14.749624 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9219 09:28:14.756385 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9220 09:28:14.766578 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9221 09:28:14.766747 DRAM rank0 size:0x100000000,
9222 09:28:14.769303 DRAM rank1 size=0x100000000
9223 09:28:14.769409 CBMEM:
9224 09:28:14.772817 IMD: root @ 0xfffff000 254 entries.
9225 09:28:14.775969 IMD: root @ 0xffffec00 62 entries.
9226 09:28:14.779143 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9227 09:28:14.785918 WARNING: RO_VPD is uninitialized or empty.
9228 09:28:14.789615 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9229 09:28:14.797172 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9230 09:28:14.809704 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9231 09:28:14.820957 BS: romstage times (exec / console): total (unknown) / 24144 ms
9232 09:28:14.821094
9233 09:28:14.821162
9234 09:28:14.830762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9235 09:28:14.834022 ARM64: Exception handlers installed.
9236 09:28:14.837262 ARM64: Testing exception
9237 09:28:14.840484 ARM64: Done test exception
9238 09:28:14.840602 Enumerating buses...
9239 09:28:14.843785 Show all devs... Before device enumeration.
9240 09:28:14.847470 Root Device: enabled 1
9241 09:28:14.851040 CPU_CLUSTER: 0: enabled 1
9242 09:28:14.851134 CPU: 00: enabled 1
9243 09:28:14.854502 Compare with tree...
9244 09:28:14.854610 Root Device: enabled 1
9245 09:28:14.857628 CPU_CLUSTER: 0: enabled 1
9246 09:28:14.860709 CPU: 00: enabled 1
9247 09:28:14.860809 Root Device scanning...
9248 09:28:14.864084 scan_static_bus for Root Device
9249 09:28:14.867115 CPU_CLUSTER: 0 enabled
9250 09:28:14.870412 scan_static_bus for Root Device done
9251 09:28:14.873644 scan_bus: bus Root Device finished in 8 msecs
9252 09:28:14.873745 done
9253 09:28:14.880319 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9254 09:28:14.883648 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9255 09:28:14.890459 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9256 09:28:14.893348 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9257 09:28:14.897017 Allocating resources...
9258 09:28:14.899903 Reading resources...
9259 09:28:14.903191 Root Device read_resources bus 0 link: 0
9260 09:28:14.906810 DRAM rank0 size:0x100000000,
9261 09:28:14.906895 DRAM rank1 size=0x100000000
9262 09:28:14.910014 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9263 09:28:14.913192 CPU: 00 missing read_resources
9264 09:28:14.919908 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9265 09:28:14.923009 Root Device read_resources bus 0 link: 0 done
9266 09:28:14.926470 Done reading resources.
9267 09:28:14.930317 Show resources in subtree (Root Device)...After reading.
9268 09:28:14.932949 Root Device child on link 0 CPU_CLUSTER: 0
9269 09:28:14.936375 CPU_CLUSTER: 0 child on link 0 CPU: 00
9270 09:28:14.946438 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9271 09:28:14.946602 CPU: 00
9272 09:28:14.952929 Root Device assign_resources, bus 0 link: 0
9273 09:28:14.953061 CPU_CLUSTER: 0 missing set_resources
9274 09:28:14.959307 Root Device assign_resources, bus 0 link: 0 done
9275 09:28:14.959437 Done setting resources.
9276 09:28:14.966140 Show resources in subtree (Root Device)...After assigning values.
9277 09:28:14.969275 Root Device child on link 0 CPU_CLUSTER: 0
9278 09:28:14.972854 CPU_CLUSTER: 0 child on link 0 CPU: 00
9279 09:28:14.982638 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9280 09:28:14.982793 CPU: 00
9281 09:28:14.985677 Done allocating resources.
9282 09:28:14.992208 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9283 09:28:14.992341 Enabling resources...
9284 09:28:14.995888 done.
9285 09:28:14.999349 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9286 09:28:15.002041 Initializing devices...
9287 09:28:15.002153 Root Device init
9288 09:28:15.005470 init hardware done!
9289 09:28:15.005580 0x00000018: ctrlr->caps
9290 09:28:15.008944 52.000 MHz: ctrlr->f_max
9291 09:28:15.012363 0.400 MHz: ctrlr->f_min
9292 09:28:15.012481 0x40ff8080: ctrlr->voltages
9293 09:28:15.015668 sclk: 390625
9294 09:28:15.015816 Bus Width = 1
9295 09:28:15.018744 sclk: 390625
9296 09:28:15.018851 Bus Width = 1
9297 09:28:15.022138 Early init status = 3
9298 09:28:15.025320 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9299 09:28:15.028620 in-header: 03 fc 00 00 01 00 00 00
9300 09:28:15.031789 in-data: 00
9301 09:28:15.035132 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9302 09:28:15.040203 in-header: 03 fd 00 00 00 00 00 00
9303 09:28:15.043394 in-data:
9304 09:28:15.046717 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9305 09:28:15.050665 in-header: 03 fc 00 00 01 00 00 00
9306 09:28:15.054068 in-data: 00
9307 09:28:15.057612 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9308 09:28:15.062863 in-header: 03 fd 00 00 00 00 00 00
9309 09:28:15.066493 in-data:
9310 09:28:15.069596 [SSUSB] Setting up USB HOST controller...
9311 09:28:15.072804 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9312 09:28:15.076584 [SSUSB] phy power-on done.
9313 09:28:15.079662 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9314 09:28:15.086238 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9315 09:28:15.089210 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9316 09:28:15.095916 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9317 09:28:15.102727 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9318 09:28:15.109380 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9319 09:28:15.115821 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9320 09:28:15.122209 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9321 09:28:15.125635 SPM: binary array size = 0x9dc
9322 09:28:15.129110 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9323 09:28:15.135563 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9324 09:28:15.142511 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9325 09:28:15.149232 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9326 09:28:15.151830 configure_display: Starting display init
9327 09:28:15.186383 anx7625_power_on_init: Init interface.
9328 09:28:15.189273 anx7625_disable_pd_protocol: Disabled PD feature.
9329 09:28:15.193089 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9330 09:28:15.220816 anx7625_start_dp_work: Secure OCM version=00
9331 09:28:15.223719 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9332 09:28:15.239040 sp_tx_get_edid_block: EDID Block = 1
9333 09:28:15.341594 Extracted contents:
9334 09:28:15.344740 header: 00 ff ff ff ff ff ff 00
9335 09:28:15.347965 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9336 09:28:15.351257 version: 01 04
9337 09:28:15.354452 basic params: 95 1f 11 78 0a
9338 09:28:15.358113 chroma info: 76 90 94 55 54 90 27 21 50 54
9339 09:28:15.361058 established: 00 00 00
9340 09:28:15.367647 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9341 09:28:15.371162 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9342 09:28:15.377479 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9343 09:28:15.385235 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9344 09:28:15.390716 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9345 09:28:15.393830 extensions: 00
9346 09:28:15.393953 checksum: fb
9347 09:28:15.394047
9348 09:28:15.397421 Manufacturer: IVO Model 57d Serial Number 0
9349 09:28:15.400620 Made week 0 of 2020
9350 09:28:15.403802 EDID version: 1.4
9351 09:28:15.403912 Digital display
9352 09:28:15.407152 6 bits per primary color channel
9353 09:28:15.407261 DisplayPort interface
9354 09:28:15.410550 Maximum image size: 31 cm x 17 cm
9355 09:28:15.413993 Gamma: 220%
9356 09:28:15.414103 Check DPMS levels
9357 09:28:15.420462 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9358 09:28:15.423704 First detailed timing is preferred timing
9359 09:28:15.423858 Established timings supported:
9360 09:28:15.426816 Standard timings supported:
9361 09:28:15.430358 Detailed timings
9362 09:28:15.433553 Hex of detail: 383680a07038204018303c0035ae10000019
9363 09:28:15.440035 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9364 09:28:15.443575 0780 0798 07c8 0820 hborder 0
9365 09:28:15.446835 0438 043b 0447 0458 vborder 0
9366 09:28:15.450042 -hsync -vsync
9367 09:28:15.450156 Did detailed timing
9368 09:28:15.457041 Hex of detail: 000000000000000000000000000000000000
9369 09:28:15.460040 Manufacturer-specified data, tag 0
9370 09:28:15.463386 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9371 09:28:15.466457 ASCII string: InfoVision
9372 09:28:15.469778 Hex of detail: 000000fe00523134304e574635205248200a
9373 09:28:15.473315 ASCII string: R140NWF5 RH
9374 09:28:15.473407 Checksum
9375 09:28:15.476482 Checksum: 0xfb (valid)
9376 09:28:15.480187 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9377 09:28:15.483054 DSI data_rate: 832800000 bps
9378 09:28:15.489812 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9379 09:28:15.493158 anx7625_parse_edid: pixelclock(138800).
9380 09:28:15.496711 hactive(1920), hsync(48), hfp(24), hbp(88)
9381 09:28:15.499566 vactive(1080), vsync(12), vfp(3), vbp(17)
9382 09:28:15.502850 anx7625_dsi_config: config dsi.
9383 09:28:15.509826 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9384 09:28:15.523573 anx7625_dsi_config: success to config DSI
9385 09:28:15.526563 anx7625_dp_start: MIPI phy setup OK.
9386 09:28:15.530121 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9387 09:28:15.532932 mtk_ddp_mode_set invalid vrefresh 60
9388 09:28:15.536451 main_disp_path_setup
9389 09:28:15.536541 ovl_layer_smi_id_en
9390 09:28:15.539849 ovl_layer_smi_id_en
9391 09:28:15.539935 ccorr_config
9392 09:28:15.540000 aal_config
9393 09:28:15.543218 gamma_config
9394 09:28:15.543301 postmask_config
9395 09:28:15.546372 dither_config
9396 09:28:15.549666 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9397 09:28:15.556692 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9398 09:28:15.559912 Root Device init finished in 553 msecs
9399 09:28:15.562918 CPU_CLUSTER: 0 init
9400 09:28:15.569460 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9401 09:28:15.576781 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9402 09:28:15.576941 APU_MBOX 0x190000b0 = 0x10001
9403 09:28:15.579619 APU_MBOX 0x190001b0 = 0x10001
9404 09:28:15.582966 APU_MBOX 0x190005b0 = 0x10001
9405 09:28:15.586513 APU_MBOX 0x190006b0 = 0x10001
9406 09:28:15.592431 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9407 09:28:15.602726 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9408 09:28:15.615161 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9409 09:28:15.621056 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9410 09:28:15.633126 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9411 09:28:15.641894 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9412 09:28:15.645731 CPU_CLUSTER: 0 init finished in 81 msecs
9413 09:28:15.648556 Devices initialized
9414 09:28:15.651978 Show all devs... After init.
9415 09:28:15.652090 Root Device: enabled 1
9416 09:28:15.655146 CPU_CLUSTER: 0: enabled 1
9417 09:28:15.658662 CPU: 00: enabled 1
9418 09:28:15.662017 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9419 09:28:15.665165 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9420 09:28:15.668193 ELOG: NV offset 0x57f000 size 0x1000
9421 09:28:15.675536 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9422 09:28:15.681490 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9423 09:28:15.685274 ELOG: Event(17) added with size 13 at 2023-10-20 09:28:17 UTC
9424 09:28:15.691455 out: cmd=0x121: 03 db 21 01 00 00 00 00
9425 09:28:15.694936 in-header: 03 a4 00 00 2c 00 00 00
9426 09:28:15.705369 in-data: bb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9427 09:28:15.711427 ELOG: Event(A1) added with size 10 at 2023-10-20 09:28:17 UTC
9428 09:28:15.718106 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9429 09:28:15.725515 ELOG: Event(A0) added with size 9 at 2023-10-20 09:28:17 UTC
9430 09:28:15.728160 elog_add_boot_reason: Logged dev mode boot
9431 09:28:15.734671 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9432 09:28:15.734792 Finalize devices...
9433 09:28:15.737988 Devices finalized
9434 09:28:15.741207 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9435 09:28:15.744268 Writing coreboot table at 0xffe64000
9436 09:28:15.747680 0. 000000000010a000-0000000000113fff: RAMSTAGE
9437 09:28:15.754371 1. 0000000040000000-00000000400fffff: RAM
9438 09:28:15.757785 2. 0000000040100000-000000004032afff: RAMSTAGE
9439 09:28:15.760775 3. 000000004032b000-00000000545fffff: RAM
9440 09:28:15.764238 4. 0000000054600000-000000005465ffff: BL31
9441 09:28:15.767778 5. 0000000054660000-00000000ffe63fff: RAM
9442 09:28:15.774300 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9443 09:28:15.777779 7. 0000000100000000-000000023fffffff: RAM
9444 09:28:15.780693 Passing 5 GPIOs to payload:
9445 09:28:15.783797 NAME | PORT | POLARITY | VALUE
9446 09:28:15.790682 EC in RW | 0x000000aa | low | undefined
9447 09:28:15.794028 EC interrupt | 0x00000005 | low | undefined
9448 09:28:15.797489 TPM interrupt | 0x000000ab | high | undefined
9449 09:28:15.803929 SD card detect | 0x00000011 | high | undefined
9450 09:28:15.807109 speaker enable | 0x00000093 | high | undefined
9451 09:28:15.810150 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9452 09:28:15.813744 in-header: 03 f9 00 00 02 00 00 00
9453 09:28:15.816933 in-data: 02 00
9454 09:28:15.820150 ADC[4]: Raw value=901552 ID=7
9455 09:28:15.823858 ADC[3]: Raw value=212912 ID=1
9456 09:28:15.823956 RAM Code: 0x71
9457 09:28:15.827082 ADC[6]: Raw value=75036 ID=0
9458 09:28:15.830150 ADC[5]: Raw value=212543 ID=1
9459 09:28:15.830241 SKU Code: 0x1
9460 09:28:15.836869 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9461 09:28:15.836977 coreboot table: 964 bytes.
9462 09:28:15.840161 IMD ROOT 0. 0xfffff000 0x00001000
9463 09:28:15.843643 IMD SMALL 1. 0xffffe000 0x00001000
9464 09:28:15.846597 RO MCACHE 2. 0xffffc000 0x00001104
9465 09:28:15.849933 CONSOLE 3. 0xfff7c000 0x00080000
9466 09:28:15.853591 FMAP 4. 0xfff7b000 0x00000452
9467 09:28:15.856910 TIME STAMP 5. 0xfff7a000 0x00000910
9468 09:28:15.859651 VBOOT WORK 6. 0xfff66000 0x00014000
9469 09:28:15.863276 RAMOOPS 7. 0xffe66000 0x00100000
9470 09:28:15.866661 COREBOOT 8. 0xffe64000 0x00002000
9471 09:28:15.869977 IMD small region:
9472 09:28:15.873108 IMD ROOT 0. 0xffffec00 0x00000400
9473 09:28:15.876373 VPD 1. 0xffffeb80 0x0000006c
9474 09:28:15.879978 MMC STATUS 2. 0xffffeb60 0x00000004
9475 09:28:15.886065 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9476 09:28:15.886175 Probing TPM: done!
9477 09:28:15.893218 Connected to device vid:did:rid of 1ae0:0028:00
9478 09:28:15.899626 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9479 09:28:15.902935 Initialized TPM device CR50 revision 0
9480 09:28:15.906714 Checking cr50 for pending updates
9481 09:28:15.911713 Reading cr50 TPM mode
9482 09:28:15.920609 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9483 09:28:15.927145 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9484 09:28:15.967272 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9485 09:28:15.970487 Checking segment from ROM address 0x40100000
9486 09:28:15.973946 Checking segment from ROM address 0x4010001c
9487 09:28:15.980547 Loading segment from ROM address 0x40100000
9488 09:28:15.980660 code (compression=0)
9489 09:28:15.990365 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9490 09:28:15.996852 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9491 09:28:15.996975 it's not compressed!
9492 09:28:16.003694 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9493 09:28:16.009814 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9494 09:28:16.027411 Loading segment from ROM address 0x4010001c
9495 09:28:16.027559 Entry Point 0x80000000
9496 09:28:16.031250 Loaded segments
9497 09:28:16.034327 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9498 09:28:16.040817 Jumping to boot code at 0x80000000(0xffe64000)
9499 09:28:16.047705 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9500 09:28:16.054011 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9501 09:28:16.061952 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9502 09:28:16.065442 Checking segment from ROM address 0x40100000
9503 09:28:16.068893 Checking segment from ROM address 0x4010001c
9504 09:28:16.076207 Loading segment from ROM address 0x40100000
9505 09:28:16.076357 code (compression=1)
9506 09:28:16.081923 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9507 09:28:16.092192 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9508 09:28:16.092363 using LZMA
9509 09:28:16.100470 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9510 09:28:16.106880 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9511 09:28:16.110523 Loading segment from ROM address 0x4010001c
9512 09:28:16.110648 Entry Point 0x54601000
9513 09:28:16.113626 Loaded segments
9514 09:28:16.116922 NOTICE: MT8192 bl31_setup
9515 09:28:16.124074 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9516 09:28:16.127217 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9517 09:28:16.131491 WARNING: region 0:
9518 09:28:16.134061 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 09:28:16.134175 WARNING: region 1:
9520 09:28:16.140462 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9521 09:28:16.144028 WARNING: region 2:
9522 09:28:16.147065 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9523 09:28:16.150860 WARNING: region 3:
9524 09:28:16.153687 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9525 09:28:16.157039 WARNING: region 4:
9526 09:28:16.163689 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9527 09:28:16.163858 WARNING: region 5:
9528 09:28:16.167814 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 09:28:16.170730 WARNING: region 6:
9530 09:28:16.173935 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 09:28:16.177473 WARNING: region 7:
9532 09:28:16.180233 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 09:28:16.187416 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9534 09:28:16.190396 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9535 09:28:16.193797 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9536 09:28:16.200345 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9537 09:28:16.203973 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9538 09:28:16.207305 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9539 09:28:16.213781 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9540 09:28:16.216863 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9541 09:28:16.223513 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9542 09:28:16.226777 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9543 09:28:16.230277 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9544 09:28:16.236759 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9545 09:28:16.240596 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9546 09:28:16.243546 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9547 09:28:16.250247 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9548 09:28:16.253516 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9549 09:28:16.260118 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9550 09:28:16.263265 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9551 09:28:16.266798 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9552 09:28:16.273993 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9553 09:28:16.276632 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9554 09:28:16.283560 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9555 09:28:16.286954 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9556 09:28:16.290136 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9557 09:28:16.296873 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9558 09:28:16.299864 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9559 09:28:16.306371 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9560 09:28:16.310356 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9561 09:28:16.313149 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9562 09:28:16.320053 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9563 09:28:16.322949 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9564 09:28:16.329909 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9565 09:28:16.332985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9566 09:28:16.336862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9567 09:28:16.339678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9568 09:28:16.346218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9569 09:28:16.349650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9570 09:28:16.352779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9571 09:28:16.356141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9572 09:28:16.363075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9573 09:28:16.366269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9574 09:28:16.369683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9575 09:28:16.372878 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9576 09:28:16.380021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9577 09:28:16.383244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9578 09:28:16.385885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9579 09:28:16.389501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9580 09:28:16.396245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9581 09:28:16.399600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9582 09:28:16.406264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9583 09:28:16.409131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9584 09:28:16.412312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9585 09:28:16.419444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9586 09:28:16.423158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9587 09:28:16.429535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9588 09:28:16.432482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9589 09:28:16.439333 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9590 09:28:16.442706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9591 09:28:16.446058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9592 09:28:16.452466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9593 09:28:16.456184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9594 09:28:16.462902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9595 09:28:16.466439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9596 09:28:16.472492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9597 09:28:16.475966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9598 09:28:16.482480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9599 09:28:16.486030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9600 09:28:16.489273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9601 09:28:16.496044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9602 09:28:16.498981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9603 09:28:16.506144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9604 09:28:16.509274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9605 09:28:16.512338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9606 09:28:16.519137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9607 09:28:16.522472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9608 09:28:16.529085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9609 09:28:16.532291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9610 09:28:16.539498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9611 09:28:16.542421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9612 09:28:16.549076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9613 09:28:16.552508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9614 09:28:16.555863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9615 09:28:16.562738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9616 09:28:16.565780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9617 09:28:16.572183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9618 09:28:16.575462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9619 09:28:16.582570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9620 09:28:16.585744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9621 09:28:16.591865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9622 09:28:16.595570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9623 09:28:16.598530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9624 09:28:16.605343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9625 09:28:16.608514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9626 09:28:16.615166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9627 09:28:16.618666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9628 09:28:16.625309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9629 09:28:16.628927 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9630 09:28:16.631761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9631 09:28:16.635329 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9632 09:28:16.642046 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9633 09:28:16.645285 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9634 09:28:16.648142 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9635 09:28:16.655043 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9636 09:28:16.658079 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9637 09:28:16.664688 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9638 09:28:16.668099 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9639 09:28:16.671544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9640 09:28:16.678938 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9641 09:28:16.681525 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9642 09:28:16.688253 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9643 09:28:16.691720 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9644 09:28:16.694687 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9645 09:28:16.701404 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9646 09:28:16.704506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9647 09:28:16.711436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9648 09:28:16.714515 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9649 09:28:16.718149 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9650 09:28:16.724426 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9651 09:28:16.727935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9652 09:28:16.731460 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9653 09:28:16.734250 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9654 09:28:16.741815 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9655 09:28:16.744564 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9656 09:28:16.747814 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9657 09:28:16.754174 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9658 09:28:16.757710 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9659 09:28:16.760929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9660 09:28:16.767811 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9661 09:28:16.770929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9662 09:28:16.777592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9663 09:28:16.780930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9664 09:28:16.784322 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9665 09:28:16.790969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9666 09:28:16.794382 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9667 09:28:16.801042 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9668 09:28:16.803815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9669 09:28:16.807621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9670 09:28:16.814032 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9671 09:28:16.817683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9672 09:28:16.820549 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9673 09:28:16.827319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9674 09:28:16.831902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9675 09:28:16.837148 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9676 09:28:16.840849 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9677 09:28:16.844262 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9678 09:28:16.850549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9679 09:28:16.854018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9680 09:28:16.860734 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9681 09:28:16.863565 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9682 09:28:16.867132 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9683 09:28:16.873963 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9684 09:28:16.876831 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9685 09:28:16.883831 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9686 09:28:16.887020 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9687 09:28:16.890151 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9688 09:28:16.896708 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9689 09:28:16.900301 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9690 09:28:16.907281 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9691 09:28:16.910107 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9692 09:28:16.913267 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9693 09:28:16.920492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9694 09:28:16.923575 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9695 09:28:16.930263 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9696 09:28:16.933540 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9697 09:28:16.936774 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9698 09:28:16.943817 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9699 09:28:16.946256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9700 09:28:16.949868 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9701 09:28:16.956146 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9702 09:28:16.959539 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9703 09:28:16.966096 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9704 09:28:16.969471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9705 09:28:16.972833 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9706 09:28:16.979361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9707 09:28:16.982786 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9708 09:28:16.989820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9709 09:28:16.992423 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9710 09:28:16.998980 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9711 09:28:17.002239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9712 09:28:17.005551 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9713 09:28:17.012470 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9714 09:28:17.015644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9715 09:28:17.022508 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9716 09:28:17.025621 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9717 09:28:17.028649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9718 09:28:17.035205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9719 09:28:17.038724 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9720 09:28:17.046048 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9721 09:28:17.049030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9722 09:28:17.052102 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9723 09:28:17.058322 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9724 09:28:17.061788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9725 09:28:17.068507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9726 09:28:17.071743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9727 09:28:17.078560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9728 09:28:17.081250 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9729 09:28:17.084906 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9730 09:28:17.091700 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9731 09:28:17.095014 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9732 09:28:17.101853 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9733 09:28:17.104633 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9734 09:28:17.108122 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9735 09:28:17.114660 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9736 09:28:17.117783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9737 09:28:17.124268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9738 09:28:17.127652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9739 09:28:17.134141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9740 09:28:17.137476 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9741 09:28:17.144237 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9742 09:28:17.147700 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9743 09:28:17.150798 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9744 09:28:17.157627 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9745 09:28:17.161155 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9746 09:28:17.167531 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9747 09:28:17.170755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9748 09:28:17.173754 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9749 09:28:17.180836 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9750 09:28:17.183833 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9751 09:28:17.190448 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9752 09:28:17.194053 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9753 09:28:17.200624 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9754 09:28:17.203742 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9755 09:28:17.207229 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9756 09:28:17.213428 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9757 09:28:17.216748 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9758 09:28:17.223731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9759 09:28:17.227156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9760 09:28:17.233412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9761 09:28:17.236660 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9762 09:28:17.239915 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9763 09:28:17.243694 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9764 09:28:17.249914 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9765 09:28:17.253175 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9766 09:28:17.256546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9767 09:28:17.260391 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9768 09:28:17.266821 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9769 09:28:17.270124 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9770 09:28:17.276370 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9771 09:28:17.279890 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9772 09:28:17.282918 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9773 09:28:17.289518 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9774 09:28:17.292773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9775 09:28:17.299541 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9776 09:28:17.302599 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9777 09:28:17.306376 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9778 09:28:17.312521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9779 09:28:17.315653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9780 09:28:17.319104 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9781 09:28:17.325526 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9782 09:28:17.329068 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9783 09:28:17.332379 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9784 09:28:17.339362 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9785 09:28:17.341977 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9786 09:28:17.349032 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9787 09:28:17.352208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9788 09:28:17.355470 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9789 09:28:17.362168 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9790 09:28:17.365521 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9791 09:28:17.368881 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9792 09:28:17.375526 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9793 09:28:17.378815 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9794 09:28:17.385115 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9795 09:28:17.389000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9796 09:28:17.392128 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9797 09:28:17.398374 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9798 09:28:17.402044 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9799 09:28:17.404921 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9800 09:28:17.411812 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9801 09:28:17.414704 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9802 09:28:17.418241 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9803 09:28:17.424644 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9804 09:28:17.428017 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9805 09:28:17.431505 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9806 09:28:17.434661 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9807 09:28:17.441563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9808 09:28:17.444580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9809 09:28:17.447895 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9810 09:28:17.451238 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9811 09:28:17.457988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9812 09:28:17.461253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9813 09:28:17.464530 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9814 09:28:17.467445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9815 09:28:17.474209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9816 09:28:17.477990 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9817 09:28:17.484400 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9818 09:28:17.487336 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9819 09:28:17.494239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9820 09:28:17.497316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9821 09:28:17.504232 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9822 09:28:17.507175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9823 09:28:17.510894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9824 09:28:17.517444 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9825 09:28:17.520172 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9826 09:28:17.527288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9827 09:28:17.530334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9828 09:28:17.533901 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9829 09:28:17.540010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9830 09:28:17.543910 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9831 09:28:17.549850 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9832 09:28:17.553175 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9833 09:28:17.556401 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9834 09:28:17.563522 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9835 09:28:17.566971 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9836 09:28:17.573546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9837 09:28:17.576410 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9838 09:28:17.580183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9839 09:28:17.586769 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9840 09:28:17.589919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9841 09:28:17.596600 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9842 09:28:17.599753 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9843 09:28:17.606264 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9844 09:28:17.609661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9845 09:28:17.616001 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9846 09:28:17.619762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9847 09:28:17.622764 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9848 09:28:17.629472 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9849 09:28:17.633130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9850 09:28:17.639184 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9851 09:28:17.642822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9852 09:28:17.645762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9853 09:28:17.652545 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9854 09:28:17.655940 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9855 09:28:17.662717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9856 09:28:17.666069 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9857 09:28:17.669222 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9858 09:28:17.675566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9859 09:28:17.678936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9860 09:28:17.685439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9861 09:28:17.689169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9862 09:28:17.692166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9863 09:28:17.699171 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9864 09:28:17.702017 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9865 09:28:17.708858 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9866 09:28:17.712050 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9867 09:28:17.718534 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9868 09:28:17.721982 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9869 09:28:17.725316 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9870 09:28:17.731852 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9871 09:28:17.734994 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9872 09:28:17.742081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9873 09:28:17.744982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9874 09:28:17.748508 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9875 09:28:17.755064 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9876 09:28:17.758440 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9877 09:28:17.764669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9878 09:28:17.768409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9879 09:28:17.771403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9880 09:28:17.778483 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9881 09:28:17.781644 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9882 09:28:17.788108 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9883 09:28:17.791418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9884 09:28:17.798017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9885 09:28:17.801522 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9886 09:28:17.804505 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9887 09:28:17.810886 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9888 09:28:17.814142 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9889 09:28:17.821085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9890 09:28:17.824044 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9891 09:28:17.830512 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9892 09:28:17.834224 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9893 09:28:17.840385 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9894 09:28:17.843810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9895 09:28:17.847065 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9896 09:28:17.854885 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9897 09:28:17.857301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9898 09:28:17.864183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9899 09:28:17.867132 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9900 09:28:17.873509 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9901 09:28:17.877324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9902 09:28:17.883535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9903 09:28:17.886820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9904 09:28:17.889898 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9905 09:28:17.896619 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9906 09:28:17.899969 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9907 09:28:17.907035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9908 09:28:17.910000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9909 09:28:17.917061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9910 09:28:17.920043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9911 09:28:17.923496 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9912 09:28:17.930431 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9913 09:28:17.933110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9914 09:28:17.940052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9915 09:28:17.943249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9916 09:28:17.949868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9917 09:28:17.952793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9918 09:28:17.959428 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9919 09:28:17.963020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9920 09:28:17.966248 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9921 09:28:17.973238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9922 09:28:17.975902 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9923 09:28:17.982941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9924 09:28:17.986437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9925 09:28:17.993372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9926 09:28:17.995979 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9927 09:28:18.002472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9928 09:28:18.005849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9929 09:28:18.009346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9930 09:28:18.015373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9931 09:28:18.018756 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9932 09:28:18.025761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9933 09:28:18.029666 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9934 09:28:18.035195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9935 09:28:18.038621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9936 09:28:18.042230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9937 09:28:18.048683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9938 09:28:18.051880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9939 09:28:18.058638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9940 09:28:18.061643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9941 09:28:18.068542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9942 09:28:18.071510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9943 09:28:18.078766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9944 09:28:18.081553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9945 09:28:18.088135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9946 09:28:18.091573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9947 09:28:18.098126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9948 09:28:18.101653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9949 09:28:18.107901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9950 09:28:18.111329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9951 09:28:18.118060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9952 09:28:18.120918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9953 09:28:18.127801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9954 09:28:18.131031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9955 09:28:18.137751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9956 09:28:18.140861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9957 09:28:18.147145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9958 09:28:18.150840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9959 09:28:18.157082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9960 09:28:18.160416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9961 09:28:18.167493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9962 09:28:18.170422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9963 09:28:18.176983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9964 09:28:18.180166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9965 09:28:18.187095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9966 09:28:18.190723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9967 09:28:18.197283 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9968 09:28:18.197368 INFO: [APUAPC] vio 0
9969 09:28:18.204090 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9970 09:28:18.207392 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9971 09:28:18.211111 INFO: [APUAPC] D0_APC_0: 0x400510
9972 09:28:18.213957 INFO: [APUAPC] D0_APC_1: 0x0
9973 09:28:18.217030 INFO: [APUAPC] D0_APC_2: 0x1540
9974 09:28:18.220952 INFO: [APUAPC] D0_APC_3: 0x0
9975 09:28:18.223932 INFO: [APUAPC] D1_APC_0: 0xffffffff
9976 09:28:18.227090 INFO: [APUAPC] D1_APC_1: 0xffffffff
9977 09:28:18.230167 INFO: [APUAPC] D1_APC_2: 0x3fffff
9978 09:28:18.233556 INFO: [APUAPC] D1_APC_3: 0x0
9979 09:28:18.236978 INFO: [APUAPC] D2_APC_0: 0xffffffff
9980 09:28:18.240292 INFO: [APUAPC] D2_APC_1: 0xffffffff
9981 09:28:18.243272 INFO: [APUAPC] D2_APC_2: 0x3fffff
9982 09:28:18.246576 INFO: [APUAPC] D2_APC_3: 0x0
9983 09:28:18.250623 INFO: [APUAPC] D3_APC_0: 0xffffffff
9984 09:28:18.253220 INFO: [APUAPC] D3_APC_1: 0xffffffff
9985 09:28:18.256603 INFO: [APUAPC] D3_APC_2: 0x3fffff
9986 09:28:18.259917 INFO: [APUAPC] D3_APC_3: 0x0
9987 09:28:18.263208 INFO: [APUAPC] D4_APC_0: 0xffffffff
9988 09:28:18.266802 INFO: [APUAPC] D4_APC_1: 0xffffffff
9989 09:28:18.269760 INFO: [APUAPC] D4_APC_2: 0x3fffff
9990 09:28:18.273018 INFO: [APUAPC] D4_APC_3: 0x0
9991 09:28:18.276274 INFO: [APUAPC] D5_APC_0: 0xffffffff
9992 09:28:18.279428 INFO: [APUAPC] D5_APC_1: 0xffffffff
9993 09:28:18.282819 INFO: [APUAPC] D5_APC_2: 0x3fffff
9994 09:28:18.286244 INFO: [APUAPC] D5_APC_3: 0x0
9995 09:28:18.289983 INFO: [APUAPC] D6_APC_0: 0xffffffff
9996 09:28:18.293261 INFO: [APUAPC] D6_APC_1: 0xffffffff
9997 09:28:18.295974 INFO: [APUAPC] D6_APC_2: 0x3fffff
9998 09:28:18.296057 INFO: [APUAPC] D6_APC_3: 0x0
9999 09:28:18.303071 INFO: [APUAPC] D7_APC_0: 0xffffffff
10000 09:28:18.306353 INFO: [APUAPC] D7_APC_1: 0xffffffff
10001 09:28:18.309325 INFO: [APUAPC] D7_APC_2: 0x3fffff
10002 09:28:18.309407 INFO: [APUAPC] D7_APC_3: 0x0
10003 09:28:18.312570 INFO: [APUAPC] D8_APC_0: 0xffffffff
10004 09:28:18.318970 INFO: [APUAPC] D8_APC_1: 0xffffffff
10005 09:28:18.322368 INFO: [APUAPC] D8_APC_2: 0x3fffff
10006 09:28:18.322449 INFO: [APUAPC] D8_APC_3: 0x0
10007 09:28:18.325491 INFO: [APUAPC] D9_APC_0: 0xffffffff
10008 09:28:18.329668 INFO: [APUAPC] D9_APC_1: 0xffffffff
10009 09:28:18.332754 INFO: [APUAPC] D9_APC_2: 0x3fffff
10010 09:28:18.335907 INFO: [APUAPC] D9_APC_3: 0x0
10011 09:28:18.339026 INFO: [APUAPC] D10_APC_0: 0xffffffff
10012 09:28:18.342530 INFO: [APUAPC] D10_APC_1: 0xffffffff
10013 09:28:18.348923 INFO: [APUAPC] D10_APC_2: 0x3fffff
10014 09:28:18.349006 INFO: [APUAPC] D10_APC_3: 0x0
10015 09:28:18.352098 INFO: [APUAPC] D11_APC_0: 0xffffffff
10016 09:28:18.358725 INFO: [APUAPC] D11_APC_1: 0xffffffff
10017 09:28:18.361807 INFO: [APUAPC] D11_APC_2: 0x3fffff
10018 09:28:18.361889 INFO: [APUAPC] D11_APC_3: 0x0
10019 09:28:18.368428 INFO: [APUAPC] D12_APC_0: 0xffffffff
10020 09:28:18.371692 INFO: [APUAPC] D12_APC_1: 0xffffffff
10021 09:28:18.375469 INFO: [APUAPC] D12_APC_2: 0x3fffff
10022 09:28:18.378965 INFO: [APUAPC] D12_APC_3: 0x0
10023 09:28:18.381673 INFO: [APUAPC] D13_APC_0: 0xffffffff
10024 09:28:18.385173 INFO: [APUAPC] D13_APC_1: 0xffffffff
10025 09:28:18.388542 INFO: [APUAPC] D13_APC_2: 0x3fffff
10026 09:28:18.391662 INFO: [APUAPC] D13_APC_3: 0x0
10027 09:28:18.394908 INFO: [APUAPC] D14_APC_0: 0xffffffff
10028 09:28:18.398292 INFO: [APUAPC] D14_APC_1: 0xffffffff
10029 09:28:18.401670 INFO: [APUAPC] D14_APC_2: 0x3fffff
10030 09:28:18.404859 INFO: [APUAPC] D14_APC_3: 0x0
10031 09:28:18.408150 INFO: [APUAPC] D15_APC_0: 0xffffffff
10032 09:28:18.411670 INFO: [APUAPC] D15_APC_1: 0xffffffff
10033 09:28:18.414788 INFO: [APUAPC] D15_APC_2: 0x3fffff
10034 09:28:18.418282 INFO: [APUAPC] D15_APC_3: 0x0
10035 09:28:18.418364 INFO: [APUAPC] APC_CON: 0x4
10036 09:28:18.421985 INFO: [NOCDAPC] D0_APC_0: 0x0
10037 09:28:18.424776 INFO: [NOCDAPC] D0_APC_1: 0x0
10038 09:28:18.428030 INFO: [NOCDAPC] D1_APC_0: 0x0
10039 09:28:18.431436 INFO: [NOCDAPC] D1_APC_1: 0xfff
10040 09:28:18.434527 INFO: [NOCDAPC] D2_APC_0: 0x0
10041 09:28:18.438032 INFO: [NOCDAPC] D2_APC_1: 0xfff
10042 09:28:18.441334 INFO: [NOCDAPC] D3_APC_0: 0x0
10043 09:28:18.444550 INFO: [NOCDAPC] D3_APC_1: 0xfff
10044 09:28:18.447838 INFO: [NOCDAPC] D4_APC_0: 0x0
10045 09:28:18.451568 INFO: [NOCDAPC] D4_APC_1: 0xfff
10046 09:28:18.451680 INFO: [NOCDAPC] D5_APC_0: 0x0
10047 09:28:18.454292 INFO: [NOCDAPC] D5_APC_1: 0xfff
10048 09:28:18.458054 INFO: [NOCDAPC] D6_APC_0: 0x0
10049 09:28:18.461088 INFO: [NOCDAPC] D6_APC_1: 0xfff
10050 09:28:18.464216 INFO: [NOCDAPC] D7_APC_0: 0x0
10051 09:28:18.467339 INFO: [NOCDAPC] D7_APC_1: 0xfff
10052 09:28:18.470721 INFO: [NOCDAPC] D8_APC_0: 0x0
10053 09:28:18.474859 INFO: [NOCDAPC] D8_APC_1: 0xfff
10054 09:28:18.477391 INFO: [NOCDAPC] D9_APC_0: 0x0
10055 09:28:18.481029 INFO: [NOCDAPC] D9_APC_1: 0xfff
10056 09:28:18.484259 INFO: [NOCDAPC] D10_APC_0: 0x0
10057 09:28:18.487853 INFO: [NOCDAPC] D10_APC_1: 0xfff
10058 09:28:18.487937 INFO: [NOCDAPC] D11_APC_0: 0x0
10059 09:28:18.490509 INFO: [NOCDAPC] D11_APC_1: 0xfff
10060 09:28:18.494199 INFO: [NOCDAPC] D12_APC_0: 0x0
10061 09:28:18.497155 INFO: [NOCDAPC] D12_APC_1: 0xfff
10062 09:28:18.500763 INFO: [NOCDAPC] D13_APC_0: 0x0
10063 09:28:18.504114 INFO: [NOCDAPC] D13_APC_1: 0xfff
10064 09:28:18.507421 INFO: [NOCDAPC] D14_APC_0: 0x0
10065 09:28:18.510403 INFO: [NOCDAPC] D14_APC_1: 0xfff
10066 09:28:18.514087 INFO: [NOCDAPC] D15_APC_0: 0x0
10067 09:28:18.517401 INFO: [NOCDAPC] D15_APC_1: 0xfff
10068 09:28:18.520530 INFO: [NOCDAPC] APC_CON: 0x4
10069 09:28:18.524124 INFO: [APUAPC] set_apusys_apc done
10070 09:28:18.526885 INFO: [DEVAPC] devapc_init done
10071 09:28:18.530783 INFO: GICv3 without legacy support detected.
10072 09:28:18.533736 INFO: ARM GICv3 driver initialized in EL3
10073 09:28:18.537326 INFO: Maximum SPI INTID supported: 639
10074 09:28:18.543659 INFO: BL31: Initializing runtime services
10075 09:28:18.546877 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10076 09:28:18.550478 INFO: SPM: enable CPC mode
10077 09:28:18.556950 INFO: mcdi ready for mcusys-off-idle and system suspend
10078 09:28:18.560070 INFO: BL31: Preparing for EL3 exit to normal world
10079 09:28:18.563451 INFO: Entry point address = 0x80000000
10080 09:28:18.566663 INFO: SPSR = 0x8
10081 09:28:18.572384
10082 09:28:18.572468
10083 09:28:18.572533
10084 09:28:18.575341 Starting depthcharge on Spherion...
10085 09:28:18.575423
10086 09:28:18.575489 Wipe memory regions:
10087 09:28:18.575549
10088 09:28:18.576200 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10089 09:28:18.576303 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10090 09:28:18.576387 Setting prompt string to ['asurada:']
10091 09:28:18.576469 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10092 09:28:18.578305 [0x00000040000000, 0x00000054600000)
10093 09:28:18.700959
10094 09:28:18.701119 [0x00000054660000, 0x00000080000000)
10095 09:28:18.961944
10096 09:28:18.962103 [0x000000821a7280, 0x000000ffe64000)
10097 09:28:19.706589
10098 09:28:19.706730 [0x00000100000000, 0x00000240000000)
10099 09:28:21.596577
10100 09:28:21.599993 Initializing XHCI USB controller at 0x11200000.
10101 09:28:22.581662
10102 09:28:22.581854 R8152: Initializing
10103 09:28:22.581966
10104 09:28:22.584424 Version 9 (ocp_data = 6010)
10105 09:28:22.584539
10106 09:28:22.587542 R8152: Done initializing
10107 09:28:22.587653
10108 09:28:22.587765 Adding net device
10109 09:28:23.110130
10110 09:28:23.113402 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10111 09:28:23.113793
10112 09:28:23.114134
10113 09:28:23.114430
10114 09:28:23.115211 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 09:28:23.216501 asurada: tftpboot 192.168.201.1 11826806/tftp-deploy-u1ub0oxe/kernel/image.itb 11826806/tftp-deploy-u1ub0oxe/kernel/cmdline
10117 09:28:23.217116 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 09:28:23.217586 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10119 09:28:23.221899 tftpboot 192.168.201.1 11826806/tftp-deploy-u1ub0oxe/kernel/image.itp-deploy-u1ub0oxe/kernel/cmdline
10120 09:28:23.222427
10121 09:28:23.222767 Waiting for link
10122 09:28:23.424664
10123 09:28:23.425191 done.
10124 09:28:23.425528
10125 09:28:23.425838 MAC: f4:f5:e8:50:de:0a
10126 09:28:23.426137
10127 09:28:23.427716 Sending DHCP discover... done.
10128 09:28:23.428166
10129 09:28:23.430571 Waiting for reply... done.
10130 09:28:23.430987
10131 09:28:23.434075 Sending DHCP request... done.
10132 09:28:23.434492
10133 09:28:23.438866 Waiting for reply... done.
10134 09:28:23.439381
10135 09:28:23.439717 My ip is 192.168.201.14
10136 09:28:23.440106
10137 09:28:23.442204 The DHCP server ip is 192.168.201.1
10138 09:28:23.442618
10139 09:28:23.449014 TFTP server IP predefined by user: 192.168.201.1
10140 09:28:23.449514
10141 09:28:23.455642 Bootfile predefined by user: 11826806/tftp-deploy-u1ub0oxe/kernel/image.itb
10142 09:28:23.456102
10143 09:28:23.458639 Sending tftp read request... done.
10144 09:28:23.459148
10145 09:28:23.465265 Waiting for the transfer...
10146 09:28:23.465803
10147 09:28:23.836243 00000000 ################################################################
10148 09:28:23.836796
10149 09:28:24.163399 00080000 ################################################################
10150 09:28:24.163539
10151 09:28:24.415948 00100000 ################################################################
10152 09:28:24.416089
10153 09:28:24.643414 00180000 ################################################################
10154 09:28:24.643558
10155 09:28:24.869561 00200000 ################################################################
10156 09:28:24.869701
10157 09:28:25.094994 00280000 ################################################################
10158 09:28:25.095141
10159 09:28:25.328591 00300000 ################################################################
10160 09:28:25.328738
10161 09:28:25.600284 00380000 ################################################################
10162 09:28:25.600427
10163 09:28:25.871019 00400000 ################################################################
10164 09:28:25.871160
10165 09:28:26.142889 00480000 ################################################################
10166 09:28:26.143032
10167 09:28:26.384705 00500000 ################################################################
10168 09:28:26.384851
10169 09:28:26.611830 00580000 ################################################################
10170 09:28:26.611965
10171 09:28:26.857049 00600000 ################################################################
10172 09:28:26.857196
10173 09:28:27.125869 00680000 ################################################################
10174 09:28:27.126011
10175 09:28:27.395803 00700000 ################################################################
10176 09:28:27.395950
10177 09:28:27.650708 00780000 ################################################################
10178 09:28:27.650844
10179 09:28:27.890601 00800000 ################################################################
10180 09:28:27.890761
10181 09:28:28.132890 00880000 ################################################################
10182 09:28:28.133023
10183 09:28:28.360022 00900000 ################################################################
10184 09:28:28.360156
10185 09:28:28.596306 00980000 ################################################################
10186 09:28:28.596464
10187 09:28:28.863017 00a00000 ################################################################
10188 09:28:28.863151
10189 09:28:29.103480 00a80000 ################################################################
10190 09:28:29.103616
10191 09:28:29.362316 00b00000 ################################################################
10192 09:28:29.362451
10193 09:28:29.603267 00b80000 ################################################################
10194 09:28:29.603403
10195 09:28:29.832481 00c00000 ################################################################
10196 09:28:29.832623
10197 09:28:30.065597 00c80000 ################################################################
10198 09:28:30.065737
10199 09:28:30.280392 00d00000 ################################################################
10200 09:28:30.280528
10201 09:28:30.497853 00d80000 ################################################################
10202 09:28:30.498022
10203 09:28:30.715237 00e00000 ################################################################
10204 09:28:30.715394
10205 09:28:30.931269 00e80000 ################################################################
10206 09:28:30.931403
10207 09:28:31.155856 00f00000 ################################################################
10208 09:28:31.155993
10209 09:28:31.378269 00f80000 ################################################################
10210 09:28:31.378418
10211 09:28:31.590107 01000000 ################################################################
10212 09:28:31.590283
10213 09:28:31.828229 01080000 ################################################################
10214 09:28:31.828377
10215 09:28:32.078959 01100000 ################################################################
10216 09:28:32.079101
10217 09:28:32.320156 01180000 ################################################################
10218 09:28:32.320296
10219 09:28:32.559253 01200000 ################################################################
10220 09:28:32.559394
10221 09:28:32.816680 01280000 ################################################################
10222 09:28:32.816826
10223 09:28:33.084549 01300000 ################################################################
10224 09:28:33.084686
10225 09:28:33.338190 01380000 ################################################################
10226 09:28:33.338334
10227 09:28:33.568080 01400000 ################################################################
10228 09:28:33.568219
10229 09:28:33.799890 01480000 ################################################################
10230 09:28:33.800062
10231 09:28:34.025391 01500000 ################################################################
10232 09:28:34.025539
10233 09:28:34.275945 01580000 ################################################################
10234 09:28:34.276089
10235 09:28:34.527657 01600000 ################################################################
10236 09:28:34.527833
10237 09:28:34.784065 01680000 ################################################################
10238 09:28:34.784212
10239 09:28:35.008027 01700000 ################################################################
10240 09:28:35.008168
10241 09:28:35.264971 01780000 ################################################################
10242 09:28:35.265145
10243 09:28:35.515148 01800000 ################################################################
10244 09:28:35.515282
10245 09:28:35.749234 01880000 ################################################################
10246 09:28:35.749377
10247 09:28:35.998186 01900000 ################################################################
10248 09:28:35.998362
10249 09:28:36.253317 01980000 ################################################################
10250 09:28:36.253459
10251 09:28:36.512481 01a00000 ################################################################
10252 09:28:36.512624
10253 09:28:36.769375 01a80000 ################################################################
10254 09:28:36.769509
10255 09:28:36.991098 01b00000 ################################################################
10256 09:28:36.991265
10257 09:28:37.209577 01b80000 ################################################################
10258 09:28:37.209727
10259 09:28:37.433356 01c00000 ################################################################
10260 09:28:37.433504
10261 09:28:37.655902 01c80000 ################################################################
10262 09:28:37.656043
10263 09:28:37.900426 01d00000 ################################################################
10264 09:28:37.900571
10265 09:28:38.143015 01d80000 ################################################################
10266 09:28:38.143162
10267 09:28:38.388864 01e00000 ################################################################
10268 09:28:38.389011
10269 09:28:38.611683 01e80000 ################################################################
10270 09:28:38.611865
10271 09:28:38.835247 01f00000 ################################################################
10272 09:28:38.835409
10273 09:28:39.058679 01f80000 ################################################################
10274 09:28:39.058821
10275 09:28:39.321330 02000000 ################################################################
10276 09:28:39.321494
10277 09:28:39.585675 02080000 ################################################################
10278 09:28:39.585818
10279 09:28:39.838851 02100000 ################################################################
10280 09:28:39.838999
10281 09:28:40.091947 02180000 ################################################################
10282 09:28:40.092113
10283 09:28:40.358158 02200000 ################################################################
10284 09:28:40.358302
10285 09:28:40.594711 02280000 ################################################################
10286 09:28:40.594847
10287 09:28:40.845200 02300000 ################################################################
10288 09:28:40.845354
10289 09:28:41.085733 02380000 ################################################################
10290 09:28:41.085876
10291 09:28:41.338042 02400000 ################################################################
10292 09:28:41.338183
10293 09:28:41.569274 02480000 ################################################################
10294 09:28:41.569417
10295 09:28:41.814705 02500000 ################################################################
10296 09:28:41.814836
10297 09:28:42.054101 02580000 ################################################################
10298 09:28:42.054235
10299 09:28:42.298596 02600000 ################################################################
10300 09:28:42.298733
10301 09:28:42.523849 02680000 ################################################################
10302 09:28:42.523993
10303 09:28:42.742261 02700000 ################################################################
10304 09:28:42.742397
10305 09:28:42.961598 02780000 ################################################################
10306 09:28:42.961773
10307 09:28:43.180140 02800000 ################################################################
10308 09:28:43.180278
10309 09:28:43.396096 02880000 ################################################################
10310 09:28:43.396261
10311 09:28:43.612243 02900000 ################################################################
10312 09:28:43.612402
10313 09:28:43.830652 02980000 ################################################################
10314 09:28:43.830786
10315 09:28:44.142609 02a00000 ################################################################
10316 09:28:44.142796
10317 09:28:44.284019 02a80000 ################################################################
10318 09:28:44.284167
10319 09:28:44.532514 02b00000 ################################################################
10320 09:28:44.532696
10321 09:28:44.771557 02b80000 ################################################################
10322 09:28:44.771691
10323 09:28:45.006612 02c00000 ################################################################
10324 09:28:45.006743
10325 09:28:45.260151 02c80000 ################################################################
10326 09:28:45.260295
10327 09:28:45.509774 02d00000 ################################################################
10328 09:28:45.509906
10329 09:28:45.751837 02d80000 ################################################################
10330 09:28:45.751974
10331 09:28:45.985540 02e00000 ################################################################
10332 09:28:45.985679
10333 09:28:46.226772 02e80000 ################################################################
10334 09:28:46.226908
10335 09:28:46.479941 02f00000 ################################################################
10336 09:28:46.480078
10337 09:28:46.719877 02f80000 ################################################################
10338 09:28:46.720011
10339 09:28:46.985203 03000000 ################################################################
10340 09:28:46.985340
10341 09:28:47.244553 03080000 ################################################################
10342 09:28:47.244700
10343 09:28:47.515503 03100000 ################################################################
10344 09:28:47.515663
10345 09:28:47.751742 03180000 ################################################################
10346 09:28:47.751887
10347 09:28:47.995648 03200000 ################################################################
10348 09:28:47.995805
10349 09:28:48.238985 03280000 ################################################################
10350 09:28:48.239143
10351 09:28:48.493433 03300000 ################################################################
10352 09:28:48.493566
10353 09:28:48.740378 03380000 ################################################################
10354 09:28:48.740532
10355 09:28:48.969918 03400000 ################################################################
10356 09:28:48.970077
10357 09:28:49.204996 03480000 ################################################################
10358 09:28:49.205155
10359 09:28:49.453968 03500000 ################################################################
10360 09:28:49.454103
10361 09:28:49.690499 03580000 ################################################################
10362 09:28:49.690660
10363 09:28:49.920152 03600000 ################################################################
10364 09:28:49.920324
10365 09:28:50.160164 03680000 ################################################################
10366 09:28:50.160316
10367 09:28:50.399357 03700000 ################################################################
10368 09:28:50.399520
10369 09:28:50.637779 03780000 ################################################################
10370 09:28:50.637924
10371 09:28:50.883285 03800000 ################################################################
10372 09:28:50.883467
10373 09:28:51.117317 03880000 ################################################################
10374 09:28:51.117466
10375 09:28:51.352591 03900000 ################################################################
10376 09:28:51.352740
10377 09:28:51.592906 03980000 ################################################################
10378 09:28:51.593066
10379 09:28:51.821460 03a00000 ################################################################
10380 09:28:51.821602
10381 09:28:52.066196 03a80000 ################################################################
10382 09:28:52.066337
10383 09:28:52.298587 03b00000 ################################################################
10384 09:28:52.298732
10385 09:28:52.537859 03b80000 ################################################################
10386 09:28:52.538045
10387 09:28:52.780585 03c00000 ################################################################
10388 09:28:52.780776
10389 09:28:53.032120 03c80000 ################################################################
10390 09:28:53.032296
10391 09:28:53.269851 03d00000 ################################################################
10392 09:28:53.269993
10393 09:28:53.500708 03d80000 ################################################################
10394 09:28:53.500849
10395 09:28:53.727003 03e00000 ################################################################
10396 09:28:53.727148
10397 09:28:53.954399 03e80000 ################################################################
10398 09:28:53.954540
10399 09:28:54.198705 03f00000 ################################################################
10400 09:28:54.198851
10401 09:28:54.446923 03f80000 ################################################################
10402 09:28:54.447062
10403 09:28:54.688793 04000000 ################################################################
10404 09:28:54.688930
10405 09:28:54.922650 04080000 ################################################################
10406 09:28:54.922797
10407 09:28:55.156101 04100000 ################################################################
10408 09:28:55.156245
10409 09:28:55.403011 04180000 ################################################################
10410 09:28:55.403161
10411 09:28:55.659289 04200000 ################################################################
10412 09:28:55.659438
10413 09:28:55.900558 04280000 ################################################################
10414 09:28:55.900692
10415 09:28:56.154918 04300000 ################################################################
10416 09:28:56.155072
10417 09:28:56.423091 04380000 ################################################################
10418 09:28:56.423242
10419 09:28:56.662877 04400000 ################################################################
10420 09:28:56.663019
10421 09:28:56.904141 04480000 ################################################################
10422 09:28:56.904288
10423 09:28:57.146044 04500000 ################################################################
10424 09:28:57.146194
10425 09:28:57.373235 04580000 ################################################################
10426 09:28:57.373395
10427 09:28:57.601639 04600000 ################################################################
10428 09:28:57.601792
10429 09:28:57.839704 04680000 ################################################################
10430 09:28:57.839859
10431 09:28:58.086976 04700000 ################################################################
10432 09:28:58.087164
10433 09:28:58.328526 04780000 ################################################################
10434 09:28:58.328679
10435 09:28:58.555779 04800000 ################################################################
10436 09:28:58.555969
10437 09:28:58.780504 04880000 ################################################################
10438 09:28:58.780663
10439 09:28:59.006480 04900000 ################################################################
10440 09:28:59.006629
10441 09:28:59.241717 04980000 ################################################################
10442 09:28:59.241879
10443 09:28:59.475314 04a00000 ################################################################
10444 09:28:59.475489
10445 09:28:59.718416 04a80000 ################################################################
10446 09:28:59.718566
10447 09:28:59.943122 04b00000 ################################################################
10448 09:28:59.943304
10449 09:29:00.167555 04b80000 ################################################################
10450 09:29:00.167697
10451 09:29:00.408197 04c00000 ################################################################
10452 09:29:00.408385
10453 09:29:00.659688 04c80000 ################################################################
10454 09:29:00.659855
10455 09:29:00.907454 04d00000 ################################################################
10456 09:29:00.907597
10457 09:29:01.164066 04d80000 ################################################################
10458 09:29:01.164215
10459 09:29:01.415235 04e00000 ################################################################
10460 09:29:01.415407
10461 09:29:01.666604 04e80000 ################################################################
10462 09:29:01.666783
10463 09:29:01.906274 04f00000 ################################################################
10464 09:29:01.906425
10465 09:29:02.139542 04f80000 ################################################################
10466 09:29:02.139758
10467 09:29:02.380098 05000000 ################################################################
10468 09:29:02.380334
10469 09:29:02.623133 05080000 ################################################################
10470 09:29:02.623278
10471 09:29:02.870645 05100000 ################################################################
10472 09:29:02.870820
10473 09:29:03.119038 05180000 ################################################################
10474 09:29:03.119216
10475 09:29:03.351747 05200000 ################################################################
10476 09:29:03.351895
10477 09:29:03.591626 05280000 ################################################################
10478 09:29:03.591790
10479 09:29:03.831127 05300000 ################################################################
10480 09:29:03.831279
10481 09:29:04.068686 05380000 ################################################################
10482 09:29:04.068863
10483 09:29:04.316205 05400000 ################################################################
10484 09:29:04.316375
10485 09:29:04.552776 05480000 ################################################################
10486 09:29:04.552919
10487 09:29:04.784235 05500000 ################################################################
10488 09:29:04.784387
10489 09:29:05.043887 05580000 ################################################################
10490 09:29:05.044030
10491 09:29:05.284759 05600000 ################################################################
10492 09:29:05.284931
10493 09:29:05.517479 05680000 ################################################################
10494 09:29:05.517702
10495 09:29:05.757372 05700000 ################################################################
10496 09:29:05.757552
10497 09:29:05.997327 05780000 ################################################################
10498 09:29:05.997538
10499 09:29:06.243990 05800000 ################################################################
10500 09:29:06.244168
10501 09:29:06.477318 05880000 ################################################################
10502 09:29:06.477494
10503 09:29:06.734042 05900000 ################################################################
10504 09:29:06.734215
10505 09:29:07.044115 05980000 ################################################################
10506 09:29:07.044266
10507 09:29:07.287677 05a00000 ################################################################
10508 09:29:07.287897
10509 09:29:07.516004 05a80000 ################################################################
10510 09:29:07.516180
10511 09:29:07.758247 05b00000 ################################################################
10512 09:29:07.758422
10513 09:29:07.983385 05b80000 ################################################################
10514 09:29:07.983555
10515 09:29:08.228902 05c00000 ################################################################
10516 09:29:08.229049
10517 09:29:08.470695 05c80000 ################################################################
10518 09:29:08.470868
10519 09:29:08.703905 05d00000 ################################################################
10520 09:29:08.704063
10521 09:29:08.956556 05d80000 ################################################################
10522 09:29:08.956694
10523 09:29:09.211801 05e00000 ################################################################
10524 09:29:09.211948
10525 09:29:09.519586 05e80000 ################################################################
10526 09:29:09.519766
10527 09:29:09.846185 05f00000 ################################################################
10528 09:29:09.846361
10529 09:29:10.101216 05f80000 ################################################################
10530 09:29:10.101350
10531 09:29:10.341856 06000000 ################################################################
10532 09:29:10.342018
10533 09:29:10.569752 06080000 ################################################################
10534 09:29:10.569900
10535 09:29:10.796081 06100000 ################################################################
10536 09:29:10.796230
10537 09:29:11.040491 06180000 ################################################################
10538 09:29:11.040678
10539 09:29:11.368659 06200000 ################################################################
10540 09:29:11.368843
10541 09:29:11.697680 06280000 ################################################################
10542 09:29:11.697852
10543 09:29:11.969898 06300000 ################################################################
10544 09:29:11.970045
10545 09:29:12.206279 06380000 ################################################################
10546 09:29:12.206414
10547 09:29:12.465625 06400000 ################################################################
10548 09:29:12.465829
10549 09:29:12.782877 06480000 ################################################################
10550 09:29:12.783067
10551 09:29:13.110021 06500000 ################################################################
10552 09:29:13.110169
10553 09:29:13.389685 06580000 ################################################################
10554 09:29:13.389856
10555 09:29:13.709963 06600000 ################################################################
10556 09:29:13.710103
10557 09:29:14.027018 06680000 ################################################################
10558 09:29:14.027160
10559 09:29:14.341424 06700000 ################################################################
10560 09:29:14.341602
10561 09:29:14.597281 06780000 ################################################################
10562 09:29:14.597429
10563 09:29:14.761511 06800000 ############################################# done.
10564 09:29:14.761683
10565 09:29:14.764631 The bootfile was 109413270 bytes long.
10566 09:29:14.764731
10567 09:29:14.768086 Sending tftp read request... done.
10568 09:29:14.768167
10569 09:29:14.771282 Waiting for the transfer...
10570 09:29:14.771362
10571 09:29:14.771427 00000000 # done.
10572 09:29:14.771490
10573 09:29:14.777569 Command line loaded dynamically from TFTP file: 11826806/tftp-deploy-u1ub0oxe/kernel/cmdline
10574 09:29:14.781243
10575 09:29:14.794510 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10576 09:29:14.794609
10577 09:29:14.794677 Loading FIT.
10578 09:29:14.794740
10579 09:29:14.797945 Image ramdisk-1 has 98319697 bytes.
10580 09:29:14.798028
10581 09:29:14.800670 Image fdt-1 has 47278 bytes.
10582 09:29:14.800750
10583 09:29:14.804191 Image kernel-1 has 11044258 bytes.
10584 09:29:14.804263
10585 09:29:14.810834 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10586 09:29:14.810916
10587 09:29:14.830453 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10588 09:29:14.830549
10589 09:29:14.833850 Choosing best match conf-1 for compat google,spherion-rev2.
10590 09:29:14.838693
10591 09:29:14.842957 Connected to device vid:did:rid of 1ae0:0028:00
10592 09:29:14.850437
10593 09:29:14.853431 tpm_get_response: command 0x17b, return code 0x0
10594 09:29:14.853505
10595 09:29:14.856869 ec_init: CrosEC protocol v3 supported (256, 248)
10596 09:29:14.861302
10597 09:29:14.864249 tpm_cleanup: add release locality here.
10598 09:29:14.864328
10599 09:29:14.864393 Shutting down all USB controllers.
10600 09:29:14.867641
10601 09:29:14.867711 Removing current net device
10602 09:29:14.867824
10603 09:29:14.874182 Exiting depthcharge with code 4 at timestamp: 85752244
10604 09:29:14.874268
10605 09:29:14.877549 LZMA decompressing kernel-1 to 0x821a6718
10606 09:29:14.877627
10607 09:29:14.880913 LZMA decompressing kernel-1 to 0x40000000
10608 09:29:16.270894
10609 09:29:16.271033 jumping to kernel
10610 09:29:16.271612 end: 2.2.4 bootloader-commands (duration 00:00:58) [common]
10611 09:29:16.271732 start: 2.2.5 auto-login-action (timeout 00:03:27) [common]
10612 09:29:16.271813 Setting prompt string to ['Linux version [0-9]']
10613 09:29:16.271893 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10614 09:29:16.271962 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10615 09:29:16.353331
10616 09:29:16.356303 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10617 09:29:16.359883 start: 2.2.5.1 login-action (timeout 00:03:27) [common]
10618 09:29:16.359971 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10619 09:29:16.360050 Setting prompt string to []
10620 09:29:16.360132 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10621 09:29:16.360217 Using line separator: #'\n'#
10622 09:29:16.360276 No login prompt set.
10623 09:29:16.360340 Parsing kernel messages
10624 09:29:16.360405 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10625 09:29:16.360509 [login-action] Waiting for messages, (timeout 00:03:27)
10626 09:29:16.379383 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10627 09:29:16.383109 [ 0.000000] random: crng init done
10628 09:29:16.389634 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10629 09:29:16.392824 [ 0.000000] efi: UEFI not found.
10630 09:29:16.399220 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10631 09:29:16.408987 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10632 09:29:16.415884 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10633 09:29:16.425628 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10634 09:29:16.432564 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10635 09:29:16.438896 [ 0.000000] printk: bootconsole [mtk8250] enabled
10636 09:29:16.445519 [ 0.000000] NUMA: No NUMA configuration found
10637 09:29:16.451970 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10638 09:29:16.458569 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10639 09:29:16.458652 [ 0.000000] Zone ranges:
10640 09:29:16.465094 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10641 09:29:16.468517 [ 0.000000] DMA32 empty
10642 09:29:16.474743 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10643 09:29:16.478238 [ 0.000000] Movable zone start for each node
10644 09:29:16.481350 [ 0.000000] Early memory node ranges
10645 09:29:16.488314 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10646 09:29:16.494634 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10647 09:29:16.501103 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10648 09:29:16.507782 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10649 09:29:16.515031 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10650 09:29:16.521116 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10651 09:29:16.577581 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10652 09:29:16.583953 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10653 09:29:16.590663 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10654 09:29:16.593980 [ 0.000000] psci: probing for conduit method from DT.
10655 09:29:16.600475 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10656 09:29:16.603663 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10657 09:29:16.610590 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10658 09:29:16.613464 [ 0.000000] psci: SMC Calling Convention v1.2
10659 09:29:16.620022 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10660 09:29:16.623273 [ 0.000000] Detected VIPT I-cache on CPU0
10661 09:29:16.630211 [ 0.000000] CPU features: detected: GIC system register CPU interface
10662 09:29:16.637409 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10663 09:29:16.643110 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10664 09:29:16.649564 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10665 09:29:16.659535 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10666 09:29:16.665969 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10667 09:29:16.669597 [ 0.000000] alternatives: applying boot alternatives
10668 09:29:16.676812 [ 0.000000] Fallback order for Node 0: 0
10669 09:29:16.682897 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10670 09:29:16.686367 [ 0.000000] Policy zone: Normal
10671 09:29:16.699565 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10672 09:29:16.709205 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10673 09:29:16.721531 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10674 09:29:16.731601 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10675 09:29:16.737861 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10676 09:29:16.741051 <6>[ 0.000000] software IO TLB: area num 8.
10677 09:29:16.797916 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10678 09:29:16.947597 <6>[ 0.000000] Memory: 7873480K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 479288K reserved, 32768K cma-reserved)
10679 09:29:16.954081 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10680 09:29:16.960324 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10681 09:29:16.963622 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10682 09:29:16.970231 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10683 09:29:16.977039 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10684 09:29:16.979988 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10685 09:29:16.990164 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10686 09:29:16.996688 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10687 09:29:17.003209 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10688 09:29:17.009634 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10689 09:29:17.013059 <6>[ 0.000000] GICv3: 608 SPIs implemented
10690 09:29:17.016780 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10691 09:29:17.023133 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10692 09:29:17.026367 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10693 09:29:17.032833 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10694 09:29:17.045911 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10695 09:29:17.059750 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10696 09:29:17.065818 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10697 09:29:17.074199 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10698 09:29:17.086903 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10699 09:29:17.093578 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10700 09:29:17.100193 <6>[ 0.009177] Console: colour dummy device 80x25
10701 09:29:17.110107 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10702 09:29:17.116829 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10703 09:29:17.120445 <6>[ 0.029239] LSM: Security Framework initializing
10704 09:29:17.126672 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10705 09:29:17.136937 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10706 09:29:17.146506 <6>[ 0.051436] cblist_init_generic: Setting adjustable number of callback queues.
10707 09:29:17.150085 <6>[ 0.058927] cblist_init_generic: Setting shift to 3 and lim to 1.
10708 09:29:17.159682 <6>[ 0.065267] cblist_init_generic: Setting adjustable number of callback queues.
10709 09:29:17.166512 <6>[ 0.072694] cblist_init_generic: Setting shift to 3 and lim to 1.
10710 09:29:17.169399 <6>[ 0.079093] rcu: Hierarchical SRCU implementation.
10711 09:29:17.176159 <6>[ 0.084109] rcu: Max phase no-delay instances is 1000.
10712 09:29:17.183157 <6>[ 0.091170] EFI services will not be available.
10713 09:29:17.186123 <6>[ 0.096125] smp: Bringing up secondary CPUs ...
10714 09:29:17.194650 <6>[ 0.101177] Detected VIPT I-cache on CPU1
10715 09:29:17.201362 <6>[ 0.101245] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10716 09:29:17.207790 <6>[ 0.101276] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10717 09:29:17.211093 <6>[ 0.101610] Detected VIPT I-cache on CPU2
10718 09:29:17.221046 <6>[ 0.101660] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10719 09:29:17.227349 <6>[ 0.101675] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10720 09:29:17.230601 <6>[ 0.101931] Detected VIPT I-cache on CPU3
10721 09:29:17.237426 <6>[ 0.101976] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10722 09:29:17.244445 <6>[ 0.101990] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10723 09:29:17.247645 <6>[ 0.102292] CPU features: detected: Spectre-v4
10724 09:29:17.253885 <6>[ 0.102298] CPU features: detected: Spectre-BHB
10725 09:29:17.257483 <6>[ 0.102303] Detected PIPT I-cache on CPU4
10726 09:29:17.264051 <6>[ 0.102360] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10727 09:29:17.273508 <6>[ 0.102377] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10728 09:29:17.276849 <6>[ 0.102667] Detected PIPT I-cache on CPU5
10729 09:29:17.283655 <6>[ 0.102729] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10730 09:29:17.290155 <6>[ 0.102746] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10731 09:29:17.293271 <6>[ 0.103025] Detected PIPT I-cache on CPU6
10732 09:29:17.303203 <6>[ 0.103089] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10733 09:29:17.309908 <6>[ 0.103105] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10734 09:29:17.313100 <6>[ 0.103403] Detected PIPT I-cache on CPU7
10735 09:29:17.319702 <6>[ 0.103467] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10736 09:29:17.326657 <6>[ 0.103483] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10737 09:29:17.329393 <6>[ 0.103530] smp: Brought up 1 node, 8 CPUs
10738 09:29:17.336281 <6>[ 0.244947] SMP: Total of 8 processors activated.
10739 09:29:17.342663 <6>[ 0.249868] CPU features: detected: 32-bit EL0 Support
10740 09:29:17.349329 <6>[ 0.255264] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10741 09:29:17.356412 <6>[ 0.264119] CPU features: detected: Common not Private translations
10742 09:29:17.362924 <6>[ 0.270594] CPU features: detected: CRC32 instructions
10743 09:29:17.369180 <6>[ 0.275945] CPU features: detected: RCpc load-acquire (LDAPR)
10744 09:29:17.372352 <6>[ 0.281942] CPU features: detected: LSE atomic instructions
10745 09:29:17.379377 <6>[ 0.287724] CPU features: detected: Privileged Access Never
10746 09:29:17.385532 <6>[ 0.293504] CPU features: detected: RAS Extension Support
10747 09:29:17.392574 <6>[ 0.299112] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10748 09:29:17.395644 <6>[ 0.306378] CPU: All CPU(s) started at EL2
10749 09:29:17.402326 <6>[ 0.310694] alternatives: applying system-wide alternatives
10750 09:29:17.413165 <6>[ 0.321401] devtmpfs: initialized
10751 09:29:17.425087 <6>[ 0.330483] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10752 09:29:17.434891 <6>[ 0.340447] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10753 09:29:17.438654 <6>[ 0.348048] pinctrl core: initialized pinctrl subsystem
10754 09:29:17.446097 <6>[ 0.354692] DMI not present or invalid.
10755 09:29:17.452422 <6>[ 0.359097] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10756 09:29:17.459050 <6>[ 0.365947] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10757 09:29:17.469140 <6>[ 0.373533] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10758 09:29:17.475481 <6>[ 0.381742] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10759 09:29:17.482259 <6>[ 0.389985] audit: initializing netlink subsys (disabled)
10760 09:29:17.488896 <5>[ 0.395674] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10761 09:29:17.495083 <6>[ 0.396377] thermal_sys: Registered thermal governor 'step_wise'
10762 09:29:17.501842 <6>[ 0.403642] thermal_sys: Registered thermal governor 'power_allocator'
10763 09:29:17.508294 <6>[ 0.409898] cpuidle: using governor menu
10764 09:29:17.511986 <6>[ 0.420858] NET: Registered PF_QIPCRTR protocol family
10765 09:29:17.518191 <6>[ 0.426336] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10766 09:29:17.525283 <6>[ 0.433442] ASID allocator initialised with 32768 entries
10767 09:29:17.531312 <6>[ 0.440004] Serial: AMBA PL011 UART driver
10768 09:29:17.540108 <4>[ 0.448793] Trying to register duplicate clock ID: 134
10769 09:29:17.594426 <6>[ 0.506592] KASLR enabled
10770 09:29:17.608775 <6>[ 0.514283] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10771 09:29:17.615058 <6>[ 0.521300] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10772 09:29:17.622198 <6>[ 0.527787] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10773 09:29:17.628462 <6>[ 0.534793] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10774 09:29:17.634854 <6>[ 0.541283] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10775 09:29:17.641856 <6>[ 0.548289] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10776 09:29:17.648034 <6>[ 0.554775] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10777 09:29:17.654810 <6>[ 0.561776] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10778 09:29:17.658227 <6>[ 0.569290] ACPI: Interpreter disabled.
10779 09:29:17.666920 <6>[ 0.575716] iommu: Default domain type: Translated
10780 09:29:17.673401 <6>[ 0.580825] iommu: DMA domain TLB invalidation policy: strict mode
10781 09:29:17.677288 <5>[ 0.587480] SCSI subsystem initialized
10782 09:29:17.683407 <6>[ 0.591651] usbcore: registered new interface driver usbfs
10783 09:29:17.689968 <6>[ 0.597383] usbcore: registered new interface driver hub
10784 09:29:17.693208 <6>[ 0.602932] usbcore: registered new device driver usb
10785 09:29:17.699934 <6>[ 0.609037] pps_core: LinuxPPS API ver. 1 registered
10786 09:29:17.709981 <6>[ 0.614231] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10787 09:29:17.713523 <6>[ 0.623581] PTP clock support registered
10788 09:29:17.716438 <6>[ 0.627825] EDAC MC: Ver: 3.0.0
10789 09:29:17.723874 <6>[ 0.632975] FPGA manager framework
10790 09:29:17.730702 <6>[ 0.636651] Advanced Linux Sound Architecture Driver Initialized.
10791 09:29:17.733914 <6>[ 0.643421] vgaarb: loaded
10792 09:29:17.740564 <6>[ 0.646583] clocksource: Switched to clocksource arch_sys_counter
10793 09:29:17.743736 <5>[ 0.653014] VFS: Disk quotas dquot_6.6.0
10794 09:29:17.750712 <6>[ 0.657198] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10795 09:29:17.753929 <6>[ 0.664389] pnp: PnP ACPI: disabled
10796 09:29:17.762321 <6>[ 0.671064] NET: Registered PF_INET protocol family
10797 09:29:17.771897 <6>[ 0.676650] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10798 09:29:17.783789 <6>[ 0.688955] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10799 09:29:17.793030 <6>[ 0.697771] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10800 09:29:17.799753 <6>[ 0.705743] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10801 09:29:17.810212 <6>[ 0.714443] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10802 09:29:17.816598 <6>[ 0.724194] TCP: Hash tables configured (established 65536 bind 65536)
10803 09:29:17.822995 <6>[ 0.731049] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10804 09:29:17.832551 <6>[ 0.738249] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10805 09:29:17.839172 <6>[ 0.745948] NET: Registered PF_UNIX/PF_LOCAL protocol family
10806 09:29:17.845694 <6>[ 0.752121] RPC: Registered named UNIX socket transport module.
10807 09:29:17.848988 <6>[ 0.758276] RPC: Registered udp transport module.
10808 09:29:17.855448 <6>[ 0.763208] RPC: Registered tcp transport module.
10809 09:29:17.862286 <6>[ 0.768140] RPC: Registered tcp NFSv4.1 backchannel transport module.
10810 09:29:17.865570 <6>[ 0.774805] PCI: CLS 0 bytes, default 64
10811 09:29:17.869066 <6>[ 0.779205] Unpacking initramfs...
10812 09:29:17.893080 <6>[ 0.798672] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10813 09:29:17.902946 <6>[ 0.807325] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10814 09:29:17.906137 <6>[ 0.816177] kvm [1]: IPA Size Limit: 40 bits
10815 09:29:17.912707 <6>[ 0.820703] kvm [1]: GICv3: no GICV resource entry
10816 09:29:17.916085 <6>[ 0.825723] kvm [1]: disabling GICv2 emulation
10817 09:29:17.922590 <6>[ 0.830411] kvm [1]: GIC system register CPU interface enabled
10818 09:29:17.926379 <6>[ 0.836576] kvm [1]: vgic interrupt IRQ18
10819 09:29:17.932467 <6>[ 0.840931] kvm [1]: VHE mode initialized successfully
10820 09:29:17.939076 <5>[ 0.847492] Initialise system trusted keyrings
10821 09:29:17.945625 <6>[ 0.852333] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10822 09:29:17.953391 <6>[ 0.862290] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10823 09:29:17.960245 <5>[ 0.868722] NFS: Registering the id_resolver key type
10824 09:29:17.963031 <5>[ 0.874025] Key type id_resolver registered
10825 09:29:17.969625 <5>[ 0.878440] Key type id_legacy registered
10826 09:29:17.976632 <6>[ 0.882721] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10827 09:29:17.982858 <6>[ 0.889640] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10828 09:29:17.989614 <6>[ 0.897351] 9p: Installing v9fs 9p2000 file system support
10829 09:29:18.026891 <5>[ 0.935713] Key type asymmetric registered
10830 09:29:18.029865 <5>[ 0.940044] Asymmetric key parser 'x509' registered
10831 09:29:18.040186 <6>[ 0.945181] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10832 09:29:18.043143 <6>[ 0.952811] io scheduler mq-deadline registered
10833 09:29:18.046471 <6>[ 0.957591] io scheduler kyber registered
10834 09:29:18.066024 <6>[ 0.974665] EINJ: ACPI disabled.
10835 09:29:18.097528 <4>[ 1.000157] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10836 09:29:18.107527 <4>[ 1.010778] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10837 09:29:18.122291 <6>[ 1.031479] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10838 09:29:18.130383 <6>[ 1.039423] printk: console [ttyS0] disabled
10839 09:29:18.158427 <6>[ 1.064070] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10840 09:29:18.164988 <6>[ 1.073551] printk: console [ttyS0] enabled
10841 09:29:18.168116 <6>[ 1.073551] printk: console [ttyS0] enabled
10842 09:29:18.174808 <6>[ 1.082451] printk: bootconsole [mtk8250] disabled
10843 09:29:18.178479 <6>[ 1.082451] printk: bootconsole [mtk8250] disabled
10844 09:29:18.184544 <6>[ 1.093681] SuperH (H)SCI(F) driver initialized
10845 09:29:18.188023 <6>[ 1.098972] msm_serial: driver initialized
10846 09:29:18.202436 <6>[ 1.107933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10847 09:29:18.212384 <6>[ 1.116486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10848 09:29:18.219235 <6>[ 1.125027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10849 09:29:18.228502 <6>[ 1.133655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10850 09:29:18.238971 <6>[ 1.142362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10851 09:29:18.245290 <6>[ 1.151081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10852 09:29:18.255526 <6>[ 1.159623] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10853 09:29:18.262049 <6>[ 1.168425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10854 09:29:18.271406 <6>[ 1.176969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10855 09:29:18.283908 <6>[ 1.192567] loop: module loaded
10856 09:29:18.290086 <6>[ 1.198528] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10857 09:29:18.312400 <4>[ 1.221663] mtk-pmic-keys: Failed to locate of_node [id: -1]
10858 09:29:18.319433 <6>[ 1.228536] megasas: 07.719.03.00-rc1
10859 09:29:18.329033 <6>[ 1.238060] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10860 09:29:18.337246 <6>[ 1.245944] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10861 09:29:18.353261 <6>[ 1.262354] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10862 09:29:18.413122 <6>[ 1.315597] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10863 09:29:21.870116 <6>[ 4.779637] Freeing initrd memory: 96008K
10864 09:29:21.880926 <6>[ 4.790000] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10865 09:29:21.891699 <6>[ 4.800940] tun: Universal TUN/TAP device driver, 1.6
10866 09:29:21.895076 <6>[ 4.807016] thunder_xcv, ver 1.0
10867 09:29:21.898157 <6>[ 4.810511] thunder_bgx, ver 1.0
10868 09:29:21.901471 <6>[ 4.814012] nicpf, ver 1.0
10869 09:29:21.912052 <6>[ 4.818031] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10870 09:29:21.915300 <6>[ 4.825507] hns3: Copyright (c) 2017 Huawei Corporation.
10871 09:29:21.921696 <6>[ 4.831093] hclge is initializing
10872 09:29:21.925120 <6>[ 4.834672] e1000: Intel(R) PRO/1000 Network Driver
10873 09:29:21.931575 <6>[ 4.839802] e1000: Copyright (c) 1999-2006 Intel Corporation.
10874 09:29:21.934938 <6>[ 4.845813] e1000e: Intel(R) PRO/1000 Network Driver
10875 09:29:21.941594 <6>[ 4.851029] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10876 09:29:21.948335 <6>[ 4.857217] igb: Intel(R) Gigabit Ethernet Network Driver
10877 09:29:21.954956 <6>[ 4.862867] igb: Copyright (c) 2007-2014 Intel Corporation.
10878 09:29:21.961627 <6>[ 4.868706] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10879 09:29:21.967934 <6>[ 4.875224] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10880 09:29:21.971269 <6>[ 4.881683] sky2: driver version 1.30
10881 09:29:21.977916 <6>[ 4.886688] VFIO - User Level meta-driver version: 0.3
10882 09:29:21.985524 <6>[ 4.894908] usbcore: registered new interface driver usb-storage
10883 09:29:21.992121 <6>[ 4.901350] usbcore: registered new device driver onboard-usb-hub
10884 09:29:22.001132 <6>[ 4.910430] mt6397-rtc mt6359-rtc: registered as rtc0
10885 09:29:22.010832 <6>[ 4.915897] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:29:23 UTC (1697794163)
10886 09:29:22.014557 <6>[ 4.925460] i2c_dev: i2c /dev entries driver
10887 09:29:22.031239 <6>[ 4.937155] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10888 09:29:22.050581 <6>[ 4.960139] cpu cpu0: EM: created perf domain
10889 09:29:22.054114 <6>[ 4.965081] cpu cpu4: EM: created perf domain
10890 09:29:22.061080 <6>[ 4.970681] sdhci: Secure Digital Host Controller Interface driver
10891 09:29:22.068075 <6>[ 4.977110] sdhci: Copyright(c) Pierre Ossman
10892 09:29:22.074508 <6>[ 4.982066] Synopsys Designware Multimedia Card Interface Driver
10893 09:29:22.081055 <6>[ 4.988694] sdhci-pltfm: SDHCI platform and OF driver helper
10894 09:29:22.084669 <6>[ 4.988747] mmc0: CQHCI version 5.10
10895 09:29:22.091038 <6>[ 4.998609] ledtrig-cpu: registered to indicate activity on CPUs
10896 09:29:22.097632 <6>[ 5.005568] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10897 09:29:22.104389 <6>[ 5.012620] usbcore: registered new interface driver usbhid
10898 09:29:22.107509 <6>[ 5.018443] usbhid: USB HID core driver
10899 09:29:22.114128 <6>[ 5.022632] spi_master spi0: will run message pump with realtime priority
10900 09:29:22.160036 <6>[ 5.063057] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10901 09:29:22.179688 <6>[ 5.078957] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10902 09:29:22.186561 <6>[ 5.093877] cros-ec-spi spi0.0: Chrome EC device registered
10903 09:29:22.189577 <6>[ 5.099964] mmc0: Command Queue Engine enabled
10904 09:29:22.196388 <6>[ 5.104731] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10905 09:29:22.202826 <6>[ 5.112339] mmcblk0: mmc0:0001 DA4128 116 GiB
10906 09:29:22.212582 <6>[ 5.116676] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10907 09:29:22.219225 <6>[ 5.121088] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10908 09:29:22.222869 <6>[ 5.127513] NET: Registered PF_PACKET protocol family
10909 09:29:22.229228 <6>[ 5.133686] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10910 09:29:22.232445 <6>[ 5.137691] 9pnet: Installing 9P2000 support
10911 09:29:22.239239 <6>[ 5.143538] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10912 09:29:22.242435 <5>[ 5.147385] Key type dns_resolver registered
10913 09:29:22.249124 <6>[ 5.153251] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10914 09:29:22.252000 <6>[ 5.157510] registered taskstats version 1
10915 09:29:22.258857 <5>[ 5.168008] Loading compiled-in X.509 certificates
10916 09:29:22.291201 <4>[ 5.193744] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10917 09:29:22.300953 <4>[ 5.204470] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10918 09:29:22.307546 <3>[ 5.215000] debugfs: File 'uA_load' in directory '/' already present!
10919 09:29:22.313833 <3>[ 5.221699] debugfs: File 'min_uV' in directory '/' already present!
10920 09:29:22.320526 <3>[ 5.228360] debugfs: File 'max_uV' in directory '/' already present!
10921 09:29:22.327534 <3>[ 5.234974] debugfs: File 'constraint_flags' in directory '/' already present!
10922 09:29:22.338609 <3>[ 5.244878] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10923 09:29:22.348467 <6>[ 5.257945] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10924 09:29:22.355653 <6>[ 5.264757] xhci-mtk 11200000.usb: xHCI Host Controller
10925 09:29:22.362169 <6>[ 5.270278] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10926 09:29:22.372181 <6>[ 5.278130] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10927 09:29:22.378761 <6>[ 5.287565] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10928 09:29:22.385115 <6>[ 5.293635] xhci-mtk 11200000.usb: xHCI Host Controller
10929 09:29:22.391636 <6>[ 5.299127] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10930 09:29:22.398516 <6>[ 5.306778] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10931 09:29:22.405129 <6>[ 5.314498] hub 1-0:1.0: USB hub found
10932 09:29:22.408472 <6>[ 5.318512] hub 1-0:1.0: 1 port detected
10933 09:29:22.418204 <6>[ 5.322789] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10934 09:29:22.421629 <6>[ 5.331368] hub 2-0:1.0: USB hub found
10935 09:29:22.424797 <6>[ 5.335374] hub 2-0:1.0: 1 port detected
10936 09:29:22.434300 <6>[ 5.343805] mtk-msdc 11f70000.mmc: Got CD GPIO
10937 09:29:22.444567 <6>[ 5.350293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10938 09:29:22.450840 <6>[ 5.358330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10939 09:29:22.460745 <4>[ 5.366226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10940 09:29:22.471063 <6>[ 5.375750] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10941 09:29:22.477099 <6>[ 5.383830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10942 09:29:22.484156 <6>[ 5.391937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10943 09:29:22.493452 <6>[ 5.399869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10944 09:29:22.500253 <6>[ 5.407746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10945 09:29:22.510341 <6>[ 5.415569] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10946 09:29:22.520384 <6>[ 5.425808] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10947 09:29:22.526656 <6>[ 5.434165] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10948 09:29:22.536804 <6>[ 5.442533] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10949 09:29:22.543188 <6>[ 5.450872] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10950 09:29:22.552842 <6>[ 5.459222] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10951 09:29:22.563099 <6>[ 5.467560] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10952 09:29:22.569500 <6>[ 5.475911] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10953 09:29:22.579597 <6>[ 5.484250] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10954 09:29:22.585968 <6>[ 5.492599] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10955 09:29:22.595939 <6>[ 5.500937] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10956 09:29:22.602893 <6>[ 5.509285] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10957 09:29:22.612654 <6>[ 5.517624] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10958 09:29:22.619184 <6>[ 5.525963] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10959 09:29:22.629076 <6>[ 5.534301] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10960 09:29:22.636023 <6>[ 5.542639] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10961 09:29:22.642219 <6>[ 5.551499] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10962 09:29:22.649223 <6>[ 5.558826] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10963 09:29:22.656285 <6>[ 5.565817] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10964 09:29:22.666833 <6>[ 5.572681] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10965 09:29:22.673222 <6>[ 5.579640] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10966 09:29:22.679865 <6>[ 5.586496] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10967 09:29:22.689855 <6>[ 5.595629] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10968 09:29:22.699449 <6>[ 5.604749] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10969 09:29:22.709415 <6>[ 5.614043] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10970 09:29:22.719180 <6>[ 5.623552] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10971 09:29:22.729496 <6>[ 5.633130] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10972 09:29:22.736033 <6>[ 5.642254] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10973 09:29:22.745614 <6>[ 5.651722] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10974 09:29:22.755732 <6>[ 5.660842] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10975 09:29:22.765927 <6>[ 5.670138] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10976 09:29:22.775568 <6>[ 5.680298] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10977 09:29:22.785828 <6>[ 5.691776] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10978 09:29:22.852997 <6>[ 5.758867] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10979 09:29:23.007527 <6>[ 5.916818] hub 1-1:1.0: USB hub found
10980 09:29:23.010785 <6>[ 5.921364] hub 1-1:1.0: 4 ports detected
10981 09:29:23.132477 <6>[ 6.038833] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10982 09:29:23.158202 <6>[ 6.067582] hub 2-1:1.0: USB hub found
10983 09:29:23.161640 <6>[ 6.071986] hub 2-1:1.0: 3 ports detected
10984 09:29:23.332676 <6>[ 6.238882] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10985 09:29:23.463833 <6>[ 6.373270] hub 1-1.1:1.0: USB hub found
10986 09:29:23.466926 <6>[ 6.377753] hub 1-1.1:1.0: 4 ports detected
10987 09:29:23.584403 <6>[ 6.490728] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10988 09:29:23.717639 <6>[ 6.627205] hub 1-1.4:1.0: USB hub found
10989 09:29:23.720809 <6>[ 6.631923] hub 1-1.4:1.0: 2 ports detected
10990 09:29:23.800814 <6>[ 6.706903] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10991 09:29:23.988537 <6>[ 6.894851] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10992 09:29:24.073450 <3>[ 6.982999] usb 1-1.1.4: device descriptor read/64, error -32
10993 09:29:24.265089 <3>[ 7.174993] usb 1-1.1.4: device descriptor read/64, error -32
10994 09:29:24.460411 <6>[ 7.366874] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10995 09:29:24.648440 <6>[ 7.554871] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10996 09:29:24.733116 <3>[ 7.643029] usb 1-1.1.4: device descriptor read/64, error -32
10997 09:29:24.925397 <3>[ 7.835049] usb 1-1.1.4: device descriptor read/64, error -32
10998 09:29:25.037639 <6>[ 7.947401] usb 1-1.1-port4: attempt power cycle
10999 09:29:25.124185 <6>[ 8.030880] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
11000 09:29:25.648692 <6>[ 8.554878] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
11001 09:29:25.655062 <4>[ 8.562336] usb 1-1.1.4: Device not responding to setup address.
11002 09:29:25.865224 <4>[ 8.775079] usb 1-1.1.4: Device not responding to setup address.
11003 09:29:26.077275 <3>[ 8.986874] usb 1-1.1.4: device not accepting address 10, error -71
11004 09:29:26.164325 <6>[ 9.070903] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
11005 09:29:26.171047 <4>[ 9.078385] usb 1-1.1.4: Device not responding to setup address.
11006 09:29:26.381068 <4>[ 9.291123] usb 1-1.1.4: Device not responding to setup address.
11007 09:29:26.592881 <3>[ 9.502896] usb 1-1.1.4: device not accepting address 11, error -71
11008 09:29:26.600646 <3>[ 9.509934] usb 1-1.1-port4: unable to enumerate USB device
11009 09:29:35.085852 <6>[ 17.999895] ALSA device list:
11010 09:29:35.092222 <6>[ 18.003191] No soundcards found.
11011 09:29:35.100166 <6>[ 18.011145] Freeing unused kernel memory: 8384K
11012 09:29:35.103475 <6>[ 18.016192] Run /init as init process
11013 09:29:35.150449 <6>[ 18.060601] NET: Registered PF_INET6 protocol family
11014 09:29:35.156494 <6>[ 18.066688] Segment Routing with IPv6
11015 09:29:35.159647 <6>[ 18.070628] In-situ OAM (IOAM) with IPv6
11016 09:29:35.193577 <30>[ 18.084723] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
11017 09:29:35.196515 <30>[ 18.108639] systemd[1]: Detected architecture arm64.
11018 09:29:35.199947
11019 09:29:35.203284 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
11020 09:29:35.203365
11021 09:29:35.220230 <30>[ 18.130818] systemd[1]: Set hostname to <debian-bullseye-arm64>.
11022 09:29:35.361758 <30>[ 18.269516] systemd[1]: Queued start job for default target Graphical Interface.
11023 09:29:35.388873 <30>[ 18.299954] systemd[1]: Created slice system-getty.slice.
11024 09:29:35.395748 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
11025 09:29:35.412324 <30>[ 18.323277] systemd[1]: Created slice system-modprobe.slice.
11026 09:29:35.418947 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
11027 09:29:35.436505 <30>[ 18.347565] systemd[1]: Created slice system-serial\x2dgetty.slice.
11028 09:29:35.446536 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
11029 09:29:35.461312 <30>[ 18.372183] systemd[1]: Created slice User and Session Slice.
11030 09:29:35.467623 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
11031 09:29:35.488421 <30>[ 18.395562] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
11032 09:29:35.497907 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
11033 09:29:35.515836 <30>[ 18.423043] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
11034 09:29:35.522149 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
11035 09:29:35.542433 <30>[ 18.446999] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
11036 09:29:35.549139 <30>[ 18.459170] systemd[1]: Reached target Local Encrypted Volumes.
11037 09:29:35.555782 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
11038 09:29:35.572817 <30>[ 18.483358] systemd[1]: Reached target Paths.
11039 09:29:35.579065 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
11040 09:29:35.592306 <30>[ 18.502875] systemd[1]: Reached target Remote File Systems.
11041 09:29:35.598827 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
11042 09:29:35.616825 <30>[ 18.527244] systemd[1]: Reached target Slices.
11043 09:29:35.622706 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
11044 09:29:35.635971 <30>[ 18.546876] systemd[1]: Reached target Swap.
11045 09:29:35.639143 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
11046 09:29:35.659730 <30>[ 18.567371] systemd[1]: Listening on initctl Compatibility Named Pipe.
11047 09:29:35.666107 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
11048 09:29:35.673193 <30>[ 18.582532] systemd[1]: Listening on Journal Audit Socket.
11049 09:29:35.679885 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
11050 09:29:35.692268 <30>[ 18.603349] systemd[1]: Listening on Journal Socket (/dev/log).
11051 09:29:35.699185 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
11052 09:29:35.717485 <30>[ 18.628092] systemd[1]: Listening on Journal Socket.
11053 09:29:35.723311 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
11054 09:29:35.736780 <30>[ 18.647432] systemd[1]: Listening on udev Control Socket.
11055 09:29:35.743035 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11056 09:29:35.760740 <30>[ 18.671886] systemd[1]: Listening on udev Kernel Socket.
11057 09:29:35.767332 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11058 09:29:35.816619 <30>[ 18.727388] systemd[1]: Mounting Huge Pages File System...
11059 09:29:35.823403 Mounting [0;1;39mHuge Pages File System[0m...
11060 09:29:35.840337 <30>[ 18.751034] systemd[1]: Mounting POSIX Message Queue File System...
11061 09:29:35.846820 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11062 09:29:35.868227 <30>[ 18.779051] systemd[1]: Mounting Kernel Debug File System...
11063 09:29:35.874524 Mounting [0;1;39mKernel Debug File System[0m...
11064 09:29:35.891841 <30>[ 18.799435] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11065 09:29:35.905024 <30>[ 18.812691] systemd[1]: Starting Create list of static device nodes for the current kernel...
11066 09:29:35.911559 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11067 09:29:35.932151 <30>[ 18.843379] systemd[1]: Starting Load Kernel Module configfs...
11068 09:29:35.938805 Starting [0;1;39mLoad Kernel Module configfs[0m...
11069 09:29:35.956568 <30>[ 18.867318] systemd[1]: Starting Load Kernel Module drm...
11070 09:29:35.963014 Starting [0;1;39mLoad Kernel Module drm[0m...
11071 09:29:35.979767 <30>[ 18.887217] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11072 09:29:36.024830 <30>[ 18.935734] systemd[1]: Starting Journal Service...
11073 09:29:36.028407 Starting [0;1;39mJournal Service[0m...
11074 09:29:36.049890 <30>[ 18.960831] systemd[1]: Starting Load Kernel Modules...
11075 09:29:36.056598 Starting [0;1;39mLoad Kernel Modules[0m...
11076 09:29:36.080493 <30>[ 18.987708] systemd[1]: Starting Remount Root and Kernel File Systems...
11077 09:29:36.086529 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11078 09:29:36.103928 <30>[ 19.014834] systemd[1]: Starting Coldplug All udev Devices...
11079 09:29:36.110117 Starting [0;1;39mColdplug All udev Devices[0m...
11080 09:29:36.126975 <30>[ 19.037660] systemd[1]: Started Journal Service.
11081 09:29:36.133136 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11082 09:29:36.150755 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11083 09:29:36.168626 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11084 09:29:36.184695 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11085 09:29:36.205088 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11086 09:29:36.226929 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11087 09:29:36.246303 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11088 09:29:36.270303 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11089 09:29:36.294311 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11090 09:29:36.311792 See 'systemctl status systemd-remount-fs.service' for details.
11091 09:29:36.375022 Mounting [0;1;39mKernel Configuration File System[0m...
11092 09:29:36.394724 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11093 09:29:36.413468 <46>[ 19.321242] systemd-journald[178]: Received client request to flush runtime journal.
11094 09:29:36.421985 Starting [0;1;39mLoad/Save Random Seed[0m...
11095 09:29:36.444299 Starting [0;1;39mApply Kernel Variables[0m...
11096 09:29:36.468397 Starting [0;1;39mCreate System Users[0m...
11097 09:29:36.491136 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11098 09:29:36.514164 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11099 09:29:36.541232 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11100 09:29:36.557894 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11101 09:29:36.577485 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11102 09:29:36.593781 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11103 09:29:36.636089 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11104 09:29:36.663818 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11105 09:29:36.676963 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11106 09:29:36.692449 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11107 09:29:36.736494 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11108 09:29:36.760422 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11109 09:29:36.780773 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11110 09:29:36.802192 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11111 09:29:36.870263 Starting [0;1;39mNetwork Time Synchronization[0m...
11112 09:29:36.899221 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11113 09:29:36.930930 <6>[ 19.838776] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11114 09:29:36.949783 <3>[ 19.857067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11115 09:29:36.955836 <3>[ 19.865323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11116 09:29:36.962289 <6>[ 19.867889] remoteproc remoteproc0: scp is available
11117 09:29:36.969137 <3>[ 19.876041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11118 09:29:36.975846 [[0;32m OK [<6>[ 19.883835] remoteproc remoteproc0: powering up scp
11119 09:29:36.985944 0m] Found device<3>[ 19.888185] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11120 09:29:36.995773 [0;1;39m/dev/t<6>[ 19.893340] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11121 09:29:36.998809 tyS0[0m.
11122 09:29:37.002075 <6>[ 19.893403] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11123 09:29:37.012467 <3>[ 19.903302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11124 09:29:37.018217 <3>[ 19.927903] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11125 09:29:37.028665 <3>[ 19.936091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11126 09:29:37.034878 <6>[ 19.937404] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11127 09:29:37.044714 [[0;32m OK [<3>[ 19.944203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11128 09:29:37.054747 <3>[ 19.949073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11129 09:29:37.064518 0m] Started [0;<6>[ 19.951826] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11130 09:29:37.075060 1;39mNetwork Tim<6>[ 19.951839] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11131 09:29:37.081399 e Synchronizatio<6>[ 19.960130] usbcore: registered new interface driver r8152
11132 09:29:37.081482 n[0m.
11133 09:29:37.088204 <3>[ 19.961958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11134 09:29:37.097703 <3>[ 20.005600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11135 09:29:37.104469 <3>[ 20.013788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11136 09:29:37.117060 <4>[ 20.024893] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11137 09:29:37.123484 <3>[ 20.026272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11138 09:29:37.130931 <6>[ 20.033441] mc: Linux media interface: v0.10
11139 09:29:37.136792 <6>[ 20.038340] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11140 09:29:37.144041 <6>[ 20.038345] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11141 09:29:37.150094 <6>[ 20.038350] remoteproc remoteproc0: remote processor scp is now up
11142 09:29:37.159970 <3>[ 20.040381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11143 09:29:37.166723 <4>[ 20.045207] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11144 09:29:37.173153 <3>[ 20.053426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11145 09:29:37.183176 <3>[ 20.053433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11146 09:29:37.190330 <6>[ 20.062658] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11147 09:29:37.200138 <3>[ 20.067105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11148 09:29:37.206222 <6>[ 20.092273] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11149 09:29:37.212981 <3>[ 20.098552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11150 09:29:37.222862 <4>[ 20.098763] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11151 09:29:37.226254 <4>[ 20.098763] Fallback method does not support PEC.
11152 09:29:37.232541 <6>[ 20.100109] videodev: Linux video capture interface: v2.00
11153 09:29:37.239507 <6>[ 20.106804] pci_bus 0000:00: root bus resource [bus 00-ff]
11154 09:29:37.246211 <6>[ 20.122114] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
11155 09:29:37.255810 <6>[ 20.130446] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11156 09:29:37.265760 <6>[ 20.170521] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11157 09:29:37.272190 <6>[ 20.170618] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11158 09:29:37.279867 <6>[ 20.171897] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11159 09:29:37.289498 <6>[ 20.172034] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11160 09:29:37.299041 <6>[ 20.172650] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11161 09:29:37.306066 <6>[ 20.174911] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11162 09:29:37.315950 <6>[ 20.184690] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11163 09:29:37.326013 [[0;32m OK [<6>[ 20.186832] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11164 09:29:37.332250 <3>[ 20.195169] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11165 09:29:37.339094 <6>[ 20.232447] usbcore: registered new interface driver cdc_ether
11166 09:29:37.345807 0m] Created slic<6>[ 20.240718] pci 0000:00:00.0: supports D1 D2
11167 09:29:37.352154 e [0;1;39msyste<6>[ 20.242499] Bluetooth: Core ver 2.22
11168 09:29:37.358943 m-systemd\x2dbac<6>[ 20.242607] NET: Registered PF_BLUETOOTH protocol family
11169 09:29:37.366029 <6>[ 20.242609] Bluetooth: HCI device and connection manager initialized
11170 09:29:37.369136 klight.slice[0m<6>[ 20.242633] Bluetooth: HCI socket layer initialized
11171 09:29:37.372501 .
11172 09:29:37.376426 <6>[ 20.242637] Bluetooth: L2CAP socket layer initialized
11173 09:29:37.379620 <6>[ 20.242647] Bluetooth: SCO socket layer initialized
11174 09:29:37.386806 <6>[ 20.261742] usbcore: registered new interface driver r8153_ecm
11175 09:29:37.393244 <6>[ 20.266708] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11176 09:29:37.403089 <6>[ 20.267977] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11177 09:29:37.410094 <6>[ 20.275223] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11178 09:29:37.420575 <4>[ 20.277712] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11179 09:29:37.427410 <4>[ 20.277722] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11180 09:29:37.433872 <6>[ 20.280416] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11181 09:29:37.440464 <6>[ 20.287559] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11182 09:29:37.453261 <6>[ 20.288019] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11183 09:29:37.456402 <6>[ 20.288157] usbcore: registered new interface driver uvcvideo
11184 09:29:37.466698 <3>[ 20.291455] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
11185 09:29:37.473229 <6>[ 20.292418] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11186 09:29:37.480002 <6>[ 20.293188] usbcore: registered new interface driver btusb
11187 09:29:37.489743 <4>[ 20.293771] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11188 09:29:37.496673 <3>[ 20.293781] Bluetooth: hci0: Failed to load firmware file (-2)
11189 09:29:37.502965 <3>[ 20.293786] Bluetooth: hci0: Failed to set up firmware (-2)
11190 09:29:37.513403 <4>[ 20.293791] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11191 09:29:37.520520 <3>[ 20.312207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11192 09:29:37.530846 <6>[ 20.318742] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11193 09:29:37.537579 <3>[ 20.337484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11194 09:29:37.543898 <6>[ 20.343246] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11195 09:29:37.550533 <6>[ 20.343356] pci 0000:01:00.0: supports D1 D2
11196 09:29:37.556993 <3>[ 20.349695] power_supply sbs-5-000b: driver failed to report `energy_now' property: -6
11197 09:29:37.563957 <6>[ 20.356015] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11198 09:29:37.570495 <6>[ 20.358926] r8152 1-1.1.1:1.0 eth0: v1.12.13
11199 09:29:37.576686 <6>[ 20.366786] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11200 09:29:37.583570 <6>[ 20.366814] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11201 09:29:37.593883 <6>[ 20.366818] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11202 09:29:37.600173 <6>[ 20.366827] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11203 09:29:37.609953 <6>[ 20.366839] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11204 09:29:37.616752 <6>[ 20.366852] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11205 09:29:37.623334 <6>[ 20.366865] pci 0000:00:00.0: PCI bridge to [bus 01]
11206 09:29:37.630078 <6>[ 20.366871] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11207 09:29:37.636430 <6>[ 20.367013] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11208 09:29:37.642805 <6>[ 20.367497] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11209 09:29:37.649664 <6>[ 20.368154] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11210 09:29:37.655885 <5>[ 20.393013] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11211 09:29:37.662567 <6>[ 20.408038] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11212 09:29:37.669190 <5>[ 20.429058] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11213 09:29:37.679029 <3>[ 20.432710] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11214 09:29:37.685760 [[0;32m OK [<3>[ 20.595232] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11215 09:29:37.695668 <4>[ 20.595377] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11216 09:29:37.702344 0m] Reached targ<6>[ 20.612421] cfg80211: failed to load regulatory.db
11217 09:29:37.705409 et [0;1;39mSystem Time Set[0m.
11218 09:29:37.717704 <3>[ 20.625693] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11219 09:29:37.724317 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11220 09:29:37.739877 <6>[ 20.647674] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11221 09:29:37.746707 <6>[ 20.655295] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11222 09:29:37.753555 <3>[ 20.659419] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11223 09:29:37.768387 Starting [0;1;39mLoad/Save Screen …o<6>[ 20.679066] mt7921e 0000:01:00.0: ASIC revision: 79610010
11224 09:29:37.771590 f leds:white:kbd_backlight[0m...
11225 09:29:37.788628 <3>[ 20.696562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11226 09:29:37.799185 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11227 09:29:37.817167 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11228 09:29:37.873553 <4>[ 20.777972] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11229 09:29:37.949551 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11230 09:29:37.963513 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11231 09:29:37.984342 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11232 09:29:37.993975 <4>[ 20.899339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11233 09:29:38.000952 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11234 09:29:38.016236 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11235 09:29:38.035637 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11236 09:29:38.051874 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11237 09:29:38.071648 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11238 09:29:38.091560 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11239 09:29:38.114826 <4>[ 21.019461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11240 09:29:38.134507 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11241 09:29:38.174806 Starting [0;1;39mUser Login Management[0m...
11242 09:29:38.192941 Starting [0;1;39mPermit User Sessions[0m...
11243 09:29:38.211576 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11244 09:29:38.229023 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11245 09:29:38.238596 <4>[ 21.144603] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11246 09:29:38.254545 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11247 09:29:38.261828 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11248 09:29:38.279864 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11249 09:29:38.297231 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11250 09:29:38.314090 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11251 09:29:38.329160 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11252 09:29:38.345307 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11253 09:29:38.362460 <4>[ 21.267390] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11254 09:29:38.421574 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11255 09:29:38.457127 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11256 09:29:38.487775 <4>[ 21.392550] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11257 09:29:38.509020
11258 09:29:38.509137
11259 09:29:38.512107 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11260 09:29:38.512188
11261 09:29:38.515386 debian-bullseye-arm64 login: root (automatic login)
11262 09:29:38.515494
11263 09:29:38.515563
11264 09:29:38.532653 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
11265 09:29:38.532745
11266 09:29:38.538821 The programs included with the Debian GNU/Linux system are free software;
11267 09:29:38.545215 the exact distribution terms for each program are described in the
11268 09:29:38.548502 individual files in /usr/share/doc/*/copyright.
11269 09:29:38.548584
11270 09:29:38.555278 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11271 09:29:38.558512 permitted by applicable law.
11272 09:29:38.558892 Matched prompt #10: / #
11274 09:29:38.559096 Setting prompt string to ['/ #']
11275 09:29:38.559185 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11277 09:29:38.559374 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11278 09:29:38.559500 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
11279 09:29:38.559568 Setting prompt string to ['/ #']
11280 09:29:38.559627 Forcing a shell prompt, looking for ['/ #']
11282 09:29:38.609869 / #
11283 09:29:38.610019 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11284 09:29:38.610170 Waiting using forced prompt support (timeout 00:02:30)
11285 09:29:38.651922 <4>[ 21.519445] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11286 09:29:38.652032
11287 09:29:38.652302 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11288 09:29:38.652397 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
11289 09:29:38.652489 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11290 09:29:38.652576 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
11291 09:29:38.652664 end: 2 depthcharge-action (duration 00:01:55) [common]
11292 09:29:38.652751 start: 3 lava-test-retry (timeout 00:05:00) [common]
11293 09:29:38.652834 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11294 09:29:38.652905 Using namespace: common
11296 09:29:38.753251 / # #
11297 09:29:38.753424 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11298 09:29:38.753573 #<4>[ 21.642939] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11299 09:29:38.758588
11300 09:29:38.758853 Using /lava-11826806
11302 09:29:38.859205 / # export SHELL=/bin/sh
11303 09:29:38.859440 export SHELL=/bin/sh<4>[ 21.763455] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11304 09:29:38.865066
11306 09:29:38.965616 / # . /lava-11826806/environment
11307 09:29:38.978555 . /lava-11826806/environment<4>[ 21.883291] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11308 09:29:38.978655
11310 09:29:39.083794 / # /lava-11826806/bin/lava-test-runner /lava-11826806/0
11311 09:29:39.083961 Test shell timeout: 10s (minimum of the action and connection timeout)
11312 09:29:39.089767 /lava-11826806/bin/lava-test-runner /lava-11826806/0<3>[ 22.001205] mt7921e 0000:01:00.0: hardware init failed
11313 09:29:39.089852
11314 09:29:39.112911 + export TESTRUN_ID=0_sleep
11315 09:29:39.116555 + cd /lava-11826806/0/tests/0_sleep
11316 09:29:39.119534 + cat uuid
11317 09:29:39.119615 + UUID=11826806_1.5.2.3.1
11318 09:29:39.123083 + set +x
11319 09:29:39.126208 <LAVA_SIGNAL_STARTRUN 0_sleep 11826806_1.5.2.3.1>
11320 09:29:39.126509 Received signal: <STARTRUN> 0_sleep 11826806_1.5.2.3.1
11321 09:29:39.126614 Starting test lava.0_sleep (11826806_1.5.2.3.1)
11322 09:29:39.126730 Skipping test definition patterns.
11323 09:29:39.129710 + ./config/lava/sleep/sleep.sh mem freeze
11324 09:29:39.133218 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11326 09:29:39.136277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11327 09:29:39.139351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11328 09:29:39.139604 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11330 09:29:39.142689 rtcwake: assuming RTC uses UTC ...
11331 09:29:39.152679 rtcwake: wakeup from "mem" using rtc0 at Fri<6>[ 22.062422] PM: suspend entry (deep)
11332 09:29:39.156222 Oct 20 09:29:46<6>[ 22.067610] Filesystems sync: 0.000 seconds
11333 09:29:39.159144 2023
11334 09:29:39.162352 <6>[ 22.074590] Freezing user space processes
11335 09:29:39.172594 <6>[ 22.080523] Freezing user space processes completed (elapsed 0.001 seconds)
11336 09:29:39.175762 <6>[ 22.087763] OOM killer disabled.
11337 09:29:39.179174 <6>[ 22.091251] Freezing remaining freezable tasks
11338 09:29:39.189188 <6>[ 22.097143] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11339 09:29:39.195561 <6>[ 22.104801] printk: Suspending console(s) (use no_console_suspend to debug)
11340 09:29:42.516607 <3>[ 25.166965] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11341 09:29:42.526862 <3>[ 25.166999] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11342 09:29:42.536535 <3>[ 25.167042] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11343 09:29:42.543002 <3>[ 25.167082] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11344 09:29:42.552974 <3>[ 25.167425] PM: Some devices failed to suspend, or early wake event detected
11345 09:29:42.559434 <4>[ 25.182444] typec port0-partner: PM: parent port0 should not be sleeping
11346 09:29:42.566461 <4>[ 25.197408] typec port0-cable: PM: parent port0 should not be sleeping
11347 09:29:42.569629 <6>[ 25.482138] OOM killer enabled.
11348 09:29:42.576119 <6>[ 25.485547] Restarting tasks ... done.
11349 09:29:42.579423 <5>[ 25.491935] random: crng reseeded on system resumption
11350 09:29:42.583758 <6>[ 25.498168] PM: suspend exit
11351 09:29:42.586279 rtcwake: write error
11352 09:29:42.595421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11353 09:29:42.595684 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11355 09:29:42.598621 rtcwake: assuming RTC uses UTC ...
11356 09:29:42.605218 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:29:50 2023
11357 09:29:42.617875 <6>[ 25.529440] PM: suspend entry (deep)
11358 09:29:42.621022 <6>[ 25.533353] Filesystems sync: 0.000 seconds
11359 09:29:42.624290 <6>[ 25.538413] Freezing user space processes
11360 09:29:42.635928 <6>[ 25.544358] Freezing user space processes completed (elapsed 0.001 seconds)
11361 09:29:42.639294 <6>[ 25.551583] OOM killer disabled.
11362 09:29:42.642693 <6>[ 25.555063] Freezing remaining freezable tasks
11363 09:29:42.662653 <6>[ 25.570751] usb 1-1.1.4: new full-speed USB device number 12 using xhci-mtk
11364 09:29:42.742901 <3>[ 25.654868] usb 1-1.1.4: device descriptor read/64, error -32
11365 09:29:42.935649 <3>[ 25.846952] usb 1-1.1.4: device descriptor read/64, error -32
11366 09:29:43.130396 <6>[ 26.038924] usb 1-1.1.4: new full-speed USB device number 13 using xhci-mtk
11367 09:29:43.215640 <3>[ 26.126932] usb 1-1.1.4: device descriptor read/64, error -32
11368 09:29:43.407339 <3>[ 26.319092] usb 1-1.1.4: device descriptor read/64, error -32
11369 09:29:43.519352 <6>[ 26.431430] usb 1-1.1-port4: attempt power cycle
11370 09:29:44.130041 <6>[ 27.038774] usb 1-1.1.4: new full-speed USB device number 14 using xhci-mtk
11371 09:29:44.136767 <4>[ 27.046228] usb 1-1.1.4: Device not responding to setup address.
11372 09:29:44.347005 <4>[ 27.259137] usb 1-1.1.4: Device not responding to setup address.
11373 09:29:44.558813 <3>[ 27.470932] usb 1-1.1.4: device not accepting address 14, error -71
11374 09:29:44.646149 <6>[ 27.554925] usb 1-1.1.4: new full-speed USB device number 15 using xhci-mtk
11375 09:29:44.653154 <4>[ 27.562316] usb 1-1.1.4: Device not responding to setup address.
11376 09:29:44.863231 <4>[ 27.775137] usb 1-1.1.4: Device not responding to setup address.
11377 09:29:45.074639 <3>[ 27.986899] usb 1-1.1.4: device not accepting address 15, error -71
11378 09:29:45.081859 <3>[ 27.993917] usb 1-1.1-port4: unable to enumerate USB device
11379 09:29:45.099443 <6>[ 28.008201] Freezing remaining freezable tasks completed (elapsed 2.448 seconds)
11380 09:29:45.106165 <6>[ 28.015894] printk: Suspending console(s) (use no_console_suspend to debug)
11381 09:29:48.412667 <3>[ 31.054946] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11382 09:29:48.422813 <3>[ 31.054983] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11383 09:29:48.432633 <3>[ 31.055040] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11384 09:29:48.438947 <3>[ 31.055085] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11385 09:29:48.449450 <3>[ 31.055397] PM: Some devices failed to suspend, or early wake event detected
11386 09:29:48.452281 <6>[ 31.364916] OOM killer enabled.
11387 09:29:48.455609 <6>[ 31.368326] Restarting tasks ... done.
11388 09:29:48.463720 <5>[ 31.375797] random: crng reseeded on system resumption
11389 09:29:48.466568 <6>[ 31.382131] PM: suspend exit
11390 09:29:48.469923 rtcwake: write error
11391 09:29:48.477854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11392 09:29:48.478114 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11394 09:29:48.481144 rtcwake: assuming RTC uses UTC ...
11395 09:29:48.487873 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:29:56 2023
11396 09:29:48.501057 <6>[ 31.413660] PM: suspend entry (deep)
11397 09:29:48.504544 <6>[ 31.417606] Filesystems sync: 0.000 seconds
11398 09:29:48.511402 <6>[ 31.422893] Freezing user space processes
11399 09:29:48.517854 <6>[ 31.429134] Freezing user space processes completed (elapsed 0.001 seconds)
11400 09:29:48.520956 <6>[ 31.436451] OOM killer disabled.
11401 09:29:48.527455 <6>[ 31.439961] Freezing remaining freezable tasks
11402 09:29:48.537361 <6>[ 31.446707] usb 1-1.1.4: new full-speed USB device number 16 using xhci-mtk
11403 09:29:48.618583 <3>[ 31.531049] usb 1-1.1.4: device descriptor read/64, error -32
11404 09:29:48.810404 <3>[ 31.722953] usb 1-1.1.4: device descriptor read/64, error -32
11405 09:29:49.006192 <6>[ 31.914979] usb 1-1.1.4: new full-speed USB device number 17 using xhci-mtk
11406 09:29:49.090603 <3>[ 32.002988] usb 1-1.1.4: device descriptor read/64, error -32
11407 09:29:49.283301 <3>[ 32.195092] usb 1-1.1.4: device descriptor read/64, error -32
11408 09:29:49.394839 <6>[ 32.307417] usb 1-1.1-port4: attempt power cycle
11409 09:29:50.005991 <6>[ 32.914923] usb 1-1.1.4: new full-speed USB device number 18 using xhci-mtk
11410 09:29:50.011974 <4>[ 32.922312] usb 1-1.1.4: Device not responding to setup address.
11411 09:29:50.222539 <4>[ 33.135135] usb 1-1.1.4: Device not responding to setup address.
11412 09:29:50.434685 <3>[ 33.346898] usb 1-1.1.4: device not accepting address 18, error -71
11413 09:29:50.521546 <6>[ 33.430907] usb 1-1.1.4: new full-speed USB device number 19 using xhci-mtk
11414 09:29:50.528603 <4>[ 33.438291] usb 1-1.1.4: Device not responding to setup address.
11415 09:29:50.738511 <4>[ 33.651140] usb 1-1.1.4: Device not responding to setup address.
11416 09:29:50.950154 <3>[ 33.862763] usb 1-1.1.4: device not accepting address 19, error -71
11417 09:29:50.956812 <3>[ 33.869776] usb 1-1.1-port4: unable to enumerate USB device
11418 09:29:50.973830 <6>[ 33.883006] Freezing remaining freezable tasks completed (elapsed 2.438 seconds)
11419 09:29:50.980164 <6>[ 33.890693] printk: Suspending console(s) (use no_console_suspend to debug)
11420 09:29:54.299889 <3>[ 36.942911] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11421 09:29:54.310228 <3>[ 36.942944] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11422 09:29:54.320279 <3>[ 36.942990] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11423 09:29:54.326896 <3>[ 36.943032] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11424 09:29:54.333238 <3>[ 36.943359] PM: Some devices failed to suspend, or early wake event detected
11425 09:29:54.340316 <6>[ 37.253105] OOM killer enabled.
11426 09:29:54.343095 <6>[ 37.256520] Restarting tasks ... done.
11427 09:29:54.350889 <5>[ 37.264224] random: crng reseeded on system resumption
11428 09:29:54.355487 <6>[ 37.271819] PM: suspend exit
11429 09:29:54.358794 rtcwake: write error
11430 09:29:54.366726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11431 09:29:54.367024 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11433 09:29:54.369961 rtcwake: assuming RTC uses UTC ...
11434 09:29:54.376834 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:01 2023
11435 09:29:54.389534 <6>[ 37.302471] PM: suspend entry (deep)
11436 09:29:54.392890 <6>[ 37.306373] Filesystems sync: 0.000 seconds
11437 09:29:54.396443 <6>[ 37.311443] Freezing user space processes
11438 09:29:54.407772 <6>[ 37.317452] Freezing user space processes completed (elapsed 0.001 seconds)
11439 09:29:54.410852 <6>[ 37.324687] OOM killer disabled.
11440 09:29:54.414634 <6>[ 37.328169] Freezing remaining freezable tasks
11441 09:29:54.429141 <6>[ 37.338880] usb 1-1.1.4: new full-speed USB device number 20 using xhci-mtk
11442 09:29:54.518524 <3>[ 37.431207] usb 1-1.1.4: device descriptor read/64, error -32
11443 09:29:54.710596 <3>[ 37.623351] usb 1-1.1.4: device descriptor read/64, error -32
11444 09:29:54.904790 <6>[ 37.814759] usb 1-1.1.4: new full-speed USB device number 21 using xhci-mtk
11445 09:29:54.990302 <3>[ 37.903016] usb 1-1.1.4: device descriptor read/64, error -32
11446 09:29:55.182303 <3>[ 38.095337] usb 1-1.1.4: device descriptor read/64, error -32
11447 09:29:55.294020 <6>[ 38.207253] usb 1-1.1-port4: attempt power cycle
11448 09:29:55.905020 <6>[ 38.814937] usb 1-1.1.4: new full-speed USB device number 22 using xhci-mtk
11449 09:29:55.911702 <4>[ 38.822559] usb 1-1.1.4: Device not responding to setup address.
11450 09:29:56.121636 <4>[ 39.035003] usb 1-1.1.4: Device not responding to setup address.
11451 09:29:56.333369 <3>[ 39.246747] usb 1-1.1.4: device not accepting address 22, error -71
11452 09:29:56.420908 <6>[ 39.330838] usb 1-1.1.4: new full-speed USB device number 23 using xhci-mtk
11453 09:29:56.427198 <4>[ 39.338226] usb 1-1.1.4: Device not responding to setup address.
11454 09:29:56.637584 <4>[ 39.550974] usb 1-1.1.4: Device not responding to setup address.
11455 09:29:56.849598 <3>[ 39.762730] usb 1-1.1.4: device not accepting address 23, error -71
11456 09:29:56.856728 <3>[ 39.769878] usb 1-1.1-port4: unable to enumerate USB device
11457 09:29:56.872614 <6>[ 39.782855] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11458 09:29:56.879281 <6>[ 39.790552] printk: Suspending console(s) (use no_console_suspend to debug)
11459 09:30:00.187496 <3>[ 42.830913] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11460 09:30:00.197568 <3>[ 42.830945] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11461 09:30:00.206885 <3>[ 42.830990] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11462 09:30:00.213989 <3>[ 42.831033] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11463 09:30:00.223918 <3>[ 42.831287] PM: Some devices failed to suspend, or early wake event detected
11464 09:30:00.226942 <6>[ 43.140869] OOM killer enabled.
11465 09:30:00.230044 <6>[ 43.144282] Restarting tasks ... done.
11466 09:30:00.236766 <5>[ 43.150643] random: crng reseeded on system resumption
11467 09:30:00.240451 <6>[ 43.157321] PM: suspend exit
11468 09:30:00.243540 rtcwake: write error
11469 09:30:00.253027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11470 09:30:00.253302 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11472 09:30:00.256541 rtcwake: assuming RTC uses UTC ...
11473 09:30:00.262898 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:07 2023
11474 09:30:00.275599 <6>[ 43.189575] PM: suspend entry (deep)
11475 09:30:00.279146 <6>[ 43.193473] Filesystems sync: 0.000 seconds
11476 09:30:00.282624 <6>[ 43.198487] Freezing user space processes
11477 09:30:00.294077 <6>[ 43.204496] Freezing user space processes completed (elapsed 0.001 seconds)
11478 09:30:00.297459 <6>[ 43.211745] OOM killer disabled.
11479 09:30:00.300495 <6>[ 43.215225] Freezing remaining freezable tasks
11480 09:30:00.320244 <6>[ 43.230758] usb 1-1.1.4: new full-speed USB device number 24 using xhci-mtk
11481 09:30:00.401492 <3>[ 43.314977] usb 1-1.1.4: device descriptor read/64, error -32
11482 09:30:00.593527 <3>[ 43.506952] usb 1-1.1.4: device descriptor read/64, error -32
11483 09:30:00.788831 <6>[ 43.698908] usb 1-1.1.4: new full-speed USB device number 25 using xhci-mtk
11484 09:30:00.873092 <3>[ 43.786944] usb 1-1.1.4: device descriptor read/64, error -32
11485 09:30:01.065327 <3>[ 43.979095] usb 1-1.1.4: device descriptor read/64, error -32
11486 09:30:01.177503 <6>[ 44.091417] usb 1-1.1-port4: attempt power cycle
11487 09:30:01.788117 <6>[ 44.698777] usb 1-1.1.4: new full-speed USB device number 26 using xhci-mtk
11488 09:30:01.794600 <4>[ 44.706170] usb 1-1.1.4: Device not responding to setup address.
11489 09:30:02.005064 <4>[ 44.919158] usb 1-1.1.4: Device not responding to setup address.
11490 09:30:02.217313 <3>[ 45.130926] usb 1-1.1.4: device not accepting address 26, error -71
11491 09:30:02.304390 <6>[ 45.214910] usb 1-1.1.4: new full-speed USB device number 27 using xhci-mtk
11492 09:30:02.310722 <4>[ 45.222295] usb 1-1.1.4: Device not responding to setup address.
11493 09:30:02.520846 <4>[ 45.435144] usb 1-1.1.4: Device not responding to setup address.
11494 09:30:02.735901 <3>[ 45.646896] usb 1-1.1.4: device not accepting address 27, error -71
11495 09:30:02.738998 <3>[ 45.653890] usb 1-1.1-port4: unable to enumerate USB device
11496 09:30:02.757549 <6>[ 45.668179] Freezing remaining freezable tasks completed (elapsed 2.448 seconds)
11497 09:30:02.763896 <6>[ 45.675867] printk: Suspending console(s) (use no_console_suspend to debug)
11498 09:30:06.071147 <6>[ 48.207198] vpu: disabling
11499 09:30:06.074528 <6>[ 48.207332] vproc2: disabling
11500 09:30:06.078020 <6>[ 48.207387] vproc1: disabling
11501 09:30:06.081226 <6>[ 48.207442] vaud18: disabling
11502 09:30:06.084228 <6>[ 48.207689] vsram_others: disabling
11503 09:30:06.087670 <6>[ 48.207891] va09: disabling
11504 09:30:06.090973 <6>[ 48.207970] vsram_md: disabling
11505 09:30:06.094256 <6>[ 48.208100] Vgpu: disabling
11506 09:30:06.101174 <3>[ 48.718928] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11507 09:30:06.110943 <3>[ 48.718962] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11508 09:30:06.120835 <3>[ 48.719006] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11509 09:30:06.127601 <3>[ 48.719049] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11510 09:30:06.133922 <3>[ 48.719392] PM: Some devices failed to suspend, or early wake event detected
11511 09:30:06.137509 <6>[ 49.054809] OOM killer enabled.
11512 09:30:06.145706 <6>[ 49.058208] Restarting tasks ... done.
11513 09:30:06.148886 <5>[ 49.064141] random: crng reseeded on system resumption
11514 09:30:06.152662 <6>[ 49.070327] PM: suspend exit
11515 09:30:06.155926 rtcwake: write error
11516 09:30:06.163186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11517 09:30:06.163442 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11519 09:30:06.166779 rtcwake: assuming RTC uses UTC ...
11520 09:30:06.172920 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:13 2023
11521 09:30:06.185983 <6>[ 49.100438] PM: suspend entry (deep)
11522 09:30:06.190035 <6>[ 49.104369] Filesystems sync: 0.000 seconds
11523 09:30:06.192613 <6>[ 49.109435] Freezing user space processes
11524 09:30:06.204490 <6>[ 49.115301] Freezing user space processes completed (elapsed 0.001 seconds)
11525 09:30:06.207833 <6>[ 49.122521] OOM killer disabled.
11526 09:30:06.210788 <6>[ 49.126001] Freezing remaining freezable tasks
11527 09:30:06.227660 <6>[ 49.138797] usb 1-1.1.4: new full-speed USB device number 28 using xhci-mtk
11528 09:30:06.312342 <3>[ 49.226836] usb 1-1.1.4: device descriptor read/64, error -32
11529 09:30:06.504649 <3>[ 49.419106] usb 1-1.1.4: device descriptor read/64, error -32
11530 09:30:06.699854 <6>[ 49.610772] usb 1-1.1.4: new full-speed USB device number 29 using xhci-mtk
11531 09:30:06.784658 <3>[ 49.699105] usb 1-1.1.4: device descriptor read/64, error -32
11532 09:30:06.977054 <3>[ 49.890949] usb 1-1.1.4: device descriptor read/64, error -32
11533 09:30:07.088990 <6>[ 50.003270] usb 1-1.1-port4: attempt power cycle
11534 09:30:07.699814 <6>[ 50.610905] usb 1-1.1.4: new full-speed USB device number 30 using xhci-mtk
11535 09:30:07.706290 <4>[ 50.618353] usb 1-1.1.4: Device not responding to setup address.
11536 09:30:07.916503 <4>[ 50.831009] usb 1-1.1.4: Device not responding to setup address.
11537 09:30:08.128351 <3>[ 51.042758] usb 1-1.1.4: device not accepting address 30, error -71
11538 09:30:08.215878 <6>[ 51.126766] usb 1-1.1.4: new full-speed USB device number 31 using xhci-mtk
11539 09:30:08.221952 <4>[ 51.134170] usb 1-1.1.4: Device not responding to setup address.
11540 09:30:08.432162 <4>[ 51.347004] usb 1-1.1.4: Device not responding to setup address.
11541 09:30:08.644361 <3>[ 51.558913] usb 1-1.1.4: device not accepting address 31, error -71
11542 09:30:08.651359 <3>[ 51.565929] usb 1-1.1-port4: unable to enumerate USB device
11543 09:30:08.668528 <6>[ 51.580217] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11544 09:30:08.675286 <6>[ 51.587909] printk: Suspending console(s) (use no_console_suspend to debug)
11545 09:30:11.966072 <3>[ 54.606906] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11546 09:30:11.975742 <3>[ 54.606941] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11547 09:30:11.985895 <3>[ 54.606986] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11548 09:30:11.992428 <3>[ 54.607029] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11549 09:30:11.999186 <3>[ 54.607298] PM: Some devices failed to suspend, or early wake event detected
11550 09:30:12.005758 <6>[ 54.920939] OOM killer enabled.
11551 09:30:12.012909 <6>[ 54.924353] Restarting tasks ... done.
11552 09:30:12.016178 <5>[ 54.931433] random: crng reseeded on system resumption
11553 09:30:12.019208 <6>[ 54.937610] PM: suspend exit
11554 09:30:12.022339 rtcwake: write error
11555 09:30:12.030849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11556 09:30:12.031105 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11558 09:30:12.033849 rtcwake: assuming RTC uses UTC ...
11559 09:30:12.040492 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:19 2023
11560 09:30:12.053117 <6>[ 54.968057] PM: suspend entry (deep)
11561 09:30:12.056633 <6>[ 54.971987] Filesystems sync: 0.000 seconds
11562 09:30:12.059433 <6>[ 54.977015] Freezing user space processes
11563 09:30:12.070915 <6>[ 54.982663] Freezing user space processes completed (elapsed 0.001 seconds)
11564 09:30:12.074110 <6>[ 54.989886] OOM killer disabled.
11565 09:30:12.077762 <6>[ 54.993366] Freezing remaining freezable tasks
11566 09:30:12.091468 <6>[ 55.002811] usb 1-1.1.4: new full-speed USB device number 32 using xhci-mtk
11567 09:30:12.175757 <3>[ 55.090790] usb 1-1.1.4: device descriptor read/64, error -32
11568 09:30:12.367964 <3>[ 55.283103] usb 1-1.1.4: device descriptor read/64, error -32
11569 09:30:12.563088 <6>[ 55.474764] usb 1-1.1.4: new full-speed USB device number 33 using xhci-mtk
11570 09:30:12.648142 <3>[ 55.563095] usb 1-1.1.4: device descriptor read/64, error -32
11571 09:30:12.840337 <3>[ 55.754942] usb 1-1.1.4: device descriptor read/64, error -32
11572 09:30:12.952322 <6>[ 55.867273] usb 1-1.1-port4: attempt power cycle
11573 09:30:13.563121 <6>[ 56.474902] usb 1-1.1.4: new full-speed USB device number 34 using xhci-mtk
11574 09:30:13.569398 <4>[ 56.482287] usb 1-1.1.4: Device not responding to setup address.
11575 09:30:13.779441 <4>[ 56.694988] usb 1-1.1.4: Device not responding to setup address.
11576 09:30:13.991388 <3>[ 56.906750] usb 1-1.1.4: device not accepting address 34, error -71
11577 09:30:14.079252 <6>[ 56.990766] usb 1-1.1.4: new full-speed USB device number 35 using xhci-mtk
11578 09:30:14.085214 <4>[ 56.998152] usb 1-1.1.4: Device not responding to setup address.
11579 09:30:14.295588 <4>[ 57.210994] usb 1-1.1.4: Device not responding to setup address.
11580 09:30:14.507945 <3>[ 57.422757] usb 1-1.1.4: device not accepting address 35, error -71
11581 09:30:14.514385 <3>[ 57.429754] usb 1-1.1-port4: unable to enumerate USB device
11582 09:30:14.531930 <6>[ 57.444044] Freezing remaining freezable tasks completed (elapsed 2.445 seconds)
11583 09:30:14.538834 <6>[ 57.451735] printk: Suspending console(s) (use no_console_suspend to debug)
11584 09:30:17.853518 <3>[ 60.494910] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11585 09:30:17.866843 <3>[ 60.494944] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11586 09:30:17.873886 <3>[ 60.494988] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11587 09:30:17.879890 <3>[ 60.495031] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11588 09:30:17.890139 <3>[ 60.495301] PM: Some devices failed to suspend, or early wake event detected
11589 09:30:17.893293 <6>[ 60.808943] OOM killer enabled.
11590 09:30:17.900229 <6>[ 60.812355] Restarting tasks ... done.
11591 09:30:17.903538 <5>[ 60.819796] random: crng reseeded on system resumption
11592 09:30:17.907563 <6>[ 60.826042] PM: suspend exit
11593 09:30:17.910757 rtcwake: write error
11594 09:30:17.918817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11595 09:30:17.919631 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11597 09:30:17.922158 rtcwake: assuming RTC uses UTC ...
11598 09:30:17.928556 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:25 2023
11599 09:30:17.941354 <6>[ 60.856584] PM: suspend entry (deep)
11600 09:30:17.944764 <6>[ 60.860474] Filesystems sync: 0.000 seconds
11601 09:30:17.947908 <6>[ 60.865512] Freezing user space processes
11602 09:30:17.959349 <6>[ 60.871417] Freezing user space processes completed (elapsed 0.001 seconds)
11603 09:30:17.962516 <6>[ 60.878646] OOM killer disabled.
11604 09:30:17.966371 <6>[ 60.882123] Freezing remaining freezable tasks
11605 09:30:17.979191 <6>[ 60.890850] usb 1-1.1.4: new full-speed USB device number 36 using xhci-mtk
11606 09:30:18.063807 <3>[ 60.979261] usb 1-1.1.4: device descriptor read/64, error -32
11607 09:30:18.255884 <3>[ 61.171371] usb 1-1.1.4: device descriptor read/64, error -32
11608 09:30:18.450594 <6>[ 61.362855] usb 1-1.1.4: new full-speed USB device number 37 using xhci-mtk
11609 09:30:18.536206 <3>[ 61.451023] usb 1-1.1.4: device descriptor read/64, error -32
11610 09:30:18.727598 <3>[ 61.642974] usb 1-1.1.4: device descriptor read/64, error -32
11611 09:30:18.839911 <6>[ 61.755158] usb 1-1.1-port4: attempt power cycle
11612 09:30:19.450889 <6>[ 62.362869] usb 1-1.1.4: new full-speed USB device number 38 using xhci-mtk
11613 09:30:19.456618 <4>[ 62.370294] usb 1-1.1.4: Device not responding to setup address.
11614 09:30:19.667502 <4>[ 62.582989] usb 1-1.1.4: Device not responding to setup address.
11615 09:30:19.879402 <3>[ 62.794746] usb 1-1.1.4: device not accepting address 38, error -71
11616 09:30:19.966405 <6>[ 62.878839] usb 1-1.1.4: new full-speed USB device number 39 using xhci-mtk
11617 09:30:19.972824 <4>[ 62.886227] usb 1-1.1.4: Device not responding to setup address.
11618 09:30:20.183245 <4>[ 63.099004] usb 1-1.1.4: Device not responding to setup address.
11619 09:30:20.398107 <3>[ 63.310729] usb 1-1.1.4: device not accepting address 39, error -71
11620 09:30:20.401487 <3>[ 63.317881] usb 1-1.1-port4: unable to enumerate USB device
11621 09:30:20.418827 <6>[ 63.330856] Freezing remaining freezable tasks completed (elapsed 2.444 seconds)
11622 09:30:20.425615 <6>[ 63.338553] printk: Suspending console(s) (use no_console_suspend to debug)
11623 09:30:23.733820 <3>[ 66.382919] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11624 09:30:23.746313 <3>[ 66.382952] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11625 09:30:23.753557 <3>[ 66.382997] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11626 09:30:23.760243 <3>[ 66.383040] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11627 09:30:23.770121 <3>[ 66.383315] PM: Some devices failed to suspend, or early wake event detected
11628 09:30:23.772904 <6>[ 66.689125] OOM killer enabled.
11629 09:30:23.779422 <6>[ 66.692537] Restarting tasks ... done.
11630 09:30:23.782701 <5>[ 66.699203] random: crng reseeded on system resumption
11631 09:30:23.786777 <6>[ 66.705530] PM: suspend exit
11632 09:30:23.789862 rtcwake: write error
11633 09:30:23.798041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11634 09:30:23.798906 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11636 09:30:23.801351 rtcwake: assuming RTC uses UTC ...
11637 09:30:23.807957 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:31 2023
11638 09:30:23.820450 <6>[ 66.736216] PM: suspend entry (deep)
11639 09:30:23.823999 <6>[ 66.740115] Filesystems sync: 0.000 seconds
11640 09:30:23.827380 <6>[ 66.745170] Freezing user space processes
11641 09:30:23.838033 <6>[ 66.750708] Freezing user space processes completed (elapsed 0.001 seconds)
11642 09:30:23.841578 <6>[ 66.757927] OOM killer disabled.
11643 09:30:23.844689 <6>[ 66.761406] Freezing remaining freezable tasks
11644 09:30:23.862343 <6>[ 66.774835] usb 1-1.1.4: new full-speed USB device number 40 using xhci-mtk
11645 09:30:23.947210 <3>[ 66.862981] usb 1-1.1.4: device descriptor read/64, error -32
11646 09:30:24.139422 <3>[ 67.054950] usb 1-1.1.4: device descriptor read/64, error -32
11647 09:30:24.334355 <6>[ 67.246911] usb 1-1.1.4: new full-speed USB device number 41 using xhci-mtk
11648 09:30:24.419188 <3>[ 67.334946] usb 1-1.1.4: device descriptor read/64, error -32
11649 09:30:24.611232 <3>[ 67.527091] usb 1-1.1.4: device descriptor read/64, error -32
11650 09:30:24.723404 <6>[ 67.639413] usb 1-1.1-port4: attempt power cycle
11651 09:30:25.334443 <6>[ 68.246918] usb 1-1.1.4: new full-speed USB device number 42 using xhci-mtk
11652 09:30:25.341053 <4>[ 68.254310] usb 1-1.1.4: Device not responding to setup address.
11653 09:30:25.551481 <4>[ 68.467133] usb 1-1.1.4: Device not responding to setup address.
11654 09:30:25.762780 <3>[ 68.678924] usb 1-1.1.4: device not accepting address 42, error -71
11655 09:30:25.850639 <6>[ 68.762904] usb 1-1.1.4: new full-speed USB device number 43 using xhci-mtk
11656 09:30:25.857172 <4>[ 68.770289] usb 1-1.1.4: Device not responding to setup address.
11657 09:30:26.067279 <4>[ 68.983172] usb 1-1.1.4: Device not responding to setup address.
11658 09:30:26.279200 <3>[ 69.194763] usb 1-1.1.4: device not accepting address 43, error -71
11659 09:30:26.285313 <3>[ 69.201809] usb 1-1.1-port4: unable to enumerate USB device
11660 09:30:26.303272 <6>[ 69.216095] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11661 09:30:26.309661 <6>[ 69.223789] printk: Suspending console(s) (use no_console_suspend to debug)
11662 09:30:29.624866 <3>[ 72.270913] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11663 09:30:29.634981 <3>[ 72.270947] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11664 09:30:29.644296 <3>[ 72.270991] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11665 09:30:29.651319 <3>[ 72.271034] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11666 09:30:29.660821 <3>[ 72.271375] PM: Some devices failed to suspend, or early wake event detected
11667 09:30:29.664053 <6>[ 72.581202] OOM killer enabled.
11668 09:30:29.671436 <6>[ 72.584615] Restarting tasks ... done.
11669 09:30:29.674414 <5>[ 72.591970] random: crng reseeded on system resumption
11670 09:30:29.678862 <6>[ 72.598384] PM: suspend exit
11671 09:30:29.681995 rtcwake: write error
11672 09:30:29.689981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11673 09:30:29.690841 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11675 09:30:29.693086 rtcwake: assuming RTC uses UTC ...
11676 09:30:29.699929 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 20 09:30:37 2023
11677 09:30:29.712366 <6>[ 72.628876] PM: suspend entry (deep)
11678 09:30:29.716046 <6>[ 72.632772] Filesystems sync: 0.000 seconds
11679 09:30:29.719142 <6>[ 72.637803] Freezing user space processes
11680 09:30:29.730662 <6>[ 72.643759] Freezing user space processes completed (elapsed 0.001 seconds)
11681 09:30:29.734275 <6>[ 72.650984] OOM killer disabled.
11682 09:30:29.737023 <6>[ 72.654461] Freezing remaining freezable tasks
11683 09:30:29.753997 <6>[ 72.666809] usb 1-1.1.4: new full-speed USB device number 44 using xhci-mtk
11684 09:30:29.838420 <3>[ 72.754843] usb 1-1.1.4: device descriptor read/64, error -32
11685 09:30:30.030741 <3>[ 72.947099] usb 1-1.1.4: device descriptor read/64, error -32
11686 09:30:30.225806 <6>[ 73.138920] usb 1-1.1.4: new full-speed USB device number 45 using xhci-mtk
11687 09:30:30.311194 <3>[ 73.227110] usb 1-1.1.4: device descriptor read/64, error -32
11688 09:30:30.502435 <3>[ 73.418941] usb 1-1.1.4: device descriptor read/64, error -32
11689 09:30:30.614932 <6>[ 73.531241] usb 1-1.1-port4: attempt power cycle
11690 09:30:31.225666 <6>[ 74.138907] usb 1-1.1.4: new full-speed USB device number 46 using xhci-mtk
11691 09:30:31.232262 <4>[ 74.146306] usb 1-1.1.4: Device not responding to setup address.
11692 09:30:31.442543 <4>[ 74.359088] usb 1-1.1.4: Device not responding to setup address.
11693 09:30:31.654143 <3>[ 74.570913] usb 1-1.1.4: device not accepting address 46, error -71
11694 09:30:31.741508 <6>[ 74.654784] usb 1-1.1.4: new full-speed USB device number 47 using xhci-mtk
11695 09:30:31.747978 <4>[ 74.662179] usb 1-1.1.4: Device not responding to setup address.
11696 09:30:31.958490 <4>[ 74.875098] usb 1-1.1.4: Device not responding to setup address.
11697 09:30:32.169693 <3>[ 75.086769] usb 1-1.1.4: device not accepting address 47, error -71
11698 09:30:32.176886 <3>[ 75.093769] usb 1-1.1-port4: unable to enumerate USB device
11699 09:30:32.187085 <6>[ 75.099889] Freezing remaining freezable tasks completed (elapsed 2.440 seconds)
11700 09:30:32.193967 <6>[ 75.107615] printk: Suspending console(s) (use no_console_suspend to debug)
11701 09:30:35.507516 <3>[ 78.158912] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11702 09:30:35.518056 <3>[ 78.158945] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11703 09:30:35.527857 <3>[ 78.158990] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11704 09:30:35.534604 <3>[ 78.159032] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11705 09:30:35.543980 <3>[ 78.159282] PM: Some devices failed to suspend, or early wake event detected
11706 09:30:35.548042 <6>[ 78.465199] OOM killer enabled.
11707 09:30:35.550802 <6>[ 78.468612] Restarting tasks ... done.
11708 09:30:35.557248 <5>[ 78.474784] random: crng reseeded on system resumption
11709 09:30:35.561205 <6>[ 78.481888] PM: suspend exit
11710 09:30:35.564660 rtcwake: write error
11711 09:30:35.572533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11712 09:30:35.573553 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11714 09:30:35.575955 rtcwake: assuming RTC uses UTC ...
11715 09:30:35.582464 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:30:43 2023
11716 09:30:35.596733 <6>[ 78.514278] PM: suspend entry (s2idle)
11717 09:30:35.600487 <6>[ 78.518418] Filesystems sync: 0.000 seconds
11718 09:30:35.606704 <6>[ 78.523474] Freezing user space processes
11719 09:30:35.613440 <6>[ 78.529452] Freezing user space processes completed (elapsed 0.001 seconds)
11720 09:30:35.616628 <6>[ 78.536681] OOM killer disabled.
11721 09:30:35.623536 <6>[ 78.540161] Freezing remaining freezable tasks
11722 09:30:35.629793 <6>[ 78.546831] usb 1-1.1.4: new full-speed USB device number 48 using xhci-mtk
11723 09:30:35.717622 <3>[ 78.634906] usb 1-1.1.4: device descriptor read/64, error -32
11724 09:30:35.910239 <3>[ 78.827099] usb 1-1.1.4: device descriptor read/64, error -32
11725 09:30:36.104843 <6>[ 79.018773] usb 1-1.1.4: new full-speed USB device number 49 using xhci-mtk
11726 09:30:36.189502 <3>[ 79.107120] usb 1-1.1.4: device descriptor read/64, error -32
11727 09:30:36.381989 <3>[ 79.298944] usb 1-1.1.4: device descriptor read/64, error -32
11728 09:30:36.493849 <6>[ 79.411276] usb 1-1.1-port4: attempt power cycle
11729 09:30:37.104997 <6>[ 80.018770] usb 1-1.1.4: new full-speed USB device number 50 using xhci-mtk
11730 09:30:37.111899 <4>[ 80.026155] usb 1-1.1.4: Device not responding to setup address.
11731 09:30:37.321296 <4>[ 80.238997] usb 1-1.1.4: Device not responding to setup address.
11732 09:30:37.533548 <3>[ 80.450759] usb 1-1.1.4: device not accepting address 50, error -71
11733 09:30:37.620317 <6>[ 80.534768] usb 1-1.1.4: new full-speed USB device number 51 using xhci-mtk
11734 09:30:37.627043 <4>[ 80.542173] usb 1-1.1.4: Device not responding to setup address.
11735 09:30:37.837316 <4>[ 80.754986] usb 1-1.1.4: Device not responding to setup address.
11736 09:30:38.049493 <3>[ 80.966897] usb 1-1.1.4: device not accepting address 51, error -71
11737 09:30:38.056235 <3>[ 80.973843] usb 1-1.1-port4: unable to enumerate USB device
11738 09:30:38.069140 <6>[ 80.983208] Freezing remaining freezable tasks completed (elapsed 2.438 seconds)
11739 09:30:38.075373 <6>[ 80.990896] printk: Suspending console(s) (use no_console_suspend to debug)
11740 09:30:41.399674 <3>[ 84.046912] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11741 09:30:41.409816 <3>[ 84.046945] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11742 09:30:41.419324 <3>[ 84.046989] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11743 09:30:41.426127 <3>[ 84.047031] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11744 09:30:41.432564 <3>[ 84.047372] PM: Some devices failed to suspend, or early wake event detected
11745 09:30:41.439235 <6>[ 84.357066] OOM killer enabled.
11746 09:30:41.446328 <6>[ 84.360475] Restarting tasks ... done.
11747 09:30:41.449451 <5>[ 84.368204] random: crng reseeded on system resumption
11748 09:30:41.453077 <6>[ 84.374341] PM: suspend exit
11749 09:30:41.456295 rtcwake: write error
11750 09:30:41.463673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11751 09:30:41.464465 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11753 09:30:41.467408 rtcwake: assuming RTC uses UTC ...
11754 09:30:41.473691 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:30:49 2023
11755 09:30:41.486741 <6>[ 84.404410] PM: suspend entry (s2idle)
11756 09:30:41.489952 <6>[ 84.408470] Filesystems sync: 0.000 seconds
11757 09:30:41.496507 <6>[ 84.413525] Freezing user space processes
11758 09:30:41.503066 <6>[ 84.419358] Freezing user space processes completed (elapsed 0.001 seconds)
11759 09:30:41.507018 <6>[ 84.426579] OOM killer disabled.
11760 09:30:41.513377 <6>[ 84.430056] Freezing remaining freezable tasks
11761 09:30:41.528589 <6>[ 84.442818] usb 1-1.1.4: new full-speed USB device number 52 using xhci-mtk
11762 09:30:41.613001 <3>[ 84.530869] usb 1-1.1.4: device descriptor read/64, error -32
11763 09:30:41.805315 <3>[ 84.723096] usb 1-1.1.4: device descriptor read/64, error -32
11764 09:30:42.000252 <6>[ 84.914777] usb 1-1.1.4: new full-speed USB device number 53 using xhci-mtk
11765 09:30:42.085506 <3>[ 85.003102] usb 1-1.1.4: device descriptor read/64, error -32
11766 09:30:42.276510 <3>[ 85.194934] usb 1-1.1.4: device descriptor read/64, error -32
11767 09:30:42.389586 <6>[ 85.307267] usb 1-1.1-port4: attempt power cycle
11768 09:30:43.000675 <6>[ 85.914905] usb 1-1.1.4: new full-speed USB device number 54 using xhci-mtk
11769 09:30:43.006847 <4>[ 85.922306] usb 1-1.1.4: Device not responding to setup address.
11770 09:30:43.217347 <4>[ 86.135142] usb 1-1.1.4: Device not responding to setup address.
11771 09:30:43.428569 <3>[ 86.346916] usb 1-1.1.4: device not accepting address 54, error -71
11772 09:30:43.516031 <6>[ 86.430780] usb 1-1.1.4: new full-speed USB device number 55 using xhci-mtk
11773 09:30:43.522866 <4>[ 86.438165] usb 1-1.1.4: Device not responding to setup address.
11774 09:30:43.732649 <4>[ 86.651098] usb 1-1.1.4: Device not responding to setup address.
11775 09:30:43.947562 <3>[ 86.862770] usb 1-1.1.4: device not accepting address 55, error -71
11776 09:30:43.951021 <3>[ 86.869770] usb 1-1.1-port4: unable to enumerate USB device
11777 09:30:43.961049 <6>[ 86.875888] Freezing remaining freezable tasks completed (elapsed 2.441 seconds)
11778 09:30:43.967449 <6>[ 86.883615] printk: Suspending console(s) (use no_console_suspend to debug)
11779 09:30:47.286333 <3>[ 89.934939] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11780 09:30:47.295867 <3>[ 89.934970] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11781 09:30:47.305682 <3>[ 89.935015] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11782 09:30:47.312796 <3>[ 89.935058] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11783 09:30:47.318938 <3>[ 89.935341] PM: Some devices failed to suspend, or early wake event detected
11784 09:30:47.325893 <6>[ 90.244790] OOM killer enabled.
11785 09:30:47.332527 <6>[ 90.248202] Restarting tasks ... done.
11786 09:30:47.339370 <5>[ 90.256313] random: crng reseeded on system resumption
11787 09:30:47.342732 <6>[ 90.262930] PM: suspend exit
11788 09:30:47.342853 rtcwake: write error
11789 09:30:47.352555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11790 09:30:47.353008 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11792 09:30:47.355741 rtcwake: assuming RTC uses UTC ...
11793 09:30:47.362378 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:30:54 2023
11794 09:30:47.375165 <6>[ 90.293921] PM: suspend entry (s2idle)
11795 09:30:47.378862 <6>[ 90.297982] Filesystems sync: 0.000 seconds
11796 09:30:47.385594 <6>[ 90.303230] Freezing user space processes
11797 09:30:47.391963 <6>[ 90.309241] Freezing user space processes completed (elapsed 0.001 seconds)
11798 09:30:47.395134 <6>[ 90.316476] OOM killer disabled.
11799 09:30:47.401916 <6>[ 90.319956] Freezing remaining freezable tasks
11800 09:30:47.415462 <6>[ 90.330847] usb 1-1.1.4: new full-speed USB device number 56 using xhci-mtk
11801 09:30:47.500265 <3>[ 90.418862] usb 1-1.1.4: device descriptor read/64, error -32
11802 09:30:47.692309 <3>[ 90.611127] usb 1-1.1.4: device descriptor read/64, error -32
11803 09:30:47.887850 <6>[ 90.802781] usb 1-1.1.4: new full-speed USB device number 57 using xhci-mtk
11804 09:30:47.972514 <3>[ 90.891096] usb 1-1.1.4: device descriptor read/64, error -32
11805 09:30:48.164541 <3>[ 91.082944] usb 1-1.1.4: device descriptor read/64, error -32
11806 09:30:48.276510 <6>[ 91.195258] usb 1-1.1-port4: attempt power cycle
11807 09:30:48.887232 <6>[ 91.802754] usb 1-1.1.4: new full-speed USB device number 58 using xhci-mtk
11808 09:30:48.893648 <4>[ 91.810177] usb 1-1.1.4: Device not responding to setup address.
11809 09:30:49.104178 <4>[ 92.023265] usb 1-1.1.4: Device not responding to setup address.
11810 09:30:49.315951 <3>[ 92.234760] usb 1-1.1.4: device not accepting address 58, error -71
11811 09:30:49.403776 <6>[ 92.318907] usb 1-1.1.4: new full-speed USB device number 59 using xhci-mtk
11812 09:30:49.409601 <4>[ 92.326315] usb 1-1.1.4: Device not responding to setup address.
11813 09:30:49.620406 <4>[ 92.539137] usb 1-1.1.4: Device not responding to setup address.
11814 09:30:49.832190 <3>[ 92.750897] usb 1-1.1.4: device not accepting address 59, error -71
11815 09:30:49.838911 <3>[ 92.757914] usb 1-1.1-port4: unable to enumerate USB device
11816 09:30:49.849156 <6>[ 92.763995] Freezing remaining freezable tasks completed (elapsed 2.439 seconds)
11817 09:30:49.855460 <6>[ 92.771694] printk: Suspending console(s) (use no_console_suspend to debug)
11818 09:30:53.177753 <3>[ 95.822915] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11819 09:30:53.187624 <3>[ 95.822948] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11820 09:30:53.197785 <3>[ 95.822993] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11821 09:30:53.204521 <3>[ 95.823037] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11822 09:30:53.214080 <3>[ 95.823302] PM: Some devices failed to suspend, or early wake event detected
11823 09:30:53.217795 <6>[ 96.137097] OOM killer enabled.
11824 09:30:53.230469 <6>[ 96.140509] Restarting tasks ... done.
11825 09:30:53.233681 <5>[ 96.153583] random: crng reseeded on system resumption
11826 09:30:53.237067 <6>[ 96.159852] PM: suspend exit
11827 09:30:53.240545 rtcwake: write error
11828 09:30:53.248184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11829 09:30:53.249132 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11831 09:30:53.251624 rtcwake: assuming RTC uses UTC ...
11832 09:30:53.258305 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:00 2023
11833 09:30:53.271114 <6>[ 96.190484] PM: suspend entry (s2idle)
11834 09:30:53.274631 <6>[ 96.194534] Filesystems sync: 0.000 seconds
11835 09:30:53.281269 <6>[ 96.199550] Freezing user space processes
11836 09:30:53.288128 <6>[ 96.205412] Freezing user space processes completed (elapsed 0.001 seconds)
11837 09:30:53.291143 <6>[ 96.212667] OOM killer disabled.
11838 09:30:53.297990 <6>[ 96.216150] Freezing remaining freezable tasks
11839 09:30:53.304599 <6>[ 96.218685] usb 1-1.1.4: new full-speed USB device number 60 using xhci-mtk
11840 09:30:53.387920 <3>[ 96.306994] usb 1-1.1.4: device descriptor read/64, error -32
11841 09:30:53.579514 <3>[ 96.498907] usb 1-1.1.4: device descriptor read/64, error -32
11842 09:30:53.774569 <6>[ 96.690760] usb 1-1.1.4: new full-speed USB device number 61 using xhci-mtk
11843 09:30:53.860091 <3>[ 96.779090] usb 1-1.1.4: device descriptor read/64, error -32
11844 09:30:54.051661 <3>[ 96.970902] usb 1-1.1.4: device descriptor read/64, error -32
11845 09:30:54.163790 <6>[ 97.083210] usb 1-1.1-port4: attempt power cycle
11846 09:30:54.774726 <6>[ 97.690763] usb 1-1.1.4: new full-speed USB device number 62 using xhci-mtk
11847 09:30:54.781134 <4>[ 97.698170] usb 1-1.1.4: Device not responding to setup address.
11848 09:30:54.991295 <4>[ 97.911006] usb 1-1.1.4: Device not responding to setup address.
11849 09:30:55.203391 <3>[ 98.122762] usb 1-1.1.4: device not accepting address 62, error -71
11850 09:30:55.290757 <6>[ 98.206767] usb 1-1.1.4: new full-speed USB device number 63 using xhci-mtk
11851 09:30:55.297590 <4>[ 98.214149] usb 1-1.1.4: Device not responding to setup address.
11852 09:30:55.507248 <4>[ 98.427029] usb 1-1.1.4: Device not responding to setup address.
11853 09:30:55.719399 <3>[ 98.638897] usb 1-1.1.4: device not accepting address 63, error -71
11854 09:30:55.726192 <3>[ 98.645908] usb 1-1.1-port4: unable to enumerate USB device
11855 09:30:55.743957 <6>[ 98.660200] Freezing remaining freezable tasks completed (elapsed 2.439 seconds)
11856 09:30:55.750356 <6>[ 98.667891] printk: Suspending console(s) (use no_console_suspend to debug)
11857 09:30:59.060477 <3>[ 101.710915] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11858 09:30:59.071021 <3>[ 101.710947] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11859 09:30:59.080652 <3>[ 101.710992] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11860 09:30:59.087077 <3>[ 101.711034] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11861 09:30:59.097320 <3>[ 101.711301] PM: Some devices failed to suspend, or early wake event detected
11862 09:30:59.100307 <6>[ 102.020859] OOM killer enabled.
11863 09:30:59.107323 <6>[ 102.024272] Restarting tasks ... done.
11864 09:30:59.109928 <5>[ 102.031523] random: crng reseeded on system resumption
11865 09:30:59.114093 <6>[ 102.037980] PM: suspend exit
11866 09:30:59.117942 rtcwake: write error
11867 09:30:59.125923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11868 09:30:59.126178 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11870 09:30:59.129548 rtcwake: assuming RTC uses UTC ...
11871 09:30:59.136447 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:06 2023
11872 09:30:59.148811 <6>[ 102.068683] PM: suspend entry (s2idle)
11873 09:30:59.152339 <6>[ 102.072749] Filesystems sync: 0.000 seconds
11874 09:30:59.158626 <6>[ 102.077806] Freezing user space processes
11875 09:30:59.165581 <6>[ 102.083740] Freezing user space processes completed (elapsed 0.001 seconds)
11876 09:30:59.168934 <6>[ 102.090967] OOM killer disabled.
11877 09:30:59.175183 <6>[ 102.094445] Freezing remaining freezable tasks
11878 09:30:59.191002 <6>[ 102.106800] usb 1-1.1.4: new full-speed USB device number 64 using xhci-mtk
11879 09:30:59.274740 <3>[ 102.194859] usb 1-1.1.4: device descriptor read/64, error -32
11880 09:30:59.467316 <3>[ 102.387130] usb 1-1.1.4: device descriptor read/64, error -32
11881 09:30:59.662158 <6>[ 102.578781] usb 1-1.1.4: new full-speed USB device number 65 using xhci-mtk
11882 09:30:59.747117 <3>[ 102.667096] usb 1-1.1.4: device descriptor read/64, error -32
11883 09:30:59.939322 <3>[ 102.858938] usb 1-1.1.4: device descriptor read/64, error -32
11884 09:31:00.051535 <6>[ 102.971256] usb 1-1.1-port4: attempt power cycle
11885 09:31:00.662341 <6>[ 103.578906] usb 1-1.1.4: new full-speed USB device number 66 using xhci-mtk
11886 09:31:00.669137 <4>[ 103.586290] usb 1-1.1.4: Device not responding to setup address.
11887 09:31:00.878848 <4>[ 103.799001] usb 1-1.1.4: Device not responding to setup address.
11888 09:31:01.090773 <3>[ 104.010760] usb 1-1.1.4: device not accepting address 66, error -71
11889 09:31:01.178764 <6>[ 104.094759] usb 1-1.1.4: new full-speed USB device number 67 using xhci-mtk
11890 09:31:01.184574 <4>[ 104.102152] usb 1-1.1.4: Device not responding to setup address.
11891 09:31:01.394694 <4>[ 104.314998] usb 1-1.1.4: Device not responding to setup address.
11892 09:31:01.606656 <3>[ 104.526760] usb 1-1.1.4: device not accepting address 67, error -71
11893 09:31:01.613690 <3>[ 104.533770] usb 1-1.1-port4: unable to enumerate USB device
11894 09:31:01.625907 <6>[ 104.542711] Freezing remaining freezable tasks completed (elapsed 2.443 seconds)
11895 09:31:01.632456 <6>[ 104.550409] printk: Suspending console(s) (use no_console_suspend to debug)
11896 09:31:04.953032 <3>[ 107.598909] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11897 09:31:04.962729 <3>[ 107.598942] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11898 09:31:04.972867 <3>[ 107.598987] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11899 09:31:04.979288 <3>[ 107.599035] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11900 09:31:04.989108 <3>[ 107.599302] PM: Some devices failed to suspend, or early wake event detected
11901 09:31:04.992302 <6>[ 107.913131] OOM killer enabled.
11902 09:31:04.995686 <6>[ 107.916543] Restarting tasks ... done.
11903 09:31:05.002921 <5>[ 107.922546] random: crng reseeded on system resumption
11904 09:31:05.006225 <6>[ 107.929284] PM: suspend exit
11905 09:31:05.008760 rtcwake: write error
11906 09:31:05.017390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11907 09:31:05.018214 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11909 09:31:05.020409 rtcwake: assuming RTC uses UTC ...
11910 09:31:05.027533 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:12 2023
11911 09:31:05.039996 <6>[ 107.960540] PM: suspend entry (s2idle)
11912 09:31:05.043468 <6>[ 107.964609] Filesystems sync: 0.000 seconds
11913 09:31:05.049528 <6>[ 107.969624] Freezing user space processes
11914 09:31:05.056356 <6>[ 107.975432] Freezing user space processes completed (elapsed 0.001 seconds)
11915 09:31:05.060204 <6>[ 107.982652] OOM killer disabled.
11916 09:31:05.066233 <6>[ 107.986129] Freezing remaining freezable tasks
11917 09:31:05.077262 <6>[ 107.994844] usb 1-1.1.4: new full-speed USB device number 68 using xhci-mtk
11918 09:31:05.162361 <3>[ 108.082950] usb 1-1.1.4: device descriptor read/64, error -32
11919 09:31:05.354836 <3>[ 108.275162] usb 1-1.1.4: device descriptor read/64, error -32
11920 09:31:05.549394 <6>[ 108.466811] usb 1-1.1.4: new full-speed USB device number 69 using xhci-mtk
11921 09:31:05.634917 <3>[ 108.554974] usb 1-1.1.4: device descriptor read/64, error -32
11922 09:31:05.827109 <3>[ 108.747126] usb 1-1.1.4: device descriptor read/64, error -32
11923 09:31:05.938530 <6>[ 108.859196] usb 1-1.1-port4: attempt power cycle
11924 09:31:06.549346 <6>[ 109.466760] usb 1-1.1.4: new full-speed USB device number 70 using xhci-mtk
11925 09:31:06.556293 <4>[ 109.474368] usb 1-1.1.4: Device not responding to setup address.
11926 09:31:06.766048 <4>[ 109.686920] usb 1-1.1.4: Device not responding to setup address.
11927 09:31:06.977631 <3>[ 109.898714] usb 1-1.1.4: device not accepting address 70, error -71
11928 09:31:07.065332 <6>[ 109.982812] usb 1-1.1.4: new full-speed USB device number 71 using xhci-mtk
11929 09:31:07.071764 <4>[ 109.990210] usb 1-1.1.4: Device not responding to setup address.
11930 09:31:07.282418 <4>[ 110.202928] usb 1-1.1.4: Device not responding to setup address.
11931 09:31:07.494611 <3>[ 110.415186] usb 1-1.1.4: device not accepting address 71, error -71
11932 09:31:07.501513 <3>[ 110.422116] usb 1-1.1-port4: unable to enumerate USB device
11933 09:31:07.517730 <6>[ 110.434836] Freezing remaining freezable tasks completed (elapsed 2.444 seconds)
11934 09:31:07.524004 <6>[ 110.442530] printk: Suspending console(s) (use no_console_suspend to debug)
11935 09:31:10.835526 <3>[ 113.486897] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11936 09:31:10.846376 <3>[ 113.486928] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11937 09:31:10.855894 <3>[ 113.486972] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11938 09:31:10.862358 <3>[ 113.487013] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11939 09:31:10.868934 <3>[ 113.487243] PM: Some devices failed to suspend, or early wake event detected
11940 09:31:10.875829 <6>[ 113.796698] OOM killer enabled.
11941 09:31:10.884775 <6>[ 113.800109] Restarting tasks ... done.
11942 09:31:10.888676 <5>[ 113.810033] random: crng reseeded on system resumption
11943 09:31:10.892694 <6>[ 113.817108] PM: suspend exit
11944 09:31:10.896459 rtcwake: write error
11945 09:31:10.904225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11946 09:31:10.905133 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11948 09:31:10.907418 rtcwake: assuming RTC uses UTC ...
11949 09:31:10.913885 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:18 2023
11950 09:31:10.927464 <6>[ 113.848138] PM: suspend entry (s2idle)
11951 09:31:10.930858 <6>[ 113.852199] Filesystems sync: 0.000 seconds
11952 09:31:10.936732 <6>[ 113.857241] Freezing user space processes
11953 09:31:10.943433 <6>[ 113.862781] Freezing user space processes completed (elapsed 0.001 seconds)
11954 09:31:10.946739 <6>[ 113.869997] OOM killer disabled.
11955 09:31:10.953616 <6>[ 113.873477] Freezing remaining freezable tasks
11956 09:31:10.964989 <6>[ 113.882803] usb 1-1.1.4: new full-speed USB device number 72 using xhci-mtk
11957 09:31:11.049591 <3>[ 113.970865] usb 1-1.1.4: device descriptor read/64, error -32
11958 09:31:11.241822 <3>[ 114.163146] usb 1-1.1.4: device descriptor read/64, error -32
11959 09:31:11.436809 <6>[ 114.354763] usb 1-1.1.4: new full-speed USB device number 73 using xhci-mtk
11960 09:31:11.521991 <3>[ 114.443099] usb 1-1.1.4: device descriptor read/64, error -32
11961 09:31:11.714207 <3>[ 114.634927] usb 1-1.1.4: device descriptor read/64, error -32
11962 09:31:11.826188 <6>[ 114.747266] usb 1-1.1-port4: attempt power cycle
11963 09:31:12.437234 <6>[ 115.354909] usb 1-1.1.4: new full-speed USB device number 74 using xhci-mtk
11964 09:31:12.443276 <4>[ 115.362296] usb 1-1.1.4: Device not responding to setup address.
11965 09:31:12.653475 <4>[ 115.575163] usb 1-1.1.4: Device not responding to setup address.
11966 09:31:12.865489 <3>[ 115.786932] usb 1-1.1.4: device not accepting address 74, error -71
11967 09:31:12.952954 <6>[ 115.870778] usb 1-1.1.4: new full-speed USB device number 75 using xhci-mtk
11968 09:31:12.959265 <4>[ 115.878237] usb 1-1.1.4: Device not responding to setup address.
11969 09:31:13.169629 <4>[ 116.091160] usb 1-1.1.4: Device not responding to setup address.
11970 09:31:13.381425 <3>[ 116.302913] usb 1-1.1.4: device not accepting address 75, error -71
11971 09:31:13.388650 <3>[ 116.309930] usb 1-1.1-port4: unable to enumerate USB device
11972 09:31:13.398309 <6>[ 116.316031] Freezing remaining freezable tasks completed (elapsed 2.437 seconds)
11973 09:31:13.404888 <6>[ 116.323759] printk: Suspending console(s) (use no_console_suspend to debug)
11974 09:31:16.723055 <3>[ 119.374929] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11975 09:31:16.732998 <3>[ 119.374961] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11976 09:31:16.742697 <3>[ 119.375006] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11977 09:31:16.749411 <3>[ 119.375048] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11978 09:31:16.759195 <3>[ 119.375322] PM: Some devices failed to suspend, or early wake event detected
11979 09:31:16.762622 <6>[ 119.684875] OOM killer enabled.
11980 09:31:16.765831 <6>[ 119.688288] Restarting tasks ... done.
11981 09:31:16.772926 <5>[ 119.694268] random: crng reseeded on system resumption
11982 09:31:16.777487 <6>[ 119.702296] PM: suspend exit
11983 09:31:16.780240 rtcwake: write error
11984 09:31:16.787952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11985 09:31:16.788720 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11987 09:31:16.791450 rtcwake: assuming RTC uses UTC ...
11988 09:31:16.798049 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:24 2023
11989 09:31:16.811096 <6>[ 119.732763] PM: suspend entry (s2idle)
11990 09:31:16.814119 <6>[ 119.736824] Filesystems sync: 0.000 seconds
11991 09:31:16.820775 <6>[ 119.741884] Freezing user space processes
11992 09:31:16.827192 <6>[ 119.747795] Freezing user space processes completed (elapsed 0.001 seconds)
11993 09:31:16.830652 <6>[ 119.755025] OOM killer disabled.
11994 09:31:16.837029 <6>[ 119.758502] Freezing remaining freezable tasks
11995 09:31:16.852416 <6>[ 119.770791] usb 1-1.1.4: new full-speed USB device number 76 using xhci-mtk
11996 09:31:16.936630 <3>[ 119.858858] usb 1-1.1.4: device descriptor read/64, error -32
11997 09:31:17.129284 <3>[ 120.050931] usb 1-1.1.4: device descriptor read/64, error -32
11998 09:31:17.324147 <6>[ 120.242915] usb 1-1.1.4: new full-speed USB device number 77 using xhci-mtk
11999 09:31:17.408821 <3>[ 120.330938] usb 1-1.1.4: device descriptor read/64, error -32
12000 09:31:17.601438 <3>[ 120.523097] usb 1-1.1.4: device descriptor read/64, error -32
12001 09:31:17.713858 <6>[ 120.635415] usb 1-1.1-port4: attempt power cycle
12002 09:31:18.324162 <6>[ 121.242909] usb 1-1.1.4: new full-speed USB device number 78 using xhci-mtk
12003 09:31:18.331124 <4>[ 121.250403] usb 1-1.1.4: Device not responding to setup address.
12004 09:31:18.541633 <4>[ 121.463131] usb 1-1.1.4: Device not responding to setup address.
12005 09:31:18.752752 <3>[ 121.674897] usb 1-1.1.4: device not accepting address 78, error -71
12006 09:31:18.840008 <6>[ 121.758911] usb 1-1.1.4: new full-speed USB device number 79 using xhci-mtk
12007 09:31:18.846122 <4>[ 121.766312] usb 1-1.1.4: Device not responding to setup address.
12008 09:31:19.056862 <4>[ 121.978976] usb 1-1.1.4: Device not responding to setup address.
12009 09:31:19.268520 <3>[ 122.190761] usb 1-1.1.4: device not accepting address 79, error -71
12010 09:31:19.275964 <3>[ 122.197759] usb 1-1.1-port4: unable to enumerate USB device
12011 09:31:19.285404 <6>[ 122.204334] Freezing remaining freezable tasks completed (elapsed 2.441 seconds)
12012 09:31:19.291805 <6>[ 122.212024] printk: Suspending console(s) (use no_console_suspend to debug)
12013 09:31:22.610914 <3>[ 125.262955] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
12014 09:31:22.620562 <3>[ 125.262990] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12015 09:31:22.630853 <3>[ 125.263043] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12016 09:31:22.637481 <3>[ 125.263090] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12017 09:31:22.644032 <3>[ 125.263220] PM: Some devices failed to suspend, or early wake event detected
12018 09:31:22.650568 <6>[ 125.573087] OOM killer enabled.
12019 09:31:22.653443 <6>[ 125.576499] Restarting tasks ... done.
12020 09:31:22.660779 <5>[ 125.582531] random: crng reseeded on system resumption
12021 09:31:22.663959 <6>[ 125.588891] PM: suspend exit
12022 09:31:22.667039 rtcwake: write error
12023 09:31:22.674850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
12024 09:31:22.675870 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
12026 09:31:22.678031 rtcwake: assuming RTC uses UTC ...
12027 09:31:22.684315 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:30 2023
12028 09:31:22.697164 <6>[ 125.619573] PM: suspend entry (s2idle)
12029 09:31:22.700298 <6>[ 125.623651] Filesystems sync: 0.000 seconds
12030 09:31:22.707045 <6>[ 125.628720] Freezing user space processes
12031 09:31:22.713974 <6>[ 125.634615] Freezing user space processes completed (elapsed 0.001 seconds)
12032 09:31:22.717302 <6>[ 125.641841] OOM killer disabled.
12033 09:31:22.724042 <6>[ 125.645322] Freezing remaining freezable tasks
12034 09:31:22.735704 <6>[ 125.654852] usb 1-1.1.4: new full-speed USB device number 80 using xhci-mtk
12035 09:31:22.820497 <3>[ 125.742802] usb 1-1.1.4: device descriptor read/64, error -32
12036 09:31:23.012825 <3>[ 125.935109] usb 1-1.1.4: device descriptor read/64, error -32
12037 09:31:23.207560 <6>[ 126.126916] usb 1-1.1.4: new full-speed USB device number 81 using xhci-mtk
12038 09:31:23.292397 <3>[ 126.215106] usb 1-1.1.4: device descriptor read/64, error -32
12039 09:31:23.484696 <3>[ 126.406941] usb 1-1.1.4: device descriptor read/64, error -32
12040 09:31:23.597170 <6>[ 126.519416] usb 1-1.1-port4: attempt power cycle
12041 09:31:24.207786 <6>[ 127.126907] usb 1-1.1.4: new full-speed USB device number 82 using xhci-mtk
12042 09:31:24.213864 <4>[ 127.134308] usb 1-1.1.4: Device not responding to setup address.
12043 09:31:24.424127 <4>[ 127.347127] usb 1-1.1.4: Device not responding to setup address.
12044 09:31:24.635982 <3>[ 127.558754] usb 1-1.1.4: device not accepting address 82, error -71
12045 09:31:24.723519 <6>[ 127.642771] usb 1-1.1.4: new full-speed USB device number 83 using xhci-mtk
12046 09:31:24.729628 <4>[ 127.650172] usb 1-1.1.4: Device not responding to setup address.
12047 09:31:24.940416 <4>[ 127.862990] usb 1-1.1.4: Device not responding to setup address.
12048 09:31:25.152368 <3>[ 128.074760] usb 1-1.1.4: device not accepting address 83, error -71
12049 09:31:25.158695 <3>[ 128.081773] usb 1-1.1-port4: unable to enumerate USB device
12050 09:31:25.171102 <6>[ 128.090643] Freezing remaining freezable tasks completed (elapsed 2.440 seconds)
12051 09:31:25.178221 <6>[ 128.098320] printk: Suspending console(s) (use no_console_suspend to debug)
12052 09:31:28.497887 <3>[ 131.150917] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
12053 09:31:28.508026 <3>[ 131.150949] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12054 09:31:28.517443 <3>[ 131.150994] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12055 09:31:28.524472 <3>[ 131.151036] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12056 09:31:28.531125 <3>[ 131.151308] PM: Some devices failed to suspend, or early wake event detected
12057 09:31:28.537525 <6>[ 131.461071] OOM killer enabled.
12058 09:31:28.541291 <6>[ 131.464506] Restarting tasks ... done.
12059 09:31:28.548167 <5>[ 131.470569] random: crng reseeded on system resumption
12060 09:31:28.550921 <6>[ 131.477134] PM: suspend exit
12061 09:31:28.554225 rtcwake: write error
12062 09:31:28.561863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
12063 09:31:28.562600 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
12065 09:31:28.565172 rtcwake: assuming RTC uses UTC ...
12066 09:31:28.571622 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 20 09:31:36 2023
12067 09:31:28.584935 <6>[ 131.508120] PM: suspend entry (s2idle)
12068 09:31:28.588042 <6>[ 131.512188] Filesystems sync: 0.000 seconds
12069 09:31:28.594703 <6>[ 131.517199] Freezing user space processes
12070 09:31:28.601283 <6>[ 131.522735] Freezing user space processes completed (elapsed 0.001 seconds)
12071 09:31:28.604533 <6>[ 131.529952] OOM killer disabled.
12072 09:31:28.610974 <6>[ 131.533432] Freezing remaining freezable tasks
12073 09:31:28.626473 <6>[ 131.546754] usb 1-1.1.4: new full-speed USB device number 84 using xhci-mtk
12074 09:31:28.711380 <3>[ 131.634993] usb 1-1.1.4: device descriptor read/64, error -32
12075 09:31:28.903848 <3>[ 131.826953] usb 1-1.1.4: device descriptor read/64, error -32
12076 09:31:29.098686 <6>[ 132.018772] usb 1-1.1.4: new full-speed USB device number 85 using xhci-mtk
12077 09:31:29.183607 <3>[ 132.106953] usb 1-1.1.4: device descriptor read/64, error -32
12078 09:31:29.376372 <3>[ 132.299091] usb 1-1.1.4: device descriptor read/64, error -32
12079 09:31:29.488012 <6>[ 132.411268] usb 1-1.1-port4: attempt power cycle
12080 09:31:30.098719 <6>[ 133.018770] usb 1-1.1.4: new full-speed USB device number 86 using xhci-mtk
12081 09:31:30.105017 <4>[ 133.026180] usb 1-1.1.4: Device not responding to setup address.
12082 09:31:30.316039 <4>[ 133.238997] usb 1-1.1.4: Device not responding to setup address.
12083 09:31:30.527464 <3>[ 133.450744] usb 1-1.1.4: device not accepting address 86, error -71
12084 09:31:30.614733 <6>[ 133.534906] usb 1-1.1.4: new full-speed USB device number 87 using xhci-mtk
12085 09:31:30.621254 <4>[ 133.542290] usb 1-1.1.4: Device not responding to setup address.
12086 09:31:30.831220 <4>[ 133.755017] usb 1-1.1.4: Device not responding to setup address.
12087 09:31:31.042858 <3>[ 133.966761] usb 1-1.1.4: device not accepting address 87, error -71
12088 09:31:31.050209 <3>[ 133.973772] usb 1-1.1-port4: unable to enumerate USB device
12089 09:31:31.060408 <6>[ 133.980847] Freezing remaining freezable tasks completed (elapsed 2.442 seconds)
12090 09:31:31.067040 <6>[ 133.988576] printk: Suspending console(s) (use no_console_suspend to debug)
12091 09:31:34.384522 <3>[ 137.038912] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
12092 09:31:34.397605 <3>[ 137.038946] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12093 09:31:34.404515 <3>[ 137.038990] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12094 09:31:34.411541 <3>[ 137.039033] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12095 09:31:34.421636 <3>[ 137.039361] PM: Some devices failed to suspend, or early wake event detected
12096 09:31:34.424621 <6>[ 137.348900] OOM killer enabled.
12097 09:31:34.428080 <6>[ 137.352305] Restarting tasks ... done.
12098 09:31:34.435039 <5>[ 137.358195] random: crng reseeded on system resumption
12099 09:31:34.438001 <6>[ 137.364691] PM: suspend exit
12100 09:31:34.441073 rtcwake: write error
12101 09:31:34.448739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
12102 09:31:34.449496 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
12104 09:31:34.451754 + set +x
12105 09:31:34.454767 <LAVA_SIGNAL_ENDRUN 0_sleep 11826806_1.5.2.3.1>
12106 09:31:34.455240 <LAVA_TEST_RUNNER EXIT>
12107 09:31:34.455854 Received signal: <ENDRUN> 0_sleep 11826806_1.5.2.3.1
12108 09:31:34.456252 Ending use of test pattern.
12109 09:31:34.456582 Ending test lava.0_sleep (11826806_1.5.2.3.1), duration 115.33
12111 09:31:34.457827 ok: lava_test_shell seems to have completed
12112 09:31:34.458799 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
12113 09:31:34.459284 end: 3.1 lava-test-shell (duration 00:01:56) [common]
12114 09:31:34.459785 end: 3 lava-test-retry (duration 00:01:56) [common]
12115 09:31:34.460289 start: 4 finalize (timeout 00:05:37) [common]
12116 09:31:34.460752 start: 4.1 power-off (timeout 00:00:30) [common]
12117 09:31:34.461537 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12118 09:31:34.582576 >> Command sent successfully.
12119 09:31:34.594203 Returned 0 in 0 seconds
12120 09:31:34.695521 end: 4.1 power-off (duration 00:00:00) [common]
12122 09:31:34.697142 start: 4.2 read-feedback (timeout 00:05:37) [common]
12123 09:31:34.698584 Listened to connection for namespace 'common' for up to 1s
12125 09:31:34.699836 Listened to connection for namespace 'common' for up to 1s
12126 09:31:35.699068 Finalising connection for namespace 'common'
12127 09:31:35.699902 Disconnecting from shell: Finalise
12128 09:31:35.800923 end: 4.2 read-feedback (duration 00:00:01) [common]
12129 09:31:35.801697 end: 4 finalize (duration 00:00:01) [common]
12130 09:31:35.802320 Cleaning after the job
12131 09:31:35.802994 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/ramdisk
12132 09:31:35.843460 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/kernel
12133 09:31:35.871180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/dtb
12134 09:31:35.871420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826806/tftp-deploy-u1ub0oxe/modules
12135 09:31:35.878763 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826806
12136 09:31:36.053773 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826806
12137 09:31:36.053955 Job finished correctly