Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Kernel Errors: 33
- Errors: 1
- Boot result: PASS
1 09:30:24.788269 lava-dispatcher, installed at version: 2023.08
2 09:30:24.788490 start: 0 validate
3 09:30:24.788620 Start time: 2023-10-20 09:30:24.788611+00:00 (UTC)
4 09:30:24.788737 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:30:24.788906 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:30:25.057490 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:30:25.057668 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:30:25.323610 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:30:25.323803 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:30:25.590757 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:30:25.590963 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.58-cip7%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:30:26.122404 validate duration: 1.33
14 09:30:26.122768 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:30:26.122897 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:30:26.123022 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:30:26.123225 Not decompressing ramdisk as can be used compressed.
18 09:30:26.123312 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 09:30:26.123377 saving as /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/ramdisk/rootfs.cpio.gz
20 09:30:26.123482 total size: 26246609 (25 MB)
21 09:30:26.124681 progress 0 % (0 MB)
22 09:30:26.132662 progress 5 % (1 MB)
23 09:30:26.139855 progress 10 % (2 MB)
24 09:30:26.147510 progress 15 % (3 MB)
25 09:30:26.154839 progress 20 % (5 MB)
26 09:30:26.162109 progress 25 % (6 MB)
27 09:30:26.169683 progress 30 % (7 MB)
28 09:30:26.176952 progress 35 % (8 MB)
29 09:30:26.184033 progress 40 % (10 MB)
30 09:30:26.191275 progress 45 % (11 MB)
31 09:30:26.198328 progress 50 % (12 MB)
32 09:30:26.205509 progress 55 % (13 MB)
33 09:30:26.212589 progress 60 % (15 MB)
34 09:30:26.219673 progress 65 % (16 MB)
35 09:30:26.226959 progress 70 % (17 MB)
36 09:30:26.234068 progress 75 % (18 MB)
37 09:30:26.241111 progress 80 % (20 MB)
38 09:30:26.248276 progress 85 % (21 MB)
39 09:30:26.255264 progress 90 % (22 MB)
40 09:30:26.262217 progress 95 % (23 MB)
41 09:30:26.269220 progress 100 % (25 MB)
42 09:30:26.269518 25 MB downloaded in 0.15 s (171.39 MB/s)
43 09:30:26.269733 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:30:26.270127 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:30:26.270246 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:30:26.270363 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:30:26.270533 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:30:26.270631 saving as /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/kernel/Image
50 09:30:26.270722 total size: 49236480 (46 MB)
51 09:30:26.270813 No compression specified
52 09:30:26.271978 progress 0 % (0 MB)
53 09:30:26.285093 progress 5 % (2 MB)
54 09:30:26.298473 progress 10 % (4 MB)
55 09:30:26.311713 progress 15 % (7 MB)
56 09:30:26.325005 progress 20 % (9 MB)
57 09:30:26.338172 progress 25 % (11 MB)
58 09:30:26.351510 progress 30 % (14 MB)
59 09:30:26.364720 progress 35 % (16 MB)
60 09:30:26.378421 progress 40 % (18 MB)
61 09:30:26.392006 progress 45 % (21 MB)
62 09:30:26.405200 progress 50 % (23 MB)
63 09:30:26.418524 progress 55 % (25 MB)
64 09:30:26.431807 progress 60 % (28 MB)
65 09:30:26.445126 progress 65 % (30 MB)
66 09:30:26.458399 progress 70 % (32 MB)
67 09:30:26.471481 progress 75 % (35 MB)
68 09:30:26.484865 progress 80 % (37 MB)
69 09:30:26.498101 progress 85 % (39 MB)
70 09:30:26.511263 progress 90 % (42 MB)
71 09:30:26.524219 progress 95 % (44 MB)
72 09:30:26.536917 progress 100 % (46 MB)
73 09:30:26.537151 46 MB downloaded in 0.27 s (176.24 MB/s)
74 09:30:26.537303 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:30:26.537534 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:30:26.537621 start: 1.3 download-retry (timeout 00:10:00) [common]
78 09:30:26.537709 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 09:30:26.537852 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:30:26.537921 saving as /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/dtb/mt8192-asurada-spherion-r0.dtb
81 09:30:26.537982 total size: 47278 (0 MB)
82 09:30:26.538042 No compression specified
83 09:30:26.539209 progress 69 % (0 MB)
84 09:30:26.539479 progress 100 % (0 MB)
85 09:30:26.539632 0 MB downloaded in 0.00 s (27.37 MB/s)
86 09:30:26.539754 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:30:26.539974 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:30:26.540057 start: 1.4 download-retry (timeout 00:10:00) [common]
90 09:30:26.540139 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 09:30:26.540250 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.58-cip7/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:30:26.540317 saving as /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/modules/modules.tar
93 09:30:26.540377 total size: 8614716 (8 MB)
94 09:30:26.540437 Using unxz to decompress xz
95 09:30:26.545122 progress 0 % (0 MB)
96 09:30:26.566714 progress 5 % (0 MB)
97 09:30:26.590975 progress 10 % (0 MB)
98 09:30:26.615409 progress 15 % (1 MB)
99 09:30:26.639594 progress 20 % (1 MB)
100 09:30:26.664392 progress 25 % (2 MB)
101 09:30:26.690796 progress 30 % (2 MB)
102 09:30:26.717479 progress 35 % (2 MB)
103 09:30:26.741272 progress 40 % (3 MB)
104 09:30:26.767890 progress 45 % (3 MB)
105 09:30:26.793690 progress 50 % (4 MB)
106 09:30:26.818491 progress 55 % (4 MB)
107 09:30:26.843709 progress 60 % (4 MB)
108 09:30:26.869951 progress 65 % (5 MB)
109 09:30:26.897314 progress 70 % (5 MB)
110 09:30:26.921460 progress 75 % (6 MB)
111 09:30:26.949614 progress 80 % (6 MB)
112 09:30:26.976053 progress 85 % (7 MB)
113 09:30:27.001237 progress 90 % (7 MB)
114 09:30:27.031423 progress 95 % (7 MB)
115 09:30:27.060013 progress 100 % (8 MB)
116 09:30:27.066415 8 MB downloaded in 0.53 s (15.62 MB/s)
117 09:30:27.066677 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:30:27.066946 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:30:27.067053 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:30:27.067189 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:30:27.067274 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:30:27.067374 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:30:27.067656 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70
125 09:30:27.067789 makedir: /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin
126 09:30:27.067894 makedir: /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/tests
127 09:30:27.067993 makedir: /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/results
128 09:30:27.068107 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-add-keys
129 09:30:27.068254 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-add-sources
130 09:30:27.068386 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-background-process-start
131 09:30:27.068517 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-background-process-stop
132 09:30:27.068643 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-common-functions
133 09:30:27.068768 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-echo-ipv4
134 09:30:27.068892 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-install-packages
135 09:30:27.069016 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-installed-packages
136 09:30:27.069140 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-os-build
137 09:30:27.069265 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-probe-channel
138 09:30:27.069398 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-probe-ip
139 09:30:27.069522 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-target-ip
140 09:30:27.069644 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-target-mac
141 09:30:27.069767 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-target-storage
142 09:30:27.069894 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-case
143 09:30:27.070016 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-event
144 09:30:27.070137 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-feedback
145 09:30:27.070259 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-raise
146 09:30:27.070382 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-reference
147 09:30:27.070506 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-runner
148 09:30:27.070628 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-set
149 09:30:27.070753 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-test-shell
150 09:30:27.070878 Updating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-install-packages (oe)
151 09:30:27.071038 Updating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/bin/lava-installed-packages (oe)
152 09:30:27.071215 Creating /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/environment
153 09:30:27.071328 LAVA metadata
154 09:30:27.071469 - LAVA_JOB_ID=11826819
155 09:30:27.071561 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:30:27.071693 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:30:27.071785 skipped lava-vland-overlay
158 09:30:27.071887 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:30:27.071999 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:30:27.072090 skipped lava-multinode-overlay
161 09:30:27.072200 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:30:27.072319 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:30:27.072394 Loading test definitions
164 09:30:27.072487 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:30:27.072560 Using /lava-11826819 at stage 0
166 09:30:27.072866 uuid=11826819_1.5.2.3.1 testdef=None
167 09:30:27.072952 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:30:27.073036 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:30:27.073723 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:30:27.074091 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:30:27.075082 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:30:27.075326 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:30:27.075935 runner path: /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/0/tests/0_v4l2-compliance-uvc test_uuid 11826819_1.5.2.3.1
176 09:30:27.076096 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:30:27.076295 Creating lava-test-runner.conf files
179 09:30:27.076356 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11826819/lava-overlay-1ngi2y70/lava-11826819/0 for stage 0
180 09:30:27.076443 - 0_v4l2-compliance-uvc
181 09:30:27.076537 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:30:27.076617 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:30:27.083474 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:30:27.083578 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:30:27.083665 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:30:27.083747 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:30:27.083833 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:30:27.823377 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:30:27.823763 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:30:27.823882 extracting modules file /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11826819/extract-overlay-ramdisk-h248wd61/ramdisk
191 09:30:28.073128 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:30:28.073283 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 09:30:28.073375 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826819/compress-overlay-64ecdht5/overlay-1.5.2.4.tar.gz to ramdisk
194 09:30:28.073446 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11826819/compress-overlay-64ecdht5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11826819/extract-overlay-ramdisk-h248wd61/ramdisk
195 09:30:28.080102 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:30:28.080209 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 09:30:28.080309 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:30:28.080403 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 09:30:28.080485 Building ramdisk /var/lib/lava/dispatcher/tmp/11826819/extract-overlay-ramdisk-h248wd61/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11826819/extract-overlay-ramdisk-h248wd61/ramdisk
200 09:30:28.738162 >> 228396 blocks
201 09:30:32.776852 rename /var/lib/lava/dispatcher/tmp/11826819/extract-overlay-ramdisk-h248wd61/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/ramdisk/ramdisk.cpio.gz
202 09:30:32.777297 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:30:32.777418 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 09:30:32.777526 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 09:30:32.777628 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/kernel/Image'
206 09:30:44.917240 Returned 0 in 12 seconds
207 09:30:45.018383 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/kernel/image.itb
208 09:30:45.652845 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:30:45.653199 output: Created: Fri Oct 20 10:30:45 2023
210 09:30:45.653271 output: Image 0 (kernel-1)
211 09:30:45.653338 output: Description:
212 09:30:45.653400 output: Created: Fri Oct 20 10:30:45 2023
213 09:30:45.653463 output: Type: Kernel Image
214 09:30:45.653525 output: Compression: lzma compressed
215 09:30:45.653586 output: Data Size: 11044258 Bytes = 10785.41 KiB = 10.53 MiB
216 09:30:45.653647 output: Architecture: AArch64
217 09:30:45.653719 output: OS: Linux
218 09:30:45.653810 output: Load Address: 0x00000000
219 09:30:45.653872 output: Entry Point: 0x00000000
220 09:30:45.653928 output: Hash algo: crc32
221 09:30:45.653982 output: Hash value: 05d3904e
222 09:30:45.654035 output: Image 1 (fdt-1)
223 09:30:45.654090 output: Description: mt8192-asurada-spherion-r0
224 09:30:45.654143 output: Created: Fri Oct 20 10:30:45 2023
225 09:30:45.654195 output: Type: Flat Device Tree
226 09:30:45.654247 output: Compression: uncompressed
227 09:30:45.654299 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:30:45.654351 output: Architecture: AArch64
229 09:30:45.654403 output: Hash algo: crc32
230 09:30:45.654454 output: Hash value: cc4352de
231 09:30:45.654506 output: Image 2 (ramdisk-1)
232 09:30:45.654558 output: Description: unavailable
233 09:30:45.654610 output: Created: Fri Oct 20 10:30:45 2023
234 09:30:45.654662 output: Type: RAMDisk Image
235 09:30:45.654713 output: Compression: Unknown Compression
236 09:30:45.654765 output: Data Size: 39353990 Bytes = 38431.63 KiB = 37.53 MiB
237 09:30:45.654816 output: Architecture: AArch64
238 09:30:45.654868 output: OS: Linux
239 09:30:45.654919 output: Load Address: unavailable
240 09:30:45.654971 output: Entry Point: unavailable
241 09:30:45.655022 output: Hash algo: crc32
242 09:30:45.655080 output: Hash value: fb3a16bd
243 09:30:45.655133 output: Default Configuration: 'conf-1'
244 09:30:45.655185 output: Configuration 0 (conf-1)
245 09:30:45.655237 output: Description: mt8192-asurada-spherion-r0
246 09:30:45.655288 output: Kernel: kernel-1
247 09:30:45.655340 output: Init Ramdisk: ramdisk-1
248 09:30:45.655391 output: FDT: fdt-1
249 09:30:45.655443 output: Loadables: kernel-1
250 09:30:45.655494 output:
251 09:30:45.655703 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 09:30:45.655819 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 09:30:45.655936 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 09:30:45.656030 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 09:30:45.656110 No LXC device requested
256 09:30:45.656188 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:30:45.656269 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 09:30:45.656343 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:30:45.656411 Checking files for TFTP limit of 4294967296 bytes.
260 09:30:45.656912 end: 1 tftp-deploy (duration 00:00:20) [common]
261 09:30:45.657012 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:30:45.657101 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:30:45.657220 substitutions:
264 09:30:45.657286 - {DTB}: 11826819/tftp-deploy-p0d7m4m5/dtb/mt8192-asurada-spherion-r0.dtb
265 09:30:45.657347 - {INITRD}: 11826819/tftp-deploy-p0d7m4m5/ramdisk/ramdisk.cpio.gz
266 09:30:45.657406 - {KERNEL}: 11826819/tftp-deploy-p0d7m4m5/kernel/Image
267 09:30:45.657461 - {LAVA_MAC}: None
268 09:30:45.657516 - {PRESEED_CONFIG}: None
269 09:30:45.657570 - {PRESEED_LOCAL}: None
270 09:30:45.657624 - {RAMDISK}: 11826819/tftp-deploy-p0d7m4m5/ramdisk/ramdisk.cpio.gz
271 09:30:45.657677 - {ROOT_PART}: None
272 09:30:45.657729 - {ROOT}: None
273 09:30:45.657782 - {SERVER_IP}: 192.168.201.1
274 09:30:45.657838 - {TEE}: None
275 09:30:45.657898 Parsed boot commands:
276 09:30:45.657971 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:30:45.658148 Parsed boot commands: tftpboot 192.168.201.1 11826819/tftp-deploy-p0d7m4m5/kernel/image.itb 11826819/tftp-deploy-p0d7m4m5/kernel/cmdline
278 09:30:45.658235 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:30:45.658319 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:30:45.658416 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:30:45.658505 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:30:45.658574 Not connected, no need to disconnect.
283 09:30:45.658646 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:30:45.658721 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:30:45.658788 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 09:30:45.662695 Setting prompt string to ['lava-test: # ']
287 09:30:45.663049 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:30:45.663166 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:30:45.663266 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:30:45.663355 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:30:45.663549 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 09:30:50.804256 >> Command sent successfully.
293 09:30:50.814896 Returned 0 in 5 seconds
294 09:30:50.916137 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:30:50.917531 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:30:50.918157 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:30:50.918726 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:30:50.919100 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:30:50.919471 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:30:50.920651 [Enter `^Ec?' for help]
302 09:30:51.081723
303 09:30:51.082296
304 09:30:51.082634 F0: 102B 0000
305 09:30:51.082953
306 09:30:51.083321 F3: 1001 0000 [0200]
307 09:30:51.083623
308 09:30:51.085561 F3: 1001 0000
309 09:30:51.086011
310 09:30:51.086353 F7: 102D 0000
311 09:30:51.086666
312 09:30:51.086962 F1: 0000 0000
313 09:30:51.087310
314 09:30:51.089629 V0: 0000 0000 [0001]
315 09:30:51.090058
316 09:30:51.090397 00: 0007 8000
317 09:30:51.090728
318 09:30:51.092447 01: 0000 0000
319 09:30:51.092876
320 09:30:51.093211 BP: 0C00 0209 [0000]
321 09:30:51.093523
322 09:30:51.096879 G0: 1182 0000
323 09:30:51.097308
324 09:30:51.097656 EC: 0000 0021 [4000]
325 09:30:51.097971
326 09:30:51.099893 S7: 0000 0000 [0000]
327 09:30:51.100309
328 09:30:51.100645 CC: 0000 0000 [0001]
329 09:30:51.100957
330 09:30:51.103220 T0: 0000 0040 [010F]
331 09:30:51.103642
332 09:30:51.103971 Jump to BL
333 09:30:51.104283
334 09:30:51.128740
335 09:30:51.129486
336 09:30:51.130014
337 09:30:51.137040 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:30:51.139803 ARM64: Exception handlers installed.
339 09:30:51.144130 ARM64: Testing exception
340 09:30:51.147183 ARM64: Done test exception
341 09:30:51.155351 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:30:51.162092 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:30:51.168974 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:30:51.179754 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:30:51.186308 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:30:51.196889 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:30:51.206643 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:30:51.213443 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:30:51.231737 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:30:51.234857 WDT: Last reset was cold boot
351 09:30:51.238665 SPI1(PAD0) initialized at 2873684 Hz
352 09:30:51.241508 SPI5(PAD0) initialized at 992727 Hz
353 09:30:51.245042 VBOOT: Loading verstage.
354 09:30:51.251432 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:30:51.254472 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:30:51.257972 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:30:51.261196 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:30:51.269507 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:30:51.275922 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:30:51.286653 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 09:30:51.287240
362 09:30:51.287589
363 09:30:51.296151 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:30:51.299722 ARM64: Exception handlers installed.
365 09:30:51.303011 ARM64: Testing exception
366 09:30:51.303486 ARM64: Done test exception
367 09:30:51.310326 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:30:51.313611 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:30:51.327591 Probing TPM: . done!
370 09:30:51.328123 TPM ready after 0 ms
371 09:30:51.335176 Connected to device vid:did:rid of 1ae0:0028:00
372 09:30:51.341776 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 09:30:51.399971 Initialized TPM device CR50 revision 0
374 09:30:51.411877 tlcl_send_startup: Startup return code is 0
375 09:30:51.412298 TPM: setup succeeded
376 09:30:51.423229 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:30:51.432022 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:30:51.443719 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:30:51.453919 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:30:51.456932 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:30:51.461875 in-header: 03 07 00 00 08 00 00 00
382 09:30:51.466391 in-data: aa e4 47 04 13 02 00 00
383 09:30:51.469295 Chrome EC: UHEPI supported
384 09:30:51.476830 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:30:51.480391 in-header: 03 95 00 00 08 00 00 00
386 09:30:51.483997 in-data: 18 20 20 08 00 00 00 00
387 09:30:51.484455 Phase 1
388 09:30:51.487353 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:30:51.494792 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:30:51.499003 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:30:51.502352 Recovery requested (1009000e)
392 09:30:51.511262 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:30:51.516477 tlcl_extend: response is 0
394 09:30:51.525649 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:30:51.531265 tlcl_extend: response is 0
396 09:30:51.538178 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:30:51.557920 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 09:30:51.565124 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 09:30:51.565652
400 09:30:51.565989
401 09:30:51.574811 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:30:51.578425 ARM64: Exception handlers installed.
403 09:30:51.581719 ARM64: Testing exception
404 09:30:51.582235 ARM64: Done test exception
405 09:30:51.603765 pmic_efuse_setting: Set efuses in 11 msecs
406 09:30:51.607300 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:30:51.613560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:30:51.616682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:30:51.623826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:30:51.626873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:30:51.630888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:30:51.637706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:30:51.641132 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:30:51.645472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:30:51.652208 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:30:51.655931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:30:51.659874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:30:51.663897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:30:51.670740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:30:51.674375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:30:51.681989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:30:51.688867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:30:51.692103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:30:51.699362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:30:51.703299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:30:51.710738 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:30:51.714027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:30:51.721123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:30:51.725124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:30:51.732396 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:30:51.736126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:30:51.743541 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:30:51.746855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:30:51.754639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:30:51.757780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:30:51.761288 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:30:51.769392 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:30:51.773220 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:30:51.776273 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:30:51.783966 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:30:51.787422 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:30:51.791239 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:30:51.798111 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:30:51.801810 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:30:51.805399 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:30:51.812518 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:30:51.815826 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:30:51.820228 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:30:51.823500 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:30:51.829978 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:30:51.834410 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:30:51.837709 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:30:51.841243 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:30:51.844805 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:30:51.852243 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:30:51.855507 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:30:51.859191 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:30:51.866782 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:30:51.874477 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:30:51.877981 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:30:51.888454 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:30:51.895912 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:30:51.900065 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:30:51.903721 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:30:51.910675 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:30:51.918253 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x12
467 09:30:51.921290 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:30:51.925281 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 09:30:51.928874 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:30:51.940858 [RTC]rtc_get_frequency_meter,154: input=15, output=850
471 09:30:51.949795 [RTC]rtc_get_frequency_meter,154: input=7, output=723
472 09:30:51.960074 [RTC]rtc_get_frequency_meter,154: input=11, output=788
473 09:30:51.969324 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 09:30:51.978334 [RTC]rtc_get_frequency_meter,154: input=12, output=803
475 09:30:51.988007 [RTC]rtc_get_frequency_meter,154: input=11, output=787
476 09:30:51.998347 [RTC]rtc_get_frequency_meter,154: input=12, output=803
477 09:30:52.002330 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 09:30:52.005770 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 09:30:52.009346 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 09:30:52.016977 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 09:30:52.020497 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 09:30:52.024478 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 09:30:52.028414 ADC[4]: Raw value=903694 ID=7
484 09:30:52.028500 ADC[3]: Raw value=213916 ID=1
485 09:30:52.031810 RAM Code: 0x71
486 09:30:52.035615 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 09:30:52.039056 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 09:30:52.050580 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 09:30:52.053882 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 09:30:52.057221 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 09:30:52.061307 in-header: 03 07 00 00 08 00 00 00
492 09:30:52.064845 in-data: aa e4 47 04 13 02 00 00
493 09:30:52.068727 Chrome EC: UHEPI supported
494 09:30:52.075965 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 09:30:52.079155 in-header: 03 95 00 00 08 00 00 00
496 09:30:52.083103 in-data: 18 20 20 08 00 00 00 00
497 09:30:52.087444 MRC: failed to locate region type 0.
498 09:30:52.090658 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 09:30:52.094703 DRAM-K: Running full calibration
500 09:30:52.102248 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 09:30:52.102501 header.status = 0x0
502 09:30:52.105381 header.version = 0x6 (expected: 0x6)
503 09:30:52.109949 header.size = 0xd00 (expected: 0xd00)
504 09:30:52.113380 header.flags = 0x0
505 09:30:52.116260 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 09:30:52.136430 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 09:30:52.143385 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 09:30:52.144004 dram_init: ddr_geometry: 2
509 09:30:52.147117 [EMI] MDL number = 2
510 09:30:52.150782 [EMI] Get MDL freq = 0
511 09:30:52.151384 dram_init: ddr_type: 0
512 09:30:52.154556 is_discrete_lpddr4: 1
513 09:30:52.155196 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 09:30:52.158852
515 09:30:52.159525
516 09:30:52.159977 [Bian_co] ETT version 0.0.0.1
517 09:30:52.166642 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 09:30:52.167214
519 09:30:52.169375 dramc_set_vcore_voltage set vcore to 650000
520 09:30:52.169966 Read voltage for 800, 4
521 09:30:52.172647 Vio18 = 0
522 09:30:52.173214 Vcore = 650000
523 09:30:52.173754 Vdram = 0
524 09:30:52.174294 Vddq = 0
525 09:30:52.176139 Vmddr = 0
526 09:30:52.176687 dram_init: config_dvfs: 1
527 09:30:52.182792 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 09:30:52.189664 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 09:30:52.193690 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 09:30:52.198176 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 09:30:52.198704 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 09:30:52.204394 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 09:30:52.204697 MEM_TYPE=3, freq_sel=18
534 09:30:52.208416 sv_algorithm_assistance_LP4_1600
535 09:30:52.211876 ============ PULL DRAM RESETB DOWN ============
536 09:30:52.215436 ========== PULL DRAM RESETB DOWN end =========
537 09:30:52.221806 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 09:30:52.225040 ===================================
539 09:30:52.225343 LPDDR4 DRAM CONFIGURATION
540 09:30:52.229177 ===================================
541 09:30:52.231563 EX_ROW_EN[0] = 0x0
542 09:30:52.235360 EX_ROW_EN[1] = 0x0
543 09:30:52.235711 LP4Y_EN = 0x0
544 09:30:52.239186 WORK_FSP = 0x0
545 09:30:52.239507 WL = 0x2
546 09:30:52.242827 RL = 0x2
547 09:30:52.243155 BL = 0x2
548 09:30:52.245941 RPST = 0x0
549 09:30:52.246246 RD_PRE = 0x0
550 09:30:52.249536 WR_PRE = 0x1
551 09:30:52.249840 WR_PST = 0x0
552 09:30:52.252812 DBI_WR = 0x0
553 09:30:52.253118 DBI_RD = 0x0
554 09:30:52.256081 OTF = 0x1
555 09:30:52.259117 ===================================
556 09:30:52.262716 ===================================
557 09:30:52.263143 ANA top config
558 09:30:52.265958 ===================================
559 09:30:52.268901 DLL_ASYNC_EN = 0
560 09:30:52.271831 ALL_SLAVE_EN = 1
561 09:30:52.272035 NEW_RANK_MODE = 1
562 09:30:52.275345 DLL_IDLE_MODE = 1
563 09:30:52.278683 LP45_APHY_COMB_EN = 1
564 09:30:52.281759 TX_ODT_DIS = 1
565 09:30:52.285419 NEW_8X_MODE = 1
566 09:30:52.288731 ===================================
567 09:30:52.291699 ===================================
568 09:30:52.291825 data_rate = 1600
569 09:30:52.295998 CKR = 1
570 09:30:52.298481 DQ_P2S_RATIO = 8
571 09:30:52.302134 ===================================
572 09:30:52.305335 CA_P2S_RATIO = 8
573 09:30:52.309099 DQ_CA_OPEN = 0
574 09:30:52.309191 DQ_SEMI_OPEN = 0
575 09:30:52.312353 CA_SEMI_OPEN = 0
576 09:30:52.316227 CA_FULL_RATE = 0
577 09:30:52.318906 DQ_CKDIV4_EN = 1
578 09:30:52.322087 CA_CKDIV4_EN = 1
579 09:30:52.325882 CA_PREDIV_EN = 0
580 09:30:52.325965 PH8_DLY = 0
581 09:30:52.329356 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 09:30:52.332586 DQ_AAMCK_DIV = 4
583 09:30:52.335985 CA_AAMCK_DIV = 4
584 09:30:52.339460 CA_ADMCK_DIV = 4
585 09:30:52.339590 DQ_TRACK_CA_EN = 0
586 09:30:52.342455 CA_PICK = 800
587 09:30:52.346249 CA_MCKIO = 800
588 09:30:52.349561 MCKIO_SEMI = 0
589 09:30:52.353083 PLL_FREQ = 3068
590 09:30:52.357238 DQ_UI_PI_RATIO = 32
591 09:30:52.357660 CA_UI_PI_RATIO = 0
592 09:30:52.360965 ===================================
593 09:30:52.364521 ===================================
594 09:30:52.368205 memory_type:LPDDR4
595 09:30:52.368629 GP_NUM : 10
596 09:30:52.371675 SRAM_EN : 1
597 09:30:52.375042 MD32_EN : 0
598 09:30:52.375624 ===================================
599 09:30:52.379216 [ANA_INIT] >>>>>>>>>>>>>>
600 09:30:52.382922 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 09:30:52.386471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 09:30:52.389679 ===================================
603 09:30:52.390103 data_rate = 1600,PCW = 0X7600
604 09:30:52.393073 ===================================
605 09:30:52.397169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 09:30:52.403762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:30:52.409872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 09:30:52.413028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 09:30:52.416676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:30:52.419734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 09:30:52.423304 [ANA_INIT] flow start
612 09:30:52.423766 [ANA_INIT] PLL >>>>>>>>
613 09:30:52.426217 [ANA_INIT] PLL <<<<<<<<
614 09:30:52.429527 [ANA_INIT] MIDPI >>>>>>>>
615 09:30:52.433027 [ANA_INIT] MIDPI <<<<<<<<
616 09:30:52.433437 [ANA_INIT] DLL >>>>>>>>
617 09:30:52.436516 [ANA_INIT] flow end
618 09:30:52.440040 ============ LP4 DIFF to SE enter ============
619 09:30:52.443115 ============ LP4 DIFF to SE exit ============
620 09:30:52.446632 [ANA_INIT] <<<<<<<<<<<<<
621 09:30:52.449600 [Flow] Enable top DCM control >>>>>
622 09:30:52.453691 [Flow] Enable top DCM control <<<<<
623 09:30:52.456729 Enable DLL master slave shuffle
624 09:30:52.462881 ==============================================================
625 09:30:52.463368 Gating Mode config
626 09:30:52.469681 ==============================================================
627 09:30:52.470081 Config description:
628 09:30:52.479842 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 09:30:52.486502 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 09:30:52.492954 SELPH_MODE 0: By rank 1: By Phase
631 09:30:52.496230 ==============================================================
632 09:30:52.499592 GAT_TRACK_EN = 1
633 09:30:52.502866 RX_GATING_MODE = 2
634 09:30:52.506388 RX_GATING_TRACK_MODE = 2
635 09:30:52.509649 SELPH_MODE = 1
636 09:30:52.513217 PICG_EARLY_EN = 1
637 09:30:52.516383 VALID_LAT_VALUE = 1
638 09:30:52.519606 ==============================================================
639 09:30:52.522825 Enter into Gating configuration >>>>
640 09:30:52.526402 Exit from Gating configuration <<<<
641 09:30:52.529378 Enter into DVFS_PRE_config >>>>>
642 09:30:52.542954 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 09:30:52.546332 Exit from DVFS_PRE_config <<<<<
644 09:30:52.549923 Enter into PICG configuration >>>>
645 09:30:52.550481 Exit from PICG configuration <<<<
646 09:30:52.552697 [RX_INPUT] configuration >>>>>
647 09:30:52.556462 [RX_INPUT] configuration <<<<<
648 09:30:52.562827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 09:30:52.566239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 09:30:52.572887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 09:30:52.579366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 09:30:52.585979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 09:30:52.592387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 09:30:52.595730 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 09:30:52.599449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 09:30:52.602549 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 09:30:52.609424 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 09:30:52.612224 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 09:30:52.615635 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 09:30:52.619301 ===================================
661 09:30:52.622136 LPDDR4 DRAM CONFIGURATION
662 09:30:52.625579 ===================================
663 09:30:52.628989 EX_ROW_EN[0] = 0x0
664 09:30:52.629073 EX_ROW_EN[1] = 0x0
665 09:30:52.632923 LP4Y_EN = 0x0
666 09:30:52.633048 WORK_FSP = 0x0
667 09:30:52.635414 WL = 0x2
668 09:30:52.635496 RL = 0x2
669 09:30:52.638968 BL = 0x2
670 09:30:52.639104 RPST = 0x0
671 09:30:52.642540 RD_PRE = 0x0
672 09:30:52.642630 WR_PRE = 0x1
673 09:30:52.645138 WR_PST = 0x0
674 09:30:52.645236 DBI_WR = 0x0
675 09:30:52.648692 DBI_RD = 0x0
676 09:30:52.648782 OTF = 0x1
677 09:30:52.651798 ===================================
678 09:30:52.658301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 09:30:52.662145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 09:30:52.665158 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 09:30:52.668587 ===================================
682 09:30:52.672370 LPDDR4 DRAM CONFIGURATION
683 09:30:52.675350 ===================================
684 09:30:52.678717 EX_ROW_EN[0] = 0x10
685 09:30:52.678876 EX_ROW_EN[1] = 0x0
686 09:30:52.682626 LP4Y_EN = 0x0
687 09:30:52.682820 WORK_FSP = 0x0
688 09:30:52.685521 WL = 0x2
689 09:30:52.685692 RL = 0x2
690 09:30:52.688763 BL = 0x2
691 09:30:52.688886 RPST = 0x0
692 09:30:52.692377 RD_PRE = 0x0
693 09:30:52.692515 WR_PRE = 0x1
694 09:30:52.695289 WR_PST = 0x0
695 09:30:52.695425 DBI_WR = 0x0
696 09:30:52.698728 DBI_RD = 0x0
697 09:30:52.698965 OTF = 0x1
698 09:30:52.701839 ===================================
699 09:30:52.708397 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 09:30:52.713782 nWR fixed to 40
701 09:30:52.717073 [ModeRegInit_LP4] CH0 RK0
702 09:30:52.717471 [ModeRegInit_LP4] CH0 RK1
703 09:30:52.720287 [ModeRegInit_LP4] CH1 RK0
704 09:30:52.723287 [ModeRegInit_LP4] CH1 RK1
705 09:30:52.723681 match AC timing 13
706 09:30:52.729906 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 09:30:52.733346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 09:30:52.736281 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 09:30:52.742911 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 09:30:52.746643 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 09:30:52.749855 [EMI DOE] emi_dcm 0
712 09:30:52.753048 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 09:30:52.753476 ==
714 09:30:52.756175 Dram Type= 6, Freq= 0, CH_0, rank 0
715 09:30:52.759697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 09:30:52.760131 ==
717 09:30:52.767213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 09:30:52.772703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 09:30:52.781378 [CA 0] Center 38 (7~69) winsize 63
720 09:30:52.784466 [CA 1] Center 37 (7~68) winsize 62
721 09:30:52.787943 [CA 2] Center 34 (4~65) winsize 62
722 09:30:52.791551 [CA 3] Center 34 (4~65) winsize 62
723 09:30:52.795026 [CA 4] Center 33 (3~64) winsize 62
724 09:30:52.798136 [CA 5] Center 33 (3~64) winsize 62
725 09:30:52.798671
726 09:30:52.800950 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 09:30:52.801376
728 09:30:52.804366 [CATrainingPosCal] consider 1 rank data
729 09:30:52.807719 u2DelayCellTimex100 = 270/100 ps
730 09:30:52.811255 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 09:30:52.817557 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 09:30:52.821205 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 09:30:52.824393 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 09:30:52.827736 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:30:52.831178 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 09:30:52.831709
737 09:30:52.834687 CA PerBit enable=1, Macro0, CA PI delay=33
738 09:30:52.835268
739 09:30:52.837996 [CBTSetCACLKResult] CA Dly = 33
740 09:30:52.838531 CS Dly: 5 (0~36)
741 09:30:52.841016 ==
742 09:30:52.844558 Dram Type= 6, Freq= 0, CH_0, rank 1
743 09:30:52.847645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 09:30:52.848177 ==
745 09:30:52.851039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 09:30:52.857657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 09:30:52.867736 [CA 0] Center 38 (7~69) winsize 63
748 09:30:52.871371 [CA 1] Center 37 (7~68) winsize 62
749 09:30:52.874675 [CA 2] Center 35 (4~66) winsize 63
750 09:30:52.877208 [CA 3] Center 35 (4~66) winsize 63
751 09:30:52.880479 [CA 4] Center 34 (3~65) winsize 63
752 09:30:52.883834 [CA 5] Center 33 (3~64) winsize 62
753 09:30:52.884263
754 09:30:52.887352 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 09:30:52.887780
756 09:30:52.891002 [CATrainingPosCal] consider 2 rank data
757 09:30:52.894175 u2DelayCellTimex100 = 270/100 ps
758 09:30:52.897398 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
759 09:30:52.904676 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 09:30:52.907730 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 09:30:52.910547 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 09:30:52.913787 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:30:52.917098 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 09:30:52.917577
765 09:30:52.921078 CA PerBit enable=1, Macro0, CA PI delay=33
766 09:30:52.921639
767 09:30:52.923613 [CBTSetCACLKResult] CA Dly = 33
768 09:30:52.924039 CS Dly: 6 (0~38)
769 09:30:52.927111
770 09:30:52.927543 ----->DramcWriteLeveling(PI) begin...
771 09:30:52.930892 ==
772 09:30:52.934611 Dram Type= 6, Freq= 0, CH_0, rank 0
773 09:30:52.937959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 09:30:52.938625 ==
775 09:30:52.942018 Write leveling (Byte 0): 33 => 33
776 09:30:52.942727 Write leveling (Byte 1): 28 => 28
777 09:30:52.945602 DramcWriteLeveling(PI) end<-----
778 09:30:52.946116
779 09:30:52.946455 ==
780 09:30:52.949702 Dram Type= 6, Freq= 0, CH_0, rank 0
781 09:30:52.952487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 09:30:52.952916 ==
783 09:30:52.956714 [Gating] SW mode calibration
784 09:30:52.963107 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 09:30:52.969672 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 09:30:52.973120 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 09:30:52.976774 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
788 09:30:52.983126 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 09:30:52.986253 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:30:52.989708 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:30:52.996309 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:30:52.999584 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:30:53.002764 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:30:53.009912 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:30:53.013331 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:30:53.016137 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:30:53.022807 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:30:53.026127 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:30:53.029324 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:30:53.035906 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:30:53.039251 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:30:53.043407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:30:53.049473 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 09:30:53.052641 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 09:30:53.056746 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:30:53.059771 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:30:53.066584 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:30:53.068937 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:30:53.072322 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:30:53.079664 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:30:53.082644 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:30:53.085637 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
813 09:30:53.092457 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
814 09:30:53.095829 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:30:53.098817 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:30:53.106018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:30:53.109286 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:30:53.112219 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 09:30:53.119690 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
820 09:30:53.123256 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
821 09:30:53.126504 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
822 09:30:53.132614 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:30:53.135616 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:30:53.139067 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:30:53.146222 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:30:53.148997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:30:53.152456 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
828 09:30:53.159607 0 11 8 | B1->B0 | 2a2a 4242 | 0 1 | (0 0) (0 0)
829 09:30:53.162623 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
830 09:30:53.165935 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:30:53.172285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:30:53.175706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:30:53.179799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:30:53.185859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:30:53.188817 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 09:30:53.192415 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 09:30:53.199033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 09:30:53.202328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:30:53.205191 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:30:53.208982 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:30:53.215826 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:30:53.218726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:30:53.222692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:30:53.228677 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:30:53.231793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:30:53.235690 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:30:53.242190 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:30:53.245603 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:30:53.248601 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:30:53.255587 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:30:53.258752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 09:30:53.261833 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 09:30:53.265274 Total UI for P1: 0, mck2ui 16
854 09:30:53.268789 best dqsien dly found for B0: ( 0, 14, 4)
855 09:30:53.275212 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 09:30:53.275731 Total UI for P1: 0, mck2ui 16
857 09:30:53.282382 best dqsien dly found for B1: ( 0, 14, 10)
858 09:30:53.285752 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 09:30:53.288556 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 09:30:53.288993
861 09:30:53.292165 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 09:30:53.295433 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 09:30:53.299064 [Gating] SW calibration Done
864 09:30:53.299727 ==
865 09:30:53.301794 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:30:53.305886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:30:53.306458 ==
868 09:30:53.306945 RX Vref Scan: 0
869 09:30:53.307417
870 09:30:53.309040 RX Vref 0 -> 0, step: 1
871 09:30:53.309489
872 09:30:53.312691 RX Delay -130 -> 252, step: 16
873 09:30:53.316659 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 09:30:53.319385 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 09:30:53.325756 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 09:30:53.329032 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 09:30:53.332530 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 09:30:53.335604 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 09:30:53.339202 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 09:30:53.346203 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 09:30:53.348682 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 09:30:53.351994 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 09:30:53.355790 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 09:30:53.362018 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 09:30:53.365261 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 09:30:53.368952 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 09:30:53.372669 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 09:30:53.375197 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 09:30:53.375634 ==
890 09:30:53.378930 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:30:53.386045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:30:53.386582 ==
893 09:30:53.387137 DQS Delay:
894 09:30:53.388766 DQS0 = 0, DQS1 = 0
895 09:30:53.389195 DQM Delay:
896 09:30:53.392191 DQM0 = 87, DQM1 = 76
897 09:30:53.392717 DQ Delay:
898 09:30:53.395639 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 09:30:53.398849 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 09:30:53.402211 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
901 09:30:53.406173 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 09:30:53.406734
903 09:30:53.407283
904 09:30:53.407703 ==
905 09:30:53.409421 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:30:53.412328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:30:53.412858 ==
908 09:30:53.413303
909 09:30:53.413718
910 09:30:53.415270 TX Vref Scan disable
911 09:30:53.419254 == TX Byte 0 ==
912 09:30:53.421903 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 09:30:53.425488 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 09:30:53.428511 == TX Byte 1 ==
915 09:30:53.432553 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 09:30:53.435472 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 09:30:53.435889 ==
918 09:30:53.438685 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:30:53.442676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:30:53.443250 ==
921 09:30:53.457043 TX Vref=22, minBit 1, minWin=27, winSum=439
922 09:30:53.460561 TX Vref=24, minBit 1, minWin=27, winSum=442
923 09:30:53.463626 TX Vref=26, minBit 4, minWin=27, winSum=446
924 09:30:53.467337 TX Vref=28, minBit 0, minWin=28, winSum=453
925 09:30:53.469984 TX Vref=30, minBit 5, minWin=27, winSum=453
926 09:30:53.477101 TX Vref=32, minBit 5, minWin=27, winSum=450
927 09:30:53.480279 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
928 09:30:53.480828
929 09:30:53.483144 Final TX Range 1 Vref 28
930 09:30:53.483570
931 09:30:53.483904 ==
932 09:30:53.486632 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:30:53.490110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:30:53.490532 ==
935 09:30:53.493709
936 09:30:53.494122
937 09:30:53.494451 TX Vref Scan disable
938 09:30:53.496886 == TX Byte 0 ==
939 09:30:53.500191 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 09:30:53.507183 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 09:30:53.507705 == TX Byte 1 ==
942 09:30:53.510554 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 09:30:53.517474 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 09:30:53.517984
945 09:30:53.518318 [DATLAT]
946 09:30:53.518678 Freq=800, CH0 RK0
947 09:30:53.518999
948 09:30:53.520183 DATLAT Default: 0xa
949 09:30:53.520632 0, 0xFFFF, sum = 0
950 09:30:53.523488 1, 0xFFFF, sum = 0
951 09:30:53.523924 2, 0xFFFF, sum = 0
952 09:30:53.527139 3, 0xFFFF, sum = 0
953 09:30:53.530063 4, 0xFFFF, sum = 0
954 09:30:53.530485 5, 0xFFFF, sum = 0
955 09:30:53.534769 6, 0xFFFF, sum = 0
956 09:30:53.535345 7, 0xFFFF, sum = 0
957 09:30:53.536931 8, 0xFFFF, sum = 0
958 09:30:53.537525 9, 0x0, sum = 1
959 09:30:53.537875 10, 0x0, sum = 2
960 09:30:53.541247 11, 0x0, sum = 3
961 09:30:53.541779 12, 0x0, sum = 4
962 09:30:53.543164 best_step = 10
963 09:30:53.543580
964 09:30:53.543911 ==
965 09:30:53.546910 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:30:53.550812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:30:53.551390 ==
968 09:30:53.553736 RX Vref Scan: 1
969 09:30:53.554256
970 09:30:53.554592 Set Vref Range= 32 -> 127
971 09:30:53.556902
972 09:30:53.557318 RX Vref 32 -> 127, step: 1
973 09:30:53.557650
974 09:30:53.559919 RX Delay -111 -> 252, step: 8
975 09:30:53.560334
976 09:30:53.563549 Set Vref, RX VrefLevel [Byte0]: 32
977 09:30:53.566597 [Byte1]: 32
978 09:30:53.567155
979 09:30:53.569745 Set Vref, RX VrefLevel [Byte0]: 33
980 09:30:53.573160 [Byte1]: 33
981 09:30:53.577239
982 09:30:53.577657 Set Vref, RX VrefLevel [Byte0]: 34
983 09:30:53.580253 [Byte1]: 34
984 09:30:53.585309
985 09:30:53.585722 Set Vref, RX VrefLevel [Byte0]: 35
986 09:30:53.587983 [Byte1]: 35
987 09:30:53.592697
988 09:30:53.593230 Set Vref, RX VrefLevel [Byte0]: 36
989 09:30:53.596056 [Byte1]: 36
990 09:30:53.600871
991 09:30:53.601394 Set Vref, RX VrefLevel [Byte0]: 37
992 09:30:53.603883 [Byte1]: 37
993 09:30:53.608596
994 09:30:53.609164 Set Vref, RX VrefLevel [Byte0]: 38
995 09:30:53.611781 [Byte1]: 38
996 09:30:53.615513
997 09:30:53.615942 Set Vref, RX VrefLevel [Byte0]: 39
998 09:30:53.619033 [Byte1]: 39
999 09:30:53.623233
1000 09:30:53.623649 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:30:53.626756 [Byte1]: 40
1002 09:30:53.631238
1003 09:30:53.631672 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:30:53.634576 [Byte1]: 41
1005 09:30:53.638913
1006 09:30:53.639388 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:30:53.642342 [Byte1]: 42
1008 09:30:53.646340
1009 09:30:53.646856 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:30:53.649761 [Byte1]: 43
1011 09:30:53.653956
1012 09:30:53.654477 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:30:53.657418 [Byte1]: 44
1014 09:30:53.661735
1015 09:30:53.662268 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:30:53.664612 [Byte1]: 45
1017 09:30:53.669061
1018 09:30:53.669575 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:30:53.672446 [Byte1]: 46
1020 09:30:53.677440
1021 09:30:53.677959 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:30:53.680258 [Byte1]: 47
1023 09:30:53.684546
1024 09:30:53.685067 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:30:53.687603 [Byte1]: 48
1026 09:30:53.692418
1027 09:30:53.692827 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:30:53.695253 [Byte1]: 49
1029 09:30:53.699664
1030 09:30:53.700191 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:30:53.702728 [Byte1]: 50
1032 09:30:53.707338
1033 09:30:53.707861 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:30:53.710770 [Byte1]: 51
1035 09:30:53.715130
1036 09:30:53.715545 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:30:53.718593 [Byte1]: 52
1038 09:30:53.722864
1039 09:30:53.723339 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:30:53.725722 [Byte1]: 53
1041 09:30:53.730413
1042 09:30:53.731037 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:30:53.733714 [Byte1]: 54
1044 09:30:53.737798
1045 09:30:53.738315 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:30:53.741217 [Byte1]: 55
1047 09:30:53.745397
1048 09:30:53.745834 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:30:53.749249 [Byte1]: 56
1050 09:30:53.753700
1051 09:30:53.754226 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:30:53.756955 [Byte1]: 57
1053 09:30:53.761515
1054 09:30:53.762020 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:30:53.764624 [Byte1]: 58
1056 09:30:53.768602
1057 09:30:53.769033 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:30:53.771888 [Byte1]: 59
1059 09:30:53.776115
1060 09:30:53.776655 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:30:53.779139 [Byte1]: 60
1062 09:30:53.783857
1063 09:30:53.784288 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:30:53.787052 [Byte1]: 61
1065 09:30:53.791341
1066 09:30:53.791791 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:30:53.794463 [Byte1]: 62
1068 09:30:53.799461
1069 09:30:53.799979 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:30:53.802518 [Byte1]: 63
1071 09:30:53.806735
1072 09:30:53.807274 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:30:53.810268 [Byte1]: 64
1074 09:30:53.814984
1075 09:30:53.815537 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:30:53.818164 [Byte1]: 65
1077 09:30:53.822591
1078 09:30:53.823127 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:30:53.826410 [Byte1]: 66
1080 09:30:53.830157
1081 09:30:53.830933 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:30:53.833183 [Byte1]: 67
1083 09:30:53.837848
1084 09:30:53.838385 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:30:53.841131 [Byte1]: 68
1086 09:30:53.844832
1087 09:30:53.845241 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:30:53.848430 [Byte1]: 69
1089 09:30:53.852723
1090 09:30:53.853233 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:30:53.856677 [Byte1]: 70
1092 09:30:53.860513
1093 09:30:53.861027 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:30:53.863402 [Byte1]: 71
1095 09:30:53.867725
1096 09:30:53.868137 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:30:53.870990 [Byte1]: 72
1098 09:30:53.875866
1099 09:30:53.876377 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:30:53.878791 [Byte1]: 73
1101 09:30:53.883157
1102 09:30:53.883665 Final RX Vref Byte 0 = 54 to rank0
1103 09:30:53.886713 Final RX Vref Byte 1 = 60 to rank0
1104 09:30:53.890122 Final RX Vref Byte 0 = 54 to rank1
1105 09:30:53.893591 Final RX Vref Byte 1 = 60 to rank1==
1106 09:30:53.896623 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 09:30:53.903739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 09:30:53.904272 ==
1109 09:30:53.904604 DQS Delay:
1110 09:30:53.904908 DQS0 = 0, DQS1 = 0
1111 09:30:53.906268 DQM Delay:
1112 09:30:53.906676 DQM0 = 88, DQM1 = 76
1113 09:30:53.909731 DQ Delay:
1114 09:30:53.913186 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1115 09:30:53.916321 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1116 09:30:53.916869 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1117 09:30:53.923423 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 09:30:53.924002
1119 09:30:53.924366
1120 09:30:53.929525 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1121 09:30:53.933193 CH0 RK0: MR19=606, MR18=2D26
1122 09:30:53.939987 CH0_RK0: MR19=0x606, MR18=0x2D26, DQSOSC=398, MR23=63, INC=93, DEC=62
1123 09:30:53.940514
1124 09:30:53.943491 ----->DramcWriteLeveling(PI) begin...
1125 09:30:53.944017 ==
1126 09:30:53.946699 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 09:30:53.949508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 09:30:53.949930 ==
1129 09:30:53.952751 Write leveling (Byte 0): 30 => 30
1130 09:30:53.956507 Write leveling (Byte 1): 28 => 28
1131 09:30:53.959736 DramcWriteLeveling(PI) end<-----
1132 09:30:53.960250
1133 09:30:53.960582 ==
1134 09:30:53.962753 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 09:30:53.966134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 09:30:53.966551 ==
1137 09:30:53.969122 [Gating] SW mode calibration
1138 09:30:53.976358 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 09:30:53.982752 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 09:30:53.986181 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 09:30:53.992322 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1142 09:30:54.037071 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 09:30:54.037686 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 09:30:54.038117 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 09:30:54.038501 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 09:30:54.039238 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 09:30:54.039602 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 09:30:54.039951 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 09:30:54.040397 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 09:30:54.040835 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 09:30:54.041258 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 09:30:54.055197 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 09:30:54.055795 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 09:30:54.056644 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 09:30:54.057051 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 09:30:54.058532 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 09:30:54.062244 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1158 09:30:54.065256 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 09:30:54.068835 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:30:54.075798 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:30:54.079504 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:30:54.082673 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:30:54.088522 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:30:54.092098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:30:54.095273 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1166 09:30:54.102070 0 9 8 | B1->B0 | 2424 3434 | 1 1 | (0 0) (0 0)
1167 09:30:54.105236 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1168 09:30:54.108695 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 09:30:54.115278 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 09:30:54.118719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 09:30:54.121342 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 09:30:54.128086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 09:30:54.131449 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
1174 09:30:54.134998 0 10 8 | B1->B0 | 3030 2626 | 0 1 | (0 1) (1 0)
1175 09:30:54.141628 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1176 09:30:54.144879 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:30:54.148059 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:30:54.155005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:30:54.158091 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:30:54.161506 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:30:54.168574 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1182 09:30:54.171324 0 11 8 | B1->B0 | 2e2e 4444 | 1 0 | (0 0) (0 0)
1183 09:30:54.174884 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1184 09:30:54.182111 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 09:30:54.185517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 09:30:54.189911 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 09:30:54.193832 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 09:30:54.196995 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 09:30:54.203193 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1190 09:30:54.206638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1191 09:30:54.210653 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 09:30:54.213879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 09:30:54.220383 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 09:30:54.224051 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 09:30:54.227043 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 09:30:54.233790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 09:30:54.237043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 09:30:54.240393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 09:30:54.247235 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 09:30:54.250496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 09:30:54.254000 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 09:30:54.260337 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 09:30:54.264194 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 09:30:54.266933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 09:30:54.274272 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1206 09:30:54.274833 Total UI for P1: 0, mck2ui 16
1207 09:30:54.280652 best dqsien dly found for B0: ( 0, 14, 2)
1208 09:30:54.283464 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1209 09:30:54.286451 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 09:30:54.290176 Total UI for P1: 0, mck2ui 16
1211 09:30:54.293332 best dqsien dly found for B1: ( 0, 14, 8)
1212 09:30:54.296900 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1213 09:30:54.299727 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1214 09:30:54.300148
1215 09:30:54.303251 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1216 09:30:54.310283 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1217 09:30:54.310704 [Gating] SW calibration Done
1218 09:30:54.311040 ==
1219 09:30:54.313714 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 09:30:54.320189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 09:30:54.320702 ==
1222 09:30:54.321117 RX Vref Scan: 0
1223 09:30:54.321447
1224 09:30:54.323139 RX Vref 0 -> 0, step: 1
1225 09:30:54.323564
1226 09:30:54.326951 RX Delay -130 -> 252, step: 16
1227 09:30:54.330229 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1228 09:30:54.333393 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1229 09:30:54.336766 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1230 09:30:54.343162 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1231 09:30:54.346584 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1232 09:30:54.349598 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1233 09:30:54.352752 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 09:30:54.356010 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 09:30:54.362682 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 09:30:54.366512 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 09:30:54.369670 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1238 09:30:54.373121 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 09:30:54.376155 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1240 09:30:54.383070 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 09:30:54.386404 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1242 09:30:54.389278 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 09:30:54.389798 ==
1244 09:30:54.392570 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 09:30:54.396246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 09:30:54.399321 ==
1247 09:30:54.399808 DQS Delay:
1248 09:30:54.400145 DQS0 = 0, DQS1 = 0
1249 09:30:54.402254 DQM Delay:
1250 09:30:54.402672 DQM0 = 84, DQM1 = 77
1251 09:30:54.405506 DQ Delay:
1252 09:30:54.408815 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1253 09:30:54.409235 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1254 09:30:54.412572 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1255 09:30:54.415878 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1256 09:30:54.418970
1257 09:30:54.419419
1258 09:30:54.419749 ==
1259 09:30:54.422278 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 09:30:54.425686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 09:30:54.426110 ==
1262 09:30:54.426443
1263 09:30:54.426751
1264 09:30:54.428941 TX Vref Scan disable
1265 09:30:54.429376 == TX Byte 0 ==
1266 09:30:54.436434 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1267 09:30:54.438881 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1268 09:30:54.439423 == TX Byte 1 ==
1269 09:30:54.445510 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1270 09:30:54.448802 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1271 09:30:54.449223 ==
1272 09:30:54.452416 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 09:30:54.455167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 09:30:54.455594 ==
1275 09:30:54.469525 TX Vref=22, minBit 0, minWin=27, winSum=438
1276 09:30:54.473054 TX Vref=24, minBit 0, minWin=27, winSum=443
1277 09:30:54.476317 TX Vref=26, minBit 1, minWin=27, winSum=446
1278 09:30:54.479228 TX Vref=28, minBit 2, minWin=27, winSum=448
1279 09:30:54.483212 TX Vref=30, minBit 3, minWin=27, winSum=448
1280 09:30:54.489315 TX Vref=32, minBit 1, minWin=27, winSum=447
1281 09:30:54.492572 [TxChooseVref] Worse bit 2, Min win 27, Win sum 448, Final Vref 28
1282 09:30:54.493098
1283 09:30:54.495867 Final TX Range 1 Vref 28
1284 09:30:54.496286
1285 09:30:54.496615 ==
1286 09:30:54.499537 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 09:30:54.502562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 09:30:54.503211 ==
1289 09:30:54.505953
1290 09:30:54.506470
1291 09:30:54.506806 TX Vref Scan disable
1292 09:30:54.509038 == TX Byte 0 ==
1293 09:30:54.512459 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 09:30:54.518916 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 09:30:54.519382 == TX Byte 1 ==
1296 09:30:54.522400 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1297 09:30:54.528882 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1298 09:30:54.529300
1299 09:30:54.529628 [DATLAT]
1300 09:30:54.529940 Freq=800, CH0 RK1
1301 09:30:54.530241
1302 09:30:54.532307 DATLAT Default: 0xa
1303 09:30:54.532722 0, 0xFFFF, sum = 0
1304 09:30:54.535499 1, 0xFFFF, sum = 0
1305 09:30:54.538838 2, 0xFFFF, sum = 0
1306 09:30:54.539164 3, 0xFFFF, sum = 0
1307 09:30:54.542402 4, 0xFFFF, sum = 0
1308 09:30:54.542702 5, 0xFFFF, sum = 0
1309 09:30:54.545470 6, 0xFFFF, sum = 0
1310 09:30:54.545796 7, 0xFFFF, sum = 0
1311 09:30:54.548671 8, 0xFFFF, sum = 0
1312 09:30:54.548969 9, 0x0, sum = 1
1313 09:30:54.552018 10, 0x0, sum = 2
1314 09:30:54.552333 11, 0x0, sum = 3
1315 09:30:54.555123 12, 0x0, sum = 4
1316 09:30:54.555424 best_step = 10
1317 09:30:54.555658
1318 09:30:54.555876 ==
1319 09:30:54.558284 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 09:30:54.561853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 09:30:54.562235 ==
1322 09:30:54.564994 RX Vref Scan: 0
1323 09:30:54.565322
1324 09:30:54.568081 RX Vref 0 -> 0, step: 1
1325 09:30:54.568488
1326 09:30:54.568886 RX Delay -95 -> 252, step: 8
1327 09:30:54.575792 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 09:30:54.578957 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1329 09:30:54.582458 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1330 09:30:54.585737 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 09:30:54.588468 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1332 09:30:54.595162 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 09:30:54.599186 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 09:30:54.602068 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 09:30:54.605725 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 09:30:54.608592 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 09:30:54.615274 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 09:30:54.618894 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1339 09:30:54.622195 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1340 09:30:54.625011 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 09:30:54.631980 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 09:30:54.635381 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 09:30:54.635677 ==
1344 09:30:54.638577 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 09:30:54.641885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 09:30:54.642183 ==
1347 09:30:54.644999 DQS Delay:
1348 09:30:54.645293 DQS0 = 0, DQS1 = 0
1349 09:30:54.645527 DQM Delay:
1350 09:30:54.648353 DQM0 = 86, DQM1 = 76
1351 09:30:54.648648 DQ Delay:
1352 09:30:54.651841 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1353 09:30:54.654842 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1354 09:30:54.658499 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1355 09:30:54.661569 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1356 09:30:54.661748
1357 09:30:54.661890
1358 09:30:54.671568 [DQSOSCAuto] RK1, (LSB)MR18= 0x201d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1359 09:30:54.671698 CH0 RK1: MR19=606, MR18=201D
1360 09:30:54.678242 CH0_RK1: MR19=0x606, MR18=0x201D, DQSOSC=401, MR23=63, INC=91, DEC=61
1361 09:30:54.681141 [RxdqsGatingPostProcess] freq 800
1362 09:30:54.687965 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 09:30:54.691663 Pre-setting of DQS Precalculation
1364 09:30:54.694532 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 09:30:54.694614 ==
1366 09:30:54.698223 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 09:30:54.704633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 09:30:54.704714 ==
1369 09:30:54.708135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 09:30:54.714733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 09:30:54.724221 [CA 0] Center 36 (6~67) winsize 62
1372 09:30:54.726875 [CA 1] Center 37 (6~68) winsize 63
1373 09:30:54.730881 [CA 2] Center 35 (5~65) winsize 61
1374 09:30:54.734739 [CA 3] Center 34 (4~65) winsize 62
1375 09:30:54.736902 [CA 4] Center 34 (4~65) winsize 62
1376 09:30:54.740799 [CA 5] Center 33 (3~64) winsize 62
1377 09:30:54.740985
1378 09:30:54.744528 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 09:30:54.744715
1380 09:30:54.747055 [CATrainingPosCal] consider 1 rank data
1381 09:30:54.750590 u2DelayCellTimex100 = 270/100 ps
1382 09:30:54.753991 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1383 09:30:54.760421 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 09:30:54.763938 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1385 09:30:54.767403 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 09:30:54.770382 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 09:30:54.774267 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 09:30:54.774682
1389 09:30:54.777470 CA PerBit enable=1, Macro0, CA PI delay=33
1390 09:30:54.777882
1391 09:30:54.780684 [CBTSetCACLKResult] CA Dly = 33
1392 09:30:54.781188 CS Dly: 4 (0~35)
1393 09:30:54.784237 ==
1394 09:30:54.787731 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 09:30:54.790266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 09:30:54.790686 ==
1397 09:30:54.793788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 09:30:54.800400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 09:30:54.810690 [CA 0] Center 36 (6~67) winsize 62
1400 09:30:54.813697 [CA 1] Center 36 (6~67) winsize 62
1401 09:30:54.817133 [CA 2] Center 34 (4~65) winsize 62
1402 09:30:54.820624 [CA 3] Center 34 (3~65) winsize 63
1403 09:30:54.823410 [CA 4] Center 34 (4~65) winsize 62
1404 09:30:54.827070 [CA 5] Center 34 (3~65) winsize 63
1405 09:30:54.827529
1406 09:30:54.830338 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 09:30:54.830752
1408 09:30:54.833667 [CATrainingPosCal] consider 2 rank data
1409 09:30:54.837274 u2DelayCellTimex100 = 270/100 ps
1410 09:30:54.840563 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 09:30:54.847511 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 09:30:54.847934 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1413 09:30:54.851454 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 09:30:54.854686 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 09:30:54.858332 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 09:30:54.862270
1417 09:30:54.865532 CA PerBit enable=1, Macro0, CA PI delay=33
1418 09:30:54.865947
1419 09:30:54.866275 [CBTSetCACLKResult] CA Dly = 33
1420 09:30:54.869015 CS Dly: 5 (0~37)
1421 09:30:54.869425
1422 09:30:54.872933 ----->DramcWriteLeveling(PI) begin...
1423 09:30:54.873358 ==
1424 09:30:54.876935 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 09:30:54.880439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 09:30:54.880856 ==
1427 09:30:54.883560 Write leveling (Byte 0): 28 => 28
1428 09:30:54.887174 Write leveling (Byte 1): 29 => 29
1429 09:30:54.890220 DramcWriteLeveling(PI) end<-----
1430 09:30:54.890634
1431 09:30:54.890960 ==
1432 09:30:54.893353 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 09:30:54.896673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 09:30:54.897093 ==
1435 09:30:54.899859 [Gating] SW mode calibration
1436 09:30:54.906650 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 09:30:54.913311 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 09:30:54.916598 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1439 09:30:54.920121 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1440 09:30:54.927182 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 09:30:54.930420 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 09:30:54.933444 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 09:30:54.940083 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 09:30:54.943106 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 09:30:54.946592 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 09:30:54.949762 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 09:30:54.956300 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 09:30:54.959842 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 09:30:54.963458 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 09:30:54.969997 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 09:30:54.973162 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 09:30:54.976374 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 09:30:54.983038 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 09:30:54.986367 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1455 09:30:54.989249 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1456 09:30:54.996340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:30:54.999513 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:30:55.002546 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:30:55.009228 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:30:55.012539 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:30:55.016032 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:30:55.022195 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:30:55.025712 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:30:55.029253 0 9 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
1465 09:30:55.035707 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 09:30:55.039068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 09:30:55.042498 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 09:30:55.049479 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 09:30:55.052635 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 09:30:55.055564 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1471 09:30:55.062170 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (0 0) (1 1)
1472 09:30:55.065372 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
1473 09:30:55.068759 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:30:55.075524 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:30:55.078803 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:30:55.082063 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:30:55.088874 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:30:55.091991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:30:55.094986 0 11 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1480 09:30:55.102049 0 11 8 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
1481 09:30:55.105219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 09:30:55.108460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 09:30:55.115798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 09:30:55.118429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 09:30:55.121844 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 09:30:55.128717 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 09:30:55.132276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1488 09:30:55.134978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 09:30:55.141980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 09:30:55.145435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 09:30:55.148492 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 09:30:55.154978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 09:30:55.158170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 09:30:55.161679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 09:30:55.168053 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 09:30:55.171740 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 09:30:55.174752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 09:30:55.181099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 09:30:55.184647 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 09:30:55.188312 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 09:30:55.194713 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 09:30:55.197970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 09:30:55.200980 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:30:55.207868 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1505 09:30:55.211145 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 09:30:55.214357 Total UI for P1: 0, mck2ui 16
1507 09:30:55.217835 best dqsien dly found for B0: ( 0, 14, 8)
1508 09:30:55.221004 Total UI for P1: 0, mck2ui 16
1509 09:30:55.224359 best dqsien dly found for B1: ( 0, 14, 8)
1510 09:30:55.227597 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1511 09:30:55.230868 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1512 09:30:55.231413
1513 09:30:55.234179 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1514 09:30:55.237841 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1515 09:30:55.241190 [Gating] SW calibration Done
1516 09:30:55.241635 ==
1517 09:30:55.244542 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 09:30:55.247883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 09:30:55.248308 ==
1520 09:30:55.250835 RX Vref Scan: 0
1521 09:30:55.251359
1522 09:30:55.254069 RX Vref 0 -> 0, step: 1
1523 09:30:55.254489
1524 09:30:55.254918 RX Delay -130 -> 252, step: 16
1525 09:30:55.260504 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1526 09:30:55.263936 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1527 09:30:55.267411 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1528 09:30:55.270911 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1529 09:30:55.273849 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1530 09:30:55.280722 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1531 09:30:55.283691 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1532 09:30:55.287456 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1533 09:30:55.290619 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1534 09:30:55.293652 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1535 09:30:55.300687 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1536 09:30:55.304282 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1537 09:30:55.307192 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1538 09:30:55.310187 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1539 09:30:55.316646 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1540 09:30:55.320016 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1541 09:30:55.320473 ==
1542 09:30:55.323388 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 09:30:55.326695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 09:30:55.327277 ==
1545 09:30:55.330021 DQS Delay:
1546 09:30:55.330489 DQS0 = 0, DQS1 = 0
1547 09:30:55.330865 DQM Delay:
1548 09:30:55.333209 DQM0 = 86, DQM1 = 82
1549 09:30:55.333674 DQ Delay:
1550 09:30:55.336371 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1551 09:30:55.339711 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1552 09:30:55.343407 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1553 09:30:55.346476 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1554 09:30:55.346900
1555 09:30:55.347450
1556 09:30:55.347906 ==
1557 09:30:55.349717 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 09:30:55.356789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 09:30:55.357211 ==
1560 09:30:55.357641
1561 09:30:55.358077
1562 09:30:55.358479 TX Vref Scan disable
1563 09:30:55.360023 == TX Byte 0 ==
1564 09:30:55.363607 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1565 09:30:55.369808 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1566 09:30:55.370255 == TX Byte 1 ==
1567 09:30:55.373609 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1568 09:30:55.380145 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1569 09:30:55.380568 ==
1570 09:30:55.383007 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 09:30:55.386583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 09:30:55.387006 ==
1573 09:30:55.398769 TX Vref=22, minBit 0, minWin=27, winSum=440
1574 09:30:55.402155 TX Vref=24, minBit 1, minWin=27, winSum=447
1575 09:30:55.405418 TX Vref=26, minBit 0, minWin=28, winSum=452
1576 09:30:55.408709 TX Vref=28, minBit 0, minWin=28, winSum=455
1577 09:30:55.412435 TX Vref=30, minBit 1, minWin=27, winSum=453
1578 09:30:55.418810 TX Vref=32, minBit 1, minWin=27, winSum=452
1579 09:30:55.422069 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1580 09:30:55.422549
1581 09:30:55.425945 Final TX Range 1 Vref 28
1582 09:30:55.426368
1583 09:30:55.426794 ==
1584 09:30:55.429402 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 09:30:55.432263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 09:30:55.432672 ==
1587 09:30:55.433055
1588 09:30:55.433369
1589 09:30:55.436259 TX Vref Scan disable
1590 09:30:55.439325 == TX Byte 0 ==
1591 09:30:55.442309 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 09:30:55.445651 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 09:30:55.449263 == TX Byte 1 ==
1594 09:30:55.452200 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1595 09:30:55.455943 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1596 09:30:55.456415
1597 09:30:55.459468 [DATLAT]
1598 09:30:55.459913 Freq=800, CH1 RK0
1599 09:30:55.460290
1600 09:30:55.462600 DATLAT Default: 0xa
1601 09:30:55.463209 0, 0xFFFF, sum = 0
1602 09:30:55.465962 1, 0xFFFF, sum = 0
1603 09:30:55.466489 2, 0xFFFF, sum = 0
1604 09:30:55.469133 3, 0xFFFF, sum = 0
1605 09:30:55.469722 4, 0xFFFF, sum = 0
1606 09:30:55.472484 5, 0xFFFF, sum = 0
1607 09:30:55.473121 6, 0xFFFF, sum = 0
1608 09:30:55.475619 7, 0xFFFF, sum = 0
1609 09:30:55.476081 8, 0xFFFF, sum = 0
1610 09:30:55.479244 9, 0x0, sum = 1
1611 09:30:55.479672 10, 0x0, sum = 2
1612 09:30:55.482624 11, 0x0, sum = 3
1613 09:30:55.483262 12, 0x0, sum = 4
1614 09:30:55.485810 best_step = 10
1615 09:30:55.486353
1616 09:30:55.486768 ==
1617 09:30:55.489016 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 09:30:55.492287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 09:30:55.492842 ==
1620 09:30:55.495813 RX Vref Scan: 1
1621 09:30:55.496264
1622 09:30:55.496715 Set Vref Range= 32 -> 127
1623 09:30:55.497210
1624 09:30:55.499630 RX Vref 32 -> 127, step: 1
1625 09:30:55.500150
1626 09:30:55.502249 RX Delay -79 -> 252, step: 8
1627 09:30:55.502704
1628 09:30:55.505476 Set Vref, RX VrefLevel [Byte0]: 32
1629 09:30:55.508891 [Byte1]: 32
1630 09:30:55.509467
1631 09:30:55.512400 Set Vref, RX VrefLevel [Byte0]: 33
1632 09:30:55.515430 [Byte1]: 33
1633 09:30:55.519115
1634 09:30:55.519598 Set Vref, RX VrefLevel [Byte0]: 34
1635 09:30:55.522142 [Byte1]: 34
1636 09:30:55.526501
1637 09:30:55.526972 Set Vref, RX VrefLevel [Byte0]: 35
1638 09:30:55.530185 [Byte1]: 35
1639 09:30:55.534406
1640 09:30:55.534892 Set Vref, RX VrefLevel [Byte0]: 36
1641 09:30:55.537682 [Byte1]: 36
1642 09:30:55.541836
1643 09:30:55.542386 Set Vref, RX VrefLevel [Byte0]: 37
1644 09:30:55.544824 [Byte1]: 37
1645 09:30:55.549372
1646 09:30:55.549937 Set Vref, RX VrefLevel [Byte0]: 38
1647 09:30:55.553095 [Byte1]: 38
1648 09:30:55.556680
1649 09:30:55.557240 Set Vref, RX VrefLevel [Byte0]: 39
1650 09:30:55.560177 [Byte1]: 39
1651 09:30:55.564324
1652 09:30:55.564905 Set Vref, RX VrefLevel [Byte0]: 40
1653 09:30:55.567720 [Byte1]: 40
1654 09:30:55.571679
1655 09:30:55.572143 Set Vref, RX VrefLevel [Byte0]: 41
1656 09:30:55.575526 [Byte1]: 41
1657 09:30:55.579422
1658 09:30:55.579871 Set Vref, RX VrefLevel [Byte0]: 42
1659 09:30:55.582948 [Byte1]: 42
1660 09:30:55.586879
1661 09:30:55.587407 Set Vref, RX VrefLevel [Byte0]: 43
1662 09:30:55.590279 [Byte1]: 43
1663 09:30:55.594500
1664 09:30:55.594964 Set Vref, RX VrefLevel [Byte0]: 44
1665 09:30:55.598047 [Byte1]: 44
1666 09:30:55.602423
1667 09:30:55.602873 Set Vref, RX VrefLevel [Byte0]: 45
1668 09:30:55.605431 [Byte1]: 45
1669 09:30:55.609601
1670 09:30:55.610109 Set Vref, RX VrefLevel [Byte0]: 46
1671 09:30:55.612998 [Byte1]: 46
1672 09:30:55.617404
1673 09:30:55.617882 Set Vref, RX VrefLevel [Byte0]: 47
1674 09:30:55.620965 [Byte1]: 47
1675 09:30:55.624744
1676 09:30:55.625268 Set Vref, RX VrefLevel [Byte0]: 48
1677 09:30:55.627959 [Byte1]: 48
1678 09:30:55.632473
1679 09:30:55.632918 Set Vref, RX VrefLevel [Byte0]: 49
1680 09:30:55.635997 [Byte1]: 49
1681 09:30:55.639544
1682 09:30:55.639977 Set Vref, RX VrefLevel [Byte0]: 50
1683 09:30:55.643185 [Byte1]: 50
1684 09:30:55.647459
1685 09:30:55.647939 Set Vref, RX VrefLevel [Byte0]: 51
1686 09:30:55.650790 [Byte1]: 51
1687 09:30:55.654815
1688 09:30:55.655353 Set Vref, RX VrefLevel [Byte0]: 52
1689 09:30:55.658175 [Byte1]: 52
1690 09:30:55.662422
1691 09:30:55.662918 Set Vref, RX VrefLevel [Byte0]: 53
1692 09:30:55.665670 [Byte1]: 53
1693 09:30:55.669746
1694 09:30:55.670159 Set Vref, RX VrefLevel [Byte0]: 54
1695 09:30:55.673369 [Byte1]: 54
1696 09:30:55.677522
1697 09:30:55.677946 Set Vref, RX VrefLevel [Byte0]: 55
1698 09:30:55.680818 [Byte1]: 55
1699 09:30:55.685200
1700 09:30:55.685681 Set Vref, RX VrefLevel [Byte0]: 56
1701 09:30:55.688269 [Byte1]: 56
1702 09:30:55.692460
1703 09:30:55.692882 Set Vref, RX VrefLevel [Byte0]: 57
1704 09:30:55.695894 [Byte1]: 57
1705 09:30:55.700464
1706 09:30:55.700886 Set Vref, RX VrefLevel [Byte0]: 58
1707 09:30:55.703668 [Byte1]: 58
1708 09:30:55.708026
1709 09:30:55.708470 Set Vref, RX VrefLevel [Byte0]: 59
1710 09:30:55.711030 [Byte1]: 59
1711 09:30:55.715349
1712 09:30:55.715769 Set Vref, RX VrefLevel [Byte0]: 60
1713 09:30:55.718830 [Byte1]: 60
1714 09:30:55.722571
1715 09:30:55.722969 Set Vref, RX VrefLevel [Byte0]: 61
1716 09:30:55.726421 [Byte1]: 61
1717 09:30:55.730820
1718 09:30:55.731286 Set Vref, RX VrefLevel [Byte0]: 62
1719 09:30:55.734135 [Byte1]: 62
1720 09:30:55.738816
1721 09:30:55.739293 Set Vref, RX VrefLevel [Byte0]: 63
1722 09:30:55.741416 [Byte1]: 63
1723 09:30:55.745580
1724 09:30:55.745995 Set Vref, RX VrefLevel [Byte0]: 64
1725 09:30:55.748756 [Byte1]: 64
1726 09:30:55.753088
1727 09:30:55.753502 Set Vref, RX VrefLevel [Byte0]: 65
1728 09:30:55.756416 [Byte1]: 65
1729 09:30:55.760529
1730 09:30:55.761013 Set Vref, RX VrefLevel [Byte0]: 66
1731 09:30:55.763741 [Byte1]: 66
1732 09:30:55.767957
1733 09:30:55.768372 Set Vref, RX VrefLevel [Byte0]: 67
1734 09:30:55.771460 [Byte1]: 67
1735 09:30:55.776003
1736 09:30:55.776475 Set Vref, RX VrefLevel [Byte0]: 68
1737 09:30:55.779134 [Byte1]: 68
1738 09:30:55.783170
1739 09:30:55.783586 Set Vref, RX VrefLevel [Byte0]: 69
1740 09:30:55.786633 [Byte1]: 69
1741 09:30:55.790833
1742 09:30:55.791284 Set Vref, RX VrefLevel [Byte0]: 70
1743 09:30:55.794149 [Byte1]: 70
1744 09:30:55.798674
1745 09:30:55.799121 Set Vref, RX VrefLevel [Byte0]: 71
1746 09:30:55.801612 [Byte1]: 71
1747 09:30:55.806663
1748 09:30:55.807226 Set Vref, RX VrefLevel [Byte0]: 72
1749 09:30:55.809160 [Byte1]: 72
1750 09:30:55.814012
1751 09:30:55.814529 Set Vref, RX VrefLevel [Byte0]: 73
1752 09:30:55.817100 [Byte1]: 73
1753 09:30:55.821184
1754 09:30:55.821615 Set Vref, RX VrefLevel [Byte0]: 74
1755 09:30:55.824166 [Byte1]: 74
1756 09:30:55.829067
1757 09:30:55.829474 Final RX Vref Byte 0 = 58 to rank0
1758 09:30:55.832044 Final RX Vref Byte 1 = 56 to rank0
1759 09:30:55.835667 Final RX Vref Byte 0 = 58 to rank1
1760 09:30:55.838566 Final RX Vref Byte 1 = 56 to rank1==
1761 09:30:55.841650 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 09:30:55.848350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 09:30:55.848770 ==
1764 09:30:55.849104 DQS Delay:
1765 09:30:55.852082 DQS0 = 0, DQS1 = 0
1766 09:30:55.852499 DQM Delay:
1767 09:30:55.852831 DQM0 = 86, DQM1 = 80
1768 09:30:55.854970 DQ Delay:
1769 09:30:55.858348 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1770 09:30:55.861332 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1771 09:30:55.865130 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1772 09:30:55.868311 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1773 09:30:55.868729
1774 09:30:55.869056
1775 09:30:55.875246 [DQSOSCAuto] RK0, (LSB)MR18= 0x1125, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
1776 09:30:55.878497 CH1 RK0: MR19=606, MR18=1125
1777 09:30:55.884948 CH1_RK0: MR19=0x606, MR18=0x1125, DQSOSC=400, MR23=63, INC=92, DEC=61
1778 09:30:55.885369
1779 09:30:55.888009 ----->DramcWriteLeveling(PI) begin...
1780 09:30:55.888434 ==
1781 09:30:55.891846 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 09:30:55.895647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 09:30:55.896066 ==
1784 09:30:55.897952 Write leveling (Byte 0): 25 => 25
1785 09:30:55.901316 Write leveling (Byte 1): 30 => 30
1786 09:30:55.904370 DramcWriteLeveling(PI) end<-----
1787 09:30:55.904785
1788 09:30:55.905113 ==
1789 09:30:55.908215 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 09:30:55.910957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 09:30:55.911410 ==
1792 09:30:55.914924 [Gating] SW mode calibration
1793 09:30:55.921214 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 09:30:55.927860 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 09:30:55.930761 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1796 09:30:55.938485 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1797 09:30:55.941442 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1798 09:30:55.944739 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 09:30:55.948329 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 09:30:55.954606 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 09:30:55.958167 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 09:30:55.960997 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 09:30:55.967498 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 09:30:55.971232 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 09:30:55.974029 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 09:30:55.981177 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 09:30:55.984498 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 09:30:55.987561 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 09:30:55.994095 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 09:30:55.997885 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 09:30:56.001039 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1812 09:30:56.007689 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1813 09:30:56.010938 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1814 09:30:56.013798 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:30:56.021084 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:30:56.023984 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:30:56.027672 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:30:56.034077 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:30:56.037444 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:30:56.040534 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1821 09:30:56.047328 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1822 09:30:56.051060 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 09:30:56.053958 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 09:30:56.060230 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 09:30:56.064720 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 09:30:56.066910 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 09:30:56.073745 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1828 09:30:56.076830 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
1829 09:30:56.080496 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
1830 09:30:56.086706 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:30:56.090359 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:30:56.093329 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:30:56.099832 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:30:56.103239 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:30:56.106471 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:30:56.113280 0 11 4 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
1837 09:30:56.116745 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1838 09:30:56.120120 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 09:30:56.126362 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 09:30:56.129827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 09:30:56.133011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 09:30:56.140012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 09:30:56.143472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 09:30:56.146530 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1845 09:30:56.153080 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1846 09:30:56.156728 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 09:30:56.159473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 09:30:56.166577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 09:30:56.169667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 09:30:56.173040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 09:30:56.176403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 09:30:56.183183 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 09:30:56.186210 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 09:30:56.189394 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 09:30:56.195926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 09:30:56.198921 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 09:30:56.202853 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 09:30:56.209741 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 09:30:56.212422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1860 09:30:56.216175 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1861 09:30:56.219374 Total UI for P1: 0, mck2ui 16
1862 09:30:56.222521 best dqsien dly found for B0: ( 0, 14, 0)
1863 09:30:56.229310 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 09:30:56.229731 Total UI for P1: 0, mck2ui 16
1865 09:30:56.235890 best dqsien dly found for B1: ( 0, 14, 6)
1866 09:30:56.239200 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1867 09:30:56.242519 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1868 09:30:56.242998
1869 09:30:56.246239 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1870 09:30:56.249263 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1871 09:30:56.252392 [Gating] SW calibration Done
1872 09:30:56.252806 ==
1873 09:30:56.255916 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 09:30:56.258882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 09:30:56.259401 ==
1876 09:30:56.262344 RX Vref Scan: 0
1877 09:30:56.262762
1878 09:30:56.263134 RX Vref 0 -> 0, step: 1
1879 09:30:56.263461
1880 09:30:56.266275 RX Delay -130 -> 252, step: 16
1881 09:30:56.272350 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1882 09:30:56.275852 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1883 09:30:56.278966 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1884 09:30:56.282451 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1885 09:30:56.286144 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1886 09:30:56.292218 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1887 09:30:56.295698 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1888 09:30:56.299404 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1889 09:30:56.302357 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1890 09:30:56.305421 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1891 09:30:56.311828 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1892 09:30:56.315492 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1893 09:30:56.318370 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1894 09:30:56.321978 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1895 09:30:56.325176 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1896 09:30:56.332195 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1897 09:30:56.332612 ==
1898 09:30:56.335611 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 09:30:56.338659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 09:30:56.339118 ==
1901 09:30:56.339467 DQS Delay:
1902 09:30:56.342131 DQS0 = 0, DQS1 = 0
1903 09:30:56.342545 DQM Delay:
1904 09:30:56.345413 DQM0 = 79, DQM1 = 79
1905 09:30:56.345833 DQ Delay:
1906 09:30:56.348808 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1907 09:30:56.352093 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1908 09:30:56.355581 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1909 09:30:56.358738 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1910 09:30:56.359300
1911 09:30:56.359690
1912 09:30:56.360020 ==
1913 09:30:56.361587 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 09:30:56.365175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 09:30:56.368358 ==
1916 09:30:56.368823
1917 09:30:56.369155
1918 09:30:56.369482 TX Vref Scan disable
1919 09:30:56.371718 == TX Byte 0 ==
1920 09:30:56.375361 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1921 09:30:56.378327 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1922 09:30:56.381264 == TX Byte 1 ==
1923 09:30:56.384743 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1924 09:30:56.388322 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1925 09:30:56.391056 ==
1926 09:30:56.394483 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 09:30:56.397901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 09:30:56.398529 ==
1929 09:30:56.410717 TX Vref=22, minBit 0, minWin=27, winSum=443
1930 09:30:56.414513 TX Vref=24, minBit 1, minWin=27, winSum=448
1931 09:30:56.417189 TX Vref=26, minBit 6, minWin=27, winSum=453
1932 09:30:56.421434 TX Vref=28, minBit 4, minWin=27, winSum=454
1933 09:30:56.424365 TX Vref=30, minBit 1, minWin=28, winSum=455
1934 09:30:56.430878 TX Vref=32, minBit 3, minWin=27, winSum=455
1935 09:30:56.433776 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 30
1936 09:30:56.434350
1937 09:30:56.437129 Final TX Range 1 Vref 30
1938 09:30:56.437701
1939 09:30:56.438207 ==
1940 09:30:56.440644 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 09:30:56.444001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 09:30:56.444644 ==
1943 09:30:56.447967
1944 09:30:56.448549
1945 09:30:56.449130 TX Vref Scan disable
1946 09:30:56.450942 == TX Byte 0 ==
1947 09:30:56.454162 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1948 09:30:56.457501 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1949 09:30:56.461152 == TX Byte 1 ==
1950 09:30:56.464492 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1951 09:30:56.467542 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1952 09:30:56.471225
1953 09:30:56.471678 [DATLAT]
1954 09:30:56.472208 Freq=800, CH1 RK1
1955 09:30:56.472614
1956 09:30:56.474146 DATLAT Default: 0xa
1957 09:30:56.474545 0, 0xFFFF, sum = 0
1958 09:30:56.477763 1, 0xFFFF, sum = 0
1959 09:30:56.478321 2, 0xFFFF, sum = 0
1960 09:30:56.480959 3, 0xFFFF, sum = 0
1961 09:30:56.481519 4, 0xFFFF, sum = 0
1962 09:30:56.484372 5, 0xFFFF, sum = 0
1963 09:30:56.487521 6, 0xFFFF, sum = 0
1964 09:30:56.487943 7, 0xFFFF, sum = 0
1965 09:30:56.490651 8, 0xFFFF, sum = 0
1966 09:30:56.491107 9, 0x0, sum = 1
1967 09:30:56.491459 10, 0x0, sum = 2
1968 09:30:56.494438 11, 0x0, sum = 3
1969 09:30:56.494861 12, 0x0, sum = 4
1970 09:30:56.497896 best_step = 10
1971 09:30:56.498471
1972 09:30:56.498821 ==
1973 09:30:56.501105 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 09:30:56.504321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 09:30:56.504891 ==
1976 09:30:56.508291 RX Vref Scan: 0
1977 09:30:56.508863
1978 09:30:56.509253 RX Vref 0 -> 0, step: 1
1979 09:30:56.509598
1980 09:30:56.511363 RX Delay -95 -> 252, step: 8
1981 09:30:56.517413 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1982 09:30:56.520912 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1983 09:30:56.524063 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1984 09:30:56.527379 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1985 09:30:56.531050 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1986 09:30:56.537332 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1987 09:30:56.540532 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1988 09:30:56.544345 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1989 09:30:56.547275 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1990 09:30:56.550670 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1991 09:30:56.557380 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1992 09:30:56.560816 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1993 09:30:56.564072 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1994 09:30:56.567562 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1995 09:30:56.573967 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1996 09:30:56.577387 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1997 09:30:56.577933 ==
1998 09:30:56.580823 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 09:30:56.584575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 09:30:56.585141 ==
2001 09:30:56.585642 DQS Delay:
2002 09:30:56.587657 DQS0 = 0, DQS1 = 0
2003 09:30:56.588074 DQM Delay:
2004 09:30:56.590503 DQM0 = 86, DQM1 = 81
2005 09:30:56.590919 DQ Delay:
2006 09:30:56.593821 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2007 09:30:56.597761 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2008 09:30:56.600688 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2009 09:30:56.604280 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2010 09:30:56.604782
2011 09:30:56.605134
2012 09:30:56.613816 [DQSOSCAuto] RK1, (LSB)MR18= 0x1935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2013 09:30:56.614273 CH1 RK1: MR19=606, MR18=1935
2014 09:30:56.620748 CH1_RK1: MR19=0x606, MR18=0x1935, DQSOSC=396, MR23=63, INC=94, DEC=62
2015 09:30:56.624345 [RxdqsGatingPostProcess] freq 800
2016 09:30:56.630349 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2017 09:30:56.633654 Pre-setting of DQS Precalculation
2018 09:30:56.637206 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2019 09:30:56.643851 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2020 09:30:56.653458 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2021 09:30:56.653967
2022 09:30:56.654300
2023 09:30:56.656958 [Calibration Summary] 1600 Mbps
2024 09:30:56.657467 CH 0, Rank 0
2025 09:30:56.660888 SW Impedance : PASS
2026 09:30:56.661396 DUTY Scan : NO K
2027 09:30:56.663624 ZQ Calibration : PASS
2028 09:30:56.664041 Jitter Meter : NO K
2029 09:30:56.666588 CBT Training : PASS
2030 09:30:56.670332 Write leveling : PASS
2031 09:30:56.670748 RX DQS gating : PASS
2032 09:30:56.673663 RX DQ/DQS(RDDQC) : PASS
2033 09:30:56.676978 TX DQ/DQS : PASS
2034 09:30:56.677417 RX DATLAT : PASS
2035 09:30:56.679688 RX DQ/DQS(Engine): PASS
2036 09:30:56.683386 TX OE : NO K
2037 09:30:56.683834 All Pass.
2038 09:30:56.684175
2039 09:30:56.684485 CH 0, Rank 1
2040 09:30:56.686493 SW Impedance : PASS
2041 09:30:56.690464 DUTY Scan : NO K
2042 09:30:56.690903 ZQ Calibration : PASS
2043 09:30:56.693591 Jitter Meter : NO K
2044 09:30:56.696574 CBT Training : PASS
2045 09:30:56.697040 Write leveling : PASS
2046 09:30:56.700123 RX DQS gating : PASS
2047 09:30:56.703389 RX DQ/DQS(RDDQC) : PASS
2048 09:30:56.703836 TX DQ/DQS : PASS
2049 09:30:56.706418 RX DATLAT : PASS
2050 09:30:56.709932 RX DQ/DQS(Engine): PASS
2051 09:30:56.710659 TX OE : NO K
2052 09:30:56.711060 All Pass.
2053 09:30:56.713494
2054 09:30:56.713942 CH 1, Rank 0
2055 09:30:56.716504 SW Impedance : PASS
2056 09:30:56.716966 DUTY Scan : NO K
2057 09:30:56.720726 ZQ Calibration : PASS
2058 09:30:56.721246 Jitter Meter : NO K
2059 09:30:56.723284 CBT Training : PASS
2060 09:30:56.726954 Write leveling : PASS
2061 09:30:56.727521 RX DQS gating : PASS
2062 09:30:56.729857 RX DQ/DQS(RDDQC) : PASS
2063 09:30:56.733077 TX DQ/DQS : PASS
2064 09:30:56.733501 RX DATLAT : PASS
2065 09:30:56.736532 RX DQ/DQS(Engine): PASS
2066 09:30:56.739888 TX OE : NO K
2067 09:30:56.740333 All Pass.
2068 09:30:56.740667
2069 09:30:56.741100 CH 1, Rank 1
2070 09:30:56.743062 SW Impedance : PASS
2071 09:30:56.746596 DUTY Scan : NO K
2072 09:30:56.747216 ZQ Calibration : PASS
2073 09:30:56.750009 Jitter Meter : NO K
2074 09:30:56.752958 CBT Training : PASS
2075 09:30:56.753516 Write leveling : PASS
2076 09:30:56.756446 RX DQS gating : PASS
2077 09:30:56.759835 RX DQ/DQS(RDDQC) : PASS
2078 09:30:56.760373 TX DQ/DQS : PASS
2079 09:30:56.763535 RX DATLAT : PASS
2080 09:30:56.763943 RX DQ/DQS(Engine): PASS
2081 09:30:56.766544 TX OE : NO K
2082 09:30:56.767176 All Pass.
2083 09:30:56.767534
2084 09:30:56.770138 DramC Write-DBI off
2085 09:30:56.773274 PER_BANK_REFRESH: Hybrid Mode
2086 09:30:56.773812 TX_TRACKING: ON
2087 09:30:56.776904 [GetDramInforAfterCalByMRR] Vendor 6.
2088 09:30:56.780557 [GetDramInforAfterCalByMRR] Revision 606.
2089 09:30:56.786224 [GetDramInforAfterCalByMRR] Revision 2 0.
2090 09:30:56.786768 MR0 0x3b3b
2091 09:30:56.787274 MR8 0x5151
2092 09:30:56.789453 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2093 09:30:56.789859
2094 09:30:56.792585 MR0 0x3b3b
2095 09:30:56.793154 MR8 0x5151
2096 09:30:56.795896 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 09:30:56.796303
2098 09:30:56.806130 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2099 09:30:56.809498 [FAST_K] Save calibration result to emmc
2100 09:30:56.813008 [FAST_K] Save calibration result to emmc
2101 09:30:56.815798 dram_init: config_dvfs: 1
2102 09:30:56.819824 dramc_set_vcore_voltage set vcore to 662500
2103 09:30:56.822987 Read voltage for 1200, 2
2104 09:30:56.823449 Vio18 = 0
2105 09:30:56.823777 Vcore = 662500
2106 09:30:56.824086 Vdram = 0
2107 09:30:56.826579 Vddq = 0
2108 09:30:56.827331 Vmddr = 0
2109 09:30:56.832665 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2110 09:30:56.836595 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2111 09:30:56.839384 MEM_TYPE=3, freq_sel=15
2112 09:30:56.842398 sv_algorithm_assistance_LP4_1600
2113 09:30:56.845776 ============ PULL DRAM RESETB DOWN ============
2114 09:30:56.849263 ========== PULL DRAM RESETB DOWN end =========
2115 09:30:56.855812 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 09:30:56.859254 ===================================
2117 09:30:56.859677 LPDDR4 DRAM CONFIGURATION
2118 09:30:56.862390 ===================================
2119 09:30:56.866026 EX_ROW_EN[0] = 0x0
2120 09:30:56.868757 EX_ROW_EN[1] = 0x0
2121 09:30:56.869253 LP4Y_EN = 0x0
2122 09:30:56.872193 WORK_FSP = 0x0
2123 09:30:56.872675 WL = 0x4
2124 09:30:56.875646 RL = 0x4
2125 09:30:56.876062 BL = 0x2
2126 09:30:56.878805 RPST = 0x0
2127 09:30:56.879340 RD_PRE = 0x0
2128 09:30:56.882244 WR_PRE = 0x1
2129 09:30:56.882661 WR_PST = 0x0
2130 09:30:56.886135 DBI_WR = 0x0
2131 09:30:56.886568 DBI_RD = 0x0
2132 09:30:56.889035 OTF = 0x1
2133 09:30:56.892001 ===================================
2134 09:30:56.895397 ===================================
2135 09:30:56.895863 ANA top config
2136 09:30:56.899193 ===================================
2137 09:30:56.902085 DLL_ASYNC_EN = 0
2138 09:30:56.905357 ALL_SLAVE_EN = 0
2139 09:30:56.908452 NEW_RANK_MODE = 1
2140 09:30:56.908875 DLL_IDLE_MODE = 1
2141 09:30:56.912299 LP45_APHY_COMB_EN = 1
2142 09:30:56.915261 TX_ODT_DIS = 1
2143 09:30:56.918899 NEW_8X_MODE = 1
2144 09:30:56.921858 ===================================
2145 09:30:56.925047 ===================================
2146 09:30:56.928298 data_rate = 2400
2147 09:30:56.928716 CKR = 1
2148 09:30:56.932292 DQ_P2S_RATIO = 8
2149 09:30:56.935123 ===================================
2150 09:30:56.938373 CA_P2S_RATIO = 8
2151 09:30:56.941911 DQ_CA_OPEN = 0
2152 09:30:56.944658 DQ_SEMI_OPEN = 0
2153 09:30:56.948410 CA_SEMI_OPEN = 0
2154 09:30:56.948885 CA_FULL_RATE = 0
2155 09:30:56.951725 DQ_CKDIV4_EN = 0
2156 09:30:56.955045 CA_CKDIV4_EN = 0
2157 09:30:56.958463 CA_PREDIV_EN = 0
2158 09:30:56.961729 PH8_DLY = 17
2159 09:30:56.964680 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2160 09:30:56.965100 DQ_AAMCK_DIV = 4
2161 09:30:56.968117 CA_AAMCK_DIV = 4
2162 09:30:56.971299 CA_ADMCK_DIV = 4
2163 09:30:56.974738 DQ_TRACK_CA_EN = 0
2164 09:30:56.978213 CA_PICK = 1200
2165 09:30:56.981377 CA_MCKIO = 1200
2166 09:30:56.984762 MCKIO_SEMI = 0
2167 09:30:56.985179 PLL_FREQ = 2366
2168 09:30:56.988535 DQ_UI_PI_RATIO = 32
2169 09:30:56.991570 CA_UI_PI_RATIO = 0
2170 09:30:56.994562 ===================================
2171 09:30:56.998077 ===================================
2172 09:30:57.001369 memory_type:LPDDR4
2173 09:30:57.004438 GP_NUM : 10
2174 09:30:57.004856 SRAM_EN : 1
2175 09:30:57.007961 MD32_EN : 0
2176 09:30:57.010899 ===================================
2177 09:30:57.011383 [ANA_INIT] >>>>>>>>>>>>>>
2178 09:30:57.014214 <<<<<< [CONFIGURE PHASE]: ANA_TX
2179 09:30:57.018131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2180 09:30:57.021395 ===================================
2181 09:30:57.024165 data_rate = 2400,PCW = 0X5b00
2182 09:30:57.027629 ===================================
2183 09:30:57.031494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2184 09:30:57.037886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 09:30:57.044657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 09:30:57.047508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2187 09:30:57.050716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2188 09:30:57.054322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2189 09:30:57.057569 [ANA_INIT] flow start
2190 09:30:57.057988 [ANA_INIT] PLL >>>>>>>>
2191 09:30:57.060736 [ANA_INIT] PLL <<<<<<<<
2192 09:30:57.064558 [ANA_INIT] MIDPI >>>>>>>>
2193 09:30:57.065000 [ANA_INIT] MIDPI <<<<<<<<
2194 09:30:57.067787 [ANA_INIT] DLL >>>>>>>>
2195 09:30:57.070786 [ANA_INIT] DLL <<<<<<<<
2196 09:30:57.071236 [ANA_INIT] flow end
2197 09:30:57.077455 ============ LP4 DIFF to SE enter ============
2198 09:30:57.080674 ============ LP4 DIFF to SE exit ============
2199 09:30:57.084142 [ANA_INIT] <<<<<<<<<<<<<
2200 09:30:57.087421 [Flow] Enable top DCM control >>>>>
2201 09:30:57.090951 [Flow] Enable top DCM control <<<<<
2202 09:30:57.091555 Enable DLL master slave shuffle
2203 09:30:57.097862 ==============================================================
2204 09:30:57.100613 Gating Mode config
2205 09:30:57.103707 ==============================================================
2206 09:30:57.107177 Config description:
2207 09:30:57.117504 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2208 09:30:57.123917 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2209 09:30:57.127534 SELPH_MODE 0: By rank 1: By Phase
2210 09:30:57.134074 ==============================================================
2211 09:30:57.137319 GAT_TRACK_EN = 1
2212 09:30:57.140448 RX_GATING_MODE = 2
2213 09:30:57.144032 RX_GATING_TRACK_MODE = 2
2214 09:30:57.144613 SELPH_MODE = 1
2215 09:30:57.147669 PICG_EARLY_EN = 1
2216 09:30:57.150882 VALID_LAT_VALUE = 1
2217 09:30:57.157439 ==============================================================
2218 09:30:57.160631 Enter into Gating configuration >>>>
2219 09:30:57.163909 Exit from Gating configuration <<<<
2220 09:30:57.167157 Enter into DVFS_PRE_config >>>>>
2221 09:30:57.177132 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2222 09:30:57.180842 Exit from DVFS_PRE_config <<<<<
2223 09:30:57.183756 Enter into PICG configuration >>>>
2224 09:30:57.187144 Exit from PICG configuration <<<<
2225 09:30:57.190700 [RX_INPUT] configuration >>>>>
2226 09:30:57.193841 [RX_INPUT] configuration <<<<<
2227 09:30:57.197203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2228 09:30:57.203695 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2229 09:30:57.210413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 09:30:57.217085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 09:30:57.223909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 09:30:57.227069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 09:30:57.233960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2234 09:30:57.236997 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2235 09:30:57.240020 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2236 09:30:57.243806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2237 09:30:57.250001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2238 09:30:57.253863 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2239 09:30:57.257206 ===================================
2240 09:30:57.260311 LPDDR4 DRAM CONFIGURATION
2241 09:30:57.263529 ===================================
2242 09:30:57.263950 EX_ROW_EN[0] = 0x0
2243 09:30:57.267266 EX_ROW_EN[1] = 0x0
2244 09:30:57.267686 LP4Y_EN = 0x0
2245 09:30:57.269946 WORK_FSP = 0x0
2246 09:30:57.270471 WL = 0x4
2247 09:30:57.273297 RL = 0x4
2248 09:30:57.273707 BL = 0x2
2249 09:30:57.276882 RPST = 0x0
2250 09:30:57.277439 RD_PRE = 0x0
2251 09:30:57.280558 WR_PRE = 0x1
2252 09:30:57.281076 WR_PST = 0x0
2253 09:30:57.283586 DBI_WR = 0x0
2254 09:30:57.283995 DBI_RD = 0x0
2255 09:30:57.286762 OTF = 0x1
2256 09:30:57.289770 ===================================
2257 09:30:57.292978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2258 09:30:57.296354 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2259 09:30:57.303130 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 09:30:57.306582 ===================================
2261 09:30:57.309643 LPDDR4 DRAM CONFIGURATION
2262 09:30:57.313241 ===================================
2263 09:30:57.313664 EX_ROW_EN[0] = 0x10
2264 09:30:57.316143 EX_ROW_EN[1] = 0x0
2265 09:30:57.316563 LP4Y_EN = 0x0
2266 09:30:57.319672 WORK_FSP = 0x0
2267 09:30:57.320083 WL = 0x4
2268 09:30:57.322973 RL = 0x4
2269 09:30:57.323504 BL = 0x2
2270 09:30:57.326244 RPST = 0x0
2271 09:30:57.326659 RD_PRE = 0x0
2272 09:30:57.329270 WR_PRE = 0x1
2273 09:30:57.329617 WR_PST = 0x0
2274 09:30:57.333237 DBI_WR = 0x0
2275 09:30:57.333774 DBI_RD = 0x0
2276 09:30:57.336463 OTF = 0x1
2277 09:30:57.339518 ===================================
2278 09:30:57.346111 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2279 09:30:57.346610 ==
2280 09:30:57.349477 Dram Type= 6, Freq= 0, CH_0, rank 0
2281 09:30:57.352686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2282 09:30:57.353098 ==
2283 09:30:57.356073 [Duty_Offset_Calibration]
2284 09:30:57.356484 B0:2 B1:0 CA:4
2285 09:30:57.357118
2286 09:30:57.359252 [DutyScan_Calibration_Flow] k_type=0
2287 09:30:57.370657
2288 09:30:57.371268 ==CLK 0==
2289 09:30:57.373424 Final CLK duty delay cell = 0
2290 09:30:57.376686 [0] MAX Duty = 5156%(X100), DQS PI = 14
2291 09:30:57.380420 [0] MIN Duty = 4969%(X100), DQS PI = 8
2292 09:30:57.380829 [0] AVG Duty = 5062%(X100)
2293 09:30:57.383956
2294 09:30:57.386679 CH0 CLK Duty spec in!! Max-Min= 187%
2295 09:30:57.389993 [DutyScan_Calibration_Flow] ====Done====
2296 09:30:57.390398
2297 09:30:57.393600 [DutyScan_Calibration_Flow] k_type=1
2298 09:30:57.409722
2299 09:30:57.410127 ==DQS 0 ==
2300 09:30:57.412681 Final DQS duty delay cell = 0
2301 09:30:57.416456 [0] MAX Duty = 5156%(X100), DQS PI = 14
2302 09:30:57.419236 [0] MIN Duty = 5093%(X100), DQS PI = 2
2303 09:30:57.419646 [0] AVG Duty = 5124%(X100)
2304 09:30:57.422802
2305 09:30:57.423248 ==DQS 1 ==
2306 09:30:57.426062 Final DQS duty delay cell = 0
2307 09:30:57.429458 [0] MAX Duty = 5125%(X100), DQS PI = 52
2308 09:30:57.432376 [0] MIN Duty = 4969%(X100), DQS PI = 16
2309 09:30:57.435918 [0] AVG Duty = 5047%(X100)
2310 09:30:57.436325
2311 09:30:57.439240 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2312 09:30:57.439650
2313 09:30:57.442737 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2314 09:30:57.445712 [DutyScan_Calibration_Flow] ====Done====
2315 09:30:57.446123
2316 09:30:57.448914 [DutyScan_Calibration_Flow] k_type=3
2317 09:30:57.465732
2318 09:30:57.466273 ==DQM 0 ==
2319 09:30:57.469828 Final DQM duty delay cell = 0
2320 09:30:57.472300 [0] MAX Duty = 5125%(X100), DQS PI = 20
2321 09:30:57.475644 [0] MIN Duty = 4844%(X100), DQS PI = 54
2322 09:30:57.478693 [0] AVG Duty = 4984%(X100)
2323 09:30:57.479115
2324 09:30:57.479442 ==DQM 1 ==
2325 09:30:57.482351 Final DQM duty delay cell = 0
2326 09:30:57.485280 [0] MAX Duty = 4969%(X100), DQS PI = 2
2327 09:30:57.489364 [0] MIN Duty = 4907%(X100), DQS PI = 12
2328 09:30:57.492040 [0] AVG Duty = 4938%(X100)
2329 09:30:57.492503
2330 09:30:57.495215 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2331 09:30:57.495776
2332 09:30:57.499364 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2333 09:30:57.502365 [DutyScan_Calibration_Flow] ====Done====
2334 09:30:57.502899
2335 09:30:57.505381 [DutyScan_Calibration_Flow] k_type=2
2336 09:30:57.522651
2337 09:30:57.523053 ==DQ 0 ==
2338 09:30:57.525475 Final DQ duty delay cell = 0
2339 09:30:57.529004 [0] MAX Duty = 5125%(X100), DQS PI = 18
2340 09:30:57.532261 [0] MIN Duty = 4938%(X100), DQS PI = 58
2341 09:30:57.532667 [0] AVG Duty = 5031%(X100)
2342 09:30:57.535371
2343 09:30:57.535770 ==DQ 1 ==
2344 09:30:57.538771 Final DQ duty delay cell = 0
2345 09:30:57.541715 [0] MAX Duty = 5125%(X100), DQS PI = 6
2346 09:30:57.545097 [0] MIN Duty = 4938%(X100), DQS PI = 16
2347 09:30:57.545522 [0] AVG Duty = 5031%(X100)
2348 09:30:57.548523
2349 09:30:57.551800 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2350 09:30:57.552354
2351 09:30:57.555068 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2352 09:30:57.558787 [DutyScan_Calibration_Flow] ====Done====
2353 09:30:57.559416 ==
2354 09:30:57.561565 Dram Type= 6, Freq= 0, CH_1, rank 0
2355 09:30:57.565210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 09:30:57.565670 ==
2357 09:30:57.568479 [Duty_Offset_Calibration]
2358 09:30:57.569022 B0:0 B1:-1 CA:3
2359 09:30:57.569514
2360 09:30:57.571176 [DutyScan_Calibration_Flow] k_type=0
2361 09:30:57.581464
2362 09:30:57.582007 ==CLK 0==
2363 09:30:57.584812 Final CLK duty delay cell = -4
2364 09:30:57.588687 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2365 09:30:57.590929 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2366 09:30:57.594422 [-4] AVG Duty = 4938%(X100)
2367 09:30:57.594889
2368 09:30:57.597567 CH1 CLK Duty spec in!! Max-Min= 124%
2369 09:30:57.601272 [DutyScan_Calibration_Flow] ====Done====
2370 09:30:57.601678
2371 09:30:57.605051 [DutyScan_Calibration_Flow] k_type=1
2372 09:30:57.621424
2373 09:30:57.621860 ==DQS 0 ==
2374 09:30:57.624546 Final DQS duty delay cell = 0
2375 09:30:57.627794 [0] MAX Duty = 5187%(X100), DQS PI = 18
2376 09:30:57.631065 [0] MIN Duty = 4907%(X100), DQS PI = 38
2377 09:30:57.634209 [0] AVG Duty = 5047%(X100)
2378 09:30:57.634734
2379 09:30:57.635222 ==DQS 1 ==
2380 09:30:57.637514 Final DQS duty delay cell = 0
2381 09:30:57.641434 [0] MAX Duty = 5156%(X100), DQS PI = 8
2382 09:30:57.644960 [0] MIN Duty = 5031%(X100), DQS PI = 18
2383 09:30:57.647499 [0] AVG Duty = 5093%(X100)
2384 09:30:57.647941
2385 09:30:57.650559 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2386 09:30:57.651220
2387 09:30:57.653820 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2388 09:30:57.657412 [DutyScan_Calibration_Flow] ====Done====
2389 09:30:57.657825
2390 09:30:57.660969 [DutyScan_Calibration_Flow] k_type=3
2391 09:30:57.677553
2392 09:30:57.677966 ==DQM 0 ==
2393 09:30:57.680735 Final DQM duty delay cell = 0
2394 09:30:57.684253 [0] MAX Duty = 5031%(X100), DQS PI = 26
2395 09:30:57.687706 [0] MIN Duty = 4782%(X100), DQS PI = 38
2396 09:30:57.688120 [0] AVG Duty = 4906%(X100)
2397 09:30:57.690722
2398 09:30:57.691286 ==DQM 1 ==
2399 09:30:57.694240 Final DQM duty delay cell = 0
2400 09:30:57.697300 [0] MAX Duty = 4969%(X100), DQS PI = 26
2401 09:30:57.700458 [0] MIN Duty = 4844%(X100), DQS PI = 0
2402 09:30:57.700954 [0] AVG Duty = 4906%(X100)
2403 09:30:57.703669
2404 09:30:57.707176 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2405 09:30:57.707595
2406 09:30:57.710853 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2407 09:30:57.714152 [DutyScan_Calibration_Flow] ====Done====
2408 09:30:57.714580
2409 09:30:57.717080 [DutyScan_Calibration_Flow] k_type=2
2410 09:30:57.734096
2411 09:30:57.734511 ==DQ 0 ==
2412 09:30:57.737658 Final DQ duty delay cell = -4
2413 09:30:57.741160 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2414 09:30:57.743831 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2415 09:30:57.747246 [-4] AVG Duty = 4953%(X100)
2416 09:30:57.747660
2417 09:30:57.747988 ==DQ 1 ==
2418 09:30:57.750326 Final DQ duty delay cell = 4
2419 09:30:57.753836 [4] MAX Duty = 5156%(X100), DQS PI = 26
2420 09:30:57.757467 [4] MIN Duty = 5031%(X100), DQS PI = 62
2421 09:30:57.760418 [4] AVG Duty = 5093%(X100)
2422 09:30:57.760972
2423 09:30:57.763797 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2424 09:30:57.764230
2425 09:30:57.767906 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2426 09:30:57.770052 [DutyScan_Calibration_Flow] ====Done====
2427 09:30:57.773815 nWR fixed to 30
2428 09:30:57.776943 [ModeRegInit_LP4] CH0 RK0
2429 09:30:57.777387 [ModeRegInit_LP4] CH0 RK1
2430 09:30:57.780249 [ModeRegInit_LP4] CH1 RK0
2431 09:30:57.783435 [ModeRegInit_LP4] CH1 RK1
2432 09:30:57.783849 match AC timing 7
2433 09:30:57.790350 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2434 09:30:57.793440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2435 09:30:57.796709 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2436 09:30:57.803799 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2437 09:30:57.806737 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2438 09:30:57.807182 ==
2439 09:30:57.810144 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 09:30:57.813056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 09:30:57.813489 ==
2442 09:30:57.820175 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2443 09:30:57.826340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2444 09:30:57.834493 [CA 0] Center 39 (9~70) winsize 62
2445 09:30:57.837481 [CA 1] Center 39 (9~70) winsize 62
2446 09:30:57.840910 [CA 2] Center 35 (5~66) winsize 62
2447 09:30:57.843881 [CA 3] Center 35 (5~66) winsize 62
2448 09:30:57.847542 [CA 4] Center 33 (3~64) winsize 62
2449 09:30:57.850884 [CA 5] Center 33 (3~63) winsize 61
2450 09:30:57.851337
2451 09:30:57.853921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2452 09:30:57.854340
2453 09:30:57.857674 [CATrainingPosCal] consider 1 rank data
2454 09:30:57.861267 u2DelayCellTimex100 = 270/100 ps
2455 09:30:57.864497 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2456 09:30:57.867700 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2457 09:30:57.874402 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2458 09:30:57.877596 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 09:30:57.881306 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2460 09:30:57.884274 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2461 09:30:57.884704
2462 09:30:57.887193 CA PerBit enable=1, Macro0, CA PI delay=33
2463 09:30:57.887611
2464 09:30:57.890640 [CBTSetCACLKResult] CA Dly = 33
2465 09:30:57.891055 CS Dly: 7 (0~38)
2466 09:30:57.894155 ==
2467 09:30:57.897602 Dram Type= 6, Freq= 0, CH_0, rank 1
2468 09:30:57.900531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 09:30:57.900949 ==
2470 09:30:57.903935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 09:30:57.910455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 09:30:57.919930 [CA 0] Center 39 (9~70) winsize 62
2473 09:30:57.923174 [CA 1] Center 39 (9~70) winsize 62
2474 09:30:57.926440 [CA 2] Center 35 (5~66) winsize 62
2475 09:30:57.930223 [CA 3] Center 35 (5~66) winsize 62
2476 09:30:57.933246 [CA 4] Center 34 (4~65) winsize 62
2477 09:30:57.936647 [CA 5] Center 33 (3~64) winsize 62
2478 09:30:57.937081
2479 09:30:57.939959 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2480 09:30:57.940379
2481 09:30:57.943267 [CATrainingPosCal] consider 2 rank data
2482 09:30:57.946500 u2DelayCellTimex100 = 270/100 ps
2483 09:30:57.949457 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 09:30:57.956422 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 09:30:57.959617 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 09:30:57.963107 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 09:30:57.966353 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2488 09:30:57.969745 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2489 09:30:57.970182
2490 09:30:57.972843 CA PerBit enable=1, Macro0, CA PI delay=33
2491 09:30:57.973247
2492 09:30:57.976491 [CBTSetCACLKResult] CA Dly = 33
2493 09:30:57.976901 CS Dly: 8 (0~41)
2494 09:30:57.979978
2495 09:30:57.983168 ----->DramcWriteLeveling(PI) begin...
2496 09:30:57.983729 ==
2497 09:30:57.986342 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 09:30:57.989514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 09:30:57.989919 ==
2500 09:30:57.992617 Write leveling (Byte 0): 32 => 32
2501 09:30:57.996287 Write leveling (Byte 1): 27 => 27
2502 09:30:57.999404 DramcWriteLeveling(PI) end<-----
2503 09:30:57.999807
2504 09:30:58.000129 ==
2505 09:30:58.003321 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 09:30:58.006304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 09:30:58.006751 ==
2508 09:30:58.009648 [Gating] SW mode calibration
2509 09:30:58.016410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2510 09:30:58.023202 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2511 09:30:58.026449 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2512 09:30:58.029179 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2513 09:30:58.035996 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 09:30:58.039648 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 09:30:58.042484 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 09:30:58.049627 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 09:30:58.052981 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2518 09:30:58.055966 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2519 09:30:58.059633 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
2520 09:30:58.065838 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 09:30:58.069185 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 09:30:58.073012 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 09:30:58.079137 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 09:30:58.082638 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 09:30:58.085588 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2526 09:30:58.092589 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2527 09:30:58.095705 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2528 09:30:58.099161 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 09:30:58.105657 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 09:30:58.109434 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 09:30:58.112833 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 09:30:58.119198 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 09:30:58.121958 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 09:30:58.125595 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 09:30:58.132749 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2536 09:30:58.135673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 09:30:58.139053 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 09:30:58.145439 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 09:30:58.149204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 09:30:58.152156 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 09:30:58.158454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 09:30:58.162664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 09:30:58.165817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 09:30:58.171877 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 09:30:58.175848 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 09:30:58.178449 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 09:30:58.185722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 09:30:58.188408 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 09:30:58.191747 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2550 09:30:58.198393 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2551 09:30:58.202032 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2552 09:30:58.205564 Total UI for P1: 0, mck2ui 16
2553 09:30:58.208245 best dqsien dly found for B0: ( 1, 3, 26)
2554 09:30:58.212222 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 09:30:58.218761 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 09:30:58.219210 Total UI for P1: 0, mck2ui 16
2557 09:30:58.221934 best dqsien dly found for B1: ( 1, 4, 2)
2558 09:30:58.229469 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2559 09:30:58.231904 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2560 09:30:58.232324
2561 09:30:58.234990 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2562 09:30:58.238368 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2563 09:30:58.241213 [Gating] SW calibration Done
2564 09:30:58.241741 ==
2565 09:30:58.244516 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 09:30:58.248126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 09:30:58.248208 ==
2568 09:30:58.251224 RX Vref Scan: 0
2569 09:30:58.251304
2570 09:30:58.251368 RX Vref 0 -> 0, step: 1
2571 09:30:58.251427
2572 09:30:58.254652 RX Delay -40 -> 252, step: 8
2573 09:30:58.258222 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 09:30:58.264897 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2575 09:30:58.268109 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 09:30:58.270992 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2577 09:30:58.274184 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2578 09:30:58.277379 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2579 09:30:58.284291 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 09:30:58.287445 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2581 09:30:58.291340 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2582 09:30:58.294691 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2583 09:30:58.297883 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2584 09:30:58.301092 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2585 09:30:58.307862 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2586 09:30:58.311541 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2587 09:30:58.314636 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2588 09:30:58.317965 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2589 09:30:58.318384 ==
2590 09:30:58.321473 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 09:30:58.328017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 09:30:58.328518 ==
2593 09:30:58.328854 DQS Delay:
2594 09:30:58.331472 DQS0 = 0, DQS1 = 0
2595 09:30:58.331881 DQM Delay:
2596 09:30:58.332273 DQM0 = 119, DQM1 = 107
2597 09:30:58.335550 DQ Delay:
2598 09:30:58.338119 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2599 09:30:58.341476 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2600 09:30:58.345066 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2601 09:30:58.348111 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2602 09:30:58.348522
2603 09:30:58.348843
2604 09:30:58.349145 ==
2605 09:30:58.351382 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 09:30:58.354648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 09:30:58.357985 ==
2608 09:30:58.358399
2609 09:30:58.358725
2610 09:30:58.359031 TX Vref Scan disable
2611 09:30:58.360898 == TX Byte 0 ==
2612 09:30:58.364222 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2613 09:30:58.367768 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2614 09:30:58.371205 == TX Byte 1 ==
2615 09:30:58.374274 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2616 09:30:58.377505 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2617 09:30:58.380970 ==
2618 09:30:58.384050 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 09:30:58.387780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 09:30:58.388200 ==
2621 09:30:58.398798 TX Vref=22, minBit 4, minWin=25, winSum=411
2622 09:30:58.402432 TX Vref=24, minBit 8, minWin=25, winSum=419
2623 09:30:58.406272 TX Vref=26, minBit 8, minWin=25, winSum=422
2624 09:30:58.408783 TX Vref=28, minBit 10, minWin=25, winSum=427
2625 09:30:58.411904 TX Vref=30, minBit 5, minWin=26, winSum=430
2626 09:30:58.418573 TX Vref=32, minBit 2, minWin=26, winSum=429
2627 09:30:58.422029 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 30
2628 09:30:58.422608
2629 09:30:58.425204 Final TX Range 1 Vref 30
2630 09:30:58.425761
2631 09:30:58.426235 ==
2632 09:30:58.428568 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 09:30:58.431633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 09:30:58.434972 ==
2635 09:30:58.435446
2636 09:30:58.435775
2637 09:30:58.436075 TX Vref Scan disable
2638 09:30:58.438680 == TX Byte 0 ==
2639 09:30:58.441880 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 09:30:58.445563 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 09:30:58.449114 == TX Byte 1 ==
2642 09:30:58.452166 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 09:30:58.455778 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 09:30:58.458840
2645 09:30:58.459287 [DATLAT]
2646 09:30:58.459623 Freq=1200, CH0 RK0
2647 09:30:58.459933
2648 09:30:58.461878 DATLAT Default: 0xd
2649 09:30:58.462291 0, 0xFFFF, sum = 0
2650 09:30:58.465650 1, 0xFFFF, sum = 0
2651 09:30:58.466073 2, 0xFFFF, sum = 0
2652 09:30:58.468985 3, 0xFFFF, sum = 0
2653 09:30:58.472459 4, 0xFFFF, sum = 0
2654 09:30:58.472904 5, 0xFFFF, sum = 0
2655 09:30:58.475705 6, 0xFFFF, sum = 0
2656 09:30:58.476199 7, 0xFFFF, sum = 0
2657 09:30:58.478680 8, 0xFFFF, sum = 0
2658 09:30:58.479159 9, 0xFFFF, sum = 0
2659 09:30:58.481981 10, 0xFFFF, sum = 0
2660 09:30:58.482406 11, 0xFFFF, sum = 0
2661 09:30:58.485539 12, 0x0, sum = 1
2662 09:30:58.485964 13, 0x0, sum = 2
2663 09:30:58.488791 14, 0x0, sum = 3
2664 09:30:58.489291 15, 0x0, sum = 4
2665 09:30:58.489653 best_step = 13
2666 09:30:58.491752
2667 09:30:58.492212 ==
2668 09:30:58.495213 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 09:30:58.498625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 09:30:58.499045 ==
2671 09:30:58.499435 RX Vref Scan: 1
2672 09:30:58.499748
2673 09:30:58.501977 Set Vref Range= 32 -> 127
2674 09:30:58.502393
2675 09:30:58.505233 RX Vref 32 -> 127, step: 1
2676 09:30:58.505648
2677 09:30:58.508600 RX Delay -21 -> 252, step: 4
2678 09:30:58.509091
2679 09:30:58.512180 Set Vref, RX VrefLevel [Byte0]: 32
2680 09:30:58.515277 [Byte1]: 32
2681 09:30:58.515763
2682 09:30:58.518277 Set Vref, RX VrefLevel [Byte0]: 33
2683 09:30:58.521639 [Byte1]: 33
2684 09:30:58.525646
2685 09:30:58.526062 Set Vref, RX VrefLevel [Byte0]: 34
2686 09:30:58.528886 [Byte1]: 34
2687 09:30:58.533486
2688 09:30:58.533901 Set Vref, RX VrefLevel [Byte0]: 35
2689 09:30:58.536446 [Byte1]: 35
2690 09:30:58.541115
2691 09:30:58.541531 Set Vref, RX VrefLevel [Byte0]: 36
2692 09:30:58.544494 [Byte1]: 36
2693 09:30:58.549172
2694 09:30:58.549587 Set Vref, RX VrefLevel [Byte0]: 37
2695 09:30:58.552857 [Byte1]: 37
2696 09:30:58.557297
2697 09:30:58.557890 Set Vref, RX VrefLevel [Byte0]: 38
2698 09:30:58.560177 [Byte1]: 38
2699 09:30:58.564895
2700 09:30:58.565348 Set Vref, RX VrefLevel [Byte0]: 39
2701 09:30:58.568129 [Byte1]: 39
2702 09:30:58.572770
2703 09:30:58.573335 Set Vref, RX VrefLevel [Byte0]: 40
2704 09:30:58.575976 [Byte1]: 40
2705 09:30:58.580763
2706 09:30:58.581181 Set Vref, RX VrefLevel [Byte0]: 41
2707 09:30:58.584118 [Byte1]: 41
2708 09:30:58.588801
2709 09:30:58.589216 Set Vref, RX VrefLevel [Byte0]: 42
2710 09:30:58.592291 [Byte1]: 42
2711 09:30:58.596870
2712 09:30:58.597433 Set Vref, RX VrefLevel [Byte0]: 43
2713 09:30:58.600877 [Byte1]: 43
2714 09:30:58.604297
2715 09:30:58.604793 Set Vref, RX VrefLevel [Byte0]: 44
2716 09:30:58.608136 [Byte1]: 44
2717 09:30:58.612709
2718 09:30:58.613234 Set Vref, RX VrefLevel [Byte0]: 45
2719 09:30:58.615649 [Byte1]: 45
2720 09:30:58.620082
2721 09:30:58.620645 Set Vref, RX VrefLevel [Byte0]: 46
2722 09:30:58.623635 [Byte1]: 46
2723 09:30:58.628459
2724 09:30:58.628877 Set Vref, RX VrefLevel [Byte0]: 47
2725 09:30:58.631869 [Byte1]: 47
2726 09:30:58.636258
2727 09:30:58.636672 Set Vref, RX VrefLevel [Byte0]: 48
2728 09:30:58.639287 [Byte1]: 48
2729 09:30:58.643907
2730 09:30:58.644449 Set Vref, RX VrefLevel [Byte0]: 49
2731 09:30:58.647921 [Byte1]: 49
2732 09:30:58.652403
2733 09:30:58.652816 Set Vref, RX VrefLevel [Byte0]: 50
2734 09:30:58.655632 [Byte1]: 50
2735 09:30:58.659716
2736 09:30:58.663178 Set Vref, RX VrefLevel [Byte0]: 51
2737 09:30:58.666753 [Byte1]: 51
2738 09:30:58.667201
2739 09:30:58.670054 Set Vref, RX VrefLevel [Byte0]: 52
2740 09:30:58.673432 [Byte1]: 52
2741 09:30:58.673960
2742 09:30:58.676668 Set Vref, RX VrefLevel [Byte0]: 53
2743 09:30:58.679556 [Byte1]: 53
2744 09:30:58.683715
2745 09:30:58.684260 Set Vref, RX VrefLevel [Byte0]: 54
2746 09:30:58.686736 [Byte1]: 54
2747 09:30:58.691985
2748 09:30:58.692397 Set Vref, RX VrefLevel [Byte0]: 55
2749 09:30:58.694904 [Byte1]: 55
2750 09:30:58.699595
2751 09:30:58.700112 Set Vref, RX VrefLevel [Byte0]: 56
2752 09:30:58.703023 [Byte1]: 56
2753 09:30:58.708028
2754 09:30:58.708547 Set Vref, RX VrefLevel [Byte0]: 57
2755 09:30:58.711250 [Byte1]: 57
2756 09:30:58.715562
2757 09:30:58.716101 Set Vref, RX VrefLevel [Byte0]: 58
2758 09:30:58.719120 [Byte1]: 58
2759 09:30:58.724071
2760 09:30:58.724585 Set Vref, RX VrefLevel [Byte0]: 59
2761 09:30:58.726804 [Byte1]: 59
2762 09:30:58.730984
2763 09:30:58.731549 Set Vref, RX VrefLevel [Byte0]: 60
2764 09:30:58.734306 [Byte1]: 60
2765 09:30:58.739208
2766 09:30:58.739622 Set Vref, RX VrefLevel [Byte0]: 61
2767 09:30:58.743223 [Byte1]: 61
2768 09:30:58.746953
2769 09:30:58.747399 Set Vref, RX VrefLevel [Byte0]: 62
2770 09:30:58.750566 [Byte1]: 62
2771 09:30:58.754802
2772 09:30:58.755399 Set Vref, RX VrefLevel [Byte0]: 63
2773 09:30:58.758495 [Byte1]: 63
2774 09:30:58.763009
2775 09:30:58.763465 Set Vref, RX VrefLevel [Byte0]: 64
2776 09:30:58.766466 [Byte1]: 64
2777 09:30:58.770921
2778 09:30:58.771367 Set Vref, RX VrefLevel [Byte0]: 65
2779 09:30:58.774571 [Byte1]: 65
2780 09:30:58.779411
2781 09:30:58.779828 Set Vref, RX VrefLevel [Byte0]: 66
2782 09:30:58.782039 [Byte1]: 66
2783 09:30:58.787222
2784 09:30:58.787732 Set Vref, RX VrefLevel [Byte0]: 67
2785 09:30:58.790456 [Byte1]: 67
2786 09:30:58.795240
2787 09:30:58.795776 Final RX Vref Byte 0 = 55 to rank0
2788 09:30:58.798384 Final RX Vref Byte 1 = 51 to rank0
2789 09:30:58.801017 Final RX Vref Byte 0 = 55 to rank1
2790 09:30:58.804993 Final RX Vref Byte 1 = 51 to rank1==
2791 09:30:58.807902 Dram Type= 6, Freq= 0, CH_0, rank 0
2792 09:30:58.814519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2793 09:30:58.814939 ==
2794 09:30:58.815315 DQS Delay:
2795 09:30:58.815723 DQS0 = 0, DQS1 = 0
2796 09:30:58.817769 DQM Delay:
2797 09:30:58.818184 DQM0 = 119, DQM1 = 105
2798 09:30:58.821352 DQ Delay:
2799 09:30:58.824497 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =114
2800 09:30:58.827761 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2801 09:30:58.831055 DQ8 =96, DQ9 =90, DQ10 =106, DQ11 =100
2802 09:30:58.834615 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2803 09:30:58.835206
2804 09:30:58.835596
2805 09:30:58.844416 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 411 ps
2806 09:30:58.844839 CH0 RK0: MR19=303, MR18=FCF8
2807 09:30:58.851172 CH0_RK0: MR19=0x303, MR18=0xFCF8, DQSOSC=411, MR23=63, INC=38, DEC=25
2808 09:30:58.851594
2809 09:30:58.854429 ----->DramcWriteLeveling(PI) begin...
2810 09:30:58.854851 ==
2811 09:30:58.857851 Dram Type= 6, Freq= 0, CH_0, rank 1
2812 09:30:58.864115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 09:30:58.864755 ==
2814 09:30:58.867721 Write leveling (Byte 0): 30 => 30
2815 09:30:58.868177 Write leveling (Byte 1): 26 => 26
2816 09:30:58.870878 DramcWriteLeveling(PI) end<-----
2817 09:30:58.871381
2818 09:30:58.871710 ==
2819 09:30:58.874230 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 09:30:58.880627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 09:30:58.881039 ==
2822 09:30:58.884513 [Gating] SW mode calibration
2823 09:30:58.890776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2824 09:30:58.894135 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2825 09:30:58.900458 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2826 09:30:58.903785 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2827 09:30:58.907519 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2828 09:30:58.913776 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2829 09:30:58.917453 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 09:30:58.920982 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 09:30:58.927345 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2832 09:30:58.930373 0 15 28 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
2833 09:30:58.933709 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2834 09:30:58.940354 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2835 09:30:58.943694 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2836 09:30:58.947112 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 09:30:58.950397 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 09:30:58.956832 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 09:30:58.960471 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2840 09:30:58.963768 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2841 09:30:58.970302 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2842 09:30:58.973714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2843 09:30:58.977265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2844 09:30:58.983680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 09:30:58.986929 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 09:30:58.990125 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 09:30:58.996630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2848 09:30:59.001445 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2849 09:30:59.003311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2850 09:30:59.009892 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 09:30:59.013161 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 09:30:59.016274 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 09:30:59.022870 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 09:30:59.026452 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 09:30:59.030261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 09:30:59.036134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 09:30:59.039862 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 09:30:59.043222 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 09:30:59.049371 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 09:30:59.052809 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 09:30:59.056160 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 09:30:59.062808 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 09:30:59.066547 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2864 09:30:59.069558 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2865 09:30:59.073217 Total UI for P1: 0, mck2ui 16
2866 09:30:59.075978 best dqsien dly found for B0: ( 1, 3, 24)
2867 09:30:59.082902 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2868 09:30:59.086294 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 09:30:59.089372 Total UI for P1: 0, mck2ui 16
2870 09:30:59.092721 best dqsien dly found for B1: ( 1, 3, 30)
2871 09:30:59.095932 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2872 09:30:59.099567 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2873 09:30:59.099647
2874 09:30:59.102752 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2875 09:30:59.106110 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2876 09:30:59.109247 [Gating] SW calibration Done
2877 09:30:59.109332 ==
2878 09:30:59.113183 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 09:30:59.116598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 09:30:59.119160 ==
2881 09:30:59.119240 RX Vref Scan: 0
2882 09:30:59.119315
2883 09:30:59.122369 RX Vref 0 -> 0, step: 1
2884 09:30:59.122448
2885 09:30:59.122511 RX Delay -40 -> 252, step: 8
2886 09:30:59.129105 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2887 09:30:59.132549 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2888 09:30:59.135943 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2889 09:30:59.139029 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2890 09:30:59.145861 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2891 09:30:59.149484 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2892 09:30:59.152459 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2893 09:30:59.155575 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2894 09:30:59.158876 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2895 09:30:59.162090 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2896 09:30:59.169030 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2897 09:30:59.172174 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2898 09:30:59.175566 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2899 09:30:59.179009 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2900 09:30:59.185232 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2901 09:30:59.188778 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2902 09:30:59.188858 ==
2903 09:30:59.192282 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 09:30:59.195640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 09:30:59.195721 ==
2906 09:30:59.199172 DQS Delay:
2907 09:30:59.199252 DQS0 = 0, DQS1 = 0
2908 09:30:59.199316 DQM Delay:
2909 09:30:59.202191 DQM0 = 119, DQM1 = 106
2910 09:30:59.202270 DQ Delay:
2911 09:30:59.205595 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2912 09:30:59.209147 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2913 09:30:59.211968 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2914 09:30:59.215469 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2915 09:30:59.218859
2916 09:30:59.218963
2917 09:30:59.219060 ==
2918 09:30:59.221988 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 09:30:59.225880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 09:30:59.225960 ==
2921 09:30:59.226023
2922 09:30:59.226081
2923 09:30:59.228713 TX Vref Scan disable
2924 09:30:59.228792 == TX Byte 0 ==
2925 09:30:59.235709 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2926 09:30:59.238869 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2927 09:30:59.238978 == TX Byte 1 ==
2928 09:30:59.245437 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2929 09:30:59.249062 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2930 09:30:59.249142 ==
2931 09:30:59.251884 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 09:30:59.255417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 09:30:59.255523 ==
2934 09:30:59.268359 TX Vref=22, minBit 0, minWin=24, winSum=407
2935 09:30:59.271677 TX Vref=24, minBit 0, minWin=25, winSum=412
2936 09:30:59.274722 TX Vref=26, minBit 2, minWin=25, winSum=418
2937 09:30:59.278236 TX Vref=28, minBit 10, minWin=25, winSum=424
2938 09:30:59.281357 TX Vref=30, minBit 4, minWin=26, winSum=427
2939 09:30:59.287841 TX Vref=32, minBit 3, minWin=26, winSum=423
2940 09:30:59.291491 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 30
2941 09:30:59.291571
2942 09:30:59.294353 Final TX Range 1 Vref 30
2943 09:30:59.294433
2944 09:30:59.294496 ==
2945 09:30:59.297785 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 09:30:59.301154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 09:30:59.304475 ==
2948 09:30:59.304555
2949 09:30:59.304618
2950 09:30:59.304676 TX Vref Scan disable
2951 09:30:59.307935 == TX Byte 0 ==
2952 09:30:59.310894 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2953 09:30:59.315004 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2954 09:30:59.317811 == TX Byte 1 ==
2955 09:30:59.321054 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2956 09:30:59.328040 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2957 09:30:59.328120
2958 09:30:59.328183 [DATLAT]
2959 09:30:59.328241 Freq=1200, CH0 RK1
2960 09:30:59.328299
2961 09:30:59.330987 DATLAT Default: 0xd
2962 09:30:59.331129 0, 0xFFFF, sum = 0
2963 09:30:59.334359 1, 0xFFFF, sum = 0
2964 09:30:59.337675 2, 0xFFFF, sum = 0
2965 09:30:59.337755 3, 0xFFFF, sum = 0
2966 09:30:59.340885 4, 0xFFFF, sum = 0
2967 09:30:59.340965 5, 0xFFFF, sum = 0
2968 09:30:59.344219 6, 0xFFFF, sum = 0
2969 09:30:59.344300 7, 0xFFFF, sum = 0
2970 09:30:59.347580 8, 0xFFFF, sum = 0
2971 09:30:59.347661 9, 0xFFFF, sum = 0
2972 09:30:59.351682 10, 0xFFFF, sum = 0
2973 09:30:59.351763 11, 0xFFFF, sum = 0
2974 09:30:59.354079 12, 0x0, sum = 1
2975 09:30:59.354160 13, 0x0, sum = 2
2976 09:30:59.358032 14, 0x0, sum = 3
2977 09:30:59.358113 15, 0x0, sum = 4
2978 09:30:59.360844 best_step = 13
2979 09:30:59.360924
2980 09:30:59.360987 ==
2981 09:30:59.364571 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 09:30:59.368028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 09:30:59.368108 ==
2984 09:30:59.368171 RX Vref Scan: 0
2985 09:30:59.368230
2986 09:30:59.371322 RX Vref 0 -> 0, step: 1
2987 09:30:59.371401
2988 09:30:59.374226 RX Delay -21 -> 252, step: 4
2989 09:30:59.377297 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2990 09:30:59.384469 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
2991 09:30:59.387239 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
2992 09:30:59.390878 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
2993 09:30:59.394406 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
2994 09:30:59.397559 iDelay=195, Bit 5, Center 110 (47 ~ 174) 128
2995 09:30:59.404047 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
2996 09:30:59.407238 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
2997 09:30:59.410981 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
2998 09:30:59.413834 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
2999 09:30:59.417496 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3000 09:30:59.423746 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3001 09:30:59.427423 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3002 09:30:59.430363 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3003 09:30:59.433814 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3004 09:30:59.440203 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3005 09:30:59.440285 ==
3006 09:30:59.443275 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 09:30:59.446708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 09:30:59.446788 ==
3009 09:30:59.446852 DQS Delay:
3010 09:30:59.450170 DQS0 = 0, DQS1 = 0
3011 09:30:59.450265 DQM Delay:
3012 09:30:59.453334 DQM0 = 118, DQM1 = 107
3013 09:30:59.453461 DQ Delay:
3014 09:30:59.456536 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3015 09:30:59.459881 DQ4 =122, DQ5 =110, DQ6 =128, DQ7 =124
3016 09:30:59.463671 DQ8 =94, DQ9 =94, DQ10 =108, DQ11 =98
3017 09:30:59.466468 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =116
3018 09:30:59.466548
3019 09:30:59.466611
3020 09:30:59.476519 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3021 09:30:59.480169 CH0 RK1: MR19=303, MR18=FAF7
3022 09:30:59.483411 CH0_RK1: MR19=0x303, MR18=0xFAF7, DQSOSC=412, MR23=63, INC=38, DEC=25
3023 09:30:59.487019 [RxdqsGatingPostProcess] freq 1200
3024 09:30:59.493105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3025 09:30:59.496496 best DQS0 dly(2T, 0.5T) = (0, 11)
3026 09:30:59.500062 best DQS1 dly(2T, 0.5T) = (0, 12)
3027 09:30:59.503809 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3028 09:30:59.506324 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3029 09:30:59.510083 best DQS0 dly(2T, 0.5T) = (0, 11)
3030 09:30:59.513304 best DQS1 dly(2T, 0.5T) = (0, 11)
3031 09:30:59.516450 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3032 09:30:59.519849 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3033 09:30:59.523617 Pre-setting of DQS Precalculation
3034 09:30:59.526887 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3035 09:30:59.526969 ==
3036 09:30:59.529816 Dram Type= 6, Freq= 0, CH_1, rank 0
3037 09:30:59.533165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 09:30:59.533246 ==
3039 09:30:59.539685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3040 09:30:59.546449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3041 09:30:59.554241 [CA 0] Center 38 (8~68) winsize 61
3042 09:30:59.557902 [CA 1] Center 37 (7~68) winsize 62
3043 09:30:59.560859 [CA 2] Center 35 (5~65) winsize 61
3044 09:30:59.564338 [CA 3] Center 34 (4~64) winsize 61
3045 09:30:59.567025 [CA 4] Center 35 (5~65) winsize 61
3046 09:30:59.570612 [CA 5] Center 34 (4~64) winsize 61
3047 09:30:59.570693
3048 09:30:59.574873 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3049 09:30:59.574979
3050 09:30:59.577728 [CATrainingPosCal] consider 1 rank data
3051 09:30:59.580657 u2DelayCellTimex100 = 270/100 ps
3052 09:30:59.584111 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3053 09:30:59.590292 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3054 09:30:59.593676 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3055 09:30:59.597266 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3056 09:30:59.600510 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3057 09:30:59.603877 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3058 09:30:59.603959
3059 09:30:59.607044 CA PerBit enable=1, Macro0, CA PI delay=34
3060 09:30:59.607171
3061 09:30:59.610705 [CBTSetCACLKResult] CA Dly = 34
3062 09:30:59.610803 CS Dly: 5 (0~36)
3063 09:30:59.613950 ==
3064 09:30:59.617288 Dram Type= 6, Freq= 0, CH_1, rank 1
3065 09:30:59.620277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 09:30:59.620359 ==
3067 09:30:59.624102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 09:30:59.630399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3069 09:30:59.640186 [CA 0] Center 37 (7~68) winsize 62
3070 09:30:59.643745 [CA 1] Center 38 (8~68) winsize 61
3071 09:30:59.647343 [CA 2] Center 34 (4~65) winsize 62
3072 09:30:59.649804 [CA 3] Center 33 (3~64) winsize 62
3073 09:30:59.653366 [CA 4] Center 34 (4~64) winsize 61
3074 09:30:59.656074 [CA 5] Center 33 (3~64) winsize 62
3075 09:30:59.656156
3076 09:30:59.659470 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3077 09:30:59.659605
3078 09:30:59.662930 [CATrainingPosCal] consider 2 rank data
3079 09:30:59.666401 u2DelayCellTimex100 = 270/100 ps
3080 09:30:59.669651 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3081 09:30:59.676294 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3082 09:30:59.679639 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3083 09:30:59.682947 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3084 09:30:59.685972 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3085 09:30:59.689364 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3086 09:30:59.689445
3087 09:30:59.692605 CA PerBit enable=1, Macro0, CA PI delay=34
3088 09:30:59.692686
3089 09:30:59.696290 [CBTSetCACLKResult] CA Dly = 34
3090 09:30:59.696371 CS Dly: 6 (0~39)
3091 09:30:59.696436
3092 09:30:59.702924 ----->DramcWriteLeveling(PI) begin...
3093 09:30:59.703006 ==
3094 09:30:59.706196 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 09:30:59.709388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 09:30:59.709470 ==
3097 09:30:59.713226 Write leveling (Byte 0): 25 => 25
3098 09:30:59.716431 Write leveling (Byte 1): 27 => 27
3099 09:30:59.719301 DramcWriteLeveling(PI) end<-----
3100 09:30:59.719383
3101 09:30:59.719447 ==
3102 09:30:59.722865 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 09:30:59.725912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 09:30:59.725993 ==
3105 09:30:59.729484 [Gating] SW mode calibration
3106 09:30:59.736132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3107 09:30:59.742941 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3108 09:30:59.745728 0 15 0 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
3109 09:30:59.749472 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 09:30:59.756089 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 09:30:59.759041 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 09:30:59.762353 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 09:30:59.769102 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 09:30:59.772177 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3115 09:30:59.775926 0 15 28 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 1)
3116 09:30:59.782394 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3117 09:30:59.785689 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 09:30:59.788599 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 09:30:59.795391 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 09:30:59.799106 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 09:30:59.801936 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 09:30:59.809104 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3123 09:30:59.811818 1 0 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
3124 09:30:59.815094 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3125 09:30:59.821822 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 09:30:59.825166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 09:30:59.828829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 09:30:59.832547 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 09:30:59.838722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 09:30:59.842470 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 09:30:59.845893 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3132 09:30:59.851771 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3133 09:30:59.855839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 09:30:59.858251 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 09:30:59.865404 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 09:30:59.868363 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 09:30:59.871727 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 09:30:59.878347 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 09:30:59.881724 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 09:30:59.885156 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 09:30:59.891457 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 09:30:59.895536 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 09:30:59.898119 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 09:30:59.904591 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 09:30:59.908178 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 09:30:59.911613 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 09:30:59.917911 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3148 09:30:59.921171 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 09:30:59.924538 Total UI for P1: 0, mck2ui 16
3150 09:30:59.928248 best dqsien dly found for B0: ( 1, 3, 28)
3151 09:30:59.931502 Total UI for P1: 0, mck2ui 16
3152 09:30:59.934831 best dqsien dly found for B1: ( 1, 3, 28)
3153 09:30:59.937830 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3154 09:30:59.941474 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3155 09:30:59.941580
3156 09:30:59.944616 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3157 09:30:59.947821 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3158 09:30:59.951112 [Gating] SW calibration Done
3159 09:30:59.951231 ==
3160 09:30:59.954498 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 09:30:59.957503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 09:30:59.961118 ==
3163 09:30:59.961258 RX Vref Scan: 0
3164 09:30:59.961378
3165 09:30:59.964137 RX Vref 0 -> 0, step: 1
3166 09:30:59.964239
3167 09:30:59.967826 RX Delay -40 -> 252, step: 8
3168 09:30:59.971035 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3169 09:30:59.974308 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3170 09:30:59.978089 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3171 09:30:59.981336 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3172 09:30:59.987824 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3173 09:30:59.991193 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3174 09:30:59.994737 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3175 09:30:59.997980 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3176 09:31:00.001313 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3177 09:31:00.007550 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3178 09:31:00.011898 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3179 09:31:00.014392 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3180 09:31:00.017549 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3181 09:31:00.021209 iDelay=200, Bit 13, Center 127 (56 ~ 199) 144
3182 09:31:00.027772 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3183 09:31:00.030895 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3184 09:31:00.030998 ==
3185 09:31:00.034102 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 09:31:00.037900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 09:31:00.038031 ==
3188 09:31:00.040760 DQS Delay:
3189 09:31:00.040862 DQS0 = 0, DQS1 = 0
3190 09:31:00.040953 DQM Delay:
3191 09:31:00.044105 DQM0 = 115, DQM1 = 113
3192 09:31:00.044224 DQ Delay:
3193 09:31:00.047001 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3194 09:31:00.050575 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3195 09:31:00.053966 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3196 09:31:00.060425 DQ12 =123, DQ13 =127, DQ14 =119, DQ15 =119
3197 09:31:00.060528
3198 09:31:00.060595
3199 09:31:00.060654 ==
3200 09:31:00.063841 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 09:31:00.067305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 09:31:00.067386 ==
3203 09:31:00.067449
3204 09:31:00.067508
3205 09:31:00.070986 TX Vref Scan disable
3206 09:31:00.071112 == TX Byte 0 ==
3207 09:31:00.077590 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3208 09:31:00.080669 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3209 09:31:00.080750 == TX Byte 1 ==
3210 09:31:00.087187 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3211 09:31:00.090714 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3212 09:31:00.090794 ==
3213 09:31:00.093690 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 09:31:00.096995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 09:31:00.097075 ==
3216 09:31:00.110046 TX Vref=22, minBit 2, minWin=25, winSum=409
3217 09:31:00.113512 TX Vref=24, minBit 3, minWin=25, winSum=417
3218 09:31:00.116023 TX Vref=26, minBit 9, minWin=25, winSum=421
3219 09:31:00.120022 TX Vref=28, minBit 8, minWin=26, winSum=427
3220 09:31:00.122930 TX Vref=30, minBit 9, minWin=26, winSum=432
3221 09:31:00.129508 TX Vref=32, minBit 11, minWin=25, winSum=428
3222 09:31:00.133333 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3223 09:31:00.133413
3224 09:31:00.136234 Final TX Range 1 Vref 30
3225 09:31:00.136324
3226 09:31:00.136388 ==
3227 09:31:00.139297 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 09:31:00.142967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 09:31:00.145791 ==
3230 09:31:00.145871
3231 09:31:00.145933
3232 09:31:00.145992 TX Vref Scan disable
3233 09:31:00.149745 == TX Byte 0 ==
3234 09:31:00.153051 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3235 09:31:00.156104 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3236 09:31:00.159761 == TX Byte 1 ==
3237 09:31:00.162755 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3238 09:31:00.169474 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3239 09:31:00.169554
3240 09:31:00.169617 [DATLAT]
3241 09:31:00.169676 Freq=1200, CH1 RK0
3242 09:31:00.169733
3243 09:31:00.172650 DATLAT Default: 0xd
3244 09:31:00.172729 0, 0xFFFF, sum = 0
3245 09:31:00.176364 1, 0xFFFF, sum = 0
3246 09:31:00.179359 2, 0xFFFF, sum = 0
3247 09:31:00.179439 3, 0xFFFF, sum = 0
3248 09:31:00.182942 4, 0xFFFF, sum = 0
3249 09:31:00.183050 5, 0xFFFF, sum = 0
3250 09:31:00.185936 6, 0xFFFF, sum = 0
3251 09:31:00.186045 7, 0xFFFF, sum = 0
3252 09:31:00.189965 8, 0xFFFF, sum = 0
3253 09:31:00.190072 9, 0xFFFF, sum = 0
3254 09:31:00.192412 10, 0xFFFF, sum = 0
3255 09:31:00.192493 11, 0xFFFF, sum = 0
3256 09:31:00.195730 12, 0x0, sum = 1
3257 09:31:00.195810 13, 0x0, sum = 2
3258 09:31:00.199304 14, 0x0, sum = 3
3259 09:31:00.199389 15, 0x0, sum = 4
3260 09:31:00.202383 best_step = 13
3261 09:31:00.202462
3262 09:31:00.202529 ==
3263 09:31:00.205708 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 09:31:00.209557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 09:31:00.209638 ==
3266 09:31:00.209701 RX Vref Scan: 1
3267 09:31:00.212556
3268 09:31:00.212635 Set Vref Range= 32 -> 127
3269 09:31:00.212698
3270 09:31:00.215847 RX Vref 32 -> 127, step: 1
3271 09:31:00.215927
3272 09:31:00.218946 RX Delay -13 -> 252, step: 4
3273 09:31:00.219050
3274 09:31:00.222874 Set Vref, RX VrefLevel [Byte0]: 32
3275 09:31:00.225519 [Byte1]: 32
3276 09:31:00.225598
3277 09:31:00.229507 Set Vref, RX VrefLevel [Byte0]: 33
3278 09:31:00.232261 [Byte1]: 33
3279 09:31:00.235984
3280 09:31:00.236063 Set Vref, RX VrefLevel [Byte0]: 34
3281 09:31:00.239290 [Byte1]: 34
3282 09:31:00.243835
3283 09:31:00.243914 Set Vref, RX VrefLevel [Byte0]: 35
3284 09:31:00.246952 [Byte1]: 35
3285 09:31:00.251971
3286 09:31:00.252050 Set Vref, RX VrefLevel [Byte0]: 36
3287 09:31:00.255216 [Byte1]: 36
3288 09:31:00.259510
3289 09:31:00.259589 Set Vref, RX VrefLevel [Byte0]: 37
3290 09:31:00.263651 [Byte1]: 37
3291 09:31:00.267600
3292 09:31:00.267679 Set Vref, RX VrefLevel [Byte0]: 38
3293 09:31:00.270693 [Byte1]: 38
3294 09:31:00.275505
3295 09:31:00.275590 Set Vref, RX VrefLevel [Byte0]: 39
3296 09:31:00.278726 [Byte1]: 39
3297 09:31:00.283352
3298 09:31:00.283447 Set Vref, RX VrefLevel [Byte0]: 40
3299 09:31:00.286660 [Byte1]: 40
3300 09:31:00.291300
3301 09:31:00.291401 Set Vref, RX VrefLevel [Byte0]: 41
3302 09:31:00.294870 [Byte1]: 41
3303 09:31:00.299059
3304 09:31:00.299183 Set Vref, RX VrefLevel [Byte0]: 42
3305 09:31:00.302959 [Byte1]: 42
3306 09:31:00.307332
3307 09:31:00.307880 Set Vref, RX VrefLevel [Byte0]: 43
3308 09:31:00.310769 [Byte1]: 43
3309 09:31:00.315598
3310 09:31:00.316020 Set Vref, RX VrefLevel [Byte0]: 44
3311 09:31:00.318963 [Byte1]: 44
3312 09:31:00.322941
3313 09:31:00.323392 Set Vref, RX VrefLevel [Byte0]: 45
3314 09:31:00.326800 [Byte1]: 45
3315 09:31:00.330900
3316 09:31:00.331433 Set Vref, RX VrefLevel [Byte0]: 46
3317 09:31:00.334408 [Byte1]: 46
3318 09:31:00.339459
3319 09:31:00.339872 Set Vref, RX VrefLevel [Byte0]: 47
3320 09:31:00.342306 [Byte1]: 47
3321 09:31:00.346594
3322 09:31:00.347003 Set Vref, RX VrefLevel [Byte0]: 48
3323 09:31:00.349725 [Byte1]: 48
3324 09:31:00.354512
3325 09:31:00.355037 Set Vref, RX VrefLevel [Byte0]: 49
3326 09:31:00.357936 [Byte1]: 49
3327 09:31:00.362858
3328 09:31:00.363360 Set Vref, RX VrefLevel [Byte0]: 50
3329 09:31:00.366027 [Byte1]: 50
3330 09:31:00.370412
3331 09:31:00.370888 Set Vref, RX VrefLevel [Byte0]: 51
3332 09:31:00.374179 [Byte1]: 51
3333 09:31:00.378233
3334 09:31:00.378646 Set Vref, RX VrefLevel [Byte0]: 52
3335 09:31:00.382109 [Byte1]: 52
3336 09:31:00.385805
3337 09:31:00.386354 Set Vref, RX VrefLevel [Byte0]: 53
3338 09:31:00.389292 [Byte1]: 53
3339 09:31:00.393910
3340 09:31:00.394312 Set Vref, RX VrefLevel [Byte0]: 54
3341 09:31:00.397143 [Byte1]: 54
3342 09:31:00.401915
3343 09:31:00.402316 Set Vref, RX VrefLevel [Byte0]: 55
3344 09:31:00.405391 [Byte1]: 55
3345 09:31:00.409519
3346 09:31:00.409924 Set Vref, RX VrefLevel [Byte0]: 56
3347 09:31:00.412927 [Byte1]: 56
3348 09:31:00.417628
3349 09:31:00.418069 Set Vref, RX VrefLevel [Byte0]: 57
3350 09:31:00.420500 [Byte1]: 57
3351 09:31:00.425649
3352 09:31:00.426054 Set Vref, RX VrefLevel [Byte0]: 58
3353 09:31:00.428838 [Byte1]: 58
3354 09:31:00.433480
3355 09:31:00.433881 Set Vref, RX VrefLevel [Byte0]: 59
3356 09:31:00.436620 [Byte1]: 59
3357 09:31:00.441139
3358 09:31:00.441657 Set Vref, RX VrefLevel [Byte0]: 60
3359 09:31:00.444885 [Byte1]: 60
3360 09:31:00.449189
3361 09:31:00.449591 Set Vref, RX VrefLevel [Byte0]: 61
3362 09:31:00.453200 [Byte1]: 61
3363 09:31:00.457520
3364 09:31:00.457922 Set Vref, RX VrefLevel [Byte0]: 62
3365 09:31:00.460396 [Byte1]: 62
3366 09:31:00.465226
3367 09:31:00.465625 Set Vref, RX VrefLevel [Byte0]: 63
3368 09:31:00.468013 [Byte1]: 63
3369 09:31:00.472733
3370 09:31:00.473142 Set Vref, RX VrefLevel [Byte0]: 64
3371 09:31:00.476918 [Byte1]: 64
3372 09:31:00.480867
3373 09:31:00.481281 Set Vref, RX VrefLevel [Byte0]: 65
3374 09:31:00.483698 [Byte1]: 65
3375 09:31:00.488606
3376 09:31:00.489046 Set Vref, RX VrefLevel [Byte0]: 66
3377 09:31:00.491763 [Byte1]: 66
3378 09:31:00.496203
3379 09:31:00.496728 Set Vref, RX VrefLevel [Byte0]: 67
3380 09:31:00.499824 [Byte1]: 67
3381 09:31:00.504068
3382 09:31:00.504549 Set Vref, RX VrefLevel [Byte0]: 68
3383 09:31:00.507665 [Byte1]: 68
3384 09:31:00.512070
3385 09:31:00.512536 Final RX Vref Byte 0 = 55 to rank0
3386 09:31:00.515709 Final RX Vref Byte 1 = 53 to rank0
3387 09:31:00.519280 Final RX Vref Byte 0 = 55 to rank1
3388 09:31:00.522076 Final RX Vref Byte 1 = 53 to rank1==
3389 09:31:00.525546 Dram Type= 6, Freq= 0, CH_1, rank 0
3390 09:31:00.532070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3391 09:31:00.532721 ==
3392 09:31:00.533063 DQS Delay:
3393 09:31:00.533467 DQS0 = 0, DQS1 = 0
3394 09:31:00.535180 DQM Delay:
3395 09:31:00.535629 DQM0 = 114, DQM1 = 113
3396 09:31:00.538427 DQ Delay:
3397 09:31:00.541611 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =116
3398 09:31:00.545427 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3399 09:31:00.548990 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3400 09:31:00.552085 DQ12 =124, DQ13 =120, DQ14 =120, DQ15 =122
3401 09:31:00.552493
3402 09:31:00.552856
3403 09:31:00.562006 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3404 09:31:00.562623 CH1 RK0: MR19=303, MR18=F3FF
3405 09:31:00.568383 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3406 09:31:00.568861
3407 09:31:00.571918 ----->DramcWriteLeveling(PI) begin...
3408 09:31:00.572423 ==
3409 09:31:00.575541 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 09:31:00.581823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 09:31:00.582287 ==
3412 09:31:00.584951 Write leveling (Byte 0): 26 => 26
3413 09:31:00.585404 Write leveling (Byte 1): 28 => 28
3414 09:31:00.588692 DramcWriteLeveling(PI) end<-----
3415 09:31:00.589063
3416 09:31:00.589369 ==
3417 09:31:00.592497 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 09:31:00.598420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 09:31:00.599069 ==
3420 09:31:00.601972 [Gating] SW mode calibration
3421 09:31:00.608493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3422 09:31:00.611480 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3423 09:31:00.618101 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3424 09:31:00.621652 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 09:31:00.625166 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 09:31:00.631725 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 09:31:00.635210 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 09:31:00.637901 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 09:31:00.644605 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (0 0) (0 0)
3430 09:31:00.648123 0 15 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
3431 09:31:00.651011 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 09:31:00.658096 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 09:31:00.661320 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 09:31:00.664669 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 09:31:00.671489 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 09:31:00.674711 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3437 09:31:00.678280 1 0 24 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
3438 09:31:00.681913 1 0 28 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
3439 09:31:00.687819 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 09:31:00.690951 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 09:31:00.697479 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 09:31:00.700710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 09:31:00.704017 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 09:31:00.707681 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 09:31:00.714789 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3446 09:31:00.717559 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3447 09:31:00.721114 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 09:31:00.727645 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 09:31:00.730401 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 09:31:00.733595 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 09:31:00.740547 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 09:31:00.743627 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 09:31:00.746941 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 09:31:00.753344 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 09:31:00.757057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 09:31:00.760090 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 09:31:00.766509 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 09:31:00.769704 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 09:31:00.773680 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 09:31:00.779663 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3461 09:31:00.783166 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3462 09:31:00.789713 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3463 09:31:00.789790 Total UI for P1: 0, mck2ui 16
3464 09:31:00.792998 best dqsien dly found for B0: ( 1, 3, 22)
3465 09:31:00.799539 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 09:31:00.802655 Total UI for P1: 0, mck2ui 16
3467 09:31:00.805880 best dqsien dly found for B1: ( 1, 3, 28)
3468 09:31:00.810127 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3469 09:31:00.813030 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3470 09:31:00.813103
3471 09:31:00.816098 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3472 09:31:00.819197 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3473 09:31:00.823166 [Gating] SW calibration Done
3474 09:31:00.823241 ==
3475 09:31:00.825607 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 09:31:00.829681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 09:31:00.832376 ==
3478 09:31:00.832449 RX Vref Scan: 0
3479 09:31:00.832511
3480 09:31:00.835454 RX Vref 0 -> 0, step: 1
3481 09:31:00.835559
3482 09:31:00.838839 RX Delay -40 -> 252, step: 8
3483 09:31:00.841828 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3484 09:31:00.845431 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3485 09:31:00.849224 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3486 09:31:00.852151 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3487 09:31:00.859134 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3488 09:31:00.862376 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3489 09:31:00.865815 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3490 09:31:00.869098 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3491 09:31:00.872399 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3492 09:31:00.878626 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3493 09:31:00.882222 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3494 09:31:00.885103 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3495 09:31:00.888887 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3496 09:31:00.895176 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3497 09:31:00.898826 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3498 09:31:00.902180 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3499 09:31:00.902618 ==
3500 09:31:00.905127 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 09:31:00.908487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 09:31:00.909063 ==
3503 09:31:00.911505 DQS Delay:
3504 09:31:00.911914 DQS0 = 0, DQS1 = 0
3505 09:31:00.914658 DQM Delay:
3506 09:31:00.915064 DQM0 = 115, DQM1 = 111
3507 09:31:00.917974 DQ Delay:
3508 09:31:00.921308 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3509 09:31:00.924671 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3510 09:31:00.927871 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3511 09:31:00.931504 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3512 09:31:00.931914
3513 09:31:00.932235
3514 09:31:00.932554 ==
3515 09:31:00.934339 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 09:31:00.937640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 09:31:00.938054 ==
3518 09:31:00.938379
3519 09:31:00.938710
3520 09:31:00.940846 TX Vref Scan disable
3521 09:31:00.944361 == TX Byte 0 ==
3522 09:31:00.948015 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3523 09:31:00.951029 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3524 09:31:00.953648 == TX Byte 1 ==
3525 09:31:00.957066 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3526 09:31:00.960347 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3527 09:31:00.960450 ==
3528 09:31:00.963582 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 09:31:00.970267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 09:31:00.970351 ==
3531 09:31:00.981131 TX Vref=22, minBit 7, minWin=25, winSum=422
3532 09:31:00.984454 TX Vref=24, minBit 3, minWin=25, winSum=423
3533 09:31:00.987288 TX Vref=26, minBit 1, minWin=26, winSum=428
3534 09:31:00.990985 TX Vref=28, minBit 3, minWin=26, winSum=432
3535 09:31:00.993682 TX Vref=30, minBit 1, minWin=26, winSum=431
3536 09:31:01.000656 TX Vref=32, minBit 15, minWin=26, winSum=435
3537 09:31:01.003615 [TxChooseVref] Worse bit 15, Min win 26, Win sum 435, Final Vref 32
3538 09:31:01.003749
3539 09:31:01.006827 Final TX Range 1 Vref 32
3540 09:31:01.006975
3541 09:31:01.007122 ==
3542 09:31:01.010610 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 09:31:01.016868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 09:31:01.017132 ==
3545 09:31:01.017342
3546 09:31:01.017536
3547 09:31:01.017703 TX Vref Scan disable
3548 09:31:01.020671 == TX Byte 0 ==
3549 09:31:01.024196 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 09:31:01.030492 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 09:31:01.030579 == TX Byte 1 ==
3552 09:31:01.033759 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3553 09:31:01.040359 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3554 09:31:01.040439
3555 09:31:01.040502 [DATLAT]
3556 09:31:01.040564 Freq=1200, CH1 RK1
3557 09:31:01.040620
3558 09:31:01.043561 DATLAT Default: 0xd
3559 09:31:01.046650 0, 0xFFFF, sum = 0
3560 09:31:01.046731 1, 0xFFFF, sum = 0
3561 09:31:01.050109 2, 0xFFFF, sum = 0
3562 09:31:01.050190 3, 0xFFFF, sum = 0
3563 09:31:01.053360 4, 0xFFFF, sum = 0
3564 09:31:01.053441 5, 0xFFFF, sum = 0
3565 09:31:01.056912 6, 0xFFFF, sum = 0
3566 09:31:01.056996 7, 0xFFFF, sum = 0
3567 09:31:01.060139 8, 0xFFFF, sum = 0
3568 09:31:01.060220 9, 0xFFFF, sum = 0
3569 09:31:01.063192 10, 0xFFFF, sum = 0
3570 09:31:01.063273 11, 0xFFFF, sum = 0
3571 09:31:01.067047 12, 0x0, sum = 1
3572 09:31:01.067178 13, 0x0, sum = 2
3573 09:31:01.069706 14, 0x0, sum = 3
3574 09:31:01.069787 15, 0x0, sum = 4
3575 09:31:01.073488 best_step = 13
3576 09:31:01.073568
3577 09:31:01.073630 ==
3578 09:31:01.076861 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 09:31:01.080070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 09:31:01.080150 ==
3581 09:31:01.082979 RX Vref Scan: 0
3582 09:31:01.083134
3583 09:31:01.083229 RX Vref 0 -> 0, step: 1
3584 09:31:01.083301
3585 09:31:01.086445 RX Delay -13 -> 252, step: 4
3586 09:31:01.092753 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3587 09:31:01.096664 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3588 09:31:01.099564 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3589 09:31:01.103003 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3590 09:31:01.106237 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3591 09:31:01.113178 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3592 09:31:01.116005 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3593 09:31:01.119831 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3594 09:31:01.122686 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3595 09:31:01.125948 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3596 09:31:01.132284 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3597 09:31:01.135889 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3598 09:31:01.138877 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3599 09:31:01.142544 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3600 09:31:01.149449 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3601 09:31:01.152431 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3602 09:31:01.152504 ==
3603 09:31:01.156000 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 09:31:01.158741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 09:31:01.158821 ==
3606 09:31:01.162335 DQS Delay:
3607 09:31:01.162408 DQS0 = 0, DQS1 = 0
3608 09:31:01.162469 DQM Delay:
3609 09:31:01.165425 DQM0 = 115, DQM1 = 112
3610 09:31:01.165505 DQ Delay:
3611 09:31:01.169455 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3612 09:31:01.171871 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3613 09:31:01.178678 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3614 09:31:01.182268 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3615 09:31:01.182393
3616 09:31:01.182479
3617 09:31:01.188186 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3618 09:31:01.191901 CH1 RK1: MR19=304, MR18=F608
3619 09:31:01.198454 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3620 09:31:01.202212 [RxdqsGatingPostProcess] freq 1200
3621 09:31:01.208076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3622 09:31:01.208156 best DQS0 dly(2T, 0.5T) = (0, 11)
3623 09:31:01.211601 best DQS1 dly(2T, 0.5T) = (0, 11)
3624 09:31:01.214755 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3625 09:31:01.218219 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3626 09:31:01.221470 best DQS0 dly(2T, 0.5T) = (0, 11)
3627 09:31:01.224579 best DQS1 dly(2T, 0.5T) = (0, 11)
3628 09:31:01.228166 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3629 09:31:01.231402 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3630 09:31:01.234436 Pre-setting of DQS Precalculation
3631 09:31:01.241392 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3632 09:31:01.247654 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3633 09:31:01.254225 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3634 09:31:01.254334
3635 09:31:01.254420
3636 09:31:01.257305 [Calibration Summary] 2400 Mbps
3637 09:31:01.257424 CH 0, Rank 0
3638 09:31:01.260732 SW Impedance : PASS
3639 09:31:01.264185 DUTY Scan : NO K
3640 09:31:01.264324 ZQ Calibration : PASS
3641 09:31:01.267664 Jitter Meter : NO K
3642 09:31:01.271024 CBT Training : PASS
3643 09:31:01.271439 Write leveling : PASS
3644 09:31:01.274841 RX DQS gating : PASS
3645 09:31:01.278124 RX DQ/DQS(RDDQC) : PASS
3646 09:31:01.278961 TX DQ/DQS : PASS
3647 09:31:01.281463 RX DATLAT : PASS
3648 09:31:01.284538 RX DQ/DQS(Engine): PASS
3649 09:31:01.284984 TX OE : NO K
3650 09:31:01.287652 All Pass.
3651 09:31:01.288155
3652 09:31:01.288723 CH 0, Rank 1
3653 09:31:01.291155 SW Impedance : PASS
3654 09:31:01.291570 DUTY Scan : NO K
3655 09:31:01.294354 ZQ Calibration : PASS
3656 09:31:01.297522 Jitter Meter : NO K
3657 09:31:01.298029 CBT Training : PASS
3658 09:31:01.300698 Write leveling : PASS
3659 09:31:01.304571 RX DQS gating : PASS
3660 09:31:01.305182 RX DQ/DQS(RDDQC) : PASS
3661 09:31:01.307557 TX DQ/DQS : PASS
3662 09:31:01.308094 RX DATLAT : PASS
3663 09:31:01.311054 RX DQ/DQS(Engine): PASS
3664 09:31:01.313714 TX OE : NO K
3665 09:31:01.314350 All Pass.
3666 09:31:01.314785
3667 09:31:01.317129 CH 1, Rank 0
3668 09:31:01.317719 SW Impedance : PASS
3669 09:31:01.320236 DUTY Scan : NO K
3670 09:31:01.320935 ZQ Calibration : PASS
3671 09:31:01.323655 Jitter Meter : NO K
3672 09:31:01.327134 CBT Training : PASS
3673 09:31:01.327569 Write leveling : PASS
3674 09:31:01.329934 RX DQS gating : PASS
3675 09:31:01.333817 RX DQ/DQS(RDDQC) : PASS
3676 09:31:01.334227 TX DQ/DQS : PASS
3677 09:31:01.337068 RX DATLAT : PASS
3678 09:31:01.340449 RX DQ/DQS(Engine): PASS
3679 09:31:01.340858 TX OE : NO K
3680 09:31:01.343221 All Pass.
3681 09:31:01.343767
3682 09:31:01.344194 CH 1, Rank 1
3683 09:31:01.346477 SW Impedance : PASS
3684 09:31:01.347194 DUTY Scan : NO K
3685 09:31:01.349882 ZQ Calibration : PASS
3686 09:31:01.353428 Jitter Meter : NO K
3687 09:31:01.353856 CBT Training : PASS
3688 09:31:01.356542 Write leveling : PASS
3689 09:31:01.359727 RX DQS gating : PASS
3690 09:31:01.360140 RX DQ/DQS(RDDQC) : PASS
3691 09:31:01.363308 TX DQ/DQS : PASS
3692 09:31:01.366689 RX DATLAT : PASS
3693 09:31:01.367256 RX DQ/DQS(Engine): PASS
3694 09:31:01.369808 TX OE : NO K
3695 09:31:01.370285 All Pass.
3696 09:31:01.370701
3697 09:31:01.373376 DramC Write-DBI off
3698 09:31:01.376464 PER_BANK_REFRESH: Hybrid Mode
3699 09:31:01.376949 TX_TRACKING: ON
3700 09:31:01.385941 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3701 09:31:01.389469 [FAST_K] Save calibration result to emmc
3702 09:31:01.392612 dramc_set_vcore_voltage set vcore to 650000
3703 09:31:01.395903 Read voltage for 600, 5
3704 09:31:01.396312 Vio18 = 0
3705 09:31:01.396648 Vcore = 650000
3706 09:31:01.399557 Vdram = 0
3707 09:31:01.399966 Vddq = 0
3708 09:31:01.400387 Vmddr = 0
3709 09:31:01.405907 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3710 09:31:01.409175 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3711 09:31:01.412991 MEM_TYPE=3, freq_sel=19
3712 09:31:01.415702 sv_algorithm_assistance_LP4_1600
3713 09:31:01.418973 ============ PULL DRAM RESETB DOWN ============
3714 09:31:01.425214 ========== PULL DRAM RESETB DOWN end =========
3715 09:31:01.428953 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3716 09:31:01.432936 ===================================
3717 09:31:01.435485 LPDDR4 DRAM CONFIGURATION
3718 09:31:01.438613 ===================================
3719 09:31:01.439022 EX_ROW_EN[0] = 0x0
3720 09:31:01.442342 EX_ROW_EN[1] = 0x0
3721 09:31:01.442784 LP4Y_EN = 0x0
3722 09:31:01.445394 WORK_FSP = 0x0
3723 09:31:01.445830 WL = 0x2
3724 09:31:01.448743 RL = 0x2
3725 09:31:01.452260 BL = 0x2
3726 09:31:01.452705 RPST = 0x0
3727 09:31:01.455055 RD_PRE = 0x0
3728 09:31:01.455551 WR_PRE = 0x1
3729 09:31:01.458689 WR_PST = 0x0
3730 09:31:01.459122 DBI_WR = 0x0
3731 09:31:01.461622 DBI_RD = 0x0
3732 09:31:01.462345 OTF = 0x1
3733 09:31:01.465036 ===================================
3734 09:31:01.468349 ===================================
3735 09:31:01.471506 ANA top config
3736 09:31:01.474910 ===================================
3737 09:31:01.475391 DLL_ASYNC_EN = 0
3738 09:31:01.478277 ALL_SLAVE_EN = 1
3739 09:31:01.481291 NEW_RANK_MODE = 1
3740 09:31:01.484916 DLL_IDLE_MODE = 1
3741 09:31:01.488115 LP45_APHY_COMB_EN = 1
3742 09:31:01.488616 TX_ODT_DIS = 1
3743 09:31:01.491425 NEW_8X_MODE = 1
3744 09:31:01.494830 ===================================
3745 09:31:01.497725 ===================================
3746 09:31:01.501003 data_rate = 1200
3747 09:31:01.504564 CKR = 1
3748 09:31:01.508069 DQ_P2S_RATIO = 8
3749 09:31:01.511312 ===================================
3750 09:31:01.514099 CA_P2S_RATIO = 8
3751 09:31:01.514562 DQ_CA_OPEN = 0
3752 09:31:01.517878 DQ_SEMI_OPEN = 0
3753 09:31:01.520723 CA_SEMI_OPEN = 0
3754 09:31:01.524578 CA_FULL_RATE = 0
3755 09:31:01.527699 DQ_CKDIV4_EN = 1
3756 09:31:01.530963 CA_CKDIV4_EN = 1
3757 09:31:01.531392 CA_PREDIV_EN = 0
3758 09:31:01.534022 PH8_DLY = 0
3759 09:31:01.537530 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3760 09:31:01.540249 DQ_AAMCK_DIV = 4
3761 09:31:01.543618 CA_AAMCK_DIV = 4
3762 09:31:01.547421 CA_ADMCK_DIV = 4
3763 09:31:01.547817 DQ_TRACK_CA_EN = 0
3764 09:31:01.550295 CA_PICK = 600
3765 09:31:01.553642 CA_MCKIO = 600
3766 09:31:01.557227 MCKIO_SEMI = 0
3767 09:31:01.560582 PLL_FREQ = 2288
3768 09:31:01.563436 DQ_UI_PI_RATIO = 32
3769 09:31:01.566727 CA_UI_PI_RATIO = 0
3770 09:31:01.570023 ===================================
3771 09:31:01.573014 ===================================
3772 09:31:01.573772 memory_type:LPDDR4
3773 09:31:01.576650 GP_NUM : 10
3774 09:31:01.579843 SRAM_EN : 1
3775 09:31:01.580340 MD32_EN : 0
3776 09:31:01.582948 ===================================
3777 09:31:01.586638 [ANA_INIT] >>>>>>>>>>>>>>
3778 09:31:01.590233 <<<<<< [CONFIGURE PHASE]: ANA_TX
3779 09:31:01.593234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3780 09:31:01.596078 ===================================
3781 09:31:01.599555 data_rate = 1200,PCW = 0X5800
3782 09:31:01.603595 ===================================
3783 09:31:01.606258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3784 09:31:01.609477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3785 09:31:01.616322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3786 09:31:01.622559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3787 09:31:01.625887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3788 09:31:01.628691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3789 09:31:01.628766 [ANA_INIT] flow start
3790 09:31:01.632329 [ANA_INIT] PLL >>>>>>>>
3791 09:31:01.635449 [ANA_INIT] PLL <<<<<<<<
3792 09:31:01.635527 [ANA_INIT] MIDPI >>>>>>>>
3793 09:31:01.639023 [ANA_INIT] MIDPI <<<<<<<<
3794 09:31:01.642236 [ANA_INIT] DLL >>>>>>>>
3795 09:31:01.642327 [ANA_INIT] flow end
3796 09:31:01.649219 ============ LP4 DIFF to SE enter ============
3797 09:31:01.652077 ============ LP4 DIFF to SE exit ============
3798 09:31:01.656025 [ANA_INIT] <<<<<<<<<<<<<
3799 09:31:01.658711 [Flow] Enable top DCM control >>>>>
3800 09:31:01.662210 [Flow] Enable top DCM control <<<<<
3801 09:31:01.662450 Enable DLL master slave shuffle
3802 09:31:01.668806 ==============================================================
3803 09:31:01.672306 Gating Mode config
3804 09:31:01.675456 ==============================================================
3805 09:31:01.678474 Config description:
3806 09:31:01.688938 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3807 09:31:01.695672 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3808 09:31:01.698675 SELPH_MODE 0: By rank 1: By Phase
3809 09:31:01.705168 ==============================================================
3810 09:31:01.708196 GAT_TRACK_EN = 1
3811 09:31:01.711720 RX_GATING_MODE = 2
3812 09:31:01.715203 RX_GATING_TRACK_MODE = 2
3813 09:31:01.718431 SELPH_MODE = 1
3814 09:31:01.721745 PICG_EARLY_EN = 1
3815 09:31:01.722153 VALID_LAT_VALUE = 1
3816 09:31:01.728618 ==============================================================
3817 09:31:01.731897 Enter into Gating configuration >>>>
3818 09:31:01.734953 Exit from Gating configuration <<<<
3819 09:31:01.737837 Enter into DVFS_PRE_config >>>>>
3820 09:31:01.748493 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3821 09:31:01.751426 Exit from DVFS_PRE_config <<<<<
3822 09:31:01.754385 Enter into PICG configuration >>>>
3823 09:31:01.757897 Exit from PICG configuration <<<<
3824 09:31:01.761376 [RX_INPUT] configuration >>>>>
3825 09:31:01.763937 [RX_INPUT] configuration <<<<<
3826 09:31:01.770910 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3827 09:31:01.774636 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3828 09:31:01.780416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3829 09:31:01.787279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3830 09:31:01.793944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3831 09:31:01.800600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3832 09:31:01.803799 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3833 09:31:01.807020 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3834 09:31:01.810723 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3835 09:31:01.817075 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3836 09:31:01.820113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3837 09:31:01.823926 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3838 09:31:01.826818 ===================================
3839 09:31:01.830332 LPDDR4 DRAM CONFIGURATION
3840 09:31:01.833263 ===================================
3841 09:31:01.836623 EX_ROW_EN[0] = 0x0
3842 09:31:01.836694 EX_ROW_EN[1] = 0x0
3843 09:31:01.839810 LP4Y_EN = 0x0
3844 09:31:01.839888 WORK_FSP = 0x0
3845 09:31:01.842936 WL = 0x2
3846 09:31:01.843017 RL = 0x2
3847 09:31:01.846639 BL = 0x2
3848 09:31:01.846718 RPST = 0x0
3849 09:31:01.849539 RD_PRE = 0x0
3850 09:31:01.849611 WR_PRE = 0x1
3851 09:31:01.853099 WR_PST = 0x0
3852 09:31:01.853173 DBI_WR = 0x0
3853 09:31:01.856236 DBI_RD = 0x0
3854 09:31:01.856306 OTF = 0x1
3855 09:31:01.859412 ===================================
3856 09:31:01.866496 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3857 09:31:01.869276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3858 09:31:01.872958 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 09:31:01.876323 ===================================
3860 09:31:01.879331 LPDDR4 DRAM CONFIGURATION
3861 09:31:01.883013 ===================================
3862 09:31:01.886231 EX_ROW_EN[0] = 0x10
3863 09:31:01.886302 EX_ROW_EN[1] = 0x0
3864 09:31:01.889160 LP4Y_EN = 0x0
3865 09:31:01.889228 WORK_FSP = 0x0
3866 09:31:01.892632 WL = 0x2
3867 09:31:01.892714 RL = 0x2
3868 09:31:01.895841 BL = 0x2
3869 09:31:01.895930 RPST = 0x0
3870 09:31:01.899349 RD_PRE = 0x0
3871 09:31:01.899431 WR_PRE = 0x1
3872 09:31:01.901992 WR_PST = 0x0
3873 09:31:01.905465 DBI_WR = 0x0
3874 09:31:01.905540 DBI_RD = 0x0
3875 09:31:01.908937 OTF = 0x1
3876 09:31:01.912136 ===================================
3877 09:31:01.915182 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3878 09:31:01.920518 nWR fixed to 30
3879 09:31:01.923976 [ModeRegInit_LP4] CH0 RK0
3880 09:31:01.924055 [ModeRegInit_LP4] CH0 RK1
3881 09:31:01.927290 [ModeRegInit_LP4] CH1 RK0
3882 09:31:01.930869 [ModeRegInit_LP4] CH1 RK1
3883 09:31:01.930943 match AC timing 17
3884 09:31:01.937381 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3885 09:31:01.940727 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3886 09:31:01.943754 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3887 09:31:01.950252 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3888 09:31:01.953513 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3889 09:31:01.953595 ==
3890 09:31:01.957170 Dram Type= 6, Freq= 0, CH_0, rank 0
3891 09:31:01.960575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3892 09:31:01.963379 ==
3893 09:31:01.967282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3894 09:31:01.973807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3895 09:31:01.976948 [CA 0] Center 36 (6~67) winsize 62
3896 09:31:01.979927 [CA 1] Center 36 (6~67) winsize 62
3897 09:31:01.983225 [CA 2] Center 34 (4~65) winsize 62
3898 09:31:01.986810 [CA 3] Center 34 (4~65) winsize 62
3899 09:31:01.989900 [CA 4] Center 33 (3~64) winsize 62
3900 09:31:01.993049 [CA 5] Center 33 (3~64) winsize 62
3901 09:31:01.993512
3902 09:31:01.996505 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3903 09:31:01.996924
3904 09:31:01.999797 [CATrainingPosCal] consider 1 rank data
3905 09:31:02.003225 u2DelayCellTimex100 = 270/100 ps
3906 09:31:02.006870 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3907 09:31:02.010544 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3908 09:31:02.016416 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3909 09:31:02.019437 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3910 09:31:02.022848 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3911 09:31:02.026493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3912 09:31:02.026906
3913 09:31:02.029255 CA PerBit enable=1, Macro0, CA PI delay=33
3914 09:31:02.029669
3915 09:31:02.032812 [CBTSetCACLKResult] CA Dly = 33
3916 09:31:02.033224 CS Dly: 5 (0~36)
3917 09:31:02.035911 ==
3918 09:31:02.039444 Dram Type= 6, Freq= 0, CH_0, rank 1
3919 09:31:02.042733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 09:31:02.043192 ==
3921 09:31:02.048690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 09:31:02.051886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3923 09:31:02.055886 [CA 0] Center 36 (6~67) winsize 62
3924 09:31:02.059999 [CA 1] Center 36 (6~67) winsize 62
3925 09:31:02.062958 [CA 2] Center 34 (4~65) winsize 62
3926 09:31:02.066051 [CA 3] Center 34 (4~65) winsize 62
3927 09:31:02.069044 [CA 4] Center 34 (3~65) winsize 63
3928 09:31:02.072807 [CA 5] Center 33 (3~64) winsize 62
3929 09:31:02.072887
3930 09:31:02.076138 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3931 09:31:02.076219
3932 09:31:02.079140 [CATrainingPosCal] consider 2 rank data
3933 09:31:02.083025 u2DelayCellTimex100 = 270/100 ps
3934 09:31:02.085850 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 09:31:02.092530 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 09:31:02.095966 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 09:31:02.099238 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 09:31:02.102324 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 09:31:02.105937 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 09:31:02.106017
3941 09:31:02.109064 CA PerBit enable=1, Macro0, CA PI delay=33
3942 09:31:02.109151
3943 09:31:02.112240 [CBTSetCACLKResult] CA Dly = 33
3944 09:31:02.115877 CS Dly: 5 (0~37)
3945 09:31:02.115970
3946 09:31:02.119667 ----->DramcWriteLeveling(PI) begin...
3947 09:31:02.119846 ==
3948 09:31:02.122669 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 09:31:02.125664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 09:31:02.125819 ==
3951 09:31:02.128981 Write leveling (Byte 0): 34 => 34
3952 09:31:02.132138 Write leveling (Byte 1): 28 => 28
3953 09:31:02.135365 DramcWriteLeveling(PI) end<-----
3954 09:31:02.135498
3955 09:31:02.135603 ==
3956 09:31:02.138481 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 09:31:02.142386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 09:31:02.142556 ==
3959 09:31:02.145414 [Gating] SW mode calibration
3960 09:31:02.151832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3961 09:31:02.158610 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3962 09:31:02.161827 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 09:31:02.165141 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 09:31:02.171880 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 09:31:02.175169 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3966 09:31:02.178528 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
3967 09:31:02.184861 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 09:31:02.188666 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 09:31:02.191561 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 09:31:02.198574 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 09:31:02.201812 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 09:31:02.204760 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 09:31:02.211733 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3974 09:31:02.214769 0 10 16 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
3975 09:31:02.218050 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 09:31:02.224549 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 09:31:02.227852 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 09:31:02.230954 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 09:31:02.237254 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 09:31:02.240663 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 09:31:02.244633 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 09:31:02.251184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3983 09:31:02.254186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 09:31:02.257580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 09:31:02.264427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 09:31:02.267227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 09:31:02.274053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 09:31:02.276858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 09:31:02.280688 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 09:31:02.286704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 09:31:02.290372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 09:31:02.293841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 09:31:02.300352 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 09:31:02.303213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 09:31:02.306442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 09:31:02.313270 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 09:31:02.316559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3998 09:31:02.319744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 09:31:02.323038 Total UI for P1: 0, mck2ui 16
4000 09:31:02.326264 best dqsien dly found for B0: ( 0, 13, 12)
4001 09:31:02.329421 Total UI for P1: 0, mck2ui 16
4002 09:31:02.332710 best dqsien dly found for B1: ( 0, 13, 14)
4003 09:31:02.336244 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4004 09:31:02.339435 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4005 09:31:02.339852
4006 09:31:02.345942 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4007 09:31:02.349584 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4008 09:31:02.352295 [Gating] SW calibration Done
4009 09:31:02.352707 ==
4010 09:31:02.355581 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 09:31:02.359009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 09:31:02.359457 ==
4013 09:31:02.359785 RX Vref Scan: 0
4014 09:31:02.360095
4015 09:31:02.362274 RX Vref 0 -> 0, step: 1
4016 09:31:02.362682
4017 09:31:02.365420 RX Delay -230 -> 252, step: 16
4018 09:31:02.368808 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4019 09:31:02.375774 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4020 09:31:02.378623 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4021 09:31:02.382097 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4022 09:31:02.385498 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4023 09:31:02.388839 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4024 09:31:02.395065 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4025 09:31:02.399182 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4026 09:31:02.401807 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4027 09:31:02.405354 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4028 09:31:02.411828 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4029 09:31:02.414928 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4030 09:31:02.418475 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4031 09:31:02.421766 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4032 09:31:02.428027 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4033 09:31:02.431878 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4034 09:31:02.432308 ==
4035 09:31:02.434692 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 09:31:02.438436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 09:31:02.438850 ==
4038 09:31:02.442085 DQS Delay:
4039 09:31:02.442494 DQS0 = 0, DQS1 = 0
4040 09:31:02.444517 DQM Delay:
4041 09:31:02.444954 DQM0 = 45, DQM1 = 35
4042 09:31:02.445284 DQ Delay:
4043 09:31:02.447868 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4044 09:31:02.450990 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4045 09:31:02.454345 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4046 09:31:02.457548 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4047 09:31:02.457955
4048 09:31:02.458279
4049 09:31:02.461360 ==
4050 09:31:02.461786 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 09:31:02.467356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 09:31:02.467756 ==
4053 09:31:02.468079
4054 09:31:02.468380
4055 09:31:02.470879 TX Vref Scan disable
4056 09:31:02.471336 == TX Byte 0 ==
4057 09:31:02.477621 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4058 09:31:02.480767 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4059 09:31:02.481195 == TX Byte 1 ==
4060 09:31:02.487608 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4061 09:31:02.490361 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4062 09:31:02.490800 ==
4063 09:31:02.494330 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 09:31:02.497051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 09:31:02.497464 ==
4066 09:31:02.497792
4067 09:31:02.498095
4068 09:31:02.500487 TX Vref Scan disable
4069 09:31:02.503953 == TX Byte 0 ==
4070 09:31:02.506840 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4071 09:31:02.513815 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4072 09:31:02.514230 == TX Byte 1 ==
4073 09:31:02.516857 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4074 09:31:02.523195 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4075 09:31:02.523609
4076 09:31:02.523933 [DATLAT]
4077 09:31:02.524234 Freq=600, CH0 RK0
4078 09:31:02.524531
4079 09:31:02.527172 DATLAT Default: 0x9
4080 09:31:02.527586 0, 0xFFFF, sum = 0
4081 09:31:02.529978 1, 0xFFFF, sum = 0
4082 09:31:02.533832 2, 0xFFFF, sum = 0
4083 09:31:02.534243 3, 0xFFFF, sum = 0
4084 09:31:02.536835 4, 0xFFFF, sum = 0
4085 09:31:02.537274 5, 0xFFFF, sum = 0
4086 09:31:02.540327 6, 0xFFFF, sum = 0
4087 09:31:02.540744 7, 0xFFFF, sum = 0
4088 09:31:02.543183 8, 0x0, sum = 1
4089 09:31:02.543599 9, 0x0, sum = 2
4090 09:31:02.546473 10, 0x0, sum = 3
4091 09:31:02.546885 11, 0x0, sum = 4
4092 09:31:02.547277 best_step = 9
4093 09:31:02.547592
4094 09:31:02.550037 ==
4095 09:31:02.553090 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 09:31:02.556449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 09:31:02.556912 ==
4098 09:31:02.557257 RX Vref Scan: 1
4099 09:31:02.557655
4100 09:31:02.559593 RX Vref 0 -> 0, step: 1
4101 09:31:02.560002
4102 09:31:02.562507 RX Delay -179 -> 252, step: 8
4103 09:31:02.563004
4104 09:31:02.565859 Set Vref, RX VrefLevel [Byte0]: 55
4105 09:31:02.569374 [Byte1]: 51
4106 09:31:02.569831
4107 09:31:02.572341 Final RX Vref Byte 0 = 55 to rank0
4108 09:31:02.575777 Final RX Vref Byte 1 = 51 to rank0
4109 09:31:02.578998 Final RX Vref Byte 0 = 55 to rank1
4110 09:31:02.582267 Final RX Vref Byte 1 = 51 to rank1==
4111 09:31:02.585860 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 09:31:02.592143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 09:31:02.592567 ==
4114 09:31:02.592995 DQS Delay:
4115 09:31:02.593402 DQS0 = 0, DQS1 = 0
4116 09:31:02.595548 DQM Delay:
4117 09:31:02.595973 DQM0 = 44, DQM1 = 36
4118 09:31:02.599040 DQ Delay:
4119 09:31:02.602053 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4120 09:31:02.605825 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4121 09:31:02.608607 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4122 09:31:02.612020 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4123 09:31:02.612500
4124 09:31:02.613006
4125 09:31:02.618246 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
4126 09:31:02.621941 CH0 RK0: MR19=808, MR18=3F38
4127 09:31:02.628386 CH0_RK0: MR19=0x808, MR18=0x3F38, DQSOSC=397, MR23=63, INC=166, DEC=110
4128 09:31:02.628965
4129 09:31:02.631591 ----->DramcWriteLeveling(PI) begin...
4130 09:31:02.632202 ==
4131 09:31:02.634765 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 09:31:02.638398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 09:31:02.638824 ==
4134 09:31:02.641621 Write leveling (Byte 0): 33 => 33
4135 09:31:02.644849 Write leveling (Byte 1): 30 => 30
4136 09:31:02.647869 DramcWriteLeveling(PI) end<-----
4137 09:31:02.648278
4138 09:31:02.648601 ==
4139 09:31:02.651541 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 09:31:02.657951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 09:31:02.658379 ==
4142 09:31:02.658812 [Gating] SW mode calibration
4143 09:31:02.667899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4144 09:31:02.671057 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4145 09:31:02.674407 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4146 09:31:02.681159 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 09:31:02.684066 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 09:31:02.687416 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
4149 09:31:02.694278 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
4150 09:31:02.697468 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 09:31:02.700882 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 09:31:02.707668 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 09:31:02.710708 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 09:31:02.713855 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 09:31:02.720513 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 09:31:02.723796 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4157 09:31:02.727058 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4158 09:31:02.733583 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 09:31:02.737337 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 09:31:02.743168 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 09:31:02.747265 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 09:31:02.750074 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 09:31:02.756726 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 09:31:02.760315 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4165 09:31:02.763124 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 09:31:02.769916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 09:31:02.773243 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 09:31:02.775916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 09:31:02.782925 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 09:31:02.785752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 09:31:02.789425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 09:31:02.796585 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 09:31:02.799331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 09:31:02.802417 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 09:31:02.809318 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 09:31:02.812059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 09:31:02.815971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 09:31:02.822518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 09:31:02.825540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4180 09:31:02.828696 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4181 09:31:02.835160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 09:31:02.835577 Total UI for P1: 0, mck2ui 16
4183 09:31:02.842635 best dqsien dly found for B0: ( 0, 13, 10)
4184 09:31:02.843177 Total UI for P1: 0, mck2ui 16
4185 09:31:02.848377 best dqsien dly found for B1: ( 0, 13, 14)
4186 09:31:02.851644 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4187 09:31:02.855470 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4188 09:31:02.855967
4189 09:31:02.858485 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4190 09:31:02.861755 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4191 09:31:02.865401 [Gating] SW calibration Done
4192 09:31:02.865885 ==
4193 09:31:02.868362 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 09:31:02.871462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 09:31:02.872063 ==
4196 09:31:02.874518 RX Vref Scan: 0
4197 09:31:02.875053
4198 09:31:02.875580 RX Vref 0 -> 0, step: 1
4199 09:31:02.877987
4200 09:31:02.878382 RX Delay -230 -> 252, step: 16
4201 09:31:02.884533 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4202 09:31:02.887646 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4203 09:31:02.891218 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4204 09:31:02.894734 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4205 09:31:02.901002 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4206 09:31:02.904226 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4207 09:31:02.907391 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4208 09:31:02.910841 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4209 09:31:02.917211 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4210 09:31:02.920720 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4211 09:31:02.924220 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4212 09:31:02.927369 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4213 09:31:02.933241 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4214 09:31:02.936954 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4215 09:31:02.940118 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4216 09:31:02.943940 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4217 09:31:02.944023 ==
4218 09:31:02.947286 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 09:31:02.952947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 09:31:02.953042 ==
4221 09:31:02.953139 DQS Delay:
4222 09:31:02.956092 DQS0 = 0, DQS1 = 0
4223 09:31:02.956195 DQM Delay:
4224 09:31:02.959427 DQM0 = 44, DQM1 = 36
4225 09:31:02.959558 DQ Delay:
4226 09:31:02.962657 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4227 09:31:02.966498 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4228 09:31:02.969466 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4229 09:31:02.972844 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4230 09:31:02.972962
4231 09:31:02.973062
4232 09:31:02.973157 ==
4233 09:31:02.976471 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 09:31:02.979247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 09:31:02.979395 ==
4236 09:31:02.979512
4237 09:31:02.979621
4238 09:31:02.982880 TX Vref Scan disable
4239 09:31:02.985881 == TX Byte 0 ==
4240 09:31:02.989331 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4241 09:31:02.992670 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4242 09:31:02.996438 == TX Byte 1 ==
4243 09:31:02.999272 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4244 09:31:03.002534 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4245 09:31:03.002910 ==
4246 09:31:03.006179 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 09:31:03.012285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 09:31:03.012700 ==
4249 09:31:03.013030
4250 09:31:03.013402
4251 09:31:03.013701 TX Vref Scan disable
4252 09:31:03.017091 == TX Byte 0 ==
4253 09:31:03.020366 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4254 09:31:03.027224 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4255 09:31:03.027733 == TX Byte 1 ==
4256 09:31:03.031104 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4257 09:31:03.036744 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4258 09:31:03.037154
4259 09:31:03.037480 [DATLAT]
4260 09:31:03.037783 Freq=600, CH0 RK1
4261 09:31:03.038080
4262 09:31:03.040137 DATLAT Default: 0x9
4263 09:31:03.043666 0, 0xFFFF, sum = 0
4264 09:31:03.044257 1, 0xFFFF, sum = 0
4265 09:31:03.047379 2, 0xFFFF, sum = 0
4266 09:31:03.047814 3, 0xFFFF, sum = 0
4267 09:31:03.049918 4, 0xFFFF, sum = 0
4268 09:31:03.050385 5, 0xFFFF, sum = 0
4269 09:31:03.053546 6, 0xFFFF, sum = 0
4270 09:31:03.054033 7, 0xFFFF, sum = 0
4271 09:31:03.056462 8, 0x0, sum = 1
4272 09:31:03.056880 9, 0x0, sum = 2
4273 09:31:03.060692 10, 0x0, sum = 3
4274 09:31:03.061109 11, 0x0, sum = 4
4275 09:31:03.061441 best_step = 9
4276 09:31:03.061746
4277 09:31:03.063267 ==
4278 09:31:03.066439 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 09:31:03.070140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 09:31:03.070600 ==
4281 09:31:03.070937 RX Vref Scan: 0
4282 09:31:03.071299
4283 09:31:03.073348 RX Vref 0 -> 0, step: 1
4284 09:31:03.073785
4285 09:31:03.076284 RX Delay -179 -> 252, step: 8
4286 09:31:03.083611 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4287 09:31:03.086541 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4288 09:31:03.089741 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4289 09:31:03.092644 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4290 09:31:03.099330 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4291 09:31:03.102453 iDelay=205, Bit 5, Center 36 (-107 ~ 180) 288
4292 09:31:03.106007 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4293 09:31:03.109125 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4294 09:31:03.112771 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4295 09:31:03.119559 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4296 09:31:03.122360 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4297 09:31:03.125214 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4298 09:31:03.128833 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4299 09:31:03.135249 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4300 09:31:03.138811 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4301 09:31:03.141807 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4302 09:31:03.142246 ==
4303 09:31:03.144917 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 09:31:03.151900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 09:31:03.152362 ==
4306 09:31:03.152693 DQS Delay:
4307 09:31:03.152994 DQS0 = 0, DQS1 = 0
4308 09:31:03.154866 DQM Delay:
4309 09:31:03.155304 DQM0 = 44, DQM1 = 37
4310 09:31:03.158048 DQ Delay:
4311 09:31:03.161356 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4312 09:31:03.164798 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =52
4313 09:31:03.168461 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4314 09:31:03.171629 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4315 09:31:03.172053
4316 09:31:03.172376
4317 09:31:03.178026 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4318 09:31:03.181288 CH0 RK1: MR19=808, MR18=3D39
4319 09:31:03.187982 CH0_RK1: MR19=0x808, MR18=0x3D39, DQSOSC=398, MR23=63, INC=165, DEC=110
4320 09:31:03.191112 [RxdqsGatingPostProcess] freq 600
4321 09:31:03.195379 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4322 09:31:03.197765 Pre-setting of DQS Precalculation
4323 09:31:03.204958 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4324 09:31:03.205441 ==
4325 09:31:03.207627 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 09:31:03.210875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 09:31:03.211319 ==
4328 09:31:03.217798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4329 09:31:03.224521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4330 09:31:03.227728 [CA 0] Center 35 (5~66) winsize 62
4331 09:31:03.230639 [CA 1] Center 35 (5~66) winsize 62
4332 09:31:03.234559 [CA 2] Center 34 (4~65) winsize 62
4333 09:31:03.237442 [CA 3] Center 34 (4~64) winsize 61
4334 09:31:03.240556 [CA 4] Center 34 (4~64) winsize 61
4335 09:31:03.244051 [CA 5] Center 33 (3~64) winsize 62
4336 09:31:03.244537
4337 09:31:03.247394 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4338 09:31:03.247799
4339 09:31:03.250674 [CATrainingPosCal] consider 1 rank data
4340 09:31:03.254224 u2DelayCellTimex100 = 270/100 ps
4341 09:31:03.257107 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4342 09:31:03.260370 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4343 09:31:03.263576 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4344 09:31:03.267227 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4345 09:31:03.270677 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4346 09:31:03.273469 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4347 09:31:03.276801
4348 09:31:03.280622 CA PerBit enable=1, Macro0, CA PI delay=33
4349 09:31:03.281029
4350 09:31:03.283564 [CBTSetCACLKResult] CA Dly = 33
4351 09:31:03.283973 CS Dly: 4 (0~35)
4352 09:31:03.284300 ==
4353 09:31:03.286502 Dram Type= 6, Freq= 0, CH_1, rank 1
4354 09:31:03.290028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 09:31:03.293124 ==
4356 09:31:03.296605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 09:31:03.303193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4358 09:31:03.306453 [CA 0] Center 35 (5~66) winsize 62
4359 09:31:03.310021 [CA 1] Center 36 (6~66) winsize 61
4360 09:31:03.313212 [CA 2] Center 34 (4~65) winsize 62
4361 09:31:03.316378 [CA 3] Center 33 (3~64) winsize 62
4362 09:31:03.319636 [CA 4] Center 34 (4~64) winsize 61
4363 09:31:03.322876 [CA 5] Center 33 (3~64) winsize 62
4364 09:31:03.323359
4365 09:31:03.326581 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4366 09:31:03.327028
4367 09:31:03.329610 [CATrainingPosCal] consider 2 rank data
4368 09:31:03.332709 u2DelayCellTimex100 = 270/100 ps
4369 09:31:03.336301 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 09:31:03.339553 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4371 09:31:03.342966 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 09:31:03.349645 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4373 09:31:03.352695 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4374 09:31:03.355747 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 09:31:03.356153
4376 09:31:03.359483 CA PerBit enable=1, Macro0, CA PI delay=33
4377 09:31:03.360008
4378 09:31:03.362290 [CBTSetCACLKResult] CA Dly = 33
4379 09:31:03.362718 CS Dly: 4 (0~36)
4380 09:31:03.363043
4381 09:31:03.365747 ----->DramcWriteLeveling(PI) begin...
4382 09:31:03.369286 ==
4383 09:31:03.372116 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 09:31:03.376060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 09:31:03.376512 ==
4386 09:31:03.378788 Write leveling (Byte 0): 30 => 30
4387 09:31:03.382069 Write leveling (Byte 1): 30 => 30
4388 09:31:03.385499 DramcWriteLeveling(PI) end<-----
4389 09:31:03.385946
4390 09:31:03.386304 ==
4391 09:31:03.388505 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 09:31:03.392226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 09:31:03.392653 ==
4394 09:31:03.395306 [Gating] SW mode calibration
4395 09:31:03.401898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4396 09:31:03.408513 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4397 09:31:03.411729 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 09:31:03.415058 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4399 09:31:03.422291 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 09:31:03.424734 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
4401 09:31:03.428107 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 09:31:03.434689 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 09:31:03.438129 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 09:31:03.441384 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 09:31:03.448568 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 09:31:03.451712 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 09:31:03.454357 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 09:31:03.461429 0 10 12 | B1->B0 | 3030 3838 | 0 0 | (0 0) (1 1)
4409 09:31:03.464263 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4410 09:31:03.467603 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 09:31:03.474153 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 09:31:03.477807 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 09:31:03.481179 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 09:31:03.487615 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 09:31:03.490825 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 09:31:03.493991 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 09:31:03.500772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 09:31:03.503896 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 09:31:03.506919 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 09:31:03.513739 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 09:31:03.516777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 09:31:03.520101 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 09:31:03.527041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 09:31:03.530000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 09:31:03.533257 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 09:31:03.539930 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 09:31:03.543350 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 09:31:03.546796 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 09:31:03.553076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 09:31:03.556140 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 09:31:03.559858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 09:31:03.566403 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4433 09:31:03.569845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 09:31:03.573125 Total UI for P1: 0, mck2ui 16
4435 09:31:03.576504 best dqsien dly found for B0: ( 0, 13, 12)
4436 09:31:03.580136 Total UI for P1: 0, mck2ui 16
4437 09:31:03.583030 best dqsien dly found for B1: ( 0, 13, 14)
4438 09:31:03.586363 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4439 09:31:03.589451 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4440 09:31:03.589857
4441 09:31:03.593119 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4442 09:31:03.596421 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4443 09:31:03.600034 [Gating] SW calibration Done
4444 09:31:03.600441 ==
4445 09:31:03.602611 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 09:31:03.609474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 09:31:03.609966 ==
4448 09:31:03.610296 RX Vref Scan: 0
4449 09:31:03.610605
4450 09:31:03.612738 RX Vref 0 -> 0, step: 1
4451 09:31:03.613234
4452 09:31:03.616394 RX Delay -230 -> 252, step: 16
4453 09:31:03.619901 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4454 09:31:03.622365 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4455 09:31:03.626225 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4456 09:31:03.632166 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4457 09:31:03.635699 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4458 09:31:03.638802 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4459 09:31:03.642528 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4460 09:31:03.649072 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4461 09:31:03.652217 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4462 09:31:03.655953 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4463 09:31:03.658874 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4464 09:31:03.665105 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4465 09:31:03.669221 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4466 09:31:03.671780 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4467 09:31:03.675343 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4468 09:31:03.681810 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4469 09:31:03.682318 ==
4470 09:31:03.686008 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 09:31:03.688474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 09:31:03.688888 ==
4473 09:31:03.689245 DQS Delay:
4474 09:31:03.691669 DQS0 = 0, DQS1 = 0
4475 09:31:03.692080 DQM Delay:
4476 09:31:03.694754 DQM0 = 42, DQM1 = 37
4477 09:31:03.695201 DQ Delay:
4478 09:31:03.698286 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4479 09:31:03.701622 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4480 09:31:03.705101 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4481 09:31:03.708137 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4482 09:31:03.708549
4483 09:31:03.708927
4484 09:31:03.709423 ==
4485 09:31:03.711544 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 09:31:03.715028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 09:31:03.718276 ==
4488 09:31:03.718932
4489 09:31:03.719389
4490 09:31:03.719732 TX Vref Scan disable
4491 09:31:03.721098 == TX Byte 0 ==
4492 09:31:03.724612 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4493 09:31:03.727698 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4494 09:31:03.731451 == TX Byte 1 ==
4495 09:31:03.734407 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4496 09:31:03.741431 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4497 09:31:03.741852 ==
4498 09:31:03.744846 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 09:31:03.747589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 09:31:03.748001 ==
4501 09:31:03.748325
4502 09:31:03.748626
4503 09:31:03.751601 TX Vref Scan disable
4504 09:31:03.753946 == TX Byte 0 ==
4505 09:31:03.757161 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4506 09:31:03.761051 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4507 09:31:03.764138 == TX Byte 1 ==
4508 09:31:03.767482 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 09:31:03.770685 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 09:31:03.771140
4511 09:31:03.771481 [DATLAT]
4512 09:31:03.773822 Freq=600, CH1 RK0
4513 09:31:03.774253
4514 09:31:03.777065 DATLAT Default: 0x9
4515 09:31:03.777796 0, 0xFFFF, sum = 0
4516 09:31:03.780292 1, 0xFFFF, sum = 0
4517 09:31:03.780875 2, 0xFFFF, sum = 0
4518 09:31:03.783558 3, 0xFFFF, sum = 0
4519 09:31:03.784155 4, 0xFFFF, sum = 0
4520 09:31:03.786660 5, 0xFFFF, sum = 0
4521 09:31:03.787292 6, 0xFFFF, sum = 0
4522 09:31:03.790271 7, 0xFFFF, sum = 0
4523 09:31:03.790807 8, 0x0, sum = 1
4524 09:31:03.793010 9, 0x0, sum = 2
4525 09:31:03.793550 10, 0x0, sum = 3
4526 09:31:03.796304 11, 0x0, sum = 4
4527 09:31:03.796831 best_step = 9
4528 09:31:03.797303
4529 09:31:03.797766 ==
4530 09:31:03.799922 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 09:31:03.803481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 09:31:03.806102 ==
4533 09:31:03.806800 RX Vref Scan: 1
4534 09:31:03.807439
4535 09:31:03.809722 RX Vref 0 -> 0, step: 1
4536 09:31:03.810357
4537 09:31:03.812915 RX Delay -179 -> 252, step: 8
4538 09:31:03.813556
4539 09:31:03.816256 Set Vref, RX VrefLevel [Byte0]: 55
4540 09:31:03.819785 [Byte1]: 53
4541 09:31:03.820352
4542 09:31:03.822878 Final RX Vref Byte 0 = 55 to rank0
4543 09:31:03.825950 Final RX Vref Byte 1 = 53 to rank0
4544 09:31:03.829299 Final RX Vref Byte 0 = 55 to rank1
4545 09:31:03.832488 Final RX Vref Byte 1 = 53 to rank1==
4546 09:31:03.836496 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 09:31:03.839457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 09:31:03.839872 ==
4549 09:31:03.842947 DQS Delay:
4550 09:31:03.843409 DQS0 = 0, DQS1 = 0
4551 09:31:03.843745 DQM Delay:
4552 09:31:03.845656 DQM0 = 40, DQM1 = 34
4553 09:31:03.846068 DQ Delay:
4554 09:31:03.849456 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4555 09:31:03.851939 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4556 09:31:03.855836 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4557 09:31:03.858876 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4558 09:31:03.858957
4559 09:31:03.859020
4560 09:31:03.868264 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4561 09:31:03.871659 CH1 RK0: MR19=808, MR18=2B44
4562 09:31:03.878597 CH1_RK0: MR19=0x808, MR18=0x2B44, DQSOSC=396, MR23=63, INC=167, DEC=111
4563 09:31:03.878681
4564 09:31:03.881579 ----->DramcWriteLeveling(PI) begin...
4565 09:31:03.881660 ==
4566 09:31:03.884958 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 09:31:03.888184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 09:31:03.888264 ==
4569 09:31:03.892160 Write leveling (Byte 0): 29 => 29
4570 09:31:03.894747 Write leveling (Byte 1): 30 => 30
4571 09:31:03.898395 DramcWriteLeveling(PI) end<-----
4572 09:31:03.898487
4573 09:31:03.898560 ==
4574 09:31:03.901630 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 09:31:03.905679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 09:31:03.905779 ==
4577 09:31:03.908043 [Gating] SW mode calibration
4578 09:31:03.914544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4579 09:31:03.921143 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4580 09:31:03.924416 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4581 09:31:03.927652 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4582 09:31:03.934225 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4583 09:31:03.938553 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
4584 09:31:03.940994 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4585 09:31:03.947569 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 09:31:03.950908 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 09:31:03.954211 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 09:31:03.961537 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 09:31:03.964068 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 09:31:03.967954 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4591 09:31:03.974126 0 10 12 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (0 0)
4592 09:31:03.977576 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4593 09:31:03.980522 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 09:31:03.987331 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 09:31:03.990245 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 09:31:03.993825 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 09:31:04.000823 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 09:31:04.003730 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4599 09:31:04.007149 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 09:31:04.013225 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 09:31:04.016604 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 09:31:04.020192 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 09:31:04.026914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 09:31:04.030121 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 09:31:04.033303 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 09:31:04.040014 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 09:31:04.042935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 09:31:04.049595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 09:31:04.053740 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 09:31:04.056079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 09:31:04.059521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 09:31:04.066218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 09:31:04.069202 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 09:31:04.073301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 09:31:04.079411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4616 09:31:04.082635 Total UI for P1: 0, mck2ui 16
4617 09:31:04.086253 best dqsien dly found for B0: ( 0, 13, 10)
4618 09:31:04.089057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 09:31:04.092539 Total UI for P1: 0, mck2ui 16
4620 09:31:04.096355 best dqsien dly found for B1: ( 0, 13, 14)
4621 09:31:04.099844 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4622 09:31:04.102147 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4623 09:31:04.102598
4624 09:31:04.106229 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4625 09:31:04.112524 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4626 09:31:04.113024 [Gating] SW calibration Done
4627 09:31:04.116100 ==
4628 09:31:04.116520 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 09:31:04.121953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 09:31:04.122376 ==
4631 09:31:04.122708 RX Vref Scan: 0
4632 09:31:04.123018
4633 09:31:04.125562 RX Vref 0 -> 0, step: 1
4634 09:31:04.125978
4635 09:31:04.128907 RX Delay -230 -> 252, step: 16
4636 09:31:04.132214 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4637 09:31:04.135348 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4638 09:31:04.142437 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4639 09:31:04.145193 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4640 09:31:04.148185 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4641 09:31:04.151851 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4642 09:31:04.158684 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4643 09:31:04.161825 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4644 09:31:04.164468 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4645 09:31:04.168281 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4646 09:31:04.171657 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4647 09:31:04.178056 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4648 09:31:04.181145 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4649 09:31:04.184527 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4650 09:31:04.191305 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4651 09:31:04.194807 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4652 09:31:04.195006 ==
4653 09:31:04.197939 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 09:31:04.201281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 09:31:04.201521 ==
4656 09:31:04.204321 DQS Delay:
4657 09:31:04.204618 DQS0 = 0, DQS1 = 0
4658 09:31:04.204857 DQM Delay:
4659 09:31:04.207425 DQM0 = 42, DQM1 = 38
4660 09:31:04.207724 DQ Delay:
4661 09:31:04.210978 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4662 09:31:04.214382 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4663 09:31:04.218046 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4664 09:31:04.220940 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4665 09:31:04.221356
4666 09:31:04.221688
4667 09:31:04.221993 ==
4668 09:31:04.223938 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 09:31:04.230175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 09:31:04.230597 ==
4671 09:31:04.230929
4672 09:31:04.231408
4673 09:31:04.231896 TX Vref Scan disable
4674 09:31:04.234657 == TX Byte 0 ==
4675 09:31:04.237627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4676 09:31:04.244572 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4677 09:31:04.244993 == TX Byte 1 ==
4678 09:31:04.247960 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4679 09:31:04.254247 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4680 09:31:04.254667 ==
4681 09:31:04.257711 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 09:31:04.260942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 09:31:04.261362 ==
4684 09:31:04.261694
4685 09:31:04.262001
4686 09:31:04.263810 TX Vref Scan disable
4687 09:31:04.267183 == TX Byte 0 ==
4688 09:31:04.270411 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4689 09:31:04.273958 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4690 09:31:04.277404 == TX Byte 1 ==
4691 09:31:04.280423 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4692 09:31:04.286361 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4693 09:31:04.286937
4694 09:31:04.287930 [DATLAT]
4695 09:31:04.288497 Freq=600, CH1 RK1
4696 09:31:04.289008
4697 09:31:04.290350 DATLAT Default: 0x9
4698 09:31:04.290944 0, 0xFFFF, sum = 0
4699 09:31:04.293624 1, 0xFFFF, sum = 0
4700 09:31:04.294220 2, 0xFFFF, sum = 0
4701 09:31:04.296604 3, 0xFFFF, sum = 0
4702 09:31:04.297144 4, 0xFFFF, sum = 0
4703 09:31:04.300397 5, 0xFFFF, sum = 0
4704 09:31:04.300962 6, 0xFFFF, sum = 0
4705 09:31:04.303501 7, 0xFFFF, sum = 0
4706 09:31:04.303956 8, 0x0, sum = 1
4707 09:31:04.306655 9, 0x0, sum = 2
4708 09:31:04.307291 10, 0x0, sum = 3
4709 09:31:04.310243 11, 0x0, sum = 4
4710 09:31:04.310795 best_step = 9
4711 09:31:04.311350
4712 09:31:04.311859 ==
4713 09:31:04.313372 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 09:31:04.316902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 09:31:04.319674 ==
4716 09:31:04.320106 RX Vref Scan: 0
4717 09:31:04.320437
4718 09:31:04.322927 RX Vref 0 -> 0, step: 1
4719 09:31:04.323390
4720 09:31:04.326246 RX Delay -179 -> 252, step: 8
4721 09:31:04.329558 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4722 09:31:04.333005 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4723 09:31:04.339765 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4724 09:31:04.343355 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4725 09:31:04.346374 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4726 09:31:04.349454 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4727 09:31:04.355902 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4728 09:31:04.359382 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4729 09:31:04.362454 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4730 09:31:04.366050 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4731 09:31:04.372334 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4732 09:31:04.375495 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4733 09:31:04.379168 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4734 09:31:04.382259 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4735 09:31:04.388784 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4736 09:31:04.392426 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4737 09:31:04.392841 ==
4738 09:31:04.395809 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 09:31:04.398956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 09:31:04.399455 ==
4741 09:31:04.402045 DQS Delay:
4742 09:31:04.402557 DQS0 = 0, DQS1 = 0
4743 09:31:04.402897 DQM Delay:
4744 09:31:04.405261 DQM0 = 37, DQM1 = 34
4745 09:31:04.405803 DQ Delay:
4746 09:31:04.408341 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4747 09:31:04.411866 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4748 09:31:04.414969 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =24
4749 09:31:04.418312 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4750 09:31:04.418728
4751 09:31:04.419055
4752 09:31:04.428461 [DQSOSCAuto] RK1, (LSB)MR18= 0x3054, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4753 09:31:04.431885 CH1 RK1: MR19=808, MR18=3054
4754 09:31:04.438354 CH1_RK1: MR19=0x808, MR18=0x3054, DQSOSC=393, MR23=63, INC=169, DEC=113
4755 09:31:04.438770 [RxdqsGatingPostProcess] freq 600
4756 09:31:04.444895 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4757 09:31:04.448145 Pre-setting of DQS Precalculation
4758 09:31:04.451321 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4759 09:31:04.461038 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4760 09:31:04.467919 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4761 09:31:04.468428
4762 09:31:04.468790
4763 09:31:04.471104 [Calibration Summary] 1200 Mbps
4764 09:31:04.471529 CH 0, Rank 0
4765 09:31:04.474337 SW Impedance : PASS
4766 09:31:04.474753 DUTY Scan : NO K
4767 09:31:04.477833 ZQ Calibration : PASS
4768 09:31:04.481252 Jitter Meter : NO K
4769 09:31:04.481755 CBT Training : PASS
4770 09:31:04.484683 Write leveling : PASS
4771 09:31:04.487794 RX DQS gating : PASS
4772 09:31:04.488211 RX DQ/DQS(RDDQC) : PASS
4773 09:31:04.491419 TX DQ/DQS : PASS
4774 09:31:04.494482 RX DATLAT : PASS
4775 09:31:04.495069 RX DQ/DQS(Engine): PASS
4776 09:31:04.497265 TX OE : NO K
4777 09:31:04.497646 All Pass.
4778 09:31:04.497962
4779 09:31:04.500704 CH 0, Rank 1
4780 09:31:04.501250 SW Impedance : PASS
4781 09:31:04.504114 DUTY Scan : NO K
4782 09:31:04.507424 ZQ Calibration : PASS
4783 09:31:04.507862 Jitter Meter : NO K
4784 09:31:04.510602 CBT Training : PASS
4785 09:31:04.513687 Write leveling : PASS
4786 09:31:04.514229 RX DQS gating : PASS
4787 09:31:04.517053 RX DQ/DQS(RDDQC) : PASS
4788 09:31:04.520234 TX DQ/DQS : PASS
4789 09:31:04.520778 RX DATLAT : PASS
4790 09:31:04.523588 RX DQ/DQS(Engine): PASS
4791 09:31:04.526829 TX OE : NO K
4792 09:31:04.527370 All Pass.
4793 09:31:04.527707
4794 09:31:04.528015 CH 1, Rank 0
4795 09:31:04.530322 SW Impedance : PASS
4796 09:31:04.534046 DUTY Scan : NO K
4797 09:31:04.534458 ZQ Calibration : PASS
4798 09:31:04.537188 Jitter Meter : NO K
4799 09:31:04.540272 CBT Training : PASS
4800 09:31:04.540687 Write leveling : PASS
4801 09:31:04.544029 RX DQS gating : PASS
4802 09:31:04.546650 RX DQ/DQS(RDDQC) : PASS
4803 09:31:04.547061 TX DQ/DQS : PASS
4804 09:31:04.550301 RX DATLAT : PASS
4805 09:31:04.550712 RX DQ/DQS(Engine): PASS
4806 09:31:04.553288 TX OE : NO K
4807 09:31:04.553702 All Pass.
4808 09:31:04.554028
4809 09:31:04.557316 CH 1, Rank 1
4810 09:31:04.557731 SW Impedance : PASS
4811 09:31:04.560056 DUTY Scan : NO K
4812 09:31:04.563685 ZQ Calibration : PASS
4813 09:31:04.564099 Jitter Meter : NO K
4814 09:31:04.566595 CBT Training : PASS
4815 09:31:04.570294 Write leveling : PASS
4816 09:31:04.570705 RX DQS gating : PASS
4817 09:31:04.573293 RX DQ/DQS(RDDQC) : PASS
4818 09:31:04.576623 TX DQ/DQS : PASS
4819 09:31:04.577059 RX DATLAT : PASS
4820 09:31:04.580209 RX DQ/DQS(Engine): PASS
4821 09:31:04.583111 TX OE : NO K
4822 09:31:04.583561 All Pass.
4823 09:31:04.583917
4824 09:31:04.586396 DramC Write-DBI off
4825 09:31:04.586809 PER_BANK_REFRESH: Hybrid Mode
4826 09:31:04.589957 TX_TRACKING: ON
4827 09:31:04.596790 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4828 09:31:04.602867 [FAST_K] Save calibration result to emmc
4829 09:31:04.606105 dramc_set_vcore_voltage set vcore to 662500
4830 09:31:04.606519 Read voltage for 933, 3
4831 09:31:04.609303 Vio18 = 0
4832 09:31:04.609762 Vcore = 662500
4833 09:31:04.610254 Vdram = 0
4834 09:31:04.613091 Vddq = 0
4835 09:31:04.613506 Vmddr = 0
4836 09:31:04.616714 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4837 09:31:04.623113 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4838 09:31:04.626161 MEM_TYPE=3, freq_sel=17
4839 09:31:04.629413 sv_algorithm_assistance_LP4_1600
4840 09:31:04.633367 ============ PULL DRAM RESETB DOWN ============
4841 09:31:04.635725 ========== PULL DRAM RESETB DOWN end =========
4842 09:31:04.642436 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4843 09:31:04.645978 ===================================
4844 09:31:04.646485 LPDDR4 DRAM CONFIGURATION
4845 09:31:04.648951 ===================================
4846 09:31:04.652361 EX_ROW_EN[0] = 0x0
4847 09:31:04.655878 EX_ROW_EN[1] = 0x0
4848 09:31:04.656408 LP4Y_EN = 0x0
4849 09:31:04.658969 WORK_FSP = 0x0
4850 09:31:04.659569 WL = 0x3
4851 09:31:04.662192 RL = 0x3
4852 09:31:04.662666 BL = 0x2
4853 09:31:04.665298 RPST = 0x0
4854 09:31:04.665809 RD_PRE = 0x0
4855 09:31:04.668601 WR_PRE = 0x1
4856 09:31:04.669058 WR_PST = 0x0
4857 09:31:04.672162 DBI_WR = 0x0
4858 09:31:04.672707 DBI_RD = 0x0
4859 09:31:04.675632 OTF = 0x1
4860 09:31:04.678689 ===================================
4861 09:31:04.682221 ===================================
4862 09:31:04.682773 ANA top config
4863 09:31:04.684935 ===================================
4864 09:31:04.688495 DLL_ASYNC_EN = 0
4865 09:31:04.692257 ALL_SLAVE_EN = 1
4866 09:31:04.695179 NEW_RANK_MODE = 1
4867 09:31:04.695678 DLL_IDLE_MODE = 1
4868 09:31:04.698487 LP45_APHY_COMB_EN = 1
4869 09:31:04.701543 TX_ODT_DIS = 1
4870 09:31:04.704883 NEW_8X_MODE = 1
4871 09:31:04.707811 ===================================
4872 09:31:04.711318 ===================================
4873 09:31:04.715043 data_rate = 1866
4874 09:31:04.717884 CKR = 1
4875 09:31:04.718327 DQ_P2S_RATIO = 8
4876 09:31:04.721204 ===================================
4877 09:31:04.724305 CA_P2S_RATIO = 8
4878 09:31:04.727945 DQ_CA_OPEN = 0
4879 09:31:04.731121 DQ_SEMI_OPEN = 0
4880 09:31:04.734482 CA_SEMI_OPEN = 0
4881 09:31:04.738193 CA_FULL_RATE = 0
4882 09:31:04.738720 DQ_CKDIV4_EN = 1
4883 09:31:04.740767 CA_CKDIV4_EN = 1
4884 09:31:04.744318 CA_PREDIV_EN = 0
4885 09:31:04.747539 PH8_DLY = 0
4886 09:31:04.751270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4887 09:31:04.754075 DQ_AAMCK_DIV = 4
4888 09:31:04.754491 CA_AAMCK_DIV = 4
4889 09:31:04.757416 CA_ADMCK_DIV = 4
4890 09:31:04.760521 DQ_TRACK_CA_EN = 0
4891 09:31:04.763651 CA_PICK = 933
4892 09:31:04.767608 CA_MCKIO = 933
4893 09:31:04.770518 MCKIO_SEMI = 0
4894 09:31:04.773885 PLL_FREQ = 3732
4895 09:31:04.777130 DQ_UI_PI_RATIO = 32
4896 09:31:04.777546 CA_UI_PI_RATIO = 0
4897 09:31:04.780142 ===================================
4898 09:31:04.783472 ===================================
4899 09:31:04.787550 memory_type:LPDDR4
4900 09:31:04.790218 GP_NUM : 10
4901 09:31:04.790761 SRAM_EN : 1
4902 09:31:04.793670 MD32_EN : 0
4903 09:31:04.796471 ===================================
4904 09:31:04.799986 [ANA_INIT] >>>>>>>>>>>>>>
4905 09:31:04.803520 <<<<<< [CONFIGURE PHASE]: ANA_TX
4906 09:31:04.806720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4907 09:31:04.810075 ===================================
4908 09:31:04.810620 data_rate = 1866,PCW = 0X8f00
4909 09:31:04.813047 ===================================
4910 09:31:04.816340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4911 09:31:04.822634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4912 09:31:04.829571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4913 09:31:04.833181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4914 09:31:04.836176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4915 09:31:04.839350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4916 09:31:04.842563 [ANA_INIT] flow start
4917 09:31:04.846011 [ANA_INIT] PLL >>>>>>>>
4918 09:31:04.846431 [ANA_INIT] PLL <<<<<<<<
4919 09:31:04.850009 [ANA_INIT] MIDPI >>>>>>>>
4920 09:31:04.852577 [ANA_INIT] MIDPI <<<<<<<<
4921 09:31:04.852996 [ANA_INIT] DLL >>>>>>>>
4922 09:31:04.855691 [ANA_INIT] flow end
4923 09:31:04.859144 ============ LP4 DIFF to SE enter ============
4924 09:31:04.865837 ============ LP4 DIFF to SE exit ============
4925 09:31:04.866355 [ANA_INIT] <<<<<<<<<<<<<
4926 09:31:04.869734 [Flow] Enable top DCM control >>>>>
4927 09:31:04.872696 [Flow] Enable top DCM control <<<<<
4928 09:31:04.875914 Enable DLL master slave shuffle
4929 09:31:04.882298 ==============================================================
4930 09:31:04.882714 Gating Mode config
4931 09:31:04.888661 ==============================================================
4932 09:31:04.892866 Config description:
4933 09:31:04.901886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4934 09:31:04.908170 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4935 09:31:04.911476 SELPH_MODE 0: By rank 1: By Phase
4936 09:31:04.918457 ==============================================================
4937 09:31:04.921227 GAT_TRACK_EN = 1
4938 09:31:04.925197 RX_GATING_MODE = 2
4939 09:31:04.925277 RX_GATING_TRACK_MODE = 2
4940 09:31:04.928221 SELPH_MODE = 1
4941 09:31:04.931333 PICG_EARLY_EN = 1
4942 09:31:04.934521 VALID_LAT_VALUE = 1
4943 09:31:04.940926 ==============================================================
4944 09:31:04.943932 Enter into Gating configuration >>>>
4945 09:31:04.947249 Exit from Gating configuration <<<<
4946 09:31:04.950809 Enter into DVFS_PRE_config >>>>>
4947 09:31:04.960799 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4948 09:31:04.963801 Exit from DVFS_PRE_config <<<<<
4949 09:31:04.967380 Enter into PICG configuration >>>>
4950 09:31:04.970338 Exit from PICG configuration <<<<
4951 09:31:04.973556 [RX_INPUT] configuration >>>>>
4952 09:31:04.977115 [RX_INPUT] configuration <<<<<
4953 09:31:04.980239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4954 09:31:04.987049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4955 09:31:04.993593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4956 09:31:05.000033 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4957 09:31:05.006429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 09:31:05.013291 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 09:31:05.016226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4960 09:31:05.020065 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4961 09:31:05.023660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4962 09:31:05.029746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4963 09:31:05.032978 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4964 09:31:05.036015 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4965 09:31:05.039580 ===================================
4966 09:31:05.043282 LPDDR4 DRAM CONFIGURATION
4967 09:31:05.046157 ===================================
4968 09:31:05.046249 EX_ROW_EN[0] = 0x0
4969 09:31:05.049646 EX_ROW_EN[1] = 0x0
4970 09:31:05.053476 LP4Y_EN = 0x0
4971 09:31:05.053665 WORK_FSP = 0x0
4972 09:31:05.056247 WL = 0x3
4973 09:31:05.056369 RL = 0x3
4974 09:31:05.060055 BL = 0x2
4975 09:31:05.060252 RPST = 0x0
4976 09:31:05.063017 RD_PRE = 0x0
4977 09:31:05.063216 WR_PRE = 0x1
4978 09:31:05.065905 WR_PST = 0x0
4979 09:31:05.066097 DBI_WR = 0x0
4980 09:31:05.069242 DBI_RD = 0x0
4981 09:31:05.069471 OTF = 0x1
4982 09:31:05.072615 ===================================
4983 09:31:05.077584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4984 09:31:05.082808 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4985 09:31:05.086052 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 09:31:05.089449 ===================================
4987 09:31:05.093621 LPDDR4 DRAM CONFIGURATION
4988 09:31:05.095936 ===================================
4989 09:31:05.096320 EX_ROW_EN[0] = 0x10
4990 09:31:05.099572 EX_ROW_EN[1] = 0x0
4991 09:31:05.103025 LP4Y_EN = 0x0
4992 09:31:05.103477 WORK_FSP = 0x0
4993 09:31:05.106476 WL = 0x3
4994 09:31:05.107007 RL = 0x3
4995 09:31:05.109210 BL = 0x2
4996 09:31:05.109618 RPST = 0x0
4997 09:31:05.112694 RD_PRE = 0x0
4998 09:31:05.113107 WR_PRE = 0x1
4999 09:31:05.115894 WR_PST = 0x0
5000 09:31:05.116308 DBI_WR = 0x0
5001 09:31:05.119575 DBI_RD = 0x0
5002 09:31:05.119991 OTF = 0x1
5003 09:31:05.122433 ===================================
5004 09:31:05.129112 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5005 09:31:05.133428 nWR fixed to 30
5006 09:31:05.136699 [ModeRegInit_LP4] CH0 RK0
5007 09:31:05.137110 [ModeRegInit_LP4] CH0 RK1
5008 09:31:05.140716 [ModeRegInit_LP4] CH1 RK0
5009 09:31:05.143346 [ModeRegInit_LP4] CH1 RK1
5010 09:31:05.143812 match AC timing 9
5011 09:31:05.149611 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5012 09:31:05.153202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5013 09:31:05.156566 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5014 09:31:05.163419 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5015 09:31:05.166416 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5016 09:31:05.166825 ==
5017 09:31:05.169876 Dram Type= 6, Freq= 0, CH_0, rank 0
5018 09:31:05.173547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5019 09:31:05.173956 ==
5020 09:31:05.180339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5021 09:31:05.186421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5022 09:31:05.189595 [CA 0] Center 38 (7~69) winsize 63
5023 09:31:05.193346 [CA 1] Center 37 (7~68) winsize 62
5024 09:31:05.197093 [CA 2] Center 34 (4~65) winsize 62
5025 09:31:05.199982 [CA 3] Center 34 (4~65) winsize 62
5026 09:31:05.202590 [CA 4] Center 33 (3~64) winsize 62
5027 09:31:05.205881 [CA 5] Center 32 (2~63) winsize 62
5028 09:31:05.206297
5029 09:31:05.209161 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5030 09:31:05.209579
5031 09:31:05.212911 [CATrainingPosCal] consider 1 rank data
5032 09:31:05.216640 u2DelayCellTimex100 = 270/100 ps
5033 09:31:05.219159 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5034 09:31:05.222397 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5035 09:31:05.226235 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5036 09:31:05.232497 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5037 09:31:05.236113 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5038 09:31:05.239179 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5039 09:31:05.239608
5040 09:31:05.242047 CA PerBit enable=1, Macro0, CA PI delay=32
5041 09:31:05.242463
5042 09:31:05.245475 [CBTSetCACLKResult] CA Dly = 32
5043 09:31:05.246005 CS Dly: 6 (0~37)
5044 09:31:05.246443 ==
5045 09:31:05.248684 Dram Type= 6, Freq= 0, CH_0, rank 1
5046 09:31:05.255414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 09:31:05.255942 ==
5048 09:31:05.258993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 09:31:05.265050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5050 09:31:05.268665 [CA 0] Center 38 (8~68) winsize 61
5051 09:31:05.271603 [CA 1] Center 37 (7~68) winsize 62
5052 09:31:05.275224 [CA 2] Center 35 (5~65) winsize 61
5053 09:31:05.278754 [CA 3] Center 34 (4~65) winsize 62
5054 09:31:05.281778 [CA 4] Center 33 (3~64) winsize 62
5055 09:31:05.284912 [CA 5] Center 32 (2~63) winsize 62
5056 09:31:05.285334
5057 09:31:05.288284 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5058 09:31:05.288703
5059 09:31:05.291406 [CATrainingPosCal] consider 2 rank data
5060 09:31:05.294892 u2DelayCellTimex100 = 270/100 ps
5061 09:31:05.298326 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5062 09:31:05.305091 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5063 09:31:05.308882 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5064 09:31:05.311242 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5065 09:31:05.314582 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5066 09:31:05.317687 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5067 09:31:05.318103
5068 09:31:05.320880 CA PerBit enable=1, Macro0, CA PI delay=32
5069 09:31:05.321310
5070 09:31:05.324300 [CBTSetCACLKResult] CA Dly = 32
5071 09:31:05.327498 CS Dly: 7 (0~39)
5072 09:31:05.327980
5073 09:31:05.331271 ----->DramcWriteLeveling(PI) begin...
5074 09:31:05.331694 ==
5075 09:31:05.334263 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 09:31:05.337502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 09:31:05.337921 ==
5078 09:31:05.341300 Write leveling (Byte 0): 28 => 28
5079 09:31:05.344039 Write leveling (Byte 1): 26 => 26
5080 09:31:05.347618 DramcWriteLeveling(PI) end<-----
5081 09:31:05.348034
5082 09:31:05.348446 ==
5083 09:31:05.350692 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 09:31:05.353848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 09:31:05.354279 ==
5086 09:31:05.357368 [Gating] SW mode calibration
5087 09:31:05.363710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5088 09:31:05.370826 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5089 09:31:05.374020 0 14 0 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
5090 09:31:05.380705 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
5091 09:31:05.383780 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 09:31:05.387365 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 09:31:05.393230 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 09:31:05.396853 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 09:31:05.400147 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 09:31:05.406389 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5097 09:31:05.409562 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5098 09:31:05.412882 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5099 09:31:05.420205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 09:31:05.422804 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 09:31:05.425993 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 09:31:05.432742 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 09:31:05.435747 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5104 09:31:05.439177 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5105 09:31:05.445795 1 0 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
5106 09:31:05.449114 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 09:31:05.453018 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 09:31:05.458617 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 09:31:05.461948 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 09:31:05.465738 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 09:31:05.472759 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 09:31:05.475487 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5113 09:31:05.478978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5114 09:31:05.484946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 09:31:05.488583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 09:31:05.491709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 09:31:05.498129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 09:31:05.501659 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 09:31:05.505466 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 09:31:05.511521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 09:31:05.514663 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 09:31:05.519377 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 09:31:05.524804 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 09:31:05.528388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 09:31:05.531600 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 09:31:05.537592 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 09:31:05.540930 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5128 09:31:05.547970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5129 09:31:05.548389 Total UI for P1: 0, mck2ui 16
5130 09:31:05.550834 best dqsien dly found for B0: ( 1, 2, 24)
5131 09:31:05.557526 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 09:31:05.560774 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 09:31:05.564008 Total UI for P1: 0, mck2ui 16
5134 09:31:05.567572 best dqsien dly found for B1: ( 1, 2, 30)
5135 09:31:05.570532 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5136 09:31:05.573832 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5137 09:31:05.574250
5138 09:31:05.577157 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5139 09:31:05.583891 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5140 09:31:05.584347 [Gating] SW calibration Done
5141 09:31:05.587507 ==
5142 09:31:05.587966 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 09:31:05.593538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 09:31:05.593960 ==
5145 09:31:05.594324 RX Vref Scan: 0
5146 09:31:05.594640
5147 09:31:05.597189 RX Vref 0 -> 0, step: 1
5148 09:31:05.597612
5149 09:31:05.600307 RX Delay -80 -> 252, step: 8
5150 09:31:05.603587 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5151 09:31:05.606622 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5152 09:31:05.610121 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5153 09:31:05.616571 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5154 09:31:05.619803 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5155 09:31:05.623442 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5156 09:31:05.626734 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5157 09:31:05.630182 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5158 09:31:05.636084 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5159 09:31:05.639387 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5160 09:31:05.642730 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5161 09:31:05.645793 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5162 09:31:05.649482 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5163 09:31:05.655740 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5164 09:31:05.658733 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5165 09:31:05.662900 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5166 09:31:05.662981 ==
5167 09:31:05.665585 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 09:31:05.669616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 09:31:05.669710 ==
5170 09:31:05.672278 DQS Delay:
5171 09:31:05.672371 DQS0 = 0, DQS1 = 0
5172 09:31:05.672444 DQM Delay:
5173 09:31:05.675652 DQM0 = 102, DQM1 = 87
5174 09:31:05.675752 DQ Delay:
5175 09:31:05.679430 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =95
5176 09:31:05.682764 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =111
5177 09:31:05.685756 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5178 09:31:05.688701 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5179 09:31:05.688833
5180 09:31:05.688938
5181 09:31:05.692248 ==
5182 09:31:05.695600 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 09:31:05.699236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 09:31:05.699406 ==
5185 09:31:05.699539
5186 09:31:05.699663
5187 09:31:05.701953 TX Vref Scan disable
5188 09:31:05.702122 == TX Byte 0 ==
5189 09:31:05.708739 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5190 09:31:05.711663 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5191 09:31:05.711743 == TX Byte 1 ==
5192 09:31:05.718583 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5193 09:31:05.721792 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5194 09:31:05.721872 ==
5195 09:31:05.725438 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 09:31:05.727965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 09:31:05.728045 ==
5198 09:31:05.728108
5199 09:31:05.728168
5200 09:31:05.731595 TX Vref Scan disable
5201 09:31:05.735322 == TX Byte 0 ==
5202 09:31:05.738408 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5203 09:31:05.741342 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5204 09:31:05.745226 == TX Byte 1 ==
5205 09:31:05.747913 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5206 09:31:05.751285 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5207 09:31:05.751366
5208 09:31:05.754685 [DATLAT]
5209 09:31:05.754764 Freq=933, CH0 RK0
5210 09:31:05.754829
5211 09:31:05.757773 DATLAT Default: 0xd
5212 09:31:05.757853 0, 0xFFFF, sum = 0
5213 09:31:05.761128 1, 0xFFFF, sum = 0
5214 09:31:05.761209 2, 0xFFFF, sum = 0
5215 09:31:05.764679 3, 0xFFFF, sum = 0
5216 09:31:05.764767 4, 0xFFFF, sum = 0
5217 09:31:05.768145 5, 0xFFFF, sum = 0
5218 09:31:05.771857 6, 0xFFFF, sum = 0
5219 09:31:05.771951 7, 0xFFFF, sum = 0
5220 09:31:05.774371 8, 0xFFFF, sum = 0
5221 09:31:05.774472 9, 0xFFFF, sum = 0
5222 09:31:05.778342 10, 0x0, sum = 1
5223 09:31:05.778462 11, 0x0, sum = 2
5224 09:31:05.778550 12, 0x0, sum = 3
5225 09:31:05.780871 13, 0x0, sum = 4
5226 09:31:05.780981 best_step = 11
5227 09:31:05.781066
5228 09:31:05.784163 ==
5229 09:31:05.787307 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 09:31:05.790778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 09:31:05.790911 ==
5232 09:31:05.791017 RX Vref Scan: 1
5233 09:31:05.791133
5234 09:31:05.794283 RX Vref 0 -> 0, step: 1
5235 09:31:05.794441
5236 09:31:05.797658 RX Delay -69 -> 252, step: 4
5237 09:31:05.797741
5238 09:31:05.800361 Set Vref, RX VrefLevel [Byte0]: 55
5239 09:31:05.804099 [Byte1]: 51
5240 09:31:05.804179
5241 09:31:05.807169 Final RX Vref Byte 0 = 55 to rank0
5242 09:31:05.810463 Final RX Vref Byte 1 = 51 to rank0
5243 09:31:05.813631 Final RX Vref Byte 0 = 55 to rank1
5244 09:31:05.816927 Final RX Vref Byte 1 = 51 to rank1==
5245 09:31:05.820452 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 09:31:05.827101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 09:31:05.827331 ==
5248 09:31:05.827463 DQS Delay:
5249 09:31:05.827542 DQS0 = 0, DQS1 = 0
5250 09:31:05.830266 DQM Delay:
5251 09:31:05.830346 DQM0 = 102, DQM1 = 90
5252 09:31:05.833540 DQ Delay:
5253 09:31:05.836709 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =98
5254 09:31:05.840602 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5255 09:31:05.843852 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5256 09:31:05.847338 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =98
5257 09:31:05.847419
5258 09:31:05.847483
5259 09:31:05.853232 [DQSOSCAuto] RK0, (LSB)MR18= 0x1510, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5260 09:31:05.856822 CH0 RK0: MR19=505, MR18=1510
5261 09:31:05.863423 CH0_RK0: MR19=0x505, MR18=0x1510, DQSOSC=415, MR23=63, INC=62, DEC=41
5262 09:31:05.863534
5263 09:31:05.866472 ----->DramcWriteLeveling(PI) begin...
5264 09:31:05.866606 ==
5265 09:31:05.870026 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 09:31:05.873561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 09:31:05.874251 ==
5268 09:31:05.876678 Write leveling (Byte 0): 30 => 30
5269 09:31:05.879959 Write leveling (Byte 1): 30 => 30
5270 09:31:05.883274 DramcWriteLeveling(PI) end<-----
5271 09:31:05.883812
5272 09:31:05.884314 ==
5273 09:31:05.886555 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 09:31:05.893050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 09:31:05.893460 ==
5276 09:31:05.893788 [Gating] SW mode calibration
5277 09:31:05.902708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5278 09:31:05.906692 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5279 09:31:05.912779 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5280 09:31:05.916560 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5281 09:31:05.919569 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 09:31:05.925851 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 09:31:05.929422 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 09:31:05.932455 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 09:31:05.939781 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5286 09:31:05.942516 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5287 09:31:05.946080 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5288 09:31:05.952215 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 09:31:05.955279 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 09:31:05.958841 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 09:31:05.965374 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 09:31:05.968623 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 09:31:05.971994 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5294 09:31:05.978890 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (1 1) (0 0)
5295 09:31:05.981920 1 0 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5296 09:31:05.985018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 09:31:05.991310 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 09:31:05.994691 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 09:31:05.998292 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 09:31:06.005200 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 09:31:06.007707 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 09:31:06.011614 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5303 09:31:06.018172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5304 09:31:06.021376 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 09:31:06.024718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 09:31:06.031484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 09:31:06.034582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 09:31:06.037826 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 09:31:06.045373 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 09:31:06.048024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 09:31:06.051489 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 09:31:06.058052 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 09:31:06.060952 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 09:31:06.064495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 09:31:06.071241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 09:31:06.074421 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 09:31:06.077438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5318 09:31:06.083682 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5319 09:31:06.084234 Total UI for P1: 0, mck2ui 16
5320 09:31:06.090413 best dqsien dly found for B0: ( 1, 2, 24)
5321 09:31:06.093571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5322 09:31:06.096710 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 09:31:06.100177 Total UI for P1: 0, mck2ui 16
5324 09:31:06.103439 best dqsien dly found for B1: ( 1, 2, 30)
5325 09:31:06.106483 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5326 09:31:06.109794 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5327 09:31:06.110380
5328 09:31:06.116427 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5329 09:31:06.119777 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5330 09:31:06.123428 [Gating] SW calibration Done
5331 09:31:06.123928 ==
5332 09:31:06.126670 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 09:31:06.129852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 09:31:06.130267 ==
5335 09:31:06.130588 RX Vref Scan: 0
5336 09:31:06.133680
5337 09:31:06.134177 RX Vref 0 -> 0, step: 1
5338 09:31:06.134507
5339 09:31:06.136209 RX Delay -80 -> 252, step: 8
5340 09:31:06.139975 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5341 09:31:06.143159 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5342 09:31:06.149685 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5343 09:31:06.152564 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5344 09:31:06.155935 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5345 09:31:06.159694 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5346 09:31:06.162537 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5347 09:31:06.165997 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5348 09:31:06.172650 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5349 09:31:06.176234 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5350 09:31:06.180056 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5351 09:31:06.182750 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5352 09:31:06.185666 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5353 09:31:06.192002 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5354 09:31:06.195641 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5355 09:31:06.198376 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5356 09:31:06.198969 ==
5357 09:31:06.201790 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 09:31:06.205041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 09:31:06.205583 ==
5360 09:31:06.208474 DQS Delay:
5361 09:31:06.208974 DQS0 = 0, DQS1 = 0
5362 09:31:06.211950 DQM Delay:
5363 09:31:06.212354 DQM0 = 100, DQM1 = 87
5364 09:31:06.214832 DQ Delay:
5365 09:31:06.215288 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5366 09:31:06.219043 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5367 09:31:06.221577 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5368 09:31:06.228041 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5369 09:31:06.228474
5370 09:31:06.228800
5371 09:31:06.229102 ==
5372 09:31:06.232256 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 09:31:06.235133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 09:31:06.235647 ==
5375 09:31:06.235977
5376 09:31:06.236282
5377 09:31:06.238264 TX Vref Scan disable
5378 09:31:06.238769 == TX Byte 0 ==
5379 09:31:06.245011 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5380 09:31:06.248467 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5381 09:31:06.248986 == TX Byte 1 ==
5382 09:31:06.255044 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5383 09:31:06.257912 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5384 09:31:06.258463 ==
5385 09:31:06.261857 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 09:31:06.264672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 09:31:06.265254 ==
5388 09:31:06.265739
5389 09:31:06.268268
5390 09:31:06.268815 TX Vref Scan disable
5391 09:31:06.271564 == TX Byte 0 ==
5392 09:31:06.274330 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5393 09:31:06.278414 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5394 09:31:06.281493 == TX Byte 1 ==
5395 09:31:06.284165 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5396 09:31:06.290961 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5397 09:31:06.291429
5398 09:31:06.291763 [DATLAT]
5399 09:31:06.292073 Freq=933, CH0 RK1
5400 09:31:06.292377
5401 09:31:06.293846 DATLAT Default: 0xb
5402 09:31:06.294336 0, 0xFFFF, sum = 0
5403 09:31:06.297277 1, 0xFFFF, sum = 0
5404 09:31:06.300254 2, 0xFFFF, sum = 0
5405 09:31:06.300677 3, 0xFFFF, sum = 0
5406 09:31:06.303926 4, 0xFFFF, sum = 0
5407 09:31:06.304347 5, 0xFFFF, sum = 0
5408 09:31:06.306889 6, 0xFFFF, sum = 0
5409 09:31:06.307351 7, 0xFFFF, sum = 0
5410 09:31:06.310212 8, 0xFFFF, sum = 0
5411 09:31:06.310656 9, 0xFFFF, sum = 0
5412 09:31:06.313657 10, 0x0, sum = 1
5413 09:31:06.314078 11, 0x0, sum = 2
5414 09:31:06.316845 12, 0x0, sum = 3
5415 09:31:06.317266 13, 0x0, sum = 4
5416 09:31:06.320867 best_step = 11
5417 09:31:06.321280
5418 09:31:06.321606 ==
5419 09:31:06.323961 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 09:31:06.327253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 09:31:06.327764 ==
5422 09:31:06.328151 RX Vref Scan: 0
5423 09:31:06.328497
5424 09:31:06.330812 RX Vref 0 -> 0, step: 1
5425 09:31:06.331371
5426 09:31:06.333621 RX Delay -61 -> 252, step: 4
5427 09:31:06.340187 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5428 09:31:06.343472 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5429 09:31:06.347164 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5430 09:31:06.349855 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5431 09:31:06.353226 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5432 09:31:06.360133 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5433 09:31:06.363480 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5434 09:31:06.366454 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5435 09:31:06.369790 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5436 09:31:06.373007 iDelay=195, Bit 9, Center 78 (-5 ~ 162) 168
5437 09:31:06.379770 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5438 09:31:06.383163 iDelay=195, Bit 11, Center 82 (-1 ~ 166) 168
5439 09:31:06.385651 iDelay=195, Bit 12, Center 96 (15 ~ 178) 164
5440 09:31:06.389395 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5441 09:31:06.392861 iDelay=195, Bit 14, Center 104 (23 ~ 186) 164
5442 09:31:06.399661 iDelay=195, Bit 15, Center 98 (15 ~ 182) 168
5443 09:31:06.400171 ==
5444 09:31:06.402704 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 09:31:06.406271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 09:31:06.406823 ==
5447 09:31:06.407294 DQS Delay:
5448 09:31:06.409269 DQS0 = 0, DQS1 = 0
5449 09:31:06.409728 DQM Delay:
5450 09:31:06.412258 DQM0 = 101, DQM1 = 90
5451 09:31:06.412709 DQ Delay:
5452 09:31:06.415444 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5453 09:31:06.418657 DQ4 =104, DQ5 =92, DQ6 =108, DQ7 =108
5454 09:31:06.422188 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5455 09:31:06.425994 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5456 09:31:06.426407
5457 09:31:06.426734
5458 09:31:06.435981 [DQSOSCAuto] RK1, (LSB)MR18= 0x100e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5459 09:31:06.439109 CH0 RK1: MR19=505, MR18=100E
5460 09:31:06.442079 CH0_RK1: MR19=0x505, MR18=0x100E, DQSOSC=416, MR23=63, INC=62, DEC=41
5461 09:31:06.445039 [RxdqsGatingPostProcess] freq 933
5462 09:31:06.451750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5463 09:31:06.455154 best DQS0 dly(2T, 0.5T) = (0, 10)
5464 09:31:06.458133 best DQS1 dly(2T, 0.5T) = (0, 10)
5465 09:31:06.461558 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5466 09:31:06.465156 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5467 09:31:06.468950 best DQS0 dly(2T, 0.5T) = (0, 10)
5468 09:31:06.471736 best DQS1 dly(2T, 0.5T) = (0, 10)
5469 09:31:06.474588 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5470 09:31:06.478089 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5471 09:31:06.481913 Pre-setting of DQS Precalculation
5472 09:31:06.484702 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5473 09:31:06.485253 ==
5474 09:31:06.487616 Dram Type= 6, Freq= 0, CH_1, rank 0
5475 09:31:06.492018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 09:31:06.492590 ==
5477 09:31:06.498057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5478 09:31:06.504284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5479 09:31:06.509231 [CA 0] Center 36 (6~67) winsize 62
5480 09:31:06.510848 [CA 1] Center 36 (6~67) winsize 62
5481 09:31:06.514547 [CA 2] Center 34 (4~65) winsize 62
5482 09:31:06.517684 [CA 3] Center 33 (3~64) winsize 62
5483 09:31:06.521022 [CA 4] Center 34 (4~65) winsize 62
5484 09:31:06.524100 [CA 5] Center 33 (3~64) winsize 62
5485 09:31:06.524555
5486 09:31:06.527396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5487 09:31:06.527817
5488 09:31:06.530564 [CATrainingPosCal] consider 1 rank data
5489 09:31:06.534135 u2DelayCellTimex100 = 270/100 ps
5490 09:31:06.537698 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5491 09:31:06.541232 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5492 09:31:06.545092 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5493 09:31:06.550537 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5494 09:31:06.553837 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 09:31:06.556759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5496 09:31:06.557293
5497 09:31:06.560581 CA PerBit enable=1, Macro0, CA PI delay=33
5498 09:31:06.561220
5499 09:31:06.563421 [CBTSetCACLKResult] CA Dly = 33
5500 09:31:06.563881 CS Dly: 5 (0~36)
5501 09:31:06.564247 ==
5502 09:31:06.567197 Dram Type= 6, Freq= 0, CH_1, rank 1
5503 09:31:06.573232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 09:31:06.573795 ==
5505 09:31:06.576546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 09:31:06.583458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5507 09:31:06.586819 [CA 0] Center 36 (6~67) winsize 62
5508 09:31:06.591112 [CA 1] Center 36 (6~67) winsize 62
5509 09:31:06.593590 [CA 2] Center 34 (4~65) winsize 62
5510 09:31:06.596989 [CA 3] Center 33 (3~64) winsize 62
5511 09:31:06.600440 [CA 4] Center 33 (3~64) winsize 62
5512 09:31:06.603466 [CA 5] Center 33 (3~64) winsize 62
5513 09:31:06.604030
5514 09:31:06.607377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5515 09:31:06.607945
5516 09:31:06.609902 [CATrainingPosCal] consider 2 rank data
5517 09:31:06.613234 u2DelayCellTimex100 = 270/100 ps
5518 09:31:06.619507 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 09:31:06.623170 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 09:31:06.625819 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5521 09:31:06.629149 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5522 09:31:06.632751 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 09:31:06.635929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 09:31:06.636393
5525 09:31:06.639366 CA PerBit enable=1, Macro0, CA PI delay=33
5526 09:31:06.639948
5527 09:31:06.642673 [CBTSetCACLKResult] CA Dly = 33
5528 09:31:06.645742 CS Dly: 6 (0~38)
5529 09:31:06.646215
5530 09:31:06.649171 ----->DramcWriteLeveling(PI) begin...
5531 09:31:06.649746 ==
5532 09:31:06.652642 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 09:31:06.655722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 09:31:06.656309 ==
5535 09:31:06.659018 Write leveling (Byte 0): 27 => 27
5536 09:31:06.662614 Write leveling (Byte 1): 27 => 27
5537 09:31:06.665925 DramcWriteLeveling(PI) end<-----
5538 09:31:06.666513
5539 09:31:06.666997 ==
5540 09:31:06.669192 Dram Type= 6, Freq= 0, CH_1, rank 0
5541 09:31:06.672388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 09:31:06.672869 ==
5543 09:31:06.675184 [Gating] SW mode calibration
5544 09:31:06.682431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5545 09:31:06.688379 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5546 09:31:06.691832 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 09:31:06.698237 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 09:31:06.701891 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 09:31:06.705469 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 09:31:06.711408 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 09:31:06.714906 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 09:31:06.718365 0 14 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
5553 09:31:06.725079 0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (1 0)
5554 09:31:06.728101 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5555 09:31:06.731167 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 09:31:06.737947 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 09:31:06.741101 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 09:31:06.744530 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 09:31:06.751472 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 09:31:06.754629 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5561 09:31:06.757518 0 15 28 | B1->B0 | 3434 3e3e | 0 0 | (1 1) (0 0)
5562 09:31:06.764620 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 09:31:06.768015 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 09:31:06.771232 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 09:31:06.777950 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 09:31:06.780718 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 09:31:06.783806 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 09:31:06.790480 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 09:31:06.793923 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 09:31:06.797135 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5571 09:31:06.803837 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 09:31:06.806873 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 09:31:06.809951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 09:31:06.817206 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 09:31:06.819973 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 09:31:06.823189 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 09:31:06.829629 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 09:31:06.833307 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 09:31:06.836386 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 09:31:06.842948 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 09:31:06.846146 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 09:31:06.849585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 09:31:06.856093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 09:31:06.859550 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 09:31:06.863219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5586 09:31:06.866149 Total UI for P1: 0, mck2ui 16
5587 09:31:06.869481 best dqsien dly found for B1: ( 1, 2, 26)
5588 09:31:06.876026 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5589 09:31:06.876548 Total UI for P1: 0, mck2ui 16
5590 09:31:06.882718 best dqsien dly found for B0: ( 1, 2, 28)
5591 09:31:06.886233 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5592 09:31:06.888976 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5593 09:31:06.889448
5594 09:31:06.892301 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5595 09:31:06.895766 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5596 09:31:06.899237 [Gating] SW calibration Done
5597 09:31:06.899658 ==
5598 09:31:06.902014 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 09:31:06.905623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 09:31:06.906194 ==
5601 09:31:06.908535 RX Vref Scan: 0
5602 09:31:06.908959
5603 09:31:06.912137 RX Vref 0 -> 0, step: 1
5604 09:31:06.912554
5605 09:31:06.912888 RX Delay -80 -> 252, step: 8
5606 09:31:06.918448 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5607 09:31:06.922562 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5608 09:31:06.925395 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5609 09:31:06.928342 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5610 09:31:06.931891 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5611 09:31:06.935029 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5612 09:31:06.941549 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5613 09:31:06.945007 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5614 09:31:06.947902 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5615 09:31:06.951608 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5616 09:31:06.954641 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5617 09:31:06.961057 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5618 09:31:06.964462 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5619 09:31:06.968295 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5620 09:31:06.971235 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5621 09:31:06.974420 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5622 09:31:06.974869 ==
5623 09:31:06.977735 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 09:31:06.984234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 09:31:06.984656 ==
5626 09:31:06.984993 DQS Delay:
5627 09:31:06.987811 DQS0 = 0, DQS1 = 0
5628 09:31:06.988242 DQM Delay:
5629 09:31:06.990707 DQM0 = 99, DQM1 = 96
5630 09:31:06.991168 DQ Delay:
5631 09:31:06.994148 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5632 09:31:06.997599 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5633 09:31:07.001264 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5634 09:31:07.004634 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5635 09:31:07.005149
5636 09:31:07.005487
5637 09:31:07.005799 ==
5638 09:31:07.007437 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 09:31:07.010468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 09:31:07.014128 ==
5641 09:31:07.014548
5642 09:31:07.014884
5643 09:31:07.015244 TX Vref Scan disable
5644 09:31:07.017355 == TX Byte 0 ==
5645 09:31:07.021276 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5646 09:31:07.023750 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5647 09:31:07.026998 == TX Byte 1 ==
5648 09:31:07.030784 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5649 09:31:07.033569 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5650 09:31:07.037386 ==
5651 09:31:07.040169 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 09:31:07.043510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 09:31:07.044021 ==
5654 09:31:07.044362
5655 09:31:07.044746
5656 09:31:07.046748 TX Vref Scan disable
5657 09:31:07.047224 == TX Byte 0 ==
5658 09:31:07.053062 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 09:31:07.056845 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 09:31:07.057375 == TX Byte 1 ==
5661 09:31:07.063528 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5662 09:31:07.066914 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5663 09:31:07.067474
5664 09:31:07.067809 [DATLAT]
5665 09:31:07.069460 Freq=933, CH1 RK0
5666 09:31:07.069880
5667 09:31:07.070215 DATLAT Default: 0xd
5668 09:31:07.073509 0, 0xFFFF, sum = 0
5669 09:31:07.074030 1, 0xFFFF, sum = 0
5670 09:31:07.076149 2, 0xFFFF, sum = 0
5671 09:31:07.079264 3, 0xFFFF, sum = 0
5672 09:31:07.079692 4, 0xFFFF, sum = 0
5673 09:31:07.083541 5, 0xFFFF, sum = 0
5674 09:31:07.084057 6, 0xFFFF, sum = 0
5675 09:31:07.086561 7, 0xFFFF, sum = 0
5676 09:31:07.087037 8, 0xFFFF, sum = 0
5677 09:31:07.088986 9, 0xFFFF, sum = 0
5678 09:31:07.089626 10, 0x0, sum = 1
5679 09:31:07.092544 11, 0x0, sum = 2
5680 09:31:07.093154 12, 0x0, sum = 3
5681 09:31:07.096254 13, 0x0, sum = 4
5682 09:31:07.096680 best_step = 11
5683 09:31:07.097012
5684 09:31:07.097324 ==
5685 09:31:07.098960 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 09:31:07.102789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 09:31:07.103241 ==
5688 09:31:07.105608 RX Vref Scan: 1
5689 09:31:07.106024
5690 09:31:07.109619 RX Vref 0 -> 0, step: 1
5691 09:31:07.110036
5692 09:31:07.110369 RX Delay -53 -> 252, step: 4
5693 09:31:07.110694
5694 09:31:07.112230 Set Vref, RX VrefLevel [Byte0]: 55
5695 09:31:07.115356 [Byte1]: 53
5696 09:31:07.120417
5697 09:31:07.120835 Final RX Vref Byte 0 = 55 to rank0
5698 09:31:07.123784 Final RX Vref Byte 1 = 53 to rank0
5699 09:31:07.127067 Final RX Vref Byte 0 = 55 to rank1
5700 09:31:07.130557 Final RX Vref Byte 1 = 53 to rank1==
5701 09:31:07.133488 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 09:31:07.140284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 09:31:07.140707 ==
5704 09:31:07.141043 DQS Delay:
5705 09:31:07.143443 DQS0 = 0, DQS1 = 0
5706 09:31:07.143872 DQM Delay:
5707 09:31:07.144206 DQM0 = 98, DQM1 = 94
5708 09:31:07.146772 DQ Delay:
5709 09:31:07.150432 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =96
5710 09:31:07.153753 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5711 09:31:07.156928 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5712 09:31:07.159659 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5713 09:31:07.160078
5714 09:31:07.160411
5715 09:31:07.166314 [DQSOSCAuto] RK0, (LSB)MR18= 0x918, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5716 09:31:07.169695 CH1 RK0: MR19=505, MR18=918
5717 09:31:07.176595 CH1_RK0: MR19=0x505, MR18=0x918, DQSOSC=414, MR23=63, INC=63, DEC=42
5718 09:31:07.177157
5719 09:31:07.179733 ----->DramcWriteLeveling(PI) begin...
5720 09:31:07.180158 ==
5721 09:31:07.183052 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 09:31:07.186094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 09:31:07.189552 ==
5724 09:31:07.190012 Write leveling (Byte 0): 26 => 26
5725 09:31:07.192658 Write leveling (Byte 1): 28 => 28
5726 09:31:07.195815 DramcWriteLeveling(PI) end<-----
5727 09:31:07.196249
5728 09:31:07.196690 ==
5729 09:31:07.199187 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 09:31:07.206056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 09:31:07.206587 ==
5732 09:31:07.208847 [Gating] SW mode calibration
5733 09:31:07.215637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5734 09:31:07.219155 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5735 09:31:07.225800 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5736 09:31:07.228879 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 09:31:07.232014 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 09:31:07.238623 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 09:31:07.242004 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 09:31:07.245457 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 09:31:07.252262 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5742 09:31:07.255363 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5743 09:31:07.258276 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5744 09:31:07.264949 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 09:31:07.268563 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 09:31:07.271904 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 09:31:07.277994 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 09:31:07.281616 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 09:31:07.284966 0 15 24 | B1->B0 | 2727 3131 | 0 1 | (0 0) (0 0)
5750 09:31:07.291782 0 15 28 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
5751 09:31:07.294724 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 09:31:07.298301 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 09:31:07.305425 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 09:31:07.307890 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 09:31:07.311126 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 09:31:07.318019 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 09:31:07.321549 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5758 09:31:07.324865 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5759 09:31:07.331256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 09:31:07.334204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 09:31:07.337425 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 09:31:07.344730 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 09:31:07.347724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 09:31:07.350845 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 09:31:07.357770 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 09:31:07.360793 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 09:31:07.363657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 09:31:07.370107 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 09:31:07.373440 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 09:31:07.376971 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 09:31:07.383554 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 09:31:07.386725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 09:31:07.390334 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5774 09:31:07.397005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5775 09:31:07.399775 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 09:31:07.402994 Total UI for P1: 0, mck2ui 16
5777 09:31:07.406962 best dqsien dly found for B0: ( 1, 2, 26)
5778 09:31:07.409794 Total UI for P1: 0, mck2ui 16
5779 09:31:07.413216 best dqsien dly found for B1: ( 1, 2, 26)
5780 09:31:07.416142 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5781 09:31:07.420662 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5782 09:31:07.421085
5783 09:31:07.422976 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5784 09:31:07.425796 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5785 09:31:07.429299 [Gating] SW calibration Done
5786 09:31:07.429380 ==
5787 09:31:07.432717 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 09:31:07.438837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 09:31:07.438962 ==
5790 09:31:07.439061 RX Vref Scan: 0
5791 09:31:07.439155
5792 09:31:07.442507 RX Vref 0 -> 0, step: 1
5793 09:31:07.442615
5794 09:31:07.445500 RX Delay -80 -> 252, step: 8
5795 09:31:07.449052 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5796 09:31:07.452302 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5797 09:31:07.455949 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5798 09:31:07.458507 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5799 09:31:07.465384 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5800 09:31:07.468481 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5801 09:31:07.471787 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5802 09:31:07.474950 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5803 09:31:07.478263 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5804 09:31:07.481740 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5805 09:31:07.488351 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5806 09:31:07.491871 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5807 09:31:07.494821 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5808 09:31:07.498153 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5809 09:31:07.501154 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5810 09:31:07.507698 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5811 09:31:07.507804 ==
5812 09:31:07.511077 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 09:31:07.514649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 09:31:07.514750 ==
5815 09:31:07.514846 DQS Delay:
5816 09:31:07.517710 DQS0 = 0, DQS1 = 0
5817 09:31:07.517808 DQM Delay:
5818 09:31:07.521603 DQM0 = 97, DQM1 = 94
5819 09:31:07.521704 DQ Delay:
5820 09:31:07.524220 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5821 09:31:07.528074 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5822 09:31:07.530914 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5823 09:31:07.534044 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5824 09:31:07.534145
5825 09:31:07.534248
5826 09:31:07.534324 ==
5827 09:31:07.537578 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 09:31:07.544184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 09:31:07.544264 ==
5830 09:31:07.544340
5831 09:31:07.544400
5832 09:31:07.544463 TX Vref Scan disable
5833 09:31:07.547626 == TX Byte 0 ==
5834 09:31:07.550765 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5835 09:31:07.557551 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5836 09:31:07.557654 == TX Byte 1 ==
5837 09:31:07.560927 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5838 09:31:07.567428 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5839 09:31:07.567509 ==
5840 09:31:07.571260 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 09:31:07.574107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 09:31:07.574222 ==
5843 09:31:07.574324
5844 09:31:07.574415
5845 09:31:07.578000 TX Vref Scan disable
5846 09:31:07.578112 == TX Byte 0 ==
5847 09:31:07.584188 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 09:31:07.587578 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 09:31:07.590700 == TX Byte 1 ==
5850 09:31:07.593607 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5851 09:31:07.597172 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5852 09:31:07.597277
5853 09:31:07.597369 [DATLAT]
5854 09:31:07.600662 Freq=933, CH1 RK1
5855 09:31:07.600764
5856 09:31:07.600853 DATLAT Default: 0xb
5857 09:31:07.603794 0, 0xFFFF, sum = 0
5858 09:31:07.607730 1, 0xFFFF, sum = 0
5859 09:31:07.607833 2, 0xFFFF, sum = 0
5860 09:31:07.610183 3, 0xFFFF, sum = 0
5861 09:31:07.610257 4, 0xFFFF, sum = 0
5862 09:31:07.613584 5, 0xFFFF, sum = 0
5863 09:31:07.613686 6, 0xFFFF, sum = 0
5864 09:31:07.616635 7, 0xFFFF, sum = 0
5865 09:31:07.616726 8, 0xFFFF, sum = 0
5866 09:31:07.620302 9, 0xFFFF, sum = 0
5867 09:31:07.620408 10, 0x0, sum = 1
5868 09:31:07.623849 11, 0x0, sum = 2
5869 09:31:07.623953 12, 0x0, sum = 3
5870 09:31:07.627548 13, 0x0, sum = 4
5871 09:31:07.627629 best_step = 11
5872 09:31:07.627692
5873 09:31:07.627752 ==
5874 09:31:07.630083 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 09:31:07.633357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 09:31:07.633456 ==
5877 09:31:07.636623 RX Vref Scan: 0
5878 09:31:07.636699
5879 09:31:07.639705 RX Vref 0 -> 0, step: 1
5880 09:31:07.639777
5881 09:31:07.639839 RX Delay -53 -> 252, step: 4
5882 09:31:07.647997 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5883 09:31:07.651605 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5884 09:31:07.654288 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5885 09:31:07.658019 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5886 09:31:07.660996 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5887 09:31:07.667375 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5888 09:31:07.670610 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5889 09:31:07.674105 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5890 09:31:07.677300 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5891 09:31:07.680495 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5892 09:31:07.687473 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5893 09:31:07.690625 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5894 09:31:07.694011 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5895 09:31:07.696896 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5896 09:31:07.700425 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5897 09:31:07.707029 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5898 09:31:07.707154 ==
5899 09:31:07.710693 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 09:31:07.713656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 09:31:07.713738 ==
5902 09:31:07.713804 DQS Delay:
5903 09:31:07.717051 DQS0 = 0, DQS1 = 0
5904 09:31:07.717156 DQM Delay:
5905 09:31:07.720081 DQM0 = 97, DQM1 = 92
5906 09:31:07.720167 DQ Delay:
5907 09:31:07.723433 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =92
5908 09:31:07.726753 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =96
5909 09:31:07.730147 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5910 09:31:07.733555 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =102
5911 09:31:07.733643
5912 09:31:07.733712
5913 09:31:07.743314 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5914 09:31:07.743441 CH1 RK1: MR19=505, MR18=A21
5915 09:31:07.749695 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5916 09:31:07.753251 [RxdqsGatingPostProcess] freq 933
5917 09:31:07.759613 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5918 09:31:07.762982 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 09:31:07.766253 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 09:31:07.770029 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 09:31:07.772989 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 09:31:07.775711 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 09:31:07.775784 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 09:31:07.779434 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 09:31:07.782640 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 09:31:07.785612 Pre-setting of DQS Precalculation
5927 09:31:07.792254 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5928 09:31:07.799207 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5929 09:31:07.805841 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5930 09:31:07.805923
5931 09:31:07.805990
5932 09:31:07.809226 [Calibration Summary] 1866 Mbps
5933 09:31:07.812126 CH 0, Rank 0
5934 09:31:07.812241 SW Impedance : PASS
5935 09:31:07.815830 DUTY Scan : NO K
5936 09:31:07.818525 ZQ Calibration : PASS
5937 09:31:07.818626 Jitter Meter : NO K
5938 09:31:07.822224 CBT Training : PASS
5939 09:31:07.825756 Write leveling : PASS
5940 09:31:07.825900 RX DQS gating : PASS
5941 09:31:07.828746 RX DQ/DQS(RDDQC) : PASS
5942 09:31:07.832076 TX DQ/DQS : PASS
5943 09:31:07.832227 RX DATLAT : PASS
5944 09:31:07.835866 RX DQ/DQS(Engine): PASS
5945 09:31:07.836032 TX OE : NO K
5946 09:31:07.838824 All Pass.
5947 09:31:07.839007
5948 09:31:07.839172 CH 0, Rank 1
5949 09:31:07.841665 SW Impedance : PASS
5950 09:31:07.841849 DUTY Scan : NO K
5951 09:31:07.845234 ZQ Calibration : PASS
5952 09:31:07.848671 Jitter Meter : NO K
5953 09:31:07.848864 CBT Training : PASS
5954 09:31:07.853308 Write leveling : PASS
5955 09:31:07.855462 RX DQS gating : PASS
5956 09:31:07.855672 RX DQ/DQS(RDDQC) : PASS
5957 09:31:07.858414 TX DQ/DQS : PASS
5958 09:31:07.861617 RX DATLAT : PASS
5959 09:31:07.861922 RX DQ/DQS(Engine): PASS
5960 09:31:07.865463 TX OE : NO K
5961 09:31:07.865849 All Pass.
5962 09:31:07.866157
5963 09:31:07.868823 CH 1, Rank 0
5964 09:31:07.869243 SW Impedance : PASS
5965 09:31:07.871770 DUTY Scan : NO K
5966 09:31:07.875003 ZQ Calibration : PASS
5967 09:31:07.875108 Jitter Meter : NO K
5968 09:31:07.878491 CBT Training : PASS
5969 09:31:07.881580 Write leveling : PASS
5970 09:31:07.881693 RX DQS gating : PASS
5971 09:31:07.884775 RX DQ/DQS(RDDQC) : PASS
5972 09:31:07.888140 TX DQ/DQS : PASS
5973 09:31:07.888220 RX DATLAT : PASS
5974 09:31:07.891529 RX DQ/DQS(Engine): PASS
5975 09:31:07.894675 TX OE : NO K
5976 09:31:07.894756 All Pass.
5977 09:31:07.894821
5978 09:31:07.894880 CH 1, Rank 1
5979 09:31:07.898271 SW Impedance : PASS
5980 09:31:07.901222 DUTY Scan : NO K
5981 09:31:07.901303 ZQ Calibration : PASS
5982 09:31:07.904197 Jitter Meter : NO K
5983 09:31:07.907661 CBT Training : PASS
5984 09:31:07.907741 Write leveling : PASS
5985 09:31:07.911113 RX DQS gating : PASS
5986 09:31:07.914112 RX DQ/DQS(RDDQC) : PASS
5987 09:31:07.914193 TX DQ/DQS : PASS
5988 09:31:07.917627 RX DATLAT : PASS
5989 09:31:07.917708 RX DQ/DQS(Engine): PASS
5990 09:31:07.921429 TX OE : NO K
5991 09:31:07.921511 All Pass.
5992 09:31:07.921576
5993 09:31:07.924123 DramC Write-DBI off
5994 09:31:07.927731 PER_BANK_REFRESH: Hybrid Mode
5995 09:31:07.927812 TX_TRACKING: ON
5996 09:31:07.937503 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5997 09:31:07.940979 [FAST_K] Save calibration result to emmc
5998 09:31:07.944049 dramc_set_vcore_voltage set vcore to 650000
5999 09:31:07.947417 Read voltage for 400, 6
6000 09:31:07.947498 Vio18 = 0
6001 09:31:07.950258 Vcore = 650000
6002 09:31:07.950339 Vdram = 0
6003 09:31:07.950403 Vddq = 0
6004 09:31:07.950463 Vmddr = 0
6005 09:31:07.957200 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6006 09:31:07.963542 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6007 09:31:07.963629 MEM_TYPE=3, freq_sel=20
6008 09:31:07.966891 sv_algorithm_assistance_LP4_800
6009 09:31:07.970835 ============ PULL DRAM RESETB DOWN ============
6010 09:31:07.976739 ========== PULL DRAM RESETB DOWN end =========
6011 09:31:07.980339 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6012 09:31:07.983267 ===================================
6013 09:31:07.986618 LPDDR4 DRAM CONFIGURATION
6014 09:31:07.989960 ===================================
6015 09:31:07.990083 EX_ROW_EN[0] = 0x0
6016 09:31:07.992946 EX_ROW_EN[1] = 0x0
6017 09:31:07.996693 LP4Y_EN = 0x0
6018 09:31:07.996775 WORK_FSP = 0x0
6019 09:31:07.999679 WL = 0x2
6020 09:31:07.999761 RL = 0x2
6021 09:31:08.002912 BL = 0x2
6022 09:31:08.003019 RPST = 0x0
6023 09:31:08.007037 RD_PRE = 0x0
6024 09:31:08.007160 WR_PRE = 0x1
6025 09:31:08.009722 WR_PST = 0x0
6026 09:31:08.009836 DBI_WR = 0x0
6027 09:31:08.013269 DBI_RD = 0x0
6028 09:31:08.013372 OTF = 0x1
6029 09:31:08.017145 ===================================
6030 09:31:08.020630 ===================================
6031 09:31:08.022956 ANA top config
6032 09:31:08.026250 ===================================
6033 09:31:08.026361 DLL_ASYNC_EN = 0
6034 09:31:08.029523 ALL_SLAVE_EN = 1
6035 09:31:08.032817 NEW_RANK_MODE = 1
6036 09:31:08.036528 DLL_IDLE_MODE = 1
6037 09:31:08.039939 LP45_APHY_COMB_EN = 1
6038 09:31:08.040373 TX_ODT_DIS = 1
6039 09:31:08.043202 NEW_8X_MODE = 1
6040 09:31:08.046790 ===================================
6041 09:31:08.050052 ===================================
6042 09:31:08.052930 data_rate = 800
6043 09:31:08.056739 CKR = 1
6044 09:31:08.059389 DQ_P2S_RATIO = 4
6045 09:31:08.062763 ===================================
6046 09:31:08.066213 CA_P2S_RATIO = 4
6047 09:31:08.066823 DQ_CA_OPEN = 0
6048 09:31:08.069397 DQ_SEMI_OPEN = 1
6049 09:31:08.072363 CA_SEMI_OPEN = 1
6050 09:31:08.076023 CA_FULL_RATE = 0
6051 09:31:08.079189 DQ_CKDIV4_EN = 0
6052 09:31:08.082084 CA_CKDIV4_EN = 1
6053 09:31:08.085467 CA_PREDIV_EN = 0
6054 09:31:08.085573 PH8_DLY = 0
6055 09:31:08.088811 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6056 09:31:08.092277 DQ_AAMCK_DIV = 0
6057 09:31:08.095447 CA_AAMCK_DIV = 0
6058 09:31:08.098443 CA_ADMCK_DIV = 4
6059 09:31:08.102126 DQ_TRACK_CA_EN = 0
6060 09:31:08.102250 CA_PICK = 800
6061 09:31:08.105012 CA_MCKIO = 400
6062 09:31:08.109098 MCKIO_SEMI = 400
6063 09:31:08.111682 PLL_FREQ = 3016
6064 09:31:08.115882 DQ_UI_PI_RATIO = 32
6065 09:31:08.118364 CA_UI_PI_RATIO = 32
6066 09:31:08.122124 ===================================
6067 09:31:08.124983 ===================================
6068 09:31:08.128215 memory_type:LPDDR4
6069 09:31:08.128366 GP_NUM : 10
6070 09:31:08.131561 SRAM_EN : 1
6071 09:31:08.131711 MD32_EN : 0
6072 09:31:08.135151 ===================================
6073 09:31:08.139013 [ANA_INIT] >>>>>>>>>>>>>>
6074 09:31:08.141806 <<<<<< [CONFIGURE PHASE]: ANA_TX
6075 09:31:08.145067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6076 09:31:08.148423 ===================================
6077 09:31:08.151704 data_rate = 800,PCW = 0X7400
6078 09:31:08.155249 ===================================
6079 09:31:08.158310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6080 09:31:08.165073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 09:31:08.174873 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 09:31:08.178031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6083 09:31:08.184518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6084 09:31:08.187587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6085 09:31:08.188137 [ANA_INIT] flow start
6086 09:31:08.191201 [ANA_INIT] PLL >>>>>>>>
6087 09:31:08.194719 [ANA_INIT] PLL <<<<<<<<
6088 09:31:08.195354 [ANA_INIT] MIDPI >>>>>>>>
6089 09:31:08.197974 [ANA_INIT] MIDPI <<<<<<<<
6090 09:31:08.200599 [ANA_INIT] DLL >>>>>>>>
6091 09:31:08.201239 [ANA_INIT] flow end
6092 09:31:08.207368 ============ LP4 DIFF to SE enter ============
6093 09:31:08.210634 ============ LP4 DIFF to SE exit ============
6094 09:31:08.214080 [ANA_INIT] <<<<<<<<<<<<<
6095 09:31:08.217123 [Flow] Enable top DCM control >>>>>
6096 09:31:08.220683 [Flow] Enable top DCM control <<<<<
6097 09:31:08.221125 Enable DLL master slave shuffle
6098 09:31:08.227563 ==============================================================
6099 09:31:08.230257 Gating Mode config
6100 09:31:08.233993 ==============================================================
6101 09:31:08.236999 Config description:
6102 09:31:08.247244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6103 09:31:08.253267 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6104 09:31:08.256780 SELPH_MODE 0: By rank 1: By Phase
6105 09:31:08.262981 ==============================================================
6106 09:31:08.266605 GAT_TRACK_EN = 0
6107 09:31:08.269847 RX_GATING_MODE = 2
6108 09:31:08.272992 RX_GATING_TRACK_MODE = 2
6109 09:31:08.276185 SELPH_MODE = 1
6110 09:31:08.279669 PICG_EARLY_EN = 1
6111 09:31:08.280081 VALID_LAT_VALUE = 1
6112 09:31:08.286457 ==============================================================
6113 09:31:08.289431 Enter into Gating configuration >>>>
6114 09:31:08.294016 Exit from Gating configuration <<<<
6115 09:31:08.296539 Enter into DVFS_PRE_config >>>>>
6116 09:31:08.306442 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6117 09:31:08.309335 Exit from DVFS_PRE_config <<<<<
6118 09:31:08.312886 Enter into PICG configuration >>>>
6119 09:31:08.315682 Exit from PICG configuration <<<<
6120 09:31:08.319172 [RX_INPUT] configuration >>>>>
6121 09:31:08.322915 [RX_INPUT] configuration <<<<<
6122 09:31:08.329213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6123 09:31:08.332141 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6124 09:31:08.338678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 09:31:08.345653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 09:31:08.351790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 09:31:08.358441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 09:31:08.361843 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6129 09:31:08.365646 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6130 09:31:08.368859 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6131 09:31:08.375111 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6132 09:31:08.378489 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6133 09:31:08.381323 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 09:31:08.384971 ===================================
6135 09:31:08.387955 LPDDR4 DRAM CONFIGURATION
6136 09:31:08.391357 ===================================
6137 09:31:08.394912 EX_ROW_EN[0] = 0x0
6138 09:31:08.395452 EX_ROW_EN[1] = 0x0
6139 09:31:08.397893 LP4Y_EN = 0x0
6140 09:31:08.398306 WORK_FSP = 0x0
6141 09:31:08.401663 WL = 0x2
6142 09:31:08.402124 RL = 0x2
6143 09:31:08.404590 BL = 0x2
6144 09:31:08.405047 RPST = 0x0
6145 09:31:08.407791 RD_PRE = 0x0
6146 09:31:08.408247 WR_PRE = 0x1
6147 09:31:08.411002 WR_PST = 0x0
6148 09:31:08.414532 DBI_WR = 0x0
6149 09:31:08.414952 DBI_RD = 0x0
6150 09:31:08.417986 OTF = 0x1
6151 09:31:08.420858 ===================================
6152 09:31:08.424127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6153 09:31:08.427620 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6154 09:31:08.431454 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 09:31:08.434806 ===================================
6156 09:31:08.437546 LPDDR4 DRAM CONFIGURATION
6157 09:31:08.440863 ===================================
6158 09:31:08.444139 EX_ROW_EN[0] = 0x10
6159 09:31:08.444552 EX_ROW_EN[1] = 0x0
6160 09:31:08.447541 LP4Y_EN = 0x0
6161 09:31:08.447954 WORK_FSP = 0x0
6162 09:31:08.450998 WL = 0x2
6163 09:31:08.451452 RL = 0x2
6164 09:31:08.454511 BL = 0x2
6165 09:31:08.454921 RPST = 0x0
6166 09:31:08.457325 RD_PRE = 0x0
6167 09:31:08.460583 WR_PRE = 0x1
6168 09:31:08.461025 WR_PST = 0x0
6169 09:31:08.463894 DBI_WR = 0x0
6170 09:31:08.464311 DBI_RD = 0x0
6171 09:31:08.467518 OTF = 0x1
6172 09:31:08.470404 ===================================
6173 09:31:08.477035 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6174 09:31:08.480215 nWR fixed to 30
6175 09:31:08.480631 [ModeRegInit_LP4] CH0 RK0
6176 09:31:08.483388 [ModeRegInit_LP4] CH0 RK1
6177 09:31:08.486647 [ModeRegInit_LP4] CH1 RK0
6178 09:31:08.487162 [ModeRegInit_LP4] CH1 RK1
6179 09:31:08.489883 match AC timing 19
6180 09:31:08.493289 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6181 09:31:08.499744 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6182 09:31:08.502957 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6183 09:31:08.509829 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6184 09:31:08.513034 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6185 09:31:08.513601 ==
6186 09:31:08.515992 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 09:31:08.519689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6188 09:31:08.520232 ==
6189 09:31:08.526582 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6190 09:31:08.533082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6191 09:31:08.536204 [CA 0] Center 36 (8~64) winsize 57
6192 09:31:08.539171 [CA 1] Center 36 (8~64) winsize 57
6193 09:31:08.539784 [CA 2] Center 36 (8~64) winsize 57
6194 09:31:08.542806 [CA 3] Center 36 (8~64) winsize 57
6195 09:31:08.545984 [CA 4] Center 36 (8~64) winsize 57
6196 09:31:08.549414 [CA 5] Center 36 (8~64) winsize 57
6197 09:31:08.550020
6198 09:31:08.552536 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6199 09:31:08.556321
6200 09:31:08.559051 [CATrainingPosCal] consider 1 rank data
6201 09:31:08.562566 u2DelayCellTimex100 = 270/100 ps
6202 09:31:08.565692 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 09:31:08.568839 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 09:31:08.572305 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 09:31:08.575368 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 09:31:08.578895 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 09:31:08.582127 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 09:31:08.582727
6209 09:31:08.585339 CA PerBit enable=1, Macro0, CA PI delay=36
6210 09:31:08.585925
6211 09:31:08.588933 [CBTSetCACLKResult] CA Dly = 36
6212 09:31:08.592305 CS Dly: 1 (0~32)
6213 09:31:08.592883 ==
6214 09:31:08.595003 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 09:31:08.598270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 09:31:08.598725 ==
6217 09:31:08.605320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 09:31:08.611843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6219 09:31:08.615062 [CA 0] Center 36 (8~64) winsize 57
6220 09:31:08.615520 [CA 1] Center 36 (8~64) winsize 57
6221 09:31:08.618248 [CA 2] Center 36 (8~64) winsize 57
6222 09:31:08.621951 [CA 3] Center 36 (8~64) winsize 57
6223 09:31:08.624739 [CA 4] Center 36 (8~64) winsize 57
6224 09:31:08.628135 [CA 5] Center 36 (8~64) winsize 57
6225 09:31:08.628552
6226 09:31:08.631304 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6227 09:31:08.631760
6228 09:31:08.637979 [CATrainingPosCal] consider 2 rank data
6229 09:31:08.638553 u2DelayCellTimex100 = 270/100 ps
6230 09:31:08.644615 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 09:31:08.648006 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 09:31:08.651007 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 09:31:08.654307 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 09:31:08.657953 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 09:31:08.661167 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 09:31:08.661676
6237 09:31:08.664278 CA PerBit enable=1, Macro0, CA PI delay=36
6238 09:31:08.664691
6239 09:31:08.667993 [CBTSetCACLKResult] CA Dly = 36
6240 09:31:08.671214 CS Dly: 1 (0~32)
6241 09:31:08.671628
6242 09:31:08.674375 ----->DramcWriteLeveling(PI) begin...
6243 09:31:08.674822 ==
6244 09:31:08.677404 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 09:31:08.680996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 09:31:08.681413 ==
6247 09:31:08.684049 Write leveling (Byte 0): 40 => 8
6248 09:31:08.687200 Write leveling (Byte 1): 40 => 8
6249 09:31:08.690464 DramcWriteLeveling(PI) end<-----
6250 09:31:08.690932
6251 09:31:08.691503 ==
6252 09:31:08.693983 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 09:31:08.697422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 09:31:08.697840 ==
6255 09:31:08.700457 [Gating] SW mode calibration
6256 09:31:08.706904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6257 09:31:08.713791 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6258 09:31:08.717238 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 09:31:08.720420 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 09:31:08.726948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 09:31:08.730023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 09:31:08.736494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 09:31:08.740181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 09:31:08.743184 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 09:31:08.749709 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 09:31:08.753070 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 09:31:08.756408 Total UI for P1: 0, mck2ui 16
6268 09:31:08.759749 best dqsien dly found for B0: ( 0, 14, 24)
6269 09:31:08.763183 Total UI for P1: 0, mck2ui 16
6270 09:31:08.766410 best dqsien dly found for B1: ( 0, 14, 24)
6271 09:31:08.769927 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6272 09:31:08.773904 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6273 09:31:08.774333
6274 09:31:08.776428 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 09:31:08.779664 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 09:31:08.782729 [Gating] SW calibration Done
6277 09:31:08.783284 ==
6278 09:31:08.785853 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 09:31:08.789776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 09:31:08.792548 ==
6281 09:31:08.792965 RX Vref Scan: 0
6282 09:31:08.793298
6283 09:31:08.796235 RX Vref 0 -> 0, step: 1
6284 09:31:08.796725
6285 09:31:08.799124 RX Delay -410 -> 252, step: 16
6286 09:31:08.802308 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6287 09:31:08.805639 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6288 09:31:08.808981 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6289 09:31:08.815634 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6290 09:31:08.819179 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6291 09:31:08.822256 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6292 09:31:08.825187 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6293 09:31:08.831978 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6294 09:31:08.835382 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6295 09:31:08.838355 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6296 09:31:08.845297 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6297 09:31:08.848360 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6298 09:31:08.851758 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6299 09:31:08.855153 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6300 09:31:08.861965 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6301 09:31:08.864942 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6302 09:31:08.865436 ==
6303 09:31:08.868239 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 09:31:08.871604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 09:31:08.872034 ==
6306 09:31:08.874793 DQS Delay:
6307 09:31:08.875365 DQS0 = 35, DQS1 = 51
6308 09:31:08.878302 DQM Delay:
6309 09:31:08.878855 DQM0 = 7, DQM1 = 12
6310 09:31:08.879341 DQ Delay:
6311 09:31:08.881799 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6312 09:31:08.884655 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6313 09:31:08.887776 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6314 09:31:08.891398 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6315 09:31:08.891899
6316 09:31:08.892441
6317 09:31:08.892926 ==
6318 09:31:08.894856 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 09:31:08.900882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 09:31:08.901298 ==
6321 09:31:08.901622
6322 09:31:08.901920
6323 09:31:08.902208 TX Vref Scan disable
6324 09:31:08.904296 == TX Byte 0 ==
6325 09:31:08.907536 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 09:31:08.911251 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 09:31:08.914414 == TX Byte 1 ==
6328 09:31:08.917723 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 09:31:08.920628 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 09:31:08.921044 ==
6331 09:31:08.923949 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 09:31:08.930486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 09:31:08.931134 ==
6334 09:31:08.931520
6335 09:31:08.931869
6336 09:31:08.932167 TX Vref Scan disable
6337 09:31:08.934013 == TX Byte 0 ==
6338 09:31:08.937288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 09:31:08.940536 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 09:31:08.944267 == TX Byte 1 ==
6341 09:31:08.947022 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 09:31:08.954392 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 09:31:08.954990
6344 09:31:08.955527 [DATLAT]
6345 09:31:08.955982 Freq=400, CH0 RK0
6346 09:31:08.956429
6347 09:31:08.957197 DATLAT Default: 0xf
6348 09:31:08.957648 0, 0xFFFF, sum = 0
6349 09:31:08.960281 1, 0xFFFF, sum = 0
6350 09:31:08.963631 2, 0xFFFF, sum = 0
6351 09:31:08.964176 3, 0xFFFF, sum = 0
6352 09:31:08.966983 4, 0xFFFF, sum = 0
6353 09:31:08.967534 5, 0xFFFF, sum = 0
6354 09:31:08.970464 6, 0xFFFF, sum = 0
6355 09:31:08.970983 7, 0xFFFF, sum = 0
6356 09:31:08.973507 8, 0xFFFF, sum = 0
6357 09:31:08.974113 9, 0xFFFF, sum = 0
6358 09:31:08.976677 10, 0xFFFF, sum = 0
6359 09:31:08.977267 11, 0xFFFF, sum = 0
6360 09:31:08.980236 12, 0xFFFF, sum = 0
6361 09:31:08.980674 13, 0x0, sum = 1
6362 09:31:08.983471 14, 0x0, sum = 2
6363 09:31:08.983966 15, 0x0, sum = 3
6364 09:31:08.986273 16, 0x0, sum = 4
6365 09:31:08.986853 best_step = 14
6366 09:31:08.987311
6367 09:31:08.987625 ==
6368 09:31:08.989784 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 09:31:08.996520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 09:31:08.997156 ==
6371 09:31:08.997708 RX Vref Scan: 1
6372 09:31:08.998173
6373 09:31:08.999885 RX Vref 0 -> 0, step: 1
6374 09:31:09.000299
6375 09:31:09.002772 RX Delay -343 -> 252, step: 8
6376 09:31:09.003312
6377 09:31:09.006534 Set Vref, RX VrefLevel [Byte0]: 55
6378 09:31:09.010254 [Byte1]: 51
6379 09:31:09.010666
6380 09:31:09.013033 Final RX Vref Byte 0 = 55 to rank0
6381 09:31:09.016198 Final RX Vref Byte 1 = 51 to rank0
6382 09:31:09.019422 Final RX Vref Byte 0 = 55 to rank1
6383 09:31:09.022847 Final RX Vref Byte 1 = 51 to rank1==
6384 09:31:09.026652 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 09:31:09.029282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 09:31:09.032880 ==
6387 09:31:09.033421 DQS Delay:
6388 09:31:09.033941 DQS0 = 44, DQS1 = 60
6389 09:31:09.036813 DQM Delay:
6390 09:31:09.037311 DQM0 = 10, DQM1 = 17
6391 09:31:09.039278 DQ Delay:
6392 09:31:09.042657 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6393 09:31:09.043258 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6394 09:31:09.045560 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6395 09:31:09.049141 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6396 09:31:09.049750
6397 09:31:09.052348
6398 09:31:09.058793 [DQSOSCAuto] RK0, (LSB)MR18= 0x877b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
6399 09:31:09.062212 CH0 RK0: MR19=C0C, MR18=877B
6400 09:31:09.068955 CH0_RK0: MR19=0xC0C, MR18=0x877B, DQSOSC=392, MR23=63, INC=384, DEC=256
6401 09:31:09.069368 ==
6402 09:31:09.072069 Dram Type= 6, Freq= 0, CH_0, rank 1
6403 09:31:09.074941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 09:31:09.075021 ==
6405 09:31:09.078094 [Gating] SW mode calibration
6406 09:31:09.084865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 09:31:09.091360 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6408 09:31:09.094415 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 09:31:09.097848 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 09:31:09.104424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 09:31:09.107722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 09:31:09.110826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 09:31:09.117910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 09:31:09.121289 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 09:31:09.124442 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 09:31:09.131019 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 09:31:09.134536 Total UI for P1: 0, mck2ui 16
6418 09:31:09.137773 best dqsien dly found for B0: ( 0, 14, 24)
6419 09:31:09.140612 Total UI for P1: 0, mck2ui 16
6420 09:31:09.144433 best dqsien dly found for B1: ( 0, 14, 24)
6421 09:31:09.147436 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6422 09:31:09.150740 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6423 09:31:09.151290
6424 09:31:09.154022 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 09:31:09.157273 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 09:31:09.160624 [Gating] SW calibration Done
6427 09:31:09.161225 ==
6428 09:31:09.163988 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 09:31:09.167488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 09:31:09.167906 ==
6431 09:31:09.170374 RX Vref Scan: 0
6432 09:31:09.171034
6433 09:31:09.174745 RX Vref 0 -> 0, step: 1
6434 09:31:09.175264
6435 09:31:09.175588 RX Delay -410 -> 252, step: 16
6436 09:31:09.180615 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6437 09:31:09.183904 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6438 09:31:09.187437 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6439 09:31:09.193772 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6440 09:31:09.197153 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6441 09:31:09.200692 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6442 09:31:09.204193 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6443 09:31:09.210466 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6444 09:31:09.213475 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6445 09:31:09.217049 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6446 09:31:09.220488 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6447 09:31:09.227615 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6448 09:31:09.229864 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6449 09:31:09.233299 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6450 09:31:09.236950 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6451 09:31:09.243438 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6452 09:31:09.243905 ==
6453 09:31:09.246411 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 09:31:09.249689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 09:31:09.250311 ==
6456 09:31:09.253085 DQS Delay:
6457 09:31:09.253573 DQS0 = 35, DQS1 = 51
6458 09:31:09.253921 DQM Delay:
6459 09:31:09.256352 DQM0 = 6, DQM1 = 10
6460 09:31:09.256770 DQ Delay:
6461 09:31:09.259676 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6462 09:31:09.262872 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6463 09:31:09.266744 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6464 09:31:09.269604 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6465 09:31:09.270051
6466 09:31:09.270442
6467 09:31:09.270762 ==
6468 09:31:09.272617 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 09:31:09.276348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 09:31:09.279246 ==
6471 09:31:09.279689
6472 09:31:09.280020
6473 09:31:09.280351 TX Vref Scan disable
6474 09:31:09.282550 == TX Byte 0 ==
6475 09:31:09.286078 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6476 09:31:09.289346 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6477 09:31:09.292895 == TX Byte 1 ==
6478 09:31:09.295524 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6479 09:31:09.299060 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6480 09:31:09.299711 ==
6481 09:31:09.302374 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 09:31:09.309108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 09:31:09.309524 ==
6484 09:31:09.309856
6485 09:31:09.310158
6486 09:31:09.310449 TX Vref Scan disable
6487 09:31:09.312225 == TX Byte 0 ==
6488 09:31:09.315905 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6489 09:31:09.318714 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6490 09:31:09.321742 == TX Byte 1 ==
6491 09:31:09.325035 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6492 09:31:09.328418 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6493 09:31:09.328921
6494 09:31:09.331865 [DATLAT]
6495 09:31:09.332467 Freq=400, CH0 RK1
6496 09:31:09.333017
6497 09:31:09.334951 DATLAT Default: 0xe
6498 09:31:09.335399 0, 0xFFFF, sum = 0
6499 09:31:09.338688 1, 0xFFFF, sum = 0
6500 09:31:09.339268 2, 0xFFFF, sum = 0
6501 09:31:09.341654 3, 0xFFFF, sum = 0
6502 09:31:09.342247 4, 0xFFFF, sum = 0
6503 09:31:09.345057 5, 0xFFFF, sum = 0
6504 09:31:09.345667 6, 0xFFFF, sum = 0
6505 09:31:09.349038 7, 0xFFFF, sum = 0
6506 09:31:09.349574 8, 0xFFFF, sum = 0
6507 09:31:09.352016 9, 0xFFFF, sum = 0
6508 09:31:09.354864 10, 0xFFFF, sum = 0
6509 09:31:09.355372 11, 0xFFFF, sum = 0
6510 09:31:09.358410 12, 0xFFFF, sum = 0
6511 09:31:09.358828 13, 0x0, sum = 1
6512 09:31:09.361738 14, 0x0, sum = 2
6513 09:31:09.362159 15, 0x0, sum = 3
6514 09:31:09.362494 16, 0x0, sum = 4
6515 09:31:09.365454 best_step = 14
6516 09:31:09.365869
6517 09:31:09.366201 ==
6518 09:31:09.368134 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 09:31:09.371800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 09:31:09.372215 ==
6521 09:31:09.374897 RX Vref Scan: 0
6522 09:31:09.375435
6523 09:31:09.378414 RX Vref 0 -> 0, step: 1
6524 09:31:09.378826
6525 09:31:09.379201 RX Delay -343 -> 252, step: 8
6526 09:31:09.386427 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6527 09:31:09.389446 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6528 09:31:09.393344 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6529 09:31:09.399691 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6530 09:31:09.403178 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6531 09:31:09.406715 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6532 09:31:09.409516 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6533 09:31:09.416295 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6534 09:31:09.419257 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6535 09:31:09.423326 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6536 09:31:09.425889 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6537 09:31:09.432559 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6538 09:31:09.436425 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6539 09:31:09.439396 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6540 09:31:09.445820 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6541 09:31:09.448999 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6542 09:31:09.449417 ==
6543 09:31:09.453030 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 09:31:09.456124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 09:31:09.456576 ==
6546 09:31:09.459017 DQS Delay:
6547 09:31:09.459498 DQS0 = 48, DQS1 = 60
6548 09:31:09.460011 DQM Delay:
6549 09:31:09.461774 DQM0 = 13, DQM1 = 15
6550 09:31:09.461880 DQ Delay:
6551 09:31:09.464994 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6552 09:31:09.468947 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =16
6553 09:31:09.471985 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6554 09:31:09.475060 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6555 09:31:09.475202
6556 09:31:09.475302
6557 09:31:09.484580 [DQSOSCAuto] RK1, (LSB)MR18= 0x817b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6558 09:31:09.487992 CH0 RK1: MR19=C0C, MR18=817B
6559 09:31:09.491541 CH0_RK1: MR19=0xC0C, MR18=0x817B, DQSOSC=393, MR23=63, INC=382, DEC=254
6560 09:31:09.494905 [RxdqsGatingPostProcess] freq 400
6561 09:31:09.501315 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6562 09:31:09.504684 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 09:31:09.507729 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 09:31:09.511898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 09:31:09.514296 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 09:31:09.517903 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 09:31:09.520817 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 09:31:09.525016 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 09:31:09.527365 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 09:31:09.531006 Pre-setting of DQS Precalculation
6571 09:31:09.534363 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6572 09:31:09.534948 ==
6573 09:31:09.537423 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 09:31:09.541183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 09:31:09.544211 ==
6576 09:31:09.547936 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6577 09:31:09.554574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6578 09:31:09.557517 [CA 0] Center 36 (8~64) winsize 57
6579 09:31:09.560523 [CA 1] Center 36 (8~64) winsize 57
6580 09:31:09.563789 [CA 2] Center 36 (8~64) winsize 57
6581 09:31:09.567202 [CA 3] Center 36 (8~64) winsize 57
6582 09:31:09.570363 [CA 4] Center 36 (8~64) winsize 57
6583 09:31:09.573961 [CA 5] Center 36 (8~64) winsize 57
6584 09:31:09.574461
6585 09:31:09.576923 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6586 09:31:09.577521
6587 09:31:09.580340 [CATrainingPosCal] consider 1 rank data
6588 09:31:09.584741 u2DelayCellTimex100 = 270/100 ps
6589 09:31:09.586822 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 09:31:09.590194 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 09:31:09.593761 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 09:31:09.596717 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 09:31:09.600195 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 09:31:09.603800 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 09:31:09.606655
6596 09:31:09.609656 CA PerBit enable=1, Macro0, CA PI delay=36
6597 09:31:09.610198
6598 09:31:09.613126 [CBTSetCACLKResult] CA Dly = 36
6599 09:31:09.613672 CS Dly: 1 (0~32)
6600 09:31:09.614145 ==
6601 09:31:09.616792 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 09:31:09.619567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 09:31:09.622664 ==
6604 09:31:09.625964 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 09:31:09.632788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6606 09:31:09.636271 [CA 0] Center 36 (8~64) winsize 57
6607 09:31:09.639211 [CA 1] Center 36 (8~64) winsize 57
6608 09:31:09.642797 [CA 2] Center 36 (8~64) winsize 57
6609 09:31:09.645806 [CA 3] Center 36 (8~64) winsize 57
6610 09:31:09.649165 [CA 4] Center 36 (8~64) winsize 57
6611 09:31:09.652341 [CA 5] Center 36 (8~64) winsize 57
6612 09:31:09.652760
6613 09:31:09.655709 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6614 09:31:09.656123
6615 09:31:09.659191 [CATrainingPosCal] consider 2 rank data
6616 09:31:09.662516 u2DelayCellTimex100 = 270/100 ps
6617 09:31:09.665437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 09:31:09.669377 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 09:31:09.672111 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 09:31:09.675273 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 09:31:09.678792 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 09:31:09.682552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 09:31:09.685413
6624 09:31:09.688574 CA PerBit enable=1, Macro0, CA PI delay=36
6625 09:31:09.688988
6626 09:31:09.692377 [CBTSetCACLKResult] CA Dly = 36
6627 09:31:09.692791 CS Dly: 1 (0~32)
6628 09:31:09.693120
6629 09:31:09.695488 ----->DramcWriteLeveling(PI) begin...
6630 09:31:09.695570 ==
6631 09:31:09.698949 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 09:31:09.701656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 09:31:09.704738 ==
6634 09:31:09.704818 Write leveling (Byte 0): 40 => 8
6635 09:31:09.707813 Write leveling (Byte 1): 40 => 8
6636 09:31:09.711312 DramcWriteLeveling(PI) end<-----
6637 09:31:09.711398
6638 09:31:09.711466 ==
6639 09:31:09.715091 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 09:31:09.720803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 09:31:09.720946 ==
6642 09:31:09.724595 [Gating] SW mode calibration
6643 09:31:09.731371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6644 09:31:09.734553 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6645 09:31:09.741040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 09:31:09.744406 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 09:31:09.748145 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 09:31:09.754496 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 09:31:09.757552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 09:31:09.760508 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 09:31:09.767441 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 09:31:09.770463 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 09:31:09.773761 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 09:31:09.777047 Total UI for P1: 0, mck2ui 16
6655 09:31:09.780460 best dqsien dly found for B0: ( 0, 14, 24)
6656 09:31:09.783741 Total UI for P1: 0, mck2ui 16
6657 09:31:09.786882 best dqsien dly found for B1: ( 0, 14, 24)
6658 09:31:09.791345 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6659 09:31:09.793581 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6660 09:31:09.793660
6661 09:31:09.800144 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 09:31:09.803820 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 09:31:09.803913 [Gating] SW calibration Done
6664 09:31:09.807053 ==
6665 09:31:09.810081 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 09:31:09.813557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 09:31:09.813669 ==
6668 09:31:09.813756 RX Vref Scan: 0
6669 09:31:09.813838
6670 09:31:09.817285 RX Vref 0 -> 0, step: 1
6671 09:31:09.817413
6672 09:31:09.820106 RX Delay -410 -> 252, step: 16
6673 09:31:09.823503 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6674 09:31:09.829841 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6675 09:31:09.833388 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6676 09:31:09.836705 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6677 09:31:09.839915 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6678 09:31:09.846429 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6679 09:31:09.849822 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6680 09:31:09.853025 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6681 09:31:09.856239 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6682 09:31:09.862781 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6683 09:31:09.865817 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6684 09:31:09.869256 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6685 09:31:09.872855 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6686 09:31:09.879391 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6687 09:31:09.882515 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6688 09:31:09.885630 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6689 09:31:09.885741 ==
6690 09:31:09.889111 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 09:31:09.895893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 09:31:09.895980 ==
6693 09:31:09.896048 DQS Delay:
6694 09:31:09.898952 DQS0 = 43, DQS1 = 51
6695 09:31:09.899080 DQM Delay:
6696 09:31:09.902450 DQM0 = 13, DQM1 = 13
6697 09:31:09.902549 DQ Delay:
6698 09:31:09.905743 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6699 09:31:09.909266 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6700 09:31:09.912519 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6701 09:31:09.915455 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6702 09:31:09.915613
6703 09:31:09.915712
6704 09:31:09.915800 ==
6705 09:31:09.918486 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 09:31:09.922326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 09:31:09.922513 ==
6708 09:31:09.922681
6709 09:31:09.922838
6710 09:31:09.925539 TX Vref Scan disable
6711 09:31:09.925666 == TX Byte 0 ==
6712 09:31:09.932435 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 09:31:09.935182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 09:31:09.935395 == TX Byte 1 ==
6715 09:31:09.941741 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 09:31:09.945533 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 09:31:09.945909 ==
6718 09:31:09.948825 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 09:31:09.952303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 09:31:09.952736 ==
6721 09:31:09.953190
6722 09:31:09.953504
6723 09:31:09.955435 TX Vref Scan disable
6724 09:31:09.955925 == TX Byte 0 ==
6725 09:31:09.961754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 09:31:09.965060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 09:31:09.965476 == TX Byte 1 ==
6728 09:31:09.972141 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 09:31:09.975105 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 09:31:09.975536
6731 09:31:09.975869 [DATLAT]
6732 09:31:09.978097 Freq=400, CH1 RK0
6733 09:31:09.978514
6734 09:31:09.978847 DATLAT Default: 0xf
6735 09:31:09.981621 0, 0xFFFF, sum = 0
6736 09:31:09.982044 1, 0xFFFF, sum = 0
6737 09:31:09.985470 2, 0xFFFF, sum = 0
6738 09:31:09.985939 3, 0xFFFF, sum = 0
6739 09:31:09.988081 4, 0xFFFF, sum = 0
6740 09:31:09.991631 5, 0xFFFF, sum = 0
6741 09:31:09.992055 6, 0xFFFF, sum = 0
6742 09:31:09.994505 7, 0xFFFF, sum = 0
6743 09:31:09.994928 8, 0xFFFF, sum = 0
6744 09:31:09.997871 9, 0xFFFF, sum = 0
6745 09:31:09.998295 10, 0xFFFF, sum = 0
6746 09:31:10.001350 11, 0xFFFF, sum = 0
6747 09:31:10.001929 12, 0xFFFF, sum = 0
6748 09:31:10.004483 13, 0x0, sum = 1
6749 09:31:10.004901 14, 0x0, sum = 2
6750 09:31:10.007674 15, 0x0, sum = 3
6751 09:31:10.008134 16, 0x0, sum = 4
6752 09:31:10.011191 best_step = 14
6753 09:31:10.011804
6754 09:31:10.012169 ==
6755 09:31:10.014433 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 09:31:10.017789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 09:31:10.018352 ==
6758 09:31:10.020946 RX Vref Scan: 1
6759 09:31:10.021363
6760 09:31:10.021743 RX Vref 0 -> 0, step: 1
6761 09:31:10.022275
6762 09:31:10.024796 RX Delay -343 -> 252, step: 8
6763 09:31:10.025416
6764 09:31:10.027484 Set Vref, RX VrefLevel [Byte0]: 55
6765 09:31:10.031183 [Byte1]: 53
6766 09:31:10.035162
6767 09:31:10.035574 Final RX Vref Byte 0 = 55 to rank0
6768 09:31:10.038336 Final RX Vref Byte 1 = 53 to rank0
6769 09:31:10.041850 Final RX Vref Byte 0 = 55 to rank1
6770 09:31:10.045027 Final RX Vref Byte 1 = 53 to rank1==
6771 09:31:10.048739 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 09:31:10.054997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 09:31:10.055451 ==
6774 09:31:10.055785 DQS Delay:
6775 09:31:10.058056 DQS0 = 44, DQS1 = 52
6776 09:31:10.058519 DQM Delay:
6777 09:31:10.058854 DQM0 = 10, DQM1 = 10
6778 09:31:10.061488 DQ Delay:
6779 09:31:10.065172 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6780 09:31:10.068237 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6781 09:31:10.068649 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6782 09:31:10.071520 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6783 09:31:10.074781
6784 09:31:10.075247
6785 09:31:10.081185 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 398 ps
6786 09:31:10.084493 CH1 RK0: MR19=C0C, MR18=5B83
6787 09:31:10.090815 CH1_RK0: MR19=0xC0C, MR18=0x5B83, DQSOSC=393, MR23=63, INC=382, DEC=254
6788 09:31:10.091288 ==
6789 09:31:10.094609 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 09:31:10.097716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 09:31:10.098143 ==
6792 09:31:10.100911 [Gating] SW mode calibration
6793 09:31:10.107796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6794 09:31:10.114072 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6795 09:31:10.117469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 09:31:10.121053 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 09:31:10.127594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 09:31:10.130984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 09:31:10.133981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 09:31:10.140945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 09:31:10.143956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 09:31:10.147641 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 09:31:10.154032 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 09:31:10.154445 Total UI for P1: 0, mck2ui 16
6805 09:31:10.160433 best dqsien dly found for B0: ( 0, 14, 24)
6806 09:31:10.160924 Total UI for P1: 0, mck2ui 16
6807 09:31:10.167279 best dqsien dly found for B1: ( 0, 14, 24)
6808 09:31:10.170699 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6809 09:31:10.173570 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6810 09:31:10.174130
6811 09:31:10.176767 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 09:31:10.180303 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 09:31:10.183385 [Gating] SW calibration Done
6814 09:31:10.183818 ==
6815 09:31:10.186555 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 09:31:10.190094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 09:31:10.190476 ==
6818 09:31:10.193417 RX Vref Scan: 0
6819 09:31:10.193813
6820 09:31:10.194159 RX Vref 0 -> 0, step: 1
6821 09:31:10.196632
6822 09:31:10.196978 RX Delay -410 -> 252, step: 16
6823 09:31:10.203530 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6824 09:31:10.206434 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6825 09:31:10.209878 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6826 09:31:10.213465 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6827 09:31:10.219678 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6828 09:31:10.223050 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6829 09:31:10.226412 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6830 09:31:10.229951 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6831 09:31:10.236040 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6832 09:31:10.239417 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6833 09:31:10.243011 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6834 09:31:10.249366 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6835 09:31:10.252917 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6836 09:31:10.256209 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6837 09:31:10.259479 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6838 09:31:10.266173 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6839 09:31:10.266726 ==
6840 09:31:10.268940 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 09:31:10.272355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 09:31:10.272919 ==
6843 09:31:10.273428 DQS Delay:
6844 09:31:10.275679 DQS0 = 43, DQS1 = 51
6845 09:31:10.276127 DQM Delay:
6846 09:31:10.279047 DQM0 = 10, DQM1 = 15
6847 09:31:10.279519 DQ Delay:
6848 09:31:10.282267 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6849 09:31:10.285838 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6850 09:31:10.289067 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6851 09:31:10.292005 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6852 09:31:10.292416
6853 09:31:10.292773
6854 09:31:10.293083 ==
6855 09:31:10.295581 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 09:31:10.299213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 09:31:10.299668 ==
6858 09:31:10.301913
6859 09:31:10.302449
6860 09:31:10.302938 TX Vref Scan disable
6861 09:31:10.305385 == TX Byte 0 ==
6862 09:31:10.308555 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6863 09:31:10.311658 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6864 09:31:10.315641 == TX Byte 1 ==
6865 09:31:10.318448 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6866 09:31:10.321643 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6867 09:31:10.322213 ==
6868 09:31:10.324976 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 09:31:10.331625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 09:31:10.332044 ==
6871 09:31:10.332374
6872 09:31:10.332678
6873 09:31:10.332966 TX Vref Scan disable
6874 09:31:10.334652 == TX Byte 0 ==
6875 09:31:10.338225 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6876 09:31:10.341758 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6877 09:31:10.344824 == TX Byte 1 ==
6878 09:31:10.347867 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6879 09:31:10.351404 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6880 09:31:10.351824
6881 09:31:10.354412 [DATLAT]
6882 09:31:10.354828 Freq=400, CH1 RK1
6883 09:31:10.355211
6884 09:31:10.357806 DATLAT Default: 0xe
6885 09:31:10.358225 0, 0xFFFF, sum = 0
6886 09:31:10.361496 1, 0xFFFF, sum = 0
6887 09:31:10.361918 2, 0xFFFF, sum = 0
6888 09:31:10.364415 3, 0xFFFF, sum = 0
6889 09:31:10.364841 4, 0xFFFF, sum = 0
6890 09:31:10.367464 5, 0xFFFF, sum = 0
6891 09:31:10.367885 6, 0xFFFF, sum = 0
6892 09:31:10.370937 7, 0xFFFF, sum = 0
6893 09:31:10.371395 8, 0xFFFF, sum = 0
6894 09:31:10.375163 9, 0xFFFF, sum = 0
6895 09:31:10.377366 10, 0xFFFF, sum = 0
6896 09:31:10.377788 11, 0xFFFF, sum = 0
6897 09:31:10.380862 12, 0xFFFF, sum = 0
6898 09:31:10.381311 13, 0x0, sum = 1
6899 09:31:10.384146 14, 0x0, sum = 2
6900 09:31:10.384571 15, 0x0, sum = 3
6901 09:31:10.387919 16, 0x0, sum = 4
6902 09:31:10.388341 best_step = 14
6903 09:31:10.388727
6904 09:31:10.389053 ==
6905 09:31:10.390680 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 09:31:10.394041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 09:31:10.394497 ==
6908 09:31:10.397195 RX Vref Scan: 0
6909 09:31:10.397611
6910 09:31:10.400678 RX Vref 0 -> 0, step: 1
6911 09:31:10.401101
6912 09:31:10.401678 RX Delay -343 -> 252, step: 8
6913 09:31:10.409585 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6914 09:31:10.412711 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6915 09:31:10.415821 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6916 09:31:10.422692 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6917 09:31:10.425678 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6918 09:31:10.428755 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6919 09:31:10.431981 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6920 09:31:10.439256 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6921 09:31:10.442131 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6922 09:31:10.445134 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6923 09:31:10.449135 iDelay=217, Bit 10, Center -36 (-279 ~ 208) 488
6924 09:31:10.455375 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6925 09:31:10.459061 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6926 09:31:10.462071 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6927 09:31:10.468623 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6928 09:31:10.471677 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6929 09:31:10.472095 ==
6930 09:31:10.475019 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 09:31:10.478357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 09:31:10.478830 ==
6933 09:31:10.481382 DQS Delay:
6934 09:31:10.481798 DQS0 = 48, DQS1 = 56
6935 09:31:10.482210 DQM Delay:
6936 09:31:10.484932 DQM0 = 12, DQM1 = 15
6937 09:31:10.485376 DQ Delay:
6938 09:31:10.488042 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6939 09:31:10.491161 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6940 09:31:10.494437 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6941 09:31:10.497948 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6942 09:31:10.498367
6943 09:31:10.498699
6944 09:31:10.507632 [DQSOSCAuto] RK1, (LSB)MR18= 0x6da4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6945 09:31:10.508055 CH1 RK1: MR19=C0C, MR18=6DA4
6946 09:31:10.514586 CH1_RK1: MR19=0xC0C, MR18=0x6DA4, DQSOSC=389, MR23=63, INC=390, DEC=260
6947 09:31:10.517814 [RxdqsGatingPostProcess] freq 400
6948 09:31:10.524506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6949 09:31:10.527664 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 09:31:10.531344 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 09:31:10.533991 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 09:31:10.537533 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 09:31:10.541126 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 09:31:10.544203 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 09:31:10.547197 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 09:31:10.550695 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 09:31:10.554171 Pre-setting of DQS Precalculation
6958 09:31:10.557685 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6959 09:31:10.563653 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6960 09:31:10.569842 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6961 09:31:10.569936
6962 09:31:10.573102
6963 09:31:10.573182 [Calibration Summary] 800 Mbps
6964 09:31:10.576417 CH 0, Rank 0
6965 09:31:10.576523 SW Impedance : PASS
6966 09:31:10.579846 DUTY Scan : NO K
6967 09:31:10.583021 ZQ Calibration : PASS
6968 09:31:10.583140 Jitter Meter : NO K
6969 09:31:10.586453 CBT Training : PASS
6970 09:31:10.589630 Write leveling : PASS
6971 09:31:10.589723 RX DQS gating : PASS
6972 09:31:10.592723 RX DQ/DQS(RDDQC) : PASS
6973 09:31:10.596389 TX DQ/DQS : PASS
6974 09:31:10.596483 RX DATLAT : PASS
6975 09:31:10.600055 RX DQ/DQS(Engine): PASS
6976 09:31:10.602827 TX OE : NO K
6977 09:31:10.602909 All Pass.
6978 09:31:10.602974
6979 09:31:10.603034 CH 0, Rank 1
6980 09:31:10.606149 SW Impedance : PASS
6981 09:31:10.609635 DUTY Scan : NO K
6982 09:31:10.609719 ZQ Calibration : PASS
6983 09:31:10.612747 Jitter Meter : NO K
6984 09:31:10.616239 CBT Training : PASS
6985 09:31:10.616321 Write leveling : NO K
6986 09:31:10.619563 RX DQS gating : PASS
6987 09:31:10.622541 RX DQ/DQS(RDDQC) : PASS
6988 09:31:10.622622 TX DQ/DQS : PASS
6989 09:31:10.625990 RX DATLAT : PASS
6990 09:31:10.628942 RX DQ/DQS(Engine): PASS
6991 09:31:10.629023 TX OE : NO K
6992 09:31:10.629089 All Pass.
6993 09:31:10.632622
6994 09:31:10.632703 CH 1, Rank 0
6995 09:31:10.635709 SW Impedance : PASS
6996 09:31:10.635790 DUTY Scan : NO K
6997 09:31:10.639394 ZQ Calibration : PASS
6998 09:31:10.642492 Jitter Meter : NO K
6999 09:31:10.642573 CBT Training : PASS
7000 09:31:10.645659 Write leveling : PASS
7001 09:31:10.645740 RX DQS gating : PASS
7002 09:31:10.649315 RX DQ/DQS(RDDQC) : PASS
7003 09:31:10.651975 TX DQ/DQS : PASS
7004 09:31:10.652055 RX DATLAT : PASS
7005 09:31:10.655776 RX DQ/DQS(Engine): PASS
7006 09:31:10.658624 TX OE : NO K
7007 09:31:10.658711 All Pass.
7008 09:31:10.658779
7009 09:31:10.658844 CH 1, Rank 1
7010 09:31:10.661956 SW Impedance : PASS
7011 09:31:10.665430 DUTY Scan : NO K
7012 09:31:10.665523 ZQ Calibration : PASS
7013 09:31:10.669017 Jitter Meter : NO K
7014 09:31:10.672509 CBT Training : PASS
7015 09:31:10.672619 Write leveling : NO K
7016 09:31:10.675195 RX DQS gating : PASS
7017 09:31:10.678323 RX DQ/DQS(RDDQC) : PASS
7018 09:31:10.678444 TX DQ/DQS : PASS
7019 09:31:10.682285 RX DATLAT : PASS
7020 09:31:10.684970 RX DQ/DQS(Engine): PASS
7021 09:31:10.685104 TX OE : NO K
7022 09:31:10.688786 All Pass.
7023 09:31:10.688934
7024 09:31:10.689052 DramC Write-DBI off
7025 09:31:10.691593 PER_BANK_REFRESH: Hybrid Mode
7026 09:31:10.691743 TX_TRACKING: ON
7027 09:31:10.701664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7028 09:31:10.705329 [FAST_K] Save calibration result to emmc
7029 09:31:10.708178 dramc_set_vcore_voltage set vcore to 725000
7030 09:31:10.711560 Read voltage for 1600, 0
7031 09:31:10.711857 Vio18 = 0
7032 09:31:10.715736 Vcore = 725000
7033 09:31:10.716118 Vdram = 0
7034 09:31:10.716475 Vddq = 0
7035 09:31:10.718436 Vmddr = 0
7036 09:31:10.721509 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7037 09:31:10.727986 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7038 09:31:10.731208 MEM_TYPE=3, freq_sel=13
7039 09:31:10.731629 sv_algorithm_assistance_LP4_3733
7040 09:31:10.738226 ============ PULL DRAM RESETB DOWN ============
7041 09:31:10.741005 ========== PULL DRAM RESETB DOWN end =========
7042 09:31:10.744243 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7043 09:31:10.747591 ===================================
7044 09:31:10.751186 LPDDR4 DRAM CONFIGURATION
7045 09:31:10.754297 ===================================
7046 09:31:10.757617 EX_ROW_EN[0] = 0x0
7047 09:31:10.758034 EX_ROW_EN[1] = 0x0
7048 09:31:10.760627 LP4Y_EN = 0x0
7049 09:31:10.761044 WORK_FSP = 0x1
7050 09:31:10.764398 WL = 0x5
7051 09:31:10.764817 RL = 0x5
7052 09:31:10.767183 BL = 0x2
7053 09:31:10.767601 RPST = 0x0
7054 09:31:10.770440 RD_PRE = 0x0
7055 09:31:10.774309 WR_PRE = 0x1
7056 09:31:10.774725 WR_PST = 0x1
7057 09:31:10.777533 DBI_WR = 0x0
7058 09:31:10.778057 DBI_RD = 0x0
7059 09:31:10.780929 OTF = 0x1
7060 09:31:10.783733 ===================================
7061 09:31:10.787574 ===================================
7062 09:31:10.787997 ANA top config
7063 09:31:10.790672 ===================================
7064 09:31:10.793712 DLL_ASYNC_EN = 0
7065 09:31:10.797137 ALL_SLAVE_EN = 0
7066 09:31:10.797570 NEW_RANK_MODE = 1
7067 09:31:10.800041 DLL_IDLE_MODE = 1
7068 09:31:10.803516 LP45_APHY_COMB_EN = 1
7069 09:31:10.807050 TX_ODT_DIS = 0
7070 09:31:10.810025 NEW_8X_MODE = 1
7071 09:31:10.813125 ===================================
7072 09:31:10.817182 ===================================
7073 09:31:10.817629 data_rate = 3200
7074 09:31:10.819933 CKR = 1
7075 09:31:10.823143 DQ_P2S_RATIO = 8
7076 09:31:10.826615 ===================================
7077 09:31:10.830188 CA_P2S_RATIO = 8
7078 09:31:10.832959 DQ_CA_OPEN = 0
7079 09:31:10.836470 DQ_SEMI_OPEN = 0
7080 09:31:10.836889 CA_SEMI_OPEN = 0
7081 09:31:10.839505 CA_FULL_RATE = 0
7082 09:31:10.843154 DQ_CKDIV4_EN = 0
7083 09:31:10.846632 CA_CKDIV4_EN = 0
7084 09:31:10.849889 CA_PREDIV_EN = 0
7085 09:31:10.853158 PH8_DLY = 12
7086 09:31:10.856271 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7087 09:31:10.856690 DQ_AAMCK_DIV = 4
7088 09:31:10.859552 CA_AAMCK_DIV = 4
7089 09:31:10.862628 CA_ADMCK_DIV = 4
7090 09:31:10.866682 DQ_TRACK_CA_EN = 0
7091 09:31:10.869523 CA_PICK = 1600
7092 09:31:10.872799 CA_MCKIO = 1600
7093 09:31:10.876102 MCKIO_SEMI = 0
7094 09:31:10.876520 PLL_FREQ = 3068
7095 09:31:10.879591 DQ_UI_PI_RATIO = 32
7096 09:31:10.883041 CA_UI_PI_RATIO = 0
7097 09:31:10.886222 ===================================
7098 09:31:10.889478 ===================================
7099 09:31:10.892773 memory_type:LPDDR4
7100 09:31:10.893219 GP_NUM : 10
7101 09:31:10.895976 SRAM_EN : 1
7102 09:31:10.899068 MD32_EN : 0
7103 09:31:10.902363 ===================================
7104 09:31:10.902782 [ANA_INIT] >>>>>>>>>>>>>>
7105 09:31:10.905416 <<<<<< [CONFIGURE PHASE]: ANA_TX
7106 09:31:10.909093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7107 09:31:10.912476 ===================================
7108 09:31:10.915353 data_rate = 3200,PCW = 0X7600
7109 09:31:10.918952 ===================================
7110 09:31:10.922158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7111 09:31:10.929965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 09:31:10.935856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 09:31:10.938686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7114 09:31:10.941771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7115 09:31:10.945532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7116 09:31:10.948978 [ANA_INIT] flow start
7117 09:31:10.949393 [ANA_INIT] PLL >>>>>>>>
7118 09:31:10.952176 [ANA_INIT] PLL <<<<<<<<
7119 09:31:10.954928 [ANA_INIT] MIDPI >>>>>>>>
7120 09:31:10.958283 [ANA_INIT] MIDPI <<<<<<<<
7121 09:31:10.958698 [ANA_INIT] DLL >>>>>>>>
7122 09:31:10.961358 [ANA_INIT] DLL <<<<<<<<
7123 09:31:10.961775 [ANA_INIT] flow end
7124 09:31:10.968514 ============ LP4 DIFF to SE enter ============
7125 09:31:10.972001 ============ LP4 DIFF to SE exit ============
7126 09:31:10.974777 [ANA_INIT] <<<<<<<<<<<<<
7127 09:31:10.978462 [Flow] Enable top DCM control >>>>>
7128 09:31:10.982080 [Flow] Enable top DCM control <<<<<
7129 09:31:10.984567 Enable DLL master slave shuffle
7130 09:31:10.988153 ==============================================================
7131 09:31:10.991106 Gating Mode config
7132 09:31:10.995488 ==============================================================
7133 09:31:10.998131 Config description:
7134 09:31:11.007913 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7135 09:31:11.014440 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7136 09:31:11.017885 SELPH_MODE 0: By rank 1: By Phase
7137 09:31:11.024545 ==============================================================
7138 09:31:11.027488 GAT_TRACK_EN = 1
7139 09:31:11.030480 RX_GATING_MODE = 2
7140 09:31:11.033862 RX_GATING_TRACK_MODE = 2
7141 09:31:11.037129 SELPH_MODE = 1
7142 09:31:11.040459 PICG_EARLY_EN = 1
7143 09:31:11.043470 VALID_LAT_VALUE = 1
7144 09:31:11.047643 ==============================================================
7145 09:31:11.050253 Enter into Gating configuration >>>>
7146 09:31:11.054389 Exit from Gating configuration <<<<
7147 09:31:11.056819 Enter into DVFS_PRE_config >>>>>
7148 09:31:11.070421 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7149 09:31:11.073595 Exit from DVFS_PRE_config <<<<<
7150 09:31:11.077084 Enter into PICG configuration >>>>
7151 09:31:11.077501 Exit from PICG configuration <<<<
7152 09:31:11.080121 [RX_INPUT] configuration >>>>>
7153 09:31:11.083580 [RX_INPUT] configuration <<<<<
7154 09:31:11.089683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7155 09:31:11.093214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7156 09:31:11.099526 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 09:31:11.106051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 09:31:11.113079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 09:31:11.119129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 09:31:11.123196 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7161 09:31:11.126160 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7162 09:31:11.132641 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7163 09:31:11.135697 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7164 09:31:11.138959 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7165 09:31:11.145891 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 09:31:11.148330 ===================================
7167 09:31:11.148434 LPDDR4 DRAM CONFIGURATION
7168 09:31:11.152063 ===================================
7169 09:31:11.155434 EX_ROW_EN[0] = 0x0
7170 09:31:11.155528 EX_ROW_EN[1] = 0x0
7171 09:31:11.158679 LP4Y_EN = 0x0
7172 09:31:11.158788 WORK_FSP = 0x1
7173 09:31:11.162165 WL = 0x5
7174 09:31:11.162265 RL = 0x5
7175 09:31:11.165777 BL = 0x2
7176 09:31:11.168453 RPST = 0x0
7177 09:31:11.168566 RD_PRE = 0x0
7178 09:31:11.172045 WR_PRE = 0x1
7179 09:31:11.172117 WR_PST = 0x1
7180 09:31:11.175209 DBI_WR = 0x0
7181 09:31:11.175278 DBI_RD = 0x0
7182 09:31:11.178562 OTF = 0x1
7183 09:31:11.181462 ===================================
7184 09:31:11.184852 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7185 09:31:11.188445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7186 09:31:11.194897 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 09:31:11.198134 ===================================
7188 09:31:11.198234 LPDDR4 DRAM CONFIGURATION
7189 09:31:11.201623 ===================================
7190 09:31:11.204858 EX_ROW_EN[0] = 0x10
7191 09:31:11.204973 EX_ROW_EN[1] = 0x0
7192 09:31:11.208043 LP4Y_EN = 0x0
7193 09:31:11.208161 WORK_FSP = 0x1
7194 09:31:11.211893 WL = 0x5
7195 09:31:11.214947 RL = 0x5
7196 09:31:11.215134 BL = 0x2
7197 09:31:11.217971 RPST = 0x0
7198 09:31:11.218052 RD_PRE = 0x0
7199 09:31:11.221281 WR_PRE = 0x1
7200 09:31:11.221392 WR_PST = 0x1
7201 09:31:11.224767 DBI_WR = 0x0
7202 09:31:11.224875 DBI_RD = 0x0
7203 09:31:11.228000 OTF = 0x1
7204 09:31:11.231609 ===================================
7205 09:31:11.237844 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7206 09:31:11.237926 ==
7207 09:31:11.241134 Dram Type= 6, Freq= 0, CH_0, rank 0
7208 09:31:11.244694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7209 09:31:11.244801 ==
7210 09:31:11.247316 [Duty_Offset_Calibration]
7211 09:31:11.247443 B0:2 B1:0 CA:4
7212 09:31:11.247509
7213 09:31:11.250616 [DutyScan_Calibration_Flow] k_type=0
7214 09:31:11.260578
7215 09:31:11.260691 ==CLK 0==
7216 09:31:11.263826 Final CLK duty delay cell = -4
7217 09:31:11.266994 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7218 09:31:11.270483 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7219 09:31:11.274433 [-4] AVG Duty = 4922%(X100)
7220 09:31:11.274880
7221 09:31:11.277211 CH0 CLK Duty spec in!! Max-Min= 218%
7222 09:31:11.280858 [DutyScan_Calibration_Flow] ====Done====
7223 09:31:11.281277
7224 09:31:11.283814 [DutyScan_Calibration_Flow] k_type=1
7225 09:31:11.300692
7226 09:31:11.300851 ==DQS 0 ==
7227 09:31:11.303963 Final DQS duty delay cell = 0
7228 09:31:11.307535 [0] MAX Duty = 5218%(X100), DQS PI = 22
7229 09:31:11.310410 [0] MIN Duty = 5062%(X100), DQS PI = 14
7230 09:31:11.313958 [0] AVG Duty = 5140%(X100)
7231 09:31:11.314057
7232 09:31:11.314154 ==DQS 1 ==
7233 09:31:11.317843 Final DQS duty delay cell = 0
7234 09:31:11.320511 [0] MAX Duty = 5187%(X100), DQS PI = 2
7235 09:31:11.323642 [0] MIN Duty = 4969%(X100), DQS PI = 58
7236 09:31:11.326926 [0] AVG Duty = 5078%(X100)
7237 09:31:11.327022
7238 09:31:11.330095 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7239 09:31:11.330176
7240 09:31:11.333453 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7241 09:31:11.337087 [DutyScan_Calibration_Flow] ====Done====
7242 09:31:11.337200
7243 09:31:11.340223 [DutyScan_Calibration_Flow] k_type=3
7244 09:31:11.358044
7245 09:31:11.358536 ==DQM 0 ==
7246 09:31:11.361556 Final DQM duty delay cell = 0
7247 09:31:11.364734 [0] MAX Duty = 5156%(X100), DQS PI = 22
7248 09:31:11.368239 [0] MIN Duty = 4875%(X100), DQS PI = 56
7249 09:31:11.371559 [0] AVG Duty = 5015%(X100)
7250 09:31:11.371977
7251 09:31:11.372310 ==DQM 1 ==
7252 09:31:11.374497 Final DQM duty delay cell = 0
7253 09:31:11.377956 [0] MAX Duty = 5000%(X100), DQS PI = 2
7254 09:31:11.381406 [0] MIN Duty = 4844%(X100), DQS PI = 14
7255 09:31:11.384569 [0] AVG Duty = 4922%(X100)
7256 09:31:11.384992
7257 09:31:11.387750 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7258 09:31:11.388326
7259 09:31:11.391017 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7260 09:31:11.394775 [DutyScan_Calibration_Flow] ====Done====
7261 09:31:11.395257
7262 09:31:11.397457 [DutyScan_Calibration_Flow] k_type=2
7263 09:31:11.415323
7264 09:31:11.415828 ==DQ 0 ==
7265 09:31:11.419329 Final DQ duty delay cell = 0
7266 09:31:11.422219 [0] MAX Duty = 5124%(X100), DQS PI = 20
7267 09:31:11.425189 [0] MIN Duty = 4938%(X100), DQS PI = 12
7268 09:31:11.428436 [0] AVG Duty = 5031%(X100)
7269 09:31:11.429005
7270 09:31:11.429517 ==DQ 1 ==
7271 09:31:11.431883 Final DQ duty delay cell = 0
7272 09:31:11.435064 [0] MAX Duty = 5187%(X100), DQS PI = 2
7273 09:31:11.438845 [0] MIN Duty = 4938%(X100), DQS PI = 12
7274 09:31:11.439309 [0] AVG Duty = 5062%(X100)
7275 09:31:11.442278
7276 09:31:11.445531 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7277 09:31:11.445949
7278 09:31:11.448871 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7279 09:31:11.451683 [DutyScan_Calibration_Flow] ====Done====
7280 09:31:11.452103 ==
7281 09:31:11.454506 Dram Type= 6, Freq= 0, CH_1, rank 0
7282 09:31:11.458190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 09:31:11.458780 ==
7284 09:31:11.461331 [Duty_Offset_Calibration]
7285 09:31:11.461955 B0:0 B1:-1 CA:3
7286 09:31:11.462420
7287 09:31:11.464517 [DutyScan_Calibration_Flow] k_type=0
7288 09:31:11.474906
7289 09:31:11.475608 ==CLK 0==
7290 09:31:11.478188 Final CLK duty delay cell = -4
7291 09:31:11.481815 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7292 09:31:11.484715 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7293 09:31:11.488005 [-4] AVG Duty = 4937%(X100)
7294 09:31:11.488645
7295 09:31:11.491883 CH1 CLK Duty spec in!! Max-Min= 187%
7296 09:31:11.494416 [DutyScan_Calibration_Flow] ====Done====
7297 09:31:11.494855
7298 09:31:11.497913 [DutyScan_Calibration_Flow] k_type=1
7299 09:31:11.514477
7300 09:31:11.514935 ==DQS 0 ==
7301 09:31:11.519360 Final DQS duty delay cell = 0
7302 09:31:11.520451 [0] MAX Duty = 5250%(X100), DQS PI = 28
7303 09:31:11.523760 [0] MIN Duty = 4907%(X100), DQS PI = 58
7304 09:31:11.527677 [0] AVG Duty = 5078%(X100)
7305 09:31:11.528238
7306 09:31:11.528578 ==DQS 1 ==
7307 09:31:11.530770 Final DQS duty delay cell = -4
7308 09:31:11.533855 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7309 09:31:11.537047 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7310 09:31:11.540089 [-4] AVG Duty = 4922%(X100)
7311 09:31:11.540533
7312 09:31:11.543469 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7313 09:31:11.543883
7314 09:31:11.547152 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7315 09:31:11.550396 [DutyScan_Calibration_Flow] ====Done====
7316 09:31:11.550811
7317 09:31:11.553532 [DutyScan_Calibration_Flow] k_type=3
7318 09:31:11.571664
7319 09:31:11.572075 ==DQM 0 ==
7320 09:31:11.574740 Final DQM duty delay cell = 0
7321 09:31:11.577877 [0] MAX Duty = 5062%(X100), DQS PI = 30
7322 09:31:11.581127 [0] MIN Duty = 4782%(X100), DQS PI = 40
7323 09:31:11.584753 [0] AVG Duty = 4922%(X100)
7324 09:31:11.585170
7325 09:31:11.585495 ==DQM 1 ==
7326 09:31:11.588002 Final DQM duty delay cell = 0
7327 09:31:11.592001 [0] MAX Duty = 5000%(X100), DQS PI = 32
7328 09:31:11.594148 [0] MIN Duty = 4813%(X100), DQS PI = 0
7329 09:31:11.597749 [0] AVG Duty = 4906%(X100)
7330 09:31:11.598268
7331 09:31:11.601245 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7332 09:31:11.601762
7333 09:31:11.604517 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7334 09:31:11.607702 [DutyScan_Calibration_Flow] ====Done====
7335 09:31:11.608142
7336 09:31:11.610672 [DutyScan_Calibration_Flow] k_type=2
7337 09:31:11.627961
7338 09:31:11.628517 ==DQ 0 ==
7339 09:31:11.631111 Final DQ duty delay cell = -4
7340 09:31:11.634239 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7341 09:31:11.637483 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7342 09:31:11.640656 [-4] AVG Duty = 4875%(X100)
7343 09:31:11.641188
7344 09:31:11.641554 ==DQ 1 ==
7345 09:31:11.643985 Final DQ duty delay cell = 0
7346 09:31:11.647204 [0] MAX Duty = 5031%(X100), DQS PI = 30
7347 09:31:11.650215 [0] MIN Duty = 4875%(X100), DQS PI = 0
7348 09:31:11.653784 [0] AVG Duty = 4953%(X100)
7349 09:31:11.654200
7350 09:31:11.657452 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7351 09:31:11.657865
7352 09:31:11.660371 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7353 09:31:11.663324 [DutyScan_Calibration_Flow] ====Done====
7354 09:31:11.666746 nWR fixed to 30
7355 09:31:11.669890 [ModeRegInit_LP4] CH0 RK0
7356 09:31:11.669971 [ModeRegInit_LP4] CH0 RK1
7357 09:31:11.672882 [ModeRegInit_LP4] CH1 RK0
7358 09:31:11.676681 [ModeRegInit_LP4] CH1 RK1
7359 09:31:11.676761 match AC timing 5
7360 09:31:11.683199 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7361 09:31:11.686279 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7362 09:31:11.689519 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7363 09:31:11.696530 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7364 09:31:11.699620 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7365 09:31:11.699793 [MiockJmeterHQA]
7366 09:31:11.702883
7367 09:31:11.703052 [DramcMiockJmeter] u1RxGatingPI = 0
7368 09:31:11.706400 0 : 4252, 4027
7369 09:31:11.706593 4 : 4252, 4026
7370 09:31:11.709529 8 : 4363, 4137
7371 09:31:11.709718 12 : 4253, 4026
7372 09:31:11.712668 16 : 4252, 4027
7373 09:31:11.712828 20 : 4362, 4137
7374 09:31:11.716793 24 : 4363, 4137
7375 09:31:11.716993 28 : 4253, 4027
7376 09:31:11.717110 32 : 4252, 4027
7377 09:31:11.719305 36 : 4252, 4027
7378 09:31:11.719510 40 : 4252, 4027
7379 09:31:11.722909 44 : 4255, 4029
7380 09:31:11.723100 48 : 4363, 4138
7381 09:31:11.725970 52 : 4250, 4026
7382 09:31:11.726153 56 : 4252, 4027
7383 09:31:11.729577 60 : 4249, 4027
7384 09:31:11.729823 64 : 4253, 4029
7385 09:31:11.730044 68 : 4250, 4027
7386 09:31:11.732535 72 : 4360, 4137
7387 09:31:11.732762 76 : 4361, 4137
7388 09:31:11.736183 80 : 4249, 4027
7389 09:31:11.736464 84 : 4250, 4026
7390 09:31:11.739516 88 : 4250, 4027
7391 09:31:11.739779 92 : 4249, 4027
7392 09:31:11.742353 96 : 4253, 3470
7393 09:31:11.742684 100 : 4360, 0
7394 09:31:11.743002 104 : 4250, 0
7395 09:31:11.746318 108 : 4363, 0
7396 09:31:11.746775 112 : 4361, 0
7397 09:31:11.747232 116 : 4360, 0
7398 09:31:11.749447 120 : 4252, 0
7399 09:31:11.749888 124 : 4250, 0
7400 09:31:11.752421 128 : 4249, 0
7401 09:31:11.752848 132 : 4250, 0
7402 09:31:11.753237 136 : 4252, 0
7403 09:31:11.755889 140 : 4249, 0
7404 09:31:11.756239 144 : 4253, 0
7405 09:31:11.758942 148 : 4250, 0
7406 09:31:11.759322 152 : 4249, 0
7407 09:31:11.759598 156 : 4252, 0
7408 09:31:11.762036 160 : 4363, 0
7409 09:31:11.762376 164 : 4361, 0
7410 09:31:11.765918 168 : 4363, 0
7411 09:31:11.766255 172 : 4253, 0
7412 09:31:11.766533 176 : 4252, 0
7413 09:31:11.769062 180 : 4249, 0
7414 09:31:11.769521 184 : 4252, 0
7415 09:31:11.772432 188 : 4252, 0
7416 09:31:11.772855 192 : 4250, 0
7417 09:31:11.773190 196 : 4252, 0
7418 09:31:11.775734 200 : 4252, 0
7419 09:31:11.776159 204 : 4249, 0
7420 09:31:11.778988 208 : 4252, 0
7421 09:31:11.779550 212 : 4363, 0
7422 09:31:11.779896 216 : 4250, 0
7423 09:31:11.782787 220 : 4360, 282
7424 09:31:11.783414 224 : 4249, 3843
7425 09:31:11.785232 228 : 4250, 4026
7426 09:31:11.785707 232 : 4253, 4029
7427 09:31:11.789005 236 : 4250, 4027
7428 09:31:11.789525 240 : 4249, 4027
7429 09:31:11.792190 244 : 4360, 4137
7430 09:31:11.792712 248 : 4250, 4026
7431 09:31:11.795579 252 : 4250, 4027
7432 09:31:11.796005 256 : 4360, 4138
7433 09:31:11.796343 260 : 4249, 4027
7434 09:31:11.799055 264 : 4250, 4026
7435 09:31:11.799609 268 : 4363, 4140
7436 09:31:11.801922 272 : 4250, 4027
7437 09:31:11.802344 276 : 4249, 4027
7438 09:31:11.805286 280 : 4250, 4026
7439 09:31:11.805781 284 : 4253, 4029
7440 09:31:11.808290 288 : 4250, 4027
7441 09:31:11.808957 292 : 4249, 4027
7442 09:31:11.812234 296 : 4360, 4137
7443 09:31:11.812749 300 : 4250, 4026
7444 09:31:11.815597 304 : 4250, 4027
7445 09:31:11.816195 308 : 4360, 4138
7446 09:31:11.818100 312 : 4249, 4027
7447 09:31:11.818556 316 : 4250, 4026
7448 09:31:11.821494 320 : 4363, 4140
7449 09:31:11.822029 324 : 4250, 4027
7450 09:31:11.822570 328 : 4252, 4027
7451 09:31:11.825051 332 : 4250, 4026
7452 09:31:11.825677 336 : 4253, 2316
7453 09:31:11.828150 340 : 4250, 45
7454 09:31:11.828854
7455 09:31:11.831989 MIOCK jitter meter ch=0
7456 09:31:11.832618
7457 09:31:11.833225 1T = (340-100) = 240 dly cells
7458 09:31:11.838274 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7459 09:31:11.838936 ==
7460 09:31:11.842020 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 09:31:11.844731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 09:31:11.848030 ==
7463 09:31:11.851703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 09:31:11.854342 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 09:31:11.861357 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 09:31:11.867490 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 09:31:11.875233 [CA 0] Center 44 (14~74) winsize 61
7468 09:31:11.879267 [CA 1] Center 43 (13~74) winsize 62
7469 09:31:11.881917 [CA 2] Center 38 (9~68) winsize 60
7470 09:31:11.884606 [CA 3] Center 38 (9~68) winsize 60
7471 09:31:11.888570 [CA 4] Center 36 (7~66) winsize 60
7472 09:31:11.891718 [CA 5] Center 36 (6~66) winsize 61
7473 09:31:11.892040
7474 09:31:11.894688 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 09:31:11.894990
7476 09:31:11.898449 [CATrainingPosCal] consider 1 rank data
7477 09:31:11.901534 u2DelayCellTimex100 = 271/100 ps
7478 09:31:11.907717 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7479 09:31:11.910933 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7480 09:31:11.914516 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7481 09:31:11.917893 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7482 09:31:11.921404 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7483 09:31:11.924522 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7484 09:31:11.924959
7485 09:31:11.928368 CA PerBit enable=1, Macro0, CA PI delay=36
7486 09:31:11.928892
7487 09:31:11.931431 [CBTSetCACLKResult] CA Dly = 36
7488 09:31:11.934539 CS Dly: 10 (0~41)
7489 09:31:11.937595 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 09:31:11.941908 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 09:31:11.942370 ==
7492 09:31:11.944691 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 09:31:11.951345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 09:31:11.951703 ==
7495 09:31:11.954061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 09:31:11.961464 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 09:31:11.963797 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 09:31:11.970588 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 09:31:11.978683 [CA 0] Center 44 (14~75) winsize 62
7500 09:31:11.981958 [CA 1] Center 44 (14~74) winsize 61
7501 09:31:11.985143 [CA 2] Center 39 (10~69) winsize 60
7502 09:31:11.988830 [CA 3] Center 39 (10~68) winsize 59
7503 09:31:11.991647 [CA 4] Center 37 (7~67) winsize 61
7504 09:31:11.995117 [CA 5] Center 36 (6~66) winsize 61
7505 09:31:11.995561
7506 09:31:11.998408 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 09:31:11.998908
7508 09:31:12.005184 [CATrainingPosCal] consider 2 rank data
7509 09:31:12.005682 u2DelayCellTimex100 = 271/100 ps
7510 09:31:12.011438 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7511 09:31:12.014994 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7512 09:31:12.018515 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7513 09:31:12.021477 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7514 09:31:12.025321 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7515 09:31:12.028237 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7516 09:31:12.028598
7517 09:31:12.031386 CA PerBit enable=1, Macro0, CA PI delay=36
7518 09:31:12.031741
7519 09:31:12.034685 [CBTSetCACLKResult] CA Dly = 36
7520 09:31:12.038430 CS Dly: 11 (0~44)
7521 09:31:12.042268 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 09:31:12.045311 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 09:31:12.045825
7524 09:31:12.047840 ----->DramcWriteLeveling(PI) begin...
7525 09:31:12.051492 ==
7526 09:31:12.054436 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 09:31:12.057959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 09:31:12.058475 ==
7529 09:31:12.061388 Write leveling (Byte 0): 34 => 34
7530 09:31:12.064323 Write leveling (Byte 1): 25 => 25
7531 09:31:12.067910 DramcWriteLeveling(PI) end<-----
7532 09:31:12.068384
7533 09:31:12.068768 ==
7534 09:31:12.071071 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 09:31:12.074074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 09:31:12.074484 ==
7537 09:31:12.077595 [Gating] SW mode calibration
7538 09:31:12.084149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 09:31:12.090473 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 09:31:12.094063 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 09:31:12.097560 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 09:31:12.103902 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 09:31:12.106977 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7544 09:31:12.110866 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7545 09:31:12.116911 1 4 20 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7546 09:31:12.120500 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 09:31:12.124119 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 09:31:12.130831 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 09:31:12.133501 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 09:31:12.137051 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 09:31:12.143488 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
7552 09:31:12.146646 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7553 09:31:12.150643 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7554 09:31:12.157290 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 09:31:12.160119 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 09:31:12.163289 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 09:31:12.169922 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 09:31:12.173516 1 6 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7559 09:31:12.176334 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7560 09:31:12.182887 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7561 09:31:12.186232 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
7562 09:31:12.190059 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 09:31:12.196555 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 09:31:12.199458 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 09:31:12.202852 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 09:31:12.209236 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 09:31:12.212983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7568 09:31:12.215849 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7569 09:31:12.222707 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 09:31:12.226200 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 09:31:12.229061 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 09:31:12.236275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 09:31:12.239058 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 09:31:12.242767 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 09:31:12.249255 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 09:31:12.251879 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 09:31:12.255322 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 09:31:12.262046 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 09:31:12.264745 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 09:31:12.268079 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 09:31:12.274798 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 09:31:12.278048 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 09:31:12.281090 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7584 09:31:12.284353 Total UI for P1: 0, mck2ui 16
7585 09:31:12.288096 best dqsien dly found for B0: ( 1, 9, 8)
7586 09:31:12.294967 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7587 09:31:12.297562 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 09:31:12.300979 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 09:31:12.304744 Total UI for P1: 0, mck2ui 16
7590 09:31:12.308086 best dqsien dly found for B1: ( 1, 9, 20)
7591 09:31:12.310857 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7592 09:31:12.314886 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 09:31:12.315352
7594 09:31:12.321467 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7595 09:31:12.324729 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 09:31:12.327558 [Gating] SW calibration Done
7597 09:31:12.327975 ==
7598 09:31:12.331433 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 09:31:12.334473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 09:31:12.334895 ==
7601 09:31:12.335276 RX Vref Scan: 0
7602 09:31:12.337401
7603 09:31:12.337816 RX Vref 0 -> 0, step: 1
7604 09:31:12.338246
7605 09:31:12.340725 RX Delay 0 -> 252, step: 8
7606 09:31:12.344089 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7607 09:31:12.347636 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7608 09:31:12.353870 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7609 09:31:12.357330 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7610 09:31:12.360380 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7611 09:31:12.363903 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7612 09:31:12.366873 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7613 09:31:12.373668 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7614 09:31:12.377367 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7615 09:31:12.380284 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7616 09:31:12.383416 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7617 09:31:12.387156 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7618 09:31:12.393599 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7619 09:31:12.397546 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7620 09:31:12.400035 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7621 09:31:12.403546 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7622 09:31:12.403967 ==
7623 09:31:12.406529 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 09:31:12.413232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 09:31:12.413657 ==
7626 09:31:12.413990 DQS Delay:
7627 09:31:12.416622 DQS0 = 0, DQS1 = 0
7628 09:31:12.417037 DQM Delay:
7629 09:31:12.420013 DQM0 = 131, DQM1 = 127
7630 09:31:12.420433 DQ Delay:
7631 09:31:12.423385 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7632 09:31:12.426356 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7633 09:31:12.430180 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7634 09:31:12.433169 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =131
7635 09:31:12.433562
7636 09:31:12.433885
7637 09:31:12.434188 ==
7638 09:31:12.436543 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 09:31:12.443022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 09:31:12.443492 ==
7641 09:31:12.443829
7642 09:31:12.444142
7643 09:31:12.444474 TX Vref Scan disable
7644 09:31:12.446620 == TX Byte 0 ==
7645 09:31:12.449959 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7646 09:31:12.456228 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7647 09:31:12.456645 == TX Byte 1 ==
7648 09:31:12.459927 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7649 09:31:12.466392 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7650 09:31:12.466974 ==
7651 09:31:12.469638 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 09:31:12.473120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 09:31:12.473628 ==
7654 09:31:12.487708
7655 09:31:12.490969 TX Vref early break, caculate TX vref
7656 09:31:12.494520 TX Vref=16, minBit 1, minWin=21, winSum=363
7657 09:31:12.497516 TX Vref=18, minBit 1, minWin=23, winSum=377
7658 09:31:12.500939 TX Vref=20, minBit 1, minWin=23, winSum=382
7659 09:31:12.504040 TX Vref=22, minBit 8, minWin=24, winSum=402
7660 09:31:12.507363 TX Vref=24, minBit 1, minWin=24, winSum=407
7661 09:31:12.514180 TX Vref=26, minBit 7, minWin=24, winSum=413
7662 09:31:12.517231 TX Vref=28, minBit 1, minWin=24, winSum=417
7663 09:31:12.520927 TX Vref=30, minBit 0, minWin=25, winSum=414
7664 09:31:12.523890 TX Vref=32, minBit 1, minWin=24, winSum=405
7665 09:31:12.527350 TX Vref=34, minBit 0, minWin=24, winSum=396
7666 09:31:12.533590 TX Vref=36, minBit 0, minWin=23, winSum=380
7667 09:31:12.537387 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 30
7668 09:31:12.537812
7669 09:31:12.540402 Final TX Range 0 Vref 30
7670 09:31:12.540823
7671 09:31:12.541150 ==
7672 09:31:12.543368 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 09:31:12.547138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 09:31:12.547626 ==
7675 09:31:12.550042
7676 09:31:12.550454
7677 09:31:12.550852 TX Vref Scan disable
7678 09:31:12.557452 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7679 09:31:12.557973 == TX Byte 0 ==
7680 09:31:12.560302 u2DelayCellOfst[0]=10 cells (3 PI)
7681 09:31:12.563719 u2DelayCellOfst[1]=18 cells (5 PI)
7682 09:31:12.567556 u2DelayCellOfst[2]=10 cells (3 PI)
7683 09:31:12.570699 u2DelayCellOfst[3]=10 cells (3 PI)
7684 09:31:12.573331 u2DelayCellOfst[4]=7 cells (2 PI)
7685 09:31:12.576443 u2DelayCellOfst[5]=0 cells (0 PI)
7686 09:31:12.579679 u2DelayCellOfst[6]=18 cells (5 PI)
7687 09:31:12.583694 u2DelayCellOfst[7]=18 cells (5 PI)
7688 09:31:12.586534 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7689 09:31:12.590105 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7690 09:31:12.593450 == TX Byte 1 ==
7691 09:31:12.596444 u2DelayCellOfst[8]=0 cells (0 PI)
7692 09:31:12.599855 u2DelayCellOfst[9]=0 cells (0 PI)
7693 09:31:12.603117 u2DelayCellOfst[10]=3 cells (1 PI)
7694 09:31:12.606195 u2DelayCellOfst[11]=0 cells (0 PI)
7695 09:31:12.609904 u2DelayCellOfst[12]=7 cells (2 PI)
7696 09:31:12.613031 u2DelayCellOfst[13]=7 cells (2 PI)
7697 09:31:12.613466 u2DelayCellOfst[14]=14 cells (4 PI)
7698 09:31:12.616089 u2DelayCellOfst[15]=10 cells (3 PI)
7699 09:31:12.623188 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7700 09:31:12.626276 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7701 09:31:12.629574 DramC Write-DBI on
7702 09:31:12.629994 ==
7703 09:31:12.633191 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 09:31:12.636543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 09:31:12.636967 ==
7706 09:31:12.637299
7707 09:31:12.637607
7708 09:31:12.639443 TX Vref Scan disable
7709 09:31:12.639893 == TX Byte 0 ==
7710 09:31:12.646468 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7711 09:31:12.646897 == TX Byte 1 ==
7712 09:31:12.649548 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7713 09:31:12.652779 DramC Write-DBI off
7714 09:31:12.653196
7715 09:31:12.653589 [DATLAT]
7716 09:31:12.656315 Freq=1600, CH0 RK0
7717 09:31:12.656736
7718 09:31:12.657068 DATLAT Default: 0xf
7719 09:31:12.659269 0, 0xFFFF, sum = 0
7720 09:31:12.659740 1, 0xFFFF, sum = 0
7721 09:31:12.663191 2, 0xFFFF, sum = 0
7722 09:31:12.666389 3, 0xFFFF, sum = 0
7723 09:31:12.666915 4, 0xFFFF, sum = 0
7724 09:31:12.669579 5, 0xFFFF, sum = 0
7725 09:31:12.670155 6, 0xFFFF, sum = 0
7726 09:31:12.672495 7, 0xFFFF, sum = 0
7727 09:31:12.672920 8, 0xFFFF, sum = 0
7728 09:31:12.675953 9, 0xFFFF, sum = 0
7729 09:31:12.676377 10, 0xFFFF, sum = 0
7730 09:31:12.678789 11, 0xFFFF, sum = 0
7731 09:31:12.678872 12, 0xFFFF, sum = 0
7732 09:31:12.682211 13, 0xFFFF, sum = 0
7733 09:31:12.682293 14, 0x0, sum = 1
7734 09:31:12.685087 15, 0x0, sum = 2
7735 09:31:12.685170 16, 0x0, sum = 3
7736 09:31:12.688361 17, 0x0, sum = 4
7737 09:31:12.688443 best_step = 15
7738 09:31:12.688507
7739 09:31:12.688566 ==
7740 09:31:12.691924 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 09:31:12.698292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 09:31:12.698375 ==
7743 09:31:12.698439 RX Vref Scan: 1
7744 09:31:12.698499
7745 09:31:12.702196 Set Vref Range= 24 -> 127
7746 09:31:12.702277
7747 09:31:12.705322 RX Vref 24 -> 127, step: 1
7748 09:31:12.705403
7749 09:31:12.705467 RX Delay 19 -> 252, step: 4
7750 09:31:12.705527
7751 09:31:12.708349 Set Vref, RX VrefLevel [Byte0]: 24
7752 09:31:12.711713 [Byte1]: 24
7753 09:31:12.715595
7754 09:31:12.715677 Set Vref, RX VrefLevel [Byte0]: 25
7755 09:31:12.719049 [Byte1]: 25
7756 09:31:12.723851
7757 09:31:12.723938 Set Vref, RX VrefLevel [Byte0]: 26
7758 09:31:12.726867 [Byte1]: 26
7759 09:31:12.730869
7760 09:31:12.730963 Set Vref, RX VrefLevel [Byte0]: 27
7761 09:31:12.734169 [Byte1]: 27
7762 09:31:12.738772
7763 09:31:12.738882 Set Vref, RX VrefLevel [Byte0]: 28
7764 09:31:12.741706 [Byte1]: 28
7765 09:31:12.745853
7766 09:31:12.745978 Set Vref, RX VrefLevel [Byte0]: 29
7767 09:31:12.749406 [Byte1]: 29
7768 09:31:12.753722
7769 09:31:12.753871 Set Vref, RX VrefLevel [Byte0]: 30
7770 09:31:12.757062 [Byte1]: 30
7771 09:31:12.761196
7772 09:31:12.761366 Set Vref, RX VrefLevel [Byte0]: 31
7773 09:31:12.764543 [Byte1]: 31
7774 09:31:12.768883
7775 09:31:12.769120 Set Vref, RX VrefLevel [Byte0]: 32
7776 09:31:12.771906 [Byte1]: 32
7777 09:31:12.776433
7778 09:31:12.776837 Set Vref, RX VrefLevel [Byte0]: 33
7779 09:31:12.779779 [Byte1]: 33
7780 09:31:12.783977
7781 09:31:12.784393 Set Vref, RX VrefLevel [Byte0]: 34
7782 09:31:12.787241 [Byte1]: 34
7783 09:31:12.791205
7784 09:31:12.791282 Set Vref, RX VrefLevel [Byte0]: 35
7785 09:31:12.794572 [Byte1]: 35
7786 09:31:12.799290
7787 09:31:12.799371 Set Vref, RX VrefLevel [Byte0]: 36
7788 09:31:12.802078 [Byte1]: 36
7789 09:31:12.806580
7790 09:31:12.806661 Set Vref, RX VrefLevel [Byte0]: 37
7791 09:31:12.809477 [Byte1]: 37
7792 09:31:12.813865
7793 09:31:12.813947 Set Vref, RX VrefLevel [Byte0]: 38
7794 09:31:12.817386 [Byte1]: 38
7795 09:31:12.821607
7796 09:31:12.821688 Set Vref, RX VrefLevel [Byte0]: 39
7797 09:31:12.824927 [Byte1]: 39
7798 09:31:12.829763
7799 09:31:12.829843 Set Vref, RX VrefLevel [Byte0]: 40
7800 09:31:12.832981 [Byte1]: 40
7801 09:31:12.837122
7802 09:31:12.837284 Set Vref, RX VrefLevel [Byte0]: 41
7803 09:31:12.840361 [Byte1]: 41
7804 09:31:12.844411
7805 09:31:12.844590 Set Vref, RX VrefLevel [Byte0]: 42
7806 09:31:12.847783 [Byte1]: 42
7807 09:31:12.852013
7808 09:31:12.852200 Set Vref, RX VrefLevel [Byte0]: 43
7809 09:31:12.855255 [Byte1]: 43
7810 09:31:12.859523
7811 09:31:12.859677 Set Vref, RX VrefLevel [Byte0]: 44
7812 09:31:12.862911 [Byte1]: 44
7813 09:31:12.866990
7814 09:31:12.867070 Set Vref, RX VrefLevel [Byte0]: 45
7815 09:31:12.870360 [Byte1]: 45
7816 09:31:12.874810
7817 09:31:12.874891 Set Vref, RX VrefLevel [Byte0]: 46
7818 09:31:12.878228 [Byte1]: 46
7819 09:31:12.882451
7820 09:31:12.882531 Set Vref, RX VrefLevel [Byte0]: 47
7821 09:31:12.885312 [Byte1]: 47
7822 09:31:12.889847
7823 09:31:12.889927 Set Vref, RX VrefLevel [Byte0]: 48
7824 09:31:12.893722 [Byte1]: 48
7825 09:31:12.898074
7826 09:31:12.898154 Set Vref, RX VrefLevel [Byte0]: 49
7827 09:31:12.900932 [Byte1]: 49
7828 09:31:12.905390
7829 09:31:12.905474 Set Vref, RX VrefLevel [Byte0]: 50
7830 09:31:12.908320 [Byte1]: 50
7831 09:31:12.912804
7832 09:31:12.912885 Set Vref, RX VrefLevel [Byte0]: 51
7833 09:31:12.915886 [Byte1]: 51
7834 09:31:12.920588
7835 09:31:12.920669 Set Vref, RX VrefLevel [Byte0]: 52
7836 09:31:12.924197 [Byte1]: 52
7837 09:31:12.927487
7838 09:31:12.927567 Set Vref, RX VrefLevel [Byte0]: 53
7839 09:31:12.930810 [Byte1]: 53
7840 09:31:12.935455
7841 09:31:12.935535 Set Vref, RX VrefLevel [Byte0]: 54
7842 09:31:12.938420 [Byte1]: 54
7843 09:31:12.942940
7844 09:31:12.943021 Set Vref, RX VrefLevel [Byte0]: 55
7845 09:31:12.945917 [Byte1]: 55
7846 09:31:12.950748
7847 09:31:12.950828 Set Vref, RX VrefLevel [Byte0]: 56
7848 09:31:12.954058 [Byte1]: 56
7849 09:31:12.957891
7850 09:31:12.957971 Set Vref, RX VrefLevel [Byte0]: 57
7851 09:31:12.961873 [Byte1]: 57
7852 09:31:12.966564
7853 09:31:12.966645 Set Vref, RX VrefLevel [Byte0]: 58
7854 09:31:12.968891 [Byte1]: 58
7855 09:31:12.972846
7856 09:31:12.972938 Set Vref, RX VrefLevel [Byte0]: 59
7857 09:31:12.976388 [Byte1]: 59
7858 09:31:12.981192
7859 09:31:12.981299 Set Vref, RX VrefLevel [Byte0]: 60
7860 09:31:12.984183 [Byte1]: 60
7861 09:31:12.988069
7862 09:31:12.988171 Set Vref, RX VrefLevel [Byte0]: 61
7863 09:31:12.991466 [Byte1]: 61
7864 09:31:12.995629
7865 09:31:12.995709 Set Vref, RX VrefLevel [Byte0]: 62
7866 09:31:12.999028 [Byte1]: 62
7867 09:31:13.004180
7868 09:31:13.004258 Set Vref, RX VrefLevel [Byte0]: 63
7869 09:31:13.006775 [Byte1]: 63
7870 09:31:13.011137
7871 09:31:13.011234 Set Vref, RX VrefLevel [Byte0]: 64
7872 09:31:13.014034 [Byte1]: 64
7873 09:31:13.018664
7874 09:31:13.018737 Set Vref, RX VrefLevel [Byte0]: 65
7875 09:31:13.021662 [Byte1]: 65
7876 09:31:13.025891
7877 09:31:13.025992 Set Vref, RX VrefLevel [Byte0]: 66
7878 09:31:13.029375 [Byte1]: 66
7879 09:31:13.033486
7880 09:31:13.033561 Set Vref, RX VrefLevel [Byte0]: 67
7881 09:31:13.036875 [Byte1]: 67
7882 09:31:13.041292
7883 09:31:13.041398 Set Vref, RX VrefLevel [Byte0]: 68
7884 09:31:13.044672 [Byte1]: 68
7885 09:31:13.049077
7886 09:31:13.049164 Set Vref, RX VrefLevel [Byte0]: 69
7887 09:31:13.052546 [Byte1]: 69
7888 09:31:13.056826
7889 09:31:13.056923 Set Vref, RX VrefLevel [Byte0]: 70
7890 09:31:13.059741 [Byte1]: 70
7891 09:31:13.064457
7892 09:31:13.064570 Set Vref, RX VrefLevel [Byte0]: 71
7893 09:31:13.067419 [Byte1]: 71
7894 09:31:13.071478
7895 09:31:13.071598 Set Vref, RX VrefLevel [Byte0]: 72
7896 09:31:13.074965 [Byte1]: 72
7897 09:31:13.079802
7898 09:31:13.079952 Set Vref, RX VrefLevel [Byte0]: 73
7899 09:31:13.083062 [Byte1]: 73
7900 09:31:13.086953
7901 09:31:13.087140 Final RX Vref Byte 0 = 63 to rank0
7902 09:31:13.090478 Final RX Vref Byte 1 = 60 to rank0
7903 09:31:13.093814 Final RX Vref Byte 0 = 63 to rank1
7904 09:31:13.096622 Final RX Vref Byte 1 = 60 to rank1==
7905 09:31:13.100066 Dram Type= 6, Freq= 0, CH_0, rank 0
7906 09:31:13.106817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7907 09:31:13.107261 ==
7908 09:31:13.107577 DQS Delay:
7909 09:31:13.110068 DQS0 = 0, DQS1 = 0
7910 09:31:13.110486 DQM Delay:
7911 09:31:13.113491 DQM0 = 130, DQM1 = 123
7912 09:31:13.113909 DQ Delay:
7913 09:31:13.116605 DQ0 =132, DQ1 =132, DQ2 =126, DQ3 =126
7914 09:31:13.119603 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
7915 09:31:13.123522 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7916 09:31:13.126868 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =132
7917 09:31:13.127333
7918 09:31:13.127667
7919 09:31:13.127976
7920 09:31:13.129545 [DramC_TX_OE_Calibration] TA2
7921 09:31:13.132855 Original DQ_B0 (3 6) =30, OEN = 27
7922 09:31:13.136454 Original DQ_B1 (3 6) =30, OEN = 27
7923 09:31:13.139466 24, 0x0, End_B0=24 End_B1=24
7924 09:31:13.142948 25, 0x0, End_B0=25 End_B1=25
7925 09:31:13.143413 26, 0x0, End_B0=26 End_B1=26
7926 09:31:13.146037 27, 0x0, End_B0=27 End_B1=27
7927 09:31:13.149563 28, 0x0, End_B0=28 End_B1=28
7928 09:31:13.152799 29, 0x0, End_B0=29 End_B1=29
7929 09:31:13.153223 30, 0x0, End_B0=30 End_B1=30
7930 09:31:13.156098 31, 0x4545, End_B0=30 End_B1=30
7931 09:31:13.159402 Byte0 end_step=30 best_step=27
7932 09:31:13.162906 Byte1 end_step=30 best_step=27
7933 09:31:13.165873 Byte0 TX OE(2T, 0.5T) = (3, 3)
7934 09:31:13.169385 Byte1 TX OE(2T, 0.5T) = (3, 3)
7935 09:31:13.169801
7936 09:31:13.170129
7937 09:31:13.175773 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7938 09:31:13.178975 CH0 RK0: MR19=303, MR18=1815
7939 09:31:13.186044 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7940 09:31:13.186501
7941 09:31:13.188992 ----->DramcWriteLeveling(PI) begin...
7942 09:31:13.189416 ==
7943 09:31:13.192289 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 09:31:13.195612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 09:31:13.198907 ==
7946 09:31:13.199364 Write leveling (Byte 0): 34 => 34
7947 09:31:13.201876 Write leveling (Byte 1): 26 => 26
7948 09:31:13.205397 DramcWriteLeveling(PI) end<-----
7949 09:31:13.205812
7950 09:31:13.206147 ==
7951 09:31:13.208532 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 09:31:13.216187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 09:31:13.216610 ==
7954 09:31:13.218185 [Gating] SW mode calibration
7955 09:31:13.225017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7956 09:31:13.228309 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7957 09:31:13.234761 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 09:31:13.238838 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7959 09:31:13.241521 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 09:31:13.248623 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7961 09:31:13.251712 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7962 09:31:13.254382 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7963 09:31:13.261252 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 09:31:13.264414 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 09:31:13.268001 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7966 09:31:13.275130 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7967 09:31:13.277923 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7968 09:31:13.280895 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7969 09:31:13.287609 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7970 09:31:13.290629 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7971 09:31:13.293937 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7972 09:31:13.300567 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 09:31:13.304080 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 09:31:13.307194 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 09:31:13.313905 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7976 09:31:13.317325 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7977 09:31:13.320777 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7978 09:31:13.327107 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7979 09:31:13.330532 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 09:31:13.333859 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 09:31:13.340335 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 09:31:13.343753 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7983 09:31:13.346923 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7984 09:31:13.353983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7985 09:31:13.356754 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7986 09:31:13.360829 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7987 09:31:13.367011 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7988 09:31:13.370368 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 09:31:13.373443 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 09:31:13.380385 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 09:31:13.383541 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 09:31:13.386823 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 09:31:13.393019 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 09:31:13.396023 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 09:31:13.399438 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 09:31:13.406013 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 09:31:13.409667 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 09:31:13.412988 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 09:31:13.419382 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8000 09:31:13.419806 Total UI for P1: 0, mck2ui 16
8001 09:31:13.425702 best dqsien dly found for B0: ( 1, 9, 6)
8002 09:31:13.429368 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8003 09:31:13.432074 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8004 09:31:13.438910 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8005 09:31:13.442141 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 09:31:13.445504 Total UI for P1: 0, mck2ui 16
8007 09:31:13.448600 best dqsien dly found for B1: ( 1, 9, 18)
8008 09:31:13.452199 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8009 09:31:13.455137 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8010 09:31:13.455561
8011 09:31:13.459433 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8012 09:31:13.462068 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8013 09:31:13.465395 [Gating] SW calibration Done
8014 09:31:13.465812 ==
8015 09:31:13.468413 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 09:31:13.475199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 09:31:13.475618 ==
8018 09:31:13.475946 RX Vref Scan: 0
8019 09:31:13.476256
8020 09:31:13.478827 RX Vref 0 -> 0, step: 1
8021 09:31:13.479273
8022 09:31:13.481829 RX Delay 0 -> 252, step: 8
8023 09:31:13.485330 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8024 09:31:13.488234 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8025 09:31:13.491698 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8026 09:31:13.494875 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8027 09:31:13.501672 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8028 09:31:13.504954 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8029 09:31:13.507899 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8030 09:31:13.511433 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8031 09:31:13.514862 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8032 09:31:13.520798 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8033 09:31:13.524491 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8034 09:31:13.527481 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8035 09:31:13.531397 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8036 09:31:13.537398 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8037 09:31:13.541007 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8038 09:31:13.544105 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8039 09:31:13.544522 ==
8040 09:31:13.547860 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 09:31:13.551259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 09:31:13.554744 ==
8043 09:31:13.555197 DQS Delay:
8044 09:31:13.555533 DQS0 = 0, DQS1 = 0
8045 09:31:13.558046 DQM Delay:
8046 09:31:13.558556 DQM0 = 132, DQM1 = 127
8047 09:31:13.560677 DQ Delay:
8048 09:31:13.564128 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =131
8049 09:31:13.566953 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
8050 09:31:13.570633 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8051 09:31:13.573804 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8052 09:31:13.574313
8053 09:31:13.574643
8054 09:31:13.574947 ==
8055 09:31:13.577020 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 09:31:13.580367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 09:31:13.580883 ==
8058 09:31:13.584011
8059 09:31:13.584544
8060 09:31:13.584871 TX Vref Scan disable
8061 09:31:13.586862 == TX Byte 0 ==
8062 09:31:13.590317 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8063 09:31:13.593408 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8064 09:31:13.596935 == TX Byte 1 ==
8065 09:31:13.600581 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8066 09:31:13.603981 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8067 09:31:13.604398 ==
8068 09:31:13.606412 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 09:31:13.613029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 09:31:13.613735 ==
8071 09:31:13.627551
8072 09:31:13.630810 TX Vref early break, caculate TX vref
8073 09:31:13.634027 TX Vref=16, minBit 2, minWin=23, winSum=380
8074 09:31:13.636933 TX Vref=18, minBit 8, minWin=23, winSum=387
8075 09:31:13.640190 TX Vref=20, minBit 2, minWin=24, winSum=399
8076 09:31:13.643379 TX Vref=22, minBit 1, minWin=25, winSum=404
8077 09:31:13.646893 TX Vref=24, minBit 1, minWin=25, winSum=410
8078 09:31:13.653602 TX Vref=26, minBit 1, minWin=25, winSum=416
8079 09:31:13.657017 TX Vref=28, minBit 4, minWin=25, winSum=417
8080 09:31:13.660185 TX Vref=30, minBit 1, minWin=25, winSum=412
8081 09:31:13.663062 TX Vref=32, minBit 1, minWin=24, winSum=406
8082 09:31:13.666404 TX Vref=34, minBit 0, minWin=24, winSum=398
8083 09:31:13.670169 TX Vref=36, minBit 8, minWin=23, winSum=392
8084 09:31:13.676773 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
8085 09:31:13.676854
8086 09:31:13.679515 Final TX Range 0 Vref 28
8087 09:31:13.679595
8088 09:31:13.679658 ==
8089 09:31:13.682899 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 09:31:13.686685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 09:31:13.686766 ==
8092 09:31:13.689818
8093 09:31:13.689897
8094 09:31:13.689960 TX Vref Scan disable
8095 09:31:13.696025 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8096 09:31:13.696105 == TX Byte 0 ==
8097 09:31:13.699615 u2DelayCellOfst[0]=10 cells (3 PI)
8098 09:31:13.702461 u2DelayCellOfst[1]=14 cells (4 PI)
8099 09:31:13.705943 u2DelayCellOfst[2]=7 cells (2 PI)
8100 09:31:13.709291 u2DelayCellOfst[3]=10 cells (3 PI)
8101 09:31:13.712373 u2DelayCellOfst[4]=7 cells (2 PI)
8102 09:31:13.715942 u2DelayCellOfst[5]=0 cells (0 PI)
8103 09:31:13.718913 u2DelayCellOfst[6]=14 cells (4 PI)
8104 09:31:13.722173 u2DelayCellOfst[7]=14 cells (4 PI)
8105 09:31:13.725337 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8106 09:31:13.728615 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8107 09:31:13.731774 == TX Byte 1 ==
8108 09:31:13.735309 u2DelayCellOfst[8]=0 cells (0 PI)
8109 09:31:13.738808 u2DelayCellOfst[9]=0 cells (0 PI)
8110 09:31:13.741883 u2DelayCellOfst[10]=3 cells (1 PI)
8111 09:31:13.745034 u2DelayCellOfst[11]=3 cells (1 PI)
8112 09:31:13.748464 u2DelayCellOfst[12]=10 cells (3 PI)
8113 09:31:13.751630 u2DelayCellOfst[13]=10 cells (3 PI)
8114 09:31:13.754935 u2DelayCellOfst[14]=18 cells (5 PI)
8115 09:31:13.758542 u2DelayCellOfst[15]=10 cells (3 PI)
8116 09:31:13.761844 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8117 09:31:13.765174 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8118 09:31:13.768321 DramC Write-DBI on
8119 09:31:13.768402 ==
8120 09:31:13.771705 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 09:31:13.774970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 09:31:13.775055 ==
8123 09:31:13.775126
8124 09:31:13.775186
8125 09:31:13.778434 TX Vref Scan disable
8126 09:31:13.781508 == TX Byte 0 ==
8127 09:31:13.784545 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8128 09:31:13.784626 == TX Byte 1 ==
8129 09:31:13.791062 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8130 09:31:13.791150 DramC Write-DBI off
8131 09:31:13.791214
8132 09:31:13.791274 [DATLAT]
8133 09:31:13.794754 Freq=1600, CH0 RK1
8134 09:31:13.794835
8135 09:31:13.797811 DATLAT Default: 0xf
8136 09:31:13.797892 0, 0xFFFF, sum = 0
8137 09:31:13.801070 1, 0xFFFF, sum = 0
8138 09:31:13.801152 2, 0xFFFF, sum = 0
8139 09:31:13.804722 3, 0xFFFF, sum = 0
8140 09:31:13.804804 4, 0xFFFF, sum = 0
8141 09:31:13.808683 5, 0xFFFF, sum = 0
8142 09:31:13.808765 6, 0xFFFF, sum = 0
8143 09:31:13.810834 7, 0xFFFF, sum = 0
8144 09:31:13.810915 8, 0xFFFF, sum = 0
8145 09:31:13.814086 9, 0xFFFF, sum = 0
8146 09:31:13.814169 10, 0xFFFF, sum = 0
8147 09:31:13.817787 11, 0xFFFF, sum = 0
8148 09:31:13.817871 12, 0xFFFF, sum = 0
8149 09:31:13.821068 13, 0xFFFF, sum = 0
8150 09:31:13.821150 14, 0x0, sum = 1
8151 09:31:13.824254 15, 0x0, sum = 2
8152 09:31:13.824337 16, 0x0, sum = 3
8153 09:31:13.827622 17, 0x0, sum = 4
8154 09:31:13.827704 best_step = 15
8155 09:31:13.827767
8156 09:31:13.827826 ==
8157 09:31:13.831028 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 09:31:13.836993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 09:31:13.837076 ==
8160 09:31:13.837141 RX Vref Scan: 0
8161 09:31:13.837201
8162 09:31:13.840544 RX Vref 0 -> 0, step: 1
8163 09:31:13.840624
8164 09:31:13.843894 RX Delay 11 -> 252, step: 4
8165 09:31:13.847463 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8166 09:31:13.850506 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8167 09:31:13.857050 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8168 09:31:13.860157 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8169 09:31:13.863484 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8170 09:31:13.867193 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8171 09:31:13.870870 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8172 09:31:13.876929 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8173 09:31:13.880126 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8174 09:31:13.883536 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8175 09:31:13.886690 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8176 09:31:13.889851 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8177 09:31:13.896478 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8178 09:31:13.900116 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8179 09:31:13.902878 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8180 09:31:13.906507 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8181 09:31:13.909606 ==
8182 09:31:13.909687 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 09:31:13.916109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 09:31:13.916203 ==
8185 09:31:13.916269 DQS Delay:
8186 09:31:13.919810 DQS0 = 0, DQS1 = 0
8187 09:31:13.919891 DQM Delay:
8188 09:31:13.923243 DQM0 = 128, DQM1 = 123
8189 09:31:13.923324 DQ Delay:
8190 09:31:13.925938 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8191 09:31:13.929229 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =136
8192 09:31:13.933044 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8193 09:31:13.936188 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8194 09:31:13.936279
8195 09:31:13.936344
8196 09:31:13.936403
8197 09:31:13.939279 [DramC_TX_OE_Calibration] TA2
8198 09:31:13.942322 Original DQ_B0 (3 6) =30, OEN = 27
8199 09:31:13.945733 Original DQ_B1 (3 6) =30, OEN = 27
8200 09:31:13.949178 24, 0x0, End_B0=24 End_B1=24
8201 09:31:13.953025 25, 0x0, End_B0=25 End_B1=25
8202 09:31:13.953107 26, 0x0, End_B0=26 End_B1=26
8203 09:31:13.955696 27, 0x0, End_B0=27 End_B1=27
8204 09:31:13.959333 28, 0x0, End_B0=28 End_B1=28
8205 09:31:13.962030 29, 0x0, End_B0=29 End_B1=29
8206 09:31:13.965683 30, 0x0, End_B0=30 End_B1=30
8207 09:31:13.965766 31, 0x4141, End_B0=30 End_B1=30
8208 09:31:13.968528 Byte0 end_step=30 best_step=27
8209 09:31:13.972272 Byte1 end_step=30 best_step=27
8210 09:31:13.975696 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 09:31:13.978568 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 09:31:13.978649
8213 09:31:13.978712
8214 09:31:13.985423 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8215 09:31:13.988460 CH0 RK1: MR19=303, MR18=110F
8216 09:31:13.994908 CH0_RK1: MR19=0x303, MR18=0x110F, DQSOSC=401, MR23=63, INC=22, DEC=15
8217 09:31:13.998715 [RxdqsGatingPostProcess] freq 1600
8218 09:31:14.005073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 09:31:14.008298 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 09:31:14.011881 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 09:31:14.011962 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 09:31:14.014978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 09:31:14.018234 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 09:31:14.021839 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 09:31:14.024753 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 09:31:14.028624 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 09:31:14.032154 Pre-setting of DQS Precalculation
8228 09:31:14.038029 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 09:31:14.038111 ==
8230 09:31:14.041035 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 09:31:14.044440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 09:31:14.044523 ==
8233 09:31:14.051016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 09:31:14.054344 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 09:31:14.057801 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 09:31:14.064509 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 09:31:14.073762 [CA 0] Center 42 (12~72) winsize 61
8238 09:31:14.076584 [CA 1] Center 42 (13~72) winsize 60
8239 09:31:14.079632 [CA 2] Center 38 (9~67) winsize 59
8240 09:31:14.083277 [CA 3] Center 37 (8~66) winsize 59
8241 09:31:14.087403 [CA 4] Center 37 (8~67) winsize 60
8242 09:31:14.089616 [CA 5] Center 36 (7~66) winsize 60
8243 09:31:14.089833
8244 09:31:14.092865 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 09:31:14.093066
8246 09:31:14.096191 [CATrainingPosCal] consider 1 rank data
8247 09:31:14.099869 u2DelayCellTimex100 = 271/100 ps
8248 09:31:14.106639 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8249 09:31:14.109802 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8250 09:31:14.112815 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8251 09:31:14.116573 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8252 09:31:14.119146 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8253 09:31:14.123625 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8254 09:31:14.124044
8255 09:31:14.126397 CA PerBit enable=1, Macro0, CA PI delay=36
8256 09:31:14.126813
8257 09:31:14.129140 [CBTSetCACLKResult] CA Dly = 36
8258 09:31:14.132742 CS Dly: 8 (0~39)
8259 09:31:14.136256 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 09:31:14.139670 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 09:31:14.140087 ==
8262 09:31:14.142494 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 09:31:14.149235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 09:31:14.149658 ==
8265 09:31:14.152476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 09:31:14.159132 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 09:31:14.162445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 09:31:14.168622 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 09:31:14.179533 [CA 0] Center 42 (12~72) winsize 61
8270 09:31:14.179952 [CA 1] Center 42 (13~72) winsize 60
8271 09:31:14.183193 [CA 2] Center 38 (8~68) winsize 61
8272 09:31:14.186345 [CA 3] Center 37 (7~67) winsize 61
8273 09:31:14.189799 [CA 4] Center 37 (8~67) winsize 60
8274 09:31:14.192625 [CA 5] Center 37 (7~67) winsize 61
8275 09:31:14.193041
8276 09:31:14.196544 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 09:31:14.197030
8278 09:31:14.202705 [CATrainingPosCal] consider 2 rank data
8279 09:31:14.203250 u2DelayCellTimex100 = 271/100 ps
8280 09:31:14.210591 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8281 09:31:14.212622 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8282 09:31:14.215939 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8283 09:31:14.218965 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8284 09:31:14.222397 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 09:31:14.225933 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 09:31:14.226355
8287 09:31:14.228767 CA PerBit enable=1, Macro0, CA PI delay=36
8288 09:31:14.229186
8289 09:31:14.232411 [CBTSetCACLKResult] CA Dly = 36
8290 09:31:14.235746 CS Dly: 10 (0~43)
8291 09:31:14.239174 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 09:31:14.241971 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 09:31:14.242518
8294 09:31:14.245553 ----->DramcWriteLeveling(PI) begin...
8295 09:31:14.248651 ==
8296 09:31:14.249108 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 09:31:14.255366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 09:31:14.255785 ==
8299 09:31:14.258404 Write leveling (Byte 0): 24 => 24
8300 09:31:14.262017 Write leveling (Byte 1): 27 => 27
8301 09:31:14.264913 DramcWriteLeveling(PI) end<-----
8302 09:31:14.264994
8303 09:31:14.265057 ==
8304 09:31:14.268134 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 09:31:14.272096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 09:31:14.272189 ==
8307 09:31:14.274768 [Gating] SW mode calibration
8308 09:31:14.281522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 09:31:14.287721 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 09:31:14.291157 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 09:31:14.294722 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 09:31:14.301139 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 09:31:14.304347 1 4 12 | B1->B0 | 2424 3434 | 1 1 | (1 1) (0 0)
8314 09:31:14.308237 1 4 16 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8315 09:31:14.314367 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 09:31:14.317473 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 09:31:14.320999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 09:31:14.327161 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 09:31:14.330661 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 09:31:14.334319 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8321 09:31:14.340991 1 5 12 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 1)
8322 09:31:14.344222 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8323 09:31:14.347517 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 09:31:14.354154 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 09:31:14.357394 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 09:31:14.361247 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 09:31:14.367010 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 09:31:14.370506 1 6 8 | B1->B0 | 2626 3030 | 0 0 | (0 0) (1 1)
8329 09:31:14.374078 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8330 09:31:14.380211 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 09:31:14.383765 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 09:31:14.387163 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 09:31:14.393687 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 09:31:14.396648 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 09:31:14.400703 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 09:31:14.406488 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 09:31:14.409923 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8338 09:31:14.413192 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8339 09:31:14.419877 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 09:31:14.423136 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 09:31:14.426263 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 09:31:14.432670 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 09:31:14.436228 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 09:31:14.439120 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 09:31:14.446158 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 09:31:14.449279 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 09:31:14.453139 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 09:31:14.459318 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 09:31:14.463027 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 09:31:14.465493 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 09:31:14.472510 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 09:31:14.475841 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 09:31:14.478647 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 09:31:14.485572 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8355 09:31:14.488902 Total UI for P1: 0, mck2ui 16
8356 09:31:14.492475 best dqsien dly found for B0: ( 1, 9, 12)
8357 09:31:14.495402 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 09:31:14.498208 Total UI for P1: 0, mck2ui 16
8359 09:31:14.502001 best dqsien dly found for B1: ( 1, 9, 14)
8360 09:31:14.505592 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8361 09:31:14.508503 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8362 09:31:14.508975
8363 09:31:14.511527 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8364 09:31:14.518285 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8365 09:31:14.518798 [Gating] SW calibration Done
8366 09:31:14.519230 ==
8367 09:31:14.521791 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 09:31:14.528208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 09:31:14.528697 ==
8370 09:31:14.529053 RX Vref Scan: 0
8371 09:31:14.529406
8372 09:31:14.531371 RX Vref 0 -> 0, step: 1
8373 09:31:14.531779
8374 09:31:14.534917 RX Delay 0 -> 252, step: 8
8375 09:31:14.538584 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8376 09:31:14.541526 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8377 09:31:14.544894 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8378 09:31:14.551462 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8379 09:31:14.554557 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8380 09:31:14.557982 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8381 09:31:14.560902 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8382 09:31:14.565237 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8383 09:31:14.570836 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8384 09:31:14.574738 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8385 09:31:14.577960 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8386 09:31:14.581005 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8387 09:31:14.587982 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8388 09:31:14.591052 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8389 09:31:14.594174 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8390 09:31:14.597553 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8391 09:31:14.597962 ==
8392 09:31:14.600552 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 09:31:14.607401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 09:31:14.608004 ==
8395 09:31:14.608350 DQS Delay:
8396 09:31:14.608659 DQS0 = 0, DQS1 = 0
8397 09:31:14.610518 DQM Delay:
8398 09:31:14.610924 DQM0 = 135, DQM1 = 131
8399 09:31:14.613705 DQ Delay:
8400 09:31:14.617854 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8401 09:31:14.620544 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8402 09:31:14.623500 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8403 09:31:14.626775 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8404 09:31:14.627229
8405 09:31:14.627558
8406 09:31:14.627861 ==
8407 09:31:14.630053 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 09:31:14.633332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 09:31:14.636668 ==
8410 09:31:14.637168
8411 09:31:14.637774
8412 09:31:14.638165 TX Vref Scan disable
8413 09:31:14.639949 == TX Byte 0 ==
8414 09:31:14.643254 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8415 09:31:14.646570 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8416 09:31:14.650246 == TX Byte 1 ==
8417 09:31:14.653371 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8418 09:31:14.656424 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8419 09:31:14.659889 ==
8420 09:31:14.663362 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 09:31:14.666224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 09:31:14.666792 ==
8423 09:31:14.679785
8424 09:31:14.683157 TX Vref early break, caculate TX vref
8425 09:31:14.686562 TX Vref=16, minBit 8, minWin=21, winSum=366
8426 09:31:14.689537 TX Vref=18, minBit 9, minWin=21, winSum=376
8427 09:31:14.693176 TX Vref=20, minBit 6, minWin=23, winSum=384
8428 09:31:14.696459 TX Vref=22, minBit 1, minWin=24, winSum=396
8429 09:31:14.699499 TX Vref=24, minBit 8, minWin=24, winSum=402
8430 09:31:14.705968 TX Vref=26, minBit 3, minWin=25, winSum=411
8431 09:31:14.709482 TX Vref=28, minBit 0, minWin=25, winSum=415
8432 09:31:14.713066 TX Vref=30, minBit 0, minWin=25, winSum=416
8433 09:31:14.716000 TX Vref=32, minBit 9, minWin=24, winSum=405
8434 09:31:14.719044 TX Vref=34, minBit 0, minWin=23, winSum=395
8435 09:31:14.726124 TX Vref=36, minBit 0, minWin=23, winSum=384
8436 09:31:14.728906 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
8437 09:31:14.729324
8438 09:31:14.732659 Final TX Range 0 Vref 30
8439 09:31:14.733075
8440 09:31:14.733401 ==
8441 09:31:14.735772 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 09:31:14.739209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 09:31:14.742506 ==
8444 09:31:14.742917
8445 09:31:14.743279
8446 09:31:14.743585 TX Vref Scan disable
8447 09:31:14.749387 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8448 09:31:14.749801 == TX Byte 0 ==
8449 09:31:14.752399 u2DelayCellOfst[0]=18 cells (5 PI)
8450 09:31:14.755612 u2DelayCellOfst[1]=14 cells (4 PI)
8451 09:31:14.759137 u2DelayCellOfst[2]=0 cells (0 PI)
8452 09:31:14.762531 u2DelayCellOfst[3]=7 cells (2 PI)
8453 09:31:14.765479 u2DelayCellOfst[4]=10 cells (3 PI)
8454 09:31:14.768753 u2DelayCellOfst[5]=18 cells (5 PI)
8455 09:31:14.772376 u2DelayCellOfst[6]=18 cells (5 PI)
8456 09:31:14.775541 u2DelayCellOfst[7]=7 cells (2 PI)
8457 09:31:14.778624 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8458 09:31:14.782732 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8459 09:31:14.785143 == TX Byte 1 ==
8460 09:31:14.788513 u2DelayCellOfst[8]=0 cells (0 PI)
8461 09:31:14.792674 u2DelayCellOfst[9]=3 cells (1 PI)
8462 09:31:14.795228 u2DelayCellOfst[10]=14 cells (4 PI)
8463 09:31:14.798574 u2DelayCellOfst[11]=7 cells (2 PI)
8464 09:31:14.801905 u2DelayCellOfst[12]=14 cells (4 PI)
8465 09:31:14.804896 u2DelayCellOfst[13]=18 cells (5 PI)
8466 09:31:14.808461 u2DelayCellOfst[14]=18 cells (5 PI)
8467 09:31:14.811544 u2DelayCellOfst[15]=18 cells (5 PI)
8468 09:31:14.815207 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8469 09:31:14.818053 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 09:31:14.821354 DramC Write-DBI on
8471 09:31:14.821895 ==
8472 09:31:14.824896 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 09:31:14.827968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 09:31:14.828385 ==
8475 09:31:14.828711
8476 09:31:14.829011
8477 09:31:14.831444 TX Vref Scan disable
8478 09:31:14.831858 == TX Byte 0 ==
8479 09:31:14.837749 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8480 09:31:14.838160 == TX Byte 1 ==
8481 09:31:14.844721 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8482 09:31:14.845137 DramC Write-DBI off
8483 09:31:14.845463
8484 09:31:14.845766 [DATLAT]
8485 09:31:14.847746 Freq=1600, CH1 RK0
8486 09:31:14.848159
8487 09:31:14.848486 DATLAT Default: 0xf
8488 09:31:14.851070 0, 0xFFFF, sum = 0
8489 09:31:14.854340 1, 0xFFFF, sum = 0
8490 09:31:14.854760 2, 0xFFFF, sum = 0
8491 09:31:14.857560 3, 0xFFFF, sum = 0
8492 09:31:14.857981 4, 0xFFFF, sum = 0
8493 09:31:14.860882 5, 0xFFFF, sum = 0
8494 09:31:14.861302 6, 0xFFFF, sum = 0
8495 09:31:14.864435 7, 0xFFFF, sum = 0
8496 09:31:14.864857 8, 0xFFFF, sum = 0
8497 09:31:14.867749 9, 0xFFFF, sum = 0
8498 09:31:14.868166 10, 0xFFFF, sum = 0
8499 09:31:14.870913 11, 0xFFFF, sum = 0
8500 09:31:14.871364 12, 0xFFFF, sum = 0
8501 09:31:14.874802 13, 0xFFFF, sum = 0
8502 09:31:14.875252 14, 0x0, sum = 1
8503 09:31:14.877474 15, 0x0, sum = 2
8504 09:31:14.877906 16, 0x0, sum = 3
8505 09:31:14.880775 17, 0x0, sum = 4
8506 09:31:14.881194 best_step = 15
8507 09:31:14.881523
8508 09:31:14.881826 ==
8509 09:31:14.884040 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 09:31:14.890710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 09:31:14.891146 ==
8512 09:31:14.891479 RX Vref Scan: 1
8513 09:31:14.891787
8514 09:31:14.893990 Set Vref Range= 24 -> 127
8515 09:31:14.894401
8516 09:31:14.897306 RX Vref 24 -> 127, step: 1
8517 09:31:14.897716
8518 09:31:14.900325 RX Delay 19 -> 252, step: 4
8519 09:31:14.900753
8520 09:31:14.904111 Set Vref, RX VrefLevel [Byte0]: 24
8521 09:31:14.907127 [Byte1]: 24
8522 09:31:14.907543
8523 09:31:14.910334 Set Vref, RX VrefLevel [Byte0]: 25
8524 09:31:14.913920 [Byte1]: 25
8525 09:31:14.914333
8526 09:31:14.916899 Set Vref, RX VrefLevel [Byte0]: 26
8527 09:31:14.920749 [Byte1]: 26
8528 09:31:14.921199
8529 09:31:14.923469 Set Vref, RX VrefLevel [Byte0]: 27
8530 09:31:14.927182 [Byte1]: 27
8531 09:31:14.930853
8532 09:31:14.931306 Set Vref, RX VrefLevel [Byte0]: 28
8533 09:31:14.933952 [Byte1]: 28
8534 09:31:14.938483
8535 09:31:14.938889 Set Vref, RX VrefLevel [Byte0]: 29
8536 09:31:14.942423 [Byte1]: 29
8537 09:31:14.946076
8538 09:31:14.946561 Set Vref, RX VrefLevel [Byte0]: 30
8539 09:31:14.949350 [Byte1]: 30
8540 09:31:14.953873
8541 09:31:14.954278 Set Vref, RX VrefLevel [Byte0]: 31
8542 09:31:14.957025 [Byte1]: 31
8543 09:31:14.960959
8544 09:31:14.961364 Set Vref, RX VrefLevel [Byte0]: 32
8545 09:31:14.964173 [Byte1]: 32
8546 09:31:14.968712
8547 09:31:14.969393 Set Vref, RX VrefLevel [Byte0]: 33
8548 09:31:14.971849 [Byte1]: 33
8549 09:31:14.976807
8550 09:31:14.977212 Set Vref, RX VrefLevel [Byte0]: 34
8551 09:31:14.979451 [Byte1]: 34
8552 09:31:14.984099
8553 09:31:14.984505 Set Vref, RX VrefLevel [Byte0]: 35
8554 09:31:14.987291 [Byte1]: 35
8555 09:31:14.991458
8556 09:31:14.991908 Set Vref, RX VrefLevel [Byte0]: 36
8557 09:31:14.994882 [Byte1]: 36
8558 09:31:14.999611
8559 09:31:15.000020 Set Vref, RX VrefLevel [Byte0]: 37
8560 09:31:15.002037 [Byte1]: 37
8561 09:31:15.006871
8562 09:31:15.007314 Set Vref, RX VrefLevel [Byte0]: 38
8563 09:31:15.009825 [Byte1]: 38
8564 09:31:15.014425
8565 09:31:15.014834 Set Vref, RX VrefLevel [Byte0]: 39
8566 09:31:15.017835 [Byte1]: 39
8567 09:31:15.021667
8568 09:31:15.022078 Set Vref, RX VrefLevel [Byte0]: 40
8569 09:31:15.024878 [Byte1]: 40
8570 09:31:15.029274
8571 09:31:15.029682 Set Vref, RX VrefLevel [Byte0]: 41
8572 09:31:15.032383 [Byte1]: 41
8573 09:31:15.036782
8574 09:31:15.037287 Set Vref, RX VrefLevel [Byte0]: 42
8575 09:31:15.040220 [Byte1]: 42
8576 09:31:15.045268
8577 09:31:15.045678 Set Vref, RX VrefLevel [Byte0]: 43
8578 09:31:15.047587 [Byte1]: 43
8579 09:31:15.052469
8580 09:31:15.052883 Set Vref, RX VrefLevel [Byte0]: 44
8581 09:31:15.055438 [Byte1]: 44
8582 09:31:15.060134
8583 09:31:15.060559 Set Vref, RX VrefLevel [Byte0]: 45
8584 09:31:15.063003 [Byte1]: 45
8585 09:31:15.067035
8586 09:31:15.067482 Set Vref, RX VrefLevel [Byte0]: 46
8587 09:31:15.070672 [Byte1]: 46
8588 09:31:15.074546
8589 09:31:15.074976 Set Vref, RX VrefLevel [Byte0]: 47
8590 09:31:15.078364 [Byte1]: 47
8591 09:31:15.082429
8592 09:31:15.082922 Set Vref, RX VrefLevel [Byte0]: 48
8593 09:31:15.086269 [Byte1]: 48
8594 09:31:15.090119
8595 09:31:15.090524 Set Vref, RX VrefLevel [Byte0]: 49
8596 09:31:15.093064 [Byte1]: 49
8597 09:31:15.097272
8598 09:31:15.097680 Set Vref, RX VrefLevel [Byte0]: 50
8599 09:31:15.101113 [Byte1]: 50
8600 09:31:15.104935
8601 09:31:15.105341 Set Vref, RX VrefLevel [Byte0]: 51
8602 09:31:15.108322 [Byte1]: 51
8603 09:31:15.112588
8604 09:31:15.112995 Set Vref, RX VrefLevel [Byte0]: 52
8605 09:31:15.116245 [Byte1]: 52
8606 09:31:15.120018
8607 09:31:15.120425 Set Vref, RX VrefLevel [Byte0]: 53
8608 09:31:15.123591 [Byte1]: 53
8609 09:31:15.128287
8610 09:31:15.128844 Set Vref, RX VrefLevel [Byte0]: 54
8611 09:31:15.131610 [Byte1]: 54
8612 09:31:15.135224
8613 09:31:15.135774 Set Vref, RX VrefLevel [Byte0]: 55
8614 09:31:15.138784 [Byte1]: 55
8615 09:31:15.143026
8616 09:31:15.143522 Set Vref, RX VrefLevel [Byte0]: 56
8617 09:31:15.146899 [Byte1]: 56
8618 09:31:15.150803
8619 09:31:15.151262 Set Vref, RX VrefLevel [Byte0]: 57
8620 09:31:15.153754 [Byte1]: 57
8621 09:31:15.158067
8622 09:31:15.158619 Set Vref, RX VrefLevel [Byte0]: 58
8623 09:31:15.161262 [Byte1]: 58
8624 09:31:15.165897
8625 09:31:15.166351 Set Vref, RX VrefLevel [Byte0]: 59
8626 09:31:15.169145 [Byte1]: 59
8627 09:31:15.173820
8628 09:31:15.174387 Set Vref, RX VrefLevel [Byte0]: 60
8629 09:31:15.176224 [Byte1]: 60
8630 09:31:15.180770
8631 09:31:15.181197 Set Vref, RX VrefLevel [Byte0]: 61
8632 09:31:15.184367 [Byte1]: 61
8633 09:31:15.188339
8634 09:31:15.188745 Set Vref, RX VrefLevel [Byte0]: 62
8635 09:31:15.191657 [Byte1]: 62
8636 09:31:15.195830
8637 09:31:15.196290 Set Vref, RX VrefLevel [Byte0]: 63
8638 09:31:15.199023 [Byte1]: 63
8639 09:31:15.203416
8640 09:31:15.203832 Set Vref, RX VrefLevel [Byte0]: 64
8641 09:31:15.207112 [Byte1]: 64
8642 09:31:15.211126
8643 09:31:15.211595 Set Vref, RX VrefLevel [Byte0]: 65
8644 09:31:15.214292 [Byte1]: 65
8645 09:31:15.218893
8646 09:31:15.219519 Set Vref, RX VrefLevel [Byte0]: 66
8647 09:31:15.222310 [Byte1]: 66
8648 09:31:15.226567
8649 09:31:15.227040 Set Vref, RX VrefLevel [Byte0]: 67
8650 09:31:15.229371 [Byte1]: 67
8651 09:31:15.233707
8652 09:31:15.234174 Set Vref, RX VrefLevel [Byte0]: 68
8653 09:31:15.237493 [Byte1]: 68
8654 09:31:15.241770
8655 09:31:15.242192 Set Vref, RX VrefLevel [Byte0]: 69
8656 09:31:15.244557 [Byte1]: 69
8657 09:31:15.249106
8658 09:31:15.249579 Set Vref, RX VrefLevel [Byte0]: 70
8659 09:31:15.252610 [Byte1]: 70
8660 09:31:15.256777
8661 09:31:15.257242 Set Vref, RX VrefLevel [Byte0]: 71
8662 09:31:15.259876 [Byte1]: 71
8663 09:31:15.264044
8664 09:31:15.264514 Final RX Vref Byte 0 = 55 to rank0
8665 09:31:15.267696 Final RX Vref Byte 1 = 55 to rank0
8666 09:31:15.271175 Final RX Vref Byte 0 = 55 to rank1
8667 09:31:15.274988 Final RX Vref Byte 1 = 55 to rank1==
8668 09:31:15.277853 Dram Type= 6, Freq= 0, CH_1, rank 0
8669 09:31:15.284007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8670 09:31:15.284428 ==
8671 09:31:15.284819 DQS Delay:
8672 09:31:15.286887 DQS0 = 0, DQS1 = 0
8673 09:31:15.287435 DQM Delay:
8674 09:31:15.287879 DQM0 = 133, DQM1 = 130
8675 09:31:15.290574 DQ Delay:
8676 09:31:15.293460 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8677 09:31:15.296864 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =126
8678 09:31:15.300447 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8679 09:31:15.303545 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8680 09:31:15.303964
8681 09:31:15.304311
8682 09:31:15.304617
8683 09:31:15.306823 [DramC_TX_OE_Calibration] TA2
8684 09:31:15.310289 Original DQ_B0 (3 6) =30, OEN = 27
8685 09:31:15.313399 Original DQ_B1 (3 6) =30, OEN = 27
8686 09:31:15.316582 24, 0x0, End_B0=24 End_B1=24
8687 09:31:15.319838 25, 0x0, End_B0=25 End_B1=25
8688 09:31:15.320476 26, 0x0, End_B0=26 End_B1=26
8689 09:31:15.323232 27, 0x0, End_B0=27 End_B1=27
8690 09:31:15.326895 28, 0x0, End_B0=28 End_B1=28
8691 09:31:15.329863 29, 0x0, End_B0=29 End_B1=29
8692 09:31:15.332877 30, 0x0, End_B0=30 End_B1=30
8693 09:31:15.333314 31, 0x5151, End_B0=30 End_B1=30
8694 09:31:15.336362 Byte0 end_step=30 best_step=27
8695 09:31:15.339430 Byte1 end_step=30 best_step=27
8696 09:31:15.343167 Byte0 TX OE(2T, 0.5T) = (3, 3)
8697 09:31:15.346312 Byte1 TX OE(2T, 0.5T) = (3, 3)
8698 09:31:15.346730
8699 09:31:15.347155
8700 09:31:15.352620 [DQSOSCAuto] RK0, (LSB)MR18= 0xb14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8701 09:31:15.356108 CH1 RK0: MR19=303, MR18=B14
8702 09:31:15.362820 CH1_RK0: MR19=0x303, MR18=0xB14, DQSOSC=399, MR23=63, INC=23, DEC=15
8703 09:31:15.363374
8704 09:31:15.365641 ----->DramcWriteLeveling(PI) begin...
8705 09:31:15.366119 ==
8706 09:31:15.369092 Dram Type= 6, Freq= 0, CH_1, rank 1
8707 09:31:15.372051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8708 09:31:15.372589 ==
8709 09:31:15.375931 Write leveling (Byte 0): 24 => 24
8710 09:31:15.378954 Write leveling (Byte 1): 26 => 26
8711 09:31:15.382639 DramcWriteLeveling(PI) end<-----
8712 09:31:15.383159
8713 09:31:15.383551 ==
8714 09:31:15.385426 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 09:31:15.392525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 09:31:15.392945 ==
8717 09:31:15.393277 [Gating] SW mode calibration
8718 09:31:15.401842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8719 09:31:15.405747 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8720 09:31:15.412035 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8721 09:31:15.415255 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8722 09:31:15.418650 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8723 09:31:15.425135 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8724 09:31:15.428526 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 09:31:15.431805 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 09:31:15.438139 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 09:31:15.441656 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 09:31:15.444457 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8729 09:31:15.451354 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 09:31:15.454912 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8731 09:31:15.458087 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8732 09:31:15.465115 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8733 09:31:15.468111 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 09:31:15.471187 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 09:31:15.477463 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 09:31:15.481119 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 09:31:15.484166 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8738 09:31:15.490690 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8739 09:31:15.494686 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8740 09:31:15.497154 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 09:31:15.503916 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 09:31:15.507010 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 09:31:15.510714 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 09:31:15.517270 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8745 09:31:15.520224 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 09:31:15.523919 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8747 09:31:15.530312 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8748 09:31:15.533401 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8749 09:31:15.536781 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 09:31:15.543244 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 09:31:15.546103 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 09:31:15.549445 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 09:31:15.556283 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 09:31:15.559733 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 09:31:15.562959 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 09:31:15.569671 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 09:31:15.572514 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 09:31:15.576084 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 09:31:15.582617 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 09:31:15.585901 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 09:31:15.589402 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8762 09:31:15.595786 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8763 09:31:15.599935 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8764 09:31:15.602460 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8765 09:31:15.605917 Total UI for P1: 0, mck2ui 16
8766 09:31:15.609699 best dqsien dly found for B0: ( 1, 9, 8)
8767 09:31:15.615761 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 09:31:15.616174 Total UI for P1: 0, mck2ui 16
8769 09:31:15.622499 best dqsien dly found for B1: ( 1, 9, 14)
8770 09:31:15.625809 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8771 09:31:15.629127 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8772 09:31:15.629543
8773 09:31:15.632566 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8774 09:31:15.635632 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8775 09:31:15.639048 [Gating] SW calibration Done
8776 09:31:15.639514 ==
8777 09:31:15.642755 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 09:31:15.645317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 09:31:15.645736 ==
8780 09:31:15.649076 RX Vref Scan: 0
8781 09:31:15.649533
8782 09:31:15.649869 RX Vref 0 -> 0, step: 1
8783 09:31:15.652015
8784 09:31:15.652447 RX Delay 0 -> 252, step: 8
8785 09:31:15.658163 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8786 09:31:15.661998 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8787 09:31:15.664949 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8788 09:31:15.668289 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8789 09:31:15.671203 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8790 09:31:15.678213 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8791 09:31:15.681085 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8792 09:31:15.684768 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8793 09:31:15.687567 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8794 09:31:15.691064 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8795 09:31:15.697632 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8796 09:31:15.701137 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8797 09:31:15.704061 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8798 09:31:15.707694 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8799 09:31:15.713867 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8800 09:31:15.717347 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8801 09:31:15.717784 ==
8802 09:31:15.720841 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 09:31:15.724508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 09:31:15.725141 ==
8805 09:31:15.727533 DQS Delay:
8806 09:31:15.727998 DQS0 = 0, DQS1 = 0
8807 09:31:15.728501 DQM Delay:
8808 09:31:15.730321 DQM0 = 136, DQM1 = 130
8809 09:31:15.730738 DQ Delay:
8810 09:31:15.733834 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8811 09:31:15.737032 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8812 09:31:15.743898 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8813 09:31:15.746600 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8814 09:31:15.747185
8815 09:31:15.747532
8816 09:31:15.747852 ==
8817 09:31:15.750233 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 09:31:15.753286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 09:31:15.753814 ==
8820 09:31:15.754337
8821 09:31:15.754694
8822 09:31:15.756926 TX Vref Scan disable
8823 09:31:15.760180 == TX Byte 0 ==
8824 09:31:15.763582 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8825 09:31:15.766317 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8826 09:31:15.769889 == TX Byte 1 ==
8827 09:31:15.773103 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8828 09:31:15.776722 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8829 09:31:15.776970 ==
8830 09:31:15.779859 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 09:31:15.783550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 09:31:15.786529 ==
8833 09:31:15.799931
8834 09:31:15.802711 TX Vref early break, caculate TX vref
8835 09:31:15.805823 TX Vref=16, minBit 9, minWin=22, winSum=378
8836 09:31:15.809729 TX Vref=18, minBit 9, minWin=21, winSum=385
8837 09:31:15.812744 TX Vref=20, minBit 9, minWin=22, winSum=391
8838 09:31:15.816141 TX Vref=22, minBit 5, minWin=24, winSum=398
8839 09:31:15.819020 TX Vref=24, minBit 9, minWin=24, winSum=407
8840 09:31:15.825795 TX Vref=26, minBit 1, minWin=25, winSum=412
8841 09:31:15.829326 TX Vref=28, minBit 5, minWin=25, winSum=418
8842 09:31:15.832235 TX Vref=30, minBit 8, minWin=24, winSum=413
8843 09:31:15.835394 TX Vref=32, minBit 8, minWin=24, winSum=409
8844 09:31:15.839688 TX Vref=34, minBit 9, minWin=23, winSum=403
8845 09:31:15.845812 TX Vref=36, minBit 8, minWin=23, winSum=399
8846 09:31:15.849516 TX Vref=38, minBit 8, minWin=22, winSum=386
8847 09:31:15.855911 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 28
8848 09:31:15.856360
8849 09:31:15.856819 Final TX Range 0 Vref 28
8850 09:31:15.857184
8851 09:31:15.857493 ==
8852 09:31:15.858764 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 09:31:15.865106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 09:31:15.865523 ==
8855 09:31:15.865851
8856 09:31:15.866156
8857 09:31:15.866448 TX Vref Scan disable
8858 09:31:15.873036 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8859 09:31:15.873462 == TX Byte 0 ==
8860 09:31:15.876049 u2DelayCellOfst[0]=14 cells (4 PI)
8861 09:31:15.879246 u2DelayCellOfst[1]=10 cells (3 PI)
8862 09:31:15.882979 u2DelayCellOfst[2]=0 cells (0 PI)
8863 09:31:15.885925 u2DelayCellOfst[3]=7 cells (2 PI)
8864 09:31:15.889500 u2DelayCellOfst[4]=7 cells (2 PI)
8865 09:31:15.892542 u2DelayCellOfst[5]=14 cells (4 PI)
8866 09:31:15.896043 u2DelayCellOfst[6]=14 cells (4 PI)
8867 09:31:15.899108 u2DelayCellOfst[7]=7 cells (2 PI)
8868 09:31:15.902983 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8869 09:31:15.905751 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8870 09:31:15.909358 == TX Byte 1 ==
8871 09:31:15.912018 u2DelayCellOfst[8]=0 cells (0 PI)
8872 09:31:15.915672 u2DelayCellOfst[9]=0 cells (0 PI)
8873 09:31:15.918510 u2DelayCellOfst[10]=10 cells (3 PI)
8874 09:31:15.921991 u2DelayCellOfst[11]=7 cells (2 PI)
8875 09:31:15.925708 u2DelayCellOfst[12]=14 cells (4 PI)
8876 09:31:15.928839 u2DelayCellOfst[13]=14 cells (4 PI)
8877 09:31:15.932342 u2DelayCellOfst[14]=18 cells (5 PI)
8878 09:31:15.932759 u2DelayCellOfst[15]=18 cells (5 PI)
8879 09:31:15.938925 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8880 09:31:15.942408 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8881 09:31:15.945385 DramC Write-DBI on
8882 09:31:15.945797 ==
8883 09:31:15.949099 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 09:31:15.951944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 09:31:15.952359 ==
8886 09:31:15.952701
8887 09:31:15.953128
8888 09:31:15.955041 TX Vref Scan disable
8889 09:31:15.955660 == TX Byte 0 ==
8890 09:31:15.961990 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8891 09:31:15.962531 == TX Byte 1 ==
8892 09:31:15.966034 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8893 09:31:15.968650 DramC Write-DBI off
8894 09:31:15.969078
8895 09:31:15.969408 [DATLAT]
8896 09:31:15.972112 Freq=1600, CH1 RK1
8897 09:31:15.972529
8898 09:31:15.972858 DATLAT Default: 0xf
8899 09:31:15.975668 0, 0xFFFF, sum = 0
8900 09:31:15.976093 1, 0xFFFF, sum = 0
8901 09:31:15.978824 2, 0xFFFF, sum = 0
8902 09:31:15.981438 3, 0xFFFF, sum = 0
8903 09:31:15.981857 4, 0xFFFF, sum = 0
8904 09:31:15.985287 5, 0xFFFF, sum = 0
8905 09:31:15.985784 6, 0xFFFF, sum = 0
8906 09:31:15.988214 7, 0xFFFF, sum = 0
8907 09:31:15.988645 8, 0xFFFF, sum = 0
8908 09:31:15.991338 9, 0xFFFF, sum = 0
8909 09:31:15.991890 10, 0xFFFF, sum = 0
8910 09:31:15.994614 11, 0xFFFF, sum = 0
8911 09:31:15.995013 12, 0xFFFF, sum = 0
8912 09:31:15.998361 13, 0xFFFF, sum = 0
8913 09:31:15.998758 14, 0x0, sum = 1
8914 09:31:16.001567 15, 0x0, sum = 2
8915 09:31:16.001965 16, 0x0, sum = 3
8916 09:31:16.006072 17, 0x0, sum = 4
8917 09:31:16.006555 best_step = 15
8918 09:31:16.006951
8919 09:31:16.007400 ==
8920 09:31:16.008130 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 09:31:16.014675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 09:31:16.015144 ==
8923 09:31:16.015587 RX Vref Scan: 0
8924 09:31:16.016005
8925 09:31:16.017700 RX Vref 0 -> 0, step: 1
8926 09:31:16.018126
8927 09:31:16.020740 RX Delay 11 -> 252, step: 4
8928 09:31:16.024380 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8929 09:31:16.027760 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8930 09:31:16.031344 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8931 09:31:16.037480 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8932 09:31:16.040795 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8933 09:31:16.044446 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8934 09:31:16.047188 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8935 09:31:16.054013 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8936 09:31:16.057016 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8937 09:31:16.060413 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8938 09:31:16.063882 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8939 09:31:16.067177 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8940 09:31:16.074319 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8941 09:31:16.077023 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8942 09:31:16.080340 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8943 09:31:16.083763 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8944 09:31:16.084190 ==
8945 09:31:16.087029 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 09:31:16.093788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 09:31:16.094198 ==
8948 09:31:16.094523 DQS Delay:
8949 09:31:16.096862 DQS0 = 0, DQS1 = 0
8950 09:31:16.097272 DQM Delay:
8951 09:31:16.097632 DQM0 = 132, DQM1 = 127
8952 09:31:16.100024 DQ Delay:
8953 09:31:16.103567 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8954 09:31:16.106738 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =128
8955 09:31:16.110064 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
8956 09:31:16.113409 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
8957 09:31:16.113846
8958 09:31:16.114172
8959 09:31:16.114471
8960 09:31:16.117039 [DramC_TX_OE_Calibration] TA2
8961 09:31:16.119662 Original DQ_B0 (3 6) =30, OEN = 27
8962 09:31:16.122829 Original DQ_B1 (3 6) =30, OEN = 27
8963 09:31:16.126549 24, 0x0, End_B0=24 End_B1=24
8964 09:31:16.129708 25, 0x0, End_B0=25 End_B1=25
8965 09:31:16.130268 26, 0x0, End_B0=26 End_B1=26
8966 09:31:16.132619 27, 0x0, End_B0=27 End_B1=27
8967 09:31:16.135897 28, 0x0, End_B0=28 End_B1=28
8968 09:31:16.139190 29, 0x0, End_B0=29 End_B1=29
8969 09:31:16.142894 30, 0x0, End_B0=30 End_B1=30
8970 09:31:16.143436 31, 0x4141, End_B0=30 End_B1=30
8971 09:31:16.145777 Byte0 end_step=30 best_step=27
8972 09:31:16.149902 Byte1 end_step=30 best_step=27
8973 09:31:16.152633 Byte0 TX OE(2T, 0.5T) = (3, 3)
8974 09:31:16.156337 Byte1 TX OE(2T, 0.5T) = (3, 3)
8975 09:31:16.156758
8976 09:31:16.157162
8977 09:31:16.162320 [DQSOSCAuto] RK1, (LSB)MR18= 0xa19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 404 ps
8978 09:31:16.166208 CH1 RK1: MR19=303, MR18=A19
8979 09:31:16.172102 CH1_RK1: MR19=0x303, MR18=0xA19, DQSOSC=397, MR23=63, INC=23, DEC=15
8980 09:31:16.175948 [RxdqsGatingPostProcess] freq 1600
8981 09:31:16.182122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8982 09:31:16.182534 best DQS0 dly(2T, 0.5T) = (1, 1)
8983 09:31:16.185596 best DQS1 dly(2T, 0.5T) = (1, 1)
8984 09:31:16.188780 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8985 09:31:16.192261 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8986 09:31:16.195337 best DQS0 dly(2T, 0.5T) = (1, 1)
8987 09:31:16.198818 best DQS1 dly(2T, 0.5T) = (1, 1)
8988 09:31:16.202416 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8989 09:31:16.205242 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8990 09:31:16.208731 Pre-setting of DQS Precalculation
8991 09:31:16.211987 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8992 09:31:16.221487 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8993 09:31:16.228636 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8994 09:31:16.229051
8995 09:31:16.229372
8996 09:31:16.231861 [Calibration Summary] 3200 Mbps
8997 09:31:16.232455 CH 0, Rank 0
8998 09:31:16.235105 SW Impedance : PASS
8999 09:31:16.238110 DUTY Scan : NO K
9000 09:31:16.238521 ZQ Calibration : PASS
9001 09:31:16.241482 Jitter Meter : NO K
9002 09:31:16.241891 CBT Training : PASS
9003 09:31:16.244653 Write leveling : PASS
9004 09:31:16.248127 RX DQS gating : PASS
9005 09:31:16.248545 RX DQ/DQS(RDDQC) : PASS
9006 09:31:16.251126 TX DQ/DQS : PASS
9007 09:31:16.254400 RX DATLAT : PASS
9008 09:31:16.254908 RX DQ/DQS(Engine): PASS
9009 09:31:16.257710 TX OE : PASS
9010 09:31:16.258303 All Pass.
9011 09:31:16.258654
9012 09:31:16.261036 CH 0, Rank 1
9013 09:31:16.261444 SW Impedance : PASS
9014 09:31:16.264356 DUTY Scan : NO K
9015 09:31:16.268026 ZQ Calibration : PASS
9016 09:31:16.268576 Jitter Meter : NO K
9017 09:31:16.270651 CBT Training : PASS
9018 09:31:16.274441 Write leveling : PASS
9019 09:31:16.274849 RX DQS gating : PASS
9020 09:31:16.277625 RX DQ/DQS(RDDQC) : PASS
9021 09:31:16.281141 TX DQ/DQS : PASS
9022 09:31:16.281705 RX DATLAT : PASS
9023 09:31:16.284303 RX DQ/DQS(Engine): PASS
9024 09:31:16.287375 TX OE : PASS
9025 09:31:16.287788 All Pass.
9026 09:31:16.288111
9027 09:31:16.288409 CH 1, Rank 0
9028 09:31:16.290662 SW Impedance : PASS
9029 09:31:16.294555 DUTY Scan : NO K
9030 09:31:16.295060 ZQ Calibration : PASS
9031 09:31:16.297826 Jitter Meter : NO K
9032 09:31:16.300579 CBT Training : PASS
9033 09:31:16.300989 Write leveling : PASS
9034 09:31:16.303905 RX DQS gating : PASS
9035 09:31:16.307055 RX DQ/DQS(RDDQC) : PASS
9036 09:31:16.307176 TX DQ/DQS : PASS
9037 09:31:16.310130 RX DATLAT : PASS
9038 09:31:16.313207 RX DQ/DQS(Engine): PASS
9039 09:31:16.313286 TX OE : PASS
9040 09:31:16.313350 All Pass.
9041 09:31:16.317203
9042 09:31:16.317384 CH 1, Rank 1
9043 09:31:16.320007 SW Impedance : PASS
9044 09:31:16.320145 DUTY Scan : NO K
9045 09:31:16.323020 ZQ Calibration : PASS
9046 09:31:16.326546 Jitter Meter : NO K
9047 09:31:16.326638 CBT Training : PASS
9048 09:31:16.329729 Write leveling : PASS
9049 09:31:16.329829 RX DQS gating : PASS
9050 09:31:16.333425 RX DQ/DQS(RDDQC) : PASS
9051 09:31:16.336527 TX DQ/DQS : PASS
9052 09:31:16.336637 RX DATLAT : PASS
9053 09:31:16.339734 RX DQ/DQS(Engine): PASS
9054 09:31:16.343086 TX OE : PASS
9055 09:31:16.343206 All Pass.
9056 09:31:16.343300
9057 09:31:16.346476 DramC Write-DBI on
9058 09:31:16.346607 PER_BANK_REFRESH: Hybrid Mode
9059 09:31:16.350454 TX_TRACKING: ON
9060 09:31:16.359717 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9061 09:31:16.366243 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9062 09:31:16.373091 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9063 09:31:16.376123 [FAST_K] Save calibration result to emmc
9064 09:31:16.379406 sync common calibartion params.
9065 09:31:16.382865 sync cbt_mode0:1, 1:1
9066 09:31:16.385807 dram_init: ddr_geometry: 2
9067 09:31:16.386233 dram_init: ddr_geometry: 2
9068 09:31:16.389400 dram_init: ddr_geometry: 2
9069 09:31:16.392546 0:dram_rank_size:100000000
9070 09:31:16.392960 1:dram_rank_size:100000000
9071 09:31:16.399593 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9072 09:31:16.403838 DFS_SHUFFLE_HW_MODE: ON
9073 09:31:16.405691 dramc_set_vcore_voltage set vcore to 725000
9074 09:31:16.409380 Read voltage for 1600, 0
9075 09:31:16.409789 Vio18 = 0
9076 09:31:16.410114 Vcore = 725000
9077 09:31:16.412705 Vdram = 0
9078 09:31:16.413173 Vddq = 0
9079 09:31:16.413501 Vmddr = 0
9080 09:31:16.415765 switch to 3200 Mbps bootup
9081 09:31:16.419031 [DramcRunTimeConfig]
9082 09:31:16.419478 PHYPLL
9083 09:31:16.419805 DPM_CONTROL_AFTERK: ON
9084 09:31:16.422835 PER_BANK_REFRESH: ON
9085 09:31:16.425843 REFRESH_OVERHEAD_REDUCTION: ON
9086 09:31:16.426248 CMD_PICG_NEW_MODE: OFF
9087 09:31:16.429088 XRTWTW_NEW_MODE: ON
9088 09:31:16.431957 XRTRTR_NEW_MODE: ON
9089 09:31:16.432367 TX_TRACKING: ON
9090 09:31:16.435212 RDSEL_TRACKING: OFF
9091 09:31:16.435620 DQS Precalculation for DVFS: ON
9092 09:31:16.438710 RX_TRACKING: OFF
9093 09:31:16.439161 HW_GATING DBG: ON
9094 09:31:16.441847 ZQCS_ENABLE_LP4: ON
9095 09:31:16.442251 RX_PICG_NEW_MODE: ON
9096 09:31:16.445075 TX_PICG_NEW_MODE: ON
9097 09:31:16.448960 ENABLE_RX_DCM_DPHY: ON
9098 09:31:16.451532 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9099 09:31:16.451940 DUMMY_READ_FOR_TRACKING: OFF
9100 09:31:16.455158 !!! SPM_CONTROL_AFTERK: OFF
9101 09:31:16.458931 !!! SPM could not control APHY
9102 09:31:16.461784 IMPEDANCE_TRACKING: ON
9103 09:31:16.462192 TEMP_SENSOR: ON
9104 09:31:16.465041 HW_SAVE_FOR_SR: OFF
9105 09:31:16.465448 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9106 09:31:16.471580 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9107 09:31:16.472051 Read ODT Tracking: ON
9108 09:31:16.475255 Refresh Rate DeBounce: ON
9109 09:31:16.478115 DFS_NO_QUEUE_FLUSH: ON
9110 09:31:16.481630 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9111 09:31:16.482037 ENABLE_DFS_RUNTIME_MRW: OFF
9112 09:31:16.484868 DDR_RESERVE_NEW_MODE: ON
9113 09:31:16.488339 MR_CBT_SWITCH_FREQ: ON
9114 09:31:16.488805 =========================
9115 09:31:16.507917 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9116 09:31:16.511388 dram_init: ddr_geometry: 2
9117 09:31:16.529467 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9118 09:31:16.532650 dram_init: dram init end (result: 0)
9119 09:31:16.539238 DRAM-K: Full calibration passed in 24432 msecs
9120 09:31:16.543167 MRC: failed to locate region type 0.
9121 09:31:16.543580 DRAM rank0 size:0x100000000,
9122 09:31:16.546060 DRAM rank1 size=0x100000000
9123 09:31:16.556266 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9124 09:31:16.562469 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9125 09:31:16.572348 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9126 09:31:16.578791 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9127 09:31:16.579241 DRAM rank0 size:0x100000000,
9128 09:31:16.582009 DRAM rank1 size=0x100000000
9129 09:31:16.582417 CBMEM:
9130 09:31:16.585295 IMD: root @ 0xfffff000 254 entries.
9131 09:31:16.588450 IMD: root @ 0xffffec00 62 entries.
9132 09:31:16.595125 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9133 09:31:16.598645 WARNING: RO_VPD is uninitialized or empty.
9134 09:31:16.601984 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9135 09:31:16.609700 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9136 09:31:16.622508 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9137 09:31:16.633794 BS: romstage times (exec / console): total (unknown) / 23962 ms
9138 09:31:16.634367
9139 09:31:16.634704
9140 09:31:16.643658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9141 09:31:16.647177 ARM64: Exception handlers installed.
9142 09:31:16.650388 ARM64: Testing exception
9143 09:31:16.653645 ARM64: Done test exception
9144 09:31:16.654074 Enumerating buses...
9145 09:31:16.656563 Show all devs... Before device enumeration.
9146 09:31:16.660296 Root Device: enabled 1
9147 09:31:16.663295 CPU_CLUSTER: 0: enabled 1
9148 09:31:16.663702 CPU: 00: enabled 1
9149 09:31:16.666655 Compare with tree...
9150 09:31:16.667062 Root Device: enabled 1
9151 09:31:16.669695 CPU_CLUSTER: 0: enabled 1
9152 09:31:16.672937 CPU: 00: enabled 1
9153 09:31:16.673343 Root Device scanning...
9154 09:31:16.676526 scan_static_bus for Root Device
9155 09:31:16.679676 CPU_CLUSTER: 0 enabled
9156 09:31:16.682718 scan_static_bus for Root Device done
9157 09:31:16.686457 scan_bus: bus Root Device finished in 8 msecs
9158 09:31:16.686891 done
9159 09:31:16.693089 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9160 09:31:16.696349 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9161 09:31:16.702817 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9162 09:31:16.709211 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9163 09:31:16.709623 Allocating resources...
9164 09:31:16.712351 Reading resources...
9165 09:31:16.716322 Root Device read_resources bus 0 link: 0
9166 09:31:16.719357 DRAM rank0 size:0x100000000,
9167 09:31:16.719775 DRAM rank1 size=0x100000000
9168 09:31:16.725711 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9169 09:31:16.726127 CPU: 00 missing read_resources
9170 09:31:16.732193 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9171 09:31:16.735392 Root Device read_resources bus 0 link: 0 done
9172 09:31:16.739277 Done reading resources.
9173 09:31:16.742482 Show resources in subtree (Root Device)...After reading.
9174 09:31:16.745663 Root Device child on link 0 CPU_CLUSTER: 0
9175 09:31:16.748593 CPU_CLUSTER: 0 child on link 0 CPU: 00
9176 09:31:16.758391 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9177 09:31:16.758811 CPU: 00
9178 09:31:16.765254 Root Device assign_resources, bus 0 link: 0
9179 09:31:16.768791 CPU_CLUSTER: 0 missing set_resources
9180 09:31:16.771844 Root Device assign_resources, bus 0 link: 0 done
9181 09:31:16.775185 Done setting resources.
9182 09:31:16.778227 Show resources in subtree (Root Device)...After assigning values.
9183 09:31:16.784654 Root Device child on link 0 CPU_CLUSTER: 0
9184 09:31:16.788424 CPU_CLUSTER: 0 child on link 0 CPU: 00
9185 09:31:16.795228 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9186 09:31:16.797853 CPU: 00
9187 09:31:16.798336 Done allocating resources.
9188 09:31:16.804382 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9189 09:31:16.807909 Enabling resources...
9190 09:31:16.808387 done.
9191 09:31:16.811307 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9192 09:31:16.814684 Initializing devices...
9193 09:31:16.815130 Root Device init
9194 09:31:16.817908 init hardware done!
9195 09:31:16.820754 0x00000018: ctrlr->caps
9196 09:31:16.821171 52.000 MHz: ctrlr->f_max
9197 09:31:16.824595 0.400 MHz: ctrlr->f_min
9198 09:31:16.827441 0x40ff8080: ctrlr->voltages
9199 09:31:16.827915 sclk: 390625
9200 09:31:16.828242 Bus Width = 1
9201 09:31:16.830931 sclk: 390625
9202 09:31:16.831423 Bus Width = 1
9203 09:31:16.834232 Early init status = 3
9204 09:31:16.837351 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9205 09:31:16.841812 in-header: 03 fb 00 00 01 00 00 00
9206 09:31:16.844900 in-data: 01
9207 09:31:16.848137 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9208 09:31:16.851611 in-header: 03 fb 00 00 01 00 00 00
9209 09:31:16.855312 in-data: 01
9210 09:31:16.858143 [SSUSB] Setting up USB HOST controller...
9211 09:31:16.861642 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9212 09:31:16.864962 [SSUSB] phy power-on done.
9213 09:31:16.868181 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9214 09:31:16.874549 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9215 09:31:16.877861 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9216 09:31:16.884784 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9217 09:31:16.891023 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9218 09:31:16.897916 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9219 09:31:16.904357 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9220 09:31:16.911052 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9221 09:31:16.914071 SPM: binary array size = 0x9dc
9222 09:31:16.921232 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9223 09:31:16.924261 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9224 09:31:16.934039 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9225 09:31:16.937513 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9226 09:31:16.940424 configure_display: Starting display init
9227 09:31:16.975593 anx7625_power_on_init: Init interface.
9228 09:31:16.978653 anx7625_disable_pd_protocol: Disabled PD feature.
9229 09:31:16.981876 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9230 09:31:17.009794 anx7625_start_dp_work: Secure OCM version=00
9231 09:31:17.012968 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9232 09:31:17.027606 sp_tx_get_edid_block: EDID Block = 1
9233 09:31:17.130280 Extracted contents:
9234 09:31:17.133265 header: 00 ff ff ff ff ff ff 00
9235 09:31:17.136530 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9236 09:31:17.140588 version: 01 04
9237 09:31:17.143300 basic params: 95 1f 11 78 0a
9238 09:31:17.146568 chroma info: 76 90 94 55 54 90 27 21 50 54
9239 09:31:17.149962 established: 00 00 00
9240 09:31:17.156315 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9241 09:31:17.163577 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9242 09:31:17.166411 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9243 09:31:17.172686 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9244 09:31:17.179597 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9245 09:31:17.182606 extensions: 00
9246 09:31:17.182982 checksum: fb
9247 09:31:17.183400
9248 09:31:17.189095 Manufacturer: IVO Model 57d Serial Number 0
9249 09:31:17.189465 Made week 0 of 2020
9250 09:31:17.192413 EDID version: 1.4
9251 09:31:17.192816 Digital display
9252 09:31:17.195784 6 bits per primary color channel
9253 09:31:17.200034 DisplayPort interface
9254 09:31:17.200581 Maximum image size: 31 cm x 17 cm
9255 09:31:17.202251 Gamma: 220%
9256 09:31:17.202649 Check DPMS levels
9257 09:31:17.208906 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9258 09:31:17.212602 First detailed timing is preferred timing
9259 09:31:17.215635 Established timings supported:
9260 09:31:17.216035 Standard timings supported:
9261 09:31:17.218735 Detailed timings
9262 09:31:17.222420 Hex of detail: 383680a07038204018303c0035ae10000019
9263 09:31:17.228591 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9264 09:31:17.231679 0780 0798 07c8 0820 hborder 0
9265 09:31:17.235257 0438 043b 0447 0458 vborder 0
9266 09:31:17.238491 -hsync -vsync
9267 09:31:17.239042 Did detailed timing
9268 09:31:17.245586 Hex of detail: 000000000000000000000000000000000000
9269 09:31:17.248182 Manufacturer-specified data, tag 0
9270 09:31:17.251995 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9271 09:31:17.255005 ASCII string: InfoVision
9272 09:31:17.258569 Hex of detail: 000000fe00523134304e574635205248200a
9273 09:31:17.261975 ASCII string: R140NWF5 RH
9274 09:31:17.262386 Checksum
9275 09:31:17.265384 Checksum: 0xfb (valid)
9276 09:31:17.268155 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9277 09:31:17.271409 DSI data_rate: 832800000 bps
9278 09:31:17.278426 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9279 09:31:17.281374 anx7625_parse_edid: pixelclock(138800).
9280 09:31:17.284796 hactive(1920), hsync(48), hfp(24), hbp(88)
9281 09:31:17.288482 vactive(1080), vsync(12), vfp(3), vbp(17)
9282 09:31:17.291335 anx7625_dsi_config: config dsi.
9283 09:31:17.297691 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9284 09:31:17.312005 anx7625_dsi_config: success to config DSI
9285 09:31:17.314915 anx7625_dp_start: MIPI phy setup OK.
9286 09:31:17.319287 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9287 09:31:17.321725 mtk_ddp_mode_set invalid vrefresh 60
9288 09:31:17.324871 main_disp_path_setup
9289 09:31:17.325017 ovl_layer_smi_id_en
9290 09:31:17.328655 ovl_layer_smi_id_en
9291 09:31:17.328737 ccorr_config
9292 09:31:17.328801 aal_config
9293 09:31:17.331853 gamma_config
9294 09:31:17.331933 postmask_config
9295 09:31:17.334697 dither_config
9296 09:31:17.338756 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9297 09:31:17.345254 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9298 09:31:17.348537 Root Device init finished in 529 msecs
9299 09:31:17.351943 CPU_CLUSTER: 0 init
9300 09:31:17.358170 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9301 09:31:17.365029 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9302 09:31:17.365194 APU_MBOX 0x190000b0 = 0x10001
9303 09:31:17.368338 APU_MBOX 0x190001b0 = 0x10001
9304 09:31:17.371354 APU_MBOX 0x190005b0 = 0x10001
9305 09:31:17.374813 APU_MBOX 0x190006b0 = 0x10001
9306 09:31:17.381740 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9307 09:31:17.390778 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9308 09:31:17.403177 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9309 09:31:17.410112 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9310 09:31:17.421909 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9311 09:31:17.430733 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9312 09:31:17.434178 CPU_CLUSTER: 0 init finished in 81 msecs
9313 09:31:17.438338 Devices initialized
9314 09:31:17.441157 Show all devs... After init.
9315 09:31:17.441615 Root Device: enabled 1
9316 09:31:17.444846 CPU_CLUSTER: 0: enabled 1
9317 09:31:17.447615 CPU: 00: enabled 1
9318 09:31:17.450394 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9319 09:31:17.454158 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9320 09:31:17.457625 ELOG: NV offset 0x57f000 size 0x1000
9321 09:31:17.464437 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9322 09:31:17.470932 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9323 09:31:17.473988 ELOG: Event(17) added with size 13 at 2023-10-20 09:31:17 UTC
9324 09:31:17.480878 out: cmd=0x121: 03 db 21 01 00 00 00 00
9325 09:31:17.483812 in-header: 03 3b 00 00 2c 00 00 00
9326 09:31:17.494302 in-data: 24 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9327 09:31:17.500900 ELOG: Event(A1) added with size 10 at 2023-10-20 09:31:17 UTC
9328 09:31:17.506845 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9329 09:31:17.513563 ELOG: Event(A0) added with size 9 at 2023-10-20 09:31:17 UTC
9330 09:31:17.517318 elog_add_boot_reason: Logged dev mode boot
9331 09:31:17.523541 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9332 09:31:17.524049 Finalize devices...
9333 09:31:17.526718 Devices finalized
9334 09:31:17.530103 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9335 09:31:17.533421 Writing coreboot table at 0xffe64000
9336 09:31:17.536315 0. 000000000010a000-0000000000113fff: RAMSTAGE
9337 09:31:17.543817 1. 0000000040000000-00000000400fffff: RAM
9338 09:31:17.546741 2. 0000000040100000-000000004032afff: RAMSTAGE
9339 09:31:17.549631 3. 000000004032b000-00000000545fffff: RAM
9340 09:31:17.553290 4. 0000000054600000-000000005465ffff: BL31
9341 09:31:17.556422 5. 0000000054660000-00000000ffe63fff: RAM
9342 09:31:17.563467 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9343 09:31:17.566583 7. 0000000100000000-000000023fffffff: RAM
9344 09:31:17.569335 Passing 5 GPIOs to payload:
9345 09:31:17.572671 NAME | PORT | POLARITY | VALUE
9346 09:31:17.579398 EC in RW | 0x000000aa | low | undefined
9347 09:31:17.582575 EC interrupt | 0x00000005 | low | undefined
9348 09:31:17.589012 TPM interrupt | 0x000000ab | high | undefined
9349 09:31:17.592598 SD card detect | 0x00000011 | high | undefined
9350 09:31:17.596277 speaker enable | 0x00000093 | high | undefined
9351 09:31:17.599486 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9352 09:31:17.602365 in-header: 03 f9 00 00 02 00 00 00
9353 09:31:17.605843 in-data: 02 00
9354 09:31:17.610148 ADC[4]: Raw value=902955 ID=7
9355 09:31:17.612656 ADC[3]: Raw value=213916 ID=1
9356 09:31:17.613070 RAM Code: 0x71
9357 09:31:17.616497 ADC[6]: Raw value=74630 ID=0
9358 09:31:17.619473 ADC[5]: Raw value=213546 ID=1
9359 09:31:17.620024 SKU Code: 0x1
9360 09:31:17.625519 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c159
9361 09:31:17.626018 coreboot table: 964 bytes.
9362 09:31:17.628695 IMD ROOT 0. 0xfffff000 0x00001000
9363 09:31:17.632256 IMD SMALL 1. 0xffffe000 0x00001000
9364 09:31:17.635317 RO MCACHE 2. 0xffffc000 0x00001104
9365 09:31:17.638792 CONSOLE 3. 0xfff7c000 0x00080000
9366 09:31:17.641837 FMAP 4. 0xfff7b000 0x00000452
9367 09:31:17.645377 TIME STAMP 5. 0xfff7a000 0x00000910
9368 09:31:17.648543 VBOOT WORK 6. 0xfff66000 0x00014000
9369 09:31:17.651512 RAMOOPS 7. 0xffe66000 0x00100000
9370 09:31:17.654883 COREBOOT 8. 0xffe64000 0x00002000
9371 09:31:17.657945 IMD small region:
9372 09:31:17.661663 IMD ROOT 0. 0xffffec00 0x00000400
9373 09:31:17.665237 VPD 1. 0xffffeb80 0x0000006c
9374 09:31:17.667972 MMC STATUS 2. 0xffffeb60 0x00000004
9375 09:31:17.674886 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9376 09:31:17.675442 Probing TPM: done!
9377 09:31:17.681526 Connected to device vid:did:rid of 1ae0:0028:00
9378 09:31:17.688729 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9379 09:31:17.691523 Initialized TPM device CR50 revision 0
9380 09:31:17.695402 Checking cr50 for pending updates
9381 09:31:17.700613 Reading cr50 TPM mode
9382 09:31:17.709713 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9383 09:31:17.715914 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9384 09:31:17.756225 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9385 09:31:17.759456 Checking segment from ROM address 0x40100000
9386 09:31:17.762681 Checking segment from ROM address 0x4010001c
9387 09:31:17.769817 Loading segment from ROM address 0x40100000
9388 09:31:17.770400 code (compression=0)
9389 09:31:17.779844 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9390 09:31:17.786334 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9391 09:31:17.786875 it's not compressed!
9392 09:31:17.793343 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9393 09:31:17.796251 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9394 09:31:17.816779 Loading segment from ROM address 0x4010001c
9395 09:31:17.817335 Entry Point 0x80000000
9396 09:31:17.819763 Loaded segments
9397 09:31:17.823483 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9398 09:31:17.830443 Jumping to boot code at 0x80000000(0xffe64000)
9399 09:31:17.836371 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9400 09:31:17.843196 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9401 09:31:17.850721 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9402 09:31:17.854217 Checking segment from ROM address 0x40100000
9403 09:31:17.857567 Checking segment from ROM address 0x4010001c
9404 09:31:17.864121 Loading segment from ROM address 0x40100000
9405 09:31:17.864620 code (compression=1)
9406 09:31:17.870353 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9407 09:31:17.880589 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9408 09:31:17.881008 using LZMA
9409 09:31:17.889333 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9410 09:31:17.896039 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9411 09:31:17.898833 Loading segment from ROM address 0x4010001c
9412 09:31:17.899423 Entry Point 0x54601000
9413 09:31:17.902470 Loaded segments
9414 09:31:17.905334 NOTICE: MT8192 bl31_setup
9415 09:31:17.913330 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9416 09:31:17.916249 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9417 09:31:17.919619 WARNING: region 0:
9418 09:31:17.923164 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9419 09:31:17.923678 WARNING: region 1:
9420 09:31:17.929580 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9421 09:31:17.933483 WARNING: region 2:
9422 09:31:17.936294 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9423 09:31:17.939422 WARNING: region 3:
9424 09:31:17.943133 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9425 09:31:17.946348 WARNING: region 4:
9426 09:31:17.953579 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9427 09:31:17.954139 WARNING: region 5:
9428 09:31:17.956692 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9429 09:31:17.959685 WARNING: region 6:
9430 09:31:17.962814 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 09:31:17.965977 WARNING: region 7:
9432 09:31:17.969865 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 09:31:17.976173 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9434 09:31:17.979839 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9435 09:31:17.983548 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9436 09:31:17.989862 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9437 09:31:17.993322 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9438 09:31:17.996702 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9439 09:31:18.002622 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9440 09:31:18.005898 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9441 09:31:18.012780 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9442 09:31:18.015616 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9443 09:31:18.019888 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9444 09:31:18.026466 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9445 09:31:18.028623 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9446 09:31:18.035388 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9447 09:31:18.039677 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9448 09:31:18.042356 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9449 09:31:18.048910 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9450 09:31:18.052198 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9451 09:31:18.055952 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9452 09:31:18.062119 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9453 09:31:18.065048 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9454 09:31:18.071866 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9455 09:31:18.075786 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9456 09:31:18.078614 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9457 09:31:18.085441 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9458 09:31:18.088514 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9459 09:31:18.095177 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9460 09:31:18.098390 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9461 09:31:18.102133 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9462 09:31:18.108515 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9463 09:31:18.111956 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9464 09:31:18.118230 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9465 09:31:18.121528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9466 09:31:18.125588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9467 09:31:18.128620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9468 09:31:18.134803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9469 09:31:18.138370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9470 09:31:18.141602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9471 09:31:18.145062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9472 09:31:18.151870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9473 09:31:18.154944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9474 09:31:18.158251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9475 09:31:18.161771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9476 09:31:18.168451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9477 09:31:18.171296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9478 09:31:18.174776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9479 09:31:18.178709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9480 09:31:18.184816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9481 09:31:18.188190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9482 09:31:18.195210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9483 09:31:18.198355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9484 09:31:18.201553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9485 09:31:18.208086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9486 09:31:18.211266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9487 09:31:18.217678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9488 09:31:18.221288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9489 09:31:18.227844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9490 09:31:18.231247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9491 09:31:18.234227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9492 09:31:18.241596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9493 09:31:18.244216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9494 09:31:18.250989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9495 09:31:18.254372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9496 09:31:18.261191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9497 09:31:18.264633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9498 09:31:18.271003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9499 09:31:18.274868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9500 09:31:18.277853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9501 09:31:18.284475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9502 09:31:18.287373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9503 09:31:18.294323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9504 09:31:18.297692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9505 09:31:18.304052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9506 09:31:18.307469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9507 09:31:18.310738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9508 09:31:18.317552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9509 09:31:18.321240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9510 09:31:18.327562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9511 09:31:18.331373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9512 09:31:18.337673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9513 09:31:18.340854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9514 09:31:18.347405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9515 09:31:18.350871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9516 09:31:18.354086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9517 09:31:18.360566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9518 09:31:18.364269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9519 09:31:18.371118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9520 09:31:18.374545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9521 09:31:18.377873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9522 09:31:18.384309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9523 09:31:18.387687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9524 09:31:18.394106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9525 09:31:18.397729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9526 09:31:18.404295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9527 09:31:18.407375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9528 09:31:18.414583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9529 09:31:18.417473 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9530 09:31:18.420667 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9531 09:31:18.424123 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9532 09:31:18.430640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9533 09:31:18.440539 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9534 09:31:18.441015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9535 09:31:18.444235 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9536 09:31:18.447756 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9537 09:31:18.454066 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9538 09:31:18.457673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9539 09:31:18.460343 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9540 09:31:18.467176 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9541 09:31:18.470426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9542 09:31:18.477463 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9543 09:31:18.480158 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9544 09:31:18.484326 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9545 09:31:18.490482 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9546 09:31:18.493840 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9547 09:31:18.500309 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9548 09:31:18.503525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9549 09:31:18.506983 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9550 09:31:18.510714 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9551 09:31:18.516907 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9552 09:31:18.520756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9553 09:31:18.523914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9554 09:31:18.530218 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9555 09:31:18.533128 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9556 09:31:18.536775 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9557 09:31:18.539661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9558 09:31:18.546518 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9559 09:31:18.549988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9560 09:31:18.556343 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9561 09:31:18.560029 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9562 09:31:18.566120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9563 09:31:18.569307 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9564 09:31:18.572889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9565 09:31:18.579520 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9566 09:31:18.582816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9567 09:31:18.585880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9568 09:31:18.592725 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9569 09:31:18.595823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9570 09:31:18.602657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9571 09:31:18.605773 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9572 09:31:18.609294 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9573 09:31:18.615902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9574 09:31:18.619463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9575 09:31:18.625660 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9576 09:31:18.628968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9577 09:31:18.632771 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9578 09:31:18.638915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9579 09:31:18.642390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9580 09:31:18.648824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9581 09:31:18.652084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9582 09:31:18.655419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9583 09:31:18.662385 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9584 09:31:18.665430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9585 09:31:18.669370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9586 09:31:18.676068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9587 09:31:18.678876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9588 09:31:18.685708 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9589 09:31:18.688863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9590 09:31:18.692545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9591 09:31:18.698869 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9592 09:31:18.702284 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9593 09:31:18.708627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9594 09:31:18.712123 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9595 09:31:18.715712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9596 09:31:18.722051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9597 09:31:18.725003 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9598 09:31:18.732090 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9599 09:31:18.734853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9600 09:31:18.738221 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9601 09:31:18.744843 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9602 09:31:18.748983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9603 09:31:18.755016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9604 09:31:18.757803 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9605 09:31:18.761027 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9606 09:31:18.767814 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9607 09:31:18.770934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9608 09:31:18.777609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9609 09:31:18.780987 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9610 09:31:18.784489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9611 09:31:18.791014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9612 09:31:18.794380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9613 09:31:18.800786 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9614 09:31:18.804059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9615 09:31:18.807185 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9616 09:31:18.813981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9617 09:31:18.817267 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9618 09:31:18.823988 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9619 09:31:18.826999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9620 09:31:18.830896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9621 09:31:18.837299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9622 09:31:18.840697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9623 09:31:18.846880 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9624 09:31:18.850566 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9625 09:31:18.856968 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9626 09:31:18.860150 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9627 09:31:18.863054 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9628 09:31:18.870156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9629 09:31:18.873052 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9630 09:31:18.880343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9631 09:31:18.883320 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9632 09:31:18.889509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9633 09:31:18.893278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9634 09:31:18.899561 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9635 09:31:18.902619 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9636 09:31:18.905968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9637 09:31:18.913273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9638 09:31:18.916084 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9639 09:31:18.922888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9640 09:31:18.925675 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9641 09:31:18.929457 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9642 09:31:18.936052 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9643 09:31:18.939316 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9644 09:31:18.945768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9645 09:31:18.949183 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9646 09:31:18.955723 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9647 09:31:18.958986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9648 09:31:18.962412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9649 09:31:18.969314 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9650 09:31:18.972400 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9651 09:31:18.978592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9652 09:31:18.982491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9653 09:31:18.988709 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9654 09:31:18.991864 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9655 09:31:18.995181 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9656 09:31:19.001787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9657 09:31:19.005408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9658 09:31:19.011637 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9659 09:31:19.014838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9660 09:31:19.022256 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9661 09:31:19.024848 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9662 09:31:19.028595 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9663 09:31:19.031807 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9664 09:31:19.038066 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9665 09:31:19.041161 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9666 09:31:19.044751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9667 09:31:19.051480 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9668 09:31:19.054708 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9669 09:31:19.058037 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9670 09:31:19.064373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9671 09:31:19.067960 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9672 09:31:19.071191 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9673 09:31:19.077852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9674 09:31:19.080619 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9675 09:31:19.087390 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9676 09:31:19.091212 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9677 09:31:19.093799 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9678 09:31:19.100519 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9679 09:31:19.104210 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9680 09:31:19.110258 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9681 09:31:19.114216 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9682 09:31:19.116791 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9683 09:31:19.123462 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9684 09:31:19.126668 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9685 09:31:19.130808 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9686 09:31:19.136709 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9687 09:31:19.140208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9688 09:31:19.146518 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9689 09:31:19.150292 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9690 09:31:19.153064 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9691 09:31:19.159641 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9692 09:31:19.162978 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9693 09:31:19.166233 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9694 09:31:19.172656 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9695 09:31:19.175927 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9696 09:31:19.179649 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9697 09:31:19.186126 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9698 09:31:19.189193 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9699 09:31:19.195980 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9700 09:31:19.199514 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9701 09:31:19.201992 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9702 09:31:19.208689 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9703 09:31:19.211920 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9704 09:31:19.215225 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9705 09:31:19.218576 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9706 09:31:19.222182 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9707 09:31:19.228696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9708 09:31:19.232381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9709 09:31:19.235344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9710 09:31:19.241772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9711 09:31:19.245168 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9712 09:31:19.248346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9713 09:31:19.255103 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9714 09:31:19.257973 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9715 09:31:19.261346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9716 09:31:19.268034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9717 09:31:19.271266 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9718 09:31:19.277629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9719 09:31:19.281128 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9720 09:31:19.284809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9721 09:31:19.291263 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9722 09:31:19.294463 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9723 09:31:19.300791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9724 09:31:19.304060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9725 09:31:19.307386 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9726 09:31:19.314045 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9727 09:31:19.317658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9728 09:31:19.324322 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9729 09:31:19.327335 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9730 09:31:19.333796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9731 09:31:19.337104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9732 09:31:19.340552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9733 09:31:19.347162 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9734 09:31:19.351535 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9735 09:31:19.357634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9736 09:31:19.360649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9737 09:31:19.367135 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9738 09:31:19.370495 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9739 09:31:19.373836 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9740 09:31:19.380397 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9741 09:31:19.383400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9742 09:31:19.390188 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9743 09:31:19.393989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9744 09:31:19.400366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9745 09:31:19.403894 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9746 09:31:19.406665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9747 09:31:19.413253 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9748 09:31:19.416688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9749 09:31:19.422975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9750 09:31:19.426198 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9751 09:31:19.429799 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9752 09:31:19.436122 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9753 09:31:19.439482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9754 09:31:19.446321 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9755 09:31:19.449326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9756 09:31:19.456163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9757 09:31:19.459286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9758 09:31:19.462567 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9759 09:31:19.469099 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9760 09:31:19.472428 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9761 09:31:19.479169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9762 09:31:19.482404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9763 09:31:19.488605 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9764 09:31:19.492047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9765 09:31:19.495564 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9766 09:31:19.501882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9767 09:31:19.505111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9768 09:31:19.511902 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9769 09:31:19.514770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9770 09:31:19.518061 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9771 09:31:19.525438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9772 09:31:19.528721 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9773 09:31:19.534823 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9774 09:31:19.538190 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9775 09:31:19.544770 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9776 09:31:19.548681 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9777 09:31:19.551476 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9778 09:31:19.557957 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9779 09:31:19.561917 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9780 09:31:19.568001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9781 09:31:19.571339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9782 09:31:19.574658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9783 09:31:19.581407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9784 09:31:19.584730 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9785 09:31:19.591258 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9786 09:31:19.594837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9787 09:31:19.600859 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9788 09:31:19.604315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9789 09:31:19.607966 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9790 09:31:19.614318 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9791 09:31:19.617757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9792 09:31:19.624292 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9793 09:31:19.627719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9794 09:31:19.633526 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9795 09:31:19.637133 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9796 09:31:19.643919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9797 09:31:19.647407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9798 09:31:19.654310 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9799 09:31:19.657421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9800 09:31:19.659926 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9801 09:31:19.666911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9802 09:31:19.670171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9803 09:31:19.677014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9804 09:31:19.679834 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9805 09:31:19.687164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9806 09:31:19.690478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9807 09:31:19.693954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9808 09:31:19.699865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9809 09:31:19.703504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9810 09:31:19.709609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9811 09:31:19.713621 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9812 09:31:19.719921 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9813 09:31:19.722675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9814 09:31:19.729977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9815 09:31:19.732650 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9816 09:31:19.739406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9817 09:31:19.742529 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9818 09:31:19.745967 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9819 09:31:19.752538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9820 09:31:19.755563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9821 09:31:19.762516 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9822 09:31:19.765740 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9823 09:31:19.772534 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9824 09:31:19.775774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9825 09:31:19.782335 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9826 09:31:19.785708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9827 09:31:19.788564 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9828 09:31:19.795412 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9829 09:31:19.798522 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9830 09:31:19.805592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9831 09:31:19.808660 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9832 09:31:19.815018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9833 09:31:19.818361 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9834 09:31:19.821475 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9835 09:31:19.828775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9836 09:31:19.831758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9837 09:31:19.838281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9838 09:31:19.841531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9839 09:31:19.847939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9840 09:31:19.851825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9841 09:31:19.858109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9842 09:31:19.861394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9843 09:31:19.867765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9844 09:31:19.871845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9845 09:31:19.878085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9846 09:31:19.881101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9847 09:31:19.887229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9848 09:31:19.890708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9849 09:31:19.898015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9850 09:31:19.900523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9851 09:31:19.907157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9852 09:31:19.910567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9853 09:31:19.917330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9854 09:31:19.920616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9855 09:31:19.926992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9856 09:31:19.930407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9857 09:31:19.936827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9858 09:31:19.939929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9859 09:31:19.946782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9860 09:31:19.950429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9861 09:31:19.956597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9862 09:31:19.959500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9863 09:31:19.967121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9864 09:31:19.969760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9865 09:31:19.976240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9866 09:31:19.980013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9867 09:31:19.986064 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9868 09:31:19.986505 INFO: [APUAPC] vio 0
9869 09:31:19.992794 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9870 09:31:19.996139 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9871 09:31:19.999148 INFO: [APUAPC] D0_APC_0: 0x400510
9872 09:31:20.002221 INFO: [APUAPC] D0_APC_1: 0x0
9873 09:31:20.005670 INFO: [APUAPC] D0_APC_2: 0x1540
9874 09:31:20.008954 INFO: [APUAPC] D0_APC_3: 0x0
9875 09:31:20.012361 INFO: [APUAPC] D1_APC_0: 0xffffffff
9876 09:31:20.015450 INFO: [APUAPC] D1_APC_1: 0xffffffff
9877 09:31:20.018618 INFO: [APUAPC] D1_APC_2: 0x3fffff
9878 09:31:20.022004 INFO: [APUAPC] D1_APC_3: 0x0
9879 09:31:20.025507 INFO: [APUAPC] D2_APC_0: 0xffffffff
9880 09:31:20.029546 INFO: [APUAPC] D2_APC_1: 0xffffffff
9881 09:31:20.032157 INFO: [APUAPC] D2_APC_2: 0x3fffff
9882 09:31:20.035568 INFO: [APUAPC] D2_APC_3: 0x0
9883 09:31:20.039052 INFO: [APUAPC] D3_APC_0: 0xffffffff
9884 09:31:20.042446 INFO: [APUAPC] D3_APC_1: 0xffffffff
9885 09:31:20.045575 INFO: [APUAPC] D3_APC_2: 0x3fffff
9886 09:31:20.048632 INFO: [APUAPC] D3_APC_3: 0x0
9887 09:31:20.051898 INFO: [APUAPC] D4_APC_0: 0xffffffff
9888 09:31:20.055144 INFO: [APUAPC] D4_APC_1: 0xffffffff
9889 09:31:20.058433 INFO: [APUAPC] D4_APC_2: 0x3fffff
9890 09:31:20.061798 INFO: [APUAPC] D4_APC_3: 0x0
9891 09:31:20.065022 INFO: [APUAPC] D5_APC_0: 0xffffffff
9892 09:31:20.068468 INFO: [APUAPC] D5_APC_1: 0xffffffff
9893 09:31:20.072438 INFO: [APUAPC] D5_APC_2: 0x3fffff
9894 09:31:20.075024 INFO: [APUAPC] D5_APC_3: 0x0
9895 09:31:20.078226 INFO: [APUAPC] D6_APC_0: 0xffffffff
9896 09:31:20.081705 INFO: [APUAPC] D6_APC_1: 0xffffffff
9897 09:31:20.084911 INFO: [APUAPC] D6_APC_2: 0x3fffff
9898 09:31:20.088259 INFO: [APUAPC] D6_APC_3: 0x0
9899 09:31:20.091305 INFO: [APUAPC] D7_APC_0: 0xffffffff
9900 09:31:20.094518 INFO: [APUAPC] D7_APC_1: 0xffffffff
9901 09:31:20.097839 INFO: [APUAPC] D7_APC_2: 0x3fffff
9902 09:31:20.098259 INFO: [APUAPC] D7_APC_3: 0x0
9903 09:31:20.104332 INFO: [APUAPC] D8_APC_0: 0xffffffff
9904 09:31:20.107549 INFO: [APUAPC] D8_APC_1: 0xffffffff
9905 09:31:20.111255 INFO: [APUAPC] D8_APC_2: 0x3fffff
9906 09:31:20.111692 INFO: [APUAPC] D8_APC_3: 0x0
9907 09:31:20.117458 INFO: [APUAPC] D9_APC_0: 0xffffffff
9908 09:31:20.120874 INFO: [APUAPC] D9_APC_1: 0xffffffff
9909 09:31:20.124022 INFO: [APUAPC] D9_APC_2: 0x3fffff
9910 09:31:20.124648 INFO: [APUAPC] D9_APC_3: 0x0
9911 09:31:20.127368 INFO: [APUAPC] D10_APC_0: 0xffffffff
9912 09:31:20.133919 INFO: [APUAPC] D10_APC_1: 0xffffffff
9913 09:31:20.137530 INFO: [APUAPC] D10_APC_2: 0x3fffff
9914 09:31:20.138359 INFO: [APUAPC] D10_APC_3: 0x0
9915 09:31:20.143898 INFO: [APUAPC] D11_APC_0: 0xffffffff
9916 09:31:20.146929 INFO: [APUAPC] D11_APC_1: 0xffffffff
9917 09:31:20.150295 INFO: [APUAPC] D11_APC_2: 0x3fffff
9918 09:31:20.154273 INFO: [APUAPC] D11_APC_3: 0x0
9919 09:31:20.158122 INFO: [APUAPC] D12_APC_0: 0xffffffff
9920 09:31:20.160169 INFO: [APUAPC] D12_APC_1: 0xffffffff
9921 09:31:20.163868 INFO: [APUAPC] D12_APC_2: 0x3fffff
9922 09:31:20.166942 INFO: [APUAPC] D12_APC_3: 0x0
9923 09:31:20.170800 INFO: [APUAPC] D13_APC_0: 0xffffffff
9924 09:31:20.173946 INFO: [APUAPC] D13_APC_1: 0xffffffff
9925 09:31:20.177141 INFO: [APUAPC] D13_APC_2: 0x3fffff
9926 09:31:20.180586 INFO: [APUAPC] D13_APC_3: 0x0
9927 09:31:20.183187 INFO: [APUAPC] D14_APC_0: 0xffffffff
9928 09:31:20.187314 INFO: [APUAPC] D14_APC_1: 0xffffffff
9929 09:31:20.190017 INFO: [APUAPC] D14_APC_2: 0x3fffff
9930 09:31:20.193581 INFO: [APUAPC] D14_APC_3: 0x0
9931 09:31:20.197007 INFO: [APUAPC] D15_APC_0: 0xffffffff
9932 09:31:20.200084 INFO: [APUAPC] D15_APC_1: 0xffffffff
9933 09:31:20.203411 INFO: [APUAPC] D15_APC_2: 0x3fffff
9934 09:31:20.206581 INFO: [APUAPC] D15_APC_3: 0x0
9935 09:31:20.209781 INFO: [APUAPC] APC_CON: 0x4
9936 09:31:20.212933 INFO: [NOCDAPC] D0_APC_0: 0x0
9937 09:31:20.213393 INFO: [NOCDAPC] D0_APC_1: 0x0
9938 09:31:20.216525 INFO: [NOCDAPC] D1_APC_0: 0x0
9939 09:31:20.219716 INFO: [NOCDAPC] D1_APC_1: 0xfff
9940 09:31:20.222947 INFO: [NOCDAPC] D2_APC_0: 0x0
9941 09:31:20.226176 INFO: [NOCDAPC] D2_APC_1: 0xfff
9942 09:31:20.229860 INFO: [NOCDAPC] D3_APC_0: 0x0
9943 09:31:20.233192 INFO: [NOCDAPC] D3_APC_1: 0xfff
9944 09:31:20.237182 INFO: [NOCDAPC] D4_APC_0: 0x0
9945 09:31:20.239271 INFO: [NOCDAPC] D4_APC_1: 0xfff
9946 09:31:20.242688 INFO: [NOCDAPC] D5_APC_0: 0x0
9947 09:31:20.245986 INFO: [NOCDAPC] D5_APC_1: 0xfff
9948 09:31:20.246446 INFO: [NOCDAPC] D6_APC_0: 0x0
9949 09:31:20.248971 INFO: [NOCDAPC] D6_APC_1: 0xfff
9950 09:31:20.252619 INFO: [NOCDAPC] D7_APC_0: 0x0
9951 09:31:20.255703 INFO: [NOCDAPC] D7_APC_1: 0xfff
9952 09:31:20.259169 INFO: [NOCDAPC] D8_APC_0: 0x0
9953 09:31:20.262486 INFO: [NOCDAPC] D8_APC_1: 0xfff
9954 09:31:20.265544 INFO: [NOCDAPC] D9_APC_0: 0x0
9955 09:31:20.269036 INFO: [NOCDAPC] D9_APC_1: 0xfff
9956 09:31:20.272542 INFO: [NOCDAPC] D10_APC_0: 0x0
9957 09:31:20.275925 INFO: [NOCDAPC] D10_APC_1: 0xfff
9958 09:31:20.278602 INFO: [NOCDAPC] D11_APC_0: 0x0
9959 09:31:20.281991 INFO: [NOCDAPC] D11_APC_1: 0xfff
9960 09:31:20.285157 INFO: [NOCDAPC] D12_APC_0: 0x0
9961 09:31:20.288734 INFO: [NOCDAPC] D12_APC_1: 0xfff
9962 09:31:20.292145 INFO: [NOCDAPC] D13_APC_0: 0x0
9963 09:31:20.292656 INFO: [NOCDAPC] D13_APC_1: 0xfff
9964 09:31:20.295067 INFO: [NOCDAPC] D14_APC_0: 0x0
9965 09:31:20.298880 INFO: [NOCDAPC] D14_APC_1: 0xfff
9966 09:31:20.301799 INFO: [NOCDAPC] D15_APC_0: 0x0
9967 09:31:20.305608 INFO: [NOCDAPC] D15_APC_1: 0xfff
9968 09:31:20.308720 INFO: [NOCDAPC] APC_CON: 0x4
9969 09:31:20.312006 INFO: [APUAPC] set_apusys_apc done
9970 09:31:20.315143 INFO: [DEVAPC] devapc_init done
9971 09:31:20.318619 INFO: GICv3 without legacy support detected.
9972 09:31:20.325324 INFO: ARM GICv3 driver initialized in EL3
9973 09:31:20.328136 INFO: Maximum SPI INTID supported: 639
9974 09:31:20.331270 INFO: BL31: Initializing runtime services
9975 09:31:20.338804 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9976 09:31:20.341006 INFO: SPM: enable CPC mode
9977 09:31:20.344791 INFO: mcdi ready for mcusys-off-idle and system suspend
9978 09:31:20.347763 INFO: BL31: Preparing for EL3 exit to normal world
9979 09:31:20.354431 INFO: Entry point address = 0x80000000
9980 09:31:20.354984 INFO: SPSR = 0x8
9981 09:31:20.360699
9982 09:31:20.361250
9983 09:31:20.361626
9984 09:31:20.364457 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9985 09:31:20.365004 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9986 09:31:20.365532 Setting prompt string to ['asurada:']
9987 09:31:20.365966 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9988 09:31:20.366745 Starting depthcharge on Spherion...
9989 09:31:20.367222
9990 09:31:20.367607 Wipe memory regions:
9991 09:31:20.367960
9992 09:31:20.368352 [0x00000040000000, 0x00000054600000)
9993 09:31:20.489605
9994 09:31:20.490150 [0x00000054660000, 0x00000080000000)
9995 09:31:20.750446
9996 09:31:20.750993 [0x000000821a7280, 0x000000ffe64000)
9997 09:31:21.495167
9998 09:31:21.495726 [0x00000100000000, 0x00000240000000)
9999 09:31:23.385689
10000 09:31:23.388248 Initializing XHCI USB controller at 0x11200000.
10001 09:31:24.426243
10002 09:31:24.429979 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10003 09:31:24.430426
10004 09:31:24.430755
10005 09:31:24.431066
10006 09:31:24.431860 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10008 09:31:24.532993 asurada: tftpboot 192.168.201.1 11826819/tftp-deploy-p0d7m4m5/kernel/image.itb 11826819/tftp-deploy-p0d7m4m5/kernel/cmdline
10009 09:31:24.533774 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10010 09:31:24.534402 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10011 09:31:24.538217 tftpboot 192.168.201.1 11826819/tftp-deploy-p0d7m4m5/kernel/image.itp-deploy-p0d7m4m5/kernel/cmdline
10012 09:31:24.538305
10013 09:31:24.538374 Waiting for link
10014 09:31:24.699156
10015 09:31:24.699308 R8152: Initializing
10016 09:31:24.699382
10017 09:31:24.702547 Version 6 (ocp_data = 5c30)
10018 09:31:24.702706
10019 09:31:24.705417 R8152: Done initializing
10020 09:31:24.705581
10021 09:31:24.705656 Adding net device
10022 09:31:26.682952
10023 09:31:26.683142 done.
10024 09:31:26.683213
10025 09:31:26.683273 MAC: 00:24:32:30:7c:7b
10026 09:31:26.683332
10027 09:31:26.686374 Sending DHCP discover... done.
10028 09:31:26.686456
10029 09:31:26.689479 Waiting for reply... done.
10030 09:31:26.689560
10031 09:31:26.692846 Sending DHCP request... done.
10032 09:31:26.692927
10033 09:31:26.697990 Waiting for reply... done.
10034 09:31:26.698071
10035 09:31:26.698135 My ip is 192.168.201.14
10036 09:31:26.698194
10037 09:31:26.701366 The DHCP server ip is 192.168.201.1
10038 09:31:26.701447
10039 09:31:26.707762 TFTP server IP predefined by user: 192.168.201.1
10040 09:31:26.707849
10041 09:31:26.714416 Bootfile predefined by user: 11826819/tftp-deploy-p0d7m4m5/kernel/image.itb
10042 09:31:26.714509
10043 09:31:26.717971 Sending tftp read request... done.
10044 09:31:26.718145
10045 09:31:26.722622 Waiting for the transfer...
10046 09:31:26.722810
10047 09:31:27.399978 00000000 ################################################################
10048 09:31:27.400502
10049 09:31:28.098225 00080000 ################################################################
10050 09:31:28.098737
10051 09:31:28.745689 00100000 ################################################################
10052 09:31:28.746186
10053 09:31:29.436015 00180000 ################################################################
10054 09:31:29.436535
10055 09:31:30.142027 00200000 ################################################################
10056 09:31:30.142601
10057 09:31:30.846877 00280000 ################################################################
10058 09:31:30.847441
10059 09:31:31.539176 00300000 ################################################################
10060 09:31:31.539710
10061 09:31:32.242030 00380000 ################################################################
10062 09:31:32.242567
10063 09:31:32.949458 00400000 ################################################################
10064 09:31:32.949987
10065 09:31:33.632792 00480000 ################################################################
10066 09:31:33.633311
10067 09:31:34.323635 00500000 ################################################################
10068 09:31:34.324154
10069 09:31:35.021932 00580000 ################################################################
10070 09:31:35.022456
10071 09:31:35.727571 00600000 ################################################################
10072 09:31:35.728090
10073 09:31:36.411708 00680000 ################################################################
10074 09:31:36.412242
10075 09:31:37.121947 00700000 ################################################################
10076 09:31:37.122463
10077 09:31:37.821094 00780000 ################################################################
10078 09:31:37.821631
10079 09:31:38.498055 00800000 ################################################################
10080 09:31:38.498579
10081 09:31:39.211786 00880000 ################################################################
10082 09:31:39.212293
10083 09:31:39.914997 00900000 ################################################################
10084 09:31:39.915531
10085 09:31:40.623110 00980000 ################################################################
10086 09:31:40.623647
10087 09:31:41.313973 00a00000 ################################################################
10088 09:31:41.314494
10089 09:31:41.964792 00a80000 ################################################################
10090 09:31:41.964947
10091 09:31:42.649378 00b00000 ################################################################
10092 09:31:42.649902
10093 09:31:43.341961 00b80000 ################################################################
10094 09:31:43.342543
10095 09:31:44.049407 00c00000 ################################################################
10096 09:31:44.049910
10097 09:31:44.751288 00c80000 ################################################################
10098 09:31:44.751822
10099 09:31:45.430768 00d00000 ################################################################
10100 09:31:45.431393
10101 09:31:46.124286 00d80000 ################################################################
10102 09:31:46.124794
10103 09:31:46.811503 00e00000 ################################################################
10104 09:31:46.812051
10105 09:31:47.482414 00e80000 ################################################################
10106 09:31:47.482945
10107 09:31:48.172543 00f00000 ################################################################
10108 09:31:48.173058
10109 09:31:48.867774 00f80000 ################################################################
10110 09:31:48.868417
10111 09:31:49.509950 01000000 ################################################################
10112 09:31:49.510476
10113 09:31:50.233309 01080000 ################################################################
10114 09:31:50.233835
10115 09:31:50.946763 01100000 ################################################################
10116 09:31:50.947353
10117 09:31:51.652843 01180000 ################################################################
10118 09:31:51.653344
10119 09:31:52.374176 01200000 ################################################################
10120 09:31:52.374729
10121 09:31:53.091680 01280000 ################################################################
10122 09:31:53.092233
10123 09:31:53.798978 01300000 ################################################################
10124 09:31:53.799561
10125 09:31:54.509243 01380000 ################################################################
10126 09:31:54.509754
10127 09:31:55.224292 01400000 ################################################################
10128 09:31:55.224823
10129 09:31:55.945015 01480000 ################################################################
10130 09:31:55.945540
10131 09:31:56.648468 01500000 ################################################################
10132 09:31:56.648981
10133 09:31:57.310759 01580000 ################################################################
10134 09:31:57.311338
10135 09:31:58.001701 01600000 ################################################################
10136 09:31:58.002235
10137 09:31:58.694818 01680000 ################################################################
10138 09:31:58.695382
10139 09:31:59.393741 01700000 ################################################################
10140 09:31:59.394288
10141 09:32:00.075045 01780000 ################################################################
10142 09:32:00.075603
10143 09:32:00.780119 01800000 ################################################################
10144 09:32:00.780651
10145 09:32:01.452483 01880000 ################################################################
10146 09:32:01.453030
10147 09:32:02.149558 01900000 ################################################################
10148 09:32:02.150068
10149 09:32:02.828572 01980000 ################################################################
10150 09:32:02.829091
10151 09:32:03.536449 01a00000 ################################################################
10152 09:32:03.536962
10153 09:32:04.201319 01a80000 ################################################################
10154 09:32:04.201540
10155 09:32:04.860296 01b00000 ################################################################
10156 09:32:04.860837
10157 09:32:05.566419 01b80000 ################################################################
10158 09:32:05.566944
10159 09:32:06.224087 01c00000 ################################################################
10160 09:32:06.224227
10161 09:32:06.786658 01c80000 ################################################################
10162 09:32:06.786813
10163 09:32:07.350572 01d00000 ################################################################
10164 09:32:07.350723
10165 09:32:07.908379 01d80000 ################################################################
10166 09:32:07.908527
10167 09:32:08.467368 01e00000 ################################################################
10168 09:32:08.467518
10169 09:32:09.024319 01e80000 ################################################################
10170 09:32:09.024466
10171 09:32:09.576403 01f00000 ################################################################
10172 09:32:09.576552
10173 09:32:10.145177 01f80000 ################################################################
10174 09:32:10.145351
10175 09:32:10.692683 02000000 ################################################################
10176 09:32:10.692832
10177 09:32:11.249718 02080000 ################################################################
10178 09:32:11.249865
10179 09:32:11.815188 02100000 ################################################################
10180 09:32:11.815331
10181 09:32:12.371709 02180000 ################################################################
10182 09:32:12.371857
10183 09:32:12.929654 02200000 ################################################################
10184 09:32:12.929798
10185 09:32:13.484097 02280000 ################################################################
10186 09:32:13.484238
10187 09:32:14.076379 02300000 ################################################################
10188 09:32:14.076521
10189 09:32:14.645075 02380000 ################################################################
10190 09:32:14.645278
10191 09:32:15.232074 02400000 ################################################################
10192 09:32:15.232224
10193 09:32:15.819840 02480000 ################################################################
10194 09:32:15.819986
10195 09:32:16.385890 02500000 ################################################################
10196 09:32:16.386045
10197 09:32:16.991113 02580000 ################################################################
10198 09:32:16.991626
10199 09:32:17.602642 02600000 ################################################################
10200 09:32:17.602790
10201 09:32:18.174758 02680000 ################################################################
10202 09:32:18.174898
10203 09:32:18.749332 02700000 ################################################################
10204 09:32:18.749479
10205 09:32:19.311835 02780000 ################################################################
10206 09:32:19.311989
10207 09:32:19.860700 02800000 ################################################################
10208 09:32:19.860842
10209 09:32:20.431228 02880000 ################################################################
10210 09:32:20.431379
10211 09:32:20.999350 02900000 ################################################################
10212 09:32:20.999499
10213 09:32:21.568272 02980000 ################################################################
10214 09:32:21.568419
10215 09:32:22.131501 02a00000 ################################################################
10216 09:32:22.131643
10217 09:32:22.690377 02a80000 ################################################################
10218 09:32:22.690543
10219 09:32:23.254675 02b00000 ################################################################
10220 09:32:23.254826
10221 09:32:23.809113 02b80000 ################################################################
10222 09:32:23.809258
10223 09:32:24.340422 02c00000 ################################################################
10224 09:32:24.340558
10225 09:32:24.875152 02c80000 ################################################################
10226 09:32:24.875287
10227 09:32:25.402495 02d00000 ################################################################
10228 09:32:25.402653
10229 09:32:25.925098 02d80000 ################################################################
10230 09:32:25.925240
10231 09:32:26.449940 02e00000 ################################################################
10232 09:32:26.450083
10233 09:32:26.975264 02e80000 ################################################################
10234 09:32:26.975413
10235 09:32:27.509069 02f00000 ################################################################
10236 09:32:27.509220
10237 09:32:28.042323 02f80000 ################################################################
10238 09:32:28.042470
10239 09:32:28.162316 03000000 ############### done.
10240 09:32:28.162465
10241 09:32:28.165515 The bootfile was 50447562 bytes long.
10242 09:32:28.165600
10243 09:32:28.169509 Sending tftp read request... done.
10244 09:32:28.169593
10245 09:32:28.172269 Waiting for the transfer...
10246 09:32:28.172352
10247 09:32:28.172436 00000000 # done.
10248 09:32:28.172519
10249 09:32:28.182104 Command line loaded dynamically from TFTP file: 11826819/tftp-deploy-p0d7m4m5/kernel/cmdline
10250 09:32:28.182202
10251 09:32:28.195103 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10252 09:32:28.195219
10253 09:32:28.195306 Loading FIT.
10254 09:32:28.195387
10255 09:32:28.198484 Image ramdisk-1 has 39353990 bytes.
10256 09:32:28.198568
10257 09:32:28.201732 Image fdt-1 has 47278 bytes.
10258 09:32:28.201815
10259 09:32:28.205346 Image kernel-1 has 11044258 bytes.
10260 09:32:28.205429
10261 09:32:28.215198 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10262 09:32:28.215288
10263 09:32:28.231448 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10264 09:32:28.231546
10265 09:32:28.237774 Choosing best match conf-1 for compat google,spherion-rev2.
10266 09:32:28.237861
10267 09:32:28.245647 Connected to device vid:did:rid of 1ae0:0028:00
10268 09:32:28.253584
10269 09:32:28.256779 tpm_get_response: command 0x17b, return code 0x0
10270 09:32:28.256864
10271 09:32:28.263265 ec_init: CrosEC protocol v3 supported (256, 248)
10272 09:32:28.263349
10273 09:32:28.266762 tpm_cleanup: add release locality here.
10274 09:32:28.266846
10275 09:32:28.270126 Shutting down all USB controllers.
10276 09:32:28.270210
10277 09:32:28.273678 Removing current net device
10278 09:32:28.273761
10279 09:32:28.277372 Exiting depthcharge with code 4 at timestamp: 97147299
10280 09:32:28.277456
10281 09:32:28.280136 LZMA decompressing kernel-1 to 0x821a6718
10282 09:32:28.280219
10283 09:32:28.286658 LZMA decompressing kernel-1 to 0x40000000
10284 09:32:29.674965
10285 09:32:29.675208 jumping to kernel
10286 09:32:29.675713 end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10287 09:32:29.675811 start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10288 09:32:29.675885 Setting prompt string to ['Linux version [0-9]']
10289 09:32:29.675951 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10290 09:32:29.676018 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10291 09:32:29.756648
10292 09:32:29.759960 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10293 09:32:29.763687 start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10294 09:32:29.763779 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10295 09:32:29.763850 Setting prompt string to []
10296 09:32:29.763927 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10297 09:32:29.764000 Using line separator: #'\n'#
10298 09:32:29.764059 No login prompt set.
10299 09:32:29.764120 Parsing kernel messages
10300 09:32:29.764177 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10301 09:32:29.764276 [login-action] Waiting for messages, (timeout 00:03:16)
10302 09:32:29.784107 [ 0.000000] Linux version 6.1.58-cip7 (KernelCI@build-j75268-arm64-gcc-10-defconfig-arm64-chromebook-xdgcn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023
10303 09:32:29.786616 [ 0.000000] random: crng init done
10304 09:32:29.792824 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10305 09:32:29.796152 [ 0.000000] efi: UEFI not found.
10306 09:32:29.802958 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10307 09:32:29.809267 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10308 09:32:29.819479 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10309 09:32:29.829287 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10310 09:32:29.835998 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10311 09:32:29.842274 [ 0.000000] printk: bootconsole [mtk8250] enabled
10312 09:32:29.848933 [ 0.000000] NUMA: No NUMA configuration found
10313 09:32:29.856055 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10314 09:32:29.858787 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10315 09:32:29.861944 [ 0.000000] Zone ranges:
10316 09:32:29.868631 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10317 09:32:29.872101 [ 0.000000] DMA32 empty
10318 09:32:29.878442 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10319 09:32:29.881828 [ 0.000000] Movable zone start for each node
10320 09:32:29.884866 [ 0.000000] Early memory node ranges
10321 09:32:29.891552 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10322 09:32:29.898941 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10323 09:32:29.904883 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10324 09:32:29.911621 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10325 09:32:29.918468 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10326 09:32:29.924949 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10327 09:32:29.981463 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10328 09:32:29.987855 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10329 09:32:29.994254 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10330 09:32:29.997658 [ 0.000000] psci: probing for conduit method from DT.
10331 09:32:30.004092 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10332 09:32:30.007427 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10333 09:32:30.014223 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10334 09:32:30.017181 [ 0.000000] psci: SMC Calling Convention v1.2
10335 09:32:30.024290 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10336 09:32:30.027433 [ 0.000000] Detected VIPT I-cache on CPU0
10337 09:32:30.033492 [ 0.000000] CPU features: detected: GIC system register CPU interface
10338 09:32:30.040590 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10339 09:32:30.046730 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10340 09:32:30.053686 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10341 09:32:30.063236 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10342 09:32:30.070201 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10343 09:32:30.073024 [ 0.000000] alternatives: applying boot alternatives
10344 09:32:30.080058 [ 0.000000] Fallback order for Node 0: 0
10345 09:32:30.086267 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10346 09:32:30.089897 [ 0.000000] Policy zone: Normal
10347 09:32:30.103275 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10348 09:32:30.112519 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10349 09:32:30.124325 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10350 09:32:30.134189 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10351 09:32:30.140369 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10352 09:32:30.143612 <6>[ 0.000000] software IO TLB: area num 8.
10353 09:32:30.200651 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10354 09:32:30.350179 <6>[ 0.000000] Memory: 7931064K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 421704K reserved, 32768K cma-reserved)
10355 09:32:30.356667 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10356 09:32:30.363207 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10357 09:32:30.366482 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10358 09:32:30.373250 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10359 09:32:30.380080 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10360 09:32:30.383486 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10361 09:32:30.393133 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10362 09:32:30.399687 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10363 09:32:30.407018 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10364 09:32:30.413371 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10365 09:32:30.416487 <6>[ 0.000000] GICv3: 608 SPIs implemented
10366 09:32:30.419344 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10367 09:32:30.426102 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10368 09:32:30.429188 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10369 09:32:30.435630 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10370 09:32:30.448997 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10371 09:32:30.462077 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10372 09:32:30.469193 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10373 09:32:30.477090 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10374 09:32:30.489831 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10375 09:32:30.496503 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10376 09:32:30.503046 <6>[ 0.009185] Console: colour dummy device 80x25
10377 09:32:30.513214 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10378 09:32:30.519430 <6>[ 0.024418] pid_max: default: 32768 minimum: 301
10379 09:32:30.523021 <6>[ 0.029289] LSM: Security Framework initializing
10380 09:32:30.529520 <6>[ 0.034256] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 09:32:30.539007 <6>[ 0.042071] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 09:32:30.548783 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10383 09:32:30.555544 <6>[ 0.058931] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 09:32:30.562454 <6>[ 0.065268] cblist_init_generic: Setting adjustable number of callback queues.
10385 09:32:30.568996 <6>[ 0.072741] cblist_init_generic: Setting shift to 3 and lim to 1.
10386 09:32:30.572157 <6>[ 0.079181] rcu: Hierarchical SRCU implementation.
10387 09:32:30.579004 <6>[ 0.084197] rcu: Max phase no-delay instances is 1000.
10388 09:32:30.585636 <6>[ 0.091263] EFI services will not be available.
10389 09:32:30.589239 <6>[ 0.096217] smp: Bringing up secondary CPUs ...
10390 09:32:30.597593 <6>[ 0.101296] Detected VIPT I-cache on CPU1
10391 09:32:30.604270 <6>[ 0.101365] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10392 09:32:30.610781 <6>[ 0.101395] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10393 09:32:30.613899 <6>[ 0.101721] Detected VIPT I-cache on CPU2
10394 09:32:30.623666 <6>[ 0.101770] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10395 09:32:30.630190 <6>[ 0.101785] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10396 09:32:30.633486 <6>[ 0.102043] Detected VIPT I-cache on CPU3
10397 09:32:30.640192 <6>[ 0.102088] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10398 09:32:30.646792 <6>[ 0.102102] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10399 09:32:30.653853 <6>[ 0.102403] CPU features: detected: Spectre-v4
10400 09:32:30.656619 <6>[ 0.102410] CPU features: detected: Spectre-BHB
10401 09:32:30.659852 <6>[ 0.102414] Detected PIPT I-cache on CPU4
10402 09:32:30.670018 <6>[ 0.102472] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10403 09:32:30.676572 <6>[ 0.102488] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10404 09:32:30.679770 <6>[ 0.102778] Detected PIPT I-cache on CPU5
10405 09:32:30.686620 <6>[ 0.102840] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10406 09:32:30.693000 <6>[ 0.102857] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10407 09:32:30.696094 <6>[ 0.103137] Detected PIPT I-cache on CPU6
10408 09:32:30.705947 <6>[ 0.103201] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10409 09:32:30.712676 <6>[ 0.103218] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10410 09:32:30.715899 <6>[ 0.103512] Detected PIPT I-cache on CPU7
10411 09:32:30.722577 <6>[ 0.103576] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10412 09:32:30.729099 <6>[ 0.103592] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10413 09:32:30.735548 <6>[ 0.103640] smp: Brought up 1 node, 8 CPUs
10414 09:32:30.738599 <6>[ 0.245087] SMP: Total of 8 processors activated.
10415 09:32:30.746042 <6>[ 0.250038] CPU features: detected: 32-bit EL0 Support
10416 09:32:30.751888 <6>[ 0.255401] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10417 09:32:30.758602 <6>[ 0.264202] CPU features: detected: Common not Private translations
10418 09:32:30.765069 <6>[ 0.270678] CPU features: detected: CRC32 instructions
10419 09:32:30.771835 <6>[ 0.276029] CPU features: detected: RCpc load-acquire (LDAPR)
10420 09:32:30.775712 <6>[ 0.282026] CPU features: detected: LSE atomic instructions
10421 09:32:30.781656 <6>[ 0.287843] CPU features: detected: Privileged Access Never
10422 09:32:30.788197 <6>[ 0.293623] CPU features: detected: RAS Extension Support
10423 09:32:30.795101 <6>[ 0.299232] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10424 09:32:30.798354 <6>[ 0.306451] CPU: All CPU(s) started at EL2
10425 09:32:30.804880 <6>[ 0.310768] alternatives: applying system-wide alternatives
10426 09:32:30.815333 <6>[ 0.321474] devtmpfs: initialized
10427 09:32:30.831396 <6>[ 0.330229] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10428 09:32:30.837847 <6>[ 0.340185] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10429 09:32:30.843970 <6>[ 0.348196] pinctrl core: initialized pinctrl subsystem
10430 09:32:30.846964 <6>[ 0.354832] DMI not present or invalid.
10431 09:32:30.854138 <6>[ 0.359236] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10432 09:32:30.863389 <6>[ 0.366083] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10433 09:32:30.870798 <6>[ 0.373664] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10434 09:32:30.879717 <6>[ 0.381877] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10435 09:32:30.883043 <6>[ 0.390119] audit: initializing netlink subsys (disabled)
10436 09:32:30.893109 <5>[ 0.395804] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10437 09:32:30.900038 <6>[ 0.396465] thermal_sys: Registered thermal governor 'step_wise'
10438 09:32:30.906257 <6>[ 0.403770] thermal_sys: Registered thermal governor 'power_allocator'
10439 09:32:30.909497 <6>[ 0.410023] cpuidle: using governor menu
10440 09:32:30.916081 <6>[ 0.420984] NET: Registered PF_QIPCRTR protocol family
10441 09:32:30.922624 <6>[ 0.426464] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10442 09:32:30.929292 <6>[ 0.433567] ASID allocator initialised with 32768 entries
10443 09:32:30.932942 <6>[ 0.440124] Serial: AMBA PL011 UART driver
10444 09:32:30.943464 <4>[ 0.448883] Trying to register duplicate clock ID: 134
10445 09:32:30.997039 <6>[ 0.506669] KASLR enabled
10446 09:32:31.011363 <6>[ 0.514362] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10447 09:32:31.017998 <6>[ 0.521377] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10448 09:32:31.024599 <6>[ 0.527867] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10449 09:32:31.030985 <6>[ 0.534870] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10450 09:32:31.037713 <6>[ 0.541360] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10451 09:32:31.044146 <6>[ 0.548367] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10452 09:32:31.050868 <6>[ 0.554854] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10453 09:32:31.057400 <6>[ 0.561858] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10454 09:32:31.060626 <6>[ 0.569349] ACPI: Interpreter disabled.
10455 09:32:31.069440 <6>[ 0.575739] iommu: Default domain type: Translated
10456 09:32:31.076108 <6>[ 0.580850] iommu: DMA domain TLB invalidation policy: strict mode
10457 09:32:31.080395 <5>[ 0.587500] SCSI subsystem initialized
10458 09:32:31.086156 <6>[ 0.591667] usbcore: registered new interface driver usbfs
10459 09:32:31.092310 <6>[ 0.597398] usbcore: registered new interface driver hub
10460 09:32:31.095735 <6>[ 0.602948] usbcore: registered new device driver usb
10461 09:32:31.102970 <6>[ 0.609036] pps_core: LinuxPPS API ver. 1 registered
10462 09:32:31.112443 <6>[ 0.614230] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10463 09:32:31.116097 <6>[ 0.623575] PTP clock support registered
10464 09:32:31.119005 <6>[ 0.627817] EDAC MC: Ver: 3.0.0
10465 09:32:31.127070 <6>[ 0.632967] FPGA manager framework
10466 09:32:31.133171 <6>[ 0.636644] Advanced Linux Sound Architecture Driver Initialized.
10467 09:32:31.136774 <6>[ 0.643412] vgaarb: loaded
10468 09:32:31.142980 <6>[ 0.646570] clocksource: Switched to clocksource arch_sys_counter
10469 09:32:31.146958 <5>[ 0.653000] VFS: Disk quotas dquot_6.6.0
10470 09:32:31.152983 <6>[ 0.657185] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10471 09:32:31.156531 <6>[ 0.664354] pnp: PnP ACPI: disabled
10472 09:32:31.165107 <6>[ 0.671002] NET: Registered PF_INET protocol family
10473 09:32:31.174751 <6>[ 0.676583] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10474 09:32:31.185964 <6>[ 0.688851] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10475 09:32:31.195803 <6>[ 0.697664] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10476 09:32:31.202509 <6>[ 0.705633] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10477 09:32:31.212853 <6>[ 0.714330] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10478 09:32:31.218933 <6>[ 0.724075] TCP: Hash tables configured (established 65536 bind 65536)
10479 09:32:31.225020 <6>[ 0.730935] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 09:32:31.235455 <6>[ 0.738134] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10481 09:32:31.241866 <6>[ 0.745830] NET: Registered PF_UNIX/PF_LOCAL protocol family
10482 09:32:31.248449 <6>[ 0.752004] RPC: Registered named UNIX socket transport module.
10483 09:32:31.251797 <6>[ 0.758154] RPC: Registered udp transport module.
10484 09:32:31.258645 <6>[ 0.763085] RPC: Registered tcp transport module.
10485 09:32:31.265046 <6>[ 0.768018] RPC: Registered tcp NFSv4.1 backchannel transport module.
10486 09:32:31.268331 <6>[ 0.774683] PCI: CLS 0 bytes, default 64
10487 09:32:31.271332 <6>[ 0.779068] Unpacking initramfs...
10488 09:32:31.288070 <6>[ 0.791191] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10489 09:32:31.298355 <6>[ 0.799847] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10490 09:32:31.301467 <6>[ 0.808699] kvm [1]: IPA Size Limit: 40 bits
10491 09:32:31.308324 <6>[ 0.813230] kvm [1]: GICv3: no GICV resource entry
10492 09:32:31.311358 <6>[ 0.818249] kvm [1]: disabling GICv2 emulation
10493 09:32:31.317808 <6>[ 0.822937] kvm [1]: GIC system register CPU interface enabled
10494 09:32:31.321391 <6>[ 0.829100] kvm [1]: vgic interrupt IRQ18
10495 09:32:31.328454 <6>[ 0.833455] kvm [1]: VHE mode initialized successfully
10496 09:32:31.334236 <5>[ 0.839939] Initialise system trusted keyrings
10497 09:32:31.341621 <6>[ 0.844730] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10498 09:32:31.348412 <6>[ 0.854673] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10499 09:32:31.355042 <5>[ 0.861033] NFS: Registering the id_resolver key type
10500 09:32:31.358457 <5>[ 0.866334] Key type id_resolver registered
10501 09:32:31.365323 <5>[ 0.870749] Key type id_legacy registered
10502 09:32:31.371523 <6>[ 0.875028] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10503 09:32:31.379466 <6>[ 0.881949] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10504 09:32:31.384487 <6>[ 0.889652] 9p: Installing v9fs 9p2000 file system support
10505 09:32:31.422360 <5>[ 0.928300] Key type asymmetric registered
10506 09:32:31.425368 <5>[ 0.932629] Asymmetric key parser 'x509' registered
10507 09:32:31.435447 <6>[ 0.937770] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10508 09:32:31.438570 <6>[ 0.945383] io scheduler mq-deadline registered
10509 09:32:31.442327 <6>[ 0.950161] io scheduler kyber registered
10510 09:32:31.460844 <6>[ 0.967222] EINJ: ACPI disabled.
10511 09:32:31.493608 <4>[ 0.993127] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 09:32:31.503039 <4>[ 1.003781] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10513 09:32:31.518231 <6>[ 1.024560] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10514 09:32:31.526024 <6>[ 1.032578] printk: console [ttyS0] disabled
10515 09:32:31.554040 <6>[ 1.057223] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10516 09:32:31.561123 <6>[ 1.066686] printk: console [ttyS0] enabled
10517 09:32:31.564057 <6>[ 1.066686] printk: console [ttyS0] enabled
10518 09:32:31.571024 <6>[ 1.075578] printk: bootconsole [mtk8250] disabled
10519 09:32:31.574617 <6>[ 1.075578] printk: bootconsole [mtk8250] disabled
10520 09:32:31.580370 <6>[ 1.086809] SuperH (H)SCI(F) driver initialized
10521 09:32:31.583702 <6>[ 1.092068] msm_serial: driver initialized
10522 09:32:31.598334 <6>[ 1.101034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10523 09:32:31.608285 <6>[ 1.109591] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10524 09:32:31.614492 <6>[ 1.118132] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10525 09:32:31.624663 <6>[ 1.126763] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10526 09:32:31.634173 <6>[ 1.135474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10527 09:32:31.641056 <6>[ 1.144194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10528 09:32:31.650827 <6>[ 1.152735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10529 09:32:31.657442 <6>[ 1.161536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10530 09:32:31.667378 <6>[ 1.170083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10531 09:32:31.679464 <6>[ 1.185334] loop: module loaded
10532 09:32:31.685765 <6>[ 1.191288] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10533 09:32:31.708165 <4>[ 1.214380] mtk-pmic-keys: Failed to locate of_node [id: -1]
10534 09:32:31.715071 <6>[ 1.221151] megasas: 07.719.03.00-rc1
10535 09:32:31.724568 <6>[ 1.230727] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10536 09:32:31.735497 <6>[ 1.241938] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10537 09:32:31.752091 <6>[ 1.258414] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10538 09:32:31.808261 <6>[ 1.308219] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10539 09:32:32.869763 <6>[ 2.376429] Freeing initrd memory: 38424K
10540 09:32:32.880089 <6>[ 2.386770] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10541 09:32:32.891636 <6>[ 2.397660] tun: Universal TUN/TAP device driver, 1.6
10542 09:32:32.894303 <6>[ 2.403723] thunder_xcv, ver 1.0
10543 09:32:32.897696 <6>[ 2.407227] thunder_bgx, ver 1.0
10544 09:32:32.901172 <6>[ 2.410721] nicpf, ver 1.0
10545 09:32:32.911599 <6>[ 2.414761] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10546 09:32:32.915290 <6>[ 2.422237] hns3: Copyright (c) 2017 Huawei Corporation.
10547 09:32:32.921731 <6>[ 2.427826] hclge is initializing
10548 09:32:32.924893 <6>[ 2.431401] e1000: Intel(R) PRO/1000 Network Driver
10549 09:32:32.931662 <6>[ 2.436529] e1000: Copyright (c) 1999-2006 Intel Corporation.
10550 09:32:32.935617 <6>[ 2.442540] e1000e: Intel(R) PRO/1000 Network Driver
10551 09:32:32.941221 <6>[ 2.447756] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10552 09:32:32.947955 <6>[ 2.453944] igb: Intel(R) Gigabit Ethernet Network Driver
10553 09:32:32.954455 <6>[ 2.459594] igb: Copyright (c) 2007-2014 Intel Corporation.
10554 09:32:32.961506 <6>[ 2.465433] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10555 09:32:32.967876 <6>[ 2.471950] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10556 09:32:32.971322 <6>[ 2.478412] sky2: driver version 1.30
10557 09:32:32.977595 <6>[ 2.483432] VFIO - User Level meta-driver version: 0.3
10558 09:32:32.985230 <6>[ 2.491665] usbcore: registered new interface driver usb-storage
10559 09:32:32.992265 <6>[ 2.498110] usbcore: registered new device driver onboard-usb-hub
10560 09:32:33.000832 <6>[ 2.507239] mt6397-rtc mt6359-rtc: registered as rtc0
10561 09:32:33.011012 <6>[ 2.512705] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-20T09:32:33 UTC (1697794353)
10562 09:32:33.014231 <6>[ 2.522276] i2c_dev: i2c /dev entries driver
10563 09:32:33.031008 <6>[ 2.534078] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10564 09:32:33.051274 <6>[ 2.557068] cpu cpu0: EM: created perf domain
10565 09:32:33.053827 <6>[ 2.561982] cpu cpu4: EM: created perf domain
10566 09:32:33.061460 <6>[ 2.567569] sdhci: Secure Digital Host Controller Interface driver
10567 09:32:33.067781 <6>[ 2.574001] sdhci: Copyright(c) Pierre Ossman
10568 09:32:33.074786 <6>[ 2.578952] Synopsys Designware Multimedia Card Interface Driver
10569 09:32:33.080867 <6>[ 2.585583] sdhci-pltfm: SDHCI platform and OF driver helper
10570 09:32:33.084315 <6>[ 2.585690] mmc0: CQHCI version 5.10
10571 09:32:33.091038 <6>[ 2.595702] ledtrig-cpu: registered to indicate activity on CPUs
10572 09:32:33.097838 <6>[ 2.602663] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10573 09:32:33.104156 <6>[ 2.609715] usbcore: registered new interface driver usbhid
10574 09:32:33.107752 <6>[ 2.615540] usbhid: USB HID core driver
10575 09:32:33.113860 <6>[ 2.619743] spi_master spi0: will run message pump with realtime priority
10576 09:32:33.157933 <6>[ 2.657739] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10577 09:32:33.177541 <6>[ 2.673573] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10578 09:32:33.184572 <6>[ 2.689700] cros-ec-spi spi0.0: Chrome EC device registered
10579 09:32:33.187580 <6>[ 2.695740] mmc0: Command Queue Engine enabled
10580 09:32:33.194422 <6>[ 2.700479] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10581 09:32:33.201621 <6>[ 2.708019] mmcblk0: mmc0:0001 DA4128 116 GiB
10582 09:32:33.212253 <6>[ 2.718629] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10583 09:32:33.221946 <6>[ 2.723067] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 09:32:33.228774 <6>[ 2.725820] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10585 09:32:33.231995 <6>[ 2.735115] NET: Registered PF_PACKET protocol family
10586 09:32:33.238653 <6>[ 2.739804] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10587 09:32:33.241962 <6>[ 2.744457] 9pnet: Installing 9P2000 support
10588 09:32:33.248885 <6>[ 2.750319] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10589 09:32:33.255870 <5>[ 2.754167] Key type dns_resolver registered
10590 09:32:33.258677 <6>[ 2.765603] registered taskstats version 1
10591 09:32:33.264730 <5>[ 2.769982] Loading compiled-in X.509 certificates
10592 09:32:33.292519 <4>[ 2.791295] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 09:32:33.301620 <4>[ 2.802036] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 09:32:33.308550 <3>[ 2.812577] debugfs: File 'uA_load' in directory '/' already present!
10595 09:32:33.314642 <3>[ 2.819282] debugfs: File 'min_uV' in directory '/' already present!
10596 09:32:33.322003 <3>[ 2.825941] debugfs: File 'max_uV' in directory '/' already present!
10597 09:32:33.328386 <3>[ 2.832560] debugfs: File 'constraint_flags' in directory '/' already present!
10598 09:32:33.338673 <3>[ 2.842024] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10599 09:32:33.350181 <6>[ 2.856555] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10600 09:32:33.356976 <6>[ 2.863341] xhci-mtk 11200000.usb: xHCI Host Controller
10601 09:32:33.363704 <6>[ 2.868833] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10602 09:32:33.373363 <6>[ 2.876656] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10603 09:32:33.380036 <6>[ 2.886098] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10604 09:32:33.386815 <6>[ 2.892182] xhci-mtk 11200000.usb: xHCI Host Controller
10605 09:32:33.393862 <6>[ 2.897660] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10606 09:32:33.400307 <6>[ 2.905311] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10607 09:32:33.407031 <6>[ 2.913143] hub 1-0:1.0: USB hub found
10608 09:32:33.410086 <6>[ 2.917163] hub 1-0:1.0: 1 port detected
10609 09:32:33.419818 <6>[ 2.921431] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10610 09:32:33.423218 <6>[ 2.930202] hub 2-0:1.0: USB hub found
10611 09:32:33.426544 <6>[ 2.934224] hub 2-0:1.0: 1 port detected
10612 09:32:33.436884 <6>[ 2.942634] mtk-msdc 11f70000.mmc: Got CD GPIO
10613 09:32:33.446110 <6>[ 2.949118] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10614 09:32:33.452650 <6>[ 2.957144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10615 09:32:33.462551 <4>[ 2.965051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10616 09:32:33.472465 <6>[ 2.974585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10617 09:32:33.479544 <6>[ 2.982661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10618 09:32:33.485742 <6>[ 2.990729] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10619 09:32:33.495472 <6>[ 2.998644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10620 09:32:33.502375 <6>[ 3.006461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10621 09:32:33.511987 <6>[ 3.014280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10622 09:32:33.522110 <6>[ 3.024699] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10623 09:32:33.528447 <6>[ 3.033056] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10624 09:32:33.538858 <6>[ 3.041408] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10625 09:32:33.545481 <6>[ 3.049750] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10626 09:32:33.555466 <6>[ 3.058088] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10627 09:32:33.561502 <6>[ 3.066426] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10628 09:32:33.571436 <6>[ 3.074764] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10629 09:32:33.581926 <6>[ 3.083102] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10630 09:32:33.588157 <6>[ 3.091441] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10631 09:32:33.597903 <6>[ 3.099778] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10632 09:32:33.604666 <6>[ 3.108117] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10633 09:32:33.614585 <6>[ 3.116456] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10634 09:32:33.621198 <6>[ 3.124797] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10635 09:32:33.631134 <6>[ 3.133136] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10636 09:32:33.637440 <6>[ 3.141475] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10637 09:32:33.644512 <6>[ 3.150204] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10638 09:32:33.650920 <6>[ 3.157344] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10639 09:32:33.658289 <6>[ 3.164121] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10640 09:32:33.668161 <6>[ 3.170885] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10641 09:32:33.674277 <6>[ 3.177824] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10642 09:32:33.680956 <6>[ 3.184678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10643 09:32:33.690812 <6>[ 3.193811] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10644 09:32:33.700754 <6>[ 3.202930] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10645 09:32:33.710490 <6>[ 3.212225] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10646 09:32:33.720539 <6>[ 3.221692] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10647 09:32:33.730747 <6>[ 3.231159] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10648 09:32:33.736927 <6>[ 3.240279] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10649 09:32:33.747107 <6>[ 3.249752] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10650 09:32:33.756917 <6>[ 3.258873] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10651 09:32:33.766818 <6>[ 3.268169] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10652 09:32:33.776297 <6>[ 3.278329] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10653 09:32:33.786866 <6>[ 3.289824] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10654 09:32:33.835544 <6>[ 3.338844] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10655 09:32:33.990021 <6>[ 3.496714] hub 1-1:1.0: USB hub found
10656 09:32:33.993946 <6>[ 3.501215] hub 1-1:1.0: 4 ports detected
10657 09:32:34.115876 <6>[ 3.619026] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10658 09:32:34.142028 <6>[ 3.648631] hub 2-1:1.0: USB hub found
10659 09:32:34.145770 <6>[ 3.653148] hub 2-1:1.0: 3 ports detected
10660 09:32:34.315708 <6>[ 3.818842] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10661 09:32:34.447881 <6>[ 3.953926] hub 1-1.4:1.0: USB hub found
10662 09:32:34.450782 <6>[ 3.958462] hub 1-1.4:1.0: 2 ports detected
10663 09:32:34.527593 <6>[ 4.031090] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10664 09:32:34.747640 <6>[ 4.250874] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10665 09:32:34.939681 <6>[ 4.442865] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10666 09:32:46.089136 <6>[ 15.599891] ALSA device list:
10667 09:32:46.095684 <6>[ 15.603187] No soundcards found.
10668 09:32:46.103557 <6>[ 15.611156] Freeing unused kernel memory: 8384K
10669 09:32:46.106731 <6>[ 15.616143] Run /init as init process
10670 09:32:46.157171 <6>[ 15.664611] NET: Registered PF_INET6 protocol family
10671 09:32:46.164144 <6>[ 15.670993] Segment Routing with IPv6
10672 09:32:46.167313 <6>[ 15.674952] In-situ OAM (IOAM) with IPv6
10673 09:32:46.202766 <30>[ 15.690026] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10674 09:32:46.206189 <30>[ 15.714054] systemd[1]: Detected architecture arm64.
10675 09:32:46.209341
10676 09:32:46.212269 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10677 09:32:46.212690
10678 09:32:46.227283 <30>[ 15.734949] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10679 09:32:46.405072 <30>[ 15.909186] systemd[1]: Queued start job for default target Graphical Interface.
10680 09:32:46.440085 <30>[ 15.947646] systemd[1]: Created slice system-getty.slice.
10681 09:32:46.447273 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10682 09:32:46.464059 <30>[ 15.971560] systemd[1]: Created slice system-modprobe.slice.
10683 09:32:46.471259 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10684 09:32:46.488313 <30>[ 15.995647] systemd[1]: Created slice system-serial\x2dgetty.slice.
10685 09:32:46.498589 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10686 09:32:46.512273 <30>[ 16.019356] systemd[1]: Created slice User and Session Slice.
10687 09:32:46.518523 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10688 09:32:46.539436 <30>[ 16.043374] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10689 09:32:46.549394 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10690 09:32:46.567819 <30>[ 16.071545] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10691 09:32:46.573972 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10692 09:32:46.598489 <30>[ 16.099326] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10693 09:32:46.605343 <30>[ 16.111677] systemd[1]: Reached target Local Encrypted Volumes.
10694 09:32:46.611683 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10695 09:32:46.627958 <30>[ 16.135435] systemd[1]: Reached target Paths.
10696 09:32:46.634756 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10697 09:32:46.647442 <30>[ 16.154867] systemd[1]: Reached target Remote File Systems.
10698 09:32:46.654365 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10699 09:32:46.671672 <30>[ 16.179229] systemd[1]: Reached target Slices.
10700 09:32:46.678450 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10701 09:32:46.691757 <30>[ 16.198877] systemd[1]: Reached target Swap.
10702 09:32:46.695154 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10703 09:32:46.715007 <30>[ 16.219381] systemd[1]: Listening on initctl Compatibility Named Pipe.
10704 09:32:46.721864 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10705 09:32:46.728614 <30>[ 16.234669] systemd[1]: Listening on Journal Audit Socket.
10706 09:32:46.735229 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10707 09:32:46.748337 <30>[ 16.255346] systemd[1]: Listening on Journal Socket (/dev/log).
10708 09:32:46.754561 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10709 09:32:46.772532 <30>[ 16.280101] systemd[1]: Listening on Journal Socket.
10710 09:32:46.779153 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10711 09:32:46.795621 <30>[ 16.299564] systemd[1]: Listening on Network Service Netlink Socket.
10712 09:32:46.802412 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10713 09:32:46.816869 <30>[ 16.324089] systemd[1]: Listening on udev Control Socket.
10714 09:32:46.823187 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10715 09:32:46.840240 <30>[ 16.347945] systemd[1]: Listening on udev Kernel Socket.
10716 09:32:46.847043 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10717 09:32:46.895826 <30>[ 16.403093] systemd[1]: Mounting Huge Pages File System...
10718 09:32:46.903020 Mounting [0;1;39mHuge Pages File System[0m...
10719 09:32:46.918541 <30>[ 16.424877] systemd[1]: Mounting POSIX Message Queue File System...
10720 09:32:46.924531 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10721 09:32:46.946817 <30>[ 16.454427] systemd[1]: Mounting Kernel Debug File System...
10722 09:32:46.953261 Mounting [0;1;39mKernel Debug File System[0m...
10723 09:32:46.975012 <30>[ 16.479401] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10724 09:32:46.987872 <30>[ 16.492411] systemd[1]: Starting Create list of static device nodes for the current kernel...
10725 09:32:46.994494 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10726 09:32:47.015422 <30>[ 16.522990] systemd[1]: Starting Load Kernel Module configfs...
10727 09:32:47.021673 Starting [0;1;39mLoad Kernel Module configfs[0m...
10728 09:32:47.039178 <30>[ 16.546937] systemd[1]: Starting Load Kernel Module drm...
10729 09:32:47.046006 Starting [0;1;39mLoad Kernel Module drm[0m...
10730 09:32:47.063201 <30>[ 16.566972] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10731 09:32:47.076661 <30>[ 16.584493] systemd[1]: Starting Journal Service...
10732 09:32:47.080176 Starting [0;1;39mJournal Service[0m...
10733 09:32:47.102052 <30>[ 16.609462] systemd[1]: Starting Load Kernel Modules...
10734 09:32:47.108245 Starting [0;1;39mLoad Kernel Modules[0m...
10735 09:32:47.135069 <30>[ 16.639275] systemd[1]: Starting Remount Root and Kernel File Systems...
10736 09:32:47.141438 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10737 09:32:47.158247 <30>[ 16.665906] systemd[1]: Starting Coldplug All udev Devices...
10738 09:32:47.164617 Starting [0;1;39mColdplug All udev Devices[0m...
10739 09:32:47.187229 <30>[ 16.694214] systemd[1]: Started Journal Service.
10740 09:32:47.193304 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10741 09:32:47.213202 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10742 09:32:47.227907 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10743 09:32:47.248191 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10744 09:32:47.268972 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10745 09:32:47.285595 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10746 09:32:47.306318 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10747 09:32:47.325255 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10748 09:32:47.345667 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10749 09:32:47.359636 See 'systemctl status systemd-remount-fs.service' for details.
10750 09:32:47.415108 Mounting [0;1;39mKernel Configuration File System[0m...
10751 09:32:47.436348 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10752 09:32:47.449528 <46>[ 16.954386] systemd-journald[182]: Received client request to flush runtime journal.
10753 09:32:47.461487 Starting [0;1;39mLoad/Save Random Seed[0m...
10754 09:32:47.480699 Starting [0;1;39mApply Kernel Variables[0m...
10755 09:32:47.501451 Starting [0;1;39mCreate System Users[0m...
10756 09:32:47.521173 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10757 09:32:47.536332 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10758 09:32:47.556461 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10759 09:32:47.569198 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10760 09:32:47.585137 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10761 09:32:47.601418 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10762 09:32:47.648522 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10763 09:32:47.671891 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10764 09:32:47.688621 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10765 09:32:47.707023 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10766 09:32:47.760893 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10767 09:32:47.790911 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10768 09:32:47.813767 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10769 09:32:47.835175 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10770 09:32:47.901914 Starting [0;1;39mNetwork Service[0m...
10771 09:32:47.929570 Starting [0;1;39mNetwork Time Synchronization[0m...
10772 09:32:47.953280 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10773 09:32:47.985761 <6>[ 17.489539] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10774 09:32:47.988659 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10775 09:32:48.000133 <6>[ 17.504189] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10776 09:32:48.009816 <6>[ 17.513080] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10777 09:32:48.030024 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10778 09:32:48.044555 <4>[ 17.548326] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10779 09:32:48.050751 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10780 09:32:48.057865 <4>[ 17.563708] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10781 09:32:48.075602 <3>[ 17.579227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 09:32:48.081671 <3>[ 17.587371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 09:32:48.091671 <3>[ 17.587376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 09:32:48.098539 <3>[ 17.596335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 09:32:48.107984 <3>[ 17.612025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 09:32:48.111064 <6>[ 17.619225] mc: Linux media interface: v0.10
10787 09:32:48.121158 <3>[ 17.620364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 09:32:48.131243 [[0;32m OK [<3>[ 17.632892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 09:32:48.138175 0m] Found device<3>[ 17.642203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 09:32:48.148205 [0;1;39m/dev/t<6>[ 17.644790] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10791 09:32:48.148720 tyS0[0m.
10792 09:32:48.157522 <3>[ 17.652360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 09:32:48.160831 <6>[ 17.653486] videodev: Linux video capture interface: v2.00
10794 09:32:48.170974 <6>[ 17.657219] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10795 09:32:48.174753 <6>[ 17.660004] pci_bus 0000:00: root bus resource [bus 00-ff]
10796 09:32:48.180297 <6>[ 17.663080] usbcore: registered new interface driver r8152
10797 09:32:48.190898 <6>[ 17.667774] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10798 09:32:48.200689 <6>[ 17.668162] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10799 09:32:48.207710 <3>[ 17.669080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 09:32:48.217001 <6>[ 17.674846] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10801 09:32:48.224331 <3>[ 17.682384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 09:32:48.230411 <3>[ 17.682389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 09:32:48.240162 <3>[ 17.682462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 09:32:48.250359 <6>[ 17.683066] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10805 09:32:48.260550 <6>[ 17.688372] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10806 09:32:48.266681 <3>[ 17.694168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 09:32:48.273335 <6>[ 17.704106] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10808 09:32:48.282998 <3>[ 17.713047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 09:32:48.290026 <3>[ 17.713059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 09:32:48.299819 <3>[ 17.713064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 09:32:48.306343 <3>[ 17.713110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 09:32:48.312646 <6>[ 17.721549] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10813 09:32:48.319397 <6>[ 17.735917] Bluetooth: Core ver 2.22
10814 09:32:48.322724 <6>[ 17.736703] pci 0000:00:00.0: supports D1 D2
10815 09:32:48.329798 <6>[ 17.737029] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10816 09:32:48.336614 <6>[ 17.743058] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10817 09:32:48.343384 <6>[ 17.748305] NET: Registered PF_BLUETOOTH protocol family
10818 09:32:48.350355 <6>[ 17.752716] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10819 09:32:48.357024 <6>[ 17.762039] Bluetooth: HCI device and connection manager initialized
10820 09:32:48.363370 <6>[ 17.763160] usbcore: registered new interface driver cdc_ether
10821 09:32:48.370357 <4>[ 17.764313] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10822 09:32:48.377486 <4>[ 17.764313] Fallback method does not support PEC.
10823 09:32:48.381139 <6>[ 17.772275] remoteproc remoteproc0: scp is available
10824 09:32:48.387885 <6>[ 17.780080] Bluetooth: HCI socket layer initialized
10825 09:32:48.391026 <6>[ 17.780090] Bluetooth: L2CAP socket layer initialized
10826 09:32:48.398057 <6>[ 17.780124] Bluetooth: SCO socket layer initialized
10827 09:32:48.405344 <6>[ 17.796923] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10828 09:32:48.409034 <6>[ 17.803175] remoteproc remoteproc0: powering up scp
10829 09:32:48.415444 <6>[ 17.803419] usbcore: registered new interface driver r8153_ecm
10830 09:32:48.425607 <4>[ 17.805892] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10831 09:32:48.432754 <4>[ 17.805907] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10832 09:32:48.438850 <6>[ 17.811874] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10833 09:32:48.449291 <6>[ 17.819479] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10834 09:32:48.456017 <6>[ 17.826887] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10835 09:32:48.462093 <6>[ 17.828384] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10836 09:32:48.469612 <6>[ 17.828550] usbcore: registered new interface driver btusb
10837 09:32:48.479338 <4>[ 17.829106] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10838 09:32:48.485798 <3>[ 17.829128] Bluetooth: hci0: Failed to load firmware file (-2)
10839 09:32:48.489192 <3>[ 17.829133] Bluetooth: hci0: Failed to set up firmware (-2)
10840 09:32:48.503201 <4>[ 17.829140] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10841 09:32:48.513410 <6>[ 17.830272] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10842 09:32:48.520540 <6>[ 17.830419] usbcore: registered new interface driver uvcvideo
10843 09:32:48.526544 <6>[ 17.831101] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10844 09:32:48.533212 <6>[ 17.834199] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10845 09:32:48.540228 <6>[ 17.835297] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10846 09:32:48.548217 <6>[ 17.835322] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10847 09:32:48.550161 <6>[ 17.850852] r8152 2-1.3:1.0 eth0: v1.12.13
10848 09:32:48.557099 <6>[ 17.855581] pci 0000:01:00.0: supports D1 D2
10849 09:32:48.564216 <3>[ 17.860592] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 09:32:48.571237 <3>[ 17.861449] power_supply sbs-5-000b: driver failed to report `health' property: -6
10851 09:32:48.577461 <6>[ 17.868767] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10852 09:32:48.584054 <6>[ 17.868788] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10853 09:32:48.593912 <3>[ 17.892495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 09:32:48.600251 <6>[ 17.906691] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10855 09:32:48.610452 <3>[ 17.915161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 09:32:48.617374 <6>[ 17.917621] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10857 09:32:48.627688 <3>[ 17.924486] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10858 09:32:48.633862 <6>[ 17.928799] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10859 09:32:48.641461 <6>[ 17.928807] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10860 09:32:48.651512 <6>[ 17.928820] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10861 09:32:48.658452 <3>[ 17.945617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 09:32:48.668405 <6>[ 17.945931] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10863 09:32:48.675239 <6>[ 17.968459] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10864 09:32:48.682609 <6>[ 17.968489] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10865 09:32:48.688765 <6>[ 17.968496] remoteproc remoteproc0: remote processor scp is now up
10866 09:32:48.695369 <6>[ 17.975106] pci 0000:00:00.0: PCI bridge to [bus 01]
10867 09:32:48.702235 <6>[ 17.975111] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10868 09:32:48.711966 <3>[ 17.983565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 09:32:48.719494 <6>[ 17.991564] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10870 09:32:48.726122 <6>[ 17.992778] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10871 09:32:48.735902 <6>[ 17.995571] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10872 09:32:48.742042 <3>[ 18.019068] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 09:32:48.748173 <6>[ 18.026703] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10874 09:32:48.758571 <3>[ 18.054074] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 09:32:48.764775 <6>[ 18.059976] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10876 09:32:48.771750 <3>[ 18.085259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 09:32:48.781606 <5>[ 18.100347] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10878 09:32:48.787631 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10879 09:32:48.807053 <5>[ 18.310651] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10880 09:32:48.813707 <4>[ 18.317539] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10881 09:32:48.819383 <6>[ 18.326420] cfg80211: failed to load regulatory.db
10882 09:32:48.825774 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10883 09:32:48.840037 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10884 09:32:48.859279 <6>[ 18.363758] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10885 09:32:48.866107 <6>[ 18.371256] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10886 09:32:48.890665 <6>[ 18.397907] mt7921e 0000:01:00.0: ASIC revision: 79610010
10887 09:32:48.900270 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10888 09:32:48.922894 Starting [0;1;39mNetwork Name Resolution[0m...
10889 09:32:48.945572 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10890 09:32:48.980056 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10891 09:32:48.997112 <4>[ 18.498535] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10892 09:32:49.069043 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10893 09:32:49.083680 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10894 09:32:49.103910 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10895 09:32:49.116428 <4>[ 18.617295] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10896 09:32:49.123420 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10897 09:32:49.147676 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10898 09:32:49.166450 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10899 09:32:49.180129 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10900 09:32:49.199296 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10901 09:32:49.211297 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10902 09:32:49.238074 [[0;32m OK [0m] Reached targ<4>[ 18.737439] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10903 09:32:49.241802 et [0;1;39mBasic System[0m.
10904 09:32:49.260413 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10905 09:32:49.300860 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10906 09:32:49.335164 Starting [0;1;39mUser Login Management[0m...
10907 09:32:49.356480 <4>[ 18.857767] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 09:32:49.373889 Starting [0;1;39mPermit User Sessions[0m...
10909 09:32:49.394910 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10910 09:32:49.413589 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10911 09:32:49.432382 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10912 09:32:49.448402 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10913 09:32:49.480564 <4>[ 18.981968] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10914 09:32:49.513457 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10915 09:32:49.532078 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10916 09:32:49.547877 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10917 09:32:49.563768 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10918 09:32:49.580522 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10919 09:32:49.599931 <4>[ 19.101421] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10920 09:32:49.666062 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10921 09:32:49.706783 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10922 09:32:49.720691 <4>[ 19.221796] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10923 09:32:49.754597
10924 09:32:49.755192
10925 09:32:49.758169 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10926 09:32:49.758581
10927 09:32:49.761184 debian-bullseye-arm64 login: root (automatic login)
10928 09:32:49.761601
10929 09:32:49.761932
10930 09:32:49.791547 Linux debian-bullseye-arm64 6.1.58-cip7 #1 SMP PREEMPT Fri Oct 20 09:09:55 UTC 2023 aarch64
10931 09:32:49.792136
10932 09:32:49.798226 The programs included with the Debian GNU/Linux system are free software;
10933 09:32:49.805081 the exact distribution terms for each program are described in the
10934 09:32:49.808251 individual files in /usr/share/doc/*/copyright.
10935 09:32:49.808778
10936 09:32:49.814576 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10937 09:32:49.817840 permitted by applicable law.
10938 09:32:49.819653 Matched prompt #10: / #
10940 09:32:49.821269 Setting prompt string to ['/ #']
10941 09:32:49.821734 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10943 09:32:49.822989 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10944 09:32:49.823640 start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
10945 09:32:49.824182 Setting prompt string to ['/ #']
10946 09:32:49.824520 Forcing a shell prompt, looking for ['/ #']
10948 09:32:49.875283 / #
10949 09:32:49.875897 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10950 09:32:49.876322 Waiting using forced prompt support (timeout 00:02:30)
10951 09:32:49.876802 <4>[ 19.341764] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10952 09:32:49.881764
10953 09:32:49.882674 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10954 09:32:49.883205 start: 2.2.7 export-device-env (timeout 00:02:56) [common]
10955 09:32:49.883669 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10956 09:32:49.884100 end: 2.2 depthcharge-retry (duration 00:02:04) [common]
10957 09:32:49.884512 end: 2 depthcharge-action (duration 00:02:04) [common]
10958 09:32:49.884964 start: 3 lava-test-retry (timeout 00:07:36) [common]
10959 09:32:49.885386 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
10960 09:32:49.885750 Using namespace: common
10962 09:32:49.987128 / # #
10963 09:32:49.987730 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10964 09:32:49.988276 #<4>[ 19.465844] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 09:32:49.993690
10966 09:32:49.994510 Using /lava-11826819
10968 09:32:50.095624 / # export SHELL=/bin/sh
10969 09:32:50.096301 <6>[ 19.540570] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
10970 09:32:50.096671 <6>[ 19.548623] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10971 09:32:50.096997 export SHELL=/bin/sh<4>[ 19.585214] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10972 09:32:50.101695
10974 09:32:50.203166 / # . /lava-11826819/environment
10975 09:32:50.203351 . /lava-11826819/environment<3>[ 19.703274] mt7921e 0000:01:00.0: hardware init failed
10976 09:32:50.208440
10978 09:32:50.309113 / # /lava-11826819/bin/lava-test-runner /lava-11826819/0
10979 09:32:50.309687 Test shell timeout: 10s (minimum of the action and connection timeout)
10980 09:32:50.315932 /lava-11826819/bin/lava-test-runner /lava-11826819/0
10981 09:32:50.342478 + export TESTRUN_ID=0_v4l2-compliance-uvc
10982 09:32:50.346113 + cd /lava-11826819/0/tests/0_v4l2-compliance-uvc
10983 09:32:50.346648 + cat uuid
10984 09:32:50.349533 + UUID=11826819_1.5.2.3.1
10985 09:32:50.349969 + set +x
10986 09:32:50.356327 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 11826819_1.5.2.3.1>
10987 09:32:50.357318 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 11826819_1.5.2.3.1
10988 09:32:50.357734 Starting test lava.0_v4l2-compliance-uvc (11826819_1.5.2.3.1)
10989 09:32:50.358263 Skipping test definition patterns.
10990 09:32:50.359262 + /usr/bin/v4l2-parser.sh -d uvcvideo
10991 09:32:50.365653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10992 09:32:50.366088 device: /dev/video0
10993 09:32:50.366779 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10995 09:32:56.845887 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10996 09:32:56.858799 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10997 09:32:56.865311
10998 09:32:56.880662 Compliance test for uvcvideo device /dev/video0:
10999 09:32:56.892392
11000 09:32:56.903881 Driver Info:
11001 09:32:56.915656 Driver name : uvcvideo
11002 09:32:56.930206 Card type : HD User Facing: HD User Facing
11003 09:32:56.945345 Bus info : usb-11200000.usb-1.4.1
11004 09:32:56.953738 Driver version : 6.1.58
11005 09:32:56.966118 Capabilities : 0x84a00001
11006 09:32:56.983655 Metadata Capture
11007 09:32:56.993983 Streaming
11008 09:32:57.005513 Extended Pix Format
11009 09:32:57.016954 Device Capabilities
11010 09:32:57.030216 Device Caps : 0x04200001
11011 09:32:57.044729 Streaming
11012 09:32:57.056941 Extended Pix Format
11013 09:32:57.069207 Media Driver Info:
11014 09:32:57.084498 Driver name : uvcvideo
11015 09:32:57.097933 Model : HD User Facing: HD User Facing
11016 09:32:57.106686 Serial : 200901010001
11017 09:32:57.121481 Bus info : usb-11200000.usb-1.4.1
11018 09:32:57.130004 Media version : 6.1.58
11019 09:32:57.146711 Hardware revision: 0x00009758 (38744)
11020 09:32:57.156029 Driver version : 6.1.58
11021 09:32:57.165778 Interface Info:
11022 09:32:57.182558 <LAVA_SIGNAL_TESTSET START Interface-Info>
11023 09:32:57.183339 ID : 0x03000002
11024 09:32:57.184005 Received signal: <TESTSET> START Interface-Info
11025 09:32:57.184404 Starting test_set Interface-Info
11026 09:32:57.193512 Type : V4L Video
11027 09:32:57.204098 Entity Info:
11028 09:32:57.212129 <LAVA_SIGNAL_TESTSET STOP>
11029 09:32:57.212975 Received signal: <TESTSET> STOP
11030 09:32:57.213368 Closing test_set Interface-Info
11031 09:32:57.221818 <LAVA_SIGNAL_TESTSET START Entity-Info>
11032 09:32:57.222641 Received signal: <TESTSET> START Entity-Info
11033 09:32:57.223024 Starting test_set Entity-Info
11034 09:32:57.224931 ID : 0x00000001 (1)
11035 09:32:57.236949 Name : HD User Facing: HD User Facing
11036 09:32:57.244031 Function : V4L2 I/O
11037 09:32:57.255732 Flags : default
11038 09:32:57.265757 Pad 0x01000007 : 0: Sink
11039 09:32:57.287826 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11040 09:32:57.288404
11041 09:32:57.300517 Required ioctls:
11042 09:32:57.309759 <LAVA_SIGNAL_TESTSET STOP>
11043 09:32:57.310436 Received signal: <TESTSET> STOP
11044 09:32:57.310787 Closing test_set Entity-Info
11045 09:32:57.320339 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11046 09:32:57.321182 Received signal: <TESTSET> START Required-ioctls
11047 09:32:57.321590 Starting test_set Required-ioctls
11048 09:32:57.323262 test MC information (see 'Media Driver Info' above): OK
11049 09:32:57.352790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11050 09:32:57.353578 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11052 09:32:57.355189 test VIDIOC_QUERYCAP: OK
11053 09:32:57.378266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11054 09:32:57.379027 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11056 09:32:57.381667 test invalid ioctls: OK
11057 09:32:57.404730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11058 09:32:57.405434
11059 09:32:57.406052 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11061 09:32:57.416719 Allow for multiple opens:
11062 09:32:57.424113 <LAVA_SIGNAL_TESTSET STOP>
11063 09:32:57.424936 Received signal: <TESTSET> STOP
11064 09:32:57.425312 Closing test_set Required-ioctls
11065 09:32:57.433497 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11066 09:32:57.434308 Received signal: <TESTSET> START Allow-for-multiple-opens
11067 09:32:57.434693 Starting test_set Allow-for-multiple-opens
11068 09:32:57.437164 test second /dev/video0 open: OK
11069 09:32:57.459264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11070 09:32:57.460103 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11072 09:32:57.462018 test VIDIOC_QUERYCAP: OK
11073 09:32:57.484416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11074 09:32:57.485241 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11076 09:32:57.486515 test VIDIOC_G/S_PRIORITY: OK
11077 09:32:57.506978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11078 09:32:57.507856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11080 09:32:57.510006 test for unlimited opens: OK
11081 09:32:57.533532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11082 09:32:57.534080
11083 09:32:57.534703 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11085 09:32:57.546020 Debug ioctls:
11086 09:32:57.553889 <LAVA_SIGNAL_TESTSET STOP>
11087 09:32:57.554720 Received signal: <TESTSET> STOP
11088 09:32:57.555161 Closing test_set Allow-for-multiple-opens
11089 09:32:57.564013 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11090 09:32:57.564848 Received signal: <TESTSET> START Debug-ioctls
11091 09:32:57.565326 Starting test_set Debug-ioctls
11092 09:32:57.567705 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11093 09:32:57.592973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11094 09:32:57.593812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11096 09:32:57.599233 test VIDIOC_LOG_STATUS: OK (Not Supported)
11097 09:32:57.624292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11098 09:32:57.624852
11099 09:32:57.625492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11101 09:32:57.635333 Input ioctls:
11102 09:32:57.642502 <LAVA_SIGNAL_TESTSET STOP>
11103 09:32:57.643357 Received signal: <TESTSET> STOP
11104 09:32:57.643909 Closing test_set Debug-ioctls
11105 09:32:57.652093 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11106 09:32:57.652924 Received signal: <TESTSET> START Input-ioctls
11107 09:32:57.653438 Starting test_set Input-ioctls
11108 09:32:57.655609 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11109 09:32:57.683172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11110 09:32:57.684006 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11112 09:32:57.686043 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11113 09:32:57.703795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11114 09:32:57.704605 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11116 09:32:57.710448 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11117 09:32:57.731286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11118 09:32:57.732111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11120 09:32:57.738128 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11121 09:32:57.759216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11122 09:32:57.760126 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11124 09:32:57.762462 test VIDIOC_G/S/ENUMINPUT: OK
11125 09:32:57.783890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11126 09:32:57.784714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11128 09:32:57.786434 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11129 09:32:57.810186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11130 09:32:57.811002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11132 09:32:57.812690 Inputs: 1 Audio Inputs: 0 Tuners: 0
11133 09:32:57.821580
11134 09:32:57.839711 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11135 09:32:57.863224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11136 09:32:57.864061 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11138 09:32:57.869536 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11139 09:32:57.892708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11140 09:32:57.893536 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11142 09:32:57.899179 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11143 09:32:57.919393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11144 09:32:57.920221 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11146 09:32:57.925857 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11147 09:32:57.944558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11148 09:32:57.945395 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11150 09:32:57.950885 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11151 09:32:57.971449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11152 09:32:57.972069
11153 09:32:57.972669 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11155 09:32:57.991130 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11156 09:32:58.013534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11157 09:32:58.014344 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11159 09:32:58.020126 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11160 09:32:58.042565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11161 09:32:58.043639 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11163 09:32:58.045658 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11164 09:32:58.064461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11165 09:32:58.065128 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11167 09:32:58.067637 test VIDIOC_G/S_EDID: OK (Not Supported)
11168 09:32:58.090331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11169 09:32:58.090836
11170 09:32:58.091458 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11172 09:32:58.102000 Control ioctls (Input 0):
11173 09:32:58.111865 <LAVA_SIGNAL_TESTSET STOP>
11174 09:32:58.112632 Received signal: <TESTSET> STOP
11175 09:32:58.112981 Closing test_set Input-ioctls
11176 09:32:58.124072 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11177 09:32:58.124901 Received signal: <TESTSET> START Control-ioctls-Input-0
11178 09:32:58.125292 Starting test_set Control-ioctls-Input-0
11179 09:32:58.127137 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11180 09:32:58.153689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11181 09:32:58.154248 test VIDIOC_QUERYCTRL: OK
11182 09:32:58.154884 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11184 09:32:58.175468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11185 09:32:58.176297 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11187 09:32:58.177904 test VIDIOC_G/S_CTRL: OK
11188 09:32:58.202718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11189 09:32:58.203589 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11191 09:32:58.205421 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11192 09:32:58.228239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11193 09:32:58.229075 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11195 09:32:58.234733 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11196 09:32:58.257235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11197 09:32:58.258047 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11199 09:32:58.260616 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11200 09:32:58.279264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11201 09:32:58.280081 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11203 09:32:58.282759 Standard Controls: 16 Private Controls: 0
11204 09:32:58.291643
11205 09:32:58.302806 Format ioctls (Input 0):
11206 09:32:58.309792 <LAVA_SIGNAL_TESTSET STOP>
11207 09:32:58.310861 Received signal: <TESTSET> STOP
11208 09:32:58.311356 Closing test_set Control-ioctls-Input-0
11209 09:32:58.319766 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11210 09:32:58.320622 Received signal: <TESTSET> START Format-ioctls-Input-0
11211 09:32:58.321012 Starting test_set Format-ioctls-Input-0
11212 09:32:58.323466 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11213 09:32:58.347712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11214 09:32:58.348546 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11216 09:32:58.351326 test VIDIOC_G/S_PARM: OK
11217 09:32:58.372415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11218 09:32:58.373245 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11220 09:32:58.375680 test VIDIOC_G_FBUF: OK (Not Supported)
11221 09:32:58.398134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11222 09:32:58.399012 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11224 09:32:58.401384 test VIDIOC_G_FMT: OK
11225 09:32:58.428455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11226 09:32:58.429287 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11228 09:32:58.431549 test VIDIOC_TRY_FMT: OK
11229 09:32:58.453705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11230 09:32:58.454513 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11232 09:32:58.460750 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11233 09:32:58.467611 test VIDIOC_S_FMT: OK
11234 09:32:58.494163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11235 09:32:58.494990 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11237 09:32:58.497374 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11238 09:32:58.525097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11239 09:32:58.525927 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11241 09:32:58.528617 test Cropping: OK (Not Supported)
11242 09:32:58.552523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11243 09:32:58.553370 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11245 09:32:58.555674 test Composing: OK (Not Supported)
11246 09:32:58.578945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11247 09:32:58.579821 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11249 09:32:58.582582 test Scaling: OK (Not Supported)
11250 09:32:58.606212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11251 09:32:58.606751
11252 09:32:58.607432 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11254 09:32:58.617384 Codec ioctls (Input 0):
11255 09:32:58.625549 <LAVA_SIGNAL_TESTSET STOP>
11256 09:32:58.626383 Received signal: <TESTSET> STOP
11257 09:32:58.626767 Closing test_set Format-ioctls-Input-0
11258 09:32:58.635672 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11259 09:32:58.636501 Received signal: <TESTSET> START Codec-ioctls-Input-0
11260 09:32:58.636888 Starting test_set Codec-ioctls-Input-0
11261 09:32:58.638041 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11262 09:32:58.661668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11263 09:32:58.662500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11265 09:32:58.667970 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11266 09:32:58.691435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11267 09:32:58.692309 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11269 09:32:58.697678 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11270 09:32:58.716379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11271 09:32:58.716980
11272 09:32:58.717613 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11274 09:32:58.733820 Buffer ioctls (Input 0):
11275 09:32:58.741937 <LAVA_SIGNAL_TESTSET STOP>
11276 09:32:58.742761 Received signal: <TESTSET> STOP
11277 09:32:58.743178 Closing test_set Codec-ioctls-Input-0
11278 09:32:58.751884 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11279 09:32:58.752693 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11280 09:32:58.753085 Starting test_set Buffer-ioctls-Input-0
11281 09:32:58.755436 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11282 09:32:58.782964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11283 09:32:58.783527 test VIDIOC_EXPBUF: OK
11284 09:32:58.784205 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11286 09:32:58.805742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11287 09:32:58.806575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11289 09:32:58.809004 test Requests: OK (Not Supported)
11290 09:32:58.837872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11291 09:32:58.838426
11292 09:32:58.839140 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11294 09:32:58.847868 Test input 0:
11295 09:32:58.859801
11296 09:32:58.869568 Streaming ioctls:
11297 09:32:58.876532 <LAVA_SIGNAL_TESTSET STOP>
11298 09:32:58.877379 Received signal: <TESTSET> STOP
11299 09:32:58.877762 Closing test_set Buffer-ioctls-Input-0
11300 09:32:58.886375 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11301 09:32:58.887227 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11302 09:32:58.887624 Starting test_set Streaming-ioctls_Test-input-0
11303 09:32:58.889423 test read/write: OK (Not Supported)
11304 09:32:58.911623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11305 09:32:58.912466 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11307 09:32:58.914708 test blocking wait: OK
11308 09:32:58.936410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11309 09:32:58.937181 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11311 09:32:58.946558 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11312 09:32:58.951483 test MMAP (no poll): FAIL
11313 09:32:58.977441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11314 09:32:58.978205 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11316 09:32:58.987739 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11317 09:32:58.991474 test MMAP (select): FAIL
11318 09:32:59.015835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11319 09:32:59.016652 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11321 09:32:59.025088 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11322 09:32:59.032209 test MMAP (epoll): FAIL
11323 09:32:59.055590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11324 09:32:59.056103
11325 09:32:59.056799 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11327 09:32:59.073418
11328 09:32:59.260382
11329 09:32:59.268221 test USERPTR (no poll): OK
11330 09:32:59.296828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11331 09:32:59.297479
11332 09:32:59.298256 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11334 09:32:59.308360
11335 09:32:59.487312
11336 09:32:59.495598 test USERPTR (select): OK
11337 09:32:59.522927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11338 09:32:59.523813 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11340 09:32:59.529700 test DMABUF: Cannot test, specify --expbuf-device
11341 09:32:59.534101
11342 09:32:59.554592 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11343 09:32:59.557971 <LAVA_TEST_RUNNER EXIT>
11344 09:32:59.558717 ok: lava_test_shell seems to have completed
11345 09:32:59.559198 Marking unfinished test run as failed
11347 09:32:59.564757 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11348 09:32:59.565411 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11349 09:32:59.565917 end: 3 lava-test-retry (duration 00:00:10) [common]
11350 09:32:59.566440 start: 4 finalize (timeout 00:07:27) [common]
11351 09:32:59.566970 start: 4.1 power-off (timeout 00:00:30) [common]
11352 09:32:59.567906 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11353 09:32:59.654067 >> Command sent successfully.
11354 09:32:59.658897 Returned 0 in 0 seconds
11355 09:32:59.759936 end: 4.1 power-off (duration 00:00:00) [common]
11357 09:32:59.761733 start: 4.2 read-feedback (timeout 00:07:26) [common]
11358 09:32:59.763038 Listened to connection for namespace 'common' for up to 1s
11359 09:33:00.763446 Finalising connection for namespace 'common'
11360 09:33:00.763624 Disconnecting from shell: Finalise
11361 09:33:00.763724 / #
11362 09:33:00.864043 end: 4.2 read-feedback (duration 00:00:01) [common]
11363 09:33:00.864208 end: 4 finalize (duration 00:00:01) [common]
11364 09:33:00.864328 Cleaning after the job
11365 09:33:00.864476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/ramdisk
11366 09:33:00.870233 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/kernel
11367 09:33:00.885800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/dtb
11368 09:33:00.885992 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11826819/tftp-deploy-p0d7m4m5/modules
11369 09:33:00.893365 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11826819
11370 09:33:00.963829 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11826819
11371 09:33:00.964005 Job finished correctly