Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 37
- Kernel Warnings: 26
- Boot result: PASS
- Errors: 0
1 10:04:16.408023 lava-dispatcher, installed at version: 2023.10
2 10:04:16.408290 start: 0 validate
3 10:04:16.408451 Start time: 2023-11-24 10:04:16.408443+00:00 (UTC)
4 10:04:16.408586 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:04:16.408727 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 10:04:16.709217 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:04:16.709398 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:04:16.990642 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:04:16.990829 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:04:17.277959 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:04:17.278140 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:04:17.577879 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:04:17.578059 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:04:17.872516 validate duration: 1.46
16 10:04:17.872776 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:04:17.872875 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:04:17.873008 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:04:17.873203 Not decompressing ramdisk as can be used compressed.
20 10:04:17.873289 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 10:04:17.873356 saving as /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/ramdisk/initrd.cpio.gz
22 10:04:17.873424 total size: 4665395 (4 MB)
23 10:04:17.874505 progress 0 % (0 MB)
24 10:04:17.876057 progress 5 % (0 MB)
25 10:04:17.877405 progress 10 % (0 MB)
26 10:04:17.878880 progress 15 % (0 MB)
27 10:04:17.880329 progress 20 % (0 MB)
28 10:04:17.881868 progress 25 % (1 MB)
29 10:04:17.883269 progress 30 % (1 MB)
30 10:04:17.884598 progress 35 % (1 MB)
31 10:04:17.886076 progress 40 % (1 MB)
32 10:04:17.887697 progress 45 % (2 MB)
33 10:04:17.888938 progress 50 % (2 MB)
34 10:04:17.890240 progress 55 % (2 MB)
35 10:04:17.891512 progress 60 % (2 MB)
36 10:04:17.892802 progress 65 % (2 MB)
37 10:04:17.894184 progress 70 % (3 MB)
38 10:04:17.895472 progress 75 % (3 MB)
39 10:04:17.896697 progress 80 % (3 MB)
40 10:04:17.898316 progress 85 % (3 MB)
41 10:04:17.899567 progress 90 % (4 MB)
42 10:04:17.900793 progress 95 % (4 MB)
43 10:04:17.902195 progress 100 % (4 MB)
44 10:04:17.902383 4 MB downloaded in 0.03 s (153.65 MB/s)
45 10:04:17.902582 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:04:17.902952 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:04:17.903068 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:04:17.903188 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:04:17.903331 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:04:17.903405 saving as /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/kernel/Image
52 10:04:17.903468 total size: 49107456 (46 MB)
53 10:04:17.903530 No compression specified
54 10:04:17.904611 progress 0 % (0 MB)
55 10:04:17.918786 progress 5 % (2 MB)
56 10:04:17.933484 progress 10 % (4 MB)
57 10:04:17.947332 progress 15 % (7 MB)
58 10:04:17.960744 progress 20 % (9 MB)
59 10:04:17.974121 progress 25 % (11 MB)
60 10:04:17.988178 progress 30 % (14 MB)
61 10:04:18.001808 progress 35 % (16 MB)
62 10:04:18.015466 progress 40 % (18 MB)
63 10:04:18.029047 progress 45 % (21 MB)
64 10:04:18.042494 progress 50 % (23 MB)
65 10:04:18.055908 progress 55 % (25 MB)
66 10:04:18.069248 progress 60 % (28 MB)
67 10:04:18.082887 progress 65 % (30 MB)
68 10:04:18.096447 progress 70 % (32 MB)
69 10:04:18.109540 progress 75 % (35 MB)
70 10:04:18.122802 progress 80 % (37 MB)
71 10:04:18.136419 progress 85 % (39 MB)
72 10:04:18.149843 progress 90 % (42 MB)
73 10:04:18.162999 progress 95 % (44 MB)
74 10:04:18.175873 progress 100 % (46 MB)
75 10:04:18.176135 46 MB downloaded in 0.27 s (171.76 MB/s)
76 10:04:18.176341 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:04:18.176720 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:04:18.176844 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:04:18.176962 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:04:18.177135 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:04:18.177234 saving as /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/dtb/mt8192-asurada-spherion-r0.dtb
83 10:04:18.177332 total size: 47278 (0 MB)
84 10:04:18.177425 No compression specified
85 10:04:18.178617 progress 69 % (0 MB)
86 10:04:18.178899 progress 100 % (0 MB)
87 10:04:18.179066 0 MB downloaded in 0.00 s (26.03 MB/s)
88 10:04:18.179193 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:04:18.179429 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:04:18.179523 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:04:18.179621 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:04:18.179749 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 10:04:18.179819 saving as /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/nfsrootfs/full.rootfs.tar
95 10:04:18.179885 total size: 200813988 (191 MB)
96 10:04:18.179952 Using unxz to decompress xz
97 10:04:18.184068 progress 0 % (0 MB)
98 10:04:18.749195 progress 5 % (9 MB)
99 10:04:19.289013 progress 10 % (19 MB)
100 10:04:19.883310 progress 15 % (28 MB)
101 10:04:20.269607 progress 20 % (38 MB)
102 10:04:20.608062 progress 25 % (47 MB)
103 10:04:21.224672 progress 30 % (57 MB)
104 10:04:21.800456 progress 35 % (67 MB)
105 10:04:22.413193 progress 40 % (76 MB)
106 10:04:22.986879 progress 45 % (86 MB)
107 10:04:23.584100 progress 50 % (95 MB)
108 10:04:24.245805 progress 55 % (105 MB)
109 10:04:24.952869 progress 60 % (114 MB)
110 10:04:25.082367 progress 65 % (124 MB)
111 10:04:25.230805 progress 70 % (134 MB)
112 10:04:25.328836 progress 75 % (143 MB)
113 10:04:25.400212 progress 80 % (153 MB)
114 10:04:25.469816 progress 85 % (162 MB)
115 10:04:25.572158 progress 90 % (172 MB)
116 10:04:25.855569 progress 95 % (181 MB)
117 10:04:26.439214 progress 100 % (191 MB)
118 10:04:26.444356 191 MB downloaded in 8.26 s (23.17 MB/s)
119 10:04:26.444613 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:04:26.444901 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:04:26.444993 start: 1.5 download-retry (timeout 00:09:51) [common]
123 10:04:26.445090 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 10:04:26.445266 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:04:26.445342 saving as /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/modules/modules.tar
126 10:04:26.445406 total size: 8622040 (8 MB)
127 10:04:26.445488 Using unxz to decompress xz
128 10:04:26.449804 progress 0 % (0 MB)
129 10:04:26.470954 progress 5 % (0 MB)
130 10:04:26.494617 progress 10 % (0 MB)
131 10:04:26.518657 progress 15 % (1 MB)
132 10:04:26.542319 progress 20 % (1 MB)
133 10:04:26.567342 progress 25 % (2 MB)
134 10:04:26.593563 progress 30 % (2 MB)
135 10:04:26.620063 progress 35 % (2 MB)
136 10:04:26.643725 progress 40 % (3 MB)
137 10:04:26.668444 progress 45 % (3 MB)
138 10:04:26.693689 progress 50 % (4 MB)
139 10:04:26.718505 progress 55 % (4 MB)
140 10:04:26.743905 progress 60 % (4 MB)
141 10:04:26.772807 progress 65 % (5 MB)
142 10:04:26.799334 progress 70 % (5 MB)
143 10:04:26.824478 progress 75 % (6 MB)
144 10:04:26.852353 progress 80 % (6 MB)
145 10:04:26.878471 progress 85 % (7 MB)
146 10:04:26.904003 progress 90 % (7 MB)
147 10:04:26.934875 progress 95 % (7 MB)
148 10:04:26.965913 progress 100 % (8 MB)
149 10:04:26.970951 8 MB downloaded in 0.53 s (15.65 MB/s)
150 10:04:26.971218 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:04:26.971493 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:04:26.971587 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:04:26.971687 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:04:30.708990 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9
156 10:04:30.709220 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 10:04:30.709342 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 10:04:30.709545 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8
159 10:04:30.709715 makedir: /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin
160 10:04:30.709842 makedir: /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/tests
161 10:04:30.709968 makedir: /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/results
162 10:04:30.710090 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-add-keys
163 10:04:30.710291 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-add-sources
164 10:04:30.710473 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-background-process-start
165 10:04:30.710650 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-background-process-stop
166 10:04:30.710802 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-common-functions
167 10:04:30.710955 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-echo-ipv4
168 10:04:30.711134 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-install-packages
169 10:04:30.711283 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-installed-packages
170 10:04:30.711432 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-os-build
171 10:04:30.711586 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-probe-channel
172 10:04:30.711739 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-probe-ip
173 10:04:30.711921 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-target-ip
174 10:04:30.712095 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-target-mac
175 10:04:30.712244 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-target-storage
176 10:04:30.712399 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-case
177 10:04:30.712574 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-event
178 10:04:30.712722 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-feedback
179 10:04:30.712872 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-raise
180 10:04:30.713039 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-reference
181 10:04:30.713217 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-runner
182 10:04:30.713392 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-set
183 10:04:30.713546 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-test-shell
184 10:04:30.713999 Updating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-add-keys (debian)
185 10:04:30.837169 Updating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-add-sources (debian)
186 10:04:30.837466 Updating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-install-packages (debian)
187 10:04:30.837708 Updating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-installed-packages (debian)
188 10:04:30.837869 Updating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/bin/lava-os-build (debian)
189 10:04:30.838003 Creating /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/environment
190 10:04:30.838143 LAVA metadata
191 10:04:30.838234 - LAVA_JOB_ID=12073332
192 10:04:30.838352 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:04:30.838477 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 10:04:30.838548 skipped lava-vland-overlay
195 10:04:30.838637 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:04:30.838729 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 10:04:30.838793 skipped lava-multinode-overlay
198 10:04:30.838877 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:04:30.838958 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 10:04:30.839071 Loading test definitions
201 10:04:30.839184 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 10:04:30.839260 Using /lava-12073332 at stage 0
203 10:04:30.839590 uuid=12073332_1.6.2.3.1 testdef=None
204 10:04:30.839752 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:04:30.839896 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 10:04:30.840422 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:04:30.840726 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 10:04:30.841432 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:04:30.841753 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 10:04:30.851272 runner path: /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/0/tests/0_timesync-off test_uuid 12073332_1.6.2.3.1
213 10:04:30.851495 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:04:30.851783 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 10:04:30.851868 Using /lava-12073332 at stage 0
217 10:04:30.851996 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:04:30.852114 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/0/tests/1_kselftest-rtc'
219 10:04:52.701532 Running '/usr/bin/git checkout kernelci.org
220 10:04:52.863155 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 10:04:52.863971 uuid=12073332_1.6.2.3.5 testdef=None
222 10:04:52.864134 end: 1.6.2.3.5 git-repo-action (duration 00:00:22) [common]
224 10:04:52.864418 start: 1.6.2.3.6 test-overlay (timeout 00:09:25) [common]
225 10:04:52.865247 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:04:52.865504 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:25) [common]
228 10:04:52.866562 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:04:52.866823 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:25) [common]
231 10:04:52.909198 runner path: /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/0/tests/1_kselftest-rtc test_uuid 12073332_1.6.2.3.5
232 10:04:52.909320 BOARD='mt8192-asurada-spherion-r0'
233 10:04:52.909399 BRANCH='cip'
234 10:04:52.909472 SKIPFILE='/dev/null'
235 10:04:52.909534 SKIP_INSTALL='True'
236 10:04:52.909616 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:04:52.909683 TST_CASENAME=''
238 10:04:52.909742 TST_CMDFILES='rtc'
239 10:04:52.909918 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:04:52.910150 Creating lava-test-runner.conf files
242 10:04:52.910227 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073332/lava-overlay-uioxnhx8/lava-12073332/0 for stage 0
243 10:04:52.910332 - 0_timesync-off
244 10:04:52.910401 - 1_kselftest-rtc
245 10:04:52.910507 end: 1.6.2.3 test-definition (duration 00:00:22) [common]
246 10:04:52.910609 start: 1.6.2.4 compress-overlay (timeout 00:09:25) [common]
247 10:05:00.590738 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:05:00.590929 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:17) [common]
249 10:05:00.591024 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:05:00.591126 end: 1.6.2 lava-overlay (duration 00:00:30) [common]
251 10:05:00.591219 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:17) [common]
252 10:05:00.712876 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:05:00.713266 start: 1.6.4 extract-modules (timeout 00:09:17) [common]
254 10:05:00.713389 extracting modules file /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9
255 10:05:00.960382 extracting modules file /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073332/extract-overlay-ramdisk-e96e0d85/ramdisk
256 10:05:01.203624 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:05:01.203821 start: 1.6.5 apply-overlay-tftp (timeout 00:09:17) [common]
258 10:05:01.203953 [common] Applying overlay to NFS
259 10:05:01.204069 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073332/compress-overlay-_x26q081/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9
260 10:05:02.242953 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:05:02.243131 start: 1.6.6 configure-preseed-file (timeout 00:09:16) [common]
262 10:05:02.243237 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:05:02.243326 start: 1.6.7 compress-ramdisk (timeout 00:09:16) [common]
264 10:05:02.243413 Building ramdisk /var/lib/lava/dispatcher/tmp/12073332/extract-overlay-ramdisk-e96e0d85/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073332/extract-overlay-ramdisk-e96e0d85/ramdisk
265 10:05:02.576551 >> 119398 blocks
266 10:05:04.639196 rename /var/lib/lava/dispatcher/tmp/12073332/extract-overlay-ramdisk-e96e0d85/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/ramdisk/ramdisk.cpio.gz
267 10:05:04.639649 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:05:04.639790 start: 1.6.8 prepare-kernel (timeout 00:09:13) [common]
269 10:05:04.639904 start: 1.6.8.1 prepare-fit (timeout 00:09:13) [common]
270 10:05:04.640024 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/kernel/Image'
271 10:05:17.595493 Returned 0 in 12 seconds
272 10:05:17.696121 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/kernel/image.itb
273 10:05:18.048154 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:05:18.048547 output: Created: Fri Nov 24 10:05:17 2023
275 10:05:18.048712 output: Image 0 (kernel-1)
276 10:05:18.048806 output: Description:
277 10:05:18.048911 output: Created: Fri Nov 24 10:05:17 2023
278 10:05:18.048973 output: Type: Kernel Image
279 10:05:18.049035 output: Compression: lzma compressed
280 10:05:18.049137 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
281 10:05:18.049227 output: Architecture: AArch64
282 10:05:18.049329 output: OS: Linux
283 10:05:18.049444 output: Load Address: 0x00000000
284 10:05:18.049535 output: Entry Point: 0x00000000
285 10:05:18.049646 output: Hash algo: crc32
286 10:05:18.049710 output: Hash value: 2edffaa3
287 10:05:18.049769 output: Image 1 (fdt-1)
288 10:05:18.049833 output: Description: mt8192-asurada-spherion-r0
289 10:05:18.049930 output: Created: Fri Nov 24 10:05:17 2023
290 10:05:18.049984 output: Type: Flat Device Tree
291 10:05:18.050037 output: Compression: uncompressed
292 10:05:18.050119 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 10:05:18.050191 output: Architecture: AArch64
294 10:05:18.050245 output: Hash algo: crc32
295 10:05:18.050298 output: Hash value: cc4352de
296 10:05:18.050352 output: Image 2 (ramdisk-1)
297 10:05:18.050405 output: Description: unavailable
298 10:05:18.050458 output: Created: Fri Nov 24 10:05:17 2023
299 10:05:18.050511 output: Type: RAMDisk Image
300 10:05:18.050565 output: Compression: Unknown Compression
301 10:05:18.050617 output: Data Size: 17794100 Bytes = 17377.05 KiB = 16.97 MiB
302 10:05:18.050671 output: Architecture: AArch64
303 10:05:18.050724 output: OS: Linux
304 10:05:18.050776 output: Load Address: unavailable
305 10:05:18.050828 output: Entry Point: unavailable
306 10:05:18.050880 output: Hash algo: crc32
307 10:05:18.050933 output: Hash value: a7d61839
308 10:05:18.050986 output: Default Configuration: 'conf-1'
309 10:05:18.051038 output: Configuration 0 (conf-1)
310 10:05:18.051091 output: Description: mt8192-asurada-spherion-r0
311 10:05:18.051176 output: Kernel: kernel-1
312 10:05:18.051228 output: Init Ramdisk: ramdisk-1
313 10:05:18.051281 output: FDT: fdt-1
314 10:05:18.051333 output: Loadables: kernel-1
315 10:05:18.051385 output:
316 10:05:18.051586 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 10:05:18.051760 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 10:05:18.051871 end: 1.6 prepare-tftp-overlay (duration 00:00:51) [common]
319 10:05:18.051969 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:00) [common]
320 10:05:18.052052 No LXC device requested
321 10:05:18.052132 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:05:18.052217 start: 1.8 deploy-device-env (timeout 00:09:00) [common]
323 10:05:18.052315 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:05:18.052451 Checking files for TFTP limit of 4294967296 bytes.
325 10:05:18.053078 end: 1 tftp-deploy (duration 00:01:00) [common]
326 10:05:18.053185 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:05:18.053280 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:05:18.053416 substitutions:
329 10:05:18.053485 - {DTB}: 12073332/tftp-deploy-iubfbl6v/dtb/mt8192-asurada-spherion-r0.dtb
330 10:05:18.053550 - {INITRD}: 12073332/tftp-deploy-iubfbl6v/ramdisk/ramdisk.cpio.gz
331 10:05:18.053639 - {KERNEL}: 12073332/tftp-deploy-iubfbl6v/kernel/Image
332 10:05:18.053713 - {LAVA_MAC}: None
333 10:05:18.053771 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9
334 10:05:18.053828 - {NFS_SERVER_IP}: 192.168.201.1
335 10:05:18.053901 - {PRESEED_CONFIG}: None
336 10:05:18.053971 - {PRESEED_LOCAL}: None
337 10:05:18.054026 - {RAMDISK}: 12073332/tftp-deploy-iubfbl6v/ramdisk/ramdisk.cpio.gz
338 10:05:18.054081 - {ROOT_PART}: None
339 10:05:18.054155 - {ROOT}: None
340 10:05:18.054226 - {SERVER_IP}: 192.168.201.1
341 10:05:18.054280 - {TEE}: None
342 10:05:18.054356 Parsed boot commands:
343 10:05:18.054451 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:05:18.054650 Parsed boot commands: tftpboot 192.168.201.1 12073332/tftp-deploy-iubfbl6v/kernel/image.itb 12073332/tftp-deploy-iubfbl6v/kernel/cmdline
345 10:05:18.054770 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:05:18.054881 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:05:18.055066 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:05:18.055188 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:05:18.055267 Not connected, no need to disconnect.
350 10:05:18.055347 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:05:18.055468 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:05:18.055536 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 10:05:18.059603 Setting prompt string to ['lava-test: # ']
354 10:05:18.059985 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:05:18.060095 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:05:18.060199 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:05:18.060314 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:05:18.060550 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 10:05:23.197400 >> Command sent successfully.
360 10:05:23.199857 Returned 0 in 5 seconds
361 10:05:23.300251 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:05:23.300683 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:05:23.300791 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:05:23.300924 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:05:23.301065 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:05:23.301186 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:05:23.301606 [Enter `^Ec?' for help]
369 10:05:23.474351
370 10:05:23.474515
371 10:05:23.474594 F0: 102B 0000
372 10:05:23.474668
373 10:05:23.474732 F3: 1001 0000 [0200]
374 10:05:23.478228
375 10:05:23.478306 F3: 1001 0000
376 10:05:23.478381
377 10:05:23.478445 F7: 102D 0000
378 10:05:23.478506
379 10:05:23.481431 F1: 0000 0000
380 10:05:23.481509
381 10:05:23.481582 V0: 0000 0000 [0001]
382 10:05:23.481661
383 10:05:23.484519 00: 0007 8000
384 10:05:23.484602
385 10:05:23.484675 01: 0000 0000
386 10:05:23.484740
387 10:05:23.487631 BP: 0C00 0209 [0000]
388 10:05:23.487716
389 10:05:23.487782 G0: 1182 0000
390 10:05:23.487843
391 10:05:23.491672 EC: 0000 0021 [4000]
392 10:05:23.491758
393 10:05:23.491824 S7: 0000 0000 [0000]
394 10:05:23.491886
395 10:05:23.495312 CC: 0000 0000 [0001]
396 10:05:23.495394
397 10:05:23.495468 T0: 0000 0040 [010F]
398 10:05:23.495532
399 10:05:23.495593 Jump to BL
400 10:05:23.495653
401 10:05:23.522035
402 10:05:23.522180
403 10:05:23.522277
404 10:05:23.529354 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:05:23.532557 ARM64: Exception handlers installed.
406 10:05:23.536580 ARM64: Testing exception
407 10:05:23.539542 ARM64: Done test exception
408 10:05:23.545997 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:05:23.556542 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:05:23.563417 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:05:23.573251 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:05:23.580215 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:05:23.586739 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:05:23.599157 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:05:23.605555 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:05:23.624301 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:05:23.627757 WDT: Last reset was cold boot
418 10:05:23.630863 SPI1(PAD0) initialized at 2873684 Hz
419 10:05:23.634095 SPI5(PAD0) initialized at 992727 Hz
420 10:05:23.637741 VBOOT: Loading verstage.
421 10:05:23.644193 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:05:23.647893 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:05:23.651190 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:05:23.654552 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:05:23.662329 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:05:23.668856 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:05:23.679722 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:05:23.679824
429 10:05:23.679913
430 10:05:23.690543 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:05:23.693801 ARM64: Exception handlers installed.
432 10:05:23.693891 ARM64: Testing exception
433 10:05:23.696997 ARM64: Done test exception
434 10:05:23.700733 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:05:23.707239 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:05:23.720912 Probing TPM: . done!
437 10:05:23.721014 TPM ready after 0 ms
438 10:05:23.727711 Connected to device vid:did:rid of 1ae0:0028:00
439 10:05:23.734639 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 10:05:23.793483 Initialized TPM device CR50 revision 0
441 10:05:23.805389 tlcl_send_startup: Startup return code is 0
442 10:05:23.805504 TPM: setup succeeded
443 10:05:23.816837 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:05:23.825673 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:05:23.837957 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:05:23.847907 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:05:23.851668 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:05:23.855659 in-header: 03 07 00 00 08 00 00 00
449 10:05:23.859525 in-data: aa e4 47 04 13 02 00 00
450 10:05:23.859615 Chrome EC: UHEPI supported
451 10:05:23.866597 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:05:23.871330 in-header: 03 95 00 00 08 00 00 00
453 10:05:23.875103 in-data: 18 20 20 08 00 00 00 00
454 10:05:23.875196 Phase 1
455 10:05:23.878449 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:05:23.886181 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:05:23.893698 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:05:23.893795 Recovery requested (1009000e)
459 10:05:23.904078 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:05:23.909302 tlcl_extend: response is 0
461 10:05:23.920849 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:05:23.924980 tlcl_extend: response is 0
463 10:05:23.931908 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:05:23.951057 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:05:23.958080 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:05:23.958180
467 10:05:23.958269
468 10:05:23.967943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:05:23.971515 ARM64: Exception handlers installed.
470 10:05:23.974521 ARM64: Testing exception
471 10:05:23.974607 ARM64: Done test exception
472 10:05:23.996723 pmic_efuse_setting: Set efuses in 11 msecs
473 10:05:24.000046 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:05:24.006799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:05:24.010401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:05:24.014328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:05:24.021514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:05:24.025381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:05:24.028958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:05:24.036683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:05:24.039849 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:05:24.043615 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:05:24.051492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:05:24.054725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:05:24.058646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:05:24.061938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:05:24.069232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:05:24.076670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:05:24.080564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:05:24.088613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:05:24.091656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:05:24.098763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:05:24.102233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:05:24.110410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:05:24.113655 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:05:24.121483 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:05:24.125296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:05:24.128906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:05:24.136000 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:05:24.139568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:05:24.147323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:05:24.150536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:05:24.154399 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:05:24.161545 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:05:24.164951 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:05:24.172818 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:05:24.176014 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:05:24.179274 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:05:24.186897 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:05:24.191235 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:05:24.194793 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:05:24.202065 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:05:24.205738 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:05:24.209550 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:05:24.213196 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:05:24.216685 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:05:24.224187 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:05:24.227908 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:05:24.231020 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:05:24.235112 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:05:24.238400 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:05:24.245928 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:05:24.249457 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:05:24.253023 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:05:24.260661 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:05:24.267840 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:05:24.271782 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:05:24.282391 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:05:24.289716 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:05:24.294089 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:05:24.297728 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:05:24.304999 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:05:24.308512 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x39
534 10:05:24.315699 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:05:24.319600 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 10:05:24.323366 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:05:24.334645 [RTC]rtc_get_frequency_meter,154: input=15, output=758
538 10:05:24.344123 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 10:05:24.353761 [RTC]rtc_get_frequency_meter,154: input=19, output=849
540 10:05:24.363120 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 10:05:24.372496 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 10:05:24.382285 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 10:05:24.392516 [RTC]rtc_get_frequency_meter,154: input=17, output=806
544 10:05:24.395868 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 10:05:24.400155 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 10:05:24.403551 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:05:24.411131 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 10:05:24.414778 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:05:24.418287 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 10:05:24.422233 ADC[4]: Raw value=906203 ID=7
551 10:05:24.422317 ADC[3]: Raw value=213441 ID=1
552 10:05:24.425242 RAM Code: 0x71
553 10:05:24.429167 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:05:24.433149 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:05:24.444014 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:05:24.447837 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:05:24.451832 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:05:24.455654 in-header: 03 07 00 00 08 00 00 00
559 10:05:24.459817 in-data: aa e4 47 04 13 02 00 00
560 10:05:24.463214 Chrome EC: UHEPI supported
561 10:05:24.466642 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:05:24.472417 in-header: 03 95 00 00 08 00 00 00
563 10:05:24.475872 in-data: 18 20 20 08 00 00 00 00
564 10:05:24.479992 MRC: failed to locate region type 0.
565 10:05:24.487827 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:05:24.487917 DRAM-K: Running full calibration
567 10:05:24.495058 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:05:24.498364 header.status = 0x0
569 10:05:24.502189 header.version = 0x6 (expected: 0x6)
570 10:05:24.506089 header.size = 0xd00 (expected: 0xd00)
571 10:05:24.506178 header.flags = 0x0
572 10:05:24.513245 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:05:24.530558 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 10:05:24.537206 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:05:24.541212 dram_init: ddr_geometry: 2
576 10:05:24.541298 [EMI] MDL number = 2
577 10:05:24.544563 [EMI] Get MDL freq = 0
578 10:05:24.544648 dram_init: ddr_type: 0
579 10:05:24.548270 is_discrete_lpddr4: 1
580 10:05:24.552283 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:05:24.552421
582 10:05:24.552542
583 10:05:24.552660 [Bian_co] ETT version 0.0.0.1
584 10:05:24.559827 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:05:24.559939
586 10:05:24.563803 dramc_set_vcore_voltage set vcore to 650000
587 10:05:24.563889 Read voltage for 800, 4
588 10:05:24.563956 Vio18 = 0
589 10:05:24.567515 Vcore = 650000
590 10:05:24.567600 Vdram = 0
591 10:05:24.567667 Vddq = 0
592 10:05:24.571035 Vmddr = 0
593 10:05:24.571119 dram_init: config_dvfs: 1
594 10:05:24.578620 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:05:24.582207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:05:24.586245 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 10:05:24.590046 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 10:05:24.593237 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 10:05:24.597302 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 10:05:24.600652 MEM_TYPE=3, freq_sel=18
601 10:05:24.603843 sv_algorithm_assistance_LP4_1600
602 10:05:24.607017 ============ PULL DRAM RESETB DOWN ============
603 10:05:24.610373 ========== PULL DRAM RESETB DOWN end =========
604 10:05:24.617342 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:05:24.620683 ===================================
606 10:05:24.620800 LPDDR4 DRAM CONFIGURATION
607 10:05:24.624626 ===================================
608 10:05:24.628388 EX_ROW_EN[0] = 0x0
609 10:05:24.628475 EX_ROW_EN[1] = 0x0
610 10:05:24.631703 LP4Y_EN = 0x0
611 10:05:24.631841 WORK_FSP = 0x0
612 10:05:24.635695 WL = 0x2
613 10:05:24.635778 RL = 0x2
614 10:05:24.635845 BL = 0x2
615 10:05:24.639397 RPST = 0x0
616 10:05:24.639481 RD_PRE = 0x0
617 10:05:24.642311 WR_PRE = 0x1
618 10:05:24.642433 WR_PST = 0x0
619 10:05:24.645786 DBI_WR = 0x0
620 10:05:24.648972 DBI_RD = 0x0
621 10:05:24.649057 OTF = 0x1
622 10:05:24.652229 ===================================
623 10:05:24.656262 ===================================
624 10:05:24.656347 ANA top config
625 10:05:24.659339 ===================================
626 10:05:24.662365 DLL_ASYNC_EN = 0
627 10:05:24.665953 ALL_SLAVE_EN = 1
628 10:05:24.668925 NEW_RANK_MODE = 1
629 10:05:24.669010 DLL_IDLE_MODE = 1
630 10:05:24.672752 LP45_APHY_COMB_EN = 1
631 10:05:24.675832 TX_ODT_DIS = 1
632 10:05:24.679697 NEW_8X_MODE = 1
633 10:05:24.683395 ===================================
634 10:05:24.686807 ===================================
635 10:05:24.686892 data_rate = 1600
636 10:05:24.690345 CKR = 1
637 10:05:24.693412 DQ_P2S_RATIO = 8
638 10:05:24.696714 ===================================
639 10:05:24.699798 CA_P2S_RATIO = 8
640 10:05:24.703193 DQ_CA_OPEN = 0
641 10:05:24.706944 DQ_SEMI_OPEN = 0
642 10:05:24.707027 CA_SEMI_OPEN = 0
643 10:05:24.710167 CA_FULL_RATE = 0
644 10:05:24.713302 DQ_CKDIV4_EN = 1
645 10:05:24.716532 CA_CKDIV4_EN = 1
646 10:05:24.720352 CA_PREDIV_EN = 0
647 10:05:24.720437 PH8_DLY = 0
648 10:05:24.723667 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:05:24.726922 DQ_AAMCK_DIV = 4
650 10:05:24.730218 CA_AAMCK_DIV = 4
651 10:05:24.733402 CA_ADMCK_DIV = 4
652 10:05:24.736709 DQ_TRACK_CA_EN = 0
653 10:05:24.736793 CA_PICK = 800
654 10:05:24.740453 CA_MCKIO = 800
655 10:05:24.744401 MCKIO_SEMI = 0
656 10:05:24.747745 PLL_FREQ = 3068
657 10:05:24.751581 DQ_UI_PI_RATIO = 32
658 10:05:24.751669 CA_UI_PI_RATIO = 0
659 10:05:24.755626 ===================================
660 10:05:24.759277 ===================================
661 10:05:24.763063 memory_type:LPDDR4
662 10:05:24.763152 GP_NUM : 10
663 10:05:24.767022 SRAM_EN : 1
664 10:05:24.767129 MD32_EN : 0
665 10:05:24.770321 ===================================
666 10:05:24.773905 [ANA_INIT] >>>>>>>>>>>>>>
667 10:05:24.777569 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:05:24.780942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:05:24.783958 ===================================
670 10:05:24.784045 data_rate = 1600,PCW = 0X7600
671 10:05:24.787738 ===================================
672 10:05:24.794184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:05:24.797121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:05:24.804123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:05:24.807205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:05:24.810793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:05:24.814122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:05:24.817396 [ANA_INIT] flow start
679 10:05:24.820944 [ANA_INIT] PLL >>>>>>>>
680 10:05:24.821045 [ANA_INIT] PLL <<<<<<<<
681 10:05:24.824028 [ANA_INIT] MIDPI >>>>>>>>
682 10:05:24.827341 [ANA_INIT] MIDPI <<<<<<<<
683 10:05:24.827429 [ANA_INIT] DLL >>>>>>>>
684 10:05:24.830631 [ANA_INIT] flow end
685 10:05:24.833913 ============ LP4 DIFF to SE enter ============
686 10:05:24.837222 ============ LP4 DIFF to SE exit ============
687 10:05:24.840418 [ANA_INIT] <<<<<<<<<<<<<
688 10:05:24.844310 [Flow] Enable top DCM control >>>>>
689 10:05:24.847559 [Flow] Enable top DCM control <<<<<
690 10:05:24.850794 Enable DLL master slave shuffle
691 10:05:24.857531 ==============================================================
692 10:05:24.857671 Gating Mode config
693 10:05:24.864221 ==============================================================
694 10:05:24.864309 Config description:
695 10:05:24.874106 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:05:24.880843 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:05:24.887621 SELPH_MODE 0: By rank 1: By Phase
698 10:05:24.891272 ==============================================================
699 10:05:24.894159 GAT_TRACK_EN = 1
700 10:05:24.897452 RX_GATING_MODE = 2
701 10:05:24.900745 RX_GATING_TRACK_MODE = 2
702 10:05:24.904385 SELPH_MODE = 1
703 10:05:24.907787 PICG_EARLY_EN = 1
704 10:05:24.910748 VALID_LAT_VALUE = 1
705 10:05:24.914037 ==============================================================
706 10:05:24.917711 Enter into Gating configuration >>>>
707 10:05:24.920868 Exit from Gating configuration <<<<
708 10:05:24.924374 Enter into DVFS_PRE_config >>>>>
709 10:05:24.938036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:05:24.938131 Exit from DVFS_PRE_config <<<<<
711 10:05:24.941104 Enter into PICG configuration >>>>
712 10:05:24.944285 Exit from PICG configuration <<<<
713 10:05:24.947604 [RX_INPUT] configuration >>>>>
714 10:05:24.950789 [RX_INPUT] configuration <<<<<
715 10:05:24.957876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:05:24.961201 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:05:24.967774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:05:24.974774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:05:24.981015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:05:24.988288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:05:24.991379 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:05:24.994709 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:05:24.997930 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:05:25.004752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:05:25.008429 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:05:25.011515 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:05:25.015011 ===================================
728 10:05:25.018125 LPDDR4 DRAM CONFIGURATION
729 10:05:25.021441 ===================================
730 10:05:25.021528 EX_ROW_EN[0] = 0x0
731 10:05:25.024690 EX_ROW_EN[1] = 0x0
732 10:05:25.024801 LP4Y_EN = 0x0
733 10:05:25.028455 WORK_FSP = 0x0
734 10:05:25.028546 WL = 0x2
735 10:05:25.031695 RL = 0x2
736 10:05:25.031806 BL = 0x2
737 10:05:25.035418 RPST = 0x0
738 10:05:25.035498 RD_PRE = 0x0
739 10:05:25.038138 WR_PRE = 0x1
740 10:05:25.041436 WR_PST = 0x0
741 10:05:25.041514 DBI_WR = 0x0
742 10:05:25.044787 DBI_RD = 0x0
743 10:05:25.044886 OTF = 0x1
744 10:05:25.048098 ===================================
745 10:05:25.051521 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:05:25.055134 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:05:25.061532 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:05:25.064881 ===================================
749 10:05:25.064967 LPDDR4 DRAM CONFIGURATION
750 10:05:25.068775 ===================================
751 10:05:25.071926 EX_ROW_EN[0] = 0x10
752 10:05:25.075163 EX_ROW_EN[1] = 0x0
753 10:05:25.075281 LP4Y_EN = 0x0
754 10:05:25.078432 WORK_FSP = 0x0
755 10:05:25.078517 WL = 0x2
756 10:05:25.081763 RL = 0x2
757 10:05:25.081864 BL = 0x2
758 10:05:25.085484 RPST = 0x0
759 10:05:25.085595 RD_PRE = 0x0
760 10:05:25.088485 WR_PRE = 0x1
761 10:05:25.088561 WR_PST = 0x0
762 10:05:25.091900 DBI_WR = 0x0
763 10:05:25.091988 DBI_RD = 0x0
764 10:05:25.095553 OTF = 0x1
765 10:05:25.098928 ===================================
766 10:05:25.105471 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:05:25.108603 nWR fixed to 40
768 10:05:25.108684 [ModeRegInit_LP4] CH0 RK0
769 10:05:25.112346 [ModeRegInit_LP4] CH0 RK1
770 10:05:25.115614 [ModeRegInit_LP4] CH1 RK0
771 10:05:25.118686 [ModeRegInit_LP4] CH1 RK1
772 10:05:25.118773 match AC timing 13
773 10:05:25.121819 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:05:25.125296 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:05:25.131864 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:05:25.135725 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:05:25.142459 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:05:25.142586 [EMI DOE] emi_dcm 0
779 10:05:25.145478 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:05:25.148726 ==
781 10:05:25.152467 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:05:25.155478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:05:25.155566 ==
784 10:05:25.159240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:05:25.165439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:05:25.175524 [CA 0] Center 36 (6~67) winsize 62
787 10:05:25.178765 [CA 1] Center 36 (6~67) winsize 62
788 10:05:25.181981 [CA 2] Center 34 (4~65) winsize 62
789 10:05:25.185242 [CA 3] Center 33 (3~64) winsize 62
790 10:05:25.188549 [CA 4] Center 33 (3~63) winsize 61
791 10:05:25.191878 [CA 5] Center 32 (3~62) winsize 60
792 10:05:25.191964
793 10:05:25.195096 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 10:05:25.195177
795 10:05:25.198862 [CATrainingPosCal] consider 1 rank data
796 10:05:25.201922 u2DelayCellTimex100 = 270/100 ps
797 10:05:25.205281 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 10:05:25.208873 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 10:05:25.215283 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 10:05:25.219012 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 10:05:25.222347 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 10:05:25.225454 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 10:05:25.225566
804 10:05:25.228953 CA PerBit enable=1, Macro0, CA PI delay=32
805 10:05:25.229039
806 10:05:25.232226 [CBTSetCACLKResult] CA Dly = 32
807 10:05:25.232313 CS Dly: 4 (0~35)
808 10:05:25.232400 ==
809 10:05:25.235423 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:05:25.242137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:05:25.242224 ==
812 10:05:25.245084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:05:25.252027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:05:25.261487 [CA 0] Center 36 (6~67) winsize 62
815 10:05:25.264802 [CA 1] Center 36 (6~67) winsize 62
816 10:05:25.267849 [CA 2] Center 34 (3~65) winsize 63
817 10:05:25.271603 [CA 3] Center 33 (3~64) winsize 62
818 10:05:25.274746 [CA 4] Center 32 (2~63) winsize 62
819 10:05:25.277973 [CA 5] Center 32 (2~63) winsize 62
820 10:05:25.278064
821 10:05:25.281635 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:05:25.281723
823 10:05:25.284817 [CATrainingPosCal] consider 2 rank data
824 10:05:25.288106 u2DelayCellTimex100 = 270/100 ps
825 10:05:25.291881 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 10:05:25.295165 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 10:05:25.301770 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 10:05:25.304980 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 10:05:25.308266 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 10:05:25.311976 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 10:05:25.312064
832 10:05:25.314883 CA PerBit enable=1, Macro0, CA PI delay=32
833 10:05:25.314969
834 10:05:25.318384 [CBTSetCACLKResult] CA Dly = 32
835 10:05:25.318491 CS Dly: 5 (0~37)
836 10:05:25.318579
837 10:05:25.322568 ----->DramcWriteLeveling(PI) begin...
838 10:05:25.322656 ==
839 10:05:25.326410 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:05:25.329547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:05:25.329667 ==
842 10:05:25.333267 Write leveling (Byte 0): 33 => 33
843 10:05:25.337076 Write leveling (Byte 1): 30 => 30
844 10:05:25.340349 DramcWriteLeveling(PI) end<-----
845 10:05:25.340467
846 10:05:25.340555 ==
847 10:05:25.343530 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:05:25.347285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:05:25.347418 ==
850 10:05:25.351128 [Gating] SW mode calibration
851 10:05:25.358331 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:05:25.361392 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:05:25.368301 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:05:25.371698 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 10:05:25.374685 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 10:05:25.381959 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 10:05:25.384707 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:05:25.388414 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:05:25.395051 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:05:25.398350 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:05:25.401552 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:05:25.408765 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:05:25.411901 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:05:25.415238 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:05:25.421541 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:05:25.425283 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:05:25.428267 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:05:25.431607 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:05:25.438743 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:05:25.441796 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 10:05:25.445439 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
872 10:05:25.451910 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 10:05:25.455226 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:05:25.458914 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:05:25.465392 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:05:25.468485 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:05:25.472204 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:05:25.478955 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:05:25.482000 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
880 10:05:25.485650 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
881 10:05:25.488776 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:05:25.495742 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:05:25.498744 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:05:25.502303 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:05:25.509021 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:05:25.512323 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
887 10:05:25.515550 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
888 10:05:25.522093 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
889 10:05:25.525417 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:05:25.529298 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:05:25.535523 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:05:25.539108 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:05:25.542281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:05:25.549267 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
895 10:05:25.552586 0 11 8 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (1 1)
896 10:05:25.555477 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
897 10:05:25.562341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:05:25.565453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:05:25.568888 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:05:25.572459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:05:25.579340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:05:25.582444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 10:05:25.585511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 10:05:25.592270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:05:25.595629 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:05:25.598776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:05:25.605856 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:05:25.609015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:05:25.612512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:05:25.618857 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:05:25.622699 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:05:25.625918 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:05:25.632304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:05:25.635599 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:05:25.638796 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:05:25.645558 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:05:25.648890 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:05:25.652331 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 10:05:25.659278 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 10:05:25.662281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 10:05:25.665746 Total UI for P1: 0, mck2ui 16
922 10:05:25.669268 best dqsien dly found for B0: ( 0, 14, 6)
923 10:05:25.672295 Total UI for P1: 0, mck2ui 16
924 10:05:25.676236 best dqsien dly found for B1: ( 0, 14, 10)
925 10:05:25.679454 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 10:05:25.682948 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 10:05:25.683027
928 10:05:25.686611 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 10:05:25.689860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 10:05:25.693195 [Gating] SW calibration Done
931 10:05:25.693280 ==
932 10:05:25.696633 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:05:25.699470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:05:25.699557 ==
935 10:05:25.703207 RX Vref Scan: 0
936 10:05:25.703292
937 10:05:25.703359 RX Vref 0 -> 0, step: 1
938 10:05:25.703423
939 10:05:25.706500 RX Delay -130 -> 252, step: 16
940 10:05:25.709755 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
941 10:05:25.716226 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 10:05:25.720006 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
943 10:05:25.723633 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
944 10:05:25.726548 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 10:05:25.730019 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 10:05:25.733185 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
947 10:05:25.739772 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
948 10:05:25.742998 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
949 10:05:25.746220 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
950 10:05:25.749929 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
951 10:05:25.753173 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 10:05:25.759661 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
953 10:05:25.762843 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
954 10:05:25.766149 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 10:05:25.769454 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
956 10:05:25.769565 ==
957 10:05:25.772794 Dram Type= 6, Freq= 0, CH_0, rank 0
958 10:05:25.779964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 10:05:25.780072 ==
960 10:05:25.780169 DQS Delay:
961 10:05:25.783236 DQS0 = 0, DQS1 = 0
962 10:05:25.783322 DQM Delay:
963 10:05:25.783389 DQM0 = 88, DQM1 = 81
964 10:05:25.786301 DQ Delay:
965 10:05:25.789721 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 10:05:25.793433 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
967 10:05:25.793522 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
968 10:05:25.800350 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 10:05:25.800461
970 10:05:25.800559
971 10:05:25.800650 ==
972 10:05:25.803253 Dram Type= 6, Freq= 0, CH_0, rank 0
973 10:05:25.806649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 10:05:25.806802 ==
975 10:05:25.806897
976 10:05:25.806991
977 10:05:25.809941 TX Vref Scan disable
978 10:05:25.810016 == TX Byte 0 ==
979 10:05:25.816762 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 10:05:25.820247 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 10:05:25.820330 == TX Byte 1 ==
982 10:05:25.826764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 10:05:25.829969 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 10:05:25.830052 ==
985 10:05:25.833722 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:05:25.836609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:05:25.836693 ==
988 10:05:25.850386 TX Vref=22, minBit 4, minWin=27, winSum=446
989 10:05:25.854176 TX Vref=24, minBit 9, minWin=27, winSum=452
990 10:05:25.857159 TX Vref=26, minBit 2, minWin=28, winSum=455
991 10:05:25.860486 TX Vref=28, minBit 8, minWin=28, winSum=458
992 10:05:25.863703 TX Vref=30, minBit 8, minWin=28, winSum=459
993 10:05:25.867658 TX Vref=32, minBit 10, minWin=27, winSum=454
994 10:05:25.874015 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
995 10:05:25.874122
996 10:05:25.877287 Final TX Range 1 Vref 30
997 10:05:25.877391
998 10:05:25.877488 ==
999 10:05:25.880475 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 10:05:25.883703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 10:05:25.883816 ==
1002 10:05:25.883909
1003 10:05:25.887004
1004 10:05:25.887080 TX Vref Scan disable
1005 10:05:25.891040 == TX Byte 0 ==
1006 10:05:25.894247 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 10:05:25.897355 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 10:05:25.900582 == TX Byte 1 ==
1009 10:05:25.903753 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 10:05:25.907728 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 10:05:25.911088
1012 10:05:25.911194 [DATLAT]
1013 10:05:25.911296 Freq=800, CH0 RK0
1014 10:05:25.911391
1015 10:05:25.914283 DATLAT Default: 0xa
1016 10:05:25.914381 0, 0xFFFF, sum = 0
1017 10:05:25.917310 1, 0xFFFF, sum = 0
1018 10:05:25.917422 2, 0xFFFF, sum = 0
1019 10:05:25.920868 3, 0xFFFF, sum = 0
1020 10:05:25.920976 4, 0xFFFF, sum = 0
1021 10:05:25.924260 5, 0xFFFF, sum = 0
1022 10:05:25.924367 6, 0xFFFF, sum = 0
1023 10:05:25.927184 7, 0xFFFF, sum = 0
1024 10:05:25.927263 8, 0xFFFF, sum = 0
1025 10:05:25.930655 9, 0x0, sum = 1
1026 10:05:25.930734 10, 0x0, sum = 2
1027 10:05:25.933904 11, 0x0, sum = 3
1028 10:05:25.934015 12, 0x0, sum = 4
1029 10:05:25.937165 best_step = 10
1030 10:05:25.937274
1031 10:05:25.937367 ==
1032 10:05:25.940517 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 10:05:25.943991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 10:05:25.944097 ==
1035 10:05:25.947370 RX Vref Scan: 1
1036 10:05:25.947470
1037 10:05:25.947536 Set Vref Range= 32 -> 127
1038 10:05:25.947597
1039 10:05:25.950573 RX Vref 32 -> 127, step: 1
1040 10:05:25.950651
1041 10:05:25.954173 RX Delay -95 -> 252, step: 8
1042 10:05:25.954249
1043 10:05:25.957444 Set Vref, RX VrefLevel [Byte0]: 32
1044 10:05:25.960697 [Byte1]: 32
1045 10:05:25.960803
1046 10:05:25.964224 Set Vref, RX VrefLevel [Byte0]: 33
1047 10:05:25.967249 [Byte1]: 33
1048 10:05:25.970798
1049 10:05:25.970902 Set Vref, RX VrefLevel [Byte0]: 34
1050 10:05:25.973987 [Byte1]: 34
1051 10:05:25.978509
1052 10:05:25.978587 Set Vref, RX VrefLevel [Byte0]: 35
1053 10:05:25.981768 [Byte1]: 35
1054 10:05:25.986334
1055 10:05:25.986414 Set Vref, RX VrefLevel [Byte0]: 36
1056 10:05:25.989731 [Byte1]: 36
1057 10:05:25.994134
1058 10:05:25.994212 Set Vref, RX VrefLevel [Byte0]: 37
1059 10:05:25.997433 [Byte1]: 37
1060 10:05:26.001971
1061 10:05:26.002075 Set Vref, RX VrefLevel [Byte0]: 38
1062 10:05:26.004994 [Byte1]: 38
1063 10:05:26.008753
1064 10:05:26.008838 Set Vref, RX VrefLevel [Byte0]: 39
1065 10:05:26.012701 [Byte1]: 39
1066 10:05:26.016710
1067 10:05:26.016817 Set Vref, RX VrefLevel [Byte0]: 40
1068 10:05:26.019852 [Byte1]: 40
1069 10:05:26.024371
1070 10:05:26.024451 Set Vref, RX VrefLevel [Byte0]: 41
1071 10:05:26.027662 [Byte1]: 41
1072 10:05:26.031677
1073 10:05:26.031771 Set Vref, RX VrefLevel [Byte0]: 42
1074 10:05:26.034840 [Byte1]: 42
1075 10:05:26.039409
1076 10:05:26.039507 Set Vref, RX VrefLevel [Byte0]: 43
1077 10:05:26.042716 [Byte1]: 43
1078 10:05:26.046630
1079 10:05:26.046732 Set Vref, RX VrefLevel [Byte0]: 44
1080 10:05:26.050213 [Byte1]: 44
1081 10:05:26.054784
1082 10:05:26.054859 Set Vref, RX VrefLevel [Byte0]: 45
1083 10:05:26.057922 [Byte1]: 45
1084 10:05:26.062079
1085 10:05:26.062176 Set Vref, RX VrefLevel [Byte0]: 46
1086 10:05:26.065689 [Byte1]: 46
1087 10:05:26.069495
1088 10:05:26.069616 Set Vref, RX VrefLevel [Byte0]: 47
1089 10:05:26.072928 [Byte1]: 47
1090 10:05:26.077482
1091 10:05:26.077603 Set Vref, RX VrefLevel [Byte0]: 48
1092 10:05:26.080683 [Byte1]: 48
1093 10:05:26.085397
1094 10:05:26.085506 Set Vref, RX VrefLevel [Byte0]: 49
1095 10:05:26.088127 [Byte1]: 49
1096 10:05:26.092355
1097 10:05:26.092456 Set Vref, RX VrefLevel [Byte0]: 50
1098 10:05:26.095836 [Byte1]: 50
1099 10:05:26.100289
1100 10:05:26.100369 Set Vref, RX VrefLevel [Byte0]: 51
1101 10:05:26.103519 [Byte1]: 51
1102 10:05:26.107442
1103 10:05:26.107518 Set Vref, RX VrefLevel [Byte0]: 52
1104 10:05:26.111118 [Byte1]: 52
1105 10:05:26.115542
1106 10:05:26.115626 Set Vref, RX VrefLevel [Byte0]: 53
1107 10:05:26.118857 [Byte1]: 53
1108 10:05:26.122726
1109 10:05:26.122827 Set Vref, RX VrefLevel [Byte0]: 54
1110 10:05:26.125927 [Byte1]: 54
1111 10:05:26.130531
1112 10:05:26.130670 Set Vref, RX VrefLevel [Byte0]: 55
1113 10:05:26.133816 [Byte1]: 55
1114 10:05:26.137965
1115 10:05:26.138044 Set Vref, RX VrefLevel [Byte0]: 56
1116 10:05:26.141128 [Byte1]: 56
1117 10:05:26.145713
1118 10:05:26.145819 Set Vref, RX VrefLevel [Byte0]: 57
1119 10:05:26.149127 [Byte1]: 57
1120 10:05:26.153440
1121 10:05:26.153544 Set Vref, RX VrefLevel [Byte0]: 58
1122 10:05:26.156728 [Byte1]: 58
1123 10:05:26.161280
1124 10:05:26.161380 Set Vref, RX VrefLevel [Byte0]: 59
1125 10:05:26.164536 [Byte1]: 59
1126 10:05:26.168518
1127 10:05:26.168617 Set Vref, RX VrefLevel [Byte0]: 60
1128 10:05:26.171820 [Byte1]: 60
1129 10:05:26.176483
1130 10:05:26.176558 Set Vref, RX VrefLevel [Byte0]: 61
1131 10:05:26.179673 [Byte1]: 61
1132 10:05:26.184035
1133 10:05:26.184136 Set Vref, RX VrefLevel [Byte0]: 62
1134 10:05:26.186919 [Byte1]: 62
1135 10:05:26.191701
1136 10:05:26.191805 Set Vref, RX VrefLevel [Byte0]: 63
1137 10:05:26.194552 [Byte1]: 63
1138 10:05:26.199297
1139 10:05:26.199380 Set Vref, RX VrefLevel [Byte0]: 64
1140 10:05:26.202190 [Byte1]: 64
1141 10:05:26.206294
1142 10:05:26.206398 Set Vref, RX VrefLevel [Byte0]: 65
1143 10:05:26.209664 [Byte1]: 65
1144 10:05:26.213942
1145 10:05:26.214046 Set Vref, RX VrefLevel [Byte0]: 66
1146 10:05:26.217502 [Byte1]: 66
1147 10:05:26.221699
1148 10:05:26.221801 Set Vref, RX VrefLevel [Byte0]: 67
1149 10:05:26.224829 [Byte1]: 67
1150 10:05:26.229603
1151 10:05:26.229721 Set Vref, RX VrefLevel [Byte0]: 68
1152 10:05:26.232894 [Byte1]: 68
1153 10:05:26.236878
1154 10:05:26.236982 Set Vref, RX VrefLevel [Byte0]: 69
1155 10:05:26.240192 [Byte1]: 69
1156 10:05:26.244621
1157 10:05:26.244722 Set Vref, RX VrefLevel [Byte0]: 70
1158 10:05:26.247646 [Byte1]: 70
1159 10:05:26.252271
1160 10:05:26.252379 Set Vref, RX VrefLevel [Byte0]: 71
1161 10:05:26.255582 [Byte1]: 71
1162 10:05:26.259937
1163 10:05:26.260042 Set Vref, RX VrefLevel [Byte0]: 72
1164 10:05:26.263164 [Byte1]: 72
1165 10:05:26.267080
1166 10:05:26.267191 Set Vref, RX VrefLevel [Byte0]: 73
1167 10:05:26.270429 [Byte1]: 73
1168 10:05:26.274993
1169 10:05:26.275092 Set Vref, RX VrefLevel [Byte0]: 74
1170 10:05:26.278213 [Byte1]: 74
1171 10:05:26.282754
1172 10:05:26.282837 Set Vref, RX VrefLevel [Byte0]: 75
1173 10:05:26.286012 [Byte1]: 75
1174 10:05:26.289790
1175 10:05:26.289892 Set Vref, RX VrefLevel [Byte0]: 76
1176 10:05:26.293549 [Byte1]: 76
1177 10:05:26.298098
1178 10:05:26.298207 Final RX Vref Byte 0 = 60 to rank0
1179 10:05:26.301173 Final RX Vref Byte 1 = 59 to rank0
1180 10:05:26.304682 Final RX Vref Byte 0 = 60 to rank1
1181 10:05:26.307984 Final RX Vref Byte 1 = 59 to rank1==
1182 10:05:26.311221 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 10:05:26.317499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 10:05:26.317662 ==
1185 10:05:26.317749 DQS Delay:
1186 10:05:26.317834 DQS0 = 0, DQS1 = 0
1187 10:05:26.321378 DQM Delay:
1188 10:05:26.321503 DQM0 = 91, DQM1 = 85
1189 10:05:26.324552 DQ Delay:
1190 10:05:26.327783 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1191 10:05:26.327894 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1192 10:05:26.330949 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1193 10:05:26.334692 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1194 10:05:26.337554
1195 10:05:26.337651
1196 10:05:26.344247 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1197 10:05:26.347672 CH0 RK0: MR19=606, MR18=493F
1198 10:05:26.354142 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1199 10:05:26.354252
1200 10:05:26.357720 ----->DramcWriteLeveling(PI) begin...
1201 10:05:26.357798 ==
1202 10:05:26.360920 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 10:05:26.364505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 10:05:26.364608 ==
1205 10:05:26.367833 Write leveling (Byte 0): 33 => 33
1206 10:05:26.371061 Write leveling (Byte 1): 29 => 29
1207 10:05:26.374306 DramcWriteLeveling(PI) end<-----
1208 10:05:26.374403
1209 10:05:26.374492 ==
1210 10:05:26.378236 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 10:05:26.381510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 10:05:26.381615 ==
1213 10:05:26.384793 [Gating] SW mode calibration
1214 10:05:26.391338 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 10:05:26.438982 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 10:05:26.439113 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 10:05:26.439487 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 10:05:26.439601 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1219 10:05:26.439737 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:05:26.439842 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:05:26.439977 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:05:26.440093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:05:26.440209 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:05:26.440300 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:05:26.451851 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:05:26.451978 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:05:26.452279 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:05:26.455025 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:05:26.458749 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:05:26.461761 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:05:26.468878 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:05:26.471648 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:05:26.474928 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1234 10:05:26.481917 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1235 10:05:26.485160 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1236 10:05:26.488482 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:05:26.495039 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 10:05:26.498254 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 10:05:26.501901 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 10:05:26.505040 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:05:26.511598 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:05:26.514849 0 9 8 | B1->B0 | 2e2e 2d2d | 0 0 | (0 0) (0 0)
1243 10:05:26.518554 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 10:05:26.524974 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 10:05:26.528429 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 10:05:26.532076 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 10:05:26.538340 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 10:05:26.541630 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 10:05:26.545612 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 10:05:26.552001 0 10 8 | B1->B0 | 2b2b 2727 | 1 1 | (1 1) (1 1)
1251 10:05:26.555206 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:05:26.558947 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:05:26.565921 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:05:26.569657 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 10:05:26.573417 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 10:05:26.577430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 10:05:26.581247 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1258 10:05:26.584557 0 11 8 | B1->B0 | 4242 3b3b | 0 0 | (0 0) (0 0)
1259 10:05:26.591666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 10:05:26.594871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 10:05:26.598204 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 10:05:26.604693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 10:05:26.608236 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 10:05:26.612074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 10:05:26.614695 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 10:05:26.621722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 10:05:26.624987 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:05:26.628284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:05:26.635224 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:05:26.638071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:05:26.641507 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:05:26.648249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:05:26.651443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:05:26.655268 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:05:26.661715 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:05:26.665400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:05:26.668566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:05:26.675085 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 10:05:26.678310 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 10:05:26.681664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 10:05:26.688198 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 10:05:26.692036 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 10:05:26.695269 Total UI for P1: 0, mck2ui 16
1284 10:05:26.698443 best dqsien dly found for B0: ( 0, 14, 6)
1285 10:05:26.701505 Total UI for P1: 0, mck2ui 16
1286 10:05:26.705303 best dqsien dly found for B1: ( 0, 14, 6)
1287 10:05:26.708342 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1288 10:05:26.711877 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1289 10:05:26.711951
1290 10:05:26.715270 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1291 10:05:26.718513 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 10:05:26.721697 [Gating] SW calibration Done
1293 10:05:26.721792 ==
1294 10:05:26.725095 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 10:05:26.728258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 10:05:26.728335 ==
1297 10:05:26.731553 RX Vref Scan: 0
1298 10:05:26.731649
1299 10:05:26.731738 RX Vref 0 -> 0, step: 1
1300 10:05:26.731854
1301 10:05:26.735375 RX Delay -130 -> 252, step: 16
1302 10:05:26.738581 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1303 10:05:26.745514 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1304 10:05:26.748650 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1305 10:05:26.751562 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1306 10:05:26.755013 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1307 10:05:26.758371 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1308 10:05:26.765357 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1309 10:05:26.768407 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1310 10:05:26.772145 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1311 10:05:26.775452 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1312 10:05:26.778725 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1313 10:05:26.784999 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1314 10:05:26.788872 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1315 10:05:26.792218 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1316 10:05:26.795458 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1317 10:05:26.798755 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1318 10:05:26.802141 ==
1319 10:05:26.805143 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 10:05:26.808858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 10:05:26.808964 ==
1322 10:05:26.809057 DQS Delay:
1323 10:05:26.812055 DQS0 = 0, DQS1 = 0
1324 10:05:26.812158 DQM Delay:
1325 10:05:26.815326 DQM0 = 91, DQM1 = 82
1326 10:05:26.815429 DQ Delay:
1327 10:05:26.818586 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1328 10:05:26.821651 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1329 10:05:26.825358 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1330 10:05:26.828920 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1331 10:05:26.829092
1332 10:05:26.829190
1333 10:05:26.829298 ==
1334 10:05:26.832223 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 10:05:26.835465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 10:05:26.835546 ==
1337 10:05:26.835613
1338 10:05:26.835674
1339 10:05:26.838617 TX Vref Scan disable
1340 10:05:26.841872 == TX Byte 0 ==
1341 10:05:26.845534 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1342 10:05:26.848569 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1343 10:05:26.851810 == TX Byte 1 ==
1344 10:05:26.855076 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1345 10:05:26.858788 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1346 10:05:26.858873 ==
1347 10:05:26.861863 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 10:05:26.865570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 10:05:26.868560 ==
1350 10:05:26.880418 TX Vref=22, minBit 9, minWin=27, winSum=448
1351 10:05:26.883699 TX Vref=24, minBit 11, minWin=27, winSum=451
1352 10:05:26.886762 TX Vref=26, minBit 8, minWin=28, winSum=460
1353 10:05:26.890424 TX Vref=28, minBit 12, minWin=27, winSum=454
1354 10:05:26.893848 TX Vref=30, minBit 7, minWin=28, winSum=461
1355 10:05:26.900317 TX Vref=32, minBit 2, minWin=28, winSum=456
1356 10:05:26.903656 [TxChooseVref] Worse bit 7, Min win 28, Win sum 461, Final Vref 30
1357 10:05:26.903740
1358 10:05:26.906935 Final TX Range 1 Vref 30
1359 10:05:26.907020
1360 10:05:26.907085 ==
1361 10:05:26.910212 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 10:05:26.913310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 10:05:26.916599 ==
1364 10:05:26.916684
1365 10:05:26.916749
1366 10:05:26.916810 TX Vref Scan disable
1367 10:05:26.920625 == TX Byte 0 ==
1368 10:05:26.923885 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1369 10:05:26.927151 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1370 10:05:26.930303 == TX Byte 1 ==
1371 10:05:26.933609 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1372 10:05:26.936985 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1373 10:05:26.940781
1374 10:05:26.940862 [DATLAT]
1375 10:05:26.940926 Freq=800, CH0 RK1
1376 10:05:26.940986
1377 10:05:26.943732 DATLAT Default: 0xa
1378 10:05:26.943815 0, 0xFFFF, sum = 0
1379 10:05:26.947041 1, 0xFFFF, sum = 0
1380 10:05:26.947124 2, 0xFFFF, sum = 0
1381 10:05:26.950586 3, 0xFFFF, sum = 0
1382 10:05:26.950669 4, 0xFFFF, sum = 0
1383 10:05:26.954037 5, 0xFFFF, sum = 0
1384 10:05:26.954121 6, 0xFFFF, sum = 0
1385 10:05:26.957295 7, 0xFFFF, sum = 0
1386 10:05:26.957378 8, 0xFFFF, sum = 0
1387 10:05:26.960647 9, 0x0, sum = 1
1388 10:05:26.960746 10, 0x0, sum = 2
1389 10:05:26.964181 11, 0x0, sum = 3
1390 10:05:26.964264 12, 0x0, sum = 4
1391 10:05:26.967041 best_step = 10
1392 10:05:26.967141
1393 10:05:26.967238 ==
1394 10:05:26.970701 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 10:05:26.973916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 10:05:26.973992 ==
1397 10:05:26.977400 RX Vref Scan: 0
1398 10:05:26.977500
1399 10:05:26.977609 RX Vref 0 -> 0, step: 1
1400 10:05:26.977684
1401 10:05:26.980424 RX Delay -79 -> 252, step: 8
1402 10:05:26.987539 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1403 10:05:26.990582 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1404 10:05:26.994219 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 10:05:26.997463 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1406 10:05:27.000589 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 10:05:27.004517 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1408 10:05:27.010760 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 10:05:27.014051 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 10:05:27.017289 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1411 10:05:27.020983 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1412 10:05:27.024229 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1413 10:05:27.031446 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1414 10:05:27.034638 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1415 10:05:27.037895 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 10:05:27.041000 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 10:05:27.044350 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1418 10:05:27.047546 ==
1419 10:05:27.051188 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 10:05:27.054406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 10:05:27.054481 ==
1422 10:05:27.054544 DQS Delay:
1423 10:05:27.057465 DQS0 = 0, DQS1 = 0
1424 10:05:27.057561 DQM Delay:
1425 10:05:27.061339 DQM0 = 92, DQM1 = 81
1426 10:05:27.061435 DQ Delay:
1427 10:05:27.064486 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1428 10:05:27.067925 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1429 10:05:27.070775 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1430 10:05:27.074232 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1431 10:05:27.074305
1432 10:05:27.074381
1433 10:05:27.081269 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1434 10:05:27.084235 CH0 RK1: MR19=606, MR18=4212
1435 10:05:27.091089 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1436 10:05:27.094163 [RxdqsGatingPostProcess] freq 800
1437 10:05:27.097641 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 10:05:27.101187 Pre-setting of DQS Precalculation
1439 10:05:27.107612 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 10:05:27.107691 ==
1441 10:05:27.111295 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 10:05:27.114550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 10:05:27.114640 ==
1444 10:05:27.120973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 10:05:27.127686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 10:05:27.135475 [CA 0] Center 36 (6~67) winsize 62
1447 10:05:27.138692 [CA 1] Center 36 (6~67) winsize 62
1448 10:05:27.141988 [CA 2] Center 34 (4~65) winsize 62
1449 10:05:27.145299 [CA 3] Center 35 (5~65) winsize 61
1450 10:05:27.148632 [CA 4] Center 35 (5~65) winsize 61
1451 10:05:27.152541 [CA 5] Center 34 (4~65) winsize 62
1452 10:05:27.152624
1453 10:05:27.155537 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1454 10:05:27.155646
1455 10:05:27.158846 [CATrainingPosCal] consider 1 rank data
1456 10:05:27.162021 u2DelayCellTimex100 = 270/100 ps
1457 10:05:27.165194 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 10:05:27.169170 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 10:05:27.175322 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 10:05:27.178546 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 10:05:27.182310 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1462 10:05:27.185255 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 10:05:27.185345
1464 10:05:27.188777 CA PerBit enable=1, Macro0, CA PI delay=34
1465 10:05:27.188902
1466 10:05:27.192225 [CBTSetCACLKResult] CA Dly = 34
1467 10:05:27.192330 CS Dly: 6 (0~37)
1468 10:05:27.192421 ==
1469 10:05:27.195435 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 10:05:27.201905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 10:05:27.201989 ==
1472 10:05:27.205351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 10:05:27.212296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 10:05:27.221554 [CA 0] Center 36 (6~67) winsize 62
1475 10:05:27.224741 [CA 1] Center 37 (6~68) winsize 63
1476 10:05:27.228773 [CA 2] Center 35 (5~66) winsize 62
1477 10:05:27.232578 [CA 3] Center 35 (5~65) winsize 61
1478 10:05:27.236269 [CA 4] Center 35 (5~66) winsize 62
1479 10:05:27.240085 [CA 5] Center 34 (4~65) winsize 62
1480 10:05:27.240164
1481 10:05:27.243338 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1482 10:05:27.243413
1483 10:05:27.246603 [CATrainingPosCal] consider 2 rank data
1484 10:05:27.249865 u2DelayCellTimex100 = 270/100 ps
1485 10:05:27.253668 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 10:05:27.257474 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 10:05:27.261213 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 10:05:27.265333 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1489 10:05:27.268180 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1490 10:05:27.271380 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 10:05:27.271459
1492 10:05:27.275286 CA PerBit enable=1, Macro0, CA PI delay=34
1493 10:05:27.275357
1494 10:05:27.278285 [CBTSetCACLKResult] CA Dly = 34
1495 10:05:27.278356 CS Dly: 6 (0~38)
1496 10:05:27.278417
1497 10:05:27.281527 ----->DramcWriteLeveling(PI) begin...
1498 10:05:27.284839 ==
1499 10:05:27.284911 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 10:05:27.291707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 10:05:27.291779 ==
1502 10:05:27.294803 Write leveling (Byte 0): 26 => 26
1503 10:05:27.298534 Write leveling (Byte 1): 26 => 26
1504 10:05:27.301505 DramcWriteLeveling(PI) end<-----
1505 10:05:27.301599
1506 10:05:27.301679 ==
1507 10:05:27.305297 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 10:05:27.308426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 10:05:27.308528 ==
1510 10:05:27.311493 [Gating] SW mode calibration
1511 10:05:27.318047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 10:05:27.321823 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 10:05:27.328669 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 10:05:27.332170 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1515 10:05:27.335299 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1516 10:05:27.341730 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:05:27.345502 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:05:27.348768 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:05:27.355329 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:05:27.358533 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:05:27.361704 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:05:27.368694 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:05:27.371829 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:05:27.374914 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:05:27.381953 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:05:27.385043 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:05:27.388324 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:05:27.391443 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:05:27.398523 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1530 10:05:27.402165 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1531 10:05:27.405046 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:05:27.411904 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:05:27.415140 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 10:05:27.418308 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 10:05:27.425008 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 10:05:27.428505 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 10:05:27.432195 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 10:05:27.438398 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1539 10:05:27.441906 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1540 10:05:27.445462 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 10:05:27.452204 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 10:05:27.455453 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 10:05:27.458675 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 10:05:27.461924 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 10:05:27.468725 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1546 10:05:27.472030 0 10 4 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 1)
1547 10:05:27.475833 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:05:27.482245 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:05:27.485442 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:05:27.488629 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:05:27.495791 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:05:27.498978 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 10:05:27.502182 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 10:05:27.509024 0 11 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (0 0)
1555 10:05:27.512083 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1556 10:05:27.515671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 10:05:27.522134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 10:05:27.525857 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 10:05:27.529153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 10:05:27.535382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 10:05:27.538936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 10:05:27.542091 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1563 10:05:27.545956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:05:27.552440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:05:27.555322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:05:27.558811 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:05:27.565748 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:05:27.569091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:05:27.572177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:05:27.578735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:05:27.582574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:05:27.585721 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:05:27.592009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:05:27.595912 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:05:27.599076 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 10:05:27.605442 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 10:05:27.608726 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 10:05:27.612552 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1579 10:05:27.615725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 10:05:27.618847 Total UI for P1: 0, mck2ui 16
1581 10:05:27.622375 best dqsien dly found for B0: ( 0, 14, 4)
1582 10:05:27.625628 Total UI for P1: 0, mck2ui 16
1583 10:05:27.629501 best dqsien dly found for B1: ( 0, 14, 4)
1584 10:05:27.632660 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1585 10:05:27.635868 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1586 10:05:27.638994
1587 10:05:27.642691 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1588 10:05:27.645639 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 10:05:27.649156 [Gating] SW calibration Done
1590 10:05:27.649261 ==
1591 10:05:27.652304 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:05:27.655523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:05:27.655629 ==
1594 10:05:27.655723 RX Vref Scan: 0
1595 10:05:27.655810
1596 10:05:27.659198 RX Vref 0 -> 0, step: 1
1597 10:05:27.659300
1598 10:05:27.662233 RX Delay -130 -> 252, step: 16
1599 10:05:27.665908 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 10:05:27.669486 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 10:05:27.676163 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1602 10:05:27.679118 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 10:05:27.682344 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1604 10:05:27.685561 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1605 10:05:27.689501 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 10:05:27.692588 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 10:05:27.699398 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1608 10:05:27.702690 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 10:05:27.705877 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1610 10:05:27.708884 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 10:05:27.715991 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 10:05:27.719153 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 10:05:27.722295 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1614 10:05:27.725628 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1615 10:05:27.725751 ==
1616 10:05:27.729264 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 10:05:27.732286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 10:05:27.735820 ==
1619 10:05:27.735933 DQS Delay:
1620 10:05:27.736026 DQS0 = 0, DQS1 = 0
1621 10:05:27.739112 DQM Delay:
1622 10:05:27.739185 DQM0 = 93, DQM1 = 86
1623 10:05:27.742318 DQ Delay:
1624 10:05:27.746074 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1625 10:05:27.746182 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1626 10:05:27.749128 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1627 10:05:27.752413 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1628 10:05:27.755614
1629 10:05:27.755715
1630 10:05:27.755808 ==
1631 10:05:27.759327 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 10:05:27.762647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 10:05:27.762720 ==
1634 10:05:27.762782
1635 10:05:27.762840
1636 10:05:27.765748 TX Vref Scan disable
1637 10:05:27.765816 == TX Byte 0 ==
1638 10:05:27.772819 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1639 10:05:27.776011 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1640 10:05:27.776085 == TX Byte 1 ==
1641 10:05:27.782556 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1642 10:05:27.785945 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1643 10:05:27.786047 ==
1644 10:05:27.789532 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 10:05:27.792263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 10:05:27.792332 ==
1647 10:05:27.805860 TX Vref=22, minBit 0, minWin=26, winSum=427
1648 10:05:27.809759 TX Vref=24, minBit 3, minWin=26, winSum=433
1649 10:05:27.813845 TX Vref=26, minBit 0, minWin=27, winSum=440
1650 10:05:27.816821 TX Vref=28, minBit 1, minWin=27, winSum=441
1651 10:05:27.819990 TX Vref=30, minBit 1, minWin=27, winSum=449
1652 10:05:27.823776 TX Vref=32, minBit 1, minWin=27, winSum=444
1653 10:05:27.830330 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1654 10:05:27.830413
1655 10:05:27.833608 Final TX Range 1 Vref 30
1656 10:05:27.833706
1657 10:05:27.833771 ==
1658 10:05:27.836540 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 10:05:27.839970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 10:05:27.840069 ==
1661 10:05:27.840166
1662 10:05:27.840240
1663 10:05:27.843735 TX Vref Scan disable
1664 10:05:27.846893 == TX Byte 0 ==
1665 10:05:27.850129 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1666 10:05:27.853132 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1667 10:05:27.857007 == TX Byte 1 ==
1668 10:05:27.860210 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1669 10:05:27.863811 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1670 10:05:27.863894
1671 10:05:27.863958 [DATLAT]
1672 10:05:27.867012 Freq=800, CH1 RK0
1673 10:05:27.867095
1674 10:05:27.870232 DATLAT Default: 0xa
1675 10:05:27.870314 0, 0xFFFF, sum = 0
1676 10:05:27.873948 1, 0xFFFF, sum = 0
1677 10:05:27.874060 2, 0xFFFF, sum = 0
1678 10:05:27.876612 3, 0xFFFF, sum = 0
1679 10:05:27.876726 4, 0xFFFF, sum = 0
1680 10:05:27.880544 5, 0xFFFF, sum = 0
1681 10:05:27.880639 6, 0xFFFF, sum = 0
1682 10:05:27.883763 7, 0xFFFF, sum = 0
1683 10:05:27.883846 8, 0xFFFF, sum = 0
1684 10:05:27.887046 9, 0x0, sum = 1
1685 10:05:27.887123 10, 0x0, sum = 2
1686 10:05:27.890385 11, 0x0, sum = 3
1687 10:05:27.890461 12, 0x0, sum = 4
1688 10:05:27.890523 best_step = 10
1689 10:05:27.890581
1690 10:05:27.894101 ==
1691 10:05:27.894209 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 10:05:27.900263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 10:05:27.900365 ==
1694 10:05:27.900459 RX Vref Scan: 1
1695 10:05:27.900548
1696 10:05:27.903567 Set Vref Range= 32 -> 127
1697 10:05:27.903664
1698 10:05:27.907078 RX Vref 32 -> 127, step: 1
1699 10:05:27.907173
1700 10:05:27.910476 RX Delay -79 -> 252, step: 8
1701 10:05:27.910564
1702 10:05:27.913750 Set Vref, RX VrefLevel [Byte0]: 32
1703 10:05:27.917026 [Byte1]: 32
1704 10:05:27.917128
1705 10:05:27.920637 Set Vref, RX VrefLevel [Byte0]: 33
1706 10:05:27.923530 [Byte1]: 33
1707 10:05:27.923603
1708 10:05:27.927392 Set Vref, RX VrefLevel [Byte0]: 34
1709 10:05:27.930760 [Byte1]: 34
1710 10:05:27.930842
1711 10:05:27.934045 Set Vref, RX VrefLevel [Byte0]: 35
1712 10:05:27.937168 [Byte1]: 35
1713 10:05:27.941009
1714 10:05:27.941090 Set Vref, RX VrefLevel [Byte0]: 36
1715 10:05:27.944706 [Byte1]: 36
1716 10:05:27.948906
1717 10:05:27.949000 Set Vref, RX VrefLevel [Byte0]: 37
1718 10:05:27.951713 [Byte1]: 37
1719 10:05:27.956116
1720 10:05:27.956194 Set Vref, RX VrefLevel [Byte0]: 38
1721 10:05:27.959215 [Byte1]: 38
1722 10:05:27.963817
1723 10:05:27.963895 Set Vref, RX VrefLevel [Byte0]: 39
1724 10:05:27.966958 [Byte1]: 39
1725 10:05:27.971245
1726 10:05:27.971327 Set Vref, RX VrefLevel [Byte0]: 40
1727 10:05:27.974462 [Byte1]: 40
1728 10:05:27.978886
1729 10:05:27.978989 Set Vref, RX VrefLevel [Byte0]: 41
1730 10:05:27.981902 [Byte1]: 41
1731 10:05:27.986584
1732 10:05:27.986690 Set Vref, RX VrefLevel [Byte0]: 42
1733 10:05:27.989848 [Byte1]: 42
1734 10:05:27.993826
1735 10:05:27.993932 Set Vref, RX VrefLevel [Byte0]: 43
1736 10:05:27.997111 [Byte1]: 43
1737 10:05:28.000944
1738 10:05:28.004786 Set Vref, RX VrefLevel [Byte0]: 44
1739 10:05:28.007900 [Byte1]: 44
1740 10:05:28.007974
1741 10:05:28.011231 Set Vref, RX VrefLevel [Byte0]: 45
1742 10:05:28.014881 [Byte1]: 45
1743 10:05:28.014971
1744 10:05:28.018194 Set Vref, RX VrefLevel [Byte0]: 46
1745 10:05:28.021433 [Byte1]: 46
1746 10:05:28.021538
1747 10:05:28.024472 Set Vref, RX VrefLevel [Byte0]: 47
1748 10:05:28.027933 [Byte1]: 47
1749 10:05:28.031840
1750 10:05:28.031950 Set Vref, RX VrefLevel [Byte0]: 48
1751 10:05:28.035326 [Byte1]: 48
1752 10:05:28.038974
1753 10:05:28.039056 Set Vref, RX VrefLevel [Byte0]: 49
1754 10:05:28.042297 [Byte1]: 49
1755 10:05:28.046851
1756 10:05:28.046955 Set Vref, RX VrefLevel [Byte0]: 50
1757 10:05:28.049968 [Byte1]: 50
1758 10:05:28.054372
1759 10:05:28.054454 Set Vref, RX VrefLevel [Byte0]: 51
1760 10:05:28.057427 [Byte1]: 51
1761 10:05:28.062043
1762 10:05:28.062121 Set Vref, RX VrefLevel [Byte0]: 52
1763 10:05:28.065024 [Byte1]: 52
1764 10:05:28.069459
1765 10:05:28.069591 Set Vref, RX VrefLevel [Byte0]: 53
1766 10:05:28.072734 [Byte1]: 53
1767 10:05:28.077041
1768 10:05:28.077145 Set Vref, RX VrefLevel [Byte0]: 54
1769 10:05:28.080267 [Byte1]: 54
1770 10:05:28.084696
1771 10:05:28.084773 Set Vref, RX VrefLevel [Byte0]: 55
1772 10:05:28.087669 [Byte1]: 55
1773 10:05:28.092326
1774 10:05:28.092426 Set Vref, RX VrefLevel [Byte0]: 56
1775 10:05:28.095519 [Byte1]: 56
1776 10:05:28.099407
1777 10:05:28.099513 Set Vref, RX VrefLevel [Byte0]: 57
1778 10:05:28.103209 [Byte1]: 57
1779 10:05:28.107152
1780 10:05:28.107255 Set Vref, RX VrefLevel [Byte0]: 58
1781 10:05:28.110375 [Byte1]: 58
1782 10:05:28.114689
1783 10:05:28.114764 Set Vref, RX VrefLevel [Byte0]: 59
1784 10:05:28.117999 [Byte1]: 59
1785 10:05:28.121970
1786 10:05:28.122048 Set Vref, RX VrefLevel [Byte0]: 60
1787 10:05:28.125665 [Byte1]: 60
1788 10:05:28.130149
1789 10:05:28.130235 Set Vref, RX VrefLevel [Byte0]: 61
1790 10:05:28.133265 [Byte1]: 61
1791 10:05:28.137121
1792 10:05:28.137237 Set Vref, RX VrefLevel [Byte0]: 62
1793 10:05:28.140329 [Byte1]: 62
1794 10:05:28.144774
1795 10:05:28.144912 Set Vref, RX VrefLevel [Byte0]: 63
1796 10:05:28.147873 [Byte1]: 63
1797 10:05:28.152386
1798 10:05:28.152522 Set Vref, RX VrefLevel [Byte0]: 64
1799 10:05:28.155594 [Byte1]: 64
1800 10:05:28.160211
1801 10:05:28.160288 Set Vref, RX VrefLevel [Byte0]: 65
1802 10:05:28.163042 [Byte1]: 65
1803 10:05:28.167763
1804 10:05:28.167840 Set Vref, RX VrefLevel [Byte0]: 66
1805 10:05:28.170848 [Byte1]: 66
1806 10:05:28.175232
1807 10:05:28.175307 Set Vref, RX VrefLevel [Byte0]: 67
1808 10:05:28.178243 [Byte1]: 67
1809 10:05:28.182484
1810 10:05:28.182574 Set Vref, RX VrefLevel [Byte0]: 68
1811 10:05:28.185785 [Byte1]: 68
1812 10:05:28.190269
1813 10:05:28.190376 Set Vref, RX VrefLevel [Byte0]: 69
1814 10:05:28.193320 [Byte1]: 69
1815 10:05:28.197755
1816 10:05:28.197846 Set Vref, RX VrefLevel [Byte0]: 70
1817 10:05:28.200986 [Byte1]: 70
1818 10:05:28.205527
1819 10:05:28.205652 Set Vref, RX VrefLevel [Byte0]: 71
1820 10:05:28.208746 [Byte1]: 71
1821 10:05:28.212749
1822 10:05:28.212847 Set Vref, RX VrefLevel [Byte0]: 72
1823 10:05:28.215989 [Byte1]: 72
1824 10:05:28.220322
1825 10:05:28.220435 Final RX Vref Byte 0 = 57 to rank0
1826 10:05:28.223443 Final RX Vref Byte 1 = 54 to rank0
1827 10:05:28.227347 Final RX Vref Byte 0 = 57 to rank1
1828 10:05:28.230214 Final RX Vref Byte 1 = 54 to rank1==
1829 10:05:28.234054 Dram Type= 6, Freq= 0, CH_1, rank 0
1830 10:05:28.237225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 10:05:28.240449 ==
1832 10:05:28.240525 DQS Delay:
1833 10:05:28.240599 DQS0 = 0, DQS1 = 0
1834 10:05:28.243686 DQM Delay:
1835 10:05:28.243755 DQM0 = 94, DQM1 = 89
1836 10:05:28.246920 DQ Delay:
1837 10:05:28.250237 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1838 10:05:28.253428 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =92
1839 10:05:28.257182 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1840 10:05:28.260256 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1841 10:05:28.260355
1842 10:05:28.260456
1843 10:05:28.267064 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1844 10:05:28.270346 CH1 RK0: MR19=606, MR18=2A46
1845 10:05:28.276945 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1846 10:05:28.277025
1847 10:05:28.280429 ----->DramcWriteLeveling(PI) begin...
1848 10:05:28.280534 ==
1849 10:05:28.283836 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 10:05:28.287182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 10:05:28.287289 ==
1852 10:05:28.290665 Write leveling (Byte 0): 29 => 29
1853 10:05:28.293869 Write leveling (Byte 1): 28 => 28
1854 10:05:28.297484 DramcWriteLeveling(PI) end<-----
1855 10:05:28.297597
1856 10:05:28.297734 ==
1857 10:05:28.300372 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 10:05:28.303980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 10:05:28.304081 ==
1860 10:05:28.307202 [Gating] SW mode calibration
1861 10:05:28.313797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1862 10:05:28.320483 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1863 10:05:28.324164 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1864 10:05:28.327281 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1865 10:05:28.334231 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 10:05:28.337289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 10:05:28.340600 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 10:05:28.347703 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:05:28.350873 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:05:28.354173 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:05:28.357439 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:05:28.364452 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:05:28.367464 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:05:28.370731 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:05:28.378067 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:05:28.381470 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:05:28.384567 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:05:28.390946 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:05:28.394298 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1880 10:05:28.397868 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1881 10:05:28.404262 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1882 10:05:28.407451 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:05:28.411073 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:05:28.417942 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:05:28.421380 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:05:28.424712 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:05:28.427848 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:05:28.434846 0 9 4 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
1889 10:05:28.437836 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1890 10:05:28.441460 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 10:05:28.447874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 10:05:28.451631 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 10:05:28.454983 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 10:05:28.461347 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 10:05:28.464600 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
1896 10:05:28.467742 0 10 4 | B1->B0 | 2525 3030 | 0 0 | (1 0) (0 1)
1897 10:05:28.474729 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1898 10:05:28.477987 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 10:05:28.481880 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 10:05:28.484805 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 10:05:28.491537 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:05:28.494667 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:05:28.497877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:05:28.505161 0 11 4 | B1->B0 | 3e3e 2727 | 0 0 | (0 0) (0 0)
1905 10:05:28.508502 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 10:05:28.511571 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 10:05:28.518469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 10:05:28.521403 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 10:05:28.525012 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 10:05:28.531523 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 10:05:28.535050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 10:05:28.538268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1913 10:05:28.544924 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 10:05:28.548270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 10:05:28.551366 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 10:05:28.558616 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 10:05:28.561667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:05:28.564873 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:05:28.568199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:05:28.575199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:05:28.578410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:05:28.581647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:05:28.588098 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:05:28.592003 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:05:28.595155 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:05:28.601840 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:05:28.605088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:05:28.608425 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1929 10:05:28.614932 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 10:05:28.615018 Total UI for P1: 0, mck2ui 16
1931 10:05:28.622092 best dqsien dly found for B0: ( 0, 14, 4)
1932 10:05:28.622170 Total UI for P1: 0, mck2ui 16
1933 10:05:28.625307 best dqsien dly found for B1: ( 0, 14, 4)
1934 10:05:28.632232 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1935 10:05:28.635392 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1936 10:05:28.635467
1937 10:05:28.638967 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1938 10:05:28.642245 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1939 10:05:28.645647 [Gating] SW calibration Done
1940 10:05:28.645730 ==
1941 10:05:28.649261 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 10:05:28.652449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 10:05:28.652533 ==
1944 10:05:28.652597 RX Vref Scan: 0
1945 10:05:28.652658
1946 10:05:28.655614 RX Vref 0 -> 0, step: 1
1947 10:05:28.655717
1948 10:05:28.658826 RX Delay -130 -> 252, step: 16
1949 10:05:28.662471 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1950 10:05:28.665496 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1951 10:05:28.672020 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1952 10:05:28.675526 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1953 10:05:28.678636 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1954 10:05:28.682265 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1955 10:05:28.685719 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1956 10:05:28.688987 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1957 10:05:28.695997 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1958 10:05:28.698713 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1959 10:05:28.702435 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1960 10:05:28.705515 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1961 10:05:28.712513 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1962 10:05:28.715734 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1963 10:05:28.718939 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1964 10:05:28.722042 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1965 10:05:28.722119 ==
1966 10:05:28.726086 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 10:05:28.729268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 10:05:28.732415 ==
1969 10:05:28.732492 DQS Delay:
1970 10:05:28.732555 DQS0 = 0, DQS1 = 0
1971 10:05:28.735514 DQM Delay:
1972 10:05:28.735590 DQM0 = 92, DQM1 = 91
1973 10:05:28.738761 DQ Delay:
1974 10:05:28.738860 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1975 10:05:28.742692 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1976 10:05:28.748976 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1977 10:05:28.752182 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1978 10:05:28.752314
1979 10:05:28.752392
1980 10:05:28.752513 ==
1981 10:05:28.755318 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 10:05:28.759002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 10:05:28.759088 ==
1984 10:05:28.759178
1985 10:05:28.759264
1986 10:05:28.762319 TX Vref Scan disable
1987 10:05:28.762398 == TX Byte 0 ==
1988 10:05:28.768759 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1989 10:05:28.772044 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1990 10:05:28.772142 == TX Byte 1 ==
1991 10:05:28.779142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 10:05:28.782304 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 10:05:28.782390 ==
1994 10:05:28.785300 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 10:05:28.788975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 10:05:28.789093 ==
1997 10:05:28.803227 TX Vref=22, minBit 1, minWin=27, winSum=446
1998 10:05:28.806582 TX Vref=24, minBit 2, minWin=27, winSum=447
1999 10:05:28.809541 TX Vref=26, minBit 2, minWin=27, winSum=448
2000 10:05:28.812794 TX Vref=28, minBit 2, minWin=27, winSum=448
2001 10:05:28.816427 TX Vref=30, minBit 2, minWin=27, winSum=450
2002 10:05:28.819803 TX Vref=32, minBit 2, minWin=27, winSum=448
2003 10:05:28.826671 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
2004 10:05:28.826820
2005 10:05:28.829799 Final TX Range 1 Vref 30
2006 10:05:28.829920
2007 10:05:28.830020 ==
2008 10:05:28.832983 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 10:05:28.836243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 10:05:28.836358 ==
2011 10:05:28.836477
2012 10:05:28.836602
2013 10:05:28.839960 TX Vref Scan disable
2014 10:05:28.843280 == TX Byte 0 ==
2015 10:05:28.846515 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2016 10:05:28.850139 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2017 10:05:28.853433 == TX Byte 1 ==
2018 10:05:28.856726 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 10:05:28.860036 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 10:05:28.860170
2021 10:05:28.863258 [DATLAT]
2022 10:05:28.863360 Freq=800, CH1 RK1
2023 10:05:28.863449
2024 10:05:28.866338 DATLAT Default: 0xa
2025 10:05:28.866430 0, 0xFFFF, sum = 0
2026 10:05:28.870168 1, 0xFFFF, sum = 0
2027 10:05:28.870259 2, 0xFFFF, sum = 0
2028 10:05:28.873400 3, 0xFFFF, sum = 0
2029 10:05:28.873505 4, 0xFFFF, sum = 0
2030 10:05:28.876687 5, 0xFFFF, sum = 0
2031 10:05:28.876807 6, 0xFFFF, sum = 0
2032 10:05:28.879888 7, 0xFFFF, sum = 0
2033 10:05:28.879980 8, 0xFFFF, sum = 0
2034 10:05:28.883245 9, 0x0, sum = 1
2035 10:05:28.883397 10, 0x0, sum = 2
2036 10:05:28.886496 11, 0x0, sum = 3
2037 10:05:28.886653 12, 0x0, sum = 4
2038 10:05:28.890220 best_step = 10
2039 10:05:28.890317
2040 10:05:28.890411 ==
2041 10:05:28.893459 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 10:05:28.896769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 10:05:28.896878 ==
2044 10:05:28.900079 RX Vref Scan: 0
2045 10:05:28.900183
2046 10:05:28.900273 RX Vref 0 -> 0, step: 1
2047 10:05:28.900368
2048 10:05:28.903224 RX Delay -79 -> 252, step: 8
2049 10:05:28.906968 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2050 10:05:28.913717 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2051 10:05:28.916584 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2052 10:05:28.920322 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2053 10:05:28.923755 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2054 10:05:28.926755 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2055 10:05:28.930617 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2056 10:05:28.936801 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2057 10:05:28.940255 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2058 10:05:28.943356 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2059 10:05:28.946942 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2060 10:05:28.949918 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2061 10:05:28.957036 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2062 10:05:28.960338 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2063 10:05:28.963534 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2064 10:05:28.966789 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2065 10:05:28.966872 ==
2066 10:05:28.969874 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 10:05:28.977044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 10:05:28.977144 ==
2069 10:05:28.977240 DQS Delay:
2070 10:05:28.977315 DQS0 = 0, DQS1 = 0
2071 10:05:28.980204 DQM Delay:
2072 10:05:28.980397 DQM0 = 97, DQM1 = 91
2073 10:05:28.983373 DQ Delay:
2074 10:05:28.986675 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2075 10:05:28.989922 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2076 10:05:28.993038 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2077 10:05:28.996312 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2078 10:05:28.996419
2079 10:05:28.996520
2080 10:05:29.003528 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2081 10:05:29.006707 CH1 RK1: MR19=606, MR18=450F
2082 10:05:29.013219 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2083 10:05:29.016939 [RxdqsGatingPostProcess] freq 800
2084 10:05:29.020149 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2085 10:05:29.023407 Pre-setting of DQS Precalculation
2086 10:05:29.030065 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2087 10:05:29.036894 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2088 10:05:29.043444 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2089 10:05:29.043621
2090 10:05:29.043797
2091 10:05:29.046515 [Calibration Summary] 1600 Mbps
2092 10:05:29.046612 CH 0, Rank 0
2093 10:05:29.050238 SW Impedance : PASS
2094 10:05:29.053394 DUTY Scan : NO K
2095 10:05:29.053513 ZQ Calibration : PASS
2096 10:05:29.056885 Jitter Meter : NO K
2097 10:05:29.060233 CBT Training : PASS
2098 10:05:29.060326 Write leveling : PASS
2099 10:05:29.063638 RX DQS gating : PASS
2100 10:05:29.063736 RX DQ/DQS(RDDQC) : PASS
2101 10:05:29.067270 TX DQ/DQS : PASS
2102 10:05:29.070315 RX DATLAT : PASS
2103 10:05:29.070413 RX DQ/DQS(Engine): PASS
2104 10:05:29.073372 TX OE : NO K
2105 10:05:29.073471 All Pass.
2106 10:05:29.073537
2107 10:05:29.076951 CH 0, Rank 1
2108 10:05:29.077047 SW Impedance : PASS
2109 10:05:29.080339 DUTY Scan : NO K
2110 10:05:29.084026 ZQ Calibration : PASS
2111 10:05:29.084126 Jitter Meter : NO K
2112 10:05:29.087135 CBT Training : PASS
2113 10:05:29.090438 Write leveling : PASS
2114 10:05:29.090537 RX DQS gating : PASS
2115 10:05:29.093742 RX DQ/DQS(RDDQC) : PASS
2116 10:05:29.096817 TX DQ/DQS : PASS
2117 10:05:29.096915 RX DATLAT : PASS
2118 10:05:29.100595 RX DQ/DQS(Engine): PASS
2119 10:05:29.100693 TX OE : NO K
2120 10:05:29.103730 All Pass.
2121 10:05:29.103827
2122 10:05:29.103922 CH 1, Rank 0
2123 10:05:29.107174 SW Impedance : PASS
2124 10:05:29.107272 DUTY Scan : NO K
2125 10:05:29.110320 ZQ Calibration : PASS
2126 10:05:29.113556 Jitter Meter : NO K
2127 10:05:29.113674 CBT Training : PASS
2128 10:05:29.117427 Write leveling : PASS
2129 10:05:29.120491 RX DQS gating : PASS
2130 10:05:29.120573 RX DQ/DQS(RDDQC) : PASS
2131 10:05:29.124171 TX DQ/DQS : PASS
2132 10:05:29.127504 RX DATLAT : PASS
2133 10:05:29.127585 RX DQ/DQS(Engine): PASS
2134 10:05:29.130773 TX OE : NO K
2135 10:05:29.130856 All Pass.
2136 10:05:29.130920
2137 10:05:29.134031 CH 1, Rank 1
2138 10:05:29.134129 SW Impedance : PASS
2139 10:05:29.137387 DUTY Scan : NO K
2140 10:05:29.140602 ZQ Calibration : PASS
2141 10:05:29.140684 Jitter Meter : NO K
2142 10:05:29.144298 CBT Training : PASS
2143 10:05:29.144380 Write leveling : PASS
2144 10:05:29.147254 RX DQS gating : PASS
2145 10:05:29.150507 RX DQ/DQS(RDDQC) : PASS
2146 10:05:29.150589 TX DQ/DQS : PASS
2147 10:05:29.154199 RX DATLAT : PASS
2148 10:05:29.157491 RX DQ/DQS(Engine): PASS
2149 10:05:29.157601 TX OE : NO K
2150 10:05:29.160696 All Pass.
2151 10:05:29.160792
2152 10:05:29.160880 DramC Write-DBI off
2153 10:05:29.163883 PER_BANK_REFRESH: Hybrid Mode
2154 10:05:29.163977 TX_TRACKING: ON
2155 10:05:29.167255 [GetDramInforAfterCalByMRR] Vendor 6.
2156 10:05:29.173713 [GetDramInforAfterCalByMRR] Revision 606.
2157 10:05:29.177540 [GetDramInforAfterCalByMRR] Revision 2 0.
2158 10:05:29.177661 MR0 0x3b3b
2159 10:05:29.177757 MR8 0x5151
2160 10:05:29.180624 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 10:05:29.180721
2162 10:05:29.183848 MR0 0x3b3b
2163 10:05:29.183930 MR8 0x5151
2164 10:05:29.186939 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 10:05:29.187036
2166 10:05:29.197278 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2167 10:05:29.200427 [FAST_K] Save calibration result to emmc
2168 10:05:29.203924 [FAST_K] Save calibration result to emmc
2169 10:05:29.207525 dram_init: config_dvfs: 1
2170 10:05:29.210479 dramc_set_vcore_voltage set vcore to 662500
2171 10:05:29.214017 Read voltage for 1200, 2
2172 10:05:29.214099 Vio18 = 0
2173 10:05:29.214163 Vcore = 662500
2174 10:05:29.217237 Vdram = 0
2175 10:05:29.217318 Vddq = 0
2176 10:05:29.217382 Vmddr = 0
2177 10:05:29.224169 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2178 10:05:29.227363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2179 10:05:29.231022 MEM_TYPE=3, freq_sel=15
2180 10:05:29.234291 sv_algorithm_assistance_LP4_1600
2181 10:05:29.237514 ============ PULL DRAM RESETB DOWN ============
2182 10:05:29.240830 ========== PULL DRAM RESETB DOWN end =========
2183 10:05:29.247291 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 10:05:29.251103 ===================================
2185 10:05:29.251186 LPDDR4 DRAM CONFIGURATION
2186 10:05:29.254242 ===================================
2187 10:05:29.257319 EX_ROW_EN[0] = 0x0
2188 10:05:29.260435 EX_ROW_EN[1] = 0x0
2189 10:05:29.260544 LP4Y_EN = 0x0
2190 10:05:29.264378 WORK_FSP = 0x0
2191 10:05:29.264492 WL = 0x4
2192 10:05:29.267510 RL = 0x4
2193 10:05:29.267622 BL = 0x2
2194 10:05:29.270889 RPST = 0x0
2195 10:05:29.270990 RD_PRE = 0x0
2196 10:05:29.274284 WR_PRE = 0x1
2197 10:05:29.274358 WR_PST = 0x0
2198 10:05:29.277524 DBI_WR = 0x0
2199 10:05:29.277629 DBI_RD = 0x0
2200 10:05:29.280781 OTF = 0x1
2201 10:05:29.283823 ===================================
2202 10:05:29.287042 ===================================
2203 10:05:29.287141 ANA top config
2204 10:05:29.290917 ===================================
2205 10:05:29.294235 DLL_ASYNC_EN = 0
2206 10:05:29.297451 ALL_SLAVE_EN = 0
2207 10:05:29.297547 NEW_RANK_MODE = 1
2208 10:05:29.300709 DLL_IDLE_MODE = 1
2209 10:05:29.304008 LP45_APHY_COMB_EN = 1
2210 10:05:29.307189 TX_ODT_DIS = 1
2211 10:05:29.310307 NEW_8X_MODE = 1
2212 10:05:29.313833 ===================================
2213 10:05:29.317346 ===================================
2214 10:05:29.317428 data_rate = 2400
2215 10:05:29.320648 CKR = 1
2216 10:05:29.323638 DQ_P2S_RATIO = 8
2217 10:05:29.327153 ===================================
2218 10:05:29.330537 CA_P2S_RATIO = 8
2219 10:05:29.334158 DQ_CA_OPEN = 0
2220 10:05:29.337204 DQ_SEMI_OPEN = 0
2221 10:05:29.337306 CA_SEMI_OPEN = 0
2222 10:05:29.340311 CA_FULL_RATE = 0
2223 10:05:29.343810 DQ_CKDIV4_EN = 0
2224 10:05:29.347010 CA_CKDIV4_EN = 0
2225 10:05:29.350172 CA_PREDIV_EN = 0
2226 10:05:29.354047 PH8_DLY = 17
2227 10:05:29.354132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2228 10:05:29.357300 DQ_AAMCK_DIV = 4
2229 10:05:29.360376 CA_AAMCK_DIV = 4
2230 10:05:29.363692 CA_ADMCK_DIV = 4
2231 10:05:29.367280 DQ_TRACK_CA_EN = 0
2232 10:05:29.370489 CA_PICK = 1200
2233 10:05:29.370564 CA_MCKIO = 1200
2234 10:05:29.373893 MCKIO_SEMI = 0
2235 10:05:29.377460 PLL_FREQ = 2366
2236 10:05:29.380679 DQ_UI_PI_RATIO = 32
2237 10:05:29.383996 CA_UI_PI_RATIO = 0
2238 10:05:29.387158 ===================================
2239 10:05:29.390476 ===================================
2240 10:05:29.393764 memory_type:LPDDR4
2241 10:05:29.393839 GP_NUM : 10
2242 10:05:29.396916 SRAM_EN : 1
2243 10:05:29.397007 MD32_EN : 0
2244 10:05:29.400175 ===================================
2245 10:05:29.404023 [ANA_INIT] >>>>>>>>>>>>>>
2246 10:05:29.407261 <<<<<< [CONFIGURE PHASE]: ANA_TX
2247 10:05:29.410551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2248 10:05:29.413757 ===================================
2249 10:05:29.417373 data_rate = 2400,PCW = 0X5b00
2250 10:05:29.420633 ===================================
2251 10:05:29.423719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2252 10:05:29.427491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 10:05:29.433839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 10:05:29.437207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2255 10:05:29.444054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2256 10:05:29.447232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2257 10:05:29.447307 [ANA_INIT] flow start
2258 10:05:29.450439 [ANA_INIT] PLL >>>>>>>>
2259 10:05:29.454167 [ANA_INIT] PLL <<<<<<<<
2260 10:05:29.454248 [ANA_INIT] MIDPI >>>>>>>>
2261 10:05:29.457099 [ANA_INIT] MIDPI <<<<<<<<
2262 10:05:29.460437 [ANA_INIT] DLL >>>>>>>>
2263 10:05:29.460539 [ANA_INIT] DLL <<<<<<<<
2264 10:05:29.463841 [ANA_INIT] flow end
2265 10:05:29.467099 ============ LP4 DIFF to SE enter ============
2266 10:05:29.470347 ============ LP4 DIFF to SE exit ============
2267 10:05:29.473541 [ANA_INIT] <<<<<<<<<<<<<
2268 10:05:29.477331 [Flow] Enable top DCM control >>>>>
2269 10:05:29.480397 [Flow] Enable top DCM control <<<<<
2270 10:05:29.483985 Enable DLL master slave shuffle
2271 10:05:29.490552 ==============================================================
2272 10:05:29.490669 Gating Mode config
2273 10:05:29.497148 ==============================================================
2274 10:05:29.497231 Config description:
2275 10:05:29.507243 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2276 10:05:29.513769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2277 10:05:29.520725 SELPH_MODE 0: By rank 1: By Phase
2278 10:05:29.523984 ==============================================================
2279 10:05:29.527648 GAT_TRACK_EN = 1
2280 10:05:29.531060 RX_GATING_MODE = 2
2281 10:05:29.534260 RX_GATING_TRACK_MODE = 2
2282 10:05:29.537337 SELPH_MODE = 1
2283 10:05:29.540702 PICG_EARLY_EN = 1
2284 10:05:29.544412 VALID_LAT_VALUE = 1
2285 10:05:29.547688 ==============================================================
2286 10:05:29.550834 Enter into Gating configuration >>>>
2287 10:05:29.554094 Exit from Gating configuration <<<<
2288 10:05:29.557381 Enter into DVFS_PRE_config >>>>>
2289 10:05:29.571097 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2290 10:05:29.571208 Exit from DVFS_PRE_config <<<<<
2291 10:05:29.574212 Enter into PICG configuration >>>>
2292 10:05:29.577286 Exit from PICG configuration <<<<
2293 10:05:29.580684 [RX_INPUT] configuration >>>>>
2294 10:05:29.584290 [RX_INPUT] configuration <<<<<
2295 10:05:29.590583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2296 10:05:29.593871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2297 10:05:29.600941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 10:05:29.607313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 10:05:29.614004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 10:05:29.621003 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 10:05:29.624140 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2302 10:05:29.627325 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2303 10:05:29.630678 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2304 10:05:29.637692 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2305 10:05:29.640952 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2306 10:05:29.644294 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2307 10:05:29.647436 ===================================
2308 10:05:29.651255 LPDDR4 DRAM CONFIGURATION
2309 10:05:29.654532 ===================================
2310 10:05:29.654649 EX_ROW_EN[0] = 0x0
2311 10:05:29.657790 EX_ROW_EN[1] = 0x0
2312 10:05:29.657873 LP4Y_EN = 0x0
2313 10:05:29.661065 WORK_FSP = 0x0
2314 10:05:29.664140 WL = 0x4
2315 10:05:29.664244 RL = 0x4
2316 10:05:29.667614 BL = 0x2
2317 10:05:29.667696 RPST = 0x0
2318 10:05:29.670815 RD_PRE = 0x0
2319 10:05:29.670896 WR_PRE = 0x1
2320 10:05:29.674024 WR_PST = 0x0
2321 10:05:29.674127 DBI_WR = 0x0
2322 10:05:29.678011 DBI_RD = 0x0
2323 10:05:29.678093 OTF = 0x1
2324 10:05:29.681253 ===================================
2325 10:05:29.684411 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2326 10:05:29.690743 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2327 10:05:29.694116 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 10:05:29.697744 ===================================
2329 10:05:29.701343 LPDDR4 DRAM CONFIGURATION
2330 10:05:29.704484 ===================================
2331 10:05:29.704585 EX_ROW_EN[0] = 0x10
2332 10:05:29.708024 EX_ROW_EN[1] = 0x0
2333 10:05:29.708152 LP4Y_EN = 0x0
2334 10:05:29.711055 WORK_FSP = 0x0
2335 10:05:29.711184 WL = 0x4
2336 10:05:29.714888 RL = 0x4
2337 10:05:29.714988 BL = 0x2
2338 10:05:29.717980 RPST = 0x0
2339 10:05:29.718065 RD_PRE = 0x0
2340 10:05:29.721110 WR_PRE = 0x1
2341 10:05:29.721232 WR_PST = 0x0
2342 10:05:29.724579 DBI_WR = 0x0
2343 10:05:29.724678 DBI_RD = 0x0
2344 10:05:29.728177 OTF = 0x1
2345 10:05:29.731232 ===================================
2346 10:05:29.737935 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2347 10:05:29.738018 ==
2348 10:05:29.741304 Dram Type= 6, Freq= 0, CH_0, rank 0
2349 10:05:29.744688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2350 10:05:29.744770 ==
2351 10:05:29.747563 [Duty_Offset_Calibration]
2352 10:05:29.747664 B0:2 B1:1 CA:1
2353 10:05:29.747730
2354 10:05:29.751286 [DutyScan_Calibration_Flow] k_type=0
2355 10:05:29.761507
2356 10:05:29.761635 ==CLK 0==
2357 10:05:29.764786 Final CLK duty delay cell = 0
2358 10:05:29.768136 [0] MAX Duty = 5156%(X100), DQS PI = 22
2359 10:05:29.771410 [0] MIN Duty = 4844%(X100), DQS PI = 48
2360 10:05:29.771526 [0] AVG Duty = 5000%(X100)
2361 10:05:29.775165
2362 10:05:29.778567 CH0 CLK Duty spec in!! Max-Min= 312%
2363 10:05:29.781855 [DutyScan_Calibration_Flow] ====Done====
2364 10:05:29.781939
2365 10:05:29.785158 [DutyScan_Calibration_Flow] k_type=1
2366 10:05:29.800363
2367 10:05:29.800470 ==DQS 0 ==
2368 10:05:29.803632 Final DQS duty delay cell = -4
2369 10:05:29.807214 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2370 10:05:29.810487 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2371 10:05:29.813445 [-4] AVG Duty = 4953%(X100)
2372 10:05:29.813570
2373 10:05:29.813725 ==DQS 1 ==
2374 10:05:29.816872 Final DQS duty delay cell = 0
2375 10:05:29.820566 [0] MAX Duty = 5156%(X100), DQS PI = 60
2376 10:05:29.823377 [0] MIN Duty = 5000%(X100), DQS PI = 36
2377 10:05:29.826782 [0] AVG Duty = 5078%(X100)
2378 10:05:29.826876
2379 10:05:29.830600 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2380 10:05:29.830677
2381 10:05:29.833838 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2382 10:05:29.836842 [DutyScan_Calibration_Flow] ====Done====
2383 10:05:29.836915
2384 10:05:29.840454 [DutyScan_Calibration_Flow] k_type=3
2385 10:05:29.857437
2386 10:05:29.857583 ==DQM 0 ==
2387 10:05:29.860604 Final DQM duty delay cell = 0
2388 10:05:29.864009 [0] MAX Duty = 5156%(X100), DQS PI = 28
2389 10:05:29.867237 [0] MIN Duty = 4875%(X100), DQS PI = 58
2390 10:05:29.867325 [0] AVG Duty = 5015%(X100)
2391 10:05:29.870799
2392 10:05:29.870899 ==DQM 1 ==
2393 10:05:29.874017 Final DQM duty delay cell = 0
2394 10:05:29.877296 [0] MAX Duty = 5093%(X100), DQS PI = 0
2395 10:05:29.880525 [0] MIN Duty = 5031%(X100), DQS PI = 18
2396 10:05:29.880617 [0] AVG Duty = 5062%(X100)
2397 10:05:29.883717
2398 10:05:29.887043 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2399 10:05:29.887117
2400 10:05:29.890267 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2401 10:05:29.894031 [DutyScan_Calibration_Flow] ====Done====
2402 10:05:29.894116
2403 10:05:29.897247 [DutyScan_Calibration_Flow] k_type=2
2404 10:05:29.913280
2405 10:05:29.913376 ==DQ 0 ==
2406 10:05:29.917075 Final DQ duty delay cell = 0
2407 10:05:29.920318 [0] MAX Duty = 5062%(X100), DQS PI = 32
2408 10:05:29.923325 [0] MIN Duty = 4906%(X100), DQS PI = 0
2409 10:05:29.923409 [0] AVG Duty = 4984%(X100)
2410 10:05:29.923473
2411 10:05:29.926788 ==DQ 1 ==
2412 10:05:29.930207 Final DQ duty delay cell = 0
2413 10:05:29.933814 [0] MAX Duty = 5093%(X100), DQS PI = 24
2414 10:05:29.937137 [0] MIN Duty = 4969%(X100), DQS PI = 14
2415 10:05:29.937212 [0] AVG Duty = 5031%(X100)
2416 10:05:29.937275
2417 10:05:29.940365 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2418 10:05:29.940463
2419 10:05:29.947058 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2420 10:05:29.950141 [DutyScan_Calibration_Flow] ====Done====
2421 10:05:29.950229 ==
2422 10:05:29.953766 Dram Type= 6, Freq= 0, CH_1, rank 0
2423 10:05:29.956950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2424 10:05:29.957036 ==
2425 10:05:29.960179 [Duty_Offset_Calibration]
2426 10:05:29.960253 B0:1 B1:0 CA:0
2427 10:05:29.960316
2428 10:05:29.963367 [DutyScan_Calibration_Flow] k_type=0
2429 10:05:29.972635
2430 10:05:29.972712 ==CLK 0==
2431 10:05:29.976350 Final CLK duty delay cell = -4
2432 10:05:29.979607 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2433 10:05:29.982844 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2434 10:05:29.985944 [-4] AVG Duty = 4937%(X100)
2435 10:05:29.986023
2436 10:05:29.989315 CH1 CLK Duty spec in!! Max-Min= 125%
2437 10:05:29.992676 [DutyScan_Calibration_Flow] ====Done====
2438 10:05:29.992750
2439 10:05:29.995891 [DutyScan_Calibration_Flow] k_type=1
2440 10:05:30.012504
2441 10:05:30.012590 ==DQS 0 ==
2442 10:05:30.015712 Final DQS duty delay cell = 0
2443 10:05:30.019484 [0] MAX Duty = 5094%(X100), DQS PI = 26
2444 10:05:30.022823 [0] MIN Duty = 4875%(X100), DQS PI = 0
2445 10:05:30.022905 [0] AVG Duty = 4984%(X100)
2446 10:05:30.026016
2447 10:05:30.026094 ==DQS 1 ==
2448 10:05:30.029316 Final DQS duty delay cell = 0
2449 10:05:30.032311 [0] MAX Duty = 5187%(X100), DQS PI = 20
2450 10:05:30.035984 [0] MIN Duty = 4938%(X100), DQS PI = 12
2451 10:05:30.036063 [0] AVG Duty = 5062%(X100)
2452 10:05:30.039339
2453 10:05:30.042457 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2454 10:05:30.042543
2455 10:05:30.046268 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2456 10:05:30.049423 [DutyScan_Calibration_Flow] ====Done====
2457 10:05:30.049524
2458 10:05:30.052537 [DutyScan_Calibration_Flow] k_type=3
2459 10:05:30.068924
2460 10:05:30.069059 ==DQM 0 ==
2461 10:05:30.072563 Final DQM duty delay cell = 0
2462 10:05:30.075860 [0] MAX Duty = 5156%(X100), DQS PI = 6
2463 10:05:30.079603 [0] MIN Duty = 5031%(X100), DQS PI = 0
2464 10:05:30.079703 [0] AVG Duty = 5093%(X100)
2465 10:05:30.079800
2466 10:05:30.082446 ==DQM 1 ==
2467 10:05:30.086159 Final DQM duty delay cell = 0
2468 10:05:30.089109 [0] MAX Duty = 5031%(X100), DQS PI = 14
2469 10:05:30.092653 [0] MIN Duty = 4907%(X100), DQS PI = 34
2470 10:05:30.092760 [0] AVG Duty = 4969%(X100)
2471 10:05:30.092856
2472 10:05:30.096168 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2473 10:05:30.099159
2474 10:05:30.102828 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2475 10:05:30.105978 [DutyScan_Calibration_Flow] ====Done====
2476 10:05:30.106082
2477 10:05:30.109175 [DutyScan_Calibration_Flow] k_type=2
2478 10:05:30.124555
2479 10:05:30.124665 ==DQ 0 ==
2480 10:05:30.128299 Final DQ duty delay cell = -4
2481 10:05:30.131523 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2482 10:05:30.134761 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2483 10:05:30.137986 [-4] AVG Duty = 4984%(X100)
2484 10:05:30.138075
2485 10:05:30.138164 ==DQ 1 ==
2486 10:05:30.141689 Final DQ duty delay cell = 0
2487 10:05:30.144811 [0] MAX Duty = 5093%(X100), DQS PI = 20
2488 10:05:30.148374 [0] MIN Duty = 4938%(X100), DQS PI = 34
2489 10:05:30.148473 [0] AVG Duty = 5015%(X100)
2490 10:05:30.151325
2491 10:05:30.154777 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2492 10:05:30.154890
2493 10:05:30.158440 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2494 10:05:30.161299 [DutyScan_Calibration_Flow] ====Done====
2495 10:05:30.165010 nWR fixed to 30
2496 10:05:30.165091 [ModeRegInit_LP4] CH0 RK0
2497 10:05:30.168356 [ModeRegInit_LP4] CH0 RK1
2498 10:05:30.171512 [ModeRegInit_LP4] CH1 RK0
2499 10:05:30.171614 [ModeRegInit_LP4] CH1 RK1
2500 10:05:30.175065 match AC timing 7
2501 10:05:30.178135 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2502 10:05:30.184836 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2503 10:05:30.187903 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2504 10:05:30.191176 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2505 10:05:30.198134 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2506 10:05:30.198225 ==
2507 10:05:30.201915 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 10:05:30.204801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 10:05:30.204898 ==
2510 10:05:30.211358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 10:05:30.214996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2512 10:05:30.224901 [CA 0] Center 39 (8~70) winsize 63
2513 10:05:30.228694 [CA 1] Center 39 (8~70) winsize 63
2514 10:05:30.231751 [CA 2] Center 35 (4~66) winsize 63
2515 10:05:30.234963 [CA 3] Center 34 (4~65) winsize 62
2516 10:05:30.238297 [CA 4] Center 33 (3~64) winsize 62
2517 10:05:30.241524 [CA 5] Center 32 (3~62) winsize 60
2518 10:05:30.241621
2519 10:05:30.245207 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2520 10:05:30.245310
2521 10:05:30.248509 [CATrainingPosCal] consider 1 rank data
2522 10:05:30.251651 u2DelayCellTimex100 = 270/100 ps
2523 10:05:30.255349 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2524 10:05:30.258395 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2525 10:05:30.265352 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2526 10:05:30.268448 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2527 10:05:30.272140 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2528 10:05:30.275151 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2529 10:05:30.275254
2530 10:05:30.278471 CA PerBit enable=1, Macro0, CA PI delay=32
2531 10:05:30.278573
2532 10:05:30.281822 [CBTSetCACLKResult] CA Dly = 32
2533 10:05:30.281908 CS Dly: 6 (0~37)
2534 10:05:30.281975 ==
2535 10:05:30.285289 Dram Type= 6, Freq= 0, CH_0, rank 1
2536 10:05:30.291755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 10:05:30.291845 ==
2538 10:05:30.295169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 10:05:30.301983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2540 10:05:30.310660 [CA 0] Center 38 (8~69) winsize 62
2541 10:05:30.313825 [CA 1] Center 38 (8~69) winsize 62
2542 10:05:30.317537 [CA 2] Center 35 (4~66) winsize 63
2543 10:05:30.321138 [CA 3] Center 34 (4~65) winsize 62
2544 10:05:30.324351 [CA 4] Center 33 (3~64) winsize 62
2545 10:05:30.327616 [CA 5] Center 32 (2~62) winsize 61
2546 10:05:30.327701
2547 10:05:30.330874 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2548 10:05:30.330958
2549 10:05:30.334024 [CATrainingPosCal] consider 2 rank data
2550 10:05:30.337849 u2DelayCellTimex100 = 270/100 ps
2551 10:05:30.341049 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2552 10:05:30.344417 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2553 10:05:30.350915 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2554 10:05:30.354178 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2555 10:05:30.357949 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2556 10:05:30.361194 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2557 10:05:30.361277
2558 10:05:30.364418 CA PerBit enable=1, Macro0, CA PI delay=32
2559 10:05:30.364502
2560 10:05:30.367667 [CBTSetCACLKResult] CA Dly = 32
2561 10:05:30.367750 CS Dly: 6 (0~38)
2562 10:05:30.367816
2563 10:05:30.370875 ----->DramcWriteLeveling(PI) begin...
2564 10:05:30.370960 ==
2565 10:05:30.374747 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 10:05:30.381125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 10:05:30.381209 ==
2568 10:05:30.384309 Write leveling (Byte 0): 34 => 34
2569 10:05:30.388136 Write leveling (Byte 1): 30 => 30
2570 10:05:30.388220 DramcWriteLeveling(PI) end<-----
2571 10:05:30.388285
2572 10:05:30.391258 ==
2573 10:05:30.394433 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 10:05:30.397549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 10:05:30.397661 ==
2576 10:05:30.401372 [Gating] SW mode calibration
2577 10:05:30.407914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2578 10:05:30.411474 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2579 10:05:30.417779 0 15 0 | B1->B0 | 2424 3232 | 0 1 | (0 0) (1 1)
2580 10:05:30.421343 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2581 10:05:30.424502 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 10:05:30.431185 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 10:05:30.434400 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 10:05:30.437614 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 10:05:30.444455 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2586 10:05:30.447691 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2587 10:05:30.450987 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2588 10:05:30.457455 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2589 10:05:30.461263 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 10:05:30.464284 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 10:05:30.468102 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 10:05:30.474445 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 10:05:30.477741 1 0 24 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2594 10:05:30.481062 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2595 10:05:30.488087 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2596 10:05:30.491679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 10:05:30.494878 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 10:05:30.501204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 10:05:30.504569 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 10:05:30.508458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 10:05:30.514695 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 10:05:30.518308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2603 10:05:30.521343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2604 10:05:30.527962 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 10:05:30.531596 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 10:05:30.534817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 10:05:30.538312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 10:05:30.545107 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 10:05:30.548145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:05:30.552001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:05:30.558415 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:05:30.561799 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:05:30.564966 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:05:30.571940 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:05:30.575146 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:05:30.578289 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:05:30.585361 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:05:30.588380 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2619 10:05:30.592258 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 10:05:30.595423 Total UI for P1: 0, mck2ui 16
2621 10:05:30.598388 best dqsien dly found for B0: ( 1, 3, 28)
2622 10:05:30.602048 Total UI for P1: 0, mck2ui 16
2623 10:05:30.605342 best dqsien dly found for B1: ( 1, 3, 30)
2624 10:05:30.608547 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2625 10:05:30.611765 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2626 10:05:30.611848
2627 10:05:30.615105 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2628 10:05:30.618462 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2629 10:05:30.622213 [Gating] SW calibration Done
2630 10:05:30.622297 ==
2631 10:05:30.625304 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 10:05:30.632282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 10:05:30.632372 ==
2634 10:05:30.632479 RX Vref Scan: 0
2635 10:05:30.632587
2636 10:05:30.635498 RX Vref 0 -> 0, step: 1
2637 10:05:30.635582
2638 10:05:30.638707 RX Delay -40 -> 252, step: 8
2639 10:05:30.641990 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2640 10:05:30.645242 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2641 10:05:30.648570 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2642 10:05:30.652005 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2643 10:05:30.658641 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2644 10:05:30.662313 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2645 10:05:30.665688 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2646 10:05:30.668787 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2647 10:05:30.671939 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2648 10:05:30.678527 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2649 10:05:30.682318 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2650 10:05:30.685367 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2651 10:05:30.688412 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2652 10:05:30.692256 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2653 10:05:30.698581 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2654 10:05:30.702395 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2655 10:05:30.702479 ==
2656 10:05:30.705445 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 10:05:30.708392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 10:05:30.708467 ==
2659 10:05:30.711999 DQS Delay:
2660 10:05:30.712080 DQS0 = 0, DQS1 = 0
2661 10:05:30.712146 DQM Delay:
2662 10:05:30.715203 DQM0 = 121, DQM1 = 113
2663 10:05:30.715274 DQ Delay:
2664 10:05:30.718374 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2665 10:05:30.721694 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2666 10:05:30.725413 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2667 10:05:30.732091 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2668 10:05:30.732170
2669 10:05:30.732235
2670 10:05:30.732295 ==
2671 10:05:30.735200 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 10:05:30.738404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 10:05:30.738475 ==
2674 10:05:30.738536
2675 10:05:30.738600
2676 10:05:30.742290 TX Vref Scan disable
2677 10:05:30.742387 == TX Byte 0 ==
2678 10:05:30.748689 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2679 10:05:30.751912 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2680 10:05:30.752017 == TX Byte 1 ==
2681 10:05:30.758407 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2682 10:05:30.761862 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2683 10:05:30.762000 ==
2684 10:05:30.765488 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 10:05:30.768416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 10:05:30.768491 ==
2687 10:05:30.781241 TX Vref=22, minBit 0, minWin=25, winSum=407
2688 10:05:30.784605 TX Vref=24, minBit 0, minWin=25, winSum=410
2689 10:05:30.787821 TX Vref=26, minBit 2, minWin=25, winSum=416
2690 10:05:30.791643 TX Vref=28, minBit 12, minWin=25, winSum=420
2691 10:05:30.794609 TX Vref=30, minBit 12, minWin=25, winSum=420
2692 10:05:30.801442 TX Vref=32, minBit 0, minWin=26, winSum=421
2693 10:05:30.804704 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 32
2694 10:05:30.804789
2695 10:05:30.807998 Final TX Range 1 Vref 32
2696 10:05:30.808083
2697 10:05:30.808149 ==
2698 10:05:30.811281 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 10:05:30.814890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 10:05:30.814975 ==
2701 10:05:30.815041
2702 10:05:30.818354
2703 10:05:30.818457 TX Vref Scan disable
2704 10:05:30.821331 == TX Byte 0 ==
2705 10:05:30.824773 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2706 10:05:30.827796 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2707 10:05:30.831774 == TX Byte 1 ==
2708 10:05:30.834875 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2709 10:05:30.838540 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2710 10:05:30.838624
2711 10:05:30.841557 [DATLAT]
2712 10:05:30.841690 Freq=1200, CH0 RK0
2713 10:05:30.841757
2714 10:05:30.844680 DATLAT Default: 0xd
2715 10:05:30.844763 0, 0xFFFF, sum = 0
2716 10:05:30.848473 1, 0xFFFF, sum = 0
2717 10:05:30.848559 2, 0xFFFF, sum = 0
2718 10:05:30.851716 3, 0xFFFF, sum = 0
2719 10:05:30.851801 4, 0xFFFF, sum = 0
2720 10:05:30.854923 5, 0xFFFF, sum = 0
2721 10:05:30.855007 6, 0xFFFF, sum = 0
2722 10:05:30.858124 7, 0xFFFF, sum = 0
2723 10:05:30.858247 8, 0xFFFF, sum = 0
2724 10:05:30.861375 9, 0xFFFF, sum = 0
2725 10:05:30.864994 10, 0xFFFF, sum = 0
2726 10:05:30.865079 11, 0xFFFF, sum = 0
2727 10:05:30.867945 12, 0x0, sum = 1
2728 10:05:30.868029 13, 0x0, sum = 2
2729 10:05:30.868107 14, 0x0, sum = 3
2730 10:05:30.871568 15, 0x0, sum = 4
2731 10:05:30.871653 best_step = 13
2732 10:05:30.871718
2733 10:05:30.874720 ==
2734 10:05:30.874807 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 10:05:30.881516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 10:05:30.881660 ==
2737 10:05:30.881728 RX Vref Scan: 1
2738 10:05:30.881789
2739 10:05:30.884917 Set Vref Range= 32 -> 127
2740 10:05:30.885000
2741 10:05:30.888284 RX Vref 32 -> 127, step: 1
2742 10:05:30.888377
2743 10:05:30.891070 RX Delay -13 -> 252, step: 4
2744 10:05:30.891156
2745 10:05:30.894462 Set Vref, RX VrefLevel [Byte0]: 32
2746 10:05:30.897692 [Byte1]: 32
2747 10:05:30.897776
2748 10:05:30.901350 Set Vref, RX VrefLevel [Byte0]: 33
2749 10:05:30.904868 [Byte1]: 33
2750 10:05:30.904951
2751 10:05:30.907918 Set Vref, RX VrefLevel [Byte0]: 34
2752 10:05:30.911268 [Byte1]: 34
2753 10:05:30.915226
2754 10:05:30.915309 Set Vref, RX VrefLevel [Byte0]: 35
2755 10:05:30.919071 [Byte1]: 35
2756 10:05:30.923307
2757 10:05:30.923390 Set Vref, RX VrefLevel [Byte0]: 36
2758 10:05:30.926557 [Byte1]: 36
2759 10:05:30.931468
2760 10:05:30.931558 Set Vref, RX VrefLevel [Byte0]: 37
2761 10:05:30.934454 [Byte1]: 37
2762 10:05:30.939250
2763 10:05:30.939350 Set Vref, RX VrefLevel [Byte0]: 38
2764 10:05:30.942469 [Byte1]: 38
2765 10:05:30.946821
2766 10:05:30.946905 Set Vref, RX VrefLevel [Byte0]: 39
2767 10:05:30.950635 [Byte1]: 39
2768 10:05:30.955225
2769 10:05:30.955309 Set Vref, RX VrefLevel [Byte0]: 40
2770 10:05:30.958458 [Byte1]: 40
2771 10:05:30.962779
2772 10:05:30.962863 Set Vref, RX VrefLevel [Byte0]: 41
2773 10:05:30.966021 [Byte1]: 41
2774 10:05:30.970685
2775 10:05:30.970768 Set Vref, RX VrefLevel [Byte0]: 42
2776 10:05:30.974322 [Byte1]: 42
2777 10:05:30.978377
2778 10:05:30.978460 Set Vref, RX VrefLevel [Byte0]: 43
2779 10:05:30.981926 [Byte1]: 43
2780 10:05:30.986588
2781 10:05:30.986671 Set Vref, RX VrefLevel [Byte0]: 44
2782 10:05:30.989860 [Byte1]: 44
2783 10:05:30.994235
2784 10:05:30.994319 Set Vref, RX VrefLevel [Byte0]: 45
2785 10:05:30.997789 [Byte1]: 45
2786 10:05:31.002488
2787 10:05:31.002571 Set Vref, RX VrefLevel [Byte0]: 46
2788 10:05:31.005572 [Byte1]: 46
2789 10:05:31.010259
2790 10:05:31.010356 Set Vref, RX VrefLevel [Byte0]: 47
2791 10:05:31.013713 [Byte1]: 47
2792 10:05:31.017969
2793 10:05:31.018075 Set Vref, RX VrefLevel [Byte0]: 48
2794 10:05:31.021200 [Byte1]: 48
2795 10:05:31.025643
2796 10:05:31.025726 Set Vref, RX VrefLevel [Byte0]: 49
2797 10:05:31.029493 [Byte1]: 49
2798 10:05:31.033994
2799 10:05:31.034078 Set Vref, RX VrefLevel [Byte0]: 50
2800 10:05:31.037016 [Byte1]: 50
2801 10:05:31.041564
2802 10:05:31.041739 Set Vref, RX VrefLevel [Byte0]: 51
2803 10:05:31.045228 [Byte1]: 51
2804 10:05:31.049788
2805 10:05:31.049944 Set Vref, RX VrefLevel [Byte0]: 52
2806 10:05:31.052809 [Byte1]: 52
2807 10:05:31.057815
2808 10:05:31.057901 Set Vref, RX VrefLevel [Byte0]: 53
2809 10:05:31.061025 [Byte1]: 53
2810 10:05:31.065555
2811 10:05:31.065664 Set Vref, RX VrefLevel [Byte0]: 54
2812 10:05:31.068867 [Byte1]: 54
2813 10:05:31.073345
2814 10:05:31.073454 Set Vref, RX VrefLevel [Byte0]: 55
2815 10:05:31.076571 [Byte1]: 55
2816 10:05:31.081086
2817 10:05:31.081184 Set Vref, RX VrefLevel [Byte0]: 56
2818 10:05:31.084758 [Byte1]: 56
2819 10:05:31.089338
2820 10:05:31.089422 Set Vref, RX VrefLevel [Byte0]: 57
2821 10:05:31.092269 [Byte1]: 57
2822 10:05:31.096864
2823 10:05:31.096942 Set Vref, RX VrefLevel [Byte0]: 58
2824 10:05:31.100133 [Byte1]: 58
2825 10:05:31.104749
2826 10:05:31.104835 Set Vref, RX VrefLevel [Byte0]: 59
2827 10:05:31.107973 [Byte1]: 59
2828 10:05:31.112766
2829 10:05:31.112850 Set Vref, RX VrefLevel [Byte0]: 60
2830 10:05:31.116014 [Byte1]: 60
2831 10:05:31.120594
2832 10:05:31.120677 Set Vref, RX VrefLevel [Byte0]: 61
2833 10:05:31.124188 [Byte1]: 61
2834 10:05:31.128686
2835 10:05:31.128769 Set Vref, RX VrefLevel [Byte0]: 62
2836 10:05:31.131911 [Byte1]: 62
2837 10:05:31.136621
2838 10:05:31.136706 Set Vref, RX VrefLevel [Byte0]: 63
2839 10:05:31.139893 [Byte1]: 63
2840 10:05:31.144410
2841 10:05:31.144493 Set Vref, RX VrefLevel [Byte0]: 64
2842 10:05:31.147566 [Byte1]: 64
2843 10:05:31.152170
2844 10:05:31.152253 Set Vref, RX VrefLevel [Byte0]: 65
2845 10:05:31.155243 [Byte1]: 65
2846 10:05:31.160023
2847 10:05:31.160144 Set Vref, RX VrefLevel [Byte0]: 66
2848 10:05:31.163481 [Byte1]: 66
2849 10:05:31.168150
2850 10:05:31.168235 Set Vref, RX VrefLevel [Byte0]: 67
2851 10:05:31.171481 [Byte1]: 67
2852 10:05:31.176038
2853 10:05:31.176122 Set Vref, RX VrefLevel [Byte0]: 68
2854 10:05:31.179441 [Byte1]: 68
2855 10:05:31.184021
2856 10:05:31.184105 Set Vref, RX VrefLevel [Byte0]: 69
2857 10:05:31.187230 [Byte1]: 69
2858 10:05:31.191736
2859 10:05:31.191819 Final RX Vref Byte 0 = 56 to rank0
2860 10:05:31.194980 Final RX Vref Byte 1 = 49 to rank0
2861 10:05:31.198380 Final RX Vref Byte 0 = 56 to rank1
2862 10:05:31.201829 Final RX Vref Byte 1 = 49 to rank1==
2863 10:05:31.205068 Dram Type= 6, Freq= 0, CH_0, rank 0
2864 10:05:31.208333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 10:05:31.211686 ==
2866 10:05:31.211770 DQS Delay:
2867 10:05:31.211837 DQS0 = 0, DQS1 = 0
2868 10:05:31.215403 DQM Delay:
2869 10:05:31.215486 DQM0 = 120, DQM1 = 111
2870 10:05:31.218612 DQ Delay:
2871 10:05:31.221868 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2872 10:05:31.225017 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2873 10:05:31.228841 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
2874 10:05:31.232034 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2875 10:05:31.232150
2876 10:05:31.232215
2877 10:05:31.238945 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2878 10:05:31.241837 CH0 RK0: MR19=404, MR18=1710
2879 10:05:31.248439 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2880 10:05:31.248570
2881 10:05:31.251692 ----->DramcWriteLeveling(PI) begin...
2882 10:05:31.251853 ==
2883 10:05:31.255355 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 10:05:31.258724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 10:05:31.258846 ==
2886 10:05:31.261832 Write leveling (Byte 0): 34 => 34
2887 10:05:31.265043 Write leveling (Byte 1): 28 => 28
2888 10:05:31.268691 DramcWriteLeveling(PI) end<-----
2889 10:05:31.268762
2890 10:05:31.268824 ==
2891 10:05:31.271726 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 10:05:31.278821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 10:05:31.278901 ==
2894 10:05:31.278972 [Gating] SW mode calibration
2895 10:05:31.288510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2896 10:05:31.291742 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2897 10:05:31.295646 0 15 0 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 0)
2898 10:05:31.301965 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 10:05:31.304943 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 10:05:31.308471 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 10:05:31.315328 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 10:05:31.318876 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 10:05:31.322196 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 10:05:31.328731 0 15 28 | B1->B0 | 2f2f 2b2b | 0 1 | (1 0) (1 0)
2905 10:05:31.331802 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 10:05:31.335051 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 10:05:31.342151 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 10:05:31.345332 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 10:05:31.348630 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 10:05:31.355526 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 10:05:31.358531 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2912 10:05:31.362040 1 0 28 | B1->B0 | 3838 3838 | 0 0 | (0 0) (0 0)
2913 10:05:31.365368 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 10:05:31.372251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 10:05:31.375421 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 10:05:31.378919 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 10:05:31.385703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 10:05:31.389035 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 10:05:31.392411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 10:05:31.398850 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2921 10:05:31.402184 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2922 10:05:31.405965 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 10:05:31.412420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 10:05:31.415948 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 10:05:31.419110 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 10:05:31.425497 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 10:05:31.429471 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:05:31.432784 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:05:31.436138 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:05:31.442497 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:05:31.445584 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:05:31.449468 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:05:31.455788 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 10:05:31.459655 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:05:31.462954 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:05:31.469304 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2937 10:05:31.472419 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2938 10:05:31.475686 Total UI for P1: 0, mck2ui 16
2939 10:05:31.479290 best dqsien dly found for B1: ( 1, 3, 28)
2940 10:05:31.482434 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 10:05:31.485899 Total UI for P1: 0, mck2ui 16
2942 10:05:31.488979 best dqsien dly found for B0: ( 1, 3, 30)
2943 10:05:31.492504 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2944 10:05:31.495864 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2945 10:05:31.495948
2946 10:05:31.499164 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2947 10:05:31.505906 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2948 10:05:31.505991 [Gating] SW calibration Done
2949 10:05:31.506057 ==
2950 10:05:31.509376 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 10:05:31.515966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 10:05:31.516052 ==
2953 10:05:31.516118 RX Vref Scan: 0
2954 10:05:31.516180
2955 10:05:31.519188 RX Vref 0 -> 0, step: 1
2956 10:05:31.519272
2957 10:05:31.522805 RX Delay -40 -> 252, step: 8
2958 10:05:31.525950 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2959 10:05:31.529104 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2960 10:05:31.532419 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2961 10:05:31.538998 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2962 10:05:31.542692 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2963 10:05:31.545766 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2964 10:05:31.549031 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2965 10:05:31.552915 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2966 10:05:31.556262 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2967 10:05:31.562578 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2968 10:05:31.565856 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2969 10:05:31.569063 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2970 10:05:31.572354 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2971 10:05:31.579193 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2972 10:05:31.582396 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2973 10:05:31.585817 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2974 10:05:31.585919 ==
2975 10:05:31.588930 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 10:05:31.592581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 10:05:31.592681 ==
2978 10:05:31.595778 DQS Delay:
2979 10:05:31.595877 DQS0 = 0, DQS1 = 0
2980 10:05:31.595974 DQM Delay:
2981 10:05:31.599086 DQM0 = 121, DQM1 = 112
2982 10:05:31.599224 DQ Delay:
2983 10:05:31.602873 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2984 10:05:31.605748 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2985 10:05:31.609372 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2986 10:05:31.616074 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2987 10:05:31.616175
2988 10:05:31.616270
2989 10:05:31.616345 ==
2990 10:05:31.619555 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 10:05:31.622651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 10:05:31.622750 ==
2993 10:05:31.622851
2994 10:05:31.622945
2995 10:05:31.626133 TX Vref Scan disable
2996 10:05:31.626222 == TX Byte 0 ==
2997 10:05:31.632885 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2998 10:05:31.636384 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2999 10:05:31.636469 == TX Byte 1 ==
3000 10:05:31.643117 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3001 10:05:31.646311 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3002 10:05:31.646394 ==
3003 10:05:31.649465 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 10:05:31.652465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 10:05:31.652562 ==
3006 10:05:31.665821 TX Vref=22, minBit 2, minWin=25, winSum=410
3007 10:05:31.669727 TX Vref=24, minBit 3, minWin=25, winSum=415
3008 10:05:31.673005 TX Vref=26, minBit 0, minWin=26, winSum=419
3009 10:05:31.676249 TX Vref=28, minBit 4, minWin=25, winSum=421
3010 10:05:31.679355 TX Vref=30, minBit 1, minWin=26, winSum=423
3011 10:05:31.682660 TX Vref=32, minBit 1, minWin=25, winSum=414
3012 10:05:31.689860 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 30
3013 10:05:31.689941
3014 10:05:31.693113 Final TX Range 1 Vref 30
3015 10:05:31.693205
3016 10:05:31.693290 ==
3017 10:05:31.696324 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 10:05:31.699341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 10:05:31.699467 ==
3020 10:05:31.699545
3021 10:05:31.699640
3022 10:05:31.703107 TX Vref Scan disable
3023 10:05:31.706385 == TX Byte 0 ==
3024 10:05:31.709683 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3025 10:05:31.712641 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3026 10:05:31.716486 == TX Byte 1 ==
3027 10:05:31.719680 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3028 10:05:31.722766 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3029 10:05:31.722852
3030 10:05:31.726626 [DATLAT]
3031 10:05:31.726712 Freq=1200, CH0 RK1
3032 10:05:31.726798
3033 10:05:31.729646 DATLAT Default: 0xd
3034 10:05:31.729732 0, 0xFFFF, sum = 0
3035 10:05:31.733066 1, 0xFFFF, sum = 0
3036 10:05:31.733153 2, 0xFFFF, sum = 0
3037 10:05:31.736218 3, 0xFFFF, sum = 0
3038 10:05:31.736305 4, 0xFFFF, sum = 0
3039 10:05:31.739791 5, 0xFFFF, sum = 0
3040 10:05:31.739878 6, 0xFFFF, sum = 0
3041 10:05:31.743320 7, 0xFFFF, sum = 0
3042 10:05:31.743407 8, 0xFFFF, sum = 0
3043 10:05:31.746206 9, 0xFFFF, sum = 0
3044 10:05:31.746293 10, 0xFFFF, sum = 0
3045 10:05:31.749941 11, 0xFFFF, sum = 0
3046 10:05:31.750027 12, 0x0, sum = 1
3047 10:05:31.753346 13, 0x0, sum = 2
3048 10:05:31.753433 14, 0x0, sum = 3
3049 10:05:31.756513 15, 0x0, sum = 4
3050 10:05:31.756599 best_step = 13
3051 10:05:31.756685
3052 10:05:31.756784 ==
3053 10:05:31.759735 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 10:05:31.766638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 10:05:31.766728 ==
3056 10:05:31.766815 RX Vref Scan: 0
3057 10:05:31.766895
3058 10:05:31.769779 RX Vref 0 -> 0, step: 1
3059 10:05:31.769861
3060 10:05:31.773098 RX Delay -13 -> 252, step: 4
3061 10:05:31.776331 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3062 10:05:31.779550 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3063 10:05:31.786496 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3064 10:05:31.789684 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3065 10:05:31.792936 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3066 10:05:31.796161 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3067 10:05:31.799979 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3068 10:05:31.803247 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3069 10:05:31.810028 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3070 10:05:31.813346 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3071 10:05:31.816400 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3072 10:05:31.820049 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3073 10:05:31.823250 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3074 10:05:31.830152 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3075 10:05:31.833286 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3076 10:05:31.836530 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3077 10:05:31.836651 ==
3078 10:05:31.839810 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 10:05:31.843606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 10:05:31.843694 ==
3081 10:05:31.846659 DQS Delay:
3082 10:05:31.846744 DQS0 = 0, DQS1 = 0
3083 10:05:31.849880 DQM Delay:
3084 10:05:31.849965 DQM0 = 120, DQM1 = 110
3085 10:05:31.853496 DQ Delay:
3086 10:05:31.856568 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3087 10:05:31.860379 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3088 10:05:31.863507 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3089 10:05:31.866812 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3090 10:05:31.866895
3091 10:05:31.866960
3092 10:05:31.873596 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3093 10:05:31.877060 CH0 RK1: MR19=403, MR18=FF0
3094 10:05:31.883417 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3095 10:05:31.887201 [RxdqsGatingPostProcess] freq 1200
3096 10:05:31.890386 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3097 10:05:31.893745 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 10:05:31.897019 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 10:05:31.900329 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 10:05:31.903646 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 10:05:31.906970 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 10:05:31.910256 best DQS1 dly(2T, 0.5T) = (0, 11)
3103 10:05:31.914055 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 10:05:31.917140 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3105 10:05:31.920254 Pre-setting of DQS Precalculation
3106 10:05:31.923485 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3107 10:05:31.923573 ==
3108 10:05:31.927202 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 10:05:31.933534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 10:05:31.933677 ==
3111 10:05:31.937310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3112 10:05:31.943475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3113 10:05:31.952058 [CA 0] Center 37 (7~68) winsize 62
3114 10:05:31.955474 [CA 1] Center 37 (7~68) winsize 62
3115 10:05:31.958667 [CA 2] Center 35 (5~65) winsize 61
3116 10:05:31.962380 [CA 3] Center 34 (4~64) winsize 61
3117 10:05:31.965569 [CA 4] Center 34 (4~64) winsize 61
3118 10:05:31.968839 [CA 5] Center 33 (3~63) winsize 61
3119 10:05:31.968920
3120 10:05:31.971986 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3121 10:05:31.972065
3122 10:05:31.975384 [CATrainingPosCal] consider 1 rank data
3123 10:05:31.979101 u2DelayCellTimex100 = 270/100 ps
3124 10:05:31.982290 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 10:05:31.985571 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3126 10:05:31.992235 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3127 10:05:31.995348 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 10:05:31.998688 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3129 10:05:32.002470 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3130 10:05:32.002552
3131 10:05:32.005633 CA PerBit enable=1, Macro0, CA PI delay=33
3132 10:05:32.005746
3133 10:05:32.008910 [CBTSetCACLKResult] CA Dly = 33
3134 10:05:32.009005 CS Dly: 7 (0~38)
3135 10:05:32.009093 ==
3136 10:05:32.012190 Dram Type= 6, Freq= 0, CH_1, rank 1
3137 10:05:32.018609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 10:05:32.018703 ==
3139 10:05:32.022362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 10:05:32.029293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3141 10:05:32.037475 [CA 0] Center 37 (7~68) winsize 62
3142 10:05:32.041325 [CA 1] Center 37 (7~68) winsize 62
3143 10:05:32.044503 [CA 2] Center 35 (5~66) winsize 62
3144 10:05:32.047984 [CA 3] Center 34 (4~65) winsize 62
3145 10:05:32.051067 [CA 4] Center 34 (4~65) winsize 62
3146 10:05:32.054664 [CA 5] Center 34 (4~64) winsize 61
3147 10:05:32.054744
3148 10:05:32.057783 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3149 10:05:32.057864
3150 10:05:32.061058 [CATrainingPosCal] consider 2 rank data
3151 10:05:32.064786 u2DelayCellTimex100 = 270/100 ps
3152 10:05:32.067847 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 10:05:32.071715 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 10:05:32.074915 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3155 10:05:32.081277 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 10:05:32.084510 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 10:05:32.087842 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3158 10:05:32.087934
3159 10:05:32.091232 CA PerBit enable=1, Macro0, CA PI delay=33
3160 10:05:32.091336
3161 10:05:32.094519 [CBTSetCACLKResult] CA Dly = 33
3162 10:05:32.094601 CS Dly: 8 (0~41)
3163 10:05:32.094684
3164 10:05:32.098274 ----->DramcWriteLeveling(PI) begin...
3165 10:05:32.098352 ==
3166 10:05:32.101154 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 10:05:32.107962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 10:05:32.108093 ==
3169 10:05:32.111271 Write leveling (Byte 0): 26 => 26
3170 10:05:32.114615 Write leveling (Byte 1): 27 => 27
3171 10:05:32.114728 DramcWriteLeveling(PI) end<-----
3172 10:05:32.117784
3173 10:05:32.117885 ==
3174 10:05:32.120995 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 10:05:32.124996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 10:05:32.125074 ==
3177 10:05:32.128122 [Gating] SW mode calibration
3178 10:05:32.134781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3179 10:05:32.137947 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3180 10:05:32.144864 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 10:05:32.148176 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 10:05:32.151411 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 10:05:32.158061 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 10:05:32.161464 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 10:05:32.165162 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 10:05:32.171667 0 15 24 | B1->B0 | 3232 2c2c | 1 1 | (0 0) (1 0)
3187 10:05:32.174788 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3188 10:05:32.177998 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 10:05:32.181760 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 10:05:32.188034 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 10:05:32.191325 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 10:05:32.195264 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 10:05:32.201665 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 10:05:32.204878 1 0 24 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
3195 10:05:32.208000 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 10:05:32.214573 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 10:05:32.217805 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 10:05:32.221191 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 10:05:32.228341 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 10:05:32.231702 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 10:05:32.234968 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 10:05:32.241121 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3203 10:05:32.244785 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3204 10:05:32.247956 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 10:05:32.255059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 10:05:32.258411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 10:05:32.261687 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 10:05:32.268012 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 10:05:32.271695 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 10:05:32.274550 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:05:32.281768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:05:32.284905 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:05:32.288364 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:05:32.291351 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:05:32.298453 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:05:32.301650 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:05:32.304848 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:05:32.311435 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 10:05:32.315193 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3220 10:05:32.318031 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 10:05:32.321772 Total UI for P1: 0, mck2ui 16
3222 10:05:32.325016 best dqsien dly found for B0: ( 1, 3, 26)
3223 10:05:32.328095 Total UI for P1: 0, mck2ui 16
3224 10:05:32.331779 best dqsien dly found for B1: ( 1, 3, 26)
3225 10:05:32.335261 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3226 10:05:32.338349 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3227 10:05:32.338437
3228 10:05:32.344915 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3229 10:05:32.348094 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3230 10:05:32.348198 [Gating] SW calibration Done
3231 10:05:32.351716 ==
3232 10:05:32.354763 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 10:05:32.358258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 10:05:32.358362 ==
3235 10:05:32.358450 RX Vref Scan: 0
3236 10:05:32.358532
3237 10:05:32.361438 RX Vref 0 -> 0, step: 1
3238 10:05:32.361549
3239 10:05:32.364648 RX Delay -40 -> 252, step: 8
3240 10:05:32.368247 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3241 10:05:32.371530 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3242 10:05:32.374705 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3243 10:05:32.381475 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3244 10:05:32.384974 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3245 10:05:32.388467 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3246 10:05:32.391435 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3247 10:05:32.395207 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3248 10:05:32.401740 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3249 10:05:32.405094 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3250 10:05:32.408448 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3251 10:05:32.411667 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3252 10:05:32.415528 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3253 10:05:32.422091 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3254 10:05:32.425214 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3255 10:05:32.428636 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3256 10:05:32.428752 ==
3257 10:05:32.431842 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 10:05:32.435019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 10:05:32.435121 ==
3260 10:05:32.438601 DQS Delay:
3261 10:05:32.438715 DQS0 = 0, DQS1 = 0
3262 10:05:32.438813 DQM Delay:
3263 10:05:32.442202 DQM0 = 119, DQM1 = 116
3264 10:05:32.442285 DQ Delay:
3265 10:05:32.445341 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3266 10:05:32.448496 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3267 10:05:32.455576 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3268 10:05:32.458735 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3269 10:05:32.458862
3270 10:05:32.458952
3271 10:05:32.459037 ==
3272 10:05:32.461932 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 10:05:32.465423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 10:05:32.465507 ==
3275 10:05:32.465595
3276 10:05:32.465676
3277 10:05:32.468559 TX Vref Scan disable
3278 10:05:32.468643 == TX Byte 0 ==
3279 10:05:32.475635 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3280 10:05:32.478930 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3281 10:05:32.479014 == TX Byte 1 ==
3282 10:05:32.485213 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3283 10:05:32.489023 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3284 10:05:32.489108 ==
3285 10:05:32.492151 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 10:05:32.495323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 10:05:32.495424 ==
3288 10:05:32.508144 TX Vref=22, minBit 9, minWin=24, winSum=411
3289 10:05:32.511332 TX Vref=24, minBit 9, minWin=25, winSum=418
3290 10:05:32.514536 TX Vref=26, minBit 11, minWin=25, winSum=423
3291 10:05:32.517865 TX Vref=28, minBit 1, minWin=26, winSum=429
3292 10:05:32.521752 TX Vref=30, minBit 9, minWin=25, winSum=428
3293 10:05:32.525071 TX Vref=32, minBit 10, minWin=25, winSum=430
3294 10:05:32.531562 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3295 10:05:32.531647
3296 10:05:32.534619 Final TX Range 1 Vref 28
3297 10:05:32.534703
3298 10:05:32.534769 ==
3299 10:05:32.538212 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 10:05:32.541381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 10:05:32.541493 ==
3302 10:05:32.541628
3303 10:05:32.544542
3304 10:05:32.544652 TX Vref Scan disable
3305 10:05:32.548332 == TX Byte 0 ==
3306 10:05:32.551391 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 10:05:32.554674 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 10:05:32.557884 == TX Byte 1 ==
3309 10:05:32.561159 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3310 10:05:32.565045 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3311 10:05:32.565130
3312 10:05:32.568216 [DATLAT]
3313 10:05:32.568300 Freq=1200, CH1 RK0
3314 10:05:32.568428
3315 10:05:32.571143 DATLAT Default: 0xd
3316 10:05:32.571254 0, 0xFFFF, sum = 0
3317 10:05:32.575023 1, 0xFFFF, sum = 0
3318 10:05:32.575160 2, 0xFFFF, sum = 0
3319 10:05:32.578209 3, 0xFFFF, sum = 0
3320 10:05:32.578293 4, 0xFFFF, sum = 0
3321 10:05:32.581838 5, 0xFFFF, sum = 0
3322 10:05:32.581953 6, 0xFFFF, sum = 0
3323 10:05:32.584925 7, 0xFFFF, sum = 0
3324 10:05:32.585074 8, 0xFFFF, sum = 0
3325 10:05:32.588156 9, 0xFFFF, sum = 0
3326 10:05:32.588242 10, 0xFFFF, sum = 0
3327 10:05:32.591934 11, 0xFFFF, sum = 0
3328 10:05:32.592019 12, 0x0, sum = 1
3329 10:05:32.594911 13, 0x0, sum = 2
3330 10:05:32.594996 14, 0x0, sum = 3
3331 10:05:32.598608 15, 0x0, sum = 4
3332 10:05:32.598693 best_step = 13
3333 10:05:32.598764
3334 10:05:32.598824 ==
3335 10:05:32.601796 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 10:05:32.608515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 10:05:32.608600 ==
3338 10:05:32.608666 RX Vref Scan: 1
3339 10:05:32.608727
3340 10:05:32.611489 Set Vref Range= 32 -> 127
3341 10:05:32.611566
3342 10:05:32.615259 RX Vref 32 -> 127, step: 1
3343 10:05:32.615360
3344 10:05:32.615454 RX Delay -5 -> 252, step: 4
3345 10:05:32.618281
3346 10:05:32.618354 Set Vref, RX VrefLevel [Byte0]: 32
3347 10:05:32.621545 [Byte1]: 32
3348 10:05:32.626175
3349 10:05:32.626255 Set Vref, RX VrefLevel [Byte0]: 33
3350 10:05:32.629481 [Byte1]: 33
3351 10:05:32.634115
3352 10:05:32.634197 Set Vref, RX VrefLevel [Byte0]: 34
3353 10:05:32.637427 [Byte1]: 34
3354 10:05:32.641996
3355 10:05:32.642078 Set Vref, RX VrefLevel [Byte0]: 35
3356 10:05:32.645424 [Byte1]: 35
3357 10:05:32.649613
3358 10:05:32.649720 Set Vref, RX VrefLevel [Byte0]: 36
3359 10:05:32.652724 [Byte1]: 36
3360 10:05:32.657769
3361 10:05:32.657852 Set Vref, RX VrefLevel [Byte0]: 37
3362 10:05:32.660925 [Byte1]: 37
3363 10:05:32.665548
3364 10:05:32.665678 Set Vref, RX VrefLevel [Byte0]: 38
3365 10:05:32.668749 [Byte1]: 38
3366 10:05:32.673269
3367 10:05:32.673373 Set Vref, RX VrefLevel [Byte0]: 39
3368 10:05:32.676436 [Byte1]: 39
3369 10:05:32.681361
3370 10:05:32.684395 Set Vref, RX VrefLevel [Byte0]: 40
3371 10:05:32.687485 [Byte1]: 40
3372 10:05:32.687560
3373 10:05:32.690630 Set Vref, RX VrefLevel [Byte0]: 41
3374 10:05:32.694416 [Byte1]: 41
3375 10:05:32.694516
3376 10:05:32.697539 Set Vref, RX VrefLevel [Byte0]: 42
3377 10:05:32.700775 [Byte1]: 42
3378 10:05:32.704514
3379 10:05:32.704613 Set Vref, RX VrefLevel [Byte0]: 43
3380 10:05:32.708180 [Byte1]: 43
3381 10:05:32.712681
3382 10:05:32.712786 Set Vref, RX VrefLevel [Byte0]: 44
3383 10:05:32.715846 [Byte1]: 44
3384 10:05:32.720108
3385 10:05:32.720216 Set Vref, RX VrefLevel [Byte0]: 45
3386 10:05:32.723705 [Byte1]: 45
3387 10:05:32.728062
3388 10:05:32.728138 Set Vref, RX VrefLevel [Byte0]: 46
3389 10:05:32.731421 [Byte1]: 46
3390 10:05:32.736038
3391 10:05:32.736124 Set Vref, RX VrefLevel [Byte0]: 47
3392 10:05:32.739367 [Byte1]: 47
3393 10:05:32.743914
3394 10:05:32.744020 Set Vref, RX VrefLevel [Byte0]: 48
3395 10:05:32.747249 [Byte1]: 48
3396 10:05:32.751561
3397 10:05:32.751636 Set Vref, RX VrefLevel [Byte0]: 49
3398 10:05:32.755132 [Byte1]: 49
3399 10:05:32.759653
3400 10:05:32.759733 Set Vref, RX VrefLevel [Byte0]: 50
3401 10:05:32.763162 [Byte1]: 50
3402 10:05:32.767301
3403 10:05:32.767409 Set Vref, RX VrefLevel [Byte0]: 51
3404 10:05:32.771038 [Byte1]: 51
3405 10:05:32.775522
3406 10:05:32.775636 Set Vref, RX VrefLevel [Byte0]: 52
3407 10:05:32.778874 [Byte1]: 52
3408 10:05:32.783561
3409 10:05:32.783641 Set Vref, RX VrefLevel [Byte0]: 53
3410 10:05:32.786680 [Byte1]: 53
3411 10:05:32.790868
3412 10:05:32.791025 Set Vref, RX VrefLevel [Byte0]: 54
3413 10:05:32.794585 [Byte1]: 54
3414 10:05:32.798783
3415 10:05:32.798881 Set Vref, RX VrefLevel [Byte0]: 55
3416 10:05:32.802022 [Byte1]: 55
3417 10:05:32.806705
3418 10:05:32.806782 Set Vref, RX VrefLevel [Byte0]: 56
3419 10:05:32.809722 [Byte1]: 56
3420 10:05:32.814772
3421 10:05:32.814856 Set Vref, RX VrefLevel [Byte0]: 57
3422 10:05:32.818054 [Byte1]: 57
3423 10:05:32.822403
3424 10:05:32.822485 Set Vref, RX VrefLevel [Byte0]: 58
3425 10:05:32.825597 [Byte1]: 58
3426 10:05:32.829961
3427 10:05:32.830048 Set Vref, RX VrefLevel [Byte0]: 59
3428 10:05:32.833731 [Byte1]: 59
3429 10:05:32.838221
3430 10:05:32.838337 Set Vref, RX VrefLevel [Byte0]: 60
3431 10:05:32.841376 [Byte1]: 60
3432 10:05:32.846119
3433 10:05:32.846201 Set Vref, RX VrefLevel [Byte0]: 61
3434 10:05:32.849314 [Byte1]: 61
3435 10:05:32.853896
3436 10:05:32.853978 Set Vref, RX VrefLevel [Byte0]: 62
3437 10:05:32.857236 [Byte1]: 62
3438 10:05:32.861596
3439 10:05:32.861742 Set Vref, RX VrefLevel [Byte0]: 63
3440 10:05:32.864681 [Byte1]: 63
3441 10:05:32.869316
3442 10:05:32.869416 Set Vref, RX VrefLevel [Byte0]: 64
3443 10:05:32.872583 [Byte1]: 64
3444 10:05:32.877745
3445 10:05:32.877829 Set Vref, RX VrefLevel [Byte0]: 65
3446 10:05:32.880699 [Byte1]: 65
3447 10:05:32.885191
3448 10:05:32.885302 Set Vref, RX VrefLevel [Byte0]: 66
3449 10:05:32.888416 [Byte1]: 66
3450 10:05:32.892816
3451 10:05:32.892899 Set Vref, RX VrefLevel [Byte0]: 67
3452 10:05:32.896493 [Byte1]: 67
3453 10:05:32.900877
3454 10:05:32.900960 Set Vref, RX VrefLevel [Byte0]: 68
3455 10:05:32.904461 [Byte1]: 68
3456 10:05:32.908933
3457 10:05:32.909015 Set Vref, RX VrefLevel [Byte0]: 69
3458 10:05:32.911889 [Byte1]: 69
3459 10:05:32.916728
3460 10:05:32.916813 Final RX Vref Byte 0 = 53 to rank0
3461 10:05:32.919719 Final RX Vref Byte 1 = 47 to rank0
3462 10:05:32.923261 Final RX Vref Byte 0 = 53 to rank1
3463 10:05:32.926769 Final RX Vref Byte 1 = 47 to rank1==
3464 10:05:32.929925 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 10:05:32.936958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 10:05:32.937045 ==
3467 10:05:32.937112 DQS Delay:
3468 10:05:32.937228 DQS0 = 0, DQS1 = 0
3469 10:05:32.940138 DQM Delay:
3470 10:05:32.940222 DQM0 = 120, DQM1 = 116
3471 10:05:32.943456 DQ Delay:
3472 10:05:32.946788 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3473 10:05:32.950005 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3474 10:05:32.953273 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3475 10:05:32.956557 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3476 10:05:32.956641
3477 10:05:32.956706
3478 10:05:32.963623 [DQSOSCAuto] RK0, (LSB)MR18= 0xff11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3479 10:05:32.966893 CH1 RK0: MR19=304, MR18=FF11
3480 10:05:32.973744 CH1_RK0: MR19=0x304, MR18=0xFF11, DQSOSC=403, MR23=63, INC=40, DEC=26
3481 10:05:32.973864
3482 10:05:32.976869 ----->DramcWriteLeveling(PI) begin...
3483 10:05:32.976973 ==
3484 10:05:32.979944 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 10:05:32.983422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 10:05:32.983527 ==
3487 10:05:32.987022 Write leveling (Byte 0): 25 => 25
3488 10:05:32.990008 Write leveling (Byte 1): 28 => 28
3489 10:05:32.993518 DramcWriteLeveling(PI) end<-----
3490 10:05:32.993643
3491 10:05:32.993713 ==
3492 10:05:32.996720 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 10:05:33.000741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 10:05:33.003935 ==
3495 10:05:33.004051 [Gating] SW mode calibration
3496 10:05:33.013510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 10:05:33.017384 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 10:05:33.020399 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 10:05:33.026995 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 10:05:33.030762 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 10:05:33.033487 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 10:05:33.040499 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 10:05:33.043551 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3504 10:05:33.047517 0 15 24 | B1->B0 | 2828 3333 | 1 1 | (1 1) (1 0)
3505 10:05:33.054021 0 15 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 0)
3506 10:05:33.057212 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 10:05:33.060511 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 10:05:33.063784 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 10:05:33.070326 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 10:05:33.074218 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 10:05:33.077429 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3512 10:05:33.083753 1 0 24 | B1->B0 | 4343 2f2f | 0 0 | (0 0) (0 0)
3513 10:05:33.087739 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 10:05:33.090798 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 10:05:33.097276 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 10:05:33.100877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 10:05:33.103933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 10:05:33.110756 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 10:05:33.113836 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3520 10:05:33.117328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3521 10:05:33.123890 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3522 10:05:33.126977 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 10:05:33.130616 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 10:05:33.137491 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 10:05:33.140656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 10:05:33.143877 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 10:05:33.150417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 10:05:33.153582 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 10:05:33.157250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 10:05:33.163796 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 10:05:33.166977 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 10:05:33.170258 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 10:05:33.176757 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 10:05:33.179892 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:05:33.183720 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3536 10:05:33.190296 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3537 10:05:33.193495 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3538 10:05:33.196527 Total UI for P1: 0, mck2ui 16
3539 10:05:33.200300 best dqsien dly found for B1: ( 1, 3, 22)
3540 10:05:33.203488 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 10:05:33.206626 Total UI for P1: 0, mck2ui 16
3542 10:05:33.210273 best dqsien dly found for B0: ( 1, 3, 26)
3543 10:05:33.213357 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3544 10:05:33.216328 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3545 10:05:33.216412
3546 10:05:33.219932 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3547 10:05:33.226331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3548 10:05:33.226433 [Gating] SW calibration Done
3549 10:05:33.226573 ==
3550 10:05:33.229627 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 10:05:33.236741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 10:05:33.236826 ==
3553 10:05:33.236892 RX Vref Scan: 0
3554 10:05:33.236952
3555 10:05:33.239634 RX Vref 0 -> 0, step: 1
3556 10:05:33.239717
3557 10:05:33.243380 RX Delay -40 -> 252, step: 8
3558 10:05:33.246685 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3559 10:05:33.249928 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3560 10:05:33.253177 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3561 10:05:33.259718 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3562 10:05:33.263565 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3563 10:05:33.266394 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3564 10:05:33.269824 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3565 10:05:33.272925 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3566 10:05:33.276241 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3567 10:05:33.283471 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3568 10:05:33.286557 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3569 10:05:33.289744 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3570 10:05:33.292952 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3571 10:05:33.299376 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3572 10:05:33.303043 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3573 10:05:33.306762 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3574 10:05:33.306846 ==
3575 10:05:33.310057 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 10:05:33.313083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 10:05:33.313167 ==
3578 10:05:33.316355 DQS Delay:
3579 10:05:33.316438 DQS0 = 0, DQS1 = 0
3580 10:05:33.319654 DQM Delay:
3581 10:05:33.319736 DQM0 = 120, DQM1 = 118
3582 10:05:33.319802 DQ Delay:
3583 10:05:33.325981 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =115
3584 10:05:33.329497 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3585 10:05:33.332942 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3586 10:05:33.336409 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3587 10:05:33.336526
3588 10:05:33.336592
3589 10:05:33.336653 ==
3590 10:05:33.339564 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 10:05:33.342756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 10:05:33.342839 ==
3593 10:05:33.342904
3594 10:05:33.342964
3595 10:05:33.345884 TX Vref Scan disable
3596 10:05:33.349432 == TX Byte 0 ==
3597 10:05:33.352576 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3598 10:05:33.356371 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3599 10:05:33.359594 == TX Byte 1 ==
3600 10:05:33.362584 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 10:05:33.365805 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 10:05:33.365890 ==
3603 10:05:33.369600 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 10:05:33.372852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 10:05:33.375952 ==
3606 10:05:33.386086 TX Vref=22, minBit 2, minWin=25, winSum=419
3607 10:05:33.389451 TX Vref=24, minBit 1, minWin=25, winSum=422
3608 10:05:33.393110 TX Vref=26, minBit 10, minWin=25, winSum=428
3609 10:05:33.396330 TX Vref=28, minBit 4, minWin=26, winSum=429
3610 10:05:33.399566 TX Vref=30, minBit 9, minWin=26, winSum=434
3611 10:05:33.405986 TX Vref=32, minBit 9, minWin=26, winSum=434
3612 10:05:33.408986 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3613 10:05:33.409069
3614 10:05:33.412642 Final TX Range 1 Vref 30
3615 10:05:33.412725
3616 10:05:33.412791 ==
3617 10:05:33.415740 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 10:05:33.419406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 10:05:33.422582 ==
3620 10:05:33.422665
3621 10:05:33.422731
3622 10:05:33.422791 TX Vref Scan disable
3623 10:05:33.425766 == TX Byte 0 ==
3624 10:05:33.429602 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3625 10:05:33.432805 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3626 10:05:33.436203 == TX Byte 1 ==
3627 10:05:33.439237 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3628 10:05:33.445961 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3629 10:05:33.446046
3630 10:05:33.446114 [DATLAT]
3631 10:05:33.446186 Freq=1200, CH1 RK1
3632 10:05:33.446246
3633 10:05:33.449331 DATLAT Default: 0xd
3634 10:05:33.449439 0, 0xFFFF, sum = 0
3635 10:05:33.452310 1, 0xFFFF, sum = 0
3636 10:05:33.452396 2, 0xFFFF, sum = 0
3637 10:05:33.456059 3, 0xFFFF, sum = 0
3638 10:05:33.458956 4, 0xFFFF, sum = 0
3639 10:05:33.459063 5, 0xFFFF, sum = 0
3640 10:05:33.462743 6, 0xFFFF, sum = 0
3641 10:05:33.462869 7, 0xFFFF, sum = 0
3642 10:05:33.465988 8, 0xFFFF, sum = 0
3643 10:05:33.466105 9, 0xFFFF, sum = 0
3644 10:05:33.469382 10, 0xFFFF, sum = 0
3645 10:05:33.469485 11, 0xFFFF, sum = 0
3646 10:05:33.472476 12, 0x0, sum = 1
3647 10:05:33.472583 13, 0x0, sum = 2
3648 10:05:33.475688 14, 0x0, sum = 3
3649 10:05:33.475766 15, 0x0, sum = 4
3650 10:05:33.475853 best_step = 13
3651 10:05:33.478853
3652 10:05:33.478963 ==
3653 10:05:33.482707 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 10:05:33.485886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 10:05:33.485971 ==
3656 10:05:33.486036 RX Vref Scan: 0
3657 10:05:33.486096
3658 10:05:33.488852 RX Vref 0 -> 0, step: 1
3659 10:05:33.488934
3660 10:05:33.492413 RX Delay -5 -> 252, step: 4
3661 10:05:33.495787 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3662 10:05:33.502296 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3663 10:05:33.505470 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3664 10:05:33.508794 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3665 10:05:33.512716 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3666 10:05:33.515720 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3667 10:05:33.519321 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3668 10:05:33.525944 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3669 10:05:33.529182 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3670 10:05:33.532432 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3671 10:05:33.535751 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3672 10:05:33.542409 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3673 10:05:33.545735 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3674 10:05:33.549018 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3675 10:05:33.552153 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3676 10:05:33.555787 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3677 10:05:33.558674 ==
3678 10:05:33.558758 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 10:05:33.565204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 10:05:33.565290 ==
3681 10:05:33.565356 DQS Delay:
3682 10:05:33.568700 DQS0 = 0, DQS1 = 0
3683 10:05:33.568783 DQM Delay:
3684 10:05:33.572093 DQM0 = 120, DQM1 = 116
3685 10:05:33.572175 DQ Delay:
3686 10:05:33.575454 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3687 10:05:33.578789 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3688 10:05:33.582156 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3689 10:05:33.585435 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3690 10:05:33.585517
3691 10:05:33.585602
3692 10:05:33.595204 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3693 10:05:33.595289 CH1 RK1: MR19=403, MR18=FEC
3694 10:05:33.602051 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3695 10:05:33.605695 [RxdqsGatingPostProcess] freq 1200
3696 10:05:33.612005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 10:05:33.615312 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 10:05:33.618446 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 10:05:33.622154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 10:05:33.625288 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 10:05:33.628915 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 10:05:33.629008 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 10:05:33.631815 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 10:05:33.635366 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 10:05:33.638496 Pre-setting of DQS Precalculation
3706 10:05:33.645027 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 10:05:33.652203 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 10:05:33.658801 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 10:05:33.658885
3710 10:05:33.658950
3711 10:05:33.661795 [Calibration Summary] 2400 Mbps
3712 10:05:33.664997 CH 0, Rank 0
3713 10:05:33.665079 SW Impedance : PASS
3714 10:05:33.668389 DUTY Scan : NO K
3715 10:05:33.671610 ZQ Calibration : PASS
3716 10:05:33.671694 Jitter Meter : NO K
3717 10:05:33.675372 CBT Training : PASS
3718 10:05:33.675466 Write leveling : PASS
3719 10:05:33.678631 RX DQS gating : PASS
3720 10:05:33.681528 RX DQ/DQS(RDDQC) : PASS
3721 10:05:33.681634 TX DQ/DQS : PASS
3722 10:05:33.685119 RX DATLAT : PASS
3723 10:05:33.688679 RX DQ/DQS(Engine): PASS
3724 10:05:33.688762 TX OE : NO K
3725 10:05:33.691981 All Pass.
3726 10:05:33.692064
3727 10:05:33.692129 CH 0, Rank 1
3728 10:05:33.695109 SW Impedance : PASS
3729 10:05:33.695192 DUTY Scan : NO K
3730 10:05:33.698323 ZQ Calibration : PASS
3731 10:05:33.701518 Jitter Meter : NO K
3732 10:05:33.701623 CBT Training : PASS
3733 10:05:33.705360 Write leveling : PASS
3734 10:05:33.708458 RX DQS gating : PASS
3735 10:05:33.708540 RX DQ/DQS(RDDQC) : PASS
3736 10:05:33.711600 TX DQ/DQS : PASS
3737 10:05:33.714776 RX DATLAT : PASS
3738 10:05:33.714859 RX DQ/DQS(Engine): PASS
3739 10:05:33.718354 TX OE : NO K
3740 10:05:33.718437 All Pass.
3741 10:05:33.718502
3742 10:05:33.721817 CH 1, Rank 0
3743 10:05:33.721899 SW Impedance : PASS
3744 10:05:33.725340 DUTY Scan : NO K
3745 10:05:33.725423 ZQ Calibration : PASS
3746 10:05:33.728396 Jitter Meter : NO K
3747 10:05:33.731466 CBT Training : PASS
3748 10:05:33.731549 Write leveling : PASS
3749 10:05:33.735101 RX DQS gating : PASS
3750 10:05:33.738087 RX DQ/DQS(RDDQC) : PASS
3751 10:05:33.738168 TX DQ/DQS : PASS
3752 10:05:33.741706 RX DATLAT : PASS
3753 10:05:33.744840 RX DQ/DQS(Engine): PASS
3754 10:05:33.744922 TX OE : NO K
3755 10:05:33.748011 All Pass.
3756 10:05:33.748092
3757 10:05:33.748157 CH 1, Rank 1
3758 10:05:33.751255 SW Impedance : PASS
3759 10:05:33.751337 DUTY Scan : NO K
3760 10:05:33.755263 ZQ Calibration : PASS
3761 10:05:33.758455 Jitter Meter : NO K
3762 10:05:33.758537 CBT Training : PASS
3763 10:05:33.761800 Write leveling : PASS
3764 10:05:33.765117 RX DQS gating : PASS
3765 10:05:33.765200 RX DQ/DQS(RDDQC) : PASS
3766 10:05:33.768366 TX DQ/DQS : PASS
3767 10:05:33.768449 RX DATLAT : PASS
3768 10:05:33.771546 RX DQ/DQS(Engine): PASS
3769 10:05:33.774753 TX OE : NO K
3770 10:05:33.774836 All Pass.
3771 10:05:33.774901
3772 10:05:33.778250 DramC Write-DBI off
3773 10:05:33.778333 PER_BANK_REFRESH: Hybrid Mode
3774 10:05:33.781498 TX_TRACKING: ON
3775 10:05:33.791588 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 10:05:33.794753 [FAST_K] Save calibration result to emmc
3777 10:05:33.798858 dramc_set_vcore_voltage set vcore to 650000
3778 10:05:33.798941 Read voltage for 600, 5
3779 10:05:33.801403 Vio18 = 0
3780 10:05:33.801486 Vcore = 650000
3781 10:05:33.801552 Vdram = 0
3782 10:05:33.805073 Vddq = 0
3783 10:05:33.805156 Vmddr = 0
3784 10:05:33.808347 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 10:05:33.814898 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 10:05:33.818195 MEM_TYPE=3, freq_sel=19
3787 10:05:33.821524 sv_algorithm_assistance_LP4_1600
3788 10:05:33.825285 ============ PULL DRAM RESETB DOWN ============
3789 10:05:33.828271 ========== PULL DRAM RESETB DOWN end =========
3790 10:05:33.834803 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 10:05:33.838262 ===================================
3792 10:05:33.838345 LPDDR4 DRAM CONFIGURATION
3793 10:05:33.841750 ===================================
3794 10:05:33.844766 EX_ROW_EN[0] = 0x0
3795 10:05:33.844850 EX_ROW_EN[1] = 0x0
3796 10:05:33.848298 LP4Y_EN = 0x0
3797 10:05:33.848381 WORK_FSP = 0x0
3798 10:05:33.851279 WL = 0x2
3799 10:05:33.851387 RL = 0x2
3800 10:05:33.855078 BL = 0x2
3801 10:05:33.858012 RPST = 0x0
3802 10:05:33.858096 RD_PRE = 0x0
3803 10:05:33.861814 WR_PRE = 0x1
3804 10:05:33.861898 WR_PST = 0x0
3805 10:05:33.864430 DBI_WR = 0x0
3806 10:05:33.864514 DBI_RD = 0x0
3807 10:05:33.868322 OTF = 0x1
3808 10:05:33.871446 ===================================
3809 10:05:33.874709 ===================================
3810 10:05:33.874792 ANA top config
3811 10:05:33.877998 ===================================
3812 10:05:33.881130 DLL_ASYNC_EN = 0
3813 10:05:33.884562 ALL_SLAVE_EN = 1
3814 10:05:33.884645 NEW_RANK_MODE = 1
3815 10:05:33.888013 DLL_IDLE_MODE = 1
3816 10:05:33.891136 LP45_APHY_COMB_EN = 1
3817 10:05:33.894781 TX_ODT_DIS = 1
3818 10:05:33.894865 NEW_8X_MODE = 1
3819 10:05:33.898000 ===================================
3820 10:05:33.901266 ===================================
3821 10:05:33.904506 data_rate = 1200
3822 10:05:33.908235 CKR = 1
3823 10:05:33.911096 DQ_P2S_RATIO = 8
3824 10:05:33.914709 ===================================
3825 10:05:33.917740 CA_P2S_RATIO = 8
3826 10:05:33.920955 DQ_CA_OPEN = 0
3827 10:05:33.921037 DQ_SEMI_OPEN = 0
3828 10:05:33.924919 CA_SEMI_OPEN = 0
3829 10:05:33.928232 CA_FULL_RATE = 0
3830 10:05:33.931256 DQ_CKDIV4_EN = 1
3831 10:05:33.934437 CA_CKDIV4_EN = 1
3832 10:05:33.937761 CA_PREDIV_EN = 0
3833 10:05:33.937844 PH8_DLY = 0
3834 10:05:33.940966 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 10:05:33.944743 DQ_AAMCK_DIV = 4
3836 10:05:33.947648 CA_AAMCK_DIV = 4
3837 10:05:33.951115 CA_ADMCK_DIV = 4
3838 10:05:33.954312 DQ_TRACK_CA_EN = 0
3839 10:05:33.954429 CA_PICK = 600
3840 10:05:33.957759 CA_MCKIO = 600
3841 10:05:33.961240 MCKIO_SEMI = 0
3842 10:05:33.964514 PLL_FREQ = 2288
3843 10:05:33.967912 DQ_UI_PI_RATIO = 32
3844 10:05:33.971114 CA_UI_PI_RATIO = 0
3845 10:05:33.974333 ===================================
3846 10:05:33.977616 ===================================
3847 10:05:33.977716 memory_type:LPDDR4
3848 10:05:33.980754 GP_NUM : 10
3849 10:05:33.984227 SRAM_EN : 1
3850 10:05:33.984330 MD32_EN : 0
3851 10:05:33.988058 ===================================
3852 10:05:33.991253 [ANA_INIT] >>>>>>>>>>>>>>
3853 10:05:33.994264 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 10:05:33.997726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 10:05:34.001129 ===================================
3856 10:05:34.004321 data_rate = 1200,PCW = 0X5800
3857 10:05:34.007468 ===================================
3858 10:05:34.010771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 10:05:34.013897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 10:05:34.020712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 10:05:34.024454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 10:05:34.027606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 10:05:34.033944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 10:05:34.034028 [ANA_INIT] flow start
3865 10:05:34.037747 [ANA_INIT] PLL >>>>>>>>
3866 10:05:34.041082 [ANA_INIT] PLL <<<<<<<<
3867 10:05:34.041165 [ANA_INIT] MIDPI >>>>>>>>
3868 10:05:34.044337 [ANA_INIT] MIDPI <<<<<<<<
3869 10:05:34.047614 [ANA_INIT] DLL >>>>>>>>
3870 10:05:34.047697 [ANA_INIT] flow end
3871 10:05:34.050855 ============ LP4 DIFF to SE enter ============
3872 10:05:34.057470 ============ LP4 DIFF to SE exit ============
3873 10:05:34.057568 [ANA_INIT] <<<<<<<<<<<<<
3874 10:05:34.060362 [Flow] Enable top DCM control >>>>>
3875 10:05:34.064329 [Flow] Enable top DCM control <<<<<
3876 10:05:34.067413 Enable DLL master slave shuffle
3877 10:05:34.073801 ==============================================================
3878 10:05:34.073885 Gating Mode config
3879 10:05:34.080318 ==============================================================
3880 10:05:34.083822 Config description:
3881 10:05:34.094127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 10:05:34.100456 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 10:05:34.103774 SELPH_MODE 0: By rank 1: By Phase
3884 10:05:34.110185 ==============================================================
3885 10:05:34.113967 GAT_TRACK_EN = 1
3886 10:05:34.116946 RX_GATING_MODE = 2
3887 10:05:34.117030 RX_GATING_TRACK_MODE = 2
3888 10:05:34.120743 SELPH_MODE = 1
3889 10:05:34.123927 PICG_EARLY_EN = 1
3890 10:05:34.126910 VALID_LAT_VALUE = 1
3891 10:05:34.133891 ==============================================================
3892 10:05:34.137146 Enter into Gating configuration >>>>
3893 10:05:34.140896 Exit from Gating configuration <<<<
3894 10:05:34.143584 Enter into DVFS_PRE_config >>>>>
3895 10:05:34.153362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 10:05:34.157258 Exit from DVFS_PRE_config <<<<<
3897 10:05:34.160554 Enter into PICG configuration >>>>
3898 10:05:34.163709 Exit from PICG configuration <<<<
3899 10:05:34.167299 [RX_INPUT] configuration >>>>>
3900 10:05:34.170225 [RX_INPUT] configuration <<<<<
3901 10:05:34.174071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 10:05:34.180593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 10:05:34.186768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 10:05:34.190257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 10:05:34.197126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 10:05:34.203810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 10:05:34.207065 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 10:05:34.210361 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 10:05:34.217082 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 10:05:34.220533 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 10:05:34.223655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 10:05:34.230415 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 10:05:34.233821 ===================================
3914 10:05:34.233940 LPDDR4 DRAM CONFIGURATION
3915 10:05:34.236828 ===================================
3916 10:05:34.240530 EX_ROW_EN[0] = 0x0
3917 10:05:34.243542 EX_ROW_EN[1] = 0x0
3918 10:05:34.243626 LP4Y_EN = 0x0
3919 10:05:34.246801 WORK_FSP = 0x0
3920 10:05:34.246911 WL = 0x2
3921 10:05:34.250647 RL = 0x2
3922 10:05:34.250730 BL = 0x2
3923 10:05:34.253925 RPST = 0x0
3924 10:05:34.254035 RD_PRE = 0x0
3925 10:05:34.257082 WR_PRE = 0x1
3926 10:05:34.257166 WR_PST = 0x0
3927 10:05:34.260376 DBI_WR = 0x0
3928 10:05:34.260485 DBI_RD = 0x0
3929 10:05:34.264157 OTF = 0x1
3930 10:05:34.267470 ===================================
3931 10:05:34.270747 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 10:05:34.273531 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 10:05:34.277210 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 10:05:34.280294 ===================================
3935 10:05:34.283539 LPDDR4 DRAM CONFIGURATION
3936 10:05:34.287445 ===================================
3937 10:05:34.290680 EX_ROW_EN[0] = 0x10
3938 10:05:34.290759 EX_ROW_EN[1] = 0x0
3939 10:05:34.293852 LP4Y_EN = 0x0
3940 10:05:34.293952 WORK_FSP = 0x0
3941 10:05:34.297073 WL = 0x2
3942 10:05:34.297175 RL = 0x2
3943 10:05:34.300244 BL = 0x2
3944 10:05:34.300348 RPST = 0x0
3945 10:05:34.303787 RD_PRE = 0x0
3946 10:05:34.303887 WR_PRE = 0x1
3947 10:05:34.307336 WR_PST = 0x0
3948 10:05:34.307439 DBI_WR = 0x0
3949 10:05:34.310485 DBI_RD = 0x0
3950 10:05:34.313882 OTF = 0x1
3951 10:05:34.314001 ===================================
3952 10:05:34.320189 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 10:05:34.325690 nWR fixed to 30
3954 10:05:34.328867 [ModeRegInit_LP4] CH0 RK0
3955 10:05:34.328969 [ModeRegInit_LP4] CH0 RK1
3956 10:05:34.332239 [ModeRegInit_LP4] CH1 RK0
3957 10:05:34.335560 [ModeRegInit_LP4] CH1 RK1
3958 10:05:34.335659 match AC timing 17
3959 10:05:34.342546 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 10:05:34.345689 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 10:05:34.348528 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 10:05:34.355501 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 10:05:34.359017 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 10:05:34.359121 ==
3965 10:05:34.362064 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 10:05:34.365408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 10:05:34.365493 ==
3968 10:05:34.371877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 10:05:34.378884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3970 10:05:34.381994 [CA 0] Center 36 (5~67) winsize 63
3971 10:05:34.385052 [CA 1] Center 36 (5~67) winsize 63
3972 10:05:34.388951 [CA 2] Center 34 (3~65) winsize 63
3973 10:05:34.392141 [CA 3] Center 34 (3~65) winsize 63
3974 10:05:34.395384 [CA 4] Center 33 (2~64) winsize 63
3975 10:05:34.398593 [CA 5] Center 32 (2~63) winsize 62
3976 10:05:34.398695
3977 10:05:34.401765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3978 10:05:34.401866
3979 10:05:34.405040 [CATrainingPosCal] consider 1 rank data
3980 10:05:34.408844 u2DelayCellTimex100 = 270/100 ps
3981 10:05:34.411835 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3982 10:05:34.415113 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3983 10:05:34.418378 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3984 10:05:34.421884 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
3985 10:05:34.424922 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3986 10:05:34.431604 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3987 10:05:34.431739
3988 10:05:34.435050 CA PerBit enable=1, Macro0, CA PI delay=32
3989 10:05:34.435129
3990 10:05:34.438340 [CBTSetCACLKResult] CA Dly = 32
3991 10:05:34.438422 CS Dly: 4 (0~35)
3992 10:05:34.438487 ==
3993 10:05:34.441661 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 10:05:34.444909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 10:05:34.448017 ==
3996 10:05:34.451361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 10:05:34.458053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 10:05:34.461616 [CA 0] Center 36 (5~67) winsize 63
3999 10:05:34.465088 [CA 1] Center 36 (5~67) winsize 63
4000 10:05:34.468696 [CA 2] Center 34 (3~65) winsize 63
4001 10:05:34.472035 [CA 3] Center 34 (3~65) winsize 63
4002 10:05:34.475104 [CA 4] Center 33 (2~64) winsize 63
4003 10:05:34.478409 [CA 5] Center 32 (2~63) winsize 62
4004 10:05:34.478531
4005 10:05:34.481713 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 10:05:34.481799
4007 10:05:34.484933 [CATrainingPosCal] consider 2 rank data
4008 10:05:34.488175 u2DelayCellTimex100 = 270/100 ps
4009 10:05:34.491768 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
4010 10:05:34.494997 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4011 10:05:34.498334 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4012 10:05:34.505197 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
4013 10:05:34.508378 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4014 10:05:34.511605 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4015 10:05:34.511714
4016 10:05:34.514655 CA PerBit enable=1, Macro0, CA PI delay=32
4017 10:05:34.514743
4018 10:05:34.518588 [CBTSetCACLKResult] CA Dly = 32
4019 10:05:34.518676 CS Dly: 4 (0~36)
4020 10:05:34.518744
4021 10:05:34.521196 ----->DramcWriteLeveling(PI) begin...
4022 10:05:34.521274 ==
4023 10:05:34.524980 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 10:05:34.531285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 10:05:34.531393 ==
4026 10:05:34.534738 Write leveling (Byte 0): 33 => 33
4027 10:05:34.538308 Write leveling (Byte 1): 33 => 33
4028 10:05:34.538423 DramcWriteLeveling(PI) end<-----
4029 10:05:34.541319
4030 10:05:34.541427 ==
4031 10:05:34.544422 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 10:05:34.547783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 10:05:34.547867 ==
4034 10:05:34.552830 [Gating] SW mode calibration
4035 10:05:34.558128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 10:05:34.561406 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 10:05:34.567708 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 10:05:34.570912 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 10:05:34.574778 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 10:05:34.581323 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (0 0)
4041 10:05:34.584219 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4042 10:05:34.587656 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 10:05:34.594473 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 10:05:34.597443 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 10:05:34.601396 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 10:05:34.607788 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 10:05:34.611002 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 10:05:34.614229 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4049 10:05:34.621088 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4050 10:05:34.624225 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 10:05:34.627542 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 10:05:34.634433 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 10:05:34.637718 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 10:05:34.640761 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 10:05:34.647362 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 10:05:34.650444 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 10:05:34.654270 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4058 10:05:34.660790 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 10:05:34.664090 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 10:05:34.667259 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 10:05:34.674183 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 10:05:34.677398 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 10:05:34.680577 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 10:05:34.687035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 10:05:34.690792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 10:05:34.694082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 10:05:34.700583 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 10:05:34.703969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 10:05:34.707354 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 10:05:34.710323 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 10:05:34.717449 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:05:34.720568 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4073 10:05:34.723653 Total UI for P1: 0, mck2ui 16
4074 10:05:34.727012 best dqsien dly found for B0: ( 0, 13, 10)
4075 10:05:34.730271 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4076 10:05:34.737430 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 10:05:34.740489 Total UI for P1: 0, mck2ui 16
4078 10:05:34.743670 best dqsien dly found for B1: ( 0, 13, 16)
4079 10:05:34.747382 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4080 10:05:34.750340 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4081 10:05:34.750445
4082 10:05:34.753709 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4083 10:05:34.757087 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4084 10:05:34.760459 [Gating] SW calibration Done
4085 10:05:34.760554 ==
4086 10:05:34.763495 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 10:05:34.766763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 10:05:34.766860 ==
4089 10:05:34.770034 RX Vref Scan: 0
4090 10:05:34.770128
4091 10:05:34.770195 RX Vref 0 -> 0, step: 1
4092 10:05:34.773849
4093 10:05:34.773953 RX Delay -230 -> 252, step: 16
4094 10:05:34.780176 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4095 10:05:34.783375 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4096 10:05:34.787345 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4097 10:05:34.790315 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4098 10:05:34.793526 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4099 10:05:34.800695 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4100 10:05:34.803921 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4101 10:05:34.807206 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4102 10:05:34.810325 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4103 10:05:34.816628 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4104 10:05:34.820048 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4105 10:05:34.823341 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4106 10:05:34.826673 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4107 10:05:34.833229 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4108 10:05:34.836781 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4109 10:05:34.839950 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4110 10:05:34.840035 ==
4111 10:05:34.843713 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 10:05:34.846838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 10:05:34.850049 ==
4114 10:05:34.850144 DQS Delay:
4115 10:05:34.850210 DQS0 = 0, DQS1 = 0
4116 10:05:34.853297 DQM Delay:
4117 10:05:34.853383 DQM0 = 52, DQM1 = 46
4118 10:05:34.856577 DQ Delay:
4119 10:05:34.856663 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4120 10:05:34.859669 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4121 10:05:34.863163 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4122 10:05:34.866646 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4123 10:05:34.866745
4124 10:05:34.869413
4125 10:05:34.869524 ==
4126 10:05:34.873222 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 10:05:34.876283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 10:05:34.876378 ==
4129 10:05:34.876445
4130 10:05:34.876505
4131 10:05:34.879513 TX Vref Scan disable
4132 10:05:34.879598 == TX Byte 0 ==
4133 10:05:34.886551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4134 10:05:34.889839 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4135 10:05:34.889933 == TX Byte 1 ==
4136 10:05:34.896142 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4137 10:05:34.899336 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4138 10:05:34.899461 ==
4139 10:05:34.902562 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 10:05:34.905880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 10:05:34.905980 ==
4142 10:05:34.906047
4143 10:05:34.906108
4144 10:05:34.909198 TX Vref Scan disable
4145 10:05:34.913087 == TX Byte 0 ==
4146 10:05:34.915715 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4147 10:05:34.919689 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4148 10:05:34.922725 == TX Byte 1 ==
4149 10:05:34.926024 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4150 10:05:34.929766 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4151 10:05:34.929862
4152 10:05:34.933035 [DATLAT]
4153 10:05:34.933122 Freq=600, CH0 RK0
4154 10:05:34.933188
4155 10:05:34.936109 DATLAT Default: 0x9
4156 10:05:34.936194 0, 0xFFFF, sum = 0
4157 10:05:34.939274 1, 0xFFFF, sum = 0
4158 10:05:34.939363 2, 0xFFFF, sum = 0
4159 10:05:34.942598 3, 0xFFFF, sum = 0
4160 10:05:34.942688 4, 0xFFFF, sum = 0
4161 10:05:34.945871 5, 0xFFFF, sum = 0
4162 10:05:34.945960 6, 0xFFFF, sum = 0
4163 10:05:34.949412 7, 0xFFFF, sum = 0
4164 10:05:34.949506 8, 0x0, sum = 1
4165 10:05:34.952796 9, 0x0, sum = 2
4166 10:05:34.952883 10, 0x0, sum = 3
4167 10:05:34.956283 11, 0x0, sum = 4
4168 10:05:34.956419 best_step = 9
4169 10:05:34.956516
4170 10:05:34.956606 ==
4171 10:05:34.959079 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 10:05:34.966038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 10:05:34.966154 ==
4174 10:05:34.966221 RX Vref Scan: 1
4175 10:05:34.966283
4176 10:05:34.969304 RX Vref 0 -> 0, step: 1
4177 10:05:34.969418
4178 10:05:34.973118 RX Delay -163 -> 252, step: 8
4179 10:05:34.973212
4180 10:05:34.976078 Set Vref, RX VrefLevel [Byte0]: 56
4181 10:05:34.979103 [Byte1]: 49
4182 10:05:34.979195
4183 10:05:34.982667 Final RX Vref Byte 0 = 56 to rank0
4184 10:05:34.985979 Final RX Vref Byte 1 = 49 to rank0
4185 10:05:34.989214 Final RX Vref Byte 0 = 56 to rank1
4186 10:05:34.992845 Final RX Vref Byte 1 = 49 to rank1==
4187 10:05:34.996238 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 10:05:34.999133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 10:05:34.999261 ==
4190 10:05:35.002447 DQS Delay:
4191 10:05:35.002539 DQS0 = 0, DQS1 = 0
4192 10:05:35.002606 DQM Delay:
4193 10:05:35.005711 DQM0 = 52, DQM1 = 47
4194 10:05:35.005799 DQ Delay:
4195 10:05:35.009547 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4196 10:05:35.012837 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4197 10:05:35.016038 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4198 10:05:35.019226 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =56
4199 10:05:35.019320
4200 10:05:35.019400
4201 10:05:35.029342 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4202 10:05:35.029501 CH0 RK0: MR19=808, MR18=6F62
4203 10:05:35.035571 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4204 10:05:35.035687
4205 10:05:35.039332 ----->DramcWriteLeveling(PI) begin...
4206 10:05:35.039422 ==
4207 10:05:35.042569 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 10:05:35.048936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 10:05:35.049086 ==
4210 10:05:35.052198 Write leveling (Byte 0): 34 => 34
4211 10:05:35.055623 Write leveling (Byte 1): 31 => 31
4212 10:05:35.059177 DramcWriteLeveling(PI) end<-----
4213 10:05:35.059279
4214 10:05:35.059349 ==
4215 10:05:35.061991 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 10:05:35.065759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 10:05:35.065857 ==
4218 10:05:35.068533 [Gating] SW mode calibration
4219 10:05:35.075628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 10:05:35.078624 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4221 10:05:35.085642 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 10:05:35.088935 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 10:05:35.091999 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 10:05:35.098527 0 9 12 | B1->B0 | 3333 3333 | 1 0 | (0 0) (0 0)
4225 10:05:35.101794 0 9 16 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
4226 10:05:35.105469 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 10:05:35.112000 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 10:05:35.115148 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 10:05:35.118466 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 10:05:35.125560 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 10:05:35.128613 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 10:05:35.131799 0 10 12 | B1->B0 | 2727 2d2d | 0 1 | (0 0) (0 0)
4233 10:05:35.138928 0 10 16 | B1->B0 | 4242 4141 | 0 0 | (0 0) (0 0)
4234 10:05:35.142061 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 10:05:35.145236 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 10:05:35.152268 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 10:05:35.155557 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 10:05:35.158782 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 10:05:35.165203 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 10:05:35.168445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4241 10:05:35.172128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 10:05:35.178519 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 10:05:35.181979 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 10:05:35.184946 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 10:05:35.191850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 10:05:35.194761 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 10:05:35.198334 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 10:05:35.204750 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 10:05:35.208403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 10:05:35.211816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 10:05:35.214714 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:05:35.221457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 10:05:35.224644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 10:05:35.228222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:05:35.234559 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:05:35.237781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4257 10:05:35.244316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 10:05:35.244435 Total UI for P1: 0, mck2ui 16
4259 10:05:35.247950 best dqsien dly found for B0: ( 0, 13, 12)
4260 10:05:35.251119 Total UI for P1: 0, mck2ui 16
4261 10:05:35.254289 best dqsien dly found for B1: ( 0, 13, 12)
4262 10:05:35.261455 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4263 10:05:35.264519 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4264 10:05:35.264623
4265 10:05:35.267625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4266 10:05:35.270769 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4267 10:05:35.274100 [Gating] SW calibration Done
4268 10:05:35.274187 ==
4269 10:05:35.277933 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 10:05:35.281262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 10:05:35.281375 ==
4272 10:05:35.284462 RX Vref Scan: 0
4273 10:05:35.284570
4274 10:05:35.284664 RX Vref 0 -> 0, step: 1
4275 10:05:35.284750
4276 10:05:35.287655 RX Delay -230 -> 252, step: 16
4277 10:05:35.290833 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4278 10:05:35.297786 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4279 10:05:35.300889 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4280 10:05:35.304483 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4281 10:05:35.307397 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4282 10:05:35.314507 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4283 10:05:35.317803 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4284 10:05:35.320829 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4285 10:05:35.324064 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4286 10:05:35.327885 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4287 10:05:35.334264 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4288 10:05:35.337275 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4289 10:05:35.341034 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4290 10:05:35.343915 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4291 10:05:35.351047 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4292 10:05:35.354176 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4293 10:05:35.354272 ==
4294 10:05:35.357332 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 10:05:35.360539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 10:05:35.360634 ==
4297 10:05:35.363801 DQS Delay:
4298 10:05:35.363906 DQS0 = 0, DQS1 = 0
4299 10:05:35.363984 DQM Delay:
4300 10:05:35.367632 DQM0 = 51, DQM1 = 43
4301 10:05:35.367728 DQ Delay:
4302 10:05:35.370781 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4303 10:05:35.373896 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4304 10:05:35.377155 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4305 10:05:35.380623 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4306 10:05:35.380719
4307 10:05:35.380786
4308 10:05:35.380845 ==
4309 10:05:35.383802 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 10:05:35.390750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 10:05:35.390859 ==
4312 10:05:35.390930
4313 10:05:35.390994
4314 10:05:35.391063 TX Vref Scan disable
4315 10:05:35.394066 == TX Byte 0 ==
4316 10:05:35.397878 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4317 10:05:35.400651 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4318 10:05:35.404682 == TX Byte 1 ==
4319 10:05:35.407938 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4320 10:05:35.413968 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4321 10:05:35.414096 ==
4322 10:05:35.417585 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 10:05:35.421104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 10:05:35.421232 ==
4325 10:05:35.421324
4326 10:05:35.421421
4327 10:05:35.423764 TX Vref Scan disable
4328 10:05:35.427238 == TX Byte 0 ==
4329 10:05:35.430510 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 10:05:35.434376 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 10:05:35.437655 == TX Byte 1 ==
4332 10:05:35.440745 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 10:05:35.443847 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 10:05:35.443957
4335 10:05:35.444048 [DATLAT]
4336 10:05:35.447530 Freq=600, CH0 RK1
4337 10:05:35.447611
4338 10:05:35.447691 DATLAT Default: 0x9
4339 10:05:35.450763 0, 0xFFFF, sum = 0
4340 10:05:35.453904 1, 0xFFFF, sum = 0
4341 10:05:35.453984 2, 0xFFFF, sum = 0
4342 10:05:35.457364 3, 0xFFFF, sum = 0
4343 10:05:35.457474 4, 0xFFFF, sum = 0
4344 10:05:35.460633 5, 0xFFFF, sum = 0
4345 10:05:35.460749 6, 0xFFFF, sum = 0
4346 10:05:35.464154 7, 0xFFFF, sum = 0
4347 10:05:35.464275 8, 0x0, sum = 1
4348 10:05:35.467214 9, 0x0, sum = 2
4349 10:05:35.467312 10, 0x0, sum = 3
4350 10:05:35.467376 11, 0x0, sum = 4
4351 10:05:35.470416 best_step = 9
4352 10:05:35.470490
4353 10:05:35.470561 ==
4354 10:05:35.473715 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 10:05:35.477440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 10:05:35.477551 ==
4357 10:05:35.480547 RX Vref Scan: 0
4358 10:05:35.480651
4359 10:05:35.480749 RX Vref 0 -> 0, step: 1
4360 10:05:35.480813
4361 10:05:35.483717 RX Delay -163 -> 252, step: 8
4362 10:05:35.491565 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4363 10:05:35.494677 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4364 10:05:35.498030 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4365 10:05:35.501135 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4366 10:05:35.504350 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4367 10:05:35.511414 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4368 10:05:35.514230 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4369 10:05:35.518134 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4370 10:05:35.521306 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4371 10:05:35.524609 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4372 10:05:35.530770 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4373 10:05:35.534196 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4374 10:05:35.537504 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4375 10:05:35.541010 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4376 10:05:35.547210 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4377 10:05:35.550486 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4378 10:05:35.550601 ==
4379 10:05:35.553830 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 10:05:35.557105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 10:05:35.557212 ==
4382 10:05:35.560873 DQS Delay:
4383 10:05:35.560984 DQS0 = 0, DQS1 = 0
4384 10:05:35.561074 DQM Delay:
4385 10:05:35.564029 DQM0 = 52, DQM1 = 46
4386 10:05:35.564135 DQ Delay:
4387 10:05:35.567092 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4388 10:05:35.570579 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4389 10:05:35.574030 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4390 10:05:35.577487 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4391 10:05:35.577648
4392 10:05:35.577718
4393 10:05:35.587195 [DQSOSCAuto] RK1, (LSB)MR18= 0x6020, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4394 10:05:35.587320 CH0 RK1: MR19=808, MR18=6020
4395 10:05:35.593996 CH0_RK1: MR19=0x808, MR18=0x6020, DQSOSC=391, MR23=63, INC=171, DEC=114
4396 10:05:35.597130 [RxdqsGatingPostProcess] freq 600
4397 10:05:35.603638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4398 10:05:35.606802 Pre-setting of DQS Precalculation
4399 10:05:35.610117 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4400 10:05:35.610216 ==
4401 10:05:35.613767 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 10:05:35.620308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 10:05:35.620413 ==
4404 10:05:35.623907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 10:05:35.630299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4406 10:05:35.633515 [CA 0] Center 36 (5~67) winsize 63
4407 10:05:35.636826 [CA 1] Center 36 (6~67) winsize 62
4408 10:05:35.640643 [CA 2] Center 35 (4~66) winsize 63
4409 10:05:35.643536 [CA 3] Center 34 (4~65) winsize 62
4410 10:05:35.646966 [CA 4] Center 34 (4~65) winsize 62
4411 10:05:35.650359 [CA 5] Center 34 (4~65) winsize 62
4412 10:05:35.650454
4413 10:05:35.653710 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4414 10:05:35.653806
4415 10:05:35.656929 [CATrainingPosCal] consider 1 rank data
4416 10:05:35.660517 u2DelayCellTimex100 = 270/100 ps
4417 10:05:35.663622 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4418 10:05:35.666898 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4419 10:05:35.673347 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4420 10:05:35.677196 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 10:05:35.680263 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 10:05:35.683703 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 10:05:35.683792
4424 10:05:35.687219 CA PerBit enable=1, Macro0, CA PI delay=34
4425 10:05:35.687301
4426 10:05:35.690214 [CBTSetCACLKResult] CA Dly = 34
4427 10:05:35.690291 CS Dly: 5 (0~36)
4428 10:05:35.690361 ==
4429 10:05:35.693734 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 10:05:35.700688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 10:05:35.700832 ==
4432 10:05:35.703608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 10:05:35.710313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4434 10:05:35.713566 [CA 0] Center 36 (5~67) winsize 63
4435 10:05:35.716811 [CA 1] Center 36 (6~67) winsize 62
4436 10:05:35.720231 [CA 2] Center 35 (5~66) winsize 62
4437 10:05:35.723443 [CA 3] Center 35 (4~66) winsize 63
4438 10:05:35.727457 [CA 4] Center 35 (4~66) winsize 63
4439 10:05:35.730597 [CA 5] Center 34 (4~65) winsize 62
4440 10:05:35.730707
4441 10:05:35.733631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4442 10:05:35.733751
4443 10:05:35.736896 [CATrainingPosCal] consider 2 rank data
4444 10:05:35.740220 u2DelayCellTimex100 = 270/100 ps
4445 10:05:35.743615 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4446 10:05:35.746957 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4447 10:05:35.753399 CA2 delay=35 (5~66),Diff = 1 PI (9 cell)
4448 10:05:35.757149 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 10:05:35.760295 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4450 10:05:35.763943 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4451 10:05:35.764089
4452 10:05:35.766760 CA PerBit enable=1, Macro0, CA PI delay=34
4453 10:05:35.766877
4454 10:05:35.770074 [CBTSetCACLKResult] CA Dly = 34
4455 10:05:35.770156 CS Dly: 6 (0~38)
4456 10:05:35.770242
4457 10:05:35.773293 ----->DramcWriteLeveling(PI) begin...
4458 10:05:35.777036 ==
4459 10:05:35.779861 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 10:05:35.783643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 10:05:35.783793 ==
4462 10:05:35.786858 Write leveling (Byte 0): 30 => 30
4463 10:05:35.790092 Write leveling (Byte 1): 27 => 27
4464 10:05:35.793458 DramcWriteLeveling(PI) end<-----
4465 10:05:35.793615
4466 10:05:35.793705 ==
4467 10:05:35.796756 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 10:05:35.799843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 10:05:35.799944 ==
4470 10:05:35.803466 [Gating] SW mode calibration
4471 10:05:35.810272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 10:05:35.813367 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4473 10:05:35.819937 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 10:05:35.823123 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 10:05:35.826519 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 10:05:35.833723 0 9 12 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
4477 10:05:35.836608 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 10:05:35.839888 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 10:05:35.846828 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 10:05:35.850057 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 10:05:35.853283 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 10:05:35.859706 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 10:05:35.863499 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 10:05:35.866524 0 10 12 | B1->B0 | 3434 3c3c | 1 0 | (0 0) (0 0)
4485 10:05:35.873308 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 10:05:35.876306 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 10:05:35.880221 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 10:05:35.886679 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 10:05:35.889929 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 10:05:35.893347 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 10:05:35.899740 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 10:05:35.903056 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4493 10:05:35.906424 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 10:05:35.913067 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 10:05:35.916599 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 10:05:35.919849 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 10:05:35.926585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 10:05:35.929572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 10:05:35.933437 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 10:05:35.936583 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 10:05:35.943428 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 10:05:35.946453 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 10:05:35.949990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 10:05:35.956424 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 10:05:35.960138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 10:05:35.963348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 10:05:35.969616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 10:05:35.973302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4509 10:05:35.976444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 10:05:35.979600 Total UI for P1: 0, mck2ui 16
4511 10:05:35.983277 best dqsien dly found for B0: ( 0, 13, 12)
4512 10:05:35.986425 Total UI for P1: 0, mck2ui 16
4513 10:05:35.989544 best dqsien dly found for B1: ( 0, 13, 12)
4514 10:05:35.993405 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4515 10:05:35.996550 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4516 10:05:35.996678
4517 10:05:36.003519 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4518 10:05:36.006501 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4519 10:05:36.006620 [Gating] SW calibration Done
4520 10:05:36.010083 ==
4521 10:05:36.013360 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 10:05:36.016273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 10:05:36.016376 ==
4524 10:05:36.016446 RX Vref Scan: 0
4525 10:05:36.016508
4526 10:05:36.019952 RX Vref 0 -> 0, step: 1
4527 10:05:36.020048
4528 10:05:36.023035 RX Delay -230 -> 252, step: 16
4529 10:05:36.026344 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4530 10:05:36.029807 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4531 10:05:36.036435 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4532 10:05:36.039888 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4533 10:05:36.043431 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4534 10:05:36.046521 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4535 10:05:36.050092 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4536 10:05:36.056263 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4537 10:05:36.060053 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4538 10:05:36.063306 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4539 10:05:36.066405 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4540 10:05:36.072868 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4541 10:05:36.076646 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4542 10:05:36.079719 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4543 10:05:36.082740 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4544 10:05:36.086518 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4545 10:05:36.089756 ==
4546 10:05:36.092858 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 10:05:36.095960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 10:05:36.096085 ==
4549 10:05:36.096158 DQS Delay:
4550 10:05:36.099212 DQS0 = 0, DQS1 = 0
4551 10:05:36.099314 DQM Delay:
4552 10:05:36.103004 DQM0 = 50, DQM1 = 49
4553 10:05:36.103111 DQ Delay:
4554 10:05:36.106026 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4555 10:05:36.109260 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4556 10:05:36.113077 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4557 10:05:36.116494 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4558 10:05:36.116603
4559 10:05:36.116673
4560 10:05:36.116735 ==
4561 10:05:36.119506 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 10:05:36.122835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 10:05:36.122972 ==
4564 10:05:36.123068
4565 10:05:36.123158
4566 10:05:36.125775 TX Vref Scan disable
4567 10:05:36.129461 == TX Byte 0 ==
4568 10:05:36.132789 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4569 10:05:36.135885 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4570 10:05:36.139486 == TX Byte 1 ==
4571 10:05:36.142497 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4572 10:05:36.146442 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4573 10:05:36.146597 ==
4574 10:05:36.149275 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 10:05:36.152546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 10:05:36.155930 ==
4577 10:05:36.156068
4578 10:05:36.156179
4579 10:05:36.156272 TX Vref Scan disable
4580 10:05:36.159687 == TX Byte 0 ==
4581 10:05:36.163199 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4582 10:05:36.169786 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4583 10:05:36.169914 == TX Byte 1 ==
4584 10:05:36.173429 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4585 10:05:36.179774 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4586 10:05:36.179955
4587 10:05:36.180056 [DATLAT]
4588 10:05:36.180161 Freq=600, CH1 RK0
4589 10:05:36.180251
4590 10:05:36.183571 DATLAT Default: 0x9
4591 10:05:36.183699 0, 0xFFFF, sum = 0
4592 10:05:36.186886 1, 0xFFFF, sum = 0
4593 10:05:36.187023 2, 0xFFFF, sum = 0
4594 10:05:36.189873 3, 0xFFFF, sum = 0
4595 10:05:36.193099 4, 0xFFFF, sum = 0
4596 10:05:36.193237 5, 0xFFFF, sum = 0
4597 10:05:36.196253 6, 0xFFFF, sum = 0
4598 10:05:36.196391 7, 0xFFFF, sum = 0
4599 10:05:36.200088 8, 0x0, sum = 1
4600 10:05:36.200236 9, 0x0, sum = 2
4601 10:05:36.200334 10, 0x0, sum = 3
4602 10:05:36.203215 11, 0x0, sum = 4
4603 10:05:36.203340 best_step = 9
4604 10:05:36.203433
4605 10:05:36.203535 ==
4606 10:05:36.206425 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 10:05:36.213175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 10:05:36.213346 ==
4609 10:05:36.213444 RX Vref Scan: 1
4610 10:05:36.213549
4611 10:05:36.216479 RX Vref 0 -> 0, step: 1
4612 10:05:36.216578
4613 10:05:36.219681 RX Delay -163 -> 252, step: 8
4614 10:05:36.219803
4615 10:05:36.223469 Set Vref, RX VrefLevel [Byte0]: 53
4616 10:05:36.226270 [Byte1]: 47
4617 10:05:36.226390
4618 10:05:36.229809 Final RX Vref Byte 0 = 53 to rank0
4619 10:05:36.232929 Final RX Vref Byte 1 = 47 to rank0
4620 10:05:36.236781 Final RX Vref Byte 0 = 53 to rank1
4621 10:05:36.239950 Final RX Vref Byte 1 = 47 to rank1==
4622 10:05:36.243188 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 10:05:36.246483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 10:05:36.246603 ==
4625 10:05:36.249708 DQS Delay:
4626 10:05:36.249805 DQS0 = 0, DQS1 = 0
4627 10:05:36.249879 DQM Delay:
4628 10:05:36.253539 DQM0 = 49, DQM1 = 45
4629 10:05:36.253681 DQ Delay:
4630 10:05:36.256468 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4631 10:05:36.260002 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4632 10:05:36.263007 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4633 10:05:36.266715 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4634 10:05:36.266836
4635 10:05:36.266920
4636 10:05:36.276592 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4637 10:05:36.276794 CH1 RK0: MR19=808, MR18=4B71
4638 10:05:36.282864 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4639 10:05:36.282989
4640 10:05:36.286585 ----->DramcWriteLeveling(PI) begin...
4641 10:05:36.290211 ==
4642 10:05:36.290399 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 10:05:36.296278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 10:05:36.296434 ==
4645 10:05:36.299841 Write leveling (Byte 0): 28 => 28
4646 10:05:36.303039 Write leveling (Byte 1): 33 => 33
4647 10:05:36.306382 DramcWriteLeveling(PI) end<-----
4648 10:05:36.306556
4649 10:05:36.306690 ==
4650 10:05:36.309478 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 10:05:36.312700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 10:05:36.312828 ==
4653 10:05:36.316566 [Gating] SW mode calibration
4654 10:05:36.323260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 10:05:36.329784 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 10:05:36.332989 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 10:05:36.336126 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 10:05:36.339326 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4659 10:05:36.346227 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4660 10:05:36.349455 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 10:05:36.352981 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 10:05:36.359771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 10:05:36.362969 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 10:05:36.366267 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 10:05:36.372790 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 10:05:36.375984 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 10:05:36.379357 0 10 12 | B1->B0 | 3b3b 3434 | 0 1 | (0 0) (0 0)
4668 10:05:36.386449 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 10:05:36.389405 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 10:05:36.392634 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 10:05:36.399545 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 10:05:36.403213 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 10:05:36.406157 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 10:05:36.412631 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 10:05:36.416177 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4676 10:05:36.419212 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 10:05:36.426251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 10:05:36.429625 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 10:05:36.432950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 10:05:36.436304 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 10:05:36.442804 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 10:05:36.445978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 10:05:36.449297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 10:05:36.455861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 10:05:36.459166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 10:05:36.462668 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 10:05:36.469108 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 10:05:36.472354 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 10:05:36.475944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:05:36.482549 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 10:05:36.485835 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4692 10:05:36.489062 Total UI for P1: 0, mck2ui 16
4693 10:05:36.492890 best dqsien dly found for B1: ( 0, 13, 10)
4694 10:05:36.495829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 10:05:36.499115 Total UI for P1: 0, mck2ui 16
4696 10:05:36.502527 best dqsien dly found for B0: ( 0, 13, 12)
4697 10:05:36.505711 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4698 10:05:36.508740 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4699 10:05:36.512739
4700 10:05:36.515972 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4701 10:05:36.519126 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4702 10:05:36.522342 [Gating] SW calibration Done
4703 10:05:36.522442 ==
4704 10:05:36.525488 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 10:05:36.528981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 10:05:36.529102 ==
4707 10:05:36.529209 RX Vref Scan: 0
4708 10:05:36.529310
4709 10:05:36.532148 RX Vref 0 -> 0, step: 1
4710 10:05:36.532253
4711 10:05:36.535551 RX Delay -230 -> 252, step: 16
4712 10:05:36.539356 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4713 10:05:36.542138 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4714 10:05:36.549402 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4715 10:05:36.552229 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4716 10:05:36.555946 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4717 10:05:36.559208 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4718 10:05:36.565918 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4719 10:05:36.569388 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4720 10:05:36.572597 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4721 10:05:36.575837 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4722 10:05:36.578939 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4723 10:05:36.585798 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4724 10:05:36.589151 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4725 10:05:36.592305 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4726 10:05:36.595581 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4727 10:05:36.602629 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4728 10:05:36.602758 ==
4729 10:05:36.605833 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 10:05:36.609123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 10:05:36.609245 ==
4732 10:05:36.609351 DQS Delay:
4733 10:05:36.612257 DQS0 = 0, DQS1 = 0
4734 10:05:36.612369 DQM Delay:
4735 10:05:36.615384 DQM0 = 50, DQM1 = 45
4736 10:05:36.615505 DQ Delay:
4737 10:05:36.619296 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4738 10:05:36.622471 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4739 10:05:36.625203 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4740 10:05:36.629073 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4741 10:05:36.629197
4742 10:05:36.629303
4743 10:05:36.629416 ==
4744 10:05:36.632208 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 10:05:36.635307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 10:05:36.635427 ==
4747 10:05:36.638540
4748 10:05:36.638631
4749 10:05:36.638718 TX Vref Scan disable
4750 10:05:36.641758 == TX Byte 0 ==
4751 10:05:36.645011 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4752 10:05:36.648778 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4753 10:05:36.651729 == TX Byte 1 ==
4754 10:05:36.655343 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4755 10:05:36.658548 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4756 10:05:36.661904 ==
4757 10:05:36.665277 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 10:05:36.667962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 10:05:36.668074 ==
4760 10:05:36.668147
4761 10:05:36.668210
4762 10:05:36.671529 TX Vref Scan disable
4763 10:05:36.675122 == TX Byte 0 ==
4764 10:05:36.678392 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4765 10:05:36.681622 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4766 10:05:36.684674 == TX Byte 1 ==
4767 10:05:36.688492 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4768 10:05:36.691638 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4769 10:05:36.691761
4770 10:05:36.691858 [DATLAT]
4771 10:05:36.694879 Freq=600, CH1 RK1
4772 10:05:36.694996
4773 10:05:36.695092 DATLAT Default: 0x9
4774 10:05:36.698039 0, 0xFFFF, sum = 0
4775 10:05:36.698118 1, 0xFFFF, sum = 0
4776 10:05:36.701381 2, 0xFFFF, sum = 0
4777 10:05:36.705072 3, 0xFFFF, sum = 0
4778 10:05:36.705193 4, 0xFFFF, sum = 0
4779 10:05:36.708311 5, 0xFFFF, sum = 0
4780 10:05:36.708428 6, 0xFFFF, sum = 0
4781 10:05:36.711656 7, 0xFFFF, sum = 0
4782 10:05:36.711743 8, 0x0, sum = 1
4783 10:05:36.711843 9, 0x0, sum = 2
4784 10:05:36.714878 10, 0x0, sum = 3
4785 10:05:36.714959 11, 0x0, sum = 4
4786 10:05:36.718482 best_step = 9
4787 10:05:36.718568
4788 10:05:36.718658 ==
4789 10:05:36.721741 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 10:05:36.725033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 10:05:36.725145 ==
4792 10:05:36.728355 RX Vref Scan: 0
4793 10:05:36.728438
4794 10:05:36.728536 RX Vref 0 -> 0, step: 1
4795 10:05:36.728617
4796 10:05:36.731517 RX Delay -163 -> 252, step: 8
4797 10:05:36.738553 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4798 10:05:36.741756 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4799 10:05:36.745220 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4800 10:05:36.748407 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4801 10:05:36.752369 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4802 10:05:36.758787 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4803 10:05:36.761838 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4804 10:05:36.765137 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4805 10:05:36.768388 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4806 10:05:36.772004 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4807 10:05:36.778783 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4808 10:05:36.782145 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4809 10:05:36.785558 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4810 10:05:36.788636 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4811 10:05:36.795564 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4812 10:05:36.798373 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4813 10:05:36.798468 ==
4814 10:05:36.801841 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 10:05:36.805125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 10:05:36.805216 ==
4817 10:05:36.808350 DQS Delay:
4818 10:05:36.808438 DQS0 = 0, DQS1 = 0
4819 10:05:36.808505 DQM Delay:
4820 10:05:36.812236 DQM0 = 49, DQM1 = 44
4821 10:05:36.812348 DQ Delay:
4822 10:05:36.815062 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4823 10:05:36.818450 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4824 10:05:36.821599 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4825 10:05:36.825301 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4826 10:05:36.825397
4827 10:05:36.825503
4828 10:05:36.835123 [DQSOSCAuto] RK1, (LSB)MR18= 0x661d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4829 10:05:36.835257 CH1 RK1: MR19=808, MR18=661D
4830 10:05:36.841373 CH1_RK1: MR19=0x808, MR18=0x661D, DQSOSC=390, MR23=63, INC=172, DEC=114
4831 10:05:36.845153 [RxdqsGatingPostProcess] freq 600
4832 10:05:36.851657 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4833 10:05:36.854884 Pre-setting of DQS Precalculation
4834 10:05:36.858091 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4835 10:05:36.865044 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4836 10:05:36.874597 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4837 10:05:36.874749
4838 10:05:36.874825
4839 10:05:36.878359 [Calibration Summary] 1200 Mbps
4840 10:05:36.878452 CH 0, Rank 0
4841 10:05:36.881411 SW Impedance : PASS
4842 10:05:36.881499 DUTY Scan : NO K
4843 10:05:36.884480 ZQ Calibration : PASS
4844 10:05:36.888226 Jitter Meter : NO K
4845 10:05:36.888319 CBT Training : PASS
4846 10:05:36.891341 Write leveling : PASS
4847 10:05:36.894473 RX DQS gating : PASS
4848 10:05:36.894567 RX DQ/DQS(RDDQC) : PASS
4849 10:05:36.897740 TX DQ/DQS : PASS
4850 10:05:36.897831 RX DATLAT : PASS
4851 10:05:36.901533 RX DQ/DQS(Engine): PASS
4852 10:05:36.904764 TX OE : NO K
4853 10:05:36.904854 All Pass.
4854 10:05:36.904921
4855 10:05:36.904983 CH 0, Rank 1
4856 10:05:36.907821 SW Impedance : PASS
4857 10:05:36.911162 DUTY Scan : NO K
4858 10:05:36.911253 ZQ Calibration : PASS
4859 10:05:36.914740 Jitter Meter : NO K
4860 10:05:36.917639 CBT Training : PASS
4861 10:05:36.917730 Write leveling : PASS
4862 10:05:36.921448 RX DQS gating : PASS
4863 10:05:36.924571 RX DQ/DQS(RDDQC) : PASS
4864 10:05:36.924658 TX DQ/DQS : PASS
4865 10:05:36.927812 RX DATLAT : PASS
4866 10:05:36.931187 RX DQ/DQS(Engine): PASS
4867 10:05:36.931276 TX OE : NO K
4868 10:05:36.931348 All Pass.
4869 10:05:36.934616
4870 10:05:36.934713 CH 1, Rank 0
4871 10:05:36.938038 SW Impedance : PASS
4872 10:05:36.938179 DUTY Scan : NO K
4873 10:05:36.941022 ZQ Calibration : PASS
4874 10:05:36.941134 Jitter Meter : NO K
4875 10:05:36.944983 CBT Training : PASS
4876 10:05:36.948036 Write leveling : PASS
4877 10:05:36.948165 RX DQS gating : PASS
4878 10:05:36.951378 RX DQ/DQS(RDDQC) : PASS
4879 10:05:36.954415 TX DQ/DQS : PASS
4880 10:05:36.954513 RX DATLAT : PASS
4881 10:05:36.957738 RX DQ/DQS(Engine): PASS
4882 10:05:36.961491 TX OE : NO K
4883 10:05:36.961644 All Pass.
4884 10:05:36.961716
4885 10:05:36.961788 CH 1, Rank 1
4886 10:05:36.964633 SW Impedance : PASS
4887 10:05:36.967823 DUTY Scan : NO K
4888 10:05:36.967948 ZQ Calibration : PASS
4889 10:05:36.971247 Jitter Meter : NO K
4890 10:05:36.974441 CBT Training : PASS
4891 10:05:36.974548 Write leveling : PASS
4892 10:05:36.977838 RX DQS gating : PASS
4893 10:05:36.977942 RX DQ/DQS(RDDQC) : PASS
4894 10:05:36.981058 TX DQ/DQS : PASS
4895 10:05:36.984287 RX DATLAT : PASS
4896 10:05:36.984388 RX DQ/DQS(Engine): PASS
4897 10:05:36.988145 TX OE : NO K
4898 10:05:36.988253 All Pass.
4899 10:05:36.988350
4900 10:05:36.991372 DramC Write-DBI off
4901 10:05:36.994804 PER_BANK_REFRESH: Hybrid Mode
4902 10:05:36.994905 TX_TRACKING: ON
4903 10:05:37.004510 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4904 10:05:37.007804 [FAST_K] Save calibration result to emmc
4905 10:05:37.010938 dramc_set_vcore_voltage set vcore to 662500
4906 10:05:37.014177 Read voltage for 933, 3
4907 10:05:37.014267 Vio18 = 0
4908 10:05:37.017974 Vcore = 662500
4909 10:05:37.018051 Vdram = 0
4910 10:05:37.018153 Vddq = 0
4911 10:05:37.018212 Vmddr = 0
4912 10:05:37.024622 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4913 10:05:37.027847 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4914 10:05:37.030490 MEM_TYPE=3, freq_sel=17
4915 10:05:37.034171 sv_algorithm_assistance_LP4_1600
4916 10:05:37.037291 ============ PULL DRAM RESETB DOWN ============
4917 10:05:37.044017 ========== PULL DRAM RESETB DOWN end =========
4918 10:05:37.047432 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4919 10:05:37.050442 ===================================
4920 10:05:37.053780 LPDDR4 DRAM CONFIGURATION
4921 10:05:37.057745 ===================================
4922 10:05:37.057869 EX_ROW_EN[0] = 0x0
4923 10:05:37.060826 EX_ROW_EN[1] = 0x0
4924 10:05:37.060919 LP4Y_EN = 0x0
4925 10:05:37.063919 WORK_FSP = 0x0
4926 10:05:37.064038 WL = 0x3
4927 10:05:37.067542 RL = 0x3
4928 10:05:37.067662 BL = 0x2
4929 10:05:37.070624 RPST = 0x0
4930 10:05:37.074104 RD_PRE = 0x0
4931 10:05:37.074220 WR_PRE = 0x1
4932 10:05:37.077254 WR_PST = 0x0
4933 10:05:37.077388 DBI_WR = 0x0
4934 10:05:37.080767 DBI_RD = 0x0
4935 10:05:37.080895 OTF = 0x1
4936 10:05:37.083992 ===================================
4937 10:05:37.087204 ===================================
4938 10:05:37.090366 ANA top config
4939 10:05:37.093592 ===================================
4940 10:05:37.093747 DLL_ASYNC_EN = 0
4941 10:05:37.096773 ALL_SLAVE_EN = 1
4942 10:05:37.100483 NEW_RANK_MODE = 1
4943 10:05:37.103419 DLL_IDLE_MODE = 1
4944 10:05:37.103521 LP45_APHY_COMB_EN = 1
4945 10:05:37.107235 TX_ODT_DIS = 1
4946 10:05:37.110540 NEW_8X_MODE = 1
4947 10:05:37.113863 ===================================
4948 10:05:37.117218 ===================================
4949 10:05:37.120630 data_rate = 1866
4950 10:05:37.123881 CKR = 1
4951 10:05:37.127177 DQ_P2S_RATIO = 8
4952 10:05:37.130536 ===================================
4953 10:05:37.130667 CA_P2S_RATIO = 8
4954 10:05:37.133869 DQ_CA_OPEN = 0
4955 10:05:37.137091 DQ_SEMI_OPEN = 0
4956 10:05:37.140238 CA_SEMI_OPEN = 0
4957 10:05:37.143890 CA_FULL_RATE = 0
4958 10:05:37.144011 DQ_CKDIV4_EN = 1
4959 10:05:37.147231 CA_CKDIV4_EN = 1
4960 10:05:37.150575 CA_PREDIV_EN = 0
4961 10:05:37.153779 PH8_DLY = 0
4962 10:05:37.157056 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4963 10:05:37.160267 DQ_AAMCK_DIV = 4
4964 10:05:37.160366 CA_AAMCK_DIV = 4
4965 10:05:37.163479 CA_ADMCK_DIV = 4
4966 10:05:37.166878 DQ_TRACK_CA_EN = 0
4967 10:05:37.170514 CA_PICK = 933
4968 10:05:37.173969 CA_MCKIO = 933
4969 10:05:37.177188 MCKIO_SEMI = 0
4970 10:05:37.180740 PLL_FREQ = 3732
4971 10:05:37.180870 DQ_UI_PI_RATIO = 32
4972 10:05:37.183666 CA_UI_PI_RATIO = 0
4973 10:05:37.187152 ===================================
4974 10:05:37.190907 ===================================
4975 10:05:37.193661 memory_type:LPDDR4
4976 10:05:37.196977 GP_NUM : 10
4977 10:05:37.197069 SRAM_EN : 1
4978 10:05:37.200368 MD32_EN : 0
4979 10:05:37.203396 ===================================
4980 10:05:37.203533 [ANA_INIT] >>>>>>>>>>>>>>
4981 10:05:37.207001 <<<<<< [CONFIGURE PHASE]: ANA_TX
4982 10:05:37.210593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4983 10:05:37.213886 ===================================
4984 10:05:37.217069 data_rate = 1866,PCW = 0X8f00
4985 10:05:37.220165 ===================================
4986 10:05:37.223424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4987 10:05:37.230548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 10:05:37.237042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 10:05:37.240324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4990 10:05:37.243580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4991 10:05:37.246672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4992 10:05:37.250507 [ANA_INIT] flow start
4993 10:05:37.250621 [ANA_INIT] PLL >>>>>>>>
4994 10:05:37.253800 [ANA_INIT] PLL <<<<<<<<
4995 10:05:37.257313 [ANA_INIT] MIDPI >>>>>>>>
4996 10:05:37.257420 [ANA_INIT] MIDPI <<<<<<<<
4997 10:05:37.260257 [ANA_INIT] DLL >>>>>>>>
4998 10:05:37.263557 [ANA_INIT] flow end
4999 10:05:37.266650 ============ LP4 DIFF to SE enter ============
5000 10:05:37.270205 ============ LP4 DIFF to SE exit ============
5001 10:05:37.273207 [ANA_INIT] <<<<<<<<<<<<<
5002 10:05:37.277167 [Flow] Enable top DCM control >>>>>
5003 10:05:37.280199 [Flow] Enable top DCM control <<<<<
5004 10:05:37.283415 Enable DLL master slave shuffle
5005 10:05:37.286554 ==============================================================
5006 10:05:37.289613 Gating Mode config
5007 10:05:37.296362 ==============================================================
5008 10:05:37.296501 Config description:
5009 10:05:37.306412 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5010 10:05:37.312801 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5011 10:05:37.319579 SELPH_MODE 0: By rank 1: By Phase
5012 10:05:37.323102 ==============================================================
5013 10:05:37.326309 GAT_TRACK_EN = 1
5014 10:05:37.329761 RX_GATING_MODE = 2
5015 10:05:37.333234 RX_GATING_TRACK_MODE = 2
5016 10:05:37.336496 SELPH_MODE = 1
5017 10:05:37.339734 PICG_EARLY_EN = 1
5018 10:05:37.343207 VALID_LAT_VALUE = 1
5019 10:05:37.346406 ==============================================================
5020 10:05:37.349700 Enter into Gating configuration >>>>
5021 10:05:37.352663 Exit from Gating configuration <<<<
5022 10:05:37.356269 Enter into DVFS_PRE_config >>>>>
5023 10:05:37.369556 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5024 10:05:37.372972 Exit from DVFS_PRE_config <<<<<
5025 10:05:37.373079 Enter into PICG configuration >>>>
5026 10:05:37.376232 Exit from PICG configuration <<<<
5027 10:05:37.379488 [RX_INPUT] configuration >>>>>
5028 10:05:37.382766 [RX_INPUT] configuration <<<<<
5029 10:05:37.389312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5030 10:05:37.392433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5031 10:05:37.399180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 10:05:37.405920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 10:05:37.412455 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 10:05:37.419414 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 10:05:37.422603 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5036 10:05:37.425771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5037 10:05:37.429558 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5038 10:05:37.435960 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5039 10:05:37.439308 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5040 10:05:37.442659 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 10:05:37.445619 ===================================
5042 10:05:37.449036 LPDDR4 DRAM CONFIGURATION
5043 10:05:37.452209 ===================================
5044 10:05:37.456164 EX_ROW_EN[0] = 0x0
5045 10:05:37.456311 EX_ROW_EN[1] = 0x0
5046 10:05:37.459130 LP4Y_EN = 0x0
5047 10:05:37.459242 WORK_FSP = 0x0
5048 10:05:37.462726 WL = 0x3
5049 10:05:37.462824 RL = 0x3
5050 10:05:37.465776 BL = 0x2
5051 10:05:37.465896 RPST = 0x0
5052 10:05:37.468889 RD_PRE = 0x0
5053 10:05:37.469009 WR_PRE = 0x1
5054 10:05:37.472536 WR_PST = 0x0
5055 10:05:37.472632 DBI_WR = 0x0
5056 10:05:37.475770 DBI_RD = 0x0
5057 10:05:37.475885 OTF = 0x1
5058 10:05:37.479041 ===================================
5059 10:05:37.482555 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5060 10:05:37.488736 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5061 10:05:37.491882 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 10:05:37.495507 ===================================
5063 10:05:37.499119 LPDDR4 DRAM CONFIGURATION
5064 10:05:37.502286 ===================================
5065 10:05:37.502412 EX_ROW_EN[0] = 0x10
5066 10:05:37.505448 EX_ROW_EN[1] = 0x0
5067 10:05:37.508959 LP4Y_EN = 0x0
5068 10:05:37.509050 WORK_FSP = 0x0
5069 10:05:37.512023 WL = 0x3
5070 10:05:37.512138 RL = 0x3
5071 10:05:37.515247 BL = 0x2
5072 10:05:37.515335 RPST = 0x0
5073 10:05:37.518486 RD_PRE = 0x0
5074 10:05:37.518608 WR_PRE = 0x1
5075 10:05:37.522339 WR_PST = 0x0
5076 10:05:37.522434 DBI_WR = 0x0
5077 10:05:37.525471 DBI_RD = 0x0
5078 10:05:37.525588 OTF = 0x1
5079 10:05:37.528679 ===================================
5080 10:05:37.534980 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5081 10:05:37.539493 nWR fixed to 30
5082 10:05:37.542779 [ModeRegInit_LP4] CH0 RK0
5083 10:05:37.542904 [ModeRegInit_LP4] CH0 RK1
5084 10:05:37.546436 [ModeRegInit_LP4] CH1 RK0
5085 10:05:37.549275 [ModeRegInit_LP4] CH1 RK1
5086 10:05:37.549362 match AC timing 9
5087 10:05:37.556334 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5088 10:05:37.559553 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5089 10:05:37.562647 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5090 10:05:37.569614 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5091 10:05:37.573227 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5092 10:05:37.573367 ==
5093 10:05:37.576224 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 10:05:37.579652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 10:05:37.579780 ==
5096 10:05:37.586394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 10:05:37.592690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5098 10:05:37.595930 [CA 0] Center 37 (6~68) winsize 63
5099 10:05:37.599703 [CA 1] Center 37 (7~68) winsize 62
5100 10:05:37.602765 [CA 2] Center 34 (4~65) winsize 62
5101 10:05:37.606316 [CA 3] Center 34 (3~65) winsize 63
5102 10:05:37.609189 [CA 4] Center 33 (3~64) winsize 62
5103 10:05:37.612861 [CA 5] Center 32 (2~62) winsize 61
5104 10:05:37.613000
5105 10:05:37.616462 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5106 10:05:37.616582
5107 10:05:37.619582 [CATrainingPosCal] consider 1 rank data
5108 10:05:37.622697 u2DelayCellTimex100 = 270/100 ps
5109 10:05:37.625951 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5110 10:05:37.629702 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5111 10:05:37.632809 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5112 10:05:37.635907 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5113 10:05:37.639211 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5114 10:05:37.642482 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5115 10:05:37.646411
5116 10:05:37.648970 CA PerBit enable=1, Macro0, CA PI delay=32
5117 10:05:37.649091
5118 10:05:37.652827 [CBTSetCACLKResult] CA Dly = 32
5119 10:05:37.652947 CS Dly: 5 (0~36)
5120 10:05:37.653048 ==
5121 10:05:37.655997 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 10:05:37.659663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 10:05:37.659772 ==
5124 10:05:37.666208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 10:05:37.672450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 10:05:37.676433 [CA 0] Center 37 (7~68) winsize 62
5127 10:05:37.679245 [CA 1] Center 37 (7~68) winsize 62
5128 10:05:37.682669 [CA 2] Center 34 (4~65) winsize 62
5129 10:05:37.686231 [CA 3] Center 34 (4~64) winsize 61
5130 10:05:37.688880 [CA 4] Center 32 (2~63) winsize 62
5131 10:05:37.692217 [CA 5] Center 32 (2~62) winsize 61
5132 10:05:37.692327
5133 10:05:37.695802 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 10:05:37.695916
5135 10:05:37.699141 [CATrainingPosCal] consider 2 rank data
5136 10:05:37.702607 u2DelayCellTimex100 = 270/100 ps
5137 10:05:37.705680 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5138 10:05:37.708884 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5139 10:05:37.712687 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5140 10:05:37.715624 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5141 10:05:37.722625 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5142 10:05:37.725329 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5143 10:05:37.725450
5144 10:05:37.729158 CA PerBit enable=1, Macro0, CA PI delay=32
5145 10:05:37.729275
5146 10:05:37.732487 [CBTSetCACLKResult] CA Dly = 32
5147 10:05:37.732603 CS Dly: 5 (0~37)
5148 10:05:37.732697
5149 10:05:37.735454 ----->DramcWriteLeveling(PI) begin...
5150 10:05:37.735539 ==
5151 10:05:37.738735 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 10:05:37.745744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 10:05:37.745868 ==
5154 10:05:37.748910 Write leveling (Byte 0): 34 => 34
5155 10:05:37.749020 Write leveling (Byte 1): 30 => 30
5156 10:05:37.752200 DramcWriteLeveling(PI) end<-----
5157 10:05:37.752308
5158 10:05:37.755603 ==
5159 10:05:37.758796 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 10:05:37.762072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 10:05:37.762192 ==
5162 10:05:37.765412 [Gating] SW mode calibration
5163 10:05:37.771748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 10:05:37.775222 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5165 10:05:37.781776 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5166 10:05:37.785470 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 10:05:37.788616 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 10:05:37.794900 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 10:05:37.798659 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 10:05:37.801613 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 10:05:37.808276 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5172 10:05:37.811838 0 14 28 | B1->B0 | 3232 2929 | 0 0 | (0 0) (1 0)
5173 10:05:37.815299 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5174 10:05:37.821809 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 10:05:37.825023 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 10:05:37.828487 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 10:05:37.834974 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 10:05:37.838255 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 10:05:37.841618 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5180 10:05:37.848269 0 15 28 | B1->B0 | 2c2c 3f3f | 1 0 | (0 0) (0 0)
5181 10:05:37.851444 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5182 10:05:37.855244 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 10:05:37.861476 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 10:05:37.864714 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 10:05:37.868458 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 10:05:37.871549 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 10:05:37.878525 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 10:05:37.881636 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5189 10:05:37.884887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5190 10:05:37.891693 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 10:05:37.894701 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 10:05:37.898498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 10:05:37.904769 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 10:05:37.907898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 10:05:37.911712 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 10:05:37.918346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 10:05:37.921325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 10:05:37.924731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 10:05:37.931426 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 10:05:37.935060 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 10:05:37.938171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 10:05:37.945125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 10:05:37.948073 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5204 10:05:37.951646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5205 10:05:37.955199 Total UI for P1: 0, mck2ui 16
5206 10:05:37.958094 best dqsien dly found for B0: ( 1, 2, 24)
5207 10:05:37.961602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5208 10:05:37.967856 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 10:05:37.971602 Total UI for P1: 0, mck2ui 16
5210 10:05:37.974836 best dqsien dly found for B1: ( 1, 2, 30)
5211 10:05:37.978011 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5212 10:05:37.981274 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5213 10:05:37.981386
5214 10:05:37.984400 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5215 10:05:37.987748 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5216 10:05:37.991066 [Gating] SW calibration Done
5217 10:05:37.991182 ==
5218 10:05:37.994822 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 10:05:37.997907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 10:05:37.998005 ==
5221 10:05:38.001389 RX Vref Scan: 0
5222 10:05:38.001502
5223 10:05:38.004398 RX Vref 0 -> 0, step: 1
5224 10:05:38.004512
5225 10:05:38.004614 RX Delay -80 -> 252, step: 8
5226 10:05:38.011333 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5227 10:05:38.014434 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5228 10:05:38.017512 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5229 10:05:38.020715 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5230 10:05:38.024546 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5231 10:05:38.031147 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5232 10:05:38.034386 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5233 10:05:38.037530 iDelay=208, Bit 7, Center 111 (24 ~ 199) 176
5234 10:05:38.041106 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5235 10:05:38.044233 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5236 10:05:38.047921 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5237 10:05:38.054384 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5238 10:05:38.057434 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5239 10:05:38.061048 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5240 10:05:38.064053 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5241 10:05:38.067689 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5242 10:05:38.070700 ==
5243 10:05:38.074379 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 10:05:38.077764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 10:05:38.077857 ==
5246 10:05:38.077925 DQS Delay:
5247 10:05:38.080890 DQS0 = 0, DQS1 = 0
5248 10:05:38.080971 DQM Delay:
5249 10:05:38.084031 DQM0 = 106, DQM1 = 96
5250 10:05:38.084140 DQ Delay:
5251 10:05:38.087727 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =103
5252 10:05:38.091096 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5253 10:05:38.094475 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5254 10:05:38.097426 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5255 10:05:38.097540
5256 10:05:38.097648
5257 10:05:38.097739 ==
5258 10:05:38.100617 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 10:05:38.104502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 10:05:38.107427 ==
5261 10:05:38.107546
5262 10:05:38.107644
5263 10:05:38.107737 TX Vref Scan disable
5264 10:05:38.110861 == TX Byte 0 ==
5265 10:05:38.114122 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5266 10:05:38.117625 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5267 10:05:38.120983 == TX Byte 1 ==
5268 10:05:38.123993 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5269 10:05:38.127179 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5270 10:05:38.130957 ==
5271 10:05:38.131083 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 10:05:38.137201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 10:05:38.137329 ==
5274 10:05:38.137426
5275 10:05:38.137517
5276 10:05:38.140883 TX Vref Scan disable
5277 10:05:38.140989 == TX Byte 0 ==
5278 10:05:38.147062 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5279 10:05:38.150238 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5280 10:05:38.150361 == TX Byte 1 ==
5281 10:05:38.156941 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5282 10:05:38.160668 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5283 10:05:38.160788
5284 10:05:38.160882 [DATLAT]
5285 10:05:38.163362 Freq=933, CH0 RK0
5286 10:05:38.163448
5287 10:05:38.163516 DATLAT Default: 0xd
5288 10:05:38.167004 0, 0xFFFF, sum = 0
5289 10:05:38.167095 1, 0xFFFF, sum = 0
5290 10:05:38.170115 2, 0xFFFF, sum = 0
5291 10:05:38.170238 3, 0xFFFF, sum = 0
5292 10:05:38.173674 4, 0xFFFF, sum = 0
5293 10:05:38.176672 5, 0xFFFF, sum = 0
5294 10:05:38.176788 6, 0xFFFF, sum = 0
5295 10:05:38.180346 7, 0xFFFF, sum = 0
5296 10:05:38.180461 8, 0xFFFF, sum = 0
5297 10:05:38.183421 9, 0xFFFF, sum = 0
5298 10:05:38.183530 10, 0x0, sum = 1
5299 10:05:38.186692 11, 0x0, sum = 2
5300 10:05:38.186801 12, 0x0, sum = 3
5301 10:05:38.186896 13, 0x0, sum = 4
5302 10:05:38.190375 best_step = 11
5303 10:05:38.190468
5304 10:05:38.190535 ==
5305 10:05:38.193511 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 10:05:38.196798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 10:05:38.196913 ==
5308 10:05:38.200033 RX Vref Scan: 1
5309 10:05:38.200135
5310 10:05:38.200228 RX Vref 0 -> 0, step: 1
5311 10:05:38.203903
5312 10:05:38.204011 RX Delay -45 -> 252, step: 4
5313 10:05:38.204107
5314 10:05:38.206399 Set Vref, RX VrefLevel [Byte0]: 56
5315 10:05:38.209742 [Byte1]: 49
5316 10:05:38.214734
5317 10:05:38.214859 Final RX Vref Byte 0 = 56 to rank0
5318 10:05:38.217854 Final RX Vref Byte 1 = 49 to rank0
5319 10:05:38.220792 Final RX Vref Byte 0 = 56 to rank1
5320 10:05:38.224133 Final RX Vref Byte 1 = 49 to rank1==
5321 10:05:38.227776 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 10:05:38.234448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 10:05:38.234571 ==
5324 10:05:38.234644 DQS Delay:
5325 10:05:38.234717 DQS0 = 0, DQS1 = 0
5326 10:05:38.237553 DQM Delay:
5327 10:05:38.237671 DQM0 = 104, DQM1 = 95
5328 10:05:38.241153 DQ Delay:
5329 10:05:38.244424 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5330 10:05:38.247522 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5331 10:05:38.251245 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5332 10:05:38.254290 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5333 10:05:38.254385
5334 10:05:38.254454
5335 10:05:38.261246 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5336 10:05:38.264474 CH0 RK0: MR19=505, MR18=322A
5337 10:05:38.270687 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5338 10:05:38.270860
5339 10:05:38.274340 ----->DramcWriteLeveling(PI) begin...
5340 10:05:38.274461 ==
5341 10:05:38.277245 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 10:05:38.280777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 10:05:38.284367 ==
5344 10:05:38.284494 Write leveling (Byte 0): 35 => 35
5345 10:05:38.287363 Write leveling (Byte 1): 31 => 31
5346 10:05:38.290964 DramcWriteLeveling(PI) end<-----
5347 10:05:38.291062
5348 10:05:38.291157 ==
5349 10:05:38.294035 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 10:05:38.300406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 10:05:38.300546 ==
5352 10:05:38.300645 [Gating] SW mode calibration
5353 10:05:38.310581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5354 10:05:38.313743 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5355 10:05:38.317078 0 14 0 | B1->B0 | 3131 3030 | 0 1 | (0 0) (1 1)
5356 10:05:38.324175 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 10:05:38.327316 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 10:05:38.330446 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 10:05:38.337550 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 10:05:38.340393 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 10:05:38.343812 0 14 24 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 0)
5362 10:05:38.350316 0 14 28 | B1->B0 | 2828 2c2c | 1 1 | (1 1) (1 0)
5363 10:05:38.353627 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5364 10:05:38.357287 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 10:05:38.364030 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 10:05:38.367302 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 10:05:38.370556 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 10:05:38.377322 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 10:05:38.380362 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5370 10:05:38.384045 0 15 28 | B1->B0 | 3e3e 3736 | 0 1 | (0 0) (1 1)
5371 10:05:38.390665 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 10:05:38.393777 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 10:05:38.397242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 10:05:38.404090 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 10:05:38.406874 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 10:05:38.410278 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 10:05:38.416779 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5378 10:05:38.420062 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5379 10:05:38.423901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 10:05:38.430278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 10:05:38.433475 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 10:05:38.436746 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 10:05:38.440531 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 10:05:38.447471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 10:05:38.450715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 10:05:38.453798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 10:05:38.460408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 10:05:38.463692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 10:05:38.467252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 10:05:38.473985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 10:05:38.477015 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 10:05:38.480224 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 10:05:38.486945 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 10:05:38.489899 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5395 10:05:38.493652 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 10:05:38.497041 Total UI for P1: 0, mck2ui 16
5397 10:05:38.500290 best dqsien dly found for B0: ( 1, 2, 28)
5398 10:05:38.503417 Total UI for P1: 0, mck2ui 16
5399 10:05:38.507032 best dqsien dly found for B1: ( 1, 2, 28)
5400 10:05:38.510485 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5401 10:05:38.513648 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5402 10:05:38.513741
5403 10:05:38.519847 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5404 10:05:38.523152 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5405 10:05:38.523246 [Gating] SW calibration Done
5406 10:05:38.526994 ==
5407 10:05:38.530196 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 10:05:38.533381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 10:05:38.533487 ==
5410 10:05:38.533593 RX Vref Scan: 0
5411 10:05:38.533689
5412 10:05:38.536589 RX Vref 0 -> 0, step: 1
5413 10:05:38.536672
5414 10:05:38.539791 RX Delay -80 -> 252, step: 8
5415 10:05:38.543458 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5416 10:05:38.546559 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5417 10:05:38.553555 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5418 10:05:38.556907 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5419 10:05:38.560148 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5420 10:05:38.563213 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5421 10:05:38.566411 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5422 10:05:38.570259 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5423 10:05:38.573250 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5424 10:05:38.580003 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5425 10:05:38.583018 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5426 10:05:38.586480 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5427 10:05:38.590186 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5428 10:05:38.593312 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5429 10:05:38.599728 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5430 10:05:38.602861 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5431 10:05:38.602978 ==
5432 10:05:38.606277 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 10:05:38.609631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 10:05:38.609755 ==
5435 10:05:38.612957 DQS Delay:
5436 10:05:38.613044 DQS0 = 0, DQS1 = 0
5437 10:05:38.613115 DQM Delay:
5438 10:05:38.616219 DQM0 = 105, DQM1 = 95
5439 10:05:38.616330 DQ Delay:
5440 10:05:38.619983 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =99
5441 10:05:38.623054 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5442 10:05:38.626211 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5443 10:05:38.629777 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5444 10:05:38.629867
5445 10:05:38.629938
5446 10:05:38.632932 ==
5447 10:05:38.636177 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 10:05:38.639317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 10:05:38.639402 ==
5450 10:05:38.639468
5451 10:05:38.639532
5452 10:05:38.643082 TX Vref Scan disable
5453 10:05:38.643164 == TX Byte 0 ==
5454 10:05:38.646207 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5455 10:05:38.653101 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5456 10:05:38.653234 == TX Byte 1 ==
5457 10:05:38.656204 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5458 10:05:38.663212 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5459 10:05:38.663326 ==
5460 10:05:38.666470 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 10:05:38.669483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 10:05:38.669616 ==
5463 10:05:38.669715
5464 10:05:38.669805
5465 10:05:38.672787 TX Vref Scan disable
5466 10:05:38.676072 == TX Byte 0 ==
5467 10:05:38.679701 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5468 10:05:38.682912 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5469 10:05:38.686139 == TX Byte 1 ==
5470 10:05:38.689154 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5471 10:05:38.692734 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5472 10:05:38.692834
5473 10:05:38.696022 [DATLAT]
5474 10:05:38.696113 Freq=933, CH0 RK1
5475 10:05:38.696181
5476 10:05:38.699282 DATLAT Default: 0xb
5477 10:05:38.699377 0, 0xFFFF, sum = 0
5478 10:05:38.702427 1, 0xFFFF, sum = 0
5479 10:05:38.702519 2, 0xFFFF, sum = 0
5480 10:05:38.706298 3, 0xFFFF, sum = 0
5481 10:05:38.706392 4, 0xFFFF, sum = 0
5482 10:05:38.709404 5, 0xFFFF, sum = 0
5483 10:05:38.709496 6, 0xFFFF, sum = 0
5484 10:05:38.712301 7, 0xFFFF, sum = 0
5485 10:05:38.712422 8, 0xFFFF, sum = 0
5486 10:05:38.715783 9, 0xFFFF, sum = 0
5487 10:05:38.715905 10, 0x0, sum = 1
5488 10:05:38.719172 11, 0x0, sum = 2
5489 10:05:38.719266 12, 0x0, sum = 3
5490 10:05:38.722828 13, 0x0, sum = 4
5491 10:05:38.722924 best_step = 11
5492 10:05:38.722992
5493 10:05:38.723054 ==
5494 10:05:38.725830 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 10:05:38.732192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 10:05:38.732311 ==
5497 10:05:38.732380 RX Vref Scan: 0
5498 10:05:38.732442
5499 10:05:38.735643 RX Vref 0 -> 0, step: 1
5500 10:05:38.735762
5501 10:05:38.739187 RX Delay -45 -> 252, step: 4
5502 10:05:38.742215 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5503 10:05:38.745854 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5504 10:05:38.752308 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5505 10:05:38.755520 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5506 10:05:38.758979 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5507 10:05:38.762076 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5508 10:05:38.765440 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5509 10:05:38.772542 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5510 10:05:38.775757 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5511 10:05:38.778847 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5512 10:05:38.782484 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5513 10:05:38.785588 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5514 10:05:38.788817 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5515 10:05:38.795217 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5516 10:05:38.798957 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5517 10:05:38.801885 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5518 10:05:38.802011 ==
5519 10:05:38.805758 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 10:05:38.809037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 10:05:38.809129 ==
5522 10:05:38.812035 DQS Delay:
5523 10:05:38.812126 DQS0 = 0, DQS1 = 0
5524 10:05:38.815408 DQM Delay:
5525 10:05:38.815523 DQM0 = 105, DQM1 = 93
5526 10:05:38.818578 DQ Delay:
5527 10:05:38.822459 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =102
5528 10:05:38.825533 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5529 10:05:38.828659 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =86
5530 10:05:38.832356 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5531 10:05:38.832461
5532 10:05:38.832531
5533 10:05:38.838658 [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5534 10:05:38.841866 CH0 RK1: MR19=505, MR18=2700
5535 10:05:38.849101 CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43
5536 10:05:38.852088 [RxdqsGatingPostProcess] freq 933
5537 10:05:38.855496 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5538 10:05:38.858885 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 10:05:38.861865 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 10:05:38.865277 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 10:05:38.868598 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 10:05:38.871990 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 10:05:38.875589 best DQS1 dly(2T, 0.5T) = (0, 10)
5544 10:05:38.878786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 10:05:38.881997 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5546 10:05:38.885917 Pre-setting of DQS Precalculation
5547 10:05:38.888704 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5548 10:05:38.888840 ==
5549 10:05:38.891978 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 10:05:38.899065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 10:05:38.899200 ==
5552 10:05:38.902150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 10:05:38.908539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 10:05:38.912281 [CA 0] Center 36 (6~67) winsize 62
5555 10:05:38.915488 [CA 1] Center 36 (6~67) winsize 62
5556 10:05:38.918897 [CA 2] Center 34 (4~65) winsize 62
5557 10:05:38.922078 [CA 3] Center 34 (4~65) winsize 62
5558 10:05:38.925307 [CA 4] Center 34 (4~65) winsize 62
5559 10:05:38.928417 [CA 5] Center 33 (3~64) winsize 62
5560 10:05:38.928528
5561 10:05:38.932169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 10:05:38.932279
5563 10:05:38.935325 [CATrainingPosCal] consider 1 rank data
5564 10:05:38.938562 u2DelayCellTimex100 = 270/100 ps
5565 10:05:38.941671 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 10:05:38.944790 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 10:05:38.951455 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 10:05:38.955194 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 10:05:38.958510 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 10:05:38.961425 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 10:05:38.961546
5572 10:05:38.964886 CA PerBit enable=1, Macro0, CA PI delay=33
5573 10:05:38.965005
5574 10:05:38.968484 [CBTSetCACLKResult] CA Dly = 33
5575 10:05:38.968601 CS Dly: 7 (0~38)
5576 10:05:38.971882 ==
5577 10:05:38.972007 Dram Type= 6, Freq= 0, CH_1, rank 1
5578 10:05:38.978430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 10:05:38.978545 ==
5580 10:05:38.981502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 10:05:38.987905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5582 10:05:38.991974 [CA 0] Center 36 (6~67) winsize 62
5583 10:05:38.994962 [CA 1] Center 37 (6~68) winsize 63
5584 10:05:38.998181 [CA 2] Center 35 (5~65) winsize 61
5585 10:05:39.001937 [CA 3] Center 34 (4~65) winsize 62
5586 10:05:39.005095 [CA 4] Center 34 (4~65) winsize 62
5587 10:05:39.008274 [CA 5] Center 34 (4~64) winsize 61
5588 10:05:39.008379
5589 10:05:39.011468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5590 10:05:39.011558
5591 10:05:39.014584 [CATrainingPosCal] consider 2 rank data
5592 10:05:39.018114 u2DelayCellTimex100 = 270/100 ps
5593 10:05:39.021325 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5594 10:05:39.028317 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5595 10:05:39.031510 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5596 10:05:39.034598 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5597 10:05:39.037753 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5598 10:05:39.041516 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5599 10:05:39.041625
5600 10:05:39.044779 CA PerBit enable=1, Macro0, CA PI delay=34
5601 10:05:39.044872
5602 10:05:39.047891 [CBTSetCACLKResult] CA Dly = 34
5603 10:05:39.051548 CS Dly: 8 (0~40)
5604 10:05:39.051644
5605 10:05:39.054622 ----->DramcWriteLeveling(PI) begin...
5606 10:05:39.054746 ==
5607 10:05:39.057694 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 10:05:39.061239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 10:05:39.061340 ==
5610 10:05:39.064322 Write leveling (Byte 0): 25 => 25
5611 10:05:39.067820 Write leveling (Byte 1): 26 => 26
5612 10:05:39.070883 DramcWriteLeveling(PI) end<-----
5613 10:05:39.071025
5614 10:05:39.071129 ==
5615 10:05:39.074198 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 10:05:39.077557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 10:05:39.077698 ==
5618 10:05:39.080949 [Gating] SW mode calibration
5619 10:05:39.087362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5620 10:05:39.094017 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5621 10:05:39.097168 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 10:05:39.100506 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 10:05:39.107676 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 10:05:39.110976 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 10:05:39.114186 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 10:05:39.120518 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 10:05:39.124238 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5628 10:05:39.127299 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5629 10:05:39.133809 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 10:05:39.137603 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 10:05:39.140884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 10:05:39.147438 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 10:05:39.150671 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 10:05:39.153776 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5635 10:05:39.160283 0 15 24 | B1->B0 | 2626 3636 | 0 0 | (1 1) (0 0)
5636 10:05:39.163995 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5637 10:05:39.166987 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 10:05:39.173759 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 10:05:39.176918 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 10:05:39.180535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 10:05:39.187321 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 10:05:39.190395 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 10:05:39.193743 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5644 10:05:39.200420 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5645 10:05:39.203863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 10:05:39.206737 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 10:05:39.210295 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 10:05:39.216620 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 10:05:39.220194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 10:05:39.223694 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 10:05:39.230339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 10:05:39.233446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 10:05:39.236646 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 10:05:39.243653 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 10:05:39.246895 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 10:05:39.250036 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 10:05:39.256520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 10:05:39.259776 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 10:05:39.263559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5660 10:05:39.270242 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 10:05:39.273671 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 10:05:39.276722 Total UI for P1: 0, mck2ui 16
5663 10:05:39.280003 best dqsien dly found for B0: ( 1, 2, 26)
5664 10:05:39.283307 Total UI for P1: 0, mck2ui 16
5665 10:05:39.286881 best dqsien dly found for B1: ( 1, 2, 26)
5666 10:05:39.289887 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5667 10:05:39.293667 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5668 10:05:39.293791
5669 10:05:39.296813 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5670 10:05:39.300017 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5671 10:05:39.303127 [Gating] SW calibration Done
5672 10:05:39.303219 ==
5673 10:05:39.306810 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 10:05:39.310272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 10:05:39.313552 ==
5676 10:05:39.313668 RX Vref Scan: 0
5677 10:05:39.313739
5678 10:05:39.316397 RX Vref 0 -> 0, step: 1
5679 10:05:39.316512
5680 10:05:39.316590 RX Delay -80 -> 252, step: 8
5681 10:05:39.323592 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5682 10:05:39.326875 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5683 10:05:39.330190 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5684 10:05:39.333590 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5685 10:05:39.337013 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5686 10:05:39.340332 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5687 10:05:39.347061 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5688 10:05:39.350218 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5689 10:05:39.353489 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5690 10:05:39.356681 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5691 10:05:39.359937 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5692 10:05:39.363745 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5693 10:05:39.370100 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5694 10:05:39.373172 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5695 10:05:39.376590 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5696 10:05:39.379934 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5697 10:05:39.380040 ==
5698 10:05:39.383293 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 10:05:39.389689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 10:05:39.389804 ==
5701 10:05:39.389873 DQS Delay:
5702 10:05:39.393481 DQS0 = 0, DQS1 = 0
5703 10:05:39.393571 DQM Delay:
5704 10:05:39.393652 DQM0 = 103, DQM1 = 98
5705 10:05:39.397064 DQ Delay:
5706 10:05:39.400003 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5707 10:05:39.403234 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =107
5708 10:05:39.406329 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5709 10:05:39.410127 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5710 10:05:39.410231
5711 10:05:39.410300
5712 10:05:39.410362 ==
5713 10:05:39.412878 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 10:05:39.416378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 10:05:39.416477 ==
5716 10:05:39.416569
5717 10:05:39.420007
5718 10:05:39.420101 TX Vref Scan disable
5719 10:05:39.423086 == TX Byte 0 ==
5720 10:05:39.426572 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 10:05:39.429531 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 10:05:39.433328 == TX Byte 1 ==
5723 10:05:39.436449 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5724 10:05:39.439999 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5725 10:05:39.440105 ==
5726 10:05:39.443008 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 10:05:39.449347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 10:05:39.449466 ==
5729 10:05:39.449572
5730 10:05:39.449686
5731 10:05:39.449788 TX Vref Scan disable
5732 10:05:39.453751 == TX Byte 0 ==
5733 10:05:39.456861 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5734 10:05:39.463562 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5735 10:05:39.463687 == TX Byte 1 ==
5736 10:05:39.466841 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5737 10:05:39.473268 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5738 10:05:39.473420
5739 10:05:39.473527 [DATLAT]
5740 10:05:39.473630 Freq=933, CH1 RK0
5741 10:05:39.473715
5742 10:05:39.476456 DATLAT Default: 0xd
5743 10:05:39.476561 0, 0xFFFF, sum = 0
5744 10:05:39.480210 1, 0xFFFF, sum = 0
5745 10:05:39.480335 2, 0xFFFF, sum = 0
5746 10:05:39.483398 3, 0xFFFF, sum = 0
5747 10:05:39.486651 4, 0xFFFF, sum = 0
5748 10:05:39.486777 5, 0xFFFF, sum = 0
5749 10:05:39.490145 6, 0xFFFF, sum = 0
5750 10:05:39.490243 7, 0xFFFF, sum = 0
5751 10:05:39.493555 8, 0xFFFF, sum = 0
5752 10:05:39.493680 9, 0xFFFF, sum = 0
5753 10:05:39.497099 10, 0x0, sum = 1
5754 10:05:39.497236 11, 0x0, sum = 2
5755 10:05:39.500359 12, 0x0, sum = 3
5756 10:05:39.500488 13, 0x0, sum = 4
5757 10:05:39.500602 best_step = 11
5758 10:05:39.500708
5759 10:05:39.503372 ==
5760 10:05:39.503470 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 10:05:39.509863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 10:05:39.510004 ==
5763 10:05:39.510079 RX Vref Scan: 1
5764 10:05:39.510143
5765 10:05:39.513139 RX Vref 0 -> 0, step: 1
5766 10:05:39.513227
5767 10:05:39.516441 RX Delay -45 -> 252, step: 4
5768 10:05:39.516551
5769 10:05:39.520359 Set Vref, RX VrefLevel [Byte0]: 53
5770 10:05:39.523284 [Byte1]: 47
5771 10:05:39.523370
5772 10:05:39.526459 Final RX Vref Byte 0 = 53 to rank0
5773 10:05:39.530259 Final RX Vref Byte 1 = 47 to rank0
5774 10:05:39.533222 Final RX Vref Byte 0 = 53 to rank1
5775 10:05:39.536717 Final RX Vref Byte 1 = 47 to rank1==
5776 10:05:39.539994 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 10:05:39.543458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 10:05:39.543554 ==
5779 10:05:39.546447 DQS Delay:
5780 10:05:39.546535 DQS0 = 0, DQS1 = 0
5781 10:05:39.550264 DQM Delay:
5782 10:05:39.550350 DQM0 = 103, DQM1 = 98
5783 10:05:39.550416 DQ Delay:
5784 10:05:39.553097 DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =98
5785 10:05:39.556476 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5786 10:05:39.560343 DQ8 =84, DQ9 =88, DQ10 =100, DQ11 =96
5787 10:05:39.566884 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =108
5788 10:05:39.567007
5789 10:05:39.567077
5790 10:05:39.573545 [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5791 10:05:39.576785 CH1 RK0: MR19=505, MR18=182F
5792 10:05:39.583208 CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43
5793 10:05:39.583318
5794 10:05:39.586668 ----->DramcWriteLeveling(PI) begin...
5795 10:05:39.586764 ==
5796 10:05:39.590326 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 10:05:39.592988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 10:05:39.593074 ==
5799 10:05:39.596630 Write leveling (Byte 0): 29 => 29
5800 10:05:39.600508 Write leveling (Byte 1): 29 => 29
5801 10:05:39.603163 DramcWriteLeveling(PI) end<-----
5802 10:05:39.603264
5803 10:05:39.603356 ==
5804 10:05:39.606529 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 10:05:39.609899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 10:05:39.609997 ==
5807 10:05:39.612972 [Gating] SW mode calibration
5808 10:05:39.620082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 10:05:39.626929 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 10:05:39.630016 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 10:05:39.633099 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 10:05:39.640144 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 10:05:39.643121 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 10:05:39.646682 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 10:05:39.652933 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 10:05:39.656407 0 14 24 | B1->B0 | 2d2d 3030 | 0 0 | (0 1) (0 0)
5817 10:05:39.659957 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
5818 10:05:39.666282 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 10:05:39.669394 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 10:05:39.673151 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 10:05:39.679504 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 10:05:39.683206 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 10:05:39.686490 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5824 10:05:39.692717 0 15 24 | B1->B0 | 3535 2727 | 0 0 | (0 0) (0 0)
5825 10:05:39.696061 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5826 10:05:39.699853 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 10:05:39.706282 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 10:05:39.709406 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 10:05:39.713219 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 10:05:39.719450 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 10:05:39.723070 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 10:05:39.726096 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5833 10:05:39.732946 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5834 10:05:39.736033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 10:05:39.739278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 10:05:39.746372 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 10:05:39.749342 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 10:05:39.752572 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 10:05:39.759365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 10:05:39.762468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 10:05:39.765861 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 10:05:39.772930 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 10:05:39.776181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 10:05:39.779374 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 10:05:39.782415 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 10:05:39.789250 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 10:05:39.792311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 10:05:39.795767 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5849 10:05:39.802308 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5850 10:05:39.806190 Total UI for P1: 0, mck2ui 16
5851 10:05:39.809114 best dqsien dly found for B1: ( 1, 2, 24)
5852 10:05:39.812217 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 10:05:39.816047 Total UI for P1: 0, mck2ui 16
5854 10:05:39.819135 best dqsien dly found for B0: ( 1, 2, 26)
5855 10:05:39.822634 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5856 10:05:39.825534 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5857 10:05:39.825682
5858 10:05:39.829118 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5859 10:05:39.832633 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5860 10:05:39.835514 [Gating] SW calibration Done
5861 10:05:39.835617 ==
5862 10:05:39.839094 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 10:05:39.846019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 10:05:39.846144 ==
5865 10:05:39.846241 RX Vref Scan: 0
5866 10:05:39.846324
5867 10:05:39.849149 RX Vref 0 -> 0, step: 1
5868 10:05:39.849263
5869 10:05:39.852354 RX Delay -80 -> 252, step: 8
5870 10:05:39.855435 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5871 10:05:39.859240 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5872 10:05:39.862568 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5873 10:05:39.865477 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5874 10:05:39.872352 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5875 10:05:39.875224 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5876 10:05:39.878792 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5877 10:05:39.882106 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5878 10:05:39.885431 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5879 10:05:39.888509 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5880 10:05:39.892241 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5881 10:05:39.898524 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5882 10:05:39.901759 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5883 10:05:39.905377 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5884 10:05:39.908684 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5885 10:05:39.915647 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5886 10:05:39.915779 ==
5887 10:05:39.918779 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 10:05:39.922049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 10:05:39.922149 ==
5890 10:05:39.922218 DQS Delay:
5891 10:05:39.925197 DQS0 = 0, DQS1 = 0
5892 10:05:39.925357 DQM Delay:
5893 10:05:39.928869 DQM0 = 102, DQM1 = 97
5894 10:05:39.928966 DQ Delay:
5895 10:05:39.931683 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5896 10:05:39.935198 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5897 10:05:39.938318 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5898 10:05:39.941819 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5899 10:05:39.941921
5900 10:05:39.942011
5901 10:05:39.942093 ==
5902 10:05:39.944932 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 10:05:39.948722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 10:05:39.951697 ==
5905 10:05:39.951797
5906 10:05:39.951887
5907 10:05:39.951970 TX Vref Scan disable
5908 10:05:39.954740 == TX Byte 0 ==
5909 10:05:39.958530 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5910 10:05:39.961653 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5911 10:05:39.965053 == TX Byte 1 ==
5912 10:05:39.968162 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 10:05:39.971752 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 10:05:39.974878 ==
5915 10:05:39.975046 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 10:05:39.981745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 10:05:39.981879 ==
5918 10:05:39.981992
5919 10:05:39.982053
5920 10:05:39.985248 TX Vref Scan disable
5921 10:05:39.985372 == TX Byte 0 ==
5922 10:05:39.991547 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5923 10:05:39.994998 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5924 10:05:39.995106 == TX Byte 1 ==
5925 10:05:40.001518 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5926 10:05:40.004673 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5927 10:05:40.004776
5928 10:05:40.004843 [DATLAT]
5929 10:05:40.008679 Freq=933, CH1 RK1
5930 10:05:40.008769
5931 10:05:40.008835 DATLAT Default: 0xb
5932 10:05:40.011664 0, 0xFFFF, sum = 0
5933 10:05:40.011753 1, 0xFFFF, sum = 0
5934 10:05:40.014926 2, 0xFFFF, sum = 0
5935 10:05:40.015017 3, 0xFFFF, sum = 0
5936 10:05:40.017961 4, 0xFFFF, sum = 0
5937 10:05:40.018049 5, 0xFFFF, sum = 0
5938 10:05:40.021542 6, 0xFFFF, sum = 0
5939 10:05:40.021670 7, 0xFFFF, sum = 0
5940 10:05:40.024769 8, 0xFFFF, sum = 0
5941 10:05:40.024857 9, 0xFFFF, sum = 0
5942 10:05:40.028862 10, 0x0, sum = 1
5943 10:05:40.028956 11, 0x0, sum = 2
5944 10:05:40.031618 12, 0x0, sum = 3
5945 10:05:40.031706 13, 0x0, sum = 4
5946 10:05:40.034911 best_step = 11
5947 10:05:40.035002
5948 10:05:40.035090 ==
5949 10:05:40.037937 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 10:05:40.041446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 10:05:40.041555 ==
5952 10:05:40.044473 RX Vref Scan: 0
5953 10:05:40.044567
5954 10:05:40.044642 RX Vref 0 -> 0, step: 1
5955 10:05:40.044705
5956 10:05:40.048116 RX Delay -45 -> 252, step: 4
5957 10:05:40.055069 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5958 10:05:40.058312 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5959 10:05:40.061882 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5960 10:05:40.065014 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5961 10:05:40.068212 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5962 10:05:40.075304 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5963 10:05:40.078538 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5964 10:05:40.081698 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5965 10:05:40.084869 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5966 10:05:40.088586 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5967 10:05:40.091609 iDelay=203, Bit 10, Center 100 (19 ~ 182) 164
5968 10:05:40.098420 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5969 10:05:40.102210 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5970 10:05:40.105083 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5971 10:05:40.108222 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5972 10:05:40.114723 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5973 10:05:40.114846 ==
5974 10:05:40.118513 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 10:05:40.121601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 10:05:40.121710 ==
5977 10:05:40.121777 DQS Delay:
5978 10:05:40.124820 DQS0 = 0, DQS1 = 0
5979 10:05:40.124908 DQM Delay:
5980 10:05:40.128589 DQM0 = 104, DQM1 = 99
5981 10:05:40.128697 DQ Delay:
5982 10:05:40.131543 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5983 10:05:40.134654 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5984 10:05:40.138371 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =92
5985 10:05:40.141315 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =108
5986 10:05:40.141412
5987 10:05:40.141478
5988 10:05:40.151416 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5989 10:05:40.151553 CH1 RK1: MR19=505, MR18=2E01
5990 10:05:40.158640 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5991 10:05:40.161554 [RxdqsGatingPostProcess] freq 933
5992 10:05:40.167938 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5993 10:05:40.171367 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 10:05:40.174443 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 10:05:40.178047 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 10:05:40.181266 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 10:05:40.184551 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 10:05:40.184641 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 10:05:40.187803 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 10:05:40.191601 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 10:05:40.194583 Pre-setting of DQS Precalculation
6002 10:05:40.201433 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6003 10:05:40.208162 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6004 10:05:40.214530 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6005 10:05:40.214664
6006 10:05:40.214735
6007 10:05:40.218004 [Calibration Summary] 1866 Mbps
6008 10:05:40.220926 CH 0, Rank 0
6009 10:05:40.221016 SW Impedance : PASS
6010 10:05:40.224801 DUTY Scan : NO K
6011 10:05:40.224892 ZQ Calibration : PASS
6012 10:05:40.227924 Jitter Meter : NO K
6013 10:05:40.230967 CBT Training : PASS
6014 10:05:40.231058 Write leveling : PASS
6015 10:05:40.234971 RX DQS gating : PASS
6016 10:05:40.238038 RX DQ/DQS(RDDQC) : PASS
6017 10:05:40.238130 TX DQ/DQS : PASS
6018 10:05:40.241064 RX DATLAT : PASS
6019 10:05:40.244926 RX DQ/DQS(Engine): PASS
6020 10:05:40.245027 TX OE : NO K
6021 10:05:40.247576 All Pass.
6022 10:05:40.247663
6023 10:05:40.247728 CH 0, Rank 1
6024 10:05:40.251556 SW Impedance : PASS
6025 10:05:40.251648 DUTY Scan : NO K
6026 10:05:40.254696 ZQ Calibration : PASS
6027 10:05:40.257900 Jitter Meter : NO K
6028 10:05:40.257993 CBT Training : PASS
6029 10:05:40.261126 Write leveling : PASS
6030 10:05:40.264601 RX DQS gating : PASS
6031 10:05:40.264697 RX DQ/DQS(RDDQC) : PASS
6032 10:05:40.267800 TX DQ/DQS : PASS
6033 10:05:40.267893 RX DATLAT : PASS
6034 10:05:40.271221 RX DQ/DQS(Engine): PASS
6035 10:05:40.274431 TX OE : NO K
6036 10:05:40.274531 All Pass.
6037 10:05:40.274598
6038 10:05:40.274659 CH 1, Rank 0
6039 10:05:40.277785 SW Impedance : PASS
6040 10:05:40.280987 DUTY Scan : NO K
6041 10:05:40.281080 ZQ Calibration : PASS
6042 10:05:40.284559 Jitter Meter : NO K
6043 10:05:40.287711 CBT Training : PASS
6044 10:05:40.287805 Write leveling : PASS
6045 10:05:40.290849 RX DQS gating : PASS
6046 10:05:40.294178 RX DQ/DQS(RDDQC) : PASS
6047 10:05:40.294273 TX DQ/DQS : PASS
6048 10:05:40.297556 RX DATLAT : PASS
6049 10:05:40.300848 RX DQ/DQS(Engine): PASS
6050 10:05:40.300943 TX OE : NO K
6051 10:05:40.304025 All Pass.
6052 10:05:40.304112
6053 10:05:40.304179 CH 1, Rank 1
6054 10:05:40.307744 SW Impedance : PASS
6055 10:05:40.307832 DUTY Scan : NO K
6056 10:05:40.310692 ZQ Calibration : PASS
6057 10:05:40.314494 Jitter Meter : NO K
6058 10:05:40.314588 CBT Training : PASS
6059 10:05:40.317504 Write leveling : PASS
6060 10:05:40.320918 RX DQS gating : PASS
6061 10:05:40.321013 RX DQ/DQS(RDDQC) : PASS
6062 10:05:40.324079 TX DQ/DQS : PASS
6063 10:05:40.324176 RX DATLAT : PASS
6064 10:05:40.327322 RX DQ/DQS(Engine): PASS
6065 10:05:40.330941 TX OE : NO K
6066 10:05:40.331035 All Pass.
6067 10:05:40.331103
6068 10:05:40.334138 DramC Write-DBI off
6069 10:05:40.334226 PER_BANK_REFRESH: Hybrid Mode
6070 10:05:40.337361 TX_TRACKING: ON
6071 10:05:40.347461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6072 10:05:40.350784 [FAST_K] Save calibration result to emmc
6073 10:05:40.353931 dramc_set_vcore_voltage set vcore to 650000
6074 10:05:40.354033 Read voltage for 400, 6
6075 10:05:40.357374 Vio18 = 0
6076 10:05:40.357462 Vcore = 650000
6077 10:05:40.357528 Vdram = 0
6078 10:05:40.360416 Vddq = 0
6079 10:05:40.360501 Vmddr = 0
6080 10:05:40.367462 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6081 10:05:40.370498 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6082 10:05:40.373543 MEM_TYPE=3, freq_sel=20
6083 10:05:40.377403 sv_algorithm_assistance_LP4_800
6084 10:05:40.380520 ============ PULL DRAM RESETB DOWN ============
6085 10:05:40.384052 ========== PULL DRAM RESETB DOWN end =========
6086 10:05:40.390582 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6087 10:05:40.393524 ===================================
6088 10:05:40.393675 LPDDR4 DRAM CONFIGURATION
6089 10:05:40.397094 ===================================
6090 10:05:40.400621 EX_ROW_EN[0] = 0x0
6091 10:05:40.403296 EX_ROW_EN[1] = 0x0
6092 10:05:40.403390 LP4Y_EN = 0x0
6093 10:05:40.406700 WORK_FSP = 0x0
6094 10:05:40.406789 WL = 0x2
6095 10:05:40.410038 RL = 0x2
6096 10:05:40.410127 BL = 0x2
6097 10:05:40.413822 RPST = 0x0
6098 10:05:40.413914 RD_PRE = 0x0
6099 10:05:40.417074 WR_PRE = 0x1
6100 10:05:40.417191 WR_PST = 0x0
6101 10:05:40.420203 DBI_WR = 0x0
6102 10:05:40.420319 DBI_RD = 0x0
6103 10:05:40.423298 OTF = 0x1
6104 10:05:40.426998 ===================================
6105 10:05:40.430076 ===================================
6106 10:05:40.430197 ANA top config
6107 10:05:40.433785 ===================================
6108 10:05:40.436971 DLL_ASYNC_EN = 0
6109 10:05:40.440268 ALL_SLAVE_EN = 1
6110 10:05:40.440360 NEW_RANK_MODE = 1
6111 10:05:40.443378 DLL_IDLE_MODE = 1
6112 10:05:40.446584 LP45_APHY_COMB_EN = 1
6113 10:05:40.450338 TX_ODT_DIS = 1
6114 10:05:40.453452 NEW_8X_MODE = 1
6115 10:05:40.456671 ===================================
6116 10:05:40.459901 ===================================
6117 10:05:40.459992 data_rate = 800
6118 10:05:40.463169 CKR = 1
6119 10:05:40.466478 DQ_P2S_RATIO = 4
6120 10:05:40.470244 ===================================
6121 10:05:40.473454 CA_P2S_RATIO = 4
6122 10:05:40.476463 DQ_CA_OPEN = 0
6123 10:05:40.480170 DQ_SEMI_OPEN = 1
6124 10:05:40.480272 CA_SEMI_OPEN = 1
6125 10:05:40.483283 CA_FULL_RATE = 0
6126 10:05:40.486418 DQ_CKDIV4_EN = 0
6127 10:05:40.490041 CA_CKDIV4_EN = 1
6128 10:05:40.493302 CA_PREDIV_EN = 0
6129 10:05:40.496940 PH8_DLY = 0
6130 10:05:40.497045 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6131 10:05:40.499945 DQ_AAMCK_DIV = 0
6132 10:05:40.503104 CA_AAMCK_DIV = 0
6133 10:05:40.506907 CA_ADMCK_DIV = 4
6134 10:05:40.510035 DQ_TRACK_CA_EN = 0
6135 10:05:40.513350 CA_PICK = 800
6136 10:05:40.513448 CA_MCKIO = 400
6137 10:05:40.516659 MCKIO_SEMI = 400
6138 10:05:40.519956 PLL_FREQ = 3016
6139 10:05:40.523258 DQ_UI_PI_RATIO = 32
6140 10:05:40.526715 CA_UI_PI_RATIO = 32
6141 10:05:40.530083 ===================================
6142 10:05:40.533392 ===================================
6143 10:05:40.536529 memory_type:LPDDR4
6144 10:05:40.536627 GP_NUM : 10
6145 10:05:40.539712 SRAM_EN : 1
6146 10:05:40.543430 MD32_EN : 0
6147 10:05:40.546264 ===================================
6148 10:05:40.546360 [ANA_INIT] >>>>>>>>>>>>>>
6149 10:05:40.549699 <<<<<< [CONFIGURE PHASE]: ANA_TX
6150 10:05:40.552855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6151 10:05:40.556482 ===================================
6152 10:05:40.559588 data_rate = 800,PCW = 0X7400
6153 10:05:40.563496 ===================================
6154 10:05:40.566579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6155 10:05:40.572910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 10:05:40.583117 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 10:05:40.586166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6158 10:05:40.589409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6159 10:05:40.596403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6160 10:05:40.596532 [ANA_INIT] flow start
6161 10:05:40.599549 [ANA_INIT] PLL >>>>>>>>
6162 10:05:40.602766 [ANA_INIT] PLL <<<<<<<<
6163 10:05:40.602864 [ANA_INIT] MIDPI >>>>>>>>
6164 10:05:40.606368 [ANA_INIT] MIDPI <<<<<<<<
6165 10:05:40.609443 [ANA_INIT] DLL >>>>>>>>
6166 10:05:40.609538 [ANA_INIT] flow end
6167 10:05:40.612550 ============ LP4 DIFF to SE enter ============
6168 10:05:40.619727 ============ LP4 DIFF to SE exit ============
6169 10:05:40.619846 [ANA_INIT] <<<<<<<<<<<<<
6170 10:05:40.622252 [Flow] Enable top DCM control >>>>>
6171 10:05:40.626077 [Flow] Enable top DCM control <<<<<
6172 10:05:40.629151 Enable DLL master slave shuffle
6173 10:05:40.635649 ==============================================================
6174 10:05:40.635773 Gating Mode config
6175 10:05:40.642909 ==============================================================
6176 10:05:40.646125 Config description:
6177 10:05:40.655844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6178 10:05:40.662297 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6179 10:05:40.665462 SELPH_MODE 0: By rank 1: By Phase
6180 10:05:40.672553 ==============================================================
6181 10:05:40.675550 GAT_TRACK_EN = 0
6182 10:05:40.679204 RX_GATING_MODE = 2
6183 10:05:40.679315 RX_GATING_TRACK_MODE = 2
6184 10:05:40.682247 SELPH_MODE = 1
6185 10:05:40.685914 PICG_EARLY_EN = 1
6186 10:05:40.689112 VALID_LAT_VALUE = 1
6187 10:05:40.695715 ==============================================================
6188 10:05:40.698839 Enter into Gating configuration >>>>
6189 10:05:40.702449 Exit from Gating configuration <<<<
6190 10:05:40.705257 Enter into DVFS_PRE_config >>>>>
6191 10:05:40.715232 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6192 10:05:40.719061 Exit from DVFS_PRE_config <<<<<
6193 10:05:40.722309 Enter into PICG configuration >>>>
6194 10:05:40.725554 Exit from PICG configuration <<<<
6195 10:05:40.728898 [RX_INPUT] configuration >>>>>
6196 10:05:40.732023 [RX_INPUT] configuration <<<<<
6197 10:05:40.735233 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6198 10:05:40.741974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6199 10:05:40.748890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 10:05:40.755385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 10:05:40.758506 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 10:05:40.764987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 10:05:40.768359 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6204 10:05:40.774824 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6205 10:05:40.778283 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6206 10:05:40.781822 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6207 10:05:40.784943 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6208 10:05:40.791826 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 10:05:40.795147 ===================================
6210 10:05:40.797983 LPDDR4 DRAM CONFIGURATION
6211 10:05:40.801740 ===================================
6212 10:05:40.801840 EX_ROW_EN[0] = 0x0
6213 10:05:40.804974 EX_ROW_EN[1] = 0x0
6214 10:05:40.805079 LP4Y_EN = 0x0
6215 10:05:40.808350 WORK_FSP = 0x0
6216 10:05:40.808440 WL = 0x2
6217 10:05:40.811726 RL = 0x2
6218 10:05:40.811817 BL = 0x2
6219 10:05:40.814857 RPST = 0x0
6220 10:05:40.814967 RD_PRE = 0x0
6221 10:05:40.818350 WR_PRE = 0x1
6222 10:05:40.818458 WR_PST = 0x0
6223 10:05:40.821295 DBI_WR = 0x0
6224 10:05:40.821387 DBI_RD = 0x0
6225 10:05:40.825037 OTF = 0x1
6226 10:05:40.828284 ===================================
6227 10:05:40.831406 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6228 10:05:40.834659 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6229 10:05:40.841376 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 10:05:40.844861 ===================================
6231 10:05:40.845011 LPDDR4 DRAM CONFIGURATION
6232 10:05:40.847920 ===================================
6233 10:05:40.851679 EX_ROW_EN[0] = 0x10
6234 10:05:40.854836 EX_ROW_EN[1] = 0x0
6235 10:05:40.854943 LP4Y_EN = 0x0
6236 10:05:40.858043 WORK_FSP = 0x0
6237 10:05:40.858134 WL = 0x2
6238 10:05:40.861465 RL = 0x2
6239 10:05:40.861558 BL = 0x2
6240 10:05:40.864452 RPST = 0x0
6241 10:05:40.864545 RD_PRE = 0x0
6242 10:05:40.867770 WR_PRE = 0x1
6243 10:05:40.867870 WR_PST = 0x0
6244 10:05:40.872068 DBI_WR = 0x0
6245 10:05:40.872170 DBI_RD = 0x0
6246 10:05:40.874651 OTF = 0x1
6247 10:05:40.877773 ===================================
6248 10:05:40.884304 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6249 10:05:40.888078 nWR fixed to 30
6250 10:05:40.891373 [ModeRegInit_LP4] CH0 RK0
6251 10:05:40.891476 [ModeRegInit_LP4] CH0 RK1
6252 10:05:40.894368 [ModeRegInit_LP4] CH1 RK0
6253 10:05:40.898285 [ModeRegInit_LP4] CH1 RK1
6254 10:05:40.898386 match AC timing 19
6255 10:05:40.904557 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6256 10:05:40.907836 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6257 10:05:40.911355 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6258 10:05:40.917798 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6259 10:05:40.920937 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6260 10:05:40.921048 ==
6261 10:05:40.924545 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 10:05:40.927897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 10:05:40.928000 ==
6264 10:05:40.934374 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 10:05:40.941253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6266 10:05:40.944544 [CA 0] Center 36 (8~64) winsize 57
6267 10:05:40.947548 [CA 1] Center 36 (8~64) winsize 57
6268 10:05:40.947655 [CA 2] Center 36 (8~64) winsize 57
6269 10:05:40.951146 [CA 3] Center 36 (8~64) winsize 57
6270 10:05:40.954083 [CA 4] Center 36 (8~64) winsize 57
6271 10:05:40.957815 [CA 5] Center 36 (8~64) winsize 57
6272 10:05:40.957922
6273 10:05:40.960994 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6274 10:05:40.961084
6275 10:05:40.967439 [CATrainingPosCal] consider 1 rank data
6276 10:05:40.967546 u2DelayCellTimex100 = 270/100 ps
6277 10:05:40.971244 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 10:05:40.977715 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 10:05:40.980911 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 10:05:40.984045 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 10:05:40.987767 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 10:05:40.990971 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 10:05:40.991071
6284 10:05:40.994075 CA PerBit enable=1, Macro0, CA PI delay=36
6285 10:05:40.994166
6286 10:05:40.998152 [CBTSetCACLKResult] CA Dly = 36
6287 10:05:40.998248 CS Dly: 1 (0~32)
6288 10:05:41.000955 ==
6289 10:05:41.004190 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 10:05:41.007422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 10:05:41.007541 ==
6292 10:05:41.014318 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 10:05:41.017453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6294 10:05:41.020602 [CA 0] Center 36 (8~64) winsize 57
6295 10:05:41.024478 [CA 1] Center 36 (8~64) winsize 57
6296 10:05:41.027469 [CA 2] Center 36 (8~64) winsize 57
6297 10:05:41.031126 [CA 3] Center 36 (8~64) winsize 57
6298 10:05:41.033977 [CA 4] Center 36 (8~64) winsize 57
6299 10:05:41.037448 [CA 5] Center 36 (8~64) winsize 57
6300 10:05:41.037549
6301 10:05:41.041015 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6302 10:05:41.041133
6303 10:05:41.043986 [CATrainingPosCal] consider 2 rank data
6304 10:05:41.047380 u2DelayCellTimex100 = 270/100 ps
6305 10:05:41.050638 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 10:05:41.053890 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 10:05:41.057067 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 10:05:41.060605 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 10:05:41.067113 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 10:05:41.070537 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 10:05:41.070634
6312 10:05:41.073790 CA PerBit enable=1, Macro0, CA PI delay=36
6313 10:05:41.073883
6314 10:05:41.077353 [CBTSetCACLKResult] CA Dly = 36
6315 10:05:41.077517 CS Dly: 1 (0~32)
6316 10:05:41.077636
6317 10:05:41.080280 ----->DramcWriteLeveling(PI) begin...
6318 10:05:41.080373 ==
6319 10:05:41.083582 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 10:05:41.091007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 10:05:41.091154 ==
6322 10:05:41.093843 Write leveling (Byte 0): 40 => 8
6323 10:05:41.096940 Write leveling (Byte 1): 40 => 8
6324 10:05:41.097037 DramcWriteLeveling(PI) end<-----
6325 10:05:41.097103
6326 10:05:41.100218 ==
6327 10:05:41.103931 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 10:05:41.107100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 10:05:41.107199 ==
6330 10:05:41.110250 [Gating] SW mode calibration
6331 10:05:41.116660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6332 10:05:41.120451 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6333 10:05:41.126727 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 10:05:41.129940 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 10:05:41.133495 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 10:05:41.139687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 10:05:41.143407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 10:05:41.146434 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 10:05:41.153267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 10:05:41.156340 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 10:05:41.160039 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 10:05:41.163161 Total UI for P1: 0, mck2ui 16
6343 10:05:41.166221 best dqsien dly found for B0: ( 0, 14, 24)
6344 10:05:41.169748 Total UI for P1: 0, mck2ui 16
6345 10:05:41.173109 best dqsien dly found for B1: ( 0, 14, 24)
6346 10:05:41.176431 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6347 10:05:41.179643 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6348 10:05:41.179744
6349 10:05:41.186172 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 10:05:41.189403 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 10:05:41.192985 [Gating] SW calibration Done
6352 10:05:41.193117 ==
6353 10:05:41.196135 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 10:05:41.199521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 10:05:41.199797 ==
6356 10:05:41.199966 RX Vref Scan: 0
6357 10:05:41.200107
6358 10:05:41.202662 RX Vref 0 -> 0, step: 1
6359 10:05:41.202801
6360 10:05:41.205679 RX Delay -410 -> 252, step: 16
6361 10:05:41.209493 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6362 10:05:41.216014 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6363 10:05:41.219132 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6364 10:05:41.223067 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6365 10:05:41.226041 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6366 10:05:41.232336 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6367 10:05:41.236042 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6368 10:05:41.239243 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6369 10:05:41.242350 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6370 10:05:41.249215 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6371 10:05:41.252991 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6372 10:05:41.256116 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6373 10:05:41.259245 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6374 10:05:41.265930 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6375 10:05:41.269137 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6376 10:05:41.272883 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6377 10:05:41.272988 ==
6378 10:05:41.275877 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 10:05:41.279073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 10:05:41.282260 ==
6381 10:05:41.282357 DQS Delay:
6382 10:05:41.282424 DQS0 = 27, DQS1 = 35
6383 10:05:41.286138 DQM Delay:
6384 10:05:41.286228 DQM0 = 10, DQM1 = 11
6385 10:05:41.289335 DQ Delay:
6386 10:05:41.289422 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6387 10:05:41.292547 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6388 10:05:41.295808 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6389 10:05:41.299006 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6390 10:05:41.299098
6391 10:05:41.299166
6392 10:05:41.299227 ==
6393 10:05:41.302685 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:05:41.308994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:05:41.309105 ==
6396 10:05:41.309173
6397 10:05:41.309234
6398 10:05:41.309293 TX Vref Scan disable
6399 10:05:41.312274 == TX Byte 0 ==
6400 10:05:41.315707 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 10:05:41.319697 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 10:05:41.322859 == TX Byte 1 ==
6403 10:05:41.325792 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 10:05:41.328838 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 10:05:41.332615 ==
6406 10:05:41.332709 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 10:05:41.339358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 10:05:41.339471 ==
6409 10:05:41.339540
6410 10:05:41.339601
6411 10:05:41.342138 TX Vref Scan disable
6412 10:05:41.342226 == TX Byte 0 ==
6413 10:05:41.345616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 10:05:41.352392 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 10:05:41.352522 == TX Byte 1 ==
6416 10:05:41.355452 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 10:05:41.359278 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 10:05:41.362441
6419 10:05:41.362537 [DATLAT]
6420 10:05:41.362630 Freq=400, CH0 RK0
6421 10:05:41.362727
6422 10:05:41.365739 DATLAT Default: 0xf
6423 10:05:41.365829 0, 0xFFFF, sum = 0
6424 10:05:41.369343 1, 0xFFFF, sum = 0
6425 10:05:41.369438 2, 0xFFFF, sum = 0
6426 10:05:41.372391 3, 0xFFFF, sum = 0
6427 10:05:41.372487 4, 0xFFFF, sum = 0
6428 10:05:41.375611 5, 0xFFFF, sum = 0
6429 10:05:41.378743 6, 0xFFFF, sum = 0
6430 10:05:41.378844 7, 0xFFFF, sum = 0
6431 10:05:41.382343 8, 0xFFFF, sum = 0
6432 10:05:41.382441 9, 0xFFFF, sum = 0
6433 10:05:41.385663 10, 0xFFFF, sum = 0
6434 10:05:41.385760 11, 0xFFFF, sum = 0
6435 10:05:41.388886 12, 0xFFFF, sum = 0
6436 10:05:41.388981 13, 0x0, sum = 1
6437 10:05:41.392008 14, 0x0, sum = 2
6438 10:05:41.392101 15, 0x0, sum = 3
6439 10:05:41.395304 16, 0x0, sum = 4
6440 10:05:41.395398 best_step = 14
6441 10:05:41.395486
6442 10:05:41.395570 ==
6443 10:05:41.398513 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 10:05:41.402307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 10:05:41.402407 ==
6446 10:05:41.405482 RX Vref Scan: 1
6447 10:05:41.405570
6448 10:05:41.408607 RX Vref 0 -> 0, step: 1
6449 10:05:41.408693
6450 10:05:41.408760 RX Delay -311 -> 252, step: 8
6451 10:05:41.408822
6452 10:05:41.411844 Set Vref, RX VrefLevel [Byte0]: 56
6453 10:05:41.415593 [Byte1]: 49
6454 10:05:41.420810
6455 10:05:41.420918 Final RX Vref Byte 0 = 56 to rank0
6456 10:05:41.424316 Final RX Vref Byte 1 = 49 to rank0
6457 10:05:41.427499 Final RX Vref Byte 0 = 56 to rank1
6458 10:05:41.430784 Final RX Vref Byte 1 = 49 to rank1==
6459 10:05:41.433895 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 10:05:41.440538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 10:05:41.440658 ==
6462 10:05:41.440729 DQS Delay:
6463 10:05:41.443994 DQS0 = 28, DQS1 = 36
6464 10:05:41.444091 DQM Delay:
6465 10:05:41.444157 DQM0 = 10, DQM1 = 12
6466 10:05:41.447362 DQ Delay:
6467 10:05:41.450704 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6468 10:05:41.450798 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6469 10:05:41.454114 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6470 10:05:41.457657 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6471 10:05:41.457752
6472 10:05:41.457860
6473 10:05:41.467783 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6474 10:05:41.470629 CH0 RK0: MR19=C0C, MR18=C8B4
6475 10:05:41.477401 CH0_RK0: MR19=0xC0C, MR18=0xC8B4, DQSOSC=385, MR23=63, INC=398, DEC=265
6476 10:05:41.477535 ==
6477 10:05:41.480926 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 10:05:41.483990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 10:05:41.484088 ==
6480 10:05:41.487650 [Gating] SW mode calibration
6481 10:05:41.494016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6482 10:05:41.497246 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6483 10:05:41.504298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 10:05:41.507482 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 10:05:41.510735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 10:05:41.517728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 10:05:41.520937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 10:05:41.524012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 10:05:41.531000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 10:05:41.534032 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 10:05:41.537277 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 10:05:41.540448 Total UI for P1: 0, mck2ui 16
6493 10:05:41.544205 best dqsien dly found for B0: ( 0, 14, 24)
6494 10:05:41.547629 Total UI for P1: 0, mck2ui 16
6495 10:05:41.550823 best dqsien dly found for B1: ( 0, 14, 24)
6496 10:05:41.553966 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6497 10:05:41.557264 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6498 10:05:41.557350
6499 10:05:41.563804 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 10:05:41.567103 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 10:05:41.567210 [Gating] SW calibration Done
6502 10:05:41.570686 ==
6503 10:05:41.574079 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 10:05:41.577525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 10:05:41.577679 ==
6506 10:05:41.577780 RX Vref Scan: 0
6507 10:05:41.577877
6508 10:05:41.580391 RX Vref 0 -> 0, step: 1
6509 10:05:41.580474
6510 10:05:41.583796 RX Delay -410 -> 252, step: 16
6511 10:05:41.586976 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6512 10:05:41.593741 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6513 10:05:41.597017 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6514 10:05:41.600162 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6515 10:05:41.603884 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6516 10:05:41.610235 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6517 10:05:41.613445 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6518 10:05:41.616621 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6519 10:05:41.619911 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6520 10:05:41.627028 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6521 10:05:41.630401 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6522 10:05:41.633898 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6523 10:05:41.636932 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6524 10:05:41.643351 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6525 10:05:41.646454 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6526 10:05:41.650153 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6527 10:05:41.650259 ==
6528 10:05:41.653603 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 10:05:41.656665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 10:05:41.660360 ==
6531 10:05:41.660484 DQS Delay:
6532 10:05:41.660584 DQS0 = 19, DQS1 = 35
6533 10:05:41.663568 DQM Delay:
6534 10:05:41.663683 DQM0 = 4, DQM1 = 11
6535 10:05:41.666721 DQ Delay:
6536 10:05:41.666828 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6537 10:05:41.670024 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6538 10:05:41.673400 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6539 10:05:41.677339 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6540 10:05:41.677462
6541 10:05:41.677566
6542 10:05:41.677647 ==
6543 10:05:41.680497 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 10:05:41.687029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 10:05:41.687121 ==
6546 10:05:41.687191
6547 10:05:41.687254
6548 10:05:41.687314 TX Vref Scan disable
6549 10:05:41.689880 == TX Byte 0 ==
6550 10:05:41.693728 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6551 10:05:41.697566 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6552 10:05:41.699973 == TX Byte 1 ==
6553 10:05:41.703444 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6554 10:05:41.706500 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6555 10:05:41.706669 ==
6556 10:05:41.710194 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 10:05:41.716356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 10:05:41.716542 ==
6559 10:05:41.716660
6560 10:05:41.716772
6561 10:05:41.716876 TX Vref Scan disable
6562 10:05:41.719908 == TX Byte 0 ==
6563 10:05:41.723636 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6564 10:05:41.726516 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6565 10:05:41.729857 == TX Byte 1 ==
6566 10:05:41.733413 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6567 10:05:41.736359 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6568 10:05:41.736516
6569 10:05:41.739734 [DATLAT]
6570 10:05:41.739884 Freq=400, CH0 RK1
6571 10:05:41.739982
6572 10:05:41.742958 DATLAT Default: 0xe
6573 10:05:41.743085 0, 0xFFFF, sum = 0
6574 10:05:41.746040 1, 0xFFFF, sum = 0
6575 10:05:41.746176 2, 0xFFFF, sum = 0
6576 10:05:41.749509 3, 0xFFFF, sum = 0
6577 10:05:41.749654 4, 0xFFFF, sum = 0
6578 10:05:41.753280 5, 0xFFFF, sum = 0
6579 10:05:41.753399 6, 0xFFFF, sum = 0
6580 10:05:41.756429 7, 0xFFFF, sum = 0
6581 10:05:41.756533 8, 0xFFFF, sum = 0
6582 10:05:41.759286 9, 0xFFFF, sum = 0
6583 10:05:41.763082 10, 0xFFFF, sum = 0
6584 10:05:41.763174 11, 0xFFFF, sum = 0
6585 10:05:41.766233 12, 0xFFFF, sum = 0
6586 10:05:41.766324 13, 0x0, sum = 1
6587 10:05:41.769511 14, 0x0, sum = 2
6588 10:05:41.769643 15, 0x0, sum = 3
6589 10:05:41.769716 16, 0x0, sum = 4
6590 10:05:41.772759 best_step = 14
6591 10:05:41.772857
6592 10:05:41.772925 ==
6593 10:05:41.776042 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 10:05:41.779317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 10:05:41.779414 ==
6596 10:05:41.782427 RX Vref Scan: 0
6597 10:05:41.782512
6598 10:05:41.785571 RX Vref 0 -> 0, step: 1
6599 10:05:41.785668
6600 10:05:41.785736 RX Delay -311 -> 252, step: 8
6601 10:05:41.794912 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6602 10:05:41.797967 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6603 10:05:41.801204 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6604 10:05:41.804364 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6605 10:05:41.811332 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6606 10:05:41.814517 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6607 10:05:41.817744 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6608 10:05:41.821007 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6609 10:05:41.828191 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6610 10:05:41.831419 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6611 10:05:41.834561 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6612 10:05:41.837826 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6613 10:05:41.844401 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6614 10:05:41.847720 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6615 10:05:41.851026 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6616 10:05:41.857482 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6617 10:05:41.857624 ==
6618 10:05:41.861227 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 10:05:41.864572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 10:05:41.864666 ==
6621 10:05:41.864736 DQS Delay:
6622 10:05:41.868124 DQS0 = 24, DQS1 = 32
6623 10:05:41.868213 DQM Delay:
6624 10:05:41.871014 DQM0 = 7, DQM1 = 10
6625 10:05:41.871102 DQ Delay:
6626 10:05:41.874272 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6627 10:05:41.877298 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6628 10:05:41.880659 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6629 10:05:41.884199 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6630 10:05:41.884293
6631 10:05:41.884362
6632 10:05:41.891076 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6633 10:05:41.894254 CH0 RK1: MR19=C0C, MR18=B959
6634 10:05:41.901143 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6635 10:05:41.904411 [RxdqsGatingPostProcess] freq 400
6636 10:05:41.907585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6637 10:05:41.910777 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 10:05:41.914039 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 10:05:41.917836 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 10:05:41.920982 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 10:05:41.924122 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 10:05:41.927343 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 10:05:41.931257 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 10:05:41.934505 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 10:05:41.937710 Pre-setting of DQS Precalculation
6646 10:05:41.940866 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6647 10:05:41.944040 ==
6648 10:05:41.947216 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 10:05:41.950641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 10:05:41.950758 ==
6651 10:05:41.953628 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 10:05:41.960875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 10:05:41.964173 [CA 0] Center 36 (8~64) winsize 57
6654 10:05:41.967322 [CA 1] Center 36 (8~64) winsize 57
6655 10:05:41.970406 [CA 2] Center 36 (8~64) winsize 57
6656 10:05:41.973522 [CA 3] Center 36 (8~64) winsize 57
6657 10:05:41.976896 [CA 4] Center 36 (8~64) winsize 57
6658 10:05:41.980588 [CA 5] Center 36 (8~64) winsize 57
6659 10:05:41.980705
6660 10:05:41.983700 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 10:05:41.983807
6662 10:05:41.986710 [CATrainingPosCal] consider 1 rank data
6663 10:05:41.990137 u2DelayCellTimex100 = 270/100 ps
6664 10:05:41.993444 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 10:05:41.997034 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 10:05:42.000246 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 10:05:42.003476 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 10:05:42.010031 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 10:05:42.013150 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 10:05:42.013261
6671 10:05:42.016460 CA PerBit enable=1, Macro0, CA PI delay=36
6672 10:05:42.016576
6673 10:05:42.020021 [CBTSetCACLKResult] CA Dly = 36
6674 10:05:42.020144 CS Dly: 1 (0~32)
6675 10:05:42.020243 ==
6676 10:05:42.023393 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 10:05:42.029892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 10:05:42.030008 ==
6679 10:05:42.033019 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 10:05:42.040123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6681 10:05:42.043277 [CA 0] Center 36 (8~64) winsize 57
6682 10:05:42.046485 [CA 1] Center 36 (8~64) winsize 57
6683 10:05:42.049580 [CA 2] Center 36 (8~64) winsize 57
6684 10:05:42.052845 [CA 3] Center 36 (8~64) winsize 57
6685 10:05:42.056904 [CA 4] Center 36 (8~64) winsize 57
6686 10:05:42.059917 [CA 5] Center 36 (8~64) winsize 57
6687 10:05:42.060029
6688 10:05:42.062864 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6689 10:05:42.062972
6690 10:05:42.066219 [CATrainingPosCal] consider 2 rank data
6691 10:05:42.069840 u2DelayCellTimex100 = 270/100 ps
6692 10:05:42.073014 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 10:05:42.076524 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 10:05:42.079722 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 10:05:42.082757 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 10:05:42.086480 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 10:05:42.089675 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 10:05:42.089789
6699 10:05:42.096174 CA PerBit enable=1, Macro0, CA PI delay=36
6700 10:05:42.096290
6701 10:05:42.099340 [CBTSetCACLKResult] CA Dly = 36
6702 10:05:42.099448 CS Dly: 1 (0~32)
6703 10:05:42.099544
6704 10:05:42.102507 ----->DramcWriteLeveling(PI) begin...
6705 10:05:42.102615 ==
6706 10:05:42.106157 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 10:05:42.109241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 10:05:42.109362 ==
6709 10:05:42.112820 Write leveling (Byte 0): 40 => 8
6710 10:05:42.116365 Write leveling (Byte 1): 40 => 8
6711 10:05:42.119335 DramcWriteLeveling(PI) end<-----
6712 10:05:42.119463
6713 10:05:42.119558 ==
6714 10:05:42.123021 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 10:05:42.125936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 10:05:42.129280 ==
6717 10:05:42.129484 [Gating] SW mode calibration
6718 10:05:42.139353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6719 10:05:42.142908 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6720 10:05:42.146264 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 10:05:42.152586 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 10:05:42.155811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 10:05:42.159742 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 10:05:42.166557 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 10:05:42.169708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 10:05:42.172776 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 10:05:42.179881 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 10:05:42.183051 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 10:05:42.186006 Total UI for P1: 0, mck2ui 16
6730 10:05:42.189834 best dqsien dly found for B0: ( 0, 14, 24)
6731 10:05:42.193007 Total UI for P1: 0, mck2ui 16
6732 10:05:42.196148 best dqsien dly found for B1: ( 0, 14, 24)
6733 10:05:42.199216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6734 10:05:42.203061 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6735 10:05:42.203185
6736 10:05:42.206431 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 10:05:42.209450 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 10:05:42.212508 [Gating] SW calibration Done
6739 10:05:42.212626 ==
6740 10:05:42.216229 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 10:05:42.219408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 10:05:42.219531 ==
6743 10:05:42.223043 RX Vref Scan: 0
6744 10:05:42.223162
6745 10:05:42.225877 RX Vref 0 -> 0, step: 1
6746 10:05:42.226000
6747 10:05:42.229061 RX Delay -410 -> 252, step: 16
6748 10:05:42.232833 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6749 10:05:42.236188 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6750 10:05:42.239271 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6751 10:05:42.246096 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6752 10:05:42.249173 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6753 10:05:42.252778 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6754 10:05:42.256047 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6755 10:05:42.259256 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6756 10:05:42.265866 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6757 10:05:42.269667 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6758 10:05:42.272824 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6759 10:05:42.275956 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6760 10:05:42.282679 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6761 10:05:42.286110 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6762 10:05:42.289482 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6763 10:05:42.296338 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6764 10:05:42.296483 ==
6765 10:05:42.299256 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 10:05:42.302890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 10:05:42.303014 ==
6768 10:05:42.303114 DQS Delay:
6769 10:05:42.306140 DQS0 = 35, DQS1 = 35
6770 10:05:42.306259 DQM Delay:
6771 10:05:42.309664 DQM0 = 17, DQM1 = 13
6772 10:05:42.309780 DQ Delay:
6773 10:05:42.312765 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6774 10:05:42.315782 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6775 10:05:42.318971 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6776 10:05:42.322885 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6777 10:05:42.323013
6778 10:05:42.323116
6779 10:05:42.323212 ==
6780 10:05:42.325988 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:05:42.329047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:05:42.329168 ==
6783 10:05:42.329273
6784 10:05:42.329371
6785 10:05:42.332668 TX Vref Scan disable
6786 10:05:42.336319 == TX Byte 0 ==
6787 10:05:42.339594 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 10:05:42.342742 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 10:05:42.342870 == TX Byte 1 ==
6790 10:05:42.349397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 10:05:42.352418 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 10:05:42.352545 ==
6793 10:05:42.355709 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 10:05:42.359562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 10:05:42.359689 ==
6796 10:05:42.359796
6797 10:05:42.359892
6798 10:05:42.362697 TX Vref Scan disable
6799 10:05:42.362812 == TX Byte 0 ==
6800 10:05:42.369542 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 10:05:42.372394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 10:05:42.372519 == TX Byte 1 ==
6803 10:05:42.379072 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 10:05:42.382593 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 10:05:42.382734
6806 10:05:42.382838 [DATLAT]
6807 10:05:42.385818 Freq=400, CH1 RK0
6808 10:05:42.385937
6809 10:05:42.386037 DATLAT Default: 0xf
6810 10:05:42.389393 0, 0xFFFF, sum = 0
6811 10:05:42.389523 1, 0xFFFF, sum = 0
6812 10:05:42.392442 2, 0xFFFF, sum = 0
6813 10:05:42.392562 3, 0xFFFF, sum = 0
6814 10:05:42.396049 4, 0xFFFF, sum = 0
6815 10:05:42.396177 5, 0xFFFF, sum = 0
6816 10:05:42.398958 6, 0xFFFF, sum = 0
6817 10:05:42.402656 7, 0xFFFF, sum = 0
6818 10:05:42.402781 8, 0xFFFF, sum = 0
6819 10:05:42.405840 9, 0xFFFF, sum = 0
6820 10:05:42.405965 10, 0xFFFF, sum = 0
6821 10:05:42.408869 11, 0xFFFF, sum = 0
6822 10:05:42.408987 12, 0xFFFF, sum = 0
6823 10:05:42.412732 13, 0x0, sum = 1
6824 10:05:42.412867 14, 0x0, sum = 2
6825 10:05:42.415619 15, 0x0, sum = 3
6826 10:05:42.415733 16, 0x0, sum = 4
6827 10:05:42.415835 best_step = 14
6828 10:05:42.419312
6829 10:05:42.419429 ==
6830 10:05:42.422473 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 10:05:42.425706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 10:05:42.425831 ==
6833 10:05:42.425932 RX Vref Scan: 1
6834 10:05:42.426031
6835 10:05:42.429361 RX Vref 0 -> 0, step: 1
6836 10:05:42.429490
6837 10:05:42.432492 RX Delay -311 -> 252, step: 8
6838 10:05:42.432620
6839 10:05:42.435996 Set Vref, RX VrefLevel [Byte0]: 53
6840 10:05:42.439243 [Byte1]: 47
6841 10:05:42.442952
6842 10:05:42.443092 Final RX Vref Byte 0 = 53 to rank0
6843 10:05:42.446099 Final RX Vref Byte 1 = 47 to rank0
6844 10:05:42.449198 Final RX Vref Byte 0 = 53 to rank1
6845 10:05:42.453066 Final RX Vref Byte 1 = 47 to rank1==
6846 10:05:42.456214 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 10:05:42.462535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 10:05:42.462696 ==
6849 10:05:42.462801 DQS Delay:
6850 10:05:42.462902 DQS0 = 32, DQS1 = 32
6851 10:05:42.465746 DQM Delay:
6852 10:05:42.465861 DQM0 = 13, DQM1 = 11
6853 10:05:42.469549 DQ Delay:
6854 10:05:42.472881 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6855 10:05:42.473018 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6856 10:05:42.476095 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6857 10:05:42.479319 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6858 10:05:42.479466
6859 10:05:42.482442
6860 10:05:42.489191 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6861 10:05:42.492515 CH1 RK0: MR19=C0C, MR18=92CA
6862 10:05:42.499076 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6863 10:05:42.499255 ==
6864 10:05:42.502415 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 10:05:42.505723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 10:05:42.505865 ==
6867 10:05:42.509372 [Gating] SW mode calibration
6868 10:05:42.516103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6869 10:05:42.522542 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6870 10:05:42.525798 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 10:05:42.528790 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 10:05:42.535747 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 10:05:42.538763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 10:05:42.542359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 10:05:42.545465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 10:05:42.552069 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 10:05:42.555553 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 10:05:42.558969 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 10:05:42.562000 Total UI for P1: 0, mck2ui 16
6880 10:05:42.565346 best dqsien dly found for B0: ( 0, 14, 24)
6881 10:05:42.568503 Total UI for P1: 0, mck2ui 16
6882 10:05:42.572258 best dqsien dly found for B1: ( 0, 14, 24)
6883 10:05:42.575698 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6884 10:05:42.582107 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6885 10:05:42.582249
6886 10:05:42.585399 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 10:05:42.588795 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 10:05:42.591837 [Gating] SW calibration Done
6889 10:05:42.591953 ==
6890 10:05:42.595737 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 10:05:42.598900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 10:05:42.599016 ==
6893 10:05:42.599116 RX Vref Scan: 0
6894 10:05:42.602182
6895 10:05:42.602292 RX Vref 0 -> 0, step: 1
6896 10:05:42.602393
6897 10:05:42.605508 RX Delay -410 -> 252, step: 16
6898 10:05:42.608899 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6899 10:05:42.615371 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6900 10:05:42.618902 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6901 10:05:42.622224 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6902 10:05:42.625068 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6903 10:05:42.631713 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6904 10:05:42.635215 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6905 10:05:42.638572 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6906 10:05:42.642002 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6907 10:05:42.648696 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6908 10:05:42.652060 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6909 10:05:42.655386 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6910 10:05:42.658438 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6911 10:05:42.665340 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6912 10:05:42.668796 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6913 10:05:42.671755 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6914 10:05:42.671894 ==
6915 10:05:42.675355 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 10:05:42.678522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 10:05:42.681736 ==
6918 10:05:42.681844 DQS Delay:
6919 10:05:42.681911 DQS0 = 35, DQS1 = 35
6920 10:05:42.685549 DQM Delay:
6921 10:05:42.685665 DQM0 = 18, DQM1 = 13
6922 10:05:42.688752 DQ Delay:
6923 10:05:42.691973 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6924 10:05:42.692060 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6925 10:05:42.695230 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6926 10:05:42.698506 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6927 10:05:42.698592
6928 10:05:42.701796
6929 10:05:42.701879 ==
6930 10:05:42.705009 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 10:05:42.708165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 10:05:42.708251 ==
6933 10:05:42.708317
6934 10:05:42.708378
6935 10:05:42.711448 TX Vref Scan disable
6936 10:05:42.711533 == TX Byte 0 ==
6937 10:05:42.715265 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6938 10:05:42.721548 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6939 10:05:42.721709 == TX Byte 1 ==
6940 10:05:42.724780 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6941 10:05:42.731857 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6942 10:05:42.731979 ==
6943 10:05:42.735009 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 10:05:42.738355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 10:05:42.738473 ==
6946 10:05:42.738572
6947 10:05:42.738668
6948 10:05:42.741885 TX Vref Scan disable
6949 10:05:42.742001 == TX Byte 0 ==
6950 10:05:42.744790 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6951 10:05:42.751342 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6952 10:05:42.751461 == TX Byte 1 ==
6953 10:05:42.754531 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6954 10:05:42.761263 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6955 10:05:42.761384
6956 10:05:42.761485 [DATLAT]
6957 10:05:42.761609 Freq=400, CH1 RK1
6958 10:05:42.761722
6959 10:05:42.764893 DATLAT Default: 0xe
6960 10:05:42.767992 0, 0xFFFF, sum = 0
6961 10:05:42.768108 1, 0xFFFF, sum = 0
6962 10:05:42.771115 2, 0xFFFF, sum = 0
6963 10:05:42.771233 3, 0xFFFF, sum = 0
6964 10:05:42.774540 4, 0xFFFF, sum = 0
6965 10:05:42.774660 5, 0xFFFF, sum = 0
6966 10:05:42.778192 6, 0xFFFF, sum = 0
6967 10:05:42.778311 7, 0xFFFF, sum = 0
6968 10:05:42.781126 8, 0xFFFF, sum = 0
6969 10:05:42.781242 9, 0xFFFF, sum = 0
6970 10:05:42.784714 10, 0xFFFF, sum = 0
6971 10:05:42.784833 11, 0xFFFF, sum = 0
6972 10:05:42.788159 12, 0xFFFF, sum = 0
6973 10:05:42.788278 13, 0x0, sum = 1
6974 10:05:42.791353 14, 0x0, sum = 2
6975 10:05:42.791469 15, 0x0, sum = 3
6976 10:05:42.794903 16, 0x0, sum = 4
6977 10:05:42.795019 best_step = 14
6978 10:05:42.795117
6979 10:05:42.795216 ==
6980 10:05:42.798020 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 10:05:42.801183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 10:05:42.804886 ==
6983 10:05:42.805000 RX Vref Scan: 0
6984 10:05:42.805103
6985 10:05:42.808166 RX Vref 0 -> 0, step: 1
6986 10:05:42.808277
6987 10:05:42.811249 RX Delay -311 -> 252, step: 8
6988 10:05:42.814459 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6989 10:05:42.821341 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6990 10:05:42.824681 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6991 10:05:42.827837 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6992 10:05:42.831049 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6993 10:05:42.838075 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6994 10:05:42.841343 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6995 10:05:42.844452 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6996 10:05:42.847881 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6997 10:05:42.854295 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6998 10:05:42.857530 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6999 10:05:42.861381 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7000 10:05:42.864435 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7001 10:05:42.871376 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7002 10:05:42.874455 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7003 10:05:42.877767 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7004 10:05:42.877886 ==
7005 10:05:42.881381 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 10:05:42.887447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 10:05:42.887568 ==
7008 10:05:42.887674 DQS Delay:
7009 10:05:42.891381 DQS0 = 28, DQS1 = 32
7010 10:05:42.891495 DQM Delay:
7011 10:05:42.891592 DQM0 = 11, DQM1 = 11
7012 10:05:42.894685 DQ Delay:
7013 10:05:42.897781 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
7014 10:05:42.897895 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7015 10:05:42.901091 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7016 10:05:42.904189 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7017 10:05:42.904279
7018 10:05:42.904348
7019 10:05:42.914534 [DQSOSCAuto] RK1, (LSB)MR18= 0xc558, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7020 10:05:42.917720 CH1 RK1: MR19=C0C, MR18=C558
7021 10:05:42.924250 CH1_RK1: MR19=0xC0C, MR18=0xC558, DQSOSC=385, MR23=63, INC=398, DEC=265
7022 10:05:42.924411 [RxdqsGatingPostProcess] freq 400
7023 10:05:42.931260 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7024 10:05:42.934471 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 10:05:42.937530 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 10:05:42.940828 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 10:05:42.944679 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 10:05:42.947923 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 10:05:42.951035 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 10:05:42.954404 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 10:05:42.957450 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 10:05:42.961071 Pre-setting of DQS Precalculation
7033 10:05:42.964384 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7034 10:05:42.971423 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7035 10:05:42.978096 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7036 10:05:42.978239
7037 10:05:42.978344
7038 10:05:42.980834 [Calibration Summary] 800 Mbps
7039 10:05:42.984583 CH 0, Rank 0
7040 10:05:42.984704 SW Impedance : PASS
7041 10:05:42.987676 DUTY Scan : NO K
7042 10:05:42.990861 ZQ Calibration : PASS
7043 10:05:42.990986 Jitter Meter : NO K
7044 10:05:42.994018 CBT Training : PASS
7045 10:05:42.997945 Write leveling : PASS
7046 10:05:42.998064 RX DQS gating : PASS
7047 10:05:43.001262 RX DQ/DQS(RDDQC) : PASS
7048 10:05:43.004261 TX DQ/DQS : PASS
7049 10:05:43.004387 RX DATLAT : PASS
7050 10:05:43.007588 RX DQ/DQS(Engine): PASS
7051 10:05:43.007706 TX OE : NO K
7052 10:05:43.010735 All Pass.
7053 10:05:43.010852
7054 10:05:43.010950 CH 0, Rank 1
7055 10:05:43.014502 SW Impedance : PASS
7056 10:05:43.014620 DUTY Scan : NO K
7057 10:05:43.017935 ZQ Calibration : PASS
7058 10:05:43.021251 Jitter Meter : NO K
7059 10:05:43.021372 CBT Training : PASS
7060 10:05:43.024204 Write leveling : NO K
7061 10:05:43.027931 RX DQS gating : PASS
7062 10:05:43.028055 RX DQ/DQS(RDDQC) : PASS
7063 10:05:43.031412 TX DQ/DQS : PASS
7064 10:05:43.034493 RX DATLAT : PASS
7065 10:05:43.034585 RX DQ/DQS(Engine): PASS
7066 10:05:43.037539 TX OE : NO K
7067 10:05:43.037682 All Pass.
7068 10:05:43.037748
7069 10:05:43.041041 CH 1, Rank 0
7070 10:05:43.041142 SW Impedance : PASS
7071 10:05:43.044792 DUTY Scan : NO K
7072 10:05:43.048014 ZQ Calibration : PASS
7073 10:05:43.048106 Jitter Meter : NO K
7074 10:05:43.051224 CBT Training : PASS
7075 10:05:43.051311 Write leveling : PASS
7076 10:05:43.054551 RX DQS gating : PASS
7077 10:05:43.057689 RX DQ/DQS(RDDQC) : PASS
7078 10:05:43.057782 TX DQ/DQS : PASS
7079 10:05:43.060962 RX DATLAT : PASS
7080 10:05:43.064066 RX DQ/DQS(Engine): PASS
7081 10:05:43.064155 TX OE : NO K
7082 10:05:43.067671 All Pass.
7083 10:05:43.067759
7084 10:05:43.067826 CH 1, Rank 1
7085 10:05:43.070833 SW Impedance : PASS
7086 10:05:43.070920 DUTY Scan : NO K
7087 10:05:43.073939 ZQ Calibration : PASS
7088 10:05:43.077266 Jitter Meter : NO K
7089 10:05:43.077354 CBT Training : PASS
7090 10:05:43.080559 Write leveling : NO K
7091 10:05:43.084192 RX DQS gating : PASS
7092 10:05:43.084285 RX DQ/DQS(RDDQC) : PASS
7093 10:05:43.087479 TX DQ/DQS : PASS
7094 10:05:43.090539 RX DATLAT : PASS
7095 10:05:43.090627 RX DQ/DQS(Engine): PASS
7096 10:05:43.094092 TX OE : NO K
7097 10:05:43.094181 All Pass.
7098 10:05:43.094247
7099 10:05:43.097214 DramC Write-DBI off
7100 10:05:43.100312 PER_BANK_REFRESH: Hybrid Mode
7101 10:05:43.100399 TX_TRACKING: ON
7102 10:05:43.110335 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7103 10:05:43.114034 [FAST_K] Save calibration result to emmc
7104 10:05:43.117326 dramc_set_vcore_voltage set vcore to 725000
7105 10:05:43.120481 Read voltage for 1600, 0
7106 10:05:43.120571 Vio18 = 0
7107 10:05:43.120638 Vcore = 725000
7108 10:05:43.124032 Vdram = 0
7109 10:05:43.124202 Vddq = 0
7110 10:05:43.124282 Vmddr = 0
7111 10:05:43.130252 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7112 10:05:43.133998 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7113 10:05:43.137165 MEM_TYPE=3, freq_sel=13
7114 10:05:43.140339 sv_algorithm_assistance_LP4_3733
7115 10:05:43.143442 ============ PULL DRAM RESETB DOWN ============
7116 10:05:43.147090 ========== PULL DRAM RESETB DOWN end =========
7117 10:05:43.153687 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7118 10:05:43.156927 ===================================
7119 10:05:43.160139 LPDDR4 DRAM CONFIGURATION
7120 10:05:43.163604 ===================================
7121 10:05:43.163739 EX_ROW_EN[0] = 0x0
7122 10:05:43.167016 EX_ROW_EN[1] = 0x0
7123 10:05:43.167143 LP4Y_EN = 0x0
7124 10:05:43.170099 WORK_FSP = 0x1
7125 10:05:43.170221 WL = 0x5
7126 10:05:43.173772 RL = 0x5
7127 10:05:43.173895 BL = 0x2
7128 10:05:43.177182 RPST = 0x0
7129 10:05:43.177300 RD_PRE = 0x0
7130 10:05:43.180280 WR_PRE = 0x1
7131 10:05:43.180411 WR_PST = 0x1
7132 10:05:43.183580 DBI_WR = 0x0
7133 10:05:43.183706 DBI_RD = 0x0
7134 10:05:43.186778 OTF = 0x1
7135 10:05:43.189912 ===================================
7136 10:05:43.193823 ===================================
7137 10:05:43.193951 ANA top config
7138 10:05:43.197229 ===================================
7139 10:05:43.200155 DLL_ASYNC_EN = 0
7140 10:05:43.203275 ALL_SLAVE_EN = 0
7141 10:05:43.207283 NEW_RANK_MODE = 1
7142 10:05:43.207409 DLL_IDLE_MODE = 1
7143 10:05:43.210486 LP45_APHY_COMB_EN = 1
7144 10:05:43.213473 TX_ODT_DIS = 0
7145 10:05:43.216668 NEW_8X_MODE = 1
7146 10:05:43.220634 ===================================
7147 10:05:43.223250 ===================================
7148 10:05:43.227195 data_rate = 3200
7149 10:05:43.227330 CKR = 1
7150 10:05:43.230377 DQ_P2S_RATIO = 8
7151 10:05:43.233451 ===================================
7152 10:05:43.236917 CA_P2S_RATIO = 8
7153 10:05:43.239975 DQ_CA_OPEN = 0
7154 10:05:43.243353 DQ_SEMI_OPEN = 0
7155 10:05:43.246492 CA_SEMI_OPEN = 0
7156 10:05:43.246629 CA_FULL_RATE = 0
7157 10:05:43.250461 DQ_CKDIV4_EN = 0
7158 10:05:43.253661 CA_CKDIV4_EN = 0
7159 10:05:43.256867 CA_PREDIV_EN = 0
7160 10:05:43.259952 PH8_DLY = 12
7161 10:05:43.263536 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7162 10:05:43.263670 DQ_AAMCK_DIV = 4
7163 10:05:43.266935 CA_AAMCK_DIV = 4
7164 10:05:43.270345 CA_ADMCK_DIV = 4
7165 10:05:43.273250 DQ_TRACK_CA_EN = 0
7166 10:05:43.277042 CA_PICK = 1600
7167 10:05:43.279904 CA_MCKIO = 1600
7168 10:05:43.283236 MCKIO_SEMI = 0
7169 10:05:43.283362 PLL_FREQ = 3068
7170 10:05:43.286492 DQ_UI_PI_RATIO = 32
7171 10:05:43.289920 CA_UI_PI_RATIO = 0
7172 10:05:43.293346 ===================================
7173 10:05:43.296499 ===================================
7174 10:05:43.299922 memory_type:LPDDR4
7175 10:05:43.300038 GP_NUM : 10
7176 10:05:43.302859 SRAM_EN : 1
7177 10:05:43.306713 MD32_EN : 0
7178 10:05:43.309759 ===================================
7179 10:05:43.309879 [ANA_INIT] >>>>>>>>>>>>>>
7180 10:05:43.312866 <<<<<< [CONFIGURE PHASE]: ANA_TX
7181 10:05:43.316699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7182 10:05:43.319808 ===================================
7183 10:05:43.322917 data_rate = 3200,PCW = 0X7600
7184 10:05:43.326706 ===================================
7185 10:05:43.329928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7186 10:05:43.336305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 10:05:43.339465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 10:05:43.346340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7189 10:05:43.349829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7190 10:05:43.353065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7191 10:05:43.356089 [ANA_INIT] flow start
7192 10:05:43.356220 [ANA_INIT] PLL >>>>>>>>
7193 10:05:43.359809 [ANA_INIT] PLL <<<<<<<<
7194 10:05:43.362805 [ANA_INIT] MIDPI >>>>>>>>
7195 10:05:43.362931 [ANA_INIT] MIDPI <<<<<<<<
7196 10:05:43.366079 [ANA_INIT] DLL >>>>>>>>
7197 10:05:43.369917 [ANA_INIT] DLL <<<<<<<<
7198 10:05:43.370039 [ANA_INIT] flow end
7199 10:05:43.373134 ============ LP4 DIFF to SE enter ============
7200 10:05:43.379506 ============ LP4 DIFF to SE exit ============
7201 10:05:43.379647 [ANA_INIT] <<<<<<<<<<<<<
7202 10:05:43.383095 [Flow] Enable top DCM control >>>>>
7203 10:05:43.386029 [Flow] Enable top DCM control <<<<<
7204 10:05:43.389704 Enable DLL master slave shuffle
7205 10:05:43.396497 ==============================================================
7206 10:05:43.396633 Gating Mode config
7207 10:05:43.402930 ==============================================================
7208 10:05:43.406290 Config description:
7209 10:05:43.416219 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7210 10:05:43.422665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7211 10:05:43.426375 SELPH_MODE 0: By rank 1: By Phase
7212 10:05:43.432509 ==============================================================
7213 10:05:43.436484 GAT_TRACK_EN = 1
7214 10:05:43.439004 RX_GATING_MODE = 2
7215 10:05:43.439123 RX_GATING_TRACK_MODE = 2
7216 10:05:43.442405 SELPH_MODE = 1
7217 10:05:43.446154 PICG_EARLY_EN = 1
7218 10:05:43.449286 VALID_LAT_VALUE = 1
7219 10:05:43.455982 ==============================================================
7220 10:05:43.459089 Enter into Gating configuration >>>>
7221 10:05:43.462598 Exit from Gating configuration <<<<
7222 10:05:43.466261 Enter into DVFS_PRE_config >>>>>
7223 10:05:43.475761 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7224 10:05:43.479448 Exit from DVFS_PRE_config <<<<<
7225 10:05:43.482707 Enter into PICG configuration >>>>
7226 10:05:43.485638 Exit from PICG configuration <<<<
7227 10:05:43.489193 [RX_INPUT] configuration >>>>>
7228 10:05:43.492268 [RX_INPUT] configuration <<<<<
7229 10:05:43.495907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7230 10:05:43.502776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7231 10:05:43.508933 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 10:05:43.515645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 10:05:43.518994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 10:05:43.526054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 10:05:43.529081 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7236 10:05:43.535897 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7237 10:05:43.539050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7238 10:05:43.542281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7239 10:05:43.545449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7240 10:05:43.552529 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 10:05:43.555798 ===================================
7242 10:05:43.555923 LPDDR4 DRAM CONFIGURATION
7243 10:05:43.558894 ===================================
7244 10:05:43.562600 EX_ROW_EN[0] = 0x0
7245 10:05:43.565983 EX_ROW_EN[1] = 0x0
7246 10:05:43.566105 LP4Y_EN = 0x0
7247 10:05:43.568728 WORK_FSP = 0x1
7248 10:05:43.568841 WL = 0x5
7249 10:05:43.572178 RL = 0x5
7250 10:05:43.572293 BL = 0x2
7251 10:05:43.575815 RPST = 0x0
7252 10:05:43.575930 RD_PRE = 0x0
7253 10:05:43.579097 WR_PRE = 0x1
7254 10:05:43.579231 WR_PST = 0x1
7255 10:05:43.582162 DBI_WR = 0x0
7256 10:05:43.582278 DBI_RD = 0x0
7257 10:05:43.585472 OTF = 0x1
7258 10:05:43.588563 ===================================
7259 10:05:43.592135 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7260 10:05:43.595767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7261 10:05:43.601989 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 10:05:43.605503 ===================================
7263 10:05:43.605656 LPDDR4 DRAM CONFIGURATION
7264 10:05:43.608739 ===================================
7265 10:05:43.612478 EX_ROW_EN[0] = 0x10
7266 10:05:43.615550 EX_ROW_EN[1] = 0x0
7267 10:05:43.615668 LP4Y_EN = 0x0
7268 10:05:43.618682 WORK_FSP = 0x1
7269 10:05:43.618800 WL = 0x5
7270 10:05:43.622293 RL = 0x5
7271 10:05:43.622414 BL = 0x2
7272 10:05:43.625407 RPST = 0x0
7273 10:05:43.625535 RD_PRE = 0x0
7274 10:05:43.628551 WR_PRE = 0x1
7275 10:05:43.628680 WR_PST = 0x1
7276 10:05:43.632274 DBI_WR = 0x0
7277 10:05:43.632387 DBI_RD = 0x0
7278 10:05:43.635150 OTF = 0x1
7279 10:05:43.638703 ===================================
7280 10:05:43.645464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7281 10:05:43.645634 ==
7282 10:05:43.648657 Dram Type= 6, Freq= 0, CH_0, rank 0
7283 10:05:43.651778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 10:05:43.651901 ==
7285 10:05:43.655329 [Duty_Offset_Calibration]
7286 10:05:43.655445 B0:2 B1:1 CA:1
7287 10:05:43.655549
7288 10:05:43.658741 [DutyScan_Calibration_Flow] k_type=0
7289 10:05:43.668932
7290 10:05:43.669066 ==CLK 0==
7291 10:05:43.672130 Final CLK duty delay cell = 0
7292 10:05:43.675795 [0] MAX Duty = 5156%(X100), DQS PI = 22
7293 10:05:43.678939 [0] MIN Duty = 4876%(X100), DQS PI = 48
7294 10:05:43.679059 [0] AVG Duty = 5016%(X100)
7295 10:05:43.682509
7296 10:05:43.682643 CH0 CLK Duty spec in!! Max-Min= 280%
7297 10:05:43.688848 [DutyScan_Calibration_Flow] ====Done====
7298 10:05:43.688981
7299 10:05:43.692117 [DutyScan_Calibration_Flow] k_type=1
7300 10:05:43.708144
7301 10:05:43.708296 ==DQS 0 ==
7302 10:05:43.711774 Final DQS duty delay cell = -4
7303 10:05:43.714887 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7304 10:05:43.718060 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7305 10:05:43.721769 [-4] AVG Duty = 4891%(X100)
7306 10:05:43.721882
7307 10:05:43.721984 ==DQS 1 ==
7308 10:05:43.724791 Final DQS duty delay cell = 0
7309 10:05:43.728487 [0] MAX Duty = 5218%(X100), DQS PI = 60
7310 10:05:43.731803 [0] MIN Duty = 5031%(X100), DQS PI = 52
7311 10:05:43.735017 [0] AVG Duty = 5124%(X100)
7312 10:05:43.735136
7313 10:05:43.738267 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7314 10:05:43.738386
7315 10:05:43.741524 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7316 10:05:43.744787 [DutyScan_Calibration_Flow] ====Done====
7317 10:05:43.744902
7318 10:05:43.748299 [DutyScan_Calibration_Flow] k_type=3
7319 10:05:43.764666
7320 10:05:43.764827 ==DQM 0 ==
7321 10:05:43.768283 Final DQM duty delay cell = 0
7322 10:05:43.771409 [0] MAX Duty = 5218%(X100), DQS PI = 34
7323 10:05:43.774580 [0] MIN Duty = 4875%(X100), DQS PI = 60
7324 10:05:43.778479 [0] AVG Duty = 5046%(X100)
7325 10:05:43.778602
7326 10:05:43.778700 ==DQM 1 ==
7327 10:05:43.781687 Final DQM duty delay cell = -4
7328 10:05:43.784723 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7329 10:05:43.788487 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7330 10:05:43.791662 [-4] AVG Duty = 4906%(X100)
7331 10:05:43.791815
7332 10:05:43.794669 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7333 10:05:43.794782
7334 10:05:43.798187 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7335 10:05:43.801446 [DutyScan_Calibration_Flow] ====Done====
7336 10:05:43.801561
7337 10:05:43.804383 [DutyScan_Calibration_Flow] k_type=2
7338 10:05:43.822783
7339 10:05:43.822939 ==DQ 0 ==
7340 10:05:43.825600 Final DQ duty delay cell = 0
7341 10:05:43.828806 [0] MAX Duty = 5062%(X100), DQS PI = 26
7342 10:05:43.832486 [0] MIN Duty = 4907%(X100), DQS PI = 0
7343 10:05:43.832601 [0] AVG Duty = 4984%(X100)
7344 10:05:43.832703
7345 10:05:43.835686 ==DQ 1 ==
7346 10:05:43.838832 Final DQ duty delay cell = 0
7347 10:05:43.842157 [0] MAX Duty = 5156%(X100), DQS PI = 22
7348 10:05:43.846057 [0] MIN Duty = 4938%(X100), DQS PI = 34
7349 10:05:43.846181 [0] AVG Duty = 5047%(X100)
7350 10:05:43.846282
7351 10:05:43.848962 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7352 10:05:43.852719
7353 10:05:43.855819 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7354 10:05:43.858832 [DutyScan_Calibration_Flow] ====Done====
7355 10:05:43.858953 ==
7356 10:05:43.862450 Dram Type= 6, Freq= 0, CH_1, rank 0
7357 10:05:43.865898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7358 10:05:43.866026 ==
7359 10:05:43.869210 [Duty_Offset_Calibration]
7360 10:05:43.869337 B0:1 B1:0 CA:0
7361 10:05:43.869435
7362 10:05:43.872049 [DutyScan_Calibration_Flow] k_type=0
7363 10:05:43.881692
7364 10:05:43.881857 ==CLK 0==
7365 10:05:43.884718 Final CLK duty delay cell = -4
7366 10:05:43.888451 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7367 10:05:43.891592 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7368 10:05:43.894867 [-4] AVG Duty = 4922%(X100)
7369 10:05:43.895028
7370 10:05:43.897878 CH1 CLK Duty spec in!! Max-Min= 156%
7371 10:05:43.901484 [DutyScan_Calibration_Flow] ====Done====
7372 10:05:43.901638
7373 10:05:43.904543 [DutyScan_Calibration_Flow] k_type=1
7374 10:05:43.921622
7375 10:05:43.921788 ==DQS 0 ==
7376 10:05:43.924944 Final DQS duty delay cell = 0
7377 10:05:43.928478 [0] MAX Duty = 5094%(X100), DQS PI = 16
7378 10:05:43.931984 [0] MIN Duty = 4844%(X100), DQS PI = 50
7379 10:05:43.932109 [0] AVG Duty = 4969%(X100)
7380 10:05:43.935477
7381 10:05:43.935593 ==DQS 1 ==
7382 10:05:43.938499 Final DQS duty delay cell = 0
7383 10:05:43.941619 [0] MAX Duty = 5249%(X100), DQS PI = 16
7384 10:05:43.944816 [0] MIN Duty = 4969%(X100), DQS PI = 8
7385 10:05:43.944941 [0] AVG Duty = 5109%(X100)
7386 10:05:43.948171
7387 10:05:43.951800 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7388 10:05:43.951924
7389 10:05:43.955007 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7390 10:05:43.958334 [DutyScan_Calibration_Flow] ====Done====
7391 10:05:43.958462
7392 10:05:43.961735 [DutyScan_Calibration_Flow] k_type=3
7393 10:05:43.978764
7394 10:05:43.978936 ==DQM 0 ==
7395 10:05:43.982110 Final DQM duty delay cell = 0
7396 10:05:43.985485 [0] MAX Duty = 5218%(X100), DQS PI = 18
7397 10:05:43.988635 [0] MIN Duty = 4969%(X100), DQS PI = 48
7398 10:05:43.988760 [0] AVG Duty = 5093%(X100)
7399 10:05:43.991904
7400 10:05:43.992023 ==DQM 1 ==
7401 10:05:43.995335 Final DQM duty delay cell = 0
7402 10:05:43.998566 [0] MAX Duty = 5093%(X100), DQS PI = 16
7403 10:05:44.001775 [0] MIN Duty = 4907%(X100), DQS PI = 34
7404 10:05:44.005033 [0] AVG Duty = 5000%(X100)
7405 10:05:44.005151
7406 10:05:44.008585 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7407 10:05:44.008708
7408 10:05:44.011808 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7409 10:05:44.014890 [DutyScan_Calibration_Flow] ====Done====
7410 10:05:44.015014
7411 10:05:44.017947 [DutyScan_Calibration_Flow] k_type=2
7412 10:05:44.034889
7413 10:05:44.035067 ==DQ 0 ==
7414 10:05:44.037907 Final DQ duty delay cell = -4
7415 10:05:44.041518 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7416 10:05:44.044590 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7417 10:05:44.047966 [-4] AVG Duty = 4953%(X100)
7418 10:05:44.048099
7419 10:05:44.048203 ==DQ 1 ==
7420 10:05:44.051041 Final DQ duty delay cell = 0
7421 10:05:44.054820 [0] MAX Duty = 5124%(X100), DQS PI = 18
7422 10:05:44.057881 [0] MIN Duty = 4938%(X100), DQS PI = 8
7423 10:05:44.061347 [0] AVG Duty = 5031%(X100)
7424 10:05:44.061475
7425 10:05:44.064620 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7426 10:05:44.064741
7427 10:05:44.068422 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7428 10:05:44.071604 [DutyScan_Calibration_Flow] ====Done====
7429 10:05:44.074812 nWR fixed to 30
7430 10:05:44.074941 [ModeRegInit_LP4] CH0 RK0
7431 10:05:44.078148 [ModeRegInit_LP4] CH0 RK1
7432 10:05:44.081337 [ModeRegInit_LP4] CH1 RK0
7433 10:05:44.084583 [ModeRegInit_LP4] CH1 RK1
7434 10:05:44.084713 match AC timing 5
7435 10:05:44.091133 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7436 10:05:44.094414 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7437 10:05:44.097704 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7438 10:05:44.105011 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7439 10:05:44.108197 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7440 10:05:44.108343 [MiockJmeterHQA]
7441 10:05:44.108446
7442 10:05:44.111225 [DramcMiockJmeter] u1RxGatingPI = 0
7443 10:05:44.114424 0 : 4253, 4027
7444 10:05:44.114555 4 : 4253, 4026
7445 10:05:44.117630 8 : 4363, 4137
7446 10:05:44.117758 12 : 4252, 4027
7447 10:05:44.117865 16 : 4252, 4027
7448 10:05:44.121413 20 : 4363, 4137
7449 10:05:44.121541 24 : 4252, 4027
7450 10:05:44.124376 28 : 4252, 4027
7451 10:05:44.124501 32 : 4253, 4026
7452 10:05:44.127830 36 : 4255, 4030
7453 10:05:44.127932 40 : 4363, 4137
7454 10:05:44.128004 44 : 4253, 4027
7455 10:05:44.131064 48 : 4363, 4137
7456 10:05:44.131156 52 : 4252, 4027
7457 10:05:44.134486 56 : 4252, 4027
7458 10:05:44.134578 60 : 4250, 4026
7459 10:05:44.138139 64 : 4361, 4137
7460 10:05:44.138226 68 : 4249, 4027
7461 10:05:44.141281 72 : 4361, 4137
7462 10:05:44.141369 76 : 4253, 4029
7463 10:05:44.141437 80 : 4250, 4026
7464 10:05:44.144468 84 : 4250, 4026
7465 10:05:44.144556 88 : 4252, 59
7466 10:05:44.147998 92 : 4361, 0
7467 10:05:44.148089 96 : 4253, 0
7468 10:05:44.148158 100 : 4250, 0
7469 10:05:44.151106 104 : 4252, 0
7470 10:05:44.151214 108 : 4250, 0
7471 10:05:44.154913 112 : 4360, 0
7472 10:05:44.155024 116 : 4361, 0
7473 10:05:44.155106 120 : 4252, 0
7474 10:05:44.158018 124 : 4250, 0
7475 10:05:44.158178 128 : 4363, 0
7476 10:05:44.158293 132 : 4250, 0
7477 10:05:44.161100 136 : 4253, 0
7478 10:05:44.161224 140 : 4250, 0
7479 10:05:44.165000 144 : 4252, 0
7480 10:05:44.165155 148 : 4250, 0
7481 10:05:44.165255 152 : 4250, 0
7482 10:05:44.167953 156 : 4252, 0
7483 10:05:44.168067 160 : 4250, 0
7484 10:05:44.171443 164 : 4360, 0
7485 10:05:44.171560 168 : 4250, 0
7486 10:05:44.171660 172 : 4250, 0
7487 10:05:44.174387 176 : 4252, 0
7488 10:05:44.174503 180 : 4363, 0
7489 10:05:44.177757 184 : 4250, 0
7490 10:05:44.177872 188 : 4250, 0
7491 10:05:44.177978 192 : 4250, 0
7492 10:05:44.180896 196 : 4252, 0
7493 10:05:44.181018 200 : 4361, 0
7494 10:05:44.184304 204 : 4250, 1002
7495 10:05:44.184421 208 : 4250, 3957
7496 10:05:44.184550 212 : 4250, 4027
7497 10:05:44.187612 216 : 4250, 4027
7498 10:05:44.187729 220 : 4250, 4027
7499 10:05:44.190923 224 : 4250, 4026
7500 10:05:44.191038 228 : 4253, 4029
7501 10:05:44.194313 232 : 4252, 4030
7502 10:05:44.194426 236 : 4250, 4027
7503 10:05:44.198348 240 : 4360, 4137
7504 10:05:44.198461 244 : 4361, 4137
7505 10:05:44.201317 248 : 4250, 4027
7506 10:05:44.201435 252 : 4363, 4140
7507 10:05:44.204331 256 : 4361, 4137
7508 10:05:44.204443 260 : 4250, 4026
7509 10:05:44.207758 264 : 4252, 4027
7510 10:05:44.207875 268 : 4252, 4030
7511 10:05:44.207978 272 : 4250, 4027
7512 10:05:44.211096 276 : 4250, 4026
7513 10:05:44.211214 280 : 4250, 4027
7514 10:05:44.214648 284 : 4252, 4030
7515 10:05:44.214767 288 : 4250, 4027
7516 10:05:44.217600 292 : 4360, 4137
7517 10:05:44.217720 296 : 4363, 4137
7518 10:05:44.221082 300 : 4250, 4027
7519 10:05:44.221212 304 : 4363, 4140
7520 10:05:44.224720 308 : 4361, 4123
7521 10:05:44.224846 312 : 4250, 2122
7522 10:05:44.224988
7523 10:05:44.227646 MIOCK jitter meter ch=0
7524 10:05:44.227763
7525 10:05:44.231252 1T = (312-88) = 224 dly cells
7526 10:05:44.234258 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7527 10:05:44.234379 ==
7528 10:05:44.237843 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 10:05:44.244534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 10:05:44.244640 ==
7531 10:05:44.247724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 10:05:44.254696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 10:05:44.257722 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 10:05:44.264474 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 10:05:44.272289 [CA 0] Center 43 (13~74) winsize 62
7536 10:05:44.275535 [CA 1] Center 43 (12~74) winsize 63
7537 10:05:44.278972 [CA 2] Center 38 (9~68) winsize 60
7538 10:05:44.282718 [CA 3] Center 38 (8~68) winsize 61
7539 10:05:44.285678 [CA 4] Center 37 (7~67) winsize 61
7540 10:05:44.288742 [CA 5] Center 36 (7~65) winsize 59
7541 10:05:44.288839
7542 10:05:44.291902 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 10:05:44.292029
7544 10:05:44.295775 [CATrainingPosCal] consider 1 rank data
7545 10:05:44.299198 u2DelayCellTimex100 = 290/100 ps
7546 10:05:44.302505 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7547 10:05:44.308495 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7548 10:05:44.312210 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7549 10:05:44.315333 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7550 10:05:44.319073 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7551 10:05:44.322148 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7552 10:05:44.322269
7553 10:05:44.325770 CA PerBit enable=1, Macro0, CA PI delay=36
7554 10:05:44.325863
7555 10:05:44.328867 [CBTSetCACLKResult] CA Dly = 36
7556 10:05:44.332313 CS Dly: 9 (0~40)
7557 10:05:44.335620 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 10:05:44.338667 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 10:05:44.338763 ==
7560 10:05:44.342043 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 10:05:44.345454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 10:05:44.345565 ==
7563 10:05:44.351941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 10:05:44.355648 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 10:05:44.362069 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 10:05:44.365453 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 10:05:44.375724 [CA 0] Center 43 (13~73) winsize 61
7568 10:05:44.378830 [CA 1] Center 43 (13~73) winsize 61
7569 10:05:44.381937 [CA 2] Center 38 (8~68) winsize 61
7570 10:05:44.385382 [CA 3] Center 38 (8~68) winsize 61
7571 10:05:44.388512 [CA 4] Center 36 (6~66) winsize 61
7572 10:05:44.391837 [CA 5] Center 35 (6~65) winsize 60
7573 10:05:44.391935
7574 10:05:44.395672 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7575 10:05:44.395767
7576 10:05:44.398374 [CATrainingPosCal] consider 2 rank data
7577 10:05:44.401748 u2DelayCellTimex100 = 290/100 ps
7578 10:05:44.405080 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7579 10:05:44.411619 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7580 10:05:44.415355 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7581 10:05:44.418660 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7582 10:05:44.422086 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7583 10:05:44.425602 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7584 10:05:44.425695
7585 10:05:44.428629 CA PerBit enable=1, Macro0, CA PI delay=36
7586 10:05:44.428716
7587 10:05:44.431983 [CBTSetCACLKResult] CA Dly = 36
7588 10:05:44.435110 CS Dly: 10 (0~42)
7589 10:05:44.438448 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 10:05:44.441703 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 10:05:44.441792
7592 10:05:44.444868 ----->DramcWriteLeveling(PI) begin...
7593 10:05:44.444983 ==
7594 10:05:44.447956 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 10:05:44.455143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 10:05:44.455250 ==
7597 10:05:44.458396 Write leveling (Byte 0): 37 => 37
7598 10:05:44.458481 Write leveling (Byte 1): 28 => 28
7599 10:05:44.461544 DramcWriteLeveling(PI) end<-----
7600 10:05:44.461643
7601 10:05:44.461709 ==
7602 10:05:44.464983 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 10:05:44.472038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 10:05:44.472137 ==
7605 10:05:44.475233 [Gating] SW mode calibration
7606 10:05:44.481809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 10:05:44.485209 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 10:05:44.491474 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7609 10:05:44.495227 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7610 10:05:44.498413 1 4 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7611 10:05:44.505432 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7612 10:05:44.508156 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7613 10:05:44.511835 1 4 20 | B1->B0 | 3434 3736 | 0 1 | (0 0) (1 1)
7614 10:05:44.515140 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7615 10:05:44.521490 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7616 10:05:44.524852 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7617 10:05:44.528622 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 10:05:44.534962 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
7619 10:05:44.538574 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7620 10:05:44.541666 1 5 16 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (0 0)
7621 10:05:44.548407 1 5 20 | B1->B0 | 2727 2626 | 0 0 | (1 0) (0 0)
7622 10:05:44.551895 1 5 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7623 10:05:44.554965 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7624 10:05:44.561498 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7625 10:05:44.564769 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7626 10:05:44.568353 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7627 10:05:44.574586 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7628 10:05:44.578169 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
7629 10:05:44.581611 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7630 10:05:44.587947 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7631 10:05:44.591721 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 10:05:44.594623 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 10:05:44.601078 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 10:05:44.604471 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 10:05:44.607636 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 10:05:44.614435 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7637 10:05:44.617828 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 10:05:44.621036 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 10:05:44.628194 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:05:44.631400 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 10:05:44.634732 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 10:05:44.641170 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 10:05:44.644272 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 10:05:44.647970 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 10:05:44.650948 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 10:05:44.657546 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 10:05:44.661164 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 10:05:44.664496 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 10:05:44.671088 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 10:05:44.674257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 10:05:44.677446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 10:05:44.684622 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 10:05:44.687475 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7654 10:05:44.690798 Total UI for P1: 0, mck2ui 16
7655 10:05:44.694268 best dqsien dly found for B0: ( 1, 9, 14)
7656 10:05:44.697683 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 10:05:44.700930 Total UI for P1: 0, mck2ui 16
7658 10:05:44.703973 best dqsien dly found for B1: ( 1, 9, 20)
7659 10:05:44.707480 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7660 10:05:44.711032 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7661 10:05:44.711124
7662 10:05:44.717619 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7663 10:05:44.721027 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7664 10:05:44.724166 [Gating] SW calibration Done
7665 10:05:44.724267 ==
7666 10:05:44.727335 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 10:05:44.731169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 10:05:44.731259 ==
7669 10:05:44.731327 RX Vref Scan: 0
7670 10:05:44.731389
7671 10:05:44.734397 RX Vref 0 -> 0, step: 1
7672 10:05:44.734483
7673 10:05:44.737573 RX Delay 0 -> 252, step: 8
7674 10:05:44.740871 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7675 10:05:44.744074 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7676 10:05:44.750998 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7677 10:05:44.754065 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7678 10:05:44.757289 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7679 10:05:44.761114 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7680 10:05:44.763678 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7681 10:05:44.767198 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7682 10:05:44.774230 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7683 10:05:44.777449 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7684 10:05:44.780742 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7685 10:05:44.783994 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7686 10:05:44.787247 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7687 10:05:44.794245 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7688 10:05:44.797331 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7689 10:05:44.800676 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7690 10:05:44.800757 ==
7691 10:05:44.803903 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 10:05:44.807365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 10:05:44.810283 ==
7694 10:05:44.810388 DQS Delay:
7695 10:05:44.810455 DQS0 = 0, DQS1 = 0
7696 10:05:44.813776 DQM Delay:
7697 10:05:44.813910 DQM0 = 136, DQM1 = 129
7698 10:05:44.817719 DQ Delay:
7699 10:05:44.820329 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7700 10:05:44.823904 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7701 10:05:44.827431 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7702 10:05:44.831124 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7703 10:05:44.831277
7704 10:05:44.831392
7705 10:05:44.831466 ==
7706 10:05:44.834243 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 10:05:44.837006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 10:05:44.837094 ==
7709 10:05:44.837163
7710 10:05:44.837252
7711 10:05:44.840610 TX Vref Scan disable
7712 10:05:44.843885 == TX Byte 0 ==
7713 10:05:44.847100 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7714 10:05:44.850682 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7715 10:05:44.853875 == TX Byte 1 ==
7716 10:05:44.857125 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7717 10:05:44.860908 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7718 10:05:44.860999 ==
7719 10:05:44.864070 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 10:05:44.870247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 10:05:44.870341 ==
7722 10:05:44.881776
7723 10:05:44.885096 TX Vref early break, caculate TX vref
7724 10:05:44.888264 TX Vref=16, minBit 7, minWin=22, winSum=380
7725 10:05:44.891336 TX Vref=18, minBit 0, minWin=23, winSum=388
7726 10:05:44.894417 TX Vref=20, minBit 0, minWin=24, winSum=402
7727 10:05:44.898382 TX Vref=22, minBit 2, minWin=24, winSum=406
7728 10:05:44.901548 TX Vref=24, minBit 7, minWin=24, winSum=420
7729 10:05:44.907873 TX Vref=26, minBit 0, minWin=25, winSum=424
7730 10:05:44.911534 TX Vref=28, minBit 1, minWin=25, winSum=420
7731 10:05:44.914887 TX Vref=30, minBit 1, minWin=24, winSum=410
7732 10:05:44.917887 TX Vref=32, minBit 6, minWin=23, winSum=400
7733 10:05:44.924478 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
7734 10:05:44.924606
7735 10:05:44.927840 Final TX Range 0 Vref 26
7736 10:05:44.927957
7737 10:05:44.928054 ==
7738 10:05:44.931311 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 10:05:44.934850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 10:05:44.934938 ==
7741 10:05:44.935006
7742 10:05:44.935070
7743 10:05:44.938323 TX Vref Scan disable
7744 10:05:44.944365 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7745 10:05:44.944455 == TX Byte 0 ==
7746 10:05:44.947846 u2DelayCellOfst[0]=13 cells (4 PI)
7747 10:05:44.950936 u2DelayCellOfst[1]=16 cells (5 PI)
7748 10:05:44.954092 u2DelayCellOfst[2]=10 cells (3 PI)
7749 10:05:44.958038 u2DelayCellOfst[3]=10 cells (3 PI)
7750 10:05:44.961144 u2DelayCellOfst[4]=10 cells (3 PI)
7751 10:05:44.964397 u2DelayCellOfst[5]=0 cells (0 PI)
7752 10:05:44.967494 u2DelayCellOfst[6]=16 cells (5 PI)
7753 10:05:44.967580 u2DelayCellOfst[7]=20 cells (6 PI)
7754 10:05:44.974633 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7755 10:05:44.977735 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7756 10:05:44.977821 == TX Byte 1 ==
7757 10:05:44.980769 u2DelayCellOfst[8]=0 cells (0 PI)
7758 10:05:44.984536 u2DelayCellOfst[9]=0 cells (0 PI)
7759 10:05:44.988020 u2DelayCellOfst[10]=6 cells (2 PI)
7760 10:05:44.990984 u2DelayCellOfst[11]=3 cells (1 PI)
7761 10:05:44.994853 u2DelayCellOfst[12]=10 cells (3 PI)
7762 10:05:44.998033 u2DelayCellOfst[13]=13 cells (4 PI)
7763 10:05:45.001348 u2DelayCellOfst[14]=16 cells (5 PI)
7764 10:05:45.004344 u2DelayCellOfst[15]=10 cells (3 PI)
7765 10:05:45.007645 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7766 10:05:45.010708 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7767 10:05:45.014593 DramC Write-DBI on
7768 10:05:45.014686 ==
7769 10:05:45.017870 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 10:05:45.020755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 10:05:45.020845 ==
7772 10:05:45.020911
7773 10:05:45.024273
7774 10:05:45.024359 TX Vref Scan disable
7775 10:05:45.027566 == TX Byte 0 ==
7776 10:05:45.031333 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7777 10:05:45.034455 == TX Byte 1 ==
7778 10:05:45.037834 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7779 10:05:45.037927 DramC Write-DBI off
7780 10:05:45.037995
7781 10:05:45.040591 [DATLAT]
7782 10:05:45.040678 Freq=1600, CH0 RK0
7783 10:05:45.040747
7784 10:05:45.044062 DATLAT Default: 0xf
7785 10:05:45.044153 0, 0xFFFF, sum = 0
7786 10:05:45.047221 1, 0xFFFF, sum = 0
7787 10:05:45.047310 2, 0xFFFF, sum = 0
7788 10:05:45.050964 3, 0xFFFF, sum = 0
7789 10:05:45.051057 4, 0xFFFF, sum = 0
7790 10:05:45.054178 5, 0xFFFF, sum = 0
7791 10:05:45.054269 6, 0xFFFF, sum = 0
7792 10:05:45.057842 7, 0xFFFF, sum = 0
7793 10:05:45.060995 8, 0xFFFF, sum = 0
7794 10:05:45.061106 9, 0xFFFF, sum = 0
7795 10:05:45.064032 10, 0xFFFF, sum = 0
7796 10:05:45.064143 11, 0xFFFF, sum = 0
7797 10:05:45.067649 12, 0xFFFF, sum = 0
7798 10:05:45.067730 13, 0xFFFF, sum = 0
7799 10:05:45.070786 14, 0x0, sum = 1
7800 10:05:45.070868 15, 0x0, sum = 2
7801 10:05:45.074048 16, 0x0, sum = 3
7802 10:05:45.074126 17, 0x0, sum = 4
7803 10:05:45.077222 best_step = 15
7804 10:05:45.077297
7805 10:05:45.077360 ==
7806 10:05:45.081005 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 10:05:45.083994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 10:05:45.084084 ==
7809 10:05:45.084153 RX Vref Scan: 1
7810 10:05:45.084216
7811 10:05:45.087247 Set Vref Range= 24 -> 127
7812 10:05:45.087335
7813 10:05:45.090919 RX Vref 24 -> 127, step: 1
7814 10:05:45.091007
7815 10:05:45.094093 RX Delay 19 -> 252, step: 4
7816 10:05:45.094210
7817 10:05:45.097111 Set Vref, RX VrefLevel [Byte0]: 24
7818 10:05:45.100417 [Byte1]: 24
7819 10:05:45.100523
7820 10:05:45.103914 Set Vref, RX VrefLevel [Byte0]: 25
7821 10:05:45.107599 [Byte1]: 25
7822 10:05:45.107718
7823 10:05:45.110904 Set Vref, RX VrefLevel [Byte0]: 26
7824 10:05:45.113512 [Byte1]: 26
7825 10:05:45.117385
7826 10:05:45.117501 Set Vref, RX VrefLevel [Byte0]: 27
7827 10:05:45.120578 [Byte1]: 27
7828 10:05:45.124909
7829 10:05:45.124999 Set Vref, RX VrefLevel [Byte0]: 28
7830 10:05:45.128524 [Byte1]: 28
7831 10:05:45.132567
7832 10:05:45.132662 Set Vref, RX VrefLevel [Byte0]: 29
7833 10:05:45.136436 [Byte1]: 29
7834 10:05:45.140123
7835 10:05:45.140212 Set Vref, RX VrefLevel [Byte0]: 30
7836 10:05:45.143309 [Byte1]: 30
7837 10:05:45.147931
7838 10:05:45.148020 Set Vref, RX VrefLevel [Byte0]: 31
7839 10:05:45.151012 [Byte1]: 31
7840 10:05:45.155342
7841 10:05:45.155435 Set Vref, RX VrefLevel [Byte0]: 32
7842 10:05:45.158524 [Byte1]: 32
7843 10:05:45.163303
7844 10:05:45.163396 Set Vref, RX VrefLevel [Byte0]: 33
7845 10:05:45.166394 [Byte1]: 33
7846 10:05:45.170254
7847 10:05:45.170351 Set Vref, RX VrefLevel [Byte0]: 34
7848 10:05:45.173668 [Byte1]: 34
7849 10:05:45.178471
7850 10:05:45.178568 Set Vref, RX VrefLevel [Byte0]: 35
7851 10:05:45.181432 [Byte1]: 35
7852 10:05:45.185895
7853 10:05:45.185992 Set Vref, RX VrefLevel [Byte0]: 36
7854 10:05:45.188999 [Byte1]: 36
7855 10:05:45.193415
7856 10:05:45.193534 Set Vref, RX VrefLevel [Byte0]: 37
7857 10:05:45.196603 [Byte1]: 37
7858 10:05:45.201031
7859 10:05:45.201123 Set Vref, RX VrefLevel [Byte0]: 38
7860 10:05:45.204290 [Byte1]: 38
7861 10:05:45.208735
7862 10:05:45.208861 Set Vref, RX VrefLevel [Byte0]: 39
7863 10:05:45.211529 [Byte1]: 39
7864 10:05:45.216223
7865 10:05:45.216343 Set Vref, RX VrefLevel [Byte0]: 40
7866 10:05:45.219509 [Byte1]: 40
7867 10:05:45.223695
7868 10:05:45.223786 Set Vref, RX VrefLevel [Byte0]: 41
7869 10:05:45.226906 [Byte1]: 41
7870 10:05:45.231327
7871 10:05:45.231423 Set Vref, RX VrefLevel [Byte0]: 42
7872 10:05:45.234435 [Byte1]: 42
7873 10:05:45.238537
7874 10:05:45.238624 Set Vref, RX VrefLevel [Byte0]: 43
7875 10:05:45.242114 [Byte1]: 43
7876 10:05:45.246069
7877 10:05:45.246184 Set Vref, RX VrefLevel [Byte0]: 44
7878 10:05:45.249702 [Byte1]: 44
7879 10:05:45.253850
7880 10:05:45.253957 Set Vref, RX VrefLevel [Byte0]: 45
7881 10:05:45.256989 [Byte1]: 45
7882 10:05:45.261131
7883 10:05:45.261219 Set Vref, RX VrefLevel [Byte0]: 46
7884 10:05:45.264486 [Byte1]: 46
7885 10:05:45.268755
7886 10:05:45.268842 Set Vref, RX VrefLevel [Byte0]: 47
7887 10:05:45.272598 [Byte1]: 47
7888 10:05:45.276467
7889 10:05:45.276584 Set Vref, RX VrefLevel [Byte0]: 48
7890 10:05:45.280024 [Byte1]: 48
7891 10:05:45.284108
7892 10:05:45.284234 Set Vref, RX VrefLevel [Byte0]: 49
7893 10:05:45.287314 [Byte1]: 49
7894 10:05:45.291503
7895 10:05:45.291597 Set Vref, RX VrefLevel [Byte0]: 50
7896 10:05:45.294941 [Byte1]: 50
7897 10:05:45.299574
7898 10:05:45.299690 Set Vref, RX VrefLevel [Byte0]: 51
7899 10:05:45.302705 [Byte1]: 51
7900 10:05:45.306647
7901 10:05:45.306732 Set Vref, RX VrefLevel [Byte0]: 52
7902 10:05:45.310554 [Byte1]: 52
7903 10:05:45.314229
7904 10:05:45.314357 Set Vref, RX VrefLevel [Byte0]: 53
7905 10:05:45.318035 [Byte1]: 53
7906 10:05:45.322009
7907 10:05:45.322153 Set Vref, RX VrefLevel [Byte0]: 54
7908 10:05:45.325441 [Byte1]: 54
7909 10:05:45.329630
7910 10:05:45.329775 Set Vref, RX VrefLevel [Byte0]: 55
7911 10:05:45.332803 [Byte1]: 55
7912 10:05:45.337214
7913 10:05:45.337358 Set Vref, RX VrefLevel [Byte0]: 56
7914 10:05:45.340442 [Byte1]: 56
7915 10:05:45.344607
7916 10:05:45.344731 Set Vref, RX VrefLevel [Byte0]: 57
7917 10:05:45.348165 [Byte1]: 57
7918 10:05:45.352068
7919 10:05:45.352162 Set Vref, RX VrefLevel [Byte0]: 58
7920 10:05:45.355864 [Byte1]: 58
7921 10:05:45.359655
7922 10:05:45.359746 Set Vref, RX VrefLevel [Byte0]: 59
7923 10:05:45.363416 [Byte1]: 59
7924 10:05:45.367251
7925 10:05:45.367345 Set Vref, RX VrefLevel [Byte0]: 60
7926 10:05:45.370426 [Byte1]: 60
7927 10:05:45.374707
7928 10:05:45.374821 Set Vref, RX VrefLevel [Byte0]: 61
7929 10:05:45.378606 [Byte1]: 61
7930 10:05:45.382455
7931 10:05:45.382552 Set Vref, RX VrefLevel [Byte0]: 62
7932 10:05:45.385598 [Byte1]: 62
7933 10:05:45.390465
7934 10:05:45.390583 Set Vref, RX VrefLevel [Byte0]: 63
7935 10:05:45.393369 [Byte1]: 63
7936 10:05:45.397777
7937 10:05:45.397896 Set Vref, RX VrefLevel [Byte0]: 64
7938 10:05:45.400811 [Byte1]: 64
7939 10:05:45.405074
7940 10:05:45.405168 Set Vref, RX VrefLevel [Byte0]: 65
7941 10:05:45.408990 [Byte1]: 65
7942 10:05:45.412750
7943 10:05:45.412872 Set Vref, RX VrefLevel [Byte0]: 66
7944 10:05:45.416298 [Byte1]: 66
7945 10:05:45.420613
7946 10:05:45.420705 Set Vref, RX VrefLevel [Byte0]: 67
7947 10:05:45.423806 [Byte1]: 67
7948 10:05:45.428104
7949 10:05:45.428192 Set Vref, RX VrefLevel [Byte0]: 68
7950 10:05:45.431276 [Byte1]: 68
7951 10:05:45.435712
7952 10:05:45.435802 Set Vref, RX VrefLevel [Byte0]: 69
7953 10:05:45.438595 [Byte1]: 69
7954 10:05:45.443141
7955 10:05:45.443256 Set Vref, RX VrefLevel [Byte0]: 70
7956 10:05:45.446440 [Byte1]: 70
7957 10:05:45.450909
7958 10:05:45.451021 Set Vref, RX VrefLevel [Byte0]: 71
7959 10:05:45.453897 [Byte1]: 71
7960 10:05:45.458115
7961 10:05:45.458204 Set Vref, RX VrefLevel [Byte0]: 72
7962 10:05:45.461980 [Byte1]: 72
7963 10:05:45.465501
7964 10:05:45.468699 Set Vref, RX VrefLevel [Byte0]: 73
7965 10:05:45.471964 [Byte1]: 73
7966 10:05:45.472079
7967 10:05:45.475472 Set Vref, RX VrefLevel [Byte0]: 74
7968 10:05:45.478775 [Byte1]: 74
7969 10:05:45.478861
7970 10:05:45.482266 Set Vref, RX VrefLevel [Byte0]: 75
7971 10:05:45.485483 [Byte1]: 75
7972 10:05:45.485586
7973 10:05:45.488751 Set Vref, RX VrefLevel [Byte0]: 76
7974 10:05:45.492136 [Byte1]: 76
7975 10:05:45.496387
7976 10:05:45.496477 Set Vref, RX VrefLevel [Byte0]: 77
7977 10:05:45.499320 [Byte1]: 77
7978 10:05:45.503655
7979 10:05:45.503774 Final RX Vref Byte 0 = 55 to rank0
7980 10:05:45.506825 Final RX Vref Byte 1 = 60 to rank0
7981 10:05:45.510466 Final RX Vref Byte 0 = 55 to rank1
7982 10:05:45.513439 Final RX Vref Byte 1 = 60 to rank1==
7983 10:05:45.516675 Dram Type= 6, Freq= 0, CH_0, rank 0
7984 10:05:45.523781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 10:05:45.523881 ==
7986 10:05:45.523949 DQS Delay:
7987 10:05:45.524048 DQS0 = 0, DQS1 = 0
7988 10:05:45.527210 DQM Delay:
7989 10:05:45.527304 DQM0 = 134, DQM1 = 127
7990 10:05:45.530220 DQ Delay:
7991 10:05:45.533487 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7992 10:05:45.537101 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7993 10:05:45.540130 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7994 10:05:45.543747 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7995 10:05:45.543858
7996 10:05:45.543963
7997 10:05:45.544065
7998 10:05:45.547004 [DramC_TX_OE_Calibration] TA2
7999 10:05:45.550589 Original DQ_B0 (3 6) =30, OEN = 27
8000 10:05:45.553819 Original DQ_B1 (3 6) =30, OEN = 27
8001 10:05:45.556960 24, 0x0, End_B0=24 End_B1=24
8002 10:05:45.557040 25, 0x0, End_B0=25 End_B1=25
8003 10:05:45.560142 26, 0x0, End_B0=26 End_B1=26
8004 10:05:45.563611 27, 0x0, End_B0=27 End_B1=27
8005 10:05:45.567059 28, 0x0, End_B0=28 End_B1=28
8006 10:05:45.567151 29, 0x0, End_B0=29 End_B1=29
8007 10:05:45.570155 30, 0x0, End_B0=30 End_B1=30
8008 10:05:45.573788 31, 0x4141, End_B0=30 End_B1=30
8009 10:05:45.576973 Byte0 end_step=30 best_step=27
8010 10:05:45.579930 Byte1 end_step=30 best_step=27
8011 10:05:45.583144 Byte0 TX OE(2T, 0.5T) = (3, 3)
8012 10:05:45.583254 Byte1 TX OE(2T, 0.5T) = (3, 3)
8013 10:05:45.587063
8014 10:05:45.587181
8015 10:05:45.593458 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8016 10:05:45.596709 CH0 RK0: MR19=303, MR18=2723
8017 10:05:45.603630 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
8018 10:05:45.603731
8019 10:05:45.606699 ----->DramcWriteLeveling(PI) begin...
8020 10:05:45.606790 ==
8021 10:05:45.610280 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 10:05:45.613420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 10:05:45.613537 ==
8024 10:05:45.617002 Write leveling (Byte 0): 36 => 36
8025 10:05:45.620031 Write leveling (Byte 1): 28 => 28
8026 10:05:45.623113 DramcWriteLeveling(PI) end<-----
8027 10:05:45.623205
8028 10:05:45.623285 ==
8029 10:05:45.626567 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 10:05:45.629586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 10:05:45.629676 ==
8032 10:05:45.633544 [Gating] SW mode calibration
8033 10:05:45.639943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8034 10:05:45.646792 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8035 10:05:45.650024 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 10:05:45.653074 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 10:05:45.659698 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 10:05:45.662940 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 10:05:45.666743 1 4 16 | B1->B0 | 3030 3635 | 1 1 | (0 0) (1 1)
8040 10:05:45.672894 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8041 10:05:45.676204 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8042 10:05:45.679709 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 10:05:45.686109 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8044 10:05:45.689782 1 5 4 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (0 0)
8045 10:05:45.693017 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8046 10:05:45.699911 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 0) (0 1)
8047 10:05:45.703360 1 5 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
8048 10:05:45.706633 1 5 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8049 10:05:45.712836 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8050 10:05:45.716293 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8051 10:05:45.719950 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8052 10:05:45.726604 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8053 10:05:45.729169 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8054 10:05:45.733032 1 6 12 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
8055 10:05:45.739542 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8056 10:05:45.742813 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 10:05:45.745855 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 10:05:45.752952 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 10:05:45.755879 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 10:05:45.759481 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 10:05:45.766291 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 10:05:45.769510 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8063 10:05:45.772784 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8064 10:05:45.779124 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 10:05:45.782405 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 10:05:45.785631 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 10:05:45.789113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 10:05:45.795801 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 10:05:45.798900 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 10:05:45.802273 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 10:05:45.809216 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 10:05:45.812595 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 10:05:45.815764 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 10:05:45.822375 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 10:05:45.825780 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 10:05:45.828704 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 10:05:45.835525 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 10:05:45.838831 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8079 10:05:45.841923 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8080 10:05:45.845778 Total UI for P1: 0, mck2ui 16
8081 10:05:45.848952 best dqsien dly found for B1: ( 1, 9, 12)
8082 10:05:45.855460 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 10:05:45.855560 Total UI for P1: 0, mck2ui 16
8084 10:05:45.862316 best dqsien dly found for B0: ( 1, 9, 14)
8085 10:05:45.865289 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8086 10:05:45.868846 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8087 10:05:45.868940
8088 10:05:45.871902 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8089 10:05:45.875695 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8090 10:05:45.878841 [Gating] SW calibration Done
8091 10:05:45.878933 ==
8092 10:05:45.882127 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 10:05:45.885288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 10:05:45.885383 ==
8095 10:05:45.889034 RX Vref Scan: 0
8096 10:05:45.889123
8097 10:05:45.889191 RX Vref 0 -> 0, step: 1
8098 10:05:45.889254
8099 10:05:45.891908 RX Delay 0 -> 252, step: 8
8100 10:05:45.895575 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8101 10:05:45.902166 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8102 10:05:45.905337 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8103 10:05:45.908358 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8104 10:05:45.911963 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8105 10:05:45.915106 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8106 10:05:45.921966 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8107 10:05:45.925108 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8108 10:05:45.928841 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8109 10:05:45.931706 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8110 10:05:45.935177 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8111 10:05:45.941619 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8112 10:05:45.945296 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8113 10:05:45.948312 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8114 10:05:45.952057 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8115 10:05:45.958516 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8116 10:05:45.958680 ==
8117 10:05:45.961727 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 10:05:45.964876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 10:05:45.964971 ==
8120 10:05:45.965038 DQS Delay:
8121 10:05:45.968579 DQS0 = 0, DQS1 = 0
8122 10:05:45.968665 DQM Delay:
8123 10:05:45.971614 DQM0 = 137, DQM1 = 128
8124 10:05:45.971700 DQ Delay:
8125 10:05:45.975163 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8126 10:05:45.978232 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =147
8127 10:05:45.981827 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8128 10:05:45.985142 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8129 10:05:45.985237
8130 10:05:45.985306
8131 10:05:45.988367 ==
8132 10:05:45.991450 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 10:05:45.994539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 10:05:45.994627 ==
8135 10:05:45.994694
8136 10:05:45.994755
8137 10:05:45.998439 TX Vref Scan disable
8138 10:05:45.998526 == TX Byte 0 ==
8139 10:05:46.001608 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8140 10:05:46.007869 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8141 10:05:46.008006 == TX Byte 1 ==
8142 10:05:46.011345 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8143 10:05:46.017736 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8144 10:05:46.017875 ==
8145 10:05:46.021469 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 10:05:46.024852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 10:05:46.024985 ==
8148 10:05:46.039677
8149 10:05:46.043037 TX Vref early break, caculate TX vref
8150 10:05:46.046423 TX Vref=16, minBit 1, minWin=23, winSum=384
8151 10:05:46.050098 TX Vref=18, minBit 3, minWin=23, winSum=396
8152 10:05:46.052963 TX Vref=20, minBit 1, minWin=23, winSum=404
8153 10:05:46.056536 TX Vref=22, minBit 1, minWin=24, winSum=411
8154 10:05:46.059691 TX Vref=24, minBit 1, minWin=25, winSum=423
8155 10:05:46.066008 TX Vref=26, minBit 0, minWin=25, winSum=425
8156 10:05:46.069302 TX Vref=28, minBit 3, minWin=25, winSum=425
8157 10:05:46.073063 TX Vref=30, minBit 6, minWin=25, winSum=418
8158 10:05:46.076130 TX Vref=32, minBit 2, minWin=24, winSum=407
8159 10:05:46.079847 TX Vref=34, minBit 3, minWin=24, winSum=403
8160 10:05:46.082898 TX Vref=36, minBit 0, minWin=23, winSum=388
8161 10:05:46.090104 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8162 10:05:46.090261
8163 10:05:46.093116 Final TX Range 0 Vref 26
8164 10:05:46.093234
8165 10:05:46.093338 ==
8166 10:05:46.096185 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 10:05:46.099206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 10:05:46.099331 ==
8169 10:05:46.099438
8170 10:05:46.102928
8171 10:05:46.103045 TX Vref Scan disable
8172 10:05:46.109298 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8173 10:05:46.109418 == TX Byte 0 ==
8174 10:05:46.112560 u2DelayCellOfst[0]=10 cells (3 PI)
8175 10:05:46.116333 u2DelayCellOfst[1]=13 cells (4 PI)
8176 10:05:46.119383 u2DelayCellOfst[2]=6 cells (2 PI)
8177 10:05:46.122738 u2DelayCellOfst[3]=10 cells (3 PI)
8178 10:05:46.126025 u2DelayCellOfst[4]=6 cells (2 PI)
8179 10:05:46.129882 u2DelayCellOfst[5]=0 cells (0 PI)
8180 10:05:46.133082 u2DelayCellOfst[6]=13 cells (4 PI)
8181 10:05:46.136141 u2DelayCellOfst[7]=16 cells (5 PI)
8182 10:05:46.139877 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8183 10:05:46.143060 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8184 10:05:46.146123 == TX Byte 1 ==
8185 10:05:46.149153 u2DelayCellOfst[8]=3 cells (1 PI)
8186 10:05:46.152682 u2DelayCellOfst[9]=0 cells (0 PI)
8187 10:05:46.152800 u2DelayCellOfst[10]=6 cells (2 PI)
8188 10:05:46.156260 u2DelayCellOfst[11]=6 cells (2 PI)
8189 10:05:46.159079 u2DelayCellOfst[12]=10 cells (3 PI)
8190 10:05:46.162671 u2DelayCellOfst[13]=10 cells (3 PI)
8191 10:05:46.166296 u2DelayCellOfst[14]=13 cells (4 PI)
8192 10:05:46.169502 u2DelayCellOfst[15]=10 cells (3 PI)
8193 10:05:46.172710 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8194 10:05:46.179147 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8195 10:05:46.179269 DramC Write-DBI on
8196 10:05:46.179373 ==
8197 10:05:46.182445 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 10:05:46.189299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 10:05:46.189468 ==
8200 10:05:46.189582
8201 10:05:46.189713
8202 10:05:46.189811 TX Vref Scan disable
8203 10:05:46.193385 == TX Byte 0 ==
8204 10:05:46.196554 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8205 10:05:46.199758 == TX Byte 1 ==
8206 10:05:46.203261 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8207 10:05:46.206535 DramC Write-DBI off
8208 10:05:46.206655
8209 10:05:46.206760 [DATLAT]
8210 10:05:46.206886 Freq=1600, CH0 RK1
8211 10:05:46.207001
8212 10:05:46.210123 DATLAT Default: 0xf
8213 10:05:46.210238 0, 0xFFFF, sum = 0
8214 10:05:46.213404 1, 0xFFFF, sum = 0
8215 10:05:46.213537 2, 0xFFFF, sum = 0
8216 10:05:46.216429 3, 0xFFFF, sum = 0
8217 10:05:46.219599 4, 0xFFFF, sum = 0
8218 10:05:46.219755 5, 0xFFFF, sum = 0
8219 10:05:46.223549 6, 0xFFFF, sum = 0
8220 10:05:46.223672 7, 0xFFFF, sum = 0
8221 10:05:46.226412 8, 0xFFFF, sum = 0
8222 10:05:46.226529 9, 0xFFFF, sum = 0
8223 10:05:46.229895 10, 0xFFFF, sum = 0
8224 10:05:46.230024 11, 0xFFFF, sum = 0
8225 10:05:46.233119 12, 0xFFFF, sum = 0
8226 10:05:46.233241 13, 0xFFFF, sum = 0
8227 10:05:46.236386 14, 0x0, sum = 1
8228 10:05:46.236504 15, 0x0, sum = 2
8229 10:05:46.239558 16, 0x0, sum = 3
8230 10:05:46.239676 17, 0x0, sum = 4
8231 10:05:46.243401 best_step = 15
8232 10:05:46.243518
8233 10:05:46.243621 ==
8234 10:05:46.246409 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 10:05:46.249846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 10:05:46.249965 ==
8237 10:05:46.250070 RX Vref Scan: 0
8238 10:05:46.253343
8239 10:05:46.253459 RX Vref 0 -> 0, step: 1
8240 10:05:46.253562
8241 10:05:46.256584 RX Delay 19 -> 252, step: 4
8242 10:05:46.260083 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8243 10:05:46.266419 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8244 10:05:46.269354 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8245 10:05:46.272934 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8246 10:05:46.276175 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8247 10:05:46.279276 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8248 10:05:46.286144 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8249 10:05:46.289869 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8250 10:05:46.293249 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8251 10:05:46.296547 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8252 10:05:46.299530 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8253 10:05:46.302756 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8254 10:05:46.309753 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8255 10:05:46.313287 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8256 10:05:46.316156 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8257 10:05:46.319527 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8258 10:05:46.319672 ==
8259 10:05:46.323232 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 10:05:46.329411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 10:05:46.329513 ==
8262 10:05:46.329589 DQS Delay:
8263 10:05:46.332872 DQS0 = 0, DQS1 = 0
8264 10:05:46.332959 DQM Delay:
8265 10:05:46.336327 DQM0 = 134, DQM1 = 127
8266 10:05:46.336415 DQ Delay:
8267 10:05:46.339605 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8268 10:05:46.342814 DQ4 =134, DQ5 =126, DQ6 =140, DQ7 =142
8269 10:05:46.346126 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8270 10:05:46.349320 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8271 10:05:46.349440
8272 10:05:46.349534
8273 10:05:46.349664
8274 10:05:46.352553 [DramC_TX_OE_Calibration] TA2
8275 10:05:46.355772 Original DQ_B0 (3 6) =30, OEN = 27
8276 10:05:46.359219 Original DQ_B1 (3 6) =30, OEN = 27
8277 10:05:46.362477 24, 0x0, End_B0=24 End_B1=24
8278 10:05:46.365764 25, 0x0, End_B0=25 End_B1=25
8279 10:05:46.365897 26, 0x0, End_B0=26 End_B1=26
8280 10:05:46.369066 27, 0x0, End_B0=27 End_B1=27
8281 10:05:46.372359 28, 0x0, End_B0=28 End_B1=28
8282 10:05:46.375462 29, 0x0, End_B0=29 End_B1=29
8283 10:05:46.378759 30, 0x0, End_B0=30 End_B1=30
8284 10:05:46.378889 31, 0x4141, End_B0=30 End_B1=30
8285 10:05:46.382297 Byte0 end_step=30 best_step=27
8286 10:05:46.385272 Byte1 end_step=30 best_step=27
8287 10:05:46.389143 Byte0 TX OE(2T, 0.5T) = (3, 3)
8288 10:05:46.392497 Byte1 TX OE(2T, 0.5T) = (3, 3)
8289 10:05:46.392592
8290 10:05:46.392658
8291 10:05:46.398664 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8292 10:05:46.402431 CH0 RK1: MR19=303, MR18=220B
8293 10:05:46.408746 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8294 10:05:46.412477 [RxdqsGatingPostProcess] freq 1600
8295 10:05:46.419015 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8296 10:05:46.419108 best DQS0 dly(2T, 0.5T) = (1, 1)
8297 10:05:46.422054 best DQS1 dly(2T, 0.5T) = (1, 1)
8298 10:05:46.425585 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8299 10:05:46.428648 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8300 10:05:46.432190 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 10:05:46.435328 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 10:05:46.438948 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 10:05:46.442336 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 10:05:46.445449 Pre-setting of DQS Precalculation
8305 10:05:46.448677 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8306 10:05:46.448795 ==
8307 10:05:46.451964 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 10:05:46.458433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 10:05:46.458570 ==
8310 10:05:46.462270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 10:05:46.468786 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 10:05:46.471921 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 10:05:46.478721 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 10:05:46.486311 [CA 0] Center 42 (13~72) winsize 60
8315 10:05:46.489388 [CA 1] Center 42 (13~72) winsize 60
8316 10:05:46.492546 [CA 2] Center 39 (10~68) winsize 59
8317 10:05:46.495966 [CA 3] Center 38 (9~68) winsize 60
8318 10:05:46.499525 [CA 4] Center 38 (9~68) winsize 60
8319 10:05:46.502764 [CA 5] Center 37 (8~67) winsize 60
8320 10:05:46.502851
8321 10:05:46.505948 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8322 10:05:46.506031
8323 10:05:46.509855 [CATrainingPosCal] consider 1 rank data
8324 10:05:46.512865 u2DelayCellTimex100 = 290/100 ps
8325 10:05:46.515913 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8326 10:05:46.523026 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8327 10:05:46.526196 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8328 10:05:46.529205 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8329 10:05:46.533009 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8330 10:05:46.535920 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8331 10:05:46.536021
8332 10:05:46.539635 CA PerBit enable=1, Macro0, CA PI delay=37
8333 10:05:46.539723
8334 10:05:46.542654 [CBTSetCACLKResult] CA Dly = 37
8335 10:05:46.546252 CS Dly: 10 (0~41)
8336 10:05:46.549297 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 10:05:46.552718 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 10:05:46.552810 ==
8339 10:05:46.555880 Dram Type= 6, Freq= 0, CH_1, rank 1
8340 10:05:46.559102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 10:05:46.562920 ==
8342 10:05:46.566052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 10:05:46.569265 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 10:05:46.576403 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 10:05:46.579446 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 10:05:46.589910 [CA 0] Center 42 (12~72) winsize 61
8347 10:05:46.592937 [CA 1] Center 42 (13~72) winsize 60
8348 10:05:46.596535 [CA 2] Center 38 (9~68) winsize 60
8349 10:05:46.599466 [CA 3] Center 37 (8~67) winsize 60
8350 10:05:46.603198 [CA 4] Center 38 (9~68) winsize 60
8351 10:05:46.606213 [CA 5] Center 37 (8~67) winsize 60
8352 10:05:46.606302
8353 10:05:46.609534 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8354 10:05:46.609660
8355 10:05:46.612803 [CATrainingPosCal] consider 2 rank data
8356 10:05:46.616231 u2DelayCellTimex100 = 290/100 ps
8357 10:05:46.622761 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8358 10:05:46.625997 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8359 10:05:46.629115 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8360 10:05:46.632690 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8361 10:05:46.635993 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8362 10:05:46.639265 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8363 10:05:46.639351
8364 10:05:46.642999 CA PerBit enable=1, Macro0, CA PI delay=37
8365 10:05:46.643127
8366 10:05:46.646059 [CBTSetCACLKResult] CA Dly = 37
8367 10:05:46.649246 CS Dly: 11 (0~44)
8368 10:05:46.652306 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 10:05:46.655817 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 10:05:46.655941
8371 10:05:46.658786 ----->DramcWriteLeveling(PI) begin...
8372 10:05:46.658908 ==
8373 10:05:46.662423 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 10:05:46.668903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 10:05:46.669048 ==
8376 10:05:46.672760 Write leveling (Byte 0): 25 => 25
8377 10:05:46.672891 Write leveling (Byte 1): 27 => 27
8378 10:05:46.675929 DramcWriteLeveling(PI) end<-----
8379 10:05:46.676050
8380 10:05:46.679194 ==
8381 10:05:46.679314 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 10:05:46.686265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 10:05:46.686370 ==
8384 10:05:46.689006 [Gating] SW mode calibration
8385 10:05:46.695399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8386 10:05:46.699243 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8387 10:05:46.705310 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 10:05:46.709102 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 10:05:46.711979 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8390 10:05:46.718650 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8391 10:05:46.722264 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 10:05:46.725687 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 10:05:46.732168 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 10:05:46.735238 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 10:05:46.738969 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 10:05:46.745465 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 10:05:46.748665 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8398 10:05:46.752278 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
8399 10:05:46.758596 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 10:05:46.761813 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 10:05:46.765571 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 10:05:46.771685 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 10:05:46.775463 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 10:05:46.778820 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 10:05:46.782147 1 6 8 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
8406 10:05:46.788631 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8407 10:05:46.791810 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 10:05:46.795046 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 10:05:46.801941 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 10:05:46.804800 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 10:05:46.808702 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 10:05:46.815019 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 10:05:46.818058 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 10:05:46.821829 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8415 10:05:46.828230 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8416 10:05:46.831326 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 10:05:46.835000 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 10:05:46.841311 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 10:05:46.844736 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 10:05:46.848103 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 10:05:46.855066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 10:05:46.858335 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 10:05:46.861725 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 10:05:46.868547 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 10:05:46.871668 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 10:05:46.875243 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 10:05:46.881476 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 10:05:46.884795 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 10:05:46.888561 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8430 10:05:46.894923 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8431 10:05:46.898146 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 10:05:46.901291 Total UI for P1: 0, mck2ui 16
8433 10:05:46.904508 best dqsien dly found for B0: ( 1, 9, 10)
8434 10:05:46.908185 Total UI for P1: 0, mck2ui 16
8435 10:05:46.911102 best dqsien dly found for B1: ( 1, 9, 10)
8436 10:05:46.914577 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8437 10:05:46.918125 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8438 10:05:46.918270
8439 10:05:46.921138 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8440 10:05:46.924675 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8441 10:05:46.927749 [Gating] SW calibration Done
8442 10:05:46.927880 ==
8443 10:05:46.930999 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 10:05:46.934433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 10:05:46.937540 ==
8446 10:05:46.937676 RX Vref Scan: 0
8447 10:05:46.937788
8448 10:05:46.941371 RX Vref 0 -> 0, step: 1
8449 10:05:46.941495
8450 10:05:46.941617 RX Delay 0 -> 252, step: 8
8451 10:05:46.947538 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8452 10:05:46.951305 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8453 10:05:46.954464 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8454 10:05:46.958081 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8455 10:05:46.961345 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8456 10:05:46.967837 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8457 10:05:46.971246 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8458 10:05:46.974164 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8459 10:05:46.977875 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8460 10:05:46.981079 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8461 10:05:46.987920 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8462 10:05:46.991046 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8463 10:05:46.994233 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8464 10:05:46.997464 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8465 10:05:47.001324 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8466 10:05:47.007732 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8467 10:05:47.007825 ==
8468 10:05:47.010936 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 10:05:47.014235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 10:05:47.014321 ==
8471 10:05:47.014388 DQS Delay:
8472 10:05:47.017428 DQS0 = 0, DQS1 = 0
8473 10:05:47.017513 DQM Delay:
8474 10:05:47.020760 DQM0 = 136, DQM1 = 133
8475 10:05:47.020844 DQ Delay:
8476 10:05:47.024164 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8477 10:05:47.027570 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8478 10:05:47.031015 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8479 10:05:47.034470 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8480 10:05:47.034556
8481 10:05:47.037748
8482 10:05:47.037830 ==
8483 10:05:47.040855 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 10:05:47.044207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 10:05:47.044307 ==
8486 10:05:47.044402
8487 10:05:47.044476
8488 10:05:47.047307 TX Vref Scan disable
8489 10:05:47.047389 == TX Byte 0 ==
8490 10:05:47.051028 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8491 10:05:47.057552 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 10:05:47.057681 == TX Byte 1 ==
8493 10:05:47.061263 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8494 10:05:47.067624 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8495 10:05:47.067709 ==
8496 10:05:47.071201 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 10:05:47.074197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 10:05:47.074279 ==
8499 10:05:47.087265
8500 10:05:47.090361 TX Vref early break, caculate TX vref
8501 10:05:47.093715 TX Vref=16, minBit 0, minWin=22, winSum=379
8502 10:05:47.096871 TX Vref=18, minBit 0, minWin=23, winSum=383
8503 10:05:47.100351 TX Vref=20, minBit 0, minWin=24, winSum=400
8504 10:05:47.103449 TX Vref=22, minBit 0, minWin=24, winSum=406
8505 10:05:47.107351 TX Vref=24, minBit 1, minWin=25, winSum=415
8506 10:05:47.113772 TX Vref=26, minBit 0, minWin=25, winSum=426
8507 10:05:47.117033 TX Vref=28, minBit 0, minWin=25, winSum=430
8508 10:05:47.120209 TX Vref=30, minBit 0, minWin=25, winSum=419
8509 10:05:47.123384 TX Vref=32, minBit 6, minWin=24, winSum=417
8510 10:05:47.127196 TX Vref=34, minBit 0, minWin=24, winSum=406
8511 10:05:47.133924 [TxChooseVref] Worse bit 0, Min win 25, Win sum 430, Final Vref 28
8512 10:05:47.134026
8513 10:05:47.136870 Final TX Range 0 Vref 28
8514 10:05:47.137011
8515 10:05:47.137136 ==
8516 10:05:47.140351 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 10:05:47.143706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 10:05:47.143877 ==
8519 10:05:47.143963
8520 10:05:47.144025
8521 10:05:47.147013 TX Vref Scan disable
8522 10:05:47.154136 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8523 10:05:47.154221 == TX Byte 0 ==
8524 10:05:47.157369 u2DelayCellOfst[0]=16 cells (5 PI)
8525 10:05:47.160448 u2DelayCellOfst[1]=10 cells (3 PI)
8526 10:05:47.164008 u2DelayCellOfst[2]=0 cells (0 PI)
8527 10:05:47.167454 u2DelayCellOfst[3]=6 cells (2 PI)
8528 10:05:47.170231 u2DelayCellOfst[4]=6 cells (2 PI)
8529 10:05:47.173926 u2DelayCellOfst[5]=16 cells (5 PI)
8530 10:05:47.174010 u2DelayCellOfst[6]=16 cells (5 PI)
8531 10:05:47.177060 u2DelayCellOfst[7]=6 cells (2 PI)
8532 10:05:47.183629 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8533 10:05:47.187411 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8534 10:05:47.187505 == TX Byte 1 ==
8535 10:05:47.190490 u2DelayCellOfst[8]=0 cells (0 PI)
8536 10:05:47.193755 u2DelayCellOfst[9]=3 cells (1 PI)
8537 10:05:47.196842 u2DelayCellOfst[10]=13 cells (4 PI)
8538 10:05:47.200321 u2DelayCellOfst[11]=3 cells (1 PI)
8539 10:05:47.203713 u2DelayCellOfst[12]=13 cells (4 PI)
8540 10:05:47.206930 u2DelayCellOfst[13]=16 cells (5 PI)
8541 10:05:47.210083 u2DelayCellOfst[14]=16 cells (5 PI)
8542 10:05:47.213463 u2DelayCellOfst[15]=16 cells (5 PI)
8543 10:05:47.216784 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8544 10:05:47.220135 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8545 10:05:47.223679 DramC Write-DBI on
8546 10:05:47.223802 ==
8547 10:05:47.226892 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 10:05:47.230578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 10:05:47.230699 ==
8550 10:05:47.230811
8551 10:05:47.230916
8552 10:05:47.233830 TX Vref Scan disable
8553 10:05:47.236773 == TX Byte 0 ==
8554 10:05:47.240017 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8555 10:05:47.240140 == TX Byte 1 ==
8556 10:05:47.246835 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8557 10:05:47.246958 DramC Write-DBI off
8558 10:05:47.247069
8559 10:05:47.250316 [DATLAT]
8560 10:05:47.250437 Freq=1600, CH1 RK0
8561 10:05:47.250561
8562 10:05:47.253816 DATLAT Default: 0xf
8563 10:05:47.253951 0, 0xFFFF, sum = 0
8564 10:05:47.257044 1, 0xFFFF, sum = 0
8565 10:05:47.257184 2, 0xFFFF, sum = 0
8566 10:05:47.260349 3, 0xFFFF, sum = 0
8567 10:05:47.260473 4, 0xFFFF, sum = 0
8568 10:05:47.263521 5, 0xFFFF, sum = 0
8569 10:05:47.263642 6, 0xFFFF, sum = 0
8570 10:05:47.266686 7, 0xFFFF, sum = 0
8571 10:05:47.266809 8, 0xFFFF, sum = 0
8572 10:05:47.269899 9, 0xFFFF, sum = 0
8573 10:05:47.270021 10, 0xFFFF, sum = 0
8574 10:05:47.273618 11, 0xFFFF, sum = 0
8575 10:05:47.276502 12, 0xFFFF, sum = 0
8576 10:05:47.276692 13, 0xFFFF, sum = 0
8577 10:05:47.279967 14, 0x0, sum = 1
8578 10:05:47.280092 15, 0x0, sum = 2
8579 10:05:47.283406 16, 0x0, sum = 3
8580 10:05:47.283530 17, 0x0, sum = 4
8581 10:05:47.283641 best_step = 15
8582 10:05:47.283746
8583 10:05:47.286945 ==
8584 10:05:47.289905 Dram Type= 6, Freq= 0, CH_1, rank 0
8585 10:05:47.293597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8586 10:05:47.293745 ==
8587 10:05:47.293870 RX Vref Scan: 1
8588 10:05:47.294020
8589 10:05:47.296918 Set Vref Range= 24 -> 127
8590 10:05:47.297037
8591 10:05:47.300216 RX Vref 24 -> 127, step: 1
8592 10:05:47.300335
8593 10:05:47.303566 RX Delay 27 -> 252, step: 4
8594 10:05:47.303685
8595 10:05:47.306794 Set Vref, RX VrefLevel [Byte0]: 24
8596 10:05:47.309858 [Byte1]: 24
8597 10:05:47.309976
8598 10:05:47.313024 Set Vref, RX VrefLevel [Byte0]: 25
8599 10:05:47.316342 [Byte1]: 25
8600 10:05:47.316463
8601 10:05:47.320121 Set Vref, RX VrefLevel [Byte0]: 26
8602 10:05:47.323251 [Byte1]: 26
8603 10:05:47.326328
8604 10:05:47.326446 Set Vref, RX VrefLevel [Byte0]: 27
8605 10:05:47.329722 [Byte1]: 27
8606 10:05:47.334203
8607 10:05:47.334321 Set Vref, RX VrefLevel [Byte0]: 28
8608 10:05:47.337299 [Byte1]: 28
8609 10:05:47.341845
8610 10:05:47.341964 Set Vref, RX VrefLevel [Byte0]: 29
8611 10:05:47.344646 [Byte1]: 29
8612 10:05:47.349091
8613 10:05:47.349211 Set Vref, RX VrefLevel [Byte0]: 30
8614 10:05:47.352183 [Byte1]: 30
8615 10:05:47.356488
8616 10:05:47.356606 Set Vref, RX VrefLevel [Byte0]: 31
8617 10:05:47.359944 [Byte1]: 31
8618 10:05:47.364354
8619 10:05:47.364474 Set Vref, RX VrefLevel [Byte0]: 32
8620 10:05:47.367530 [Byte1]: 32
8621 10:05:47.371371
8622 10:05:47.371491 Set Vref, RX VrefLevel [Byte0]: 33
8623 10:05:47.375179 [Byte1]: 33
8624 10:05:47.379079
8625 10:05:47.379198 Set Vref, RX VrefLevel [Byte0]: 34
8626 10:05:47.382168 [Byte1]: 34
8627 10:05:47.386499
8628 10:05:47.386631 Set Vref, RX VrefLevel [Byte0]: 35
8629 10:05:47.390090 [Byte1]: 35
8630 10:05:47.394244
8631 10:05:47.394374 Set Vref, RX VrefLevel [Byte0]: 36
8632 10:05:47.397645 [Byte1]: 36
8633 10:05:47.401987
8634 10:05:47.402212 Set Vref, RX VrefLevel [Byte0]: 37
8635 10:05:47.405384 [Byte1]: 37
8636 10:05:47.409609
8637 10:05:47.409795 Set Vref, RX VrefLevel [Byte0]: 38
8638 10:05:47.412828 [Byte1]: 38
8639 10:05:47.417177
8640 10:05:47.417345 Set Vref, RX VrefLevel [Byte0]: 39
8641 10:05:47.420318 [Byte1]: 39
8642 10:05:47.424198
8643 10:05:47.424339 Set Vref, RX VrefLevel [Byte0]: 40
8644 10:05:47.428044 [Byte1]: 40
8645 10:05:47.431790
8646 10:05:47.431896 Set Vref, RX VrefLevel [Byte0]: 41
8647 10:05:47.435051 [Byte1]: 41
8648 10:05:47.439482
8649 10:05:47.439595 Set Vref, RX VrefLevel [Byte0]: 42
8650 10:05:47.443110 [Byte1]: 42
8651 10:05:47.447068
8652 10:05:47.447175 Set Vref, RX VrefLevel [Byte0]: 43
8653 10:05:47.450564 [Byte1]: 43
8654 10:05:47.454482
8655 10:05:47.454666 Set Vref, RX VrefLevel [Byte0]: 44
8656 10:05:47.457734 [Byte1]: 44
8657 10:05:47.461876
8658 10:05:47.462033 Set Vref, RX VrefLevel [Byte0]: 45
8659 10:05:47.465463 [Byte1]: 45
8660 10:05:47.469854
8661 10:05:47.470011 Set Vref, RX VrefLevel [Byte0]: 46
8662 10:05:47.472996 [Byte1]: 46
8663 10:05:47.476874
8664 10:05:47.477030 Set Vref, RX VrefLevel [Byte0]: 47
8665 10:05:47.480749 [Byte1]: 47
8666 10:05:47.484654
8667 10:05:47.484812 Set Vref, RX VrefLevel [Byte0]: 48
8668 10:05:47.487754 [Byte1]: 48
8669 10:05:47.491990
8670 10:05:47.492127 Set Vref, RX VrefLevel [Byte0]: 49
8671 10:05:47.495365 [Byte1]: 49
8672 10:05:47.499849
8673 10:05:47.499980 Set Vref, RX VrefLevel [Byte0]: 50
8674 10:05:47.502932 [Byte1]: 50
8675 10:05:47.507342
8676 10:05:47.507468 Set Vref, RX VrefLevel [Byte0]: 51
8677 10:05:47.510424 [Byte1]: 51
8678 10:05:47.514759
8679 10:05:47.514890 Set Vref, RX VrefLevel [Byte0]: 52
8680 10:05:47.518015 [Byte1]: 52
8681 10:05:47.522714
8682 10:05:47.522836 Set Vref, RX VrefLevel [Byte0]: 53
8683 10:05:47.525713 [Byte1]: 53
8684 10:05:47.529560
8685 10:05:47.529686 Set Vref, RX VrefLevel [Byte0]: 54
8686 10:05:47.533373 [Byte1]: 54
8687 10:05:47.537349
8688 10:05:47.537507 Set Vref, RX VrefLevel [Byte0]: 55
8689 10:05:47.540637 [Byte1]: 55
8690 10:05:47.545089
8691 10:05:47.545244 Set Vref, RX VrefLevel [Byte0]: 56
8692 10:05:47.548313 [Byte1]: 56
8693 10:05:47.552573
8694 10:05:47.552721 Set Vref, RX VrefLevel [Byte0]: 57
8695 10:05:47.555657 [Byte1]: 57
8696 10:05:47.559870
8697 10:05:47.560023 Set Vref, RX VrefLevel [Byte0]: 58
8698 10:05:47.563357 [Byte1]: 58
8699 10:05:47.567888
8700 10:05:47.568050 Set Vref, RX VrefLevel [Byte0]: 59
8701 10:05:47.571041 [Byte1]: 59
8702 10:05:47.574990
8703 10:05:47.575137 Set Vref, RX VrefLevel [Byte0]: 60
8704 10:05:47.578397 [Byte1]: 60
8705 10:05:47.582824
8706 10:05:47.582993 Set Vref, RX VrefLevel [Byte0]: 61
8707 10:05:47.585795 [Byte1]: 61
8708 10:05:47.590335
8709 10:05:47.590510 Set Vref, RX VrefLevel [Byte0]: 62
8710 10:05:47.593444 [Byte1]: 62
8711 10:05:47.597800
8712 10:05:47.597953 Set Vref, RX VrefLevel [Byte0]: 63
8713 10:05:47.600992 [Byte1]: 63
8714 10:05:47.605461
8715 10:05:47.605605 Set Vref, RX VrefLevel [Byte0]: 64
8716 10:05:47.608538 [Byte1]: 64
8717 10:05:47.612932
8718 10:05:47.613055 Set Vref, RX VrefLevel [Byte0]: 65
8719 10:05:47.616309 [Byte1]: 65
8720 10:05:47.620261
8721 10:05:47.620383 Set Vref, RX VrefLevel [Byte0]: 66
8722 10:05:47.623327 [Byte1]: 66
8723 10:05:47.627632
8724 10:05:47.627763 Set Vref, RX VrefLevel [Byte0]: 67
8725 10:05:47.631253 [Byte1]: 67
8726 10:05:47.635257
8727 10:05:47.635383 Set Vref, RX VrefLevel [Byte0]: 68
8728 10:05:47.638744 [Byte1]: 68
8729 10:05:47.643166
8730 10:05:47.643289 Set Vref, RX VrefLevel [Byte0]: 69
8731 10:05:47.646287 [Byte1]: 69
8732 10:05:47.650580
8733 10:05:47.650719 Set Vref, RX VrefLevel [Byte0]: 70
8734 10:05:47.653805 [Byte1]: 70
8735 10:05:47.657663
8736 10:05:47.657797 Set Vref, RX VrefLevel [Byte0]: 71
8737 10:05:47.661380 [Byte1]: 71
8738 10:05:47.665834
8739 10:05:47.665971 Set Vref, RX VrefLevel [Byte0]: 72
8740 10:05:47.668817 [Byte1]: 72
8741 10:05:47.673141
8742 10:05:47.673331 Set Vref, RX VrefLevel [Byte0]: 73
8743 10:05:47.676511 [Byte1]: 73
8744 10:05:47.680461
8745 10:05:47.680608 Set Vref, RX VrefLevel [Byte0]: 74
8746 10:05:47.683658 [Byte1]: 74
8747 10:05:47.687846
8748 10:05:47.687938 Set Vref, RX VrefLevel [Byte0]: 75
8749 10:05:47.690975 [Byte1]: 75
8750 10:05:47.695403
8751 10:05:47.695520 Set Vref, RX VrefLevel [Byte0]: 76
8752 10:05:47.698877 [Byte1]: 76
8753 10:05:47.703320
8754 10:05:47.703454 Final RX Vref Byte 0 = 57 to rank0
8755 10:05:47.706477 Final RX Vref Byte 1 = 57 to rank0
8756 10:05:47.709929 Final RX Vref Byte 0 = 57 to rank1
8757 10:05:47.713097 Final RX Vref Byte 1 = 57 to rank1==
8758 10:05:47.716301 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 10:05:47.722761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 10:05:47.722860 ==
8761 10:05:47.722950 DQS Delay:
8762 10:05:47.723033 DQS0 = 0, DQS1 = 0
8763 10:05:47.726581 DQM Delay:
8764 10:05:47.726688 DQM0 = 134, DQM1 = 131
8765 10:05:47.729703 DQ Delay:
8766 10:05:47.733046 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8767 10:05:47.736163 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8768 10:05:47.739268 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =124
8769 10:05:47.742693 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8770 10:05:47.742834
8771 10:05:47.742958
8772 10:05:47.743077
8773 10:05:47.745838 [DramC_TX_OE_Calibration] TA2
8774 10:05:47.749424 Original DQ_B0 (3 6) =30, OEN = 27
8775 10:05:47.752899 Original DQ_B1 (3 6) =30, OEN = 27
8776 10:05:47.755973 24, 0x0, End_B0=24 End_B1=24
8777 10:05:47.756111 25, 0x0, End_B0=25 End_B1=25
8778 10:05:47.759165 26, 0x0, End_B0=26 End_B1=26
8779 10:05:47.763116 27, 0x0, End_B0=27 End_B1=27
8780 10:05:47.766296 28, 0x0, End_B0=28 End_B1=28
8781 10:05:47.769351 29, 0x0, End_B0=29 End_B1=29
8782 10:05:47.769491 30, 0x0, End_B0=30 End_B1=30
8783 10:05:47.772460 31, 0x4141, End_B0=30 End_B1=30
8784 10:05:47.775915 Byte0 end_step=30 best_step=27
8785 10:05:47.779231 Byte1 end_step=30 best_step=27
8786 10:05:47.782847 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 10:05:47.785983 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 10:05:47.786072
8789 10:05:47.786139
8790 10:05:47.792408 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8791 10:05:47.796024 CH1 RK0: MR19=303, MR18=1422
8792 10:05:47.802812 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8793 10:05:47.802908
8794 10:05:47.806227 ----->DramcWriteLeveling(PI) begin...
8795 10:05:47.806315 ==
8796 10:05:47.809116 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 10:05:47.812288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 10:05:47.812375 ==
8799 10:05:47.815511 Write leveling (Byte 0): 25 => 25
8800 10:05:47.818896 Write leveling (Byte 1): 28 => 28
8801 10:05:47.822321 DramcWriteLeveling(PI) end<-----
8802 10:05:47.822407
8803 10:05:47.822474 ==
8804 10:05:47.825494 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 10:05:47.829134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 10:05:47.829237 ==
8807 10:05:47.832716 [Gating] SW mode calibration
8808 10:05:47.839119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 10:05:47.845995 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 10:05:47.849328 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 10:05:47.855359 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 10:05:47.859030 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8813 10:05:47.862372 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8814 10:05:47.865544 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 10:05:47.872029 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 10:05:47.875416 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 10:05:47.878948 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 10:05:47.885951 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 10:05:47.888755 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8820 10:05:47.892505 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8821 10:05:47.898496 1 5 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (1 0)
8822 10:05:47.901763 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8823 10:05:47.905356 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 10:05:47.911855 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 10:05:47.915101 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 10:05:47.918861 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 10:05:47.924981 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 10:05:47.928670 1 6 8 | B1->B0 | 3a3a 2323 | 0 0 | (0 0) (0 0)
8829 10:05:47.932453 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 10:05:47.938839 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 10:05:47.941982 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 10:05:47.945362 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 10:05:47.952142 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 10:05:47.955247 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 10:05:47.958379 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8836 10:05:47.965429 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8837 10:05:47.968692 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8838 10:05:47.971949 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8839 10:05:47.978258 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 10:05:47.982037 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 10:05:47.984862 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 10:05:47.991588 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 10:05:47.995123 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 10:05:47.998547 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 10:05:48.004790 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 10:05:48.008524 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 10:05:48.011309 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 10:05:48.018176 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 10:05:48.021833 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 10:05:48.024914 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 10:05:48.028473 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8852 10:05:48.034955 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8853 10:05:48.038081 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8854 10:05:48.041169 Total UI for P1: 0, mck2ui 16
8855 10:05:48.044860 best dqsien dly found for B1: ( 1, 9, 6)
8856 10:05:48.048005 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 10:05:48.051071 Total UI for P1: 0, mck2ui 16
8858 10:05:48.054594 best dqsien dly found for B0: ( 1, 9, 12)
8859 10:05:48.058064 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8860 10:05:48.064584 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8861 10:05:48.064676
8862 10:05:48.067766 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8863 10:05:48.071236 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8864 10:05:48.074358 [Gating] SW calibration Done
8865 10:05:48.074444 ==
8866 10:05:48.077904 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 10:05:48.080939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 10:05:48.081025 ==
8869 10:05:48.081091 RX Vref Scan: 0
8870 10:05:48.084207
8871 10:05:48.084291 RX Vref 0 -> 0, step: 1
8872 10:05:48.084357
8873 10:05:48.087983 RX Delay 0 -> 252, step: 8
8874 10:05:48.091060 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8875 10:05:48.094286 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8876 10:05:48.101270 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8877 10:05:48.104157 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8878 10:05:48.107721 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8879 10:05:48.110799 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8880 10:05:48.114568 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8881 10:05:48.120957 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8882 10:05:48.124216 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8883 10:05:48.127391 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8884 10:05:48.131083 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8885 10:05:48.134112 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8886 10:05:48.141001 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8887 10:05:48.144099 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8888 10:05:48.147835 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8889 10:05:48.150997 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8890 10:05:48.151082 ==
8891 10:05:48.154236 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 10:05:48.161167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 10:05:48.161295 ==
8894 10:05:48.161365 DQS Delay:
8895 10:05:48.161425 DQS0 = 0, DQS1 = 0
8896 10:05:48.164481 DQM Delay:
8897 10:05:48.164582 DQM0 = 136, DQM1 = 133
8898 10:05:48.167646 DQ Delay:
8899 10:05:48.171228 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8900 10:05:48.174303 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8901 10:05:48.177926 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8902 10:05:48.181156 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8903 10:05:48.181246
8904 10:05:48.181313
8905 10:05:48.181374 ==
8906 10:05:48.184394 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 10:05:48.187356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 10:05:48.187443 ==
8909 10:05:48.191359
8910 10:05:48.191470
8911 10:05:48.191552 TX Vref Scan disable
8912 10:05:48.194889 == TX Byte 0 ==
8913 10:05:48.197464 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8914 10:05:48.201019 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8915 10:05:48.204209 == TX Byte 1 ==
8916 10:05:48.207520 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8917 10:05:48.210652 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 10:05:48.210745 ==
8919 10:05:48.214111 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 10:05:48.220727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 10:05:48.220855 ==
8922 10:05:48.232147
8923 10:05:48.235965 TX Vref early break, caculate TX vref
8924 10:05:48.239083 TX Vref=16, minBit 0, minWin=23, winSum=384
8925 10:05:48.242621 TX Vref=18, minBit 0, minWin=23, winSum=391
8926 10:05:48.245898 TX Vref=20, minBit 0, minWin=24, winSum=403
8927 10:05:48.248926 TX Vref=22, minBit 0, minWin=23, winSum=412
8928 10:05:48.252049 TX Vref=24, minBit 0, minWin=25, winSum=416
8929 10:05:48.259140 TX Vref=26, minBit 0, minWin=25, winSum=424
8930 10:05:48.262295 TX Vref=28, minBit 0, minWin=26, winSum=427
8931 10:05:48.265332 TX Vref=30, minBit 1, minWin=25, winSum=420
8932 10:05:48.268981 TX Vref=32, minBit 0, minWin=25, winSum=413
8933 10:05:48.272210 TX Vref=34, minBit 0, minWin=24, winSum=404
8934 10:05:48.278698 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8935 10:05:48.278799
8936 10:05:48.281988 Final TX Range 0 Vref 28
8937 10:05:48.282081
8938 10:05:48.282150 ==
8939 10:05:48.285784 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 10:05:48.288517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 10:05:48.288617 ==
8942 10:05:48.288688
8943 10:05:48.288751
8944 10:05:48.292237 TX Vref Scan disable
8945 10:05:48.298591 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8946 10:05:48.298682 == TX Byte 0 ==
8947 10:05:48.302131 u2DelayCellOfst[0]=20 cells (6 PI)
8948 10:05:48.305232 u2DelayCellOfst[1]=13 cells (4 PI)
8949 10:05:48.308716 u2DelayCellOfst[2]=0 cells (0 PI)
8950 10:05:48.312079 u2DelayCellOfst[3]=6 cells (2 PI)
8951 10:05:48.315498 u2DelayCellOfst[4]=10 cells (3 PI)
8952 10:05:48.318913 u2DelayCellOfst[5]=16 cells (5 PI)
8953 10:05:48.321950 u2DelayCellOfst[6]=16 cells (5 PI)
8954 10:05:48.322040 u2DelayCellOfst[7]=6 cells (2 PI)
8955 10:05:48.328992 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8956 10:05:48.332060 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8957 10:05:48.332149 == TX Byte 1 ==
8958 10:05:48.335775 u2DelayCellOfst[8]=0 cells (0 PI)
8959 10:05:48.338905 u2DelayCellOfst[9]=3 cells (1 PI)
8960 10:05:48.342203 u2DelayCellOfst[10]=10 cells (3 PI)
8961 10:05:48.345514 u2DelayCellOfst[11]=6 cells (2 PI)
8962 10:05:48.349394 u2DelayCellOfst[12]=13 cells (4 PI)
8963 10:05:48.352491 u2DelayCellOfst[13]=16 cells (5 PI)
8964 10:05:48.355531 u2DelayCellOfst[14]=16 cells (5 PI)
8965 10:05:48.358761 u2DelayCellOfst[15]=16 cells (5 PI)
8966 10:05:48.362527 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8967 10:05:48.368754 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8968 10:05:48.368844 DramC Write-DBI on
8969 10:05:48.368911 ==
8970 10:05:48.372019 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 10:05:48.375308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 10:05:48.375394 ==
8973 10:05:48.378485
8974 10:05:48.378570
8975 10:05:48.378637 TX Vref Scan disable
8976 10:05:48.382117 == TX Byte 0 ==
8977 10:05:48.385329 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8978 10:05:48.388535 == TX Byte 1 ==
8979 10:05:48.392235 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8980 10:05:48.392340 DramC Write-DBI off
8981 10:05:48.395268
8982 10:05:48.395356 [DATLAT]
8983 10:05:48.395422 Freq=1600, CH1 RK1
8984 10:05:48.395485
8985 10:05:48.398468 DATLAT Default: 0xf
8986 10:05:48.398553 0, 0xFFFF, sum = 0
8987 10:05:48.402049 1, 0xFFFF, sum = 0
8988 10:05:48.402146 2, 0xFFFF, sum = 0
8989 10:05:48.405170 3, 0xFFFF, sum = 0
8990 10:05:48.405258 4, 0xFFFF, sum = 0
8991 10:05:48.408554 5, 0xFFFF, sum = 0
8992 10:05:48.411606 6, 0xFFFF, sum = 0
8993 10:05:48.411694 7, 0xFFFF, sum = 0
8994 10:05:48.415246 8, 0xFFFF, sum = 0
8995 10:05:48.415390 9, 0xFFFF, sum = 0
8996 10:05:48.418147 10, 0xFFFF, sum = 0
8997 10:05:48.418300 11, 0xFFFF, sum = 0
8998 10:05:48.421560 12, 0xFFFF, sum = 0
8999 10:05:48.421700 13, 0xFFFF, sum = 0
9000 10:05:48.424897 14, 0x0, sum = 1
9001 10:05:48.424983 15, 0x0, sum = 2
9002 10:05:48.428331 16, 0x0, sum = 3
9003 10:05:48.428419 17, 0x0, sum = 4
9004 10:05:48.431703 best_step = 15
9005 10:05:48.431788
9006 10:05:48.431856 ==
9007 10:05:48.435180 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 10:05:48.438288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 10:05:48.438379 ==
9010 10:05:48.441383 RX Vref Scan: 0
9011 10:05:48.441493
9012 10:05:48.441631 RX Vref 0 -> 0, step: 1
9013 10:05:48.441727
9014 10:05:48.444473 RX Delay 19 -> 252, step: 4
9015 10:05:48.448010 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9016 10:05:48.454681 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9017 10:05:48.458301 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9018 10:05:48.461162 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9019 10:05:48.464514 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9020 10:05:48.467737 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9021 10:05:48.471395 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9022 10:05:48.477907 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9023 10:05:48.481144 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9024 10:05:48.484826 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9025 10:05:48.488178 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9026 10:05:48.494405 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9027 10:05:48.497635 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9028 10:05:48.501351 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9029 10:05:48.504450 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9030 10:05:48.507962 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9031 10:05:48.511155 ==
9032 10:05:48.511244 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 10:05:48.517548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 10:05:48.517666 ==
9035 10:05:48.517733 DQS Delay:
9036 10:05:48.521271 DQS0 = 0, DQS1 = 0
9037 10:05:48.521357 DQM Delay:
9038 10:05:48.524158 DQM0 = 134, DQM1 = 130
9039 10:05:48.524243 DQ Delay:
9040 10:05:48.527964 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9041 10:05:48.530940 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9042 10:05:48.534338 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9043 10:05:48.537495 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9044 10:05:48.537613
9045 10:05:48.537683
9046 10:05:48.537745
9047 10:05:48.541244 [DramC_TX_OE_Calibration] TA2
9048 10:05:48.544478 Original DQ_B0 (3 6) =30, OEN = 27
9049 10:05:48.547485 Original DQ_B1 (3 6) =30, OEN = 27
9050 10:05:48.550750 24, 0x0, End_B0=24 End_B1=24
9051 10:05:48.554348 25, 0x0, End_B0=25 End_B1=25
9052 10:05:48.554436 26, 0x0, End_B0=26 End_B1=26
9053 10:05:48.557886 27, 0x0, End_B0=27 End_B1=27
9054 10:05:48.561521 28, 0x0, End_B0=28 End_B1=28
9055 10:05:48.564344 29, 0x0, End_B0=29 End_B1=29
9056 10:05:48.564433 30, 0x0, End_B0=30 End_B1=30
9057 10:05:48.567530 31, 0x4545, End_B0=30 End_B1=30
9058 10:05:48.571214 Byte0 end_step=30 best_step=27
9059 10:05:48.574518 Byte1 end_step=30 best_step=27
9060 10:05:48.577554 Byte0 TX OE(2T, 0.5T) = (3, 3)
9061 10:05:48.580986 Byte1 TX OE(2T, 0.5T) = (3, 3)
9062 10:05:48.581073
9063 10:05:48.581139
9064 10:05:48.587535 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9065 10:05:48.590863 CH1 RK1: MR19=303, MR18=2308
9066 10:05:48.597861 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9067 10:05:48.601045 [RxdqsGatingPostProcess] freq 1600
9068 10:05:48.604301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9069 10:05:48.607479 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 10:05:48.610781 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 10:05:48.614524 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 10:05:48.617856 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 10:05:48.621001 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 10:05:48.624076 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 10:05:48.627746 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 10:05:48.630880 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 10:05:48.634130 Pre-setting of DQS Precalculation
9078 10:05:48.637210 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9079 10:05:48.643964 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9080 10:05:48.654446 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 10:05:48.654564
9082 10:05:48.654639
9083 10:05:48.654712 [Calibration Summary] 3200 Mbps
9084 10:05:48.657593 CH 0, Rank 0
9085 10:05:48.657698 SW Impedance : PASS
9086 10:05:48.660920 DUTY Scan : NO K
9087 10:05:48.664228 ZQ Calibration : PASS
9088 10:05:48.664318 Jitter Meter : NO K
9089 10:05:48.667636 CBT Training : PASS
9090 10:05:48.670597 Write leveling : PASS
9091 10:05:48.670685 RX DQS gating : PASS
9092 10:05:48.673965 RX DQ/DQS(RDDQC) : PASS
9093 10:05:48.677504 TX DQ/DQS : PASS
9094 10:05:48.677635 RX DATLAT : PASS
9095 10:05:48.680920 RX DQ/DQS(Engine): PASS
9096 10:05:48.683847 TX OE : PASS
9097 10:05:48.683938 All Pass.
9098 10:05:48.684005
9099 10:05:48.684067 CH 0, Rank 1
9100 10:05:48.687257 SW Impedance : PASS
9101 10:05:48.690496 DUTY Scan : NO K
9102 10:05:48.690647 ZQ Calibration : PASS
9103 10:05:48.694132 Jitter Meter : NO K
9104 10:05:48.697424 CBT Training : PASS
9105 10:05:48.697538 Write leveling : PASS
9106 10:05:48.700745 RX DQS gating : PASS
9107 10:05:48.700872 RX DQ/DQS(RDDQC) : PASS
9108 10:05:48.703838 TX DQ/DQS : PASS
9109 10:05:48.707324 RX DATLAT : PASS
9110 10:05:48.707433 RX DQ/DQS(Engine): PASS
9111 10:05:48.710570 TX OE : PASS
9112 10:05:48.710657 All Pass.
9113 10:05:48.710724
9114 10:05:48.713774 CH 1, Rank 0
9115 10:05:48.713860 SW Impedance : PASS
9116 10:05:48.717473 DUTY Scan : NO K
9117 10:05:48.720503 ZQ Calibration : PASS
9118 10:05:48.720594 Jitter Meter : NO K
9119 10:05:48.723736 CBT Training : PASS
9120 10:05:48.727537 Write leveling : PASS
9121 10:05:48.727631 RX DQS gating : PASS
9122 10:05:48.730762 RX DQ/DQS(RDDQC) : PASS
9123 10:05:48.734282 TX DQ/DQS : PASS
9124 10:05:48.734375 RX DATLAT : PASS
9125 10:05:48.737482 RX DQ/DQS(Engine): PASS
9126 10:05:48.740824 TX OE : PASS
9127 10:05:48.740915 All Pass.
9128 10:05:48.740982
9129 10:05:48.741044 CH 1, Rank 1
9130 10:05:48.744058 SW Impedance : PASS
9131 10:05:48.747264 DUTY Scan : NO K
9132 10:05:48.747368 ZQ Calibration : PASS
9133 10:05:48.750884 Jitter Meter : NO K
9134 10:05:48.751018 CBT Training : PASS
9135 10:05:48.753927 Write leveling : PASS
9136 10:05:48.757570 RX DQS gating : PASS
9137 10:05:48.757698 RX DQ/DQS(RDDQC) : PASS
9138 10:05:48.760429 TX DQ/DQS : PASS
9139 10:05:48.763633 RX DATLAT : PASS
9140 10:05:48.763742 RX DQ/DQS(Engine): PASS
9141 10:05:48.767580 TX OE : PASS
9142 10:05:48.767680 All Pass.
9143 10:05:48.767751
9144 10:05:48.770864 DramC Write-DBI on
9145 10:05:48.773514 PER_BANK_REFRESH: Hybrid Mode
9146 10:05:48.773643 TX_TRACKING: ON
9147 10:05:48.783938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9148 10:05:48.790520 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9149 10:05:48.796837 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9150 10:05:48.803363 [FAST_K] Save calibration result to emmc
9151 10:05:48.803462 sync common calibartion params.
9152 10:05:48.807227 sync cbt_mode0:1, 1:1
9153 10:05:48.809997 dram_init: ddr_geometry: 2
9154 10:05:48.810086 dram_init: ddr_geometry: 2
9155 10:05:48.813547 dram_init: ddr_geometry: 2
9156 10:05:48.817056 0:dram_rank_size:100000000
9157 10:05:48.820393 1:dram_rank_size:100000000
9158 10:05:48.823506 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9159 10:05:48.826516 DFS_SHUFFLE_HW_MODE: ON
9160 10:05:48.830103 dramc_set_vcore_voltage set vcore to 725000
9161 10:05:48.833739 Read voltage for 1600, 0
9162 10:05:48.833833 Vio18 = 0
9163 10:05:48.836740 Vcore = 725000
9164 10:05:48.836823 Vdram = 0
9165 10:05:48.836889 Vddq = 0
9166 10:05:48.836966 Vmddr = 0
9167 10:05:48.839809 switch to 3200 Mbps bootup
9168 10:05:48.843181 [DramcRunTimeConfig]
9169 10:05:48.843296 PHYPLL
9170 10:05:48.846402 DPM_CONTROL_AFTERK: ON
9171 10:05:48.846517 PER_BANK_REFRESH: ON
9172 10:05:48.849560 REFRESH_OVERHEAD_REDUCTION: ON
9173 10:05:48.853350 CMD_PICG_NEW_MODE: OFF
9174 10:05:48.853429 XRTWTW_NEW_MODE: ON
9175 10:05:48.856630 XRTRTR_NEW_MODE: ON
9176 10:05:48.856715 TX_TRACKING: ON
9177 10:05:48.859848 RDSEL_TRACKING: OFF
9178 10:05:48.863030 DQS Precalculation for DVFS: ON
9179 10:05:48.863115 RX_TRACKING: OFF
9180 10:05:48.863181 HW_GATING DBG: ON
9181 10:05:48.866152 ZQCS_ENABLE_LP4: ON
9182 10:05:48.869584 RX_PICG_NEW_MODE: ON
9183 10:05:48.869698 TX_PICG_NEW_MODE: ON
9184 10:05:48.873308 ENABLE_RX_DCM_DPHY: ON
9185 10:05:48.876490 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9186 10:05:48.876592 DUMMY_READ_FOR_TRACKING: OFF
9187 10:05:48.879810 !!! SPM_CONTROL_AFTERK: OFF
9188 10:05:48.883215 !!! SPM could not control APHY
9189 10:05:48.886582 IMPEDANCE_TRACKING: ON
9190 10:05:48.886667 TEMP_SENSOR: ON
9191 10:05:48.889685 HW_SAVE_FOR_SR: OFF
9192 10:05:48.893422 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9193 10:05:48.896556 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9194 10:05:48.896644 Read ODT Tracking: ON
9195 10:05:48.900160 Refresh Rate DeBounce: ON
9196 10:05:48.902798 DFS_NO_QUEUE_FLUSH: ON
9197 10:05:48.906178 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9198 10:05:48.906264 ENABLE_DFS_RUNTIME_MRW: OFF
9199 10:05:48.909433 DDR_RESERVE_NEW_MODE: ON
9200 10:05:48.912789 MR_CBT_SWITCH_FREQ: ON
9201 10:05:48.912872 =========================
9202 10:05:48.932623 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9203 10:05:48.936368 dram_init: ddr_geometry: 2
9204 10:05:48.954317 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9205 10:05:48.958099 dram_init: dram init end (result: 0)
9206 10:05:48.964890 DRAM-K: Full calibration passed in 24463 msecs
9207 10:05:48.968153 MRC: failed to locate region type 0.
9208 10:05:48.968253 DRAM rank0 size:0x100000000,
9209 10:05:48.971421 DRAM rank1 size=0x100000000
9210 10:05:48.980969 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9211 10:05:48.987757 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9212 10:05:48.994237 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9213 10:05:49.001042 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9214 10:05:49.003904 DRAM rank0 size:0x100000000,
9215 10:05:49.007675 DRAM rank1 size=0x100000000
9216 10:05:49.007760 CBMEM:
9217 10:05:49.010818 IMD: root @ 0xfffff000 254 entries.
9218 10:05:49.014076 IMD: root @ 0xffffec00 62 entries.
9219 10:05:49.017443 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9220 10:05:49.020826 WARNING: RO_VPD is uninitialized or empty.
9221 10:05:49.026830 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9222 10:05:49.034207 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9223 10:05:49.047258 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9224 10:05:49.058287 BS: romstage times (exec / console): total (unknown) / 23991 ms
9225 10:05:49.058429
9226 10:05:49.058498
9227 10:05:49.068508 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9228 10:05:49.071873 ARM64: Exception handlers installed.
9229 10:05:49.074940 ARM64: Testing exception
9230 10:05:49.078292 ARM64: Done test exception
9231 10:05:49.078395 Enumerating buses...
9232 10:05:49.081742 Show all devs... Before device enumeration.
9233 10:05:49.085112 Root Device: enabled 1
9234 10:05:49.088282 CPU_CLUSTER: 0: enabled 1
9235 10:05:49.088372 CPU: 00: enabled 1
9236 10:05:49.092058 Compare with tree...
9237 10:05:49.092157 Root Device: enabled 1
9238 10:05:49.094890 CPU_CLUSTER: 0: enabled 1
9239 10:05:49.098412 CPU: 00: enabled 1
9240 10:05:49.098498 Root Device scanning...
9241 10:05:49.101902 scan_static_bus for Root Device
9242 10:05:49.105303 CPU_CLUSTER: 0 enabled
9243 10:05:49.108462 scan_static_bus for Root Device done
9244 10:05:49.111450 scan_bus: bus Root Device finished in 8 msecs
9245 10:05:49.111542 done
9246 10:05:49.118551 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9247 10:05:49.121540 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9248 10:05:49.128083 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9249 10:05:49.132092 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9250 10:05:49.134687 Allocating resources...
9251 10:05:49.138545 Reading resources...
9252 10:05:49.141791 Root Device read_resources bus 0 link: 0
9253 10:05:49.141884 DRAM rank0 size:0x100000000,
9254 10:05:49.145122 DRAM rank1 size=0x100000000
9255 10:05:49.148429 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9256 10:05:49.151549 CPU: 00 missing read_resources
9257 10:05:49.154976 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9258 10:05:49.161500 Root Device read_resources bus 0 link: 0 done
9259 10:05:49.161658 Done reading resources.
9260 10:05:49.167834 Show resources in subtree (Root Device)...After reading.
9261 10:05:49.171236 Root Device child on link 0 CPU_CLUSTER: 0
9262 10:05:49.174496 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 10:05:49.184725 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 10:05:49.184820 CPU: 00
9265 10:05:49.187781 Root Device assign_resources, bus 0 link: 0
9266 10:05:49.191216 CPU_CLUSTER: 0 missing set_resources
9267 10:05:49.198051 Root Device assign_resources, bus 0 link: 0 done
9268 10:05:49.198142 Done setting resources.
9269 10:05:49.204718 Show resources in subtree (Root Device)...After assigning values.
9270 10:05:49.207614 Root Device child on link 0 CPU_CLUSTER: 0
9271 10:05:49.210984 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 10:05:49.221641 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 10:05:49.221758 CPU: 00
9274 10:05:49.224549 Done allocating resources.
9275 10:05:49.228254 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9276 10:05:49.231291 Enabling resources...
9277 10:05:49.231381 done.
9278 10:05:49.237853 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9279 10:05:49.237942 Initializing devices...
9280 10:05:49.241703 Root Device init
9281 10:05:49.241787 init hardware done!
9282 10:05:49.244929 0x00000018: ctrlr->caps
9283 10:05:49.248131 52.000 MHz: ctrlr->f_max
9284 10:05:49.248219 0.400 MHz: ctrlr->f_min
9285 10:05:49.251399 0x40ff8080: ctrlr->voltages
9286 10:05:49.251485 sclk: 390625
9287 10:05:49.254656 Bus Width = 1
9288 10:05:49.254740 sclk: 390625
9289 10:05:49.254805 Bus Width = 1
9290 10:05:49.258428 Early init status = 3
9291 10:05:49.261506 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9292 10:05:49.266794 in-header: 03 fc 00 00 01 00 00 00
9293 10:05:49.270003 in-data: 00
9294 10:05:49.273301 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9295 10:05:49.279163 in-header: 03 fd 00 00 00 00 00 00
9296 10:05:49.282347 in-data:
9297 10:05:49.285722 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9298 10:05:49.290083 in-header: 03 fc 00 00 01 00 00 00
9299 10:05:49.293394 in-data: 00
9300 10:05:49.296605 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9301 10:05:49.302050 in-header: 03 fd 00 00 00 00 00 00
9302 10:05:49.305630 in-data:
9303 10:05:49.308848 [SSUSB] Setting up USB HOST controller...
9304 10:05:49.311936 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9305 10:05:49.315415 [SSUSB] phy power-on done.
9306 10:05:49.318919 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9307 10:05:49.325824 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9308 10:05:49.328855 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9309 10:05:49.335318 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9310 10:05:49.341828 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9311 10:05:49.348584 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9312 10:05:49.355090 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9313 10:05:49.361832 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9314 10:05:49.365218 SPM: binary array size = 0x9dc
9315 10:05:49.368766 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9316 10:05:49.375015 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9317 10:05:49.382121 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9318 10:05:49.385249 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9319 10:05:49.392045 configure_display: Starting display init
9320 10:05:49.425277 anx7625_power_on_init: Init interface.
9321 10:05:49.428963 anx7625_disable_pd_protocol: Disabled PD feature.
9322 10:05:49.431939 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9323 10:05:49.459925 anx7625_start_dp_work: Secure OCM version=00
9324 10:05:49.463339 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9325 10:05:49.477740 sp_tx_get_edid_block: EDID Block = 1
9326 10:05:49.580414 Extracted contents:
9327 10:05:49.583793 header: 00 ff ff ff ff ff ff 00
9328 10:05:49.586941 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9329 10:05:49.590449 version: 01 04
9330 10:05:49.594002 basic params: 95 1f 11 78 0a
9331 10:05:49.596985 chroma info: 76 90 94 55 54 90 27 21 50 54
9332 10:05:49.600235 established: 00 00 00
9333 10:05:49.606683 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9334 10:05:49.610372 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9335 10:05:49.617008 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 10:05:49.623628 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9337 10:05:49.630060 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9338 10:05:49.633410 extensions: 00
9339 10:05:49.633494 checksum: fb
9340 10:05:49.633559
9341 10:05:49.636420 Manufacturer: IVO Model 57d Serial Number 0
9342 10:05:49.639746 Made week 0 of 2020
9343 10:05:49.639828 EDID version: 1.4
9344 10:05:49.643145 Digital display
9345 10:05:49.646354 6 bits per primary color channel
9346 10:05:49.646439 DisplayPort interface
9347 10:05:49.649561 Maximum image size: 31 cm x 17 cm
9348 10:05:49.653458 Gamma: 220%
9349 10:05:49.653543 Check DPMS levels
9350 10:05:49.656576 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9351 10:05:49.663235 First detailed timing is preferred timing
9352 10:05:49.663330 Established timings supported:
9353 10:05:49.666355 Standard timings supported:
9354 10:05:49.669865 Detailed timings
9355 10:05:49.673219 Hex of detail: 383680a07038204018303c0035ae10000019
9356 10:05:49.676661 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9357 10:05:49.683237 0780 0798 07c8 0820 hborder 0
9358 10:05:49.686429 0438 043b 0447 0458 vborder 0
9359 10:05:49.689429 -hsync -vsync
9360 10:05:49.689538 Did detailed timing
9361 10:05:49.696539 Hex of detail: 000000000000000000000000000000000000
9362 10:05:49.699391 Manufacturer-specified data, tag 0
9363 10:05:49.702975 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9364 10:05:49.706341 ASCII string: InfoVision
9365 10:05:49.709352 Hex of detail: 000000fe00523134304e574635205248200a
9366 10:05:49.712751 ASCII string: R140NWF5 RH
9367 10:05:49.712839 Checksum
9368 10:05:49.715825 Checksum: 0xfb (valid)
9369 10:05:49.719429 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9370 10:05:49.722923 DSI data_rate: 832800000 bps
9371 10:05:49.729324 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9372 10:05:49.732868 anx7625_parse_edid: pixelclock(138800).
9373 10:05:49.735731 hactive(1920), hsync(48), hfp(24), hbp(88)
9374 10:05:49.739410 vactive(1080), vsync(12), vfp(3), vbp(17)
9375 10:05:49.742670 anx7625_dsi_config: config dsi.
9376 10:05:49.749285 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9377 10:05:49.762263 anx7625_dsi_config: success to config DSI
9378 10:05:49.766046 anx7625_dp_start: MIPI phy setup OK.
9379 10:05:49.768944 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9380 10:05:49.772324 mtk_ddp_mode_set invalid vrefresh 60
9381 10:05:49.775473 main_disp_path_setup
9382 10:05:49.775577 ovl_layer_smi_id_en
9383 10:05:49.778957 ovl_layer_smi_id_en
9384 10:05:49.779057 ccorr_config
9385 10:05:49.779147 aal_config
9386 10:05:49.782183 gamma_config
9387 10:05:49.782254 postmask_config
9388 10:05:49.785443 dither_config
9389 10:05:49.789297 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9390 10:05:49.795788 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9391 10:05:49.799118 Root Device init finished in 555 msecs
9392 10:05:49.802691 CPU_CLUSTER: 0 init
9393 10:05:49.809158 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9394 10:05:49.812417 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9395 10:05:49.815871 APU_MBOX 0x190000b0 = 0x10001
9396 10:05:49.819327 APU_MBOX 0x190001b0 = 0x10001
9397 10:05:49.822577 APU_MBOX 0x190005b0 = 0x10001
9398 10:05:49.826012 APU_MBOX 0x190006b0 = 0x10001
9399 10:05:49.829406 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9400 10:05:49.841942 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9401 10:05:49.854611 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9402 10:05:49.860761 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9403 10:05:49.872358 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9404 10:05:49.881720 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9405 10:05:49.884526 CPU_CLUSTER: 0 init finished in 81 msecs
9406 10:05:49.887962 Devices initialized
9407 10:05:49.891341 Show all devs... After init.
9408 10:05:49.891740 Root Device: enabled 1
9409 10:05:49.895143 CPU_CLUSTER: 0: enabled 1
9410 10:05:49.897831 CPU: 00: enabled 1
9411 10:05:49.901217 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9412 10:05:49.904798 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9413 10:05:49.907978 ELOG: NV offset 0x57f000 size 0x1000
9414 10:05:49.914627 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9415 10:05:49.921403 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9416 10:05:49.925033 ELOG: Event(17) added with size 13 at 2023-11-24 10:03:39 UTC
9417 10:05:49.928476 out: cmd=0x121: 03 db 21 01 00 00 00 00
9418 10:05:49.931786 in-header: 03 d3 00 00 2c 00 00 00
9419 10:05:49.945269 in-data: 8c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9420 10:05:49.951868 ELOG: Event(A1) added with size 10 at 2023-11-24 10:03:39 UTC
9421 10:05:49.958383 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9422 10:05:49.965441 ELOG: Event(A0) added with size 9 at 2023-11-24 10:03:39 UTC
9423 10:05:49.968267 elog_add_boot_reason: Logged dev mode boot
9424 10:05:49.971775 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9425 10:05:49.975157 Finalize devices...
9426 10:05:49.975682 Devices finalized
9427 10:05:49.981653 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9428 10:05:49.984825 Writing coreboot table at 0xffe64000
9429 10:05:49.988113 0. 000000000010a000-0000000000113fff: RAMSTAGE
9430 10:05:49.991442 1. 0000000040000000-00000000400fffff: RAM
9431 10:05:49.998357 2. 0000000040100000-000000004032afff: RAMSTAGE
9432 10:05:50.001346 3. 000000004032b000-00000000545fffff: RAM
9433 10:05:50.004638 4. 0000000054600000-000000005465ffff: BL31
9434 10:05:50.008228 5. 0000000054660000-00000000ffe63fff: RAM
9435 10:05:50.014841 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9436 10:05:50.018076 7. 0000000100000000-000000023fffffff: RAM
9437 10:05:50.018485 Passing 5 GPIOs to payload:
9438 10:05:50.024476 NAME | PORT | POLARITY | VALUE
9439 10:05:50.028500 EC in RW | 0x000000aa | low | undefined
9440 10:05:50.034856 EC interrupt | 0x00000005 | low | undefined
9441 10:05:50.037784 TPM interrupt | 0x000000ab | high | undefined
9442 10:05:50.041732 SD card detect | 0x00000011 | high | undefined
9443 10:05:50.048545 speaker enable | 0x00000093 | high | undefined
9444 10:05:50.051805 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9445 10:05:50.054950 in-header: 03 f9 00 00 02 00 00 00
9446 10:05:50.058052 in-data: 02 00
9447 10:05:50.058459 ADC[4]: Raw value=904357 ID=7
9448 10:05:50.061257 ADC[3]: Raw value=213441 ID=1
9449 10:05:50.064586 RAM Code: 0x71
9450 10:05:50.067904 ADC[6]: Raw value=75332 ID=0
9451 10:05:50.068297 ADC[5]: Raw value=213441 ID=1
9452 10:05:50.071294 SKU Code: 0x1
9453 10:05:50.074523 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2e6b
9454 10:05:50.077737 coreboot table: 964 bytes.
9455 10:05:50.081157 IMD ROOT 0. 0xfffff000 0x00001000
9456 10:05:50.084246 IMD SMALL 1. 0xffffe000 0x00001000
9457 10:05:50.087787 RO MCACHE 2. 0xffffc000 0x00001104
9458 10:05:50.091294 CONSOLE 3. 0xfff7c000 0x00080000
9459 10:05:50.094456 FMAP 4. 0xfff7b000 0x00000452
9460 10:05:50.097439 TIME STAMP 5. 0xfff7a000 0x00000910
9461 10:05:50.100788 VBOOT WORK 6. 0xfff66000 0x00014000
9462 10:05:50.104373 RAMOOPS 7. 0xffe66000 0x00100000
9463 10:05:50.108004 COREBOOT 8. 0xffe64000 0x00002000
9464 10:05:50.110839 IMD small region:
9465 10:05:50.114481 IMD ROOT 0. 0xffffec00 0x00000400
9466 10:05:50.117298 VPD 1. 0xffffeb80 0x0000006c
9467 10:05:50.120496 MMC STATUS 2. 0xffffeb60 0x00000004
9468 10:05:50.124143 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9469 10:05:50.127397 Probing TPM: done!
9470 10:05:50.130992 Connected to device vid:did:rid of 1ae0:0028:00
9471 10:05:50.141713 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9472 10:05:50.145052 Initialized TPM device CR50 revision 0
9473 10:05:50.148396 Checking cr50 for pending updates
9474 10:05:50.152464 Reading cr50 TPM mode
9475 10:05:50.160478 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9476 10:05:50.167739 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9477 10:05:50.207711 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9478 10:05:50.210925 Checking segment from ROM address 0x40100000
9479 10:05:50.214611 Checking segment from ROM address 0x4010001c
9480 10:05:50.220842 Loading segment from ROM address 0x40100000
9481 10:05:50.221240 code (compression=0)
9482 10:05:50.227909 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9483 10:05:50.237659 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9484 10:05:50.238169 it's not compressed!
9485 10:05:50.244127 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9486 10:05:50.247868 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9487 10:05:50.267857 Loading segment from ROM address 0x4010001c
9488 10:05:50.268431 Entry Point 0x80000000
9489 10:05:50.271059 Loaded segments
9490 10:05:50.275000 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9491 10:05:50.281652 Jumping to boot code at 0x80000000(0xffe64000)
9492 10:05:50.287975 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9493 10:05:50.294237 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9494 10:05:50.302653 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9495 10:05:50.305906 Checking segment from ROM address 0x40100000
9496 10:05:50.309263 Checking segment from ROM address 0x4010001c
9497 10:05:50.315804 Loading segment from ROM address 0x40100000
9498 10:05:50.316320 code (compression=1)
9499 10:05:50.322065 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9500 10:05:50.332277 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9501 10:05:50.332795 using LZMA
9502 10:05:50.340925 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9503 10:05:50.347267 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9504 10:05:50.350477 Loading segment from ROM address 0x4010001c
9505 10:05:50.350903 Entry Point 0x54601000
9506 10:05:50.354042 Loaded segments
9507 10:05:50.357195 NOTICE: MT8192 bl31_setup
9508 10:05:50.364262 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9509 10:05:50.367978 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9510 10:05:50.370925 WARNING: region 0:
9511 10:05:50.374232 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 10:05:50.374631 WARNING: region 1:
9513 10:05:50.381164 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9514 10:05:50.384104 WARNING: region 2:
9515 10:05:50.387595 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9516 10:05:50.391012 WARNING: region 3:
9517 10:05:50.393885 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9518 10:05:50.397219 WARNING: region 4:
9519 10:05:50.404247 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 10:05:50.404584 WARNING: region 5:
9521 10:05:50.407152 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 10:05:50.410984 WARNING: region 6:
9523 10:05:50.414151 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 10:05:50.417565 WARNING: region 7:
9525 10:05:50.420742 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 10:05:50.427759 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9527 10:05:50.430884 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9528 10:05:50.434281 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9529 10:05:50.440582 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9530 10:05:50.444006 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9531 10:05:50.447399 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9532 10:05:50.454271 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9533 10:05:50.457536 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9534 10:05:50.464003 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9535 10:05:50.467238 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9536 10:05:50.470677 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9537 10:05:50.477168 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9538 10:05:50.480366 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9539 10:05:50.483646 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9540 10:05:50.490867 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9541 10:05:50.494003 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9542 10:05:50.500473 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9543 10:05:50.504262 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9544 10:05:50.507027 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9545 10:05:50.513802 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9546 10:05:50.517254 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9547 10:05:50.520657 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9548 10:05:50.527223 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9549 10:05:50.530633 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9550 10:05:50.537526 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9551 10:05:50.540579 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9552 10:05:50.544331 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9553 10:05:50.550800 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9554 10:05:50.554338 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9555 10:05:50.560716 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9556 10:05:50.564497 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9557 10:05:50.567247 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9558 10:05:50.574269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9559 10:05:50.577475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9560 10:05:50.580370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9561 10:05:50.583660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9562 10:05:50.590268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9563 10:05:50.593441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9564 10:05:50.597365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9565 10:05:50.600573 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9566 10:05:50.606897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9567 10:05:50.610174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9568 10:05:50.613516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9569 10:05:50.616971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9570 10:05:50.624211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9571 10:05:50.626928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9572 10:05:50.630707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9573 10:05:50.633952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9574 10:05:50.640637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9575 10:05:50.643790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9576 10:05:50.650555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9577 10:05:50.653899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9578 10:05:50.657401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9579 10:05:50.664060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9580 10:05:50.667327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9581 10:05:50.674065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9582 10:05:50.677029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9583 10:05:50.684304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9584 10:05:50.688014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9585 10:05:50.691341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9586 10:05:50.697781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9587 10:05:50.700917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9588 10:05:50.707966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9589 10:05:50.711278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9590 10:05:50.717607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9591 10:05:50.720892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9592 10:05:50.724726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9593 10:05:50.731346 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9594 10:05:50.734530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9595 10:05:50.741556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9596 10:05:50.744525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9597 10:05:50.755323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9598 10:05:50.755902 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9599 10:05:50.757572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9600 10:05:50.764466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9601 10:05:50.768196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9602 10:05:50.774743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9603 10:05:50.777553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9604 10:05:50.784542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9605 10:05:50.788369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9606 10:05:50.791208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9607 10:05:50.797694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9608 10:05:50.801028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9609 10:05:50.808271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9610 10:05:50.811503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9611 10:05:50.817849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9612 10:05:50.820929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9613 10:05:50.824909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9614 10:05:50.831265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9615 10:05:50.834618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9616 10:05:50.840944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9617 10:05:50.844682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9618 10:05:50.851451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9619 10:05:50.854652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9620 10:05:50.858079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9621 10:05:50.864440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9622 10:05:50.868113 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9623 10:05:50.871254 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9624 10:05:50.878200 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9625 10:05:50.881474 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9626 10:05:50.885206 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9627 10:05:50.891648 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9628 10:05:50.894773 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9629 10:05:50.898308 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9630 10:05:50.905328 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9631 10:05:50.908592 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9632 10:05:50.911552 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9633 10:05:50.918564 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9634 10:05:50.921527 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9635 10:05:50.928054 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9636 10:05:50.931691 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9637 10:05:50.935057 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9638 10:05:50.941877 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9639 10:05:50.945315 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9640 10:05:50.951559 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9641 10:05:50.955519 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9642 10:05:50.958724 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9643 10:05:50.961485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9644 10:05:50.968622 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9645 10:05:50.971793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9646 10:05:50.975221 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9647 10:05:50.978800 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9648 10:05:50.985050 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9649 10:05:50.988510 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9650 10:05:50.992261 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9651 10:05:50.998560 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9652 10:05:51.002089 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9653 10:05:51.008509 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9654 10:05:51.011760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9655 10:05:51.015472 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9656 10:05:51.022503 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9657 10:05:51.025435 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9658 10:05:51.028587 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9659 10:05:51.035845 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9660 10:05:51.039063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9661 10:05:51.045377 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9662 10:05:51.048696 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9663 10:05:51.052255 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9664 10:05:51.058824 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9665 10:05:51.062665 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9666 10:05:51.066025 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9667 10:05:51.072519 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9668 10:05:51.075651 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9669 10:05:51.082104 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9670 10:05:51.085895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9671 10:05:51.089152 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9672 10:05:51.095704 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9673 10:05:51.098921 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9674 10:05:51.105432 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9675 10:05:51.109150 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9676 10:05:51.112277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9677 10:05:51.119232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9678 10:05:51.122586 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9679 10:05:51.125756 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9680 10:05:51.132377 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9681 10:05:51.135974 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9682 10:05:51.142381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9683 10:05:51.145490 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9684 10:05:51.149427 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9685 10:05:51.156126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9686 10:05:51.159222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9687 10:05:51.162296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9688 10:05:51.168712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9689 10:05:51.172447 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9690 10:05:51.178767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9691 10:05:51.182056 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9692 10:05:51.185204 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9693 10:05:51.192278 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9694 10:05:51.195850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9695 10:05:51.202220 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9696 10:05:51.205377 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9697 10:05:51.208719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9698 10:05:51.215251 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9699 10:05:51.218446 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9700 10:05:51.225049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9701 10:05:51.228752 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9702 10:05:51.231735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9703 10:05:51.238384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9704 10:05:51.241715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9705 10:05:51.248424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9706 10:05:51.251898 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9707 10:05:51.255239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9708 10:05:51.261637 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9709 10:05:51.264808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9710 10:05:51.271510 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9711 10:05:51.274847 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9712 10:05:51.278469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9713 10:05:51.284930 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9714 10:05:51.288882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9715 10:05:51.295109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9716 10:05:51.298422 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9717 10:05:51.301827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9718 10:05:51.308702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9719 10:05:51.311762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9720 10:05:51.318389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9721 10:05:51.321685 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9722 10:05:51.324851 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9723 10:05:51.331599 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9724 10:05:51.334696 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9725 10:05:51.341753 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9726 10:05:51.344854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9727 10:05:51.351715 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9728 10:05:51.354615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9729 10:05:51.358121 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9730 10:05:51.364789 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9731 10:05:51.367951 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9732 10:05:51.375285 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9733 10:05:51.378395 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9734 10:05:51.381458 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9735 10:05:51.387938 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9736 10:05:51.391053 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9737 10:05:51.397954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9738 10:05:51.401215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9739 10:05:51.407731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9740 10:05:51.410954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9741 10:05:51.414714 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9742 10:05:51.420949 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9743 10:05:51.424052 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9744 10:05:51.430602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9745 10:05:51.434347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9746 10:05:51.437492 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9747 10:05:51.443757 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9748 10:05:51.447606 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9749 10:05:51.454005 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9750 10:05:51.457202 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9751 10:05:51.464366 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9752 10:05:51.467329 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9753 10:05:51.470854 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9754 10:05:51.477502 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9755 10:05:51.480772 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9756 10:05:51.484011 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9757 10:05:51.487233 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9758 10:05:51.493631 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9759 10:05:51.497039 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9760 10:05:51.500443 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9761 10:05:51.506952 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9762 10:05:51.510374 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9763 10:05:51.514118 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9764 10:05:51.520625 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9765 10:05:51.523807 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9766 10:05:51.530432 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9767 10:05:51.533665 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9768 10:05:51.536810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9769 10:05:51.543961 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9770 10:05:51.546834 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9771 10:05:51.550509 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9772 10:05:51.557439 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9773 10:05:51.560748 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9774 10:05:51.563872 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9775 10:05:51.570770 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9776 10:05:51.573990 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9777 10:05:51.577389 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9778 10:05:51.584130 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9779 10:05:51.587579 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9780 10:05:51.590952 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9781 10:05:51.597469 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9782 10:05:51.600589 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9783 10:05:51.607491 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9784 10:05:51.610956 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9785 10:05:51.614316 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9786 10:05:51.620607 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9787 10:05:51.623864 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9788 10:05:51.630401 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9789 10:05:51.633743 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9790 10:05:51.636982 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9791 10:05:51.644368 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9792 10:05:51.647334 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9793 10:05:51.650599 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9794 10:05:51.657455 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9795 10:05:51.659948 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9796 10:05:51.663647 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9797 10:05:51.666881 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9798 10:05:51.673523 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9799 10:05:51.676587 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9800 10:05:51.679922 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9801 10:05:51.683546 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9802 10:05:51.689983 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9803 10:05:51.693945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9804 10:05:51.696943 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9805 10:05:51.700223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9806 10:05:51.706777 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9807 10:05:51.709890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9808 10:05:51.713061 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9809 10:05:51.720185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9810 10:05:51.723231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9811 10:05:51.730082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9812 10:05:51.733379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9813 10:05:51.736597 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9814 10:05:51.743637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9815 10:05:51.746931 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9816 10:05:51.750279 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9817 10:05:51.756710 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9818 10:05:51.760010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9819 10:05:51.766874 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9820 10:05:51.770107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9821 10:05:51.776586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9822 10:05:51.779682 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9823 10:05:51.783258 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9824 10:05:51.790133 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9825 10:05:51.793253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9826 10:05:51.799627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9827 10:05:51.802729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9828 10:05:51.806173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9829 10:05:51.812915 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9830 10:05:51.816239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9831 10:05:51.822944 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9832 10:05:51.826058 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9833 10:05:51.829670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9834 10:05:51.836177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9835 10:05:51.839497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9836 10:05:51.846093 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9837 10:05:51.849240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9838 10:05:51.856580 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9839 10:05:51.859717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9840 10:05:51.862947 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9841 10:05:51.869439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9842 10:05:51.872492 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9843 10:05:51.879459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9844 10:05:51.882607 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9845 10:05:51.885910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9846 10:05:51.892479 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9847 10:05:51.896139 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9848 10:05:51.902816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9849 10:05:51.906070 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9850 10:05:51.909076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9851 10:05:51.916021 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9852 10:05:51.919264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9853 10:05:51.925939 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9854 10:05:51.929137 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9855 10:05:51.932603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9856 10:05:51.939350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9857 10:05:51.942249 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9858 10:05:51.949311 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9859 10:05:51.952792 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9860 10:05:51.959034 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9861 10:05:51.962417 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9862 10:05:51.966103 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9863 10:05:51.972234 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9864 10:05:51.976122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9865 10:05:51.982143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9866 10:05:51.985960 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9867 10:05:51.989164 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9868 10:05:51.995880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9869 10:05:51.998946 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9870 10:05:52.005511 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9871 10:05:52.008755 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9872 10:05:52.012473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9873 10:05:52.018950 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9874 10:05:52.022441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9875 10:05:52.028984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9876 10:05:52.032240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9877 10:05:52.035390 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9878 10:05:52.042228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9879 10:05:52.045454 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9880 10:05:52.052276 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9881 10:05:52.055383 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9882 10:05:52.062106 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9883 10:05:52.065446 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9884 10:05:52.068612 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9885 10:05:52.075230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9886 10:05:52.078204 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9887 10:05:52.085267 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9888 10:05:52.088249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9889 10:05:52.095096 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9890 10:05:52.097955 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9891 10:05:52.101733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9892 10:05:52.108217 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9893 10:05:52.111488 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9894 10:05:52.117925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9895 10:05:52.121224 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9896 10:05:52.127772 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9897 10:05:52.131168 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9898 10:05:52.137844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9899 10:05:52.141293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9900 10:05:52.144959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9901 10:05:52.151697 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9902 10:05:52.154412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9903 10:05:52.161587 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9904 10:05:52.164896 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9905 10:05:52.171390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9906 10:05:52.174518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9907 10:05:52.178061 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9908 10:05:52.184625 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9909 10:05:52.187751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9910 10:05:52.194514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9911 10:05:52.198070 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9912 10:05:52.205061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9913 10:05:52.207729 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9914 10:05:52.211140 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9915 10:05:52.217707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9916 10:05:52.221123 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9917 10:05:52.228065 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9918 10:05:52.231228 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9919 10:05:52.237629 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9920 10:05:52.241448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9921 10:05:52.244665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9922 10:05:52.250882 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9923 10:05:52.254556 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9924 10:05:52.261330 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9925 10:05:52.264715 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9926 10:05:52.271324 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9927 10:05:52.274302 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9928 10:05:52.277527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9929 10:05:52.284234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9930 10:05:52.287738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9931 10:05:52.294400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9932 10:05:52.297682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9933 10:05:52.304287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9934 10:05:52.307900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9935 10:05:52.314098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9936 10:05:52.317903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9937 10:05:52.324450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9938 10:05:52.328248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9939 10:05:52.331266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9940 10:05:52.337762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9941 10:05:52.341214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9942 10:05:52.347805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9943 10:05:52.351387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9944 10:05:52.357991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9945 10:05:52.361195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9946 10:05:52.367721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9947 10:05:52.371045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9948 10:05:52.377689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9949 10:05:52.380907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9950 10:05:52.388233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9951 10:05:52.391566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9952 10:05:52.397900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9953 10:05:52.401392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9954 10:05:52.408533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9955 10:05:52.411963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9956 10:05:52.417863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9957 10:05:52.421754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9958 10:05:52.428111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9959 10:05:52.431402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9960 10:05:52.434939 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9961 10:05:52.438228 INFO: [APUAPC] vio 0
9962 10:05:52.444926 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9963 10:05:52.448154 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9964 10:05:52.451165 INFO: [APUAPC] D0_APC_0: 0x400510
9965 10:05:52.454132 INFO: [APUAPC] D0_APC_1: 0x0
9966 10:05:52.457683 INFO: [APUAPC] D0_APC_2: 0x1540
9967 10:05:52.461088 INFO: [APUAPC] D0_APC_3: 0x0
9968 10:05:52.464530 INFO: [APUAPC] D1_APC_0: 0xffffffff
9969 10:05:52.467736 INFO: [APUAPC] D1_APC_1: 0xffffffff
9970 10:05:52.470755 INFO: [APUAPC] D1_APC_2: 0x3fffff
9971 10:05:52.474132 INFO: [APUAPC] D1_APC_3: 0x0
9972 10:05:52.477340 INFO: [APUAPC] D2_APC_0: 0xffffffff
9973 10:05:52.480451 INFO: [APUAPC] D2_APC_1: 0xffffffff
9974 10:05:52.483733 INFO: [APUAPC] D2_APC_2: 0x3fffff
9975 10:05:52.486975 INFO: [APUAPC] D2_APC_3: 0x0
9976 10:05:52.490477 INFO: [APUAPC] D3_APC_0: 0xffffffff
9977 10:05:52.493609 INFO: [APUAPC] D3_APC_1: 0xffffffff
9978 10:05:52.497101 INFO: [APUAPC] D3_APC_2: 0x3fffff
9979 10:05:52.500591 INFO: [APUAPC] D3_APC_3: 0x0
9980 10:05:52.503543 INFO: [APUAPC] D4_APC_0: 0xffffffff
9981 10:05:52.507295 INFO: [APUAPC] D4_APC_1: 0xffffffff
9982 10:05:52.510850 INFO: [APUAPC] D4_APC_2: 0x3fffff
9983 10:05:52.511281 INFO: [APUAPC] D4_APC_3: 0x0
9984 10:05:52.517171 INFO: [APUAPC] D5_APC_0: 0xffffffff
9985 10:05:52.520559 INFO: [APUAPC] D5_APC_1: 0xffffffff
9986 10:05:52.523664 INFO: [APUAPC] D5_APC_2: 0x3fffff
9987 10:05:52.524093 INFO: [APUAPC] D5_APC_3: 0x0
9988 10:05:52.527140 INFO: [APUAPC] D6_APC_0: 0xffffffff
9989 10:05:52.530151 INFO: [APUAPC] D6_APC_1: 0xffffffff
9990 10:05:52.533652 INFO: [APUAPC] D6_APC_2: 0x3fffff
9991 10:05:52.536724 INFO: [APUAPC] D6_APC_3: 0x0
9992 10:05:52.540447 INFO: [APUAPC] D7_APC_0: 0xffffffff
9993 10:05:52.543579 INFO: [APUAPC] D7_APC_1: 0xffffffff
9994 10:05:52.546627 INFO: [APUAPC] D7_APC_2: 0x3fffff
9995 10:05:52.550486 INFO: [APUAPC] D7_APC_3: 0x0
9996 10:05:52.553842 INFO: [APUAPC] D8_APC_0: 0xffffffff
9997 10:05:52.557051 INFO: [APUAPC] D8_APC_1: 0xffffffff
9998 10:05:52.560202 INFO: [APUAPC] D8_APC_2: 0x3fffff
9999 10:05:52.563957 INFO: [APUAPC] D8_APC_3: 0x0
10000 10:05:52.567275 INFO: [APUAPC] D9_APC_0: 0xffffffff
10001 10:05:52.570362 INFO: [APUAPC] D9_APC_1: 0xffffffff
10002 10:05:52.573667 INFO: [APUAPC] D9_APC_2: 0x3fffff
10003 10:05:52.577163 INFO: [APUAPC] D9_APC_3: 0x0
10004 10:05:52.580244 INFO: [APUAPC] D10_APC_0: 0xffffffff
10005 10:05:52.583513 INFO: [APUAPC] D10_APC_1: 0xffffffff
10006 10:05:52.586653 INFO: [APUAPC] D10_APC_2: 0x3fffff
10007 10:05:52.590109 INFO: [APUAPC] D10_APC_3: 0x0
10008 10:05:52.593186 INFO: [APUAPC] D11_APC_0: 0xffffffff
10009 10:05:52.596560 INFO: [APUAPC] D11_APC_1: 0xffffffff
10010 10:05:52.600142 INFO: [APUAPC] D11_APC_2: 0x3fffff
10011 10:05:52.603178 INFO: [APUAPC] D11_APC_3: 0x0
10012 10:05:52.606493 INFO: [APUAPC] D12_APC_0: 0xffffffff
10013 10:05:52.610218 INFO: [APUAPC] D12_APC_1: 0xffffffff
10014 10:05:52.613514 INFO: [APUAPC] D12_APC_2: 0x3fffff
10015 10:05:52.616487 INFO: [APUAPC] D12_APC_3: 0x0
10016 10:05:52.619921 INFO: [APUAPC] D13_APC_0: 0xffffffff
10017 10:05:52.623158 INFO: [APUAPC] D13_APC_1: 0xffffffff
10018 10:05:52.626618 INFO: [APUAPC] D13_APC_2: 0x3fffff
10019 10:05:52.629714 INFO: [APUAPC] D13_APC_3: 0x0
10020 10:05:52.633552 INFO: [APUAPC] D14_APC_0: 0xffffffff
10021 10:05:52.636441 INFO: [APUAPC] D14_APC_1: 0xffffffff
10022 10:05:52.639843 INFO: [APUAPC] D14_APC_2: 0x3fffff
10023 10:05:52.643550 INFO: [APUAPC] D14_APC_3: 0x0
10024 10:05:52.646503 INFO: [APUAPC] D15_APC_0: 0xffffffff
10025 10:05:52.650022 INFO: [APUAPC] D15_APC_1: 0xffffffff
10026 10:05:52.653163 INFO: [APUAPC] D15_APC_2: 0x3fffff
10027 10:05:52.656435 INFO: [APUAPC] D15_APC_3: 0x0
10028 10:05:52.659723 INFO: [APUAPC] APC_CON: 0x4
10029 10:05:52.662976 INFO: [NOCDAPC] D0_APC_0: 0x0
10030 10:05:52.666150 INFO: [NOCDAPC] D0_APC_1: 0x0
10031 10:05:52.669994 INFO: [NOCDAPC] D1_APC_0: 0x0
10032 10:05:52.673278 INFO: [NOCDAPC] D1_APC_1: 0xfff
10033 10:05:52.673618 INFO: [NOCDAPC] D2_APC_0: 0x0
10034 10:05:52.676498 INFO: [NOCDAPC] D2_APC_1: 0xfff
10035 10:05:52.679775 INFO: [NOCDAPC] D3_APC_0: 0x0
10036 10:05:52.682926 INFO: [NOCDAPC] D3_APC_1: 0xfff
10037 10:05:52.686189 INFO: [NOCDAPC] D4_APC_0: 0x0
10038 10:05:52.689416 INFO: [NOCDAPC] D4_APC_1: 0xfff
10039 10:05:52.692747 INFO: [NOCDAPC] D5_APC_0: 0x0
10040 10:05:52.696008 INFO: [NOCDAPC] D5_APC_1: 0xfff
10041 10:05:52.699317 INFO: [NOCDAPC] D6_APC_0: 0x0
10042 10:05:52.703022 INFO: [NOCDAPC] D6_APC_1: 0xfff
10043 10:05:52.705991 INFO: [NOCDAPC] D7_APC_0: 0x0
10044 10:05:52.706076 INFO: [NOCDAPC] D7_APC_1: 0xfff
10045 10:05:52.709440 INFO: [NOCDAPC] D8_APC_0: 0x0
10046 10:05:52.712884 INFO: [NOCDAPC] D8_APC_1: 0xfff
10047 10:05:52.716066 INFO: [NOCDAPC] D9_APC_0: 0x0
10048 10:05:52.719610 INFO: [NOCDAPC] D9_APC_1: 0xfff
10049 10:05:52.722843 INFO: [NOCDAPC] D10_APC_0: 0x0
10050 10:05:52.725956 INFO: [NOCDAPC] D10_APC_1: 0xfff
10051 10:05:52.729288 INFO: [NOCDAPC] D11_APC_0: 0x0
10052 10:05:52.732369 INFO: [NOCDAPC] D11_APC_1: 0xfff
10053 10:05:52.736183 INFO: [NOCDAPC] D12_APC_0: 0x0
10054 10:05:52.739142 INFO: [NOCDAPC] D12_APC_1: 0xfff
10055 10:05:52.742308 INFO: [NOCDAPC] D13_APC_0: 0x0
10056 10:05:52.745546 INFO: [NOCDAPC] D13_APC_1: 0xfff
10057 10:05:52.749293 INFO: [NOCDAPC] D14_APC_0: 0x0
10058 10:05:52.749402 INFO: [NOCDAPC] D14_APC_1: 0xfff
10059 10:05:52.752557 INFO: [NOCDAPC] D15_APC_0: 0x0
10060 10:05:52.755691 INFO: [NOCDAPC] D15_APC_1: 0xfff
10061 10:05:52.759540 INFO: [NOCDAPC] APC_CON: 0x4
10062 10:05:52.762517 INFO: [APUAPC] set_apusys_apc done
10063 10:05:52.765906 INFO: [DEVAPC] devapc_init done
10064 10:05:52.769130 INFO: GICv3 without legacy support detected.
10065 10:05:52.776025 INFO: ARM GICv3 driver initialized in EL3
10066 10:05:52.779241 INFO: Maximum SPI INTID supported: 639
10067 10:05:52.782486 INFO: BL31: Initializing runtime services
10068 10:05:52.788954 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10069 10:05:52.789038 INFO: SPM: enable CPC mode
10070 10:05:52.795468 INFO: mcdi ready for mcusys-off-idle and system suspend
10071 10:05:52.798787 INFO: BL31: Preparing for EL3 exit to normal world
10072 10:05:52.805372 INFO: Entry point address = 0x80000000
10073 10:05:52.805498 INFO: SPSR = 0x8
10074 10:05:52.811979
10075 10:05:52.812062
10076 10:05:52.812127
10077 10:05:52.815293 Starting depthcharge on Spherion...
10078 10:05:52.815402
10079 10:05:52.815523 Wipe memory regions:
10080 10:05:52.815618
10081 10:05:52.816455 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10082 10:05:52.816586 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10083 10:05:52.816694 Setting prompt string to ['asurada:']
10084 10:05:52.816803 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10085 10:05:52.818302 [0x00000040000000, 0x00000054600000)
10086 10:05:52.941325
10087 10:05:52.941873 [0x00000054660000, 0x00000080000000)
10088 10:05:53.200883
10089 10:05:53.201114 [0x000000821a7280, 0x000000ffe64000)
10090 10:05:53.945741
10091 10:05:53.946032 [0x00000100000000, 0x00000240000000)
10092 10:05:55.834461
10093 10:05:55.837910 Initializing XHCI USB controller at 0x11200000.
10094 10:05:56.876591
10095 10:05:56.880209 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10096 10:05:56.880295
10097 10:05:56.880360
10098 10:05:56.880442
10099 10:05:56.880786 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10101 10:05:56.981175 asurada: tftpboot 192.168.201.1 12073332/tftp-deploy-iubfbl6v/kernel/image.itb 12073332/tftp-deploy-iubfbl6v/kernel/cmdline
10102 10:05:56.981334 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 10:05:56.981419 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10104 10:05:56.985711 tftpboot 192.168.201.1 12073332/tftp-deploy-iubfbl6v/kernel/image.ittp-deploy-iubfbl6v/kernel/cmdline
10105 10:05:56.985798
10106 10:05:56.985863 Waiting for link
10107 10:05:57.146471
10108 10:05:57.146617 R8152: Initializing
10109 10:05:57.146686
10110 10:05:57.149945 Version 9 (ocp_data = 6010)
10111 10:05:57.150030
10112 10:05:57.152892 R8152: Done initializing
10113 10:05:57.152995
10114 10:05:57.153075 Adding net device
10115 10:05:59.098398
10116 10:05:59.098549 done.
10117 10:05:59.098623
10118 10:05:59.098687 MAC: 00:e0:4c:78:7a:aa
10119 10:05:59.098761
10120 10:05:59.101782 Sending DHCP discover... done.
10121 10:05:59.101884
10122 10:06:09.710684 Waiting for reply... R8152: Bulk read error 0xffffffbf
10123 10:06:09.710829
10124 10:06:09.714336 Receive failed.
10125 10:06:09.714426
10126 10:06:09.714499 done.
10127 10:06:09.714563
10128 10:06:09.717537 Sending DHCP request... done.
10129 10:06:09.717641
10130 10:06:09.722695 Waiting for reply... done.
10131 10:06:09.722784
10132 10:06:09.722866 My ip is 192.168.201.12
10133 10:06:09.722930
10134 10:06:09.726457 The DHCP server ip is 192.168.201.1
10135 10:06:09.726534
10136 10:06:09.732586 TFTP server IP predefined by user: 192.168.201.1
10137 10:06:09.732668
10138 10:06:09.739512 Bootfile predefined by user: 12073332/tftp-deploy-iubfbl6v/kernel/image.itb
10139 10:06:09.739606
10140 10:06:09.739674 Sending tftp read request... done.
10141 10:06:09.742718
10142 10:06:09.745904 Waiting for the transfer...
10143 10:06:09.745995
10144 10:06:09.993097 00000000 ################################################################
10145 10:06:09.993232
10146 10:06:10.239691 00080000 ################################################################
10147 10:06:10.239861
10148 10:06:10.498023 00100000 ################################################################
10149 10:06:10.498189
10150 10:06:10.765940 00180000 ################################################################
10151 10:06:10.766110
10152 10:06:11.019282 00200000 ################################################################
10153 10:06:11.019448
10154 10:06:11.272153 00280000 ################################################################
10155 10:06:11.272322
10156 10:06:11.533543 00300000 ################################################################
10157 10:06:11.533715
10158 10:06:11.790287 00380000 ################################################################
10159 10:06:11.790440
10160 10:06:12.036738 00400000 ################################################################
10161 10:06:12.036901
10162 10:06:12.279690 00480000 ################################################################
10163 10:06:12.279855
10164 10:06:12.518813 00500000 ################################################################
10165 10:06:12.518985
10166 10:06:12.762440 00580000 ################################################################
10167 10:06:12.762582
10168 10:06:13.023016 00600000 ################################################################
10169 10:06:13.023177
10170 10:06:13.284248 00680000 ################################################################
10171 10:06:13.284388
10172 10:06:13.536458 00700000 ################################################################
10173 10:06:13.536596
10174 10:06:13.784623 00780000 ################################################################
10175 10:06:13.784788
10176 10:06:14.037192 00800000 ################################################################
10177 10:06:14.037351
10178 10:06:14.287125 00880000 ################################################################
10179 10:06:14.287288
10180 10:06:14.542406 00900000 ################################################################
10181 10:06:14.542543
10182 10:06:14.797637 00980000 ################################################################
10183 10:06:14.797773
10184 10:06:15.050579 00a00000 ################################################################
10185 10:06:15.050716
10186 10:06:15.307277 00a80000 ################################################################
10187 10:06:15.307416
10188 10:06:15.558204 00b00000 ################################################################
10189 10:06:15.558369
10190 10:06:15.818041 00b80000 ################################################################
10191 10:06:15.818205
10192 10:06:16.077120 00c00000 ################################################################
10193 10:06:16.077282
10194 10:06:16.338754 00c80000 ################################################################
10195 10:06:16.338895
10196 10:06:16.587355 00d00000 ################################################################
10197 10:06:16.587506
10198 10:06:16.837525 00d80000 ################################################################
10199 10:06:16.837705
10200 10:06:17.090797 00e00000 ################################################################
10201 10:06:17.090928
10202 10:06:17.341769 00e80000 ################################################################
10203 10:06:17.341908
10204 10:06:17.592742 00f00000 ################################################################
10205 10:06:17.592898
10206 10:06:17.873044 00f80000 ################################################################
10207 10:06:17.873233
10208 10:06:18.128729 01000000 ################################################################
10209 10:06:18.128864
10210 10:06:18.384741 01080000 ################################################################
10211 10:06:18.384883
10212 10:06:18.636257 01100000 ################################################################
10213 10:06:18.636420
10214 10:06:18.892323 01180000 ################################################################
10215 10:06:18.892476
10216 10:06:19.149674 01200000 ################################################################
10217 10:06:19.149820
10218 10:06:19.402446 01280000 ################################################################
10219 10:06:19.402594
10220 10:06:19.656136 01300000 ################################################################
10221 10:06:19.656334
10222 10:06:19.909399 01380000 ################################################################
10223 10:06:19.909563
10224 10:06:20.163235 01400000 ################################################################
10225 10:06:20.163414
10226 10:06:20.417695 01480000 ################################################################
10227 10:06:20.417831
10228 10:06:20.694255 01500000 ################################################################
10229 10:06:20.694400
10230 10:06:20.950586 01580000 ################################################################
10231 10:06:20.950763
10232 10:06:21.214139 01600000 ################################################################
10233 10:06:21.214314
10234 10:06:21.475969 01680000 ################################################################
10235 10:06:21.476121
10236 10:06:21.741824 01700000 ################################################################
10237 10:06:21.741968
10238 10:06:22.001944 01780000 ################################################################
10239 10:06:22.002093
10240 10:06:22.261651 01800000 ################################################################
10241 10:06:22.261796
10242 10:06:22.531101 01880000 ################################################################
10243 10:06:22.531251
10244 10:06:22.801560 01900000 ################################################################
10245 10:06:22.801748
10246 10:06:23.057357 01980000 ################################################################
10247 10:06:23.057536
10248 10:06:23.302659 01a00000 ################################################################
10249 10:06:23.302840
10250 10:06:23.549859 01a80000 ################################################################
10251 10:06:23.550042
10252 10:06:23.810584 01b00000 ################################################################
10253 10:06:23.810720
10254 10:06:23.838221 01b80000 ####### done.
10255 10:06:23.838321
10256 10:06:23.841227 The bootfile was 28890954 bytes long.
10257 10:06:23.841313
10258 10:06:23.841424 Sending tftp read request... done.
10259 10:06:23.841518
10260 10:06:23.844867 Waiting for the transfer...
10261 10:06:23.844950
10262 10:06:23.848323 00000000 # done.
10263 10:06:23.848430
10264 10:06:23.854876 Command line loaded dynamically from TFTP file: 12073332/tftp-deploy-iubfbl6v/kernel/cmdline
10265 10:06:23.854957
10266 10:06:23.877836 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10267 10:06:23.877945
10268 10:06:23.878014 Loading FIT.
10269 10:06:23.878075
10270 10:06:23.881159 Image ramdisk-1 has 17794100 bytes.
10271 10:06:23.881239
10272 10:06:23.884470 Image fdt-1 has 47278 bytes.
10273 10:06:23.884551
10274 10:06:23.887778 Image kernel-1 has 11047542 bytes.
10275 10:06:23.887904
10276 10:06:23.894457 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10277 10:06:23.894542
10278 10:06:23.914331 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10279 10:06:23.914459
10280 10:06:23.917864 Choosing best match conf-1 for compat google,spherion-rev2.
10281 10:06:23.923388
10282 10:06:23.927793 Connected to device vid:did:rid of 1ae0:0028:00
10283 10:06:23.936042
10284 10:06:23.939270 tpm_get_response: command 0x17b, return code 0x0
10285 10:06:23.939358
10286 10:06:23.945789 ec_init: CrosEC protocol v3 supported (256, 248)
10287 10:06:23.945876
10288 10:06:23.949474 tpm_cleanup: add release locality here.
10289 10:06:23.949593
10290 10:06:23.952769 Shutting down all USB controllers.
10291 10:06:23.952855
10292 10:06:23.955993 Removing current net device
10293 10:06:23.956080
10294 10:06:23.959231 Exiting depthcharge with code 4 at timestamp: 60436245
10295 10:06:23.962373
10296 10:06:23.966063 LZMA decompressing kernel-1 to 0x821a6718
10297 10:06:23.966149
10298 10:06:23.969109 LZMA decompressing kernel-1 to 0x40000000
10299 10:06:25.357603
10300 10:06:25.357815 jumping to kernel
10301 10:06:25.358632 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10302 10:06:25.358801 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10303 10:06:25.358918 Setting prompt string to ['Linux version [0-9]']
10304 10:06:25.359026 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10305 10:06:25.359138 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10306 10:06:25.439433
10307 10:06:25.442602 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10308 10:06:25.446848 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10309 10:06:25.446961 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10310 10:06:25.447045 Setting prompt string to []
10311 10:06:25.447143 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10312 10:06:25.447230 Using line separator: #'\n'#
10313 10:06:25.447327 No login prompt set.
10314 10:06:25.447429 Parsing kernel messages
10315 10:06:25.447539 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10316 10:06:25.447750 [login-action] Waiting for messages, (timeout 00:03:53)
10317 10:06:25.466173 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10318 10:06:25.469510 [ 0.000000] random: crng init done
10319 10:06:25.472845 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10320 10:06:25.476203 [ 0.000000] efi: UEFI not found.
10321 10:06:25.485773 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10322 10:06:25.492948 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10323 10:06:25.502760 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10324 10:06:25.512783 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10325 10:06:25.519222 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10326 10:06:25.522447 [ 0.000000] printk: bootconsole [mtk8250] enabled
10327 10:06:25.531324 [ 0.000000] NUMA: No NUMA configuration found
10328 10:06:25.537828 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10329 10:06:25.544746 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10330 10:06:25.544833 [ 0.000000] Zone ranges:
10331 10:06:25.551196 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10332 10:06:25.554504 [ 0.000000] DMA32 empty
10333 10:06:25.560826 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10334 10:06:25.564757 [ 0.000000] Movable zone start for each node
10335 10:06:25.567912 [ 0.000000] Early memory node ranges
10336 10:06:25.574292 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10337 10:06:25.580916 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10338 10:06:25.587536 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10339 10:06:25.594470 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10340 10:06:25.601063 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10341 10:06:25.607564 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10342 10:06:25.663720 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10343 10:06:25.670717 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10344 10:06:25.677109 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10345 10:06:25.680383 [ 0.000000] psci: probing for conduit method from DT.
10346 10:06:25.686814 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10347 10:06:25.690185 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10348 10:06:25.696718 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10349 10:06:25.700110 [ 0.000000] psci: SMC Calling Convention v1.2
10350 10:06:25.707170 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10351 10:06:25.710387 [ 0.000000] Detected VIPT I-cache on CPU0
10352 10:06:25.717040 [ 0.000000] CPU features: detected: GIC system register CPU interface
10353 10:06:25.723531 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10354 10:06:25.729922 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10355 10:06:25.736666 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10356 10:06:25.743314 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10357 10:06:25.750315 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10358 10:06:25.756487 [ 0.000000] alternatives: applying boot alternatives
10359 10:06:25.760191 [ 0.000000] Fallback order for Node 0: 0
10360 10:06:25.766398 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10361 10:06:25.769818 [ 0.000000] Policy zone: Normal
10362 10:06:25.793228 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10363 10:06:25.803075 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10364 10:06:25.815911 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10365 10:06:25.826393 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10366 10:06:25.832768 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10367 10:06:25.835994 <6>[ 0.000000] software IO TLB: area num 8.
10368 10:06:25.892759 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10369 10:06:26.042021 <6>[ 0.000000] Memory: 7952232K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400536K reserved, 32768K cma-reserved)
10370 10:06:26.048207 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10371 10:06:26.054944 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10372 10:06:26.058710 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10373 10:06:26.065213 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10374 10:06:26.071512 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10375 10:06:26.074738 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10376 10:06:26.085128 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10377 10:06:26.091703 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10378 10:06:26.098069 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10379 10:06:26.104519 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10380 10:06:26.108447 <6>[ 0.000000] GICv3: 608 SPIs implemented
10381 10:06:26.111786 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10382 10:06:26.118349 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10383 10:06:26.121556 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10384 10:06:26.128143 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10385 10:06:26.141266 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10386 10:06:26.151521 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10387 10:06:26.161492 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10388 10:06:26.168570 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10389 10:06:26.181538 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10390 10:06:26.188698 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10391 10:06:26.195056 <6>[ 0.009229] Console: colour dummy device 80x25
10392 10:06:26.205090 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10393 10:06:26.208385 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10394 10:06:26.214783 <6>[ 0.029271] LSM: Security Framework initializing
10395 10:06:26.221442 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 10:06:26.231567 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10397 10:06:26.237947 <6>[ 0.051418] cblist_init_generic: Setting adjustable number of callback queues.
10398 10:06:26.244950 <6>[ 0.058860] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 10:06:26.254526 <6>[ 0.065198] cblist_init_generic: Setting adjustable number of callback queues.
10400 10:06:26.257831 <6>[ 0.072623] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 10:06:26.264897 <6>[ 0.079022] rcu: Hierarchical SRCU implementation.
10402 10:06:26.271416 <6>[ 0.084037] rcu: Max phase no-delay instances is 1000.
10403 10:06:26.277858 <6>[ 0.091057] EFI services will not be available.
10404 10:06:26.281173 <6>[ 0.096009] smp: Bringing up secondary CPUs ...
10405 10:06:26.289154 <6>[ 0.101058] Detected VIPT I-cache on CPU1
10406 10:06:26.295562 <6>[ 0.101127] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10407 10:06:26.302022 <6>[ 0.101159] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10408 10:06:26.305776 <6>[ 0.101496] Detected VIPT I-cache on CPU2
10409 10:06:26.312547 <6>[ 0.101547] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10410 10:06:26.322491 <6>[ 0.101562] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10411 10:06:26.325936 <6>[ 0.101821] Detected VIPT I-cache on CPU3
10412 10:06:26.332597 <6>[ 0.101867] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10413 10:06:26.338764 <6>[ 0.101881] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10414 10:06:26.342538 <6>[ 0.102183] CPU features: detected: Spectre-v4
10415 10:06:26.348975 <6>[ 0.102190] CPU features: detected: Spectre-BHB
10416 10:06:26.352177 <6>[ 0.102195] Detected PIPT I-cache on CPU4
10417 10:06:26.359083 <6>[ 0.102251] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10418 10:06:26.365736 <6>[ 0.102268] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10419 10:06:26.372345 <6>[ 0.102562] Detected PIPT I-cache on CPU5
10420 10:06:26.378382 <6>[ 0.102626] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10421 10:06:26.385530 <6>[ 0.102642] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10422 10:06:26.388618 <6>[ 0.102924] Detected PIPT I-cache on CPU6
10423 10:06:26.394937 <6>[ 0.102989] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10424 10:06:26.402018 <6>[ 0.103005] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10425 10:06:26.408398 <6>[ 0.103299] Detected PIPT I-cache on CPU7
10426 10:06:26.415237 <6>[ 0.103364] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10427 10:06:26.421710 <6>[ 0.103380] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10428 10:06:26.424928 <6>[ 0.103428] smp: Brought up 1 node, 8 CPUs
10429 10:06:26.431664 <6>[ 0.244819] SMP: Total of 8 processors activated.
10430 10:06:26.435196 <6>[ 0.249739] CPU features: detected: 32-bit EL0 Support
10431 10:06:26.445069 <6>[ 0.255103] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10432 10:06:26.451387 <6>[ 0.263903] CPU features: detected: Common not Private translations
10433 10:06:26.454677 <6>[ 0.270419] CPU features: detected: CRC32 instructions
10434 10:06:26.461707 <6>[ 0.275770] CPU features: detected: RCpc load-acquire (LDAPR)
10435 10:06:26.468371 <6>[ 0.281730] CPU features: detected: LSE atomic instructions
10436 10:06:26.474763 <6>[ 0.287511] CPU features: detected: Privileged Access Never
10437 10:06:26.477858 <6>[ 0.293326] CPU features: detected: RAS Extension Support
10438 10:06:26.487791 <6>[ 0.298970] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10439 10:06:26.491624 <6>[ 0.306232] CPU: All CPU(s) started at EL2
10440 10:06:26.497908 <6>[ 0.310575] alternatives: applying system-wide alternatives
10441 10:06:26.507022 <6>[ 0.321317] devtmpfs: initialized
10442 10:06:26.519275 <6>[ 0.330303] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10443 10:06:26.529229 <6>[ 0.340268] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10444 10:06:26.535522 <6>[ 0.348285] pinctrl core: initialized pinctrl subsystem
10445 10:06:26.539079 <6>[ 0.354959] DMI not present or invalid.
10446 10:06:26.545540 <6>[ 0.359374] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10447 10:06:26.555350 <6>[ 0.366250] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10448 10:06:26.562011 <6>[ 0.373834] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10449 10:06:26.572082 <6>[ 0.382051] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10450 10:06:26.575195 <6>[ 0.390296] audit: initializing netlink subsys (disabled)
10451 10:06:26.585441 <5>[ 0.395992] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10452 10:06:26.592091 <6>[ 0.396701] thermal_sys: Registered thermal governor 'step_wise'
10453 10:06:26.598604 <6>[ 0.403964] thermal_sys: Registered thermal governor 'power_allocator'
10454 10:06:26.601595 <6>[ 0.410222] cpuidle: using governor menu
10455 10:06:26.608109 <6>[ 0.421188] NET: Registered PF_QIPCRTR protocol family
10456 10:06:26.614870 <6>[ 0.426682] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10457 10:06:26.621802 <6>[ 0.433790] ASID allocator initialised with 32768 entries
10458 10:06:26.624915 <6>[ 0.440366] Serial: AMBA PL011 UART driver
10459 10:06:26.634489 <4>[ 0.449166] Trying to register duplicate clock ID: 134
10460 10:06:26.690859 <6>[ 0.508577] KASLR enabled
10461 10:06:26.705119 <6>[ 0.516319] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10462 10:06:26.711991 <6>[ 0.523338] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10463 10:06:26.718637 <6>[ 0.529831] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10464 10:06:26.725455 <6>[ 0.536842] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10465 10:06:26.731883 <6>[ 0.543335] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10466 10:06:26.738288 <6>[ 0.550346] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10467 10:06:26.745237 <6>[ 0.556839] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10468 10:06:26.751701 <6>[ 0.563849] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10469 10:06:26.754806 <6>[ 0.571356] ACPI: Interpreter disabled.
10470 10:06:26.763260 <6>[ 0.577756] iommu: Default domain type: Translated
10471 10:06:26.770340 <6>[ 0.582870] iommu: DMA domain TLB invalidation policy: strict mode
10472 10:06:26.773547 <5>[ 0.589530] SCSI subsystem initialized
10473 10:06:26.779905 <6>[ 0.593697] usbcore: registered new interface driver usbfs
10474 10:06:26.786378 <6>[ 0.599433] usbcore: registered new interface driver hub
10475 10:06:26.789698 <6>[ 0.604987] usbcore: registered new device driver usb
10476 10:06:26.796562 <6>[ 0.611083] pps_core: LinuxPPS API ver. 1 registered
10477 10:06:26.806327 <6>[ 0.616279] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10478 10:06:26.809762 <6>[ 0.625627] PTP clock support registered
10479 10:06:26.813216 <6>[ 0.629872] EDAC MC: Ver: 3.0.0
10480 10:06:26.820463 <6>[ 0.635032] FPGA manager framework
10481 10:06:26.827168 <6>[ 0.638712] Advanced Linux Sound Architecture Driver Initialized.
10482 10:06:26.830453 <6>[ 0.645485] vgaarb: loaded
10483 10:06:26.837055 <6>[ 0.648676] clocksource: Switched to clocksource arch_sys_counter
10484 10:06:26.840396 <5>[ 0.655111] VFS: Disk quotas dquot_6.6.0
10485 10:06:26.847253 <6>[ 0.659296] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10486 10:06:26.850426 <6>[ 0.666487] pnp: PnP ACPI: disabled
10487 10:06:26.858803 <6>[ 0.673180] NET: Registered PF_INET protocol family
10488 10:06:26.865282 <6>[ 0.678780] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10489 10:06:26.879679 <6>[ 0.691106] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10490 10:06:26.889663 <6>[ 0.699924] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10491 10:06:26.896183 <6>[ 0.707896] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10492 10:06:26.906249 <6>[ 0.716598] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10493 10:06:26.912715 <6>[ 0.726309] TCP: Hash tables configured (established 65536 bind 65536)
10494 10:06:26.919620 <6>[ 0.733166] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 10:06:26.929754 <6>[ 0.740366] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10496 10:06:26.932659 <6>[ 0.748067] NET: Registered PF_UNIX/PF_LOCAL protocol family
10497 10:06:26.939527 <6>[ 0.754236] RPC: Registered named UNIX socket transport module.
10498 10:06:26.946671 <6>[ 0.760393] RPC: Registered udp transport module.
10499 10:06:26.949811 <6>[ 0.765326] RPC: Registered tcp transport module.
10500 10:06:26.956301 <6>[ 0.770260] RPC: Registered tcp NFSv4.1 backchannel transport module.
10501 10:06:26.963044 <6>[ 0.776932] PCI: CLS 0 bytes, default 64
10502 10:06:26.965843 <6>[ 0.781322] Unpacking initramfs...
10503 10:06:26.990101 <6>[ 0.800794] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10504 10:06:26.999708 <6>[ 0.809445] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10505 10:06:27.003032 <6>[ 0.818293] kvm [1]: IPA Size Limit: 40 bits
10506 10:06:27.009417 <6>[ 0.822822] kvm [1]: GICv3: no GICV resource entry
10507 10:06:27.012754 <6>[ 0.827846] kvm [1]: disabling GICv2 emulation
10508 10:06:27.019594 <6>[ 0.832537] kvm [1]: GIC system register CPU interface enabled
10509 10:06:27.022850 <6>[ 0.838715] kvm [1]: vgic interrupt IRQ18
10510 10:06:27.029284 <6>[ 0.843076] kvm [1]: VHE mode initialized successfully
10511 10:06:27.036346 <5>[ 0.849526] Initialise system trusted keyrings
10512 10:06:27.042778 <6>[ 0.854339] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10513 10:06:27.049862 <6>[ 0.864363] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10514 10:06:27.056647 <5>[ 0.870815] NFS: Registering the id_resolver key type
10515 10:06:27.059652 <5>[ 0.876124] Key type id_resolver registered
10516 10:06:27.066795 <5>[ 0.880540] Key type id_legacy registered
10517 10:06:27.073366 <6>[ 0.884823] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10518 10:06:27.079393 <6>[ 0.891746] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10519 10:06:27.086116 <6>[ 0.899460] 9p: Installing v9fs 9p2000 file system support
10520 10:06:27.122424 <5>[ 0.936629] Key type asymmetric registered
10521 10:06:27.125473 <5>[ 0.940982] Asymmetric key parser 'x509' registered
10522 10:06:27.135830 <6>[ 0.946134] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10523 10:06:27.138508 <6>[ 0.953757] io scheduler mq-deadline registered
10524 10:06:27.142343 <6>[ 0.958521] io scheduler kyber registered
10525 10:06:27.161081 <6>[ 0.975647] EINJ: ACPI disabled.
10526 10:06:27.194019 <4>[ 1.001742] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 10:06:27.203591 <4>[ 1.012419] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 10:06:27.218549 <6>[ 1.033371] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10529 10:06:27.227045 <6>[ 1.041472] printk: console [ttyS0] disabled
10530 10:06:27.254933 <6>[ 1.066118] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10531 10:06:27.261714 <6>[ 1.075598] printk: console [ttyS0] enabled
10532 10:06:27.264962 <6>[ 1.075598] printk: console [ttyS0] enabled
10533 10:06:27.271572 <6>[ 1.084495] printk: bootconsole [mtk8250] disabled
10534 10:06:27.274699 <6>[ 1.084495] printk: bootconsole [mtk8250] disabled
10535 10:06:27.281232 <6>[ 1.095653] SuperH (H)SCI(F) driver initialized
10536 10:06:27.284640 <6>[ 1.100952] msm_serial: driver initialized
10537 10:06:27.298776 <6>[ 1.109986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10538 10:06:27.309133 <6>[ 1.118533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10539 10:06:27.315510 <6>[ 1.127075] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10540 10:06:27.325801 <6>[ 1.135703] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10541 10:06:27.332053 <6>[ 1.144420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10542 10:06:27.341892 <6>[ 1.153134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10543 10:06:27.352206 <6>[ 1.161674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10544 10:06:27.358579 <6>[ 1.170478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10545 10:06:27.368816 <6>[ 1.179021] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10546 10:06:27.380060 <6>[ 1.194796] loop: module loaded
10547 10:06:27.387157 <6>[ 1.200874] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10548 10:06:27.409664 <4>[ 1.224393] mtk-pmic-keys: Failed to locate of_node [id: -1]
10549 10:06:27.416725 <6>[ 1.231321] megasas: 07.719.03.00-rc1
10550 10:06:27.426359 <6>[ 1.240880] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10551 10:06:27.433926 <6>[ 1.248059] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10552 10:06:27.450226 <6>[ 1.264628] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10553 10:06:27.506690 <6>[ 1.314422] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10554 10:06:27.704186 <6>[ 1.518713] Freeing initrd memory: 17376K
10555 10:06:27.714901 <6>[ 1.529151] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10556 10:06:27.726018 <6>[ 1.540296] tun: Universal TUN/TAP device driver, 1.6
10557 10:06:27.729316 <6>[ 1.546376] thunder_xcv, ver 1.0
10558 10:06:27.732443 <6>[ 1.549882] thunder_bgx, ver 1.0
10559 10:06:27.735940 <6>[ 1.553380] nicpf, ver 1.0
10560 10:06:27.746245 <6>[ 1.557406] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10561 10:06:27.749655 <6>[ 1.564883] hns3: Copyright (c) 2017 Huawei Corporation.
10562 10:06:27.753167 <6>[ 1.570472] hclge is initializing
10563 10:06:27.759397 <6>[ 1.574052] e1000: Intel(R) PRO/1000 Network Driver
10564 10:06:27.766392 <6>[ 1.579181] e1000: Copyright (c) 1999-2006 Intel Corporation.
10565 10:06:27.769594 <6>[ 1.585196] e1000e: Intel(R) PRO/1000 Network Driver
10566 10:06:27.776232 <6>[ 1.590411] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10567 10:06:27.782683 <6>[ 1.596597] igb: Intel(R) Gigabit Ethernet Network Driver
10568 10:06:27.789235 <6>[ 1.602247] igb: Copyright (c) 2007-2014 Intel Corporation.
10569 10:06:27.795978 <6>[ 1.608084] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10570 10:06:27.803051 <6>[ 1.614602] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10571 10:06:27.806225 <6>[ 1.621070] sky2: driver version 1.30
10572 10:06:27.812621 <6>[ 1.626087] VFIO - User Level meta-driver version: 0.3
10573 10:06:27.820034 <6>[ 1.634369] usbcore: registered new interface driver usb-storage
10574 10:06:27.826813 <6>[ 1.640814] usbcore: registered new device driver onboard-usb-hub
10575 10:06:27.835740 <6>[ 1.650015] mt6397-rtc mt6359-rtc: registered as rtc0
10576 10:06:27.845490 <6>[ 1.655482] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:04:17 UTC (1700820257)
10577 10:06:27.848793 <6>[ 1.665056] i2c_dev: i2c /dev entries driver
10578 10:06:27.865728 <6>[ 1.676904] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10579 10:06:27.885401 <6>[ 1.699904] cpu cpu0: EM: created perf domain
10580 10:06:27.888677 <6>[ 1.704852] cpu cpu4: EM: created perf domain
10581 10:06:27.895927 <6>[ 1.710461] sdhci: Secure Digital Host Controller Interface driver
10582 10:06:27.902480 <6>[ 1.716894] sdhci: Copyright(c) Pierre Ossman
10583 10:06:27.909617 <6>[ 1.721853] Synopsys Designware Multimedia Card Interface Driver
10584 10:06:27.916140 <6>[ 1.728484] sdhci-pltfm: SDHCI platform and OF driver helper
10585 10:06:27.919252 <6>[ 1.728593] mmc0: CQHCI version 5.10
10586 10:06:27.925785 <6>[ 1.738449] ledtrig-cpu: registered to indicate activity on CPUs
10587 10:06:27.932301 <6>[ 1.745435] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 10:06:27.939451 <6>[ 1.752484] usbcore: registered new interface driver usbhid
10589 10:06:27.942247 <6>[ 1.758308] usbhid: USB HID core driver
10590 10:06:27.949433 <6>[ 1.762507] spi_master spi0: will run message pump with realtime priority
10591 10:06:27.992121 <6>[ 1.799707] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 10:06:28.010462 <6>[ 1.814954] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 10:06:28.017753 <6>[ 1.829893] cros-ec-spi spi0.0: Chrome EC device registered
10594 10:06:28.021429 <6>[ 1.835997] mmc0: Command Queue Engine enabled
10595 10:06:28.027680 <6>[ 1.840760] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 10:06:28.034665 <6>[ 1.848463] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 10:06:28.045600 <6>[ 1.859875] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10598 10:06:28.055274 <6>[ 1.864854] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10599 10:06:28.062291 <6>[ 1.867129] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10600 10:06:28.065249 <6>[ 1.876307] NET: Registered PF_PACKET protocol family
10601 10:06:28.072189 <6>[ 1.881141] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10602 10:06:28.075400 <6>[ 1.885709] 9pnet: Installing 9P2000 support
10603 10:06:28.081962 <6>[ 1.891563] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10604 10:06:28.085247 <5>[ 1.895415] Key type dns_resolver registered
10605 10:06:28.092108 <6>[ 1.906857] registered taskstats version 1
10606 10:06:28.095108 <5>[ 1.911235] Loading compiled-in X.509 certificates
10607 10:06:28.126388 <4>[ 1.934079] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 10:06:28.136411 <4>[ 1.945018] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 10:06:28.142887 <3>[ 1.955565] debugfs: File 'uA_load' in directory '/' already present!
10610 10:06:28.149430 <3>[ 1.962321] debugfs: File 'min_uV' in directory '/' already present!
10611 10:06:28.155858 <3>[ 1.968954] debugfs: File 'max_uV' in directory '/' already present!
10612 10:06:28.162905 <3>[ 1.975674] debugfs: File 'constraint_flags' in directory '/' already present!
10613 10:06:28.174168 <3>[ 1.985435] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10614 10:06:28.183150 <6>[ 1.997693] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10615 10:06:28.189732 <6>[ 2.004455] xhci-mtk 11200000.usb: xHCI Host Controller
10616 10:06:28.196787 <6>[ 2.009960] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10617 10:06:28.206900 <6>[ 2.017797] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 10:06:28.213549 <6>[ 2.027223] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10619 10:06:28.220246 <6>[ 2.033267] xhci-mtk 11200000.usb: xHCI Host Controller
10620 10:06:28.226862 <6>[ 2.038742] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10621 10:06:28.233174 <6>[ 2.046385] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10622 10:06:28.239917 <6>[ 2.054071] hub 1-0:1.0: USB hub found
10623 10:06:28.243003 <6>[ 2.058080] hub 1-0:1.0: 1 port detected
10624 10:06:28.249817 <6>[ 2.062343] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10625 10:06:28.256818 <6>[ 2.070861] hub 2-0:1.0: USB hub found
10626 10:06:28.260099 <6>[ 2.074864] hub 2-0:1.0: 1 port detected
10627 10:06:28.269039 <6>[ 2.083253] mtk-msdc 11f70000.mmc: Got CD GPIO
10628 10:06:28.278821 <6>[ 2.089798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10629 10:06:28.285302 <6>[ 2.097821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10630 10:06:28.295661 <4>[ 2.105797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10631 10:06:28.305392 <6>[ 2.115328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10632 10:06:28.311941 <6>[ 2.123425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10633 10:06:28.318879 <6>[ 2.131435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10634 10:06:28.328425 <6>[ 2.139363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10635 10:06:28.335584 <6>[ 2.147184] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10636 10:06:28.345397 <6>[ 2.155013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10637 10:06:28.355471 <6>[ 2.165439] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10638 10:06:28.362160 <6>[ 2.173818] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10639 10:06:28.371856 <6>[ 2.182161] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10640 10:06:28.378366 <6>[ 2.190513] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10641 10:06:28.388245 <6>[ 2.198852] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10642 10:06:28.395467 <6>[ 2.207203] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10643 10:06:28.405432 <6>[ 2.215543] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10644 10:06:28.412197 <6>[ 2.223895] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10645 10:06:28.421667 <6>[ 2.232238] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10646 10:06:28.428536 <6>[ 2.240587] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10647 10:06:28.438364 <6>[ 2.248928] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10648 10:06:28.444860 <6>[ 2.257269] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10649 10:06:28.455169 <6>[ 2.265608] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10650 10:06:28.461749 <6>[ 2.273946] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10651 10:06:28.472270 <6>[ 2.282284] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10652 10:06:28.478361 <6>[ 2.291064] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10653 10:06:28.485230 <6>[ 2.298234] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10654 10:06:28.491677 <6>[ 2.305000] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10655 10:06:28.498462 <6>[ 2.311760] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10656 10:06:28.505063 <6>[ 2.318694] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10657 10:06:28.514831 <6>[ 2.325537] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10658 10:06:28.524822 <6>[ 2.334664] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10659 10:06:28.535065 <6>[ 2.343783] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10660 10:06:28.541511 <6>[ 2.353099] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10661 10:06:28.551262 <6>[ 2.362576] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10662 10:06:28.560975 <6>[ 2.372046] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10663 10:06:28.571389 <6>[ 2.381167] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10664 10:06:28.580979 <6>[ 2.390634] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10665 10:06:28.591276 <6>[ 2.399752] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10666 10:06:28.600889 <6>[ 2.409046] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10667 10:06:28.611021 <6>[ 2.419206] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10668 10:06:28.620508 <6>[ 2.430855] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10669 10:06:28.627093 <6>[ 2.440474] Trying to probe devices needed for running init ...
10670 10:06:28.649746 <6>[ 2.461172] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 10:06:28.677219 <6>[ 2.491834] hub 2-1:1.0: USB hub found
10672 10:06:28.680446 <6>[ 2.496255] hub 2-1:1.0: 3 ports detected
10673 10:06:28.688879 <6>[ 2.503245] hub 2-1:1.0: USB hub found
10674 10:06:28.691942 <6>[ 2.507756] hub 2-1:1.0: 3 ports detected
10675 10:06:28.801748 <6>[ 2.612973] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10676 10:06:28.956359 <6>[ 2.771032] hub 1-1:1.0: USB hub found
10677 10:06:28.959916 <6>[ 2.775500] hub 1-1:1.0: 4 ports detected
10678 10:06:28.969005 <6>[ 2.783869] hub 1-1:1.0: USB hub found
10679 10:06:28.972806 <6>[ 2.788409] hub 1-1:1.0: 4 ports detected
10680 10:06:29.041383 <6>[ 2.853043] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10681 10:06:29.293602 <6>[ 3.104946] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10682 10:06:29.426340 <6>[ 3.240960] hub 1-1.4:1.0: USB hub found
10683 10:06:29.429602 <6>[ 3.245636] hub 1-1.4:1.0: 2 ports detected
10684 10:06:29.439516 <6>[ 3.254210] hub 1-1.4:1.0: USB hub found
10685 10:06:29.442649 <6>[ 3.258883] hub 1-1.4:1.0: 2 ports detected
10686 10:06:29.741425 <6>[ 3.552972] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10687 10:06:29.933807 <6>[ 3.744972] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10688 10:06:40.914702 <6>[ 14.733968] ALSA device list:
10689 10:06:40.921089 <6>[ 14.737260] No soundcards found.
10690 10:06:40.929453 <6>[ 14.745186] Freeing unused kernel memory: 8384K
10691 10:06:40.932329 <6>[ 14.750174] Run /init as init process
10692 10:06:40.943420 Loading, please wait...
10693 10:06:40.964344 Starting version 247.3-7+deb11u2
10694 10:06:41.156844 <6>[ 14.969658] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10695 10:06:41.165684 <6>[ 14.981715] remoteproc remoteproc0: scp is available
10696 10:06:41.172739 <6>[ 14.987312] remoteproc remoteproc0: powering up scp
10697 10:06:41.178917 <6>[ 14.992498] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10698 10:06:41.186138 <6>[ 15.002275] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10699 10:06:41.208377 <3>[ 15.020896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 10:06:41.214709 <6>[ 15.022514] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10701 10:06:41.224827 <3>[ 15.029151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 10:06:41.231675 <6>[ 15.036655] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10703 10:06:41.241286 <3>[ 15.044812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 10:06:41.248283 <6>[ 15.053456] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10705 10:06:41.261694 <6>[ 15.077620] mc: Linux media interface: v0.10
10706 10:06:41.272473 <3>[ 15.085314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 10:06:41.279183 <4>[ 15.091863] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10708 10:06:41.289554 <3>[ 15.093499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 10:06:41.296049 <6>[ 15.097747] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10710 10:06:41.302532 <4>[ 15.101247] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 10:06:41.312706 <3>[ 15.108837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 10:06:41.318959 <3>[ 15.108844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 10:06:41.326130 <6>[ 15.116977] videodev: Linux video capture interface: v2.00
10714 10:06:41.332290 <3>[ 15.123790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 10:06:41.339065 <6>[ 15.123860] usbcore: registered new interface driver r8152
10716 10:06:41.345406 <3>[ 15.125450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 10:06:41.355667 <3>[ 15.126972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 10:06:41.362315 <3>[ 15.126995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 10:06:41.372718 <3>[ 15.126998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 10:06:41.379579 <3>[ 15.130517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 10:06:41.385804 <3>[ 15.130548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 10:06:41.396451 <3>[ 15.130557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 10:06:41.402936 <3>[ 15.130569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 10:06:41.412940 <3>[ 15.130578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 10:06:41.419579 <3>[ 15.130645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 10:06:41.429711 <6>[ 15.133276] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10727 10:06:41.436033 <6>[ 15.133281] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10728 10:06:41.443271 <4>[ 15.160009] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10729 10:06:41.449641 <4>[ 15.160009] Fallback method does not support PEC.
10730 10:06:41.456030 <6>[ 15.168065] remoteproc remoteproc0: remote processor scp is now up
10731 10:06:41.463170 <6>[ 15.185171] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10732 10:06:41.469603 <6>[ 15.189964] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10733 10:06:41.476109 <6>[ 15.189969] pci_bus 0000:00: root bus resource [bus 00-ff]
10734 10:06:41.482719 <6>[ 15.189973] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10735 10:06:41.492263 <6>[ 15.189976] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10736 10:06:41.499062 <6>[ 15.190009] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10737 10:06:41.505773 <6>[ 15.190022] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10738 10:06:41.512479 <6>[ 15.190091] pci 0000:00:00.0: supports D1 D2
10739 10:06:41.519124 <6>[ 15.190094] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10740 10:06:41.525389 <6>[ 15.191056] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10741 10:06:41.532204 <6>[ 15.191142] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10742 10:06:41.538640 <6>[ 15.191166] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10743 10:06:41.548457 <6>[ 15.191181] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10744 10:06:41.555312 <6>[ 15.191196] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10745 10:06:41.558320 <6>[ 15.191298] pci 0000:01:00.0: supports D1 D2
10746 10:06:41.564830 <6>[ 15.191300] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10747 10:06:41.575453 <3>[ 15.191773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10748 10:06:41.581784 <6>[ 15.200856] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 10:06:41.591987 <6>[ 15.205124] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10750 10:06:41.601729 <6>[ 15.205524] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10751 10:06:41.607919 <6>[ 15.211248] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10752 10:06:41.618516 <6>[ 15.212965] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10753 10:06:41.624949 <3>[ 15.215164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 10:06:41.635113 <6>[ 15.216415] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10755 10:06:41.641208 <6>[ 15.221373] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10756 10:06:41.651594 <4>[ 15.244798] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10757 10:06:41.658220 <6>[ 15.252839] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10758 10:06:41.667934 <4>[ 15.256285] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10759 10:06:41.674986 <6>[ 15.270072] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10760 10:06:41.678322 <6>[ 15.274159] Bluetooth: Core ver 2.22
10761 10:06:41.684865 <6>[ 15.274227] NET: Registered PF_BLUETOOTH protocol family
10762 10:06:41.691148 <6>[ 15.274229] Bluetooth: HCI device and connection manager initialized
10763 10:06:41.698245 <6>[ 15.274245] Bluetooth: HCI socket layer initialized
10764 10:06:41.701421 <6>[ 15.274248] Bluetooth: L2CAP socket layer initialized
10765 10:06:41.707828 <6>[ 15.274254] Bluetooth: SCO socket layer initialized
10766 10:06:41.714878 <6>[ 15.276938] usbcore: registered new interface driver cdc_ether
10767 10:06:41.721386 <6>[ 15.277567] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10768 10:06:41.734764 <6>[ 15.278797] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10769 10:06:41.737999 <6>[ 15.278943] usbcore: registered new interface driver uvcvideo
10770 10:06:41.747694 <6>[ 15.284578] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10771 10:06:41.750784 <6>[ 15.284860] r8152 2-1.3:1.0 eth0: v1.12.13
10772 10:06:41.757465 <6>[ 15.297376] usbcore: registered new interface driver r8153_ecm
10773 10:06:41.764365 <6>[ 15.304292] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10774 10:06:41.770897 <6>[ 15.314964] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10775 10:06:41.777770 <6>[ 15.320467] pci 0000:00:00.0: PCI bridge to [bus 01]
10776 10:06:41.784482 <6>[ 15.323645] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10777 10:06:41.787711 <6>[ 15.332935] usbcore: registered new interface driver btusb
10778 10:06:41.801038 <4>[ 15.333790] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10779 10:06:41.804378 <3>[ 15.333796] Bluetooth: hci0: Failed to load firmware file (-2)
10780 10:06:41.810648 <3>[ 15.333798] Bluetooth: hci0: Failed to set up firmware (-2)
10781 10:06:41.820373 <4>[ 15.333800] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10782 10:06:41.830574 <6>[ 15.339296] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10783 10:06:41.837417 <6>[ 15.650808] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10784 10:06:41.844088 <6>[ 15.657615] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10785 10:06:41.850364 <6>[ 15.663955] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10786 10:06:41.866296 <5>[ 15.679072] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10787 10:06:41.884523 <5>[ 15.700112] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10788 10:06:41.894478 <4>[ 15.707159] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 10:06:41.901443 <6>[ 15.716062] cfg80211: failed to load regulatory.db
10790 10:06:41.957411 <6>[ 15.770321] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10791 10:06:41.963942 <6>[ 15.777869] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10792 10:06:41.988521 <6>[ 15.804722] mt7921e 0000:01:00.0: ASIC revision: 79610010
10793 10:06:42.095179 <4>[ 15.904478] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 10:06:42.102675 Begin: Loading essential drivers ... done.
10795 10:06:42.106247 Begin: Running /scripts/init-premount ... done.
10796 10:06:42.113109 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10797 10:06:42.123474 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10798 10:06:42.126128 Device /sys/class/net/enx00e04c787aaa found
10799 10:06:42.126208 done.
10800 10:06:42.218136 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mt<4>[ 16.025769] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 10:06:42.218257 u 1500 DHCP
10802 10:06:42.339096 <4>[ 16.148508] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 10:06:42.458693 <4>[ 16.268436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 10:06:42.578641 <4>[ 16.388472] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 10:06:42.698614 <4>[ 16.508309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 10:06:42.818921 <4>[ 16.628475] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 10:06:42.938426 <4>[ 16.748274] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 10:06:43.058447 <4>[ 16.868292] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 10:06:43.154727 <6>[ 16.971113] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10810 10:06:43.182412 <4>[ 16.991915] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 10:06:43.293829 <3>[ 17.110254] mt7921e 0000:01:00.0: hardware init failed
10812 10:06:43.339259 IP-Config: no response after 2 secs - giving up
10813 10:06:43.371904 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10814 10:06:44.474387 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10815 10:06:44.481213 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 10:06:44.487674 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 10:06:44.493946 host : mt8192-asurada-spherion-r0-cbg-0
10818 10:06:44.500915 domain : lava-rack
10819 10:06:44.503724 rootserver: 192.168.201.1 rootpath:
10820 10:06:44.507598 filename :
10821 10:06:44.599264 done.
10822 10:06:44.605583 Begin: Running /scripts/nfs-bottom ... done.
10823 10:06:44.626949 Begin: Running /scripts/init-bottom ... done.
10824 10:06:45.788062 <6>[ 19.604983] NET: Registered PF_INET6 protocol family
10825 10:06:45.795516 <6>[ 19.612204] Segment Routing with IPv6
10826 10:06:45.799114 <6>[ 19.616236] In-situ OAM (IOAM) with IPv6
10827 10:06:45.913782 <30>[ 19.710220] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10828 10:06:45.916741 <30>[ 19.734553] systemd[1]: Detected architecture arm64.
10829 10:06:45.937213
10830 10:06:45.940419 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10831 10:06:45.940510
10832 10:06:45.958344 <30>[ 19.775078] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10833 10:06:46.782779 <30>[ 20.596316] systemd[1]: Queued start job for default target Graphical Interface.
10834 10:06:46.818689 <30>[ 20.635325] systemd[1]: Created slice system-getty.slice.
10835 10:06:46.825311 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10836 10:06:46.841706 <30>[ 20.658437] systemd[1]: Created slice system-modprobe.slice.
10837 10:06:46.847989 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10838 10:06:46.866174 <30>[ 20.682949] systemd[1]: Created slice system-serial\x2dgetty.slice.
10839 10:06:46.876889 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10840 10:06:46.889712 <30>[ 20.706063] systemd[1]: Created slice User and Session Slice.
10841 10:06:46.896250 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10842 10:06:46.916314 <30>[ 20.729455] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10843 10:06:46.925910 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10844 10:06:46.944667 <30>[ 20.757718] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10845 10:06:46.950917 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10846 10:06:46.975167 <30>[ 20.785133] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10847 10:06:46.981725 <30>[ 20.797297] systemd[1]: Reached target Local Encrypted Volumes.
10848 10:06:46.988428 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10849 10:06:47.004654 <30>[ 20.821493] systemd[1]: Reached target Paths.
10850 10:06:47.011040 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10851 10:06:47.024496 <30>[ 20.840989] systemd[1]: Reached target Remote File Systems.
10852 10:06:47.030904 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10853 10:06:47.049078 <30>[ 20.865330] systemd[1]: Reached target Slices.
10854 10:06:47.055532 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10855 10:06:47.068580 <30>[ 20.885006] systemd[1]: Reached target Swap.
10856 10:06:47.071699 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10857 10:06:47.092172 <30>[ 20.905489] systemd[1]: Listening on initctl Compatibility Named Pipe.
10858 10:06:47.099067 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10859 10:06:47.105393 <30>[ 20.921579] systemd[1]: Listening on Journal Audit Socket.
10860 10:06:47.111878 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10861 10:06:47.129432 <30>[ 20.946081] systemd[1]: Listening on Journal Socket (/dev/log).
10862 10:06:47.135988 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10863 10:06:47.152964 <30>[ 20.969707] systemd[1]: Listening on Journal Socket.
10864 10:06:47.159407 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10865 10:06:47.173714 <30>[ 20.990333] systemd[1]: Listening on Network Service Netlink Socket.
10866 10:06:47.184092 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10867 10:06:47.198661 <30>[ 21.015626] systemd[1]: Listening on udev Control Socket.
10868 10:06:47.205787 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10869 10:06:47.220586 <30>[ 21.037419] systemd[1]: Listening on udev Kernel Socket.
10870 10:06:47.227273 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10871 10:06:47.284245 <30>[ 21.101169] systemd[1]: Mounting Huge Pages File System...
10872 10:06:47.291142 Mounting [0;1;39mHuge Pages File System[0m...
10873 10:06:47.308829 <30>[ 21.125650] systemd[1]: Mounting POSIX Message Queue File System...
10874 10:06:47.315856 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10875 10:06:47.337212 <30>[ 21.153636] systemd[1]: Mounting Kernel Debug File System...
10876 10:06:47.343303 Mounting [0;1;39mKernel Debug File System[0m...
10877 10:06:47.360270 <30>[ 21.173554] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10878 10:06:47.375565 <30>[ 21.189160] systemd[1]: Starting Create list of static device nodes for the current kernel...
10879 10:06:47.385621 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10880 10:06:47.405340 <30>[ 21.222144] systemd[1]: Starting Load Kernel Module configfs...
10881 10:06:47.412461 Starting [0;1;39mLoad Kernel Module configfs[0m...
10882 10:06:47.433099 <30>[ 21.249609] systemd[1]: Starting Load Kernel Module drm...
10883 10:06:47.439290 Starting [0;1;39mLoad Kernel Module drm[0m...
10884 10:06:47.457320 <30>[ 21.273841] systemd[1]: Starting Load Kernel Module fuse...
10885 10:06:47.463819 Starting [0;1;39mLoad Kernel Module fuse[0m...
10886 10:06:47.499537 <30>[ 21.312824] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10887 10:06:47.506763 <6>[ 21.322999] fuse: init (API version 7.37)
10888 10:06:47.537175 <30>[ 21.353748] systemd[1]: Starting Journal Service...
10889 10:06:47.543329 Starting [0;1;39mJournal Service[0m...
10890 10:06:47.565251 <30>[ 21.381710] systemd[1]: Starting Load Kernel Modules...
10891 10:06:47.571480 Starting [0;1;39mLoad Kernel Modules[0m...
10892 10:06:47.592781 <30>[ 21.406010] systemd[1]: Starting Remount Root and Kernel File Systems...
10893 10:06:47.599178 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10894 10:06:47.617529 <30>[ 21.434121] systemd[1]: Starting Coldplug All udev Devices...
10895 10:06:47.623961 Starting [0;1;39mColdplug All udev Devices[0m...
10896 10:06:47.647235 <30>[ 21.463496] systemd[1]: Mounted Huge Pages File System.
10897 10:06:47.653418 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10898 10:06:47.669086 <30>[ 21.485748] systemd[1]: Mounted POSIX Message Queue File System.
10899 10:06:47.675564 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10900 10:06:47.697265 <30>[ 21.513446] systemd[1]: Mounted Kernel Debug File System.
10901 10:06:47.710272 [[0;32m OK [0m] Mounted [0;<3>[ 21.521422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 10:06:47.713861 1;39mKernel Debug File System[0m.
10903 10:06:47.737484 <30>[ 21.550435] systemd[1]: Finished Create list of static device nodes for the current kernel.
10904 10:06:47.746991 [[0;32m OK [<3>[ 21.560784] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 10:06:47.753551 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10906 10:06:47.769291 <30>[ 21.586164] systemd[1]: modprobe@configfs.service: Succeeded.
10907 10:06:47.776480 <30>[ 21.593347] systemd[1]: Finished Load Kernel Module configfs.
10908 10:06:47.782857 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10909 10:06:47.801969 <30>[ 21.618479] systemd[1]: modprobe@drm.service: Succeeded.
10910 10:06:47.811623 <3>[ 21.620207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 10:06:47.818543 <30>[ 21.625553] systemd[1]: Finished Load Kernel Module drm.
10912 10:06:47.821812 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10913 10:06:47.842235 <3>[ 21.655614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 10:06:47.849487 <30>[ 21.666070] systemd[1]: modprobe@fuse.service: Succeeded.
10915 10:06:47.856448 <30>[ 21.673236] systemd[1]: Finished Load Kernel Module fuse.
10916 10:06:47.863537 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10917 10:06:47.874164 <3>[ 21.687339] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 10:06:47.882782 <30>[ 21.699292] systemd[1]: Finished Load Kernel Modules.
10919 10:06:47.889256 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10920 10:06:47.907856 <3>[ 21.721490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 10:06:47.914821 <30>[ 21.721615] systemd[1]: Finished Remount Root and Kernel File Systems.
10922 10:06:47.924409 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10923 10:06:47.939691 <3>[ 21.753052] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 10:06:47.971714 <3>[ 21.785001] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 10:06:47.978327 <30>[ 21.786342] systemd[1]: Mounting FUSE Control File System...
10926 10:06:47.984713 Mounting [0;1;39mFUSE Control File System[0m...
10927 10:06:48.001388 <30>[ 21.817555] systemd[1]: Mounting Kernel Configuration File System...
10928 10:06:48.011187 <3>[ 21.819563] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 10:06:48.017342 Mounting [0;1;39mKernel Configuration File System[0m...
10930 10:06:48.038827 <30>[ 21.851696] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10931 10:06:48.048826 <3>[ 21.854280] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 10:06:48.058630 <30>[ 21.861197] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10933 10:06:48.064886 <30>[ 21.882002] systemd[1]: Starting Load/Save Random Seed...
10934 10:06:48.072140 Starting [0;1;39mLoad/Save Random Seed[0m...
10935 10:06:48.086905 <30>[ 21.903528] systemd[1]: Starting Apply Kernel Variables...
10936 10:06:48.093774 Starting [0;1;39mApply Kernel Variables[0m...
10937 10:06:48.111991 <30>[ 21.928743] systemd[1]: Starting Create System Users...
10938 10:06:48.118547 Starting [0;1;39mCreate System Users[0m...
10939 10:06:48.134817 <30>[ 21.951544] systemd[1]: Started Journal Service.
10940 10:06:48.141303 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10941 10:06:48.164399 <4>[ 21.970978] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10942 10:06:48.171116 <3>[ 21.986648] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10943 10:06:48.177779 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10944 10:06:48.194560 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10945 10:06:48.208284 See 'systemctl status systemd-udev-trigger.service' for details.
10946 10:06:48.225416 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10947 10:06:48.241647 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10948 10:06:48.258447 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10949 10:06:48.278210 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10950 10:06:48.325612 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10951 10:06:48.342952 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10952 10:06:48.362429 <46>[ 22.176085] systemd-journald[301]: Received client request to flush runtime journal.
10953 10:06:49.461007 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10954 10:06:49.479105 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10955 10:06:49.496047 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10956 10:06:49.548316 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10957 10:06:49.793113 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10958 10:06:49.857472 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10959 10:06:49.900630 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10960 10:06:49.949787 Starting [0;1;39mNetwork Service[0m...
10961 10:06:50.219039 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10962 10:06:50.247630 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10963 10:06:50.292274 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10964 10:06:50.488234 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10965 10:06:50.646051 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10966 10:06:50.660462 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10967 10:06:50.680691 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10968 10:06:50.699665 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10969 10:06:50.756843 Starting [0;1;39mNetwork Name Resolution[0m...
10970 10:06:50.784337 Starting [0;1;39mNetwork Time Synchronization[0m...
10971 10:06:50.803754 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10972 10:06:50.825741 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10973 10:06:50.856099 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10974 10:06:50.872970 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10975 10:06:51.014223 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10976 10:06:51.032684 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10977 10:06:51.051475 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10978 10:06:51.067882 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10979 10:06:51.087930 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10980 10:06:51.195760 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10981 10:06:51.234455 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10982 10:06:51.259430 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10983 10:06:51.292280 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10984 10:06:51.303843 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10985 10:06:51.337950 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10986 10:06:51.351780 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10987 10:06:51.368401 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10988 10:06:51.421127 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10989 10:06:52.108509 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10990 10:06:52.484895 Starting [0;1;39mUser Login Management[0m...
10991 10:06:52.501303 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10992 10:06:52.523877 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10993 10:06:52.543411 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10994 10:06:52.580046 Starting [0;1;39mPermit User Sessions[0m...
10995 10:06:52.672192 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10996 10:06:52.732700 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10997 10:06:52.751816 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10998 10:06:52.772244 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10999 10:06:52.799075 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11000 10:06:52.820092 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11001 10:06:52.837993 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11002 10:06:52.856431 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11003 10:06:52.909162 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11004 10:06:52.954194 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11005 10:06:53.018804
11006 10:06:53.018944
11007 10:06:53.021913 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11008 10:06:53.021997
11009 10:06:53.025165 debian-bullseye-arm64 login: root (automatic login)
11010 10:06:53.025237
11011 10:06:53.025300
11012 10:06:53.354328 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11013 10:06:53.354473
11014 10:06:53.361159 The programs included with the Debian GNU/Linux system are free software;
11015 10:06:53.367783 the exact distribution terms for each program are described in the
11016 10:06:53.371017 individual files in /usr/share/doc/*/copyright.
11017 10:06:53.371092
11018 10:06:53.377372 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 10:06:53.381066 permitted by applicable law.
11020 10:06:54.270340 Matched prompt #10: / #
11022 10:06:54.270625 Setting prompt string to ['/ #']
11023 10:06:54.270726 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11025 10:06:54.270927 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11026 10:06:54.271016 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11027 10:06:54.271090 Setting prompt string to ['/ #']
11028 10:06:54.271152 Forcing a shell prompt, looking for ['/ #']
11030 10:06:54.321399 / #
11031 10:06:54.322103 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 10:06:54.322752 Waiting using forced prompt support (timeout 00:02:30)
11033 10:06:54.327704
11034 10:06:54.328574 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11035 10:06:54.329119 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11037 10:06:54.430455 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9'
11038 10:06:54.436729 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073332/extract-nfsrootfs-xegtlup9'
11040 10:06:54.538119 / # export NFS_SERVER_IP='192.168.201.1'
11041 10:06:54.544167 export NFS_SERVER_IP='192.168.201.1'
11042 10:06:54.544963 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11043 10:06:54.545560 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11044 10:06:54.546110 end: 2 depthcharge-action (duration 00:01:36) [common]
11045 10:06:54.546630 start: 3 lava-test-retry (timeout 00:07:23) [common]
11046 10:06:54.547103 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
11047 10:06:54.547502 Using namespace: common
11049 10:06:54.648375 / # #
11050 10:06:54.648539 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11051 10:06:54.653744 #
11052 10:06:54.654006 Using /lava-12073332
11054 10:06:54.754297 / # export SHELL=/bin/bash
11055 10:06:54.760250 export SHELL=/bin/bash
11057 10:06:54.860773 / # . /lava-12073332/environment
11058 10:06:54.865546 . /lava-12073332/environment
11060 10:06:54.970936 / # /lava-12073332/bin/lava-test-runner /lava-12073332/0
11061 10:06:54.971124 Test shell timeout: 10s (minimum of the action and connection timeout)
11062 10:06:54.976588 /lava-12073332/bin/lava-test-runner /lava-12073332/0
11063 10:06:55.209396 + export TESTRUN_ID=0_timesync-off
11064 10:06:55.212543 + TESTRUN_ID=0_timesync-off
11065 10:06:55.215724 + cd /lava-12073332/0/tests/0_timesync-off
11066 10:06:55.219506 ++ cat uuid
11067 10:06:55.219584 + UUID=12073332_1.6.2.3.1
11068 10:06:55.222341 + set +x
11069 10:06:55.225994 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12073332_1.6.2.3.1>
11070 10:06:55.226253 Received signal: <STARTRUN> 0_timesync-off 12073332_1.6.2.3.1
11071 10:06:55.226330 Starting test lava.0_timesync-off (12073332_1.6.2.3.1)
11072 10:06:55.226441 Skipping test definition patterns.
11073 10:06:55.229182 + systemctl stop systemd-timesyncd
11074 10:06:55.273411 + set +x
11075 10:06:55.276661 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12073332_1.6.2.3.1>
11076 10:06:55.277634 Received signal: <ENDRUN> 0_timesync-off 12073332_1.6.2.3.1
11077 10:06:55.278307 Ending use of test pattern.
11078 10:06:55.278895 Ending test lava.0_timesync-off (12073332_1.6.2.3.1), duration 0.05
11080 10:06:55.328150 + export TESTRUN_ID=1_kselftest-rtc
11081 10:06:55.331536 + TESTRUN_ID=1_kselftest-rtc
11082 10:06:55.334729 + cd /lava-12073332/0/tests/1_kselftest-rtc
11083 10:06:55.338552 ++ cat uuid
11084 10:06:55.338662 + UUID=12073332_1.6.2.3.5
11085 10:06:55.341755 + set +x
11086 10:06:55.345131 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12073332_1.6.2.3.5>
11087 10:06:55.345416 Received signal: <STARTRUN> 1_kselftest-rtc 12073332_1.6.2.3.5
11088 10:06:55.345518 Starting test lava.1_kselftest-rtc (12073332_1.6.2.3.5)
11089 10:06:55.345661 Skipping test definition patterns.
11090 10:06:55.348107 + cd ./automated/linux/kselftest/
11091 10:06:55.374740 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11092 10:06:55.395735 INFO: install_deps skipped
11093 10:06:55.499106 --2023-11-24 10:04:43-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11094 10:06:55.512299 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11095 10:06:55.648774 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11096 10:06:55.790757 HTTP request sent, awaiting response... 200 OK
11097 10:06:55.794046 Length: 2964448 (2.8M) [application/octet-stream]
11098 10:06:55.797626 Saving to: 'kselftest.tar.xz'
11099 10:06:55.797715
11100 10:06:55.797802
11101 10:06:56.065664 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11102 10:06:56.341459 kselftest.tar.xz 1%[ ] 49.22K 180KB/s
11103 10:06:56.616559 kselftest.tar.xz 7%[> ] 217.50K 396KB/s
11104 10:06:56.821573 kselftest.tar.xz 25%[====> ] 735.04K 892KB/s
11105 10:06:57.026658 kselftest.tar.xz 34%[=====> ] 985.33K 957KB/s
11106 10:06:57.231150 kselftest.tar.xz 49%[========> ] 1.41M 1.14MB/s
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11113 10:06:58.281281 2023-11-24 10:04:46 (1.27 MB/s) - 'kselftest.tar.xz' saved [2964448/2964448]
11114 10:06:58.281448
11115 10:07:03.382826 skiplist:
11116 10:07:03.386127 ========================================
11117 10:07:03.389259 ========================================
11118 10:07:03.434551 rtc:rtctest
11119 10:07:03.452444 ============== Tests to run ===============
11120 10:07:03.452987 rtc:rtctest
11121 10:07:03.455682 ===========End Tests to run ===============
11122 10:07:03.459460 shardfile-rtc pass
11123 10:07:03.559185 <12>[ 37.377578] kselftest: Running tests in rtc
11124 10:07:03.570944 TAP version 13
11125 10:07:03.582809 1..1
11126 10:07:03.616167 # selftests: rtc: rtctest
11127 10:07:04.043433 # TAP version 13
11128 10:07:04.043567 # 1..8
11129 10:07:04.046406 # # Starting 8 tests from 2 test cases.
11130 10:07:04.049360 # # RUN rtc.date_read ...
11131 10:07:04.055838 # # rtctest.c:49:date_read:Current RTC date/time is 24/11/2023 10:04:51.
11132 10:07:04.059225 # # OK rtc.date_read
11133 10:07:04.062624 # ok 1 rtc.date_read
11134 10:07:04.065819 # # RUN rtc.date_read_loop ...
11135 10:07:04.075709 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11136 10:07:12.334504 <6>[ 46.156918] vpu: disabling
11137 10:07:12.338484 <6>[ 46.160021] vproc2: disabling
11138 10:07:12.341235 <6>[ 46.163349] vproc1: disabling
11139 10:07:12.344559 <6>[ 46.166662] vaud18: disabling
11140 10:07:12.351458 <6>[ 46.170166] vsram_others: disabling
11141 10:07:12.354775 <6>[ 46.174222] va09: disabling
11142 10:07:12.357889 <6>[ 46.177391] vsram_md: disabling
11143 10:07:12.361315 <6>[ 46.180955] Vgpu: disabling
11144 10:07:34.002308 # # rtctest.c:115:date_read_loop:Performed 2640 RTC time reads.
11145 10:07:34.005514 # # OK rtc.date_read_loop
11146 10:07:34.008748 # ok 2 rtc.date_read_loop
11147 10:07:34.012430 # # RUN rtc.uie_read ...
11148 10:07:36.982628 # # OK rtc.uie_read
11149 10:07:36.985980 # ok 3 rtc.uie_read
11150 10:07:36.988781 # # RUN rtc.uie_select ...
11151 10:07:39.981548 # # OK rtc.uie_select
11152 10:07:39.985200 # ok 4 rtc.uie_select
11153 10:07:39.988316 # # RUN rtc.alarm_alm_set ...
11154 10:07:39.994718 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 10:05:31.
11155 10:07:39.998384 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11156 10:07:40.004264 # # alarm_alm_set: Test terminated by assertion
11157 10:07:40.007936 # # FAIL rtc.alarm_alm_set
11158 10:07:40.008117 # not ok 5 rtc.alarm_alm_set
11159 10:07:40.014299 # # RUN rtc.alarm_wkalm_set ...
11160 10:07:40.020916 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 24/11/2023 10:05:31.
11161 10:07:42.984332 # # OK rtc.alarm_wkalm_set
11162 10:07:42.984484 # ok 6 rtc.alarm_wkalm_set
11163 10:07:42.990864 # # RUN rtc.alarm_alm_set_minute ...
11164 10:07:42.994393 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 10:06:00.
11165 10:07:43.001240 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11166 10:07:43.007413 # # alarm_alm_set_minute: Test terminated by assertion
11167 10:07:43.010660 # # FAIL rtc.alarm_alm_set_minute
11168 10:07:43.013730 # not ok 7 rtc.alarm_alm_set_minute
11169 10:07:43.017485 # # RUN rtc.alarm_wkalm_set_minute ...
11170 10:07:43.023701 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 24/11/2023 10:06:00.
11171 10:08:11.981300 # # OK rtc.alarm_wkalm_set_minute
11172 10:08:11.984544 # ok 8 rtc.alarm_wkalm_set_minute
11173 10:08:11.988491 # # FAILED: 6 / 8 tests passed.
11174 10:08:11.991309 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11175 10:08:11.994467 not ok 1 selftests: rtc: rtctest # exit=1
11176 10:08:12.619330 rtc_rtctest_rtc_date_read pass
11177 10:08:12.622281 rtc_rtctest_rtc_date_read_loop pass
11178 10:08:12.625419 rtc_rtctest_rtc_uie_read pass
11179 10:08:12.629260 rtc_rtctest_rtc_uie_select pass
11180 10:08:12.632483 rtc_rtctest_rtc_alarm_alm_set fail
11181 10:08:12.635773 rtc_rtctest_rtc_alarm_wkalm_set pass
11182 10:08:12.638731 rtc_rtctest_rtc_alarm_alm_set_minute fail
11183 10:08:12.642318 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11184 10:08:12.645835 rtc_rtctest fail
11185 10:08:12.648915 + ../../utils/send-to-lava.sh ./output/result.txt
11186 10:08:12.711148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11187 10:08:12.711437 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11189 10:08:12.754234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11190 10:08:12.754958 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11192 10:08:12.797960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11193 10:08:12.798226 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11195 10:08:12.834397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11196 10:08:12.834673 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11198 10:08:12.872141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11199 10:08:12.872402 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11201 10:08:12.916544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11202 10:08:12.916838 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11204 10:08:12.953214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11205 10:08:12.953491 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11207 10:08:12.986421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11208 10:08:12.986683 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11210 10:08:13.024024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11211 10:08:13.024288 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11213 10:08:13.061693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11214 10:08:13.061795 + set +x
11215 10:08:13.062041 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11217 10:08:13.068956 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12073332_1.6.2.3.5>
11218 10:08:13.069226 Received signal: <ENDRUN> 1_kselftest-rtc 12073332_1.6.2.3.5
11219 10:08:13.069312 Ending use of test pattern.
11220 10:08:13.069385 Ending test lava.1_kselftest-rtc (12073332_1.6.2.3.5), duration 77.72
11222 10:08:13.069675 ok: lava_test_shell seems to have completed
11223 10:08:13.069841 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11224 10:08:13.069955 end: 3.1 lava-test-shell (duration 00:01:19) [common]
11225 10:08:13.070059 end: 3 lava-test-retry (duration 00:01:19) [common]
11226 10:08:13.070163 start: 4 finalize (timeout 00:06:05) [common]
11227 10:08:13.070276 start: 4.1 power-off (timeout 00:00:30) [common]
11228 10:08:13.070464 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11229 10:08:13.149870 >> Command sent successfully.
11230 10:08:13.153799 Returned 0 in 0 seconds
11231 10:08:13.254577 end: 4.1 power-off (duration 00:00:00) [common]
11233 10:08:13.255983 start: 4.2 read-feedback (timeout 00:06:05) [common]
11235 10:08:13.257983 Listened to connection for namespace 'common' for up to 1s
11236 10:08:14.257873 Finalising connection for namespace 'common'
11237 10:08:14.258512 Disconnecting from shell: Finalise
11238 10:08:14.258896 / #
11239 10:08:14.359859 end: 4.2 read-feedback (duration 00:00:01) [common]
11240 10:08:14.360500 end: 4 finalize (duration 00:00:01) [common]
11241 10:08:14.361033 Cleaning after the job
11242 10:08:14.361514 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/ramdisk
11243 10:08:14.374079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/kernel
11244 10:08:14.408937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/dtb
11245 10:08:14.409259 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/nfsrootfs
11246 10:08:14.501395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073332/tftp-deploy-iubfbl6v/modules
11247 10:08:14.508603 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073332
11248 10:08:15.155397 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073332
11249 10:08:15.155584 Job finished correctly