Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 135
- Kernel Warnings: 23
- Boot result: PASS
- Errors: 0
1 09:56:19.476113 lava-dispatcher, installed at version: 2023.10
2 09:56:19.476320 start: 0 validate
3 09:56:19.476459 Start time: 2023-11-24 09:56:19.476451+00:00 (UTC)
4 09:56:19.476580 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:56:19.476713 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:56:19.751920 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:56:19.752692 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:57:02.264631 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:57:02.265645 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:57:02.536606 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:57:02.537345 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:57:05.810603 validate duration: 46.33
14 09:57:05.810878 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:57:05.810977 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:57:05.811063 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:57:05.811194 Not decompressing ramdisk as can be used compressed.
18 09:57:05.811279 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 09:57:05.811343 saving as /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/ramdisk/rootfs.cpio.gz
20 09:57:05.811407 total size: 84918747 (80 MB)
21 09:57:06.078888 progress 0 % (0 MB)
22 09:57:06.101188 progress 5 % (4 MB)
23 09:57:06.124003 progress 10 % (8 MB)
24 09:57:06.147330 progress 15 % (12 MB)
25 09:57:06.170495 progress 20 % (16 MB)
26 09:57:06.192919 progress 25 % (20 MB)
27 09:57:06.215325 progress 30 % (24 MB)
28 09:57:06.239416 progress 35 % (28 MB)
29 09:57:06.263377 progress 40 % (32 MB)
30 09:57:06.286861 progress 45 % (36 MB)
31 09:57:06.309616 progress 50 % (40 MB)
32 09:57:06.332548 progress 55 % (44 MB)
33 09:57:06.356550 progress 60 % (48 MB)
34 09:57:06.380614 progress 65 % (52 MB)
35 09:57:06.405118 progress 70 % (56 MB)
36 09:57:06.428703 progress 75 % (60 MB)
37 09:57:06.452038 progress 80 % (64 MB)
38 09:57:06.474657 progress 85 % (68 MB)
39 09:57:06.497149 progress 90 % (72 MB)
40 09:57:06.519555 progress 95 % (76 MB)
41 09:57:06.541767 progress 100 % (80 MB)
42 09:57:06.542019 80 MB downloaded in 0.73 s (110.85 MB/s)
43 09:57:06.542188 end: 1.1.1 http-download (duration 00:00:01) [common]
45 09:57:06.542457 end: 1.1 download-retry (duration 00:00:01) [common]
46 09:57:06.542549 start: 1.2 download-retry (timeout 00:09:59) [common]
47 09:57:06.542637 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 09:57:06.542783 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:57:06.542857 saving as /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/kernel/Image
50 09:57:06.542921 total size: 49107456 (46 MB)
51 09:57:06.542984 No compression specified
52 09:57:06.544141 progress 0 % (0 MB)
53 09:57:06.556946 progress 5 % (2 MB)
54 09:57:06.569954 progress 10 % (4 MB)
55 09:57:06.583070 progress 15 % (7 MB)
56 09:57:06.596739 progress 20 % (9 MB)
57 09:57:06.610364 progress 25 % (11 MB)
58 09:57:06.624049 progress 30 % (14 MB)
59 09:57:06.637811 progress 35 % (16 MB)
60 09:57:06.651022 progress 40 % (18 MB)
61 09:57:06.664023 progress 45 % (21 MB)
62 09:57:06.676986 progress 50 % (23 MB)
63 09:57:06.690046 progress 55 % (25 MB)
64 09:57:06.703138 progress 60 % (28 MB)
65 09:57:06.716270 progress 65 % (30 MB)
66 09:57:06.729792 progress 70 % (32 MB)
67 09:57:06.742968 progress 75 % (35 MB)
68 09:57:06.756245 progress 80 % (37 MB)
69 09:57:06.769549 progress 85 % (39 MB)
70 09:57:06.782526 progress 90 % (42 MB)
71 09:57:06.795413 progress 95 % (44 MB)
72 09:57:06.808197 progress 100 % (46 MB)
73 09:57:06.808460 46 MB downloaded in 0.27 s (176.37 MB/s)
74 09:57:06.808625 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:57:06.808862 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:57:06.808956 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:57:06.809046 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:57:06.809193 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:57:06.809267 saving as /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/dtb/mt8192-asurada-spherion-r0.dtb
81 09:57:06.809331 total size: 47278 (0 MB)
82 09:57:06.809397 No compression specified
83 09:57:06.810881 progress 69 % (0 MB)
84 09:57:06.811170 progress 100 % (0 MB)
85 09:57:06.811330 0 MB downloaded in 0.00 s (22.59 MB/s)
86 09:57:06.811455 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:57:06.811685 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:57:06.811841 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:57:06.811953 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:57:06.812079 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:57:06.812151 saving as /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/modules/modules.tar
93 09:57:06.812215 total size: 8622040 (8 MB)
94 09:57:06.812279 Using unxz to decompress xz
95 09:57:06.816739 progress 0 % (0 MB)
96 09:57:06.838471 progress 5 % (0 MB)
97 09:57:06.862497 progress 10 % (0 MB)
98 09:57:06.887131 progress 15 % (1 MB)
99 09:57:06.911225 progress 20 % (1 MB)
100 09:57:06.935972 progress 25 % (2 MB)
101 09:57:06.962260 progress 30 % (2 MB)
102 09:57:06.989072 progress 35 % (2 MB)
103 09:57:07.012826 progress 40 % (3 MB)
104 09:57:07.037576 progress 45 % (3 MB)
105 09:57:07.063360 progress 50 % (4 MB)
106 09:57:07.088122 progress 55 % (4 MB)
107 09:57:07.113554 progress 60 % (4 MB)
108 09:57:07.141757 progress 65 % (5 MB)
109 09:57:07.167194 progress 70 % (5 MB)
110 09:57:07.191061 progress 75 % (6 MB)
111 09:57:07.218764 progress 80 % (6 MB)
112 09:57:07.245170 progress 85 % (7 MB)
113 09:57:07.270614 progress 90 % (7 MB)
114 09:57:07.301310 progress 95 % (7 MB)
115 09:57:07.332596 progress 100 % (8 MB)
116 09:57:07.337550 8 MB downloaded in 0.53 s (15.65 MB/s)
117 09:57:07.337836 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:57:07.338100 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:57:07.338194 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 09:57:07.338332 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 09:57:07.338416 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:57:07.338503 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 09:57:07.338721 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3
125 09:57:07.338856 makedir: /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin
126 09:57:07.338963 makedir: /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/tests
127 09:57:07.339062 makedir: /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/results
128 09:57:07.339177 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-add-keys
129 09:57:07.339321 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-add-sources
130 09:57:07.339453 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-background-process-start
131 09:57:07.339582 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-background-process-stop
132 09:57:07.339707 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-common-functions
133 09:57:07.339833 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-echo-ipv4
134 09:57:07.339957 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-install-packages
135 09:57:07.340081 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-installed-packages
136 09:57:07.340204 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-os-build
137 09:57:07.340328 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-probe-channel
138 09:57:07.340454 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-probe-ip
139 09:57:07.340580 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-target-ip
140 09:57:07.340702 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-target-mac
141 09:57:07.340826 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-target-storage
142 09:57:07.341026 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-case
143 09:57:07.341150 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-event
144 09:57:07.341275 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-feedback
145 09:57:07.341399 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-raise
146 09:57:07.341525 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-reference
147 09:57:07.341649 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-runner
148 09:57:07.341774 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-set
149 09:57:07.341899 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-test-shell
150 09:57:07.342028 Updating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-install-packages (oe)
151 09:57:07.342187 Updating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/bin/lava-installed-packages (oe)
152 09:57:07.342352 Creating /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/environment
153 09:57:07.342457 LAVA metadata
154 09:57:07.342530 - LAVA_JOB_ID=12073287
155 09:57:07.342595 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:57:07.342700 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 09:57:07.342767 skipped lava-vland-overlay
158 09:57:07.342840 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:57:07.342965 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 09:57:07.343062 skipped lava-multinode-overlay
161 09:57:07.343137 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:57:07.343218 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 09:57:07.343291 Loading test definitions
164 09:57:07.343381 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 09:57:07.343459 Using /lava-12073287 at stage 0
166 09:57:07.343556 Fetching tests from https://github.com/kernelci/kernelci-core
167 09:57:07.343637 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/0/tests/0_sleep'
168 09:57:08.381896 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/0/tests/0_sleep
169 09:57:08.383333 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 09:57:08.383764 uuid=12073287_1.5.2.3.1 testdef=None
171 09:57:08.383912 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 09:57:08.384171 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
174 09:57:08.384753 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 09:57:08.385013 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
177 09:57:08.385808 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 09:57:08.386190 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
180 09:57:08.387017 runner path: /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/0/tests/0_sleep test_uuid 12073287_1.5.2.3.1
181 09:57:08.387103 sleep_params='mem freeze'
182 09:57:08.387256 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 09:57:08.387468 Creating lava-test-runner.conf files
185 09:57:08.387533 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073287/lava-overlay-sa0iirf3/lava-12073287/0 for stage 0
186 09:57:08.387634 - 0_sleep
187 09:57:08.387740 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 09:57:08.387831 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
189 09:57:08.519422 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 09:57:08.519582 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 09:57:08.519677 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 09:57:08.519780 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 09:57:08.519875 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 09:57:11.043277 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 09:57:11.043695 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 09:57:11.043817 extracting modules file /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073287/extract-overlay-ramdisk-oghkgq7w/ramdisk
197 09:57:11.289338 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 09:57:11.289510 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 09:57:11.289645 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073287/compress-overlay-mmsqg4qg/overlay-1.5.2.4.tar.gz to ramdisk
200 09:57:11.289721 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073287/compress-overlay-mmsqg4qg/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073287/extract-overlay-ramdisk-oghkgq7w/ramdisk
201 09:57:11.388683 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 09:57:11.388849 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 09:57:11.388976 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 09:57:11.389080 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 09:57:11.389161 Building ramdisk /var/lib/lava/dispatcher/tmp/12073287/extract-overlay-ramdisk-oghkgq7w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073287/extract-overlay-ramdisk-oghkgq7w/ramdisk
206 09:57:12.982318 >> 563549 blocks
207 09:57:22.856244 rename /var/lib/lava/dispatcher/tmp/12073287/extract-overlay-ramdisk-oghkgq7w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/ramdisk/ramdisk.cpio.gz
208 09:57:22.856728 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 09:57:22.856905 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 09:57:22.857054 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 09:57:22.857221 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/kernel/Image'
212 09:57:35.365156 Returned 0 in 12 seconds
213 09:57:35.465793 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/kernel/image.itb
214 09:57:36.807993 output: FIT description: Kernel Image image with one or more FDT blobs
215 09:57:36.808371 output: Created: Fri Nov 24 09:57:36 2023
216 09:57:36.808450 output: Image 0 (kernel-1)
217 09:57:36.808521 output: Description:
218 09:57:36.808585 output: Created: Fri Nov 24 09:57:36 2023
219 09:57:36.808650 output: Type: Kernel Image
220 09:57:36.808710 output: Compression: lzma compressed
221 09:57:36.808766 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
222 09:57:36.808823 output: Architecture: AArch64
223 09:57:36.808878 output: OS: Linux
224 09:57:36.808937 output: Load Address: 0x00000000
225 09:57:36.808992 output: Entry Point: 0x00000000
226 09:57:36.809048 output: Hash algo: crc32
227 09:57:36.809108 output: Hash value: 2edffaa3
228 09:57:36.809169 output: Image 1 (fdt-1)
229 09:57:36.809227 output: Description: mt8192-asurada-spherion-r0
230 09:57:36.809281 output: Created: Fri Nov 24 09:57:36 2023
231 09:57:36.809335 output: Type: Flat Device Tree
232 09:57:36.809389 output: Compression: uncompressed
233 09:57:36.809442 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 09:57:36.809495 output: Architecture: AArch64
235 09:57:36.809548 output: Hash algo: crc32
236 09:57:36.809601 output: Hash value: cc4352de
237 09:57:36.809654 output: Image 2 (ramdisk-1)
238 09:57:36.809707 output: Description: unavailable
239 09:57:36.809759 output: Created: Fri Nov 24 09:57:36 2023
240 09:57:36.809813 output: Type: RAMDisk Image
241 09:57:36.809866 output: Compression: Unknown Compression
242 09:57:36.809919 output: Data Size: 98323028 Bytes = 96018.58 KiB = 93.77 MiB
243 09:57:36.809972 output: Architecture: AArch64
244 09:57:36.810026 output: OS: Linux
245 09:57:36.810079 output: Load Address: unavailable
246 09:57:36.810132 output: Entry Point: unavailable
247 09:57:36.810185 output: Hash algo: crc32
248 09:57:36.810238 output: Hash value: 09c60d45
249 09:57:36.810338 output: Default Configuration: 'conf-1'
250 09:57:36.810392 output: Configuration 0 (conf-1)
251 09:57:36.810446 output: Description: mt8192-asurada-spherion-r0
252 09:57:36.810500 output: Kernel: kernel-1
253 09:57:36.810553 output: Init Ramdisk: ramdisk-1
254 09:57:36.810606 output: FDT: fdt-1
255 09:57:36.810660 output: Loadables: kernel-1
256 09:57:36.810713 output:
257 09:57:36.810922 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 09:57:36.811021 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 09:57:36.811125 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 09:57:36.811223 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 09:57:36.811299 No LXC device requested
262 09:57:36.811379 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 09:57:36.811463 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 09:57:36.811542 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 09:57:36.811614 Checking files for TFTP limit of 4294967296 bytes.
266 09:57:36.812124 end: 1 tftp-deploy (duration 00:00:31) [common]
267 09:57:36.812235 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 09:57:36.812329 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 09:57:36.812456 substitutions:
270 09:57:36.812525 - {DTB}: 12073287/tftp-deploy-c1unlv2r/dtb/mt8192-asurada-spherion-r0.dtb
271 09:57:36.812591 - {INITRD}: 12073287/tftp-deploy-c1unlv2r/ramdisk/ramdisk.cpio.gz
272 09:57:36.812651 - {KERNEL}: 12073287/tftp-deploy-c1unlv2r/kernel/Image
273 09:57:36.812710 - {LAVA_MAC}: None
274 09:57:36.812767 - {PRESEED_CONFIG}: None
275 09:57:36.812823 - {PRESEED_LOCAL}: None
276 09:57:36.812878 - {RAMDISK}: 12073287/tftp-deploy-c1unlv2r/ramdisk/ramdisk.cpio.gz
277 09:57:36.812934 - {ROOT_PART}: None
278 09:57:36.812988 - {ROOT}: None
279 09:57:36.813043 - {SERVER_IP}: 192.168.201.1
280 09:57:36.813098 - {TEE}: None
281 09:57:36.813153 Parsed boot commands:
282 09:57:36.813207 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 09:57:36.813377 Parsed boot commands: tftpboot 192.168.201.1 12073287/tftp-deploy-c1unlv2r/kernel/image.itb 12073287/tftp-deploy-c1unlv2r/kernel/cmdline
284 09:57:36.813470 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 09:57:36.813556 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 09:57:36.813652 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 09:57:36.813737 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 09:57:36.813809 Not connected, no need to disconnect.
289 09:57:36.813885 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 09:57:36.813965 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 09:57:36.814032 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
292 09:57:36.818068 Setting prompt string to ['lava-test: # ']
293 09:57:36.818487 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 09:57:36.818600 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 09:57:36.818703 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 09:57:36.818819 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 09:57:36.819076 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
298 09:57:41.954379 >> Command sent successfully.
299 09:57:41.956756 Returned 0 in 5 seconds
300 09:57:42.057198 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 09:57:42.057619 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 09:57:42.057725 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 09:57:42.057813 Setting prompt string to 'Starting depthcharge on Spherion...'
305 09:57:42.057883 Changing prompt to 'Starting depthcharge on Spherion...'
306 09:57:42.057955 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 09:57:42.058224 [Enter `^Ec?' for help]
308 09:57:42.230676
309 09:57:42.230852
310 09:57:42.230933 F0: 102B 0000
311 09:57:42.231005
312 09:57:42.231071 F3: 1001 0000 [0200]
313 09:57:42.231132
314 09:57:42.234200 F3: 1001 0000
315 09:57:42.234334
316 09:57:42.234402 F7: 102D 0000
317 09:57:42.234465
318 09:57:42.234525 F1: 0000 0000
319 09:57:42.237733
320 09:57:42.237838 V0: 0000 0000 [0001]
321 09:57:42.237913
322 09:57:42.237975 00: 0007 8000
323 09:57:42.238040
324 09:57:42.241209 01: 0000 0000
325 09:57:42.241343
326 09:57:42.241412 BP: 0C00 0209 [0000]
327 09:57:42.241475
328 09:57:42.244627 G0: 1182 0000
329 09:57:42.244730
330 09:57:42.244804 EC: 0000 0021 [4000]
331 09:57:42.244868
332 09:57:42.248582 S7: 0000 0000 [0000]
333 09:57:42.248696
334 09:57:42.248812 CC: 0000 0000 [0001]
335 09:57:42.248890
336 09:57:42.251911 T0: 0000 0040 [010F]
337 09:57:42.252035
338 09:57:42.252143 Jump to BL
339 09:57:42.252206
340 09:57:42.277430
341 09:57:42.277592
342 09:57:42.277664
343 09:57:42.285159 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 09:57:42.288313 ARM64: Exception handlers installed.
345 09:57:42.292403 ARM64: Testing exception
346 09:57:42.295673 ARM64: Done test exception
347 09:57:42.303124 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 09:57:42.309988 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 09:57:42.317320 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 09:57:42.327966 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 09:57:42.334432 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 09:57:42.345018 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 09:57:42.355266 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 09:57:42.362114 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 09:57:42.380367 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 09:57:42.383593 WDT: Last reset was cold boot
357 09:57:42.387345 SPI1(PAD0) initialized at 2873684 Hz
358 09:57:42.390301 SPI5(PAD0) initialized at 992727 Hz
359 09:57:42.393289 VBOOT: Loading verstage.
360 09:57:42.400512 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 09:57:42.403362 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 09:57:42.407166 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 09:57:42.410490 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 09:57:42.418061 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 09:57:42.424273 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 09:57:42.435210 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 09:57:42.435368
368 09:57:42.435444
369 09:57:42.444799 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 09:57:42.448339 ARM64: Exception handlers installed.
371 09:57:42.451621 ARM64: Testing exception
372 09:57:42.454966 ARM64: Done test exception
373 09:57:42.458605 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 09:57:42.461840 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 09:57:42.476306 Probing TPM: . done!
376 09:57:42.476475 TPM ready after 0 ms
377 09:57:42.483458 Connected to device vid:did:rid of 1ae0:0028:00
378 09:57:42.490206 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 09:57:42.493223 Initialized TPM device CR50 revision 0
380 09:57:42.559152 tlcl_send_startup: Startup return code is 0
381 09:57:42.559317 TPM: setup succeeded
382 09:57:42.570510 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 09:57:42.579228 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 09:57:42.590905 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 09:57:42.600541 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 09:57:42.604350 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 09:57:42.611952 in-header: 03 07 00 00 08 00 00 00
388 09:57:42.615810 in-data: aa e4 47 04 13 02 00 00
389 09:57:42.619381 Chrome EC: UHEPI supported
390 09:57:42.626302 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 09:57:42.630329 in-header: 03 95 00 00 08 00 00 00
392 09:57:42.633852 in-data: 18 20 20 08 00 00 00 00
393 09:57:42.634015 Phase 1
394 09:57:42.637163 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 09:57:42.644619 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 09:57:42.648858 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 09:57:42.652115 Recovery requested (1009000e)
398 09:57:42.660399 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 09:57:42.666014 tlcl_extend: response is 0
400 09:57:42.675274 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 09:57:42.680541 tlcl_extend: response is 0
402 09:57:42.687693 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 09:57:42.707752 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 09:57:42.714500 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 09:57:42.714651
406 09:57:42.714724
407 09:57:42.723975 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 09:57:42.727396 ARM64: Exception handlers installed.
409 09:57:42.731403 ARM64: Testing exception
410 09:57:42.731532 ARM64: Done test exception
411 09:57:42.752714 pmic_efuse_setting: Set efuses in 11 msecs
412 09:57:42.756420 pmwrap_interface_init: Select PMIF_VLD_RDY
413 09:57:42.763045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 09:57:42.765839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 09:57:42.773387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 09:57:42.777229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 09:57:42.780738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 09:57:42.787890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 09:57:42.791113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 09:57:42.794977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 09:57:42.799023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 09:57:42.806447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 09:57:42.809830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 09:57:42.813941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 09:57:42.817288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 09:57:42.825356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 09:57:42.832471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 09:57:42.836086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 09:57:42.843882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 09:57:42.846815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 09:57:42.854489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 09:57:42.857816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 09:57:42.865760 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 09:57:42.869774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 09:57:42.876533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 09:57:42.880130 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 09:57:42.887131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 09:57:42.892190 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 09:57:42.898556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 09:57:42.902879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 09:57:42.905582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 09:57:42.912900 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 09:57:42.916820 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 09:57:42.920855 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 09:57:42.927825 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 09:57:42.931765 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 09:57:42.935093 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 09:57:42.942956 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 09:57:42.946553 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 09:57:42.953522 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 09:57:42.957087 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 09:57:42.960745 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 09:57:42.964392 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 09:57:42.967970 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 09:57:42.975865 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 09:57:42.979458 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 09:57:42.983081 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 09:57:42.986357 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 09:57:42.990419 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 09:57:42.994330 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 09:57:43.000923 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 09:57:43.005027 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 09:57:43.008315 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 09:57:43.016570 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 09:57:43.023704 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 09:57:43.026783 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 09:57:43.038267 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 09:57:43.045496 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 09:57:43.049665 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 09:57:43.053247 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 09:57:43.060868 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 09:57:43.063956 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x7
473 09:57:43.071643 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 09:57:43.075118 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
475 09:57:43.079342 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 09:57:43.090666 [RTC]rtc_get_frequency_meter,154: input=15, output=852
477 09:57:43.099594 [RTC]rtc_get_frequency_meter,154: input=7, output=725
478 09:57:43.109719 [RTC]rtc_get_frequency_meter,154: input=11, output=788
479 09:57:43.119087 [RTC]rtc_get_frequency_meter,154: input=13, output=821
480 09:57:43.128139 [RTC]rtc_get_frequency_meter,154: input=12, output=805
481 09:57:43.137501 [RTC]rtc_get_frequency_meter,154: input=11, output=789
482 09:57:43.148465 [RTC]rtc_get_frequency_meter,154: input=12, output=804
483 09:57:43.152006 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
484 09:57:43.155907 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
485 09:57:43.159319 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 09:57:43.167244 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 09:57:43.171117 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 09:57:43.174207 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 09:57:43.174369 ADC[4]: Raw value=904064 ID=7
490 09:57:43.178739 ADC[3]: Raw value=213546 ID=1
491 09:57:43.181968 RAM Code: 0x71
492 09:57:43.186132 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 09:57:43.189771 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 09:57:43.196732 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 09:57:43.204145 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 09:57:43.208094 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 09:57:43.211322 in-header: 03 07 00 00 08 00 00 00
498 09:57:43.215100 in-data: aa e4 47 04 13 02 00 00
499 09:57:43.219380 Chrome EC: UHEPI supported
500 09:57:43.222512 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 09:57:43.226032 in-header: 03 95 00 00 08 00 00 00
502 09:57:43.229693 in-data: 18 20 20 08 00 00 00 00
503 09:57:43.233372 MRC: failed to locate region type 0.
504 09:57:43.241312 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 09:57:43.244767 DRAM-K: Running full calibration
506 09:57:43.252260 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 09:57:43.252414 header.status = 0x0
508 09:57:43.255701 header.version = 0x6 (expected: 0x6)
509 09:57:43.259527 header.size = 0xd00 (expected: 0xd00)
510 09:57:43.259660 header.flags = 0x0
511 09:57:43.266152 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 09:57:43.285023 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
513 09:57:43.291642 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 09:57:43.295064 dram_init: ddr_geometry: 2
515 09:57:43.295195 [EMI] MDL number = 2
516 09:57:43.298821 [EMI] Get MDL freq = 0
517 09:57:43.298941 dram_init: ddr_type: 0
518 09:57:43.302050 is_discrete_lpddr4: 1
519 09:57:43.305736 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 09:57:43.305887
521 09:57:43.305963
522 09:57:43.309265 [Bian_co] ETT version 0.0.0.1
523 09:57:43.313316 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 09:57:43.313471
525 09:57:43.317281 dramc_set_vcore_voltage set vcore to 650000
526 09:57:43.320801 Read voltage for 800, 4
527 09:57:43.320927 Vio18 = 0
528 09:57:43.321000 Vcore = 650000
529 09:57:43.324341 Vdram = 0
530 09:57:43.324441 Vddq = 0
531 09:57:43.324510 Vmddr = 0
532 09:57:43.326841 dram_init: config_dvfs: 1
533 09:57:43.330464 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 09:57:43.336899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 09:57:43.341465 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 09:57:43.344699 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 09:57:43.347854 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 09:57:43.352031 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 09:57:43.355635 MEM_TYPE=3, freq_sel=18
540 09:57:43.355794 sv_algorithm_assistance_LP4_1600
541 09:57:43.362547 ============ PULL DRAM RESETB DOWN ============
542 09:57:43.365658 ========== PULL DRAM RESETB DOWN end =========
543 09:57:43.368976 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 09:57:43.372989 ===================================
545 09:57:43.376154 LPDDR4 DRAM CONFIGURATION
546 09:57:43.379027 ===================================
547 09:57:43.382653 EX_ROW_EN[0] = 0x0
548 09:57:43.382793 EX_ROW_EN[1] = 0x0
549 09:57:43.382892 LP4Y_EN = 0x0
550 09:57:43.386200 WORK_FSP = 0x0
551 09:57:43.386334 WL = 0x2
552 09:57:43.390394 RL = 0x2
553 09:57:43.390536 BL = 0x2
554 09:57:43.393572 RPST = 0x0
555 09:57:43.393705 RD_PRE = 0x0
556 09:57:43.396646 WR_PRE = 0x1
557 09:57:43.396764 WR_PST = 0x0
558 09:57:43.400302 DBI_WR = 0x0
559 09:57:43.400426 DBI_RD = 0x0
560 09:57:43.403871 OTF = 0x1
561 09:57:43.407903 ===================================
562 09:57:43.410008 ===================================
563 09:57:43.410145 ANA top config
564 09:57:43.413145 ===================================
565 09:57:43.416822 DLL_ASYNC_EN = 0
566 09:57:43.420590 ALL_SLAVE_EN = 1
567 09:57:43.423853 NEW_RANK_MODE = 1
568 09:57:43.423993 DLL_IDLE_MODE = 1
569 09:57:43.426815 LP45_APHY_COMB_EN = 1
570 09:57:43.430780 TX_ODT_DIS = 1
571 09:57:43.433152 NEW_8X_MODE = 1
572 09:57:43.436938 ===================================
573 09:57:43.440185 ===================================
574 09:57:43.443519 data_rate = 1600
575 09:57:43.447129 CKR = 1
576 09:57:43.447276 DQ_P2S_RATIO = 8
577 09:57:43.449926 ===================================
578 09:57:43.453438 CA_P2S_RATIO = 8
579 09:57:43.457460 DQ_CA_OPEN = 0
580 09:57:43.460986 DQ_SEMI_OPEN = 0
581 09:57:43.461139 CA_SEMI_OPEN = 0
582 09:57:43.464014 CA_FULL_RATE = 0
583 09:57:43.467581 DQ_CKDIV4_EN = 1
584 09:57:43.470956 CA_CKDIV4_EN = 1
585 09:57:43.473876 CA_PREDIV_EN = 0
586 09:57:43.477616 PH8_DLY = 0
587 09:57:43.477764 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 09:57:43.480964 DQ_AAMCK_DIV = 4
589 09:57:43.484206 CA_AAMCK_DIV = 4
590 09:57:43.487243 CA_ADMCK_DIV = 4
591 09:57:43.491645 DQ_TRACK_CA_EN = 0
592 09:57:43.494060 CA_PICK = 800
593 09:57:43.494188 CA_MCKIO = 800
594 09:57:43.497429 MCKIO_SEMI = 0
595 09:57:43.501382 PLL_FREQ = 3068
596 09:57:43.504556 DQ_UI_PI_RATIO = 32
597 09:57:43.508022 CA_UI_PI_RATIO = 0
598 09:57:43.512966 ===================================
599 09:57:43.513157 ===================================
600 09:57:43.516288 memory_type:LPDDR4
601 09:57:43.519726 GP_NUM : 10
602 09:57:43.519873 SRAM_EN : 1
603 09:57:43.523526 MD32_EN : 0
604 09:57:43.527106 ===================================
605 09:57:43.527276 [ANA_INIT] >>>>>>>>>>>>>>
606 09:57:43.530883 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 09:57:43.534771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 09:57:43.538358 ===================================
609 09:57:43.541618 data_rate = 1600,PCW = 0X7600
610 09:57:43.545111 ===================================
611 09:57:43.548214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 09:57:43.551443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 09:57:43.558453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 09:57:43.561539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 09:57:43.564820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 09:57:43.568722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 09:57:43.571053 [ANA_INIT] flow start
618 09:57:43.574498 [ANA_INIT] PLL >>>>>>>>
619 09:57:43.574639 [ANA_INIT] PLL <<<<<<<<
620 09:57:43.578094 [ANA_INIT] MIDPI >>>>>>>>
621 09:57:43.580947 [ANA_INIT] MIDPI <<<<<<<<
622 09:57:43.584827 [ANA_INIT] DLL >>>>>>>>
623 09:57:43.584980 [ANA_INIT] flow end
624 09:57:43.587950 ============ LP4 DIFF to SE enter ============
625 09:57:43.594986 ============ LP4 DIFF to SE exit ============
626 09:57:43.595135 [ANA_INIT] <<<<<<<<<<<<<
627 09:57:43.597887 [Flow] Enable top DCM control >>>>>
628 09:57:43.601580 [Flow] Enable top DCM control <<<<<
629 09:57:43.604562 Enable DLL master slave shuffle
630 09:57:43.611203 ==============================================================
631 09:57:43.611356 Gating Mode config
632 09:57:43.617759 ==============================================================
633 09:57:43.621328 Config description:
634 09:57:43.627972 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 09:57:43.634554 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 09:57:43.641063 SELPH_MODE 0: By rank 1: By Phase
637 09:57:43.647829 ==============================================================
638 09:57:43.647978 GAT_TRACK_EN = 1
639 09:57:43.651467 RX_GATING_MODE = 2
640 09:57:43.654636 RX_GATING_TRACK_MODE = 2
641 09:57:43.657630 SELPH_MODE = 1
642 09:57:43.660878 PICG_EARLY_EN = 1
643 09:57:43.664185 VALID_LAT_VALUE = 1
644 09:57:43.671455 ==============================================================
645 09:57:43.674760 Enter into Gating configuration >>>>
646 09:57:43.677963 Exit from Gating configuration <<<<
647 09:57:43.681074 Enter into DVFS_PRE_config >>>>>
648 09:57:43.691138 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 09:57:43.694290 Exit from DVFS_PRE_config <<<<<
650 09:57:43.697321 Enter into PICG configuration >>>>
651 09:57:43.700910 Exit from PICG configuration <<<<
652 09:57:43.703967 [RX_INPUT] configuration >>>>>
653 09:57:43.704087 [RX_INPUT] configuration <<<<<
654 09:57:43.710800 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 09:57:43.717336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 09:57:43.721153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 09:57:43.727630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 09:57:43.733963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 09:57:43.740860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 09:57:43.744926 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 09:57:43.747736 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 09:57:43.754405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 09:57:43.758035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 09:57:43.760909 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 09:57:43.767407 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 09:57:43.770903 ===================================
667 09:57:43.771027 LPDDR4 DRAM CONFIGURATION
668 09:57:43.774544 ===================================
669 09:57:43.777199 EX_ROW_EN[0] = 0x0
670 09:57:43.777308 EX_ROW_EN[1] = 0x0
671 09:57:43.781141 LP4Y_EN = 0x0
672 09:57:43.781251 WORK_FSP = 0x0
673 09:57:43.783969 WL = 0x2
674 09:57:43.788029 RL = 0x2
675 09:57:43.788152 BL = 0x2
676 09:57:43.790507 RPST = 0x0
677 09:57:43.790602 RD_PRE = 0x0
678 09:57:43.793827 WR_PRE = 0x1
679 09:57:43.793955 WR_PST = 0x0
680 09:57:43.797753 DBI_WR = 0x0
681 09:57:43.797882 DBI_RD = 0x0
682 09:57:43.800743 OTF = 0x1
683 09:57:43.803682 ===================================
684 09:57:43.807191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 09:57:43.810578 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 09:57:43.813600 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 09:57:43.817217 ===================================
688 09:57:43.820685 LPDDR4 DRAM CONFIGURATION
689 09:57:43.824065 ===================================
690 09:57:43.826854 EX_ROW_EN[0] = 0x10
691 09:57:43.826962 EX_ROW_EN[1] = 0x0
692 09:57:43.830401 LP4Y_EN = 0x0
693 09:57:43.830500 WORK_FSP = 0x0
694 09:57:43.833798 WL = 0x2
695 09:57:43.833898 RL = 0x2
696 09:57:43.837490 BL = 0x2
697 09:57:43.837590 RPST = 0x0
698 09:57:43.840462 RD_PRE = 0x0
699 09:57:43.840558 WR_PRE = 0x1
700 09:57:43.843869 WR_PST = 0x0
701 09:57:43.847185 DBI_WR = 0x0
702 09:57:43.847297 DBI_RD = 0x0
703 09:57:43.850494 OTF = 0x1
704 09:57:43.853674 ===================================
705 09:57:43.856993 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 09:57:43.862672 nWR fixed to 40
707 09:57:43.865600 [ModeRegInit_LP4] CH0 RK0
708 09:57:43.865723 [ModeRegInit_LP4] CH0 RK1
709 09:57:43.868944 [ModeRegInit_LP4] CH1 RK0
710 09:57:43.872305 [ModeRegInit_LP4] CH1 RK1
711 09:57:43.872417 match AC timing 13
712 09:57:43.878815 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 09:57:43.882165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 09:57:43.885434 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 09:57:43.892237 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 09:57:43.895256 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 09:57:43.898597 [EMI DOE] emi_dcm 0
718 09:57:43.902514 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 09:57:43.902643 ==
720 09:57:43.905631 Dram Type= 6, Freq= 0, CH_0, rank 0
721 09:57:43.908830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 09:57:43.908940 ==
723 09:57:43.915181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 09:57:43.922062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 09:57:43.930045 [CA 0] Center 37 (7~68) winsize 62
726 09:57:43.933105 [CA 1] Center 37 (6~68) winsize 63
727 09:57:43.936339 [CA 2] Center 34 (4~65) winsize 62
728 09:57:43.939703 [CA 3] Center 35 (4~66) winsize 63
729 09:57:43.942578 [CA 4] Center 33 (3~64) winsize 62
730 09:57:43.946778 [CA 5] Center 33 (3~64) winsize 62
731 09:57:43.946907
732 09:57:43.949277 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 09:57:43.949372
734 09:57:43.952843 [CATrainingPosCal] consider 1 rank data
735 09:57:43.957020 u2DelayCellTimex100 = 270/100 ps
736 09:57:43.959594 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 09:57:43.966479 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 09:57:43.969309 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 09:57:43.972481 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
740 09:57:43.975670 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 09:57:43.979047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 09:57:43.979186
743 09:57:43.982462 CA PerBit enable=1, Macro0, CA PI delay=33
744 09:57:43.982587
745 09:57:43.986659 [CBTSetCACLKResult] CA Dly = 33
746 09:57:43.989702 CS Dly: 5 (0~36)
747 09:57:43.989830 ==
748 09:57:43.992949 Dram Type= 6, Freq= 0, CH_0, rank 1
749 09:57:43.996116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 09:57:43.996247 ==
751 09:57:44.002736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 09:57:44.006150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 09:57:44.016127 [CA 0] Center 38 (7~69) winsize 63
754 09:57:44.019271 [CA 1] Center 37 (7~68) winsize 62
755 09:57:44.022694 [CA 2] Center 35 (4~66) winsize 63
756 09:57:44.025794 [CA 3] Center 35 (4~66) winsize 63
757 09:57:44.029417 [CA 4] Center 34 (3~65) winsize 63
758 09:57:44.032809 [CA 5] Center 33 (3~64) winsize 62
759 09:57:44.032950
760 09:57:44.036509 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 09:57:44.036637
762 09:57:44.039355 [CATrainingPosCal] consider 2 rank data
763 09:57:44.042702 u2DelayCellTimex100 = 270/100 ps
764 09:57:44.045803 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 09:57:44.052519 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 09:57:44.055643 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 09:57:44.059329 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
768 09:57:44.062521 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 09:57:44.065550 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 09:57:44.065698
771 09:57:44.069456 CA PerBit enable=1, Macro0, CA PI delay=33
772 09:57:44.069603
773 09:57:44.072332 [CBTSetCACLKResult] CA Dly = 33
774 09:57:44.072450 CS Dly: 6 (0~38)
775 09:57:44.076119
776 09:57:44.079538 ----->DramcWriteLeveling(PI) begin...
777 09:57:44.079674 ==
778 09:57:44.082936 Dram Type= 6, Freq= 0, CH_0, rank 0
779 09:57:44.087397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 09:57:44.087562 ==
781 09:57:44.090884 Write leveling (Byte 0): 31 => 31
782 09:57:44.091024 Write leveling (Byte 1): 30 => 30
783 09:57:44.094539 DramcWriteLeveling(PI) end<-----
784 09:57:44.094675
785 09:57:44.094774 ==
786 09:57:44.097656 Dram Type= 6, Freq= 0, CH_0, rank 0
787 09:57:44.101254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 09:57:44.101399 ==
789 09:57:44.104684 [Gating] SW mode calibration
790 09:57:44.111483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 09:57:44.118482 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 09:57:44.122637 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 09:57:44.125045 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 09:57:44.131729 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 09:57:44.135357 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:57:44.137941 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:57:44.145413 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:57:44.148093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:57:44.151594 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:57:44.158360 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:57:44.161311 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:57:44.164763 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:57:44.171543 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:57:44.174903 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:57:44.178450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:57:44.184929 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:57:44.187903 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:57:44.191439 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 09:57:44.197684 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
810 09:57:44.201156 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 09:57:44.204677 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
812 09:57:44.211514 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 09:57:44.214836 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 09:57:44.218175 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 09:57:44.224826 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 09:57:44.227904 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 09:57:44.231196 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 09:57:44.235028 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
819 09:57:44.241180 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
820 09:57:44.244703 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 09:57:44.248416 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 09:57:44.254746 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 09:57:44.258280 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 09:57:44.261229 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 09:57:44.267834 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
826 09:57:44.271627 0 10 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
827 09:57:44.274798 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
828 09:57:44.281260 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 09:57:44.284118 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 09:57:44.287507 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 09:57:44.294434 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 09:57:44.297678 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 09:57:44.301222 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
834 09:57:44.307888 0 11 8 | B1->B0 | 2828 4040 | 0 0 | (0 0) (0 0)
835 09:57:44.311300 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
836 09:57:44.314683 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 09:57:44.321105 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 09:57:44.324603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 09:57:44.327981 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 09:57:44.334424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 09:57:44.337879 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 09:57:44.341079 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 09:57:44.345696 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:57:44.351752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:57:44.354912 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:57:44.357683 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:57:44.364452 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:57:44.367615 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:57:44.371654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:57:44.377619 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:57:44.381278 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 09:57:44.384419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 09:57:44.391403 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 09:57:44.394413 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 09:57:44.397746 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 09:57:44.404326 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 09:57:44.407902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 09:57:44.410845 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 09:57:44.413986 Total UI for P1: 0, mck2ui 16
860 09:57:44.418247 best dqsien dly found for B0: ( 0, 14, 4)
861 09:57:44.424080 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 09:57:44.424255 Total UI for P1: 0, mck2ui 16
863 09:57:44.430901 best dqsien dly found for B1: ( 0, 14, 8)
864 09:57:44.434024 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
865 09:57:44.437424 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 09:57:44.437572
867 09:57:44.440677 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
868 09:57:44.444265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 09:57:44.447133 [Gating] SW calibration Done
870 09:57:44.447265 ==
871 09:57:44.450972 Dram Type= 6, Freq= 0, CH_0, rank 0
872 09:57:44.454085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 09:57:44.454217 ==
874 09:57:44.457725 RX Vref Scan: 0
875 09:57:44.457857
876 09:57:44.457955 RX Vref 0 -> 0, step: 1
877 09:57:44.458048
878 09:57:44.461138 RX Delay -130 -> 252, step: 16
879 09:57:44.464384 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 09:57:44.468275 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 09:57:44.474479 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 09:57:44.477695 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 09:57:44.481073 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 09:57:44.484496 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 09:57:44.487995 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 09:57:44.494466 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
887 09:57:44.497569 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 09:57:44.501011 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
889 09:57:44.504623 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
890 09:57:44.508000 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 09:57:44.515160 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 09:57:44.517762 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 09:57:44.520959 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 09:57:44.524527 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 09:57:44.524648 ==
896 09:57:44.527571 Dram Type= 6, Freq= 0, CH_0, rank 0
897 09:57:44.534275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 09:57:44.534431 ==
899 09:57:44.534507 DQS Delay:
900 09:57:44.537540 DQS0 = 0, DQS1 = 0
901 09:57:44.537635 DQM Delay:
902 09:57:44.537703 DQM0 = 87, DQM1 = 75
903 09:57:44.541173 DQ Delay:
904 09:57:44.544105 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 09:57:44.547730 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
906 09:57:44.551266 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
907 09:57:44.554259 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 09:57:44.554384
909 09:57:44.554456
910 09:57:44.554518 ==
911 09:57:44.557858 Dram Type= 6, Freq= 0, CH_0, rank 0
912 09:57:44.560862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 09:57:44.560973 ==
914 09:57:44.561069
915 09:57:44.561154
916 09:57:44.564353 TX Vref Scan disable
917 09:57:44.564450 == TX Byte 0 ==
918 09:57:44.570672 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
919 09:57:44.574025 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
920 09:57:44.574144 == TX Byte 1 ==
921 09:57:44.581028 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
922 09:57:44.583974 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
923 09:57:44.584089 ==
924 09:57:44.587471 Dram Type= 6, Freq= 0, CH_0, rank 0
925 09:57:44.590887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 09:57:44.591002 ==
927 09:57:44.604909 TX Vref=22, minBit 0, minWin=27, winSum=440
928 09:57:44.608409 TX Vref=24, minBit 3, minWin=27, winSum=446
929 09:57:44.611168 TX Vref=26, minBit 1, minWin=27, winSum=450
930 09:57:44.615038 TX Vref=28, minBit 7, minWin=27, winSum=456
931 09:57:44.618280 TX Vref=30, minBit 1, minWin=27, winSum=454
932 09:57:44.624710 TX Vref=32, minBit 1, minWin=27, winSum=452
933 09:57:44.628009 [TxChooseVref] Worse bit 7, Min win 27, Win sum 456, Final Vref 28
934 09:57:44.628151
935 09:57:44.631606 Final TX Range 1 Vref 28
936 09:57:44.631717
937 09:57:44.631810 ==
938 09:57:44.635157 Dram Type= 6, Freq= 0, CH_0, rank 0
939 09:57:44.638092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 09:57:44.638200 ==
941 09:57:44.641069
942 09:57:44.641165
943 09:57:44.641255 TX Vref Scan disable
944 09:57:44.644691 == TX Byte 0 ==
945 09:57:44.648040 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
946 09:57:44.651527 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
947 09:57:44.654729 == TX Byte 1 ==
948 09:57:44.659090 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
949 09:57:44.661387 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
950 09:57:44.664687
951 09:57:44.664802 [DATLAT]
952 09:57:44.664902 Freq=800, CH0 RK0
953 09:57:44.664986
954 09:57:44.667831 DATLAT Default: 0xa
955 09:57:44.667938 0, 0xFFFF, sum = 0
956 09:57:44.671277 1, 0xFFFF, sum = 0
957 09:57:44.671387 2, 0xFFFF, sum = 0
958 09:57:44.675226 3, 0xFFFF, sum = 0
959 09:57:44.675331 4, 0xFFFF, sum = 0
960 09:57:44.678536 5, 0xFFFF, sum = 0
961 09:57:44.681212 6, 0xFFFF, sum = 0
962 09:57:44.681314 7, 0xFFFF, sum = 0
963 09:57:44.685012 8, 0xFFFF, sum = 0
964 09:57:44.685119 9, 0x0, sum = 1
965 09:57:44.685211 10, 0x0, sum = 2
966 09:57:44.688231 11, 0x0, sum = 3
967 09:57:44.688331 12, 0x0, sum = 4
968 09:57:44.691144 best_step = 10
969 09:57:44.691238
970 09:57:44.691328 ==
971 09:57:44.694394 Dram Type= 6, Freq= 0, CH_0, rank 0
972 09:57:44.697786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 09:57:44.697895 ==
974 09:57:44.701233 RX Vref Scan: 1
975 09:57:44.701337
976 09:57:44.701429 Set Vref Range= 32 -> 127
977 09:57:44.704405
978 09:57:44.704499 RX Vref 32 -> 127, step: 1
979 09:57:44.704590
980 09:57:44.707939 RX Delay -111 -> 252, step: 8
981 09:57:44.708044
982 09:57:44.711151 Set Vref, RX VrefLevel [Byte0]: 32
983 09:57:44.714552 [Byte1]: 32
984 09:57:44.714679
985 09:57:44.717520 Set Vref, RX VrefLevel [Byte0]: 33
986 09:57:44.720941 [Byte1]: 33
987 09:57:44.725391
988 09:57:44.725522 Set Vref, RX VrefLevel [Byte0]: 34
989 09:57:44.728317 [Byte1]: 34
990 09:57:44.733068
991 09:57:44.733198 Set Vref, RX VrefLevel [Byte0]: 35
992 09:57:44.736638 [Byte1]: 35
993 09:57:44.740481
994 09:57:44.740605 Set Vref, RX VrefLevel [Byte0]: 36
995 09:57:44.743626 [Byte1]: 36
996 09:57:44.748713
997 09:57:44.748855 Set Vref, RX VrefLevel [Byte0]: 37
998 09:57:44.751917 [Byte1]: 37
999 09:57:44.757308
1000 09:57:44.757450 Set Vref, RX VrefLevel [Byte0]: 38
1001 09:57:44.759610 [Byte1]: 38
1002 09:57:44.763669
1003 09:57:44.763799 Set Vref, RX VrefLevel [Byte0]: 39
1004 09:57:44.766767 [Byte1]: 39
1005 09:57:44.771535
1006 09:57:44.771674 Set Vref, RX VrefLevel [Byte0]: 40
1007 09:57:44.774495 [Byte1]: 40
1008 09:57:44.779425
1009 09:57:44.779565 Set Vref, RX VrefLevel [Byte0]: 41
1010 09:57:44.782458 [Byte1]: 41
1011 09:57:44.786460
1012 09:57:44.786616 Set Vref, RX VrefLevel [Byte0]: 42
1013 09:57:44.789548 [Byte1]: 42
1014 09:57:44.793932
1015 09:57:44.794057 Set Vref, RX VrefLevel [Byte0]: 43
1016 09:57:44.797391 [Byte1]: 43
1017 09:57:44.801581
1018 09:57:44.801706 Set Vref, RX VrefLevel [Byte0]: 44
1019 09:57:44.804726 [Byte1]: 44
1020 09:57:44.809301
1021 09:57:44.809429 Set Vref, RX VrefLevel [Byte0]: 45
1022 09:57:44.812515 [Byte1]: 45
1023 09:57:44.816944
1024 09:57:44.817071 Set Vref, RX VrefLevel [Byte0]: 46
1025 09:57:44.820674 [Byte1]: 46
1026 09:57:44.825724
1027 09:57:44.825856 Set Vref, RX VrefLevel [Byte0]: 47
1028 09:57:44.827882 [Byte1]: 47
1029 09:57:44.832265
1030 09:57:44.832422 Set Vref, RX VrefLevel [Byte0]: 48
1031 09:57:44.835299 [Byte1]: 48
1032 09:57:44.840232
1033 09:57:44.840403 Set Vref, RX VrefLevel [Byte0]: 49
1034 09:57:44.843240 [Byte1]: 49
1035 09:57:44.847566
1036 09:57:44.847705 Set Vref, RX VrefLevel [Byte0]: 50
1037 09:57:44.851553 [Byte1]: 50
1038 09:57:44.855931
1039 09:57:44.856082 Set Vref, RX VrefLevel [Byte0]: 51
1040 09:57:44.858223 [Byte1]: 51
1041 09:57:44.862716
1042 09:57:44.862868 Set Vref, RX VrefLevel [Byte0]: 52
1043 09:57:44.865913 [Byte1]: 52
1044 09:57:44.870239
1045 09:57:44.870433 Set Vref, RX VrefLevel [Byte0]: 53
1046 09:57:44.873930 [Byte1]: 53
1047 09:57:44.878236
1048 09:57:44.878420 Set Vref, RX VrefLevel [Byte0]: 54
1049 09:57:44.881778 [Byte1]: 54
1050 09:57:44.886010
1051 09:57:44.886160 Set Vref, RX VrefLevel [Byte0]: 55
1052 09:57:44.888890 [Byte1]: 55
1053 09:57:44.893260
1054 09:57:44.893404 Set Vref, RX VrefLevel [Byte0]: 56
1055 09:57:44.896631 [Byte1]: 56
1056 09:57:44.901053
1057 09:57:44.901204 Set Vref, RX VrefLevel [Byte0]: 57
1058 09:57:44.904404 [Byte1]: 57
1059 09:57:44.908961
1060 09:57:44.909106 Set Vref, RX VrefLevel [Byte0]: 58
1061 09:57:44.911689 [Byte1]: 58
1062 09:57:44.916411
1063 09:57:44.916572 Set Vref, RX VrefLevel [Byte0]: 59
1064 09:57:44.919708 [Byte1]: 59
1065 09:57:44.924138
1066 09:57:44.924283 Set Vref, RX VrefLevel [Byte0]: 60
1067 09:57:44.927641 [Byte1]: 60
1068 09:57:44.931721
1069 09:57:44.931870 Set Vref, RX VrefLevel [Byte0]: 61
1070 09:57:44.934764 [Byte1]: 61
1071 09:57:44.939081
1072 09:57:44.939224 Set Vref, RX VrefLevel [Byte0]: 62
1073 09:57:44.942337 [Byte1]: 62
1074 09:57:44.946756
1075 09:57:44.946907 Set Vref, RX VrefLevel [Byte0]: 63
1076 09:57:44.950224 [Byte1]: 63
1077 09:57:44.954663
1078 09:57:44.954815 Set Vref, RX VrefLevel [Byte0]: 64
1079 09:57:44.958024 [Byte1]: 64
1080 09:57:44.962536
1081 09:57:44.962696 Set Vref, RX VrefLevel [Byte0]: 65
1082 09:57:44.965539 [Byte1]: 65
1083 09:57:44.969881
1084 09:57:44.970031 Set Vref, RX VrefLevel [Byte0]: 66
1085 09:57:44.973694 [Byte1]: 66
1086 09:57:44.977794
1087 09:57:44.977948 Set Vref, RX VrefLevel [Byte0]: 67
1088 09:57:44.980578 [Byte1]: 67
1089 09:57:44.984964
1090 09:57:44.985106 Set Vref, RX VrefLevel [Byte0]: 68
1091 09:57:44.988255 [Byte1]: 68
1092 09:57:44.992975
1093 09:57:44.993131 Set Vref, RX VrefLevel [Byte0]: 69
1094 09:57:44.996097 [Byte1]: 69
1095 09:57:45.000517
1096 09:57:45.000669 Set Vref, RX VrefLevel [Byte0]: 70
1097 09:57:45.004190 [Byte1]: 70
1098 09:57:45.007859
1099 09:57:45.007994 Set Vref, RX VrefLevel [Byte0]: 71
1100 09:57:45.011769 [Byte1]: 71
1101 09:57:45.016161
1102 09:57:45.016326 Set Vref, RX VrefLevel [Byte0]: 72
1103 09:57:45.019023 [Byte1]: 72
1104 09:57:45.023724
1105 09:57:45.023877 Set Vref, RX VrefLevel [Byte0]: 73
1106 09:57:45.026554 [Byte1]: 73
1107 09:57:45.031057
1108 09:57:45.031204 Set Vref, RX VrefLevel [Byte0]: 74
1109 09:57:45.034281 [Byte1]: 74
1110 09:57:45.038740
1111 09:57:45.038889 Set Vref, RX VrefLevel [Byte0]: 75
1112 09:57:45.042021 [Byte1]: 75
1113 09:57:45.046892
1114 09:57:45.047045 Set Vref, RX VrefLevel [Byte0]: 76
1115 09:57:45.049602 [Byte1]: 76
1116 09:57:45.053634
1117 09:57:45.053777 Final RX Vref Byte 0 = 56 to rank0
1118 09:57:45.057159 Final RX Vref Byte 1 = 59 to rank0
1119 09:57:45.060513 Final RX Vref Byte 0 = 56 to rank1
1120 09:57:45.063742 Final RX Vref Byte 1 = 59 to rank1==
1121 09:57:45.067620 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 09:57:45.073717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 09:57:45.073897 ==
1124 09:57:45.074004 DQS Delay:
1125 09:57:45.074095 DQS0 = 0, DQS1 = 0
1126 09:57:45.077075 DQM Delay:
1127 09:57:45.077189 DQM0 = 88, DQM1 = 75
1128 09:57:45.080895 DQ Delay:
1129 09:57:45.083587 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1130 09:57:45.083711 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1131 09:57:45.086973 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1132 09:57:45.093573 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1133 09:57:45.093753
1134 09:57:45.093854
1135 09:57:45.100619 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1136 09:57:45.103906 CH0 RK0: MR19=606, MR18=2D26
1137 09:57:45.110639 CH0_RK0: MR19=0x606, MR18=0x2D26, DQSOSC=398, MR23=63, INC=93, DEC=62
1138 09:57:45.110819
1139 09:57:45.113462 ----->DramcWriteLeveling(PI) begin...
1140 09:57:45.113596 ==
1141 09:57:45.117178 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 09:57:45.120182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 09:57:45.120315 ==
1144 09:57:45.123505 Write leveling (Byte 0): 31 => 31
1145 09:57:45.126832 Write leveling (Byte 1): 28 => 28
1146 09:57:45.130409 DramcWriteLeveling(PI) end<-----
1147 09:57:45.130547
1148 09:57:45.130650 ==
1149 09:57:45.133778 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 09:57:45.136964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 09:57:45.137093 ==
1152 09:57:45.140843 [Gating] SW mode calibration
1153 09:57:45.187951 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 09:57:45.188358 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 09:57:45.188852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 09:57:45.188957 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 09:57:45.189306 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:57:45.189747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:57:45.190703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:57:45.191299 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:57:45.191403 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:57:45.191689 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:57:45.218225 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:57:45.218702 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:57:45.218832 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:57:45.218928 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:57:45.219217 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:57:45.219510 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:57:45.222375 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:57:45.225497 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:57:45.228919 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:57:45.232499 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 09:57:45.235529 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1174 09:57:45.241946 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:57:45.245606 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:57:45.249492 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:57:45.255672 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:57:45.258831 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:57:45.262475 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 09:57:45.268713 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1181 09:57:45.271849 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1182 09:57:45.275115 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1183 09:57:45.281936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 09:57:45.285288 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 09:57:45.288538 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 09:57:45.295469 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 09:57:45.298786 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 09:57:45.301784 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
1189 09:57:45.305018 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
1190 09:57:45.312211 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1191 09:57:45.315200 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 09:57:45.318648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:57:45.325183 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:57:45.329040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:57:45.332681 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:57:45.336775 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1197 09:57:45.344053 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1198 09:57:45.346693 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 09:57:45.350041 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 09:57:45.353536 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 09:57:45.360483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 09:57:45.364146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 09:57:45.366927 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 09:57:45.373650 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 09:57:45.377000 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 09:57:45.380640 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 09:57:45.386824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:57:45.390821 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:57:45.393947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:57:45.400358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:57:45.403921 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:57:45.407419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:57:45.414095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:57:45.416838 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:57:45.420131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:57:45.426925 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:57:45.429908 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 09:57:45.433502 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 09:57:45.439931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:57:45.443300 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1221 09:57:45.446567 Total UI for P1: 0, mck2ui 16
1222 09:57:45.449768 best dqsien dly found for B0: ( 0, 14, 2)
1223 09:57:45.453038 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1224 09:57:45.456667 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 09:57:45.460034 Total UI for P1: 0, mck2ui 16
1226 09:57:45.463723 best dqsien dly found for B1: ( 0, 14, 6)
1227 09:57:45.466234 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1228 09:57:45.474621 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1229 09:57:45.474806
1230 09:57:45.476162 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1231 09:57:45.480168 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1232 09:57:45.483576 [Gating] SW calibration Done
1233 09:57:45.483718 ==
1234 09:57:45.486619 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 09:57:45.490132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 09:57:45.490281 ==
1237 09:57:45.490381 RX Vref Scan: 0
1238 09:57:45.490472
1239 09:57:45.493138 RX Vref 0 -> 0, step: 1
1240 09:57:45.493249
1241 09:57:45.496751 RX Delay -130 -> 252, step: 16
1242 09:57:45.500005 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1243 09:57:45.503073 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1244 09:57:45.509663 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1245 09:57:45.512976 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1246 09:57:45.516219 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1247 09:57:45.519630 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1248 09:57:45.523566 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1249 09:57:45.529470 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1250 09:57:45.532807 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1251 09:57:45.536361 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1252 09:57:45.539929 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1253 09:57:45.542943 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1254 09:57:45.549434 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1255 09:57:45.552949 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1256 09:57:45.555985 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1257 09:57:45.559216 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1258 09:57:45.559352 ==
1259 09:57:45.562937 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 09:57:45.569390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 09:57:45.569570 ==
1262 09:57:45.569674 DQS Delay:
1263 09:57:45.572991 DQS0 = 0, DQS1 = 0
1264 09:57:45.573117 DQM Delay:
1265 09:57:45.575959 DQM0 = 86, DQM1 = 77
1266 09:57:45.576070 DQ Delay:
1267 09:57:45.579242 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1268 09:57:45.582971 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1269 09:57:45.585824 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1270 09:57:45.589165 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1271 09:57:45.589304
1272 09:57:45.589400
1273 09:57:45.589489 ==
1274 09:57:45.592493 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 09:57:45.595555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 09:57:45.595676 ==
1277 09:57:45.595771
1278 09:57:45.595860
1279 09:57:45.599063 TX Vref Scan disable
1280 09:57:45.602135 == TX Byte 0 ==
1281 09:57:45.605707 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 09:57:45.609051 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 09:57:45.612142 == TX Byte 1 ==
1284 09:57:45.615381 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 09:57:45.618862 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 09:57:45.619002 ==
1287 09:57:45.621804 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 09:57:45.625279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 09:57:45.628433 ==
1290 09:57:45.640210 TX Vref=22, minBit 0, minWin=27, winSum=443
1291 09:57:45.643683 TX Vref=24, minBit 0, minWin=27, winSum=442
1292 09:57:45.646666 TX Vref=26, minBit 1, minWin=27, winSum=445
1293 09:57:45.650195 TX Vref=28, minBit 1, minWin=27, winSum=449
1294 09:57:45.653488 TX Vref=30, minBit 2, minWin=27, winSum=451
1295 09:57:45.660108 TX Vref=32, minBit 0, minWin=28, winSum=449
1296 09:57:45.663507 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 32
1297 09:57:45.663657
1298 09:57:45.666952 Final TX Range 1 Vref 32
1299 09:57:45.667089
1300 09:57:45.667185 ==
1301 09:57:45.670631 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 09:57:45.673974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 09:57:45.674112 ==
1304 09:57:45.676632
1305 09:57:45.676745
1306 09:57:45.676838 TX Vref Scan disable
1307 09:57:45.680630 == TX Byte 0 ==
1308 09:57:45.683762 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 09:57:45.690152 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 09:57:45.690335 == TX Byte 1 ==
1311 09:57:45.693636 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 09:57:45.700188 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 09:57:45.700360
1314 09:57:45.700457 [DATLAT]
1315 09:57:45.700547 Freq=800, CH0 RK1
1316 09:57:45.700636
1317 09:57:45.703701 DATLAT Default: 0xa
1318 09:57:45.703816 0, 0xFFFF, sum = 0
1319 09:57:45.706755 1, 0xFFFF, sum = 0
1320 09:57:45.706871 2, 0xFFFF, sum = 0
1321 09:57:45.710135 3, 0xFFFF, sum = 0
1322 09:57:45.713453 4, 0xFFFF, sum = 0
1323 09:57:45.713577 5, 0xFFFF, sum = 0
1324 09:57:45.716545 6, 0xFFFF, sum = 0
1325 09:57:45.716677 7, 0xFFFF, sum = 0
1326 09:57:45.719776 8, 0xFFFF, sum = 0
1327 09:57:45.719895 9, 0x0, sum = 1
1328 09:57:45.723272 10, 0x0, sum = 2
1329 09:57:45.723398 11, 0x0, sum = 3
1330 09:57:45.723493 12, 0x0, sum = 4
1331 09:57:45.726357 best_step = 10
1332 09:57:45.726470
1333 09:57:45.726564 ==
1334 09:57:45.729628 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 09:57:45.733194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 09:57:45.733323 ==
1337 09:57:45.736252 RX Vref Scan: 0
1338 09:57:45.736366
1339 09:57:45.739537 RX Vref 0 -> 0, step: 1
1340 09:57:45.739651
1341 09:57:45.739743 RX Delay -95 -> 252, step: 8
1342 09:57:45.746719 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1343 09:57:45.750082 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 09:57:45.753925 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1345 09:57:45.756759 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1346 09:57:45.760480 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 09:57:45.766885 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 09:57:45.769924 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 09:57:45.773498 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 09:57:45.776889 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1351 09:57:45.780494 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1352 09:57:45.787077 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1353 09:57:45.789669 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1354 09:57:45.793179 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1355 09:57:45.796686 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1356 09:57:45.803200 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1357 09:57:45.806164 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1358 09:57:45.806304 ==
1359 09:57:45.809491 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 09:57:45.813203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 09:57:45.813338 ==
1362 09:57:45.816793 DQS Delay:
1363 09:57:45.816929 DQS0 = 0, DQS1 = 0
1364 09:57:45.817024 DQM Delay:
1365 09:57:45.820061 DQM0 = 86, DQM1 = 77
1366 09:57:45.820179 DQ Delay:
1367 09:57:45.823520 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1368 09:57:45.826355 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 09:57:45.829801 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1370 09:57:45.832683 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1371 09:57:45.832813
1372 09:57:45.832906
1373 09:57:45.842514 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1374 09:57:45.842702 CH0 RK1: MR19=606, MR18=2D2A
1375 09:57:45.849714 CH0_RK1: MR19=0x606, MR18=0x2D2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1376 09:57:45.852876 [RxdqsGatingPostProcess] freq 800
1377 09:57:45.859494 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 09:57:45.862966 Pre-setting of DQS Precalculation
1379 09:57:45.866151 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 09:57:45.866285 ==
1381 09:57:45.869593 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 09:57:45.875963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 09:57:45.876107 ==
1384 09:57:45.879147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 09:57:45.885808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 09:57:45.895108 [CA 0] Center 37 (6~68) winsize 63
1387 09:57:45.898174 [CA 1] Center 36 (6~67) winsize 62
1388 09:57:45.902041 [CA 2] Center 34 (4~65) winsize 62
1389 09:57:45.905403 [CA 3] Center 34 (4~65) winsize 62
1390 09:57:45.908318 [CA 4] Center 34 (4~65) winsize 62
1391 09:57:45.912197 [CA 5] Center 33 (3~64) winsize 62
1392 09:57:45.912309
1393 09:57:45.915258 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 09:57:45.915365
1395 09:57:45.918706 [CATrainingPosCal] consider 1 rank data
1396 09:57:45.921734 u2DelayCellTimex100 = 270/100 ps
1397 09:57:45.925608 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1398 09:57:45.931612 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1399 09:57:45.935809 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 09:57:45.937998 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1401 09:57:45.941276 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 09:57:45.945183 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 09:57:45.945300
1404 09:57:45.948040 CA PerBit enable=1, Macro0, CA PI delay=33
1405 09:57:45.948136
1406 09:57:45.951920 [CBTSetCACLKResult] CA Dly = 33
1407 09:57:45.952024 CS Dly: 4 (0~35)
1408 09:57:45.954918 ==
1409 09:57:45.958417 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 09:57:45.961417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 09:57:45.961518 ==
1412 09:57:45.964702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 09:57:45.971133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 09:57:45.981242 [CA 0] Center 36 (6~67) winsize 62
1415 09:57:45.984293 [CA 1] Center 36 (6~67) winsize 62
1416 09:57:45.987927 [CA 2] Center 34 (4~65) winsize 62
1417 09:57:45.991078 [CA 3] Center 34 (3~65) winsize 63
1418 09:57:45.994600 [CA 4] Center 34 (4~65) winsize 62
1419 09:57:45.998531 [CA 5] Center 33 (3~64) winsize 62
1420 09:57:45.998678
1421 09:57:46.002195 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 09:57:46.002341
1423 09:57:46.005721 [CATrainingPosCal] consider 2 rank data
1424 09:57:46.009222 u2DelayCellTimex100 = 270/100 ps
1425 09:57:46.012799 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 09:57:46.016846 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1427 09:57:46.020318 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1428 09:57:46.023536 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1429 09:57:46.027426 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 09:57:46.030921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 09:57:46.031069
1432 09:57:46.034127 CA PerBit enable=1, Macro0, CA PI delay=33
1433 09:57:46.034284
1434 09:57:46.037632 [CBTSetCACLKResult] CA Dly = 33
1435 09:57:46.040793 CS Dly: 5 (0~37)
1436 09:57:46.040918
1437 09:57:46.044637 ----->DramcWriteLeveling(PI) begin...
1438 09:57:46.044795 ==
1439 09:57:46.047130 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 09:57:46.050565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 09:57:46.050690 ==
1442 09:57:46.053860 Write leveling (Byte 0): 25 => 25
1443 09:57:46.057342 Write leveling (Byte 1): 28 => 28
1444 09:57:46.060724 DramcWriteLeveling(PI) end<-----
1445 09:57:46.060895
1446 09:57:46.061035 ==
1447 09:57:46.063822 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 09:57:46.067133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 09:57:46.067261 ==
1450 09:57:46.070696 [Gating] SW mode calibration
1451 09:57:46.077394 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 09:57:46.083700 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 09:57:46.087035 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1454 09:57:46.090737 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 09:57:46.097500 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:57:46.100726 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:57:46.104135 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:57:46.110175 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 09:57:46.113970 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:57:46.116754 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:57:46.123689 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:57:46.126976 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:57:46.130077 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:57:46.137186 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:57:46.139820 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:57:46.143554 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:57:46.150037 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:57:46.153729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:57:46.156660 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 09:57:46.160131 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1471 09:57:46.166665 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1472 09:57:46.170315 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:57:46.174509 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:57:46.180129 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:57:46.183202 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:57:46.186694 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 09:57:46.193266 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:57:46.196591 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:57:46.199972 0 9 8 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
1480 09:57:46.206776 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 09:57:46.209979 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 09:57:46.213617 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 09:57:46.220280 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 09:57:46.223393 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 09:57:46.226522 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 09:57:46.233364 0 10 4 | B1->B0 | 3232 3131 | 1 1 | (0 0) (0 0)
1487 09:57:46.236639 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1488 09:57:46.239898 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:57:46.247543 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 09:57:46.250422 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:57:46.252969 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:57:46.259928 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:57:46.263389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:57:46.266536 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1495 09:57:46.270244 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1496 09:57:46.276981 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 09:57:46.279976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 09:57:46.283884 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 09:57:46.290709 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 09:57:46.293449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 09:57:46.296442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 09:57:46.303311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1503 09:57:46.306310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1504 09:57:46.309687 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:57:46.317242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:57:46.319791 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:57:46.322978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:57:46.329645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:57:46.333146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:57:46.336991 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:57:46.342845 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:57:46.346112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:57:46.349468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:57:46.356238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:57:46.359477 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:57:46.363117 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:57:46.369666 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:57:46.372853 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 09:57:46.376592 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 09:57:46.379854 Total UI for P1: 0, mck2ui 16
1521 09:57:46.383090 best dqsien dly found for B0: ( 0, 14, 4)
1522 09:57:46.386544 Total UI for P1: 0, mck2ui 16
1523 09:57:46.389701 best dqsien dly found for B1: ( 0, 14, 4)
1524 09:57:46.393353 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 09:57:46.396002 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 09:57:46.396094
1527 09:57:46.399501 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 09:57:46.405852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 09:57:46.405970 [Gating] SW calibration Done
1530 09:57:46.406043 ==
1531 09:57:46.409402 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 09:57:46.415741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 09:57:46.415872 ==
1534 09:57:46.415999 RX Vref Scan: 0
1535 09:57:46.416228
1536 09:57:46.419787 RX Vref 0 -> 0, step: 1
1537 09:57:46.419867
1538 09:57:46.422721 RX Delay -130 -> 252, step: 16
1539 09:57:46.425608 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 09:57:46.429505 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1541 09:57:46.432398 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 09:57:46.439387 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1543 09:57:46.443030 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1544 09:57:46.446070 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1545 09:57:46.449543 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 09:57:46.452343 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1547 09:57:46.459289 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1548 09:57:46.462456 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1549 09:57:46.465927 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1550 09:57:46.468797 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 09:57:46.472367 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1552 09:57:46.479274 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1553 09:57:46.482235 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1554 09:57:46.485838 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1555 09:57:46.485966 ==
1556 09:57:46.489709 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 09:57:46.492260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 09:57:46.492352 ==
1559 09:57:46.496032 DQS Delay:
1560 09:57:46.496125 DQS0 = 0, DQS1 = 0
1561 09:57:46.499782 DQM Delay:
1562 09:57:46.499878 DQM0 = 86, DQM1 = 79
1563 09:57:46.499947 DQ Delay:
1564 09:57:46.502412 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1565 09:57:46.505942 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1566 09:57:46.509270 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1567 09:57:46.512739 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1568 09:57:46.512846
1569 09:57:46.512916
1570 09:57:46.516369 ==
1571 09:57:46.519183 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 09:57:46.522171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 09:57:46.522314 ==
1574 09:57:46.522383
1575 09:57:46.522443
1576 09:57:46.525813 TX Vref Scan disable
1577 09:57:46.525909 == TX Byte 0 ==
1578 09:57:46.532640 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 09:57:46.535994 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 09:57:46.536120 == TX Byte 1 ==
1581 09:57:46.542280 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1582 09:57:46.545522 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1583 09:57:46.545612 ==
1584 09:57:46.549367 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 09:57:46.552111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 09:57:46.552219 ==
1587 09:57:46.566117 TX Vref=22, minBit 0, minWin=27, winSum=444
1588 09:57:46.569684 TX Vref=24, minBit 0, minWin=27, winSum=443
1589 09:57:46.572185 TX Vref=26, minBit 4, minWin=27, winSum=450
1590 09:57:46.577244 TX Vref=28, minBit 5, minWin=27, winSum=454
1591 09:57:46.580366 TX Vref=30, minBit 2, minWin=27, winSum=454
1592 09:57:46.583243 TX Vref=32, minBit 0, minWin=27, winSum=450
1593 09:57:46.589733 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 28
1594 09:57:46.589871
1595 09:57:46.593311 Final TX Range 1 Vref 28
1596 09:57:46.593400
1597 09:57:46.593466 ==
1598 09:57:46.597048 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 09:57:46.600357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 09:57:46.600442 ==
1601 09:57:46.600511
1602 09:57:46.600570
1603 09:57:46.603052 TX Vref Scan disable
1604 09:57:46.606220 == TX Byte 0 ==
1605 09:57:46.609829 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 09:57:46.613290 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 09:57:46.616207 == TX Byte 1 ==
1608 09:57:46.619634 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1609 09:57:46.623311 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1610 09:57:46.623415
1611 09:57:46.626223 [DATLAT]
1612 09:57:46.626351 Freq=800, CH1 RK0
1613 09:57:46.626425
1614 09:57:46.630425 DATLAT Default: 0xa
1615 09:57:46.630504 0, 0xFFFF, sum = 0
1616 09:57:46.633544 1, 0xFFFF, sum = 0
1617 09:57:46.633625 2, 0xFFFF, sum = 0
1618 09:57:46.636612 3, 0xFFFF, sum = 0
1619 09:57:46.636694 4, 0xFFFF, sum = 0
1620 09:57:46.639338 5, 0xFFFF, sum = 0
1621 09:57:46.639419 6, 0xFFFF, sum = 0
1622 09:57:46.643073 7, 0xFFFF, sum = 0
1623 09:57:46.643175 8, 0xFFFF, sum = 0
1624 09:57:46.646177 9, 0x0, sum = 1
1625 09:57:46.646307 10, 0x0, sum = 2
1626 09:57:46.649931 11, 0x0, sum = 3
1627 09:57:46.650010 12, 0x0, sum = 4
1628 09:57:46.653225 best_step = 10
1629 09:57:46.653299
1630 09:57:46.653360 ==
1631 09:57:46.656098 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 09:57:46.659197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 09:57:46.659295 ==
1634 09:57:46.663051 RX Vref Scan: 1
1635 09:57:46.663199
1636 09:57:46.663309 Set Vref Range= 32 -> 127
1637 09:57:46.663443
1638 09:57:46.666196 RX Vref 32 -> 127, step: 1
1639 09:57:46.666303
1640 09:57:46.669090 RX Delay -95 -> 252, step: 8
1641 09:57:46.669188
1642 09:57:46.672670 Set Vref, RX VrefLevel [Byte0]: 32
1643 09:57:46.675886 [Byte1]: 32
1644 09:57:46.675998
1645 09:57:46.679662 Set Vref, RX VrefLevel [Byte0]: 33
1646 09:57:46.682223 [Byte1]: 33
1647 09:57:46.686101
1648 09:57:46.686217 Set Vref, RX VrefLevel [Byte0]: 34
1649 09:57:46.690205 [Byte1]: 34
1650 09:57:46.693968
1651 09:57:46.694088 Set Vref, RX VrefLevel [Byte0]: 35
1652 09:57:46.697607 [Byte1]: 35
1653 09:57:46.701107
1654 09:57:46.701223 Set Vref, RX VrefLevel [Byte0]: 36
1655 09:57:46.704926 [Byte1]: 36
1656 09:57:46.708695
1657 09:57:46.708795 Set Vref, RX VrefLevel [Byte0]: 37
1658 09:57:46.712161 [Byte1]: 37
1659 09:57:46.716515
1660 09:57:46.716683 Set Vref, RX VrefLevel [Byte0]: 38
1661 09:57:46.720302 [Byte1]: 38
1662 09:57:46.724455
1663 09:57:46.724582 Set Vref, RX VrefLevel [Byte0]: 39
1664 09:57:46.727356 [Byte1]: 39
1665 09:57:46.731741
1666 09:57:46.731935 Set Vref, RX VrefLevel [Byte0]: 40
1667 09:57:46.735077 [Byte1]: 40
1668 09:57:46.739337
1669 09:57:46.739515 Set Vref, RX VrefLevel [Byte0]: 41
1670 09:57:46.742505 [Byte1]: 41
1671 09:57:46.746840
1672 09:57:46.746942 Set Vref, RX VrefLevel [Byte0]: 42
1673 09:57:46.750401 [Byte1]: 42
1674 09:57:46.754785
1675 09:57:46.754885 Set Vref, RX VrefLevel [Byte0]: 43
1676 09:57:46.757888 [Byte1]: 43
1677 09:57:46.762003
1678 09:57:46.762134 Set Vref, RX VrefLevel [Byte0]: 44
1679 09:57:46.765658 [Byte1]: 44
1680 09:57:46.769639
1681 09:57:46.769795 Set Vref, RX VrefLevel [Byte0]: 45
1682 09:57:46.773263 [Byte1]: 45
1683 09:57:46.777708
1684 09:57:46.777824 Set Vref, RX VrefLevel [Byte0]: 46
1685 09:57:46.780827 [Byte1]: 46
1686 09:57:46.784857
1687 09:57:46.784952 Set Vref, RX VrefLevel [Byte0]: 47
1688 09:57:46.787931 [Byte1]: 47
1689 09:57:46.792702
1690 09:57:46.792825 Set Vref, RX VrefLevel [Byte0]: 48
1691 09:57:46.795526 [Byte1]: 48
1692 09:57:46.799922
1693 09:57:46.800115 Set Vref, RX VrefLevel [Byte0]: 49
1694 09:57:46.803135 [Byte1]: 49
1695 09:57:46.807339
1696 09:57:46.807480 Set Vref, RX VrefLevel [Byte0]: 50
1697 09:57:46.810868 [Byte1]: 50
1698 09:57:46.815132
1699 09:57:46.815267 Set Vref, RX VrefLevel [Byte0]: 51
1700 09:57:46.818625 [Byte1]: 51
1701 09:57:46.822938
1702 09:57:46.823092 Set Vref, RX VrefLevel [Byte0]: 52
1703 09:57:46.826407 [Byte1]: 52
1704 09:57:46.830239
1705 09:57:46.830400 Set Vref, RX VrefLevel [Byte0]: 53
1706 09:57:46.833728 [Byte1]: 53
1707 09:57:46.838222
1708 09:57:46.838357 Set Vref, RX VrefLevel [Byte0]: 54
1709 09:57:46.841788 [Byte1]: 54
1710 09:57:46.845536
1711 09:57:46.845644 Set Vref, RX VrefLevel [Byte0]: 55
1712 09:57:46.848977 [Byte1]: 55
1713 09:57:46.853386
1714 09:57:46.853509 Set Vref, RX VrefLevel [Byte0]: 56
1715 09:57:46.856587 [Byte1]: 56
1716 09:57:46.860946
1717 09:57:46.861073 Set Vref, RX VrefLevel [Byte0]: 57
1718 09:57:46.864355 [Byte1]: 57
1719 09:57:46.868284
1720 09:57:46.868396 Set Vref, RX VrefLevel [Byte0]: 58
1721 09:57:46.871655 [Byte1]: 58
1722 09:57:46.876144
1723 09:57:46.876256 Set Vref, RX VrefLevel [Byte0]: 59
1724 09:57:46.879746 [Byte1]: 59
1725 09:57:46.883433
1726 09:57:46.883535 Set Vref, RX VrefLevel [Byte0]: 60
1727 09:57:46.886831 [Byte1]: 60
1728 09:57:46.891203
1729 09:57:46.891310 Set Vref, RX VrefLevel [Byte0]: 61
1730 09:57:46.894317 [Byte1]: 61
1731 09:57:46.899225
1732 09:57:46.899338 Set Vref, RX VrefLevel [Byte0]: 62
1733 09:57:46.901902 [Byte1]: 62
1734 09:57:46.906268
1735 09:57:46.906386 Set Vref, RX VrefLevel [Byte0]: 63
1736 09:57:46.910072 [Byte1]: 63
1737 09:57:46.914495
1738 09:57:46.914594 Set Vref, RX VrefLevel [Byte0]: 64
1739 09:57:46.917197 [Byte1]: 64
1740 09:57:46.922048
1741 09:57:46.922171 Set Vref, RX VrefLevel [Byte0]: 65
1742 09:57:46.924782 [Byte1]: 65
1743 09:57:46.929020
1744 09:57:46.929130 Set Vref, RX VrefLevel [Byte0]: 66
1745 09:57:46.932774 [Byte1]: 66
1746 09:57:46.936590
1747 09:57:46.936707 Set Vref, RX VrefLevel [Byte0]: 67
1748 09:57:46.940022 [Byte1]: 67
1749 09:57:46.944506
1750 09:57:46.944630 Set Vref, RX VrefLevel [Byte0]: 68
1751 09:57:46.947735 [Byte1]: 68
1752 09:57:46.952151
1753 09:57:46.952249 Set Vref, RX VrefLevel [Byte0]: 69
1754 09:57:46.955214 [Byte1]: 69
1755 09:57:46.959950
1756 09:57:46.960037 Set Vref, RX VrefLevel [Byte0]: 70
1757 09:57:46.962789 [Byte1]: 70
1758 09:57:46.967512
1759 09:57:46.967607 Set Vref, RX VrefLevel [Byte0]: 71
1760 09:57:46.970423 [Byte1]: 71
1761 09:57:46.975143
1762 09:57:46.975256 Set Vref, RX VrefLevel [Byte0]: 72
1763 09:57:46.978106 [Byte1]: 72
1764 09:57:46.982709
1765 09:57:46.982811 Set Vref, RX VrefLevel [Byte0]: 73
1766 09:57:46.985437 [Byte1]: 73
1767 09:57:46.989664
1768 09:57:46.989754 Set Vref, RX VrefLevel [Byte0]: 74
1769 09:57:46.993114 [Byte1]: 74
1770 09:57:46.997468
1771 09:57:46.997560 Final RX Vref Byte 0 = 55 to rank0
1772 09:57:47.001426 Final RX Vref Byte 1 = 59 to rank0
1773 09:57:47.004231 Final RX Vref Byte 0 = 55 to rank1
1774 09:57:47.007569 Final RX Vref Byte 1 = 59 to rank1==
1775 09:57:47.010727 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 09:57:47.017563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 09:57:47.017712 ==
1778 09:57:47.017786 DQS Delay:
1779 09:57:47.017850 DQS0 = 0, DQS1 = 0
1780 09:57:47.020915 DQM Delay:
1781 09:57:47.021008 DQM0 = 85, DQM1 = 81
1782 09:57:47.024443 DQ Delay:
1783 09:57:47.027346 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1784 09:57:47.027433 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1785 09:57:47.031052 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1786 09:57:47.034700 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1787 09:57:47.037727
1788 09:57:47.037821
1789 09:57:47.044205 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1790 09:57:47.047946 CH1 RK0: MR19=606, MR18=1A2D
1791 09:57:47.054320 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1792 09:57:47.054436
1793 09:57:47.057685 ----->DramcWriteLeveling(PI) begin...
1794 09:57:47.057775 ==
1795 09:57:47.060665 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 09:57:47.064310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 09:57:47.064401 ==
1798 09:57:47.067335 Write leveling (Byte 0): 27 => 27
1799 09:57:47.070930 Write leveling (Byte 1): 28 => 28
1800 09:57:47.074059 DramcWriteLeveling(PI) end<-----
1801 09:57:47.074187
1802 09:57:47.074328 ==
1803 09:57:47.077812 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 09:57:47.081024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 09:57:47.081147 ==
1806 09:57:47.084258 [Gating] SW mode calibration
1807 09:57:47.090517 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 09:57:47.097118 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 09:57:47.100655 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1810 09:57:47.103962 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1811 09:57:47.110841 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1812 09:57:47.114131 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 09:57:47.117329 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 09:57:47.123879 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:57:47.127397 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:57:47.130991 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:57:47.137094 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:57:47.141382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:57:47.144267 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:57:47.150210 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:57:47.153604 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:57:47.156852 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:57:47.163454 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:57:47.167035 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:57:47.170022 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1826 09:57:47.176590 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1827 09:57:47.180298 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:57:47.183623 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:57:47.189988 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:57:47.193318 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:57:47.196550 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:57:47.203279 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:57:47.206569 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:57:47.209957 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1835 09:57:47.216347 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1836 09:57:47.220096 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 09:57:47.223544 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 09:57:47.229536 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 09:57:47.232966 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 09:57:47.236406 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 09:57:47.242949 0 10 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
1842 09:57:47.246680 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (1 1)
1843 09:57:47.249759 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1844 09:57:47.256090 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:57:47.259638 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:57:47.263160 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:57:47.269408 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:57:47.272950 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:57:47.276298 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1850 09:57:47.282897 0 11 4 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
1851 09:57:47.286245 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1852 09:57:47.289311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 09:57:47.296028 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 09:57:47.299310 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 09:57:47.302394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 09:57:47.305974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 09:57:47.312438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 09:57:47.315754 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1859 09:57:47.319334 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 09:57:47.326077 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1861 09:57:47.329118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 09:57:47.332654 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 09:57:47.339010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 09:57:47.342313 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:57:47.345978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:57:47.352032 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:57:47.355415 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:57:47.359040 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 09:57:47.365533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 09:57:47.368555 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:57:47.372191 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 09:57:47.378775 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:57:47.382878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 09:57:47.385267 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1875 09:57:47.391730 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1876 09:57:47.391819 Total UI for P1: 0, mck2ui 16
1877 09:57:47.398736 best dqsien dly found for B0: ( 0, 14, 4)
1878 09:57:47.402207 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 09:57:47.406505 Total UI for P1: 0, mck2ui 16
1880 09:57:47.408498 best dqsien dly found for B1: ( 0, 14, 8)
1881 09:57:47.411934 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1882 09:57:47.414968 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1883 09:57:47.415041
1884 09:57:47.418515 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 09:57:47.422096 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1886 09:57:47.424869 [Gating] SW calibration Done
1887 09:57:47.424947 ==
1888 09:57:47.428339 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 09:57:47.431583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 09:57:47.434853 ==
1891 09:57:47.434934 RX Vref Scan: 0
1892 09:57:47.435006
1893 09:57:47.438591 RX Vref 0 -> 0, step: 1
1894 09:57:47.438707
1895 09:57:47.441556 RX Delay -130 -> 252, step: 16
1896 09:57:47.444887 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1897 09:57:47.448325 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1898 09:57:47.452093 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1899 09:57:47.455110 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1900 09:57:47.461339 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1901 09:57:47.465377 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1902 09:57:47.467996 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1903 09:57:47.471320 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1904 09:57:47.474869 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1905 09:57:47.481529 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1906 09:57:47.484888 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1907 09:57:47.488315 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1908 09:57:47.491261 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1909 09:57:47.494718 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1910 09:57:47.501096 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1911 09:57:47.504695 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1912 09:57:47.504782 ==
1913 09:57:47.507807 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 09:57:47.511152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 09:57:47.511227 ==
1916 09:57:47.514203 DQS Delay:
1917 09:57:47.514333 DQS0 = 0, DQS1 = 0
1918 09:57:47.514397 DQM Delay:
1919 09:57:47.518283 DQM0 = 85, DQM1 = 83
1920 09:57:47.518394 DQ Delay:
1921 09:57:47.521133 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1922 09:57:47.524710 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1923 09:57:47.527884 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1924 09:57:47.530742 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1925 09:57:47.530852
1926 09:57:47.530933
1927 09:57:47.530995 ==
1928 09:57:47.534541 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 09:57:47.541183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 09:57:47.541276 ==
1931 09:57:47.541345
1932 09:57:47.541406
1933 09:57:47.541465 TX Vref Scan disable
1934 09:57:47.544980 == TX Byte 0 ==
1935 09:57:47.548945 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1936 09:57:47.551391 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1937 09:57:47.554810 == TX Byte 1 ==
1938 09:57:47.557815 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1939 09:57:47.564513 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1940 09:57:47.564616 ==
1941 09:57:47.567995 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 09:57:47.571028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 09:57:47.571133 ==
1944 09:57:47.584386 TX Vref=22, minBit 1, minWin=27, winSum=450
1945 09:57:47.586710 TX Vref=24, minBit 1, minWin=27, winSum=451
1946 09:57:47.590206 TX Vref=26, minBit 0, minWin=28, winSum=453
1947 09:57:47.593411 TX Vref=28, minBit 5, minWin=27, winSum=454
1948 09:57:47.597170 TX Vref=30, minBit 0, minWin=28, winSum=455
1949 09:57:47.604510 TX Vref=32, minBit 1, minWin=27, winSum=453
1950 09:57:47.606795 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1951 09:57:47.606900
1952 09:57:47.609980 Final TX Range 1 Vref 30
1953 09:57:47.610081
1954 09:57:47.610147 ==
1955 09:57:47.614402 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 09:57:47.617021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 09:57:47.617123 ==
1958 09:57:47.620110
1959 09:57:47.620211
1960 09:57:47.620310 TX Vref Scan disable
1961 09:57:47.623679 == TX Byte 0 ==
1962 09:57:47.626604 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 09:57:47.633440 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 09:57:47.633531 == TX Byte 1 ==
1965 09:57:47.637118 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 09:57:47.643213 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 09:57:47.643300
1968 09:57:47.643365 [DATLAT]
1969 09:57:47.643461 Freq=800, CH1 RK1
1970 09:57:47.643520
1971 09:57:47.646628 DATLAT Default: 0xa
1972 09:57:47.646708 0, 0xFFFF, sum = 0
1973 09:57:47.650150 1, 0xFFFF, sum = 0
1974 09:57:47.650275 2, 0xFFFF, sum = 0
1975 09:57:47.653792 3, 0xFFFF, sum = 0
1976 09:57:47.653864 4, 0xFFFF, sum = 0
1977 09:57:47.656905 5, 0xFFFF, sum = 0
1978 09:57:47.660019 6, 0xFFFF, sum = 0
1979 09:57:47.660093 7, 0xFFFF, sum = 0
1980 09:57:47.663485 8, 0xFFFF, sum = 0
1981 09:57:47.663559 9, 0x0, sum = 1
1982 09:57:47.663618 10, 0x0, sum = 2
1983 09:57:47.666847 11, 0x0, sum = 3
1984 09:57:47.666942 12, 0x0, sum = 4
1985 09:57:47.669776 best_step = 10
1986 09:57:47.669861
1987 09:57:47.669939 ==
1988 09:57:47.673329 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 09:57:47.676543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 09:57:47.676621 ==
1991 09:57:47.680163 RX Vref Scan: 0
1992 09:57:47.680234
1993 09:57:47.680295 RX Vref 0 -> 0, step: 1
1994 09:57:47.684063
1995 09:57:47.684141 RX Delay -95 -> 252, step: 8
1996 09:57:47.690428 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1997 09:57:47.693685 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1998 09:57:47.696847 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1999 09:57:47.700615 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2000 09:57:47.704108 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2001 09:57:47.710008 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2002 09:57:47.713394 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2003 09:57:47.716975 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2004 09:57:47.720148 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2005 09:57:47.723692 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2006 09:57:47.730424 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2007 09:57:47.733512 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2008 09:57:47.736821 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2009 09:57:47.740192 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2010 09:57:47.747226 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2011 09:57:47.750837 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2012 09:57:47.750922 ==
2013 09:57:47.753399 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 09:57:47.756869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 09:57:47.756975 ==
2016 09:57:47.757062 DQS Delay:
2017 09:57:47.760309 DQS0 = 0, DQS1 = 0
2018 09:57:47.760396 DQM Delay:
2019 09:57:47.763182 DQM0 = 86, DQM1 = 82
2020 09:57:47.763285 DQ Delay:
2021 09:57:47.767031 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2022 09:57:47.770511 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2023 09:57:47.773556 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =72
2024 09:57:47.776642 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2025 09:57:47.776739
2026 09:57:47.776828
2027 09:57:47.786449 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2028 09:57:47.786582 CH1 RK1: MR19=606, MR18=1F3A
2029 09:57:47.793426 CH1_RK1: MR19=0x606, MR18=0x1F3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2030 09:57:47.796551 [RxdqsGatingPostProcess] freq 800
2031 09:57:47.803709 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 09:57:47.806531 Pre-setting of DQS Precalculation
2033 09:57:47.809695 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 09:57:47.816558 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 09:57:47.826754 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 09:57:47.826902
2037 09:57:47.827008
2038 09:57:47.827095 [Calibration Summary] 1600 Mbps
2039 09:57:47.830018 CH 0, Rank 0
2040 09:57:47.833228 SW Impedance : PASS
2041 09:57:47.833342 DUTY Scan : NO K
2042 09:57:47.836357 ZQ Calibration : PASS
2043 09:57:47.836448 Jitter Meter : NO K
2044 09:57:47.840472 CBT Training : PASS
2045 09:57:47.843675 Write leveling : PASS
2046 09:57:47.843775 RX DQS gating : PASS
2047 09:57:47.846552 RX DQ/DQS(RDDQC) : PASS
2048 09:57:47.850114 TX DQ/DQS : PASS
2049 09:57:47.850261 RX DATLAT : PASS
2050 09:57:47.853688 RX DQ/DQS(Engine): PASS
2051 09:57:47.856555 TX OE : NO K
2052 09:57:47.856661 All Pass.
2053 09:57:47.856754
2054 09:57:47.856837 CH 0, Rank 1
2055 09:57:47.859530 SW Impedance : PASS
2056 09:57:47.863126 DUTY Scan : NO K
2057 09:57:47.863235 ZQ Calibration : PASS
2058 09:57:47.865908 Jitter Meter : NO K
2059 09:57:47.869867 CBT Training : PASS
2060 09:57:47.869978 Write leveling : PASS
2061 09:57:47.872677 RX DQS gating : PASS
2062 09:57:47.876615 RX DQ/DQS(RDDQC) : PASS
2063 09:57:47.876730 TX DQ/DQS : PASS
2064 09:57:47.879321 RX DATLAT : PASS
2065 09:57:47.879415 RX DQ/DQS(Engine): PASS
2066 09:57:47.882568 TX OE : NO K
2067 09:57:47.882692 All Pass.
2068 09:57:47.882782
2069 09:57:47.886038 CH 1, Rank 0
2070 09:57:47.889217 SW Impedance : PASS
2071 09:57:47.889322 DUTY Scan : NO K
2072 09:57:47.892605 ZQ Calibration : PASS
2073 09:57:47.892707 Jitter Meter : NO K
2074 09:57:47.895981 CBT Training : PASS
2075 09:57:47.899210 Write leveling : PASS
2076 09:57:47.899320 RX DQS gating : PASS
2077 09:57:47.903173 RX DQ/DQS(RDDQC) : PASS
2078 09:57:47.906181 TX DQ/DQS : PASS
2079 09:57:47.906336 RX DATLAT : PASS
2080 09:57:47.909491 RX DQ/DQS(Engine): PASS
2081 09:57:47.912490 TX OE : NO K
2082 09:57:47.912595 All Pass.
2083 09:57:47.912683
2084 09:57:47.912765 CH 1, Rank 1
2085 09:57:47.915892 SW Impedance : PASS
2086 09:57:47.919200 DUTY Scan : NO K
2087 09:57:47.919353 ZQ Calibration : PASS
2088 09:57:47.922707 Jitter Meter : NO K
2089 09:57:47.926089 CBT Training : PASS
2090 09:57:47.926227 Write leveling : PASS
2091 09:57:47.930142 RX DQS gating : PASS
2092 09:57:47.932656 RX DQ/DQS(RDDQC) : PASS
2093 09:57:47.932763 TX DQ/DQS : PASS
2094 09:57:47.935956 RX DATLAT : PASS
2095 09:57:47.936076 RX DQ/DQS(Engine): PASS
2096 09:57:47.939900 TX OE : NO K
2097 09:57:47.940002 All Pass.
2098 09:57:47.940092
2099 09:57:47.943043 DramC Write-DBI off
2100 09:57:47.946008 PER_BANK_REFRESH: Hybrid Mode
2101 09:57:47.946097 TX_TRACKING: ON
2102 09:57:47.948952 [GetDramInforAfterCalByMRR] Vendor 6.
2103 09:57:47.952658 [GetDramInforAfterCalByMRR] Revision 606.
2104 09:57:47.958756 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 09:57:47.958850 MR0 0x3b3b
2106 09:57:47.958937 MR8 0x5151
2107 09:57:47.962196 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 09:57:47.962321
2109 09:57:47.965662 MR0 0x3b3b
2110 09:57:47.965750 MR8 0x5151
2111 09:57:47.968829 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 09:57:47.968918
2113 09:57:47.979331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 09:57:47.982620 [FAST_K] Save calibration result to emmc
2115 09:57:47.985447 [FAST_K] Save calibration result to emmc
2116 09:57:47.989609 dram_init: config_dvfs: 1
2117 09:57:47.991852 dramc_set_vcore_voltage set vcore to 662500
2118 09:57:47.995488 Read voltage for 1200, 2
2119 09:57:47.995598 Vio18 = 0
2120 09:57:47.995686 Vcore = 662500
2121 09:57:47.998289 Vdram = 0
2122 09:57:47.998366 Vddq = 0
2123 09:57:47.998448 Vmddr = 0
2124 09:57:48.005732 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 09:57:48.008351 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 09:57:48.011605 MEM_TYPE=3, freq_sel=15
2127 09:57:48.014997 sv_algorithm_assistance_LP4_1600
2128 09:57:48.018546 ============ PULL DRAM RESETB DOWN ============
2129 09:57:48.021906 ========== PULL DRAM RESETB DOWN end =========
2130 09:57:48.028373 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 09:57:48.031532 ===================================
2132 09:57:48.031630 LPDDR4 DRAM CONFIGURATION
2133 09:57:48.035156 ===================================
2134 09:57:48.038447 EX_ROW_EN[0] = 0x0
2135 09:57:48.041681 EX_ROW_EN[1] = 0x0
2136 09:57:48.041774 LP4Y_EN = 0x0
2137 09:57:48.044828 WORK_FSP = 0x0
2138 09:57:48.044916 WL = 0x4
2139 09:57:48.048119 RL = 0x4
2140 09:57:48.048208 BL = 0x2
2141 09:57:48.051964 RPST = 0x0
2142 09:57:48.052054 RD_PRE = 0x0
2143 09:57:48.055272 WR_PRE = 0x1
2144 09:57:48.055359 WR_PST = 0x0
2145 09:57:48.058111 DBI_WR = 0x0
2146 09:57:48.058223 DBI_RD = 0x0
2147 09:57:48.061801 OTF = 0x1
2148 09:57:48.064912 ===================================
2149 09:57:48.068732 ===================================
2150 09:57:48.068830 ANA top config
2151 09:57:48.071691 ===================================
2152 09:57:48.074845 DLL_ASYNC_EN = 0
2153 09:57:48.077966 ALL_SLAVE_EN = 0
2154 09:57:48.081405 NEW_RANK_MODE = 1
2155 09:57:48.081502 DLL_IDLE_MODE = 1
2156 09:57:48.084759 LP45_APHY_COMB_EN = 1
2157 09:57:48.088546 TX_ODT_DIS = 1
2158 09:57:48.091735 NEW_8X_MODE = 1
2159 09:57:48.095016 ===================================
2160 09:57:48.098734 ===================================
2161 09:57:48.101293 data_rate = 2400
2162 09:57:48.101382 CKR = 1
2163 09:57:48.104807 DQ_P2S_RATIO = 8
2164 09:57:48.108045 ===================================
2165 09:57:48.111749 CA_P2S_RATIO = 8
2166 09:57:48.114772 DQ_CA_OPEN = 0
2167 09:57:48.117776 DQ_SEMI_OPEN = 0
2168 09:57:48.121438 CA_SEMI_OPEN = 0
2169 09:57:48.121533 CA_FULL_RATE = 0
2170 09:57:48.124524 DQ_CKDIV4_EN = 0
2171 09:57:48.127726 CA_CKDIV4_EN = 0
2172 09:57:48.131335 CA_PREDIV_EN = 0
2173 09:57:48.134687 PH8_DLY = 17
2174 09:57:48.138088 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 09:57:48.138177 DQ_AAMCK_DIV = 4
2176 09:57:48.141463 CA_AAMCK_DIV = 4
2177 09:57:48.144459 CA_ADMCK_DIV = 4
2178 09:57:48.147587 DQ_TRACK_CA_EN = 0
2179 09:57:48.151214 CA_PICK = 1200
2180 09:57:48.154245 CA_MCKIO = 1200
2181 09:57:48.158107 MCKIO_SEMI = 0
2182 09:57:48.158198 PLL_FREQ = 2366
2183 09:57:48.160923 DQ_UI_PI_RATIO = 32
2184 09:57:48.164258 CA_UI_PI_RATIO = 0
2185 09:57:48.167826 ===================================
2186 09:57:48.170987 ===================================
2187 09:57:48.174176 memory_type:LPDDR4
2188 09:57:48.174293 GP_NUM : 10
2189 09:57:48.177460 SRAM_EN : 1
2190 09:57:48.180865 MD32_EN : 0
2191 09:57:48.184453 ===================================
2192 09:57:48.184546 [ANA_INIT] >>>>>>>>>>>>>>
2193 09:57:48.188174 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 09:57:48.190798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 09:57:48.194535 ===================================
2196 09:57:48.197417 data_rate = 2400,PCW = 0X5b00
2197 09:57:48.200602 ===================================
2198 09:57:48.204328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 09:57:48.210646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 09:57:48.214597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 09:57:48.220573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 09:57:48.224442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 09:57:48.227447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 09:57:48.230507 [ANA_INIT] flow start
2205 09:57:48.230596 [ANA_INIT] PLL >>>>>>>>
2206 09:57:48.234154 [ANA_INIT] PLL <<<<<<<<
2207 09:57:48.237314 [ANA_INIT] MIDPI >>>>>>>>
2208 09:57:48.237402 [ANA_INIT] MIDPI <<<<<<<<
2209 09:57:48.240191 [ANA_INIT] DLL >>>>>>>>
2210 09:57:48.243772 [ANA_INIT] DLL <<<<<<<<
2211 09:57:48.243862 [ANA_INIT] flow end
2212 09:57:48.250054 ============ LP4 DIFF to SE enter ============
2213 09:57:48.253914 ============ LP4 DIFF to SE exit ============
2214 09:57:48.256891 [ANA_INIT] <<<<<<<<<<<<<
2215 09:57:48.260867 [Flow] Enable top DCM control >>>>>
2216 09:57:48.263915 [Flow] Enable top DCM control <<<<<
2217 09:57:48.264007 Enable DLL master slave shuffle
2218 09:57:48.271281 ==============================================================
2219 09:57:48.273184 Gating Mode config
2220 09:57:48.277021 ==============================================================
2221 09:57:48.279737 Config description:
2222 09:57:48.289508 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 09:57:48.296776 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 09:57:48.299251 SELPH_MODE 0: By rank 1: By Phase
2225 09:57:48.306929 ==============================================================
2226 09:57:48.309452 GAT_TRACK_EN = 1
2227 09:57:48.312637 RX_GATING_MODE = 2
2228 09:57:48.316464 RX_GATING_TRACK_MODE = 2
2229 09:57:48.319408 SELPH_MODE = 1
2230 09:57:48.323111 PICG_EARLY_EN = 1
2231 09:57:48.323208 VALID_LAT_VALUE = 1
2232 09:57:48.329438 ==============================================================
2233 09:57:48.332716 Enter into Gating configuration >>>>
2234 09:57:48.336025 Exit from Gating configuration <<<<
2235 09:57:48.339106 Enter into DVFS_PRE_config >>>>>
2236 09:57:48.349380 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 09:57:48.352427 Exit from DVFS_PRE_config <<<<<
2238 09:57:48.356244 Enter into PICG configuration >>>>
2239 09:57:48.359141 Exit from PICG configuration <<<<
2240 09:57:48.362616 [RX_INPUT] configuration >>>>>
2241 09:57:48.365661 [RX_INPUT] configuration <<<<<
2242 09:57:48.372379 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 09:57:48.375962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 09:57:48.382238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 09:57:48.389105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 09:57:48.395716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 09:57:48.402387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 09:57:48.405626 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 09:57:48.409293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 09:57:48.412444 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 09:57:48.418911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 09:57:48.422382 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 09:57:48.425392 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 09:57:48.428654 ===================================
2255 09:57:48.431968 LPDDR4 DRAM CONFIGURATION
2256 09:57:48.435715 ===================================
2257 09:57:48.435806 EX_ROW_EN[0] = 0x0
2258 09:57:48.438857 EX_ROW_EN[1] = 0x0
2259 09:57:48.441871 LP4Y_EN = 0x0
2260 09:57:48.442019 WORK_FSP = 0x0
2261 09:57:48.445104 WL = 0x4
2262 09:57:48.445192 RL = 0x4
2263 09:57:48.448919 BL = 0x2
2264 09:57:48.449007 RPST = 0x0
2265 09:57:48.452574 RD_PRE = 0x0
2266 09:57:48.452701 WR_PRE = 0x1
2267 09:57:48.455232 WR_PST = 0x0
2268 09:57:48.455319 DBI_WR = 0x0
2269 09:57:48.458743 DBI_RD = 0x0
2270 09:57:48.458832 OTF = 0x1
2271 09:57:48.462213 ===================================
2272 09:57:48.465824 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 09:57:48.472151 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 09:57:48.475721 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 09:57:48.478268 ===================================
2276 09:57:48.481994 LPDDR4 DRAM CONFIGURATION
2277 09:57:48.486052 ===================================
2278 09:57:48.486149 EX_ROW_EN[0] = 0x10
2279 09:57:48.488730 EX_ROW_EN[1] = 0x0
2280 09:57:48.488818 LP4Y_EN = 0x0
2281 09:57:48.491826 WORK_FSP = 0x0
2282 09:57:48.494945 WL = 0x4
2283 09:57:48.495034 RL = 0x4
2284 09:57:48.498259 BL = 0x2
2285 09:57:48.498350 RPST = 0x0
2286 09:57:48.501818 RD_PRE = 0x0
2287 09:57:48.501923 WR_PRE = 0x1
2288 09:57:48.505178 WR_PST = 0x0
2289 09:57:48.505288 DBI_WR = 0x0
2290 09:57:48.508185 DBI_RD = 0x0
2291 09:57:48.508291 OTF = 0x1
2292 09:57:48.511447 ===================================
2293 09:57:48.518069 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 09:57:48.518187 ==
2295 09:57:48.521623 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 09:57:48.524764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 09:57:48.524875 ==
2298 09:57:48.529078 [Duty_Offset_Calibration]
2299 09:57:48.531553 B0:2 B1:0 CA:4
2300 09:57:48.531655
2301 09:57:48.534551 [DutyScan_Calibration_Flow] k_type=0
2302 09:57:48.542747
2303 09:57:48.542844 ==CLK 0==
2304 09:57:48.545695 Final CLK duty delay cell = -4
2305 09:57:48.548665 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2306 09:57:48.552313 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2307 09:57:48.555331 [-4] AVG Duty = 4937%(X100)
2308 09:57:48.555419
2309 09:57:48.559058 CH0 CLK Duty spec in!! Max-Min= 187%
2310 09:57:48.561950 [DutyScan_Calibration_Flow] ====Done====
2311 09:57:48.562035
2312 09:57:48.565568 [DutyScan_Calibration_Flow] k_type=1
2313 09:57:48.581038
2314 09:57:48.581180 ==DQS 0 ==
2315 09:57:48.584117 Final DQS duty delay cell = -4
2316 09:57:48.587730 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2317 09:57:48.591762 [-4] MIN Duty = 4844%(X100), DQS PI = 28
2318 09:57:48.594235 [-4] AVG Duty = 4906%(X100)
2319 09:57:48.594359
2320 09:57:48.594425 ==DQS 1 ==
2321 09:57:48.597428 Final DQS duty delay cell = 0
2322 09:57:48.600955 [0] MAX Duty = 5125%(X100), DQS PI = 4
2323 09:57:48.604542 [0] MIN Duty = 5000%(X100), DQS PI = 0
2324 09:57:48.607684 [0] AVG Duty = 5062%(X100)
2325 09:57:48.607774
2326 09:57:48.611171 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2327 09:57:48.611257
2328 09:57:48.614509 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2329 09:57:48.617479 [DutyScan_Calibration_Flow] ====Done====
2330 09:57:48.617590
2331 09:57:48.620970 [DutyScan_Calibration_Flow] k_type=3
2332 09:57:48.637732
2333 09:57:48.637878 ==DQM 0 ==
2334 09:57:48.641347 Final DQM duty delay cell = 0
2335 09:57:48.644576 [0] MAX Duty = 5125%(X100), DQS PI = 20
2336 09:57:48.647631 [0] MIN Duty = 4844%(X100), DQS PI = 54
2337 09:57:48.651448 [0] AVG Duty = 4984%(X100)
2338 09:57:48.651536
2339 09:57:48.651601 ==DQM 1 ==
2340 09:57:48.654691 Final DQM duty delay cell = 0
2341 09:57:48.657625 [0] MAX Duty = 5000%(X100), DQS PI = 6
2342 09:57:48.661184 [0] MIN Duty = 4875%(X100), DQS PI = 20
2343 09:57:48.661272 [0] AVG Duty = 4937%(X100)
2344 09:57:48.664363
2345 09:57:48.667593 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2346 09:57:48.667684
2347 09:57:48.671452 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2348 09:57:48.674294 [DutyScan_Calibration_Flow] ====Done====
2349 09:57:48.674401
2350 09:57:48.677433 [DutyScan_Calibration_Flow] k_type=2
2351 09:57:48.694308
2352 09:57:48.694473 ==DQ 0 ==
2353 09:57:48.697621 Final DQ duty delay cell = 0
2354 09:57:48.700863 [0] MAX Duty = 5125%(X100), DQS PI = 18
2355 09:57:48.704244 [0] MIN Duty = 4969%(X100), DQS PI = 52
2356 09:57:48.704366 [0] AVG Duty = 5047%(X100)
2357 09:57:48.704456
2358 09:57:48.707520 ==DQ 1 ==
2359 09:57:48.710736 Final DQ duty delay cell = 0
2360 09:57:48.713995 [0] MAX Duty = 5156%(X100), DQS PI = 6
2361 09:57:48.718059 [0] MIN Duty = 4938%(X100), DQS PI = 16
2362 09:57:48.718179 [0] AVG Duty = 5047%(X100)
2363 09:57:48.718307
2364 09:57:48.720973 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2365 09:57:48.721069
2366 09:57:48.727437 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2367 09:57:48.730992 [DutyScan_Calibration_Flow] ====Done====
2368 09:57:48.731092 ==
2369 09:57:48.734290 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 09:57:48.737439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 09:57:48.737533 ==
2372 09:57:48.740551 [Duty_Offset_Calibration]
2373 09:57:48.740636 B0:0 B1:-1 CA:3
2374 09:57:48.740702
2375 09:57:48.743920 [DutyScan_Calibration_Flow] k_type=0
2376 09:57:48.753674
2377 09:57:48.753798 ==CLK 0==
2378 09:57:48.756988 Final CLK duty delay cell = -4
2379 09:57:48.760478 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2380 09:57:48.763824 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2381 09:57:48.767065 [-4] AVG Duty = 4938%(X100)
2382 09:57:48.767169
2383 09:57:48.770060 CH1 CLK Duty spec in!! Max-Min= 124%
2384 09:57:48.773723 [DutyScan_Calibration_Flow] ====Done====
2385 09:57:48.773838
2386 09:57:48.776636 [DutyScan_Calibration_Flow] k_type=1
2387 09:57:48.792373
2388 09:57:48.792548 ==DQS 0 ==
2389 09:57:48.796252 Final DQS duty delay cell = 0
2390 09:57:48.799127 [0] MAX Duty = 5187%(X100), DQS PI = 18
2391 09:57:48.802528 [0] MIN Duty = 4907%(X100), DQS PI = 38
2392 09:57:48.805156 [0] AVG Duty = 5047%(X100)
2393 09:57:48.805268
2394 09:57:48.805357 ==DQS 1 ==
2395 09:57:48.808557 Final DQS duty delay cell = -4
2396 09:57:48.811967 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2397 09:57:48.815516 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2398 09:57:48.818895 [-4] AVG Duty = 4937%(X100)
2399 09:57:48.819012
2400 09:57:48.821931 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2401 09:57:48.822030
2402 09:57:48.825414 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2403 09:57:48.829290 [DutyScan_Calibration_Flow] ====Done====
2404 09:57:48.829387
2405 09:57:48.832305 [DutyScan_Calibration_Flow] k_type=3
2406 09:57:48.848876
2407 09:57:48.849028 ==DQM 0 ==
2408 09:57:48.852095 Final DQM duty delay cell = 0
2409 09:57:48.855811 [0] MAX Duty = 5031%(X100), DQS PI = 28
2410 09:57:48.859405 [0] MIN Duty = 4813%(X100), DQS PI = 38
2411 09:57:48.862467 [0] AVG Duty = 4922%(X100)
2412 09:57:48.862558
2413 09:57:48.862622 ==DQM 1 ==
2414 09:57:48.865730 Final DQM duty delay cell = 0
2415 09:57:48.868920 [0] MAX Duty = 5000%(X100), DQS PI = 36
2416 09:57:48.871879 [0] MIN Duty = 4844%(X100), DQS PI = 0
2417 09:57:48.875596 [0] AVG Duty = 4922%(X100)
2418 09:57:48.875728
2419 09:57:48.878962 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2420 09:57:48.879048
2421 09:57:48.882215 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2422 09:57:48.885206 [DutyScan_Calibration_Flow] ====Done====
2423 09:57:48.885310
2424 09:57:48.888778 [DutyScan_Calibration_Flow] k_type=2
2425 09:57:48.905076
2426 09:57:48.905249 ==DQ 0 ==
2427 09:57:48.907969 Final DQ duty delay cell = -4
2428 09:57:48.911425 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2429 09:57:48.914608 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2430 09:57:48.917882 [-4] AVG Duty = 4937%(X100)
2431 09:57:48.917994
2432 09:57:48.918084 ==DQ 1 ==
2433 09:57:48.921407 Final DQ duty delay cell = 0
2434 09:57:48.924973 [0] MAX Duty = 5031%(X100), DQS PI = 10
2435 09:57:48.928476 [0] MIN Duty = 4844%(X100), DQS PI = 62
2436 09:57:48.932067 [0] AVG Duty = 4937%(X100)
2437 09:57:48.932166
2438 09:57:48.934531 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2439 09:57:48.934618
2440 09:57:48.938572 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2441 09:57:48.941510 [DutyScan_Calibration_Flow] ====Done====
2442 09:57:48.944901 nWR fixed to 30
2443 09:57:48.947888 [ModeRegInit_LP4] CH0 RK0
2444 09:57:48.947984 [ModeRegInit_LP4] CH0 RK1
2445 09:57:48.951084 [ModeRegInit_LP4] CH1 RK0
2446 09:57:48.954823 [ModeRegInit_LP4] CH1 RK1
2447 09:57:48.954920 match AC timing 7
2448 09:57:48.961661 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 09:57:48.964530 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 09:57:48.967854 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 09:57:48.974468 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 09:57:48.978054 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 09:57:48.978157 ==
2454 09:57:48.980954 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 09:57:48.984472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 09:57:48.984562 ==
2457 09:57:48.991859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 09:57:48.998218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2459 09:57:49.005350 [CA 0] Center 39 (9~70) winsize 62
2460 09:57:49.008746 [CA 1] Center 39 (9~70) winsize 62
2461 09:57:49.011731 [CA 2] Center 35 (5~66) winsize 62
2462 09:57:49.015635 [CA 3] Center 35 (5~66) winsize 62
2463 09:57:49.018191 [CA 4] Center 34 (4~64) winsize 61
2464 09:57:49.021372 [CA 5] Center 33 (3~63) winsize 61
2465 09:57:49.021547
2466 09:57:49.024727 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2467 09:57:49.024814
2468 09:57:49.028188 [CATrainingPosCal] consider 1 rank data
2469 09:57:49.031658 u2DelayCellTimex100 = 270/100 ps
2470 09:57:49.035299 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2471 09:57:49.041764 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2472 09:57:49.044730 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2473 09:57:49.047798 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 09:57:49.051228 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2475 09:57:49.054549 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2476 09:57:49.054641
2477 09:57:49.057762 CA PerBit enable=1, Macro0, CA PI delay=33
2478 09:57:49.057847
2479 09:57:49.061145 [CBTSetCACLKResult] CA Dly = 33
2480 09:57:49.061258 CS Dly: 7 (0~38)
2481 09:57:49.064562 ==
2482 09:57:49.067951 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 09:57:49.071378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 09:57:49.071468 ==
2485 09:57:49.074752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 09:57:49.081254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2487 09:57:49.091033 [CA 0] Center 39 (9~70) winsize 62
2488 09:57:49.094128 [CA 1] Center 39 (9~70) winsize 62
2489 09:57:49.097660 [CA 2] Center 35 (5~66) winsize 62
2490 09:57:49.100809 [CA 3] Center 35 (5~66) winsize 62
2491 09:57:49.104641 [CA 4] Center 34 (3~65) winsize 63
2492 09:57:49.107842 [CA 5] Center 33 (3~63) winsize 61
2493 09:57:49.107939
2494 09:57:49.110757 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 09:57:49.110847
2496 09:57:49.114227 [CATrainingPosCal] consider 2 rank data
2497 09:57:49.117718 u2DelayCellTimex100 = 270/100 ps
2498 09:57:49.120737 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2499 09:57:49.127447 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 09:57:49.130537 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 09:57:49.134241 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 09:57:49.137221 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2503 09:57:49.140442 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2504 09:57:49.140534
2505 09:57:49.144225 CA PerBit enable=1, Macro0, CA PI delay=33
2506 09:57:49.144336
2507 09:57:49.146963 [CBTSetCACLKResult] CA Dly = 33
2508 09:57:49.147040 CS Dly: 8 (0~41)
2509 09:57:49.150635
2510 09:57:49.153849 ----->DramcWriteLeveling(PI) begin...
2511 09:57:49.153933 ==
2512 09:57:49.157158 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 09:57:49.160596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 09:57:49.160687 ==
2515 09:57:49.164749 Write leveling (Byte 0): 32 => 32
2516 09:57:49.167539 Write leveling (Byte 1): 26 => 26
2517 09:57:49.170282 DramcWriteLeveling(PI) end<-----
2518 09:57:49.170384
2519 09:57:49.170449 ==
2520 09:57:49.173537 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 09:57:49.177392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 09:57:49.177505 ==
2523 09:57:49.180271 [Gating] SW mode calibration
2524 09:57:49.187031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 09:57:49.193650 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 09:57:49.196760 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2527 09:57:49.200773 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2528 09:57:49.207014 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 09:57:49.210411 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 09:57:49.213830 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 09:57:49.220581 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 09:57:49.223631 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2533 09:57:49.226843 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2534 09:57:49.230449 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
2535 09:57:49.237010 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2536 09:57:49.240069 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 09:57:49.243268 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 09:57:49.250208 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 09:57:49.253258 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 09:57:49.256912 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2541 09:57:49.263814 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2542 09:57:49.267395 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2543 09:57:49.270480 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 09:57:49.277242 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 09:57:49.280410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 09:57:49.283603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 09:57:49.290654 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 09:57:49.293460 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 09:57:49.296978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 09:57:49.303439 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 09:57:49.306849 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 09:57:49.310152 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 09:57:49.316451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 09:57:49.320246 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 09:57:49.324087 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:57:49.329710 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:57:49.332924 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 09:57:49.336406 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 09:57:49.343027 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 09:57:49.346285 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 09:57:49.349974 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 09:57:49.356407 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:57:49.359668 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:57:49.363202 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 09:57:49.370206 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 09:57:49.373181 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 09:57:49.376152 Total UI for P1: 0, mck2ui 16
2568 09:57:49.379543 best dqsien dly found for B0: ( 1, 3, 26)
2569 09:57:49.382942 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 09:57:49.386278 Total UI for P1: 0, mck2ui 16
2571 09:57:49.389652 best dqsien dly found for B1: ( 1, 4, 0)
2572 09:57:49.392903 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2573 09:57:49.396238 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2574 09:57:49.396325
2575 09:57:49.400034 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2576 09:57:49.403455 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2577 09:57:49.406687 [Gating] SW calibration Done
2578 09:57:49.406772 ==
2579 09:57:49.409293 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 09:57:49.416236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 09:57:49.416342 ==
2582 09:57:49.416413 RX Vref Scan: 0
2583 09:57:49.416473
2584 09:57:49.420044 RX Vref 0 -> 0, step: 1
2585 09:57:49.420134
2586 09:57:49.422652 RX Delay -40 -> 252, step: 8
2587 09:57:49.425579 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2588 09:57:49.429630 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2589 09:57:49.432965 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2590 09:57:49.439027 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2591 09:57:49.442635 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2592 09:57:49.445627 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2593 09:57:49.448915 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2594 09:57:49.452415 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2595 09:57:49.456110 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2596 09:57:49.462375 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2597 09:57:49.465940 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2598 09:57:49.468940 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2599 09:57:49.472205 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2600 09:57:49.478783 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2601 09:57:49.482141 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2602 09:57:49.486148 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2603 09:57:49.486245 ==
2604 09:57:49.488945 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 09:57:49.492058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 09:57:49.492150 ==
2607 09:57:49.496337 DQS Delay:
2608 09:57:49.496424 DQS0 = 0, DQS1 = 0
2609 09:57:49.498687 DQM Delay:
2610 09:57:49.498784 DQM0 = 119, DQM1 = 108
2611 09:57:49.498852 DQ Delay:
2612 09:57:49.502000 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2613 09:57:49.509224 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2614 09:57:49.511783 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2615 09:57:49.515737 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2616 09:57:49.515832
2617 09:57:49.515900
2618 09:57:49.515961 ==
2619 09:57:49.519011 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 09:57:49.521728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 09:57:49.521813 ==
2622 09:57:49.521879
2623 09:57:49.521938
2624 09:57:49.525607 TX Vref Scan disable
2625 09:57:49.528797 == TX Byte 0 ==
2626 09:57:49.532002 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2627 09:57:49.535227 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2628 09:57:49.538495 == TX Byte 1 ==
2629 09:57:49.542159 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2630 09:57:49.545654 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2631 09:57:49.545751 ==
2632 09:57:49.548683 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 09:57:49.551981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 09:57:49.555082 ==
2635 09:57:49.565965 TX Vref=22, minBit 1, minWin=25, winSum=411
2636 09:57:49.569112 TX Vref=24, minBit 1, minWin=25, winSum=419
2637 09:57:49.572661 TX Vref=26, minBit 1, minWin=25, winSum=419
2638 09:57:49.575681 TX Vref=28, minBit 5, minWin=26, winSum=430
2639 09:57:49.579313 TX Vref=30, minBit 5, minWin=26, winSum=428
2640 09:57:49.582096 TX Vref=32, minBit 0, minWin=26, winSum=426
2641 09:57:49.588638 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2642 09:57:49.588749
2643 09:57:49.592357 Final TX Range 1 Vref 28
2644 09:57:49.592449
2645 09:57:49.592515 ==
2646 09:57:49.596097 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 09:57:49.598661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 09:57:49.598749 ==
2649 09:57:49.601859
2650 09:57:49.601946
2651 09:57:49.602011 TX Vref Scan disable
2652 09:57:49.606044 == TX Byte 0 ==
2653 09:57:49.609297 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2654 09:57:49.612182 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2655 09:57:49.615670 == TX Byte 1 ==
2656 09:57:49.618692 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2657 09:57:49.625299 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2658 09:57:49.625418
2659 09:57:49.625486 [DATLAT]
2660 09:57:49.625548 Freq=1200, CH0 RK0
2661 09:57:49.625607
2662 09:57:49.629065 DATLAT Default: 0xd
2663 09:57:49.629152 0, 0xFFFF, sum = 0
2664 09:57:49.632555 1, 0xFFFF, sum = 0
2665 09:57:49.632641 2, 0xFFFF, sum = 0
2666 09:57:49.635808 3, 0xFFFF, sum = 0
2667 09:57:49.635896 4, 0xFFFF, sum = 0
2668 09:57:49.638999 5, 0xFFFF, sum = 0
2669 09:57:49.639084 6, 0xFFFF, sum = 0
2670 09:57:49.642871 7, 0xFFFF, sum = 0
2671 09:57:49.645398 8, 0xFFFF, sum = 0
2672 09:57:49.645486 9, 0xFFFF, sum = 0
2673 09:57:49.648906 10, 0xFFFF, sum = 0
2674 09:57:49.648998 11, 0xFFFF, sum = 0
2675 09:57:49.652095 12, 0x0, sum = 1
2676 09:57:49.652224 13, 0x0, sum = 2
2677 09:57:49.655567 14, 0x0, sum = 3
2678 09:57:49.655662 15, 0x0, sum = 4
2679 09:57:49.655729 best_step = 13
2680 09:57:49.655791
2681 09:57:49.658613 ==
2682 09:57:49.661704 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 09:57:49.665623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 09:57:49.665730 ==
2685 09:57:49.665796 RX Vref Scan: 1
2686 09:57:49.665858
2687 09:57:49.668719 Set Vref Range= 32 -> 127
2688 09:57:49.668805
2689 09:57:49.672080 RX Vref 32 -> 127, step: 1
2690 09:57:49.672164
2691 09:57:49.675902 RX Delay -21 -> 252, step: 4
2692 09:57:49.675989
2693 09:57:49.678997 Set Vref, RX VrefLevel [Byte0]: 32
2694 09:57:49.681822 [Byte1]: 32
2695 09:57:49.681908
2696 09:57:49.684925 Set Vref, RX VrefLevel [Byte0]: 33
2697 09:57:49.688336 [Byte1]: 33
2698 09:57:49.692052
2699 09:57:49.695774 Set Vref, RX VrefLevel [Byte0]: 34
2700 09:57:49.698163 [Byte1]: 34
2701 09:57:49.698248
2702 09:57:49.701998 Set Vref, RX VrefLevel [Byte0]: 35
2703 09:57:49.705155 [Byte1]: 35
2704 09:57:49.705240
2705 09:57:49.708417 Set Vref, RX VrefLevel [Byte0]: 36
2706 09:57:49.711834 [Byte1]: 36
2707 09:57:49.716127
2708 09:57:49.716216 Set Vref, RX VrefLevel [Byte0]: 37
2709 09:57:49.718964 [Byte1]: 37
2710 09:57:49.723530
2711 09:57:49.723829 Set Vref, RX VrefLevel [Byte0]: 38
2712 09:57:49.726839 [Byte1]: 38
2713 09:57:49.731572
2714 09:57:49.731664 Set Vref, RX VrefLevel [Byte0]: 39
2715 09:57:49.734896 [Byte1]: 39
2716 09:57:49.739907
2717 09:57:49.739998 Set Vref, RX VrefLevel [Byte0]: 40
2718 09:57:49.742488 [Byte1]: 40
2719 09:57:49.747242
2720 09:57:49.747331 Set Vref, RX VrefLevel [Byte0]: 41
2721 09:57:49.750695 [Byte1]: 41
2722 09:57:49.755317
2723 09:57:49.755413 Set Vref, RX VrefLevel [Byte0]: 42
2724 09:57:49.758714 [Byte1]: 42
2725 09:57:49.763742
2726 09:57:49.763839 Set Vref, RX VrefLevel [Byte0]: 43
2727 09:57:49.766561 [Byte1]: 43
2728 09:57:49.770959
2729 09:57:49.771050 Set Vref, RX VrefLevel [Byte0]: 44
2730 09:57:49.774596 [Byte1]: 44
2731 09:57:49.778970
2732 09:57:49.779072 Set Vref, RX VrefLevel [Byte0]: 45
2733 09:57:49.782333 [Byte1]: 45
2734 09:57:49.786733
2735 09:57:49.786832 Set Vref, RX VrefLevel [Byte0]: 46
2736 09:57:49.793736 [Byte1]: 46
2737 09:57:49.793863
2738 09:57:49.797127 Set Vref, RX VrefLevel [Byte0]: 47
2739 09:57:49.800237 [Byte1]: 47
2740 09:57:49.800322
2741 09:57:49.803378 Set Vref, RX VrefLevel [Byte0]: 48
2742 09:57:49.806469 [Byte1]: 48
2743 09:57:49.810552
2744 09:57:49.810671 Set Vref, RX VrefLevel [Byte0]: 49
2745 09:57:49.813916 [Byte1]: 49
2746 09:57:49.818513
2747 09:57:49.818639 Set Vref, RX VrefLevel [Byte0]: 50
2748 09:57:49.821687 [Byte1]: 50
2749 09:57:49.826566
2750 09:57:49.826668 Set Vref, RX VrefLevel [Byte0]: 51
2751 09:57:49.830024 [Byte1]: 51
2752 09:57:49.834442
2753 09:57:49.834528 Set Vref, RX VrefLevel [Byte0]: 52
2754 09:57:49.837726 [Byte1]: 52
2755 09:57:49.842811
2756 09:57:49.842900 Set Vref, RX VrefLevel [Byte0]: 53
2757 09:57:49.846293 [Byte1]: 53
2758 09:57:49.850448
2759 09:57:49.850533 Set Vref, RX VrefLevel [Byte0]: 54
2760 09:57:49.853658 [Byte1]: 54
2761 09:57:49.858169
2762 09:57:49.858304 Set Vref, RX VrefLevel [Byte0]: 55
2763 09:57:49.861340 [Byte1]: 55
2764 09:57:49.866132
2765 09:57:49.866223 Set Vref, RX VrefLevel [Byte0]: 56
2766 09:57:49.869640 [Byte1]: 56
2767 09:57:49.874176
2768 09:57:49.874332 Set Vref, RX VrefLevel [Byte0]: 57
2769 09:57:49.877833 [Byte1]: 57
2770 09:57:49.882196
2771 09:57:49.882319 Set Vref, RX VrefLevel [Byte0]: 58
2772 09:57:49.885291 [Byte1]: 58
2773 09:57:49.890238
2774 09:57:49.890351 Set Vref, RX VrefLevel [Byte0]: 59
2775 09:57:49.893120 [Byte1]: 59
2776 09:57:49.898169
2777 09:57:49.898288 Set Vref, RX VrefLevel [Byte0]: 60
2778 09:57:49.901130 [Byte1]: 60
2779 09:57:49.906025
2780 09:57:49.906112 Set Vref, RX VrefLevel [Byte0]: 61
2781 09:57:49.908934 [Byte1]: 61
2782 09:57:49.913798
2783 09:57:49.913886 Set Vref, RX VrefLevel [Byte0]: 62
2784 09:57:49.916858 [Byte1]: 62
2785 09:57:49.921606
2786 09:57:49.925044 Set Vref, RX VrefLevel [Byte0]: 63
2787 09:57:49.925147 [Byte1]: 63
2788 09:57:49.930043
2789 09:57:49.930137 Set Vref, RX VrefLevel [Byte0]: 64
2790 09:57:49.933325 [Byte1]: 64
2791 09:57:49.937781
2792 09:57:49.937870 Set Vref, RX VrefLevel [Byte0]: 65
2793 09:57:49.940508 [Byte1]: 65
2794 09:57:49.945396
2795 09:57:49.945481 Set Vref, RX VrefLevel [Byte0]: 66
2796 09:57:49.948954 [Byte1]: 66
2797 09:57:49.953069
2798 09:57:49.953152 Set Vref, RX VrefLevel [Byte0]: 67
2799 09:57:49.956833 [Byte1]: 67
2800 09:57:49.961041
2801 09:57:49.961126 Set Vref, RX VrefLevel [Byte0]: 68
2802 09:57:49.964379 [Byte1]: 68
2803 09:57:49.969121
2804 09:57:49.969209 Set Vref, RX VrefLevel [Byte0]: 69
2805 09:57:49.972365 [Byte1]: 69
2806 09:57:49.977240
2807 09:57:49.977330 Final RX Vref Byte 0 = 57 to rank0
2808 09:57:49.980712 Final RX Vref Byte 1 = 59 to rank0
2809 09:57:49.983825 Final RX Vref Byte 0 = 57 to rank1
2810 09:57:49.987071 Final RX Vref Byte 1 = 59 to rank1==
2811 09:57:49.990434 Dram Type= 6, Freq= 0, CH_0, rank 0
2812 09:57:49.997250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 09:57:49.997345 ==
2814 09:57:49.997411 DQS Delay:
2815 09:57:49.997473 DQS0 = 0, DQS1 = 0
2816 09:57:50.000560 DQM Delay:
2817 09:57:50.000644 DQM0 = 117, DQM1 = 105
2818 09:57:50.004517 DQ Delay:
2819 09:57:50.007587 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2820 09:57:50.010767 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2821 09:57:50.013668 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2822 09:57:50.017200 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2823 09:57:50.017290
2824 09:57:50.017357
2825 09:57:50.023769 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2826 09:57:50.026931 CH0 RK0: MR19=404, MR18=500
2827 09:57:50.033748 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2828 09:57:50.033853
2829 09:57:50.036825 ----->DramcWriteLeveling(PI) begin...
2830 09:57:50.036987 ==
2831 09:57:50.040827 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 09:57:50.043335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 09:57:50.046777 ==
2834 09:57:50.046862 Write leveling (Byte 0): 31 => 31
2835 09:57:50.049986 Write leveling (Byte 1): 25 => 25
2836 09:57:50.053288 DramcWriteLeveling(PI) end<-----
2837 09:57:50.053371
2838 09:57:50.053436 ==
2839 09:57:50.056813 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 09:57:50.063103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 09:57:50.063188 ==
2842 09:57:50.066406 [Gating] SW mode calibration
2843 09:57:50.073213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2844 09:57:50.076575 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2845 09:57:50.082840 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2846 09:57:50.086325 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2847 09:57:50.090187 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 09:57:50.096706 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 09:57:50.099478 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 09:57:50.103022 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 09:57:50.109955 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2852 09:57:50.112968 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2853 09:57:50.116775 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
2854 09:57:50.123158 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 09:57:50.126102 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 09:57:50.129300 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 09:57:50.136036 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 09:57:50.139409 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 09:57:50.142613 1 0 24 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
2860 09:57:50.149731 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2861 09:57:50.152485 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2862 09:57:50.156107 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 09:57:50.162434 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 09:57:50.166139 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 09:57:50.169189 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 09:57:50.175754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 09:57:50.178603 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2868 09:57:50.182412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2869 09:57:50.188527 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2870 09:57:50.192575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 09:57:50.195619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 09:57:50.199360 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 09:57:50.205498 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 09:57:50.208828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 09:57:50.212110 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 09:57:50.219218 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 09:57:50.222204 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:57:50.225439 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:57:50.233033 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:57:50.236354 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 09:57:50.238565 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 09:57:50.246806 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 09:57:50.249090 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2884 09:57:50.252017 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2885 09:57:50.258902 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2886 09:57:50.258994 Total UI for P1: 0, mck2ui 16
2887 09:57:50.265304 best dqsien dly found for B0: ( 1, 3, 26)
2888 09:57:50.268958 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 09:57:50.272159 Total UI for P1: 0, mck2ui 16
2890 09:57:50.275407 best dqsien dly found for B1: ( 1, 4, 0)
2891 09:57:50.278301 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2892 09:57:50.282556 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2893 09:57:50.282645
2894 09:57:50.285219 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2895 09:57:50.288426 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2896 09:57:50.292315 [Gating] SW calibration Done
2897 09:57:50.292399 ==
2898 09:57:50.295142 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 09:57:50.298850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 09:57:50.298935 ==
2901 09:57:50.301933 RX Vref Scan: 0
2902 09:57:50.302014
2903 09:57:50.305192 RX Vref 0 -> 0, step: 1
2904 09:57:50.305274
2905 09:57:50.305337 RX Delay -40 -> 252, step: 8
2906 09:57:50.312268 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2907 09:57:50.315884 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2908 09:57:50.318812 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2909 09:57:50.322188 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2910 09:57:50.324905 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2911 09:57:50.331581 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2912 09:57:50.335328 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2913 09:57:50.338508 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2914 09:57:50.341822 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2915 09:57:50.345014 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2916 09:57:50.351900 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2917 09:57:50.354793 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2918 09:57:50.358494 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2919 09:57:50.361634 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2920 09:57:50.364815 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2921 09:57:50.371252 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2922 09:57:50.371348 ==
2923 09:57:50.374687 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 09:57:50.378867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 09:57:50.378955 ==
2926 09:57:50.379021 DQS Delay:
2927 09:57:50.381435 DQS0 = 0, DQS1 = 0
2928 09:57:50.381531 DQM Delay:
2929 09:57:50.384607 DQM0 = 117, DQM1 = 109
2930 09:57:50.384690 DQ Delay:
2931 09:57:50.388444 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2932 09:57:50.391108 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2933 09:57:50.394652 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2934 09:57:50.398227 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2935 09:57:50.398364
2936 09:57:50.401534
2937 09:57:50.401615 ==
2938 09:57:50.404515 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 09:57:50.407646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 09:57:50.407729 ==
2941 09:57:50.407794
2942 09:57:50.407854
2943 09:57:50.411139 TX Vref Scan disable
2944 09:57:50.411220 == TX Byte 0 ==
2945 09:57:50.417575 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2946 09:57:50.420807 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2947 09:57:50.420890 == TX Byte 1 ==
2948 09:57:50.427595 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2949 09:57:50.431264 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2950 09:57:50.431355 ==
2951 09:57:50.435188 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 09:57:50.438084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 09:57:50.438191 ==
2954 09:57:50.450540 TX Vref=22, minBit 10, minWin=25, winSum=418
2955 09:57:50.454160 TX Vref=24, minBit 13, minWin=25, winSum=423
2956 09:57:50.457179 TX Vref=26, minBit 1, minWin=26, winSum=428
2957 09:57:50.460658 TX Vref=28, minBit 10, minWin=25, winSum=434
2958 09:57:50.464462 TX Vref=30, minBit 2, minWin=26, winSum=429
2959 09:57:50.470633 TX Vref=32, minBit 8, minWin=26, winSum=432
2960 09:57:50.473844 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 32
2961 09:57:50.473932
2962 09:57:50.476945 Final TX Range 1 Vref 32
2963 09:57:50.477029
2964 09:57:50.477093 ==
2965 09:57:50.480258 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 09:57:50.487505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 09:57:50.487601 ==
2968 09:57:50.487716
2969 09:57:50.487776
2970 09:57:50.487833 TX Vref Scan disable
2971 09:57:50.490755 == TX Byte 0 ==
2972 09:57:50.494499 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2973 09:57:50.500538 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2974 09:57:50.500634 == TX Byte 1 ==
2975 09:57:50.504095 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2976 09:57:50.510648 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2977 09:57:50.510739
2978 09:57:50.510804 [DATLAT]
2979 09:57:50.510864 Freq=1200, CH0 RK1
2980 09:57:50.510924
2981 09:57:50.514005 DATLAT Default: 0xd
2982 09:57:50.514086 0, 0xFFFF, sum = 0
2983 09:57:50.518017 1, 0xFFFF, sum = 0
2984 09:57:50.520905 2, 0xFFFF, sum = 0
2985 09:57:50.520989 3, 0xFFFF, sum = 0
2986 09:57:50.524230 4, 0xFFFF, sum = 0
2987 09:57:50.524314 5, 0xFFFF, sum = 0
2988 09:57:50.527058 6, 0xFFFF, sum = 0
2989 09:57:50.527158 7, 0xFFFF, sum = 0
2990 09:57:50.530554 8, 0xFFFF, sum = 0
2991 09:57:50.530637 9, 0xFFFF, sum = 0
2992 09:57:50.533967 10, 0xFFFF, sum = 0
2993 09:57:50.534051 11, 0xFFFF, sum = 0
2994 09:57:50.537277 12, 0x0, sum = 1
2995 09:57:50.537360 13, 0x0, sum = 2
2996 09:57:50.540350 14, 0x0, sum = 3
2997 09:57:50.540432 15, 0x0, sum = 4
2998 09:57:50.543759 best_step = 13
2999 09:57:50.543840
3000 09:57:50.543903 ==
3001 09:57:50.546916 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 09:57:50.550419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 09:57:50.550502 ==
3004 09:57:50.550568 RX Vref Scan: 0
3005 09:57:50.553604
3006 09:57:50.553686 RX Vref 0 -> 0, step: 1
3007 09:57:50.553750
3008 09:57:50.556821 RX Delay -21 -> 252, step: 4
3009 09:57:50.560249 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3010 09:57:50.567672 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3011 09:57:50.570673 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3012 09:57:50.573688 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3013 09:57:50.577005 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3014 09:57:50.580111 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3015 09:57:50.586690 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3016 09:57:50.590032 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3017 09:57:50.593890 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3018 09:57:50.597062 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3019 09:57:50.600186 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3020 09:57:50.606851 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3021 09:57:50.609888 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3022 09:57:50.613169 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3023 09:57:50.616404 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3024 09:57:50.623652 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3025 09:57:50.623742 ==
3026 09:57:50.626462 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 09:57:50.629933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 09:57:50.630072 ==
3029 09:57:50.630177 DQS Delay:
3030 09:57:50.633692 DQS0 = 0, DQS1 = 0
3031 09:57:50.633774 DQM Delay:
3032 09:57:50.636664 DQM0 = 116, DQM1 = 106
3033 09:57:50.636746 DQ Delay:
3034 09:57:50.640237 DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =114
3035 09:57:50.643063 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =120
3036 09:57:50.646391 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3037 09:57:50.649904 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3038 09:57:50.650018
3039 09:57:50.650109
3040 09:57:50.659883 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3041 09:57:50.662785 CH0 RK1: MR19=403, MR18=FD
3042 09:57:50.666348 CH0_RK1: MR19=0x403, MR18=0xFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3043 09:57:50.670292 [RxdqsGatingPostProcess] freq 1200
3044 09:57:50.676277 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3045 09:57:50.679639 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 09:57:50.683020 best DQS1 dly(2T, 0.5T) = (0, 12)
3047 09:57:50.686157 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 09:57:50.689343 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3049 09:57:50.693063 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 09:57:50.695975 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 09:57:50.699786 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 09:57:50.699873 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 09:57:50.703175 Pre-setting of DQS Precalculation
3054 09:57:50.709244 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3055 09:57:50.709337 ==
3056 09:57:50.713157 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 09:57:50.716014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 09:57:50.716099 ==
3059 09:57:50.723007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3060 09:57:50.730581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3061 09:57:50.736304 [CA 0] Center 38 (8~68) winsize 61
3062 09:57:50.740219 [CA 1] Center 37 (7~68) winsize 62
3063 09:57:50.743046 [CA 2] Center 35 (5~65) winsize 61
3064 09:57:50.746895 [CA 3] Center 34 (4~64) winsize 61
3065 09:57:50.749591 [CA 4] Center 34 (4~65) winsize 62
3066 09:57:50.753615 [CA 5] Center 34 (4~64) winsize 61
3067 09:57:50.753704
3068 09:57:50.756361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3069 09:57:50.756442
3070 09:57:50.759380 [CATrainingPosCal] consider 1 rank data
3071 09:57:50.763396 u2DelayCellTimex100 = 270/100 ps
3072 09:57:50.766222 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3073 09:57:50.773659 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3074 09:57:50.776858 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3075 09:57:50.779423 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3076 09:57:50.782609 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3077 09:57:50.786208 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3078 09:57:50.786345
3079 09:57:50.789643 CA PerBit enable=1, Macro0, CA PI delay=34
3080 09:57:50.789725
3081 09:57:50.792455 [CBTSetCACLKResult] CA Dly = 34
3082 09:57:50.795816 CS Dly: 5 (0~36)
3083 09:57:50.795899 ==
3084 09:57:50.799307 Dram Type= 6, Freq= 0, CH_1, rank 1
3085 09:57:50.802991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 09:57:50.803074 ==
3087 09:57:50.809251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 09:57:50.812598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3089 09:57:50.822133 [CA 0] Center 37 (7~68) winsize 62
3090 09:57:50.825519 [CA 1] Center 38 (8~68) winsize 61
3091 09:57:50.828901 [CA 2] Center 34 (4~65) winsize 62
3092 09:57:50.832004 [CA 3] Center 33 (3~64) winsize 62
3093 09:57:50.835599 [CA 4] Center 34 (4~64) winsize 61
3094 09:57:50.838802 [CA 5] Center 33 (3~63) winsize 61
3095 09:57:50.838891
3096 09:57:50.842856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 09:57:50.842946
3098 09:57:50.845572 [CATrainingPosCal] consider 2 rank data
3099 09:57:50.848583 u2DelayCellTimex100 = 270/100 ps
3100 09:57:50.852347 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3101 09:57:50.855156 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3102 09:57:50.862613 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3103 09:57:50.865025 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 09:57:50.868740 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 09:57:50.871964 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3106 09:57:50.872076
3107 09:57:50.875367 CA PerBit enable=1, Macro0, CA PI delay=33
3108 09:57:50.875450
3109 09:57:50.878540 [CBTSetCACLKResult] CA Dly = 33
3110 09:57:50.878623 CS Dly: 6 (0~39)
3111 09:57:50.878689
3112 09:57:50.882226 ----->DramcWriteLeveling(PI) begin...
3113 09:57:50.885525 ==
3114 09:57:50.888575 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 09:57:50.891613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 09:57:50.891722 ==
3117 09:57:50.895517 Write leveling (Byte 0): 26 => 26
3118 09:57:50.898375 Write leveling (Byte 1): 27 => 27
3119 09:57:50.901888 DramcWriteLeveling(PI) end<-----
3120 09:57:50.901972
3121 09:57:50.902035 ==
3122 09:57:50.905784 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 09:57:50.908522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 09:57:50.908606 ==
3125 09:57:50.912045 [Gating] SW mode calibration
3126 09:57:50.918229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3127 09:57:50.924851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3128 09:57:50.928426 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3129 09:57:50.931762 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 09:57:50.938560 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 09:57:50.941366 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 09:57:50.944370 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 09:57:50.951417 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 09:57:50.954450 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3135 09:57:50.957802 0 15 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
3136 09:57:50.964976 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 09:57:50.967794 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 09:57:50.971534 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 09:57:50.978139 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 09:57:50.981201 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 09:57:50.984323 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 09:57:50.991021 1 0 24 | B1->B0 | 2525 3535 | 1 0 | (0 0) (0 0)
3143 09:57:50.994228 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3144 09:57:50.999041 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3145 09:57:51.004941 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 09:57:51.007488 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 09:57:51.010769 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 09:57:51.014169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 09:57:51.020849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 09:57:51.024373 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 09:57:51.027653 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3152 09:57:51.034149 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 09:57:51.037599 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 09:57:51.040872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 09:57:51.047289 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 09:57:51.050780 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 09:57:51.054057 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 09:57:51.060493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 09:57:51.063985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 09:57:51.067265 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:57:51.074142 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 09:57:51.077860 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 09:57:51.080374 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 09:57:51.087396 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 09:57:51.090304 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 09:57:51.094096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 09:57:51.100852 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3168 09:57:51.103919 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 09:57:51.107175 Total UI for P1: 0, mck2ui 16
3170 09:57:51.110673 best dqsien dly found for B0: ( 1, 3, 26)
3171 09:57:51.113945 Total UI for P1: 0, mck2ui 16
3172 09:57:51.117240 best dqsien dly found for B1: ( 1, 3, 26)
3173 09:57:51.120320 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3174 09:57:51.123707 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3175 09:57:51.123795
3176 09:57:51.127377 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3177 09:57:51.130735 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3178 09:57:51.133849 [Gating] SW calibration Done
3179 09:57:51.133933 ==
3180 09:57:51.137593 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 09:57:51.140392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 09:57:51.140491 ==
3183 09:57:51.143785 RX Vref Scan: 0
3184 09:57:51.143867
3185 09:57:51.147074 RX Vref 0 -> 0, step: 1
3186 09:57:51.147156
3187 09:57:51.147221 RX Delay -40 -> 252, step: 8
3188 09:57:51.153922 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3189 09:57:51.157087 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3190 09:57:51.160884 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3191 09:57:51.164322 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3192 09:57:51.167352 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3193 09:57:51.173737 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3194 09:57:51.176961 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3195 09:57:51.180441 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3196 09:57:51.183879 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3197 09:57:51.186835 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3198 09:57:51.193936 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3199 09:57:51.197002 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3200 09:57:51.200318 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3201 09:57:51.203399 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3202 09:57:51.210011 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3203 09:57:51.213403 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3204 09:57:51.213494 ==
3205 09:57:51.216597 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 09:57:51.220303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 09:57:51.220389 ==
3208 09:57:51.220454 DQS Delay:
3209 09:57:51.223779 DQS0 = 0, DQS1 = 0
3210 09:57:51.223861 DQM Delay:
3211 09:57:51.226793 DQM0 = 115, DQM1 = 113
3212 09:57:51.226953 DQ Delay:
3213 09:57:51.230463 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3214 09:57:51.233315 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3215 09:57:51.236886 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3216 09:57:51.243177 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3217 09:57:51.243269
3218 09:57:51.243335
3219 09:57:51.243395 ==
3220 09:57:51.246591 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 09:57:51.250041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 09:57:51.250123 ==
3223 09:57:51.250188
3224 09:57:51.250247
3225 09:57:51.253253 TX Vref Scan disable
3226 09:57:51.253334 == TX Byte 0 ==
3227 09:57:51.259958 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3228 09:57:51.263403 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3229 09:57:51.263494 == TX Byte 1 ==
3230 09:57:51.269858 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3231 09:57:51.273003 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3232 09:57:51.273088 ==
3233 09:57:51.276200 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 09:57:51.279796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 09:57:51.279895 ==
3236 09:57:51.292618 TX Vref=22, minBit 8, minWin=24, winSum=409
3237 09:57:51.296145 TX Vref=24, minBit 9, minWin=24, winSum=416
3238 09:57:51.299077 TX Vref=26, minBit 8, minWin=25, winSum=423
3239 09:57:51.302178 TX Vref=28, minBit 9, minWin=25, winSum=428
3240 09:57:51.305186 TX Vref=30, minBit 9, minWin=25, winSum=427
3241 09:57:51.312074 TX Vref=32, minBit 9, minWin=25, winSum=423
3242 09:57:51.315329 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 28
3243 09:57:51.315415
3244 09:57:51.319173 Final TX Range 1 Vref 28
3245 09:57:51.319256
3246 09:57:51.319320 ==
3247 09:57:51.322115 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 09:57:51.325454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 09:57:51.325535 ==
3250 09:57:51.328672
3251 09:57:51.328757
3252 09:57:51.328822 TX Vref Scan disable
3253 09:57:51.332056 == TX Byte 0 ==
3254 09:57:51.335577 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3255 09:57:51.338811 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3256 09:57:51.342145 == TX Byte 1 ==
3257 09:57:51.345528 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3258 09:57:51.351900 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3259 09:57:51.352009
3260 09:57:51.352073 [DATLAT]
3261 09:57:51.352133 Freq=1200, CH1 RK0
3262 09:57:51.352191
3263 09:57:51.355430 DATLAT Default: 0xd
3264 09:57:51.355512 0, 0xFFFF, sum = 0
3265 09:57:51.358605 1, 0xFFFF, sum = 0
3266 09:57:51.358689 2, 0xFFFF, sum = 0
3267 09:57:51.361831 3, 0xFFFF, sum = 0
3268 09:57:51.365773 4, 0xFFFF, sum = 0
3269 09:57:51.365858 5, 0xFFFF, sum = 0
3270 09:57:51.368621 6, 0xFFFF, sum = 0
3271 09:57:51.368704 7, 0xFFFF, sum = 0
3272 09:57:51.371670 8, 0xFFFF, sum = 0
3273 09:57:51.371754 9, 0xFFFF, sum = 0
3274 09:57:51.375441 10, 0xFFFF, sum = 0
3275 09:57:51.375526 11, 0xFFFF, sum = 0
3276 09:57:51.378543 12, 0x0, sum = 1
3277 09:57:51.378627 13, 0x0, sum = 2
3278 09:57:51.381654 14, 0x0, sum = 3
3279 09:57:51.381737 15, 0x0, sum = 4
3280 09:57:51.381803 best_step = 13
3281 09:57:51.385126
3282 09:57:51.385207 ==
3283 09:57:51.388858 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 09:57:51.391900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 09:57:51.391984 ==
3286 09:57:51.392048 RX Vref Scan: 1
3287 09:57:51.392108
3288 09:57:51.394861 Set Vref Range= 32 -> 127
3289 09:57:51.394941
3290 09:57:51.398245 RX Vref 32 -> 127, step: 1
3291 09:57:51.398365
3292 09:57:51.401661 RX Delay -13 -> 252, step: 4
3293 09:57:51.401742
3294 09:57:51.405166 Set Vref, RX VrefLevel [Byte0]: 32
3295 09:57:51.408259 [Byte1]: 32
3296 09:57:51.408341
3297 09:57:51.411749 Set Vref, RX VrefLevel [Byte0]: 33
3298 09:57:51.414762 [Byte1]: 33
3299 09:57:51.418234
3300 09:57:51.418331 Set Vref, RX VrefLevel [Byte0]: 34
3301 09:57:51.421549 [Byte1]: 34
3302 09:57:51.426184
3303 09:57:51.426292 Set Vref, RX VrefLevel [Byte0]: 35
3304 09:57:51.429963 [Byte1]: 35
3305 09:57:51.434038
3306 09:57:51.434125 Set Vref, RX VrefLevel [Byte0]: 36
3307 09:57:51.437449 [Byte1]: 36
3308 09:57:51.441788
3309 09:57:51.441879 Set Vref, RX VrefLevel [Byte0]: 37
3310 09:57:51.445276 [Byte1]: 37
3311 09:57:51.449839
3312 09:57:51.449926 Set Vref, RX VrefLevel [Byte0]: 38
3313 09:57:51.453293 [Byte1]: 38
3314 09:57:51.457958
3315 09:57:51.458041 Set Vref, RX VrefLevel [Byte0]: 39
3316 09:57:51.460898 [Byte1]: 39
3317 09:57:51.466007
3318 09:57:51.466120 Set Vref, RX VrefLevel [Byte0]: 40
3319 09:57:51.469513 [Byte1]: 40
3320 09:57:51.473814
3321 09:57:51.473902 Set Vref, RX VrefLevel [Byte0]: 41
3322 09:57:51.476955 [Byte1]: 41
3323 09:57:51.481180
3324 09:57:51.481326 Set Vref, RX VrefLevel [Byte0]: 42
3325 09:57:51.484599 [Byte1]: 42
3326 09:57:51.488982
3327 09:57:51.489068 Set Vref, RX VrefLevel [Byte0]: 43
3328 09:57:51.493102 [Byte1]: 43
3329 09:57:51.497677
3330 09:57:51.497763 Set Vref, RX VrefLevel [Byte0]: 44
3331 09:57:51.500454 [Byte1]: 44
3332 09:57:51.505106
3333 09:57:51.505192 Set Vref, RX VrefLevel [Byte0]: 45
3334 09:57:51.508358 [Byte1]: 45
3335 09:57:51.512793
3336 09:57:51.512874 Set Vref, RX VrefLevel [Byte0]: 46
3337 09:57:51.516173 [Byte1]: 46
3338 09:57:51.520736
3339 09:57:51.520818 Set Vref, RX VrefLevel [Byte0]: 47
3340 09:57:51.524222 [Byte1]: 47
3341 09:57:51.528662
3342 09:57:51.528753 Set Vref, RX VrefLevel [Byte0]: 48
3343 09:57:51.532458 [Byte1]: 48
3344 09:57:51.537232
3345 09:57:51.537315 Set Vref, RX VrefLevel [Byte0]: 49
3346 09:57:51.539724 [Byte1]: 49
3347 09:57:51.544256
3348 09:57:51.544338 Set Vref, RX VrefLevel [Byte0]: 50
3349 09:57:51.547837 [Byte1]: 50
3350 09:57:51.552570
3351 09:57:51.552654 Set Vref, RX VrefLevel [Byte0]: 51
3352 09:57:51.555614 [Byte1]: 51
3353 09:57:51.560138
3354 09:57:51.560224 Set Vref, RX VrefLevel [Byte0]: 52
3355 09:57:51.563828 [Byte1]: 52
3356 09:57:51.568265
3357 09:57:51.568353 Set Vref, RX VrefLevel [Byte0]: 53
3358 09:57:51.571916 [Byte1]: 53
3359 09:57:51.577197
3360 09:57:51.577328 Set Vref, RX VrefLevel [Byte0]: 54
3361 09:57:51.579252 [Byte1]: 54
3362 09:57:51.583919
3363 09:57:51.584007 Set Vref, RX VrefLevel [Byte0]: 55
3364 09:57:51.587396 [Byte1]: 55
3365 09:57:51.591674
3366 09:57:51.591761 Set Vref, RX VrefLevel [Byte0]: 56
3367 09:57:51.595251 [Byte1]: 56
3368 09:57:51.599699
3369 09:57:51.599791 Set Vref, RX VrefLevel [Byte0]: 57
3370 09:57:51.602593 [Byte1]: 57
3371 09:57:51.607796
3372 09:57:51.607885 Set Vref, RX VrefLevel [Byte0]: 58
3373 09:57:51.610766 [Byte1]: 58
3374 09:57:51.615375
3375 09:57:51.615460 Set Vref, RX VrefLevel [Byte0]: 59
3376 09:57:51.618431 [Byte1]: 59
3377 09:57:51.623270
3378 09:57:51.623359 Set Vref, RX VrefLevel [Byte0]: 60
3379 09:57:51.626590 [Byte1]: 60
3380 09:57:51.631015
3381 09:57:51.631111 Set Vref, RX VrefLevel [Byte0]: 61
3382 09:57:51.634707 [Byte1]: 61
3383 09:57:51.638938
3384 09:57:51.639024 Set Vref, RX VrefLevel [Byte0]: 62
3385 09:57:51.642096 [Byte1]: 62
3386 09:57:51.646976
3387 09:57:51.647063 Set Vref, RX VrefLevel [Byte0]: 63
3388 09:57:51.650543 [Byte1]: 63
3389 09:57:51.654848
3390 09:57:51.654932 Set Vref, RX VrefLevel [Byte0]: 64
3391 09:57:51.658216 [Byte1]: 64
3392 09:57:51.662363
3393 09:57:51.662450 Set Vref, RX VrefLevel [Byte0]: 65
3394 09:57:51.666488 [Byte1]: 65
3395 09:57:51.670446
3396 09:57:51.670536 Final RX Vref Byte 0 = 51 to rank0
3397 09:57:51.674083 Final RX Vref Byte 1 = 52 to rank0
3398 09:57:51.677035 Final RX Vref Byte 0 = 51 to rank1
3399 09:57:51.680703 Final RX Vref Byte 1 = 52 to rank1==
3400 09:57:51.683633 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 09:57:51.691377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 09:57:51.691474 ==
3403 09:57:51.691552 DQS Delay:
3404 09:57:51.691615 DQS0 = 0, DQS1 = 0
3405 09:57:51.693709 DQM Delay:
3406 09:57:51.693791 DQM0 = 114, DQM1 = 113
3407 09:57:51.698554 DQ Delay:
3408 09:57:51.700255 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3409 09:57:51.703671 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3410 09:57:51.707044 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3411 09:57:51.710214 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3412 09:57:51.710323
3413 09:57:51.710389
3414 09:57:51.719914 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3415 09:57:51.720013 CH1 RK0: MR19=303, MR18=F0FD
3416 09:57:51.726982 CH1_RK0: MR19=0x303, MR18=0xF0FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3417 09:57:51.727073
3418 09:57:51.730543 ----->DramcWriteLeveling(PI) begin...
3419 09:57:51.730636 ==
3420 09:57:51.733883 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 09:57:51.739902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 09:57:51.739992 ==
3423 09:57:51.743474 Write leveling (Byte 0): 27 => 27
3424 09:57:51.743558 Write leveling (Byte 1): 28 => 28
3425 09:57:51.746773 DramcWriteLeveling(PI) end<-----
3426 09:57:51.746854
3427 09:57:51.750569 ==
3428 09:57:51.750651 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 09:57:51.756918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 09:57:51.757003 ==
3431 09:57:51.760047 [Gating] SW mode calibration
3432 09:57:51.766582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 09:57:51.770047 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 09:57:51.776482 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3435 09:57:51.780328 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 09:57:51.783191 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 09:57:51.789945 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 09:57:51.792953 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 09:57:51.797163 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3440 09:57:51.802692 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
3441 09:57:51.805957 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
3442 09:57:51.809370 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 09:57:51.816141 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 09:57:51.819062 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 09:57:51.822822 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 09:57:51.829371 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 09:57:51.832599 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3448 09:57:51.835984 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3449 09:57:51.842927 1 0 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3450 09:57:51.846701 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 09:57:51.849413 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 09:57:51.855881 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 09:57:51.859140 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 09:57:51.861988 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 09:57:51.868929 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 09:57:51.871803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3457 09:57:51.875239 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3458 09:57:51.881563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3459 09:57:51.885636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 09:57:51.888689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 09:57:51.895172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 09:57:51.898219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 09:57:51.901521 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 09:57:51.908247 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 09:57:51.911814 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 09:57:51.914955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 09:57:51.921460 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 09:57:51.925062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 09:57:51.928571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 09:57:51.934530 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 09:57:51.937658 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 09:57:51.941263 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 09:57:51.948224 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3474 09:57:51.951314 Total UI for P1: 0, mck2ui 16
3475 09:57:51.954049 best dqsien dly found for B0: ( 1, 3, 24)
3476 09:57:51.957647 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 09:57:51.961110 Total UI for P1: 0, mck2ui 16
3478 09:57:51.964235 best dqsien dly found for B1: ( 1, 3, 26)
3479 09:57:51.967513 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3480 09:57:51.970512 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3481 09:57:51.970591
3482 09:57:51.974166 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3483 09:57:51.980758 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3484 09:57:51.980851 [Gating] SW calibration Done
3485 09:57:51.980917 ==
3486 09:57:51.983855 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 09:57:51.990723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 09:57:51.990810 ==
3489 09:57:51.990875 RX Vref Scan: 0
3490 09:57:51.990935
3491 09:57:51.993483 RX Vref 0 -> 0, step: 1
3492 09:57:51.993563
3493 09:57:51.996884 RX Delay -40 -> 252, step: 8
3494 09:57:52.000489 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3495 09:57:52.003332 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3496 09:57:52.006763 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3497 09:57:52.013047 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3498 09:57:52.016446 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3499 09:57:52.019924 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3500 09:57:52.023343 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3501 09:57:52.026667 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3502 09:57:52.033535 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3503 09:57:52.036706 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3504 09:57:52.039417 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3505 09:57:52.042885 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3506 09:57:52.049352 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3507 09:57:52.052876 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3508 09:57:52.056065 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3509 09:57:52.059006 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3510 09:57:52.059088 ==
3511 09:57:52.062726 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 09:57:52.068896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 09:57:52.068980 ==
3514 09:57:52.069045 DQS Delay:
3515 09:57:52.072721 DQS0 = 0, DQS1 = 0
3516 09:57:52.072803 DQM Delay:
3517 09:57:52.075669 DQM0 = 114, DQM1 = 111
3518 09:57:52.075751 DQ Delay:
3519 09:57:52.079034 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3520 09:57:52.082417 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3521 09:57:52.085325 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3522 09:57:52.088966 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3523 09:57:52.089048
3524 09:57:52.089122
3525 09:57:52.089242 ==
3526 09:57:52.092119 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 09:57:52.098291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 09:57:52.098392 ==
3529 09:57:52.098466
3530 09:57:52.098529
3531 09:57:52.098607 TX Vref Scan disable
3532 09:57:52.102287 == TX Byte 0 ==
3533 09:57:52.105472 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 09:57:52.111877 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 09:57:52.111986 == TX Byte 1 ==
3536 09:57:52.115176 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 09:57:52.121573 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 09:57:52.121658 ==
3539 09:57:52.124938 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 09:57:52.128270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 09:57:52.128368 ==
3542 09:57:52.139368 TX Vref=22, minBit 0, minWin=25, winSum=416
3543 09:57:52.143092 TX Vref=24, minBit 9, minWin=25, winSum=422
3544 09:57:52.146218 TX Vref=26, minBit 9, minWin=25, winSum=427
3545 09:57:52.149349 TX Vref=28, minBit 1, minWin=26, winSum=428
3546 09:57:52.152767 TX Vref=30, minBit 9, minWin=25, winSum=429
3547 09:57:52.159173 TX Vref=32, minBit 1, minWin=26, winSum=429
3548 09:57:52.162691 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 32
3549 09:57:52.162775
3550 09:57:52.166297 Final TX Range 1 Vref 32
3551 09:57:52.166416
3552 09:57:52.166483 ==
3553 09:57:52.169244 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 09:57:52.172509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 09:57:52.176160 ==
3556 09:57:52.176250
3557 09:57:52.176316
3558 09:57:52.176376 TX Vref Scan disable
3559 09:57:52.179162 == TX Byte 0 ==
3560 09:57:52.182953 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 09:57:52.189381 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 09:57:52.189476 == TX Byte 1 ==
3563 09:57:52.192547 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 09:57:52.198740 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 09:57:52.198846
3566 09:57:52.198911 [DATLAT]
3567 09:57:52.198971 Freq=1200, CH1 RK1
3568 09:57:52.199029
3569 09:57:52.202495 DATLAT Default: 0xd
3570 09:57:52.205949 0, 0xFFFF, sum = 0
3571 09:57:52.206032 1, 0xFFFF, sum = 0
3572 09:57:52.208880 2, 0xFFFF, sum = 0
3573 09:57:52.208968 3, 0xFFFF, sum = 0
3574 09:57:52.212457 4, 0xFFFF, sum = 0
3575 09:57:52.212532 5, 0xFFFF, sum = 0
3576 09:57:52.215803 6, 0xFFFF, sum = 0
3577 09:57:52.215876 7, 0xFFFF, sum = 0
3578 09:57:52.219003 8, 0xFFFF, sum = 0
3579 09:57:52.219077 9, 0xFFFF, sum = 0
3580 09:57:52.222175 10, 0xFFFF, sum = 0
3581 09:57:52.222246 11, 0xFFFF, sum = 0
3582 09:57:52.225518 12, 0x0, sum = 1
3583 09:57:52.225589 13, 0x0, sum = 2
3584 09:57:52.228737 14, 0x0, sum = 3
3585 09:57:52.228808 15, 0x0, sum = 4
3586 09:57:52.231906 best_step = 13
3587 09:57:52.231991
3588 09:57:52.232056 ==
3589 09:57:52.235254 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 09:57:52.238922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 09:57:52.239004 ==
3592 09:57:52.241579 RX Vref Scan: 0
3593 09:57:52.241673
3594 09:57:52.241749 RX Vref 0 -> 0, step: 1
3595 09:57:52.241809
3596 09:57:52.245152 RX Delay -13 -> 252, step: 4
3597 09:57:52.251905 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3598 09:57:52.254973 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3599 09:57:52.258620 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3600 09:57:52.262166 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3601 09:57:52.264824 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3602 09:57:52.271687 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3603 09:57:52.274737 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3604 09:57:52.278147 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3605 09:57:52.281819 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3606 09:57:52.285312 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3607 09:57:52.291195 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3608 09:57:52.294782 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3609 09:57:52.297740 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3610 09:57:52.300999 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3611 09:57:52.307869 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3612 09:57:52.311503 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3613 09:57:52.311678 ==
3614 09:57:52.314739 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 09:57:52.317426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 09:57:52.317605 ==
3617 09:57:52.320944 DQS Delay:
3618 09:57:52.321096 DQS0 = 0, DQS1 = 0
3619 09:57:52.321168 DQM Delay:
3620 09:57:52.324465 DQM0 = 115, DQM1 = 112
3621 09:57:52.324601 DQ Delay:
3622 09:57:52.327787 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3623 09:57:52.330935 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3624 09:57:52.337418 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3625 09:57:52.340855 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3626 09:57:52.340974
3627 09:57:52.341043
3628 09:57:52.347325 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3629 09:57:52.351173 CH1 RK1: MR19=304, MR18=F608
3630 09:57:52.357055 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3631 09:57:52.360207 [RxdqsGatingPostProcess] freq 1200
3632 09:57:52.367057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 09:57:52.367197 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 09:57:52.371191 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 09:57:52.373843 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 09:57:52.376891 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 09:57:52.380684 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 09:57:52.383880 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 09:57:52.387097 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 09:57:52.390126 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 09:57:52.393746 Pre-setting of DQS Precalculation
3642 09:57:52.400311 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 09:57:52.406682 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 09:57:52.413218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 09:57:52.413351
3646 09:57:52.413434
3647 09:57:52.416647 [Calibration Summary] 2400 Mbps
3648 09:57:52.416733 CH 0, Rank 0
3649 09:57:52.419500 SW Impedance : PASS
3650 09:57:52.423060 DUTY Scan : NO K
3651 09:57:52.423210 ZQ Calibration : PASS
3652 09:57:52.426555 Jitter Meter : NO K
3653 09:57:52.429285 CBT Training : PASS
3654 09:57:52.429403 Write leveling : PASS
3655 09:57:52.432969 RX DQS gating : PASS
3656 09:57:52.436086 RX DQ/DQS(RDDQC) : PASS
3657 09:57:52.436199 TX DQ/DQS : PASS
3658 09:57:52.439802 RX DATLAT : PASS
3659 09:57:52.442795 RX DQ/DQS(Engine): PASS
3660 09:57:52.442933 TX OE : NO K
3661 09:57:52.446266 All Pass.
3662 09:57:52.446381
3663 09:57:52.446475 CH 0, Rank 1
3664 09:57:52.449053 SW Impedance : PASS
3665 09:57:52.449165 DUTY Scan : NO K
3666 09:57:52.452370 ZQ Calibration : PASS
3667 09:57:52.456710 Jitter Meter : NO K
3668 09:57:52.456823 CBT Training : PASS
3669 09:57:52.458706 Write leveling : PASS
3670 09:57:52.462100 RX DQS gating : PASS
3671 09:57:52.462245 RX DQ/DQS(RDDQC) : PASS
3672 09:57:52.465316 TX DQ/DQS : PASS
3673 09:57:52.465427 RX DATLAT : PASS
3674 09:57:52.469321 RX DQ/DQS(Engine): PASS
3675 09:57:52.472114 TX OE : NO K
3676 09:57:52.472225 All Pass.
3677 09:57:52.472320
3678 09:57:52.472414 CH 1, Rank 0
3679 09:57:52.475387 SW Impedance : PASS
3680 09:57:52.478791 DUTY Scan : NO K
3681 09:57:52.478927 ZQ Calibration : PASS
3682 09:57:52.481804 Jitter Meter : NO K
3683 09:57:52.485299 CBT Training : PASS
3684 09:57:52.485410 Write leveling : PASS
3685 09:57:52.488520 RX DQS gating : PASS
3686 09:57:52.491635 RX DQ/DQS(RDDQC) : PASS
3687 09:57:52.491775 TX DQ/DQS : PASS
3688 09:57:52.495310 RX DATLAT : PASS
3689 09:57:52.498550 RX DQ/DQS(Engine): PASS
3690 09:57:52.498702 TX OE : NO K
3691 09:57:52.501753 All Pass.
3692 09:57:52.501866
3693 09:57:52.501963 CH 1, Rank 1
3694 09:57:52.505504 SW Impedance : PASS
3695 09:57:52.505639 DUTY Scan : NO K
3696 09:57:52.508342 ZQ Calibration : PASS
3697 09:57:52.511966 Jitter Meter : NO K
3698 09:57:52.512105 CBT Training : PASS
3699 09:57:52.515252 Write leveling : PASS
3700 09:57:52.518525 RX DQS gating : PASS
3701 09:57:52.518616 RX DQ/DQS(RDDQC) : PASS
3702 09:57:52.521674 TX DQ/DQS : PASS
3703 09:57:52.524888 RX DATLAT : PASS
3704 09:57:52.524997 RX DQ/DQS(Engine): PASS
3705 09:57:52.528632 TX OE : NO K
3706 09:57:52.528735 All Pass.
3707 09:57:52.528816
3708 09:57:52.531828 DramC Write-DBI off
3709 09:57:52.535100 PER_BANK_REFRESH: Hybrid Mode
3710 09:57:52.535207 TX_TRACKING: ON
3711 09:57:52.544347 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 09:57:52.548477 [FAST_K] Save calibration result to emmc
3713 09:57:52.551630 dramc_set_vcore_voltage set vcore to 650000
3714 09:57:52.554314 Read voltage for 600, 5
3715 09:57:52.554415 Vio18 = 0
3716 09:57:52.554516 Vcore = 650000
3717 09:57:52.557518 Vdram = 0
3718 09:57:52.557621 Vddq = 0
3719 09:57:52.557721 Vmddr = 0
3720 09:57:52.564586 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 09:57:52.567403 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 09:57:52.571109 MEM_TYPE=3, freq_sel=19
3723 09:57:52.574831 sv_algorithm_assistance_LP4_1600
3724 09:57:52.577224 ============ PULL DRAM RESETB DOWN ============
3725 09:57:52.580678 ========== PULL DRAM RESETB DOWN end =========
3726 09:57:52.587831 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 09:57:52.590584 ===================================
3728 09:57:52.593828 LPDDR4 DRAM CONFIGURATION
3729 09:57:52.597372 ===================================
3730 09:57:52.597487 EX_ROW_EN[0] = 0x0
3731 09:57:52.600801 EX_ROW_EN[1] = 0x0
3732 09:57:52.600879 LP4Y_EN = 0x0
3733 09:57:52.603953 WORK_FSP = 0x0
3734 09:57:52.604069 WL = 0x2
3735 09:57:52.607282 RL = 0x2
3736 09:57:52.607357 BL = 0x2
3737 09:57:52.610702 RPST = 0x0
3738 09:57:52.610824 RD_PRE = 0x0
3739 09:57:52.613993 WR_PRE = 0x1
3740 09:57:52.614109 WR_PST = 0x0
3741 09:57:52.617854 DBI_WR = 0x0
3742 09:57:52.617961 DBI_RD = 0x0
3743 09:57:52.620657 OTF = 0x1
3744 09:57:52.623689 ===================================
3745 09:57:52.628282 ===================================
3746 09:57:52.628389 ANA top config
3747 09:57:52.630558 ===================================
3748 09:57:52.633439 DLL_ASYNC_EN = 0
3749 09:57:52.636818 ALL_SLAVE_EN = 1
3750 09:57:52.640423 NEW_RANK_MODE = 1
3751 09:57:52.643784 DLL_IDLE_MODE = 1
3752 09:57:52.643871 LP45_APHY_COMB_EN = 1
3753 09:57:52.647425 TX_ODT_DIS = 1
3754 09:57:52.650321 NEW_8X_MODE = 1
3755 09:57:52.653383 ===================================
3756 09:57:52.656739 ===================================
3757 09:57:52.660040 data_rate = 1200
3758 09:57:52.663283 CKR = 1
3759 09:57:52.663389 DQ_P2S_RATIO = 8
3760 09:57:52.666650 ===================================
3761 09:57:52.669703 CA_P2S_RATIO = 8
3762 09:57:52.673648 DQ_CA_OPEN = 0
3763 09:57:52.676434 DQ_SEMI_OPEN = 0
3764 09:57:52.680081 CA_SEMI_OPEN = 0
3765 09:57:52.683159 CA_FULL_RATE = 0
3766 09:57:52.686875 DQ_CKDIV4_EN = 1
3767 09:57:52.687037 CA_CKDIV4_EN = 1
3768 09:57:52.689889 CA_PREDIV_EN = 0
3769 09:57:52.692815 PH8_DLY = 0
3770 09:57:52.696408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 09:57:52.699198 DQ_AAMCK_DIV = 4
3772 09:57:52.702619 CA_AAMCK_DIV = 4
3773 09:57:52.702750 CA_ADMCK_DIV = 4
3774 09:57:52.706120 DQ_TRACK_CA_EN = 0
3775 09:57:52.709588 CA_PICK = 600
3776 09:57:52.713095 CA_MCKIO = 600
3777 09:57:52.715890 MCKIO_SEMI = 0
3778 09:57:52.719386 PLL_FREQ = 2288
3779 09:57:52.722458 DQ_UI_PI_RATIO = 32
3780 09:57:52.722550 CA_UI_PI_RATIO = 0
3781 09:57:52.725665 ===================================
3782 09:57:52.728974 ===================================
3783 09:57:52.732523 memory_type:LPDDR4
3784 09:57:52.736241 GP_NUM : 10
3785 09:57:52.736346 SRAM_EN : 1
3786 09:57:52.738978 MD32_EN : 0
3787 09:57:52.742066 ===================================
3788 09:57:52.745793 [ANA_INIT] >>>>>>>>>>>>>>
3789 09:57:52.748736 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 09:57:52.752207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 09:57:52.755079 ===================================
3792 09:57:52.758968 data_rate = 1200,PCW = 0X5800
3793 09:57:52.761823 ===================================
3794 09:57:52.765329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 09:57:52.768550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 09:57:52.775326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 09:57:52.778392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 09:57:52.781728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 09:57:52.785478 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 09:57:52.788158 [ANA_INIT] flow start
3801 09:57:52.791638 [ANA_INIT] PLL >>>>>>>>
3802 09:57:52.791743 [ANA_INIT] PLL <<<<<<<<
3803 09:57:52.794810 [ANA_INIT] MIDPI >>>>>>>>
3804 09:57:52.798041 [ANA_INIT] MIDPI <<<<<<<<
3805 09:57:52.801951 [ANA_INIT] DLL >>>>>>>>
3806 09:57:52.802028 [ANA_INIT] flow end
3807 09:57:52.805024 ============ LP4 DIFF to SE enter ============
3808 09:57:52.811018 ============ LP4 DIFF to SE exit ============
3809 09:57:52.811102 [ANA_INIT] <<<<<<<<<<<<<
3810 09:57:52.814926 [Flow] Enable top DCM control >>>>>
3811 09:57:52.818174 [Flow] Enable top DCM control <<<<<
3812 09:57:52.820978 Enable DLL master slave shuffle
3813 09:57:52.827863 ==============================================================
3814 09:57:52.827968 Gating Mode config
3815 09:57:52.834476 ==============================================================
3816 09:57:52.837364 Config description:
3817 09:57:52.848045 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 09:57:52.854157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 09:57:52.857721 SELPH_MODE 0: By rank 1: By Phase
3820 09:57:52.864190 ==============================================================
3821 09:57:52.867282 GAT_TRACK_EN = 1
3822 09:57:52.870469 RX_GATING_MODE = 2
3823 09:57:52.873595 RX_GATING_TRACK_MODE = 2
3824 09:57:52.873676 SELPH_MODE = 1
3825 09:57:52.877371 PICG_EARLY_EN = 1
3826 09:57:52.880249 VALID_LAT_VALUE = 1
3827 09:57:52.886904 ==============================================================
3828 09:57:52.890902 Enter into Gating configuration >>>>
3829 09:57:52.893840 Exit from Gating configuration <<<<
3830 09:57:52.897035 Enter into DVFS_PRE_config >>>>>
3831 09:57:52.907339 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 09:57:52.910347 Exit from DVFS_PRE_config <<<<<
3833 09:57:52.913248 Enter into PICG configuration >>>>
3834 09:57:52.916956 Exit from PICG configuration <<<<
3835 09:57:52.920460 [RX_INPUT] configuration >>>>>
3836 09:57:52.923345 [RX_INPUT] configuration <<<<<
3837 09:57:52.926593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 09:57:52.933677 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 09:57:52.939821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 09:57:52.946681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 09:57:52.952988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 09:57:52.959684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 09:57:52.963010 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 09:57:52.966190 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 09:57:52.969211 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 09:57:52.975966 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 09:57:52.979245 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 09:57:52.982424 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 09:57:52.985757 ===================================
3850 09:57:52.989502 LPDDR4 DRAM CONFIGURATION
3851 09:57:52.992435 ===================================
3852 09:57:52.992526 EX_ROW_EN[0] = 0x0
3853 09:57:52.995668 EX_ROW_EN[1] = 0x0
3854 09:57:52.999039 LP4Y_EN = 0x0
3855 09:57:52.999119 WORK_FSP = 0x0
3856 09:57:53.002949 WL = 0x2
3857 09:57:53.003029 RL = 0x2
3858 09:57:53.005720 BL = 0x2
3859 09:57:53.005800 RPST = 0x0
3860 09:57:53.008618 RD_PRE = 0x0
3861 09:57:53.008698 WR_PRE = 0x1
3862 09:57:53.011956 WR_PST = 0x0
3863 09:57:53.012037 DBI_WR = 0x0
3864 09:57:53.015427 DBI_RD = 0x0
3865 09:57:53.015507 OTF = 0x1
3866 09:57:53.019121 ===================================
3867 09:57:53.022127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 09:57:53.028534 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 09:57:53.031824 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 09:57:53.035313 ===================================
3871 09:57:53.039552 LPDDR4 DRAM CONFIGURATION
3872 09:57:53.041758 ===================================
3873 09:57:53.041856 EX_ROW_EN[0] = 0x10
3874 09:57:53.045760 EX_ROW_EN[1] = 0x0
3875 09:57:53.048510 LP4Y_EN = 0x0
3876 09:57:53.048607 WORK_FSP = 0x0
3877 09:57:53.051813 WL = 0x2
3878 09:57:53.051900 RL = 0x2
3879 09:57:53.055124 BL = 0x2
3880 09:57:53.055216 RPST = 0x0
3881 09:57:53.058327 RD_PRE = 0x0
3882 09:57:53.058416 WR_PRE = 0x1
3883 09:57:53.061746 WR_PST = 0x0
3884 09:57:53.061831 DBI_WR = 0x0
3885 09:57:53.065328 DBI_RD = 0x0
3886 09:57:53.065410 OTF = 0x1
3887 09:57:53.067923 ===================================
3888 09:57:53.075058 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 09:57:53.079511 nWR fixed to 30
3890 09:57:53.082428 [ModeRegInit_LP4] CH0 RK0
3891 09:57:53.082536 [ModeRegInit_LP4] CH0 RK1
3892 09:57:53.085790 [ModeRegInit_LP4] CH1 RK0
3893 09:57:53.088905 [ModeRegInit_LP4] CH1 RK1
3894 09:57:53.088990 match AC timing 17
3895 09:57:53.095664 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 09:57:53.098910 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 09:57:53.101938 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 09:57:53.108981 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 09:57:53.112006 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 09:57:53.112089 ==
3901 09:57:53.115374 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 09:57:53.118734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 09:57:53.122123 ==
3904 09:57:53.125118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 09:57:53.132585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3906 09:57:53.134933 [CA 0] Center 36 (6~67) winsize 62
3907 09:57:53.138528 [CA 1] Center 36 (5~67) winsize 63
3908 09:57:53.142191 [CA 2] Center 34 (4~65) winsize 62
3909 09:57:53.145531 [CA 3] Center 34 (4~65) winsize 62
3910 09:57:53.148286 [CA 4] Center 33 (3~64) winsize 62
3911 09:57:53.151936 [CA 5] Center 33 (3~64) winsize 62
3912 09:57:53.152012
3913 09:57:53.154748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3914 09:57:53.154840
3915 09:57:53.158668 [CATrainingPosCal] consider 1 rank data
3916 09:57:53.161694 u2DelayCellTimex100 = 270/100 ps
3917 09:57:53.164837 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3918 09:57:53.168205 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3919 09:57:53.171486 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3920 09:57:53.177897 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3921 09:57:53.181312 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3922 09:57:53.184409 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3923 09:57:53.184487
3924 09:57:53.188162 CA PerBit enable=1, Macro0, CA PI delay=33
3925 09:57:53.188233
3926 09:57:53.191946 [CBTSetCACLKResult] CA Dly = 33
3927 09:57:53.192019 CS Dly: 5 (0~36)
3928 09:57:53.192081 ==
3929 09:57:53.194436 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 09:57:53.200827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 09:57:53.200903 ==
3932 09:57:53.204518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 09:57:53.210923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 09:57:53.214690 [CA 0] Center 36 (6~67) winsize 62
3935 09:57:53.217906 [CA 1] Center 36 (6~67) winsize 62
3936 09:57:53.221092 [CA 2] Center 34 (4~65) winsize 62
3937 09:57:53.225057 [CA 3] Center 34 (4~65) winsize 62
3938 09:57:53.227993 [CA 4] Center 34 (3~65) winsize 63
3939 09:57:53.231173 [CA 5] Center 33 (3~64) winsize 62
3940 09:57:53.231296
3941 09:57:53.235088 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 09:57:53.235166
3943 09:57:53.238120 [CATrainingPosCal] consider 2 rank data
3944 09:57:53.240946 u2DelayCellTimex100 = 270/100 ps
3945 09:57:53.244412 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 09:57:53.250723 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3947 09:57:53.254233 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 09:57:53.257707 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 09:57:53.261849 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 09:57:53.263983 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 09:57:53.264086
3952 09:57:53.267871 CA PerBit enable=1, Macro0, CA PI delay=33
3953 09:57:53.267948
3954 09:57:53.271041 [CBTSetCACLKResult] CA Dly = 33
3955 09:57:53.273708 CS Dly: 6 (0~38)
3956 09:57:53.273788
3957 09:57:53.277014 ----->DramcWriteLeveling(PI) begin...
3958 09:57:53.277095 ==
3959 09:57:53.280615 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 09:57:53.283874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 09:57:53.283955 ==
3962 09:57:53.287725 Write leveling (Byte 0): 33 => 33
3963 09:57:53.290762 Write leveling (Byte 1): 28 => 28
3964 09:57:53.293544 DramcWriteLeveling(PI) end<-----
3965 09:57:53.293624
3966 09:57:53.293687 ==
3967 09:57:53.297003 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 09:57:53.300398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 09:57:53.300479 ==
3970 09:57:53.304026 [Gating] SW mode calibration
3971 09:57:53.310475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 09:57:53.316671 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 09:57:53.319983 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 09:57:53.323066 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 09:57:53.330087 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 09:57:53.333271 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3977 09:57:53.336467 0 9 16 | B1->B0 | 2e2e 2626 | 1 0 | (1 1) (0 0)
3978 09:57:53.343323 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 09:57:53.346285 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 09:57:53.352945 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 09:57:53.356372 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 09:57:53.359299 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 09:57:53.365931 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 09:57:53.369282 0 10 12 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
3985 09:57:53.372892 0 10 16 | B1->B0 | 3b3b 3e3e | 0 0 | (1 1) (0 0)
3986 09:57:53.379613 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 09:57:53.382384 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 09:57:53.385525 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 09:57:53.392360 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 09:57:53.395907 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 09:57:53.398744 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 09:57:53.405732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 09:57:53.408853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 09:57:53.411858 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 09:57:53.418901 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 09:57:53.422238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 09:57:53.425058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 09:57:53.432073 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 09:57:53.435602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 09:57:53.438641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 09:57:53.444766 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 09:57:53.448122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 09:57:53.451420 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 09:57:53.458178 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 09:57:53.461386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 09:57:53.464733 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 09:57:53.471517 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 09:57:53.474863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4009 09:57:53.477867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4010 09:57:53.484680 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 09:57:53.484755 Total UI for P1: 0, mck2ui 16
4012 09:57:53.488247 best dqsien dly found for B0: ( 0, 13, 14)
4013 09:57:53.491035 Total UI for P1: 0, mck2ui 16
4014 09:57:53.494745 best dqsien dly found for B1: ( 0, 13, 14)
4015 09:57:53.500945 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4016 09:57:53.504471 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4017 09:57:53.504544
4018 09:57:53.507827 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4019 09:57:53.511097 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4020 09:57:53.514603 [Gating] SW calibration Done
4021 09:57:53.514671 ==
4022 09:57:53.517770 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 09:57:53.520688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 09:57:53.520757 ==
4025 09:57:53.524506 RX Vref Scan: 0
4026 09:57:53.524573
4027 09:57:53.524632 RX Vref 0 -> 0, step: 1
4028 09:57:53.524689
4029 09:57:53.527785 RX Delay -230 -> 252, step: 16
4030 09:57:53.533853 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 09:57:53.537165 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4032 09:57:53.540657 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 09:57:53.543863 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4034 09:57:53.547337 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4035 09:57:53.553627 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4036 09:57:53.557418 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 09:57:53.560593 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4038 09:57:53.563571 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4039 09:57:53.570594 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4040 09:57:53.573845 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4041 09:57:53.576682 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4042 09:57:53.580192 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4043 09:57:53.586830 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4044 09:57:53.590161 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4045 09:57:53.593382 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4046 09:57:53.593450 ==
4047 09:57:53.596838 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 09:57:53.600244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 09:57:53.603518 ==
4050 09:57:53.603586 DQS Delay:
4051 09:57:53.603647 DQS0 = 0, DQS1 = 0
4052 09:57:53.607038 DQM Delay:
4053 09:57:53.607103 DQM0 = 43, DQM1 = 34
4054 09:57:53.610108 DQ Delay:
4055 09:57:53.610173 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4056 09:57:53.613190 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4057 09:57:53.616623 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4058 09:57:53.620111 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4059 09:57:53.620177
4060 09:57:53.623253
4061 09:57:53.623318 ==
4062 09:57:53.626151 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 09:57:53.629746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 09:57:53.629812 ==
4065 09:57:53.629872
4066 09:57:53.629928
4067 09:57:53.633134 TX Vref Scan disable
4068 09:57:53.633200 == TX Byte 0 ==
4069 09:57:53.640334 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 09:57:53.643039 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 09:57:53.643110 == TX Byte 1 ==
4072 09:57:53.649655 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4073 09:57:53.653001 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4074 09:57:53.653072 ==
4075 09:57:53.656147 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 09:57:53.659458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 09:57:53.659530 ==
4078 09:57:53.659592
4079 09:57:53.659657
4080 09:57:53.662451 TX Vref Scan disable
4081 09:57:53.666003 == TX Byte 0 ==
4082 09:57:53.669537 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 09:57:53.675885 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 09:57:53.675962 == TX Byte 1 ==
4085 09:57:53.679271 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4086 09:57:53.685832 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4087 09:57:53.685914
4088 09:57:53.685977 [DATLAT]
4089 09:57:53.686036 Freq=600, CH0 RK0
4090 09:57:53.686099
4091 09:57:53.689531 DATLAT Default: 0x9
4092 09:57:53.692252 0, 0xFFFF, sum = 0
4093 09:57:53.692324 1, 0xFFFF, sum = 0
4094 09:57:53.695498 2, 0xFFFF, sum = 0
4095 09:57:53.695568 3, 0xFFFF, sum = 0
4096 09:57:53.698991 4, 0xFFFF, sum = 0
4097 09:57:53.699061 5, 0xFFFF, sum = 0
4098 09:57:53.702637 6, 0xFFFF, sum = 0
4099 09:57:53.702708 7, 0xFFFF, sum = 0
4100 09:57:53.705673 8, 0x0, sum = 1
4101 09:57:53.705742 9, 0x0, sum = 2
4102 09:57:53.709137 10, 0x0, sum = 3
4103 09:57:53.709205 11, 0x0, sum = 4
4104 09:57:53.709266 best_step = 9
4105 09:57:53.709323
4106 09:57:53.712407 ==
4107 09:57:53.716008 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 09:57:53.718694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 09:57:53.718766 ==
4110 09:57:53.718827 RX Vref Scan: 1
4111 09:57:53.718893
4112 09:57:53.722077 RX Vref 0 -> 0, step: 1
4113 09:57:53.722149
4114 09:57:53.725637 RX Delay -195 -> 252, step: 8
4115 09:57:53.725705
4116 09:57:53.728861 Set Vref, RX VrefLevel [Byte0]: 57
4117 09:57:53.732177 [Byte1]: 59
4118 09:57:53.732252
4119 09:57:53.735349 Final RX Vref Byte 0 = 57 to rank0
4120 09:57:53.738858 Final RX Vref Byte 1 = 59 to rank0
4121 09:57:53.741571 Final RX Vref Byte 0 = 57 to rank1
4122 09:57:53.745331 Final RX Vref Byte 1 = 59 to rank1==
4123 09:57:53.748863 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 09:57:53.755029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 09:57:53.755101 ==
4126 09:57:53.755164 DQS Delay:
4127 09:57:53.755228 DQS0 = 0, DQS1 = 0
4128 09:57:53.758160 DQM Delay:
4129 09:57:53.758283 DQM0 = 41, DQM1 = 33
4130 09:57:53.761566 DQ Delay:
4131 09:57:53.764749 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4132 09:57:53.768327 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4133 09:57:53.771739 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4134 09:57:53.775421 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4135 09:57:53.775503
4136 09:57:53.775567
4137 09:57:53.781092 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4138 09:57:53.784731 CH0 RK0: MR19=808, MR18=4A42
4139 09:57:53.791161 CH0_RK0: MR19=0x808, MR18=0x4A42, DQSOSC=395, MR23=63, INC=168, DEC=112
4140 09:57:53.791239
4141 09:57:53.794597 ----->DramcWriteLeveling(PI) begin...
4142 09:57:53.794669 ==
4143 09:57:53.797708 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 09:57:53.800866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 09:57:53.800940 ==
4146 09:57:53.804251 Write leveling (Byte 0): 34 => 34
4147 09:57:53.807908 Write leveling (Byte 1): 31 => 31
4148 09:57:53.810575 DramcWriteLeveling(PI) end<-----
4149 09:57:53.810644
4150 09:57:53.810705 ==
4151 09:57:53.814597 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 09:57:53.817160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 09:57:53.820487 ==
4154 09:57:53.820556 [Gating] SW mode calibration
4155 09:57:53.830716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 09:57:53.833991 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 09:57:53.837269 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 09:57:53.843511 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 09:57:53.847090 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 09:57:53.850563 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4161 09:57:53.856800 0 9 16 | B1->B0 | 2f2f 2424 | 1 1 | (1 0) (0 0)
4162 09:57:53.860033 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 09:57:53.863653 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 09:57:53.870343 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 09:57:53.873183 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 09:57:53.877071 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 09:57:53.883473 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 09:57:53.887067 0 10 12 | B1->B0 | 2828 3838 | 0 0 | (1 1) (0 0)
4169 09:57:53.889955 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4170 09:57:53.896763 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 09:57:53.899678 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 09:57:53.902919 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 09:57:53.910050 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 09:57:53.912853 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 09:57:53.916143 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 09:57:53.922822 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4177 09:57:53.926563 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4178 09:57:53.929231 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 09:57:53.936077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 09:57:53.939526 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 09:57:53.942494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 09:57:53.949640 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 09:57:53.952353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 09:57:53.955961 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 09:57:53.962649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 09:57:53.965784 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 09:57:53.969261 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 09:57:53.975397 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 09:57:53.978427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 09:57:53.982144 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 09:57:53.988657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 09:57:53.991729 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4193 09:57:53.995002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 09:57:53.998531 Total UI for P1: 0, mck2ui 16
4195 09:57:54.001525 best dqsien dly found for B0: ( 0, 13, 12)
4196 09:57:54.004619 Total UI for P1: 0, mck2ui 16
4197 09:57:54.008106 best dqsien dly found for B1: ( 0, 13, 12)
4198 09:57:54.014730 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4199 09:57:54.017859 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4200 09:57:54.017929
4201 09:57:54.021029 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4202 09:57:54.024666 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4203 09:57:54.027796 [Gating] SW calibration Done
4204 09:57:54.027874 ==
4205 09:57:54.031372 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 09:57:54.034645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 09:57:54.034740 ==
4208 09:57:54.038383 RX Vref Scan: 0
4209 09:57:54.038454
4210 09:57:54.038515 RX Vref 0 -> 0, step: 1
4211 09:57:54.038574
4212 09:57:54.040976 RX Delay -230 -> 252, step: 16
4213 09:57:54.044567 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4214 09:57:54.051095 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4215 09:57:54.054487 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4216 09:57:54.057730 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4217 09:57:54.060949 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4218 09:57:54.067835 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4219 09:57:54.071274 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 09:57:54.074136 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4221 09:57:54.077516 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4222 09:57:54.084605 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4223 09:57:54.088165 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4224 09:57:54.091119 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4225 09:57:54.094154 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4226 09:57:54.100691 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4227 09:57:54.104250 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4228 09:57:54.107353 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4229 09:57:54.107434 ==
4230 09:57:54.110576 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 09:57:54.114295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 09:57:54.114377 ==
4233 09:57:54.117064 DQS Delay:
4234 09:57:54.117145 DQS0 = 0, DQS1 = 0
4235 09:57:54.120254 DQM Delay:
4236 09:57:54.120334 DQM0 = 43, DQM1 = 33
4237 09:57:54.120399 DQ Delay:
4238 09:57:54.124040 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4239 09:57:54.126981 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4240 09:57:54.130169 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4241 09:57:54.133685 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4242 09:57:54.133766
4243 09:57:54.133831
4244 09:57:54.136940 ==
4245 09:57:54.140884 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 09:57:54.143558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 09:57:54.143640 ==
4248 09:57:54.143705
4249 09:57:54.143766
4250 09:57:54.146780 TX Vref Scan disable
4251 09:57:54.146862 == TX Byte 0 ==
4252 09:57:54.153497 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4253 09:57:54.156743 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4254 09:57:54.156825 == TX Byte 1 ==
4255 09:57:54.163779 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4256 09:57:54.167026 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4257 09:57:54.167108 ==
4258 09:57:54.169952 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 09:57:54.173582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 09:57:54.173708 ==
4261 09:57:54.173773
4262 09:57:54.173833
4263 09:57:54.176721 TX Vref Scan disable
4264 09:57:54.180005 == TX Byte 0 ==
4265 09:57:54.183271 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 09:57:54.186281 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 09:57:54.189697 == TX Byte 1 ==
4268 09:57:54.193385 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4269 09:57:54.199446 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4270 09:57:54.199528
4271 09:57:54.199591 [DATLAT]
4272 09:57:54.199652 Freq=600, CH0 RK1
4273 09:57:54.199713
4274 09:57:54.203105 DATLAT Default: 0x9
4275 09:57:54.203186 0, 0xFFFF, sum = 0
4276 09:57:54.206874 1, 0xFFFF, sum = 0
4277 09:57:54.209504 2, 0xFFFF, sum = 0
4278 09:57:54.209586 3, 0xFFFF, sum = 0
4279 09:57:54.212534 4, 0xFFFF, sum = 0
4280 09:57:54.212617 5, 0xFFFF, sum = 0
4281 09:57:54.216191 6, 0xFFFF, sum = 0
4282 09:57:54.216273 7, 0xFFFF, sum = 0
4283 09:57:54.219376 8, 0x0, sum = 1
4284 09:57:54.219459 9, 0x0, sum = 2
4285 09:57:54.222586 10, 0x0, sum = 3
4286 09:57:54.222668 11, 0x0, sum = 4
4287 09:57:54.222733 best_step = 9
4288 09:57:54.222794
4289 09:57:54.226144 ==
4290 09:57:54.226226 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 09:57:54.232564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 09:57:54.232646 ==
4293 09:57:54.232712 RX Vref Scan: 0
4294 09:57:54.232790
4295 09:57:54.236095 RX Vref 0 -> 0, step: 1
4296 09:57:54.236176
4297 09:57:54.238914 RX Delay -195 -> 252, step: 8
4298 09:57:54.245567 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4299 09:57:54.248947 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4300 09:57:54.252281 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4301 09:57:54.255391 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4302 09:57:54.258967 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4303 09:57:54.265577 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4304 09:57:54.268442 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4305 09:57:54.272314 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4306 09:57:54.275021 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4307 09:57:54.281963 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4308 09:57:54.285155 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4309 09:57:54.288613 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4310 09:57:54.291649 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4311 09:57:54.298124 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4312 09:57:54.301498 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4313 09:57:54.305149 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4314 09:57:54.305229 ==
4315 09:57:54.307898 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 09:57:54.311774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 09:57:54.314864 ==
4318 09:57:54.314944 DQS Delay:
4319 09:57:54.315008 DQS0 = 0, DQS1 = 0
4320 09:57:54.318105 DQM Delay:
4321 09:57:54.318184 DQM0 = 42, DQM1 = 33
4322 09:57:54.321290 DQ Delay:
4323 09:57:54.324765 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4324 09:57:54.324845 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4325 09:57:54.328065 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4326 09:57:54.334405 DQ12 =40, DQ13 =36, DQ14 =48, DQ15 =40
4327 09:57:54.334485
4328 09:57:54.334548
4329 09:57:54.340837 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4330 09:57:54.344028 CH0 RK1: MR19=808, MR18=3D38
4331 09:57:54.350865 CH0_RK1: MR19=0x808, MR18=0x3D38, DQSOSC=398, MR23=63, INC=165, DEC=110
4332 09:57:54.354275 [RxdqsGatingPostProcess] freq 600
4333 09:57:54.357738 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 09:57:54.360854 Pre-setting of DQS Precalculation
4335 09:57:54.367438 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 09:57:54.367520 ==
4337 09:57:54.371070 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 09:57:54.373826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 09:57:54.373907 ==
4340 09:57:54.380587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 09:57:54.387079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4342 09:57:54.390684 [CA 0] Center 35 (5~66) winsize 62
4343 09:57:54.393833 [CA 1] Center 35 (5~66) winsize 62
4344 09:57:54.397327 [CA 2] Center 34 (4~65) winsize 62
4345 09:57:54.400311 [CA 3] Center 34 (3~65) winsize 63
4346 09:57:54.403571 [CA 4] Center 34 (4~65) winsize 62
4347 09:57:54.406620 [CA 5] Center 34 (3~65) winsize 63
4348 09:57:54.406700
4349 09:57:54.410066 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4350 09:57:54.410146
4351 09:57:54.413799 [CATrainingPosCal] consider 1 rank data
4352 09:57:54.416599 u2DelayCellTimex100 = 270/100 ps
4353 09:57:54.420252 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4354 09:57:54.423123 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4355 09:57:54.426394 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 09:57:54.429765 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4357 09:57:54.433151 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 09:57:54.436570 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4359 09:57:54.436650
4360 09:57:54.442823 CA PerBit enable=1, Macro0, CA PI delay=34
4361 09:57:54.442904
4362 09:57:54.446121 [CBTSetCACLKResult] CA Dly = 34
4363 09:57:54.446201 CS Dly: 5 (0~36)
4364 09:57:54.446289 ==
4365 09:57:54.449479 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 09:57:54.452670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 09:57:54.452751 ==
4368 09:57:54.459274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 09:57:54.466102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 09:57:54.470067 [CA 0] Center 35 (5~66) winsize 62
4371 09:57:54.472458 [CA 1] Center 35 (5~66) winsize 62
4372 09:57:54.475942 [CA 2] Center 34 (4~65) winsize 62
4373 09:57:54.479410 [CA 3] Center 33 (3~64) winsize 62
4374 09:57:54.482797 [CA 4] Center 34 (3~65) winsize 63
4375 09:57:54.485937 [CA 5] Center 33 (3~64) winsize 62
4376 09:57:54.486017
4377 09:57:54.489006 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 09:57:54.489088
4379 09:57:54.492581 [CATrainingPosCal] consider 2 rank data
4380 09:57:54.495931 u2DelayCellTimex100 = 270/100 ps
4381 09:57:54.498874 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 09:57:54.502330 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 09:57:54.505534 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 09:57:54.512276 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 09:57:54.515851 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 09:57:54.518547 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 09:57:54.518628
4388 09:57:54.522392 CA PerBit enable=1, Macro0, CA PI delay=33
4389 09:57:54.522473
4390 09:57:54.525467 [CBTSetCACLKResult] CA Dly = 33
4391 09:57:54.525548 CS Dly: 5 (0~36)
4392 09:57:54.525612
4393 09:57:54.528600 ----->DramcWriteLeveling(PI) begin...
4394 09:57:54.528683 ==
4395 09:57:54.532105 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 09:57:54.538453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 09:57:54.538534 ==
4398 09:57:54.541948 Write leveling (Byte 0): 30 => 30
4399 09:57:54.545178 Write leveling (Byte 1): 30 => 30
4400 09:57:54.548251 DramcWriteLeveling(PI) end<-----
4401 09:57:54.548332
4402 09:57:54.548396 ==
4403 09:57:54.551881 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 09:57:54.555037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 09:57:54.555123 ==
4406 09:57:54.558402 [Gating] SW mode calibration
4407 09:57:54.565191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 09:57:54.571253 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 09:57:54.575049 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 09:57:54.577884 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 09:57:54.584848 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 09:57:54.587973 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (0 0)
4413 09:57:54.591013 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 09:57:54.597795 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 09:57:54.601177 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 09:57:54.604149 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 09:57:54.611001 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 09:57:54.614458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 09:57:54.617381 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4420 09:57:54.624064 0 10 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (0 0)
4421 09:57:54.627206 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 09:57:54.630894 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 09:57:54.637096 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 09:57:54.640249 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 09:57:54.643804 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 09:57:54.650172 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 09:57:54.653498 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 09:57:54.657096 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4429 09:57:54.663311 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 09:57:54.666909 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 09:57:54.669738 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 09:57:54.676635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 09:57:54.680327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 09:57:54.697463 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 09:57:54.697593 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 09:57:54.697697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 09:57:54.697778 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 09:57:54.703261 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 09:57:54.706441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 09:57:54.709598 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 09:57:54.716124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 09:57:54.720247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 09:57:54.723128 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 09:57:54.729776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4445 09:57:54.729860 Total UI for P1: 0, mck2ui 16
4446 09:57:54.733023 best dqsien dly found for B0: ( 0, 13, 10)
4447 09:57:54.739785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 09:57:54.742617 Total UI for P1: 0, mck2ui 16
4449 09:57:54.745893 best dqsien dly found for B1: ( 0, 13, 12)
4450 09:57:54.749196 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4451 09:57:54.752677 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4452 09:57:54.752761
4453 09:57:54.756037 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4454 09:57:54.759134 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 09:57:54.762606 [Gating] SW calibration Done
4456 09:57:54.762690 ==
4457 09:57:54.765751 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 09:57:54.769042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 09:57:54.772331 ==
4460 09:57:54.772414 RX Vref Scan: 0
4461 09:57:54.772518
4462 09:57:54.775682 RX Vref 0 -> 0, step: 1
4463 09:57:54.775766
4464 09:57:54.778899 RX Delay -230 -> 252, step: 16
4465 09:57:54.782184 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4466 09:57:54.785815 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4467 09:57:54.789037 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4468 09:57:54.795815 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 09:57:54.799219 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 09:57:54.802704 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4471 09:57:54.805685 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4472 09:57:54.808583 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4473 09:57:54.815245 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4474 09:57:54.818477 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4475 09:57:54.821536 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4476 09:57:54.824915 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4477 09:57:54.831562 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4478 09:57:54.835129 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4479 09:57:54.838747 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4480 09:57:54.844907 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 09:57:54.844988 ==
4482 09:57:54.847873 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 09:57:54.851798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 09:57:54.851880 ==
4485 09:57:54.851945 DQS Delay:
4486 09:57:54.854718 DQS0 = 0, DQS1 = 0
4487 09:57:54.854799 DQM Delay:
4488 09:57:54.858216 DQM0 = 44, DQM1 = 40
4489 09:57:54.858307 DQ Delay:
4490 09:57:54.861324 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4491 09:57:54.864442 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4492 09:57:54.867845 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4493 09:57:54.871147 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4494 09:57:54.871230
4495 09:57:54.871294
4496 09:57:54.871354 ==
4497 09:57:54.874504 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 09:57:54.877849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 09:57:54.877930 ==
4500 09:57:54.877995
4501 09:57:54.881216
4502 09:57:54.881337 TX Vref Scan disable
4503 09:57:54.884218 == TX Byte 0 ==
4504 09:57:54.887462 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4505 09:57:54.890969 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4506 09:57:54.894557 == TX Byte 1 ==
4507 09:57:54.897335 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 09:57:54.900673 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 09:57:54.903953 ==
4510 09:57:54.904034 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 09:57:54.910528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 09:57:54.910609 ==
4513 09:57:54.910674
4514 09:57:54.910733
4515 09:57:54.913863 TX Vref Scan disable
4516 09:57:54.913945 == TX Byte 0 ==
4517 09:57:54.920461 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 09:57:54.923622 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 09:57:54.923703 == TX Byte 1 ==
4520 09:57:54.930072 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4521 09:57:54.933463 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4522 09:57:54.933544
4523 09:57:54.933609 [DATLAT]
4524 09:57:54.936740 Freq=600, CH1 RK0
4525 09:57:54.936821
4526 09:57:54.936886 DATLAT Default: 0x9
4527 09:57:54.940087 0, 0xFFFF, sum = 0
4528 09:57:54.940169 1, 0xFFFF, sum = 0
4529 09:57:54.943776 2, 0xFFFF, sum = 0
4530 09:57:54.946653 3, 0xFFFF, sum = 0
4531 09:57:54.946735 4, 0xFFFF, sum = 0
4532 09:57:54.950201 5, 0xFFFF, sum = 0
4533 09:57:54.950324 6, 0xFFFF, sum = 0
4534 09:57:54.953293 7, 0xFFFF, sum = 0
4535 09:57:54.953376 8, 0x0, sum = 1
4536 09:57:54.953442 9, 0x0, sum = 2
4537 09:57:54.956817 10, 0x0, sum = 3
4538 09:57:54.956899 11, 0x0, sum = 4
4539 09:57:54.959948 best_step = 9
4540 09:57:54.960029
4541 09:57:54.960094 ==
4542 09:57:54.963597 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 09:57:54.966378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 09:57:54.966461 ==
4545 09:57:54.969948 RX Vref Scan: 1
4546 09:57:54.970029
4547 09:57:54.970093 RX Vref 0 -> 0, step: 1
4548 09:57:54.970154
4549 09:57:54.973184 RX Delay -179 -> 252, step: 8
4550 09:57:54.973265
4551 09:57:54.976775 Set Vref, RX VrefLevel [Byte0]: 51
4552 09:57:54.979551 [Byte1]: 52
4553 09:57:54.984204
4554 09:57:54.984283 Final RX Vref Byte 0 = 51 to rank0
4555 09:57:54.987786 Final RX Vref Byte 1 = 52 to rank0
4556 09:57:54.990582 Final RX Vref Byte 0 = 51 to rank1
4557 09:57:54.994613 Final RX Vref Byte 1 = 52 to rank1==
4558 09:57:54.997268 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 09:57:55.004166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 09:57:55.004247 ==
4561 09:57:55.004313 DQS Delay:
4562 09:57:55.007285 DQS0 = 0, DQS1 = 0
4563 09:57:55.007365 DQM Delay:
4564 09:57:55.007428 DQM0 = 41, DQM1 = 34
4565 09:57:55.010413 DQ Delay:
4566 09:57:55.013743 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4567 09:57:55.016945 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4568 09:57:55.020617 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4569 09:57:55.023530 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4570 09:57:55.023621
4571 09:57:55.023685
4572 09:57:55.030796 [DQSOSCAuto] RK0, (LSB)MR18= 0x304a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4573 09:57:55.033709 CH1 RK0: MR19=808, MR18=304A
4574 09:57:55.040460 CH1_RK0: MR19=0x808, MR18=0x304A, DQSOSC=395, MR23=63, INC=168, DEC=112
4575 09:57:55.040541
4576 09:57:55.043464 ----->DramcWriteLeveling(PI) begin...
4577 09:57:55.043556 ==
4578 09:57:55.046686 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 09:57:55.050015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 09:57:55.050096 ==
4581 09:57:55.053048 Write leveling (Byte 0): 29 => 29
4582 09:57:55.056828 Write leveling (Byte 1): 28 => 28
4583 09:57:55.060653 DramcWriteLeveling(PI) end<-----
4584 09:57:55.060732
4585 09:57:55.060795 ==
4586 09:57:55.063350 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 09:57:55.066818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 09:57:55.069771 ==
4589 09:57:55.069850 [Gating] SW mode calibration
4590 09:57:55.079579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 09:57:55.082774 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 09:57:55.086446 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 09:57:55.092601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 09:57:55.096059 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4595 09:57:55.099666 0 9 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4596 09:57:55.106170 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 09:57:55.109697 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 09:57:55.112516 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 09:57:55.119254 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 09:57:55.122644 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 09:57:55.125775 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 09:57:55.132174 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4603 09:57:55.135867 0 10 12 | B1->B0 | 3232 4242 | 0 0 | (0 0) (1 1)
4604 09:57:55.139063 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 09:57:55.145406 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 09:57:55.148781 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 09:57:55.152053 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 09:57:55.158830 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 09:57:55.162177 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 09:57:55.164984 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 09:57:55.171774 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 09:57:55.175185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 09:57:55.178133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 09:57:55.185186 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 09:57:55.188298 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 09:57:55.194382 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 09:57:55.198041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 09:57:55.201269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 09:57:55.207780 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 09:57:55.211492 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 09:57:55.214398 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 09:57:55.221441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 09:57:55.224419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 09:57:55.227693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 09:57:55.234443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 09:57:55.238086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 09:57:55.240943 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 09:57:55.243878 Total UI for P1: 0, mck2ui 16
4629 09:57:55.247194 best dqsien dly found for B0: ( 0, 13, 10)
4630 09:57:55.250459 Total UI for P1: 0, mck2ui 16
4631 09:57:55.254235 best dqsien dly found for B1: ( 0, 13, 10)
4632 09:57:55.257663 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4633 09:57:55.260740 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4634 09:57:55.260821
4635 09:57:55.267150 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4636 09:57:55.270502 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4637 09:57:55.270583 [Gating] SW calibration Done
4638 09:57:55.273792 ==
4639 09:57:55.276743 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 09:57:55.280308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 09:57:55.280390 ==
4642 09:57:55.280455 RX Vref Scan: 0
4643 09:57:55.280515
4644 09:57:55.283285 RX Vref 0 -> 0, step: 1
4645 09:57:55.283368
4646 09:57:55.286951 RX Delay -230 -> 252, step: 16
4647 09:57:55.290152 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4648 09:57:55.293318 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4649 09:57:55.300042 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4650 09:57:55.303676 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4651 09:57:55.306898 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4652 09:57:55.310108 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4653 09:57:55.316542 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4654 09:57:55.319891 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4655 09:57:55.322996 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4656 09:57:55.326284 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4657 09:57:55.332768 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4658 09:57:55.336239 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4659 09:57:55.339620 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4660 09:57:55.342784 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4661 09:57:55.349360 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4662 09:57:55.352888 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4663 09:57:55.352969 ==
4664 09:57:55.356142 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 09:57:55.359423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 09:57:55.359505 ==
4667 09:57:55.362898 DQS Delay:
4668 09:57:55.362979 DQS0 = 0, DQS1 = 0
4669 09:57:55.363044 DQM Delay:
4670 09:57:55.366672 DQM0 = 43, DQM1 = 40
4671 09:57:55.366753 DQ Delay:
4672 09:57:55.369228 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4673 09:57:55.372694 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4674 09:57:55.375894 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4675 09:57:55.379328 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4676 09:57:55.379409
4677 09:57:55.379473
4678 09:57:55.379533 ==
4679 09:57:55.382585 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 09:57:55.389267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 09:57:55.389380 ==
4682 09:57:55.389476
4683 09:57:55.389565
4684 09:57:55.389663 TX Vref Scan disable
4685 09:57:55.392724 == TX Byte 0 ==
4686 09:57:55.396180 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4687 09:57:55.402685 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4688 09:57:55.402777 == TX Byte 1 ==
4689 09:57:55.405788 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4690 09:57:55.412626 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4691 09:57:55.412731 ==
4692 09:57:55.415422 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 09:57:55.418721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 09:57:55.418797 ==
4695 09:57:55.418865
4696 09:57:55.418925
4697 09:57:55.422215 TX Vref Scan disable
4698 09:57:55.425498 == TX Byte 0 ==
4699 09:57:55.428894 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4700 09:57:55.432557 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4701 09:57:55.435341 == TX Byte 1 ==
4702 09:57:55.438558 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4703 09:57:55.442367 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4704 09:57:55.442450
4705 09:57:55.445182 [DATLAT]
4706 09:57:55.445264 Freq=600, CH1 RK1
4707 09:57:55.445329
4708 09:57:55.448665 DATLAT Default: 0x9
4709 09:57:55.448747 0, 0xFFFF, sum = 0
4710 09:57:55.452208 1, 0xFFFF, sum = 0
4711 09:57:55.452291 2, 0xFFFF, sum = 0
4712 09:57:55.455291 3, 0xFFFF, sum = 0
4713 09:57:55.455374 4, 0xFFFF, sum = 0
4714 09:57:55.458181 5, 0xFFFF, sum = 0
4715 09:57:55.458290 6, 0xFFFF, sum = 0
4716 09:57:55.461558 7, 0xFFFF, sum = 0
4717 09:57:55.461639 8, 0x0, sum = 1
4718 09:57:55.464859 9, 0x0, sum = 2
4719 09:57:55.464941 10, 0x0, sum = 3
4720 09:57:55.468759 11, 0x0, sum = 4
4721 09:57:55.468841 best_step = 9
4722 09:57:55.468907
4723 09:57:55.468967 ==
4724 09:57:55.471904 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 09:57:55.474767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 09:57:55.474849 ==
4727 09:57:55.478052 RX Vref Scan: 0
4728 09:57:55.478133
4729 09:57:55.481965 RX Vref 0 -> 0, step: 1
4730 09:57:55.482046
4731 09:57:55.484867 RX Delay -179 -> 252, step: 8
4732 09:57:55.487940 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4733 09:57:55.491354 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4734 09:57:55.497943 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4735 09:57:55.501493 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4736 09:57:55.505094 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4737 09:57:55.508065 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4738 09:57:55.514600 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4739 09:57:55.517567 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4740 09:57:55.520809 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4741 09:57:55.524697 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4742 09:57:55.531147 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4743 09:57:55.534506 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4744 09:57:55.537535 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4745 09:57:55.540804 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4746 09:57:55.547410 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4747 09:57:55.550568 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4748 09:57:55.550650 ==
4749 09:57:55.553903 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 09:57:55.557598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 09:57:55.557680 ==
4752 09:57:55.561056 DQS Delay:
4753 09:57:55.561137 DQS0 = 0, DQS1 = 0
4754 09:57:55.561202 DQM Delay:
4755 09:57:55.563834 DQM0 = 38, DQM1 = 35
4756 09:57:55.563916 DQ Delay:
4757 09:57:55.566970 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4758 09:57:55.570230 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4759 09:57:55.573812 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4760 09:57:55.576693 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4761 09:57:55.576774
4762 09:57:55.576839
4763 09:57:55.586584 [DQSOSCAuto] RK1, (LSB)MR18= 0x355a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4764 09:57:55.590173 CH1 RK1: MR19=808, MR18=355A
4765 09:57:55.593416 CH1_RK1: MR19=0x808, MR18=0x355A, DQSOSC=392, MR23=63, INC=170, DEC=113
4766 09:57:55.596665 [RxdqsGatingPostProcess] freq 600
4767 09:57:55.603346 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4768 09:57:55.606487 Pre-setting of DQS Precalculation
4769 09:57:55.609953 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4770 09:57:55.619791 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4771 09:57:55.626569 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4772 09:57:55.626652
4773 09:57:55.626717
4774 09:57:55.629406 [Calibration Summary] 1200 Mbps
4775 09:57:55.629487 CH 0, Rank 0
4776 09:57:55.632899 SW Impedance : PASS
4777 09:57:55.632979 DUTY Scan : NO K
4778 09:57:55.636275 ZQ Calibration : PASS
4779 09:57:55.639653 Jitter Meter : NO K
4780 09:57:55.639734 CBT Training : PASS
4781 09:57:55.642592 Write leveling : PASS
4782 09:57:55.646073 RX DQS gating : PASS
4783 09:57:55.646154 RX DQ/DQS(RDDQC) : PASS
4784 09:57:55.649631 TX DQ/DQS : PASS
4785 09:57:55.652461 RX DATLAT : PASS
4786 09:57:55.652542 RX DQ/DQS(Engine): PASS
4787 09:57:55.656193 TX OE : NO K
4788 09:57:55.656276 All Pass.
4789 09:57:55.656372
4790 09:57:55.659080 CH 0, Rank 1
4791 09:57:55.659162 SW Impedance : PASS
4792 09:57:55.662161 DUTY Scan : NO K
4793 09:57:55.665624 ZQ Calibration : PASS
4794 09:57:55.665705 Jitter Meter : NO K
4795 09:57:55.669199 CBT Training : PASS
4796 09:57:55.672671 Write leveling : PASS
4797 09:57:55.672752 RX DQS gating : PASS
4798 09:57:55.675733 RX DQ/DQS(RDDQC) : PASS
4799 09:57:55.679088 TX DQ/DQS : PASS
4800 09:57:55.679170 RX DATLAT : PASS
4801 09:57:55.682209 RX DQ/DQS(Engine): PASS
4802 09:57:55.685489 TX OE : NO K
4803 09:57:55.685571 All Pass.
4804 09:57:55.685635
4805 09:57:55.685694 CH 1, Rank 0
4806 09:57:55.688828 SW Impedance : PASS
4807 09:57:55.691862 DUTY Scan : NO K
4808 09:57:55.691943 ZQ Calibration : PASS
4809 09:57:55.695389 Jitter Meter : NO K
4810 09:57:55.698869 CBT Training : PASS
4811 09:57:55.698950 Write leveling : PASS
4812 09:57:55.701746 RX DQS gating : PASS
4813 09:57:55.705267 RX DQ/DQS(RDDQC) : PASS
4814 09:57:55.705348 TX DQ/DQS : PASS
4815 09:57:55.708230 RX DATLAT : PASS
4816 09:57:55.708311 RX DQ/DQS(Engine): PASS
4817 09:57:55.711871 TX OE : NO K
4818 09:57:55.711953 All Pass.
4819 09:57:55.712017
4820 09:57:55.715301 CH 1, Rank 1
4821 09:57:55.718816 SW Impedance : PASS
4822 09:57:55.718897 DUTY Scan : NO K
4823 09:57:55.721504 ZQ Calibration : PASS
4824 09:57:55.721585 Jitter Meter : NO K
4825 09:57:55.724644 CBT Training : PASS
4826 09:57:55.728272 Write leveling : PASS
4827 09:57:55.728353 RX DQS gating : PASS
4828 09:57:55.731110 RX DQ/DQS(RDDQC) : PASS
4829 09:57:55.734553 TX DQ/DQS : PASS
4830 09:57:55.734635 RX DATLAT : PASS
4831 09:57:55.738067 RX DQ/DQS(Engine): PASS
4832 09:57:55.741097 TX OE : NO K
4833 09:57:55.741179 All Pass.
4834 09:57:55.741243
4835 09:57:55.744211 DramC Write-DBI off
4836 09:57:55.744292 PER_BANK_REFRESH: Hybrid Mode
4837 09:57:55.747842 TX_TRACKING: ON
4838 09:57:55.757618 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4839 09:57:55.761075 [FAST_K] Save calibration result to emmc
4840 09:57:55.763983 dramc_set_vcore_voltage set vcore to 662500
4841 09:57:55.764058 Read voltage for 933, 3
4842 09:57:55.767742 Vio18 = 0
4843 09:57:55.767818 Vcore = 662500
4844 09:57:55.767887 Vdram = 0
4845 09:57:55.771320 Vddq = 0
4846 09:57:55.771419 Vmddr = 0
4847 09:57:55.777370 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4848 09:57:55.780860 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4849 09:57:55.784199 MEM_TYPE=3, freq_sel=17
4850 09:57:55.787085 sv_algorithm_assistance_LP4_1600
4851 09:57:55.790383 ============ PULL DRAM RESETB DOWN ============
4852 09:57:55.793549 ========== PULL DRAM RESETB DOWN end =========
4853 09:57:55.800379 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4854 09:57:55.804260 ===================================
4855 09:57:55.804334 LPDDR4 DRAM CONFIGURATION
4856 09:57:55.807483 ===================================
4857 09:57:55.810547 EX_ROW_EN[0] = 0x0
4858 09:57:55.813593 EX_ROW_EN[1] = 0x0
4859 09:57:55.813694 LP4Y_EN = 0x0
4860 09:57:55.817230 WORK_FSP = 0x0
4861 09:57:55.817325 WL = 0x3
4862 09:57:55.820561 RL = 0x3
4863 09:57:55.820664 BL = 0x2
4864 09:57:55.823280 RPST = 0x0
4865 09:57:55.823358 RD_PRE = 0x0
4866 09:57:55.826718 WR_PRE = 0x1
4867 09:57:55.826787 WR_PST = 0x0
4868 09:57:55.830302 DBI_WR = 0x0
4869 09:57:55.830386 DBI_RD = 0x0
4870 09:57:55.833519 OTF = 0x1
4871 09:57:55.836879 ===================================
4872 09:57:55.839884 ===================================
4873 09:57:55.839955 ANA top config
4874 09:57:55.843251 ===================================
4875 09:57:55.846535 DLL_ASYNC_EN = 0
4876 09:57:55.850485 ALL_SLAVE_EN = 1
4877 09:57:55.853466 NEW_RANK_MODE = 1
4878 09:57:55.853565 DLL_IDLE_MODE = 1
4879 09:57:55.856555 LP45_APHY_COMB_EN = 1
4880 09:57:55.859766 TX_ODT_DIS = 1
4881 09:57:55.863154 NEW_8X_MODE = 1
4882 09:57:55.866279 ===================================
4883 09:57:55.869620 ===================================
4884 09:57:55.873010 data_rate = 1866
4885 09:57:55.873092 CKR = 1
4886 09:57:55.876188 DQ_P2S_RATIO = 8
4887 09:57:55.879589 ===================================
4888 09:57:55.883032 CA_P2S_RATIO = 8
4889 09:57:55.886098 DQ_CA_OPEN = 0
4890 09:57:55.889644 DQ_SEMI_OPEN = 0
4891 09:57:55.892708 CA_SEMI_OPEN = 0
4892 09:57:55.892821 CA_FULL_RATE = 0
4893 09:57:55.896152 DQ_CKDIV4_EN = 1
4894 09:57:55.899753 CA_CKDIV4_EN = 1
4895 09:57:55.902521 CA_PREDIV_EN = 0
4896 09:57:55.906553 PH8_DLY = 0
4897 09:57:55.909586 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4898 09:57:55.909701 DQ_AAMCK_DIV = 4
4899 09:57:55.912899 CA_AAMCK_DIV = 4
4900 09:57:55.916120 CA_ADMCK_DIV = 4
4901 09:57:55.919348 DQ_TRACK_CA_EN = 0
4902 09:57:55.922813 CA_PICK = 933
4903 09:57:55.925989 CA_MCKIO = 933
4904 09:57:55.929411 MCKIO_SEMI = 0
4905 09:57:55.929492 PLL_FREQ = 3732
4906 09:57:55.932475 DQ_UI_PI_RATIO = 32
4907 09:57:55.935846 CA_UI_PI_RATIO = 0
4908 09:57:55.939273 ===================================
4909 09:57:55.942434 ===================================
4910 09:57:55.945885 memory_type:LPDDR4
4911 09:57:55.948913 GP_NUM : 10
4912 09:57:55.948993 SRAM_EN : 1
4913 09:57:55.952625 MD32_EN : 0
4914 09:57:55.955441 ===================================
4915 09:57:55.958906 [ANA_INIT] >>>>>>>>>>>>>>
4916 09:57:55.958987 <<<<<< [CONFIGURE PHASE]: ANA_TX
4917 09:57:55.962161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4918 09:57:55.965280 ===================================
4919 09:57:55.968608 data_rate = 1866,PCW = 0X8f00
4920 09:57:55.972261 ===================================
4921 09:57:55.975502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4922 09:57:55.981808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 09:57:55.988206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 09:57:55.991643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4925 09:57:55.994875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4926 09:57:55.998433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4927 09:57:56.001556 [ANA_INIT] flow start
4928 09:57:56.001637 [ANA_INIT] PLL >>>>>>>>
4929 09:57:56.004949 [ANA_INIT] PLL <<<<<<<<
4930 09:57:56.008267 [ANA_INIT] MIDPI >>>>>>>>
4931 09:57:56.011649 [ANA_INIT] MIDPI <<<<<<<<
4932 09:57:56.011730 [ANA_INIT] DLL >>>>>>>>
4933 09:57:56.014636 [ANA_INIT] flow end
4934 09:57:56.017831 ============ LP4 DIFF to SE enter ============
4935 09:57:56.021567 ============ LP4 DIFF to SE exit ============
4936 09:57:56.024972 [ANA_INIT] <<<<<<<<<<<<<
4937 09:57:56.028537 [Flow] Enable top DCM control >>>>>
4938 09:57:56.030992 [Flow] Enable top DCM control <<<<<
4939 09:57:56.034470 Enable DLL master slave shuffle
4940 09:57:56.040852 ==============================================================
4941 09:57:56.040934 Gating Mode config
4942 09:57:56.047898 ==============================================================
4943 09:57:56.047979 Config description:
4944 09:57:56.057608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4945 09:57:56.064003 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4946 09:57:56.070716 SELPH_MODE 0: By rank 1: By Phase
4947 09:57:56.077501 ==============================================================
4948 09:57:56.077583 GAT_TRACK_EN = 1
4949 09:57:56.080386 RX_GATING_MODE = 2
4950 09:57:56.083992 RX_GATING_TRACK_MODE = 2
4951 09:57:56.087172 SELPH_MODE = 1
4952 09:57:56.090927 PICG_EARLY_EN = 1
4953 09:57:56.093682 VALID_LAT_VALUE = 1
4954 09:57:56.100243 ==============================================================
4955 09:57:56.103862 Enter into Gating configuration >>>>
4956 09:57:56.107132 Exit from Gating configuration <<<<
4957 09:57:56.110206 Enter into DVFS_PRE_config >>>>>
4958 09:57:56.120557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4959 09:57:56.123489 Exit from DVFS_PRE_config <<<<<
4960 09:57:56.126621 Enter into PICG configuration >>>>
4961 09:57:56.130363 Exit from PICG configuration <<<<
4962 09:57:56.133360 [RX_INPUT] configuration >>>>>
4963 09:57:56.136617 [RX_INPUT] configuration <<<<<
4964 09:57:56.139720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4965 09:57:56.146498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4966 09:57:56.153221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 09:57:56.159920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 09:57:56.163300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 09:57:56.169870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 09:57:56.172848 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4971 09:57:56.179028 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4972 09:57:56.182842 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4973 09:57:56.185841 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4974 09:57:56.189293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4975 09:57:56.195554 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 09:57:56.198858 ===================================
4977 09:57:56.202527 LPDDR4 DRAM CONFIGURATION
4978 09:57:56.205638 ===================================
4979 09:57:56.205719 EX_ROW_EN[0] = 0x0
4980 09:57:56.209025 EX_ROW_EN[1] = 0x0
4981 09:57:56.209106 LP4Y_EN = 0x0
4982 09:57:56.212328 WORK_FSP = 0x0
4983 09:57:56.212409 WL = 0x3
4984 09:57:56.215588 RL = 0x3
4985 09:57:56.215669 BL = 0x2
4986 09:57:56.218973 RPST = 0x0
4987 09:57:56.219054 RD_PRE = 0x0
4988 09:57:56.222054 WR_PRE = 0x1
4989 09:57:56.222135 WR_PST = 0x0
4990 09:57:56.225464 DBI_WR = 0x0
4991 09:57:56.225545 DBI_RD = 0x0
4992 09:57:56.228470 OTF = 0x1
4993 09:57:56.231841 ===================================
4994 09:57:56.235963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4995 09:57:56.239610 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4996 09:57:56.245364 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 09:57:56.248454 ===================================
4998 09:57:56.252194 LPDDR4 DRAM CONFIGURATION
4999 09:57:56.255253 ===================================
5000 09:57:56.255335 EX_ROW_EN[0] = 0x10
5001 09:57:56.258361 EX_ROW_EN[1] = 0x0
5002 09:57:56.258442 LP4Y_EN = 0x0
5003 09:57:56.262075 WORK_FSP = 0x0
5004 09:57:56.262156 WL = 0x3
5005 09:57:56.265030 RL = 0x3
5006 09:57:56.265111 BL = 0x2
5007 09:57:56.268741 RPST = 0x0
5008 09:57:56.268823 RD_PRE = 0x0
5009 09:57:56.271953 WR_PRE = 0x1
5010 09:57:56.272034 WR_PST = 0x0
5011 09:57:56.274684 DBI_WR = 0x0
5012 09:57:56.278200 DBI_RD = 0x0
5013 09:57:56.278321 OTF = 0x1
5014 09:57:56.281682 ===================================
5015 09:57:56.288455 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5016 09:57:56.291365 nWR fixed to 30
5017 09:57:56.295003 [ModeRegInit_LP4] CH0 RK0
5018 09:57:56.295107 [ModeRegInit_LP4] CH0 RK1
5019 09:57:56.298197 [ModeRegInit_LP4] CH1 RK0
5020 09:57:56.301650 [ModeRegInit_LP4] CH1 RK1
5021 09:57:56.301731 match AC timing 9
5022 09:57:56.308135 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5023 09:57:56.311624 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5024 09:57:56.314828 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5025 09:57:56.321055 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5026 09:57:56.324930 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5027 09:57:56.325012 ==
5028 09:57:56.327925 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 09:57:56.331737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5030 09:57:56.331818 ==
5031 09:57:56.337708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5032 09:57:56.344595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5033 09:57:56.347886 [CA 0] Center 37 (7~68) winsize 62
5034 09:57:56.350918 [CA 1] Center 37 (7~68) winsize 62
5035 09:57:56.354558 [CA 2] Center 34 (4~64) winsize 61
5036 09:57:56.357539 [CA 3] Center 34 (3~65) winsize 63
5037 09:57:56.360958 [CA 4] Center 33 (3~64) winsize 62
5038 09:57:56.364432 [CA 5] Center 32 (2~63) winsize 62
5039 09:57:56.364513
5040 09:57:56.367285 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5041 09:57:56.367366
5042 09:57:56.370912 [CATrainingPosCal] consider 1 rank data
5043 09:57:56.374154 u2DelayCellTimex100 = 270/100 ps
5044 09:57:56.377396 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 09:57:56.380824 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 09:57:56.384327 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5047 09:57:56.390791 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5048 09:57:56.394124 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5049 09:57:56.396996 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5050 09:57:56.397078
5051 09:57:56.400946 CA PerBit enable=1, Macro0, CA PI delay=32
5052 09:57:56.401027
5053 09:57:56.403558 [CBTSetCACLKResult] CA Dly = 32
5054 09:57:56.403639 CS Dly: 5 (0~36)
5055 09:57:56.403703 ==
5056 09:57:56.407460 Dram Type= 6, Freq= 0, CH_0, rank 1
5057 09:57:56.413740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 09:57:56.413821 ==
5059 09:57:56.416791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 09:57:56.423338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5061 09:57:56.426943 [CA 0] Center 38 (7~69) winsize 63
5062 09:57:56.430414 [CA 1] Center 37 (7~68) winsize 62
5063 09:57:56.433527 [CA 2] Center 34 (4~65) winsize 62
5064 09:57:56.436801 [CA 3] Center 34 (4~65) winsize 62
5065 09:57:56.439959 [CA 4] Center 33 (3~64) winsize 62
5066 09:57:56.443597 [CA 5] Center 32 (2~63) winsize 62
5067 09:57:56.443679
5068 09:57:56.446989 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5069 09:57:56.447070
5070 09:57:56.449781 [CATrainingPosCal] consider 2 rank data
5071 09:57:56.453512 u2DelayCellTimex100 = 270/100 ps
5072 09:57:56.456708 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 09:57:56.462869 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 09:57:56.466652 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5075 09:57:56.469647 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 09:57:56.473015 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5077 09:57:56.476277 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5078 09:57:56.476358
5079 09:57:56.480082 CA PerBit enable=1, Macro0, CA PI delay=32
5080 09:57:56.480163
5081 09:57:56.482899 [CBTSetCACLKResult] CA Dly = 32
5082 09:57:56.486132 CS Dly: 6 (0~38)
5083 09:57:56.486213
5084 09:57:56.489751 ----->DramcWriteLeveling(PI) begin...
5085 09:57:56.489833 ==
5086 09:57:56.492551 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 09:57:56.495862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 09:57:56.495945 ==
5089 09:57:56.499467 Write leveling (Byte 0): 33 => 33
5090 09:57:56.502515 Write leveling (Byte 1): 28 => 28
5091 09:57:56.506050 DramcWriteLeveling(PI) end<-----
5092 09:57:56.506131
5093 09:57:56.506195 ==
5094 09:57:56.509280 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 09:57:56.512345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 09:57:56.512427 ==
5097 09:57:56.515865 [Gating] SW mode calibration
5098 09:57:56.522365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5099 09:57:56.529129 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5100 09:57:56.532633 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5101 09:57:56.538610 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 09:57:56.542550 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 09:57:56.545550 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 09:57:56.551992 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 09:57:56.555453 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 09:57:56.558462 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5107 09:57:56.565030 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
5108 09:57:56.568671 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5109 09:57:56.571978 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 09:57:56.578373 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 09:57:56.581729 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 09:57:56.584889 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 09:57:56.591786 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 09:57:56.594781 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5115 09:57:56.598230 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5116 09:57:56.604806 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5117 09:57:56.608060 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 09:57:56.611645 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 09:57:56.614831 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 09:57:56.621458 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 09:57:56.624379 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 09:57:56.631357 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 09:57:56.634475 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5124 09:57:56.637931 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 09:57:56.644334 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 09:57:56.647549 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 09:57:56.650962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 09:57:56.654306 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 09:57:56.661091 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 09:57:56.664849 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 09:57:56.667611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 09:57:56.674496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 09:57:56.677719 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 09:57:56.680684 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 09:57:56.687186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 09:57:56.690395 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 09:57:56.693729 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 09:57:56.700938 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 09:57:56.704026 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 09:57:56.707111 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 09:57:56.710882 Total UI for P1: 0, mck2ui 16
5142 09:57:56.713783 best dqsien dly found for B0: ( 1, 2, 28)
5143 09:57:56.720293 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 09:57:56.723702 Total UI for P1: 0, mck2ui 16
5145 09:57:56.727015 best dqsien dly found for B1: ( 1, 3, 0)
5146 09:57:56.730168 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5147 09:57:56.733653 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5148 09:57:56.733734
5149 09:57:56.737099 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5150 09:57:56.740182 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5151 09:57:56.743215 [Gating] SW calibration Done
5152 09:57:56.743296 ==
5153 09:57:56.746688 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 09:57:56.750372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 09:57:56.750454 ==
5156 09:57:56.753820 RX Vref Scan: 0
5157 09:57:56.753918
5158 09:57:56.756468 RX Vref 0 -> 0, step: 1
5159 09:57:56.756549
5160 09:57:56.756613 RX Delay -80 -> 252, step: 8
5161 09:57:56.763305 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5162 09:57:56.766454 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5163 09:57:56.769731 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5164 09:57:56.773052 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5165 09:57:56.776216 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5166 09:57:56.779572 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5167 09:57:56.786244 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5168 09:57:56.789220 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5169 09:57:56.792677 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5170 09:57:56.796041 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5171 09:57:56.799587 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5172 09:57:56.806231 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5173 09:57:56.809371 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5174 09:57:56.812556 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5175 09:57:56.815823 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5176 09:57:56.819211 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5177 09:57:56.819292 ==
5178 09:57:56.822235 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 09:57:56.829064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 09:57:56.829146 ==
5181 09:57:56.829210 DQS Delay:
5182 09:57:56.832479 DQS0 = 0, DQS1 = 0
5183 09:57:56.832560 DQM Delay:
5184 09:57:56.835787 DQM0 = 101, DQM1 = 90
5185 09:57:56.835868 DQ Delay:
5186 09:57:56.838822 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5187 09:57:56.842122 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5188 09:57:56.845616 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5189 09:57:56.848845 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5190 09:57:56.848926
5191 09:57:56.848990
5192 09:57:56.849049 ==
5193 09:57:56.852028 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 09:57:56.855326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 09:57:56.855408 ==
5196 09:57:56.855473
5197 09:57:56.858505
5198 09:57:56.858586 TX Vref Scan disable
5199 09:57:56.861988 == TX Byte 0 ==
5200 09:57:56.865265 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5201 09:57:56.868915 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5202 09:57:56.872217 == TX Byte 1 ==
5203 09:57:56.875630 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5204 09:57:56.878434 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5205 09:57:56.878515 ==
5206 09:57:56.881732 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 09:57:56.888043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 09:57:56.888125 ==
5209 09:57:56.888190
5210 09:57:56.888250
5211 09:57:56.891406 TX Vref Scan disable
5212 09:57:56.891487 == TX Byte 0 ==
5213 09:57:56.898208 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5214 09:57:56.901463 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5215 09:57:56.901544 == TX Byte 1 ==
5216 09:57:56.908068 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5217 09:57:56.911409 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5218 09:57:56.911490
5219 09:57:56.911555 [DATLAT]
5220 09:57:56.914414 Freq=933, CH0 RK0
5221 09:57:56.914495
5222 09:57:56.914560 DATLAT Default: 0xd
5223 09:57:56.917922 0, 0xFFFF, sum = 0
5224 09:57:56.918004 1, 0xFFFF, sum = 0
5225 09:57:56.921300 2, 0xFFFF, sum = 0
5226 09:57:56.921383 3, 0xFFFF, sum = 0
5227 09:57:56.924848 4, 0xFFFF, sum = 0
5228 09:57:56.924930 5, 0xFFFF, sum = 0
5229 09:57:56.927574 6, 0xFFFF, sum = 0
5230 09:57:56.931386 7, 0xFFFF, sum = 0
5231 09:57:56.931468 8, 0xFFFF, sum = 0
5232 09:57:56.934145 9, 0xFFFF, sum = 0
5233 09:57:56.934228 10, 0x0, sum = 1
5234 09:57:56.934335 11, 0x0, sum = 2
5235 09:57:56.937767 12, 0x0, sum = 3
5236 09:57:56.937895 13, 0x0, sum = 4
5237 09:57:56.941153 best_step = 11
5238 09:57:56.941234
5239 09:57:56.941299 ==
5240 09:57:56.944564 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 09:57:56.947623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 09:57:56.947705 ==
5243 09:57:56.950499 RX Vref Scan: 1
5244 09:57:56.950580
5245 09:57:56.954248 RX Vref 0 -> 0, step: 1
5246 09:57:56.954350
5247 09:57:56.954415 RX Delay -53 -> 252, step: 4
5248 09:57:56.954477
5249 09:57:56.957287 Set Vref, RX VrefLevel [Byte0]: 57
5250 09:57:56.960562 [Byte1]: 59
5251 09:57:56.965225
5252 09:57:56.965305 Final RX Vref Byte 0 = 57 to rank0
5253 09:57:56.968895 Final RX Vref Byte 1 = 59 to rank0
5254 09:57:56.971625 Final RX Vref Byte 0 = 57 to rank1
5255 09:57:56.975409 Final RX Vref Byte 1 = 59 to rank1==
5256 09:57:56.978374 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 09:57:56.984991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 09:57:56.985120 ==
5259 09:57:56.985209 DQS Delay:
5260 09:57:56.988110 DQS0 = 0, DQS1 = 0
5261 09:57:56.988201 DQM Delay:
5262 09:57:56.988267 DQM0 = 98, DQM1 = 88
5263 09:57:56.991414 DQ Delay:
5264 09:57:56.994681 DQ0 =100, DQ1 =100, DQ2 =92, DQ3 =94
5265 09:57:56.998480 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =104
5266 09:57:57.001484 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =84
5267 09:57:57.004924 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5268 09:57:57.005006
5269 09:57:57.005071
5270 09:57:57.011608 [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5271 09:57:57.014845 CH0 RK0: MR19=505, MR18=1711
5272 09:57:57.021544 CH0_RK0: MR19=0x505, MR18=0x1711, DQSOSC=414, MR23=63, INC=63, DEC=42
5273 09:57:57.021626
5274 09:57:57.024575 ----->DramcWriteLeveling(PI) begin...
5275 09:57:57.024657 ==
5276 09:57:57.027866 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 09:57:57.031071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 09:57:57.031153 ==
5279 09:57:57.034358 Write leveling (Byte 0): 30 => 30
5280 09:57:57.037385 Write leveling (Byte 1): 29 => 29
5281 09:57:57.040907 DramcWriteLeveling(PI) end<-----
5282 09:57:57.040988
5283 09:57:57.041052 ==
5284 09:57:57.044470 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 09:57:57.050564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 09:57:57.050646 ==
5287 09:57:57.050711 [Gating] SW mode calibration
5288 09:57:57.060842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5289 09:57:57.064632 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5290 09:57:57.070404 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5291 09:57:57.073905 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 09:57:57.077562 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 09:57:57.083960 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 09:57:57.087481 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 09:57:57.090765 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 09:57:57.096856 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5297 09:57:57.100093 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5298 09:57:57.103654 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5299 09:57:57.110378 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 09:57:57.113728 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 09:57:57.116600 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 09:57:57.123433 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 09:57:57.126636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 09:57:57.129979 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5305 09:57:57.136445 0 15 28 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (0 0)
5306 09:57:57.139863 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5307 09:57:57.143216 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 09:57:57.149656 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 09:57:57.153262 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 09:57:57.156137 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 09:57:57.162989 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 09:57:57.166076 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5313 09:57:57.169459 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5314 09:57:57.176107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5315 09:57:57.179315 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 09:57:57.182580 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 09:57:57.189069 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 09:57:57.192797 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 09:57:57.196040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 09:57:57.202378 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 09:57:57.206144 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 09:57:57.208915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 09:57:57.215823 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 09:57:57.218797 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 09:57:57.222605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 09:57:57.229000 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 09:57:57.232230 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 09:57:57.235702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 09:57:57.242491 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5330 09:57:57.245237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5331 09:57:57.248727 Total UI for P1: 0, mck2ui 16
5332 09:57:57.252089 best dqsien dly found for B0: ( 1, 2, 28)
5333 09:57:57.255351 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 09:57:57.258678 Total UI for P1: 0, mck2ui 16
5335 09:57:57.261875 best dqsien dly found for B1: ( 1, 3, 0)
5336 09:57:57.265173 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 09:57:57.268239 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5338 09:57:57.268319
5339 09:57:57.271858 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 09:57:57.278746 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5341 09:57:57.278829 [Gating] SW calibration Done
5342 09:57:57.278912 ==
5343 09:57:57.281617 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 09:57:57.288091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 09:57:57.288174 ==
5346 09:57:57.288239 RX Vref Scan: 0
5347 09:57:57.288315
5348 09:57:57.291170 RX Vref 0 -> 0, step: 1
5349 09:57:57.291251
5350 09:57:57.294629 RX Delay -80 -> 252, step: 8
5351 09:57:57.297764 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5352 09:57:57.301243 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5353 09:57:57.304606 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5354 09:57:57.308037 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5355 09:57:57.314651 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5356 09:57:57.317887 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5357 09:57:57.321055 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5358 09:57:57.324203 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5359 09:57:57.327702 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5360 09:57:57.334164 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5361 09:57:57.337914 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5362 09:57:57.340582 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 09:57:57.344208 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5364 09:57:57.347552 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5365 09:57:57.350455 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5366 09:57:57.357056 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 09:57:57.357158 ==
5368 09:57:57.360651 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 09:57:57.363758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 09:57:57.363830 ==
5371 09:57:57.363897 DQS Delay:
5372 09:57:57.367392 DQS0 = 0, DQS1 = 0
5373 09:57:57.367462 DQM Delay:
5374 09:57:57.370028 DQM0 = 98, DQM1 = 91
5375 09:57:57.370123 DQ Delay:
5376 09:57:57.373772 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5377 09:57:57.377098 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5378 09:57:57.380449 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5379 09:57:57.383268 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5380 09:57:57.383344
5381 09:57:57.383420
5382 09:57:57.383479 ==
5383 09:57:57.386746 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 09:57:57.393509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 09:57:57.393618 ==
5386 09:57:57.393710
5387 09:57:57.393797
5388 09:57:57.393895 TX Vref Scan disable
5389 09:57:57.396734 == TX Byte 0 ==
5390 09:57:57.400177 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5391 09:57:57.406445 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5392 09:57:57.406520 == TX Byte 1 ==
5393 09:57:57.409779 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5394 09:57:57.416015 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5395 09:57:57.416100 ==
5396 09:57:57.419222 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 09:57:57.422553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 09:57:57.422642 ==
5399 09:57:57.422707
5400 09:57:57.422766
5401 09:57:57.426049 TX Vref Scan disable
5402 09:57:57.429826 == TX Byte 0 ==
5403 09:57:57.432907 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5404 09:57:57.436207 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5405 09:57:57.439273 == TX Byte 1 ==
5406 09:57:57.442316 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5407 09:57:57.445681 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5408 09:57:57.445762
5409 09:57:57.445826 [DATLAT]
5410 09:57:57.449044 Freq=933, CH0 RK1
5411 09:57:57.449125
5412 09:57:57.452320 DATLAT Default: 0xb
5413 09:57:57.452401 0, 0xFFFF, sum = 0
5414 09:57:57.455925 1, 0xFFFF, sum = 0
5415 09:57:57.456008 2, 0xFFFF, sum = 0
5416 09:57:57.459539 3, 0xFFFF, sum = 0
5417 09:57:57.459622 4, 0xFFFF, sum = 0
5418 09:57:57.462422 5, 0xFFFF, sum = 0
5419 09:57:57.462504 6, 0xFFFF, sum = 0
5420 09:57:57.465550 7, 0xFFFF, sum = 0
5421 09:57:57.465632 8, 0xFFFF, sum = 0
5422 09:57:57.469517 9, 0xFFFF, sum = 0
5423 09:57:57.469599 10, 0x0, sum = 1
5424 09:57:57.472552 11, 0x0, sum = 2
5425 09:57:57.472634 12, 0x0, sum = 3
5426 09:57:57.475589 13, 0x0, sum = 4
5427 09:57:57.475687 best_step = 11
5428 09:57:57.475752
5429 09:57:57.475812 ==
5430 09:57:57.479037 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 09:57:57.482513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 09:57:57.485522 ==
5433 09:57:57.485598 RX Vref Scan: 0
5434 09:57:57.485661
5435 09:57:57.488773 RX Vref 0 -> 0, step: 1
5436 09:57:57.488869
5437 09:57:57.492367 RX Delay -53 -> 252, step: 4
5438 09:57:57.495746 iDelay=199, Bit 0, Center 98 (11 ~ 186) 176
5439 09:57:57.498694 iDelay=199, Bit 1, Center 102 (11 ~ 194) 184
5440 09:57:57.502133 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5441 09:57:57.508682 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5442 09:57:57.511692 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5443 09:57:57.514856 iDelay=199, Bit 5, Center 88 (-1 ~ 178) 180
5444 09:57:57.518241 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5445 09:57:57.521567 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5446 09:57:57.528238 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5447 09:57:57.531527 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5448 09:57:57.534574 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5449 09:57:57.537953 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5450 09:57:57.541417 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5451 09:57:57.547868 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5452 09:57:57.551248 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5453 09:57:57.554984 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5454 09:57:57.555059 ==
5455 09:57:57.557788 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 09:57:57.561540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 09:57:57.561639 ==
5458 09:57:57.564370 DQS Delay:
5459 09:57:57.564469 DQS0 = 0, DQS1 = 0
5460 09:57:57.567935 DQM Delay:
5461 09:57:57.568020 DQM0 = 98, DQM1 = 89
5462 09:57:57.568082 DQ Delay:
5463 09:57:57.571211 DQ0 =98, DQ1 =102, DQ2 =92, DQ3 =94
5464 09:57:57.574446 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =104
5465 09:57:57.577652 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5466 09:57:57.584347 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5467 09:57:57.584423
5468 09:57:57.584499
5469 09:57:57.590977 [DQSOSCAuto] RK1, (LSB)MR18= 0x1612, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5470 09:57:57.594200 CH0 RK1: MR19=505, MR18=1612
5471 09:57:57.600681 CH0_RK1: MR19=0x505, MR18=0x1612, DQSOSC=414, MR23=63, INC=63, DEC=42
5472 09:57:57.604044 [RxdqsGatingPostProcess] freq 933
5473 09:57:57.607350 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 09:57:57.610577 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 09:57:57.614001 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 09:57:57.617043 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 09:57:57.620358 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 09:57:57.624116 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 09:57:57.626867 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 09:57:57.630238 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 09:57:57.633710 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 09:57:57.636784 Pre-setting of DQS Precalculation
5483 09:57:57.640325 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 09:57:57.640425 ==
5485 09:57:57.643521 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 09:57:57.649888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 09:57:57.649994 ==
5488 09:57:57.653397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 09:57:57.659952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5490 09:57:57.663729 [CA 0] Center 36 (6~67) winsize 62
5491 09:57:57.666731 [CA 1] Center 36 (5~67) winsize 63
5492 09:57:57.670067 [CA 2] Center 34 (4~65) winsize 62
5493 09:57:57.673420 [CA 3] Center 34 (3~65) winsize 63
5494 09:57:57.676569 [CA 4] Center 34 (4~65) winsize 62
5495 09:57:57.679872 [CA 5] Center 33 (3~64) winsize 62
5496 09:57:57.679968
5497 09:57:57.683248 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5498 09:57:57.683343
5499 09:57:57.686494 [CATrainingPosCal] consider 1 rank data
5500 09:57:57.689778 u2DelayCellTimex100 = 270/100 ps
5501 09:57:57.693114 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 09:57:57.699682 CA1 delay=36 (5~67),Diff = 3 PI (18 cell)
5503 09:57:57.703079 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 09:57:57.706179 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5505 09:57:57.709488 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 09:57:57.713370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 09:57:57.713479
5508 09:57:57.716501 CA PerBit enable=1, Macro0, CA PI delay=33
5509 09:57:57.716606
5510 09:57:57.719387 [CBTSetCACLKResult] CA Dly = 33
5511 09:57:57.723074 CS Dly: 5 (0~36)
5512 09:57:57.723153 ==
5513 09:57:57.726032 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 09:57:57.729271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 09:57:57.729348 ==
5516 09:57:57.736185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 09:57:57.739328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 09:57:57.743246 [CA 0] Center 36 (6~67) winsize 62
5519 09:57:57.746631 [CA 1] Center 36 (6~67) winsize 62
5520 09:57:57.750178 [CA 2] Center 34 (4~64) winsize 61
5521 09:57:57.753445 [CA 3] Center 33 (3~64) winsize 62
5522 09:57:57.756331 [CA 4] Center 33 (3~64) winsize 62
5523 09:57:57.759855 [CA 5] Center 33 (3~64) winsize 62
5524 09:57:57.759953
5525 09:57:57.763022 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 09:57:57.763095
5527 09:57:57.766245 [CATrainingPosCal] consider 2 rank data
5528 09:57:57.769348 u2DelayCellTimex100 = 270/100 ps
5529 09:57:57.775950 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 09:57:57.779739 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 09:57:57.782578 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5532 09:57:57.785949 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5533 09:57:57.789004 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 09:57:57.793098 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 09:57:57.793177
5536 09:57:57.795692 CA PerBit enable=1, Macro0, CA PI delay=33
5537 09:57:57.795768
5538 09:57:57.799353 [CBTSetCACLKResult] CA Dly = 33
5539 09:57:57.802520 CS Dly: 6 (0~38)
5540 09:57:57.802611
5541 09:57:57.806407 ----->DramcWriteLeveling(PI) begin...
5542 09:57:57.806496 ==
5543 09:57:57.809591 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 09:57:57.812433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 09:57:57.812538 ==
5546 09:57:57.815414 Write leveling (Byte 0): 27 => 27
5547 09:57:57.819054 Write leveling (Byte 1): 28 => 28
5548 09:57:57.822567 DramcWriteLeveling(PI) end<-----
5549 09:57:57.822644
5550 09:57:57.822707 ==
5551 09:57:57.826053 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 09:57:57.828932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 09:57:57.829042 ==
5554 09:57:57.832405 [Gating] SW mode calibration
5555 09:57:57.839041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 09:57:57.845590 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 09:57:57.848723 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 09:57:57.855197 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 09:57:57.858391 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 09:57:57.861884 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 09:57:57.868435 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 09:57:57.871449 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 09:57:57.874758 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5564 09:57:57.881884 0 14 28 | B1->B0 | 2828 2525 | 0 0 | (1 1) (1 0)
5565 09:57:57.884918 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5566 09:57:57.888261 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 09:57:57.894601 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 09:57:57.898387 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 09:57:57.901012 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 09:57:57.907906 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 09:57:57.911404 0 15 24 | B1->B0 | 2525 2525 | 1 0 | (0 0) (0 0)
5572 09:57:57.914596 0 15 28 | B1->B0 | 3a3a 3c3c | 0 0 | (1 1) (1 1)
5573 09:57:57.921057 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 09:57:57.924591 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 09:57:57.927937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 09:57:57.933890 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 09:57:57.937360 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 09:57:57.940569 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 09:57:57.947078 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 09:57:57.950773 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 09:57:57.954141 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 09:57:57.960412 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 09:57:57.963986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 09:57:57.967263 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 09:57:57.973495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 09:57:57.976650 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 09:57:57.980235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 09:57:57.986472 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 09:57:57.990067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 09:57:57.993464 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 09:57:58.000018 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 09:57:58.003243 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 09:57:58.006670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 09:57:58.012806 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 09:57:58.016548 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 09:57:58.019601 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 09:57:58.026050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5598 09:57:58.026132 Total UI for P1: 0, mck2ui 16
5599 09:57:58.032649 best dqsien dly found for B0: ( 1, 2, 28)
5600 09:57:58.036099 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 09:57:58.039250 Total UI for P1: 0, mck2ui 16
5602 09:57:58.042750 best dqsien dly found for B1: ( 1, 2, 30)
5603 09:57:58.045967 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5604 09:57:58.048948 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5605 09:57:58.049076
5606 09:57:58.052672 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5607 09:57:58.055874 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5608 09:57:58.058719 [Gating] SW calibration Done
5609 09:57:58.058854 ==
5610 09:57:58.062712 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 09:57:58.068935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 09:57:58.069034 ==
5613 09:57:58.069100 RX Vref Scan: 0
5614 09:57:58.069162
5615 09:57:58.072455 RX Vref 0 -> 0, step: 1
5616 09:57:58.072538
5617 09:57:58.075681 RX Delay -80 -> 252, step: 8
5618 09:57:58.078941 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5619 09:57:58.082392 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5620 09:57:58.085511 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5621 09:57:58.088767 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5622 09:57:58.095249 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5623 09:57:58.098488 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5624 09:57:58.101879 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5625 09:57:58.104860 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5626 09:57:58.108364 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5627 09:57:58.112061 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5628 09:57:58.118207 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5629 09:57:58.121598 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5630 09:57:58.125230 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5631 09:57:58.128251 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5632 09:57:58.131856 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5633 09:57:58.137991 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5634 09:57:58.138074 ==
5635 09:57:58.141580 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 09:57:58.144644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 09:57:58.144727 ==
5638 09:57:58.144793 DQS Delay:
5639 09:57:58.148655 DQS0 = 0, DQS1 = 0
5640 09:57:58.148736 DQM Delay:
5641 09:57:58.151057 DQM0 = 99, DQM1 = 95
5642 09:57:58.151138 DQ Delay:
5643 09:57:58.154270 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5644 09:57:58.157592 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5645 09:57:58.160859 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5646 09:57:58.164526 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5647 09:57:58.164608
5648 09:57:58.164673
5649 09:57:58.164732 ==
5650 09:57:58.167585 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 09:57:58.174227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 09:57:58.174349 ==
5653 09:57:58.174413
5654 09:57:58.174472
5655 09:57:58.174529 TX Vref Scan disable
5656 09:57:58.177808 == TX Byte 0 ==
5657 09:57:58.181089 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5658 09:57:58.187889 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5659 09:57:58.187969 == TX Byte 1 ==
5660 09:57:58.190828 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5661 09:57:58.197691 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5662 09:57:58.197771 ==
5663 09:57:58.200835 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 09:57:58.204171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 09:57:58.204252 ==
5666 09:57:58.204316
5667 09:57:58.204376
5668 09:57:58.207684 TX Vref Scan disable
5669 09:57:58.210733 == TX Byte 0 ==
5670 09:57:58.214791 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5671 09:57:58.217223 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5672 09:57:58.220636 == TX Byte 1 ==
5673 09:57:58.223884 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 09:57:58.227039 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 09:57:58.227119
5676 09:57:58.227186 [DATLAT]
5677 09:57:58.230548 Freq=933, CH1 RK0
5678 09:57:58.230628
5679 09:57:58.233772 DATLAT Default: 0xd
5680 09:57:58.233852 0, 0xFFFF, sum = 0
5681 09:57:58.237381 1, 0xFFFF, sum = 0
5682 09:57:58.237462 2, 0xFFFF, sum = 0
5683 09:57:58.240640 3, 0xFFFF, sum = 0
5684 09:57:58.240722 4, 0xFFFF, sum = 0
5685 09:57:58.243642 5, 0xFFFF, sum = 0
5686 09:57:58.243723 6, 0xFFFF, sum = 0
5687 09:57:58.247352 7, 0xFFFF, sum = 0
5688 09:57:58.247434 8, 0xFFFF, sum = 0
5689 09:57:58.250230 9, 0xFFFF, sum = 0
5690 09:57:58.250351 10, 0x0, sum = 1
5691 09:57:58.253820 11, 0x0, sum = 2
5692 09:57:58.253901 12, 0x0, sum = 3
5693 09:57:58.256616 13, 0x0, sum = 4
5694 09:57:58.256696 best_step = 11
5695 09:57:58.256760
5696 09:57:58.256818 ==
5697 09:57:58.260420 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 09:57:58.263165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 09:57:58.266907 ==
5700 09:57:58.266987 RX Vref Scan: 1
5701 09:57:58.267051
5702 09:57:58.270099 RX Vref 0 -> 0, step: 1
5703 09:57:58.270194
5704 09:57:58.273084 RX Delay -53 -> 252, step: 4
5705 09:57:58.273210
5706 09:57:58.276432 Set Vref, RX VrefLevel [Byte0]: 51
5707 09:57:58.279633 [Byte1]: 52
5708 09:57:58.279722
5709 09:57:58.283249 Final RX Vref Byte 0 = 51 to rank0
5710 09:57:58.286564 Final RX Vref Byte 1 = 52 to rank0
5711 09:57:58.289469 Final RX Vref Byte 0 = 51 to rank1
5712 09:57:58.293116 Final RX Vref Byte 1 = 52 to rank1==
5713 09:57:58.296180 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 09:57:58.299449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 09:57:58.299540 ==
5716 09:57:58.302538 DQS Delay:
5717 09:57:58.302666 DQS0 = 0, DQS1 = 0
5718 09:57:58.302740 DQM Delay:
5719 09:57:58.305970 DQM0 = 98, DQM1 = 94
5720 09:57:58.306054 DQ Delay:
5721 09:57:58.309298 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5722 09:57:58.312564 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5723 09:57:58.315801 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5724 09:57:58.322374 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5725 09:57:58.322476
5726 09:57:58.322569
5727 09:57:58.329453 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5728 09:57:58.332507 CH1 RK0: MR19=505, MR18=919
5729 09:57:58.339152 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5730 09:57:58.339231
5731 09:57:58.342312 ----->DramcWriteLeveling(PI) begin...
5732 09:57:58.342398 ==
5733 09:57:58.345070 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 09:57:58.348703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 09:57:58.348786 ==
5736 09:57:58.352077 Write leveling (Byte 0): 27 => 27
5737 09:57:58.355158 Write leveling (Byte 1): 28 => 28
5738 09:57:58.358845 DramcWriteLeveling(PI) end<-----
5739 09:57:58.358929
5740 09:57:58.359013 ==
5741 09:57:58.361779 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 09:57:58.365264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 09:57:58.365404 ==
5744 09:57:58.368917 [Gating] SW mode calibration
5745 09:57:58.375150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5746 09:57:58.381901 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5747 09:57:58.384830 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 09:57:58.391338 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 09:57:58.394926 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 09:57:58.398341 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 09:57:58.404508 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 09:57:58.408210 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 09:57:58.411027 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
5754 09:57:58.417567 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5755 09:57:58.421372 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 09:57:58.424668 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 09:57:58.431106 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 09:57:58.434384 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 09:57:58.437619 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 09:57:58.443770 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 09:57:58.447140 0 15 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5762 09:57:58.450463 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5763 09:57:58.457007 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 09:57:58.460185 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 09:57:58.463834 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 09:57:58.470222 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 09:57:58.473470 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 09:57:58.476737 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 09:57:58.483661 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 09:57:58.486771 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5771 09:57:58.489936 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 09:57:58.496793 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 09:57:58.500139 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 09:57:58.503246 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 09:57:58.509885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 09:57:58.512819 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 09:57:58.516424 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 09:57:58.522769 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 09:57:58.526225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 09:57:58.529302 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 09:57:58.536220 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 09:57:58.539184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 09:57:58.542922 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 09:57:58.549280 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 09:57:58.552351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 09:57:58.556279 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5787 09:57:58.562827 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 09:57:58.562909 Total UI for P1: 0, mck2ui 16
5789 09:57:58.569280 best dqsien dly found for B0: ( 1, 2, 28)
5790 09:57:58.569361 Total UI for P1: 0, mck2ui 16
5791 09:57:58.575556 best dqsien dly found for B1: ( 1, 2, 28)
5792 09:57:58.578790 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5793 09:57:58.582064 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5794 09:57:58.582145
5795 09:57:58.585518 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5796 09:57:58.589067 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5797 09:57:58.591857 [Gating] SW calibration Done
5798 09:57:58.591937 ==
5799 09:57:58.595437 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 09:57:58.598482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 09:57:58.598563 ==
5802 09:57:58.601728 RX Vref Scan: 0
5803 09:57:58.601808
5804 09:57:58.601871 RX Vref 0 -> 0, step: 1
5805 09:57:58.605035
5806 09:57:58.605115 RX Delay -80 -> 252, step: 8
5807 09:57:58.611762 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5808 09:57:58.614973 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5809 09:57:58.618166 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5810 09:57:58.621540 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5811 09:57:58.625256 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5812 09:57:58.628420 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5813 09:57:58.635157 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5814 09:57:58.638083 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5815 09:57:58.641454 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5816 09:57:58.644793 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5817 09:57:58.648320 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5818 09:57:58.651677 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5819 09:57:58.657698 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5820 09:57:58.661145 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5821 09:57:58.664506 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5822 09:57:58.667931 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5823 09:57:58.668015 ==
5824 09:57:58.671056 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 09:57:58.677830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 09:57:58.677915 ==
5827 09:57:58.678048 DQS Delay:
5828 09:57:58.681049 DQS0 = 0, DQS1 = 0
5829 09:57:58.681161 DQM Delay:
5830 09:57:58.681262 DQM0 = 97, DQM1 = 94
5831 09:57:58.684294 DQ Delay:
5832 09:57:58.687677 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5833 09:57:58.690732 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5834 09:57:58.693931 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5835 09:57:58.697166 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5836 09:57:58.697304
5837 09:57:58.697405
5838 09:57:58.697503 ==
5839 09:57:58.700839 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 09:57:58.703876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 09:57:58.703959 ==
5842 09:57:58.704044
5843 09:57:58.706873
5844 09:57:58.706956 TX Vref Scan disable
5845 09:57:58.710368 == TX Byte 0 ==
5846 09:57:58.713621 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5847 09:57:58.716977 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5848 09:57:58.720339 == TX Byte 1 ==
5849 09:57:58.723523 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5850 09:57:58.727184 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5851 09:57:58.727269 ==
5852 09:57:58.730195 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 09:57:58.736889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 09:57:58.737000 ==
5855 09:57:58.737102
5856 09:57:58.737198
5857 09:57:58.737277 TX Vref Scan disable
5858 09:57:58.741346 == TX Byte 0 ==
5859 09:57:58.744591 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 09:57:58.751471 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 09:57:58.751554 == TX Byte 1 ==
5862 09:57:58.754404 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5863 09:57:58.760831 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5864 09:57:58.760913
5865 09:57:58.760978 [DATLAT]
5866 09:57:58.761038 Freq=933, CH1 RK1
5867 09:57:58.761097
5868 09:57:58.763918 DATLAT Default: 0xb
5869 09:57:58.764000 0, 0xFFFF, sum = 0
5870 09:57:58.767530 1, 0xFFFF, sum = 0
5871 09:57:58.770800 2, 0xFFFF, sum = 0
5872 09:57:58.770883 3, 0xFFFF, sum = 0
5873 09:57:58.774212 4, 0xFFFF, sum = 0
5874 09:57:58.774344 5, 0xFFFF, sum = 0
5875 09:57:58.777467 6, 0xFFFF, sum = 0
5876 09:57:58.777550 7, 0xFFFF, sum = 0
5877 09:57:58.780672 8, 0xFFFF, sum = 0
5878 09:57:58.780754 9, 0xFFFF, sum = 0
5879 09:57:58.784005 10, 0x0, sum = 1
5880 09:57:58.784087 11, 0x0, sum = 2
5881 09:57:58.787308 12, 0x0, sum = 3
5882 09:57:58.787391 13, 0x0, sum = 4
5883 09:57:58.790176 best_step = 11
5884 09:57:58.790271
5885 09:57:58.790389 ==
5886 09:57:58.793950 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 09:57:58.797145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 09:57:58.797230 ==
5889 09:57:58.797316 RX Vref Scan: 0
5890 09:57:58.797397
5891 09:57:58.800205 RX Vref 0 -> 0, step: 1
5892 09:57:58.800288
5893 09:57:58.803671 RX Delay -53 -> 252, step: 4
5894 09:57:58.810271 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5895 09:57:58.813390 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5896 09:57:58.816650 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5897 09:57:58.820071 iDelay=203, Bit 3, Center 96 (3 ~ 190) 188
5898 09:57:58.823497 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5899 09:57:58.829928 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5900 09:57:58.833373 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5901 09:57:58.836352 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5902 09:57:58.839640 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5903 09:57:58.842889 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5904 09:57:58.846215 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5905 09:57:58.852684 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5906 09:57:58.856095 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5907 09:57:58.859054 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5908 09:57:58.862805 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5909 09:57:58.865555 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5910 09:57:58.869219 ==
5911 09:57:58.872349 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 09:57:58.875739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 09:57:58.875851 ==
5914 09:57:58.875976 DQS Delay:
5915 09:57:58.879199 DQS0 = 0, DQS1 = 0
5916 09:57:58.879277 DQM Delay:
5917 09:57:58.882432 DQM0 = 97, DQM1 = 91
5918 09:57:58.882513 DQ Delay:
5919 09:57:58.885586 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5920 09:57:58.889195 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5921 09:57:58.892296 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5922 09:57:58.895523 DQ12 =98, DQ13 =100, DQ14 =96, DQ15 =102
5923 09:57:58.895604
5924 09:57:58.895668
5925 09:57:58.902093 [DQSOSCAuto] RK1, (LSB)MR18= 0xf25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5926 09:57:58.905679 CH1 RK1: MR19=505, MR18=F25
5927 09:57:58.911869 CH1_RK1: MR19=0x505, MR18=0xF25, DQSOSC=410, MR23=63, INC=64, DEC=42
5928 09:57:58.915300 [RxdqsGatingPostProcess] freq 933
5929 09:57:58.921943 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 09:57:58.925665 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 09:57:58.928479 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 09:57:58.931910 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 09:57:58.935223 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 09:57:58.935333 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 09:57:58.938397 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 09:57:58.942170 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 09:57:58.944870 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 09:57:58.948250 Pre-setting of DQS Precalculation
5939 09:57:58.955064 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 09:57:58.961327 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 09:57:58.968128 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 09:57:58.968212
5943 09:57:58.968298
5944 09:57:58.971569 [Calibration Summary] 1866 Mbps
5945 09:57:58.974501 CH 0, Rank 0
5946 09:57:58.974586 SW Impedance : PASS
5947 09:57:58.977999 DUTY Scan : NO K
5948 09:57:58.978107 ZQ Calibration : PASS
5949 09:57:58.981215 Jitter Meter : NO K
5950 09:57:58.984110 CBT Training : PASS
5951 09:57:58.984196 Write leveling : PASS
5952 09:57:58.987903 RX DQS gating : PASS
5953 09:57:58.990877 RX DQ/DQS(RDDQC) : PASS
5954 09:57:58.990958 TX DQ/DQS : PASS
5955 09:57:58.994212 RX DATLAT : PASS
5956 09:57:58.997522 RX DQ/DQS(Engine): PASS
5957 09:57:58.997603 TX OE : NO K
5958 09:57:59.000810 All Pass.
5959 09:57:59.000891
5960 09:57:59.000956 CH 0, Rank 1
5961 09:57:59.003945 SW Impedance : PASS
5962 09:57:59.004026 DUTY Scan : NO K
5963 09:57:59.007448 ZQ Calibration : PASS
5964 09:57:59.010865 Jitter Meter : NO K
5965 09:57:59.010996 CBT Training : PASS
5966 09:57:59.014246 Write leveling : PASS
5967 09:57:59.017275 RX DQS gating : PASS
5968 09:57:59.017359 RX DQ/DQS(RDDQC) : PASS
5969 09:57:59.020441 TX DQ/DQS : PASS
5970 09:57:59.024470 RX DATLAT : PASS
5971 09:57:59.024554 RX DQ/DQS(Engine): PASS
5972 09:57:59.027398 TX OE : NO K
5973 09:57:59.027481 All Pass.
5974 09:57:59.027565
5975 09:57:59.030998 CH 1, Rank 0
5976 09:57:59.031144 SW Impedance : PASS
5977 09:57:59.033743 DUTY Scan : NO K
5978 09:57:59.037250 ZQ Calibration : PASS
5979 09:57:59.037373 Jitter Meter : NO K
5980 09:57:59.040597 CBT Training : PASS
5981 09:57:59.043986 Write leveling : PASS
5982 09:57:59.044070 RX DQS gating : PASS
5983 09:57:59.047078 RX DQ/DQS(RDDQC) : PASS
5984 09:57:59.050113 TX DQ/DQS : PASS
5985 09:57:59.050224 RX DATLAT : PASS
5986 09:57:59.053728 RX DQ/DQS(Engine): PASS
5987 09:57:59.053811 TX OE : NO K
5988 09:57:59.056807 All Pass.
5989 09:57:59.056976
5990 09:57:59.057146 CH 1, Rank 1
5991 09:57:59.060238 SW Impedance : PASS
5992 09:57:59.060399 DUTY Scan : NO K
5993 09:57:59.063279 ZQ Calibration : PASS
5994 09:57:59.066706 Jitter Meter : NO K
5995 09:57:59.066787 CBT Training : PASS
5996 09:57:59.070320 Write leveling : PASS
5997 09:57:59.073658 RX DQS gating : PASS
5998 09:57:59.073739 RX DQ/DQS(RDDQC) : PASS
5999 09:57:59.076760 TX DQ/DQS : PASS
6000 09:57:59.080591 RX DATLAT : PASS
6001 09:57:59.080700 RX DQ/DQS(Engine): PASS
6002 09:57:59.083198 TX OE : NO K
6003 09:57:59.083283 All Pass.
6004 09:57:59.083376
6005 09:57:59.086629 DramC Write-DBI off
6006 09:57:59.089535 PER_BANK_REFRESH: Hybrid Mode
6007 09:57:59.089641 TX_TRACKING: ON
6008 09:57:59.099435 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 09:57:59.102752 [FAST_K] Save calibration result to emmc
6010 09:57:59.106015 dramc_set_vcore_voltage set vcore to 650000
6011 09:57:59.109190 Read voltage for 400, 6
6012 09:57:59.109271 Vio18 = 0
6013 09:57:59.112732 Vcore = 650000
6014 09:57:59.112830 Vdram = 0
6015 09:57:59.112895 Vddq = 0
6016 09:57:59.112955 Vmddr = 0
6017 09:57:59.119806 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 09:57:59.125962 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 09:57:59.126074 MEM_TYPE=3, freq_sel=20
6020 09:57:59.129456 sv_algorithm_assistance_LP4_800
6021 09:57:59.132078 ============ PULL DRAM RESETB DOWN ============
6022 09:57:59.138713 ========== PULL DRAM RESETB DOWN end =========
6023 09:57:59.142741 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 09:57:59.145390 ===================================
6025 09:57:59.148610 LPDDR4 DRAM CONFIGURATION
6026 09:57:59.152294 ===================================
6027 09:57:59.152376 EX_ROW_EN[0] = 0x0
6028 09:57:59.155707 EX_ROW_EN[1] = 0x0
6029 09:57:59.155789 LP4Y_EN = 0x0
6030 09:57:59.158542 WORK_FSP = 0x0
6031 09:57:59.161879 WL = 0x2
6032 09:57:59.161960 RL = 0x2
6033 09:57:59.165107 BL = 0x2
6034 09:57:59.165218 RPST = 0x0
6035 09:57:59.168437 RD_PRE = 0x0
6036 09:57:59.168518 WR_PRE = 0x1
6037 09:57:59.172023 WR_PST = 0x0
6038 09:57:59.172103 DBI_WR = 0x0
6039 09:57:59.175648 DBI_RD = 0x0
6040 09:57:59.175760 OTF = 0x1
6041 09:57:59.179178 ===================================
6042 09:57:59.181746 ===================================
6043 09:57:59.185248 ANA top config
6044 09:57:59.188480 ===================================
6045 09:57:59.188562 DLL_ASYNC_EN = 0
6046 09:57:59.191847 ALL_SLAVE_EN = 1
6047 09:57:59.195281 NEW_RANK_MODE = 1
6048 09:57:59.198669 DLL_IDLE_MODE = 1
6049 09:57:59.201558 LP45_APHY_COMB_EN = 1
6050 09:57:59.201640 TX_ODT_DIS = 1
6051 09:57:59.204947 NEW_8X_MODE = 1
6052 09:57:59.208468 ===================================
6053 09:57:59.211568 ===================================
6054 09:57:59.214933 data_rate = 800
6055 09:57:59.217876 CKR = 1
6056 09:57:59.221739 DQ_P2S_RATIO = 4
6057 09:57:59.224625 ===================================
6058 09:57:59.224710 CA_P2S_RATIO = 4
6059 09:57:59.228016 DQ_CA_OPEN = 0
6060 09:57:59.231956 DQ_SEMI_OPEN = 1
6061 09:57:59.234473 CA_SEMI_OPEN = 1
6062 09:57:59.237817 CA_FULL_RATE = 0
6063 09:57:59.241500 DQ_CKDIV4_EN = 0
6064 09:57:59.244530 CA_CKDIV4_EN = 1
6065 09:57:59.244615 CA_PREDIV_EN = 0
6066 09:57:59.247441 PH8_DLY = 0
6067 09:57:59.250847 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 09:57:59.254287 DQ_AAMCK_DIV = 0
6069 09:57:59.257329 CA_AAMCK_DIV = 0
6070 09:57:59.261024 CA_ADMCK_DIV = 4
6071 09:57:59.261106 DQ_TRACK_CA_EN = 0
6072 09:57:59.264604 CA_PICK = 800
6073 09:57:59.267613 CA_MCKIO = 400
6074 09:57:59.271262 MCKIO_SEMI = 400
6075 09:57:59.273931 PLL_FREQ = 3016
6076 09:57:59.277858 DQ_UI_PI_RATIO = 32
6077 09:57:59.280684 CA_UI_PI_RATIO = 32
6078 09:57:59.284143 ===================================
6079 09:57:59.287341 ===================================
6080 09:57:59.287422 memory_type:LPDDR4
6081 09:57:59.290401 GP_NUM : 10
6082 09:57:59.293703 SRAM_EN : 1
6083 09:57:59.293784 MD32_EN : 0
6084 09:57:59.297124 ===================================
6085 09:57:59.300367 [ANA_INIT] >>>>>>>>>>>>>>
6086 09:57:59.303745 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 09:57:59.306920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 09:57:59.310865 ===================================
6089 09:57:59.313348 data_rate = 800,PCW = 0X7400
6090 09:57:59.316610 ===================================
6091 09:57:59.320108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 09:57:59.323323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 09:57:59.336453 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 09:57:59.339795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 09:57:59.343136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 09:57:59.346552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 09:57:59.349835 [ANA_INIT] flow start
6098 09:57:59.353195 [ANA_INIT] PLL >>>>>>>>
6099 09:57:59.353277 [ANA_INIT] PLL <<<<<<<<
6100 09:57:59.356666 [ANA_INIT] MIDPI >>>>>>>>
6101 09:57:59.359360 [ANA_INIT] MIDPI <<<<<<<<
6102 09:57:59.362807 [ANA_INIT] DLL >>>>>>>>
6103 09:57:59.362888 [ANA_INIT] flow end
6104 09:57:59.366005 ============ LP4 DIFF to SE enter ============
6105 09:57:59.372999 ============ LP4 DIFF to SE exit ============
6106 09:57:59.373081 [ANA_INIT] <<<<<<<<<<<<<
6107 09:57:59.375940 [Flow] Enable top DCM control >>>>>
6108 09:57:59.379865 [Flow] Enable top DCM control <<<<<
6109 09:57:59.383105 Enable DLL master slave shuffle
6110 09:57:59.389190 ==============================================================
6111 09:57:59.389271 Gating Mode config
6112 09:57:59.395643 ==============================================================
6113 09:57:59.398948 Config description:
6114 09:57:59.408849 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 09:57:59.415481 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 09:57:59.418850 SELPH_MODE 0: By rank 1: By Phase
6117 09:57:59.425309 ==============================================================
6118 09:57:59.428712 GAT_TRACK_EN = 0
6119 09:57:59.431906 RX_GATING_MODE = 2
6120 09:57:59.435071 RX_GATING_TRACK_MODE = 2
6121 09:57:59.438609 SELPH_MODE = 1
6122 09:57:59.438693 PICG_EARLY_EN = 1
6123 09:57:59.441932 VALID_LAT_VALUE = 1
6124 09:57:59.448306 ==============================================================
6125 09:57:59.451785 Enter into Gating configuration >>>>
6126 09:57:59.454965 Exit from Gating configuration <<<<
6127 09:57:59.458472 Enter into DVFS_PRE_config >>>>>
6128 09:57:59.468258 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 09:57:59.471449 Exit from DVFS_PRE_config <<<<<
6130 09:57:59.474825 Enter into PICG configuration >>>>
6131 09:57:59.478049 Exit from PICG configuration <<<<
6132 09:57:59.481866 [RX_INPUT] configuration >>>>>
6133 09:57:59.484609 [RX_INPUT] configuration <<<<<
6134 09:57:59.487821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 09:57:59.494955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 09:57:59.501820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 09:57:59.507718 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 09:57:59.514389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 09:57:59.520913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 09:57:59.524265 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 09:57:59.527305 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 09:57:59.530730 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 09:57:59.537654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 09:57:59.541141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 09:57:59.543976 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 09:57:59.547241 ===================================
6147 09:57:59.550604 LPDDR4 DRAM CONFIGURATION
6148 09:57:59.553861 ===================================
6149 09:57:59.553945 EX_ROW_EN[0] = 0x0
6150 09:57:59.557233 EX_ROW_EN[1] = 0x0
6151 09:57:59.560601 LP4Y_EN = 0x0
6152 09:57:59.560685 WORK_FSP = 0x0
6153 09:57:59.564213 WL = 0x2
6154 09:57:59.564297 RL = 0x2
6155 09:57:59.567134 BL = 0x2
6156 09:57:59.567218 RPST = 0x0
6157 09:57:59.570527 RD_PRE = 0x0
6158 09:57:59.570611 WR_PRE = 0x1
6159 09:57:59.573804 WR_PST = 0x0
6160 09:57:59.573888 DBI_WR = 0x0
6161 09:57:59.577326 DBI_RD = 0x0
6162 09:57:59.577410 OTF = 0x1
6163 09:57:59.580392 ===================================
6164 09:57:59.583798 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 09:57:59.590046 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 09:57:59.593469 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 09:57:59.597036 ===================================
6168 09:57:59.599991 LPDDR4 DRAM CONFIGURATION
6169 09:57:59.603595 ===================================
6170 09:57:59.603707 EX_ROW_EN[0] = 0x10
6171 09:57:59.606391 EX_ROW_EN[1] = 0x0
6172 09:57:59.610033 LP4Y_EN = 0x0
6173 09:57:59.610148 WORK_FSP = 0x0
6174 09:57:59.613657 WL = 0x2
6175 09:57:59.613770 RL = 0x2
6176 09:57:59.616406 BL = 0x2
6177 09:57:59.616534 RPST = 0x0
6178 09:57:59.619809 RD_PRE = 0x0
6179 09:57:59.619955 WR_PRE = 0x1
6180 09:57:59.623193 WR_PST = 0x0
6181 09:57:59.623277 DBI_WR = 0x0
6182 09:57:59.626546 DBI_RD = 0x0
6183 09:57:59.626630 OTF = 0x1
6184 09:57:59.630020 ===================================
6185 09:57:59.636077 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 09:57:59.640562 nWR fixed to 30
6187 09:57:59.644012 [ModeRegInit_LP4] CH0 RK0
6188 09:57:59.644096 [ModeRegInit_LP4] CH0 RK1
6189 09:57:59.647608 [ModeRegInit_LP4] CH1 RK0
6190 09:57:59.650649 [ModeRegInit_LP4] CH1 RK1
6191 09:57:59.650732 match AC timing 19
6192 09:57:59.657337 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 09:57:59.660590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 09:57:59.663922 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 09:57:59.670527 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 09:57:59.673822 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 09:57:59.673923 ==
6198 09:57:59.676899 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 09:57:59.680549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 09:57:59.680631 ==
6201 09:57:59.686990 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 09:57:59.693844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6203 09:57:59.696767 [CA 0] Center 36 (8~64) winsize 57
6204 09:57:59.700165 [CA 1] Center 36 (8~64) winsize 57
6205 09:57:59.704032 [CA 2] Center 36 (8~64) winsize 57
6206 09:57:59.706769 [CA 3] Center 36 (8~64) winsize 57
6207 09:57:59.709970 [CA 4] Center 36 (8~64) winsize 57
6208 09:57:59.713310 [CA 5] Center 36 (8~64) winsize 57
6209 09:57:59.713387
6210 09:57:59.716484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6211 09:57:59.716570
6212 09:57:59.720183 [CATrainingPosCal] consider 1 rank data
6213 09:57:59.723282 u2DelayCellTimex100 = 270/100 ps
6214 09:57:59.726726 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 09:57:59.729675 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 09:57:59.732995 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 09:57:59.736180 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 09:57:59.739675 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 09:57:59.742959 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 09:57:59.743044
6221 09:57:59.749600 CA PerBit enable=1, Macro0, CA PI delay=36
6222 09:57:59.749700
6223 09:57:59.749816 [CBTSetCACLKResult] CA Dly = 36
6224 09:57:59.753029 CS Dly: 1 (0~32)
6225 09:57:59.753128 ==
6226 09:57:59.755983 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 09:57:59.759355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 09:57:59.759440 ==
6229 09:57:59.765918 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 09:57:59.772953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 09:57:59.776294 [CA 0] Center 36 (8~64) winsize 57
6232 09:57:59.778921 [CA 1] Center 36 (8~64) winsize 57
6233 09:57:59.782272 [CA 2] Center 36 (8~64) winsize 57
6234 09:57:59.785844 [CA 3] Center 36 (8~64) winsize 57
6235 09:57:59.789306 [CA 4] Center 36 (8~64) winsize 57
6236 09:57:59.789405 [CA 5] Center 36 (8~64) winsize 57
6237 09:57:59.789550
6238 09:57:59.796042 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 09:57:59.796128
6240 09:57:59.798766 [CATrainingPosCal] consider 2 rank data
6241 09:57:59.802361 u2DelayCellTimex100 = 270/100 ps
6242 09:57:59.805576 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 09:57:59.808898 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 09:57:59.811947 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 09:57:59.815343 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 09:57:59.818713 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 09:57:59.822220 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 09:57:59.822346
6249 09:57:59.825436 CA PerBit enable=1, Macro0, CA PI delay=36
6250 09:57:59.825520
6251 09:57:59.828550 [CBTSetCACLKResult] CA Dly = 36
6252 09:57:59.831583 CS Dly: 1 (0~32)
6253 09:57:59.831667
6254 09:57:59.835595 ----->DramcWriteLeveling(PI) begin...
6255 09:57:59.835681 ==
6256 09:57:59.838149 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 09:57:59.842002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 09:57:59.842088 ==
6259 09:57:59.844814 Write leveling (Byte 0): 40 => 8
6260 09:57:59.848336 Write leveling (Byte 1): 40 => 8
6261 09:57:59.851685 DramcWriteLeveling(PI) end<-----
6262 09:57:59.851769
6263 09:57:59.851855 ==
6264 09:57:59.854585 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 09:57:59.858110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 09:57:59.861449 ==
6267 09:57:59.861533 [Gating] SW mode calibration
6268 09:57:59.871661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 09:57:59.874518 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 09:57:59.877852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 09:57:59.884476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 09:57:59.887904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 09:57:59.890758 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 09:57:59.897620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 09:57:59.901182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 09:57:59.903991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 09:57:59.910732 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 09:57:59.914124 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 09:57:59.917298 Total UI for P1: 0, mck2ui 16
6280 09:57:59.920502 best dqsien dly found for B0: ( 0, 14, 24)
6281 09:57:59.923925 Total UI for P1: 0, mck2ui 16
6282 09:57:59.927044 best dqsien dly found for B1: ( 0, 14, 24)
6283 09:57:59.930241 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 09:57:59.933796 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 09:57:59.933899
6286 09:57:59.937125 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 09:57:59.943700 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 09:57:59.943790 [Gating] SW calibration Done
6289 09:57:59.943898 ==
6290 09:57:59.946941 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 09:57:59.953778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 09:57:59.953860 ==
6293 09:57:59.953925 RX Vref Scan: 0
6294 09:57:59.953986
6295 09:57:59.956936 RX Vref 0 -> 0, step: 1
6296 09:57:59.957018
6297 09:57:59.960104 RX Delay -410 -> 252, step: 16
6298 09:57:59.963576 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6299 09:57:59.966725 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6300 09:57:59.973702 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6301 09:57:59.976665 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6302 09:57:59.980116 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6303 09:57:59.983072 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6304 09:57:59.989922 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6305 09:57:59.993083 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6306 09:57:59.996162 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6307 09:57:59.999296 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6308 09:58:00.006203 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6309 09:58:00.009162 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6310 09:58:00.012614 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6311 09:58:00.019313 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6312 09:58:00.022616 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6313 09:58:00.025946 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6314 09:58:00.026046 ==
6315 09:58:00.029356 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 09:58:00.032614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 09:58:00.035956 ==
6318 09:58:00.036031 DQS Delay:
6319 09:58:00.036098 DQS0 = 35, DQS1 = 51
6320 09:58:00.038995 DQM Delay:
6321 09:58:00.039096 DQM0 = 5, DQM1 = 10
6322 09:58:00.043043 DQ Delay:
6323 09:58:00.043147 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6324 09:58:00.045920 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6325 09:58:00.048805 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6326 09:58:00.052867 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6327 09:58:00.052967
6328 09:58:00.053057
6329 09:58:00.053163 ==
6330 09:58:00.055862 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 09:58:00.062025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 09:58:00.062130 ==
6333 09:58:00.062195
6334 09:58:00.062266
6335 09:58:00.066703 TX Vref Scan disable
6336 09:58:00.066784 == TX Byte 0 ==
6337 09:58:00.068814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 09:58:00.075892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 09:58:00.075988 == TX Byte 1 ==
6340 09:58:00.078576 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 09:58:00.085161 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 09:58:00.085243 ==
6343 09:58:00.088659 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 09:58:00.091615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 09:58:00.091722 ==
6346 09:58:00.091819
6347 09:58:00.091908
6348 09:58:00.095387 TX Vref Scan disable
6349 09:58:00.095475 == TX Byte 0 ==
6350 09:58:00.098833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 09:58:00.105093 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 09:58:00.105196 == TX Byte 1 ==
6353 09:58:00.108108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 09:58:00.114612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 09:58:00.114695
6356 09:58:00.114760 [DATLAT]
6357 09:58:00.114822 Freq=400, CH0 RK0
6358 09:58:00.118041
6359 09:58:00.118139 DATLAT Default: 0xf
6360 09:58:00.121864 0, 0xFFFF, sum = 0
6361 09:58:00.121964 1, 0xFFFF, sum = 0
6362 09:58:00.124889 2, 0xFFFF, sum = 0
6363 09:58:00.124991 3, 0xFFFF, sum = 0
6364 09:58:00.128187 4, 0xFFFF, sum = 0
6365 09:58:00.128263 5, 0xFFFF, sum = 0
6366 09:58:00.131490 6, 0xFFFF, sum = 0
6367 09:58:00.131595 7, 0xFFFF, sum = 0
6368 09:58:00.135056 8, 0xFFFF, sum = 0
6369 09:58:00.135134 9, 0xFFFF, sum = 0
6370 09:58:00.137794 10, 0xFFFF, sum = 0
6371 09:58:00.137895 11, 0xFFFF, sum = 0
6372 09:58:00.141581 12, 0xFFFF, sum = 0
6373 09:58:00.141710 13, 0x0, sum = 1
6374 09:58:00.144446 14, 0x0, sum = 2
6375 09:58:00.144550 15, 0x0, sum = 3
6376 09:58:00.147951 16, 0x0, sum = 4
6377 09:58:00.148051 best_step = 14
6378 09:58:00.148143
6379 09:58:00.148229 ==
6380 09:58:00.151285 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 09:58:00.157767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 09:58:00.157872 ==
6383 09:58:00.157963 RX Vref Scan: 1
6384 09:58:00.158050
6385 09:58:00.161164 RX Vref 0 -> 0, step: 1
6386 09:58:00.161259
6387 09:58:00.164608 RX Delay -343 -> 252, step: 8
6388 09:58:00.164703
6389 09:58:00.167452 Set Vref, RX VrefLevel [Byte0]: 57
6390 09:58:00.171382 [Byte1]: 59
6391 09:58:00.174607
6392 09:58:00.174681 Final RX Vref Byte 0 = 57 to rank0
6393 09:58:00.177317 Final RX Vref Byte 1 = 59 to rank0
6394 09:58:00.180890 Final RX Vref Byte 0 = 57 to rank1
6395 09:58:00.183752 Final RX Vref Byte 1 = 59 to rank1==
6396 09:58:00.187503 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 09:58:00.194193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 09:58:00.194319 ==
6399 09:58:00.194417 DQS Delay:
6400 09:58:00.197522 DQS0 = 44, DQS1 = 60
6401 09:58:00.197634 DQM Delay:
6402 09:58:00.197728 DQM0 = 11, DQM1 = 16
6403 09:58:00.200491 DQ Delay:
6404 09:58:00.203812 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6405 09:58:00.206969 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6406 09:58:00.207070 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6407 09:58:00.210831 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6408 09:58:00.213590
6409 09:58:00.213663
6410 09:58:00.220132 [DQSOSCAuto] RK0, (LSB)MR18= 0x9488, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6411 09:58:00.223340 CH0 RK0: MR19=C0C, MR18=9488
6412 09:58:00.229952 CH0_RK0: MR19=0xC0C, MR18=0x9488, DQSOSC=391, MR23=63, INC=386, DEC=257
6413 09:58:00.230053 ==
6414 09:58:00.233157 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 09:58:00.236843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 09:58:00.236942 ==
6417 09:58:00.240016 [Gating] SW mode calibration
6418 09:58:00.246503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 09:58:00.252932 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 09:58:00.256628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 09:58:00.259697 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 09:58:00.267079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 09:58:00.270283 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 09:58:00.273230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 09:58:00.280248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 09:58:00.283029 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 09:58:00.286188 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 09:58:00.293125 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 09:58:00.296309 Total UI for P1: 0, mck2ui 16
6430 09:58:00.299614 best dqsien dly found for B0: ( 0, 14, 24)
6431 09:58:00.299689 Total UI for P1: 0, mck2ui 16
6432 09:58:00.305817 best dqsien dly found for B1: ( 0, 14, 24)
6433 09:58:00.309283 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 09:58:00.312704 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 09:58:00.312801
6436 09:58:00.315671 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 09:58:00.319054 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 09:58:00.322518 [Gating] SW calibration Done
6439 09:58:00.322596 ==
6440 09:58:00.325761 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 09:58:00.329597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 09:58:00.329672 ==
6443 09:58:00.332259 RX Vref Scan: 0
6444 09:58:00.332335
6445 09:58:00.335493 RX Vref 0 -> 0, step: 1
6446 09:58:00.335567
6447 09:58:00.335633 RX Delay -410 -> 252, step: 16
6448 09:58:00.342426 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6449 09:58:00.346000 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6450 09:58:00.349071 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6451 09:58:00.355672 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6452 09:58:00.358923 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6453 09:58:00.362350 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6454 09:58:00.365357 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6455 09:58:00.372253 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6456 09:58:00.375303 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6457 09:58:00.378565 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6458 09:58:00.381781 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6459 09:58:00.388362 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6460 09:58:00.392752 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6461 09:58:00.394976 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6462 09:58:00.401806 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6463 09:58:00.404770 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6464 09:58:00.404882 ==
6465 09:58:00.407851 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 09:58:00.411650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 09:58:00.411728 ==
6468 09:58:00.414431 DQS Delay:
6469 09:58:00.414538 DQS0 = 35, DQS1 = 59
6470 09:58:00.414637 DQM Delay:
6471 09:58:00.418388 DQM0 = 7, DQM1 = 17
6472 09:58:00.418462 DQ Delay:
6473 09:58:00.421044 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6474 09:58:00.424777 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6475 09:58:00.427936 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6476 09:58:00.431117 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6477 09:58:00.431222
6478 09:58:00.431322
6479 09:58:00.431416 ==
6480 09:58:00.434183 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 09:58:00.437368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 09:58:00.440806 ==
6483 09:58:00.440910
6484 09:58:00.440999
6485 09:58:00.441088 TX Vref Scan disable
6486 09:58:00.444113 == TX Byte 0 ==
6487 09:58:00.447433 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6488 09:58:00.450563 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6489 09:58:00.453940 == TX Byte 1 ==
6490 09:58:00.457305 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 09:58:00.460623 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 09:58:00.460721 ==
6493 09:58:00.464270 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 09:58:00.470569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 09:58:00.470671 ==
6496 09:58:00.470761
6497 09:58:00.470850
6498 09:58:00.470936 TX Vref Scan disable
6499 09:58:00.473868 == TX Byte 0 ==
6500 09:58:00.477341 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6501 09:58:00.480183 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6502 09:58:00.483679 == TX Byte 1 ==
6503 09:58:00.486614 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 09:58:00.490011 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 09:58:00.490114
6506 09:58:00.493526 [DATLAT]
6507 09:58:00.493605 Freq=400, CH0 RK1
6508 09:58:00.493669
6509 09:58:00.497332 DATLAT Default: 0xe
6510 09:58:00.497406 0, 0xFFFF, sum = 0
6511 09:58:00.500544 1, 0xFFFF, sum = 0
6512 09:58:00.500651 2, 0xFFFF, sum = 0
6513 09:58:00.503493 3, 0xFFFF, sum = 0
6514 09:58:00.503567 4, 0xFFFF, sum = 0
6515 09:58:00.506224 5, 0xFFFF, sum = 0
6516 09:58:00.506349 6, 0xFFFF, sum = 0
6517 09:58:00.509999 7, 0xFFFF, sum = 0
6518 09:58:00.513196 8, 0xFFFF, sum = 0
6519 09:58:00.513296 9, 0xFFFF, sum = 0
6520 09:58:00.516094 10, 0xFFFF, sum = 0
6521 09:58:00.516192 11, 0xFFFF, sum = 0
6522 09:58:00.519387 12, 0xFFFF, sum = 0
6523 09:58:00.519491 13, 0x0, sum = 1
6524 09:58:00.522890 14, 0x0, sum = 2
6525 09:58:00.522968 15, 0x0, sum = 3
6526 09:58:00.526165 16, 0x0, sum = 4
6527 09:58:00.526289 best_step = 14
6528 09:58:00.526391
6529 09:58:00.526480 ==
6530 09:58:00.529582 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 09:58:00.532606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 09:58:00.532703 ==
6533 09:58:00.536339 RX Vref Scan: 0
6534 09:58:00.536438
6535 09:58:00.539238 RX Vref 0 -> 0, step: 1
6536 09:58:00.539312
6537 09:58:00.542286 RX Delay -359 -> 252, step: 8
6538 09:58:00.549054 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6539 09:58:00.553029 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6540 09:58:00.555990 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6541 09:58:00.559171 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6542 09:58:00.565379 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6543 09:58:00.568826 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6544 09:58:00.572176 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6545 09:58:00.575769 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6546 09:58:00.581935 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6547 09:58:00.585560 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6548 09:58:00.588617 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6549 09:58:00.591977 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6550 09:58:00.598495 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6551 09:58:00.601831 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6552 09:58:00.605303 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6553 09:58:00.608626 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6554 09:58:00.611784 ==
6555 09:58:00.615005 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 09:58:00.618436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 09:58:00.618518 ==
6558 09:58:00.618582 DQS Delay:
6559 09:58:00.621313 DQS0 = 40, DQS1 = 60
6560 09:58:00.621393 DQM Delay:
6561 09:58:00.624701 DQM0 = 6, DQM1 = 15
6562 09:58:00.624782 DQ Delay:
6563 09:58:00.628262 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6564 09:58:00.631638 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6565 09:58:00.634507 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6566 09:58:00.638345 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6567 09:58:00.638426
6568 09:58:00.638491
6569 09:58:00.644430 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d86, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6570 09:58:00.648250 CH0 RK1: MR19=C0C, MR18=8D86
6571 09:58:00.654908 CH0_RK1: MR19=0xC0C, MR18=0x8D86, DQSOSC=392, MR23=63, INC=384, DEC=256
6572 09:58:00.658185 [RxdqsGatingPostProcess] freq 400
6573 09:58:00.661330 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 09:58:00.664922 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 09:58:00.668023 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 09:58:00.671670 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 09:58:00.674541 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 09:58:00.677604 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 09:58:00.680961 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 09:58:00.684319 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 09:58:00.687537 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 09:58:00.690711 Pre-setting of DQS Precalculation
6583 09:58:00.697252 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 09:58:00.697333 ==
6585 09:58:00.700936 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 09:58:00.704181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 09:58:00.704291 ==
6588 09:58:00.710246 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 09:58:00.713793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6590 09:58:00.717088 [CA 0] Center 36 (8~64) winsize 57
6591 09:58:00.720401 [CA 1] Center 36 (8~64) winsize 57
6592 09:58:00.723308 [CA 2] Center 36 (8~64) winsize 57
6593 09:58:00.727210 [CA 3] Center 36 (8~64) winsize 57
6594 09:58:00.730438 [CA 4] Center 36 (8~64) winsize 57
6595 09:58:00.733317 [CA 5] Center 36 (8~64) winsize 57
6596 09:58:00.733402
6597 09:58:00.736781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6598 09:58:00.736862
6599 09:58:00.740116 [CATrainingPosCal] consider 1 rank data
6600 09:58:00.743158 u2DelayCellTimex100 = 270/100 ps
6601 09:58:00.746394 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 09:58:00.752936 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 09:58:00.756923 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 09:58:00.759949 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 09:58:00.763237 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 09:58:00.766422 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 09:58:00.766520
6608 09:58:00.769760 CA PerBit enable=1, Macro0, CA PI delay=36
6609 09:58:00.769856
6610 09:58:00.772949 [CBTSetCACLKResult] CA Dly = 36
6611 09:58:00.776704 CS Dly: 1 (0~32)
6612 09:58:00.776800 ==
6613 09:58:00.779703 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 09:58:00.782884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 09:58:00.782955 ==
6616 09:58:00.789447 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 09:58:00.792939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 09:58:00.796099 [CA 0] Center 36 (8~64) winsize 57
6619 09:58:00.799597 [CA 1] Center 36 (8~64) winsize 57
6620 09:58:00.802743 [CA 2] Center 36 (8~64) winsize 57
6621 09:58:00.806047 [CA 3] Center 36 (8~64) winsize 57
6622 09:58:00.809488 [CA 4] Center 36 (8~64) winsize 57
6623 09:58:00.812281 [CA 5] Center 36 (8~64) winsize 57
6624 09:58:00.812363
6625 09:58:00.816180 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 09:58:00.816253
6627 09:58:00.819317 [CATrainingPosCal] consider 2 rank data
6628 09:58:00.822173 u2DelayCellTimex100 = 270/100 ps
6629 09:58:00.825749 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 09:58:00.829037 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 09:58:00.835480 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 09:58:00.838554 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 09:58:00.841973 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 09:58:00.845756 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 09:58:00.845865
6636 09:58:00.848622 CA PerBit enable=1, Macro0, CA PI delay=36
6637 09:58:00.848719
6638 09:58:00.852445 [CBTSetCACLKResult] CA Dly = 36
6639 09:58:00.852542 CS Dly: 1 (0~32)
6640 09:58:00.855121
6641 09:58:00.858917 ----->DramcWriteLeveling(PI) begin...
6642 09:58:00.858990 ==
6643 09:58:00.861835 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 09:58:00.865296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 09:58:00.865403 ==
6646 09:58:00.868708 Write leveling (Byte 0): 40 => 8
6647 09:58:00.871840 Write leveling (Byte 1): 40 => 8
6648 09:58:00.875224 DramcWriteLeveling(PI) end<-----
6649 09:58:00.875294
6650 09:58:00.875370 ==
6651 09:58:00.878459 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 09:58:00.881678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 09:58:00.881775 ==
6654 09:58:00.885123 [Gating] SW mode calibration
6655 09:58:00.891718 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 09:58:00.897852 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 09:58:00.901556 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 09:58:00.904691 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 09:58:00.911122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 09:58:00.914362 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 09:58:00.917785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 09:58:00.924514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 09:58:00.927752 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 09:58:00.930749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 09:58:00.937563 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 09:58:00.937672 Total UI for P1: 0, mck2ui 16
6667 09:58:00.944090 best dqsien dly found for B0: ( 0, 14, 24)
6668 09:58:00.944198 Total UI for P1: 0, mck2ui 16
6669 09:58:00.950953 best dqsien dly found for B1: ( 0, 14, 24)
6670 09:58:00.954080 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 09:58:00.957277 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 09:58:00.957378
6673 09:58:00.960813 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 09:58:00.964098 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 09:58:00.967211 [Gating] SW calibration Done
6676 09:58:00.967285 ==
6677 09:58:00.970572 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 09:58:00.973770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 09:58:00.973873 ==
6680 09:58:00.977116 RX Vref Scan: 0
6681 09:58:00.977223
6682 09:58:00.980267 RX Vref 0 -> 0, step: 1
6683 09:58:00.980345
6684 09:58:00.980409 RX Delay -410 -> 252, step: 16
6685 09:58:00.986711 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6686 09:58:00.990282 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6687 09:58:00.993427 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6688 09:58:01.000196 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6689 09:58:01.003113 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6690 09:58:01.006819 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6691 09:58:01.009896 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6692 09:58:01.016148 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6693 09:58:01.019932 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6694 09:58:01.023306 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6695 09:58:01.026562 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6696 09:58:01.032785 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6697 09:58:01.036214 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6698 09:58:01.039707 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6699 09:58:01.045871 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6700 09:58:01.050084 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6701 09:58:01.050186 ==
6702 09:58:01.052334 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 09:58:01.055947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 09:58:01.056046 ==
6705 09:58:01.059046 DQS Delay:
6706 09:58:01.059135 DQS0 = 35, DQS1 = 51
6707 09:58:01.059197 DQM Delay:
6708 09:58:01.062484 DQM0 = 6, DQM1 = 13
6709 09:58:01.062561 DQ Delay:
6710 09:58:01.066054 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6711 09:58:01.068811 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6712 09:58:01.072196 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 09:58:01.075745 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6714 09:58:01.075815
6715 09:58:01.075881
6716 09:58:01.075940 ==
6717 09:58:01.078685 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 09:58:01.081971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 09:58:01.085260 ==
6720 09:58:01.085371
6721 09:58:01.085465
6722 09:58:01.085554 TX Vref Scan disable
6723 09:58:01.088497 == TX Byte 0 ==
6724 09:58:01.091669 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 09:58:01.095404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 09:58:01.098705 == TX Byte 1 ==
6727 09:58:01.101852 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 09:58:01.105081 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 09:58:01.105191 ==
6730 09:58:01.108342 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 09:58:01.115541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 09:58:01.115637 ==
6733 09:58:01.115739
6734 09:58:01.115862
6735 09:58:01.115980 TX Vref Scan disable
6736 09:58:01.118056 == TX Byte 0 ==
6737 09:58:01.121655 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 09:58:01.124754 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 09:58:01.127870 == TX Byte 1 ==
6740 09:58:01.131238 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 09:58:01.134706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 09:58:01.134781
6743 09:58:01.137959 [DATLAT]
6744 09:58:01.138056 Freq=400, CH1 RK0
6745 09:58:01.138149
6746 09:58:01.141384 DATLAT Default: 0xf
6747 09:58:01.141462 0, 0xFFFF, sum = 0
6748 09:58:01.144938 1, 0xFFFF, sum = 0
6749 09:58:01.145044 2, 0xFFFF, sum = 0
6750 09:58:01.148354 3, 0xFFFF, sum = 0
6751 09:58:01.148457 4, 0xFFFF, sum = 0
6752 09:58:01.151222 5, 0xFFFF, sum = 0
6753 09:58:01.151318 6, 0xFFFF, sum = 0
6754 09:58:01.155158 7, 0xFFFF, sum = 0
6755 09:58:01.155240 8, 0xFFFF, sum = 0
6756 09:58:01.157796 9, 0xFFFF, sum = 0
6757 09:58:01.161256 10, 0xFFFF, sum = 0
6758 09:58:01.161360 11, 0xFFFF, sum = 0
6759 09:58:01.164748 12, 0xFFFF, sum = 0
6760 09:58:01.164877 13, 0x0, sum = 1
6761 09:58:01.167669 14, 0x0, sum = 2
6762 09:58:01.167769 15, 0x0, sum = 3
6763 09:58:01.170945 16, 0x0, sum = 4
6764 09:58:01.171091 best_step = 14
6765 09:58:01.171196
6766 09:58:01.171294 ==
6767 09:58:01.174338 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 09:58:01.177445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 09:58:01.177544 ==
6770 09:58:01.181063 RX Vref Scan: 1
6771 09:58:01.181164
6772 09:58:01.184334 RX Vref 0 -> 0, step: 1
6773 09:58:01.184432
6774 09:58:01.184526 RX Delay -343 -> 252, step: 8
6775 09:58:01.184628
6776 09:58:01.187589 Set Vref, RX VrefLevel [Byte0]: 51
6777 09:58:01.190983 [Byte1]: 52
6778 09:58:01.196087
6779 09:58:01.196189 Final RX Vref Byte 0 = 51 to rank0
6780 09:58:01.199596 Final RX Vref Byte 1 = 52 to rank0
6781 09:58:01.203102 Final RX Vref Byte 0 = 51 to rank1
6782 09:58:01.206769 Final RX Vref Byte 1 = 52 to rank1==
6783 09:58:01.209486 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 09:58:01.216039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 09:58:01.216120 ==
6786 09:58:01.216185 DQS Delay:
6787 09:58:01.219461 DQS0 = 44, DQS1 = 52
6788 09:58:01.219535 DQM Delay:
6789 09:58:01.219602 DQM0 = 10, DQM1 = 10
6790 09:58:01.222726 DQ Delay:
6791 09:58:01.225978 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6792 09:58:01.229669 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6793 09:58:01.229743 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6794 09:58:01.232368 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6795 09:58:01.232440
6796 09:58:01.235872
6797 09:58:01.242516 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e95, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6798 09:58:01.246042 CH1 RK0: MR19=C0C, MR18=6E95
6799 09:58:01.252935 CH1_RK0: MR19=0xC0C, MR18=0x6E95, DQSOSC=391, MR23=63, INC=386, DEC=257
6800 09:58:01.253013 ==
6801 09:58:01.255556 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 09:58:01.259332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 09:58:01.259412 ==
6804 09:58:01.262088 [Gating] SW mode calibration
6805 09:58:01.268444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 09:58:01.275307 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 09:58:01.278753 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 09:58:01.281941 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 09:58:01.288275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 09:58:01.291823 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 09:58:01.294892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 09:58:01.301486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 09:58:01.305098 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 09:58:01.308335 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 09:58:01.314983 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 09:58:01.318136 Total UI for P1: 0, mck2ui 16
6817 09:58:01.321331 best dqsien dly found for B0: ( 0, 14, 24)
6818 09:58:01.321406 Total UI for P1: 0, mck2ui 16
6819 09:58:01.328027 best dqsien dly found for B1: ( 0, 14, 24)
6820 09:58:01.331718 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 09:58:01.334716 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 09:58:01.334793
6823 09:58:01.338066 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 09:58:01.341021 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 09:58:01.344236 [Gating] SW calibration Done
6826 09:58:01.344311 ==
6827 09:58:01.347691 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 09:58:01.350794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 09:58:01.350896 ==
6830 09:58:01.354176 RX Vref Scan: 0
6831 09:58:01.354306
6832 09:58:01.357556 RX Vref 0 -> 0, step: 1
6833 09:58:01.357631
6834 09:58:01.357692 RX Delay -410 -> 252, step: 16
6835 09:58:01.364299 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6836 09:58:01.367522 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6837 09:58:01.371184 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6838 09:58:01.377813 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6839 09:58:01.380839 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6840 09:58:01.383944 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6841 09:58:01.387467 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6842 09:58:01.393843 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6843 09:58:01.396984 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6844 09:58:01.400464 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6845 09:58:01.403616 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6846 09:58:01.410089 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6847 09:58:01.413483 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6848 09:58:01.416698 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6849 09:58:01.423290 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6850 09:58:01.426525 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6851 09:58:01.426601 ==
6852 09:58:01.430340 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 09:58:01.433651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 09:58:01.433749 ==
6855 09:58:01.436724 DQS Delay:
6856 09:58:01.436822 DQS0 = 43, DQS1 = 51
6857 09:58:01.436912 DQM Delay:
6858 09:58:01.440094 DQM0 = 10, DQM1 = 14
6859 09:58:01.440164 DQ Delay:
6860 09:58:01.443162 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6861 09:58:01.446399 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6862 09:58:01.449633 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6863 09:58:01.453414 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6864 09:58:01.453490
6865 09:58:01.453553
6866 09:58:01.453620 ==
6867 09:58:01.456542 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 09:58:01.459956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 09:58:01.462821 ==
6870 09:58:01.462895
6871 09:58:01.462956
6872 09:58:01.463014 TX Vref Scan disable
6873 09:58:01.466248 == TX Byte 0 ==
6874 09:58:01.469549 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6875 09:58:01.473501 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6876 09:58:01.476450 == TX Byte 1 ==
6877 09:58:01.479806 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 09:58:01.482815 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 09:58:01.482891 ==
6880 09:58:01.486234 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 09:58:01.492818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 09:58:01.492920 ==
6883 09:58:01.493011
6884 09:58:01.493100
6885 09:58:01.493187 TX Vref Scan disable
6886 09:58:01.495752 == TX Byte 0 ==
6887 09:58:01.499216 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6888 09:58:01.502693 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6889 09:58:01.506450 == TX Byte 1 ==
6890 09:58:01.509220 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 09:58:01.512502 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 09:58:01.512601
6893 09:58:01.515953 [DATLAT]
6894 09:58:01.516024 Freq=400, CH1 RK1
6895 09:58:01.516090
6896 09:58:01.518827 DATLAT Default: 0xe
6897 09:58:01.518898 0, 0xFFFF, sum = 0
6898 09:58:01.522186 1, 0xFFFF, sum = 0
6899 09:58:01.522322 2, 0xFFFF, sum = 0
6900 09:58:01.525402 3, 0xFFFF, sum = 0
6901 09:58:01.525500 4, 0xFFFF, sum = 0
6902 09:58:01.528933 5, 0xFFFF, sum = 0
6903 09:58:01.529031 6, 0xFFFF, sum = 0
6904 09:58:01.532509 7, 0xFFFF, sum = 0
6905 09:58:01.532610 8, 0xFFFF, sum = 0
6906 09:58:01.536096 9, 0xFFFF, sum = 0
6907 09:58:01.538598 10, 0xFFFF, sum = 0
6908 09:58:01.538670 11, 0xFFFF, sum = 0
6909 09:58:01.542748 12, 0xFFFF, sum = 0
6910 09:58:01.542820 13, 0x0, sum = 1
6911 09:58:01.545145 14, 0x0, sum = 2
6912 09:58:01.545249 15, 0x0, sum = 3
6913 09:58:01.545342 16, 0x0, sum = 4
6914 09:58:01.548864 best_step = 14
6915 09:58:01.548963
6916 09:58:01.549052 ==
6917 09:58:01.552149 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 09:58:01.555653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 09:58:01.555742 ==
6920 09:58:01.558793 RX Vref Scan: 0
6921 09:58:01.558866
6922 09:58:01.561628 RX Vref 0 -> 0, step: 1
6923 09:58:01.561701
6924 09:58:01.561790 RX Delay -343 -> 252, step: 8
6925 09:58:01.570732 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6926 09:58:01.573819 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6927 09:58:01.577519 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6928 09:58:01.583907 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6929 09:58:01.587486 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6930 09:58:01.590381 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6931 09:58:01.593771 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6932 09:58:01.599966 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6933 09:58:01.603461 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6934 09:58:01.606958 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6935 09:58:01.610490 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6936 09:58:01.616730 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6937 09:58:01.620166 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6938 09:58:01.623237 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6939 09:58:01.626405 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6940 09:58:01.633209 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6941 09:58:01.633306 ==
6942 09:58:01.636722 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 09:58:01.639871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 09:58:01.639970 ==
6945 09:58:01.640061 DQS Delay:
6946 09:58:01.643132 DQS0 = 48, DQS1 = 52
6947 09:58:01.643208 DQM Delay:
6948 09:58:01.646189 DQM0 = 11, DQM1 = 10
6949 09:58:01.646313 DQ Delay:
6950 09:58:01.649795 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6951 09:58:01.653125 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6952 09:58:01.656206 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6953 09:58:01.659425 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6954 09:58:01.659525
6955 09:58:01.659613
6956 09:58:01.665872 [DQSOSCAuto] RK1, (LSB)MR18= 0x74ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6957 09:58:01.669664 CH1 RK1: MR19=C0C, MR18=74AC
6958 09:58:01.676427 CH1_RK1: MR19=0xC0C, MR18=0x74AC, DQSOSC=388, MR23=63, INC=392, DEC=261
6959 09:58:01.679387 [RxdqsGatingPostProcess] freq 400
6960 09:58:01.685913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 09:58:01.689137 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 09:58:01.692527 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 09:58:01.695914 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 09:58:01.699109 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 09:58:01.702235 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 09:58:01.702318 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 09:58:01.705866 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 09:58:01.708820 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 09:58:01.712196 Pre-setting of DQS Precalculation
6970 09:58:01.718487 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 09:58:01.725218 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 09:58:01.731749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 09:58:01.731824
6974 09:58:01.731886
6975 09:58:01.735019 [Calibration Summary] 800 Mbps
6976 09:58:01.738362 CH 0, Rank 0
6977 09:58:01.738433 SW Impedance : PASS
6978 09:58:01.741605 DUTY Scan : NO K
6979 09:58:01.745126 ZQ Calibration : PASS
6980 09:58:01.745228 Jitter Meter : NO K
6981 09:58:01.748125 CBT Training : PASS
6982 09:58:01.751633 Write leveling : PASS
6983 09:58:01.751712 RX DQS gating : PASS
6984 09:58:01.754961 RX DQ/DQS(RDDQC) : PASS
6985 09:58:01.755033 TX DQ/DQS : PASS
6986 09:58:01.758459 RX DATLAT : PASS
6987 09:58:01.761960 RX DQ/DQS(Engine): PASS
6988 09:58:01.762057 TX OE : NO K
6989 09:58:01.764897 All Pass.
6990 09:58:01.764993
6991 09:58:01.765081 CH 0, Rank 1
6992 09:58:01.768245 SW Impedance : PASS
6993 09:58:01.768341 DUTY Scan : NO K
6994 09:58:01.771338 ZQ Calibration : PASS
6995 09:58:01.774644 Jitter Meter : NO K
6996 09:58:01.774719 CBT Training : PASS
6997 09:58:01.777961 Write leveling : NO K
6998 09:58:01.781441 RX DQS gating : PASS
6999 09:58:01.781543 RX DQ/DQS(RDDQC) : PASS
7000 09:58:01.784508 TX DQ/DQS : PASS
7001 09:58:01.787931 RX DATLAT : PASS
7002 09:58:01.788039 RX DQ/DQS(Engine): PASS
7003 09:58:01.791124 TX OE : NO K
7004 09:58:01.791202 All Pass.
7005 09:58:01.791266
7006 09:58:01.794430 CH 1, Rank 0
7007 09:58:01.794507 SW Impedance : PASS
7008 09:58:01.798051 DUTY Scan : NO K
7009 09:58:01.800854 ZQ Calibration : PASS
7010 09:58:01.800951 Jitter Meter : NO K
7011 09:58:01.804211 CBT Training : PASS
7012 09:58:01.808215 Write leveling : PASS
7013 09:58:01.808312 RX DQS gating : PASS
7014 09:58:01.811242 RX DQ/DQS(RDDQC) : PASS
7015 09:58:01.814508 TX DQ/DQS : PASS
7016 09:58:01.814604 RX DATLAT : PASS
7017 09:58:01.817812 RX DQ/DQS(Engine): PASS
7018 09:58:01.820932 TX OE : NO K
7019 09:58:01.821007 All Pass.
7020 09:58:01.821069
7021 09:58:01.821126 CH 1, Rank 1
7022 09:58:01.823919 SW Impedance : PASS
7023 09:58:01.827211 DUTY Scan : NO K
7024 09:58:01.827309 ZQ Calibration : PASS
7025 09:58:01.830471 Jitter Meter : NO K
7026 09:58:01.834388 CBT Training : PASS
7027 09:58:01.834488 Write leveling : NO K
7028 09:58:01.837333 RX DQS gating : PASS
7029 09:58:01.837429 RX DQ/DQS(RDDQC) : PASS
7030 09:58:01.840693 TX DQ/DQS : PASS
7031 09:58:01.844033 RX DATLAT : PASS
7032 09:58:01.844134 RX DQ/DQS(Engine): PASS
7033 09:58:01.847107 TX OE : NO K
7034 09:58:01.847206 All Pass.
7035 09:58:01.847289
7036 09:58:01.850725 DramC Write-DBI off
7037 09:58:01.853606 PER_BANK_REFRESH: Hybrid Mode
7038 09:58:01.853705 TX_TRACKING: ON
7039 09:58:01.863862 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 09:58:01.866987 [FAST_K] Save calibration result to emmc
7041 09:58:01.870474 dramc_set_vcore_voltage set vcore to 725000
7042 09:58:01.873834 Read voltage for 1600, 0
7043 09:58:01.873930 Vio18 = 0
7044 09:58:01.876839 Vcore = 725000
7045 09:58:01.876911 Vdram = 0
7046 09:58:01.876979 Vddq = 0
7047 09:58:01.877037 Vmddr = 0
7048 09:58:01.883296 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 09:58:01.889818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 09:58:01.889919 MEM_TYPE=3, freq_sel=13
7051 09:58:01.893230 sv_algorithm_assistance_LP4_3733
7052 09:58:01.896601 ============ PULL DRAM RESETB DOWN ============
7053 09:58:01.903272 ========== PULL DRAM RESETB DOWN end =========
7054 09:58:01.906653 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 09:58:01.909918 ===================================
7056 09:58:01.912953 LPDDR4 DRAM CONFIGURATION
7057 09:58:01.916273 ===================================
7058 09:58:01.916346 EX_ROW_EN[0] = 0x0
7059 09:58:01.919822 EX_ROW_EN[1] = 0x0
7060 09:58:01.922678 LP4Y_EN = 0x0
7061 09:58:01.922751 WORK_FSP = 0x1
7062 09:58:01.926202 WL = 0x5
7063 09:58:01.926307 RL = 0x5
7064 09:58:01.929336 BL = 0x2
7065 09:58:01.929432 RPST = 0x0
7066 09:58:01.932861 RD_PRE = 0x0
7067 09:58:01.932960 WR_PRE = 0x1
7068 09:58:01.936471 WR_PST = 0x1
7069 09:58:01.936567 DBI_WR = 0x0
7070 09:58:01.939198 DBI_RD = 0x0
7071 09:58:01.939272 OTF = 0x1
7072 09:58:01.942417 ===================================
7073 09:58:01.946571 ===================================
7074 09:58:01.949442 ANA top config
7075 09:58:01.952630 ===================================
7076 09:58:01.952736 DLL_ASYNC_EN = 0
7077 09:58:01.956104 ALL_SLAVE_EN = 0
7078 09:58:01.959309 NEW_RANK_MODE = 1
7079 09:58:01.962672 DLL_IDLE_MODE = 1
7080 09:58:01.965545 LP45_APHY_COMB_EN = 1
7081 09:58:01.965641 TX_ODT_DIS = 0
7082 09:58:01.968648 NEW_8X_MODE = 1
7083 09:58:01.972563 ===================================
7084 09:58:01.975243 ===================================
7085 09:58:01.978808 data_rate = 3200
7086 09:58:01.981917 CKR = 1
7087 09:58:01.985556 DQ_P2S_RATIO = 8
7088 09:58:01.988350 ===================================
7089 09:58:01.991668 CA_P2S_RATIO = 8
7090 09:58:01.995051 DQ_CA_OPEN = 0
7091 09:58:01.995147 DQ_SEMI_OPEN = 0
7092 09:58:01.998682 CA_SEMI_OPEN = 0
7093 09:58:02.001596 CA_FULL_RATE = 0
7094 09:58:02.004908 DQ_CKDIV4_EN = 0
7095 09:58:02.008289 CA_CKDIV4_EN = 0
7096 09:58:02.011462 CA_PREDIV_EN = 0
7097 09:58:02.011534 PH8_DLY = 12
7098 09:58:02.015274 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 09:58:02.018084 DQ_AAMCK_DIV = 4
7100 09:58:02.021606 CA_AAMCK_DIV = 4
7101 09:58:02.024457 CA_ADMCK_DIV = 4
7102 09:58:02.027714 DQ_TRACK_CA_EN = 0
7103 09:58:02.030951 CA_PICK = 1600
7104 09:58:02.031054 CA_MCKIO = 1600
7105 09:58:02.034194 MCKIO_SEMI = 0
7106 09:58:02.037930 PLL_FREQ = 3068
7107 09:58:02.040823 DQ_UI_PI_RATIO = 32
7108 09:58:02.044178 CA_UI_PI_RATIO = 0
7109 09:58:02.047784 ===================================
7110 09:58:02.050727 ===================================
7111 09:58:02.053915 memory_type:LPDDR4
7112 09:58:02.054011 GP_NUM : 10
7113 09:58:02.057410 SRAM_EN : 1
7114 09:58:02.060996 MD32_EN : 0
7115 09:58:02.064232 ===================================
7116 09:58:02.064302 [ANA_INIT] >>>>>>>>>>>>>>
7117 09:58:02.067632 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 09:58:02.070736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 09:58:02.073782 ===================================
7120 09:58:02.077362 data_rate = 3200,PCW = 0X7600
7121 09:58:02.080710 ===================================
7122 09:58:02.083493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 09:58:02.090732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 09:58:02.093892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 09:58:02.100150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 09:58:02.103484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 09:58:02.106600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 09:58:02.106702 [ANA_INIT] flow start
7129 09:58:02.110431 [ANA_INIT] PLL >>>>>>>>
7130 09:58:02.113695 [ANA_INIT] PLL <<<<<<<<
7131 09:58:02.116522 [ANA_INIT] MIDPI >>>>>>>>
7132 09:58:02.116605 [ANA_INIT] MIDPI <<<<<<<<
7133 09:58:02.119816 [ANA_INIT] DLL >>>>>>>>
7134 09:58:02.123188 [ANA_INIT] DLL <<<<<<<<
7135 09:58:02.123263 [ANA_INIT] flow end
7136 09:58:02.126432 ============ LP4 DIFF to SE enter ============
7137 09:58:02.133114 ============ LP4 DIFF to SE exit ============
7138 09:58:02.133216 [ANA_INIT] <<<<<<<<<<<<<
7139 09:58:02.136502 [Flow] Enable top DCM control >>>>>
7140 09:58:02.139659 [Flow] Enable top DCM control <<<<<
7141 09:58:02.142860 Enable DLL master slave shuffle
7142 09:58:02.149505 ==============================================================
7143 09:58:02.153019 Gating Mode config
7144 09:58:02.156377 ==============================================================
7145 09:58:02.159839 Config description:
7146 09:58:02.169576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 09:58:02.175957 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 09:58:02.179008 SELPH_MODE 0: By rank 1: By Phase
7149 09:58:02.185958 ==============================================================
7150 09:58:02.188882 GAT_TRACK_EN = 1
7151 09:58:02.192590 RX_GATING_MODE = 2
7152 09:58:02.195409 RX_GATING_TRACK_MODE = 2
7153 09:58:02.199208 SELPH_MODE = 1
7154 09:58:02.202050 PICG_EARLY_EN = 1
7155 09:58:02.202146 VALID_LAT_VALUE = 1
7156 09:58:02.208609 ==============================================================
7157 09:58:02.212485 Enter into Gating configuration >>>>
7158 09:58:02.215623 Exit from Gating configuration <<<<
7159 09:58:02.219278 Enter into DVFS_PRE_config >>>>>
7160 09:58:02.228661 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 09:58:02.232186 Exit from DVFS_PRE_config <<<<<
7162 09:58:02.235188 Enter into PICG configuration >>>>
7163 09:58:02.238294 Exit from PICG configuration <<<<
7164 09:58:02.242020 [RX_INPUT] configuration >>>>>
7165 09:58:02.245168 [RX_INPUT] configuration <<<<<
7166 09:58:02.251713 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 09:58:02.255047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 09:58:02.261596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 09:58:02.268381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 09:58:02.274769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 09:58:02.281514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 09:58:02.284839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 09:58:02.288291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 09:58:02.291610 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 09:58:02.297791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 09:58:02.301356 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 09:58:02.304578 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 09:58:02.307898 ===================================
7179 09:58:02.311096 LPDDR4 DRAM CONFIGURATION
7180 09:58:02.314630 ===================================
7181 09:58:02.314702 EX_ROW_EN[0] = 0x0
7182 09:58:02.318022 EX_ROW_EN[1] = 0x0
7183 09:58:02.320843 LP4Y_EN = 0x0
7184 09:58:02.320937 WORK_FSP = 0x1
7185 09:58:02.324567 WL = 0x5
7186 09:58:02.324658 RL = 0x5
7187 09:58:02.327597 BL = 0x2
7188 09:58:02.327688 RPST = 0x0
7189 09:58:02.330674 RD_PRE = 0x0
7190 09:58:02.330767 WR_PRE = 0x1
7191 09:58:02.334166 WR_PST = 0x1
7192 09:58:02.334281 DBI_WR = 0x0
7193 09:58:02.337589 DBI_RD = 0x0
7194 09:58:02.337680 OTF = 0x1
7195 09:58:02.340948 ===================================
7196 09:58:02.347127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 09:58:02.350784 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 09:58:02.354358 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 09:58:02.357458 ===================================
7200 09:58:02.360774 LPDDR4 DRAM CONFIGURATION
7201 09:58:02.363831 ===================================
7202 09:58:02.367169 EX_ROW_EN[0] = 0x10
7203 09:58:02.367266 EX_ROW_EN[1] = 0x0
7204 09:58:02.370520 LP4Y_EN = 0x0
7205 09:58:02.370589 WORK_FSP = 0x1
7206 09:58:02.373670 WL = 0x5
7207 09:58:02.373740 RL = 0x5
7208 09:58:02.376844 BL = 0x2
7209 09:58:02.376912 RPST = 0x0
7210 09:58:02.380341 RD_PRE = 0x0
7211 09:58:02.380434 WR_PRE = 0x1
7212 09:58:02.383154 WR_PST = 0x1
7213 09:58:02.383250 DBI_WR = 0x0
7214 09:58:02.386800 DBI_RD = 0x0
7215 09:58:02.386897 OTF = 0x1
7216 09:58:02.389795 ===================================
7217 09:58:02.396820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 09:58:02.396900 ==
7219 09:58:02.399701 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 09:58:02.406322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 09:58:02.406401 ==
7222 09:58:02.406472 [Duty_Offset_Calibration]
7223 09:58:02.409832 B0:2 B1:0 CA:4
7224 09:58:02.409925
7225 09:58:02.412858 [DutyScan_Calibration_Flow] k_type=0
7226 09:58:02.422043
7227 09:58:02.422142 ==CLK 0==
7228 09:58:02.425250 Final CLK duty delay cell = -4
7229 09:58:02.428504 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7230 09:58:02.431478 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7231 09:58:02.434727 [-4] AVG Duty = 4937%(X100)
7232 09:58:02.434796
7233 09:58:02.438616 CH0 CLK Duty spec in!! Max-Min= 187%
7234 09:58:02.441460 [DutyScan_Calibration_Flow] ====Done====
7235 09:58:02.441552
7236 09:58:02.444942 [DutyScan_Calibration_Flow] k_type=1
7237 09:58:02.462184
7238 09:58:02.462287 ==DQS 0 ==
7239 09:58:02.465877 Final DQS duty delay cell = 0
7240 09:58:02.468803 [0] MAX Duty = 5218%(X100), DQS PI = 38
7241 09:58:02.472036 [0] MIN Duty = 5062%(X100), DQS PI = 14
7242 09:58:02.474938 [0] AVG Duty = 5140%(X100)
7243 09:58:02.475006
7244 09:58:02.475067 ==DQS 1 ==
7245 09:58:02.478566 Final DQS duty delay cell = 0
7246 09:58:02.481953 [0] MAX Duty = 5187%(X100), DQS PI = 2
7247 09:58:02.484933 [0] MIN Duty = 4969%(X100), DQS PI = 10
7248 09:58:02.488605 [0] AVG Duty = 5078%(X100)
7249 09:58:02.488698
7250 09:58:02.491762 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7251 09:58:02.491837
7252 09:58:02.495038 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7253 09:58:02.498068 [DutyScan_Calibration_Flow] ====Done====
7254 09:58:02.498168
7255 09:58:02.501227 [DutyScan_Calibration_Flow] k_type=3
7256 09:58:02.519225
7257 09:58:02.519298 ==DQM 0 ==
7258 09:58:02.522389 Final DQM duty delay cell = 0
7259 09:58:02.525613 [0] MAX Duty = 5124%(X100), DQS PI = 20
7260 09:58:02.528916 [0] MIN Duty = 4875%(X100), DQS PI = 56
7261 09:58:02.532019 [0] AVG Duty = 4999%(X100)
7262 09:58:02.532093
7263 09:58:02.532156 ==DQM 1 ==
7264 09:58:02.535447 Final DQM duty delay cell = 0
7265 09:58:02.539563 [0] MAX Duty = 5000%(X100), DQS PI = 2
7266 09:58:02.542381 [0] MIN Duty = 4844%(X100), DQS PI = 16
7267 09:58:02.545245 [0] AVG Duty = 4922%(X100)
7268 09:58:02.545343
7269 09:58:02.549093 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7270 09:58:02.549188
7271 09:58:02.552671 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7272 09:58:02.555507 [DutyScan_Calibration_Flow] ====Done====
7273 09:58:02.555605
7274 09:58:02.558786 [DutyScan_Calibration_Flow] k_type=2
7275 09:58:02.576683
7276 09:58:02.576755 ==DQ 0 ==
7277 09:58:02.579604 Final DQ duty delay cell = 0
7278 09:58:02.583204 [0] MAX Duty = 5124%(X100), DQS PI = 22
7279 09:58:02.586100 [0] MIN Duty = 4938%(X100), DQS PI = 12
7280 09:58:02.589323 [0] AVG Duty = 5031%(X100)
7281 09:58:02.589394
7282 09:58:02.589455 ==DQ 1 ==
7283 09:58:02.592975 Final DQ duty delay cell = 0
7284 09:58:02.596103 [0] MAX Duty = 5218%(X100), DQS PI = 2
7285 09:58:02.599610 [0] MIN Duty = 4907%(X100), DQS PI = 32
7286 09:58:02.599681 [0] AVG Duty = 5062%(X100)
7287 09:58:02.602681
7288 09:58:02.606131 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7289 09:58:02.606226
7290 09:58:02.609445 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7291 09:58:02.612656 [DutyScan_Calibration_Flow] ====Done====
7292 09:58:02.612741 ==
7293 09:58:02.615834 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 09:58:02.619157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 09:58:02.619226 ==
7296 09:58:02.622526 [Duty_Offset_Calibration]
7297 09:58:02.622597 B0:0 B1:-1 CA:3
7298 09:58:02.622657
7299 09:58:02.625757 [DutyScan_Calibration_Flow] k_type=0
7300 09:58:02.635920
7301 09:58:02.635991 ==CLK 0==
7302 09:58:02.639114 Final CLK duty delay cell = -4
7303 09:58:02.642581 [-4] MAX Duty = 5062%(X100), DQS PI = 36
7304 09:58:02.645603 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7305 09:58:02.649155 [-4] AVG Duty = 4937%(X100)
7306 09:58:02.649259
7307 09:58:02.652076 CH1 CLK Duty spec in!! Max-Min= 249%
7308 09:58:02.655488 [DutyScan_Calibration_Flow] ====Done====
7309 09:58:02.655583
7310 09:58:02.659102 [DutyScan_Calibration_Flow] k_type=1
7311 09:58:02.674887
7312 09:58:02.674966 ==DQS 0 ==
7313 09:58:02.678174 Final DQS duty delay cell = 0
7314 09:58:02.682012 [0] MAX Duty = 5187%(X100), DQS PI = 62
7315 09:58:02.684842 [0] MIN Duty = 4969%(X100), DQS PI = 6
7316 09:58:02.687881 [0] AVG Duty = 5078%(X100)
7317 09:58:02.687978
7318 09:58:02.688067 ==DQS 1 ==
7319 09:58:02.691708 Final DQS duty delay cell = -4
7320 09:58:02.694725 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7321 09:58:02.698016 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7322 09:58:02.701469 [-4] AVG Duty = 4922%(X100)
7323 09:58:02.701539
7324 09:58:02.704741 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7325 09:58:02.704811
7326 09:58:02.708160 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7327 09:58:02.711058 [DutyScan_Calibration_Flow] ====Done====
7328 09:58:02.711151
7329 09:58:02.714601 [DutyScan_Calibration_Flow] k_type=3
7330 09:58:02.732015
7331 09:58:02.732085 ==DQM 0 ==
7332 09:58:02.735269 Final DQM duty delay cell = 0
7333 09:58:02.738738 [0] MAX Duty = 5031%(X100), DQS PI = 38
7334 09:58:02.742150 [0] MIN Duty = 4782%(X100), DQS PI = 6
7335 09:58:02.745519 [0] AVG Duty = 4906%(X100)
7336 09:58:02.745592
7337 09:58:02.745653 ==DQM 1 ==
7338 09:58:02.748690 Final DQM duty delay cell = 0
7339 09:58:02.751806 [0] MAX Duty = 5000%(X100), DQS PI = 14
7340 09:58:02.755353 [0] MIN Duty = 4813%(X100), DQS PI = 28
7341 09:58:02.758923 [0] AVG Duty = 4906%(X100)
7342 09:58:02.759023
7343 09:58:02.762039 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7344 09:58:02.762135
7345 09:58:02.765804 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7346 09:58:02.768213 [DutyScan_Calibration_Flow] ====Done====
7347 09:58:02.768307
7348 09:58:02.771488 [DutyScan_Calibration_Flow] k_type=2
7349 09:58:02.789448
7350 09:58:02.789553 ==DQ 0 ==
7351 09:58:02.792438 Final DQ duty delay cell = 0
7352 09:58:02.795677 [0] MAX Duty = 5187%(X100), DQS PI = 0
7353 09:58:02.798736 [0] MIN Duty = 5031%(X100), DQS PI = 6
7354 09:58:02.798859 [0] AVG Duty = 5109%(X100)
7355 09:58:02.799009
7356 09:58:02.802127 ==DQ 1 ==
7357 09:58:02.805498 Final DQ duty delay cell = 0
7358 09:58:02.808551 [0] MAX Duty = 5031%(X100), DQS PI = 0
7359 09:58:02.812146 [0] MIN Duty = 4875%(X100), DQS PI = 26
7360 09:58:02.812220 [0] AVG Duty = 4953%(X100)
7361 09:58:02.812284
7362 09:58:02.818492 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7363 09:58:02.818565
7364 09:58:02.821851 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7365 09:58:02.825281 [DutyScan_Calibration_Flow] ====Done====
7366 09:58:02.828674 nWR fixed to 30
7367 09:58:02.828751 [ModeRegInit_LP4] CH0 RK0
7368 09:58:02.831885 [ModeRegInit_LP4] CH0 RK1
7369 09:58:02.834968 [ModeRegInit_LP4] CH1 RK0
7370 09:58:02.838244 [ModeRegInit_LP4] CH1 RK1
7371 09:58:02.838322 match AC timing 5
7372 09:58:02.844844 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 09:58:02.848153 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 09:58:02.851322 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 09:58:02.857811 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 09:58:02.861426 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 09:58:02.861503 [MiockJmeterHQA]
7378 09:58:02.861564
7379 09:58:02.865111 [DramcMiockJmeter] u1RxGatingPI = 0
7380 09:58:02.867787 0 : 4252, 4027
7381 09:58:02.867885 4 : 4363, 4137
7382 09:58:02.871693 8 : 4252, 4027
7383 09:58:02.871791 12 : 4363, 4137
7384 09:58:02.874246 16 : 4363, 4138
7385 09:58:02.874356 20 : 4253, 4026
7386 09:58:02.874419 24 : 4252, 4027
7387 09:58:02.877528 28 : 4253, 4026
7388 09:58:02.877624 32 : 4366, 4140
7389 09:58:02.880601 36 : 4252, 4027
7390 09:58:02.880678 40 : 4363, 4137
7391 09:58:02.884409 44 : 4252, 4027
7392 09:58:02.884488 48 : 4253, 4026
7393 09:58:02.887239 52 : 4252, 4027
7394 09:58:02.887311 56 : 4252, 4027
7395 09:58:02.887373 60 : 4361, 4137
7396 09:58:02.890530 64 : 4253, 4029
7397 09:58:02.890626 68 : 4360, 4137
7398 09:58:02.894227 72 : 4250, 4027
7399 09:58:02.894366 76 : 4252, 4029
7400 09:58:02.897214 80 : 4250, 4026
7401 09:58:02.897311 84 : 4360, 4138
7402 09:58:02.900515 88 : 4250, 4027
7403 09:58:02.900586 92 : 4361, 4137
7404 09:58:02.900649 96 : 4250, 3153
7405 09:58:02.903937 100 : 4250, 0
7406 09:58:02.904009 104 : 4250, 0
7407 09:58:02.907173 108 : 4250, 0
7408 09:58:02.907249 112 : 4250, 0
7409 09:58:02.907310 116 : 4249, 0
7410 09:58:02.910423 120 : 4360, 0
7411 09:58:02.910520 124 : 4361, 0
7412 09:58:02.913843 128 : 4247, 0
7413 09:58:02.913913 132 : 4250, 0
7414 09:58:02.913981 136 : 4360, 0
7415 09:58:02.916708 140 : 4360, 0
7416 09:58:02.916803 144 : 4250, 0
7417 09:58:02.920417 148 : 4250, 0
7418 09:58:02.920496 152 : 4250, 0
7419 09:58:02.920557 156 : 4250, 0
7420 09:58:02.923670 160 : 4250, 0
7421 09:58:02.923744 164 : 4250, 0
7422 09:58:02.926805 168 : 4253, 0
7423 09:58:02.926874 172 : 4360, 0
7424 09:58:02.926935 176 : 4361, 0
7425 09:58:02.930372 180 : 4247, 0
7426 09:58:02.930440 184 : 4360, 0
7427 09:58:02.933722 188 : 4360, 0
7428 09:58:02.933818 192 : 4360, 0
7429 09:58:02.933907 196 : 4250, 0
7430 09:58:02.936606 200 : 4249, 0
7431 09:58:02.936676 204 : 4250, 0
7432 09:58:02.936742 208 : 4250, 0
7433 09:58:02.940201 212 : 4249, 0
7434 09:58:02.940273 216 : 4250, 0
7435 09:58:02.943458 220 : 4250, 313
7436 09:58:02.943576 224 : 4361, 4000
7437 09:58:02.947027 228 : 4250, 4026
7438 09:58:02.947196 232 : 4250, 4027
7439 09:58:02.950369 236 : 4252, 4030
7440 09:58:02.950478 240 : 4250, 4026
7441 09:58:02.953544 244 : 4250, 4027
7442 09:58:02.953616 248 : 4250, 4027
7443 09:58:02.953679 252 : 4250, 4027
7444 09:58:02.956309 256 : 4250, 4026
7445 09:58:02.956406 260 : 4361, 4137
7446 09:58:02.959780 264 : 4360, 4138
7447 09:58:02.959883 268 : 4247, 4024
7448 09:58:02.962930 272 : 4360, 4137
7449 09:58:02.963007 276 : 4361, 4137
7450 09:58:02.967139 280 : 4250, 4027
7451 09:58:02.967225 284 : 4250, 4027
7452 09:58:02.970101 288 : 4249, 4027
7453 09:58:02.970210 292 : 4250, 4026
7454 09:58:02.973424 296 : 4250, 4027
7455 09:58:02.973504 300 : 4250, 4027
7456 09:58:02.976650 304 : 4250, 4027
7457 09:58:02.976752 308 : 4250, 4026
7458 09:58:02.979516 312 : 4361, 4137
7459 09:58:02.979620 316 : 4360, 4138
7460 09:58:02.979714 320 : 4247, 4024
7461 09:58:02.983356 324 : 4364, 4140
7462 09:58:02.983464 328 : 4361, 4137
7463 09:58:02.986058 332 : 4250, 3950
7464 09:58:02.986159 336 : 4250, 2069
7465 09:58:02.986257
7466 09:58:02.989239 MIOCK jitter meter ch=0
7467 09:58:02.989340
7468 09:58:02.992729 1T = (336-100) = 236 dly cells
7469 09:58:02.999529 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7470 09:58:02.999629 ==
7471 09:58:03.002618 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 09:58:03.006123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 09:58:03.006226 ==
7474 09:58:03.012672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 09:58:03.015903 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 09:58:03.019113 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 09:58:03.025484 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 09:58:03.035129 [CA 0] Center 43 (13~73) winsize 61
7479 09:58:03.038340 [CA 1] Center 43 (13~73) winsize 61
7480 09:58:03.041560 [CA 2] Center 38 (9~67) winsize 59
7481 09:58:03.045029 [CA 3] Center 37 (8~67) winsize 60
7482 09:58:03.048202 [CA 4] Center 35 (6~65) winsize 60
7483 09:58:03.052009 [CA 5] Center 35 (5~66) winsize 62
7484 09:58:03.052114
7485 09:58:03.054429 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7486 09:58:03.054525
7487 09:58:03.060930 [CATrainingPosCal] consider 1 rank data
7488 09:58:03.061031 u2DelayCellTimex100 = 275/100 ps
7489 09:58:03.067681 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7490 09:58:03.071377 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7491 09:58:03.074077 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7492 09:58:03.077450 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7493 09:58:03.080832 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7494 09:58:03.083913 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7495 09:58:03.084014
7496 09:58:03.087550 CA PerBit enable=1, Macro0, CA PI delay=35
7497 09:58:03.087655
7498 09:58:03.090939 [CBTSetCACLKResult] CA Dly = 35
7499 09:58:03.094497 CS Dly: 10 (0~41)
7500 09:58:03.097876 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 09:58:03.100604 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 09:58:03.100704 ==
7503 09:58:03.103755 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 09:58:03.110235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 09:58:03.110370 ==
7506 09:58:03.113919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 09:58:03.120457 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 09:58:03.123442 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 09:58:03.130064 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 09:58:03.138803 [CA 0] Center 44 (14~75) winsize 62
7511 09:58:03.141645 [CA 1] Center 44 (14~74) winsize 61
7512 09:58:03.144851 [CA 2] Center 39 (10~69) winsize 60
7513 09:58:03.148974 [CA 3] Center 39 (10~68) winsize 59
7514 09:58:03.151433 [CA 4] Center 37 (7~67) winsize 61
7515 09:58:03.155111 [CA 5] Center 36 (6~66) winsize 61
7516 09:58:03.155215
7517 09:58:03.158446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 09:58:03.158545
7519 09:58:03.164892 [CATrainingPosCal] consider 2 rank data
7520 09:58:03.164995 u2DelayCellTimex100 = 275/100 ps
7521 09:58:03.171091 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7522 09:58:03.174659 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7523 09:58:03.177851 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7524 09:58:03.181185 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7525 09:58:03.184406 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7526 09:58:03.187830 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7527 09:58:03.187930
7528 09:58:03.191358 CA PerBit enable=1, Macro0, CA PI delay=36
7529 09:58:03.191468
7530 09:58:03.194874 [CBTSetCACLKResult] CA Dly = 36
7531 09:58:03.197936 CS Dly: 11 (0~44)
7532 09:58:03.201257 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 09:58:03.204324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 09:58:03.204419
7535 09:58:03.208036 ----->DramcWriteLeveling(PI) begin...
7536 09:58:03.210644 ==
7537 09:58:03.213963 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 09:58:03.217520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 09:58:03.217628 ==
7540 09:58:03.221079 Write leveling (Byte 0): 34 => 34
7541 09:58:03.223912 Write leveling (Byte 1): 26 => 26
7542 09:58:03.227238 DramcWriteLeveling(PI) end<-----
7543 09:58:03.227312
7544 09:58:03.227405 ==
7545 09:58:03.231079 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 09:58:03.233820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 09:58:03.233919 ==
7548 09:58:03.237622 [Gating] SW mode calibration
7549 09:58:03.244029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 09:58:03.250365 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 09:58:03.253550 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 09:58:03.257248 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 09:58:03.263808 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 09:58:03.267244 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7555 09:58:03.270062 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7556 09:58:03.276444 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7557 09:58:03.280311 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 09:58:03.283653 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 09:58:03.289699 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 09:58:03.293008 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 09:58:03.296538 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
7562 09:58:03.302979 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
7563 09:58:03.306451 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7564 09:58:03.309915 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
7565 09:58:03.316217 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
7566 09:58:03.319594 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 09:58:03.322894 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 09:58:03.329558 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 09:58:03.332815 1 6 8 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
7570 09:58:03.335994 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7571 09:58:03.342562 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7572 09:58:03.346003 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7573 09:58:03.349236 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 09:58:03.355853 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 09:58:03.359153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 09:58:03.362394 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 09:58:03.369012 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 09:58:03.372221 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 09:58:03.375568 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7580 09:58:03.382419 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 09:58:03.385362 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 09:58:03.388792 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 09:58:03.395635 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 09:58:03.398501 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 09:58:03.402582 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 09:58:03.408463 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 09:58:03.411809 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 09:58:03.415313 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 09:58:03.422058 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 09:58:03.425062 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 09:58:03.428278 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 09:58:03.435942 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 09:58:03.438174 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 09:58:03.441722 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 09:58:03.448226 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7596 09:58:03.448336 Total UI for P1: 0, mck2ui 16
7597 09:58:03.454707 best dqsien dly found for B0: ( 1, 9, 10)
7598 09:58:03.457759 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 09:58:03.460846 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7600 09:58:03.467462 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 09:58:03.467542 Total UI for P1: 0, mck2ui 16
7602 09:58:03.474088 best dqsien dly found for B1: ( 1, 9, 22)
7603 09:58:03.478006 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7604 09:58:03.481366 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7605 09:58:03.481474
7606 09:58:03.484328 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7607 09:58:03.487340 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7608 09:58:03.491156 [Gating] SW calibration Done
7609 09:58:03.491237 ==
7610 09:58:03.494550 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 09:58:03.497236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 09:58:03.497318 ==
7613 09:58:03.500920 RX Vref Scan: 0
7614 09:58:03.501039
7615 09:58:03.503977 RX Vref 0 -> 0, step: 1
7616 09:58:03.504058
7617 09:58:03.504122 RX Delay 0 -> 252, step: 8
7618 09:58:03.510712 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7619 09:58:03.514140 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7620 09:58:03.517406 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7621 09:58:03.520562 iDelay=192, Bit 3, Center 127 (80 ~ 175) 96
7622 09:58:03.524097 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7623 09:58:03.530015 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7624 09:58:03.533583 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7625 09:58:03.537205 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7626 09:58:03.540263 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7627 09:58:03.543909 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7628 09:58:03.550215 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7629 09:58:03.553309 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7630 09:58:03.556553 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7631 09:58:03.559993 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7632 09:58:03.563619 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7633 09:58:03.570149 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7634 09:58:03.570230 ==
7635 09:58:03.572944 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 09:58:03.576723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 09:58:03.576805 ==
7638 09:58:03.576870 DQS Delay:
7639 09:58:03.579857 DQS0 = 0, DQS1 = 0
7640 09:58:03.580012 DQM Delay:
7641 09:58:03.582742 DQM0 = 131, DQM1 = 127
7642 09:58:03.582824 DQ Delay:
7643 09:58:03.585986 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7644 09:58:03.589442 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7645 09:58:03.592997 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7646 09:58:03.599577 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7647 09:58:03.599658
7648 09:58:03.599721
7649 09:58:03.599781 ==
7650 09:58:03.603002 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 09:58:03.606467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 09:58:03.606564 ==
7653 09:58:03.606673
7654 09:58:03.606747
7655 09:58:03.609031 TX Vref Scan disable
7656 09:58:03.609112 == TX Byte 0 ==
7657 09:58:03.615747 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7658 09:58:03.619026 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7659 09:58:03.619107 == TX Byte 1 ==
7660 09:58:03.625930 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7661 09:58:03.628894 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7662 09:58:03.628975 ==
7663 09:58:03.632998 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 09:58:03.635974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 09:58:03.636056 ==
7666 09:58:03.650567
7667 09:58:03.654138 TX Vref early break, caculate TX vref
7668 09:58:03.657817 TX Vref=16, minBit 4, minWin=22, winSum=369
7669 09:58:03.660230 TX Vref=18, minBit 8, minWin=22, winSum=380
7670 09:58:03.663332 TX Vref=20, minBit 1, minWin=23, winSum=391
7671 09:58:03.667145 TX Vref=22, minBit 1, minWin=24, winSum=399
7672 09:58:03.673389 TX Vref=24, minBit 0, minWin=25, winSum=410
7673 09:58:03.676564 TX Vref=26, minBit 3, minWin=25, winSum=415
7674 09:58:03.679694 TX Vref=28, minBit 4, minWin=25, winSum=422
7675 09:58:03.683204 TX Vref=30, minBit 0, minWin=25, winSum=416
7676 09:58:03.686170 TX Vref=32, minBit 2, minWin=24, winSum=408
7677 09:58:03.689649 TX Vref=34, minBit 0, minWin=24, winSum=398
7678 09:58:03.696461 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
7679 09:58:03.696560
7680 09:58:03.699458 Final TX Range 0 Vref 28
7681 09:58:03.699540
7682 09:58:03.699603 ==
7683 09:58:03.703109 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 09:58:03.706637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 09:58:03.706718 ==
7686 09:58:03.706782
7687 09:58:03.709284
7688 09:58:03.709364 TX Vref Scan disable
7689 09:58:03.716706 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7690 09:58:03.716787 == TX Byte 0 ==
7691 09:58:03.719233 u2DelayCellOfst[0]=14 cells (4 PI)
7692 09:58:03.722663 u2DelayCellOfst[1]=17 cells (5 PI)
7693 09:58:03.726176 u2DelayCellOfst[2]=14 cells (4 PI)
7694 09:58:03.729177 u2DelayCellOfst[3]=14 cells (4 PI)
7695 09:58:03.733054 u2DelayCellOfst[4]=10 cells (3 PI)
7696 09:58:03.735822 u2DelayCellOfst[5]=0 cells (0 PI)
7697 09:58:03.739407 u2DelayCellOfst[6]=17 cells (5 PI)
7698 09:58:03.742642 u2DelayCellOfst[7]=17 cells (5 PI)
7699 09:58:03.745640 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7700 09:58:03.748961 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7701 09:58:03.751892 == TX Byte 1 ==
7702 09:58:03.755642 u2DelayCellOfst[8]=0 cells (0 PI)
7703 09:58:03.758695 u2DelayCellOfst[9]=0 cells (0 PI)
7704 09:58:03.761737 u2DelayCellOfst[10]=3 cells (1 PI)
7705 09:58:03.765414 u2DelayCellOfst[11]=3 cells (1 PI)
7706 09:58:03.768740 u2DelayCellOfst[12]=10 cells (3 PI)
7707 09:58:03.771818 u2DelayCellOfst[13]=10 cells (3 PI)
7708 09:58:03.775418 u2DelayCellOfst[14]=14 cells (4 PI)
7709 09:58:03.778647 u2DelayCellOfst[15]=10 cells (3 PI)
7710 09:58:03.781448 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7711 09:58:03.785094 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7712 09:58:03.788576 DramC Write-DBI on
7713 09:58:03.788656 ==
7714 09:58:03.791333 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 09:58:03.794555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 09:58:03.794636 ==
7717 09:58:03.794700
7718 09:58:03.794798
7719 09:58:03.798077 TX Vref Scan disable
7720 09:58:03.801439 == TX Byte 0 ==
7721 09:58:03.804636 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7722 09:58:03.804718 == TX Byte 1 ==
7723 09:58:03.811750 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7724 09:58:03.811831 DramC Write-DBI off
7725 09:58:03.811895
7726 09:58:03.811955 [DATLAT]
7727 09:58:03.814902 Freq=1600, CH0 RK0
7728 09:58:03.814983
7729 09:58:03.818210 DATLAT Default: 0xf
7730 09:58:03.818331 0, 0xFFFF, sum = 0
7731 09:58:03.821366 1, 0xFFFF, sum = 0
7732 09:58:03.821447 2, 0xFFFF, sum = 0
7733 09:58:03.824797 3, 0xFFFF, sum = 0
7734 09:58:03.824879 4, 0xFFFF, sum = 0
7735 09:58:03.827868 5, 0xFFFF, sum = 0
7736 09:58:03.827950 6, 0xFFFF, sum = 0
7737 09:58:03.831232 7, 0xFFFF, sum = 0
7738 09:58:03.831314 8, 0xFFFF, sum = 0
7739 09:58:03.834485 9, 0xFFFF, sum = 0
7740 09:58:03.834567 10, 0xFFFF, sum = 0
7741 09:58:03.837490 11, 0xFFFF, sum = 0
7742 09:58:03.837572 12, 0xFFFF, sum = 0
7743 09:58:03.841323 13, 0xFFFF, sum = 0
7744 09:58:03.841405 14, 0x0, sum = 1
7745 09:58:03.844647 15, 0x0, sum = 2
7746 09:58:03.844729 16, 0x0, sum = 3
7747 09:58:03.847943 17, 0x0, sum = 4
7748 09:58:03.848025 best_step = 15
7749 09:58:03.848088
7750 09:58:03.848148 ==
7751 09:58:03.851081 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 09:58:03.857904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 09:58:03.858057 ==
7754 09:58:03.858152 RX Vref Scan: 1
7755 09:58:03.858241
7756 09:58:03.861025 Set Vref Range= 24 -> 127
7757 09:58:03.861106
7758 09:58:03.864279 RX Vref 24 -> 127, step: 1
7759 09:58:03.864387
7760 09:58:03.867629 RX Delay 11 -> 252, step: 4
7761 09:58:03.867710
7762 09:58:03.870649 Set Vref, RX VrefLevel [Byte0]: 24
7763 09:58:03.874176 [Byte1]: 24
7764 09:58:03.874267
7765 09:58:03.877907 Set Vref, RX VrefLevel [Byte0]: 25
7766 09:58:03.880754 [Byte1]: 25
7767 09:58:03.880834
7768 09:58:03.884208 Set Vref, RX VrefLevel [Byte0]: 26
7769 09:58:03.887646 [Byte1]: 26
7770 09:58:03.890228
7771 09:58:03.890320 Set Vref, RX VrefLevel [Byte0]: 27
7772 09:58:03.893653 [Byte1]: 27
7773 09:58:03.897896
7774 09:58:03.897978 Set Vref, RX VrefLevel [Byte0]: 28
7775 09:58:03.901214 [Byte1]: 28
7776 09:58:03.905757
7777 09:58:03.905871 Set Vref, RX VrefLevel [Byte0]: 29
7778 09:58:03.908880 [Byte1]: 29
7779 09:58:03.913129
7780 09:58:03.913209 Set Vref, RX VrefLevel [Byte0]: 30
7781 09:58:03.916667 [Byte1]: 30
7782 09:58:03.920967
7783 09:58:03.921047 Set Vref, RX VrefLevel [Byte0]: 31
7784 09:58:03.924009 [Byte1]: 31
7785 09:58:03.928694
7786 09:58:03.928774 Set Vref, RX VrefLevel [Byte0]: 32
7787 09:58:03.932087 [Byte1]: 32
7788 09:58:03.936013
7789 09:58:03.936094 Set Vref, RX VrefLevel [Byte0]: 33
7790 09:58:03.939347 [Byte1]: 33
7791 09:58:03.943994
7792 09:58:03.944098 Set Vref, RX VrefLevel [Byte0]: 34
7793 09:58:03.947540 [Byte1]: 34
7794 09:58:03.951170
7795 09:58:03.951275 Set Vref, RX VrefLevel [Byte0]: 35
7796 09:58:03.954513 [Byte1]: 35
7797 09:58:03.958823
7798 09:58:03.958903 Set Vref, RX VrefLevel [Byte0]: 36
7799 09:58:03.962323 [Byte1]: 36
7800 09:58:03.966296
7801 09:58:03.969530 Set Vref, RX VrefLevel [Byte0]: 37
7802 09:58:03.972924 [Byte1]: 37
7803 09:58:03.973007
7804 09:58:03.976607 Set Vref, RX VrefLevel [Byte0]: 38
7805 09:58:03.980108 [Byte1]: 38
7806 09:58:03.980192
7807 09:58:03.983005 Set Vref, RX VrefLevel [Byte0]: 39
7808 09:58:03.986265 [Byte1]: 39
7809 09:58:03.986349
7810 09:58:03.989643 Set Vref, RX VrefLevel [Byte0]: 40
7811 09:58:03.992561 [Byte1]: 40
7812 09:58:03.996873
7813 09:58:03.996956 Set Vref, RX VrefLevel [Byte0]: 41
7814 09:58:04.000261 [Byte1]: 41
7815 09:58:04.004374
7816 09:58:04.004456 Set Vref, RX VrefLevel [Byte0]: 42
7817 09:58:04.008052 [Byte1]: 42
7818 09:58:04.012458
7819 09:58:04.012541 Set Vref, RX VrefLevel [Byte0]: 43
7820 09:58:04.015657 [Byte1]: 43
7821 09:58:04.020077
7822 09:58:04.020160 Set Vref, RX VrefLevel [Byte0]: 44
7823 09:58:04.022855 [Byte1]: 44
7824 09:58:04.027742
7825 09:58:04.027823 Set Vref, RX VrefLevel [Byte0]: 45
7826 09:58:04.030962 [Byte1]: 45
7827 09:58:04.035001
7828 09:58:04.035082 Set Vref, RX VrefLevel [Byte0]: 46
7829 09:58:04.038324 [Byte1]: 46
7830 09:58:04.042933
7831 09:58:04.043015 Set Vref, RX VrefLevel [Byte0]: 47
7832 09:58:04.046257 [Byte1]: 47
7833 09:58:04.050078
7834 09:58:04.050161 Set Vref, RX VrefLevel [Byte0]: 48
7835 09:58:04.053369 [Byte1]: 48
7836 09:58:04.057823
7837 09:58:04.057905 Set Vref, RX VrefLevel [Byte0]: 49
7838 09:58:04.061322 [Byte1]: 49
7839 09:58:04.065493
7840 09:58:04.065575 Set Vref, RX VrefLevel [Byte0]: 50
7841 09:58:04.068904 [Byte1]: 50
7842 09:58:04.072882
7843 09:58:04.072962 Set Vref, RX VrefLevel [Byte0]: 51
7844 09:58:04.076250 [Byte1]: 51
7845 09:58:04.080687
7846 09:58:04.080768 Set Vref, RX VrefLevel [Byte0]: 52
7847 09:58:04.084018 [Byte1]: 52
7848 09:58:04.088259
7849 09:58:04.088339 Set Vref, RX VrefLevel [Byte0]: 53
7850 09:58:04.091924 [Byte1]: 53
7851 09:58:04.095839
7852 09:58:04.095950 Set Vref, RX VrefLevel [Byte0]: 54
7853 09:58:04.099574 [Byte1]: 54
7854 09:58:04.104065
7855 09:58:04.104161 Set Vref, RX VrefLevel [Byte0]: 55
7856 09:58:04.106775 [Byte1]: 55
7857 09:58:04.111045
7858 09:58:04.111128 Set Vref, RX VrefLevel [Byte0]: 56
7859 09:58:04.114344 [Byte1]: 56
7860 09:58:04.118520
7861 09:58:04.118631 Set Vref, RX VrefLevel [Byte0]: 57
7862 09:58:04.122121 [Byte1]: 57
7863 09:58:04.126137
7864 09:58:04.126217 Set Vref, RX VrefLevel [Byte0]: 58
7865 09:58:04.130096 [Byte1]: 58
7866 09:58:04.134084
7867 09:58:04.134164 Set Vref, RX VrefLevel [Byte0]: 59
7868 09:58:04.137171 [Byte1]: 59
7869 09:58:04.141646
7870 09:58:04.141727 Set Vref, RX VrefLevel [Byte0]: 60
7871 09:58:04.145024 [Byte1]: 60
7872 09:58:04.149179
7873 09:58:04.149261 Set Vref, RX VrefLevel [Byte0]: 61
7874 09:58:04.152662 [Byte1]: 61
7875 09:58:04.156875
7876 09:58:04.156955 Set Vref, RX VrefLevel [Byte0]: 62
7877 09:58:04.160210 [Byte1]: 62
7878 09:58:04.164209
7879 09:58:04.164289 Set Vref, RX VrefLevel [Byte0]: 63
7880 09:58:04.167937 [Byte1]: 63
7881 09:58:04.172577
7882 09:58:04.172658 Set Vref, RX VrefLevel [Byte0]: 64
7883 09:58:04.175527 [Byte1]: 64
7884 09:58:04.179585
7885 09:58:04.179666 Set Vref, RX VrefLevel [Byte0]: 65
7886 09:58:04.183407 [Byte1]: 65
7887 09:58:04.187261
7888 09:58:04.187342 Set Vref, RX VrefLevel [Byte0]: 66
7889 09:58:04.190839 [Byte1]: 66
7890 09:58:04.194769
7891 09:58:04.194851 Set Vref, RX VrefLevel [Byte0]: 67
7892 09:58:04.198552 [Byte1]: 67
7893 09:58:04.202482
7894 09:58:04.202564 Set Vref, RX VrefLevel [Byte0]: 68
7895 09:58:04.205586 [Byte1]: 68
7896 09:58:04.210256
7897 09:58:04.210339 Set Vref, RX VrefLevel [Byte0]: 69
7898 09:58:04.213214 [Byte1]: 69
7899 09:58:04.217818
7900 09:58:04.217899 Set Vref, RX VrefLevel [Byte0]: 70
7901 09:58:04.221541 [Byte1]: 70
7902 09:58:04.225973
7903 09:58:04.226054 Set Vref, RX VrefLevel [Byte0]: 71
7904 09:58:04.229270 [Byte1]: 71
7905 09:58:04.232878
7906 09:58:04.232986 Set Vref, RX VrefLevel [Byte0]: 72
7907 09:58:04.236576 [Byte1]: 72
7908 09:58:04.240353
7909 09:58:04.240454 Set Vref, RX VrefLevel [Byte0]: 73
7910 09:58:04.243799 [Byte1]: 73
7911 09:58:04.248286
7912 09:58:04.248388 Set Vref, RX VrefLevel [Byte0]: 74
7913 09:58:04.251770 [Byte1]: 74
7914 09:58:04.255937
7915 09:58:04.256037 Final RX Vref Byte 0 = 61 to rank0
7916 09:58:04.258899 Final RX Vref Byte 1 = 58 to rank0
7917 09:58:04.262645 Final RX Vref Byte 0 = 61 to rank1
7918 09:58:04.266223 Final RX Vref Byte 1 = 58 to rank1==
7919 09:58:04.269172 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 09:58:04.275498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 09:58:04.275578 ==
7922 09:58:04.275647 DQS Delay:
7923 09:58:04.278971 DQS0 = 0, DQS1 = 0
7924 09:58:04.279045 DQM Delay:
7925 09:58:04.282173 DQM0 = 129, DQM1 = 124
7926 09:58:04.282300 DQ Delay:
7927 09:58:04.285542 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7928 09:58:04.288721 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
7929 09:58:04.291624 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7930 09:58:04.294864 DQ12 =132, DQ13 =128, DQ14 =132, DQ15 =130
7931 09:58:04.294945
7932 09:58:04.295008
7933 09:58:04.295066
7934 09:58:04.298189 [DramC_TX_OE_Calibration] TA2
7935 09:58:04.301630 Original DQ_B0 (3 6) =30, OEN = 27
7936 09:58:04.305120 Original DQ_B1 (3 6) =30, OEN = 27
7937 09:58:04.308013 24, 0x0, End_B0=24 End_B1=24
7938 09:58:04.311356 25, 0x0, End_B0=25 End_B1=25
7939 09:58:04.311439 26, 0x0, End_B0=26 End_B1=26
7940 09:58:04.315066 27, 0x0, End_B0=27 End_B1=27
7941 09:58:04.317929 28, 0x0, End_B0=28 End_B1=28
7942 09:58:04.321510 29, 0x0, End_B0=29 End_B1=29
7943 09:58:04.325187 30, 0x0, End_B0=30 End_B1=30
7944 09:58:04.325266 31, 0x4545, End_B0=30 End_B1=30
7945 09:58:04.327657 Byte0 end_step=30 best_step=27
7946 09:58:04.331076 Byte1 end_step=30 best_step=27
7947 09:58:04.334345 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 09:58:04.337970 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 09:58:04.338043
7950 09:58:04.338103
7951 09:58:04.344003 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7952 09:58:04.347313 CH0 RK0: MR19=303, MR18=1A17
7953 09:58:04.354147 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7954 09:58:04.354273
7955 09:58:04.357464 ----->DramcWriteLeveling(PI) begin...
7956 09:58:04.357539 ==
7957 09:58:04.360793 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 09:58:04.367335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 09:58:04.367416 ==
7960 09:58:04.370340 Write leveling (Byte 0): 35 => 35
7961 09:58:04.370415 Write leveling (Byte 1): 27 => 27
7962 09:58:04.373574 DramcWriteLeveling(PI) end<-----
7963 09:58:04.373648
7964 09:58:04.373717 ==
7965 09:58:04.377053 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 09:58:04.383663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 09:58:04.383750 ==
7968 09:58:04.387158 [Gating] SW mode calibration
7969 09:58:04.393705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 09:58:04.396903 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 09:58:04.403351 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 09:58:04.406898 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 09:58:04.410019 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7974 09:58:04.416835 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7975 09:58:04.419865 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7976 09:58:04.423173 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7977 09:58:04.430145 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 09:58:04.433151 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 09:58:04.436492 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 09:58:04.443204 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7981 09:58:04.446058 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7982 09:58:04.449946 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
7983 09:58:04.456164 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7984 09:58:04.459450 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7985 09:58:04.462577 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 09:58:04.469482 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 09:58:04.473067 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 09:58:04.475907 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 09:58:04.482215 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7990 09:58:04.486061 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7991 09:58:04.488948 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7992 09:58:04.495702 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 09:58:04.498849 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 09:58:04.502150 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 09:58:04.509031 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 09:58:04.511922 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 09:58:04.515504 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7998 09:58:04.522379 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7999 09:58:04.525866 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8000 09:58:04.528550 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8001 09:58:04.535193 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 09:58:04.538501 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 09:58:04.541585 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 09:58:04.548564 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 09:58:04.551727 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 09:58:04.555044 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 09:58:04.562009 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 09:58:04.564715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 09:58:04.568030 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 09:58:04.574519 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 09:58:04.577764 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 09:58:04.581102 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 09:58:04.587754 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8014 09:58:04.591073 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8015 09:58:04.594533 Total UI for P1: 0, mck2ui 16
8016 09:58:04.597472 best dqsien dly found for B0: ( 1, 9, 8)
8017 09:58:04.601225 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8018 09:58:04.607853 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8019 09:58:04.610902 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8020 09:58:04.614631 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 09:58:04.617460 Total UI for P1: 0, mck2ui 16
8022 09:58:04.620860 best dqsien dly found for B1: ( 1, 9, 20)
8023 09:58:04.624242 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8024 09:58:04.627465 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8025 09:58:04.627572
8026 09:58:04.634231 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8027 09:58:04.637182 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8028 09:58:04.640689 [Gating] SW calibration Done
8029 09:58:04.640765 ==
8030 09:58:04.643649 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 09:58:04.647064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 09:58:04.647143 ==
8033 09:58:04.647225 RX Vref Scan: 0
8034 09:58:04.647330
8035 09:58:04.650951 RX Vref 0 -> 0, step: 1
8036 09:58:04.651032
8037 09:58:04.653521 RX Delay 0 -> 252, step: 8
8038 09:58:04.657110 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8039 09:58:04.660209 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8040 09:58:04.666936 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8041 09:58:04.670093 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8042 09:58:04.673408 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8043 09:58:04.677287 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8044 09:58:04.680613 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8045 09:58:04.686591 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8046 09:58:04.689980 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8047 09:58:04.693244 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8048 09:58:04.696626 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8049 09:58:04.699851 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8050 09:58:04.706733 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8051 09:58:04.709866 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8052 09:58:04.713493 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8053 09:58:04.716512 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8054 09:58:04.716590 ==
8055 09:58:04.719844 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 09:58:04.726878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 09:58:04.726954 ==
8058 09:58:04.727023 DQS Delay:
8059 09:58:04.730033 DQS0 = 0, DQS1 = 0
8060 09:58:04.730110 DQM Delay:
8061 09:58:04.732750 DQM0 = 132, DQM1 = 127
8062 09:58:04.732825 DQ Delay:
8063 09:58:04.736145 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8064 09:58:04.739453 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
8065 09:58:04.743074 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8066 09:58:04.746057 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8067 09:58:04.746135
8068 09:58:04.746240
8069 09:58:04.746359 ==
8070 09:58:04.749327 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 09:58:04.756073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 09:58:04.756159 ==
8073 09:58:04.756240
8074 09:58:04.756317
8075 09:58:04.756399 TX Vref Scan disable
8076 09:58:04.760170 == TX Byte 0 ==
8077 09:58:04.763031 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8078 09:58:04.769464 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8079 09:58:04.769542 == TX Byte 1 ==
8080 09:58:04.772546 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8081 09:58:04.779259 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8082 09:58:04.779343 ==
8083 09:58:04.782515 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 09:58:04.786121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 09:58:04.786234 ==
8086 09:58:04.799156
8087 09:58:04.802293 TX Vref early break, caculate TX vref
8088 09:58:04.805730 TX Vref=16, minBit 8, minWin=23, winSum=384
8089 09:58:04.809109 TX Vref=18, minBit 8, minWin=23, winSum=393
8090 09:58:04.812514 TX Vref=20, minBit 2, minWin=24, winSum=397
8091 09:58:04.815655 TX Vref=22, minBit 4, minWin=24, winSum=404
8092 09:58:04.818873 TX Vref=24, minBit 1, minWin=25, winSum=415
8093 09:58:04.825220 TX Vref=26, minBit 4, minWin=25, winSum=423
8094 09:58:04.828697 TX Vref=28, minBit 0, minWin=26, winSum=424
8095 09:58:04.831992 TX Vref=30, minBit 0, minWin=25, winSum=415
8096 09:58:04.835478 TX Vref=32, minBit 7, minWin=24, winSum=407
8097 09:58:04.838646 TX Vref=34, minBit 7, minWin=24, winSum=401
8098 09:58:04.844943 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8099 09:58:04.845023
8100 09:58:04.848257 Final TX Range 0 Vref 28
8101 09:58:04.848336
8102 09:58:04.848399 ==
8103 09:58:04.851726 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 09:58:04.855284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 09:58:04.855364 ==
8106 09:58:04.855430
8107 09:58:04.855490
8108 09:58:04.858503 TX Vref Scan disable
8109 09:58:04.864944 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8110 09:58:04.865024 == TX Byte 0 ==
8111 09:58:04.868483 u2DelayCellOfst[0]=10 cells (3 PI)
8112 09:58:04.871394 u2DelayCellOfst[1]=14 cells (4 PI)
8113 09:58:04.874803 u2DelayCellOfst[2]=7 cells (2 PI)
8114 09:58:04.878012 u2DelayCellOfst[3]=10 cells (3 PI)
8115 09:58:04.881200 u2DelayCellOfst[4]=7 cells (2 PI)
8116 09:58:04.885052 u2DelayCellOfst[5]=0 cells (0 PI)
8117 09:58:04.887974 u2DelayCellOfst[6]=14 cells (4 PI)
8118 09:58:04.891288 u2DelayCellOfst[7]=14 cells (4 PI)
8119 09:58:04.894509 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8120 09:58:04.897786 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8121 09:58:04.901127 == TX Byte 1 ==
8122 09:58:04.904532 u2DelayCellOfst[8]=0 cells (0 PI)
8123 09:58:04.907666 u2DelayCellOfst[9]=0 cells (0 PI)
8124 09:58:04.910915 u2DelayCellOfst[10]=3 cells (1 PI)
8125 09:58:04.910997 u2DelayCellOfst[11]=0 cells (0 PI)
8126 09:58:04.914152 u2DelayCellOfst[12]=10 cells (3 PI)
8127 09:58:04.917751 u2DelayCellOfst[13]=10 cells (3 PI)
8128 09:58:04.920947 u2DelayCellOfst[14]=14 cells (4 PI)
8129 09:58:04.924602 u2DelayCellOfst[15]=10 cells (3 PI)
8130 09:58:04.930830 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8131 09:58:04.934035 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8132 09:58:04.934115 DramC Write-DBI on
8133 09:58:04.937622 ==
8134 09:58:04.940586 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 09:58:04.943770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 09:58:04.943845 ==
8137 09:58:04.943909
8138 09:58:04.943976
8139 09:58:04.947601 TX Vref Scan disable
8140 09:58:04.947677 == TX Byte 0 ==
8141 09:58:04.954032 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8142 09:58:04.954111 == TX Byte 1 ==
8143 09:58:04.957309 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8144 09:58:04.960519 DramC Write-DBI off
8145 09:58:04.960591
8146 09:58:04.960653 [DATLAT]
8147 09:58:04.963942 Freq=1600, CH0 RK1
8148 09:58:04.964011
8149 09:58:04.964075 DATLAT Default: 0xf
8150 09:58:04.967058 0, 0xFFFF, sum = 0
8151 09:58:04.967151 1, 0xFFFF, sum = 0
8152 09:58:04.970432 2, 0xFFFF, sum = 0
8153 09:58:04.970503 3, 0xFFFF, sum = 0
8154 09:58:04.973579 4, 0xFFFF, sum = 0
8155 09:58:04.976978 5, 0xFFFF, sum = 0
8156 09:58:04.977052 6, 0xFFFF, sum = 0
8157 09:58:04.980282 7, 0xFFFF, sum = 0
8158 09:58:04.980353 8, 0xFFFF, sum = 0
8159 09:58:04.983241 9, 0xFFFF, sum = 0
8160 09:58:04.983312 10, 0xFFFF, sum = 0
8161 09:58:04.986815 11, 0xFFFF, sum = 0
8162 09:58:04.986889 12, 0xFFFF, sum = 0
8163 09:58:04.989993 13, 0xFFFF, sum = 0
8164 09:58:04.990065 14, 0x0, sum = 1
8165 09:58:04.993580 15, 0x0, sum = 2
8166 09:58:04.993657 16, 0x0, sum = 3
8167 09:58:04.996651 17, 0x0, sum = 4
8168 09:58:04.996739 best_step = 15
8169 09:58:04.996804
8170 09:58:04.996867 ==
8171 09:58:05.000101 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 09:58:05.003446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 09:58:05.006879 ==
8174 09:58:05.006958 RX Vref Scan: 0
8175 09:58:05.007025
8176 09:58:05.010367 RX Vref 0 -> 0, step: 1
8177 09:58:05.010440
8178 09:58:05.013294 RX Delay 11 -> 252, step: 4
8179 09:58:05.016539 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8180 09:58:05.019705 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8181 09:58:05.023251 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8182 09:58:05.029746 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8183 09:58:05.032903 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8184 09:58:05.036312 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8185 09:58:05.039705 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8186 09:58:05.042756 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8187 09:58:05.049217 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8188 09:58:05.052633 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8189 09:58:05.056106 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8190 09:58:05.059506 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8191 09:58:05.065725 iDelay=191, Bit 12, Center 126 (71 ~ 182) 112
8192 09:58:05.069036 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8193 09:58:05.072256 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8194 09:58:05.075959 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8195 09:58:05.076081 ==
8196 09:58:05.079235 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 09:58:05.085530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 09:58:05.085608 ==
8199 09:58:05.085679 DQS Delay:
8200 09:58:05.085743 DQS0 = 0, DQS1 = 0
8201 09:58:05.088915 DQM Delay:
8202 09:58:05.088987 DQM0 = 128, DQM1 = 123
8203 09:58:05.092544 DQ Delay:
8204 09:58:05.095642 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8205 09:58:05.098879 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8206 09:58:05.101921 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =118
8207 09:58:05.105155 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8208 09:58:05.105230
8209 09:58:05.105295
8210 09:58:05.105362
8211 09:58:05.108534 [DramC_TX_OE_Calibration] TA2
8212 09:58:05.111882 Original DQ_B0 (3 6) =30, OEN = 27
8213 09:58:05.115441 Original DQ_B1 (3 6) =30, OEN = 27
8214 09:58:05.118782 24, 0x0, End_B0=24 End_B1=24
8215 09:58:05.121868 25, 0x0, End_B0=25 End_B1=25
8216 09:58:05.121941 26, 0x0, End_B0=26 End_B1=26
8217 09:58:05.125135 27, 0x0, End_B0=27 End_B1=27
8218 09:58:05.128962 28, 0x0, End_B0=28 End_B1=28
8219 09:58:05.131867 29, 0x0, End_B0=29 End_B1=29
8220 09:58:05.131940 30, 0x0, End_B0=30 End_B1=30
8221 09:58:05.134896 31, 0x4141, End_B0=30 End_B1=30
8222 09:58:05.138157 Byte0 end_step=30 best_step=27
8223 09:58:05.141473 Byte1 end_step=30 best_step=27
8224 09:58:05.144857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8225 09:58:05.148124 Byte1 TX OE(2T, 0.5T) = (3, 3)
8226 09:58:05.148221
8227 09:58:05.148304
8228 09:58:05.154438 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8229 09:58:05.157861 CH0 RK1: MR19=303, MR18=1412
8230 09:58:05.164481 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8231 09:58:05.167807 [RxdqsGatingPostProcess] freq 1600
8232 09:58:05.174065 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8233 09:58:05.174142 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 09:58:05.177986 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 09:58:05.180728 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 09:58:05.184024 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 09:58:05.187205 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 09:58:05.191106 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 09:58:05.193887 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 09:58:05.197270 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 09:58:05.200721 Pre-setting of DQS Precalculation
8242 09:58:05.203638 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8243 09:58:05.207419 ==
8244 09:58:05.210396 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 09:58:05.213825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 09:58:05.213901 ==
8247 09:58:05.216974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8248 09:58:05.223966 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8249 09:58:05.226741 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8250 09:58:05.233546 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8251 09:58:05.241824 [CA 0] Center 42 (12~72) winsize 61
8252 09:58:05.245251 [CA 1] Center 42 (12~72) winsize 61
8253 09:58:05.248260 [CA 2] Center 38 (9~67) winsize 59
8254 09:58:05.251494 [CA 3] Center 36 (7~66) winsize 60
8255 09:58:05.255548 [CA 4] Center 37 (8~67) winsize 60
8256 09:58:05.258101 [CA 5] Center 36 (7~66) winsize 60
8257 09:58:05.258179
8258 09:58:05.261507 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8259 09:58:05.261592
8260 09:58:05.268075 [CATrainingPosCal] consider 1 rank data
8261 09:58:05.268166 u2DelayCellTimex100 = 275/100 ps
8262 09:58:05.274476 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8263 09:58:05.277874 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8264 09:58:05.281177 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8265 09:58:05.284616 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8266 09:58:05.288314 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8267 09:58:05.291666 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8268 09:58:05.291748
8269 09:58:05.294362 CA PerBit enable=1, Macro0, CA PI delay=36
8270 09:58:05.294435
8271 09:58:05.297755 [CBTSetCACLKResult] CA Dly = 36
8272 09:58:05.300784 CS Dly: 8 (0~39)
8273 09:58:05.304593 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8274 09:58:05.307693 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8275 09:58:05.307769 ==
8276 09:58:05.310915 Dram Type= 6, Freq= 0, CH_1, rank 1
8277 09:58:05.317633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 09:58:05.317718 ==
8279 09:58:05.320786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 09:58:05.327277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 09:58:05.330443 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 09:58:05.337037 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 09:58:05.345207 [CA 0] Center 42 (12~72) winsize 61
8284 09:58:05.348063 [CA 1] Center 42 (13~72) winsize 60
8285 09:58:05.351313 [CA 2] Center 38 (9~68) winsize 60
8286 09:58:05.354713 [CA 3] Center 37 (7~67) winsize 61
8287 09:58:05.358145 [CA 4] Center 37 (8~67) winsize 60
8288 09:58:05.361115 [CA 5] Center 37 (7~67) winsize 61
8289 09:58:05.361187
8290 09:58:05.364781 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 09:58:05.364868
8292 09:58:05.368142 [CATrainingPosCal] consider 2 rank data
8293 09:58:05.371173 u2DelayCellTimex100 = 275/100 ps
8294 09:58:05.378473 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8295 09:58:05.381204 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8296 09:58:05.384575 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8297 09:58:05.387767 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 09:58:05.390969 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8299 09:58:05.394797 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 09:58:05.394902
8301 09:58:05.397938 CA PerBit enable=1, Macro0, CA PI delay=36
8302 09:58:05.398048
8303 09:58:05.400799 [CBTSetCACLKResult] CA Dly = 36
8304 09:58:05.404789 CS Dly: 9 (0~42)
8305 09:58:05.407772 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 09:58:05.411279 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 09:58:05.411368
8308 09:58:05.414761 ----->DramcWriteLeveling(PI) begin...
8309 09:58:05.414842 ==
8310 09:58:05.417606 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 09:58:05.424320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 09:58:05.424404 ==
8313 09:58:05.427414 Write leveling (Byte 0): 24 => 24
8314 09:58:05.427508 Write leveling (Byte 1): 28 => 28
8315 09:58:05.431082 DramcWriteLeveling(PI) end<-----
8316 09:58:05.431162
8317 09:58:05.434526 ==
8318 09:58:05.437662 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 09:58:05.440733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 09:58:05.440816 ==
8321 09:58:05.444086 [Gating] SW mode calibration
8322 09:58:05.450711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8323 09:58:05.453848 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8324 09:58:05.460471 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 09:58:05.463680 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 09:58:05.466878 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 09:58:05.473296 1 4 12 | B1->B0 | 2727 3434 | 1 0 | (1 1) (0 0)
8328 09:58:05.476865 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 09:58:05.480378 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 09:58:05.487304 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 09:58:05.490061 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 09:58:05.493395 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 09:58:05.499775 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 09:58:05.503122 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8335 09:58:05.506280 1 5 12 | B1->B0 | 3333 2525 | 0 0 | (0 0) (1 0)
8336 09:58:05.513389 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8337 09:58:05.516576 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 09:58:05.519554 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 09:58:05.526055 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 09:58:05.529437 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 09:58:05.532771 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 09:58:05.539493 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8343 09:58:05.542958 1 6 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8344 09:58:05.545803 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 09:58:05.552397 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 09:58:05.555745 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 09:58:05.559212 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 09:58:05.565944 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 09:58:05.569447 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 09:58:05.572244 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8351 09:58:05.579304 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8352 09:58:05.582429 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8353 09:58:05.585764 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 09:58:05.592043 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 09:58:05.595521 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 09:58:05.598813 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 09:58:05.605479 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 09:58:05.608912 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 09:58:05.611726 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 09:58:05.618284 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 09:58:05.622060 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 09:58:05.625080 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 09:58:05.631555 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 09:58:05.635189 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 09:58:05.638229 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 09:58:05.645042 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8367 09:58:05.648188 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 09:58:05.651595 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8369 09:58:05.654614 Total UI for P1: 0, mck2ui 16
8370 09:58:05.657980 best dqsien dly found for B0: ( 1, 9, 10)
8371 09:58:05.664386 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 09:58:05.667637 Total UI for P1: 0, mck2ui 16
8373 09:58:05.671280 best dqsien dly found for B1: ( 1, 9, 14)
8374 09:58:05.674512 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8375 09:58:05.677738 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8376 09:58:05.677815
8377 09:58:05.681120 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 09:58:05.684122 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8379 09:58:05.687888 [Gating] SW calibration Done
8380 09:58:05.687968 ==
8381 09:58:05.690919 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 09:58:05.694271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 09:58:05.694360 ==
8384 09:58:05.697446 RX Vref Scan: 0
8385 09:58:05.697516
8386 09:58:05.700877 RX Vref 0 -> 0, step: 1
8387 09:58:05.700952
8388 09:58:05.701017 RX Delay 0 -> 252, step: 8
8389 09:58:05.707213 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8390 09:58:05.711051 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 09:58:05.714039 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8392 09:58:05.717417 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 09:58:05.720849 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 09:58:05.727504 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8395 09:58:05.730462 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8396 09:58:05.734027 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8397 09:58:05.737367 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8398 09:58:05.740326 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8399 09:58:05.747792 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 09:58:05.750702 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8401 09:58:05.753876 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 09:58:05.756728 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8403 09:58:05.763577 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 09:58:05.766887 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8405 09:58:05.766965 ==
8406 09:58:05.770238 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 09:58:05.773586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 09:58:05.773661 ==
8409 09:58:05.777027 DQS Delay:
8410 09:58:05.777108 DQS0 = 0, DQS1 = 0
8411 09:58:05.777170 DQM Delay:
8412 09:58:05.780489 DQM0 = 135, DQM1 = 131
8413 09:58:05.780563 DQ Delay:
8414 09:58:05.783625 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8415 09:58:05.787416 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8416 09:58:05.790222 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8417 09:58:05.796502 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8418 09:58:05.796649
8419 09:58:05.796756
8420 09:58:05.796842 ==
8421 09:58:05.799884 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 09:58:05.803199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 09:58:05.803275 ==
8424 09:58:05.803338
8425 09:58:05.803401
8426 09:58:05.806132 TX Vref Scan disable
8427 09:58:05.806218 == TX Byte 0 ==
8428 09:58:05.812919 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 09:58:05.816487 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 09:58:05.820129 == TX Byte 1 ==
8431 09:58:05.823345 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8432 09:58:05.826697 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8433 09:58:05.826767 ==
8434 09:58:05.829337 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 09:58:05.832580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 09:58:05.836205 ==
8437 09:58:05.847168
8438 09:58:05.850474 TX Vref early break, caculate TX vref
8439 09:58:05.853917 TX Vref=16, minBit 9, minWin=21, winSum=369
8440 09:58:05.857585 TX Vref=18, minBit 8, minWin=22, winSum=377
8441 09:58:05.860282 TX Vref=20, minBit 8, minWin=23, winSum=390
8442 09:58:05.864208 TX Vref=22, minBit 8, minWin=22, winSum=395
8443 09:58:05.867055 TX Vref=24, minBit 8, minWin=24, winSum=408
8444 09:58:05.873555 TX Vref=26, minBit 9, minWin=25, winSum=420
8445 09:58:05.876726 TX Vref=28, minBit 1, minWin=25, winSum=418
8446 09:58:05.879981 TX Vref=30, minBit 1, minWin=25, winSum=412
8447 09:58:05.883566 TX Vref=32, minBit 11, minWin=23, winSum=403
8448 09:58:05.887073 TX Vref=34, minBit 1, minWin=23, winSum=397
8449 09:58:05.893316 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 26
8450 09:58:05.893422
8451 09:58:05.896622 Final TX Range 0 Vref 26
8452 09:58:05.896719
8453 09:58:05.896809 ==
8454 09:58:05.899704 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 09:58:05.903344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 09:58:05.903416 ==
8457 09:58:05.903480
8458 09:58:05.903537
8459 09:58:05.906581 TX Vref Scan disable
8460 09:58:05.913321 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8461 09:58:05.913394 == TX Byte 0 ==
8462 09:58:05.916429 u2DelayCellOfst[0]=17 cells (5 PI)
8463 09:58:05.919353 u2DelayCellOfst[1]=14 cells (4 PI)
8464 09:58:05.923238 u2DelayCellOfst[2]=0 cells (0 PI)
8465 09:58:05.926497 u2DelayCellOfst[3]=7 cells (2 PI)
8466 09:58:05.929520 u2DelayCellOfst[4]=7 cells (2 PI)
8467 09:58:05.932960 u2DelayCellOfst[5]=17 cells (5 PI)
8468 09:58:05.936303 u2DelayCellOfst[6]=17 cells (5 PI)
8469 09:58:05.939541 u2DelayCellOfst[7]=7 cells (2 PI)
8470 09:58:05.942547 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8471 09:58:05.946091 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8472 09:58:05.949269 == TX Byte 1 ==
8473 09:58:05.952514 u2DelayCellOfst[8]=0 cells (0 PI)
8474 09:58:05.956088 u2DelayCellOfst[9]=3 cells (1 PI)
8475 09:58:05.958984 u2DelayCellOfst[10]=10 cells (3 PI)
8476 09:58:05.962191 u2DelayCellOfst[11]=7 cells (2 PI)
8477 09:58:05.962309 u2DelayCellOfst[12]=14 cells (4 PI)
8478 09:58:05.965665 u2DelayCellOfst[13]=17 cells (5 PI)
8479 09:58:05.968787 u2DelayCellOfst[14]=17 cells (5 PI)
8480 09:58:05.972666 u2DelayCellOfst[15]=17 cells (5 PI)
8481 09:58:05.978588 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8482 09:58:05.982128 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8483 09:58:05.982238 DramC Write-DBI on
8484 09:58:05.985550 ==
8485 09:58:05.988423 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 09:58:05.992160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 09:58:05.992243 ==
8488 09:58:05.992309
8489 09:58:05.992369
8490 09:58:05.995384 TX Vref Scan disable
8491 09:58:05.995466 == TX Byte 0 ==
8492 09:58:06.001894 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8493 09:58:06.001976 == TX Byte 1 ==
8494 09:58:06.005130 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8495 09:58:06.008264 DramC Write-DBI off
8496 09:58:06.008346
8497 09:58:06.008411 [DATLAT]
8498 09:58:06.011610 Freq=1600, CH1 RK0
8499 09:58:06.011717
8500 09:58:06.011802 DATLAT Default: 0xf
8501 09:58:06.014800 0, 0xFFFF, sum = 0
8502 09:58:06.014884 1, 0xFFFF, sum = 0
8503 09:58:06.018020 2, 0xFFFF, sum = 0
8504 09:58:06.021262 3, 0xFFFF, sum = 0
8505 09:58:06.021352 4, 0xFFFF, sum = 0
8506 09:58:06.024571 5, 0xFFFF, sum = 0
8507 09:58:06.024642 6, 0xFFFF, sum = 0
8508 09:58:06.027688 7, 0xFFFF, sum = 0
8509 09:58:06.027763 8, 0xFFFF, sum = 0
8510 09:58:06.031175 9, 0xFFFF, sum = 0
8511 09:58:06.031252 10, 0xFFFF, sum = 0
8512 09:58:06.034900 11, 0xFFFF, sum = 0
8513 09:58:06.034978 12, 0xFFFF, sum = 0
8514 09:58:06.037934 13, 0xFFFF, sum = 0
8515 09:58:06.038005 14, 0x0, sum = 1
8516 09:58:06.041141 15, 0x0, sum = 2
8517 09:58:06.041215 16, 0x0, sum = 3
8518 09:58:06.044653 17, 0x0, sum = 4
8519 09:58:06.044721 best_step = 15
8520 09:58:06.044780
8521 09:58:06.044845 ==
8522 09:58:06.047781 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 09:58:06.054245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 09:58:06.054370 ==
8525 09:58:06.054437 RX Vref Scan: 1
8526 09:58:06.054498
8527 09:58:06.057432 Set Vref Range= 24 -> 127
8528 09:58:06.057497
8529 09:58:06.061212 RX Vref 24 -> 127, step: 1
8530 09:58:06.061285
8531 09:58:06.061346 RX Delay 19 -> 252, step: 4
8532 09:58:06.064249
8533 09:58:06.064320 Set Vref, RX VrefLevel [Byte0]: 24
8534 09:58:06.067632 [Byte1]: 24
8535 09:58:06.071826
8536 09:58:06.071895 Set Vref, RX VrefLevel [Byte0]: 25
8537 09:58:06.075029 [Byte1]: 25
8538 09:58:06.079594
8539 09:58:06.079667 Set Vref, RX VrefLevel [Byte0]: 26
8540 09:58:06.082809 [Byte1]: 26
8541 09:58:06.087298
8542 09:58:06.087443 Set Vref, RX VrefLevel [Byte0]: 27
8543 09:58:06.089990 [Byte1]: 27
8544 09:58:06.094501
8545 09:58:06.094581 Set Vref, RX VrefLevel [Byte0]: 28
8546 09:58:06.097460 [Byte1]: 28
8547 09:58:06.102017
8548 09:58:06.102098 Set Vref, RX VrefLevel [Byte0]: 29
8549 09:58:06.105126 [Byte1]: 29
8550 09:58:06.110114
8551 09:58:06.110187 Set Vref, RX VrefLevel [Byte0]: 30
8552 09:58:06.113084 [Byte1]: 30
8553 09:58:06.117652
8554 09:58:06.117731 Set Vref, RX VrefLevel [Byte0]: 31
8555 09:58:06.120302 [Byte1]: 31
8556 09:58:06.124776
8557 09:58:06.124845 Set Vref, RX VrefLevel [Byte0]: 32
8558 09:58:06.127907 [Byte1]: 32
8559 09:58:06.131999
8560 09:58:06.132077 Set Vref, RX VrefLevel [Byte0]: 33
8561 09:58:06.135279 [Byte1]: 33
8562 09:58:06.139568
8563 09:58:06.139646 Set Vref, RX VrefLevel [Byte0]: 34
8564 09:58:06.143008 [Byte1]: 34
8565 09:58:06.147330
8566 09:58:06.147404 Set Vref, RX VrefLevel [Byte0]: 35
8567 09:58:06.150752 [Byte1]: 35
8568 09:58:06.154923
8569 09:58:06.155014 Set Vref, RX VrefLevel [Byte0]: 36
8570 09:58:06.158547 [Byte1]: 36
8571 09:58:06.162531
8572 09:58:06.162612 Set Vref, RX VrefLevel [Byte0]: 37
8573 09:58:06.165558 [Byte1]: 37
8574 09:58:06.170055
8575 09:58:06.170124 Set Vref, RX VrefLevel [Byte0]: 38
8576 09:58:06.173238 [Byte1]: 38
8577 09:58:06.177438
8578 09:58:06.177509 Set Vref, RX VrefLevel [Byte0]: 39
8579 09:58:06.181297 [Byte1]: 39
8580 09:58:06.185092
8581 09:58:06.185166 Set Vref, RX VrefLevel [Byte0]: 40
8582 09:58:06.188580 [Byte1]: 40
8583 09:58:06.192970
8584 09:58:06.193043 Set Vref, RX VrefLevel [Byte0]: 41
8585 09:58:06.196209 [Byte1]: 41
8586 09:58:06.200277
8587 09:58:06.200354 Set Vref, RX VrefLevel [Byte0]: 42
8588 09:58:06.203495 [Byte1]: 42
8589 09:58:06.207696
8590 09:58:06.207766 Set Vref, RX VrefLevel [Byte0]: 43
8591 09:58:06.211336 [Byte1]: 43
8592 09:58:06.215544
8593 09:58:06.215624 Set Vref, RX VrefLevel [Byte0]: 44
8594 09:58:06.218989 [Byte1]: 44
8595 09:58:06.223372
8596 09:58:06.223441 Set Vref, RX VrefLevel [Byte0]: 45
8597 09:58:06.227012 [Byte1]: 45
8598 09:58:06.230754
8599 09:58:06.230826 Set Vref, RX VrefLevel [Byte0]: 46
8600 09:58:06.234154 [Byte1]: 46
8601 09:58:06.238062
8602 09:58:06.238138 Set Vref, RX VrefLevel [Byte0]: 47
8603 09:58:06.241441 [Byte1]: 47
8604 09:58:06.245877
8605 09:58:06.245947 Set Vref, RX VrefLevel [Byte0]: 48
8606 09:58:06.249618 [Byte1]: 48
8607 09:58:06.253370
8608 09:58:06.253454 Set Vref, RX VrefLevel [Byte0]: 49
8609 09:58:06.256713 [Byte1]: 49
8610 09:58:06.261079
8611 09:58:06.261150 Set Vref, RX VrefLevel [Byte0]: 50
8612 09:58:06.264381 [Byte1]: 50
8613 09:58:06.268451
8614 09:58:06.268523 Set Vref, RX VrefLevel [Byte0]: 51
8615 09:58:06.272029 [Byte1]: 51
8616 09:58:06.276125
8617 09:58:06.276202 Set Vref, RX VrefLevel [Byte0]: 52
8618 09:58:06.279502 [Byte1]: 52
8619 09:58:06.283769
8620 09:58:06.283838 Set Vref, RX VrefLevel [Byte0]: 53
8621 09:58:06.286885 [Byte1]: 53
8622 09:58:06.291016
8623 09:58:06.291132 Set Vref, RX VrefLevel [Byte0]: 54
8624 09:58:06.294906 [Byte1]: 54
8625 09:58:06.299686
8626 09:58:06.299763 Set Vref, RX VrefLevel [Byte0]: 55
8627 09:58:06.302143 [Byte1]: 55
8628 09:58:06.306213
8629 09:58:06.306312 Set Vref, RX VrefLevel [Byte0]: 56
8630 09:58:06.309612 [Byte1]: 56
8631 09:58:06.313885
8632 09:58:06.313967 Set Vref, RX VrefLevel [Byte0]: 57
8633 09:58:06.317314 [Byte1]: 57
8634 09:58:06.321721
8635 09:58:06.321806 Set Vref, RX VrefLevel [Byte0]: 58
8636 09:58:06.324640 [Byte1]: 58
8637 09:58:06.329763
8638 09:58:06.329846 Set Vref, RX VrefLevel [Byte0]: 59
8639 09:58:06.332252 [Byte1]: 59
8640 09:58:06.336716
8641 09:58:06.336798 Set Vref, RX VrefLevel [Byte0]: 60
8642 09:58:06.340064 [Byte1]: 60
8643 09:58:06.344321
8644 09:58:06.344404 Set Vref, RX VrefLevel [Byte0]: 61
8645 09:58:06.347569 [Byte1]: 61
8646 09:58:06.351903
8647 09:58:06.351986 Set Vref, RX VrefLevel [Byte0]: 62
8648 09:58:06.355363 [Byte1]: 62
8649 09:58:06.359338
8650 09:58:06.359421 Set Vref, RX VrefLevel [Byte0]: 63
8651 09:58:06.362915 [Byte1]: 63
8652 09:58:06.367171
8653 09:58:06.367253 Set Vref, RX VrefLevel [Byte0]: 64
8654 09:58:06.370449 [Byte1]: 64
8655 09:58:06.374740
8656 09:58:06.374823 Set Vref, RX VrefLevel [Byte0]: 65
8657 09:58:06.378652 [Byte1]: 65
8658 09:58:06.382015
8659 09:58:06.382098 Set Vref, RX VrefLevel [Byte0]: 66
8660 09:58:06.385492 [Byte1]: 66
8661 09:58:06.389922
8662 09:58:06.390004 Set Vref, RX VrefLevel [Byte0]: 67
8663 09:58:06.393043 [Byte1]: 67
8664 09:58:06.397445
8665 09:58:06.397528 Set Vref, RX VrefLevel [Byte0]: 68
8666 09:58:06.400859 [Byte1]: 68
8667 09:58:06.404864
8668 09:58:06.404947 Set Vref, RX VrefLevel [Byte0]: 69
8669 09:58:06.408087 [Byte1]: 69
8670 09:58:06.412435
8671 09:58:06.412518 Set Vref, RX VrefLevel [Byte0]: 70
8672 09:58:06.416308 [Byte1]: 70
8673 09:58:06.420725
8674 09:58:06.420807 Final RX Vref Byte 0 = 57 to rank0
8675 09:58:06.423247 Final RX Vref Byte 1 = 61 to rank0
8676 09:58:06.426850 Final RX Vref Byte 0 = 57 to rank1
8677 09:58:06.430005 Final RX Vref Byte 1 = 61 to rank1==
8678 09:58:06.433157 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 09:58:06.439775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 09:58:06.439860 ==
8681 09:58:06.439927 DQS Delay:
8682 09:58:06.442940 DQS0 = 0, DQS1 = 0
8683 09:58:06.443023 DQM Delay:
8684 09:58:06.443089 DQM0 = 133, DQM1 = 130
8685 09:58:06.446115 DQ Delay:
8686 09:58:06.449757 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8687 09:58:06.452858 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8688 09:58:06.456120 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8689 09:58:06.459161 DQ12 =142, DQ13 =140, DQ14 =136, DQ15 =140
8690 09:58:06.459250
8691 09:58:06.459323
8692 09:58:06.459394
8693 09:58:06.462698 [DramC_TX_OE_Calibration] TA2
8694 09:58:06.466173 Original DQ_B0 (3 6) =30, OEN = 27
8695 09:58:06.469227 Original DQ_B1 (3 6) =30, OEN = 27
8696 09:58:06.472504 24, 0x0, End_B0=24 End_B1=24
8697 09:58:06.475715 25, 0x0, End_B0=25 End_B1=25
8698 09:58:06.475794 26, 0x0, End_B0=26 End_B1=26
8699 09:58:06.479404 27, 0x0, End_B0=27 End_B1=27
8700 09:58:06.482650 28, 0x0, End_B0=28 End_B1=28
8701 09:58:06.485984 29, 0x0, End_B0=29 End_B1=29
8702 09:58:06.486059 30, 0x0, End_B0=30 End_B1=30
8703 09:58:06.489186 31, 0x4141, End_B0=30 End_B1=30
8704 09:58:06.492385 Byte0 end_step=30 best_step=27
8705 09:58:06.495694 Byte1 end_step=30 best_step=27
8706 09:58:06.499082 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 09:58:06.502566 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 09:58:06.502641
8709 09:58:06.502712
8710 09:58:06.508802 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8711 09:58:06.512309 CH1 RK0: MR19=303, MR18=D17
8712 09:58:06.518912 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8713 09:58:06.518988
8714 09:58:06.522405 ----->DramcWriteLeveling(PI) begin...
8715 09:58:06.522483 ==
8716 09:58:06.525406 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 09:58:06.528982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 09:58:06.529059 ==
8719 09:58:06.532081 Write leveling (Byte 0): 23 => 23
8720 09:58:06.535209 Write leveling (Byte 1): 27 => 27
8721 09:58:06.538911 DramcWriteLeveling(PI) end<-----
8722 09:58:06.538993
8723 09:58:06.539054 ==
8724 09:58:06.541893 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 09:58:06.545056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 09:58:06.548695 ==
8727 09:58:06.548795 [Gating] SW mode calibration
8728 09:58:06.558568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 09:58:06.561783 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 09:58:06.565532 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 09:58:06.571235 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8732 09:58:06.575294 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8733 09:58:06.578171 1 4 12 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8734 09:58:06.584889 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 09:58:06.587801 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 09:58:06.591008 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 09:58:06.597756 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 09:58:06.600964 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 09:58:06.604339 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8740 09:58:06.610729 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8741 09:58:06.614135 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8742 09:58:06.617621 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
8743 09:58:06.624378 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 09:58:06.627192 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 09:58:06.630710 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 09:58:06.637393 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 09:58:06.640952 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8748 09:58:06.643719 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8749 09:58:06.650636 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8750 09:58:06.653758 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 09:58:06.657082 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 09:58:06.663683 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 09:58:06.666777 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 09:58:06.670031 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 09:58:06.676724 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 09:58:06.680041 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8757 09:58:06.683734 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8758 09:58:06.690183 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8759 09:58:06.693133 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 09:58:06.696707 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 09:58:06.703156 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 09:58:06.706494 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 09:58:06.709849 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 09:58:06.716387 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 09:58:06.720155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 09:58:06.722981 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 09:58:06.729570 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 09:58:06.732970 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 09:58:06.735923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 09:58:06.742915 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 09:58:06.745673 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 09:58:06.749256 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8773 09:58:06.752356 Total UI for P1: 0, mck2ui 16
8774 09:58:06.755652 best dqsien dly found for B0: ( 1, 9, 6)
8775 09:58:06.762062 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8776 09:58:06.765457 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 09:58:06.768902 Total UI for P1: 0, mck2ui 16
8778 09:58:06.772004 best dqsien dly found for B1: ( 1, 9, 10)
8779 09:58:06.775220 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8780 09:58:06.778833 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8781 09:58:06.778902
8782 09:58:06.781819 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8783 09:58:06.788710 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8784 09:58:06.788805 [Gating] SW calibration Done
8785 09:58:06.788873 ==
8786 09:58:06.792006 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 09:58:06.799010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 09:58:06.799099 ==
8789 09:58:06.799166 RX Vref Scan: 0
8790 09:58:06.799228
8791 09:58:06.801815 RX Vref 0 -> 0, step: 1
8792 09:58:06.801888
8793 09:58:06.805256 RX Delay 0 -> 252, step: 8
8794 09:58:06.808589 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8795 09:58:06.811437 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8796 09:58:06.814835 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8797 09:58:06.821705 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8798 09:58:06.824537 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8799 09:58:06.828642 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8800 09:58:06.831673 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8801 09:58:06.834829 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8802 09:58:06.841389 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8803 09:58:06.844801 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8804 09:58:06.848076 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8805 09:58:06.851316 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8806 09:58:06.858037 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8807 09:58:06.861301 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8808 09:58:06.864710 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8809 09:58:06.867939 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8810 09:58:06.868021 ==
8811 09:58:06.871376 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 09:58:06.877590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 09:58:06.877672 ==
8814 09:58:06.877737 DQS Delay:
8815 09:58:06.877798 DQS0 = 0, DQS1 = 0
8816 09:58:06.881041 DQM Delay:
8817 09:58:06.881123 DQM0 = 137, DQM1 = 130
8818 09:58:06.884024 DQ Delay:
8819 09:58:06.887417 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8820 09:58:06.890710 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8821 09:58:06.894373 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8822 09:58:06.897160 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8823 09:58:06.897241
8824 09:58:06.897305
8825 09:58:06.897366 ==
8826 09:58:06.900512 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 09:58:06.904106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 09:58:06.907971 ==
8829 09:58:06.908052
8830 09:58:06.908116
8831 09:58:06.908176 TX Vref Scan disable
8832 09:58:06.910583 == TX Byte 0 ==
8833 09:58:06.913711 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8834 09:58:06.917257 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8835 09:58:06.920452 == TX Byte 1 ==
8836 09:58:06.923882 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8837 09:58:06.927229 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8838 09:58:06.930144 ==
8839 09:58:06.933673 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 09:58:06.937319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 09:58:06.937416 ==
8842 09:58:06.950405
8843 09:58:06.954096 TX Vref early break, caculate TX vref
8844 09:58:06.957460 TX Vref=16, minBit 9, minWin=22, winSum=375
8845 09:58:06.960326 TX Vref=18, minBit 9, minWin=21, winSum=385
8846 09:58:06.963812 TX Vref=20, minBit 9, minWin=22, winSum=395
8847 09:58:06.966645 TX Vref=22, minBit 9, minWin=23, winSum=404
8848 09:58:06.970004 TX Vref=24, minBit 9, minWin=24, winSum=414
8849 09:58:06.976640 TX Vref=26, minBit 9, minWin=24, winSum=417
8850 09:58:06.979891 TX Vref=28, minBit 0, minWin=25, winSum=420
8851 09:58:06.983428 TX Vref=30, minBit 0, minWin=25, winSum=415
8852 09:58:06.986566 TX Vref=32, minBit 5, minWin=24, winSum=405
8853 09:58:06.989593 TX Vref=34, minBit 5, minWin=24, winSum=399
8854 09:58:06.996347 TX Vref=36, minBit 5, minWin=22, winSum=388
8855 09:58:07.000269 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8856 09:58:07.000397
8857 09:58:07.003157 Final TX Range 0 Vref 28
8858 09:58:07.003238
8859 09:58:07.003320 ==
8860 09:58:07.006402 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 09:58:07.009953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 09:58:07.012699 ==
8863 09:58:07.012797
8864 09:58:07.012862
8865 09:58:07.012922 TX Vref Scan disable
8866 09:58:07.019618 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8867 09:58:07.019734 == TX Byte 0 ==
8868 09:58:07.022941 u2DelayCellOfst[0]=14 cells (4 PI)
8869 09:58:07.026584 u2DelayCellOfst[1]=10 cells (3 PI)
8870 09:58:07.029637 u2DelayCellOfst[2]=0 cells (0 PI)
8871 09:58:07.032617 u2DelayCellOfst[3]=7 cells (2 PI)
8872 09:58:07.035937 u2DelayCellOfst[4]=7 cells (2 PI)
8873 09:58:07.039666 u2DelayCellOfst[5]=17 cells (5 PI)
8874 09:58:07.042750 u2DelayCellOfst[6]=17 cells (5 PI)
8875 09:58:07.045915 u2DelayCellOfst[7]=7 cells (2 PI)
8876 09:58:07.049140 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8877 09:58:07.052599 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8878 09:58:07.055822 == TX Byte 1 ==
8879 09:58:07.059402 u2DelayCellOfst[8]=0 cells (0 PI)
8880 09:58:07.062186 u2DelayCellOfst[9]=3 cells (1 PI)
8881 09:58:07.066010 u2DelayCellOfst[10]=10 cells (3 PI)
8882 09:58:07.069378 u2DelayCellOfst[11]=7 cells (2 PI)
8883 09:58:07.072310 u2DelayCellOfst[12]=14 cells (4 PI)
8884 09:58:07.075946 u2DelayCellOfst[13]=17 cells (5 PI)
8885 09:58:07.076030 u2DelayCellOfst[14]=17 cells (5 PI)
8886 09:58:07.079307 u2DelayCellOfst[15]=17 cells (5 PI)
8887 09:58:07.085495 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8888 09:58:07.088767 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8889 09:58:07.092199 DramC Write-DBI on
8890 09:58:07.092282 ==
8891 09:58:07.095340 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 09:58:07.098833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 09:58:07.098942 ==
8894 09:58:07.099027
8895 09:58:07.099091
8896 09:58:07.101815 TX Vref Scan disable
8897 09:58:07.101898 == TX Byte 0 ==
8898 09:58:07.108362 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8899 09:58:07.108446 == TX Byte 1 ==
8900 09:58:07.111822 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8901 09:58:07.115199 DramC Write-DBI off
8902 09:58:07.115282
8903 09:58:07.115348 [DATLAT]
8904 09:58:07.118357 Freq=1600, CH1 RK1
8905 09:58:07.118467
8906 09:58:07.118568 DATLAT Default: 0xf
8907 09:58:07.121915 0, 0xFFFF, sum = 0
8908 09:58:07.124902 1, 0xFFFF, sum = 0
8909 09:58:07.124991 2, 0xFFFF, sum = 0
8910 09:58:07.128253 3, 0xFFFF, sum = 0
8911 09:58:07.128338 4, 0xFFFF, sum = 0
8912 09:58:07.131677 5, 0xFFFF, sum = 0
8913 09:58:07.131762 6, 0xFFFF, sum = 0
8914 09:58:07.134862 7, 0xFFFF, sum = 0
8915 09:58:07.134946 8, 0xFFFF, sum = 0
8916 09:58:07.138089 9, 0xFFFF, sum = 0
8917 09:58:07.138200 10, 0xFFFF, sum = 0
8918 09:58:07.141704 11, 0xFFFF, sum = 0
8919 09:58:07.141788 12, 0xFFFF, sum = 0
8920 09:58:07.144896 13, 0xFFFF, sum = 0
8921 09:58:07.145010 14, 0x0, sum = 1
8922 09:58:07.148164 15, 0x0, sum = 2
8923 09:58:07.148249 16, 0x0, sum = 3
8924 09:58:07.151611 17, 0x0, sum = 4
8925 09:58:07.151695 best_step = 15
8926 09:58:07.151762
8927 09:58:07.151844 ==
8928 09:58:07.155006 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 09:58:07.161272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 09:58:07.161356 ==
8931 09:58:07.161423 RX Vref Scan: 0
8932 09:58:07.161484
8933 09:58:07.164473 RX Vref 0 -> 0, step: 1
8934 09:58:07.164557
8935 09:58:07.168091 RX Delay 11 -> 252, step: 4
8936 09:58:07.171126 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8937 09:58:07.174595 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8938 09:58:07.177464 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8939 09:58:07.184619 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8940 09:58:07.187653 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8941 09:58:07.190953 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8942 09:58:07.194348 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8943 09:58:07.197820 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8944 09:58:07.204309 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8945 09:58:07.207589 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8946 09:58:07.210724 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8947 09:58:07.214185 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8948 09:58:07.220746 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8949 09:58:07.224019 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8950 09:58:07.227895 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8951 09:58:07.230579 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8952 09:58:07.230655 ==
8953 09:58:07.233968 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 09:58:07.240451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 09:58:07.240536 ==
8956 09:58:07.240610 DQS Delay:
8957 09:58:07.243670 DQS0 = 0, DQS1 = 0
8958 09:58:07.243764 DQM Delay:
8959 09:58:07.246777 DQM0 = 133, DQM1 = 128
8960 09:58:07.246861 DQ Delay:
8961 09:58:07.250362 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8962 09:58:07.253493 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
8963 09:58:07.256833 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8964 09:58:07.260167 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8965 09:58:07.260251
8966 09:58:07.260316
8967 09:58:07.260378
8968 09:58:07.263592 [DramC_TX_OE_Calibration] TA2
8969 09:58:07.266359 Original DQ_B0 (3 6) =30, OEN = 27
8970 09:58:07.269547 Original DQ_B1 (3 6) =30, OEN = 27
8971 09:58:07.273027 24, 0x0, End_B0=24 End_B1=24
8972 09:58:07.276466 25, 0x0, End_B0=25 End_B1=25
8973 09:58:07.276551 26, 0x0, End_B0=26 End_B1=26
8974 09:58:07.279586 27, 0x0, End_B0=27 End_B1=27
8975 09:58:07.282807 28, 0x0, End_B0=28 End_B1=28
8976 09:58:07.286454 29, 0x0, End_B0=29 End_B1=29
8977 09:58:07.289426 30, 0x0, End_B0=30 End_B1=30
8978 09:58:07.289512 31, 0x4141, End_B0=30 End_B1=30
8979 09:58:07.292753 Byte0 end_step=30 best_step=27
8980 09:58:07.295893 Byte1 end_step=30 best_step=27
8981 09:58:07.299269 Byte0 TX OE(2T, 0.5T) = (3, 3)
8982 09:58:07.302593 Byte1 TX OE(2T, 0.5T) = (3, 3)
8983 09:58:07.302680
8984 09:58:07.302746
8985 09:58:07.309392 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8986 09:58:07.312772 CH1 RK1: MR19=303, MR18=C1A
8987 09:58:07.319095 CH1_RK1: MR19=0x303, MR18=0xC1A, DQSOSC=396, MR23=63, INC=23, DEC=15
8988 09:58:07.322507 [RxdqsGatingPostProcess] freq 1600
8989 09:58:07.329058 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8990 09:58:07.329164 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 09:58:07.332247 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 09:58:07.335303 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 09:58:07.339251 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 09:58:07.341764 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 09:58:07.345494 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 09:58:07.348550 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 09:58:07.351907 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 09:58:07.355827 Pre-setting of DQS Precalculation
8999 09:58:07.358715 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9000 09:58:07.368461 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9001 09:58:07.375131 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9002 09:58:07.375210
9003 09:58:07.375282
9004 09:58:07.378349 [Calibration Summary] 3200 Mbps
9005 09:58:07.378419 CH 0, Rank 0
9006 09:58:07.381263 SW Impedance : PASS
9007 09:58:07.385033 DUTY Scan : NO K
9008 09:58:07.385140 ZQ Calibration : PASS
9009 09:58:07.388150 Jitter Meter : NO K
9010 09:58:07.391441 CBT Training : PASS
9011 09:58:07.391516 Write leveling : PASS
9012 09:58:07.394424 RX DQS gating : PASS
9013 09:58:07.394507 RX DQ/DQS(RDDQC) : PASS
9014 09:58:07.397749 TX DQ/DQS : PASS
9015 09:58:07.401340 RX DATLAT : PASS
9016 09:58:07.401420 RX DQ/DQS(Engine): PASS
9017 09:58:07.404774 TX OE : PASS
9018 09:58:07.404844 All Pass.
9019 09:58:07.404904
9020 09:58:07.408098 CH 0, Rank 1
9021 09:58:07.408167 SW Impedance : PASS
9022 09:58:07.411356 DUTY Scan : NO K
9023 09:58:07.414364 ZQ Calibration : PASS
9024 09:58:07.414473 Jitter Meter : NO K
9025 09:58:07.417414 CBT Training : PASS
9026 09:58:07.421315 Write leveling : PASS
9027 09:58:07.421390 RX DQS gating : PASS
9028 09:58:07.424146 RX DQ/DQS(RDDQC) : PASS
9029 09:58:07.427459 TX DQ/DQS : PASS
9030 09:58:07.427539 RX DATLAT : PASS
9031 09:58:07.431199 RX DQ/DQS(Engine): PASS
9032 09:58:07.433916 TX OE : PASS
9033 09:58:07.433987 All Pass.
9034 09:58:07.434047
9035 09:58:07.434105 CH 1, Rank 0
9036 09:58:07.437457 SW Impedance : PASS
9037 09:58:07.440413 DUTY Scan : NO K
9038 09:58:07.440486 ZQ Calibration : PASS
9039 09:58:07.444052 Jitter Meter : NO K
9040 09:58:07.447357 CBT Training : PASS
9041 09:58:07.447430 Write leveling : PASS
9042 09:58:07.450770 RX DQS gating : PASS
9043 09:58:07.453745 RX DQ/DQS(RDDQC) : PASS
9044 09:58:07.453825 TX DQ/DQS : PASS
9045 09:58:07.457456 RX DATLAT : PASS
9046 09:58:07.460478 RX DQ/DQS(Engine): PASS
9047 09:58:07.460588 TX OE : PASS
9048 09:58:07.463385 All Pass.
9049 09:58:07.463468
9050 09:58:07.463534 CH 1, Rank 1
9051 09:58:07.467282 SW Impedance : PASS
9052 09:58:07.467365 DUTY Scan : NO K
9053 09:58:07.470055 ZQ Calibration : PASS
9054 09:58:07.473527 Jitter Meter : NO K
9055 09:58:07.473605 CBT Training : PASS
9056 09:58:07.477246 Write leveling : PASS
9057 09:58:07.477353 RX DQS gating : PASS
9058 09:58:07.480224 RX DQ/DQS(RDDQC) : PASS
9059 09:58:07.483423 TX DQ/DQS : PASS
9060 09:58:07.483505 RX DATLAT : PASS
9061 09:58:07.486701 RX DQ/DQS(Engine): PASS
9062 09:58:07.490062 TX OE : PASS
9063 09:58:07.490134 All Pass.
9064 09:58:07.490202
9065 09:58:07.493094 DramC Write-DBI on
9066 09:58:07.493164 PER_BANK_REFRESH: Hybrid Mode
9067 09:58:07.496873 TX_TRACKING: ON
9068 09:58:07.506377 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9069 09:58:07.513104 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9070 09:58:07.519464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 09:58:07.522912 [FAST_K] Save calibration result to emmc
9072 09:58:07.525998 sync common calibartion params.
9073 09:58:07.529416 sync cbt_mode0:1, 1:1
9074 09:58:07.532805 dram_init: ddr_geometry: 2
9075 09:58:07.532915 dram_init: ddr_geometry: 2
9076 09:58:07.536394 dram_init: ddr_geometry: 2
9077 09:58:07.539573 0:dram_rank_size:100000000
9078 09:58:07.539676 1:dram_rank_size:100000000
9079 09:58:07.546084 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9080 09:58:07.549595 DFS_SHUFFLE_HW_MODE: ON
9081 09:58:07.552413 dramc_set_vcore_voltage set vcore to 725000
9082 09:58:07.555821 Read voltage for 1600, 0
9083 09:58:07.555929 Vio18 = 0
9084 09:58:07.556020 Vcore = 725000
9085 09:58:07.559274 Vdram = 0
9086 09:58:07.559349 Vddq = 0
9087 09:58:07.559410 Vmddr = 0
9088 09:58:07.562546 switch to 3200 Mbps bootup
9089 09:58:07.565953 [DramcRunTimeConfig]
9090 09:58:07.566061 PHYPLL
9091 09:58:07.566155 DPM_CONTROL_AFTERK: ON
9092 09:58:07.569246 PER_BANK_REFRESH: ON
9093 09:58:07.572195 REFRESH_OVERHEAD_REDUCTION: ON
9094 09:58:07.572279 CMD_PICG_NEW_MODE: OFF
9095 09:58:07.575770 XRTWTW_NEW_MODE: ON
9096 09:58:07.575858 XRTRTR_NEW_MODE: ON
9097 09:58:07.579033 TX_TRACKING: ON
9098 09:58:07.579117 RDSEL_TRACKING: OFF
9099 09:58:07.582691 DQS Precalculation for DVFS: ON
9100 09:58:07.586101 RX_TRACKING: OFF
9101 09:58:07.586210 HW_GATING DBG: ON
9102 09:58:07.589311 ZQCS_ENABLE_LP4: ON
9103 09:58:07.589394 RX_PICG_NEW_MODE: ON
9104 09:58:07.592611 TX_PICG_NEW_MODE: ON
9105 09:58:07.595860 ENABLE_RX_DCM_DPHY: ON
9106 09:58:07.599282 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9107 09:58:07.599365 DUMMY_READ_FOR_TRACKING: OFF
9108 09:58:07.601993 !!! SPM_CONTROL_AFTERK: OFF
9109 09:58:07.605529 !!! SPM could not control APHY
9110 09:58:07.608688 IMPEDANCE_TRACKING: ON
9111 09:58:07.608771 TEMP_SENSOR: ON
9112 09:58:07.612010 HW_SAVE_FOR_SR: OFF
9113 09:58:07.612094 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9114 09:58:07.618452 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9115 09:58:07.618536 Read ODT Tracking: ON
9116 09:58:07.621987 Refresh Rate DeBounce: ON
9117 09:58:07.625361 DFS_NO_QUEUE_FLUSH: ON
9118 09:58:07.628492 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9119 09:58:07.628576 ENABLE_DFS_RUNTIME_MRW: OFF
9120 09:58:07.631930 DDR_RESERVE_NEW_MODE: ON
9121 09:58:07.635252 MR_CBT_SWITCH_FREQ: ON
9122 09:58:07.635339 =========================
9123 09:58:07.654822 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9124 09:58:07.658088 dram_init: ddr_geometry: 2
9125 09:58:07.676703 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9126 09:58:07.679516 dram_init: dram init end (result: 0)
9127 09:58:07.686282 DRAM-K: Full calibration passed in 24430 msecs
9128 09:58:07.689948 MRC: failed to locate region type 0.
9129 09:58:07.690085 DRAM rank0 size:0x100000000,
9130 09:58:07.692770 DRAM rank1 size=0x100000000
9131 09:58:07.703113 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9132 09:58:07.709445 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9133 09:58:07.715786 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9134 09:58:07.725852 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9135 09:58:07.725938 DRAM rank0 size:0x100000000,
9136 09:58:07.729338 DRAM rank1 size=0x100000000
9137 09:58:07.729411 CBMEM:
9138 09:58:07.732550 IMD: root @ 0xfffff000 254 entries.
9139 09:58:07.735689 IMD: root @ 0xffffec00 62 entries.
9140 09:58:07.738788 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9141 09:58:07.745573 WARNING: RO_VPD is uninitialized or empty.
9142 09:58:07.748905 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9143 09:58:07.756558 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9144 09:58:07.769228 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9145 09:58:07.780339 BS: romstage times (exec / console): total (unknown) / 23961 ms
9146 09:58:07.780453
9147 09:58:07.780547
9148 09:58:07.790888 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9149 09:58:07.793600 ARM64: Exception handlers installed.
9150 09:58:07.796743 ARM64: Testing exception
9151 09:58:07.800042 ARM64: Done test exception
9152 09:58:07.800127 Enumerating buses...
9153 09:58:07.803801 Show all devs... Before device enumeration.
9154 09:58:07.806854 Root Device: enabled 1
9155 09:58:07.810140 CPU_CLUSTER: 0: enabled 1
9156 09:58:07.810224 CPU: 00: enabled 1
9157 09:58:07.813625 Compare with tree...
9158 09:58:07.813708 Root Device: enabled 1
9159 09:58:07.816592 CPU_CLUSTER: 0: enabled 1
9160 09:58:07.819893 CPU: 00: enabled 1
9161 09:58:07.819976 Root Device scanning...
9162 09:58:07.823414 scan_static_bus for Root Device
9163 09:58:07.826864 CPU_CLUSTER: 0 enabled
9164 09:58:07.830063 scan_static_bus for Root Device done
9165 09:58:07.833505 scan_bus: bus Root Device finished in 8 msecs
9166 09:58:07.833589 done
9167 09:58:07.839850 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9168 09:58:07.843271 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9169 09:58:07.849964 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9170 09:58:07.852856 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9171 09:58:07.856390 Allocating resources...
9172 09:58:07.859862 Reading resources...
9173 09:58:07.863168 Root Device read_resources bus 0 link: 0
9174 09:58:07.866364 DRAM rank0 size:0x100000000,
9175 09:58:07.866448 DRAM rank1 size=0x100000000
9176 09:58:07.872787 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9177 09:58:07.872870 CPU: 00 missing read_resources
9178 09:58:07.879474 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9179 09:58:07.882958 Root Device read_resources bus 0 link: 0 done
9180 09:58:07.885809 Done reading resources.
9181 09:58:07.889363 Show resources in subtree (Root Device)...After reading.
9182 09:58:07.892827 Root Device child on link 0 CPU_CLUSTER: 0
9183 09:58:07.896414 CPU_CLUSTER: 0 child on link 0 CPU: 00
9184 09:58:07.905754 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9185 09:58:07.905843 CPU: 00
9186 09:58:07.909046 Root Device assign_resources, bus 0 link: 0
9187 09:58:07.912500 CPU_CLUSTER: 0 missing set_resources
9188 09:58:07.918998 Root Device assign_resources, bus 0 link: 0 done
9189 09:58:07.919082 Done setting resources.
9190 09:58:07.925400 Show resources in subtree (Root Device)...After assigning values.
9191 09:58:07.929019 Root Device child on link 0 CPU_CLUSTER: 0
9192 09:58:07.932461 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 09:58:07.942136 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 09:58:07.942220 CPU: 00
9195 09:58:07.945734 Done allocating resources.
9196 09:58:07.951751 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9197 09:58:07.951835 Enabling resources...
9198 09:58:07.955355 done.
9199 09:58:07.958802 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9200 09:58:07.961980 Initializing devices...
9201 09:58:07.962063 Root Device init
9202 09:58:07.965300 init hardware done!
9203 09:58:07.965384 0x00000018: ctrlr->caps
9204 09:58:07.968669 52.000 MHz: ctrlr->f_max
9205 09:58:07.972076 0.400 MHz: ctrlr->f_min
9206 09:58:07.972161 0x40ff8080: ctrlr->voltages
9207 09:58:07.975077 sclk: 390625
9208 09:58:07.975160 Bus Width = 1
9209 09:58:07.978244 sclk: 390625
9210 09:58:07.978335 Bus Width = 1
9211 09:58:07.981559 Early init status = 3
9212 09:58:07.984769 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9213 09:58:07.988087 in-header: 03 fb 00 00 01 00 00 00
9214 09:58:07.991955 in-data: 01
9215 09:58:07.995024 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9216 09:58:07.998362 in-header: 03 fb 00 00 01 00 00 00
9217 09:58:08.001518 in-data: 01
9218 09:58:08.004629 [SSUSB] Setting up USB HOST controller...
9219 09:58:08.008299 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9220 09:58:08.011414 [SSUSB] phy power-on done.
9221 09:58:08.015141 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9222 09:58:08.021571 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9223 09:58:08.024785 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9224 09:58:08.031652 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9225 09:58:08.038023 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9226 09:58:08.044712 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9227 09:58:08.051169 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9228 09:58:08.057464 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9229 09:58:08.061141 SPM: binary array size = 0x9dc
9230 09:58:08.067651 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9231 09:58:08.070861 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9232 09:58:08.080550 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9233 09:58:08.084081 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9234 09:58:08.086952 configure_display: Starting display init
9235 09:58:08.121984 anx7625_power_on_init: Init interface.
9236 09:58:08.125380 anx7625_disable_pd_protocol: Disabled PD feature.
9237 09:58:08.128530 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9238 09:58:08.156194 anx7625_start_dp_work: Secure OCM version=00
9239 09:58:08.159669 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9240 09:58:08.174302 sp_tx_get_edid_block: EDID Block = 1
9241 09:58:08.276901 Extracted contents:
9242 09:58:08.280374 header: 00 ff ff ff ff ff ff 00
9243 09:58:08.283522 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9244 09:58:08.287074 version: 01 04
9245 09:58:08.290003 basic params: 95 1f 11 78 0a
9246 09:58:08.293281 chroma info: 76 90 94 55 54 90 27 21 50 54
9247 09:58:08.296704 established: 00 00 00
9248 09:58:08.303546 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9249 09:58:08.306564 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9250 09:58:08.313208 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9251 09:58:08.319854 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9252 09:58:08.326413 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9253 09:58:08.329730 extensions: 00
9254 09:58:08.329812 checksum: fb
9255 09:58:08.329924
9256 09:58:08.333239 Manufacturer: IVO Model 57d Serial Number 0
9257 09:58:08.336591 Made week 0 of 2020
9258 09:58:08.339759 EDID version: 1.4
9259 09:58:08.339879 Digital display
9260 09:58:08.342705 6 bits per primary color channel
9261 09:58:08.342804 DisplayPort interface
9262 09:58:08.346094 Maximum image size: 31 cm x 17 cm
9263 09:58:08.349489 Gamma: 220%
9264 09:58:08.349610 Check DPMS levels
9265 09:58:08.356301 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9266 09:58:08.359593 First detailed timing is preferred timing
9267 09:58:08.359690 Established timings supported:
9268 09:58:08.362635 Standard timings supported:
9269 09:58:08.365525 Detailed timings
9270 09:58:08.368954 Hex of detail: 383680a07038204018303c0035ae10000019
9271 09:58:08.375616 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9272 09:58:08.379402 0780 0798 07c8 0820 hborder 0
9273 09:58:08.382369 0438 043b 0447 0458 vborder 0
9274 09:58:08.385448 -hsync -vsync
9275 09:58:08.385532 Did detailed timing
9276 09:58:08.392432 Hex of detail: 000000000000000000000000000000000000
9277 09:58:08.395445 Manufacturer-specified data, tag 0
9278 09:58:08.399062 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9279 09:58:08.402256 ASCII string: InfoVision
9280 09:58:08.405702 Hex of detail: 000000fe00523134304e574635205248200a
9281 09:58:08.408491 ASCII string: R140NWF5 RH
9282 09:58:08.408592 Checksum
9283 09:58:08.412118 Checksum: 0xfb (valid)
9284 09:58:08.415386 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9285 09:58:08.418714 DSI data_rate: 832800000 bps
9286 09:58:08.425236 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9287 09:58:08.428976 anx7625_parse_edid: pixelclock(138800).
9288 09:58:08.432042 hactive(1920), hsync(48), hfp(24), hbp(88)
9289 09:58:08.434872 vactive(1080), vsync(12), vfp(3), vbp(17)
9290 09:58:08.438043 anx7625_dsi_config: config dsi.
9291 09:58:08.444726 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9292 09:58:08.459396 anx7625_dsi_config: success to config DSI
9293 09:58:08.462430 anx7625_dp_start: MIPI phy setup OK.
9294 09:58:08.465542 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9295 09:58:08.469239 mtk_ddp_mode_set invalid vrefresh 60
9296 09:58:08.472008 main_disp_path_setup
9297 09:58:08.472091 ovl_layer_smi_id_en
9298 09:58:08.475630 ovl_layer_smi_id_en
9299 09:58:08.475714 ccorr_config
9300 09:58:08.475781 aal_config
9301 09:58:08.478636 gamma_config
9302 09:58:08.478718 postmask_config
9303 09:58:08.481841 dither_config
9304 09:58:08.485331 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9305 09:58:08.491899 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9306 09:58:08.495099 Root Device init finished in 529 msecs
9307 09:58:08.498466 CPU_CLUSTER: 0 init
9308 09:58:08.505223 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9309 09:58:08.511516 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9310 09:58:08.511636 APU_MBOX 0x190000b0 = 0x10001
9311 09:58:08.514939 APU_MBOX 0x190001b0 = 0x10001
9312 09:58:08.518171 APU_MBOX 0x190005b0 = 0x10001
9313 09:58:08.521552 APU_MBOX 0x190006b0 = 0x10001
9314 09:58:08.527806 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9315 09:58:08.537904 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9316 09:58:08.550128 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9317 09:58:08.556710 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9318 09:58:08.568866 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9319 09:58:08.577747 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9320 09:58:08.580809 CPU_CLUSTER: 0 init finished in 81 msecs
9321 09:58:08.583969 Devices initialized
9322 09:58:08.587491 Show all devs... After init.
9323 09:58:08.587606 Root Device: enabled 1
9324 09:58:08.590583 CPU_CLUSTER: 0: enabled 1
9325 09:58:08.594031 CPU: 00: enabled 1
9326 09:58:08.598021 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9327 09:58:08.600512 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9328 09:58:08.604099 ELOG: NV offset 0x57f000 size 0x1000
9329 09:58:08.610917 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9330 09:58:08.617280 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9331 09:58:08.620410 ELOG: Event(17) added with size 13 at 2023-11-24 09:58:10 UTC
9332 09:58:08.627104 out: cmd=0x121: 03 db 21 01 00 00 00 00
9333 09:58:08.630750 in-header: 03 41 00 00 2c 00 00 00
9334 09:58:08.640650 in-data: 1e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9335 09:58:08.647086 ELOG: Event(A1) added with size 10 at 2023-11-24 09:58:11 UTC
9336 09:58:08.653919 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9337 09:58:08.660392 ELOG: Event(A0) added with size 9 at 2023-11-24 09:58:11 UTC
9338 09:58:08.663429 elog_add_boot_reason: Logged dev mode boot
9339 09:58:08.670154 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9340 09:58:08.670276 Finalize devices...
9341 09:58:08.673679 Devices finalized
9342 09:58:08.677257 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9343 09:58:08.679939 Writing coreboot table at 0xffe64000
9344 09:58:08.683326 0. 000000000010a000-0000000000113fff: RAMSTAGE
9345 09:58:08.690021 1. 0000000040000000-00000000400fffff: RAM
9346 09:58:08.693278 2. 0000000040100000-000000004032afff: RAMSTAGE
9347 09:58:08.696416 3. 000000004032b000-00000000545fffff: RAM
9348 09:58:08.699915 4. 0000000054600000-000000005465ffff: BL31
9349 09:58:08.703178 5. 0000000054660000-00000000ffe63fff: RAM
9350 09:58:08.709656 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9351 09:58:08.712895 7. 0000000100000000-000000023fffffff: RAM
9352 09:58:08.716432 Passing 5 GPIOs to payload:
9353 09:58:08.719581 NAME | PORT | POLARITY | VALUE
9354 09:58:08.726389 EC in RW | 0x000000aa | low | undefined
9355 09:58:08.729395 EC interrupt | 0x00000005 | low | undefined
9356 09:58:08.732604 TPM interrupt | 0x000000ab | high | undefined
9357 09:58:08.739726 SD card detect | 0x00000011 | high | undefined
9358 09:58:08.742734 speaker enable | 0x00000093 | high | undefined
9359 09:58:08.746336 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9360 09:58:08.749231 in-header: 03 f9 00 00 02 00 00 00
9361 09:58:08.752803 in-data: 02 00
9362 09:58:08.756098 ADC[4]: Raw value=902955 ID=7
9363 09:58:08.756210 ADC[3]: Raw value=213546 ID=1
9364 09:58:08.759180 RAM Code: 0x71
9365 09:58:08.762563 ADC[6]: Raw value=74630 ID=0
9366 09:58:08.762643 ADC[5]: Raw value=213546 ID=1
9367 09:58:08.766155 SKU Code: 0x1
9368 09:58:08.772636 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum db3
9369 09:58:08.772772 coreboot table: 964 bytes.
9370 09:58:08.776141 IMD ROOT 0. 0xfffff000 0x00001000
9371 09:58:08.778963 IMD SMALL 1. 0xffffe000 0x00001000
9372 09:58:08.782517 RO MCACHE 2. 0xffffc000 0x00001104
9373 09:58:08.785422 CONSOLE 3. 0xfff7c000 0x00080000
9374 09:58:08.789442 FMAP 4. 0xfff7b000 0x00000452
9375 09:58:08.792612 TIME STAMP 5. 0xfff7a000 0x00000910
9376 09:58:08.796103 VBOOT WORK 6. 0xfff66000 0x00014000
9377 09:58:08.798828 RAMOOPS 7. 0xffe66000 0x00100000
9378 09:58:08.802119 COREBOOT 8. 0xffe64000 0x00002000
9379 09:58:08.805796 IMD small region:
9380 09:58:08.808580 IMD ROOT 0. 0xffffec00 0x00000400
9381 09:58:08.811975 VPD 1. 0xffffeb80 0x0000006c
9382 09:58:08.815258 MMC STATUS 2. 0xffffeb60 0x00000004
9383 09:58:08.818911 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9384 09:58:08.821775 Probing TPM: done!
9385 09:58:08.825490 Connected to device vid:did:rid of 1ae0:0028:00
9386 09:58:08.836679 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9387 09:58:08.840013 Initialized TPM device CR50 revision 0
9388 09:58:08.843251 Checking cr50 for pending updates
9389 09:58:08.847325 Reading cr50 TPM mode
9390 09:58:08.855802 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9391 09:58:08.862348 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9392 09:58:08.902423 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9393 09:58:08.905608 Checking segment from ROM address 0x40100000
9394 09:58:08.909560 Checking segment from ROM address 0x4010001c
9395 09:58:08.916163 Loading segment from ROM address 0x40100000
9396 09:58:08.916244 code (compression=0)
9397 09:58:08.925608 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9398 09:58:08.932648 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9399 09:58:08.932759 it's not compressed!
9400 09:58:08.939031 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9401 09:58:08.945898 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9402 09:58:08.962865 Loading segment from ROM address 0x4010001c
9403 09:58:08.962978 Entry Point 0x80000000
9404 09:58:08.966161 Loaded segments
9405 09:58:08.969684 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9406 09:58:08.976234 Jumping to boot code at 0x80000000(0xffe64000)
9407 09:58:08.982794 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9408 09:58:08.990030 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9409 09:58:08.997474 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9410 09:58:09.001546 Checking segment from ROM address 0x40100000
9411 09:58:09.004053 Checking segment from ROM address 0x4010001c
9412 09:58:09.011147 Loading segment from ROM address 0x40100000
9413 09:58:09.011232 code (compression=1)
9414 09:58:09.017428 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9415 09:58:09.027806 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9416 09:58:09.027893 using LZMA
9417 09:58:09.035796 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9418 09:58:09.042492 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9419 09:58:09.045605 Loading segment from ROM address 0x4010001c
9420 09:58:09.045689 Entry Point 0x54601000
9421 09:58:09.048945 Loaded segments
9422 09:58:09.052168 NOTICE: MT8192 bl31_setup
9423 09:58:09.059918 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9424 09:58:09.062709 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9425 09:58:09.066269 WARNING: region 0:
9426 09:58:09.069599 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9427 09:58:09.069675 WARNING: region 1:
9428 09:58:09.075990 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9429 09:58:09.079134 WARNING: region 2:
9430 09:58:09.082881 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9431 09:58:09.086102 WARNING: region 3:
9432 09:58:09.089047 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9433 09:58:09.092735 WARNING: region 4:
9434 09:58:09.099453 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9435 09:58:09.099540 WARNING: region 5:
9436 09:58:09.103268 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 09:58:09.106342 WARNING: region 6:
9438 09:58:09.109348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 09:58:09.112570 WARNING: region 7:
9440 09:58:09.115983 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 09:58:09.122946 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9442 09:58:09.126166 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9443 09:58:09.129483 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9444 09:58:09.135802 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9445 09:58:09.139262 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9446 09:58:09.143012 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9447 09:58:09.149214 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9448 09:58:09.152631 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9449 09:58:09.159110 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9450 09:58:09.162853 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9451 09:58:09.165732 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9452 09:58:09.172742 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9453 09:58:09.175863 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9454 09:58:09.179066 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9455 09:58:09.186000 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9456 09:58:09.189194 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9457 09:58:09.196041 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9458 09:58:09.198887 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9459 09:58:09.202648 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9460 09:58:09.208951 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9461 09:58:09.212455 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9462 09:58:09.215960 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9463 09:58:09.222490 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9464 09:58:09.225484 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9465 09:58:09.232776 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9466 09:58:09.235697 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9467 09:58:09.242594 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9468 09:58:09.246072 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9469 09:58:09.249397 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9470 09:58:09.255423 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9471 09:58:09.258855 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9472 09:58:09.262329 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9473 09:58:09.268777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9474 09:58:09.271920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9475 09:58:09.275305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9476 09:58:09.278598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9477 09:58:09.285671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9478 09:58:09.288586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9479 09:58:09.292385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9480 09:58:09.295251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9481 09:58:09.302209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9482 09:58:09.305556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9483 09:58:09.308872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9484 09:58:09.312322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9485 09:58:09.318580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9486 09:58:09.322521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9487 09:58:09.325623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9488 09:58:09.331907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9489 09:58:09.335217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9490 09:58:09.338764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9491 09:58:09.345080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9492 09:58:09.348157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9493 09:58:09.355434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9494 09:58:09.358502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9495 09:58:09.365135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9496 09:58:09.368395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9497 09:58:09.371682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9498 09:58:09.378110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9499 09:58:09.381450 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9500 09:58:09.388628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9501 09:58:09.391447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9502 09:58:09.397996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9503 09:58:09.401552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9504 09:58:09.408190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9505 09:58:09.411641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9506 09:58:09.415015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9507 09:58:09.421505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9508 09:58:09.424941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9509 09:58:09.431289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9510 09:58:09.435727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9511 09:58:09.441890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9512 09:58:09.444727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9513 09:58:09.448078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9514 09:58:09.454924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9515 09:58:09.457943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9516 09:58:09.464687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9517 09:58:09.468107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9518 09:58:09.475191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9519 09:58:09.478442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9520 09:58:09.481746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9521 09:58:09.488525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9522 09:58:09.491668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9523 09:58:09.498171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9524 09:58:09.501626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9525 09:58:09.508318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9526 09:58:09.511697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9527 09:58:09.514833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9528 09:58:09.521691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9529 09:58:09.524918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9530 09:58:09.531482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9531 09:58:09.534546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9532 09:58:09.541871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9533 09:58:09.544905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9534 09:58:09.551097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9535 09:58:09.555274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9536 09:58:09.557921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9537 09:58:09.565057 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9538 09:58:09.567714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9539 09:58:09.571152 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9540 09:58:09.574388 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9541 09:58:09.581058 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9542 09:58:09.584401 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9543 09:58:09.591091 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9544 09:58:09.594699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9545 09:58:09.598024 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9546 09:58:09.604237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9547 09:58:09.607665 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9548 09:58:09.614113 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9549 09:58:09.617495 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9550 09:58:09.620786 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9551 09:58:09.627429 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9552 09:58:09.631059 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9553 09:58:09.637674 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9554 09:58:09.641442 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9555 09:58:09.644111 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9556 09:58:09.650720 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9557 09:58:09.654166 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9558 09:58:09.658268 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9559 09:58:09.664435 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9560 09:58:09.667659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9561 09:58:09.670768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9562 09:58:09.674012 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9563 09:58:09.680531 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9564 09:58:09.684677 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9565 09:58:09.687422 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9566 09:58:09.693951 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9567 09:58:09.697175 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9568 09:58:09.703890 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9569 09:58:09.707371 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9570 09:58:09.710641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9571 09:58:09.717411 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9572 09:58:09.720688 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9573 09:58:09.723836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9574 09:58:09.730513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9575 09:58:09.733733 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9576 09:58:09.740365 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9577 09:58:09.744144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9578 09:58:09.747022 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9579 09:58:09.753974 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9580 09:58:09.757723 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9581 09:58:09.764226 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9582 09:58:09.766838 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9583 09:58:09.770213 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9584 09:58:09.777098 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9585 09:58:09.780495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9586 09:58:09.787191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9587 09:58:09.790680 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9588 09:58:09.793536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9589 09:58:09.800305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9590 09:58:09.803785 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9591 09:58:09.810092 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9592 09:58:09.813346 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9593 09:58:09.817002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9594 09:58:09.823459 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9595 09:58:09.826760 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9596 09:58:09.829838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9597 09:58:09.837125 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9598 09:58:09.840499 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9599 09:58:09.846949 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9600 09:58:09.849994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9601 09:58:09.853239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9602 09:58:09.859659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9603 09:58:09.863025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9604 09:58:09.869784 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9605 09:58:09.872935 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9606 09:58:09.876208 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9607 09:58:09.882615 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9608 09:58:09.886152 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9609 09:58:09.892789 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9610 09:58:09.895861 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9611 09:58:09.899684 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9612 09:58:09.906147 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9613 09:58:09.909517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9614 09:58:09.915822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9615 09:58:09.919524 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9616 09:58:09.922760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9617 09:58:09.928834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9618 09:58:09.932403 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9619 09:58:09.938960 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9620 09:58:09.942269 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9621 09:58:09.945745 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9622 09:58:09.951990 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9623 09:58:09.955793 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9624 09:58:09.962022 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9625 09:58:09.965141 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9626 09:58:09.968893 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9627 09:58:09.975130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9628 09:58:09.978616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9629 09:58:09.985539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9630 09:58:09.988787 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9631 09:58:09.991847 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9632 09:58:09.998389 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9633 09:58:10.001848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9634 09:58:10.008036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9635 09:58:10.011883 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9636 09:58:10.017785 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9637 09:58:10.021142 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9638 09:58:10.024750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9639 09:58:10.031160 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9640 09:58:10.034614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9641 09:58:10.040983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9642 09:58:10.044484 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9643 09:58:10.051141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9644 09:58:10.054593 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9645 09:58:10.057723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9646 09:58:10.064689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9647 09:58:10.068062 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9648 09:58:10.074325 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9649 09:58:10.077857 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9650 09:58:10.081119 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9651 09:58:10.087698 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9652 09:58:10.091065 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9653 09:58:10.097651 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9654 09:58:10.100856 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9655 09:58:10.107359 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9656 09:58:10.110644 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9657 09:58:10.114192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9658 09:58:10.120459 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9659 09:58:10.123665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9660 09:58:10.130437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9661 09:58:10.133645 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9662 09:58:10.140590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9663 09:58:10.143964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9664 09:58:10.147020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9665 09:58:10.153444 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9666 09:58:10.156618 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9667 09:58:10.163113 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9668 09:58:10.166978 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9669 09:58:10.173066 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9670 09:58:10.176323 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9671 09:58:10.179908 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9672 09:58:10.183577 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9673 09:58:10.189764 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9674 09:58:10.192839 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9675 09:58:10.196414 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9676 09:58:10.203242 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9677 09:58:10.206204 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9678 09:58:10.209477 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9679 09:58:10.216325 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9680 09:58:10.219361 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9681 09:58:10.222729 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9682 09:58:10.229432 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9683 09:58:10.232400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9684 09:58:10.236230 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9685 09:58:10.242765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9686 09:58:10.245780 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9687 09:58:10.252153 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9688 09:58:10.255307 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9689 09:58:10.258822 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9690 09:58:10.265612 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9691 09:58:10.268993 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9692 09:58:10.275495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9693 09:58:10.278915 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9694 09:58:10.281765 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9695 09:58:10.288527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9696 09:58:10.291925 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9697 09:58:10.295195 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9698 09:58:10.301812 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9699 09:58:10.304898 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9700 09:58:10.308286 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9701 09:58:10.314905 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9702 09:58:10.318057 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9703 09:58:10.324946 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9704 09:58:10.328546 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9705 09:58:10.331701 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9706 09:58:10.338194 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9707 09:58:10.341242 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9708 09:58:10.348093 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9709 09:58:10.351151 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9710 09:58:10.354480 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9711 09:58:10.357888 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9712 09:58:10.364494 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9713 09:58:10.367665 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9714 09:58:10.370957 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9715 09:58:10.374320 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9716 09:58:10.380472 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9717 09:58:10.384185 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9718 09:58:10.387218 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9719 09:58:10.390517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9720 09:58:10.397290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9721 09:58:10.400735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9722 09:58:10.404050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9723 09:58:10.410811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9724 09:58:10.413415 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9725 09:58:10.420496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9726 09:58:10.423353 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9727 09:58:10.426619 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9728 09:58:10.433448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9729 09:58:10.436753 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9730 09:58:10.443398 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9731 09:58:10.446630 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9732 09:58:10.450304 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9733 09:58:10.456960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9734 09:58:10.459621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9735 09:58:10.466599 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9736 09:58:10.469712 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9737 09:58:10.476192 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9738 09:58:10.479282 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9739 09:58:10.482706 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9740 09:58:10.489203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9741 09:58:10.492587 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9742 09:58:10.499517 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9743 09:58:10.502452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9744 09:58:10.509418 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9745 09:58:10.512305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9746 09:58:10.515414 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9747 09:58:10.522759 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9748 09:58:10.525353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9749 09:58:10.532008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9750 09:58:10.535421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9751 09:58:10.542147 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9752 09:58:10.545363 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9753 09:58:10.548995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9754 09:58:10.555041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9755 09:58:10.558553 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9756 09:58:10.565296 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9757 09:58:10.568570 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9758 09:58:10.571793 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9759 09:58:10.578326 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9760 09:58:10.581552 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9761 09:58:10.588161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9762 09:58:10.591687 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9763 09:58:10.594778 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9764 09:58:10.601444 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9765 09:58:10.604545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9766 09:58:10.611277 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9767 09:58:10.614897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9768 09:58:10.621153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9769 09:58:10.624384 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9770 09:58:10.627541 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9771 09:58:10.634722 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9772 09:58:10.637602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9773 09:58:10.644338 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9774 09:58:10.647350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9775 09:58:10.654460 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9776 09:58:10.657578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9777 09:58:10.661326 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9778 09:58:10.667295 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9779 09:58:10.670684 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9780 09:58:10.676988 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9781 09:58:10.680358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9782 09:58:10.683982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9783 09:58:10.690541 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9784 09:58:10.693965 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9785 09:58:10.700243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9786 09:58:10.703778 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9787 09:58:10.706715 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9788 09:58:10.713413 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9789 09:58:10.716986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9790 09:58:10.723331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9791 09:58:10.726722 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9792 09:58:10.732990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9793 09:58:10.736424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9794 09:58:10.740045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9795 09:58:10.746207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9796 09:58:10.749812 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9797 09:58:10.756474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9798 09:58:10.759635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9799 09:58:10.766231 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9800 09:58:10.769656 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9801 09:58:10.776044 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9802 09:58:10.779515 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9803 09:58:10.782551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9804 09:58:10.789286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9805 09:58:10.793046 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9806 09:58:10.799457 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9807 09:58:10.802810 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9808 09:58:10.809226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9809 09:58:10.812860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9810 09:58:10.815777 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9811 09:58:10.822470 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9812 09:58:10.825786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9813 09:58:10.832360 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9814 09:58:10.836033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9815 09:58:10.842106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9816 09:58:10.845635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9817 09:58:10.852357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9818 09:58:10.855272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9819 09:58:10.858731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9820 09:58:10.865126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9821 09:58:10.868689 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9822 09:58:10.875267 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9823 09:58:10.878273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9824 09:58:10.885360 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9825 09:58:10.888138 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9826 09:58:10.894914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9827 09:58:10.898118 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9828 09:58:10.901798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9829 09:58:10.907660 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9830 09:58:10.910976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9831 09:58:10.917846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9832 09:58:10.921099 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9833 09:58:10.927642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9834 09:58:10.930799 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9835 09:58:10.937638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9836 09:58:10.941011 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9837 09:58:10.947104 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9838 09:58:10.950464 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9839 09:58:10.958170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9840 09:58:10.960547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9841 09:58:10.963862 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9842 09:58:10.970520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9843 09:58:10.974124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9844 09:58:10.980533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9845 09:58:10.984112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9846 09:58:10.987133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9847 09:58:10.993750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9848 09:58:10.997115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9849 09:58:11.003714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9850 09:58:11.006744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9851 09:58:11.013254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9852 09:58:11.016743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9853 09:58:11.023638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9854 09:58:11.026674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9855 09:58:11.033307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9856 09:58:11.036603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9857 09:58:11.042759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9858 09:58:11.046398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9859 09:58:11.052944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9860 09:58:11.056403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9861 09:58:11.062585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9862 09:58:11.066073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9863 09:58:11.072279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9864 09:58:11.076703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9865 09:58:11.082679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9866 09:58:11.085871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9867 09:58:11.092135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9868 09:58:11.095385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9869 09:58:11.102065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9870 09:58:11.108491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9871 09:58:11.112072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9872 09:58:11.118804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9873 09:58:11.121855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9874 09:58:11.128890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9875 09:58:11.131772 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9876 09:58:11.131857 INFO: [APUAPC] vio 0
9877 09:58:11.139346 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9878 09:58:11.142392 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9879 09:58:11.145698 INFO: [APUAPC] D0_APC_0: 0x400510
9880 09:58:11.149236 INFO: [APUAPC] D0_APC_1: 0x0
9881 09:58:11.152531 INFO: [APUAPC] D0_APC_2: 0x1540
9882 09:58:11.155796 INFO: [APUAPC] D0_APC_3: 0x0
9883 09:58:11.158936 INFO: [APUAPC] D1_APC_0: 0xffffffff
9884 09:58:11.162721 INFO: [APUAPC] D1_APC_1: 0xffffffff
9885 09:58:11.165508 INFO: [APUAPC] D1_APC_2: 0x3fffff
9886 09:58:11.168751 INFO: [APUAPC] D1_APC_3: 0x0
9887 09:58:11.172126 INFO: [APUAPC] D2_APC_0: 0xffffffff
9888 09:58:11.175292 INFO: [APUAPC] D2_APC_1: 0xffffffff
9889 09:58:11.179017 INFO: [APUAPC] D2_APC_2: 0x3fffff
9890 09:58:11.182018 INFO: [APUAPC] D2_APC_3: 0x0
9891 09:58:11.185465 INFO: [APUAPC] D3_APC_0: 0xffffffff
9892 09:58:11.188975 INFO: [APUAPC] D3_APC_1: 0xffffffff
9893 09:58:11.191986 INFO: [APUAPC] D3_APC_2: 0x3fffff
9894 09:58:11.195490 INFO: [APUAPC] D3_APC_3: 0x0
9895 09:58:11.198611 INFO: [APUAPC] D4_APC_0: 0xffffffff
9896 09:58:11.202168 INFO: [APUAPC] D4_APC_1: 0xffffffff
9897 09:58:11.205522 INFO: [APUAPC] D4_APC_2: 0x3fffff
9898 09:58:11.209023 INFO: [APUAPC] D4_APC_3: 0x0
9899 09:58:11.212037 INFO: [APUAPC] D5_APC_0: 0xffffffff
9900 09:58:11.215432 INFO: [APUAPC] D5_APC_1: 0xffffffff
9901 09:58:11.218828 INFO: [APUAPC] D5_APC_2: 0x3fffff
9902 09:58:11.218929 INFO: [APUAPC] D5_APC_3: 0x0
9903 09:58:11.222193 INFO: [APUAPC] D6_APC_0: 0xffffffff
9904 09:58:11.228770 INFO: [APUAPC] D6_APC_1: 0xffffffff
9905 09:58:11.232280 INFO: [APUAPC] D6_APC_2: 0x3fffff
9906 09:58:11.232364 INFO: [APUAPC] D6_APC_3: 0x0
9907 09:58:11.235491 INFO: [APUAPC] D7_APC_0: 0xffffffff
9908 09:58:11.238444 INFO: [APUAPC] D7_APC_1: 0xffffffff
9909 09:58:11.242188 INFO: [APUAPC] D7_APC_2: 0x3fffff
9910 09:58:11.245768 INFO: [APUAPC] D7_APC_3: 0x0
9911 09:58:11.248742 INFO: [APUAPC] D8_APC_0: 0xffffffff
9912 09:58:11.251775 INFO: [APUAPC] D8_APC_1: 0xffffffff
9913 09:58:11.254984 INFO: [APUAPC] D8_APC_2: 0x3fffff
9914 09:58:11.258273 INFO: [APUAPC] D8_APC_3: 0x0
9915 09:58:11.261906 INFO: [APUAPC] D9_APC_0: 0xffffffff
9916 09:58:11.265150 INFO: [APUAPC] D9_APC_1: 0xffffffff
9917 09:58:11.268072 INFO: [APUAPC] D9_APC_2: 0x3fffff
9918 09:58:11.271218 INFO: [APUAPC] D9_APC_3: 0x0
9919 09:58:11.274949 INFO: [APUAPC] D10_APC_0: 0xffffffff
9920 09:58:11.277999 INFO: [APUAPC] D10_APC_1: 0xffffffff
9921 09:58:11.281236 INFO: [APUAPC] D10_APC_2: 0x3fffff
9922 09:58:11.284684 INFO: [APUAPC] D10_APC_3: 0x0
9923 09:58:11.287976 INFO: [APUAPC] D11_APC_0: 0xffffffff
9924 09:58:11.291936 INFO: [APUAPC] D11_APC_1: 0xffffffff
9925 09:58:11.295363 INFO: [APUAPC] D11_APC_2: 0x3fffff
9926 09:58:11.298163 INFO: [APUAPC] D11_APC_3: 0x0
9927 09:58:11.301169 INFO: [APUAPC] D12_APC_0: 0xffffffff
9928 09:58:11.304234 INFO: [APUAPC] D12_APC_1: 0xffffffff
9929 09:58:11.307742 INFO: [APUAPC] D12_APC_2: 0x3fffff
9930 09:58:11.310899 INFO: [APUAPC] D12_APC_3: 0x0
9931 09:58:11.314539 INFO: [APUAPC] D13_APC_0: 0xffffffff
9932 09:58:11.317575 INFO: [APUAPC] D13_APC_1: 0xffffffff
9933 09:58:11.324059 INFO: [APUAPC] D13_APC_2: 0x3fffff
9934 09:58:11.324142 INFO: [APUAPC] D13_APC_3: 0x0
9935 09:58:11.328189 INFO: [APUAPC] D14_APC_0: 0xffffffff
9936 09:58:11.334259 INFO: [APUAPC] D14_APC_1: 0xffffffff
9937 09:58:11.337367 INFO: [APUAPC] D14_APC_2: 0x3fffff
9938 09:58:11.337451 INFO: [APUAPC] D14_APC_3: 0x0
9939 09:58:11.343961 INFO: [APUAPC] D15_APC_0: 0xffffffff
9940 09:58:11.347166 INFO: [APUAPC] D15_APC_1: 0xffffffff
9941 09:58:11.350818 INFO: [APUAPC] D15_APC_2: 0x3fffff
9942 09:58:11.350902 INFO: [APUAPC] D15_APC_3: 0x0
9943 09:58:11.354237 INFO: [APUAPC] APC_CON: 0x4
9944 09:58:11.357246 INFO: [NOCDAPC] D0_APC_0: 0x0
9945 09:58:11.360368 INFO: [NOCDAPC] D0_APC_1: 0x0
9946 09:58:11.364057 INFO: [NOCDAPC] D1_APC_0: 0x0
9947 09:58:11.367070 INFO: [NOCDAPC] D1_APC_1: 0xfff
9948 09:58:11.370611 INFO: [NOCDAPC] D2_APC_0: 0x0
9949 09:58:11.373934 INFO: [NOCDAPC] D2_APC_1: 0xfff
9950 09:58:11.376719 INFO: [NOCDAPC] D3_APC_0: 0x0
9951 09:58:11.380721 INFO: [NOCDAPC] D3_APC_1: 0xfff
9952 09:58:11.380804 INFO: [NOCDAPC] D4_APC_0: 0x0
9953 09:58:11.383901 INFO: [NOCDAPC] D4_APC_1: 0xfff
9954 09:58:11.387011 INFO: [NOCDAPC] D5_APC_0: 0x0
9955 09:58:11.390419 INFO: [NOCDAPC] D5_APC_1: 0xfff
9956 09:58:11.393657 INFO: [NOCDAPC] D6_APC_0: 0x0
9957 09:58:11.396845 INFO: [NOCDAPC] D6_APC_1: 0xfff
9958 09:58:11.400079 INFO: [NOCDAPC] D7_APC_0: 0x0
9959 09:58:11.403310 INFO: [NOCDAPC] D7_APC_1: 0xfff
9960 09:58:11.406955 INFO: [NOCDAPC] D8_APC_0: 0x0
9961 09:58:11.410816 INFO: [NOCDAPC] D8_APC_1: 0xfff
9962 09:58:11.413187 INFO: [NOCDAPC] D9_APC_0: 0x0
9963 09:58:11.416951 INFO: [NOCDAPC] D9_APC_1: 0xfff
9964 09:58:11.419915 INFO: [NOCDAPC] D10_APC_0: 0x0
9965 09:58:11.420017 INFO: [NOCDAPC] D10_APC_1: 0xfff
9966 09:58:11.423136 INFO: [NOCDAPC] D11_APC_0: 0x0
9967 09:58:11.426371 INFO: [NOCDAPC] D11_APC_1: 0xfff
9968 09:58:11.429613 INFO: [NOCDAPC] D12_APC_0: 0x0
9969 09:58:11.432955 INFO: [NOCDAPC] D12_APC_1: 0xfff
9970 09:58:11.436947 INFO: [NOCDAPC] D13_APC_0: 0x0
9971 09:58:11.439896 INFO: [NOCDAPC] D13_APC_1: 0xfff
9972 09:58:11.442755 INFO: [NOCDAPC] D14_APC_0: 0x0
9973 09:58:11.446659 INFO: [NOCDAPC] D14_APC_1: 0xfff
9974 09:58:11.449315 INFO: [NOCDAPC] D15_APC_0: 0x0
9975 09:58:11.452643 INFO: [NOCDAPC] D15_APC_1: 0xfff
9976 09:58:11.455829 INFO: [NOCDAPC] APC_CON: 0x4
9977 09:58:11.459162 INFO: [APUAPC] set_apusys_apc done
9978 09:58:11.462774 INFO: [DEVAPC] devapc_init done
9979 09:58:11.465959 INFO: GICv3 without legacy support detected.
9980 09:58:11.469154 INFO: ARM GICv3 driver initialized in EL3
9981 09:58:11.472892 INFO: Maximum SPI INTID supported: 639
9982 09:58:11.479020 INFO: BL31: Initializing runtime services
9983 09:58:11.482357 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9984 09:58:11.485807 INFO: SPM: enable CPC mode
9985 09:58:11.492519 INFO: mcdi ready for mcusys-off-idle and system suspend
9986 09:58:11.495593 INFO: BL31: Preparing for EL3 exit to normal world
9987 09:58:11.498834 INFO: Entry point address = 0x80000000
9988 09:58:11.502220 INFO: SPSR = 0x8
9989 09:58:11.507282
9990 09:58:11.507370
9991 09:58:11.507435
9992 09:58:11.510571 Starting depthcharge on Spherion...
9993 09:58:11.510680
9994 09:58:11.510775 Wipe memory regions:
9995 09:58:11.510865
9996 09:58:11.511682 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9997 09:58:11.511813 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9998 09:58:11.511901 Setting prompt string to ['asurada:']
9999 09:58:11.511984 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10000 09:58:11.514699 [0x00000040000000, 0x00000054600000)
10001 09:58:11.636202
10002 09:58:11.636337 [0x00000054660000, 0x00000080000000)
10003 09:58:11.897051
10004 09:58:11.897192 [0x000000821a7280, 0x000000ffe64000)
10005 09:58:12.642167
10006 09:58:12.642336 [0x00000100000000, 0x00000240000000)
10007 09:58:14.532425
10008 09:58:14.535644 Initializing XHCI USB controller at 0x11200000.
10009 09:58:15.574709
10010 09:58:15.577951 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10011 09:58:15.578038
10012 09:58:15.578103
10013 09:58:15.578164
10014 09:58:15.578448 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10016 09:58:15.678804 asurada: tftpboot 192.168.201.1 12073287/tftp-deploy-c1unlv2r/kernel/image.itb 12073287/tftp-deploy-c1unlv2r/kernel/cmdline
10017 09:58:15.678946 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10018 09:58:15.679035 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10019 09:58:15.683089 tftpboot 192.168.201.1 12073287/tftp-deploy-c1unlv2r/kernel/image.ittp-deploy-c1unlv2r/kernel/cmdline
10020 09:58:15.683174
10021 09:58:15.683239 Waiting for link
10022 09:58:15.843791
10023 09:58:15.843914 R8152: Initializing
10024 09:58:15.843982
10025 09:58:15.847053 Version 6 (ocp_data = 5c30)
10026 09:58:15.847135
10027 09:58:15.850372 R8152: Done initializing
10028 09:58:15.850455
10029 09:58:15.850519 Adding net device
10030 09:58:17.894954
10031 09:58:17.895092 done.
10032 09:58:17.895161
10033 09:58:17.895261 MAC: 00:24:32:30:7c:7b
10034 09:58:17.895321
10035 09:58:17.897982 Sending DHCP discover... done.
10036 09:58:17.898064
10037 09:58:21.531770 Waiting for reply... done.
10038 09:58:21.531973
10039 09:58:21.532081 Sending DHCP request... done.
10040 09:58:21.535159
10041 09:58:21.535308 Waiting for reply... done.
10042 09:58:21.538674
10043 09:58:21.538903 My ip is 192.168.201.14
10044 09:58:21.539029
10045 09:58:21.541446 The DHCP server ip is 192.168.201.1
10046 09:58:21.541686
10047 09:58:21.544993 TFTP server IP predefined by user: 192.168.201.1
10048 09:58:21.545284
10049 09:58:21.551545 Bootfile predefined by user: 12073287/tftp-deploy-c1unlv2r/kernel/image.itb
10050 09:58:21.551793
10051 09:58:21.555295 Sending tftp read request... done.
10052 09:58:21.555667
10053 09:58:21.563449 Waiting for the transfer...
10054 09:58:21.563838
10055 09:58:22.243368 00000000 ################################################################
10056 09:58:22.243861
10057 09:58:22.917767 00080000 ################################################################
10058 09:58:22.918451
10059 09:58:23.583050 00100000 ################################################################
10060 09:58:23.583188
10061 09:58:24.136788 00180000 ################################################################
10062 09:58:24.136949
10063 09:58:24.669933 00200000 ################################################################
10064 09:58:24.670146
10065 09:58:25.250418 00280000 ################################################################
10066 09:58:25.250557
10067 09:58:25.803805 00300000 ################################################################
10068 09:58:25.804165
10069 09:58:26.432570 00380000 ################################################################
10070 09:58:26.432705
10071 09:58:27.025156 00400000 ################################################################
10072 09:58:27.025292
10073 09:58:27.634049 00480000 ################################################################
10074 09:58:27.634194
10075 09:58:28.277872 00500000 ################################################################
10076 09:58:28.278400
10077 09:58:28.952271 00580000 ################################################################
10078 09:58:28.952942
10079 09:58:29.624743 00600000 ################################################################
10080 09:58:29.625299
10081 09:58:30.302798 00680000 ################################################################
10082 09:58:30.303344
10083 09:58:30.972245 00700000 ################################################################
10084 09:58:30.972769
10085 09:58:31.648041 00780000 ################################################################
10086 09:58:31.648660
10087 09:58:32.320224 00800000 ################################################################
10088 09:58:32.320737
10089 09:58:32.990247 00880000 ################################################################
10090 09:58:32.990778
10091 09:58:33.679549 00900000 ################################################################
10092 09:58:33.680100
10093 09:58:34.357597 00980000 ################################################################
10094 09:58:34.358124
10095 09:58:35.041866 00a00000 ################################################################
10096 09:58:35.042400
10097 09:58:35.735381 00a80000 ################################################################
10098 09:58:35.735880
10099 09:58:36.424223 00b00000 ################################################################
10100 09:58:36.424709
10101 09:58:37.108589 00b80000 ################################################################
10102 09:58:37.109143
10103 09:58:37.793053 00c00000 ################################################################
10104 09:58:37.793546
10105 09:58:38.453426 00c80000 ################################################################
10106 09:58:38.453914
10107 09:58:39.049991 00d00000 ################################################################
10108 09:58:39.050130
10109 09:58:39.658375 00d80000 ################################################################
10110 09:58:39.658544
10111 09:58:40.251264 00e00000 ################################################################
10112 09:58:40.251403
10113 09:58:40.825109 00e80000 ################################################################
10114 09:58:40.825254
10115 09:58:41.412504 00f00000 ################################################################
10116 09:58:41.412633
10117 09:58:42.066108 00f80000 ################################################################
10118 09:58:42.066694
10119 09:58:42.719944 01000000 ################################################################
10120 09:58:42.720477
10121 09:58:43.334765 01080000 ################################################################
10122 09:58:43.334910
10123 09:58:43.899190 01100000 ################################################################
10124 09:58:43.899376
10125 09:58:44.445083 01180000 ################################################################
10126 09:58:44.445251
10127 09:58:45.006170 01200000 ################################################################
10128 09:58:45.006398
10129 09:58:45.559785 01280000 ################################################################
10130 09:58:45.559941
10131 09:58:46.107468 01300000 ################################################################
10132 09:58:46.107619
10133 09:58:46.672473 01380000 ################################################################
10134 09:58:46.672603
10135 09:58:47.286116 01400000 ################################################################
10136 09:58:47.286285
10137 09:58:47.969951 01480000 ################################################################
10138 09:58:47.970102
10139 09:58:48.599210 01500000 ################################################################
10140 09:58:48.599381
10141 09:58:49.172706 01580000 ################################################################
10142 09:58:49.172841
10143 09:58:49.749146 01600000 ################################################################
10144 09:58:49.749278
10145 09:58:50.324770 01680000 ################################################################
10146 09:58:50.324906
10147 09:58:50.915301 01700000 ################################################################
10148 09:58:50.915439
10149 09:58:51.499018 01780000 ################################################################
10150 09:58:51.499180
10151 09:58:52.066107 01800000 ################################################################
10152 09:58:52.066244
10153 09:58:52.617200 01880000 ################################################################
10154 09:58:52.617363
10155 09:58:53.141786 01900000 ################################################################
10156 09:58:53.141947
10157 09:58:53.671547 01980000 ################################################################
10158 09:58:53.671723
10159 09:58:54.220709 01a00000 ################################################################
10160 09:58:54.220855
10161 09:58:54.753862 01a80000 ################################################################
10162 09:58:54.754037
10163 09:58:55.286259 01b00000 ################################################################
10164 09:58:55.286419
10165 09:58:55.861162 01b80000 ################################################################
10166 09:58:55.861680
10167 09:58:56.502772 01c00000 ################################################################
10168 09:58:56.502922
10169 09:58:57.049502 01c80000 ################################################################
10170 09:58:57.049652
10171 09:58:57.610720 01d00000 ################################################################
10172 09:58:57.610867
10173 09:58:58.182637 01d80000 ################################################################
10174 09:58:58.183124
10175 09:58:58.795742 01e00000 ################################################################
10176 09:58:58.796006
10177 09:58:59.459373 01e80000 ################################################################
10178 09:58:59.459887
10179 09:59:00.132486 01f00000 ################################################################
10180 09:59:00.132983
10181 09:59:00.798059 01f80000 ################################################################
10182 09:59:00.798808
10183 09:59:01.353793 02000000 ################################################################
10184 09:59:01.353942
10185 09:59:01.963308 02080000 ################################################################
10186 09:59:01.963466
10187 09:59:02.549235 02100000 ################################################################
10188 09:59:02.549370
10189 09:59:03.225396 02180000 ################################################################
10190 09:59:03.225898
10191 09:59:03.790700 02200000 ################################################################
10192 09:59:03.790837
10193 09:59:04.346119 02280000 ################################################################
10194 09:59:04.346265
10195 09:59:04.948262 02300000 ################################################################
10196 09:59:04.948393
10197 09:59:05.512100 02380000 ################################################################
10198 09:59:05.512234
10199 09:59:06.093928 02400000 ################################################################
10200 09:59:06.094061
10201 09:59:06.739223 02480000 ################################################################
10202 09:59:06.739359
10203 09:59:07.345522 02500000 ################################################################
10204 09:59:07.345663
10205 09:59:07.911602 02580000 ################################################################
10206 09:59:07.911735
10207 09:59:08.492896 02600000 ################################################################
10208 09:59:08.493035
10209 09:59:09.124559 02680000 ################################################################
10210 09:59:09.124697
10211 09:59:09.696864 02700000 ################################################################
10212 09:59:09.697002
10213 09:59:10.288371 02780000 ################################################################
10214 09:59:10.288506
10215 09:59:10.854650 02800000 ################################################################
10216 09:59:10.854796
10217 09:59:11.415639 02880000 ################################################################
10218 09:59:11.416171
10219 09:59:12.037678 02900000 ################################################################
10220 09:59:12.037837
10221 09:59:12.610879 02980000 ################################################################
10222 09:59:12.611012
10223 09:59:13.188735 02a00000 ################################################################
10224 09:59:13.189225
10225 09:59:13.832323 02a80000 ################################################################
10226 09:59:13.832954
10227 09:59:14.429567 02b00000 ################################################################
10228 09:59:14.429722
10229 09:59:14.999640 02b80000 ################################################################
10230 09:59:14.999777
10231 09:59:15.580565 02c00000 ################################################################
10232 09:59:15.580700
10233 09:59:16.123919 02c80000 ################################################################
10234 09:59:16.124061
10235 09:59:16.736434 02d00000 ################################################################
10236 09:59:16.736571
10237 09:59:17.357584 02d80000 ################################################################
10238 09:59:17.358158
10239 09:59:17.989475 02e00000 ################################################################
10240 09:59:17.989608
10241 09:59:18.548465 02e80000 ################################################################
10242 09:59:18.548602
10243 09:59:19.128944 02f00000 ################################################################
10244 09:59:19.129081
10245 09:59:19.711729 02f80000 ################################################################
10246 09:59:19.711864
10247 09:59:20.290570 03000000 ################################################################
10248 09:59:20.290707
10249 09:59:20.842134 03080000 ################################################################
10250 09:59:20.842347
10251 09:59:21.387665 03100000 ################################################################
10252 09:59:21.387802
10253 09:59:21.908079 03180000 ################################################################
10254 09:59:21.908217
10255 09:59:22.437324 03200000 ################################################################
10256 09:59:22.437469
10257 09:59:22.995828 03280000 ################################################################
10258 09:59:22.995974
10259 09:59:23.548910 03300000 ################################################################
10260 09:59:23.549051
10261 09:59:24.073566 03380000 ################################################################
10262 09:59:24.073697
10263 09:59:24.601472 03400000 ################################################################
10264 09:59:24.601608
10265 09:59:25.137096 03480000 ################################################################
10266 09:59:25.137232
10267 09:59:25.719266 03500000 ################################################################
10268 09:59:25.719400
10269 09:59:26.267924 03580000 ################################################################
10270 09:59:26.268089
10271 09:59:26.798751 03600000 ################################################################
10272 09:59:26.798895
10273 09:59:27.336508 03680000 ################################################################
10274 09:59:27.336642
10275 09:59:27.889257 03700000 ################################################################
10276 09:59:27.889417
10277 09:59:28.415890 03780000 ################################################################
10278 09:59:28.416024
10279 09:59:28.949608 03800000 ################################################################
10280 09:59:28.949748
10281 09:59:29.476245 03880000 ################################################################
10282 09:59:29.476390
10283 09:59:30.015065 03900000 ################################################################
10284 09:59:30.015220
10285 09:59:30.541162 03980000 ################################################################
10286 09:59:30.541317
10287 09:59:31.102624 03a00000 ################################################################
10288 09:59:31.102787
10289 09:59:31.676194 03a80000 ################################################################
10290 09:59:31.676358
10291 09:59:32.237385 03b00000 ################################################################
10292 09:59:32.237543
10293 09:59:32.783178 03b80000 ################################################################
10294 09:59:32.783345
10295 09:59:33.354071 03c00000 ################################################################
10296 09:59:33.354230
10297 09:59:33.940783 03c80000 ################################################################
10298 09:59:33.940940
10299 09:59:34.527750 03d00000 ################################################################
10300 09:59:34.527905
10301 09:59:35.094120 03d80000 ################################################################
10302 09:59:35.094321
10303 09:59:35.646231 03e00000 ################################################################
10304 09:59:35.646395
10305 09:59:36.182685 03e80000 ################################################################
10306 09:59:36.182838
10307 09:59:36.753268 03f00000 ################################################################
10308 09:59:36.753420
10309 09:59:37.290984 03f80000 ################################################################
10310 09:59:37.291139
10311 09:59:37.833092 04000000 ################################################################
10312 09:59:37.833241
10313 09:59:38.429705 04080000 ################################################################
10314 09:59:38.429858
10315 09:59:39.011856 04100000 ################################################################
10316 09:59:39.012028
10317 09:59:39.603370 04180000 ################################################################
10318 09:59:39.603543
10319 09:59:40.161445 04200000 ################################################################
10320 09:59:40.161595
10321 09:59:40.731944 04280000 ################################################################
10322 09:59:40.732082
10323 09:59:41.293187 04300000 ################################################################
10324 09:59:41.293338
10325 09:59:41.838904 04380000 ################################################################
10326 09:59:41.839090
10327 09:59:42.373067 04400000 ################################################################
10328 09:59:42.373222
10329 09:59:42.899497 04480000 ################################################################
10330 09:59:42.899651
10331 09:59:43.461739 04500000 ################################################################
10332 09:59:43.461884
10333 09:59:44.039194 04580000 ################################################################
10334 09:59:44.039339
10335 09:59:44.596728 04600000 ################################################################
10336 09:59:44.596872
10337 09:59:45.168718 04680000 ################################################################
10338 09:59:45.168865
10339 09:59:45.740112 04700000 ################################################################
10340 09:59:45.740248
10341 09:59:46.312629 04780000 ################################################################
10342 09:59:46.312772
10343 09:59:46.887943 04800000 ################################################################
10344 09:59:46.888088
10345 09:59:47.464431 04880000 ################################################################
10346 09:59:47.464577
10347 09:59:48.035985 04900000 ################################################################
10348 09:59:48.036144
10349 09:59:48.601775 04980000 ################################################################
10350 09:59:48.601923
10351 09:59:49.159193 04a00000 ################################################################
10352 09:59:49.159341
10353 09:59:49.702479 04a80000 ################################################################
10354 09:59:49.702616
10355 09:59:50.252722 04b00000 ################################################################
10356 09:59:50.252857
10357 09:59:50.814811 04b80000 ################################################################
10358 09:59:50.814947
10359 09:59:51.383315 04c00000 ################################################################
10360 09:59:51.383453
10361 09:59:51.957215 04c80000 ################################################################
10362 09:59:51.957368
10363 09:59:52.533811 04d00000 ################################################################
10364 09:59:52.533964
10365 09:59:53.110349 04d80000 ################################################################
10366 09:59:53.110504
10367 09:59:53.686860 04e00000 ################################################################
10368 09:59:53.687020
10369 09:59:54.251193 04e80000 ################################################################
10370 09:59:54.251354
10371 09:59:54.828353 04f00000 ################################################################
10372 09:59:54.828514
10373 09:59:55.398372 04f80000 ################################################################
10374 09:59:55.398529
10375 09:59:55.951882 05000000 ################################################################
10376 09:59:55.952064
10377 09:59:56.493587 05080000 ################################################################
10378 09:59:56.493747
10379 09:59:57.033862 05100000 ################################################################
10380 09:59:57.034016
10381 09:59:57.599645 05180000 ################################################################
10382 09:59:57.599804
10383 09:59:58.129379 05200000 ################################################################
10384 09:59:58.129528
10385 09:59:58.667646 05280000 ################################################################
10386 09:59:58.667824
10387 09:59:59.212819 05300000 ################################################################
10388 09:59:59.212969
10389 09:59:59.761476 05380000 ################################################################
10390 09:59:59.761637
10391 10:00:00.303880 05400000 ################################################################
10392 10:00:00.304075
10393 10:00:00.836891 05480000 ################################################################
10394 10:00:00.837069
10395 10:00:01.354113 05500000 ################################################################
10396 10:00:01.354293
10397 10:00:01.892796 05580000 ################################################################
10398 10:00:01.892940
10399 10:00:02.418856 05600000 ################################################################
10400 10:00:02.419014
10401 10:00:02.961546 05680000 ################################################################
10402 10:00:02.961703
10403 10:00:03.506750 05700000 ################################################################
10404 10:00:03.506905
10405 10:00:04.035319 05780000 ################################################################
10406 10:00:04.035473
10407 10:00:04.554673 05800000 ################################################################
10408 10:00:04.554820
10409 10:00:05.084111 05880000 ################################################################
10410 10:00:05.084259
10411 10:00:05.612824 05900000 ################################################################
10412 10:00:05.613005
10413 10:00:06.130612 05980000 ################################################################
10414 10:00:06.130750
10415 10:00:06.653791 05a00000 ################################################################
10416 10:00:06.653933
10417 10:00:07.178068 05a80000 ################################################################
10418 10:00:07.178261
10419 10:00:07.691825 05b00000 ################################################################
10420 10:00:07.691987
10421 10:00:08.206058 05b80000 ################################################################
10422 10:00:08.206217
10423 10:00:08.725086 05c00000 ################################################################
10424 10:00:08.725231
10425 10:00:09.251747 05c80000 ################################################################
10426 10:00:09.251890
10427 10:00:09.771958 05d00000 ################################################################
10428 10:00:09.772099
10429 10:00:10.292805 05d80000 ################################################################
10430 10:00:10.292938
10431 10:00:10.811892 05e00000 ################################################################
10432 10:00:10.812039
10433 10:00:11.339942 05e80000 ################################################################
10434 10:00:11.340088
10435 10:00:11.853074 05f00000 ################################################################
10436 10:00:11.853224
10437 10:00:12.373989 05f80000 ################################################################
10438 10:00:12.374163
10439 10:00:12.900631 06000000 ################################################################
10440 10:00:12.900785
10441 10:00:13.431453 06080000 ################################################################
10442 10:00:13.431612
10443 10:00:13.970426 06100000 ################################################################
10444 10:00:13.970579
10445 10:00:14.503495 06180000 ################################################################
10446 10:00:14.503645
10447 10:00:15.011934 06200000 ################################################################
10448 10:00:15.012086
10449 10:00:15.538307 06280000 ################################################################
10450 10:00:15.538460
10451 10:00:16.057168 06300000 ################################################################
10452 10:00:16.057320
10453 10:00:16.584665 06380000 ################################################################
10454 10:00:16.584816
10455 10:00:17.104316 06400000 ################################################################
10456 10:00:17.104475
10457 10:00:17.622093 06480000 ################################################################
10458 10:00:17.622275
10459 10:00:18.141667 06500000 ################################################################
10460 10:00:18.141831
10461 10:00:18.660791 06580000 ################################################################
10462 10:00:18.660947
10463 10:00:19.178112 06600000 ################################################################
10464 10:00:19.178263
10465 10:00:19.690906 06680000 ################################################################
10466 10:00:19.691059
10467 10:00:20.203432 06700000 ################################################################
10468 10:00:20.203635
10469 10:00:20.721314 06780000 ################################################################
10470 10:00:20.721484
10471 10:00:21.087711 06800000 ############################################# done.
10472 10:00:21.087861
10473 10:00:21.090456 The bootfile was 109419882 bytes long.
10474 10:00:21.090580
10475 10:00:21.094301 Sending tftp read request... done.
10476 10:00:21.094420
10477 10:00:21.094518 Waiting for the transfer...
10478 10:00:21.096770
10479 10:00:21.096850 00000000 # done.
10480 10:00:21.096918
10481 10:00:21.103855 Command line loaded dynamically from TFTP file: 12073287/tftp-deploy-c1unlv2r/kernel/cmdline
10482 10:00:21.103943
10483 10:00:21.116817 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10484 10:00:21.120116
10485 10:00:21.120229 Loading FIT.
10486 10:00:21.120321
10487 10:00:21.124252 Image ramdisk-1 has 98323028 bytes.
10488 10:00:21.124359
10489 10:00:21.126903 Image fdt-1 has 47278 bytes.
10490 10:00:21.126986
10491 10:00:21.130204 Image kernel-1 has 11047542 bytes.
10492 10:00:21.130337
10493 10:00:21.136700 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10494 10:00:21.136801
10495 10:00:21.157391 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10496 10:00:21.157506
10497 10:00:21.159435 Choosing best match conf-1 for compat google,spherion-rev2.
10498 10:00:21.164217
10499 10:00:21.169047 Connected to device vid:did:rid of 1ae0:0028:00
10500 10:00:21.177574
10501 10:00:21.180642 tpm_get_response: command 0x17b, return code 0x0
10502 10:00:21.180757
10503 10:00:21.187162 ec_init: CrosEC protocol v3 supported (256, 248)
10504 10:00:21.187247
10505 10:00:21.190115 tpm_cleanup: add release locality here.
10506 10:00:21.190221
10507 10:00:21.194005 Shutting down all USB controllers.
10508 10:00:21.194086
10509 10:00:21.197036 Removing current net device
10510 10:00:21.197118
10511 10:00:21.200210 Exiting depthcharge with code 4 at timestamp: 158921893
10512 10:00:21.203672
10513 10:00:21.206848 LZMA decompressing kernel-1 to 0x821a6718
10514 10:00:21.206930
10515 10:00:21.210308 LZMA decompressing kernel-1 to 0x40000000
10516 10:00:22.599372
10517 10:00:22.599550 jumping to kernel
10518 10:00:22.600128 end: 2.2.4 bootloader-commands (duration 00:02:11) [common]
10519 10:00:22.600244 start: 2.2.5 auto-login-action (timeout 00:02:14) [common]
10520 10:00:22.600349 Setting prompt string to ['Linux version [0-9]']
10521 10:00:22.600447 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10522 10:00:22.600551 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10523 10:00:22.680688
10524 10:00:22.684541 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10525 10:00:22.687305 start: 2.2.5.1 login-action (timeout 00:02:14) [common]
10526 10:00:22.687420 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10527 10:00:22.687526 Setting prompt string to []
10528 10:00:22.687636 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10529 10:00:22.687747 Using line separator: #'\n'#
10530 10:00:22.687836 No login prompt set.
10531 10:00:22.687927 Parsing kernel messages
10532 10:00:22.688066 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10533 10:00:22.688258 [login-action] Waiting for messages, (timeout 00:02:14)
10534 10:00:22.707481 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10535 10:00:22.710295 [ 0.000000] random: crng init done
10536 10:00:22.717444 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10537 10:00:22.720592 [ 0.000000] efi: UEFI not found.
10538 10:00:22.726657 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10539 10:00:22.733816 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10540 10:00:22.743512 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10541 10:00:22.756161 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10542 10:00:22.760276 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10543 10:00:22.766152 [ 0.000000] printk: bootconsole [mtk8250] enabled
10544 10:00:22.773180 [ 0.000000] NUMA: No NUMA configuration found
10545 10:00:22.779562 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10546 10:00:22.782918 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10547 10:00:22.786087 [ 0.000000] Zone ranges:
10548 10:00:22.793187 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10549 10:00:22.796888 [ 0.000000] DMA32 empty
10550 10:00:22.803064 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10551 10:00:22.806093 [ 0.000000] Movable zone start for each node
10552 10:00:22.809098 [ 0.000000] Early memory node ranges
10553 10:00:22.815601 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10554 10:00:22.822497 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10555 10:00:22.829050 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10556 10:00:22.836008 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10557 10:00:22.842291 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10558 10:00:22.848505 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10559 10:00:22.904694 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10560 10:00:22.911608 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10561 10:00:22.918512 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10562 10:00:22.921965 [ 0.000000] psci: probing for conduit method from DT.
10563 10:00:22.928109 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10564 10:00:22.931592 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10565 10:00:22.938503 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10566 10:00:22.941188 [ 0.000000] psci: SMC Calling Convention v1.2
10567 10:00:22.947734 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10568 10:00:22.951442 [ 0.000000] Detected VIPT I-cache on CPU0
10569 10:00:22.957896 [ 0.000000] CPU features: detected: GIC system register CPU interface
10570 10:00:22.964343 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10571 10:00:22.970719 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10572 10:00:22.977419 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10573 10:00:22.987152 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10574 10:00:22.994184 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10575 10:00:22.997035 [ 0.000000] alternatives: applying boot alternatives
10576 10:00:23.003866 [ 0.000000] Fallback order for Node 0: 0
10577 10:00:23.010504 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10578 10:00:23.013590 [ 0.000000] Policy zone: Normal
10579 10:00:23.026622 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10580 10:00:23.036528 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10581 10:00:23.049120 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10582 10:00:23.059090 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10583 10:00:23.065938 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10584 10:00:23.069477 <6>[ 0.000000] software IO TLB: area num 8.
10585 10:00:23.126405 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10586 10:00:23.275414 <6>[ 0.000000] Memory: 7873600K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 479168K reserved, 32768K cma-reserved)
10587 10:00:23.282146 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10588 10:00:23.288405 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10589 10:00:23.291557 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10590 10:00:23.298562 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10591 10:00:23.305040 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10592 10:00:23.308522 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10593 10:00:23.318365 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10594 10:00:23.325104 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10595 10:00:23.331480 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10596 10:00:23.338371 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10597 10:00:23.341199 <6>[ 0.000000] GICv3: 608 SPIs implemented
10598 10:00:23.344135 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10599 10:00:23.351122 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10600 10:00:23.354509 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10601 10:00:23.360700 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10602 10:00:23.374014 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10603 10:00:23.387243 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10604 10:00:23.393765 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10605 10:00:23.402022 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10606 10:00:23.415365 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10607 10:00:23.421845 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10608 10:00:23.428111 <6>[ 0.009177] Console: colour dummy device 80x25
10609 10:00:23.437968 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10610 10:00:23.445026 <6>[ 0.024375] pid_max: default: 32768 minimum: 301
10611 10:00:23.448498 <6>[ 0.029248] LSM: Security Framework initializing
10612 10:00:23.454633 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10613 10:00:23.464370 <6>[ 0.041998] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10614 10:00:23.474098 <6>[ 0.051458] cblist_init_generic: Setting adjustable number of callback queues.
10615 10:00:23.480933 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10616 10:00:23.487925 <6>[ 0.065239] cblist_init_generic: Setting adjustable number of callback queues.
10617 10:00:23.493949 <6>[ 0.072667] cblist_init_generic: Setting shift to 3 and lim to 1.
10618 10:00:23.497168 <6>[ 0.079065] rcu: Hierarchical SRCU implementation.
10619 10:00:23.503738 <6>[ 0.084111] rcu: Max phase no-delay instances is 1000.
10620 10:00:23.510393 <6>[ 0.091167] EFI services will not be available.
10621 10:00:23.514122 <6>[ 0.096120] smp: Bringing up secondary CPUs ...
10622 10:00:23.522935 <6>[ 0.101200] Detected VIPT I-cache on CPU1
10623 10:00:23.529166 <6>[ 0.101269] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10624 10:00:23.536171 <6>[ 0.101300] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10625 10:00:23.539170 <6>[ 0.101637] Detected VIPT I-cache on CPU2
10626 10:00:23.548831 <6>[ 0.101688] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10627 10:00:23.555412 <6>[ 0.101703] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10628 10:00:23.558950 <6>[ 0.101962] Detected VIPT I-cache on CPU3
10629 10:00:23.565566 <6>[ 0.102008] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10630 10:00:23.572013 <6>[ 0.102021] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10631 10:00:23.578744 <6>[ 0.102326] CPU features: detected: Spectre-v4
10632 10:00:23.581883 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10633 10:00:23.585679 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10634 10:00:23.595114 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10635 10:00:23.601815 <6>[ 0.102412] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10636 10:00:23.605097 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10637 10:00:23.611504 <6>[ 0.102768] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10638 10:00:23.618289 <6>[ 0.102785] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10639 10:00:23.621173 <6>[ 0.103064] Detected PIPT I-cache on CPU6
10640 10:00:23.631705 <6>[ 0.103130] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10641 10:00:23.638122 <6>[ 0.103146] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10642 10:00:23.641355 <6>[ 0.103444] Detected PIPT I-cache on CPU7
10643 10:00:23.647583 <6>[ 0.103510] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10644 10:00:23.654322 <6>[ 0.103526] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10645 10:00:23.657813 <6>[ 0.103574] smp: Brought up 1 node, 8 CPUs
10646 10:00:23.664762 <6>[ 0.245060] SMP: Total of 8 processors activated.
10647 10:00:23.670743 <6>[ 0.250011] CPU features: detected: 32-bit EL0 Support
10648 10:00:23.677592 <6>[ 0.255407] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10649 10:00:23.684352 <6>[ 0.264262] CPU features: detected: Common not Private translations
10650 10:00:23.691068 <6>[ 0.270737] CPU features: detected: CRC32 instructions
10651 10:00:23.697634 <6>[ 0.276121] CPU features: detected: RCpc load-acquire (LDAPR)
10652 10:00:23.700809 <6>[ 0.282081] CPU features: detected: LSE atomic instructions
10653 10:00:23.707114 <6>[ 0.287862] CPU features: detected: Privileged Access Never
10654 10:00:23.713660 <6>[ 0.293678] CPU features: detected: RAS Extension Support
10655 10:00:23.720603 <6>[ 0.299286] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10656 10:00:23.723867 <6>[ 0.306550] CPU: All CPU(s) started at EL2
10657 10:00:23.730103 <6>[ 0.310867] alternatives: applying system-wide alternatives
10658 10:00:23.740604 <6>[ 0.321590] devtmpfs: initialized
10659 10:00:23.753040 <6>[ 0.330441] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10660 10:00:23.762986 <6>[ 0.340404] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10661 10:00:23.769554 <6>[ 0.348425] pinctrl core: initialized pinctrl subsystem
10662 10:00:23.773251 <6>[ 0.355082] DMI not present or invalid.
10663 10:00:23.779487 <6>[ 0.359495] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10664 10:00:23.789100 <6>[ 0.366365] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10665 10:00:23.795789 <6>[ 0.373948] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10666 10:00:23.805980 <6>[ 0.382162] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10667 10:00:23.809420 <6>[ 0.390408] audit: initializing netlink subsys (disabled)
10668 10:00:23.819150 <5>[ 0.396100] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10669 10:00:23.825448 <6>[ 0.396798] thermal_sys: Registered thermal governor 'step_wise'
10670 10:00:23.832406 <6>[ 0.404068] thermal_sys: Registered thermal governor 'power_allocator'
10671 10:00:23.835264 <6>[ 0.410325] cpuidle: using governor menu
10672 10:00:23.841760 <6>[ 0.421281] NET: Registered PF_QIPCRTR protocol family
10673 10:00:23.848461 <6>[ 0.426766] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10674 10:00:23.852149 <6>[ 0.433867] ASID allocator initialised with 32768 entries
10675 10:00:23.859357 <6>[ 0.440425] Serial: AMBA PL011 UART driver
10676 10:00:23.868150 <4>[ 0.449205] Trying to register duplicate clock ID: 134
10677 10:00:23.922911 <6>[ 0.506649] KASLR enabled
10678 10:00:23.936532 <6>[ 0.514333] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10679 10:00:23.943207 <6>[ 0.521348] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10680 10:00:23.949777 <6>[ 0.527840] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10681 10:00:23.956325 <6>[ 0.534845] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10682 10:00:23.963070 <6>[ 0.541333] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10683 10:00:23.969575 <6>[ 0.548337] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10684 10:00:23.976304 <6>[ 0.554825] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10685 10:00:23.982930 <6>[ 0.561830] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10686 10:00:23.986024 <6>[ 0.569323] ACPI: Interpreter disabled.
10687 10:00:23.994740 <6>[ 0.575720] iommu: Default domain type: Translated
10688 10:00:24.001263 <6>[ 0.580830] iommu: DMA domain TLB invalidation policy: strict mode
10689 10:00:24.004505 <5>[ 0.587485] SCSI subsystem initialized
10690 10:00:24.011848 <6>[ 0.591645] usbcore: registered new interface driver usbfs
10691 10:00:24.018146 <6>[ 0.597375] usbcore: registered new interface driver hub
10692 10:00:24.020828 <6>[ 0.602926] usbcore: registered new device driver usb
10693 10:00:24.028823 <6>[ 0.609021] pps_core: LinuxPPS API ver. 1 registered
10694 10:00:24.037886 <6>[ 0.614214] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10695 10:00:24.041553 <6>[ 0.623561] PTP clock support registered
10696 10:00:24.044856 <6>[ 0.627802] EDAC MC: Ver: 3.0.0
10697 10:00:24.052197 <6>[ 0.632956] FPGA manager framework
10698 10:00:24.058493 <6>[ 0.636634] Advanced Linux Sound Architecture Driver Initialized.
10699 10:00:24.061826 <6>[ 0.643397] vgaarb: loaded
10700 10:00:24.068663 <6>[ 0.646564] clocksource: Switched to clocksource arch_sys_counter
10701 10:00:24.072202 <5>[ 0.652992] VFS: Disk quotas dquot_6.6.0
10702 10:00:24.079217 <6>[ 0.657179] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10703 10:00:24.082087 <6>[ 0.664365] pnp: PnP ACPI: disabled
10704 10:00:24.090290 <6>[ 0.670952] NET: Registered PF_INET protocol family
10705 10:00:24.099620 <6>[ 0.676536] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10706 10:00:24.111857 <6>[ 0.688833] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10707 10:00:24.120901 <6>[ 0.697647] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10708 10:00:24.127558 <6>[ 0.705618] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10709 10:00:24.138027 <6>[ 0.714318] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10710 10:00:24.144321 <6>[ 0.724063] TCP: Hash tables configured (established 65536 bind 65536)
10711 10:00:24.150958 <6>[ 0.730925] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10712 10:00:24.160837 <6>[ 0.738126] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10713 10:00:24.167233 <6>[ 0.745826] NET: Registered PF_UNIX/PF_LOCAL protocol family
10714 10:00:24.173706 <6>[ 0.751992] RPC: Registered named UNIX socket transport module.
10715 10:00:24.177399 <6>[ 0.758142] RPC: Registered udp transport module.
10716 10:00:24.183701 <6>[ 0.763075] RPC: Registered tcp transport module.
10717 10:00:24.190264 <6>[ 0.768009] RPC: Registered tcp NFSv4.1 backchannel transport module.
10718 10:00:24.193539 <6>[ 0.774675] PCI: CLS 0 bytes, default 64
10719 10:00:24.196931 <6>[ 0.779028] Unpacking initramfs...
10720 10:00:24.213339 <6>[ 0.791252] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10721 10:00:24.223555 <6>[ 0.799912] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10722 10:00:24.226441 <6>[ 0.808775] kvm [1]: IPA Size Limit: 40 bits
10723 10:00:24.233081 <6>[ 0.813304] kvm [1]: GICv3: no GICV resource entry
10724 10:00:24.236567 <6>[ 0.818326] kvm [1]: disabling GICv2 emulation
10725 10:00:24.242995 <6>[ 0.823017] kvm [1]: GIC system register CPU interface enabled
10726 10:00:24.246709 <6>[ 0.829188] kvm [1]: vgic interrupt IRQ18
10727 10:00:24.252918 <6>[ 0.833548] kvm [1]: VHE mode initialized successfully
10728 10:00:24.259833 <5>[ 0.840148] Initialise system trusted keyrings
10729 10:00:24.266260 <6>[ 0.844979] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10730 10:00:24.274301 <6>[ 0.854969] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10731 10:00:24.280507 <5>[ 0.861433] NFS: Registering the id_resolver key type
10732 10:00:24.283879 <5>[ 0.866735] Key type id_resolver registered
10733 10:00:24.290323 <5>[ 0.871149] Key type id_legacy registered
10734 10:00:24.297116 <6>[ 0.875425] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10735 10:00:24.304285 <6>[ 0.882346] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10736 10:00:24.310302 <6>[ 0.890099] 9p: Installing v9fs 9p2000 file system support
10737 10:00:24.347631 <5>[ 0.928504] Key type asymmetric registered
10738 10:00:24.351066 <5>[ 0.932838] Asymmetric key parser 'x509' registered
10739 10:00:24.360971 <6>[ 0.937983] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10740 10:00:24.363892 <6>[ 0.945599] io scheduler mq-deadline registered
10741 10:00:24.367512 <6>[ 0.950360] io scheduler kyber registered
10742 10:00:24.386198 <6>[ 0.967534] EINJ: ACPI disabled.
10743 10:00:24.418674 <4>[ 0.993292] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10744 10:00:24.428436 <4>[ 1.003897] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10745 10:00:24.444367 <6>[ 1.024908] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10746 10:00:24.451773 <6>[ 1.032967] printk: console [ttyS0] disabled
10747 10:00:24.479986 <6>[ 1.057624] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10748 10:00:24.486411 <6>[ 1.067106] printk: console [ttyS0] enabled
10749 10:00:24.489700 <6>[ 1.067106] printk: console [ttyS0] enabled
10750 10:00:24.496644 <6>[ 1.075999] printk: bootconsole [mtk8250] disabled
10751 10:00:24.499930 <6>[ 1.075999] printk: bootconsole [mtk8250] disabled
10752 10:00:24.506583 <6>[ 1.087281] SuperH (H)SCI(F) driver initialized
10753 10:00:24.509886 <6>[ 1.092568] msm_serial: driver initialized
10754 10:00:24.523775 <6>[ 1.101546] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10755 10:00:24.534130 <6>[ 1.110094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10756 10:00:24.540333 <6>[ 1.118640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10757 10:00:24.550939 <6>[ 1.127269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10758 10:00:24.560158 <6>[ 1.135975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10759 10:00:24.566751 <6>[ 1.144696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10760 10:00:24.576877 <6>[ 1.153237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10761 10:00:24.583465 <6>[ 1.162041] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10762 10:00:24.593258 <6>[ 1.170586] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10763 10:00:24.605274 <6>[ 1.186142] loop: module loaded
10764 10:00:24.611968 <6>[ 1.192175] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10765 10:00:24.634542 <4>[ 1.215673] mtk-pmic-keys: Failed to locate of_node [id: -1]
10766 10:00:24.641900 <6>[ 1.222625] megasas: 07.719.03.00-rc1
10767 10:00:24.651479 <6>[ 1.232429] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10768 10:00:24.661176 <6>[ 1.241941] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10769 10:00:24.677869 <6>[ 1.258538] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10770 10:00:24.734440 <6>[ 1.308489] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10771 10:00:28.205675 <6>[ 4.787099] Freeing initrd memory: 96016K
10772 10:00:28.216492 <6>[ 4.797719] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10773 10:00:28.227229 <6>[ 4.808735] tun: Universal TUN/TAP device driver, 1.6
10774 10:00:28.231085 <6>[ 4.814826] thunder_xcv, ver 1.0
10775 10:00:28.233975 <6>[ 4.818319] thunder_bgx, ver 1.0
10776 10:00:28.237293 <6>[ 4.821820] nicpf, ver 1.0
10777 10:00:28.247764 <6>[ 4.825840] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10778 10:00:28.250907 <6>[ 4.833316] hns3: Copyright (c) 2017 Huawei Corporation.
10779 10:00:28.257719 <6>[ 4.838906] hclge is initializing
10780 10:00:28.261272 <6>[ 4.842482] e1000: Intel(R) PRO/1000 Network Driver
10781 10:00:28.267548 <6>[ 4.847611] e1000: Copyright (c) 1999-2006 Intel Corporation.
10782 10:00:28.270948 <6>[ 4.853624] e1000e: Intel(R) PRO/1000 Network Driver
10783 10:00:28.277323 <6>[ 4.858840] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10784 10:00:28.284266 <6>[ 4.865024] igb: Intel(R) Gigabit Ethernet Network Driver
10785 10:00:28.290821 <6>[ 4.870674] igb: Copyright (c) 2007-2014 Intel Corporation.
10786 10:00:28.297475 <6>[ 4.876509] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10787 10:00:28.304328 <6>[ 4.883027] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10788 10:00:28.307231 <6>[ 4.889495] sky2: driver version 1.30
10789 10:00:28.313957 <6>[ 4.894499] VFIO - User Level meta-driver version: 0.3
10790 10:00:28.321618 <6>[ 4.902761] usbcore: registered new interface driver usb-storage
10791 10:00:28.327817 <6>[ 4.909204] usbcore: registered new device driver onboard-usb-hub
10792 10:00:28.337034 <6>[ 4.918379] mt6397-rtc mt6359-rtc: registered as rtc0
10793 10:00:28.347025 <6>[ 4.923847] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:00:30 UTC (1700820030)
10794 10:00:28.350486 <6>[ 4.933417] i2c_dev: i2c /dev entries driver
10795 10:00:28.367392 <6>[ 4.945261] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10796 10:00:28.387368 <6>[ 4.968252] cpu cpu0: EM: created perf domain
10797 10:00:28.390000 <6>[ 4.973173] cpu cpu4: EM: created perf domain
10798 10:00:28.397426 <6>[ 4.978802] sdhci: Secure Digital Host Controller Interface driver
10799 10:00:28.403797 <6>[ 4.985231] sdhci: Copyright(c) Pierre Ossman
10800 10:00:28.410918 <6>[ 4.990180] Synopsys Designware Multimedia Card Interface Driver
10801 10:00:28.417200 <6>[ 4.996814] sdhci-pltfm: SDHCI platform and OF driver helper
10802 10:00:28.420449 <6>[ 4.996873] mmc0: CQHCI version 5.10
10803 10:00:28.427687 <6>[ 5.006703] ledtrig-cpu: registered to indicate activity on CPUs
10804 10:00:28.434015 <6>[ 5.013619] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10805 10:00:28.440466 <6>[ 5.020672] usbcore: registered new interface driver usbhid
10806 10:00:28.443776 <6>[ 5.026496] usbhid: USB HID core driver
10807 10:00:28.450424 <6>[ 5.030693] spi_master spi0: will run message pump with realtime priority
10808 10:00:28.495693 <6>[ 5.070685] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10809 10:00:28.514701 <6>[ 5.086237] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10810 10:00:28.521923 <6>[ 5.101248] cros-ec-spi spi0.0: Chrome EC device registered
10811 10:00:28.525378 <6>[ 5.107327] mmc0: Command Queue Engine enabled
10812 10:00:28.531739 <6>[ 5.112073] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10813 10:00:28.541935 <6>[ 5.119120] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10814 10:00:28.548515 <6>[ 5.119592] mmcblk0: mmc0:0001 DA4128 116 GiB
10815 10:00:28.551268 <6>[ 5.129519] NET: Registered PF_PACKET protocol family
10816 10:00:28.558656 <6>[ 5.137426] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10817 10:00:28.561421 <6>[ 5.138540] 9pnet: Installing 9P2000 support
10818 10:00:28.568238 <6>[ 5.145832] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10819 10:00:28.571587 <5>[ 5.148908] Key type dns_resolver registered
10820 10:00:28.578444 <6>[ 5.154755] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10821 10:00:28.581837 <6>[ 5.159175] registered taskstats version 1
10822 10:00:28.588064 <6>[ 5.164519] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10823 10:00:28.594492 <5>[ 5.168199] Loading compiled-in X.509 certificates
10824 10:00:28.610180 <4>[ 5.184939] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10825 10:00:28.619849 <4>[ 5.195653] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10826 10:00:28.626892 <3>[ 5.206197] debugfs: File 'uA_load' in directory '/' already present!
10827 10:00:28.633060 <3>[ 5.212895] debugfs: File 'min_uV' in directory '/' already present!
10828 10:00:28.639687 <3>[ 5.219502] debugfs: File 'max_uV' in directory '/' already present!
10829 10:00:28.646481 <3>[ 5.226109] debugfs: File 'constraint_flags' in directory '/' already present!
10830 10:00:28.657894 <3>[ 5.235851] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10831 10:00:28.667306 <6>[ 5.249165] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10832 10:00:28.674884 <6>[ 5.255935] xhci-mtk 11200000.usb: xHCI Host Controller
10833 10:00:28.680923 <6>[ 5.261434] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10834 10:00:28.691316 <6>[ 5.269386] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10835 10:00:28.698052 <6>[ 5.278850] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10836 10:00:28.704377 <6>[ 5.284944] xhci-mtk 11200000.usb: xHCI Host Controller
10837 10:00:28.711181 <6>[ 5.290435] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10838 10:00:28.717456 <6>[ 5.298098] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10839 10:00:28.724617 <6>[ 5.306064] hub 1-0:1.0: USB hub found
10840 10:00:28.727682 <6>[ 5.310101] hub 1-0:1.0: 1 port detected
10841 10:00:28.737763 <6>[ 5.314387] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10842 10:00:28.740988 <6>[ 5.323189] hub 2-0:1.0: USB hub found
10843 10:00:28.744598 <6>[ 5.327209] hub 2-0:1.0: 1 port detected
10844 10:00:28.754139 <6>[ 5.335423] mtk-msdc 11f70000.mmc: Got CD GPIO
10845 10:00:28.763977 <6>[ 5.341623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10846 10:00:28.770965 <6>[ 5.349655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10847 10:00:28.780580 <4>[ 5.357584] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10848 10:00:28.790670 <6>[ 5.367117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10849 10:00:28.797153 <6>[ 5.375194] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10850 10:00:28.803498 <6>[ 5.383214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10851 10:00:28.813880 <6>[ 5.391132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10852 10:00:28.820157 <6>[ 5.398949] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10853 10:00:28.829703 <6>[ 5.406767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10854 10:00:28.840475 <6>[ 5.417188] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10855 10:00:28.846850 <6>[ 5.425545] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10856 10:00:28.856503 <6>[ 5.433891] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10857 10:00:28.863309 <6>[ 5.442235] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10858 10:00:28.873189 <6>[ 5.450576] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10859 10:00:28.879660 <6>[ 5.458915] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10860 10:00:28.889639 <6>[ 5.467253] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10861 10:00:28.896348 <6>[ 5.475598] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10862 10:00:28.905854 <6>[ 5.483938] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10863 10:00:28.912354 <6>[ 5.492277] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10864 10:00:28.922231 <6>[ 5.500616] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10865 10:00:28.932526 <6>[ 5.508955] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10866 10:00:28.938831 <6>[ 5.517293] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10867 10:00:28.949186 <6>[ 5.525644] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10868 10:00:28.955656 <6>[ 5.533986] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10869 10:00:28.961844 <6>[ 5.542748] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10870 10:00:28.968493 <6>[ 5.549914] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10871 10:00:28.975171 <6>[ 5.556680] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10872 10:00:28.985378 <6>[ 5.563432] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10873 10:00:28.991944 <6>[ 5.570366] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10874 10:00:28.998471 <6>[ 5.577204] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10875 10:00:29.008410 <6>[ 5.586332] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10876 10:00:29.018451 <6>[ 5.595450] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10877 10:00:29.027930 <6>[ 5.604743] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10878 10:00:29.037907 <6>[ 5.614214] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10879 10:00:29.047757 <6>[ 5.623682] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10880 10:00:29.054629 <6>[ 5.632802] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10881 10:00:29.064625 <6>[ 5.642271] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10882 10:00:29.074683 <6>[ 5.651390] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10883 10:00:29.084244 <6>[ 5.660683] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10884 10:00:29.093835 <6>[ 5.670843] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10885 10:00:29.104105 <6>[ 5.682312] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10886 10:00:29.152678 <6>[ 5.730798] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10887 10:00:29.307247 <6>[ 5.888784] hub 1-1:1.0: USB hub found
10888 10:00:29.310532 <6>[ 5.893320] hub 1-1:1.0: 4 ports detected
10889 10:00:29.321138 <6>[ 5.902138] hub 1-1:1.0: USB hub found
10890 10:00:29.323999 <6>[ 5.906507] hub 1-1:1.0: 4 ports detected
10891 10:00:29.433115 <6>[ 6.011048] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10892 10:00:29.459493 <6>[ 6.040831] hub 2-1:1.0: USB hub found
10893 10:00:29.462706 <6>[ 6.045364] hub 2-1:1.0: 3 ports detected
10894 10:00:29.472054 <6>[ 6.053772] hub 2-1:1.0: USB hub found
10895 10:00:29.475435 <6>[ 6.058147] hub 2-1:1.0: 3 ports detected
10896 10:00:29.644695 <6>[ 6.222892] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10897 10:00:29.777303 <6>[ 6.358718] hub 1-1.4:1.0: USB hub found
10898 10:00:29.780286 <6>[ 6.363365] hub 1-1.4:1.0: 2 ports detected
10899 10:00:29.789364 <6>[ 6.370755] hub 1-1.4:1.0: USB hub found
10900 10:00:29.792844 <6>[ 6.375353] hub 1-1.4:1.0: 2 ports detected
10901 10:00:29.857184 <6>[ 6.435080] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10902 10:00:30.088476 <6>[ 6.666889] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10903 10:00:30.280449 <6>[ 6.858863] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10904 10:00:41.381997 <6>[ 17.967926] ALSA device list:
10905 10:00:41.388058 <6>[ 17.971223] No soundcards found.
10906 10:00:41.396458 <6>[ 17.979347] Freeing unused kernel memory: 8384K
10907 10:00:41.399660 <6>[ 17.984348] Run /init as init process
10908 10:00:41.449955 <6>[ 18.032761] NET: Registered PF_INET6 protocol family
10909 10:00:41.456960 <6>[ 18.038996] Segment Routing with IPv6
10910 10:00:41.459904 <6>[ 18.043022] In-situ OAM (IOAM) with IPv6
10911 10:00:41.493988 <30>[ 18.057121] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10912 10:00:41.497445 <30>[ 18.081030] systemd[1]: Detected architecture arm64.
10913 10:00:41.500648
10914 10:00:41.503664 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10915 10:00:41.503741
10916 10:00:41.520296 <30>[ 18.103016] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10917 10:00:41.662780 <30>[ 18.242033] systemd[1]: Queued start job for default target Graphical Interface.
10918 10:00:41.701147 <30>[ 18.283787] systemd[1]: Created slice system-getty.slice.
10919 10:00:41.707656 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10920 10:00:41.724750 <30>[ 18.307349] systemd[1]: Created slice system-modprobe.slice.
10921 10:00:41.731048 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10922 10:00:41.748857 <30>[ 18.331526] systemd[1]: Created slice system-serial\x2dgetty.slice.
10923 10:00:41.758516 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10924 10:00:41.772563 <30>[ 18.355212] systemd[1]: Created slice User and Session Slice.
10925 10:00:41.778747 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10926 10:00:41.799887 <30>[ 18.379471] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10927 10:00:41.810020 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10928 10:00:41.827757 <30>[ 18.407493] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10929 10:00:41.834571 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10930 10:00:41.858996 <30>[ 18.435387] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10931 10:00:41.865637 <30>[ 18.447694] systemd[1]: Reached target Local Encrypted Volumes.
10932 10:00:41.872282 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10933 10:00:41.888609 <30>[ 18.471424] systemd[1]: Reached target Paths.
10934 10:00:41.895416 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10935 10:00:41.908346 <30>[ 18.490864] systemd[1]: Reached target Remote File Systems.
10936 10:00:41.914814 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10937 10:00:41.932352 <30>[ 18.515234] systemd[1]: Reached target Slices.
10938 10:00:41.939416 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10939 10:00:41.952287 <30>[ 18.534929] systemd[1]: Reached target Swap.
10940 10:00:41.955313 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10941 10:00:41.975939 <30>[ 18.555392] systemd[1]: Listening on initctl Compatibility Named Pipe.
10942 10:00:41.982305 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10943 10:00:41.988965 <30>[ 18.570688] systemd[1]: Listening on Journal Audit Socket.
10944 10:00:41.995609 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10945 10:00:42.008495 <30>[ 18.591388] systemd[1]: Listening on Journal Socket (/dev/log).
10946 10:00:42.015048 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10947 10:00:42.033355 <30>[ 18.616181] systemd[1]: Listening on Journal Socket.
10948 10:00:42.039780 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10949 10:00:42.053180 <30>[ 18.635519] systemd[1]: Listening on udev Control Socket.
10950 10:00:42.058930 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10951 10:00:42.077131 <30>[ 18.659948] systemd[1]: Listening on udev Kernel Socket.
10952 10:00:42.084000 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10953 10:00:42.140224 <30>[ 18.723048] systemd[1]: Mounting Huge Pages File System...
10954 10:00:42.146552 Mounting [0;1;39mHuge Pages File System[0m...
10955 10:00:42.164274 <30>[ 18.747312] systemd[1]: Mounting POSIX Message Queue File System...
10956 10:00:42.170797 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10957 10:00:42.192658 <30>[ 18.775283] systemd[1]: Mounting Kernel Debug File System...
10958 10:00:42.198609 Mounting [0;1;39mKernel Debug File System[0m...
10959 10:00:42.215857 <30>[ 18.795386] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10960 10:00:42.263706 <30>[ 18.843380] systemd[1]: Starting Create list of static device nodes for the current kernel...
10961 10:00:42.270086 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10962 10:00:42.292817 <30>[ 18.875575] systemd[1]: Starting Load Kernel Module configfs...
10963 10:00:42.298961 Starting [0;1;39mLoad Kernel Module configfs[0m...
10964 10:00:42.314021 <30>[ 18.897177] systemd[1]: Starting Load Kernel Module drm...
10965 10:00:42.320733 Starting [0;1;39mLoad Kernel Module drm[0m...
10966 10:00:42.339413 <30>[ 18.919249] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10967 10:00:42.384620 <30>[ 18.967317] systemd[1]: Starting Journal Service...
10968 10:00:42.390876 Starting [0;1;39mJournal Service[0m...
10969 10:00:42.406896 <30>[ 18.989799] systemd[1]: Starting Load Kernel Modules...
10970 10:00:42.413156 Starting [0;1;39mLoad Kernel Modules[0m...
10971 10:00:42.433408 <30>[ 19.013396] systemd[1]: Starting Remount Root and Kernel File Systems...
10972 10:00:42.440773 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10973 10:00:42.459421 <30>[ 19.042413] systemd[1]: Starting Coldplug All udev Devices...
10974 10:00:42.465841 Starting [0;1;39mColdplug All udev Devices[0m...
10975 10:00:42.483103 <30>[ 19.066139] systemd[1]: Started Journal Service.
10976 10:00:42.490024 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10977 10:00:42.506014 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10978 10:00:42.524740 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10979 10:00:42.540704 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10980 10:00:42.561182 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10981 10:00:42.577881 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10982 10:00:42.597473 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10983 10:00:42.612544 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10984 10:00:42.632628 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10985 10:00:42.647597 See 'systemctl status systemd-remount-fs.service' for details.
10986 10:00:42.701279 Mounting [0;1;39mKernel Configuration File System[0m...
10987 10:00:42.724628 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10988 10:00:42.745882 <46>[ 19.325598] systemd-journald[179]: Received client request to flush runtime journal.
10989 10:00:42.752199 Starting [0;1;39mLoad/Save Random Seed[0m...
10990 10:00:42.769100 Starting [0;1;39mApply Kernel Variables[0m...
10991 10:00:42.790387 Starting [0;1;39mCreate System Users[0m...
10992 10:00:42.810013 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10993 10:00:42.829349 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10994 10:00:42.849187 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10995 10:00:42.862150 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10996 10:00:42.881886 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10997 10:00:42.901922 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10998 10:00:42.948901 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10999 10:00:42.968571 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11000 10:00:42.984603 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11001 10:00:43.003627 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11002 10:00:43.040306 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11003 10:00:43.064970 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11004 10:00:43.085231 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11005 10:00:43.106769 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11006 10:00:43.151135 Starting [0;1;39mNetwork Time Synchronization[0m...
11007 10:00:43.170600 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11008 10:00:43.221146 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11009 10:00:43.248772 <6>[ 19.828164] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11010 10:00:43.254968 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11011 10:00:43.279163 [[0;32m OK [0m] Finished [0<6>[ 19.861563] remoteproc remoteproc0: scp is available
11012 10:00:43.285937 ;1;39mUpdate UTM<6>[ 19.867312] remoteproc remoteproc0: powering up scp
11013 10:00:43.295791 P about System B<6>[ 19.873805] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11014 10:00:43.302233 oot/Shutdown[0m<6>[ 19.883540] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11015 10:00:43.302389 .
11016 10:00:43.314483 <6>[ 19.894415] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11017 10:00:43.321665 <4>[ 19.895553] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11018 10:00:43.327733 <3>[ 19.896532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 10:00:43.338101 <3>[ 19.896561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11020 10:00:43.344193 <3>[ 19.896583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11021 10:00:43.354514 <3>[ 19.899388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11022 10:00:43.360889 <3>[ 19.899398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11023 10:00:43.370828 <3>[ 19.899402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11024 10:00:43.377629 <3>[ 19.899406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11025 10:00:43.387401 <3>[ 19.899409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11026 10:00:43.393967 <3>[ 19.899443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11027 10:00:43.400360 <3>[ 19.899469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11028 10:00:43.410407 <3>[ 19.899471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11029 10:00:43.417119 <3>[ 19.899474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11030 10:00:43.426872 <3>[ 19.899498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11031 10:00:43.433506 <3>[ 19.899501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11032 10:00:43.443595 <3>[ 19.899504] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11033 10:00:43.449891 <3>[ 19.899506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11034 10:00:43.460323 <3>[ 19.899509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11035 10:00:43.467085 <3>[ 19.899521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11036 10:00:43.477040 <6>[ 19.902428] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11037 10:00:43.483834 <4>[ 19.925960] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11038 10:00:43.493281 <6>[ 19.933666] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11039 10:00:43.496508 <6>[ 19.937015] usbcore: registered new interface driver r8152
11040 10:00:43.503347 <6>[ 19.990369] mc: Linux media interface: v0.10
11041 10:00:43.510568 <6>[ 20.008061] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11042 10:00:43.520631 <6>[ 20.016106] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11043 10:00:43.527321 <6>[ 20.022787] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11044 10:00:43.533971 <6>[ 20.022800] remoteproc remoteproc0: remote processor scp is now up
11045 10:00:43.540582 <6>[ 20.047514] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11046 10:00:43.546799 <6>[ 20.056714] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11047 10:00:43.556579 <6>[ 20.059499] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11048 10:00:43.563384 <4>[ 20.064632] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11049 10:00:43.570155 <4>[ 20.064632] Fallback method does not support PEC.
11050 10:00:43.580047 <6>[ 20.067558] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11051 10:00:43.589615 <6>[ 20.068616] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11052 10:00:43.593132 <6>[ 20.088033] pci_bus 0000:00: root bus resource [bus 00-ff]
11053 10:00:43.599867 <6>[ 20.096351] videodev: Linux video capture interface: v2.00
11054 10:00:43.606929 <6>[ 20.099227] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11055 10:00:43.617150 <4>[ 20.103451] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11056 10:00:43.624219 <4>[ 20.103464] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11057 10:00:43.633465 <3>[ 20.115600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 10:00:43.643879 <6>[ 20.121382] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11059 10:00:43.650783 <6>[ 20.121442] usbcore: registered new interface driver cdc_ether
11060 10:00:43.654145 <6>[ 20.132042] usbcore: registered new interface driver r8153_ecm
11061 10:00:43.661296 <6>[ 20.138707] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11062 10:00:43.665001 <6>[ 20.159079] Bluetooth: Core ver 2.22
11063 10:00:43.674389 <6>[ 20.159661] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11064 10:00:43.681461 <6>[ 20.161988] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11065 10:00:43.687877 <6>[ 20.166670] r8152 2-1.3:1.0 eth0: v1.12.13
11066 10:00:43.694869 <6>[ 20.168412] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11067 10:00:43.701948 <6>[ 20.177092] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11068 10:00:43.705447 <6>[ 20.177322] NET: Registered PF_BLUETOOTH protocol family
11069 10:00:43.711749 <6>[ 20.183031] pci 0000:00:00.0: supports D1 D2
11070 10:00:43.715373 <6>[ 20.188692] Bluetooth: HCI device and connection manager initialized
11071 10:00:43.721887 <6>[ 20.195817] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11072 10:00:43.732159 <6>[ 20.196623] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11073 10:00:43.743172 <6>[ 20.197738] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11074 10:00:43.749716 <6>[ 20.197861] usbcore: registered new interface driver uvcvideo
11075 10:00:43.759676 <3>[ 20.203020] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11076 10:00:43.766148 <3>[ 20.203717] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11077 10:00:43.773226 <6>[ 20.204870] Bluetooth: HCI socket layer initialized
11078 10:00:43.779109 <6>[ 20.214184] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11079 10:00:43.786516 <6>[ 20.221703] Bluetooth: L2CAP socket layer initialized
11080 10:00:43.789905 <6>[ 20.221719] Bluetooth: SCO socket layer initialized
11081 10:00:43.796569 <6>[ 20.222266] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11082 10:00:43.803278 <6>[ 20.231726] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11083 10:00:43.813541 <3>[ 20.237178] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11084 10:00:43.820555 <3>[ 20.237923] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11085 10:00:43.830582 <6>[ 20.243797] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11086 10:00:43.837456 <3>[ 20.251164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11087 10:00:43.844172 <6>[ 20.253881] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11088 10:00:43.850718 <6>[ 20.282753] usbcore: registered new interface driver btusb
11089 10:00:43.861203 <4>[ 20.283645] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11090 10:00:43.868389 <3>[ 20.283661] Bluetooth: hci0: Failed to load firmware file (-2)
11091 10:00:43.874847 <3>[ 20.283668] Bluetooth: hci0: Failed to set up firmware (-2)
11092 10:00:43.885553 <4>[ 20.283675] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11093 10:00:43.891755 <3>[ 20.283877] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11094 10:00:43.898568 <6>[ 20.288313] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11095 10:00:43.908189 <3>[ 20.304540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11096 10:00:43.911432 <6>[ 20.305087] pci 0000:01:00.0: supports D1 D2
11097 10:00:43.921333 <3>[ 20.331949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11098 10:00:43.928293 <6>[ 20.337282] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11099 10:00:43.934969 <6>[ 20.350697] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11100 10:00:43.944575 <3>[ 20.375032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11101 10:00:43.951550 <6>[ 20.379095] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11102 10:00:43.961233 <6>[ 20.540491] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11103 10:00:43.967822 <6>[ 20.540500] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11104 10:00:43.977768 <6>[ 20.540513] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11105 10:00:43.984247 <6>[ 20.540525] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11106 10:00:43.990796 <6>[ 20.540537] pci 0000:00:00.0: PCI bridge to [bus 01]
11107 10:00:43.997841 <6>[ 20.540542] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11108 10:00:44.003989 <6>[ 20.540706] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11109 10:00:44.010573 [[0;32m OK [<6>[ 20.592668] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11110 10:00:44.017969 0m] Created slic<6>[ 20.600460] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11111 10:00:44.023863 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11112 10:00:44.038367 <5>[ 20.618322] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11113 10:00:44.045192 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11114 10:00:44.061963 <5>[ 20.641598] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11115 10:00:44.068117 <4>[ 20.648516] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11116 10:00:44.074832 <6>[ 20.657426] cfg80211: failed to load regulatory.db
11117 10:00:44.081499 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11118 10:00:44.125555 <6>[ 20.705268] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11119 10:00:44.131832 <6>[ 20.712794] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11120 10:00:44.148532 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11121 10:00:44.156931 <6>[ 20.739508] mt7921e 0000:01:00.0: ASIC revision: 79610010
11122 10:00:44.173862 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11123 10:00:44.262506 <4>[ 20.839180] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11124 10:00:44.331081 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11125 10:00:44.343503 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11126 10:00:44.367570 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11127 10:00:44.383100 <4>[ 20.959971] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11128 10:00:44.390030 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11129 10:00:44.408068 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11130 10:00:44.427836 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11131 10:00:44.439671 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11132 10:00:44.456436 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11133 10:00:44.479938 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11134 10:00:44.507103 <4>[ 21.083729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11135 10:00:44.536524 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11136 10:00:44.573182 Starting [0;1;39mUser Login Management[0m...
11137 10:00:44.592679 Starting [0;1;39mPermit User Sessions[0m...
11138 10:00:44.617582 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11139 10:00:44.630703 <4>[ 21.207009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11140 10:00:44.708598 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11141 10:00:44.727736 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11142 10:00:44.754859 [[0;32m OK [0m] Reached target [0;1;39mLogi<4>[ 21.331876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11143 10:00:44.757950 n Prompts[0m.
11144 10:00:44.780423 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11145 10:00:44.797674 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11146 10:00:44.818959 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11147 10:00:44.838062 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11148 10:00:44.856765 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11149 10:00:44.879138 <4>[ 21.456041] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11150 10:00:44.902738 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11151 10:00:44.933403 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11152 10:00:44.950072
11153 10:00:44.950179
11154 10:00:44.953779 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11155 10:00:44.953882
11156 10:00:44.957213 debian-bullseye-arm64 login: root (automatic login)
11157 10:00:44.957312
11158 10:00:44.957403
11159 10:00:44.973684 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11160 10:00:44.973762
11161 10:00:44.980105 The programs included with the Debian GNU/Linux system are free software;
11162 10:00:44.986888 the exact distribution terms for each program are described in the
11163 10:00:44.990053 individual files in /usr/share/doc/*/copyright.
11164 10:00:44.990154
11165 10:00:45.003340 Debian GNU/Linux comes with ABS<4>[ 21.580995] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11166 10:00:45.006749 OLUTELY NO WARRANTY, to the extent
11167 10:00:45.010061 permitted by applicable law.
11168 10:00:45.010431 Matched prompt #10: / #
11170 10:00:45.010636 Setting prompt string to ['/ #']
11171 10:00:45.010730 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11173 10:00:45.010927 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11174 10:00:45.011012 start: 2.2.6 expect-shell-connection (timeout 00:01:52) [common]
11175 10:00:45.011080 Setting prompt string to ['/ #']
11176 10:00:45.011145 Forcing a shell prompt, looking for ['/ #']
11178 10:00:45.061331 / #
11179 10:00:45.061467 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11180 10:00:45.061554 Waiting using forced prompt support (timeout 00:02:30)
11181 10:00:45.066173
11182 10:00:45.066472 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11183 10:00:45.066589 start: 2.2.7 export-device-env (timeout 00:01:52) [common]
11184 10:00:45.066687 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11185 10:00:45.066789 end: 2.2 depthcharge-retry (duration 00:03:08) [common]
11186 10:00:45.066880 end: 2 depthcharge-action (duration 00:03:08) [common]
11187 10:00:45.066967 start: 3 lava-test-retry (timeout 00:05:00) [common]
11188 10:00:45.067064 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11189 10:00:45.067140 Using namespace: common
11191 10:00:45.167408 / # #
11192 10:00:45.167560 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11193 10:00:45.167709 <4>[ 21.703937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11194 10:00:45.172892 #
11195 10:00:45.173150 Using /lava-12073287
11197 10:00:45.273478 / # export SHELL=/bin/sh
11198 10:00:45.273676 export SHELL=/bin/sh<4>[ 21.827731] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11199 10:00:45.278432
11201 10:00:45.378882 / # . /lava-12073287/environment
11202 10:00:45.379046 . /lava-12073287/environment<4>[ 21.951777] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11203 10:00:45.384125
11205 10:00:45.484642 / # /lava-12073287/bin/lava-test-runner /lava-12073287/0
11206 10:00:45.484793 Test shell timeout: 10s (minimum of the action and connection timeout)
11207 10:00:45.490201 /lava-12073287/bin/lava-test-runner /lava-12073287/0<3>[ 22.073807] mt7921e 0000:01:00.0: hardware init failed
11208 10:00:45.490338
11209 10:00:45.513803 + export TESTRUN_ID=0_sleep
11210 10:00:45.517479 + cd /lava-12073287/0/tests/0_sleep
11211 10:00:45.520815 + cat uuid
11212 10:00:45.520888 + UUID=12073287_1.5.2.3.1
11213 10:00:45.523860 + set +x
11214 10:00:45.527042 <LAVA_SIGNAL_STARTRUN 0_sleep 12073287_1.5.2.3.1>
11215 10:00:45.527296 Received signal: <STARTRUN> 0_sleep 12073287_1.5.2.3.1
11216 10:00:45.527398 Starting test lava.0_sleep (12073287_1.5.2.3.1)
11217 10:00:45.527512 Skipping test definition patterns.
11218 10:00:45.530315 + ./config/lava/sleep/sleep.sh mem freeze
11219 10:00:45.536978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11220 10:00:45.537252 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11222 10:00:45.540259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11223 10:00:45.540504 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11225 10:00:45.543810 rtcwake: assuming RTC uses UTC ...
11226 10:00:45.553463 rtcwake: wakeup from "mem" using rtc0 at Fri<6>[ 22.136101] PM: suspend entry (deep)
11227 10:00:45.556635 Nov 24 10:00:53<6>[ 22.140746] Filesystems sync: 0.000 seconds
11228 10:00:45.560286 2023
11229 10:00:45.563254 <6>[ 22.148371] Freezing user space processes
11230 10:00:45.574061 <6>[ 22.154174] Freezing user space processes completed (elapsed 0.001 seconds)
11231 10:00:45.577219 <6>[ 22.161470] OOM killer disabled.
11232 10:00:45.580764 <6>[ 22.164954] Freezing remaining freezable tasks
11233 10:00:45.590435 <6>[ 22.170589] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11234 10:00:45.597040 <6>[ 22.178242] printk: Suspending console(s) (use no_console_suspend to debug)
11235 10:00:49.066072 <3>[ 25.422881] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11236 10:00:49.075375 <3>[ 25.422914] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11237 10:00:49.085621 <3>[ 25.422961] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11238 10:00:49.092244 <3>[ 25.423006] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11239 10:00:49.101749 <3>[ 25.423383] PM: Some devices failed to suspend, or early wake event detected
11240 10:00:49.108588 <4>[ 25.440439] typec port0-partner: PM: parent port0 should not be sleeping
11241 10:00:49.111888 <6>[ 25.695858] OOM killer enabled.
11242 10:00:49.124236 <6>[ 25.699273] Restarting tasks ... done.
11243 10:00:49.128002 <5>[ 25.711644] random: crng reseeded on system resumption
11244 10:00:49.131863 <6>[ 25.718325] PM: suspend exit
11245 10:00:49.135227 rtcwake: write error
11246 10:00:49.143605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11247 10:00:49.144558 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11249 10:00:49.146104 rtcwake: assuming RTC uses UTC ...
11250 10:00:49.152623 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:00:57 2023
11251 10:00:49.165841 <6>[ 25.748544] PM: suspend entry (deep)
11252 10:00:49.168927 <6>[ 25.752439] Filesystems sync: 0.000 seconds
11253 10:00:49.171817 <6>[ 25.757422] Freezing user space processes
11254 10:00:49.183892 <6>[ 25.763365] Freezing user space processes completed (elapsed 0.001 seconds)
11255 10:00:49.186754 <6>[ 25.770585] OOM killer disabled.
11256 10:00:49.190205 <6>[ 25.774061] Freezing remaining freezable tasks
11257 10:00:49.200112 <6>[ 25.780316] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11258 10:00:49.206876 <6>[ 25.787998] printk: Suspending console(s) (use no_console_suspend to debug)
11259 10:00:52.649189 <3>[ 29.006948] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11260 10:00:52.659485 <3>[ 29.006985] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11261 10:00:52.669305 <3>[ 29.007036] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11262 10:00:52.675654 <3>[ 29.007084] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11263 10:00:52.685532 <3>[ 29.007317] PM: Some devices failed to suspend, or early wake event detected
11264 10:00:52.688787 <6>[ 29.272896] OOM killer enabled.
11265 10:00:52.698361 <6>[ 29.276313] Restarting tasks ... done.
11266 10:00:52.701697 <5>[ 29.286222] random: crng reseeded on system resumption
11267 10:00:52.706003 <6>[ 29.292812] PM: suspend exit
11268 10:00:52.708725 rtcwake: write error
11269 10:00:52.716133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11270 10:00:52.717121 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11272 10:00:52.719426 rtcwake: assuming RTC uses UTC ...
11273 10:00:52.726034 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:01 2023
11274 10:00:52.741134 <6>[ 29.324588] PM: suspend entry (deep)
11275 10:00:52.744403 <6>[ 29.328504] Filesystems sync: 0.000 seconds
11276 10:00:52.750617 <6>[ 29.333690] Freezing user space processes
11277 10:00:52.757744 <6>[ 29.339940] Freezing user space processes completed (elapsed 0.001 seconds)
11278 10:00:52.761133 <6>[ 29.347175] OOM killer disabled.
11279 10:00:52.767179 <6>[ 29.350663] Freezing remaining freezable tasks
11280 10:00:52.777042 <6>[ 29.356678] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11281 10:00:52.783709 <6>[ 29.364348] printk: Suspending console(s) (use no_console_suspend to debug)
11282 10:00:56.240429 <3>[ 32.590842] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11283 10:00:56.250746 <3>[ 32.590868] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11284 10:00:56.260270 <3>[ 32.590899] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11285 10:00:56.267347 <3>[ 32.590930] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11286 10:00:56.277040 <3>[ 32.591182] PM: Some devices failed to suspend, or early wake event detected
11287 10:00:56.280320 <6>[ 32.864588] OOM killer enabled.
11288 10:00:56.283771 <6>[ 32.868004] Restarting tasks ... done.
11289 10:00:56.290677 <5>[ 32.874248] random: crng reseeded on system resumption
11290 10:00:56.293250 <6>[ 32.880930] PM: suspend exit
11291 10:00:56.296733 rtcwake: write error
11292 10:00:56.303751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11293 10:00:56.304568 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11295 10:00:56.307194 rtcwake: assuming RTC uses UTC ...
11296 10:00:56.313705 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:04 2023
11297 10:00:56.327254 <6>[ 32.911348] PM: suspend entry (deep)
11298 10:00:56.330360 <6>[ 32.915260] Filesystems sync: 0.000 seconds
11299 10:00:56.337048 <6>[ 32.920428] Freezing user space processes
11300 10:00:56.344027 <6>[ 32.926697] Freezing user space processes completed (elapsed 0.001 seconds)
11301 10:00:56.347093 <6>[ 32.933999] OOM killer disabled.
11302 10:00:56.353690 <6>[ 32.937497] Freezing remaining freezable tasks
11303 10:00:56.360657 <6>[ 32.943494] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11304 10:00:56.369839 <6>[ 32.951155] printk: Suspending console(s) (use no_console_suspend to debug)
11305 10:00:59.823603 <3>[ 36.174967] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11306 10:00:59.833820 <3>[ 36.175040] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11307 10:00:59.843761 <3>[ 36.175109] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11308 10:00:59.850330 <3>[ 36.175133] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11309 10:00:59.856914 <3>[ 36.175316] PM: Some devices failed to suspend, or early wake event detected
11310 10:00:59.863319 <6>[ 36.448422] OOM killer enabled.
11311 10:00:59.866421 <6>[ 36.451834] Restarting tasks ... done.
11312 10:00:59.873206 <5>[ 36.457989] random: crng reseeded on system resumption
11313 10:00:59.876884 <6>[ 36.464974] PM: suspend exit
11314 10:00:59.880114 rtcwake: write error
11315 10:00:59.886752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11316 10:00:59.887062 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11318 10:00:59.890166 rtcwake: assuming RTC uses UTC ...
11319 10:00:59.896972 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:08 2023
11320 10:00:59.909158 <6>[ 36.494189] PM: suspend entry (deep)
11321 10:00:59.912482 <6>[ 36.498081] Filesystems sync: 0.000 seconds
11322 10:00:59.919239 <6>[ 36.503239] Freezing user space processes
11323 10:00:59.926612 <6>[ 36.509284] Freezing user space processes completed (elapsed 0.001 seconds)
11324 10:00:59.929356 <6>[ 36.516526] OOM killer disabled.
11325 10:00:59.936027 <6>[ 36.520007] Freezing remaining freezable tasks
11326 10:00:59.942649 <6>[ 36.526072] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11327 10:00:59.952560 <6>[ 36.533743] printk: Suspending console(s) (use no_console_suspend to debug)
11328 10:01:03.408266 <3>[ 39.758897] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11329 10:01:03.421471 <3>[ 39.758931] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11330 10:01:03.428115 <3>[ 39.758979] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11331 10:01:03.434874 <3>[ 39.759027] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11332 10:01:03.444925 <3>[ 39.759613] PM: Some devices failed to suspend, or early wake event detected
11333 10:01:03.448217 <6>[ 40.033153] OOM killer enabled.
11334 10:01:03.451579 <6>[ 40.036568] Restarting tasks ... done.
11335 10:01:03.458183 <5>[ 40.042703] random: crng reseeded on system resumption
11336 10:01:03.461660 <6>[ 40.049448] PM: suspend exit
11337 10:01:03.464362 rtcwake: write error
11338 10:01:03.471522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11339 10:01:03.472355 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11341 10:01:03.475116 rtcwake: assuming RTC uses UTC ...
11342 10:01:03.481614 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:11 2023
11343 10:01:03.494469 <6>[ 40.078894] PM: suspend entry (deep)
11344 10:01:03.497708 <6>[ 40.082794] Filesystems sync: 0.000 seconds
11345 10:01:03.500435 <6>[ 40.087831] Freezing user space processes
11346 10:01:03.512431 <6>[ 40.093811] Freezing user space processes completed (elapsed 0.001 seconds)
11347 10:01:03.515563 <6>[ 40.101056] OOM killer disabled.
11348 10:01:03.519084 <6>[ 40.104539] Freezing remaining freezable tasks
11349 10:01:03.529064 <6>[ 40.110608] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11350 10:01:03.536061 <6>[ 40.118267] printk: Suspending console(s) (use no_console_suspend to debug)
11351 10:01:06.991654 <3>[ 43.342951] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11352 10:01:07.005046 <3>[ 43.342989] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11353 10:01:07.011771 <3>[ 43.343040] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11354 10:01:07.018444 <3>[ 43.343083] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11355 10:01:07.028516 <3>[ 43.343358] PM: Some devices failed to suspend, or early wake event detected
11356 10:01:07.031648 <6>[ 43.617094] OOM killer enabled.
11357 10:01:07.043455 <6>[ 43.620508] Restarting tasks ... done.
11358 10:01:07.046530 <5>[ 43.632880] random: crng reseeded on system resumption
11359 10:01:07.051460 <6>[ 43.639911] PM: suspend exit
11360 10:01:07.054591 rtcwake: write error
11361 10:01:07.061629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11362 10:01:07.062366 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11364 10:01:07.065705 rtcwake: assuming RTC uses UTC ...
11365 10:01:07.071827 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:15 2023
11366 10:01:07.084581 <6>[ 43.669481] PM: suspend entry (deep)
11367 10:01:07.087657 <6>[ 43.673390] Filesystems sync: 0.000 seconds
11368 10:01:07.091187 <6>[ 43.678371] Freezing user space processes
11369 10:01:07.102219 <6>[ 43.684499] Freezing user space processes completed (elapsed 0.001 seconds)
11370 10:01:07.106030 <6>[ 43.691737] OOM killer disabled.
11371 10:01:07.109080 <6>[ 43.695219] Freezing remaining freezable tasks
11372 10:01:07.119371 <6>[ 43.701268] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11373 10:01:07.125918 <6>[ 43.708944] printk: Suspending console(s) (use no_console_suspend to debug)
11374 10:01:10.567438 <3>[ 46.926895] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11375 10:01:10.577559 <3>[ 46.926929] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11376 10:01:10.587262 <3>[ 46.926976] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11377 10:01:10.593855 <3>[ 46.927025] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11378 10:01:10.603908 <3>[ 46.927221] PM: Some devices failed to suspend, or early wake event detected
11379 10:01:10.607141 <6>[ 47.193144] OOM killer enabled.
11380 10:01:10.613463 <6>[ 47.196556] Restarting tasks ... done.
11381 10:01:10.616815 <5>[ 47.202986] random: crng reseeded on system resumption
11382 10:01:10.620646 <6>[ 47.209934] PM: suspend exit
11383 10:01:10.624145 rtcwake: write error
11384 10:01:10.631369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11385 10:01:10.632083 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11387 10:01:10.634863 rtcwake: assuming RTC uses UTC ...
11388 10:01:10.640977 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:19 2023
11389 10:01:10.656048 <6>[ 47.242066] PM: suspend entry (deep)
11390 10:01:10.659346 <6>[ 47.245992] Filesystems sync: 0.000 seconds
11391 10:01:10.666152 <6>[ 47.251278] Freezing user space processes
11392 10:01:10.672738 <6>[ 47.257453] Freezing user space processes completed (elapsed 0.001 seconds)
11393 10:01:10.675846 <6>[ 47.264782] OOM killer disabled.
11394 10:01:10.682928 <6>[ 47.268279] Freezing remaining freezable tasks
11395 10:01:10.692673 <6>[ 47.274380] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11396 10:01:10.699497 <6>[ 47.282093] printk: Suspending console(s) (use no_console_suspend to debug)
11397 10:01:14.150777 <6>[ 48.206932] vpu: disabling
11398 10:01:14.153840 <6>[ 48.207041] vproc2: disabling
11399 10:01:14.157222 <6>[ 48.207085] vproc1: disabling
11400 10:01:14.160596 <6>[ 48.207127] vaud18: disabling
11401 10:01:14.163848 <6>[ 48.207320] vsram_others: disabling
11402 10:01:14.167478 <6>[ 48.207474] va09: disabling
11403 10:01:14.170510 <6>[ 48.207534] vsram_md: disabling
11404 10:01:14.173818 <6>[ 48.207637] Vgpu: disabling
11405 10:01:14.180513 <3>[ 50.510887] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11406 10:01:14.190643 <3>[ 50.510931] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11407 10:01:14.201147 <3>[ 50.510970] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11408 10:01:14.207189 <3>[ 50.511001] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11409 10:01:14.213967 <3>[ 50.511205] PM: Some devices failed to suspend, or early wake event detected
11410 10:01:14.217315 <6>[ 50.806424] OOM killer enabled.
11411 10:01:14.225369 <6>[ 50.809832] Restarting tasks ... done.
11412 10:01:14.232104 <5>[ 50.816599] random: crng reseeded on system resumption
11413 10:01:14.235313 <6>[ 50.824187] PM: suspend exit
11414 10:01:14.238631 rtcwake: write error
11415 10:01:14.245301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11416 10:01:14.246136 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11418 10:01:14.248673 rtcwake: assuming RTC uses UTC ...
11419 10:01:14.255135 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:22 2023
11420 10:01:14.267763 <6>[ 50.853410] PM: suspend entry (deep)
11421 10:01:14.270873 <6>[ 50.857321] Filesystems sync: 0.000 seconds
11422 10:01:14.274411 <6>[ 50.862355] Freezing user space processes
11423 10:01:14.285501 <6>[ 50.868398] Freezing user space processes completed (elapsed 0.001 seconds)
11424 10:01:14.289018 <6>[ 50.875630] OOM killer disabled.
11425 10:01:14.292434 <6>[ 50.879110] Freezing remaining freezable tasks
11426 10:01:14.302883 <6>[ 50.885178] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11427 10:01:14.308955 <6>[ 50.892852] printk: Suspending console(s) (use no_console_suspend to debug)
11428 10:01:17.742630 <3>[ 54.094876] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11429 10:01:17.755520 <3>[ 54.094908] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11430 10:01:17.762330 <3>[ 54.094957] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11431 10:01:17.768999 <3>[ 54.095002] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11432 10:01:17.778707 <3>[ 54.095316] PM: Some devices failed to suspend, or early wake event detected
11433 10:01:17.782153 <6>[ 54.368969] OOM killer enabled.
11434 10:01:17.785564 <6>[ 54.372382] Restarting tasks ... done.
11435 10:01:17.791750 <5>[ 54.378339] random: crng reseeded on system resumption
11436 10:01:17.795080 <6>[ 54.385162] PM: suspend exit
11437 10:01:17.798666 rtcwake: write error
11438 10:01:17.806031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11439 10:01:17.806933 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11441 10:01:17.808870 rtcwake: assuming RTC uses UTC ...
11442 10:01:17.815346 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 10:01:26 2023
11443 10:01:17.827589 <6>[ 54.414413] PM: suspend entry (deep)
11444 10:01:17.831355 <6>[ 54.418307] Filesystems sync: 0.000 seconds
11445 10:01:17.834875 <6>[ 54.423339] Freezing user space processes
11446 10:01:17.845889 <6>[ 54.429194] Freezing user space processes completed (elapsed 0.001 seconds)
11447 10:01:17.849044 <6>[ 54.436420] OOM killer disabled.
11448 10:01:17.852829 <6>[ 54.439901] Freezing remaining freezable tasks
11449 10:01:17.863051 <6>[ 54.446010] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11450 10:01:17.869986 <6>[ 54.453680] printk: Suspending console(s) (use no_console_suspend to debug)
11451 10:01:21.325908 <3>[ 57.678884] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11452 10:01:21.339391 <3>[ 57.678918] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11453 10:01:21.346580 <3>[ 57.678964] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11454 10:01:21.352949 <3>[ 57.679009] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11455 10:01:21.362826 <3>[ 57.679261] PM: Some devices failed to suspend, or early wake event detected
11456 10:01:21.365884 <6>[ 57.953135] OOM killer enabled.
11457 10:01:21.369268 <6>[ 57.956555] Restarting tasks ... done.
11458 10:01:21.376219 <5>[ 57.962640] random: crng reseeded on system resumption
11459 10:01:21.379681 <6>[ 57.969417] PM: suspend exit
11460 10:01:21.382601 rtcwake: write error
11461 10:01:21.389596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11462 10:01:21.390330 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11464 10:01:21.393023 rtcwake: assuming RTC uses UTC ...
11465 10:01:21.399136 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:29 2023
11466 10:01:21.413300 <6>[ 58.000331] PM: suspend entry (s2idle)
11467 10:01:21.417015 <6>[ 58.004419] Filesystems sync: 0.000 seconds
11468 10:01:21.423258 <6>[ 58.009496] Freezing user space processes
11469 10:01:21.429783 <6>[ 58.015318] Freezing user space processes completed (elapsed 0.001 seconds)
11470 10:01:21.433169 <6>[ 58.022538] OOM killer disabled.
11471 10:01:21.439868 <6>[ 58.026016] Freezing remaining freezable tasks
11472 10:01:21.446545 <6>[ 58.032056] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11473 10:01:21.456672 <6>[ 58.039724] printk: Suspending console(s) (use no_console_suspend to debug)
11474 10:01:24.910347 <3>[ 61.262921] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11475 10:01:24.920072 <3>[ 61.262955] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11476 10:01:24.929680 <3>[ 61.263003] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11477 10:01:24.936582 <3>[ 61.263048] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11478 10:01:24.946533 <3>[ 61.263302] PM: Some devices failed to suspend, or early wake event detected
11479 10:01:24.949854 <6>[ 61.537093] OOM killer enabled.
11480 10:01:24.956251 <6>[ 61.540506] Restarting tasks ... done.
11481 10:01:24.959468 <5>[ 61.547740] random: crng reseeded on system resumption
11482 10:01:24.964004 <6>[ 61.554666] PM: suspend exit
11483 10:01:24.966845 rtcwake: write error
11484 10:01:24.974303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11485 10:01:24.975308 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11487 10:01:24.978014 rtcwake: assuming RTC uses UTC ...
11488 10:01:24.984282 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:33 2023
11489 10:01:24.996887 <6>[ 61.583864] PM: suspend entry (s2idle)
11490 10:01:24.999685 <6>[ 61.587927] Filesystems sync: 0.000 seconds
11491 10:01:25.006416 <6>[ 61.592957] Freezing user space processes
11492 10:01:25.013364 <6>[ 61.598896] Freezing user space processes completed (elapsed 0.001 seconds)
11493 10:01:25.016030 <6>[ 61.606125] OOM killer disabled.
11494 10:01:25.023453 <6>[ 61.609604] Freezing remaining freezable tasks
11495 10:01:25.029373 <6>[ 61.615707] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11496 10:01:25.039994 <6>[ 61.623379] printk: Suspending console(s) (use no_console_suspend to debug)
11497 10:01:28.493792 <3>[ 64.846885] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11498 10:01:28.503494 <3>[ 64.846918] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11499 10:01:28.513743 <3>[ 64.846966] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11500 10:01:28.520716 <3>[ 64.847014] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11501 10:01:28.526331 <3>[ 64.847272] PM: Some devices failed to suspend, or early wake event detected
11502 10:01:28.533660 <6>[ 65.121123] OOM killer enabled.
11503 10:01:28.540188 <6>[ 65.124536] Restarting tasks ... done.
11504 10:01:28.543666 <5>[ 65.131974] random: crng reseeded on system resumption
11505 10:01:28.548152 <6>[ 65.139567] PM: suspend exit
11506 10:01:28.551620 rtcwake: write error
11507 10:01:28.558663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11508 10:01:28.559360 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11510 10:01:28.561968 rtcwake: assuming RTC uses UTC ...
11511 10:01:28.569266 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:36 2023
11512 10:01:28.581142 <6>[ 65.168736] PM: suspend entry (s2idle)
11513 10:01:28.585106 <6>[ 65.172862] Filesystems sync: 0.000 seconds
11514 10:01:28.591388 <6>[ 65.177840] Freezing user space processes
11515 10:01:28.597575 <6>[ 65.183758] Freezing user space processes completed (elapsed 0.001 seconds)
11516 10:01:28.601137 <6>[ 65.191012] OOM killer disabled.
11517 10:01:28.607513 <6>[ 65.194490] Freezing remaining freezable tasks
11518 10:01:28.614231 <6>[ 65.200604] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11519 10:01:28.624194 <6>[ 65.208284] printk: Suspending console(s) (use no_console_suspend to debug)
11520 10:01:32.077117 <3>[ 68.430882] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11521 10:01:32.086862 <3>[ 68.430915] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11522 10:01:32.097337 <3>[ 68.430963] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11523 10:01:32.103616 <3>[ 68.431012] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11524 10:01:32.113980 <3>[ 68.431209] PM: Some devices failed to suspend, or early wake event detected
11525 10:01:32.116802 <6>[ 68.705077] OOM killer enabled.
11526 10:01:32.123615 <6>[ 68.708491] Restarting tasks ... done.
11527 10:01:32.126717 <5>[ 68.715525] random: crng reseeded on system resumption
11528 10:01:32.130674 <6>[ 68.722184] PM: suspend exit
11529 10:01:32.134336 rtcwake: write error
11530 10:01:32.141007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11531 10:01:32.141806 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11533 10:01:32.144599 rtcwake: assuming RTC uses UTC ...
11534 10:01:32.151060 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:40 2023
11535 10:01:32.163332 <6>[ 68.751293] PM: suspend entry (s2idle)
11536 10:01:32.166622 <6>[ 68.755360] Filesystems sync: 0.000 seconds
11537 10:01:32.172939 <6>[ 68.760402] Freezing user space processes
11538 10:01:32.179542 <6>[ 68.766335] Freezing user space processes completed (elapsed 0.001 seconds)
11539 10:01:32.182803 <6>[ 68.773568] OOM killer disabled.
11540 10:01:32.190019 <6>[ 68.777050] Freezing remaining freezable tasks
11541 10:01:32.196426 <6>[ 68.782654] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11542 10:01:32.203067 <6>[ 68.790306] printk: Suspending console(s) (use no_console_suspend to debug)
11543 10:01:35.660696 <3>[ 72.014914] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11544 10:01:35.670871 <3>[ 72.014947] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11545 10:01:35.680387 <3>[ 72.014995] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11546 10:01:35.687251 <3>[ 72.015040] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11547 10:01:35.696855 <3>[ 72.015520] PM: Some devices failed to suspend, or early wake event detected
11548 10:01:35.700249 <6>[ 72.289074] OOM killer enabled.
11549 10:01:35.706683 <6>[ 72.292489] Restarting tasks ... done.
11550 10:01:35.710032 <5>[ 72.299531] random: crng reseeded on system resumption
11551 10:01:35.714641 <6>[ 72.306220] PM: suspend exit
11552 10:01:35.717799 rtcwake: write error
11553 10:01:35.724320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11554 10:01:35.725107 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11556 10:01:35.728199 rtcwake: assuming RTC uses UTC ...
11557 10:01:35.734113 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:44 2023
11558 10:01:35.746536 <6>[ 72.335197] PM: suspend entry (s2idle)
11559 10:01:35.750008 <6>[ 72.339271] Filesystems sync: 0.000 seconds
11560 10:01:35.756903 <6>[ 72.344287] Freezing user space processes
11561 10:01:35.763474 <6>[ 72.350238] Freezing user space processes completed (elapsed 0.001 seconds)
11562 10:01:35.766794 <6>[ 72.357474] OOM killer disabled.
11563 10:01:35.773462 <6>[ 72.360954] Freezing remaining freezable tasks
11564 10:01:35.779975 <6>[ 72.366606] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11565 10:01:35.786464 <6>[ 72.374265] printk: Suspending console(s) (use no_console_suspend to debug)
11566 10:01:39.244369 <3>[ 75.598876] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11567 10:01:39.254375 <3>[ 75.598908] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11568 10:01:39.264060 <3>[ 75.598957] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11569 10:01:39.270915 <3>[ 75.599005] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11570 10:01:39.280833 <3>[ 75.599270] PM: Some devices failed to suspend, or early wake event detected
11571 10:01:39.283498 <6>[ 75.873078] OOM killer enabled.
11572 10:01:39.286755 <6>[ 75.876493] Restarting tasks ... done.
11573 10:01:39.295457 <5>[ 75.884434] random: crng reseeded on system resumption
11574 10:01:39.298941 <6>[ 75.891433] PM: suspend exit
11575 10:01:39.302986 rtcwake: write error
11576 10:01:39.309375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11577 10:01:39.310365 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11579 10:01:39.312393 rtcwake: assuming RTC uses UTC ...
11580 10:01:39.319182 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:47 2023
11581 10:01:39.331538 <6>[ 75.920504] PM: suspend entry (s2idle)
11582 10:01:39.334879 <6>[ 75.924580] Filesystems sync: 0.000 seconds
11583 10:01:39.341706 <6>[ 75.929585] Freezing user space processes
11584 10:01:39.348344 <6>[ 75.935443] Freezing user space processes completed (elapsed 0.001 seconds)
11585 10:01:39.351493 <6>[ 75.942683] OOM killer disabled.
11586 10:01:39.358372 <6>[ 75.946160] Freezing remaining freezable tasks
11587 10:01:39.364923 <6>[ 75.952295] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11588 10:01:39.374795 <6>[ 75.959969] printk: Suspending console(s) (use no_console_suspend to debug)
11589 10:01:42.827826 <3>[ 79.182906] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11590 10:01:42.838332 <3>[ 79.182940] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11591 10:01:42.848353 <3>[ 79.182988] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11592 10:01:42.854194 <3>[ 79.183036] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11593 10:01:42.864149 <3>[ 79.183647] PM: Some devices failed to suspend, or early wake event detected
11594 10:01:42.867582 <6>[ 79.457072] OOM killer enabled.
11595 10:01:42.871135 <6>[ 79.460485] Restarting tasks ... done.
11596 10:01:42.878767 <5>[ 79.468233] random: crng reseeded on system resumption
11597 10:01:42.882520 <6>[ 79.474957] PM: suspend exit
11598 10:01:42.885387 rtcwake: write error
11599 10:01:42.892660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11600 10:01:42.893561 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11602 10:01:42.895887 rtcwake: assuming RTC uses UTC ...
11603 10:01:42.901839 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:51 2023
11604 10:01:42.914812 <6>[ 79.504102] PM: suspend entry (s2idle)
11605 10:01:42.918497 <6>[ 79.508193] Filesystems sync: 0.000 seconds
11606 10:01:42.924858 <6>[ 79.513263] Freezing user space processes
11607 10:01:42.931725 <6>[ 79.518693] Freezing user space processes completed (elapsed 0.001 seconds)
11608 10:01:42.934599 <6>[ 79.525915] OOM killer disabled.
11609 10:01:42.941734 <6>[ 79.529394] Freezing remaining freezable tasks
11610 10:01:42.947890 <6>[ 79.535380] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11611 10:01:42.954479 <6>[ 79.543033] printk: Suspending console(s) (use no_console_suspend to debug)
11612 10:01:46.411069 <3>[ 82.766963] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11613 10:01:46.421331 <3>[ 82.767003] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11614 10:01:46.431076 <3>[ 82.767055] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11615 10:01:46.438167 <3>[ 82.767100] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11616 10:01:46.445027 <3>[ 82.767368] PM: Some devices failed to suspend, or early wake event detected
11617 10:01:46.451795 <6>[ 83.040968] OOM killer enabled.
11618 10:01:46.454717 <6>[ 83.044381] Restarting tasks ... done.
11619 10:01:46.462856 <5>[ 83.051998] random: crng reseeded on system resumption
11620 10:01:46.466511 <6>[ 83.059384] PM: suspend exit
11621 10:01:46.469733 rtcwake: write error
11622 10:01:46.476813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11623 10:01:46.477665 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11625 10:01:46.480274 rtcwake: assuming RTC uses UTC ...
11626 10:01:46.486428 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:54 2023
11627 10:01:46.498944 <6>[ 83.088651] PM: suspend entry (s2idle)
11628 10:01:46.502739 <6>[ 83.092759] Filesystems sync: 0.000 seconds
11629 10:01:46.508980 <6>[ 83.097840] Freezing user space processes
11630 10:01:46.515143 <6>[ 83.103780] Freezing user space processes completed (elapsed 0.001 seconds)
11631 10:01:46.518696 <6>[ 83.111021] OOM killer disabled.
11632 10:01:46.525668 <6>[ 83.114498] Freezing remaining freezable tasks
11633 10:01:46.532268 <6>[ 83.120635] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11634 10:01:46.541869 <6>[ 83.128321] printk: Suspending console(s) (use no_console_suspend to debug)
11635 10:01:49.995294 <3>[ 86.350874] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11636 10:01:50.005060 <3>[ 86.350906] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11637 10:01:50.014682 <3>[ 86.350954] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11638 10:01:50.021363 <3>[ 86.351000] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11639 10:01:50.031770 <3>[ 86.351312] PM: Some devices failed to suspend, or early wake event detected
11640 10:01:50.034498 <6>[ 86.625064] OOM killer enabled.
11641 10:01:50.037769 <6>[ 86.628478] Restarting tasks ... done.
11642 10:01:50.045875 <5>[ 86.636258] random: crng reseeded on system resumption
11643 10:01:50.049774 <6>[ 86.642968] PM: suspend exit
11644 10:01:50.052877 rtcwake: write error
11645 10:01:50.059753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11646 10:01:50.060619 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11648 10:01:50.062804 rtcwake: assuming RTC uses UTC ...
11649 10:01:50.069814 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:01:58 2023
11650 10:01:50.082415 <6>[ 86.672174] PM: suspend entry (s2idle)
11651 10:01:50.085783 <6>[ 86.676258] Filesystems sync: 0.000 seconds
11652 10:01:50.092027 <6>[ 86.681271] Freezing user space processes
11653 10:01:50.098911 <6>[ 86.686711] Freezing user space processes completed (elapsed 0.001 seconds)
11654 10:01:50.102046 <6>[ 86.693931] OOM killer disabled.
11655 10:01:50.108130 <6>[ 86.697411] Freezing remaining freezable tasks
11656 10:01:50.115092 <6>[ 86.703391] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11657 10:01:50.121308 <6>[ 86.711044] printk: Suspending console(s) (use no_console_suspend to debug)
11658 10:01:53.578436 <3>[ 89.934891] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11659 10:01:53.588672 <3>[ 89.934923] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11660 10:01:53.598432 <3>[ 89.934971] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11661 10:01:53.605031 <3>[ 89.935016] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11662 10:01:53.611448 <3>[ 89.935269] PM: Some devices failed to suspend, or early wake event detected
11663 10:01:53.618312 <6>[ 90.209073] OOM killer enabled.
11664 10:01:53.621986 <6>[ 90.212495] Restarting tasks ... done.
11665 10:01:53.629149 <5>[ 90.220114] random: crng reseeded on system resumption
11666 10:01:53.633085 <6>[ 90.226748] PM: suspend exit
11667 10:01:53.636152 rtcwake: write error
11668 10:01:53.643343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11669 10:01:53.644046 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11671 10:01:53.646483 rtcwake: assuming RTC uses UTC ...
11672 10:01:53.653588 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 10:02:02 2023
11673 10:01:53.665660 <6>[ 90.256262] PM: suspend entry (s2idle)
11674 10:01:53.669071 <6>[ 90.260353] Filesystems sync: 0.000 seconds
11675 10:01:53.675433 <6>[ 90.265396] Freezing user space processes
11676 10:01:53.682621 <6>[ 90.271217] Freezing user space processes completed (elapsed 0.001 seconds)
11677 10:01:53.685555 <6>[ 90.278437] OOM killer disabled.
11678 10:01:53.692500 <6>[ 90.281916] Freezing remaining freezable tasks
11679 10:01:53.698938 <6>[ 90.288017] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11680 10:01:53.708684 <6>[ 90.295686] printk: Suspending console(s) (use no_console_suspend to debug)
11681 10:01:57.157901 <3>[ 93.518956] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11682 10:01:57.170790 <3>[ 93.518996] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11683 10:01:57.178090 <3>[ 93.519053] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11684 10:01:57.184948 <3>[ 93.519103] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11685 10:01:57.194457 <3>[ 93.519431] PM: Some devices failed to suspend, or early wake event detected
11686 10:01:57.197811 <6>[ 93.789003] OOM killer enabled.
11687 10:01:57.204156 <6>[ 93.792415] Restarting tasks ... done.
11688 10:01:57.207710 <5>[ 93.799356] random: crng reseeded on system resumption
11689 10:01:57.211511 <6>[ 93.805994] PM: suspend exit
11690 10:01:57.214893 rtcwake: write error
11691 10:01:57.221968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11692 10:01:57.222881 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11694 10:01:57.225004 + set +x
11695 10:01:57.229088 <LAVA_SIGNAL_ENDRUN 0_sleep 12073287_1.5.2.3.1>
11696 10:01:57.229614 <LAVA_TEST_RUNNER EXIT>
11697 10:01:57.230222 Received signal: <ENDRUN> 0_sleep 12073287_1.5.2.3.1
11698 10:01:57.230715 Ending use of test pattern.
11699 10:01:57.231087 Ending test lava.0_sleep (12073287_1.5.2.3.1), duration 71.70
11701 10:01:57.232275 ok: lava_test_shell seems to have completed
11702 10:01:57.233211 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11703 10:01:57.233728 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11704 10:01:57.234178 end: 3 lava-test-retry (duration 00:01:12) [common]
11705 10:01:57.234671 start: 4 finalize (timeout 00:05:09) [common]
11706 10:01:57.235122 start: 4.1 power-off (timeout 00:00:30) [common]
11707 10:01:57.236015 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11708 10:01:57.323064 >> Command sent successfully.
11709 10:01:57.327688 Returned 0 in 0 seconds
11710 10:01:57.428729 end: 4.1 power-off (duration 00:00:00) [common]
11712 10:01:57.430208 start: 4.2 read-feedback (timeout 00:05:08) [common]
11713 10:01:57.431447 Listened to connection for namespace 'common' for up to 1s
11714 10:01:58.432081 Finalising connection for namespace 'common'
11715 10:01:58.432750 Disconnecting from shell: Finalise
11716 10:01:58.433212 / #
11717 10:01:58.534208 end: 4.2 read-feedback (duration 00:00:01) [common]
11718 10:01:58.535127 end: 4 finalize (duration 00:00:01) [common]
11719 10:01:58.535797 Cleaning after the job
11720 10:01:58.536294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/ramdisk
11721 10:01:58.580508 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/kernel
11722 10:01:58.609131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/dtb
11723 10:01:58.609365 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073287/tftp-deploy-c1unlv2r/modules
11724 10:01:58.616573 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073287
11725 10:01:58.787474 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073287
11726 10:01:58.787634 Job finished correctly